From 3c4d296e58a23687f2076d8ad531e6ae2b725846 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 30 Oct 2017 11:11:03 +0200 Subject: [PATCH 0001/2547] ARM: OMAP3: hwmod_data: add missing module_offs for MMC3 MMC3 hwmod data is missing the module_offs definition. MMC3 belongs under core, so add CORE_MOD for it. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index c3276436b0ae..c12e7b572a41 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1656,6 +1656,7 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = { .main_clk = "mmchs3_fck", .prcm = { .omap2 = { + .module_offs = CORE_MOD, .prcm_reg_id = 1, .module_bit = OMAP3430_EN_MMC3_SHIFT, .idlest_reg_id = 1, -- GitLab From 6301d58477bc11116c78c9542871f27ae374278d Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 30 Oct 2017 11:11:04 +0200 Subject: [PATCH 0002/2547] ARM: OMAP2/3: CM: fix cm_split_idlest functionality cm_split_idlest doesn't take the CM base offset into account right now, causing it to read reserved registers which show idlestatus as active always. This will cause the wait_module_ready functionality to be effectively an expensive NOP, which will cause problems if the module hasn't really activated during its execution. Fix by adding the CM offset into the calculation so the wait_module_ready will access correct register. Signed-off-by: Tero Kristo Reported-by: Filip Matijevic Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/cm_common.c | 6 +++++- arch/arm/mach-omap2/prcm-common.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c index d555791cf349..83c6fa74cc31 100644 --- a/arch/arm/mach-omap2/cm_common.c +++ b/arch/arm/mach-omap2/cm_common.c @@ -68,14 +68,17 @@ void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2) int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst, u8 *idlest_reg_id) { + int ret; if (!cm_ll_data->split_idlest_reg) { WARN_ONCE(1, "cm: %s: no low-level function defined\n", __func__); return -EINVAL; } - return cm_ll_data->split_idlest_reg(idlest_reg, prcm_inst, + ret = cm_ll_data->split_idlest_reg(idlest_reg, prcm_inst, idlest_reg_id); + *prcm_inst -= cm_base.offset; + return ret; } /** @@ -337,6 +340,7 @@ int __init omap2_cm_base_init(void) if (mem) { mem->pa = res.start + data->offset; mem->va = data->mem + data->offset; + mem->offset = data->offset; } data->np = np; diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index ee7041d523cf..ac9ee2ef3471 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -529,6 +529,7 @@ struct omap_prcm_irq_setup { struct omap_domain_base { u32 pa; void __iomem *va; + s16 offset; }; /** -- GitLab From f0c96c6d40312b1a76cd36709dc3eb5948c1b97f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 30 Oct 2017 10:01:39 -0700 Subject: [PATCH 0003/2547] ARM: OMAP2+: Fix smatch found issue for omap_device The patch d85a2d61432a: "ARM: OMAP2+: Populate legacy resources for dma and smartreflex" from Oct 10, 2017, leads to the following Smatch complaint: arch/arm/mach-omap2/omap_device.c:453 omap_device_copy_resources() error: we previously assumed 'oh' could be null (see line 394) Fixes: d85a2d61432a: ("ARM: OMAP2+: Populate legacy resources for dma and smartreflex") Reported-by: Dan Carpenter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_device.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index d45cbfdb4be6..184acd95c216 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -391,10 +391,8 @@ omap_device_copy_resources(struct omap_hwmod *oh, const char *name; int error, irq = 0; - if (!oh || !oh->od || !oh->od->pdev) { - error = -EINVAL; - goto error; - } + if (!oh || !oh->od || !oh->od->pdev) + return -EINVAL; np = oh->od->pdev->dev.of_node; if (!np) { -- GitLab From 7ce66118aaca8c9ed23cd44d629b8037a4117c11 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 1 Nov 2017 19:21:58 -0400 Subject: [PATCH 0004/2547] drm/amd: Update kgd_kfd interface for resuming SDMA queues Add wptr and mm parameters to hqd_sdma_load and pass these parameters from device_queue_manager through the mqd_manager. SDMA doesn't support polling while the engine believes it's idle. The driver must update the wptr. The new parameters will be used for looking up the updated value from the specified mm when SDMA queues are resumed after being disabled. Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 6 ++++-- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 4 +++- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 3 ++- 4 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index 1e3e9be7d77e..a55d7948075b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c @@ -105,7 +105,8 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm); -static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd); +static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, + uint32_t __user *wptr, struct mm_struct *mm); static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); @@ -375,7 +376,8 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, return 0; } -static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd) +static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, + uint32_t __user *wptr, struct mm_struct *mm) { struct amdgpu_device *adev = get_amdgpu_device(kgd); struct cik_sdma_rlc_registers *m; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index 056929b8ccd0..1017ff51c957 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -64,7 +64,8 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm); -static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd); +static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, + uint32_t __user *wptr, struct mm_struct *mm); static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); @@ -358,7 +359,8 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, return 0; } -static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd) +static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, + uint32_t __user *wptr, struct mm_struct *mm) { return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 4728fad3fd74..ea02bfa3bda3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -160,7 +160,9 @@ static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, uint32_t queue_id, struct queue_properties *p, struct mm_struct *mms) { - return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd); + return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd, + (uint32_t __user *)p->write_ptr, + mms); } static int update_mqd(struct mqd_manager *mm, void *mqd, diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index f516fd10e6ba..c6d4e64531c7 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -184,7 +184,8 @@ struct kfd2kgd_calls { uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm); - int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd); + int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd, + uint32_t __user *wptr, struct mm_struct *mm); bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); -- GitLab From fd0f0762dc590736a6692707860af3ce793f5028 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 1 Nov 2017 19:21:59 -0400 Subject: [PATCH 0005/2547] drm/amdgpu: Add support for resuming SDMA queues w/o HWS Save wptr in hqd_sdma_destroy, restore it in hqd_sdma_load. Also read updated wptr from user mode when resuming an SDMA queue. Signed-off-by: Jay Cornwall Signed-off-by: Yong Zhao Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 30 ++++++++++++------- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 7 ++--- 2 files changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index a55d7948075b..14333af92ed9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c @@ -412,10 +412,17 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data); } - WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, - m->sdma_rlc_doorbell); - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0); - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0); + data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL, + ENABLE, 1); + WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr); + + if (read_user_wptr(mm, wptr, data)) + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data); + else + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, + m->sdma_rlc_rb_rptr); + WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, m->sdma_rlc_virtual_addr); WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base); @@ -425,8 +432,10 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, m->sdma_rlc_rb_rptr_addr_lo); WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, m->sdma_rlc_rb_rptr_addr_hi); - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, - m->sdma_rlc_rb_cntl); + + data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL, + RB_ENABLE, 1); + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); return 0; } @@ -577,7 +586,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, struct cik_sdma_rlc_registers *m; uint32_t sdma_base_addr; uint32_t temp; - int timeout = utimeout; + unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; m = get_sdma_mqd(mqd); sdma_base_addr = get_sdma_base_addr(m); @@ -590,10 +599,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT) break; - if (timeout <= 0) + if (time_after(jiffies, end_jiffies)) return -ETIME; - msleep(20); - timeout -= 20; + usleep_range(500, 1000); } WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); @@ -601,6 +609,8 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); + m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index 1017ff51c957..c0c8cc3b23b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -514,7 +514,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, struct cik_sdma_rlc_registers *m; uint32_t sdma_base_addr; uint32_t temp; - int timeout = utimeout; + unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; m = get_sdma_mqd(mqd); sdma_base_addr = get_sdma_base_addr(m); @@ -527,10 +527,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT) break; - if (timeout <= 0) + if (time_after(jiffies, end_jiffies)) return -ETIME; - msleep(20); - timeout -= 20; + usleep_range(500, 1000); } WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); -- GitLab From 9807c3668500b0964e8ee59d68083675971bc224 Mon Sep 17 00:00:00 2001 From: Philip Cox Date: Wed, 1 Nov 2017 19:22:00 -0400 Subject: [PATCH 0006/2547] drm/amdgpu: Implement amdgpu SDMA functions for VI Signed-off-by: Philip Cox Signed-off-by: shaoyun liu Signed-off-by: Yong Zhao Signed-off-by: Jay Cornwall Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 87 ++++++++++++++++--- drivers/gpu/drm/amd/amdgpu/vid.h | 2 + drivers/gpu/drm/amd/include/vi_structs.h | 2 + 3 files changed, 80 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index c0c8cc3b23b0..1d989e4915b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -45,7 +45,7 @@ enum hqd_dequeue_request_type { RESET_WAVES }; -struct cik_sdma_rlc_registers; +struct vi_sdma_mqd; /* * Register access functions @@ -269,9 +269,15 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) return 0; } -static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m) +static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m) { - return 0; + uint32_t retval; + + retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + + m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET; + pr_debug("kfd: sdma base address: 0x%x\n", retval); + + return retval; } static inline struct vi_mqd *get_mqd(void *mqd) @@ -279,9 +285,9 @@ static inline struct vi_mqd *get_mqd(void *mqd) return (struct vi_mqd *)mqd; } -static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) +static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd) { - return (struct cik_sdma_rlc_registers *)mqd; + return (struct vi_sdma_mqd *)mqd; } static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, @@ -362,6 +368,63 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) { + struct amdgpu_device *adev = get_amdgpu_device(kgd); + struct vi_sdma_mqd *m; + unsigned long end_jiffies; + uint32_t sdma_base_addr; + uint32_t data; + + m = get_sdma_mqd(mqd); + sdma_base_addr = get_sdma_base_addr(m); + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, + m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); + + end_jiffies = msecs_to_jiffies(2000) + jiffies; + while (true) { + data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); + if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) + break; + if (time_after(jiffies, end_jiffies)) + return -ETIME; + usleep_range(500, 1000); + } + if (m->sdma_engine_id) { + data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL); + data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL, + RESUME_CTX, 0); + WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data); + } else { + data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL); + data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, + RESUME_CTX, 0); + WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data); + } + + data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, + ENABLE, 1); + WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); + + if (read_user_wptr(mm, wptr, data)) + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data); + else + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, + m->sdmax_rlcx_rb_rptr); + + WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, + m->sdmax_rlcx_virtual_addr); + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, + m->sdmax_rlcx_rb_base_hi); + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, + m->sdmax_rlcx_rb_rptr_addr_lo); + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, + m->sdmax_rlcx_rb_rptr_addr_hi); + + data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, + RB_ENABLE, 1); + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); + return 0; } @@ -390,7 +453,7 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) { struct amdgpu_device *adev = get_amdgpu_device(kgd); - struct cik_sdma_rlc_registers *m; + struct vi_sdma_mqd *m; uint32_t sdma_base_addr; uint32_t sdma_rlc_rb_cntl; @@ -511,7 +574,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, unsigned int utimeout) { struct amdgpu_device *adev = get_amdgpu_device(kgd); - struct cik_sdma_rlc_registers *m; + struct vi_sdma_mqd *m; uint32_t sdma_base_addr; uint32_t temp; unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; @@ -525,7 +588,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, while (true) { temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); - if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT) + if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) break; if (time_after(jiffies, end_jiffies)) return -ETIME; @@ -533,9 +596,11 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, } WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0); - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0); - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0); + WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, + RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | + SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); + + m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h index dbf3703cbd1b..19ddd2312e00 100644 --- a/drivers/gpu/drm/amd/amdgpu/vid.h +++ b/drivers/gpu/drm/amd/amdgpu/vid.h @@ -27,6 +27,8 @@ #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ #define SDMA_MAX_INSTANCE 2 +#define KFD_VI_SDMA_QUEUE_OFFSET 0x80 /* not a register */ + /* crtc instance offsets */ #define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c) #define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c) diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h index 20234820194b..717fbae1d362 100644 --- a/drivers/gpu/drm/amd/include/vi_structs.h +++ b/drivers/gpu/drm/amd/include/vi_structs.h @@ -153,6 +153,8 @@ struct vi_sdma_mqd { uint32_t reserved_125; uint32_t reserved_126; uint32_t reserved_127; + uint32_t sdma_engine_id; + uint32_t sdma_queue_id; }; struct vi_mqd { -- GitLab From 97b9ad12ba08353b3e19d85e65761b4cd936c12c Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 1 Nov 2017 19:22:01 -0400 Subject: [PATCH 0007/2547] drm/amdkfd: Use ASIC-specific SDMA MQD type Signed-off-by: shaoyun liu Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 13 +++++-------- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 5 +++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 -- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index ea02bfa3bda3..9873929ab4ef 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -36,6 +36,11 @@ static inline struct cik_mqd *get_mqd(void *mqd) return (struct cik_mqd *)mqd; } +static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) +{ + return (struct cik_sdma_rlc_registers *)mqd; +} + static int init_mqd(struct mqd_manager *mm, void **mqd, struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, struct queue_properties *q) @@ -362,14 +367,6 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, return 0; } -struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) -{ - struct cik_sdma_rlc_registers *m; - - m = (struct cik_sdma_rlc_registers *)mqd; - - return m; -} struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, struct kfd_dev *dev) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 4ea854f9007b..dc9249709e9b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -38,6 +38,11 @@ static inline struct vi_mqd *get_mqd(void *mqd) return (struct vi_mqd *)mqd; } +static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd) +{ + return (struct vi_sdma_mqd *)mqd; +} + static int init_mqd(struct mqd_manager *mm, void **mqd, struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, struct queue_properties *q) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 9e4134c5b481..47504737ab4a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -643,8 +643,6 @@ int kgd2kfd_resume(struct kfd_dev *kfd); int kfd_init_apertures(struct kfd_process *process); /* Queue Context Management */ -struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd); - int init_queue(struct queue **q, const struct queue_properties *properties); void uninit_queue(struct queue *q); void print_queue_properties(struct queue_properties *q); -- GitLab From 5aaf2befd4eceb2efa16c63ccb64c8e13785594a Mon Sep 17 00:00:00 2001 From: Philip Cox Date: Wed, 1 Nov 2017 19:22:02 -0400 Subject: [PATCH 0008/2547] drm/amdkfd: Implement amdkfd SDMA functions for VI Signed-off-by: Philip Cox Signed-off-by: shaoyun liu Signed-off-by: Jay Cornwall Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 103 +++++++++++++++++- 1 file changed, 102 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index dc9249709e9b..a117d2b7721f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -30,7 +30,7 @@ #include "vi_structs.h" #include "gca/gfx_8_0_sh_mask.h" #include "gca/gfx_8_0_enum.h" - +#include "oss/oss_3_0_sh_mask.h" #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 static inline struct vi_mqd *get_mqd(void *mqd) @@ -239,6 +239,101 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, return retval; } +static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, + struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, + struct queue_properties *q) +{ + int retval; + struct vi_sdma_mqd *m; + + + retval = kfd_gtt_sa_allocate(mm->dev, + sizeof(struct vi_sdma_mqd), + mqd_mem_obj); + + if (retval != 0) + return -ENOMEM; + + m = (struct vi_sdma_mqd *) (*mqd_mem_obj)->cpu_ptr; + + memset(m, 0, sizeof(struct vi_sdma_mqd)); + + *mqd = m; + if (gart_addr != NULL) + *gart_addr = (*mqd_mem_obj)->gpu_addr; + + retval = mm->update_mqd(mm, m, q); + + return retval; +} + +static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd, + struct kfd_mem_obj *mqd_mem_obj) +{ + kfd_gtt_sa_free(mm->dev, mqd_mem_obj); +} + +static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, + uint32_t pipe_id, uint32_t queue_id, + struct queue_properties *p, struct mm_struct *mms) +{ + return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd, + (uint32_t __user *)p->write_ptr, + mms); +} + +static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, + struct queue_properties *q) +{ + struct vi_sdma_mqd *m; + + m = get_sdma_mqd(mqd); + m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) + << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | + q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | + 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | + 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; + + m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); + m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); + m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); + m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); + m->sdmax_rlcx_doorbell = + q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT; + + m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr; + + m->sdma_engine_id = q->sdma_engine_id; + m->sdma_queue_id = q->sdma_queue_id; + + q->is_active = (q->queue_size > 0 && + q->queue_address != 0 && + q->queue_percent > 0); + + return 0; +} + +/* + * * preempt type here is ignored because there is only one way + * * to preempt sdma queue + */ +static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, + enum kfd_preempt_type type, + unsigned int timeout, uint32_t pipe_id, + uint32_t queue_id) +{ + return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout); +} + +static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, + uint64_t queue_address, uint32_t pipe_id, + uint32_t queue_id) +{ + return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); +} + + + struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, struct kfd_dev *dev) { @@ -272,6 +367,12 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->is_occupied = is_occupied; break; case KFD_MQD_TYPE_SDMA: + mqd->init_mqd = init_mqd_sdma; + mqd->uninit_mqd = uninit_mqd_sdma; + mqd->load_mqd = load_mqd_sdma; + mqd->update_mqd = update_mqd_sdma; + mqd->destroy_mqd = destroy_mqd_sdma; + mqd->is_occupied = is_occupied_sdma; break; default: kfree(mqd); -- GitLab From 6d566930257df564d0aaacad0f02855d9c85aecd Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 6 Nov 2017 14:52:27 -0500 Subject: [PATCH 0009/2547] drm/amdkfd: Hardware DWORD size is 4 bytes Don't use sizeof(uint32_t) or similar types for hardware or firmware DWORD size. The hardware and firmware don't care about Linux types. Signed-off-by: Felix Kuehling Reviewed-by: Alex Deucher Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c | 14 +++++--------- drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 10 ++++------ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 9 ++++----- drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 2 +- 5 files changed, 15 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c index c407f6bd9956..afb26f205d29 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c @@ -95,7 +95,7 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev, ib_packet->bitfields3.ib_base_hi = largep->u.high_part; ib_packet->control = (1 << 23) | (1 << 31) | - ((size_in_bytes / sizeof(uint32_t)) & 0xfffff); + ((size_in_bytes / 4) & 0xfffff); ib_packet->bitfields5.pasid = pasid; @@ -126,8 +126,7 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev, rm_packet->header.opcode = IT_RELEASE_MEM; rm_packet->header.type = PM4_TYPE_3; - rm_packet->header.count = sizeof(struct pm4__release_mem) / - sizeof(unsigned int) - 2; + rm_packet->header.count = sizeof(struct pm4__release_mem) / 4 - 2; rm_packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT; rm_packet->bitfields2.event_index = @@ -652,8 +651,7 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev, packets_vec[0].header.opcode = IT_SET_UCONFIG_REG; packets_vec[0].header.type = PM4_TYPE_3; packets_vec[0].bitfields2.reg_offset = - GRBM_GFX_INDEX / (sizeof(uint32_t)) - - USERCONFIG_REG_BASE; + GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE; packets_vec[0].bitfields2.insert_vmid = 0; packets_vec[0].reg_data[0] = reg_gfx_index.u32All; @@ -661,8 +659,7 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev, packets_vec[1].header.count = 1; packets_vec[1].header.opcode = IT_SET_CONFIG_REG; packets_vec[1].header.type = PM4_TYPE_3; - packets_vec[1].bitfields2.reg_offset = SQ_CMD / (sizeof(uint32_t)) - - AMD_CONFIG_REG_BASE; + packets_vec[1].bitfields2.reg_offset = SQ_CMD / 4 - AMD_CONFIG_REG_BASE; packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET; packets_vec[1].bitfields2.insert_vmid = 1; @@ -678,8 +675,7 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev, packets_vec[2].ordinal1 = packets_vec[0].ordinal1; packets_vec[2].bitfields2.reg_offset = - GRBM_GFX_INDEX / (sizeof(uint32_t)) - - USERCONFIG_REG_BASE; + GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE; packets_vec[2].bitfields2.insert_vmid = 0; packets_vec[2].reg_data[0] = reg_gfx_index.u32All; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c index 8b0c0645d7c0..5dc6567d4a13 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c @@ -218,7 +218,7 @@ static int acquire_packet_buffer(struct kernel_queue *kq, rptr = *kq->rptr_kernel; wptr = *kq->wptr_kernel; queue_address = (unsigned int *)kq->pq_kernel_addr; - queue_size_dwords = kq->queue->properties.queue_size / sizeof(uint32_t); + queue_size_dwords = kq->queue->properties.queue_size / 4; pr_debug("rptr: %d\n", rptr); pr_debug("wptr: %d\n", wptr); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 9873929ab4ef..efed6ef6dad8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -154,7 +154,7 @@ static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, { /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); - uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1); + uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1); return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, (uint32_t __user *)p->write_ptr, @@ -183,8 +183,7 @@ static int update_mqd(struct mqd_manager *mm, void *mqd, * Calculating queue size which is log base 2 of actual queue size -1 * dwords and another -1 for ffs */ - m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) - - 1 - 1; + m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1; m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); @@ -209,7 +208,7 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, struct cik_sdma_rlc_registers *m; m = get_sdma_mqd(mqd); - m->sdma_rlc_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) + m->sdma_rlc_rb_cntl = (ffs(q->queue_size / 4) - 1) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | @@ -350,8 +349,7 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, * Calculating queue size which is log base 2 of actual queue * size -1 dwords */ - m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) - - 1 - 1; + m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1; m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index a117d2b7721f..85e1b676b1d7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -103,7 +103,7 @@ static int load_mqd(struct mqd_manager *mm, void *mqd, { /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); - uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1); + uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1); return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, (uint32_t __user *)p->write_ptr, @@ -121,8 +121,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT | mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT; - m->cp_hqd_pq_control |= - ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; + m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1; pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); @@ -152,7 +151,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, * is safe, giving a maximum field value of 0xA. */ m->cp_hqd_eop_control |= min(0xA, - ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); + ffs(q->eop_ring_buffer_size / 4) - 1 - 1); m->cp_hqd_eop_base_addr_lo = lower_32_bits(q->eop_ring_buffer_address >> 8); m->cp_hqd_eop_base_addr_hi = @@ -288,7 +287,7 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, struct vi_sdma_mqd *m; m = get_sdma_mqd(mqd); - m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) + m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / 4) - 1) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index 16da8ad02d8b..69c147a83591 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -45,7 +45,7 @@ static unsigned int build_pm4_header(unsigned int opcode, size_t packet_size) header.u32All = 0; header.opcode = opcode; - header.count = packet_size/sizeof(uint32_t) - 2; + header.count = packet_size / 4 - 2; header.type = PM4_TYPE_3; return header.u32All; -- GitLab From 115c8c4104bab4c435e0eaf7ffd5aabaf2adbbd2 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 6 Nov 2017 14:52:28 -0500 Subject: [PATCH 0010/2547] drm/amdkfd: Use order_base_2 to get log2 of buffes sizes Replace (ffs(size) - 1) with order_base_2(size) as a more straight forward way to get log2 of buffer sizes. Signed-off-by: Felix Kuehling Reviewed-by: Alex Deucher Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index efed6ef6dad8..7aa57abebbcd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -183,7 +183,7 @@ static int update_mqd(struct mqd_manager *mm, void *mqd, * Calculating queue size which is log base 2 of actual queue size -1 * dwords and another -1 for ffs */ - m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1; + m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); @@ -208,7 +208,7 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, struct cik_sdma_rlc_registers *m; m = get_sdma_mqd(mqd); - m->sdma_rlc_rb_cntl = (ffs(q->queue_size / 4) - 1) + m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | @@ -349,7 +349,7 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, * Calculating queue size which is log base 2 of actual queue * size -1 dwords */ - m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1; + m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 85e1b676b1d7..2ba7cea7b99b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -121,7 +121,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT | mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT; - m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1; + m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); @@ -151,7 +151,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, * is safe, giving a maximum field value of 0xA. */ m->cp_hqd_eop_control |= min(0xA, - ffs(q->eop_ring_buffer_size / 4) - 1 - 1); + order_base_2(q->eop_ring_buffer_size / 4) - 1); m->cp_hqd_eop_base_addr_lo = lower_32_bits(q->eop_ring_buffer_address >> 8); m->cp_hqd_eop_base_addr_hi = @@ -287,7 +287,7 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, struct vi_sdma_mqd *m; m = get_sdma_mqd(mqd); - m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / 4) - 1) + m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | -- GitLab From f568f6f554b817edafebf28a06b73ec9b4986dd1 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 9 Nov 2017 16:26:13 -0600 Subject: [PATCH 0011/2547] ARM: dts: omap: Add missing #phy-cells to usb-nop-xceiv MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "usb-nop-xceiv" is using the phy binding, but is missing #phy-cells property. This is probably because the binding was the precursor to the phy binding. Fixes the following warning in OMAP dts files: Warning (phys_property): Missing property '#phy-cells' in node ... Signed-off-by: Rob Herring Cc: "Benoît Cousson" Cc: Tony Lindgren Cc: Enric Balletbo i Serra Cc: Javier Martinez Canillas Cc: linux-omap@vger.kernel.org Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/logicpd-som-lv.dtsi | 1 + arch/arm/boot/dts/omap3-beagle-xm.dts | 1 + arch/arm/boot/dts/omap3-beagle.dts | 1 + arch/arm/boot/dts/omap3-cm-t3x.dtsi | 2 ++ arch/arm/boot/dts/omap3-evm-common.dtsi | 1 + arch/arm/boot/dts/omap3-gta04.dtsi | 1 + arch/arm/boot/dts/omap3-igep0020-common.dtsi | 1 + arch/arm/boot/dts/omap3-igep0030-common.dtsi | 1 + arch/arm/boot/dts/omap3-lilly-a83x.dtsi | 1 + arch/arm/boot/dts/omap3-overo-base.dtsi | 1 + arch/arm/boot/dts/omap3-pandora-common.dtsi | 1 + arch/arm/boot/dts/omap3-tao3530.dtsi | 1 + arch/arm/boot/dts/omap4-droid4-xt894.dts | 1 + arch/arm/boot/dts/omap4-duovero.dtsi | 1 + arch/arm/boot/dts/omap4-panda-common.dtsi | 1 + arch/arm/boot/dts/omap4-var-som-om44.dtsi | 1 + arch/arm/boot/dts/omap5-board-common.dtsi | 2 ++ arch/arm/boot/dts/omap5-cm-t54.dts | 2 ++ 18 files changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi index 26cce4d18405..4a79ce84045c 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -33,6 +33,7 @@ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ + #phy-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 683b96a8f73e..0349fcc9dc26 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -90,6 +90,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; }; tfp410: encoder0 { diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 4d2eaf843fa9..3ca8991a6c3e 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -64,6 +64,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; }; sound { diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi index fccd5383243c..08533fcdbbe8 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi @@ -42,12 +42,14 @@ hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; vcc-supply = <&hsusb1_power>; + #phy-cells = <0>; }; /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; }; ads7846reg: ads7846-reg { diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index ff35803088e3..26badcc64d77 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -28,6 +28,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; }; leds { diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 4504908c23fe..3dc56fb156b7 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -120,6 +120,7 @@ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + #phy-cells = <0>; }; tv0: connector { diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi index 667f96245729..ecbec23af49f 100644 --- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi +++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi @@ -58,6 +58,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ vcc-supply = <&hsusb1_power>; + #phy-cells = <0>; }; tfp410: encoder { diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi index e94d9427450c..443f71707437 100644 --- a/arch/arm/boot/dts/omap3-igep0030-common.dtsi +++ b/arch/arm/boot/dts/omap3-igep0030-common.dtsi @@ -37,6 +37,7 @@ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ + #phy-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index fa611a5e4850..a87c0b630435 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -51,6 +51,7 @@ hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_vcc3>; + #phy-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index f25e158e7163..ac141fcd1742 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -51,6 +51,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */ vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; }; /* Regulator to trigger the nPoweron signal of the Wifi module */ diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi index 53e007abdc71..cd53dc6c0051 100644 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -205,6 +205,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO_16 */ vcc-supply = <&vaux2>; + #phy-cells = <0>; }; /* HS USB Host VBUS supply diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index 9a601d15247b..6f5bd027b717 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -46,6 +46,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */ vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; }; sound { diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 8b93d37310f2..24a463f8641f 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -73,6 +73,7 @@ /* HS USB Host PHY on PORT 1 */ hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; /* LCD regulator from sw5 source */ diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi index 6e6810c258eb..eb123b24c8e3 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/omap4-duovero.dtsi @@ -43,6 +43,7 @@ hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ + #phy-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsusb1phy_pins>; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 2b48e51c372a..83b31682e5f1 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -85,6 +85,7 @@ hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ + #phy-cells = <0>; vcc-supply = <&hsusb1_power>; clocks = <&auxclk3_ck>; clock-names = "main_clk"; diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi index 6500bfc8d130..10fce28ceb5b 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi @@ -44,6 +44,7 @@ reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; /* gpio 177 */ vcc-supply = <&vbat>; + #phy-cells = <0>; clocks = <&auxclk3_ck>; clock-names = "main_clk"; diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index 7824b2631cb6..d9ca403d8b24 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -69,12 +69,14 @@ clocks = <&auxclk1_ck>; clock-names = "main_clk"; clock-frequency = <19200000>; + #phy-cells = <0>; }; /* HS USB Host PHY on PORT 3 */ hsusb3_phy: hsusb3_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ + #phy-cells = <0>; }; tpd12s015: encoder { diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index 552a5c4c5942..73fcdda57dc2 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -62,12 +62,14 @@ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */ + #phy-cells = <0>; }; /* HS USB Host PHY on PORT 3 */ hsusb3_phy: hsusb3_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 ETH_RESET */ + #phy-cells = <0>; }; leds { -- GitLab From f0e11ff8ff6595cb49bc18929b525d35721b8383 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 9 Nov 2017 16:26:14 -0600 Subject: [PATCH 0012/2547] ARM: dts: am33xx: Add missing #phy-cells to ti,am335x-usb-phy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "ti,am335x-usb-phy" is using the phy binding, but is missing #phy-cells property. Fixes the following warning in TI dts files: Warning (phys_property): Missing property '#phy-cells' in node ... Signed-off-by: Rob Herring Cc: "Benoît Cousson" Cc: Tony Lindgren Cc: linux-omap@vger.kernel.org Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/usb/am33xx-usb.txt | 2 ++ arch/arm/boot/dts/am33xx.dtsi | 2 ++ arch/arm/boot/dts/dm814x.dtsi | 1 + 3 files changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/am33xx-usb.txt b/Documentation/devicetree/bindings/usb/am33xx-usb.txt index 16920d78e1b8..6eb0a74d50a7 100644 --- a/Documentation/devicetree/bindings/usb/am33xx-usb.txt +++ b/Documentation/devicetree/bindings/usb/am33xx-usb.txt @@ -95,6 +95,7 @@ usb: usb@47400000 { reg = <0x47401300 0x100>; reg-names = "phy"; ti,ctrl_mod = <&ctrl_mod>; + #phy-cells = <0>; }; usb0: usb@47401000 { @@ -141,6 +142,7 @@ usb: usb@47400000 { reg = <0x47401b00 0x100>; reg-names = "phy"; ti,ctrl_mod = <&ctrl_mod>; + #phy-cells = <0>; }; usb1: usb@47401800 { diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 08653552db71..29f3fbb6bee2 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -628,6 +628,7 @@ reg-names = "phy"; status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; }; usb0: usb@47401000 { @@ -676,6 +677,7 @@ reg-names = "phy"; status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; }; usb1: usb@47401800 { diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 9708157f5daf..b7a11c1168d1 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -75,6 +75,7 @@ reg = <0x47401300 0x100>; reg-names = "phy"; ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; }; usb0: usb@47401000 { -- GitLab From 60636a5d0fa2f8bc6d0c23c4027100ba20866f9b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 10 Nov 2017 09:00:16 -0800 Subject: [PATCH 0013/2547] ARM: dts: Add remote-wakeup-connected for omap OHCI Add remote-wakeup-connected for omap OHCI as that's needed by ohci-platform driver. Cc: devicetree@vger.kernel.org Cc: Hans de Goede Cc: Rob Herring Cc: Sebastian Reichel Cc: Yoshihiro Shimoda Acked-by: Alan Stern Acked-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3.dtsi | 1 + arch/arm/boot/dts/omap4.dtsi | 1 + arch/arm/boot/dts/omap5.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 90b5c7148feb..bb33935df7b0 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -715,6 +715,7 @@ compatible = "ti,ohci-omap3"; reg = <0x48064400 0x400>; interrupts = <76>; + remote-wakeup-connected; }; usbhsehci: ehci@48064800 { diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 1dc5a76b3c71..27454b1c2fdf 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -1083,6 +1083,7 @@ reg = <0x4a064800 0x400>; interrupt-parent = <&gic>; interrupts = ; + remote-wakeup-connected; }; usbhsehci: ehci@4a064c00 { diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index b86ac7df620d..86054e89fa72 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -940,6 +940,7 @@ compatible = "ti,ohci-omap3"; reg = <0x4a064800 0x400>; interrupts = ; + remote-wakeup-connected; }; usbhsehci: ehci@4a064c00 { -- GitLab From b20cd0df152cf4a64e6ae5a1be5f7f346a27eedd Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 14 Nov 2017 16:41:17 -0500 Subject: [PATCH 0014/2547] drm/amdkfd: Cleanup qpd.pqm initialization The PQM doesn't change after process creation. So initialize it in kfd_create_process_device_data. Signed-off-by: Felix Kuehling Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 4 +--- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 1f5ccd28bd41..1bb9b2643d5a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -348,6 +348,7 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev, INIT_LIST_HEAD(&pdd->qpd.queues_list); INIT_LIST_HEAD(&pdd->qpd.priv_queue_list); pdd->qpd.dqm = dev->dqm; + pdd->qpd.pqm = &p->pqm; pdd->process = p; pdd->bound = PDD_UNBOUND; pdd->already_dequeued = false; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index a3f1e62c60ba..eeb7726b6299 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -178,10 +178,8 @@ int pqm_create_queue(struct process_queue_manager *pqm, return retval; if (list_empty(&pdd->qpd.queues_list) && - list_empty(&pdd->qpd.priv_queue_list)) { - pdd->qpd.pqm = pqm; + list_empty(&pdd->qpd.priv_queue_list)) dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); - } pqn = kzalloc(sizeof(*pqn), GFP_KERNEL); if (!pqn) { -- GitLab From 449fea612690c3a5ae69d5c09fa7d2ce5773e736 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 14 Nov 2017 16:41:18 -0500 Subject: [PATCH 0015/2547] drm/amdkfd: Add trap handler for CWSR The trap handler is like an interrupt handler running on the GPU compute unit. It is needed for supporting CWSR (compute wave save/restore). This file defines an array with the pre-compiled GFXv8 shader ISA. The assembly code is included for reference in #if 0 ... #endif. Signed-off-by: Shaoyun.liu Signed-off-by: Jay Cornwall Signed-off-by: Felix Kuehling Signed-off-by: Oded Gabbay --- .../drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm | 1384 +++++++++++++++++ 1 file changed, 1384 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm new file mode 100644 index 000000000000..997a383dcb8b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm @@ -0,0 +1,1384 @@ +/* + * Copyright 2015-2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#if 0 +HW (VI) source code for CWSR trap handler +#Version 18 + multiple trap handler + +// this performance-optimal version was originally from Seven Xu at SRDC + +// Revison #18 --... +/* Rev History +** #1. Branch from gc dv. //gfxip/gfx8/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV) +** #4. SR Memory Layout: +** 1. VGPR-SGPR-HWREG-{LDS} +** 2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern.. +** #5. Update: 1. Accurate g8sr_ts_save_d timestamp +** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation) +** #7. Update: 1. don't barrier if noLDS +** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version +** 2. Fix SQ issue by s_sleep 2 +** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last +** 2. optimize s_buffer save by burst 16sgprs... +** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs. +** #11. Update 1. Add 2 more timestamp for debug version +** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance +** #13. Integ 1. Always use MUBUF for PV trap shader... +** #14. Update 1. s_buffer_store soft clause... +** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot. +** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree +** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part] +** 2. PERF - Save LDS before save VGPR to cover LDS save long latency... +** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32 +** 2. FUNC - Handle non-CWSR traps +*/ + +var G8SR_WDMEM_HWREG_OFFSET = 0 +var G8SR_WDMEM_SGPR_OFFSET = 128 // in bytes + +// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore. + +var G8SR_DEBUG_TIMESTAMP = 0 +var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4 // ts_save_d timestamp offset relative to SGPR_SR_memory_offset +var s_g8sr_ts_save_s = s[34:35] // save start +var s_g8sr_ts_sq_save_msg = s[36:37] // The save shader send SAVEWAVE msg to spi +var s_g8sr_ts_spi_wrexec = s[38:39] // the SPI write the sr address to SQ +var s_g8sr_ts_save_d = s[40:41] // save end +var s_g8sr_ts_restore_s = s[42:43] // restore start +var s_g8sr_ts_restore_d = s[44:45] // restore end + +var G8SR_VGPR_SR_IN_DWX4 = 0 +var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000 // DWx4 stride is 4*4Bytes +var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 + + +/*************************************************************************/ +/* control on how to run the shader */ +/*************************************************************************/ +//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run) +var EMU_RUN_HACK = 0 +var EMU_RUN_HACK_RESTORE_NORMAL = 0 +var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0 +var EMU_RUN_HACK_SAVE_SINGLE_WAVE = 0 +var EMU_RUN_HACK_SAVE_FIRST_TIME = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK +var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK +var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK +var SAVE_LDS = 1 +var WG_BASE_ADDR_LO = 0x9000a000 +var WG_BASE_ADDR_HI = 0x0 +var WAVE_SPACE = 0x5000 //memory size that each wave occupies in workgroup state mem +var CTX_SAVE_CONTROL = 0x0 +var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL +var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run) +var SGPR_SAVE_USE_SQC = 1 //use SQC D$ to do the write +var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes +var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing + +/**************************************************************************/ +/* variables */ +/**************************************************************************/ +var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23 +var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000 +var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 + +var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 +var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 +var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 +var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 +var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 +var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits + +var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 +var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask +var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 +var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 +var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 +var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF +var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 +var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 +var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 +var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 +var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 + +var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME +var SQ_WAVE_IB_STS_RCNT_SIZE = 4 //FIXME +var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME +var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE = 1 //FIXME +var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME + +var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24 +var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27 + + +/* Save */ +var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes +var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE + +var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit +var S_SAVE_SPI_INIT_ATC_SHIFT = 27 +var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype +var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28 +var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG +var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 + +var S_SAVE_PC_HI_RCNT_SHIFT = 28 //FIXME check with Brian to ensure all fields other than PC[47:0] can be used +var S_SAVE_PC_HI_RCNT_MASK = 0xF0000000 //FIXME +var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 27 //FIXME +var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x08000000 //FIXME + +var s_save_spi_init_lo = exec_lo +var s_save_spi_init_hi = exec_hi + + //tba_lo and tba_hi need to be saved/restored +var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3??h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]} +var s_save_pc_hi = ttmp1 +var s_save_exec_lo = ttmp2 +var s_save_exec_hi = ttmp3 +var s_save_status = ttmp4 +var s_save_trapsts = ttmp5 //not really used until the end of the SAVE routine +var s_save_xnack_mask_lo = ttmp6 +var s_save_xnack_mask_hi = ttmp7 +var s_save_buf_rsrc0 = ttmp8 +var s_save_buf_rsrc1 = ttmp9 +var s_save_buf_rsrc2 = ttmp10 +var s_save_buf_rsrc3 = ttmp11 + +var s_save_mem_offset = tma_lo +var s_save_alloc_size = s_save_trapsts //conflict +var s_save_tmp = s_save_buf_rsrc2 //shared with s_save_buf_rsrc2 (conflict: should not use mem access with s_save_tmp at the same time) +var s_save_m0 = tma_hi + +/* Restore */ +var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE +var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC + +var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit +var S_RESTORE_SPI_INIT_ATC_SHIFT = 27 +var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype +var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28 +var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG +var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 + +var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT +var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK +var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT +var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK + +var s_restore_spi_init_lo = exec_lo +var s_restore_spi_init_hi = exec_hi + +var s_restore_mem_offset = ttmp2 +var s_restore_alloc_size = ttmp3 +var s_restore_tmp = ttmp6 //tba_lo/hi need to be restored +var s_restore_mem_offset_save = s_restore_tmp //no conflict + +var s_restore_m0 = s_restore_alloc_size //no conflict + +var s_restore_mode = ttmp7 + +var s_restore_pc_lo = ttmp0 +var s_restore_pc_hi = ttmp1 +var s_restore_exec_lo = tma_lo //no conflict +var s_restore_exec_hi = tma_hi //no conflict +var s_restore_status = ttmp4 +var s_restore_trapsts = ttmp5 +var s_restore_xnack_mask_lo = xnack_mask_lo +var s_restore_xnack_mask_hi = xnack_mask_hi +var s_restore_buf_rsrc0 = ttmp8 +var s_restore_buf_rsrc1 = ttmp9 +var s_restore_buf_rsrc2 = ttmp10 +var s_restore_buf_rsrc3 = ttmp11 + +/**************************************************************************/ +/* trap handler entry points */ +/**************************************************************************/ +/* Shader Main*/ + +shader main + asic(VI) + type(CS) + + + if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) //hack to use trap_id for determining save/restore + //FIXME VCCZ un-init assertion s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC + s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 //change SCC + s_cmp_eq_u32 s_save_tmp, 0x007e0000 //Save: trap_id = 0x7e. Restore: trap_id = 0x7f. + s_cbranch_scc0 L_JUMP_TO_RESTORE //do not need to recover STATUS here since we are going to RESTORE + //FIXME s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //need to recover STATUS since we are going to SAVE + s_branch L_SKIP_RESTORE //NOT restore, SAVE actually + else + s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save + end + +L_JUMP_TO_RESTORE: + s_branch L_RESTORE //restore + +L_SKIP_RESTORE: + + s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC + s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK //check whether this is for save + s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) + s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save + s_cbranch_scc1 L_SAVE //this is the operation for save + + // ********* Handle non-CWSR traps ******************* +if (!EMU_RUN_HACK) + /* read tba and tma for next level trap handler, ttmp4 is used as s_save_status */ + s_load_dwordx4 [ttmp8,ttmp9,ttmp10, ttmp11], [tma_lo,tma_hi], 0 + s_waitcnt lgkmcnt(0) + s_or_b32 ttmp7, ttmp8, ttmp9 + s_cbranch_scc0 L_NO_NEXT_TRAP //next level trap handler not been set + s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //restore HW status(SCC) + s_setpc_b64 [ttmp8,ttmp9] //jump to next level trap handler + +L_NO_NEXT_TRAP: + s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) + s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception + s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly. + s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0 + s_addc_u32 ttmp1, ttmp1, 0 +L_EXCP_CASE: + s_and_b32 ttmp1, ttmp1, 0xFFFF + s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //restore HW status(SCC) + s_rfe_b64 [ttmp0, ttmp1] +end + // ********* End handling of non-CWSR traps ******************* + +/**************************************************************************/ +/* save routine */ +/**************************************************************************/ + +L_SAVE: + +if G8SR_DEBUG_TIMESTAMP + s_memrealtime s_g8sr_ts_save_s + s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? +end + + //check whether there is mem_viol + s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) + s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK + s_cbranch_scc0 L_NO_PC_REWIND + + //if so, need rewind PC assuming GDS operation gets NACKed + s_mov_b32 s_save_tmp, 0 //clear mem_viol bit + s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT, 1), s_save_tmp //clear mem_viol bit + s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] + s_sub_u32 s_save_pc_lo, s_save_pc_lo, 8 //pc[31:0]-8 + s_subb_u32 s_save_pc_hi, s_save_pc_hi, 0x0 // -scc + +L_NO_PC_REWIND: + s_mov_b32 s_save_tmp, 0 //clear saveCtx bit + s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit + + s_mov_b32 s_save_xnack_mask_lo, xnack_mask_lo //save XNACK_MASK + s_mov_b32 s_save_xnack_mask_hi, xnack_mask_hi //save XNACK must before any memory operation + s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) //save RCNT + s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT + s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp + s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) //save FIRST_REPLAY + s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT + s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp + s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY in IB_STS + s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG + + s_setreg_b32 hwreg(HW_REG_IB_STS), s_save_tmp + + /* inform SPI the readiness and wait for SPI's go signal */ + s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI + s_mov_b32 s_save_exec_hi, exec_hi + s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive + +if G8SR_DEBUG_TIMESTAMP + s_memrealtime s_g8sr_ts_sq_save_msg + s_waitcnt lgkmcnt(0) +end + + if (EMU_RUN_HACK) + + else + s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC + end + + L_SLEEP: + s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 + + if (EMU_RUN_HACK) + + else + s_cbranch_execz L_SLEEP + end + +if G8SR_DEBUG_TIMESTAMP + s_memrealtime s_g8sr_ts_spi_wrexec + s_waitcnt lgkmcnt(0) +end + + /* setup Resource Contants */ + if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE)) + //calculate wd_addr using absolute thread id + v_readlane_b32 s_save_tmp, v9, 0 + s_lshr_b32 s_save_tmp, s_save_tmp, 6 + s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE + s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO + s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI + s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL + else + end + if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE)) + s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO + s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI + s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL + else + end + + + s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo + s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi + s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE + s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited + s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC + s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK + s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position + s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC + s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK + s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position + s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE + + //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?) + s_mov_b32 s_save_m0, m0 //save M0 + + /* global mem offset */ + s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0 + + + + + /* save HW registers */ + ////////////////////////////// + + L_SAVE_HWREG: + // HWREG SR memory offset : size(VGPR)+size(SGPR) + get_vgpr_size_bytes(s_save_mem_offset) + get_sgpr_size_bytes(s_save_tmp) + s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp + + + s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes + if (SWIZZLE_EN) + s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? + else + s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + end + + + write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0 + + if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME)) + s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 + s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over + s_mov_b32 tba_lo, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO + s_mov_b32 tba_hi, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI + end + + write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC + write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) + write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC + write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) + write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) //STATUS + + //s_save_trapsts conflicts with s_save_alloc_size + s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) + write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) //TRAPSTS + + write_hwreg_to_mem(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_LO + write_hwreg_to_mem(s_save_xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_HI + + //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2 + s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE + write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) + write_hwreg_to_mem(tba_lo, s_save_buf_rsrc0, s_save_mem_offset) //TBA_LO + write_hwreg_to_mem(tba_hi, s_save_buf_rsrc0, s_save_mem_offset) //TBA_HI + + + + /* the first wave in the threadgroup */ + // save fist_wave bits in tba_hi unused bit.26 + s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit + //s_or_b32 tba_hi, s_save_tmp, tba_hi // save first wave bit to tba_hi.bits[26] + s_mov_b32 s_save_exec_hi, 0x0 + s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26] + + + /* save SGPRs */ + // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... + ////////////////////////////// + + // SGPR SR memory offset : size(VGPR) + get_vgpr_size_bytes(s_save_mem_offset) + // TODO, change RSRC word to rearrange memory layout for SGPRS + + s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size + s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 + s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) + + if (SGPR_SAVE_USE_SQC) + s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes + else + s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) + end + + if (SWIZZLE_EN) + s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? + else + s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + end + + + // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 + //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0 + s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0 + s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset + s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 + + s_mov_b32 m0, 0x0 //SGPR initial index value =0 + L_SAVE_SGPR_LOOP: + // SGPR is allocated in 16 SGPR granularity + s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] + s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] + s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] + s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] + s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] + s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] + s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] + s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] + + write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4 + s_add_u32 m0, m0, 16 //next sgpr index + s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 + s_cbranch_scc1 L_SAVE_SGPR_LOOP //SGPR save is complete? + // restore s_save_buf_rsrc0,1 + //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo + s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo + + + + + /* save first 4 VGPR, then LDS save could use */ + // each wave will alloc 4 vgprs at least... + ///////////////////////////////////////////////////////////////////////////////////// + + s_mov_b32 s_save_mem_offset, 0 + s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on + s_mov_b32 exec_hi, 0xFFFFFFFF + + if (SWIZZLE_EN) + s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? + else + s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + end + + + // VGPR Allocated in 4-GPR granularity + +if G8SR_VGPR_SR_IN_DWX4 + // the const stride for DWx4 is 4*4 bytes + s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 + s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes + + buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 + + s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 + s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes +else + buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 + buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 + buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 + buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 +end + + + + /* save LDS */ + ////////////////////////////// + + L_SAVE_LDS: + + // Change EXEC to all threads... + s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on + s_mov_b32 exec_hi, 0xFFFFFFFF + + s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size + s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? + s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE + + s_barrier //LDS is used? wait for other waves in the same TG + //s_and_b32 s_save_tmp, tba_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here + s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here + s_cbranch_scc0 L_SAVE_LDS_DONE + + // first wave do LDS save; + + s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw + s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes + s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes + + // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) + // + get_vgpr_size_bytes(s_save_mem_offset) + get_sgpr_size_bytes(s_save_tmp) + s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp + s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() + + + if (SWIZZLE_EN) + s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? + else + s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + end + + s_mov_b32 m0, 0x0 //lds_offset initial value = 0 + + +var LDS_DMA_ENABLE = 0 +var UNROLL = 0 +if UNROLL==0 && LDS_DMA_ENABLE==1 + s_mov_b32 s3, 256*2 + s_nop 0 + s_nop 0 + s_nop 0 + L_SAVE_LDS_LOOP: + //TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.??? + if (SAVE_LDS) //SPI always alloc LDS space in 128DW granularity + buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 // first 64DW + buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW + end + + s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes + s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 //mem offset increased by 256 bytes + s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 + s_cbranch_scc1 L_SAVE_LDS_LOOP //LDS save is complete? + +elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL , has ichace miss + // store from higest LDS address to lowest + s_mov_b32 s3, 256*2 + s_sub_u32 m0, s_save_alloc_size, s3 + s_add_u32 s_save_mem_offset, s_save_mem_offset, m0 + s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9 // how many 128 trunks... + s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size // store from higheset addr to lowest + s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4 // PC offset increment, each LDS save block cost 6*4 Bytes instruction + s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4 //2is the below 2 inst...//s_addc and s_setpc + s_nop 0 + s_nop 0 + s_nop 0 //pad 3 dw to let LDS_DMA align with 64Bytes + s_getpc_b64 s[0:1] // reuse s[0:1], since s[0:1] already saved + s_add_u32 s0, s0,s_save_alloc_size + s_addc_u32 s1, s1, 0 + s_setpc_b64 s[0:1] + + + for var i =0; i< 128; i++ + // be careful to make here a 64Byte aligned address, which could improve performance... + buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0 // first 64DW + buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW + + if i!=127 + s_sub_u32 m0, m0, s3 // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e. pack more LDS_DMA inst to one Cacheline + s_sub_u32 s_save_mem_offset, s_save_mem_offset, s3 + end + end + +else // BUFFER_STORE + v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0 + v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid + v_mul_i32_i24 v2, v3, 8 // tid*8 + v_mov_b32 v3, 256*2 + s_mov_b32 m0, 0x10000 + s_mov_b32 s0, s_save_buf_rsrc3 + s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF // disable add_tid + s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000 //DFMT + +L_SAVE_LDS_LOOP_VECTOR: + ds_read_b64 v[0:1], v2 //x =LDS[a], byte address + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1 +// s_waitcnt vmcnt(0) + v_add_u32 v2, vcc[0:1], v2, v3 + v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size + s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR + + // restore rsrc3 + s_mov_b32 s_save_buf_rsrc3, s0 + +end + +L_SAVE_LDS_DONE: + + + /* save VGPRs - set the Rest VGPRs */ + ////////////////////////////////////////////////////////////////////////////////////// + L_SAVE_VGPR: + // VGPR SR memory offset: 0 + // TODO rearrange the RSRC words to use swizzle for VGPR save... + + s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs + s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on + s_mov_b32 exec_hi, 0xFFFFFFFF + + s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size + s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 + s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible + s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) + if (SWIZZLE_EN) + s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? + else + s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + end + + + // VGPR Allocated in 4-GPR granularity + +if G8SR_VGPR_SR_IN_DWX4 + // the const stride for DWx4 is 4*4 bytes + s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 + s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes + + s_mov_b32 m0, 4 // skip first 4 VGPRs + s_cmp_lt_u32 m0, s_save_alloc_size + s_cbranch_scc0 L_SAVE_VGPR_LOOP_END // no more vgprs + + s_set_gpr_idx_on m0, 0x1 // This will change M0 + s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 // because above inst change m0 +L_SAVE_VGPR_LOOP: + v_mov_b32 v0, v0 // v0 = v[0+m0] + v_mov_b32 v1, v1 + v_mov_b32 v2, v2 + v_mov_b32 v3, v3 + + + buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 + s_add_u32 m0, m0, 4 + s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 + s_cmp_lt_u32 m0, s_save_alloc_size + s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? + s_set_gpr_idx_off +L_SAVE_VGPR_LOOP_END: + + s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 + s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes +else + // VGPR store using dw burst + s_mov_b32 m0, 0x4 //VGPR initial index value =0 + s_cmp_lt_u32 m0, s_save_alloc_size + s_cbranch_scc0 L_SAVE_VGPR_END + + + s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 + s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later + + L_SAVE_VGPR_LOOP: + v_mov_b32 v0, v0 //v0 = v[0+m0] + v_mov_b32 v1, v1 //v0 = v[0+m0] + v_mov_b32 v2, v2 //v0 = v[0+m0] + v_mov_b32 v3, v3 //v0 = v[0+m0] + + if(USE_MTBUF_INSTEAD_OF_MUBUF) + tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 + else + buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 + buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 + buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 + buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 + end + + s_add_u32 m0, m0, 4 //next vgpr index + s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes + s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 + s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? + s_set_gpr_idx_off +end + +L_SAVE_VGPR_END: + + + + + + + /* S_PGM_END_SAVED */ //FIXME graphics ONLY + if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT)) + s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] + s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 + s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over + s_rfe_b64 s_save_pc_lo //Return to the main shader program + else + end + +// Save Done timestamp +if G8SR_DEBUG_TIMESTAMP + s_memrealtime s_g8sr_ts_save_d + // SGPR SR memory offset : size(VGPR) + get_vgpr_size_bytes(s_save_mem_offset) + s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET + s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? + // Need reset rsrc2?? + s_mov_b32 m0, s_save_mem_offset + s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0 glc:1 +end + + + s_branch L_END_PGM + + + +/**************************************************************************/ +/* restore routine */ +/**************************************************************************/ + +L_RESTORE: + /* Setup Resource Contants */ + if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) + //calculate wd_addr using absolute thread id + v_readlane_b32 s_restore_tmp, v9, 0 + s_lshr_b32 s_restore_tmp, s_restore_tmp, 6 + s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE + s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO + s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI + s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL + else + end + +if G8SR_DEBUG_TIMESTAMP + s_memrealtime s_g8sr_ts_restore_s + s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? + // tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case... + s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0] + s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1] //backup ts to ttmp0/1, sicne exec will be finally restored.. +end + + + + s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo + s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi + s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE + s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) + s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC + s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK + s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position + s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC + s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK + s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position + s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE + + /* global mem offset */ +// s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0 + + /* the first wave in the threadgroup */ + s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK + s_cbranch_scc0 L_RESTORE_VGPR + + /* restore LDS */ + ////////////////////////////// + L_RESTORE_LDS: + + s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead + s_mov_b32 exec_hi, 0xFFFFFFFF + + s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size + s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? + s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR + s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw + s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes + s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes + + // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) + // + get_vgpr_size_bytes(s_restore_mem_offset) + get_sgpr_size_bytes(s_restore_tmp) + s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp + s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow??? + + + if (SWIZZLE_EN) + s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? + else + s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + end + s_mov_b32 m0, 0x0 //lds_offset initial value = 0 + + L_RESTORE_LDS_LOOP: + if (SAVE_LDS) + buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW + buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW + end + s_add_u32 m0, m0, 256*2 // 128 DW + s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW + s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 + s_cbranch_scc1 L_RESTORE_LDS_LOOP //LDS restore is complete? + + + /* restore VGPRs */ + ////////////////////////////// + L_RESTORE_VGPR: + // VGPR SR memory offset : 0 + s_mov_b32 s_restore_mem_offset, 0x0 + s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead + s_mov_b32 exec_hi, 0xFFFFFFFF + + s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size + s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 + s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) + s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) + if (SWIZZLE_EN) + s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? + else + s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + end + +if G8SR_VGPR_SR_IN_DWX4 + get_vgpr_size_bytes(s_restore_mem_offset) + s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 + + // the const stride for DWx4 is 4*4 bytes + s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 + s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes + + s_mov_b32 m0, s_restore_alloc_size + s_set_gpr_idx_on m0, 0x8 // Note.. This will change m0 + +L_RESTORE_VGPR_LOOP: + buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 + s_waitcnt vmcnt(0) + s_sub_u32 m0, m0, 4 + v_mov_b32 v0, v0 // v[0+m0] = v0 + v_mov_b32 v1, v1 + v_mov_b32 v2, v2 + v_mov_b32 v3, v3 + s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 + s_cmp_eq_u32 m0, 0x8000 + s_cbranch_scc0 L_RESTORE_VGPR_LOOP + s_set_gpr_idx_off + + s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 + s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE // const stride to 4*4 bytes + +else + // VGPR load using dw burst + s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last + s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 + s_mov_b32 m0, 4 //VGPR initial index value = 1 + s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 + s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later + + L_RESTORE_VGPR_LOOP: + if(USE_MTBUF_INSTEAD_OF_MUBUF) + tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 + else + buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 + buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 + buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 + buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 + end + s_waitcnt vmcnt(0) //ensure data ready + v_mov_b32 v0, v0 //v[0+m0] = v0 + v_mov_b32 v1, v1 + v_mov_b32 v2, v2 + v_mov_b32 v3, v3 + s_add_u32 m0, m0, 4 //next vgpr index + s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes + s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 + s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? + s_set_gpr_idx_off + /* VGPR restore on v0 */ + if(USE_MTBUF_INSTEAD_OF_MUBUF) + tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 + else + buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 + buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 + buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 + buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 + end + +end + + /* restore SGPRs */ + ////////////////////////////// + + // SGPR SR memory offset : size(VGPR) + get_vgpr_size_bytes(s_restore_mem_offset) + get_sgpr_size_bytes(s_restore_tmp) + s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp + s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group + // TODO, change RSRC word to rearrange memory layout for SGPRS + + s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size + s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 + s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) + + if (SGPR_SAVE_USE_SQC) + s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes + else + s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) + end + if (SWIZZLE_EN) + s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? + else + s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + end + + /* If 112 SGPRs ar allocated, 4 sgprs are not used TBA(108,109),TMA(110,111), + However, we are safe to restore these 4 SGPRs anyway, since TBA,TMA will later be restored by HWREG + */ + s_mov_b32 m0, s_restore_alloc_size + + L_RESTORE_SGPR_LOOP: + read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) //PV: further performance improvement can be made + s_waitcnt lgkmcnt(0) //ensure data ready + + s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] + + s_movreld_b64 s0, s0 //s[0+m0] = s0 + s_movreld_b64 s2, s2 + s_movreld_b64 s4, s4 + s_movreld_b64 s6, s6 + s_movreld_b64 s8, s8 + s_movreld_b64 s10, s10 + s_movreld_b64 s12, s12 + s_movreld_b64 s14, s14 + + s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0 + s_cbranch_scc0 L_RESTORE_SGPR_LOOP //SGPR restore (except s0) is complete? + + /* restore HW registers */ + ////////////////////////////// + L_RESTORE_HWREG: + + +if G8SR_DEBUG_TIMESTAMP + s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo + s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi +end + + // HWREG SR memory offset : size(VGPR)+size(SGPR) + get_vgpr_size_bytes(s_restore_mem_offset) + get_sgpr_size_bytes(s_restore_tmp) + s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp + + + s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes + if (SWIZZLE_EN) + s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? + else + s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + end + + read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0 + read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC + read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) + read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //EXEC + read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) + read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) //STATUS + read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) //TRAPSTS + read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_LO + read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_HI + read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) //MODE + read_hwreg_from_mem(tba_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //TBA_LO + read_hwreg_from_mem(tba_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //TBA_HI + + s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS + + s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS + + //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise: + if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) + s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8 //pc[31:0]+8 //two back-to-back s_trap are used (first for save and second for restore) + s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over + end + if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL)) + s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4 //pc[31:0]+4 // save is hack through s_trap but restore is normal + s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over + end + + s_mov_b32 m0, s_restore_m0 + s_mov_b32 exec_lo, s_restore_exec_lo + s_mov_b32 exec_hi, s_restore_exec_hi + + s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts + s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 + s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts + s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT + s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 + //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore + s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode + //reuse s_restore_m0 as a temp register + s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK + s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT + s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT + s_mov_b32 s_restore_tmp, 0x0 //IB_STS is zero + s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 + s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK + s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT + s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT + s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 + s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK + s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT + s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_tmp + + s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 + s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 + s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu + + s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time + +if G8SR_DEBUG_TIMESTAMP + s_memrealtime s_g8sr_ts_restore_d + s_waitcnt lgkmcnt(0) +end + +// s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution + s_rfe_restore_b64 s_restore_pc_lo, s_restore_m0 // s_restore_m0[0] is used to set STATUS.inst_atc + + +/**************************************************************************/ +/* the END */ +/**************************************************************************/ +L_END_PGM: + s_endpgm + +end + + +/**************************************************************************/ +/* the helper functions */ +/**************************************************************************/ + +//Only for save hwreg to mem +function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) + s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on + s_mov_b32 m0, s_mem_offset + s_buffer_store_dword s, s_rsrc, m0 glc:1 + s_add_u32 s_mem_offset, s_mem_offset, 4 + s_mov_b32 m0, exec_lo +end + + +// HWREG are saved before SGPRs, so all HWREG could be use. +function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) + + s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 + s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 + s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 + s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 + s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 + s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc +end + + +function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) + s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 + s_add_u32 s_mem_offset, s_mem_offset, 4 +end + +function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) + s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 + s_sub_u32 s_mem_offset, s_mem_offset, 4*16 +end + + + +function get_lds_size_bytes(s_lds_size_byte) + // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW + s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) // lds_size + s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW +end + +function get_vgpr_size_bytes(s_vgpr_size_byte) + s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size + s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 + s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible +end + +function get_sgpr_size_bytes(s_sgpr_size_byte) + s_getreg_b32 s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size + s_add_u32 s_sgpr_size_byte, s_sgpr_size_byte, 1 + s_lshl_b32 s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4 (non-zero value) +end + +function get_hwreg_size_bytes + return 128 //HWREG size 128 bytes +end + + +#endif + +static const uint32_t cwsr_trap_gfx8_hex[] = { + 0xbf820001, 0xbf820123, + 0xb8f4f802, 0x89748674, + 0xb8f5f803, 0x8675ff75, + 0x00000400, 0xbf850011, + 0xc00a1e37, 0x00000000, + 0xbf8c007f, 0x87777978, + 0xbf840002, 0xb974f802, + 0xbe801d78, 0xb8f5f803, + 0x8675ff75, 0x000001ff, + 0xbf850002, 0x80708470, + 0x82718071, 0x8671ff71, + 0x0000ffff, 0xb974f802, + 0xbe801f70, 0xb8f5f803, + 0x8675ff75, 0x00000100, + 0xbf840006, 0xbefa0080, + 0xb97a0203, 0x8671ff71, + 0x0000ffff, 0x80f08870, + 0x82f18071, 0xbefa0080, + 0xb97a0283, 0xbef60068, + 0xbef70069, 0xb8fa1c07, + 0x8e7a9c7a, 0x87717a71, + 0xb8fa03c7, 0x8e7a9b7a, + 0x87717a71, 0xb8faf807, + 0x867aff7a, 0x00007fff, + 0xb97af807, 0xbef2007e, + 0xbef3007f, 0xbefe0180, + 0xbf900004, 0xbf8e0002, + 0xbf88fffe, 0xbef8007e, + 0x8679ff7f, 0x0000ffff, + 0x8779ff79, 0x00040000, + 0xbefa0080, 0xbefb00ff, + 0x00807fac, 0x867aff7f, + 0x08000000, 0x8f7a837a, + 0x877b7a7b, 0x867aff7f, + 0x70000000, 0x8f7a817a, + 0x877b7a7b, 0xbeef007c, + 0xbeee0080, 0xb8ee2a05, + 0x806e816e, 0x8e6e8a6e, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x806e7a6e, + 0xbefa0084, 0xbefa00ff, + 0x01000000, 0xbefe007c, + 0xbefc006e, 0xc0611bfc, + 0x0000007c, 0x806e846e, + 0xbefc007e, 0xbefe007c, + 0xbefc006e, 0xc0611c3c, + 0x0000007c, 0x806e846e, + 0xbefc007e, 0xbefe007c, + 0xbefc006e, 0xc0611c7c, + 0x0000007c, 0x806e846e, + 0xbefc007e, 0xbefe007c, + 0xbefc006e, 0xc0611cbc, + 0x0000007c, 0x806e846e, + 0xbefc007e, 0xbefe007c, + 0xbefc006e, 0xc0611cfc, + 0x0000007c, 0x806e846e, + 0xbefc007e, 0xbefe007c, + 0xbefc006e, 0xc0611d3c, + 0x0000007c, 0x806e846e, + 0xbefc007e, 0xb8f5f803, + 0xbefe007c, 0xbefc006e, + 0xc0611d7c, 0x0000007c, + 0x806e846e, 0xbefc007e, + 0xbefe007c, 0xbefc006e, + 0xc0611dbc, 0x0000007c, + 0x806e846e, 0xbefc007e, + 0xbefe007c, 0xbefc006e, + 0xc0611dfc, 0x0000007c, + 0x806e846e, 0xbefc007e, + 0xb8eff801, 0xbefe007c, + 0xbefc006e, 0xc0611bfc, + 0x0000007c, 0x806e846e, + 0xbefc007e, 0xbefe007c, + 0xbefc006e, 0xc0611b3c, + 0x0000007c, 0x806e846e, + 0xbefc007e, 0xbefe007c, + 0xbefc006e, 0xc0611b7c, + 0x0000007c, 0x806e846e, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbef30080, + 0x8773737a, 0xb8ee2a05, + 0x806e816e, 0x8e6e8a6e, + 0xb8f51605, 0x80758175, + 0x8e758475, 0x8e7a8275, + 0xbefa00ff, 0x01000000, + 0xbef60178, 0x80786e78, + 0x82798079, 0xbefc0080, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003c, 0x00000000, + 0xc06b013c, 0x00000010, + 0xc06b023c, 0x00000020, + 0xc06b033c, 0x00000030, + 0x8078c078, 0x82798079, + 0x807c907c, 0xbf0a757c, + 0xbf85ffeb, 0xbef80176, + 0xbeee0080, 0xbefe00c1, + 0xbeff00c1, 0xbefa00ff, + 0x01000000, 0xe0724000, + 0x6e1e0000, 0xe0724100, + 0x6e1e0100, 0xe0724200, + 0x6e1e0200, 0xe0724300, + 0x6e1e0300, 0xbefe00c1, + 0xbeff00c1, 0xb8f54306, + 0x8675c175, 0xbf84002c, + 0xbf8a0000, 0x867aff73, + 0x04000000, 0xbf840028, + 0x8e758675, 0x8e758275, + 0xbefa0075, 0xb8ee2a05, + 0x806e816e, 0x8e6e8a6e, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x806e7a6e, + 0x806eff6e, 0x00000080, + 0xbefa00ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe80007b, + 0x867bff7b, 0xff7fffff, + 0x877bff7b, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8c007f, 0xe0765000, + 0x6e1e0002, 0x32040702, + 0xd0c9006a, 0x0000eb02, + 0xbf87fff7, 0xbefb0000, + 0xbeee00ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8f52a05, 0x80758175, + 0x8e758275, 0x8e7a8875, + 0xbefa00ff, 0x01000000, + 0xbefc0084, 0xbf0a757c, + 0xbf840015, 0xbf11017c, + 0x8075ff75, 0x00001000, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0xe0724000, 0x6e1e0000, + 0xe0724100, 0x6e1e0100, + 0xe0724200, 0x6e1e0200, + 0xe0724300, 0x6e1e0300, + 0x807c847c, 0x806eff6e, + 0x00000400, 0xbf0a757c, + 0xbf85ffef, 0xbf9c0000, + 0xbf8200ca, 0xbef8007e, + 0x8679ff7f, 0x0000ffff, + 0x8779ff79, 0x00040000, + 0xbefa0080, 0xbefb00ff, + 0x00807fac, 0x8676ff7f, + 0x08000000, 0x8f768376, + 0x877b767b, 0x8676ff7f, + 0x70000000, 0x8f768176, + 0x877b767b, 0x8676ff7f, + 0x04000000, 0xbf84001e, + 0xbefe00c1, 0xbeff00c1, + 0xb8f34306, 0x8673c173, + 0xbf840019, 0x8e738673, + 0x8e738273, 0xbefa0073, + 0xb8f22a05, 0x80728172, + 0x8e728a72, 0xb8f61605, + 0x80768176, 0x8e768676, + 0x80727672, 0x8072ff72, + 0x00000080, 0xbefa00ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x721e0000, + 0xe0510100, 0x721e0000, + 0x807cff7c, 0x00000200, + 0x8072ff72, 0x00000200, + 0xbf0a737c, 0xbf85fff6, + 0xbef20080, 0xbefe00c1, + 0xbeff00c1, 0xb8f32a05, + 0x80738173, 0x8e738273, + 0x8e7a8873, 0xbefa00ff, + 0x01000000, 0xbef60072, + 0x8072ff72, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0x8073ff73, 0x00008000, + 0xe0524000, 0x721e0000, + 0xe0524100, 0x721e0100, + 0xe0524200, 0x721e0200, + 0xe0524300, 0x721e0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8072ff72, 0x00000400, + 0xbf0a737c, 0xbf85ffee, + 0xbf9c0000, 0xe0524000, + 0x761e0000, 0xe0524100, + 0x761e0100, 0xe0524200, + 0x761e0200, 0xe0524300, + 0x761e0300, 0xb8f22a05, + 0x80728172, 0x8e728a72, + 0xb8f61605, 0x80768176, + 0x8e768676, 0x80727672, + 0x80f2c072, 0xb8f31605, + 0x80738173, 0x8e738473, + 0x8e7a8273, 0xbefa00ff, + 0x01000000, 0xbefc0073, + 0xc031003c, 0x00000072, + 0x80f2c072, 0xbf8c007f, + 0x80fc907c, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff1, 0xb8f22a05, + 0x80728172, 0x8e728a72, + 0xb8f61605, 0x80768176, + 0x8e768676, 0x80727672, + 0xbefa0084, 0xbefa00ff, + 0x01000000, 0xc0211cfc, + 0x00000072, 0x80728472, + 0xc0211c3c, 0x00000072, + 0x80728472, 0xc0211c7c, + 0x00000072, 0x80728472, + 0xc0211bbc, 0x00000072, + 0x80728472, 0xc0211bfc, + 0x00000072, 0x80728472, + 0xc0211d3c, 0x00000072, + 0x80728472, 0xc0211d7c, + 0x00000072, 0x80728472, + 0xc0211a3c, 0x00000072, + 0x80728472, 0xc0211a7c, + 0x00000072, 0x80728472, + 0xc0211dfc, 0x00000072, + 0x80728472, 0xc0211b3c, + 0x00000072, 0x80728472, + 0xc0211b7c, 0x00000072, + 0x80728472, 0xbf8c007f, + 0x8671ff71, 0x0000ffff, + 0xbefc0073, 0xbefe006e, + 0xbeff006f, 0x867375ff, + 0x000003ff, 0xb9734803, + 0x867375ff, 0xfffff800, + 0x8f738b73, 0xb973a2c3, + 0xb977f801, 0x8673ff71, + 0xf0000000, 0x8f739c73, + 0x8e739073, 0xbef60080, + 0x87767376, 0x8673ff71, + 0x08000000, 0x8f739b73, + 0x8e738f73, 0x87767376, + 0x8673ff74, 0x00800000, + 0x8f739773, 0xb976f807, + 0x86fe7e7e, 0x86ea6a6a, + 0xb974f802, 0xbf8a0000, + 0x95807370, 0xbf810000, +}; + -- GitLab From 373d7080896a3cb3b28ae3a2abdafb7bb87552b1 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 14 Nov 2017 16:41:19 -0500 Subject: [PATCH 0016/2547] drm/amdkfd: Add CWSR support This hardware feature allows the GPU to preempt shader execution in the middle of a compute wave, save the state and restore it later to resume execution. Memory for saving the state is allocated per queue in user mode and the address and size passed to the create_queue ioctl. The size depends on the number of waves that can be in flight simultaneously on a given ASIC. Signed-off-by: Shaoyun.liu Signed-off-by: Yong Zhao Signed-off-by: Felix Kuehling Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 7 +- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 20 ++++- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 6 ++ drivers/gpu/drm/amd/amdkfd/kfd_module.c | 4 + .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 27 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 31 ++++++- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 87 ++++++++++++++++++- include/uapi/linux/kfd_ioctl.h | 3 +- 8 files changed, 179 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 505d39156acd..2a4612d8437a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -117,7 +117,7 @@ static int kfd_open(struct inode *inode, struct file *filep) return -EPERM; } - process = kfd_create_process(current); + process = kfd_create_process(filep); if (IS_ERR(process)) return PTR_ERR(process); @@ -206,6 +206,7 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, q_properties->ctx_save_restore_area_address = args->ctx_save_restore_address; q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size; + q_properties->ctl_stack_size = args->ctl_stack_size; if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE || args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) q_properties->type = KFD_QUEUE_TYPE_COMPUTE; @@ -1088,6 +1089,10 @@ static int kfd_mmap(struct file *filp, struct vm_area_struct *vma) KFD_MMAP_EVENTS_MASK) { vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_EVENTS_MASK; return kfd_event_mmap(process, vma); + } else if ((vma->vm_pgoff & KFD_MMAP_RESERVED_MEM_MASK) == + KFD_MMAP_RESERVED_MEM_MASK) { + vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_RESERVED_MEM_MASK; + return kfd_reserved_mem_mmap(process, vma); } return -EFAULT; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 621a3b53a038..4f05eacca786 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -27,6 +27,7 @@ #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_pm4_headers_vi.h" +#include "cwsr_trap_handler_gfx8.asm" #define MQD_SIZE_ALIGNED 768 @@ -38,7 +39,8 @@ static const struct kfd_device_info kaveri_device_info = { .ih_ring_entry_size = 4 * sizeof(uint32_t), .event_interrupt_class = &event_interrupt_class_cik, .num_of_watch_points = 4, - .mqd_size_aligned = MQD_SIZE_ALIGNED + .mqd_size_aligned = MQD_SIZE_ALIGNED, + .supports_cwsr = false, }; static const struct kfd_device_info carrizo_device_info = { @@ -49,7 +51,8 @@ static const struct kfd_device_info carrizo_device_info = { .ih_ring_entry_size = 4 * sizeof(uint32_t), .event_interrupt_class = &event_interrupt_class_cik, .num_of_watch_points = 4, - .mqd_size_aligned = MQD_SIZE_ALIGNED + .mqd_size_aligned = MQD_SIZE_ALIGNED, + .supports_cwsr = true, }; struct kfd_deviceid { @@ -212,6 +215,17 @@ static int iommu_invalid_ppr_cb(struct pci_dev *pdev, int pasid, return AMD_IOMMU_INV_PRI_RSP_INVALID; } +static void kfd_cwsr_init(struct kfd_dev *kfd) +{ + if (cwsr_enable && kfd->device_info->supports_cwsr) { + BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); + + kfd->cwsr_isa = cwsr_trap_gfx8_hex; + kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); + kfd->cwsr_enabled = true; + } +} + bool kgd2kfd_device_init(struct kfd_dev *kfd, const struct kgd2kfd_shared_resources *gpu_resources) { @@ -286,6 +300,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, goto device_iommu_pasid_error; } + kfd_cwsr_init(kfd); + if (kfd_resume(kfd)) goto kfd_resume_error; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index e202921c150e..5c065024e285 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -173,6 +173,9 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, *allocated_vmid = qpd->vmid; q->properties.vmid = qpd->vmid; + q->properties.tba_addr = qpd->tba_addr; + q->properties.tma_addr = qpd->tma_addr; + if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) retval = create_compute_queue_nocpsch(dqm, q, qpd); else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) @@ -846,6 +849,9 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, } dqm->asic_ops.init_sdma_vm(dqm, q, qpd); + + q->properties.tba_addr = qpd->tba_addr; + q->properties.tma_addr = qpd->tma_addr; retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj, &q->gart_mqd_addr, &q->properties); if (retval) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index f744caeaee04..ee8adf654cd0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -50,6 +50,10 @@ module_param(sched_policy, int, 0444); MODULE_PARM_DESC(sched_policy, "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); +int cwsr_enable = 1; +module_param(cwsr_enable, int, 0444); +MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); + int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; module_param(max_num_of_queues_per_device, int, 0444); MODULE_PARM_DESC(max_num_of_queues_per_device, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 2ba7cea7b99b..00e1f1a9728b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -89,6 +89,28 @@ static int init_mqd(struct mqd_manager *mm, void **mqd, if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_iq_rptr = 1; + if (q->tba_addr) { + m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8); + m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8); + m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8); + m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8); + m->compute_pgm_rsrc2 |= + (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); + } + + if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) { + m->cp_hqd_persistent_state |= + (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); + m->cp_hqd_ctx_save_base_addr_lo = + lower_32_bits(q->ctx_save_restore_area_address); + m->cp_hqd_ctx_save_base_addr_hi = + upper_32_bits(q->ctx_save_restore_area_address); + m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; + m->cp_hqd_cntl_stack_size = q->ctl_stack_size; + m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; + m->cp_hqd_wg_state_offset = q->ctl_stack_size; + } + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -167,6 +189,11 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT; } + if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) + m->cp_hqd_ctx_save_control = + atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | + mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT; + q->is_active = (q->queue_size > 0 && q->queue_address != 0 && q->queue_percent > 0); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 47504737ab4a..a66876467995 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -41,6 +41,7 @@ #define KFD_MMAP_DOORBELL_MASK 0x8000000000000 #define KFD_MMAP_EVENTS_MASK 0x4000000000000 +#define KFD_MMAP_RESERVED_MEM_MASK 0x2000000000000 /* * When working with cp scheduler we should assign the HIQ manually or via @@ -62,6 +63,15 @@ #define KFD_MAX_NUM_OF_PROCESSES 512 #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024 +/* + * Size of the per-process TBA+TMA buffer: 2 pages + * + * The first page is the TBA used for the CWSR ISA code. The second + * page is used as TMA for daisy changing a user-mode trap handler. + */ +#define KFD_CWSR_TBA_TMA_SIZE (PAGE_SIZE * 2) +#define KFD_CWSR_TMA_OFFSET PAGE_SIZE + /* * Kernel module parameter to specify maximum number of supported queues per * device @@ -78,6 +88,8 @@ extern int max_num_of_queues_per_device; /* Kernel module parameter to specify the scheduling policy */ extern int sched_policy; +extern int cwsr_enable; + /* * Kernel module parameter to specify whether to send sigterm to HSA process on * unhandled exception @@ -131,6 +143,7 @@ struct kfd_device_info { size_t ih_ring_entry_size; uint8_t num_of_watch_points; uint16_t mqd_size_aligned; + bool supports_cwsr; }; struct kfd_mem_obj { @@ -200,6 +213,11 @@ struct kfd_dev { /* Debug manager */ struct kfd_dbgmgr *dbgmgr; + + /* CWSR */ + bool cwsr_enabled; + const void *cwsr_isa; + unsigned int cwsr_isa_size; }; /* KGD2KFD callbacks */ @@ -332,6 +350,9 @@ struct queue_properties { uint32_t eop_ring_buffer_size; uint64_t ctx_save_restore_area_address; uint32_t ctx_save_restore_area_size; + uint32_t ctl_stack_size; + uint64_t tba_addr; + uint64_t tma_addr; }; /** @@ -439,6 +460,11 @@ struct qcm_process_device { uint32_t num_gws; uint32_t num_oac; uint32_t sh_hidden_private_base; + + /* CWSR memory */ + void *cwsr_kaddr; + uint64_t tba_addr; + uint64_t tma_addr; }; @@ -563,7 +589,7 @@ struct amdkfd_ioctl_desc { void kfd_process_create_wq(void); void kfd_process_destroy_wq(void); -struct kfd_process *kfd_create_process(const struct task_struct *); +struct kfd_process *kfd_create_process(struct file *filep); struct kfd_process *kfd_get_process(const struct task_struct *); struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid); @@ -577,6 +603,9 @@ struct kfd_process_device *kfd_get_process_device_data(struct kfd_dev *dev, struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev, struct kfd_process *p); +int kfd_reserved_mem_mmap(struct kfd_process *process, + struct vm_area_struct *vma); + /* Process device data iterator */ struct kfd_process_device *kfd_get_first_process_device_data( struct kfd_process *p); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 1bb9b2643d5a..39f4c19aaf61 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -28,6 +28,7 @@ #include #include #include +#include struct mm_struct; @@ -53,6 +54,8 @@ struct kfd_process_release_work { static struct kfd_process *find_process(const struct task_struct *thread); static struct kfd_process *create_process(const struct task_struct *thread); +static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep); + void kfd_process_create_wq(void) { @@ -68,9 +71,10 @@ void kfd_process_destroy_wq(void) } } -struct kfd_process *kfd_create_process(const struct task_struct *thread) +struct kfd_process *kfd_create_process(struct file *filep) { struct kfd_process *process; + struct task_struct *thread = current; if (!thread->mm) return ERR_PTR(-EINVAL); @@ -101,6 +105,8 @@ struct kfd_process *kfd_create_process(const struct task_struct *thread) up_write(&thread->mm->mmap_sem); + kfd_process_init_cwsr(process, filep); + return process; } @@ -168,6 +174,11 @@ static void kfd_process_wq_release(struct work_struct *work) amd_iommu_unbind_pasid(pdd->dev->pdev, p->pasid); list_del(&pdd->per_device_list); + + if (pdd->qpd.cwsr_kaddr) + free_pages((unsigned long)pdd->qpd.cwsr_kaddr, + get_order(KFD_CWSR_TBA_TMA_SIZE)); + kfree(pdd); } @@ -260,6 +271,46 @@ static const struct mmu_notifier_ops kfd_process_mmu_notifier_ops = { .release = kfd_process_notifier_release, }; +static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep) +{ + int err = 0; + unsigned long offset; + struct kfd_process_device *temp, *pdd = NULL; + struct kfd_dev *dev = NULL; + struct qcm_process_device *qpd = NULL; + + mutex_lock(&p->mutex); + list_for_each_entry_safe(pdd, temp, &p->per_device_data, + per_device_list) { + dev = pdd->dev; + qpd = &pdd->qpd; + if (!dev->cwsr_enabled || qpd->cwsr_kaddr) + continue; + offset = (dev->id | KFD_MMAP_RESERVED_MEM_MASK) << PAGE_SHIFT; + qpd->tba_addr = (int64_t)vm_mmap(filep, 0, + KFD_CWSR_TBA_TMA_SIZE, PROT_READ | PROT_EXEC, + MAP_SHARED, offset); + + if (IS_ERR_VALUE(qpd->tba_addr)) { + pr_err("Failure to set tba address. error -%d.\n", + (int)qpd->tba_addr); + err = qpd->tba_addr; + qpd->tba_addr = 0; + qpd->cwsr_kaddr = NULL; + goto out; + } + + memcpy(qpd->cwsr_kaddr, dev->cwsr_isa, dev->cwsr_isa_size); + + qpd->tma_addr = qpd->tba_addr + KFD_CWSR_TMA_OFFSET; + pr_debug("set tba :0x%llx, tma:0x%llx, cwsr_kaddr:%p for pqm.\n", + qpd->tba_addr, qpd->tma_addr, qpd->cwsr_kaddr); + } +out: + mutex_unlock(&p->mutex); + return err; +} + static struct kfd_process *create_process(const struct task_struct *thread) { struct kfd_process *process; @@ -535,3 +586,37 @@ struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid) return p; } + +int kfd_reserved_mem_mmap(struct kfd_process *process, + struct vm_area_struct *vma) +{ + struct kfd_dev *dev = kfd_device_by_id(vma->vm_pgoff); + struct kfd_process_device *pdd; + struct qcm_process_device *qpd; + + if (!dev) + return -EINVAL; + if ((vma->vm_end - vma->vm_start) != KFD_CWSR_TBA_TMA_SIZE) { + pr_err("Incorrect CWSR mapping size.\n"); + return -EINVAL; + } + + pdd = kfd_get_process_device_data(dev, process); + if (!pdd) + return -EINVAL; + qpd = &pdd->qpd; + + qpd->cwsr_kaddr = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, + get_order(KFD_CWSR_TBA_TMA_SIZE)); + if (!qpd->cwsr_kaddr) { + pr_err("Error allocating per process CWSR buffer.\n"); + return -ENOMEM; + } + + vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND + | VM_NORESERVE | VM_DONTDUMP | VM_PFNMAP; + /* Mapping pages to user process */ + return remap_pfn_range(vma, vma->vm_start, + PFN_DOWN(__pa(qpd->cwsr_kaddr)), + KFD_CWSR_TBA_TMA_SIZE, vma->vm_page_prot); +} diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 6e80501368ae..f7563ef2e883 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -58,7 +58,8 @@ struct kfd_ioctl_create_queue_args { __u64 eop_buffer_address; /* to KFD */ __u64 eop_buffer_size; /* to KFD */ __u64 ctx_save_restore_address; /* to KFD */ - __u64 ctx_save_restore_size; /* to KFD */ + __u32 ctx_save_restore_size; /* to KFD */ + __u32 ctl_stack_size; /* to KFD */ }; struct kfd_ioctl_destroy_queue_args { -- GitLab From d7b9bd2248d794275b53d34e665f7c5a08c4b396 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 14 Nov 2017 16:41:20 -0500 Subject: [PATCH 0017/2547] drm/amdkfd: Add support for user-mode trap handlers A second-level user mode trap handler can be installed. The CWSR trap handler jumps to the secondary trap handler conditionally for any conditions not handled by it. This can be used e.g. for debugging or catching math exceptions. When CWSR is disabled, the user mode trap handler is installed as first level trap handler. Signed-off-by: Shaoyun.liu Signed-off-by: Jay Cornwall Signed-off-by: Felix Kuehling Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 37 ++++++++++++++++++- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 22 +++++++++++ .../drm/amd/amdkfd/kfd_device_queue_manager.h | 5 +++ include/uapi/linux/kfd_ioctl.h | 12 +++++- 4 files changed, 74 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 2a4612d8437a..cc61ec289880 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -432,6 +432,38 @@ static int kfd_ioctl_set_memory_policy(struct file *filep, return err; } +static int kfd_ioctl_set_trap_handler(struct file *filep, + struct kfd_process *p, void *data) +{ + struct kfd_ioctl_set_trap_handler_args *args = data; + struct kfd_dev *dev; + int err = 0; + struct kfd_process_device *pdd; + + dev = kfd_device_by_id(args->gpu_id); + if (dev == NULL) + return -EINVAL; + + mutex_lock(&p->mutex); + + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + err = -ESRCH; + goto out; + } + + if (dev->dqm->ops.set_trap_handler(dev->dqm, + &pdd->qpd, + args->tba_addr, + args->tma_addr)) + err = -EINVAL; + +out: + mutex_unlock(&p->mutex); + + return err; +} + static int kfd_ioctl_dbg_register(struct file *filep, struct kfd_process *p, void *data) { @@ -980,7 +1012,10 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { kfd_ioctl_set_scratch_backing_va, 0), AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG, - kfd_ioctl_get_tile_config, 0) + kfd_ioctl_get_tile_config, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER, + kfd_ioctl_set_trap_handler, 0), }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 5c065024e285..8447810c9a1e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1116,6 +1116,26 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, return retval; } +static int set_trap_handler(struct device_queue_manager *dqm, + struct qcm_process_device *qpd, + uint64_t tba_addr, + uint64_t tma_addr) +{ + uint64_t *tma; + + if (dqm->dev->cwsr_enabled) { + /* Jump from CWSR trap handler to user trap */ + tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); + tma[0] = tba_addr; + tma[1] = tma_addr; + } else { + qpd->tba_addr = tba_addr; + qpd->tma_addr = tma_addr; + } + + return 0; +} + static int process_termination_nocpsch(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { @@ -1247,6 +1267,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) dqm->ops.create_kernel_queue = create_kernel_queue_cpsch; dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch; dqm->ops.set_cache_memory_policy = set_cache_memory_policy; + dqm->ops.set_trap_handler = set_trap_handler; dqm->ops.process_termination = process_termination_cpsch; break; case KFD_SCHED_POLICY_NO_HWS: @@ -1262,6 +1283,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) dqm->ops.initialize = initialize_nocpsch; dqm->ops.uninitialize = uninitialize; dqm->ops.set_cache_memory_policy = set_cache_memory_policy; + dqm->ops.set_trap_handler = set_trap_handler; dqm->ops.process_termination = process_termination_nocpsch; break; default: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 5b77cb69f732..8752edf9cd9b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -123,6 +123,11 @@ struct device_queue_manager_ops { void __user *alternate_aperture_base, uint64_t alternate_aperture_size); + int (*set_trap_handler)(struct device_queue_manager *dqm, + struct qcm_process_device *qpd, + uint64_t tba_addr, + uint64_t tma_addr); + int (*process_termination)(struct device_queue_manager *dqm, struct qcm_process_device *qpd); }; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index f7563ef2e883..f4cab5b3ba9a 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -262,6 +262,13 @@ struct kfd_ioctl_get_tile_config_args { */ }; +struct kfd_ioctl_set_trap_handler_args { + uint64_t tba_addr; /* to KFD */ + uint64_t tma_addr; /* to KFD */ + uint32_t gpu_id; /* to KFD */ + uint32_t pad; +}; + #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) @@ -322,7 +329,10 @@ struct kfd_ioctl_get_tile_config_args { #define AMDKFD_IOC_GET_TILE_CONFIG \ AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) +#define AMDKFD_IOC_SET_TRAP_HANDLER \ + AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args) + #define AMDKFD_COMMAND_START 0x01 -#define AMDKFD_COMMAND_END 0x13 +#define AMDKFD_COMMAND_END 0x14 #endif -- GitLab From 0e18dd12064e07519f7cbff4149ca7fff620cbed Mon Sep 17 00:00:00 2001 From: Vasily Averin Date: Wed, 15 Nov 2017 08:47:02 +0300 Subject: [PATCH 0018/2547] perf/core: Fix memory leak triggered by perf --namespace perf with --namespace key leaks various memory objects including namespaces 4.14.0+ pid_namespace 1 12 2568 12 8 user_namespace 1 39 824 39 8 net_namespace 1 5 6272 5 8 This happen because perf_fill_ns_link_info() struct patch ns_path: during initialization ns_path incremented counters on related mnt and dentry, but without lost path_put nobody decremented them back. Leaked dentry is name of related namespace, and its leak does not allow to free unused namespace. Signed-off-by: Vasily Averin Acked-by: Peter Zijlstra Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Hari Bathini Cc: Jiri Olsa Cc: Linus Torvalds Cc: Namhyung Kim Cc: Thomas Gleixner Fixes: commit e422267322cd ("perf: Add PERF_RECORD_NAMESPACES to include namespaces related info") Link: http://lkml.kernel.org/r/c510711b-3904-e5e1-d296-61273d21118d@virtuozzo.com Signed-off-by: Ingo Molnar --- kernel/events/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/events/core.c b/kernel/events/core.c index 10cdb9c26b5d..ab5ac84f82e2 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -6756,6 +6756,7 @@ static void perf_fill_ns_link_info(struct perf_ns_link_info *ns_link_info, ns_inode = ns_path.dentry->d_inode; ns_link_info->dev = new_encode_dev(ns_inode->i_sb->s_dev); ns_link_info->ino = ns_inode->i_ino; + path_put(&ns_path); } } -- GitLab From 30b4e122d71cbec2944a5f8b558b88936ee42f10 Mon Sep 17 00:00:00 2001 From: Sean Young Date: Wed, 8 Nov 2017 16:19:45 -0500 Subject: [PATCH 0019/2547] media: rc: sir_ir: detect presence of port Without this test, sir_ir clumsy claims resources for a device which does not exist. The 0-day kernel test robot reports the following errors (in a loop): sir_ir sir_ir.0: Trapped in interrupt genirq: Flags mismatch irq 4. 00000000 (ttyS0) vs. 00000000 (sir_ir) When sir_ir is loaded with the default io and irq, the following happens: - sir_ir claims irq 4 - user space opens /dev/ttyS0 - in serial8250_do_startup(), some setup is done for ttyS0, which causes irq 4 to fire (in THRE test) - sir_ir does not realise it was not for it, and spins until the "trapped in interrupt" - now serial driver calls setup_irq() and fails and we get the "Flags mismatch" error. There is no port present at 0x3e8 so simply check for the presence of a port, as suggested by Linus. Reported-by: kbuild test robot Tested-by: Fengguang Wu Signed-off-by: Sean Young Cc: # 4.12+ Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/sir_ir.c | 40 +++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/media/rc/sir_ir.c b/drivers/media/rc/sir_ir.c index 76120664b700..9ee2c9196b4d 100644 --- a/drivers/media/rc/sir_ir.c +++ b/drivers/media/rc/sir_ir.c @@ -57,7 +57,7 @@ static void add_read_queue(int flag, unsigned long val); static irqreturn_t sir_interrupt(int irq, void *dev_id); static void send_space(unsigned long len); static void send_pulse(unsigned long len); -static void init_hardware(void); +static int init_hardware(void); static void drop_hardware(void); /* Initialisation */ @@ -263,11 +263,36 @@ static void send_pulse(unsigned long len) } } -static void init_hardware(void) +static int init_hardware(void) { + u8 scratch, scratch2, scratch3; unsigned long flags; spin_lock_irqsave(&hardware_lock, flags); + + /* + * This is a simple port existence test, borrowed from the autoconfig + * function in drivers/tty/serial/8250/8250_port.c + */ + scratch = sinp(UART_IER); + soutp(UART_IER, 0); +#ifdef __i386__ + outb(0xff, 0x080); +#endif + scratch2 = sinp(UART_IER) & 0x0f; + soutp(UART_IER, 0x0f); +#ifdef __i386__ + outb(0x00, 0x080); +#endif + scratch3 = sinp(UART_IER) & 0x0f; + soutp(UART_IER, scratch); + if (scratch2 != 0 || scratch3 != 0x0f) { + /* we fail, there's nothing here */ + spin_unlock_irqrestore(&hardware_lock, flags); + pr_err("port existence test failed, cannot continue\n"); + return -ENODEV; + } + /* reset UART */ outb(0, io + UART_MCR); outb(0, io + UART_IER); @@ -285,6 +310,8 @@ static void init_hardware(void) /* turn on UART */ outb(UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2, io + UART_MCR); spin_unlock_irqrestore(&hardware_lock, flags); + + return 0; } static void drop_hardware(void) @@ -334,14 +361,19 @@ static int sir_ir_probe(struct platform_device *dev) pr_err("IRQ %d already in use.\n", irq); return retval; } + + retval = init_hardware(); + if (retval) { + del_timer_sync(&timerlist); + return retval; + } + pr_info("I/O port 0x%.4x, IRQ %d.\n", io, irq); retval = devm_rc_register_device(&sir_ir_dev->dev, rcdev); if (retval < 0) return retval; - init_hardware(); - return 0; } -- GitLab From 014d6da6cb2525d7f48fb08c705cb130cc7b5f4a Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 29 Oct 2017 12:49:05 +0100 Subject: [PATCH 0020/2547] ARM: dts: bcm283x: Fix DTC warnings about missing phy-cells This patch fixes the DTC warnings about missing property #phy-cells. Signed-off-by: Stefan Wahren Signed-off-by: Eric Anholt Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm283x.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 013431e3d7c3..dcde93c85c2d 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -639,5 +639,6 @@ usbphy: phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; }; -- GitLab From c20c6704bf2dafaba0d90c8310ef9e919fe4d2e2 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 16 Nov 2017 04:36:51 +0000 Subject: [PATCH 0021/2547] ASoC: rcar: revert IOMMU support so far commit 4821d914fe74 ("ASoC: rsnd: use dma_sync_single_for_xxx() for IOMMU") had supported IOMMU, but it breaks normal sound "recorde" and both PulseAudio's "playback/recorde". The sound will be noisy. That commit was using dma_sync_single_for_xxx(), and driver should make sure memory is protected during CPU or Device are using it. But if driver returns current "residue" data size correctly on pointer function, player/recorder will access to protected memory. IOMMU feature should be supported, but I don't know how to handle it without memory cache problem at this point. Thus, this patch simply revert it to avoid current noisy sound. Tested-by: Hiroyuki Yokoyama Tested-by: Ryo Kodama Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- sound/soc/sh/rcar/core.c | 4 +- sound/soc/sh/rcar/dma.c | 86 +++------------------------------------- 2 files changed, 8 insertions(+), 82 deletions(-) diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c index c70eb2097816..f12a88a21dfa 100644 --- a/sound/soc/sh/rcar/core.c +++ b/sound/soc/sh/rcar/core.c @@ -1332,8 +1332,8 @@ static int rsnd_pcm_new(struct snd_soc_pcm_runtime *rtd) return snd_pcm_lib_preallocate_pages_for_all( rtd->pcm, - SNDRV_DMA_TYPE_CONTINUOUS, - snd_dma_continuous_data(GFP_KERNEL), + SNDRV_DMA_TYPE_DEV, + rtd->card->snd_card->dev, PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); } diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c index fd557abfe390..4d750bdf8e24 100644 --- a/sound/soc/sh/rcar/dma.c +++ b/sound/soc/sh/rcar/dma.c @@ -26,10 +26,7 @@ struct rsnd_dmaen { struct dma_chan *chan; dma_cookie_t cookie; - dma_addr_t dma_buf; unsigned int dma_len; - unsigned int dma_period; - unsigned int dma_cnt; }; struct rsnd_dmapp { @@ -71,38 +68,10 @@ static struct rsnd_mod mem = { /* * Audio DMAC */ -#define rsnd_dmaen_sync(dmaen, io, i) __rsnd_dmaen_sync(dmaen, io, i, 1) -#define rsnd_dmaen_unsync(dmaen, io, i) __rsnd_dmaen_sync(dmaen, io, i, 0) -static void __rsnd_dmaen_sync(struct rsnd_dmaen *dmaen, struct rsnd_dai_stream *io, - int i, int sync) -{ - struct device *dev = dmaen->chan->device->dev; - enum dma_data_direction dir; - int is_play = rsnd_io_is_play(io); - dma_addr_t buf; - int len, max; - size_t period; - - len = dmaen->dma_len; - period = dmaen->dma_period; - max = len / period; - i = i % max; - buf = dmaen->dma_buf + (period * i); - - dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE; - - if (sync) - dma_sync_single_for_device(dev, buf, period, dir); - else - dma_sync_single_for_cpu(dev, buf, period, dir); -} - static void __rsnd_dmaen_complete(struct rsnd_mod *mod, struct rsnd_dai_stream *io) { struct rsnd_priv *priv = rsnd_mod_to_priv(mod); - struct rsnd_dma *dma = rsnd_mod_to_dma(mod); - struct rsnd_dmaen *dmaen = rsnd_dma_to_dmaen(dma); bool elapsed = false; unsigned long flags; @@ -115,22 +84,9 @@ static void __rsnd_dmaen_complete(struct rsnd_mod *mod, */ spin_lock_irqsave(&priv->lock, flags); - if (rsnd_io_is_working(io)) { - rsnd_dmaen_unsync(dmaen, io, dmaen->dma_cnt); - - /* - * Next period is already started. - * Let's sync Next Next period - * see - * rsnd_dmaen_start() - */ - rsnd_dmaen_sync(dmaen, io, dmaen->dma_cnt + 2); - + if (rsnd_io_is_working(io)) elapsed = true; - dmaen->dma_cnt++; - } - spin_unlock_irqrestore(&priv->lock, flags); if (elapsed) @@ -165,14 +121,8 @@ static int rsnd_dmaen_stop(struct rsnd_mod *mod, struct rsnd_dma *dma = rsnd_mod_to_dma(mod); struct rsnd_dmaen *dmaen = rsnd_dma_to_dmaen(dma); - if (dmaen->chan) { - int is_play = rsnd_io_is_play(io); - + if (dmaen->chan) dmaengine_terminate_all(dmaen->chan); - dma_unmap_single(dmaen->chan->device->dev, - dmaen->dma_buf, dmaen->dma_len, - is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE); - } return 0; } @@ -237,11 +187,7 @@ static int rsnd_dmaen_start(struct rsnd_mod *mod, struct device *dev = rsnd_priv_to_dev(priv); struct dma_async_tx_descriptor *desc; struct dma_slave_config cfg = {}; - dma_addr_t buf; - size_t len; - size_t period; int is_play = rsnd_io_is_play(io); - int i; int ret; cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; @@ -258,19 +204,10 @@ static int rsnd_dmaen_start(struct rsnd_mod *mod, if (ret < 0) return ret; - len = snd_pcm_lib_buffer_bytes(substream); - period = snd_pcm_lib_period_bytes(substream); - buf = dma_map_single(dmaen->chan->device->dev, - substream->runtime->dma_area, - len, - is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE); - if (dma_mapping_error(dmaen->chan->device->dev, buf)) { - dev_err(dev, "dma map failed\n"); - return -EIO; - } - desc = dmaengine_prep_dma_cyclic(dmaen->chan, - buf, len, period, + substream->runtime->dma_addr, + snd_pcm_lib_buffer_bytes(substream), + snd_pcm_lib_period_bytes(substream), is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); @@ -282,18 +219,7 @@ static int rsnd_dmaen_start(struct rsnd_mod *mod, desc->callback = rsnd_dmaen_complete; desc->callback_param = rsnd_mod_get(dma); - dmaen->dma_buf = buf; - dmaen->dma_len = len; - dmaen->dma_period = period; - dmaen->dma_cnt = 0; - - /* - * synchronize this and next period - * see - * __rsnd_dmaen_complete() - */ - for (i = 0; i < 2; i++) - rsnd_dmaen_sync(dmaen, io, i); + dmaen->dma_len = snd_pcm_lib_buffer_bytes(substream); dmaen->cookie = dmaengine_submit(desc); if (dmaen->cookie < 0) { -- GitLab From 8c059a4676038967dd6efe614538c329b61e68a1 Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Wed, 15 Nov 2017 11:52:32 -0800 Subject: [PATCH 0022/2547] spi: imx: Update device tree binding documentation Update documentation for gpio-cs and num-cs to reflect the standard SPI bindings. The dma properties are optional. Include a warning that native CS do not work in a commonly useful manner with this hardware/driver, and therefor most users probably should use GPIO based CS lines rather than native. CC: Mark Brown CC: Shawn Guo CC: Sascha Hauer CC: Fabio Estevam CC: Oleksij Rempel Signed-off-by: Trent Piepho Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/fsl-imx-cspi.txt | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt index 5bf13960f7f4..e3c48b20b1a6 100644 --- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt @@ -12,24 +12,30 @@ Required properties: - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc - reg : Offset and length of the register set for the device - interrupts : Should contain CSPI/eCSPI interrupt -- cs-gpios : Specifies the gpio pins to be used for chipselects. - clocks : Clock specifiers for both ipg and per clocks. - clock-names : Clock names should include both "ipg" and "per" See the clock consumer binding, Documentation/devicetree/bindings/clock/clock-bindings.txt -- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: DMA request names should include "tx" and "rx" if present. -Obsolete properties: -- fsl,spi-num-chipselects : Contains the number of the chipselect +Recommended properties: +- cs-gpios : GPIOs to use as chip selects, see spi-bus.txt. While the native chip +select lines can be used, they appear to always generate a pulse between each +word of a transfer. Most use cases will require GPIO based chip selects to +generate a valid transaction. Optional properties: +- num-cs : Number of total chip selects, see spi-bus.txt. +- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, +Documentation/devicetree/bindings/dma/dma.txt. +- dma-names: DMA request names, if present, should include "tx" and "rx". - fsl,spi-rdy-drctl: Integer, representing the value of DRCTL, the register controlling the SPI_READY handling. Note that to enable the DRCTL consideration, the SPI_READY mode-flag needs to be set too. Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst). +Obsolete properties: +- fsl,spi-num-chipselects : Contains the number of the chipselect + Example: ecspi@70010000 { -- GitLab From 4c761ebfcb2d04ee36783c4c8c45ae00caf59d36 Mon Sep 17 00:00:00 2001 From: Naveen Manohar Date: Fri, 3 Nov 2017 19:15:02 +0530 Subject: [PATCH 0023/2547] ASoC: Intel: kbl: Modify map for Headset Playback to fix pop-noise Patch fixes wrong path in commit 0b06122fc8d0 ("ASoC: Intel: kbl: Add map for new DAIs for Multi-Playback & Echo Ref") which resulted in pop noise. Current topology for Headset results in unwanted pop noise, while switching from spk->hs at the start of Headset Playback. Hence re-introduced mixin-mixout dsp module in topology for headset playback pipe to fix the regression. And the corresponding modification for headset route is updated here. Fixes: 0b06122fc8d0 ("ASoC: Intel: kbl: Add map for new DAIs for Multi-Playback & Echo Ref") Signed-off-by: Naveen Manohar Signed-off-by: Sathya Prakash M R Acked-By: Vinod Koul Signed-off-by: Mark Brown --- sound/soc/intel/boards/kbl_rt5663_max98927.c | 2 +- sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/intel/boards/kbl_rt5663_max98927.c b/sound/soc/intel/boards/kbl_rt5663_max98927.c index 6f9a8bcf20f3..6dcad0a8a0d0 100644 --- a/sound/soc/intel/boards/kbl_rt5663_max98927.c +++ b/sound/soc/intel/boards/kbl_rt5663_max98927.c @@ -101,7 +101,7 @@ static const struct snd_soc_dapm_route kabylake_map[] = { { "ssp0 Tx", NULL, "spk_out" }, { "AIF Playback", NULL, "ssp1 Tx" }, - { "ssp1 Tx", NULL, "hs_out" }, + { "ssp1 Tx", NULL, "codec1_out" }, { "hs_in", NULL, "ssp1 Rx" }, { "ssp1 Rx", NULL, "AIF Capture" }, diff --git a/sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c b/sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c index 6072164f2d43..271ae3c2c535 100644 --- a/sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c +++ b/sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c @@ -109,7 +109,7 @@ static const struct snd_soc_dapm_route kabylake_map[] = { { "ssp0 Tx", NULL, "spk_out" }, { "AIF Playback", NULL, "ssp1 Tx" }, - { "ssp1 Tx", NULL, "hs_out" }, + { "ssp1 Tx", NULL, "codec1_out" }, { "hs_in", NULL, "ssp1 Rx" }, { "ssp1 Rx", NULL, "AIF Capture" }, -- GitLab From bc6476d6c1edcb9b97621b5131bd169aa81f27db Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 13 Nov 2017 12:12:55 +0100 Subject: [PATCH 0024/2547] ASoC: da7218: fix fix child-node lookup Fix child-node lookup during probe, which ended up searching the whole device tree depth-first starting at the parent rather than just matching on its children. To make things worse, the parent codec node was also prematurely freed. Fixes: 4d50934abd22 ("ASoC: da7218: Add da7218 codec driver") Signed-off-by: Johan Hovold Acked-by: Adam Thomson Signed-off-by: Mark Brown Cc: stable --- sound/soc/codecs/da7218.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/da7218.c b/sound/soc/codecs/da7218.c index b2d42ec1dcd9..56564ce90cb6 100644 --- a/sound/soc/codecs/da7218.c +++ b/sound/soc/codecs/da7218.c @@ -2520,7 +2520,7 @@ static struct da7218_pdata *da7218_of_to_pdata(struct snd_soc_codec *codec) } if (da7218->dev_id == DA7218_DEV_ID) { - hpldet_np = of_find_node_by_name(np, "da7218_hpldet"); + hpldet_np = of_get_child_by_name(np, "da7218_hpldet"); if (!hpldet_np) return pdata; -- GitLab From 15f8c5f2415bfac73f33a14bcd83422bcbfb5298 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 13 Nov 2017 12:12:56 +0100 Subject: [PATCH 0025/2547] ASoC: twl4030: fix child-node lookup Fix child-node lookup during probe, which ended up searching the whole device tree depth-first starting at the parent rather than just matching on its children. To make things worse, the parent codec node was also prematurely freed, while the child node was leaked. Fixes: 2d6d649a2e0f ("ASoC: twl4030: Support for DT booted kernel") Signed-off-by: Johan Hovold Signed-off-by: Mark Brown Cc: stable --- sound/soc/codecs/twl4030.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index c482b2e7a7d2..cfe72b9d4356 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -232,7 +232,7 @@ static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec) struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev); struct device_node *twl4030_codec_node = NULL; - twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node, + twl4030_codec_node = of_get_child_by_name(codec->dev->parent->of_node, "codec"); if (!pdata && twl4030_codec_node) { @@ -241,9 +241,11 @@ static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec) GFP_KERNEL); if (!pdata) { dev_err(codec->dev, "Can not allocate memory\n"); + of_node_put(twl4030_codec_node); return NULL; } twl4030_setup_pdata_of(pdata, twl4030_codec_node); + of_node_put(twl4030_codec_node); } return pdata; -- GitLab From 29a90b70893817e2f2bb3cea40a29f5308e21b21 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Thu, 28 Sep 2017 15:14:01 +0100 Subject: [PATCH 0026/2547] iommu/vt-d: Fix scatterlist offset handling The intel-iommu DMA ops fail to correctly handle scatterlists where sg->offset is greater than PAGE_SIZE - the IOVA allocation is computed appropriately based on the page-aligned portion of the offset, but the mapping is set up relative to sg->page, which means it fails to actually cover the whole buffer (and in the worst case doesn't cover it at all): (sg->dma_address + sg->dma_len) ----+ sg->dma_address ---------+ | iov_pfn------+ | | | | | v v v iova: a b c d e f |--------|--------|--------|--------|--------| <...calculated....> [_____mapped______] pfn: 0 1 2 3 4 5 |--------|--------|--------|--------|--------| ^ ^ ^ | | | sg->page ----+ | | sg->offset --------------+ | (sg->offset + sg->length) ----------+ As a result, the caller ends up overrunning the mapping into whatever lies beyond, which usually goes badly: [ 429.645492] DMAR: DRHD: handling fault status reg 2 [ 429.650847] DMAR: [DMA Write] Request device [02:00.4] fault addr f2682000 ... Whilst this is a fairly rare occurrence, it can happen from the result of intermediate scatterlist processing such as scatterwalk_ffwd() in the crypto layer. Whilst that particular site could be fixed up, it still seems worthwhile to bring intel-iommu in line with other DMA API implementations in handling this robustly. To that end, fix the intel_map_sg() path to line up the mapping correctly (in units of MM pages rather than VT-d pages to match the aligned_nrpages() calculation) regardless of the offset, and use sg_phys() consistently for clarity. Reported-by: Harsh Jain Signed-off-by: Robin Murphy Reviewed by: Ashok Raj Tested by: Jacob Pan Cc: stable@vger.kernel.org Signed-off-by: Alex Williamson --- drivers/iommu/intel-iommu.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index a0babdbf7146..4a2de34895ec 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -2250,10 +2250,12 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, uint64_t tmp; if (!sg_res) { + unsigned int pgoff = sg->offset & ~PAGE_MASK; + sg_res = aligned_nrpages(sg->offset, sg->length); - sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; + sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + pgoff; sg->dma_length = sg->length; - pteval = page_to_phys(sg_page(sg)) | prot; + pteval = (sg_phys(sg) - pgoff) | prot; phys_pfn = pteval >> VTD_PAGE_SHIFT; } @@ -3787,7 +3789,7 @@ static int intel_nontranslate_map_sg(struct device *hddev, for_each_sg(sglist, sg, nelems, i) { BUG_ON(!sg_page(sg)); - sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset; + sg->dma_address = sg_phys(sg); sg->dma_length = sg->length; } return nelems; -- GitLab From 098f53050154498876ef3febde706ff5c8b25cf4 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 16 Nov 2017 14:35:57 +0100 Subject: [PATCH 0027/2547] ARM: dts: r8a779x: Add '#reset-cells' in cpg-mssr With the latest dtc, we get many warnings about the missing '#reset-cells' property in these controllers, e.g.: arch/arm/boot/dts/r8a7790-lager.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /can@e6e80000:resets[0]) arch/arm/boot/dts/r8a7792-blanche.dtb: Warning (resets_property): Missing property '#reset-cells' in node /soc/clock-controller@e6150000 or bad phandle (referred from /soc/dma-controller@e6700000:resets[0]) arch/arm/boot/dts/r8a7792-wheat.dtb: Warning (resets_property): Missing property '#reset-cells' in node /soc/clock-controller@e6150000 or bad phandle (referred from /soc/ethernet@e6800000:resets[0]) arch/arm/boot/dts/r8a7793-gose.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /gpio@e6050000:resets[0]) arch/arm/boot/dts/r8a7794-alt.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /i2c@e6500000:resets[0]) arch/arm/boot/dts/r8a7794-silk.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /interrupt-controller@e61c0000:resets[0]) This adds it for the three r8a779x chips that were lacking it. The binding mandates this as <1>, so this is the value I use. Signed-off-by: Arnd Bergmann [geert: Add fix for r8a7793.dtsi] Fixes: 34fbd2b12761d111 ("ARM: dts: r8a7790: Add reset control properties") Fixes: 6e11a322f1d7505d ("ARM: dts: r8a7792: Add reset control properties") Fixes: 84fb19e1d201ba86 ("ARM: dts: r8a7793: Add reset control properties") Fixes: 615beb759ca494a4 ("ARM: dts: r8a7794: Add reset control properties") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 1 + arch/arm/boot/dts/r8a7792.dtsi | 1 + arch/arm/boot/dts/r8a7793.dtsi | 1 + arch/arm/boot/dts/r8a7794.dtsi | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 2f017fee4009..62baabd757b6 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1201,6 +1201,7 @@ clock-names = "extal", "usb_extal"; #clock-cells = <2>; #power-domain-cells = <0>; + #reset-cells = <1>; }; prr: chipid@ff000044 { diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 131f65b0426e..3d080e07374c 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -829,6 +829,7 @@ clock-names = "extal"; #clock-cells = <2>; #power-domain-cells = <0>; + #reset-cells = <1>; }; }; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 58eae569b4e0..0cd1035de1a4 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -1088,6 +1088,7 @@ clock-names = "extal", "usb_extal"; #clock-cells = <2>; #power-domain-cells = <0>; + #reset-cells = <1>; }; rst: reset-controller@e6160000 { diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 905e50c9b524..5643976c1356 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1099,6 +1099,7 @@ clock-names = "extal", "usb_extal"; #clock-cells = <2>; #power-domain-cells = <0>; + #reset-cells = <1>; }; rst: reset-controller@e6160000 { -- GitLab From 07dc8bc9a6b15f54d3ad962af74a096c7d7b42b4 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 7 Nov 2017 10:08:01 +0000 Subject: [PATCH 0028/2547] netfilter: remove redundant assignment to e The assignment to variable e is redundant since the same assignment occurs just a few lines later, hence it can be removed. Cleans up clang warning for arp_tables, ip_tables and ip6_tables: warning: Value stored to 'e' is never read Signed-off-by: Colin Ian King Signed-off-by: Pablo Neira Ayuso --- net/ipv4/netfilter/arp_tables.c | 1 - net/ipv4/netfilter/ip_tables.c | 1 - net/ipv6/netfilter/ip6_tables.c | 1 - 3 files changed, 3 deletions(-) diff --git a/net/ipv4/netfilter/arp_tables.c b/net/ipv4/netfilter/arp_tables.c index f88221aebc9d..0c3c944a7b72 100644 --- a/net/ipv4/netfilter/arp_tables.c +++ b/net/ipv4/netfilter/arp_tables.c @@ -373,7 +373,6 @@ static int mark_source_chains(const struct xt_table_info *newinfo, if (!xt_find_jump_offset(offsets, newpos, newinfo->number)) return 0; - e = entry0 + newpos; } else { /* ... this is a fallthru */ newpos = pos + e->next_offset; diff --git a/net/ipv4/netfilter/ip_tables.c b/net/ipv4/netfilter/ip_tables.c index 4cbe5e80f3bf..2e0d339028bb 100644 --- a/net/ipv4/netfilter/ip_tables.c +++ b/net/ipv4/netfilter/ip_tables.c @@ -439,7 +439,6 @@ mark_source_chains(const struct xt_table_info *newinfo, if (!xt_find_jump_offset(offsets, newpos, newinfo->number)) return 0; - e = entry0 + newpos; } else { /* ... this is a fallthru */ newpos = pos + e->next_offset; diff --git a/net/ipv6/netfilter/ip6_tables.c b/net/ipv6/netfilter/ip6_tables.c index f06e25065a34..1d7ae9366335 100644 --- a/net/ipv6/netfilter/ip6_tables.c +++ b/net/ipv6/netfilter/ip6_tables.c @@ -458,7 +458,6 @@ mark_source_chains(const struct xt_table_info *newinfo, if (!xt_find_jump_offset(offsets, newpos, newinfo->number)) return 0; - e = entry0 + newpos; } else { /* ... this is a fallthru */ newpos = pos + e->next_offset; -- GitLab From 613d0776d3fe7eb28c695a63a5533a1ec8258c86 Mon Sep 17 00:00:00 2001 From: Vasily Averin Date: Sun, 12 Nov 2017 14:32:37 +0300 Subject: [PATCH 0029/2547] netfilter: exit_net cleanup check added Be sure that lists initialized in net_init hook was return to initial state. Signed-off-by: Vasily Averin Signed-off-by: Pablo Neira Ayuso --- net/ipv4/netfilter/ipt_CLUSTERIP.c | 1 + net/netfilter/nf_tables_api.c | 7 +++++++ net/netfilter/nfnetlink_log.c | 5 +++++ net/netfilter/nfnetlink_queue.c | 5 +++++ net/netfilter/x_tables.c | 9 +++++++++ 5 files changed, 27 insertions(+) diff --git a/net/ipv4/netfilter/ipt_CLUSTERIP.c b/net/ipv4/netfilter/ipt_CLUSTERIP.c index 17b4ca562944..e35b8d074f06 100644 --- a/net/ipv4/netfilter/ipt_CLUSTERIP.c +++ b/net/ipv4/netfilter/ipt_CLUSTERIP.c @@ -819,6 +819,7 @@ static void clusterip_net_exit(struct net *net) cn->procdir = NULL; #endif nf_unregister_net_hook(net, &cip_arp_ops); + WARN_ON_ONCE(!list_empty(&cn->configs)); } static struct pernet_operations clusterip_net_ops = { diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index d8327b43e4dc..10798b357481 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -5847,6 +5847,12 @@ static int __net_init nf_tables_init_net(struct net *net) return 0; } +static void __net_exit nf_tables_exit_net(struct net *net) +{ + WARN_ON_ONCE(!list_empty(&net->nft.af_info)); + WARN_ON_ONCE(!list_empty(&net->nft.commit_list)); +} + int __nft_release_basechain(struct nft_ctx *ctx) { struct nft_rule *rule, *nr; @@ -5917,6 +5923,7 @@ static void __nft_release_afinfo(struct net *net, struct nft_af_info *afi) static struct pernet_operations nf_tables_net_ops = { .init = nf_tables_init_net, + .exit = nf_tables_exit_net, }; static int __init nf_tables_module_init(void) diff --git a/net/netfilter/nfnetlink_log.c b/net/netfilter/nfnetlink_log.c index cad6498f10b0..1f511ed0fea3 100644 --- a/net/netfilter/nfnetlink_log.c +++ b/net/netfilter/nfnetlink_log.c @@ -1093,10 +1093,15 @@ static int __net_init nfnl_log_net_init(struct net *net) static void __net_exit nfnl_log_net_exit(struct net *net) { + struct nfnl_log_net *log = nfnl_log_pernet(net); + unsigned int i; + #ifdef CONFIG_PROC_FS remove_proc_entry("nfnetlink_log", net->nf.proc_netfilter); #endif nf_log_unset(net, &nfulnl_logger); + for (i = 0; i < INSTANCE_BUCKETS; i++) + WARN_ON_ONCE(!hlist_empty(&log->instance_table[i])); } static struct pernet_operations nfnl_log_net_ops = { diff --git a/net/netfilter/nfnetlink_queue.c b/net/netfilter/nfnetlink_queue.c index a16356cacec3..c09b36755ed7 100644 --- a/net/netfilter/nfnetlink_queue.c +++ b/net/netfilter/nfnetlink_queue.c @@ -1512,10 +1512,15 @@ static int __net_init nfnl_queue_net_init(struct net *net) static void __net_exit nfnl_queue_net_exit(struct net *net) { + struct nfnl_queue_net *q = nfnl_queue_pernet(net); + unsigned int i; + nf_unregister_queue_handler(net); #ifdef CONFIG_PROC_FS remove_proc_entry("nfnetlink_queue", net->nf.proc_netfilter); #endif + for (i = 0; i < INSTANCE_BUCKETS; i++) + WARN_ON_ONCE(!hlist_empty(&q->instance_table[i])); } static void nfnl_queue_net_exit_batch(struct list_head *net_exit_list) diff --git a/net/netfilter/x_tables.c b/net/netfilter/x_tables.c index a77dd514297c..55802e97f906 100644 --- a/net/netfilter/x_tables.c +++ b/net/netfilter/x_tables.c @@ -1729,8 +1729,17 @@ static int __net_init xt_net_init(struct net *net) return 0; } +static void __net_exit xt_net_exit(struct net *net) +{ + int i; + + for (i = 0; i < NFPROTO_NUMPROTO; i++) + WARN_ON_ONCE(!list_empty(&net->xt.tables[i])); +} + static struct pernet_operations xt_net_ops = { .init = xt_net_init, + .exit = xt_net_exit, }; static int __init xt_init(void) -- GitLab From bc7d811ace4ad39a3941089ca871633366878719 Mon Sep 17 00:00:00 2001 From: Eric Sesterhenn Date: Mon, 13 Nov 2017 09:09:40 +0100 Subject: [PATCH 0030/2547] netfilter: nf_ct_h323: Convert CHECK_BOUND macro to function It is bad practive to return in a macro, this patch moves the check into a function. Signed-off-by: Eric Sesterhenn Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_conntrack_h323_asn1.c | 94 ++++++++++++++++++-------- 1 file changed, 65 insertions(+), 29 deletions(-) diff --git a/net/netfilter/nf_conntrack_h323_asn1.c b/net/netfilter/nf_conntrack_h323_asn1.c index cf1bf2605c10..3d9a009ac147 100644 --- a/net/netfilter/nf_conntrack_h323_asn1.c +++ b/net/netfilter/nf_conntrack_h323_asn1.c @@ -103,7 +103,6 @@ struct bitstr { #define INC_BIT(bs) if((++(bs)->bit)>7){(bs)->cur++;(bs)->bit=0;} #define INC_BITS(bs,b) if(((bs)->bit+=(b))>7){(bs)->cur+=(bs)->bit>>3;(bs)->bit&=7;} #define BYTE_ALIGN(bs) if((bs)->bit){(bs)->cur++;(bs)->bit=0;} -#define CHECK_BOUND(bs,n) if((bs)->cur+(n)>(bs)->end)return(H323_ERROR_BOUND) static unsigned int get_len(struct bitstr *bs); static unsigned int get_bit(struct bitstr *bs); static unsigned int get_bits(struct bitstr *bs, unsigned int b); @@ -165,6 +164,14 @@ static unsigned int get_len(struct bitstr *bs) return v; } +static int nf_h323_error_boundary(struct bitstr *bs, size_t bytes) +{ + if (*bs->cur + bytes > *bs->end) + return 1; + + return 0; +} + /****************************************************************************/ static unsigned int get_bit(struct bitstr *bs) { @@ -280,7 +287,8 @@ static int decode_bool(struct bitstr *bs, const struct field_t *f, INC_BIT(bs); - CHECK_BOUND(bs, 0); + if (nf_h323_error_boundary(bs, 0)) + return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -293,11 +301,14 @@ static int decode_oid(struct bitstr *bs, const struct field_t *f, PRINT("%*.s%s\n", level * TAB_SIZE, " ", f->name); BYTE_ALIGN(bs); - CHECK_BOUND(bs, 1); + if (nf_h323_error_boundary(bs, 1)) + return H323_ERROR_BOUND; + len = *bs->cur++; bs->cur += len; + if (nf_h323_error_boundary(bs, 0)) + return H323_ERROR_BOUND; - CHECK_BOUND(bs, 0); return H323_ERROR_NONE; } @@ -330,7 +341,8 @@ static int decode_int(struct bitstr *bs, const struct field_t *f, break; case UNCO: BYTE_ALIGN(bs); - CHECK_BOUND(bs, 2); + if (nf_h323_error_boundary(bs, 2)) + return H323_ERROR_BOUND; len = get_len(bs); bs->cur += len; break; @@ -341,7 +353,8 @@ static int decode_int(struct bitstr *bs, const struct field_t *f, PRINT("\n"); - CHECK_BOUND(bs, 0); + if (nf_h323_error_boundary(bs, 0)) + return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -357,7 +370,8 @@ static int decode_enum(struct bitstr *bs, const struct field_t *f, INC_BITS(bs, f->sz); } - CHECK_BOUND(bs, 0); + if (nf_h323_error_boundary(bs, 0)) + return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -375,12 +389,14 @@ static int decode_bitstr(struct bitstr *bs, const struct field_t *f, len = f->lb; break; case WORD: /* 2-byte length */ - CHECK_BOUND(bs, 2); + if (nf_h323_error_boundary(bs, 2)) + return H323_ERROR_BOUND; len = (*bs->cur++) << 8; len += (*bs->cur++) + f->lb; break; case SEMI: - CHECK_BOUND(bs, 2); + if (nf_h323_error_boundary(bs, 2)) + return H323_ERROR_BOUND; len = get_len(bs); break; default: @@ -391,7 +407,8 @@ static int decode_bitstr(struct bitstr *bs, const struct field_t *f, bs->cur += len >> 3; bs->bit = len & 7; - CHECK_BOUND(bs, 0); + if (nf_h323_error_boundary(bs, 0)) + return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -409,7 +426,8 @@ static int decode_numstr(struct bitstr *bs, const struct field_t *f, BYTE_ALIGN(bs); INC_BITS(bs, (len << 2)); - CHECK_BOUND(bs, 0); + if (nf_h323_error_boundary(bs, 0)) + return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -440,12 +458,14 @@ static int decode_octstr(struct bitstr *bs, const struct field_t *f, break; case BYTE: /* Range == 256 */ BYTE_ALIGN(bs); - CHECK_BOUND(bs, 1); + if (nf_h323_error_boundary(bs, 1)) + return H323_ERROR_BOUND; len = (*bs->cur++) + f->lb; break; case SEMI: BYTE_ALIGN(bs); - CHECK_BOUND(bs, 2); + if (nf_h323_error_boundary(bs, 2)) + return H323_ERROR_BOUND; len = get_len(bs) + f->lb; break; default: /* 2 <= Range <= 255 */ @@ -458,7 +478,8 @@ static int decode_octstr(struct bitstr *bs, const struct field_t *f, PRINT("\n"); - CHECK_BOUND(bs, 0); + if (nf_h323_error_boundary(bs, 0)) + return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -473,7 +494,8 @@ static int decode_bmpstr(struct bitstr *bs, const struct field_t *f, switch (f->sz) { case BYTE: /* Range == 256 */ BYTE_ALIGN(bs); - CHECK_BOUND(bs, 1); + if (nf_h323_error_boundary(bs, 1)) + return H323_ERROR_BOUND; len = (*bs->cur++) + f->lb; break; default: /* 2 <= Range <= 255 */ @@ -484,7 +506,8 @@ static int decode_bmpstr(struct bitstr *bs, const struct field_t *f, bs->cur += len << 1; - CHECK_BOUND(bs, 0); + if (nf_h323_error_boundary(bs, 0)) + return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -525,9 +548,11 @@ static int decode_seq(struct bitstr *bs, const struct field_t *f, /* Decode */ if (son->attr & OPEN) { /* Open field */ - CHECK_BOUND(bs, 2); + if (nf_h323_error_boundary(bs, 2)) + return H323_ERROR_BOUND; len = get_len(bs); - CHECK_BOUND(bs, len); + if (nf_h323_error_boundary(bs, len)) + return H323_ERROR_BOUND; if (!base || !(son->attr & DECODE)) { PRINT("%*.s%s\n", (level + 1) * TAB_SIZE, " ", son->name); @@ -556,7 +581,8 @@ static int decode_seq(struct bitstr *bs, const struct field_t *f, /* Get the extension bitmap */ bmp2_len = get_bits(bs, 7) + 1; - CHECK_BOUND(bs, (bmp2_len + 7) >> 3); + if (nf_h323_error_boundary(bs, (bmp2_len + 7) >> 3)) + return H323_ERROR_BOUND; bmp2 = get_bitmap(bs, bmp2_len); bmp |= bmp2 >> f->sz; if (base) @@ -567,9 +593,11 @@ static int decode_seq(struct bitstr *bs, const struct field_t *f, for (opt = 0; opt < bmp2_len; opt++, i++, son++) { /* Check Range */ if (i >= f->ub) { /* Newer Version? */ - CHECK_BOUND(bs, 2); + if (nf_h323_error_boundary(bs, 2)) + return H323_ERROR_BOUND; len = get_len(bs); - CHECK_BOUND(bs, len); + if (nf_h323_error_boundary(bs, len)) + return H323_ERROR_BOUND; bs->cur += len; continue; } @@ -583,9 +611,11 @@ static int decode_seq(struct bitstr *bs, const struct field_t *f, if (!((0x80000000 >> opt) & bmp2)) /* Not present */ continue; - CHECK_BOUND(bs, 2); + if (nf_h323_error_boundary(bs, 2)) + return H323_ERROR_BOUND; len = get_len(bs); - CHECK_BOUND(bs, len); + if (nf_h323_error_boundary(bs, len)) + return H323_ERROR_BOUND; if (!base || !(son->attr & DECODE)) { PRINT("%*.s%s\n", (level + 1) * TAB_SIZE, " ", son->name); @@ -623,19 +653,22 @@ static int decode_seqof(struct bitstr *bs, const struct field_t *f, switch (f->sz) { case BYTE: BYTE_ALIGN(bs); - CHECK_BOUND(bs, 1); + if (nf_h323_error_boundary(bs, 1)) + return H323_ERROR_BOUND; count = *bs->cur++; break; case WORD: BYTE_ALIGN(bs); - CHECK_BOUND(bs, 2); + if (nf_h323_error_boundary(bs, 2)) + return H323_ERROR_BOUND; count = *bs->cur++; count <<= 8; count += *bs->cur++; break; case SEMI: BYTE_ALIGN(bs); - CHECK_BOUND(bs, 2); + if (nf_h323_error_boundary(bs, 2)) + return H323_ERROR_BOUND; count = get_len(bs); break; default: @@ -659,7 +692,8 @@ static int decode_seqof(struct bitstr *bs, const struct field_t *f, if (son->attr & OPEN) { BYTE_ALIGN(bs); len = get_len(bs); - CHECK_BOUND(bs, len); + if (nf_h323_error_boundary(bs, len)) + return H323_ERROR_BOUND; if (!base || !(son->attr & DECODE)) { PRINT("%*.s%s\n", (level + 1) * TAB_SIZE, " ", son->name); @@ -728,7 +762,8 @@ static int decode_choice(struct bitstr *bs, const struct field_t *f, if (type >= f->ub) { /* Newer version? */ BYTE_ALIGN(bs); len = get_len(bs); - CHECK_BOUND(bs, len); + if (nf_h323_error_boundary(bs, len)) + return H323_ERROR_BOUND; bs->cur += len; return H323_ERROR_NONE; } @@ -743,7 +778,8 @@ static int decode_choice(struct bitstr *bs, const struct field_t *f, if (ext || (son->attr & OPEN)) { BYTE_ALIGN(bs); len = get_len(bs); - CHECK_BOUND(bs, len); + if (nf_h323_error_boundary(bs, len)) + return H323_ERROR_BOUND; if (!base || !(son->attr & DECODE)) { PRINT("%*.s%s\n", (level + 1) * TAB_SIZE, " ", son->name); -- GitLab From ec8a8f3c31ddef0a7d9626c4b8a4baa30f3b80aa Mon Sep 17 00:00:00 2001 From: Eric Sesterhenn Date: Mon, 13 Nov 2017 09:09:41 +0100 Subject: [PATCH 0031/2547] netfilter: nf_ct_h323: Extend nf_h323_error_boundary to work on bits as well This patch fixes several out of bounds memory reads by extending the nf_h323_error_boundary() function to work on bits as well an check the affected parts. Signed-off-by: Eric Sesterhenn Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_conntrack_h323_asn1.c | 92 +++++++++++++++++--------- 1 file changed, 62 insertions(+), 30 deletions(-) diff --git a/net/netfilter/nf_conntrack_h323_asn1.c b/net/netfilter/nf_conntrack_h323_asn1.c index 3d9a009ac147..dc6347342e34 100644 --- a/net/netfilter/nf_conntrack_h323_asn1.c +++ b/net/netfilter/nf_conntrack_h323_asn1.c @@ -164,8 +164,13 @@ static unsigned int get_len(struct bitstr *bs) return v; } -static int nf_h323_error_boundary(struct bitstr *bs, size_t bytes) +static int nf_h323_error_boundary(struct bitstr *bs, size_t bytes, size_t bits) { + bits += bs->bit; + bytes += bits / BITS_PER_BYTE; + if (bits % BITS_PER_BYTE > 0) + bytes++; + if (*bs->cur + bytes > *bs->end) return 1; @@ -286,8 +291,7 @@ static int decode_bool(struct bitstr *bs, const struct field_t *f, PRINT("%*.s%s\n", level * TAB_SIZE, " ", f->name); INC_BIT(bs); - - if (nf_h323_error_boundary(bs, 0)) + if (nf_h323_error_boundary(bs, 0, 0)) return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -301,12 +305,12 @@ static int decode_oid(struct bitstr *bs, const struct field_t *f, PRINT("%*.s%s\n", level * TAB_SIZE, " ", f->name); BYTE_ALIGN(bs); - if (nf_h323_error_boundary(bs, 1)) + if (nf_h323_error_boundary(bs, 1, 0)) return H323_ERROR_BOUND; len = *bs->cur++; bs->cur += len; - if (nf_h323_error_boundary(bs, 0)) + if (nf_h323_error_boundary(bs, 0, 0)) return H323_ERROR_BOUND; return H323_ERROR_NONE; @@ -330,6 +334,8 @@ static int decode_int(struct bitstr *bs, const struct field_t *f, bs->cur += 2; break; case CONS: /* 64K < Range < 4G */ + if (nf_h323_error_boundary(bs, 0, 2)) + return H323_ERROR_BOUND; len = get_bits(bs, 2) + 1; BYTE_ALIGN(bs); if (base && (f->attr & DECODE)) { /* timeToLive */ @@ -341,7 +347,7 @@ static int decode_int(struct bitstr *bs, const struct field_t *f, break; case UNCO: BYTE_ALIGN(bs); - if (nf_h323_error_boundary(bs, 2)) + if (nf_h323_error_boundary(bs, 2, 0)) return H323_ERROR_BOUND; len = get_len(bs); bs->cur += len; @@ -353,7 +359,7 @@ static int decode_int(struct bitstr *bs, const struct field_t *f, PRINT("\n"); - if (nf_h323_error_boundary(bs, 0)) + if (nf_h323_error_boundary(bs, 0, 0)) return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -370,7 +376,7 @@ static int decode_enum(struct bitstr *bs, const struct field_t *f, INC_BITS(bs, f->sz); } - if (nf_h323_error_boundary(bs, 0)) + if (nf_h323_error_boundary(bs, 0, 0)) return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -389,13 +395,13 @@ static int decode_bitstr(struct bitstr *bs, const struct field_t *f, len = f->lb; break; case WORD: /* 2-byte length */ - if (nf_h323_error_boundary(bs, 2)) + if (nf_h323_error_boundary(bs, 2, 0)) return H323_ERROR_BOUND; len = (*bs->cur++) << 8; len += (*bs->cur++) + f->lb; break; case SEMI: - if (nf_h323_error_boundary(bs, 2)) + if (nf_h323_error_boundary(bs, 2, 0)) return H323_ERROR_BOUND; len = get_len(bs); break; @@ -407,7 +413,7 @@ static int decode_bitstr(struct bitstr *bs, const struct field_t *f, bs->cur += len >> 3; bs->bit = len & 7; - if (nf_h323_error_boundary(bs, 0)) + if (nf_h323_error_boundary(bs, 0, 0)) return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -421,12 +427,14 @@ static int decode_numstr(struct bitstr *bs, const struct field_t *f, PRINT("%*.s%s\n", level * TAB_SIZE, " ", f->name); /* 2 <= Range <= 255 */ + if (nf_h323_error_boundary(bs, 0, f->sz)) + return H323_ERROR_BOUND; len = get_bits(bs, f->sz) + f->lb; BYTE_ALIGN(bs); INC_BITS(bs, (len << 2)); - if (nf_h323_error_boundary(bs, 0)) + if (nf_h323_error_boundary(bs, 0, 0)) return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -458,17 +466,19 @@ static int decode_octstr(struct bitstr *bs, const struct field_t *f, break; case BYTE: /* Range == 256 */ BYTE_ALIGN(bs); - if (nf_h323_error_boundary(bs, 1)) + if (nf_h323_error_boundary(bs, 1, 0)) return H323_ERROR_BOUND; len = (*bs->cur++) + f->lb; break; case SEMI: BYTE_ALIGN(bs); - if (nf_h323_error_boundary(bs, 2)) + if (nf_h323_error_boundary(bs, 2, 0)) return H323_ERROR_BOUND; len = get_len(bs) + f->lb; break; default: /* 2 <= Range <= 255 */ + if (nf_h323_error_boundary(bs, 0, f->sz)) + return H323_ERROR_BOUND; len = get_bits(bs, f->sz) + f->lb; BYTE_ALIGN(bs); break; @@ -478,7 +488,7 @@ static int decode_octstr(struct bitstr *bs, const struct field_t *f, PRINT("\n"); - if (nf_h323_error_boundary(bs, 0)) + if (nf_h323_error_boundary(bs, 0, 0)) return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -494,11 +504,13 @@ static int decode_bmpstr(struct bitstr *bs, const struct field_t *f, switch (f->sz) { case BYTE: /* Range == 256 */ BYTE_ALIGN(bs); - if (nf_h323_error_boundary(bs, 1)) + if (nf_h323_error_boundary(bs, 1, 0)) return H323_ERROR_BOUND; len = (*bs->cur++) + f->lb; break; default: /* 2 <= Range <= 255 */ + if (nf_h323_error_boundary(bs, 0, f->sz)) + return H323_ERROR_BOUND; len = get_bits(bs, f->sz) + f->lb; BYTE_ALIGN(bs); break; @@ -506,7 +518,7 @@ static int decode_bmpstr(struct bitstr *bs, const struct field_t *f, bs->cur += len << 1; - if (nf_h323_error_boundary(bs, 0)) + if (nf_h323_error_boundary(bs, 0, 0)) return H323_ERROR_BOUND; return H323_ERROR_NONE; } @@ -526,9 +538,13 @@ static int decode_seq(struct bitstr *bs, const struct field_t *f, base = (base && (f->attr & DECODE)) ? base + f->offset : NULL; /* Extensible? */ + if (nf_h323_error_boundary(bs, 0, 1)) + return H323_ERROR_BOUND; ext = (f->attr & EXT) ? get_bit(bs) : 0; /* Get fields bitmap */ + if (nf_h323_error_boundary(bs, 0, f->sz)) + return H323_ERROR_BOUND; bmp = get_bitmap(bs, f->sz); if (base) *(unsigned int *)base = bmp; @@ -548,10 +564,10 @@ static int decode_seq(struct bitstr *bs, const struct field_t *f, /* Decode */ if (son->attr & OPEN) { /* Open field */ - if (nf_h323_error_boundary(bs, 2)) + if (nf_h323_error_boundary(bs, 2, 0)) return H323_ERROR_BOUND; len = get_len(bs); - if (nf_h323_error_boundary(bs, len)) + if (nf_h323_error_boundary(bs, len, 0)) return H323_ERROR_BOUND; if (!base || !(son->attr & DECODE)) { PRINT("%*.s%s\n", (level + 1) * TAB_SIZE, @@ -580,8 +596,10 @@ static int decode_seq(struct bitstr *bs, const struct field_t *f, return H323_ERROR_NONE; /* Get the extension bitmap */ + if (nf_h323_error_boundary(bs, 0, 7)) + return H323_ERROR_BOUND; bmp2_len = get_bits(bs, 7) + 1; - if (nf_h323_error_boundary(bs, (bmp2_len + 7) >> 3)) + if (nf_h323_error_boundary(bs, 0, bmp2_len)) return H323_ERROR_BOUND; bmp2 = get_bitmap(bs, bmp2_len); bmp |= bmp2 >> f->sz; @@ -593,10 +611,10 @@ static int decode_seq(struct bitstr *bs, const struct field_t *f, for (opt = 0; opt < bmp2_len; opt++, i++, son++) { /* Check Range */ if (i >= f->ub) { /* Newer Version? */ - if (nf_h323_error_boundary(bs, 2)) + if (nf_h323_error_boundary(bs, 2, 0)) return H323_ERROR_BOUND; len = get_len(bs); - if (nf_h323_error_boundary(bs, len)) + if (nf_h323_error_boundary(bs, len, 0)) return H323_ERROR_BOUND; bs->cur += len; continue; @@ -611,10 +629,10 @@ static int decode_seq(struct bitstr *bs, const struct field_t *f, if (!((0x80000000 >> opt) & bmp2)) /* Not present */ continue; - if (nf_h323_error_boundary(bs, 2)) + if (nf_h323_error_boundary(bs, 2, 0)) return H323_ERROR_BOUND; len = get_len(bs); - if (nf_h323_error_boundary(bs, len)) + if (nf_h323_error_boundary(bs, len, 0)) return H323_ERROR_BOUND; if (!base || !(son->attr & DECODE)) { PRINT("%*.s%s\n", (level + 1) * TAB_SIZE, " ", @@ -653,13 +671,13 @@ static int decode_seqof(struct bitstr *bs, const struct field_t *f, switch (f->sz) { case BYTE: BYTE_ALIGN(bs); - if (nf_h323_error_boundary(bs, 1)) + if (nf_h323_error_boundary(bs, 1, 0)) return H323_ERROR_BOUND; count = *bs->cur++; break; case WORD: BYTE_ALIGN(bs); - if (nf_h323_error_boundary(bs, 2)) + if (nf_h323_error_boundary(bs, 2, 0)) return H323_ERROR_BOUND; count = *bs->cur++; count <<= 8; @@ -667,11 +685,13 @@ static int decode_seqof(struct bitstr *bs, const struct field_t *f, break; case SEMI: BYTE_ALIGN(bs); - if (nf_h323_error_boundary(bs, 2)) + if (nf_h323_error_boundary(bs, 2, 0)) return H323_ERROR_BOUND; count = get_len(bs); break; default: + if (nf_h323_error_boundary(bs, 0, f->sz)) + return H323_ERROR_BOUND; count = get_bits(bs, f->sz); break; } @@ -691,8 +711,10 @@ static int decode_seqof(struct bitstr *bs, const struct field_t *f, for (i = 0; i < count; i++) { if (son->attr & OPEN) { BYTE_ALIGN(bs); + if (nf_h323_error_boundary(bs, 2, 0)) + return H323_ERROR_BOUND; len = get_len(bs); - if (nf_h323_error_boundary(bs, len)) + if (nf_h323_error_boundary(bs, len, 0)) return H323_ERROR_BOUND; if (!base || !(son->attr & DECODE)) { PRINT("%*.s%s\n", (level + 1) * TAB_SIZE, @@ -744,11 +766,17 @@ static int decode_choice(struct bitstr *bs, const struct field_t *f, base = (base && (f->attr & DECODE)) ? base + f->offset : NULL; /* Decode the choice index number */ + if (nf_h323_error_boundary(bs, 0, 1)) + return H323_ERROR_BOUND; if ((f->attr & EXT) && get_bit(bs)) { ext = 1; + if (nf_h323_error_boundary(bs, 0, 7)) + return H323_ERROR_BOUND; type = get_bits(bs, 7) + f->lb; } else { ext = 0; + if (nf_h323_error_boundary(bs, 0, f->sz)) + return H323_ERROR_BOUND; type = get_bits(bs, f->sz); if (type >= f->lb) return H323_ERROR_RANGE; @@ -761,8 +789,10 @@ static int decode_choice(struct bitstr *bs, const struct field_t *f, /* Check Range */ if (type >= f->ub) { /* Newer version? */ BYTE_ALIGN(bs); + if (nf_h323_error_boundary(bs, 2, 0)) + return H323_ERROR_BOUND; len = get_len(bs); - if (nf_h323_error_boundary(bs, len)) + if (nf_h323_error_boundary(bs, len, 0)) return H323_ERROR_BOUND; bs->cur += len; return H323_ERROR_NONE; @@ -777,8 +807,10 @@ static int decode_choice(struct bitstr *bs, const struct field_t *f, if (ext || (son->attr & OPEN)) { BYTE_ALIGN(bs); + if (nf_h323_error_boundary(bs, len, 0)) + return H323_ERROR_BOUND; len = get_len(bs); - if (nf_h323_error_boundary(bs, len)) + if (nf_h323_error_boundary(bs, len, 0)) return H323_ERROR_BOUND; if (!base || !(son->attr & DECODE)) { PRINT("%*.s%s\n", (level + 1) * TAB_SIZE, " ", -- GitLab From fbcd253d2448b8f168241e38f629a36c4c8c1e94 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Sun, 19 Nov 2017 21:27:28 +0100 Subject: [PATCH 0032/2547] netfilter: conntrack: lower timeout to RETRANS seconds if window is 0 When zero window is announced we can get into a situation where connection stays around forever: 1. One side announces zero window. 2. Other side closes. In this case, no FIN is sent (stuck in send queue). Unless other side opens the window up again conntrack stays in ESTABLISHED state for a very long time. Lets alleviate this by lowering the timeout to RETRANS (5 minutes), the other end should be sending zero window probes to keep the connection established as long as a socket still exists. Cc: Jozsef Kadlecsik Signed-off-by: Florian Westphal Acked-by: Jozsef Kadlecsik Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_conntrack_proto_tcp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/netfilter/nf_conntrack_proto_tcp.c b/net/netfilter/nf_conntrack_proto_tcp.c index b12fc07111d0..37ef35b861f2 100644 --- a/net/netfilter/nf_conntrack_proto_tcp.c +++ b/net/netfilter/nf_conntrack_proto_tcp.c @@ -1039,6 +1039,9 @@ static int tcp_packet(struct nf_conn *ct, IP_CT_TCP_FLAG_DATA_UNACKNOWLEDGED && timeouts[new_state] > timeouts[TCP_CONNTRACK_UNACK]) timeout = timeouts[TCP_CONNTRACK_UNACK]; + else if (ct->proto.tcp.last_win == 0 && + timeouts[new_state] > timeouts[TCP_CONNTRACK_RETRANS]) + timeout = timeouts[TCP_CONNTRACK_RETRANS]; else timeout = timeouts[new_state]; spin_unlock_bh(&ct->lock); -- GitLab From 675f7ff35bd256e65d3d0f52718d8babf5d1002a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Thu, 16 Nov 2017 18:02:15 +0200 Subject: [PATCH 0033/2547] drm/i915: Fix init_clock_gating for resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Moving the init_clock_gating() call from intel_modeset_init_hw() to intel_modeset_gem_init() had an unintended effect of not applying some workarounds on resume. This, for example, cause some kind of corruption to appear at the top of my IVB Thinkpad X1 Carbon LVDS screen after hibernation. Fix the problem by explicitly calling init_clock_gating() from the resume path. I really hope this doesn't break something else again. At least the problems reported at https://bugs.freedesktop.org/show_bug.cgi?id=103549 didn't make a comeback, even after a hibernate cycle. v2: Reorder the init_clock_gating vs. modeset_init_hw to match the display reset path (Rodrigo) Cc: stable@vger.kernel.org Cc: Chris Wilson Cc: Rodrigo Vivi Fixes: 6ac43272768c ("drm/i915: Move init_clock_gating() back to where it was") Reviewed-by: Rodrigo Vivi Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171116160215.25715-1-ville.syrjala@linux.intel.com Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 8ea6ce7027d4..87452c5558d3 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1714,6 +1714,7 @@ static int i915_drm_resume(struct drm_device *dev) i915_gem_resume(dev_priv); intel_modeset_init_hw(dev); + intel_init_clock_gating(dev_priv); spin_lock_irq(&dev_priv->irq_lock); if (dev_priv->display.hpd_irq_setup) -- GitLab From e40dd226246d2a0fb463a04bd4c6f1b9e0a650ed Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 12:34:55 +0000 Subject: [PATCH 0034/2547] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE Since commit e1fee72c2ea2e9c0c6e6743d32a6832f21337d6c Author: Oscar Mateo Date: Thu Jul 24 17:04:40 2014 +0100 drm/i915/bdw: Avoid non-lite-restore preemptions execlists has listened to (ACTIVE_IDLE | ELEMENT_SWITCH) for detecting when one context completed and it either continued onto the next (in port 1) or idled. We would always see COMPLETE | ACTIVE_IDLE on the final context-switch event, but on recent gen it appears that we now get separate ACTIVE_IDLE and COMPLETE events. In particular, the ACTIVE_IDLE events may not be coupled to a context (since it is a general state rather than a specific context completion event). v2: Update the history, execlists did originally start out by listening to the COMPLETE event not ACTIVE_IDLE. v3: Update preempt completion test to also use COMPLETE not ACTIVE_IDLE. References: bspec/12255 References: https://bugs.freedesktop.org/show_bug.cgi?id=103800 Signed-off-by: Chris Wilson Cc: Oscar Mateo Cc: Mika Kuoppala Cc: Tvrtko Ursulin Cc: Joonas Lahtinen Cc: Michal Winiarski Cc: Michel Thierry Acked-by: Michel Thierry Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171120123458.23242-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_lrc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index be6c39adebdf..c2cfdfdc0722 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -154,7 +154,7 @@ #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) #define GEN8_CTX_STATUS_COMPLETED_MASK \ - (GEN8_CTX_STATUS_ACTIVE_IDLE | \ + (GEN8_CTX_STATUS_COMPLETE | \ GEN8_CTX_STATUS_PREEMPTED | \ GEN8_CTX_STATUS_ELEMENT_SWITCH) @@ -876,7 +876,7 @@ static void execlists_submission_tasklet(unsigned long data) if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) continue; - if (status & GEN8_CTX_STATUS_ACTIVE_IDLE && + if (status & GEN8_CTX_STATUS_COMPLETE && buf[2*head + 1] == PREEMPT_ID) { execlists_cancel_port_requests(execlists); execlists_unwind_incomplete_requests(execlists); -- GitLab From d8747afb115f4967c4e900919d631c84ad58f573 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 12:34:56 +0000 Subject: [PATCH 0035/2547] drm/i915/execlists: Reduce completed event mask to COMPLETE | PREEMPTED Since we get a COMPLETE event when the context switch occurs on RING_HEAD == RING_TAIL and a PREEMPTED event when a switch occurs before that point, COMPLETE | PREEMPTED should cover all possible context switch completion events. We can move the ELEMENT_SWITCH info message from the COMPLETED_MASK into an assertion for when we are performing a switch to port[1]. Suggested-by: Joonas Lahtinen Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Tvrtko Ursulin Cc: Joonas Lahtinen Cc: Michal Winiarski Cc: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20171120123458.23242-2-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index c2cfdfdc0722..a2c7fc7bf4a4 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -154,9 +154,7 @@ #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) #define GEN8_CTX_STATUS_COMPLETED_MASK \ - (GEN8_CTX_STATUS_COMPLETE | \ - GEN8_CTX_STATUS_PREEMPTED | \ - GEN8_CTX_STATUS_ELEMENT_SWITCH) + (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED) #define CTX_LRI_HEADER_0 0x01 #define CTX_CONTEXT_CONTROL 0x02 @@ -907,6 +905,8 @@ static void execlists_submission_tasklet(unsigned long data) GEM_BUG_ON(count == 0); if (--count == 0) { GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); + GEM_BUG_ON(port_isset(&port[1]) && + !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH)); GEM_BUG_ON(!i915_gem_request_completed(rq)); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); -- GitLab From 1f5f9edb44ca9fd7255cdc60a1880241d2d17e48 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 12:34:57 +0000 Subject: [PATCH 0036/2547] drm/i915/execlists: Assert that we don't get mixed IDLE_ACTIVE | COMPLETE events If IDLE_ACTIVE is set, then all other bits are invalid. For us, we can assert that if we see a COMPLETE | PREEMPTED event, then it should be impossible for it to also contain an IDLE_ACTIVE flag. Suggested-by: Joonas Lahtinen Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Tvrtko Ursulin Cc: Joonas Lahtinen Cc: Michal Winiarski Cc: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20171120123458.23242-3-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_lrc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index a2c7fc7bf4a4..4aed00323780 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -874,6 +874,9 @@ static void execlists_submission_tasklet(unsigned long data) if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) continue; + /* We should never get a COMPLETED | IDLE_ACTIVE! */ + GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE); + if (status & GEN8_CTX_STATUS_COMPLETE && buf[2*head + 1] == PREEMPT_ID) { execlists_cancel_port_requests(execlists); -- GitLab From 7c52a2219da1e551e19af6a4c50619952c6d7bde Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 13 Nov 2017 23:34:52 +0000 Subject: [PATCH 0037/2547] drm/i915/perf: replace .reg accesses with i915_mmio_reg_offset This replaces accesses to the reg field of the i915_reg_t structure with the i915_mmio_reg_offset() inline function. Suggested-by: Chris Wilson Signed-off-by: Lionel Landwerlin Reviewed-by: Ewelina Musial Link: https://patchwork.freedesktop.org/patch/msgid/20171113233455.12085-2-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/i915_perf.c | 39 ++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 00be015e01df..0f48e666098d 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3007,7 +3007,7 @@ static bool gen8_is_valid_flex_addr(struct drm_i915_private *dev_priv, u32 addr) int i; for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) { - if (flex_eu_regs[i].reg == addr) + if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr) return true; } return false; @@ -3015,38 +3015,47 @@ static bool gen8_is_valid_flex_addr(struct drm_i915_private *dev_priv, u32 addr) static bool gen7_is_valid_b_counter_addr(struct drm_i915_private *dev_priv, u32 addr) { - return (addr >= OASTARTTRIG1.reg && addr <= OASTARTTRIG8.reg) || - (addr >= OAREPORTTRIG1.reg && addr <= OAREPORTTRIG8.reg) || - (addr >= OACEC0_0.reg && addr <= OACEC7_1.reg); + return (addr >= i915_mmio_reg_offset(OASTARTTRIG1) && + addr <= i915_mmio_reg_offset(OASTARTTRIG8)) || + (addr >= i915_mmio_reg_offset(OAREPORTTRIG1) && + addr <= i915_mmio_reg_offset(OAREPORTTRIG8)) || + (addr >= i915_mmio_reg_offset(OACEC0_0) && + addr <= i915_mmio_reg_offset(OACEC7_1)); } static bool gen7_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) { - return addr == HALF_SLICE_CHICKEN2.reg || - (addr >= MICRO_BP0_0.reg && addr <= NOA_WRITE.reg) || - (addr >= OA_PERFCNT1_LO.reg && addr <= OA_PERFCNT2_HI.reg) || - (addr >= OA_PERFMATRIX_LO.reg && addr <= OA_PERFMATRIX_HI.reg); + return addr == i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) || + (addr >= i915_mmio_reg_offset(MICRO_BP0_0) && + addr <= i915_mmio_reg_offset(NOA_WRITE)) || + (addr >= i915_mmio_reg_offset(OA_PERFCNT1_LO) && + addr <= i915_mmio_reg_offset(OA_PERFCNT2_HI)) || + (addr >= i915_mmio_reg_offset(OA_PERFMATRIX_LO) && + addr <= i915_mmio_reg_offset(OA_PERFMATRIX_HI)); } static bool gen8_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) { return gen7_is_valid_mux_addr(dev_priv, addr) || - addr == WAIT_FOR_RC6_EXIT.reg || - (addr >= RPM_CONFIG0.reg && addr <= NOA_CONFIG(8).reg); + addr == i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) || + (addr >= i915_mmio_reg_offset(RPM_CONFIG0) && + addr <= i915_mmio_reg_offset(NOA_CONFIG(8))); } static bool gen10_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) { return gen8_is_valid_mux_addr(dev_priv, addr) || - (addr >= OA_PERFCNT3_LO.reg && addr <= OA_PERFCNT4_HI.reg); + (addr >= i915_mmio_reg_offset(OA_PERFCNT3_LO) && + addr <= i915_mmio_reg_offset(OA_PERFCNT4_HI)); } static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) { return gen7_is_valid_mux_addr(dev_priv, addr) || (addr >= 0x25100 && addr <= 0x2FF90) || - (addr >= HSW_MBVID2_NOA0.reg && addr <= HSW_MBVID2_NOA9.reg) || - addr == HSW_MBVID2_MISR0.reg; + (addr >= i915_mmio_reg_offset(HSW_MBVID2_NOA0) && + addr <= i915_mmio_reg_offset(HSW_MBVID2_NOA9)) || + addr == i915_mmio_reg_offset(HSW_MBVID2_MISR0); } static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) @@ -3061,14 +3070,14 @@ static uint32_t mask_reg_value(u32 reg, u32 val) * WaDisableSTUnitPowerOptimization workaround. Make sure the value * programmed by userspace doesn't change this. */ - if (HALF_SLICE_CHICKEN2.reg == reg) + if (i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) == reg) val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function * indicated by its name and a bunch of selection fields used by OA * configs. */ - if (WAIT_FOR_RC6_EXIT.reg == reg) + if (i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) == reg) val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); return val; -- GitLab From 2113184c6f6749f6e4e86a42894f67a50ead6775 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 10:20:01 +0000 Subject: [PATCH 0038/2547] drm/i915: Pull the unconditional GPU cache invalidation into request construction As the request will, in the following patch, implicitly invoke a context-switch on construction, we should precede that with a GPU TLB invalidation. Also, even before using GGTT, we always want to invalidate the TLBs for any updates (as well as the ppgtt invalidates that are unconditionally applied by execbuf). Since we almost always require the TLB invalidate, do it unconditionally on request allocation and so we can remove it from all other paths. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171120102002.22254-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 7 +----- drivers/gpu/drm/i915/i915_gem_render_state.c | 4 ---- drivers/gpu/drm/i915/i915_gem_request.c | 24 +++++++++++++++---- drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ---- .../gpu/drm/i915/selftests/i915_gem_context.c | 4 ---- .../gpu/drm/i915/selftests/i915_gem_request.c | 10 -------- .../gpu/drm/i915/selftests/intel_hangcheck.c | 4 ---- 7 files changed, 20 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 53ccb27bfe91..b7895788bc75 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1111,10 +1111,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, if (err) goto err_request; - err = eb->engine->emit_flush(rq, EMIT_INVALIDATE); - if (err) - goto err_request; - err = i915_switch_context(rq); if (err) goto err_request; @@ -1818,8 +1814,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) /* Unconditionally flush any chipset caches (for streaming writes). */ i915_gem_chipset_flush(eb->i915); - /* Unconditionally invalidate GPU caches and TLBs. */ - return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE); + return 0; } static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c index c2723a06fbb4..f7fc0df251ac 100644 --- a/drivers/gpu/drm/i915/i915_gem_render_state.c +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c @@ -208,10 +208,6 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request *rq) if (err) goto err_unpin; - err = engine->emit_flush(rq, EMIT_INVALIDATE); - if (err) - goto err_unpin; - err = engine->emit_bb_start(rq, so.batch_offset, so.batch_size, I915_DISPATCH_SECURE); diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index e0d6221022a8..91eae1b20c42 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -703,17 +703,31 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz); - ret = engine->request_alloc(req); - if (ret) - goto err_ctx; - - /* Record the position of the start of the request so that + /* + * Record the position of the start of the request so that * should we detect the updated seqno part-way through the * GPU processing the request, we never over-estimate the * position of the head. */ req->head = req->ring->emit; + /* Unconditionally invalidate GPU caches and TLBs. */ + ret = engine->emit_flush(req, EMIT_INVALIDATE); + if (ret) + goto err_ctx; + + ret = engine->request_alloc(req); + if (ret) { + /* + * Past the point-of-no-return. Since we may have updated + * global state after partially completing the request alloc, + * we need to commit any commands so far emitted in the + * request to the HW. + */ + __i915_add_request(req, false); + return ERR_PTR(ret); + } + /* Check that we didn't interrupt ourselves with a new request */ GEM_BUG_ON(req->timeline->seqno != req->fence.seqno); return req; diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c index 01af540b6ef9..159a2cb68765 100644 --- a/drivers/gpu/drm/i915/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c @@ -989,10 +989,6 @@ static int gpu_write(struct i915_vma *vma, i915_vma_unpin(batch); i915_vma_close(batch); - err = rq->engine->emit_flush(rq, EMIT_INVALIDATE); - if (err) - goto err_request; - err = i915_switch_context(rq); if (err) goto err_request; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index c82780a9d455..4ff30b9af1fe 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -158,10 +158,6 @@ static int gpu_fill(struct drm_i915_gem_object *obj, goto err_batch; } - err = engine->emit_flush(rq, EMIT_INVALIDATE); - if (err) - goto err_request; - err = i915_switch_context(rq); if (err) goto err_request; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_request.c b/drivers/gpu/drm/i915/selftests/i915_gem_request.c index 6bce99050e94..d7bf53ff8f84 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_request.c @@ -459,10 +459,6 @@ empty_request(struct intel_engine_cs *engine, if (IS_ERR(request)) return request; - err = engine->emit_flush(request, EMIT_INVALIDATE); - if (err) - goto out_request; - err = i915_switch_context(request); if (err) goto out_request; @@ -675,9 +671,6 @@ static int live_all_engines(void *arg) goto out_request; } - err = engine->emit_flush(request[id], EMIT_INVALIDATE); - GEM_BUG_ON(err); - err = i915_switch_context(request[id]); GEM_BUG_ON(err); @@ -797,9 +790,6 @@ static int live_sequential_engines(void *arg) } } - err = engine->emit_flush(request[id], EMIT_INVALIDATE); - GEM_BUG_ON(err); - err = i915_switch_context(request[id]); GEM_BUG_ON(err); diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 71ce06680d66..145bdc26553c 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -114,10 +114,6 @@ static int emit_recurse_batch(struct hang *h, if (err) goto unpin_vma; - err = rq->engine->emit_flush(rq, EMIT_INVALIDATE); - if (err) - goto unpin_hws; - err = i915_switch_context(rq); if (err) goto unpin_hws; -- GitLab From 3fef5cda970124a15c553c1672d800e40fc08a9e Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 10:20:02 +0000 Subject: [PATCH 0039/2547] drm/i915: Automatic i915_switch_context for legacy During request construction, after pinning the context we know whether or not we have to emit a context switch. So move this common operation from every caller into i915_gem_request_alloc() itself. v2: Always submit the request if we emitted some commands during request construction, as typically it also involves changes in global state. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171120102002.22254-2-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gem_context.c | 7 +------ drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 -------- drivers/gpu/drm/i915/i915_gem_request.c | 4 ++++ drivers/gpu/drm/i915/i915_perf.c | 3 +-- drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++ drivers/gpu/drm/i915/selftests/huge_pages.c | 10 +++------- drivers/gpu/drm/i915/selftests/i915_gem_context.c | 4 ---- drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 ---------- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 5 ----- 10 files changed, 14 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 61ba321e9970..e07eb0beef13 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5045,7 +5045,7 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915) goto out_ctx; } - err = i915_switch_context(rq); + err = 0; if (engine->init_context) err = engine->init_context(rq); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 2db040695035..c1efbaf02bf2 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -842,8 +842,7 @@ int i915_switch_context(struct drm_i915_gem_request *req) struct intel_engine_cs *engine = req->engine; lockdep_assert_held(&req->i915->drm.struct_mutex); - if (i915_modparams.enable_execlists) - return 0; + GEM_BUG_ON(i915_modparams.enable_execlists); if (!req->ctx->engine[engine->id].state) { struct i915_gem_context *to = req->ctx; @@ -899,7 +898,6 @@ int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv) for_each_engine(engine, dev_priv, id) { struct drm_i915_gem_request *req; - int ret; if (engine_has_idle_kernel_context(engine)) continue; @@ -922,10 +920,7 @@ int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv) GFP_KERNEL); } - ret = i915_switch_context(req); i915_add_request(req); - if (ret) - return ret; } return 0; diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index b7895788bc75..14d9e61a1e06 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1111,10 +1111,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, if (err) goto err_request; - err = i915_switch_context(rq); - if (err) - goto err_request; - err = eb->engine->emit_bb_start(rq, batch->node.start, PAGE_SIZE, cache->gen > 5 ? 0 : I915_DISPATCH_SECURE); @@ -1960,10 +1956,6 @@ static int eb_submit(struct i915_execbuffer *eb) if (err) return err; - err = i915_switch_context(eb->request); - if (err) - return err; - if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) { err = i915_reset_gen7_sol_offsets(eb->request); if (err) diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 91eae1b20c42..86e2346357cf 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -624,6 +624,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, if (ret) goto err_unpin; + ret = intel_ring_wait_for_space(ring, MIN_SPACE_FOR_ADD_REQUEST); + if (ret) + goto err_unreserve; + /* Move the oldest request to the slab-cache (if not in use!) */ req = list_first_entry_or_null(&engine->timeline->requests, typeof(*req), link); diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 0f48e666098d..fd150099978c 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1726,10 +1726,9 @@ static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_pr GFP_KERNEL); } - ret = i915_switch_context(req); i915_add_request(req); - return ret; + return 0; } /* diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 12e734b29463..be98868115bf 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1592,6 +1592,10 @@ static int ring_request_alloc(struct drm_i915_gem_request *request) if (ret) return ret; + ret = i915_switch_context(request); + if (ret) + return ret; + request->reserved_space -= LEGACY_REQUEST_SIZE; return 0; } diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c index 159a2cb68765..db7a0a1f2960 100644 --- a/drivers/gpu/drm/i915/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c @@ -989,13 +989,9 @@ static int gpu_write(struct i915_vma *vma, i915_vma_unpin(batch); i915_vma_close(batch); - err = i915_switch_context(rq); - if (err) - goto err_request; - - err = rq->engine->emit_bb_start(rq, - batch->node.start, batch->node.size, - flags); + err = engine->emit_bb_start(rq, + batch->node.start, batch->node.size, + flags); if (err) goto err_request; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index 4ff30b9af1fe..09340b3c1156 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -158,10 +158,6 @@ static int gpu_fill(struct drm_i915_gem_object *obj, goto err_batch; } - err = i915_switch_context(rq); - if (err) - goto err_request; - flags = 0; if (INTEL_GEN(vm->i915) <= 5) flags |= I915_DISPATCH_SECURE; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_request.c b/drivers/gpu/drm/i915/selftests/i915_gem_request.c index d7bf53ff8f84..647bf2bbd799 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_request.c @@ -459,10 +459,6 @@ empty_request(struct intel_engine_cs *engine, if (IS_ERR(request)) return request; - err = i915_switch_context(request); - if (err) - goto out_request; - err = engine->emit_bb_start(request, batch->node.start, batch->node.size, @@ -671,9 +667,6 @@ static int live_all_engines(void *arg) goto out_request; } - err = i915_switch_context(request[id]); - GEM_BUG_ON(err); - err = engine->emit_bb_start(request[id], batch->node.start, batch->node.size, @@ -790,9 +783,6 @@ static int live_sequential_engines(void *arg) } } - err = i915_switch_context(request[id]); - GEM_BUG_ON(err); - err = engine->emit_bb_start(request[id], batch->node.start, batch->node.size, diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 145bdc26553c..1bbb8c46e2d9 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -114,10 +114,6 @@ static int emit_recurse_batch(struct hang *h, if (err) goto unpin_vma; - err = i915_switch_context(rq); - if (err) - goto unpin_hws; - i915_vma_move_to_active(vma, rq, 0); if (!i915_gem_object_has_active_reference(vma->obj)) { i915_gem_object_get(vma->obj); @@ -169,7 +165,6 @@ static int emit_recurse_batch(struct hang *h, err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags); -unpin_hws: i915_vma_unpin(hws); unpin_vma: i915_vma_unpin(vma); -- GitLab From 9f9b2792b6d38fbc8028f31b41ebd38a3f28a401 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Fri, 27 Oct 2017 15:59:31 +0100 Subject: [PATCH 0040/2547] drm/i915/perf: reuse timestamp frequency from device info Now that we have this stored in the device info, we can drop it from perf part of the driver. Note that this requires to init perf after we've computed the frequency, hence why we move i915_perf_init() from i915_driver_init_early() to after intel_device_info_runtime_init(). v2: Use div_u64 (Chris) v3: Drop u64 divs by switching to kHz (Chris/Ville) Move i915_perf_fini to i915_driver_cleanup_hw (Matthew) Signed-off-by: Lionel Landwerlin Reviewed-by: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20171113181902.12411-2-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/i915_drv.c | 7 ++++--- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_perf.c | 36 +++++--------------------------- 3 files changed, 9 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 87452c5558d3..2b4ced93011b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -936,8 +936,6 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, intel_detect_preproduction_hw(dev_priv); - i915_perf_init(dev_priv); - return 0; err_irq: @@ -954,7 +952,6 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, */ static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv) { - i915_perf_fini(dev_priv); i915_gem_load_cleanup(dev_priv); intel_irq_fini(dev_priv); i915_workqueues_cleanup(dev_priv); @@ -1101,6 +1098,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) intel_sanitize_options(dev_priv); + i915_perf_init(dev_priv); + ret = i915_ggtt_probe_hw(dev_priv); if (ret) return ret; @@ -1206,6 +1205,8 @@ static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv) { struct pci_dev *pdev = dev_priv->drm.pdev; + i915_perf_fini(dev_priv); + if (pdev->msi_enabled) pci_disable_msi(pdev); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 36bb4927484a..2b766253f970 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2619,7 +2619,6 @@ struct drm_i915_private { bool periodic; int period_exponent; - int timestamp_frequency; struct i915_oa_config test_config; diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index fd150099978c..adbce839a918 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2690,8 +2690,8 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv, static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent) { - return div_u64(1000000000ULL * (2ULL << exponent), - dev_priv->perf.oa.timestamp_frequency); + return div64_u64(1000000000ULL * (2ULL << exponent), + 1000ULL * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz); } /** @@ -3423,8 +3423,6 @@ static struct ctl_table dev_root[] = { */ void i915_perf_init(struct drm_i915_private *dev_priv) { - dev_priv->perf.oa.timestamp_frequency = 0; - if (IS_HASWELL(dev_priv)) { dev_priv->perf.oa.ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr; @@ -3440,8 +3438,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.ops.oa_hw_tail_read = gen7_oa_hw_tail_read; - dev_priv->perf.oa.timestamp_frequency = 12500000; - dev_priv->perf.oa.oa_formats = hsw_oa_formats; } else if (i915_modparams.enable_execlists) { /* Note: that although we could theoretically also support the @@ -3485,23 +3481,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); } - - switch (dev_priv->info.platform) { - case INTEL_BROADWELL: - dev_priv->perf.oa.timestamp_frequency = 12500000; - break; - case INTEL_BROXTON: - case INTEL_GEMINILAKE: - dev_priv->perf.oa.timestamp_frequency = 19200000; - break; - case INTEL_SKYLAKE: - case INTEL_KABYLAKE: - case INTEL_COFFEELAKE: - dev_priv->perf.oa.timestamp_frequency = 12000000; - break; - default: - break; - } } else if (IS_GEN10(dev_priv)) { dev_priv->perf.oa.ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr; @@ -3517,15 +3496,10 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de; dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); - - /* Default frequency, although we need to read it from - * the register as it might vary between parts. - */ - dev_priv->perf.oa.timestamp_frequency = 12000000; } } - if (dev_priv->perf.oa.timestamp_frequency) { + if (dev_priv->perf.oa.ops.enable_metric_set) { hrtimer_init(&dev_priv->perf.oa.poll_check_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); dev_priv->perf.oa.poll_check_timer.function = oa_poll_check_timer_cb; @@ -3535,8 +3509,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv) mutex_init(&dev_priv->perf.lock); spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock); - oa_sample_rate_hard_limit = - dev_priv->perf.oa.timestamp_frequency / 2; + oa_sample_rate_hard_limit = 1000 * + (INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz / 2); dev_priv->perf.sysctl_header = register_sysctl_table(dev_root); mutex_init(&dev_priv->perf.metrics_lock); -- GitLab From 2a6c4241fcc3d942a0a6b09e445561d099fa7884 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 13:26:06 +0000 Subject: [PATCH 0041/2547] drm/i915/selftest: Make guc clients static Make the private array used for stashing test clients static, to silence sparse. References: 55bd6bd75717 ("drm/i915/selftests: Add a GuC doorbells selftest") Signed-off-by: Chris Wilson Cc: Michel Thierry Cc: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Link: https://patchwork.freedesktop.org/patch/msgid/20171120132606.4254-1-chris@chris-wilson.co.uk Reviewed-by: Michel Thierry --- drivers/gpu/drm/i915/selftests/intel_guc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c index f10029e18820..f1baeda8b4a8 100644 --- a/drivers/gpu/drm/i915/selftests/intel_guc.c +++ b/drivers/gpu/drm/i915/selftests/intel_guc.c @@ -27,7 +27,7 @@ /* max doorbell number + negative test for each client type */ #define ATTEMPTS (GUC_NUM_DOORBELLS + GUC_CLIENT_PRIORITY_NUM) -struct intel_guc_client *clients[ATTEMPTS]; +static struct intel_guc_client *clients[ATTEMPTS]; static bool available_dbs(struct intel_guc *guc, u32 priority) { -- GitLab From ba74cb10c775c839f6e1d0fabd1e772eabd9c43f Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Mon, 20 Nov 2017 12:34:58 +0000 Subject: [PATCH 0042/2547] drm/i915/execlists: Delay writing to ELSP until HW has processed the previous write The hardware needs some time to process the information received in the ExecList Submission Port, and expects us to not write anything more until it has 'acknowledged' this new submission by sending an IDLE_ACTIVE or PREEMPTED CSB event. If we do not follow this, the driver could write new data into the ELSP before HW had finishing fetching the previous one, putting us in 'undefined behaviour' space. This seems to be the problem causing the spurious PREEMPTED & COMPLETE events after a COMPLETE like the one below: [] vcs0: sw rd pointer = 2, hw wr pointer = 0, current 'head' = 3. [] vcs0: Execlist CSB[0]: 0x00000018 _ 0x00000007 [] vcs0: Execlist CSB[1]: 0x00000001 _ 0x00000000 [] vcs0: Execlist CSB[2]: 0x00000018 _ 0x00000007 <<< COMPLETE [] vcs0: Execlist CSB[3]: 0x00000012 _ 0x00000007 <<< PREEMPTED & COMPLETE [] vcs0: Execlist CSB[4]: 0x00008002 _ 0x00000006 [] vcs0: Execlist CSB[5]: 0x00000014 _ 0x00000006 The ELSP writes that lead to this CSB sequence show that the HW hadn't started executing the previous execlist (the one with only ctx 0x6) by the time the new one was submitted; this is a bit more clear in the data show in the EXECLIST_STATUS register at the time of the ELSP write. [] vcs0: ELSP[0] = 0x0_0 [execlist1] - status_reg = 0x0_302 [] vcs0: ELSP[1] = 0x6_fedb2119 [execlist0] - status_reg = 0x0_8302 [] vcs0: ELSP[2] = 0x7_fedaf119 [execlist1] - status_reg = 0x0_8308 [] vcs0: ELSP[3] = 0x6_fedb2119 [execlist0] - status_reg = 0x7_8308 Note that having to wait for this ack does not disable lite-restores, although it may reduce their numbers. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102035 Signed-off-by: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/<20171118003038.7935-1-michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171120123458.23242-4-chris@chris-wilson.co.uk Reviewed-by: Chris Wilson Tested-by: Chris Wilson Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 4aed00323780..8d0c49388863 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -477,6 +477,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine) elsp_write(desc, elsp); } + execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK); } static bool ctx_single_port_submission(const struct i915_gem_context *ctx) @@ -529,6 +530,7 @@ static void inject_preempt_context(struct intel_engine_cs *engine) elsp_write(0, elsp); elsp_write(ce->lrc_desc, elsp); + execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK); } static void execlists_dequeue(struct intel_engine_cs *engine) @@ -575,9 +577,20 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * know the next preemption status we see corresponds * to this ELSP update. */ + GEM_BUG_ON(!port_count(&port[0])); if (port_count(&port[0]) > 1) goto unlock; + /* + * If we write to ELSP a second time before the HW has had + * a chance to respond to the previous write, we can confuse + * the HW and hit "undefined behaviour". After writing to ELSP, + * we must then wait until we see a context-switch event from + * the HW to indicate that it has had a chance to respond. + */ + if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK)) + goto unlock; + if (HAS_LOGICAL_RING_PREEMPTION(engine->i915) && rb_entry(rb, struct i915_priolist, node)->priority > max(last->priotree.priority, 0)) { @@ -871,6 +884,15 @@ static void execlists_submission_tasklet(unsigned long data) GEM_TRACE("%s csb[%dd]: status=0x%08x:0x%08x\n", engine->name, head, status, buf[2*head + 1]); + + if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE | + GEN8_CTX_STATUS_PREEMPTED)) + execlists_set_active(execlists, + EXECLISTS_ACTIVE_HWACK); + if (status & GEN8_CTX_STATUS_ACTIVE_IDLE) + execlists_clear_active(execlists, + EXECLISTS_ACTIVE_HWACK); + if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) continue; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index c00804ed64c6..e437a9556c08 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -251,6 +251,7 @@ struct intel_engine_execlists { unsigned int active; #define EXECLISTS_ACTIVE_USER 0 #define EXECLISTS_ACTIVE_PREEMPT 1 +#define EXECLISTS_ACTIVE_HWACK 2 /** * @port_mask: number of execlist ports - 1 -- GitLab From fb5c551ad510e4a408c105670f89c725ebbfe6c8 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 20:55:00 +0000 Subject: [PATCH 0043/2547] drm/i915: Remove i915.enable_execlists module parameter Execlists and legacy ringbuffer submission are no longer feature comparable (execlists now offer greater functionality that should overcome their performance hit) and obsoletes the unsafe module parameter, i.e. comparing the two modes of execution is no longer useful, so remove the debug tool. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen Reviewed-by: Lionel Landwerlin #i915_perf.c Link: https://patchwork.freedesktop.org/patch/msgid/20171120205504.21892-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/gvt/render.c | 3 +- drivers/gpu/drm/i915/i915_debugfs.c | 70 ------------------------- drivers/gpu/drm/i915/i915_drv.c | 8 +-- drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_gem.c | 10 ++-- drivers/gpu/drm/i915/i915_gem_context.c | 10 +--- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +- drivers/gpu/drm/i915/i915_params.c | 4 -- drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/i915_perf.c | 8 +-- drivers/gpu/drm/i915/intel_engine_cs.c | 8 ++- drivers/gpu/drm/i915/intel_gvt.c | 5 -- drivers/gpu/drm/i915/intel_lrc.c | 31 ----------- drivers/gpu/drm/i915/intel_lrc.h | 4 -- 14 files changed, 20 insertions(+), 149 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index 0672178548ef..dac12c25f349 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -294,8 +294,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) * write. */ if (mmio->in_context && - ((ctx_ctrl & inhibit_mask) != inhibit_mask) && - i915_modparams.enable_execlists) + (ctx_ctrl & inhibit_mask) != inhibit_mask) continue; if (mmio->mask) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index df3852c02a35..5e2a6e18771f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1989,75 +1989,6 @@ static int i915_context_status(struct seq_file *m, void *unused) return 0; } -static void i915_dump_lrc_obj(struct seq_file *m, - struct i915_gem_context *ctx, - struct intel_engine_cs *engine) -{ - struct i915_vma *vma = ctx->engine[engine->id].state; - struct page *page; - int j; - - seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); - - if (!vma) { - seq_puts(m, "\tFake context\n"); - return; - } - - if (vma->flags & I915_VMA_GLOBAL_BIND) - seq_printf(m, "\tBound in GGTT at 0x%08x\n", - i915_ggtt_offset(vma)); - - if (i915_gem_object_pin_pages(vma->obj)) { - seq_puts(m, "\tFailed to get pages for context object\n\n"); - return; - } - - page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); - if (page) { - u32 *reg_state = kmap_atomic(page); - - for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { - seq_printf(m, - "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", - j * 4, - reg_state[j], reg_state[j + 1], - reg_state[j + 2], reg_state[j + 3]); - } - kunmap_atomic(reg_state); - } - - i915_gem_object_unpin_pages(vma->obj); - seq_putc(m, '\n'); -} - -static int i915_dump_lrc(struct seq_file *m, void *unused) -{ - struct drm_i915_private *dev_priv = node_to_i915(m->private); - struct drm_device *dev = &dev_priv->drm; - struct intel_engine_cs *engine; - struct i915_gem_context *ctx; - enum intel_engine_id id; - int ret; - - if (!i915_modparams.enable_execlists) { - seq_printf(m, "Logical Ring Contexts are disabled\n"); - return 0; - } - - ret = mutex_lock_interruptible(&dev->struct_mutex); - if (ret) - return ret; - - list_for_each_entry(ctx, &dev_priv->contexts.list, link) - for_each_engine(engine, dev_priv, id) - i915_dump_lrc_obj(m, ctx, engine); - - mutex_unlock(&dev->struct_mutex); - - return 0; -} - static const char *swizzle_string(unsigned swizzle) { switch (swizzle) { @@ -4833,7 +4764,6 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_vbt", i915_vbt, 0}, {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, {"i915_context_status", i915_context_status, 0}, - {"i915_dump_lrc", i915_dump_lrc, 0}, {"i915_forcewake_domains", i915_forcewake_domains, 0}, {"i915_swizzle_info", i915_swizzle_info, 0}, {"i915_ppgtt_info", i915_ppgtt_info, 0}, diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 2b4ced93011b..c608fd96771c 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -371,9 +371,7 @@ static int i915_getparam(struct drm_device *dev, void *data, if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) { value |= I915_SCHEDULER_CAP_ENABLED; value |= I915_SCHEDULER_CAP_PRIORITY; - - if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) && - i915_modparams.enable_execlists) + if (HAS_LOGICAL_RING_PREEMPTION(dev_priv)) value |= I915_SCHEDULER_CAP_PREEMPTION; } break; @@ -1054,10 +1052,6 @@ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) static void intel_sanitize_options(struct drm_i915_private *dev_priv) { - i915_modparams.enable_execlists = - intel_sanitize_enable_execlists(dev_priv, - i915_modparams.enable_execlists); - /* * i915.enable_ppgtt is read-only, so do an early pass to validate the * user's requested state against the hardware/driver capabilities. We diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2b766253f970..d2c6ba7f8acd 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3153,6 +3153,9 @@ intel_info(const struct drm_i915_private *dev_priv) ((dev_priv)->info.has_logical_ring_contexts) #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ ((dev_priv)->info.has_logical_ring_preemption) + +#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) + #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt) #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2) #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e07eb0beef13..494c6be035b2 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5003,7 +5003,7 @@ bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) return false; /* TODO: make semaphores and Execlists play nicely together */ - if (i915_modparams.enable_execlists) + if (HAS_EXECLISTS(dev_priv)) return false; if (value >= 0) @@ -5147,12 +5147,12 @@ int i915_gem_init(struct drm_i915_private *dev_priv) dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1); - if (!i915_modparams.enable_execlists) { - dev_priv->gt.resume = intel_legacy_submission_resume; - dev_priv->gt.cleanup_engine = intel_engine_cleanup; - } else { + if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { dev_priv->gt.resume = intel_lr_context_resume; dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; + } else { + dev_priv->gt.resume = intel_legacy_submission_resume; + dev_priv->gt.cleanup_engine = intel_engine_cleanup; } /* This is just a security blanket to placate dragons. diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index c1efbaf02bf2..c75941d3d7e7 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -460,14 +460,6 @@ int i915_gem_contexts_init(struct drm_i915_private *dev_priv) INIT_WORK(&dev_priv->contexts.free_work, contexts_free_worker); init_llist_head(&dev_priv->contexts.free_list); - if (intel_vgpu_active(dev_priv) && - HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { - if (!i915_modparams.enable_execlists) { - DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); - return -EINVAL; - } - } - /* Using the simple ida interface, the max is limited by sizeof(int) */ BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX); ida_init(&dev_priv->contexts.hw_ida); @@ -842,7 +834,7 @@ int i915_switch_context(struct drm_i915_gem_request *req) struct intel_engine_cs *engine = req->engine; lockdep_assert_held(&req->i915->drm.struct_mutex); - GEM_BUG_ON(i915_modparams.enable_execlists); + GEM_BUG_ON(HAS_EXECLISTS(req->i915)); if (!req->ctx->engine[engine->id].state) { struct i915_gem_context *to = req->ctx; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index f92a39fc511c..e101b9a98957 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -178,7 +178,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, return 0; } - if (INTEL_GEN(dev_priv) >= 8 && i915_modparams.enable_execlists) { + if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { if (has_full_48bit_ppgtt) return 3; @@ -2162,7 +2162,7 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) /* In the case of execlists, PPGTT is enabled by the context descriptor * and the PDPs are contained within the context itself. We don't * need to do anything here. */ - if (i915_modparams.enable_execlists) + if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) return 0; if (!USES_PPGTT(dev_priv)) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index b4faeb6aa2bd..d61c1787c164 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -99,10 +99,6 @@ i915_param_named_unsafe(enable_ppgtt, int, 0400, "Override PPGTT usage. " "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)"); -i915_param_named_unsafe(enable_execlists, int, 0400, - "Override execlists usage. " - "(-1=auto [default], 0=disabled, 1=enabled)"); - i915_param_named_unsafe(enable_psr, int, 0600, "Enable PSR " "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) " diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c7292268ed43..0aef3d7178eb 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -39,7 +39,6 @@ param(int, enable_dc, -1) \ param(int, enable_fbc, -1) \ param(int, enable_ppgtt, -1) \ - param(int, enable_execlists, -1) \ param(int, enable_psr, -1) \ param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index adbce839a918..f0cfdece14ae 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1216,9 +1216,9 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream) { struct drm_i915_private *dev_priv = stream->dev_priv; - if (i915_modparams.enable_execlists) + if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { dev_priv->perf.oa.specific_ctx_id = stream->ctx->hw_id; - else { + } else { struct intel_engine_cs *engine = dev_priv->engine[RCS]; struct intel_ring *ring; int ret; @@ -1262,7 +1262,7 @@ static void oa_put_render_ctx_id(struct i915_perf_stream *stream) { struct drm_i915_private *dev_priv = stream->dev_priv; - if (i915_modparams.enable_execlists) { + if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { dev_priv->perf.oa.specific_ctx_id = INVALID_CTX_ID; } else { struct intel_engine_cs *engine = dev_priv->engine[RCS]; @@ -3439,7 +3439,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) gen7_oa_hw_tail_read; dev_priv->perf.oa.oa_formats = hsw_oa_formats; - } else if (i915_modparams.enable_execlists) { + } else if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { /* Note: that although we could theoretically also support the * legacy ringbuffer mode on BDW (and earlier iterations of * this driver, before upstreaming did this) it didn't seem diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 9897c7f78c51..cae76f47fec2 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -164,9 +164,7 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class) case 9: return GEN9_LR_CONTEXT_RENDER_SIZE; case 8: - return i915_modparams.enable_execlists ? - GEN8_LR_CONTEXT_RENDER_SIZE : - GEN8_CXT_TOTAL_SIZE; + return GEN8_LR_CONTEXT_RENDER_SIZE; case 7: if (IS_HASWELL(dev_priv)) return HSW_CXT_TOTAL_SIZE; @@ -316,7 +314,7 @@ int intel_engines_init(struct drm_i915_private *dev_priv) &intel_engine_classes[engine->class]; int (*init)(struct intel_engine_cs *engine); - if (i915_modparams.enable_execlists) + if (HAS_EXECLISTS(dev_priv)) init = class_info->init_execlists; else init = class_info->init_legacy; @@ -1739,7 +1737,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m) drm_printf(m, "\tBBADDR: 0x%08x_%08x\n", upper_32_bits(addr), lower_32_bits(addr)); - if (i915_modparams.enable_execlists) { + if (HAS_EXECLISTS(dev_priv)) { const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX]; u32 ptr, read, write; unsigned int idx; diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c index b4a7f31f0214..126f7c769c69 100644 --- a/drivers/gpu/drm/i915/intel_gvt.c +++ b/drivers/gpu/drm/i915/intel_gvt.c @@ -95,11 +95,6 @@ int intel_gvt_init(struct drm_i915_private *dev_priv) return 0; } - if (!i915_modparams.enable_execlists) { - DRM_ERROR("i915 GVT-g loading failed due to disabled execlists mode\n"); - return -EIO; - } - if (i915_modparams.enable_guc_submission) { DRM_ERROR("i915 GVT-g loading failed due to Graphics virtualization is not yet supported with GuC submission\n"); return -EIO; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 8d0c49388863..16d4936e2368 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -218,37 +218,6 @@ static void execlists_init_reg_state(u32 *reg_state, struct intel_engine_cs *engine, struct intel_ring *ring); -/** - * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists - * @dev_priv: i915 device private - * @enable_execlists: value of i915.enable_execlists module parameter. - * - * Only certain platforms support Execlists (the prerequisites being - * support for Logical Ring Contexts and Aliasing PPGTT or better). - * - * Return: 1 if Execlists is supported and has to be enabled. - */ -int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) -{ - /* On platforms with execlist available, vGPU will only - * support execlist mode, no ring buffer mode. - */ - if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) - return 1; - - if (INTEL_GEN(dev_priv) >= 9) - return 1; - - if (enable_execlists == 0) - return 0; - - if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && - USES_PPGTT(dev_priv)) - return 1; - - return 0; -} - /** * intel_lr_context_descriptor_update() - calculate & cache the descriptor * descriptor for a pinned context diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 17182ce29674..6d4f9b995a11 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -107,8 +107,4 @@ intel_lr_context_descriptor(struct i915_gem_context *ctx, return ctx->engine[engine->id].lrc_desc; } -/* Execlists */ -int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, - int enable_execlists); - #endif /* _INTEL_LRC_H_ */ -- GitLab From 79e6770cb1f5e32eb49590edbb794a97d0113aed Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 20:55:01 +0000 Subject: [PATCH 0044/2547] drm/i915: Remove obsolete ringbuffer emission for gen8+ Since removing the module parameter to force selection of ringbuffer emission for gen8, the code is defunct. Remove it. To put the difference into perspective, a couple of microbenchmarks (bdw i7-5557u, 20170324): ring execlists exec continuous nops on all rings: 1.491us 2.223us exec sequential nops on each ring: 12.508us 53.682us single nop + sync: 9.272us 30.291us vblank_mode=0 glxgears: ~11000fps ~9000fps Since the earlier submission, gen8 ringbuffer submission has fallen further and further behind in features. So while ringbuffer may hold the throughput crown, in terms of interactive latency, execlists is much better. Alas, we have no convenient metrics for such, other than demonstrating things we can do with execlists but can not using legacy ringbuffer submission. We have made a few improvements to lowlevel execlists throughput, and ringbuffer currently panics on boot! (bdw i7-5557u, 20171026): ring execlists exec continuous nops on all rings: n/a 1.921us exec sequential nops on each ring: n/a 44.621us single nop + sync: n/a 21.953us vblank_mode=0 glxgears: n/a ~18500fps References: https://bugs.freedesktop.org/show_bug.cgi?id=87725 Signed-off-by: Chris Wilson Once-upon-a-time-Reviewed-by: Joonas Lahtinen Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171120205504.21892-2-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_debugfs.c | 44 +-- drivers/gpu/drm/i915/i915_drv.h | 2 - drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gem_context.c | 47 +-- drivers/gpu/drm/i915/i915_gpu_error.c | 36 -- drivers/gpu/drm/i915/intel_engine_cs.c | 14 - drivers/gpu/drm/i915/intel_hangcheck.c | 44 +-- drivers/gpu/drm/i915/intel_ringbuffer.c | 431 ++++-------------------- drivers/gpu/drm/i915/intel_ringbuffer.h | 25 +- 9 files changed, 94 insertions(+), 551 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 5e2a6e18771f..9cef1463d411 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3254,44 +3254,12 @@ static int i915_semaphore_status(struct seq_file *m, void *unused) return ret; intel_runtime_pm_get(dev_priv); - if (IS_BROADWELL(dev_priv)) { - struct page *page; - uint64_t *seqno; - - page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); - - seqno = (uint64_t *)kmap_atomic(page); - for_each_engine(engine, dev_priv, id) { - uint64_t offset; - - seq_printf(m, "%s\n", engine->name); - - seq_puts(m, " Last signal:"); - for (j = 0; j < num_rings; j++) { - offset = id * I915_NUM_ENGINES + j; - seq_printf(m, "0x%08llx (0x%02llx) ", - seqno[offset], offset * 8); - } - seq_putc(m, '\n'); - - seq_puts(m, " Last wait: "); - for (j = 0; j < num_rings; j++) { - offset = id + (j * I915_NUM_ENGINES); - seq_printf(m, "0x%08llx (0x%02llx) ", - seqno[offset], offset * 8); - } - seq_putc(m, '\n'); - - } - kunmap_atomic(seqno); - } else { - seq_puts(m, " Last signal:"); - for_each_engine(engine, dev_priv, id) - for (j = 0; j < num_rings; j++) - seq_printf(m, "0x%08x\n", - I915_READ(engine->semaphore.mbox.signal[j])); - seq_putc(m, '\n'); - } + seq_puts(m, " Last signal:"); + for_each_engine(engine, dev_priv, id) + for (j = 0; j < num_rings; j++) + seq_printf(m, "0x%08x\n", + I915_READ(engine->semaphore.mbox.signal[j])); + seq_putc(m, '\n'); intel_runtime_pm_put(dev_priv); mutex_unlock(&dev->struct_mutex); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d2c6ba7f8acd..5ce778c26bb8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -942,7 +942,6 @@ struct i915_gpu_state { u64 fence[I915_MAX_NUM_FENCES]; struct intel_overlay_error_state *overlay; struct intel_display_error_state *display; - struct drm_i915_error_object *semaphore; struct drm_i915_error_engine { int engine_id; @@ -2291,7 +2290,6 @@ struct drm_i915_private { struct i915_gem_context *kernel_context; /* Context only to be used for injecting preemption commands */ struct i915_gem_context *preempt_context; - struct i915_vma *semaphore; struct drm_dma_handle *status_page_dmah; struct resource mch_res; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 494c6be035b2..d470e10b2edd 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4999,7 +4999,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv) bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) { - if (INTEL_INFO(dev_priv)->gen < 6) + if (INTEL_GEN(dev_priv) < 6) return false; /* TODO: make semaphores and Execlists play nicely together */ diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index c75941d3d7e7..0704d9af261b 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -574,21 +574,21 @@ mi_set_context(struct drm_i915_gem_request *req, u32 flags) enum intel_engine_id id; const int num_rings = /* Use an extended w/a on gen7 if signalling from other rings */ - (i915_modparams.semaphores && INTEL_GEN(dev_priv) == 7) ? + (i915_modparams.semaphores && IS_GEN7(dev_priv)) ? INTEL_INFO(dev_priv)->num_rings - 1 : 0; int len; u32 *cs; flags |= MI_MM_SPACE_GTT; - if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) + if (IS_HASWELL(dev_priv)) /* These flags are for resource streamer on HSW+ */ flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; else flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; len = 4; - if (INTEL_GEN(dev_priv) >= 7) + if (IS_GEN7(dev_priv)) len += 2 + (num_rings ? 4*num_rings + 6 : 0); cs = intel_ring_begin(req, len); @@ -596,7 +596,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 flags) return PTR_ERR(cs); /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ - if (INTEL_GEN(dev_priv) >= 7) { + if (IS_GEN7(dev_priv)) { *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; if (num_rings) { struct intel_engine_cs *signaller; @@ -623,7 +623,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 flags) */ *cs++ = MI_NOOP; - if (INTEL_GEN(dev_priv) >= 7) { + if (IS_GEN7(dev_priv)) { if (num_rings) { struct intel_engine_cs *signaller; i915_reg_t last_reg = {}; /* keep gcc quiet */ @@ -714,27 +714,7 @@ needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, struct intel_engine_cs *engine) if (engine->id != RCS) return true; - if (INTEL_GEN(engine->i915) < 8) - return true; - - return false; -} - -static bool -needs_pd_load_post(struct i915_hw_ppgtt *ppgtt, - struct i915_gem_context *to, - u32 hw_flags) -{ - if (!ppgtt) - return false; - - if (!IS_GEN8(to->i915)) - return false; - - if (hw_flags & MI_RESTORE_INHIBIT) - return true; - - return false; + return true; } static int do_rcs_switch(struct drm_i915_gem_request *req) @@ -784,21 +764,6 @@ static int do_rcs_switch(struct drm_i915_gem_request *req) engine->legacy_active_context = to; } - /* GEN8 does *not* require an explicit reload if the PDPs have been - * setup, and we do not wish to move them. - */ - if (needs_pd_load_post(ppgtt, to, hw_flags)) { - trace_switch_mm(engine, to); - ret = ppgtt->switch_mm(ppgtt, req); - /* The hardware context switch is emitted, but we haven't - * actually changed the state - so it's probably safe to bail - * here. Still, let the user know something dangerous has - * happened. - */ - if (ret) - return ret; - } - if (ppgtt) ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 7481c8e1b5a8..3d18d67d065f 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -793,8 +793,6 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, "WA batchbuffer", ee->wa_batchbuffer); } - print_error_obj(m, NULL, "Semaphores", error->semaphore); - if (error->overlay) intel_overlay_print_error_state(m, error->overlay); @@ -903,8 +901,6 @@ void __i915_gpu_state_free(struct kref *error_ref) kfree(ee->waiters); } - i915_error_object_free(error->semaphore); - for (i = 0; i < ARRAY_SIZE(error->active_bo); i++) kfree(error->active_bo[i]); kfree(error->pinned_bo); @@ -1116,34 +1112,6 @@ gen8_engine_sync_index(struct intel_engine_cs *engine, return idx; } -static void gen8_record_semaphore_state(struct i915_gpu_state *error, - struct intel_engine_cs *engine, - struct drm_i915_error_engine *ee) -{ - struct drm_i915_private *dev_priv = engine->i915; - struct intel_engine_cs *to; - enum intel_engine_id id; - - if (!error->semaphore) - return; - - for_each_engine(to, dev_priv, id) { - int idx; - u16 signal_offset; - u32 *tmp; - - if (engine == to) - continue; - - signal_offset = - (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4; - tmp = error->semaphore->pages[0]; - idx = gen8_engine_sync_index(engine, to); - - ee->semaphore_mboxes[idx] = tmp[signal_offset]; - } -} - static void gen6_record_semaphore_state(struct intel_engine_cs *engine, struct drm_i915_error_engine *ee) { @@ -1218,7 +1186,6 @@ static void error_record_engine_registers(struct i915_gpu_state *error, if (INTEL_GEN(dev_priv) >= 6) { ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); if (INTEL_GEN(dev_priv) >= 8) { - gen8_record_semaphore_state(error, engine, ee); ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); } else { gen6_record_semaphore_state(engine, ee); @@ -1453,9 +1420,6 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv, struct i915_ggtt *ggtt = &dev_priv->ggtt; int i; - error->semaphore = - i915_error_object_create(dev_priv, dev_priv->semaphore); - for (i = 0; i < I915_NUM_ENGINES; i++) { struct intel_engine_cs *engine = dev_priv->engine[i]; struct drm_i915_error_engine *ee = &error->engine[i]; diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index cae76f47fec2..1fca7ac3b059 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -37,8 +37,6 @@ * Resource Streamer, is 66944 bytes, which rounds to 17 pages. */ #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) -/* Same as Haswell, but 72064 bytes now. */ -#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) @@ -364,18 +362,6 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) if (HAS_VEBOX(dev_priv)) I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); } - if (dev_priv->semaphore) { - struct page *page = i915_vma_first_page(dev_priv->semaphore); - void *semaphores; - - /* Semaphores are in noncoherent memory, flush to be safe */ - semaphores = kmap_atomic(page); - memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), - 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); - drm_clflush_virt_range(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), - I915_NUM_ENGINES * gen8_semaphore_seqno_size); - kunmap_atomic(semaphores); - } intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted); diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c index 12ac270a5f93..95bbb5a79c4f 100644 --- a/drivers/gpu/drm/i915/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/intel_hangcheck.c @@ -27,13 +27,9 @@ static bool ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr) { - if (INTEL_GEN(engine->i915) >= 8) { - return (ipehr >> 23) == 0x1c; - } else { - ipehr &= ~MI_SEMAPHORE_SYNC_MASK; - return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | - MI_SEMAPHORE_REGISTER); - } + ipehr &= ~MI_SEMAPHORE_SYNC_MASK; + return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | + MI_SEMAPHORE_REGISTER); } static struct intel_engine_cs * @@ -41,31 +37,20 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr, u64 offset) { struct drm_i915_private *dev_priv = engine->i915; + u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; struct intel_engine_cs *signaller; enum intel_engine_id id; - if (INTEL_GEN(dev_priv) >= 8) { - for_each_engine(signaller, dev_priv, id) { - if (engine == signaller) - continue; - - if (offset == signaller->semaphore.signal_ggtt[engine->hw_id]) - return signaller; - } - } else { - u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; - - for_each_engine(signaller, dev_priv, id) { - if(engine == signaller) - continue; + for_each_engine(signaller, dev_priv, id) { + if (engine == signaller) + continue; - if (sync_bits == signaller->semaphore.mbox.wait[engine->hw_id]) - return signaller; - } + if (sync_bits == signaller->semaphore.mbox.wait[engine->hw_id]) + return signaller; } - DRM_DEBUG_DRIVER("No signaller ring found for %s, ipehr 0x%08x, offset 0x%016llx\n", - engine->name, ipehr, offset); + DRM_DEBUG_DRIVER("No signaller ring found for %s, ipehr 0x%08x\n", + engine->name, ipehr); return ERR_PTR(-ENODEV); } @@ -135,11 +120,6 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno) return NULL; *seqno = ioread32(vaddr + head + 4) + 1; - if (INTEL_GEN(dev_priv) >= 8) { - offset = ioread32(vaddr + head + 12); - offset <<= 32; - offset |= ioread32(vaddr + head + 8); - } return semaphore_wait_to_signaller_ring(engine, ipehr, offset); } @@ -273,7 +253,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) return ENGINE_WAIT_KICK; } - if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) { + if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { switch (semaphore_passed(engine)) { default: return ENGINE_DEAD; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index be98868115bf..5465e708545f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -340,50 +340,6 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) return 0; } -static int -gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) -{ - u32 flags; - u32 *cs; - - cs = intel_ring_begin(req, mode & EMIT_INVALIDATE ? 12 : 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - flags = PIPE_CONTROL_CS_STALL; - - if (mode & EMIT_FLUSH) { - flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; - flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; - flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; - flags |= PIPE_CONTROL_FLUSH_ENABLE; - } - if (mode & EMIT_INVALIDATE) { - flags |= PIPE_CONTROL_TLB_INVALIDATE; - flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_QW_WRITE; - flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; - - /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ - cs = gen8_emit_pipe_control(cs, - PIPE_CONTROL_CS_STALL | - PIPE_CONTROL_STALL_AT_SCOREBOARD, - 0); - } - - cs = gen8_emit_pipe_control(cs, flags, - i915_ggtt_offset(req->engine->scratch) + - 2 * CACHELINE_BYTES); - - intel_ring_advance(req, cs); - - return 0; -} - static void ring_setup_phys_status_page(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; @@ -427,7 +383,6 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) } else if (IS_GEN6(dev_priv)) { mmio = RING_HWS_PGA_GEN6(engine->mmio_base); } else { - /* XXX: gen8 returns to sanity */ mmio = RING_HWS_PGA(engine->mmio_base); } @@ -437,13 +392,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) I915_WRITE(mmio, engine->status_page.ggtt_offset); POSTING_READ(mmio); - /* - * Flush the TLB for this page - * - * FIXME: These two bits have disappeared on gen8, so a question - * arises: do we still need this and if so how should we go about - * invalidating the TLB? - */ + /* Flush the TLB for this page */ if (IS_GEN(dev_priv, 6, 7)) { i915_reg_t reg = RING_INSTPM(engine->mmio_base); @@ -611,8 +560,6 @@ static void reset_ring_common(struct intel_engine_cs *engine, struct intel_context *ce = &request->ctx->engine[engine->id]; struct i915_hw_ppgtt *ppgtt; - /* FIXME consider gen8 reset */ - if (ce->state) { I915_WRITE(CCID, i915_ggtt_offset(ce->state) | @@ -713,62 +660,6 @@ static int init_render_ring(struct intel_engine_cs *engine) return init_workarounds_ring(engine); } -static void render_ring_cleanup(struct intel_engine_cs *engine) -{ - struct drm_i915_private *dev_priv = engine->i915; - - i915_vma_unpin_and_release(&dev_priv->semaphore); -} - -static u32 *gen8_rcs_signal(struct drm_i915_gem_request *req, u32 *cs) -{ - struct drm_i915_private *dev_priv = req->i915; - struct intel_engine_cs *waiter; - enum intel_engine_id id; - - for_each_engine(waiter, dev_priv, id) { - u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; - if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) - continue; - - *cs++ = GFX_OP_PIPE_CONTROL(6); - *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_QW_WRITE | - PIPE_CONTROL_CS_STALL; - *cs++ = lower_32_bits(gtt_offset); - *cs++ = upper_32_bits(gtt_offset); - *cs++ = req->global_seqno; - *cs++ = 0; - *cs++ = MI_SEMAPHORE_SIGNAL | - MI_SEMAPHORE_TARGET(waiter->hw_id); - *cs++ = 0; - } - - return cs; -} - -static u32 *gen8_xcs_signal(struct drm_i915_gem_request *req, u32 *cs) -{ - struct drm_i915_private *dev_priv = req->i915; - struct intel_engine_cs *waiter; - enum intel_engine_id id; - - for_each_engine(waiter, dev_priv, id) { - u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; - if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) - continue; - - *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; - *cs++ = lower_32_bits(gtt_offset) | MI_FLUSH_DW_USE_GTT; - *cs++ = upper_32_bits(gtt_offset); - *cs++ = req->global_seqno; - *cs++ = MI_SEMAPHORE_SIGNAL | - MI_SEMAPHORE_TARGET(waiter->hw_id); - *cs++ = 0; - } - - return cs; -} - static u32 *gen6_signal(struct drm_i915_gem_request *req, u32 *cs) { struct drm_i915_private *dev_priv = req->i915; @@ -851,70 +742,6 @@ static void gen6_sema_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) req->engine->semaphore.signal(req, cs)); } -static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req, - u32 *cs) -{ - struct intel_engine_cs *engine = req->engine; - - if (engine->semaphore.signal) - cs = engine->semaphore.signal(req, cs); - - *cs++ = GFX_OP_PIPE_CONTROL(6); - *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | - PIPE_CONTROL_QW_WRITE; - *cs++ = intel_hws_seqno_address(engine); - *cs++ = 0; - *cs++ = req->global_seqno; - /* We're thrashing one dword of HWS. */ - *cs++ = 0; - *cs++ = MI_USER_INTERRUPT; - *cs++ = MI_NOOP; - - req->tail = intel_ring_offset(req, cs); - assert_ring_tail_valid(req->ring, req->tail); -} - -static const int gen8_render_emit_breadcrumb_sz = 8; - -/** - * intel_ring_sync - sync the waiter to the signaller on seqno - * - * @waiter - ring that is waiting - * @signaller - ring which has, or will signal - * @seqno - seqno which the waiter will block on - */ - -static int -gen8_ring_sync_to(struct drm_i915_gem_request *req, - struct drm_i915_gem_request *signal) -{ - struct drm_i915_private *dev_priv = req->i915; - u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id); - struct i915_hw_ppgtt *ppgtt; - u32 *cs; - - cs = intel_ring_begin(req, 4); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_SEMAPHORE_WAIT | MI_SEMAPHORE_GLOBAL_GTT | - MI_SEMAPHORE_SAD_GTE_SDD; - *cs++ = signal->global_seqno; - *cs++ = lower_32_bits(offset); - *cs++ = upper_32_bits(offset); - intel_ring_advance(req, cs); - - /* When the !RCS engines idle waiting upon a semaphore, they lose their - * pagetables and we must reload them before executing the batch. - * We do this on the i915_switch_context() following the wait and - * before the dispatch. - */ - ppgtt = req->ctx->ppgtt; - if (ppgtt && req->engine->id != RCS) - ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine); - return 0; -} - static int gen6_ring_sync_to(struct drm_i915_gem_request *req, struct drm_i915_gem_request *signal) @@ -1090,25 +917,6 @@ hsw_vebox_irq_disable(struct intel_engine_cs *engine) gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); } -static void -gen8_irq_enable(struct intel_engine_cs *engine) -{ - struct drm_i915_private *dev_priv = engine->i915; - - I915_WRITE_IMR(engine, - ~(engine->irq_enable_mask | - engine->irq_keep_mask)); - POSTING_READ_FW(RING_IMR(engine->mmio_base)); -} - -static void -gen8_irq_disable(struct intel_engine_cs *engine) -{ - struct drm_i915_private *dev_priv = engine->i915; - - I915_WRITE_IMR(engine, ~engine->irq_keep_mask); -} - static int i965_emit_bb_start(struct drm_i915_gem_request *req, u64 offset, u32 length, @@ -1796,8 +1604,6 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) return PTR_ERR(cs); cmd = MI_FLUSH_DW; - if (INTEL_GEN(req->i915) >= 8) - cmd += 1; /* We always require a command barrier so that subsequent * commands, such as breadcrumb interrupts, are strictly ordered @@ -1817,38 +1623,9 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) *cs++ = cmd; *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; - if (INTEL_GEN(req->i915) >= 8) { - *cs++ = 0; /* upper addr */ - *cs++ = 0; /* value */ - } else { - *cs++ = 0; - *cs++ = MI_NOOP; - } - intel_ring_advance(req, cs); - return 0; -} - -static int -gen8_emit_bb_start(struct drm_i915_gem_request *req, - u64 offset, u32 len, - unsigned int dispatch_flags) -{ - bool ppgtt = USES_PPGTT(req->i915) && - !(dispatch_flags & I915_DISPATCH_SECURE); - u32 *cs; - - cs = intel_ring_begin(req, 4); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* FIXME(BDW): Address space and security selectors. */ - *cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags & - I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); - *cs++ = lower_32_bits(offset); - *cs++ = upper_32_bits(offset); + *cs++ = 0; *cs++ = MI_NOOP; intel_ring_advance(req, cs); - return 0; } @@ -1905,8 +1682,6 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) return PTR_ERR(cs); cmd = MI_FLUSH_DW; - if (INTEL_GEN(req->i915) >= 8) - cmd += 1; /* We always require a command barrier so that subsequent * commands, such as breadcrumb interrupts, are strictly ordered @@ -1925,13 +1700,8 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) cmd |= MI_INVALIDATE_TLB; *cs++ = cmd; *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; - if (INTEL_GEN(req->i915) >= 8) { - *cs++ = 0; /* upper addr */ - *cs++ = 0; /* value */ - } else { - *cs++ = 0; - *cs++ = MI_NOOP; - } + *cs++ = 0; + *cs++ = MI_NOOP; intel_ring_advance(req, cs); return 0; @@ -1940,110 +1710,61 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, struct intel_engine_cs *engine) { - struct drm_i915_gem_object *obj; - int ret, i; + int i; if (!i915_modparams.semaphores) return; - if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) { - struct i915_vma *vma; - - obj = i915_gem_object_create(dev_priv, PAGE_SIZE); - if (IS_ERR(obj)) - goto err; - - vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); - if (IS_ERR(vma)) - goto err_obj; - - ret = i915_gem_object_set_to_gtt_domain(obj, false); - if (ret) - goto err_obj; - - ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); - if (ret) - goto err_obj; + GEM_BUG_ON(INTEL_GEN(dev_priv) < 6); + engine->semaphore.sync_to = gen6_ring_sync_to; + engine->semaphore.signal = gen6_signal; - dev_priv->semaphore = vma; - } - - if (INTEL_GEN(dev_priv) >= 8) { - u32 offset = i915_ggtt_offset(dev_priv->semaphore); - - engine->semaphore.sync_to = gen8_ring_sync_to; - engine->semaphore.signal = gen8_xcs_signal; - - for (i = 0; i < I915_NUM_ENGINES; i++) { - u32 ring_offset; - - if (i != engine->id) - ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); - else - ring_offset = MI_SEMAPHORE_SYNC_INVALID; - - engine->semaphore.signal_ggtt[i] = ring_offset; - } - } else if (INTEL_GEN(dev_priv) >= 6) { - engine->semaphore.sync_to = gen6_ring_sync_to; - engine->semaphore.signal = gen6_signal; - - /* - * The current semaphore is only applied on pre-gen8 - * platform. And there is no VCS2 ring on the pre-gen8 - * platform. So the semaphore between RCS and VCS2 is - * initialized as INVALID. Gen8 will initialize the - * sema between VCS2 and RCS later. - */ - for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { - static const struct { - u32 wait_mbox; - i915_reg_t mbox_reg; - } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { - [RCS_HW] = { - [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, - [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, - [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, - }, - [VCS_HW] = { - [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, - [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, - [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, - }, - [BCS_HW] = { - [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, - [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, - [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, - }, - [VECS_HW] = { - [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, - [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, - [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, - }, - }; + /* + * The current semaphore is only applied on pre-gen8 + * platform. And there is no VCS2 ring on the pre-gen8 + * platform. So the semaphore between RCS and VCS2 is + * initialized as INVALID. + */ + for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { + static const struct { u32 wait_mbox; i915_reg_t mbox_reg; + } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { + [RCS_HW] = { + [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, + [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, + [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, + }, + [VCS_HW] = { + [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, + [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, + [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, + }, + [BCS_HW] = { + [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, + [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, + [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, + }, + [VECS_HW] = { + [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, + [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, + [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, + }, + }; + u32 wait_mbox; + i915_reg_t mbox_reg; - if (i == engine->hw_id) { - wait_mbox = MI_SEMAPHORE_SYNC_INVALID; - mbox_reg = GEN6_NOSYNC; - } else { - wait_mbox = sem_data[engine->hw_id][i].wait_mbox; - mbox_reg = sem_data[engine->hw_id][i].mbox_reg; - } - - engine->semaphore.mbox.wait[i] = wait_mbox; - engine->semaphore.mbox.signal[i] = mbox_reg; + if (i == engine->hw_id) { + wait_mbox = MI_SEMAPHORE_SYNC_INVALID; + mbox_reg = GEN6_NOSYNC; + } else { + wait_mbox = sem_data[engine->hw_id][i].wait_mbox; + mbox_reg = sem_data[engine->hw_id][i].mbox_reg; } - } - - return; -err_obj: - i915_gem_object_put(obj); -err: - DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n"); - i915_modparams.semaphores = 0; + engine->semaphore.mbox.wait[i] = wait_mbox; + engine->semaphore.mbox.signal[i] = mbox_reg; + } } static void intel_ring_init_irq(struct drm_i915_private *dev_priv, @@ -2051,11 +1772,7 @@ static void intel_ring_init_irq(struct drm_i915_private *dev_priv, { engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; - if (INTEL_GEN(dev_priv) >= 8) { - engine->irq_enable = gen8_irq_enable; - engine->irq_disable = gen8_irq_disable; - engine->irq_seqno_barrier = gen6_seqno_barrier; - } else if (INTEL_GEN(dev_priv) >= 6) { + if (INTEL_GEN(dev_priv) >= 6) { engine->irq_enable = gen6_irq_enable; engine->irq_disable = gen6_irq_disable; engine->irq_seqno_barrier = gen6_seqno_barrier; @@ -2090,6 +1807,9 @@ static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, struct intel_engine_cs *engine) { + /* gen8+ are only supported with execlists */ + GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8); + intel_ring_init_irq(dev_priv, engine); intel_ring_init_semaphores(dev_priv, engine); @@ -2109,20 +1829,14 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; num_rings = INTEL_INFO(dev_priv)->num_rings - 1; - if (INTEL_GEN(dev_priv) >= 8) { - engine->emit_breadcrumb_sz += num_rings * 6; - } else { - engine->emit_breadcrumb_sz += num_rings * 3; - if (num_rings & 1) - engine->emit_breadcrumb_sz++; - } + engine->emit_breadcrumb_sz += num_rings * 3; + if (num_rings & 1) + engine->emit_breadcrumb_sz++; } engine->set_default_submission = i9xx_set_default_submission; - if (INTEL_GEN(dev_priv) >= 8) - engine->emit_bb_start = gen8_emit_bb_start; - else if (INTEL_GEN(dev_priv) >= 6) + if (INTEL_GEN(dev_priv) >= 6) engine->emit_bb_start = gen6_emit_bb_start; else if (INTEL_GEN(dev_priv) >= 4) engine->emit_bb_start = i965_emit_bb_start; @@ -2142,20 +1856,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine) if (HAS_L3_DPF(dev_priv)) engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; - if (INTEL_GEN(dev_priv) >= 8) { - engine->init_context = intel_rcs_ctx_init; - engine->emit_breadcrumb = gen8_render_emit_breadcrumb; - engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz; - engine->emit_flush = gen8_render_ring_flush; - if (i915_modparams.semaphores) { - int num_rings; - - engine->semaphore.signal = gen8_rcs_signal; - - num_rings = INTEL_INFO(dev_priv)->num_rings - 1; - engine->emit_breadcrumb_sz += num_rings * 8; - } - } else if (INTEL_GEN(dev_priv) >= 6) { + if (INTEL_GEN(dev_priv) >= 6) { engine->init_context = intel_rcs_ctx_init; engine->emit_flush = gen7_render_ring_flush; if (IS_GEN6(dev_priv)) @@ -2174,7 +1875,6 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine) engine->emit_bb_start = hsw_emit_bb_start; engine->init_hw = init_render_ring; - engine->cleanup = render_ring_cleanup; ret = intel_init_ring_buffer(engine); if (ret) @@ -2204,8 +1904,7 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) if (IS_GEN6(dev_priv)) engine->set_default_submission = gen6_bsd_set_default_submission; engine->emit_flush = gen6_bsd_ring_flush; - if (INTEL_GEN(dev_priv) < 8) - engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; + engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; } else { engine->mmio_base = BSD_RING_BASE; engine->emit_flush = bsd_ring_flush; @@ -2225,8 +1924,7 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) intel_ring_default_vfuncs(dev_priv, engine); engine->emit_flush = gen6_ring_flush; - if (INTEL_GEN(dev_priv) < 8) - engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; + engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; return intel_init_ring_buffer(engine); } @@ -2238,12 +1936,9 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) intel_ring_default_vfuncs(dev_priv, engine); engine->emit_flush = gen6_ring_flush; - - if (INTEL_GEN(dev_priv) < 8) { - engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; - engine->irq_enable = hsw_vebox_irq_enable; - engine->irq_disable = hsw_vebox_irq_disable; - } + engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; + engine->irq_enable = hsw_vebox_irq_enable; + engine->irq_disable = hsw_vebox_irq_disable; return intel_init_ring_buffer(engine); } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index e437a9556c08..80cd7812ce02 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -46,16 +46,6 @@ struct intel_hw_status_page { /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. */ -#define gen8_semaphore_seqno_size sizeof(uint64_t) -#define GEN8_SEMAPHORE_OFFSET(__from, __to) \ - (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size) -#define GEN8_SIGNAL_OFFSET(__ring, to) \ - (dev_priv->semaphore->node.start + \ - GEN8_SEMAPHORE_OFFSET((__ring)->id, (to))) -#define GEN8_WAIT_OFFSET(__ring, from) \ - (dev_priv->semaphore->node.start + \ - GEN8_SEMAPHORE_OFFSET(from, (__ring)->id)) - enum intel_engine_hangcheck_action { ENGINE_IDLE = 0, ENGINE_WAIT, @@ -467,18 +457,15 @@ struct intel_engine_cs { * ie. transpose of f(x, y) */ struct { - union { #define GEN6_SEMAPHORE_LAST VECS_HW #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1) #define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0) - struct { - /* our mbox written by others */ - u32 wait[GEN6_NUM_SEMAPHORES]; - /* mboxes this ring signals to */ - i915_reg_t signal[GEN6_NUM_SEMAPHORES]; - } mbox; - u64 signal_ggtt[I915_NUM_ENGINES]; - }; + struct { + /* our mbox written by others */ + u32 wait[GEN6_NUM_SEMAPHORES]; + /* mboxes this ring signals to */ + i915_reg_t signal[GEN6_NUM_SEMAPHORES]; + } mbox; /* AKA wait() */ int (*sync_to)(struct drm_i915_gem_request *req, -- GitLab From 0da715ee60774401bea00dc71fca6fd1096c734a Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 20:55:02 +0000 Subject: [PATCH 0045/2547] drm/i915: Disable semaphores on Sandybridge I should have admitted defeat long ago as there has been a rare but persistent error on Sandybridge where semaphore signaling did not propagate to the waiter, leading to a GPU hang. With the work on fence signaling for v4.9, the impact of using CPU driven signaling was greatly reduced wrt to the latency of GPU semaphores, though without logical rings support, the benefit of reordering work to avoid bubbles is not realised (i.e. as it stands fence signaling is just a slower, more costly version of HW semaphores; but works more consistently). As a rough indicator of the difference, with semaphores: Sequential (3 engines, 1 processes): average 5.470us per cycle [expected 4.988us] w/o semaphores: Sequential (3 engines, 1 processes): average 15.771us per cycle [expected 4.923us] In comparison, v3.4: with semaphores: Sequential (3 engines, 1 processes): average 16.066us per cycle [expected 11.842us] w/o semaphores: Sequential (3 engines, 1 processes): average 23.460us per cycle [expected 11.839us] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54226 #and 100+ dupes Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Acked-by: Mika Kuoppala Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171120205504.21892-3-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index d470e10b2edd..d53bb8e872ba 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4999,20 +4999,12 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv) bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) { - if (INTEL_GEN(dev_priv) < 6) - return false; - - /* TODO: make semaphores and Execlists play nicely together */ - if (HAS_EXECLISTS(dev_priv)) + if (!IS_GEN7(dev_priv)) return false; if (value >= 0) return value; - /* Enable semaphores on SNB when IO remapping is off */ - if (IS_GEN6(dev_priv) && intel_vtd_active()) - return false; - return true; } -- GitLab From af9ff6c70df452b42779aac1bb787ec72d5f257b Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 20:55:03 +0000 Subject: [PATCH 0046/2547] drm/i915: Move debugfs/i915_semaphore_status to i915_engine_info As the semaphores is just part of the engine, include it with the general pretty printer universally used for debugging. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171120205504.21892-4-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_debugfs.c | 32 -------------------------- drivers/gpu/drm/i915/intel_engine_cs.c | 9 ++++++++ 2 files changed, 9 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9cef1463d411..41d49a4d25d3 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3235,37 +3235,6 @@ static int i915_shrinker_info(struct seq_file *m, void *unused) return 0; } -static int i915_semaphore_status(struct seq_file *m, void *unused) -{ - struct drm_i915_private *dev_priv = node_to_i915(m->private); - struct drm_device *dev = &dev_priv->drm; - struct intel_engine_cs *engine; - int num_rings = INTEL_INFO(dev_priv)->num_rings; - enum intel_engine_id id; - int j, ret; - - if (!i915_modparams.semaphores) { - seq_puts(m, "Semaphores are disabled\n"); - return 0; - } - - ret = mutex_lock_interruptible(&dev->struct_mutex); - if (ret) - return ret; - intel_runtime_pm_get(dev_priv); - - seq_puts(m, " Last signal:"); - for_each_engine(engine, dev_priv, id) - for (j = 0; j < num_rings; j++) - seq_printf(m, "0x%08x\n", - I915_READ(engine->semaphore.mbox.signal[j])); - seq_putc(m, '\n'); - - intel_runtime_pm_put(dev_priv); - mutex_unlock(&dev->struct_mutex); - return 0; -} - static int i915_shared_dplls_info(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -4745,7 +4714,6 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_display_info", i915_display_info, 0}, {"i915_engine_info", i915_engine_info, 0}, {"i915_shrinker_info", i915_shrinker_info, 0}, - {"i915_semaphore_status", i915_semaphore_status, 0}, {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, {"i915_dp_mst_info", i915_dp_mst_info, 0}, {"i915_wa_registers", i915_wa_registers, 0}, diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 1fca7ac3b059..ef8e101ebd98 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1713,6 +1713,15 @@ void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m) I915_READ(RING_MI_MODE(engine->mmio_base)), I915_READ(RING_MI_MODE(engine->mmio_base)) & (MODE_IDLE) ? " [idle]" : ""); } + if (i915_modparams.semaphores) { + drm_printf(m, "\tSYNC_0: 0x%08x\n", + I915_READ(RING_SYNC_0(engine->mmio_base))); + drm_printf(m, "\tSYNC_1: 0x%08x\n", + I915_READ(RING_SYNC_1(engine->mmio_base))); + if (HAS_VEBOX(dev_priv)) + drm_printf(m, "\tSYNC_2: 0x%08x\n", + I915_READ(RING_SYNC_2(engine->mmio_base))); + } rcu_read_unlock(); -- GitLab From 93c6e966b4cd1c99d02b488e149df606f811587b Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 20:55:04 +0000 Subject: [PATCH 0047/2547] drm/i915: Remove i915.semaphores modparam Having disabled the broken semaphores on Sandybridge, there is no need for a modparam any more, so remove it in favour of a simple HAS_LEGACY_SEMAPHORES() guard. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Reviewed-by: Maarten Lankhorst Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171120205504.21892-5-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_drv.c | 7 +------ drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm/i915/i915_gem.c | 11 ----------- drivers/gpu/drm/i915/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/i915_params.c | 4 ---- drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++-- 8 files changed, 7 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index c608fd96771c..8dbcb03b5f54 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -321,7 +321,7 @@ static int i915_getparam(struct drm_device *dev, void *data, value = USES_PPGTT(dev_priv); break; case I915_PARAM_HAS_SEMAPHORES: - value = i915_modparams.semaphores; + value = HAS_LEGACY_SEMAPHORES(dev_priv); break; case I915_PARAM_HAS_SECURE_BATCHES: value = capable(CAP_SYS_ADMIN); @@ -1063,11 +1063,6 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv) i915_modparams.enable_ppgtt); DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt); - i915_modparams.semaphores = - intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores); - DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", - yesno(i915_modparams.semaphores)); - intel_uc_sanitize_options(dev_priv); intel_gvt_sanitize_options(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5ce778c26bb8..9a0654e10a55 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3139,6 +3139,8 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) +#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv) + #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) @@ -3302,8 +3304,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, int enable_ppgtt); -bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value); - /* i915_drv.c */ void __printf(3, 4) __i915_printk(struct drm_i915_private *dev_priv, const char *level, diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index d53bb8e872ba..792e6dc7e19b 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4997,17 +4997,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv) return ret; } -bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) -{ - if (!IS_GEN7(dev_priv)) - return false; - - if (value >= 0) - return value; - - return true; -} - static int __intel_engines_record_defaults(struct drm_i915_private *i915) { struct i915_gem_context *ctx; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 0704d9af261b..6ca56e482d79 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -574,7 +574,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 flags) enum intel_engine_id id; const int num_rings = /* Use an extended w/a on gen7 if signalling from other rings */ - (i915_modparams.semaphores && IS_GEN7(dev_priv)) ? + (HAS_LEGACY_SEMAPHORES(dev_priv) && IS_GEN7(dev_priv)) ? INTEL_INFO(dev_priv)->num_rings - 1 : 0; int len; diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index d61c1787c164..3328147b4863 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -46,10 +46,6 @@ i915_param_named_unsafe(panel_ignore_lid, int, 0600, "Override lid status (0=autodetect, 1=autodetect disabled [default], " "-1=force lid closed, -2=force lid open)"); -i915_param_named_unsafe(semaphores, int, 0400, - "Use semaphores for inter-ring sync " - "(default: -1 (use per-chip defaults))"); - i915_param_named_unsafe(enable_rc6, int, 0400, "Enable power-saving render C-state 6. " "Different stages can be selected via bitmask values " diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 0aef3d7178eb..8321bd86cba5 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -31,7 +31,6 @@ param(char *, vbt_firmware, NULL) \ param(int, modeset, -1) \ param(int, panel_ignore_lid, 1) \ - param(int, semaphores, -1) \ param(int, lvds_channel_mode, 0) \ param(int, panel_use_ssc, -1) \ param(int, vbt_sdvo_panel_type, -1) \ diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index ef8e101ebd98..22c095035539 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1713,7 +1713,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m) I915_READ(RING_MI_MODE(engine->mmio_base)), I915_READ(RING_MI_MODE(engine->mmio_base)) & (MODE_IDLE) ? " [idle]" : ""); } - if (i915_modparams.semaphores) { + if (HAS_LEGACY_SEMAPHORES(dev_priv)) { drm_printf(m, "\tSYNC_0: 0x%08x\n", I915_READ(RING_SYNC_0(engine->mmio_base))); drm_printf(m, "\tSYNC_1: 0x%08x\n", diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 5465e708545f..bfa11a84e476 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1712,7 +1712,7 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, { int i; - if (!i915_modparams.semaphores) + if (!HAS_LEGACY_SEMAPHORES(dev_priv)) return; GEM_BUG_ON(INTEL_GEN(dev_priv) < 6); @@ -1823,7 +1823,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, engine->emit_breadcrumb = i9xx_emit_breadcrumb; engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz; - if (i915_modparams.semaphores) { + if (HAS_LEGACY_SEMAPHORES(dev_priv)) { int num_rings; engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; -- GitLab From 0ab42a78712acbdcfefe5aa3205a15393ebbc6d7 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 21:19:07 +0000 Subject: [PATCH 0048/2547] drm/i915/selftests: Declare we allocated the guc clients Silence smatch over drivers/gpu/drm/i915/selftests/intel_guc.c:135 igt_guc_init_doorbell_hw() error: we previously assumed 'guc->execbuf_client' could be null (see line 123) drivers/gpu/drm/i915/selftests/intel_guc.c:142 igt_guc_init_doorbell_hw() error: we previously assumed 'guc->preempt_client' could be null (see line 123) by asserting that we did succeed in creating the pair of clients for testing. References: 55bd6bd75717 ("drm/i915/selftests: Add a GuC doorbells selftest") Signed-off-by: Chris Wilson Cc: Michel Thierry Cc: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Link: https://patchwork.freedesktop.org/patch/msgid/20171120211907.1649-1-chris@chris-wilson.co.uk Reviewed-by: Michel Thierry --- drivers/gpu/drm/i915/selftests/intel_guc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c index f1baeda8b4a8..7b23597858bb 100644 --- a/drivers/gpu/drm/i915/selftests/intel_guc.c +++ b/drivers/gpu/drm/i915/selftests/intel_guc.c @@ -131,6 +131,8 @@ static int igt_guc_init_doorbell_hw(void *args) pr_err("Failed to create clients\n"); goto unlock; } + GEM_BUG_ON(!guc->execbuf_client); + GEM_BUG_ON(!guc->preempt_client); err = validate_client(guc->execbuf_client, GUC_CLIENT_PRIORITY_KMD_NORMAL, false); -- GitLab From 36fe778a489e0461126fc657ff333522c24d5391 Mon Sep 17 00:00:00 2001 From: David Weinehall Date: Fri, 17 Nov 2017 10:01:46 +0200 Subject: [PATCH 0049/2547] drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+ GEN6_RC_VIDEO_FREQ is deprecated for >= gen10; don't try to program it. v2: Use IS_GEN9() instead of INTEL_GEN() and remove comment (Rodrigo) Signed-off-by: David Weinehall Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20171117080146.20150-1-david.weinehall@linux.intel.com --- drivers/gpu/drm/i915/intel_pm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4d2cd432f739..ce5cd75b8130 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6602,9 +6602,10 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv) { intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); - /* Program defaults and thresholds for RPS*/ - I915_WRITE(GEN6_RC_VIDEO_FREQ, - GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq)); + /* Program defaults and thresholds for RPS */ + if (IS_GEN9(dev_priv)) + I915_WRITE(GEN6_RC_VIDEO_FREQ, + GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq)); /* 1 second timeout*/ I915_WRITE(GEN6_RP_DOWN_TIMEOUT, -- GitLab From 7b30255698edc91f9235faf586d21625ca7bbbac Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 20 Nov 2017 13:29:58 +0000 Subject: [PATCH 0050/2547] drm/i915/gvt: Cleanup unwanted public symbols drivers/gpu/drm/i915/gvt/execlist.c:531:6: warning: symbol 'clean_execlist' was not declared. Should it be static? drivers/gpu/drm/i915/gvt/execlist.c:545:6: warning: symbol 'reset_execlist' was not declared. Should it be static? drivers/gpu/drm/i915/gvt/execlist.c:556:5: warning: symbol 'init_execlist' was not declared. Should it be static? drivers/gpu/drm/i915/gvt/scheduler.c:248:6: warning: symbol 'release_shadow_wa_ctx' was not declared. Should it be static? References: 06bb372f9ace ("drm/i915/gvt: Introduce intel_vgpu_reset_submission") Signed-off-by: Chris Wilson Cc: Zhi Wang Cc: Zhenyu Wang Cc: intel-gvt-dev@lists.freedesktop.org Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/execlist.c | 6 +++--- drivers/gpu/drm/i915/gvt/scheduler.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index c9fa0fb488d3..fa4929584744 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c @@ -528,7 +528,7 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu, int ring_id) vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw; } -void clean_execlist(struct intel_vgpu *vgpu) +static void clean_execlist(struct intel_vgpu *vgpu) { enum intel_engine_id i; struct intel_engine_cs *engine; @@ -542,7 +542,7 @@ void clean_execlist(struct intel_vgpu *vgpu) } } -void reset_execlist(struct intel_vgpu *vgpu, +static void reset_execlist(struct intel_vgpu *vgpu, unsigned long engine_mask) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; @@ -553,7 +553,7 @@ void reset_execlist(struct intel_vgpu *vgpu, init_vgpu_execlist(vgpu, engine->id); } -int init_execlist(struct intel_vgpu *vgpu) +static int init_execlist(struct intel_vgpu *vgpu) { reset_execlist(vgpu, ALL_ENGINES); return 0; diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index a742b364c2c3..13ccc00f0d40 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -245,7 +245,7 @@ static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload) return 0; } -void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) +static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) { if (!wa_ctx->indirect_ctx.obj) return; -- GitLab From bd257b2f3bc68514fad19763f540fea581c12d22 Mon Sep 17 00:00:00 2001 From: "Guilherme G. Piccoli" Date: Fri, 17 Nov 2017 19:14:53 -0200 Subject: [PATCH 0051/2547] scsi: aacraid: Check for PCI state of device in a generic way Commit 16ae9dd35d37 ("scsi: aacraid: Fix for excessive prints on EEH") introduced checks about the state of device before any PCI operations in the driver. Basically, this prevents it to perform PCI accesses when device is in the process of recover from a PCI error. In PowerPC, such mechanism is called EEH, and the aforementioned commit introduced checks that are based on EEH-specific primitives for that. The potential problems with this approach are three: first, these checks are "locked" to powerpc only - another archs could have error recovery methods too, like AER in Intel. Also, the powerpc primitives perform expensive FW accesses to validate the precise PCI state of a device. Finally, code becomes more complicated and needs ifdef validation based on arch config being set. So, this patch makes use of generic PCI state checks, which are lightweight and non-dependent of arch configs - also, it makes the code cleaner. Fixes: 16ae9dd35d37 ("scsi: aacraid: Fix for excessive prints on EEH") Signed-off-by: Guilherme G. Piccoli Reviewed-by: Dave Carroll Signed-off-by: Martin K. Petersen --- drivers/scsi/aacraid/commsup.c | 33 ++------------------------------- 1 file changed, 2 insertions(+), 31 deletions(-) diff --git a/drivers/scsi/aacraid/commsup.c b/drivers/scsi/aacraid/commsup.c index 525a652dab48..2abe8fd83494 100644 --- a/drivers/scsi/aacraid/commsup.c +++ b/drivers/scsi/aacraid/commsup.c @@ -467,35 +467,6 @@ int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw return 0; } -#ifdef CONFIG_EEH -static inline int aac_check_eeh_failure(struct aac_dev *dev) -{ - /* Check for an EEH failure for the given - * device node. Function eeh_dev_check_failure() - * returns 0 if there has not been an EEH error - * otherwise returns a non-zero value. - * - * Need to be called before any PCI operation, - * i.e.,before aac_adapter_check_health() - */ - struct eeh_dev *edev = pci_dev_to_eeh_dev(dev->pdev); - - if (eeh_dev_check_failure(edev)) { - /* The EEH mechanisms will handle this - * error and reset the device if - * necessary. - */ - return 1; - } - return 0; -} -#else -static inline int aac_check_eeh_failure(struct aac_dev *dev) -{ - return 0; -} -#endif - /* * Define the highest level of host to adapter communication routines. * These routines will support host to adapter FS commuication. These @@ -701,7 +672,7 @@ int aac_fib_send(u16 command, struct fib *fibptr, unsigned long size, return -ETIMEDOUT; } - if (aac_check_eeh_failure(dev)) + if (unlikely(pci_channel_offline(dev->pdev))) return -EFAULT; if ((blink = aac_adapter_check_health(dev)) > 0) { @@ -801,7 +772,7 @@ int aac_hba_send(u8 command, struct fib *fibptr, fib_callback callback, spin_unlock_irqrestore(&fibptr->event_lock, flags); - if (aac_check_eeh_failure(dev)) + if (unlikely(pci_channel_offline(dev->pdev))) return -EFAULT; fibptr->flags |= FIB_CONTEXT_FLAG_WAIT; -- GitLab From d9b6d85a38df398cfe0ba3f0fae59d58c9a6d433 Mon Sep 17 00:00:00 2001 From: "Guilherme G. Piccoli" Date: Fri, 17 Nov 2017 19:14:54 -0200 Subject: [PATCH 0052/2547] scsi: aacraid: Perform initialization reset only once Currently the driver accepts two ways of requesting an initialization reset on the adapter: by passing aac_reset_devices module parameter, or the generic kernel parameter reset_devices. It's working as intended...but if we end up reaching a scsi hang and the scsi EH mechanism takes place, aacraid performs resets as part of the scsi error recovery procedure. These EH routines might reinitialize the device, and if we have provided some of the reset parameters in the kernel command-line, we again perform an "initialization" reset. So, to avoid this duplication of resets in case of scsi EH path, this patch adds a field to aac_dev struct to keep per-adapter track of the init reset request - once it's done, we set it to false and don't proactively reset anymore in case of reinitializations. Signed-off-by: Guilherme G. Piccoli Reviewed-by: Raghava Aditya Renukunta Signed-off-by: Martin K. Petersen --- drivers/scsi/aacraid/aacraid.h | 1 + drivers/scsi/aacraid/linit.c | 3 +++ drivers/scsi/aacraid/rx.c | 15 ++++++++++----- drivers/scsi/aacraid/src.c | 20 ++++++++++++++------ 4 files changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/scsi/aacraid/aacraid.h b/drivers/scsi/aacraid/aacraid.h index 403a639574e5..6e3d81969a77 100644 --- a/drivers/scsi/aacraid/aacraid.h +++ b/drivers/scsi/aacraid/aacraid.h @@ -1673,6 +1673,7 @@ struct aac_dev struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS]; u8 adapter_shutdown; u32 handle_pci_error; + bool init_reset; }; #define aac_adapter_interrupt(dev) \ diff --git a/drivers/scsi/aacraid/linit.c b/drivers/scsi/aacraid/linit.c index c9252b138c1f..bdf127aaab41 100644 --- a/drivers/scsi/aacraid/linit.c +++ b/drivers/scsi/aacraid/linit.c @@ -1680,6 +1680,9 @@ static int aac_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) aac->cardtype = index; INIT_LIST_HEAD(&aac->entry); + if (aac_reset_devices || reset_devices) + aac->init_reset = true; + aac->fibs = kzalloc(sizeof(struct fib) * (shost->can_queue + AAC_NUM_MGT_FIB), GFP_KERNEL); if (!aac->fibs) goto out_free_host; diff --git a/drivers/scsi/aacraid/rx.c b/drivers/scsi/aacraid/rx.c index 93ef7c37e568..620166694171 100644 --- a/drivers/scsi/aacraid/rx.c +++ b/drivers/scsi/aacraid/rx.c @@ -561,11 +561,16 @@ int _aac_rx_init(struct aac_dev *dev) dev->a_ops.adapter_sync_cmd = rx_sync_cmd; dev->a_ops.adapter_enable_int = aac_rx_disable_interrupt; dev->OIMR = status = rx_readb (dev, MUnit.OIMR); - if ((((status & 0x0c) != 0x0c) || aac_reset_devices || reset_devices) && - !aac_rx_restart_adapter(dev, 0, IOP_HWSOFT_RESET)) - /* Make sure the Hardware FIFO is empty */ - while ((++restart < 512) && - (rx_readl(dev, MUnit.OutboundQueue) != 0xFFFFFFFFL)); + + if (((status & 0x0c) != 0x0c) || dev->init_reset) { + dev->init_reset = false; + if (!aac_rx_restart_adapter(dev, 0, IOP_HWSOFT_RESET)) { + /* Make sure the Hardware FIFO is empty */ + while ((++restart < 512) && + (rx_readl(dev, MUnit.OutboundQueue) != 0xFFFFFFFFL)); + } + } + /* * Check to see if the board panic'd while booting. */ diff --git a/drivers/scsi/aacraid/src.c b/drivers/scsi/aacraid/src.c index 0c9361c87ec8..fde6b6aa86e3 100644 --- a/drivers/scsi/aacraid/src.c +++ b/drivers/scsi/aacraid/src.c @@ -868,9 +868,13 @@ int aac_src_init(struct aac_dev *dev) /* Failure to reset here is an option ... */ dev->a_ops.adapter_sync_cmd = src_sync_cmd; dev->a_ops.adapter_enable_int = aac_src_disable_interrupt; - if ((aac_reset_devices || reset_devices) && - !aac_src_restart_adapter(dev, 0, IOP_HWSOFT_RESET)) - ++restart; + + if (dev->init_reset) { + dev->init_reset = false; + if (!aac_src_restart_adapter(dev, 0, IOP_HWSOFT_RESET)) + ++restart; + } + /* * Check to see if the board panic'd while booting. */ @@ -1014,9 +1018,13 @@ int aac_srcv_init(struct aac_dev *dev) /* Failure to reset here is an option ... */ dev->a_ops.adapter_sync_cmd = src_sync_cmd; dev->a_ops.adapter_enable_int = aac_src_disable_interrupt; - if ((aac_reset_devices || reset_devices) && - !aac_src_restart_adapter(dev, 0, IOP_HWSOFT_RESET)) - ++restart; + + if (dev->init_reset) { + dev->init_reset = false; + if (!aac_src_restart_adapter(dev, 0, IOP_HWSOFT_RESET)) + ++restart; + } + /* * Check to see if flash update is running. * Wait for the adapter to be up and running. Wait up to 5 minutes -- GitLab From e4717292ddebcfe231651b5aff9fa19ca158d178 Mon Sep 17 00:00:00 2001 From: "Guilherme G. Piccoli" Date: Fri, 17 Nov 2017 19:14:55 -0200 Subject: [PATCH 0053/2547] scsi: aacraid: Prevent crash in case of free interrupt during scsi EH path As part of the scsi EH path, aacraid performs a reinitialization of the adapter, which encompass freeing resources and IRQs, NULLifying lots of pointers, and then initialize it all over again. We've identified a problem during the free IRQ portion of this path if CONFIG_DEBUG_SHIRQ is enabled on kernel config file. Happens that, in case this flag was set, right after free_irq() effectively clears the interrupt, it checks if it was requested as IRQF_SHARED. In positive case, it performs another call to the IRQ handler on driver. Problem is: since aacraid currently free some resources *before* freeing the IRQ, once free_irq() path calls the handler again (due to CONFIG_DEBUG_SHIRQ), aacraid crashes due to NULL pointer dereference with the following trace: aac_src_intr_message+0xf8/0x740 [aacraid] __free_irq+0x33c/0x4a0 free_irq+0x78/0xb0 aac_free_irq+0x13c/0x150 [aacraid] aac_reset_adapter+0x2e8/0x970 [aacraid] aac_eh_reset+0x3a8/0x5d0 [aacraid] scsi_try_host_reset+0x74/0x180 scsi_eh_ready_devs+0xc70/0x1510 scsi_error_handler+0x624/0xa20 This patch prevents the crash by changing the order of the deinitialization in this path of aacraid: first we clear the IRQ, then we free other resources. No functional change intended. Signed-off-by: Guilherme G. Piccoli Reviewed-by: Raghava Aditya Renukunta Signed-off-by: Martin K. Petersen --- drivers/scsi/aacraid/commsup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/scsi/aacraid/commsup.c b/drivers/scsi/aacraid/commsup.c index 2abe8fd83494..bec9f3193f60 100644 --- a/drivers/scsi/aacraid/commsup.c +++ b/drivers/scsi/aacraid/commsup.c @@ -1554,6 +1554,7 @@ static int _aac_reset_adapter(struct aac_dev *aac, int forced, u8 reset_type) * will ensure that i/o is queisced and the card is flushed in that * case. */ + aac_free_irq(aac); aac_fib_map_free(aac); dma_free_coherent(&aac->pdev->dev, aac->comm_size, aac->comm_addr, aac->comm_phys); @@ -1561,7 +1562,6 @@ static int _aac_reset_adapter(struct aac_dev *aac, int forced, u8 reset_type) aac->comm_phys = 0; kfree(aac->queues); aac->queues = NULL; - aac_free_irq(aac); kfree(aac->fsa_dev); aac->fsa_dev = NULL; -- GitLab From 51f5a096398433a881e845d3685a2c1dac756019 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 17 Nov 2017 21:19:08 +0200 Subject: [PATCH 0054/2547] drm/i915: Add .get_hw_state() method for planes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a .get_hw_state() method for planes, returning true or false depending on whether the plane is enabled. Use it to rewrite the plane enabled/disabled asserts in platform agnostic fashion. We do lose the pre-gen4 plane<->pipe mapping checks, but since we're supposed sanitize that anyway it doesn't really matter. v2: Reoder patches to not depend on enum old_plane_id Just call assert_plane_disabled() from assert_planes_disabled() v3: Deal with disabled power wells in .get_hw_state() v4: Rebase due skl primary plane code removal Cc: Thierry Reding Cc: Alex Villacís Lasso Reviewed-by: Daniel Vetter #v2 Tested-by: Thierry Reding #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20171117191917.11506-2-ville.syrjala@linux.intel.com Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 188 +++++++++++++-------------- drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_sprite.c | 83 ++++++++++++ 3 files changed, 175 insertions(+), 98 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3b3dec1e6640..7bf8290f0343 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1190,23 +1190,6 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) pipe_name(pipe)); } -static void assert_cursor(struct drm_i915_private *dev_priv, - enum pipe pipe, bool state) -{ - bool cur_state; - - if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) - cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; - else - cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; - - I915_STATE_WARN(cur_state != state, - "cursor on pipe %c assertion failure (expected %s, current %s)\n", - pipe_name(pipe), onoff(state), onoff(cur_state)); -} -#define assert_cursor_enabled(d, p) assert_cursor(d, p, true) -#define assert_cursor_disabled(d, p) assert_cursor(d, p, false) - void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state) { @@ -1234,77 +1217,25 @@ void assert_pipe(struct drm_i915_private *dev_priv, pipe_name(pipe), onoff(state), onoff(cur_state)); } -static void assert_plane(struct drm_i915_private *dev_priv, - enum plane plane, bool state) +static void assert_plane(struct intel_plane *plane, bool state) { - u32 val; - bool cur_state; + bool cur_state = plane->get_hw_state(plane); - val = I915_READ(DSPCNTR(plane)); - cur_state = !!(val & DISPLAY_PLANE_ENABLE); I915_STATE_WARN(cur_state != state, - "plane %c assertion failure (expected %s, current %s)\n", - plane_name(plane), onoff(state), onoff(cur_state)); + "%s assertion failure (expected %s, current %s)\n", + plane->base.name, onoff(state), onoff(cur_state)); } -#define assert_plane_enabled(d, p) assert_plane(d, p, true) -#define assert_plane_disabled(d, p) assert_plane(d, p, false) +#define assert_plane_enabled(p) assert_plane(p, true) +#define assert_plane_disabled(p) assert_plane(p, false) -static void assert_planes_disabled(struct drm_i915_private *dev_priv, - enum pipe pipe) +static void assert_planes_disabled(struct intel_crtc *crtc) { - int i; - - /* Primary planes are fixed to pipes on gen4+ */ - if (INTEL_GEN(dev_priv) >= 4) { - u32 val = I915_READ(DSPCNTR(pipe)); - I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, - "plane %c assertion failure, should be disabled but not\n", - plane_name(pipe)); - return; - } - - /* Need to check both planes against the pipe */ - for_each_pipe(dev_priv, i) { - u32 val = I915_READ(DSPCNTR(i)); - enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> - DISPPLANE_SEL_PIPE_SHIFT; - I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, - "plane %c assertion failure, should be off on pipe %c but is still active\n", - plane_name(i), pipe_name(pipe)); - } -} - -static void assert_sprites_disabled(struct drm_i915_private *dev_priv, - enum pipe pipe) -{ - int sprite; + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_plane *plane; - if (INTEL_GEN(dev_priv) >= 9) { - for_each_sprite(dev_priv, pipe, sprite) { - u32 val = I915_READ(PLANE_CTL(pipe, sprite)); - I915_STATE_WARN(val & PLANE_CTL_ENABLE, - "plane %d assertion failure, should be off on pipe %c but is still active\n", - sprite, pipe_name(pipe)); - } - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - for_each_sprite(dev_priv, pipe, sprite) { - u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); - I915_STATE_WARN(val & SP_ENABLE, - "sprite %c assertion failure, should be off on pipe %c but is still active\n", - sprite_name(pipe, sprite), pipe_name(pipe)); - } - } else if (INTEL_GEN(dev_priv) >= 7) { - u32 val = I915_READ(SPRCTL(pipe)); - I915_STATE_WARN(val & SPRITE_ENABLE, - "sprite %c assertion failure, should be off on pipe %c but is still active\n", - plane_name(pipe), pipe_name(pipe)); - } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { - u32 val = I915_READ(DVSCNTR(pipe)); - I915_STATE_WARN(val & DVS_ENABLE, - "sprite %c assertion failure, should be off on pipe %c but is still active\n", - plane_name(pipe), pipe_name(pipe)); - } + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) + assert_plane_disabled(plane); } static void assert_vblank_disabled(struct drm_crtc *crtc) @@ -1896,9 +1827,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); - assert_planes_disabled(dev_priv, pipe); - assert_cursor_disabled(dev_priv, pipe); - assert_sprites_disabled(dev_priv, pipe); + assert_planes_disabled(crtc); /* * A pipe without a PLL won't actually be able to drive bits from @@ -1968,9 +1897,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc) * Make sure planes won't keep trying to pump pixels to us, * or we might hang the display. */ - assert_planes_disabled(dev_priv, pipe); - assert_cursor_disabled(dev_priv, pipe); - assert_sprites_disabled(dev_priv, pipe); + assert_planes_disabled(crtc); reg = PIPECONF(cpu_transcoder); val = I915_READ(reg); @@ -3364,6 +3291,31 @@ static void i9xx_disable_primary_plane(struct intel_plane *primary, spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } +static bool i9xx_plane_get_hw_state(struct intel_plane *primary) +{ + + struct drm_i915_private *dev_priv = to_i915(primary->base.dev); + enum intel_display_power_domain power_domain; + enum plane plane = primary->plane; + enum pipe pipe = primary->pipe; + bool ret; + + /* + * Not 100% correct for planes that can move between pipes, + * but that's only the case for gen2-4 which don't have any + * display power wells. + */ + power_domain = POWER_DOMAIN_PIPE(pipe); + if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) + return false; + + ret = I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE; + + intel_display_power_put(dev_priv, power_domain); + + return ret; +} + static u32 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane) { @@ -4879,7 +4831,8 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) * a vblank wait. */ - assert_plane_enabled(dev_priv, crtc->plane); + assert_plane_enabled(to_intel_plane(crtc->base.primary)); + if (IS_BROADWELL(dev_priv)) { mutex_lock(&dev_priv->pcu_lock); WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, @@ -4913,7 +4866,8 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state) if (!crtc_state->ips_enabled) return; - assert_plane_enabled(dev_priv, crtc->plane); + assert_plane_enabled(to_intel_plane(crtc->base.primary)); + if (IS_BROADWELL(dev_priv)) { mutex_lock(&dev_priv->pcu_lock); WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); @@ -9499,6 +9453,23 @@ static void i845_disable_cursor(struct intel_plane *plane, i845_update_cursor(plane, NULL, NULL); } +static bool i845_cursor_get_hw_state(struct intel_plane *plane) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + enum intel_display_power_domain power_domain; + bool ret; + + power_domain = POWER_DOMAIN_PIPE(PIPE_A); + if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) + return false; + + ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; + + intel_display_power_put(dev_priv, power_domain); + + return ret; +} + static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { @@ -9692,6 +9663,28 @@ static void i9xx_disable_cursor(struct intel_plane *plane, i9xx_update_cursor(plane, NULL, NULL); } +static bool i9xx_cursor_get_hw_state(struct intel_plane *plane) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + enum intel_display_power_domain power_domain; + enum pipe pipe = plane->pipe; + bool ret; + + /* + * Not 100% correct for planes that can move between pipes, + * but that's only the case for gen2-3 which don't have any + * display power wells. + */ + power_domain = POWER_DOMAIN_PIPE(pipe); + if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) + return false; + + ret = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; + + intel_display_power_put(dev_priv, power_domain); + + return ret; +} /* VESA 640x480x72Hz mode to set on the pipe */ static const struct drm_display_mode load_detect_mode = { @@ -13279,6 +13272,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) primary->update_plane = skl_update_plane; primary->disable_plane = skl_disable_plane; + primary->get_hw_state = skl_plane_get_hw_state; } else if (INTEL_GEN(dev_priv) >= 9) { intel_primary_formats = skl_primary_formats; num_formats = ARRAY_SIZE(skl_primary_formats); @@ -13289,6 +13283,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) primary->update_plane = skl_update_plane; primary->disable_plane = skl_disable_plane; + primary->get_hw_state = skl_plane_get_hw_state; } else if (INTEL_GEN(dev_priv) >= 4) { intel_primary_formats = i965_primary_formats; num_formats = ARRAY_SIZE(i965_primary_formats); @@ -13296,6 +13291,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) primary->update_plane = i9xx_update_primary_plane; primary->disable_plane = i9xx_disable_primary_plane; + primary->get_hw_state = i9xx_plane_get_hw_state; } else { intel_primary_formats = i8xx_primary_formats; num_formats = ARRAY_SIZE(i8xx_primary_formats); @@ -13303,6 +13299,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) primary->update_plane = i9xx_update_primary_plane; primary->disable_plane = i9xx_disable_primary_plane; + primary->get_hw_state = i9xx_plane_get_hw_state; } if (INTEL_GEN(dev_priv) >= 9) @@ -13392,10 +13389,12 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { cursor->update_plane = i845_update_cursor; cursor->disable_plane = i845_disable_cursor; + cursor->get_hw_state = i845_cursor_get_hw_state; cursor->check_plane = i845_check_cursor; } else { cursor->update_plane = i9xx_update_cursor; cursor->disable_plane = i9xx_disable_cursor; + cursor->get_hw_state = i9xx_cursor_get_hw_state; cursor->check_plane = i9xx_check_cursor; } @@ -14761,8 +14760,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n", pipe_name(pipe)); - assert_plane_disabled(dev_priv, PLANE_A); - assert_plane_disabled(dev_priv, PLANE_B); + assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_A)); + assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_B)); I915_WRITE(PIPECONF(pipe), 0); POSTING_READ(PIPECONF(pipe)); @@ -14976,20 +14975,13 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv) intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); } -static bool primary_get_hw_state(struct intel_plane *plane) -{ - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); - - return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; -} - /* FIXME read out full plane state for all planes */ static void readout_plane_state(struct intel_crtc *crtc) { struct intel_plane *primary = to_intel_plane(crtc->base.primary); bool visible; - visible = crtc->active && primary_get_hw_state(primary); + visible = crtc->active && primary->get_hw_state(primary); intel_set_plane_visible(to_intel_crtc_state(crtc->base.state), to_intel_plane_state(primary->base.state), diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 69aab324aaa1..99840f3940c7 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -866,6 +866,7 @@ struct intel_plane { const struct intel_plane_state *plane_state); void (*disable_plane)(struct intel_plane *plane, struct intel_crtc *crtc); + bool (*get_hw_state)(struct intel_plane *plane); int (*check_plane)(struct intel_plane *plane, struct intel_crtc_state *crtc_state, struct intel_plane_state *state); @@ -1934,6 +1935,7 @@ void skl_update_plane(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc); +bool skl_plane_get_hw_state(struct intel_plane *plane); /* intel_tv.c */ void intel_tv_init(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index ce615704982a..5baa0023964e 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -325,6 +325,26 @@ skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } +bool +skl_plane_get_hw_state(struct intel_plane *plane) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + enum intel_display_power_domain power_domain; + enum plane_id plane_id = plane->id; + enum pipe pipe = plane->pipe; + bool ret; + + power_domain = POWER_DOMAIN_PIPE(pipe); + if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) + return false; + + ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE; + + intel_display_power_put(dev_priv, power_domain); + + return ret; +} + static void chv_update_csc(struct intel_plane *plane, uint32_t format) { @@ -502,6 +522,26 @@ vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } +static bool +vlv_plane_get_hw_state(struct intel_plane *plane) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + enum intel_display_power_domain power_domain; + enum plane_id plane_id = plane->id; + enum pipe pipe = plane->pipe; + bool ret; + + power_domain = POWER_DOMAIN_PIPE(pipe); + if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) + return false; + + ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE; + + intel_display_power_put(dev_priv, power_domain); + + return ret; +} + static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { @@ -642,6 +682,25 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } +static bool +ivb_plane_get_hw_state(struct intel_plane *plane) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + enum intel_display_power_domain power_domain; + enum pipe pipe = plane->pipe; + bool ret; + + power_domain = POWER_DOMAIN_PIPE(pipe); + if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) + return false; + + ret = I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE; + + intel_display_power_put(dev_priv, power_domain); + + return ret; +} + static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { @@ -773,6 +832,25 @@ g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } +static bool +g4x_plane_get_hw_state(struct intel_plane *plane) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + enum intel_display_power_domain power_domain; + enum pipe pipe = plane->pipe; + bool ret; + + power_domain = POWER_DOMAIN_PIPE(pipe); + if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) + return false; + + ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE; + + intel_display_power_put(dev_priv, power_domain); + + return ret; +} + static int intel_check_sprite_plane(struct intel_plane *plane, struct intel_crtc_state *crtc_state, @@ -1231,6 +1309,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, intel_plane->update_plane = skl_update_plane; intel_plane->disable_plane = skl_disable_plane; + intel_plane->get_hw_state = skl_plane_get_hw_state; plane_formats = skl_plane_formats; num_plane_formats = ARRAY_SIZE(skl_plane_formats); @@ -1241,6 +1320,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, intel_plane->update_plane = skl_update_plane; intel_plane->disable_plane = skl_disable_plane; + intel_plane->get_hw_state = skl_plane_get_hw_state; plane_formats = skl_plane_formats; num_plane_formats = ARRAY_SIZE(skl_plane_formats); @@ -1251,6 +1331,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, intel_plane->update_plane = vlv_update_plane; intel_plane->disable_plane = vlv_disable_plane; + intel_plane->get_hw_state = vlv_plane_get_hw_state; plane_formats = vlv_plane_formats; num_plane_formats = ARRAY_SIZE(vlv_plane_formats); @@ -1266,6 +1347,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, intel_plane->update_plane = ivb_update_plane; intel_plane->disable_plane = ivb_disable_plane; + intel_plane->get_hw_state = ivb_plane_get_hw_state; plane_formats = snb_plane_formats; num_plane_formats = ARRAY_SIZE(snb_plane_formats); @@ -1276,6 +1358,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, intel_plane->update_plane = g4x_update_plane; intel_plane->disable_plane = g4x_disable_plane; + intel_plane->get_hw_state = g4x_plane_get_hw_state; modifiers = i9xx_plane_format_modifiers; if (IS_GEN6(dev_priv)) { -- GitLab From b1e01595a66dc206a2c75401ec4c285740537f3f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 17 Nov 2017 21:19:09 +0200 Subject: [PATCH 0055/2547] drm/i915: Redo plane sanitation during readout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unify the plane disabling during state readout by pulling the code into a new helper intel_plane_disable_noatomic(). We'll also read out the state of all planes, so that we know which planes really need to be diabled. Additonally we change the plane<->pipe mapping sanitation to work by simply disabling the offending planes instead of entire pipes. And we do it before we otherwise sanitize the crtcs, which means we don't have to worry about misassigned planes during crtc sanitation anymore. v2: Reoder patches to not depend on enum old_plane_id v3: s/for_each_pipe/for_each_intel_crtc/ Cc: Thierry Reding Cc: Alex Villacís Lasso Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103223 Reviewed-by: Daniel Vetter Tested-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20171117191917.11506-3-ville.syrjala@linux.intel.com Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 114 +++++++++++++++------------ 1 file changed, 65 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7bf8290f0343..91f74c5373b3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2726,6 +2726,23 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state, crtc_state->active_planes); } +static void intel_plane_disable_noatomic(struct intel_crtc *crtc, + struct intel_plane *plane) +{ + struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + struct intel_plane_state *plane_state = + to_intel_plane_state(plane->base.state); + + intel_set_plane_visible(crtc_state, plane_state, false); + + if (plane->id == PLANE_PRIMARY) + intel_pre_disable_primary_noatomic(&crtc->base); + + trace_intel_disable_plane(&plane->base, crtc); + plane->disable_plane(plane, crtc); +} + static void intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, struct intel_initial_plane_config *plane_config) @@ -2783,12 +2800,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, * simplest solution is to just disable the primary plane now and * pretend the BIOS never had it enabled. */ - intel_set_plane_visible(to_intel_crtc_state(crtc_state), - to_intel_plane_state(plane_state), - false); - intel_pre_disable_primary_noatomic(&intel_crtc->base); - trace_intel_disable_plane(primary, intel_crtc); - intel_plane->disable_plane(intel_plane, intel_crtc); + intel_plane_disable_noatomic(intel_crtc, intel_plane); return; @@ -5869,6 +5881,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->dev); enum intel_display_power_domain domain; + struct intel_plane *plane; u64 domains; struct drm_atomic_state *state; struct intel_crtc_state *crtc_state; @@ -5877,11 +5890,12 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, if (!intel_crtc->active) return; - if (crtc->primary->state->visible) { - intel_pre_disable_primary_noatomic(crtc); + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) { + const struct intel_plane_state *plane_state = + to_intel_plane_state(plane->base.state); - intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); - crtc->primary->state->visible = false; + if (plane_state->base.visible) + intel_plane_disable_noatomic(intel_crtc, plane); } state = drm_atomic_state_alloc(crtc->dev); @@ -14773,22 +14787,36 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) POSTING_READ(DPLL(pipe)); } -static bool -intel_check_plane_mapping(struct intel_crtc *crtc) +static bool intel_plane_mapping_ok(struct intel_crtc *crtc, + struct intel_plane *primary) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 val; + enum plane plane = primary->plane; + u32 val = I915_READ(DSPCNTR(plane)); - if (INTEL_INFO(dev_priv)->num_pipes == 1) - return true; + return (val & DISPLAY_PLANE_ENABLE) == 0 || + (val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe); +} - val = I915_READ(DSPCNTR(!crtc->plane)); +static void +intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) +{ + struct intel_crtc *crtc; - if ((val & DISPLAY_PLANE_ENABLE) && - (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) - return false; + if (INTEL_GEN(dev_priv) >= 4) + return; - return true; + for_each_intel_crtc(&dev_priv->drm, crtc) { + struct intel_plane *plane = + to_intel_plane(crtc->base.primary); + + if (intel_plane_mapping_ok(crtc, plane)) + continue; + + DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n", + plane->base.name); + intel_plane_disable_noatomic(crtc, plane); + } } static bool intel_crtc_has_encoders(struct intel_crtc *crtc) @@ -14844,33 +14872,15 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc, /* Disable everything but the primary plane */ for_each_intel_plane_on_crtc(dev, crtc, plane) { - if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) - continue; + const struct intel_plane_state *plane_state = + to_intel_plane_state(plane->base.state); - trace_intel_disable_plane(&plane->base, crtc); - plane->disable_plane(plane, crtc); + if (plane_state->base.visible && + plane->base.type != DRM_PLANE_TYPE_PRIMARY) + intel_plane_disable_noatomic(crtc, plane); } } - /* We need to sanitize the plane -> pipe mapping first because this will - * disable the crtc (and hence change the state) if it is wrong. Note - * that gen4+ has a fixed plane -> pipe mapping. */ - if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { - bool plane; - - DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", - crtc->base.base.id, crtc->base.name); - - /* Pipe has the wrong plane attached and the plane is active. - * Temporarily change the plane mapping and disable everything - * ... */ - plane = crtc->plane; - crtc->base.primary->state->visible = true; - crtc->plane = !plane; - intel_crtc_disable_noatomic(&crtc->base, ctx); - crtc->plane = plane; - } - /* Adjust the state of the output pipe according to whether we * have active connectors/encoders. */ if (crtc->active && !intel_crtc_has_encoders(crtc)) @@ -14978,14 +14988,18 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv) /* FIXME read out full plane state for all planes */ static void readout_plane_state(struct intel_crtc *crtc) { - struct intel_plane *primary = to_intel_plane(crtc->base.primary); - bool visible; + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + struct intel_plane *plane; - visible = crtc->active && primary->get_hw_state(primary); + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { + struct intel_plane_state *plane_state = + to_intel_plane_state(plane->base.state); + bool visible = plane->get_hw_state(plane); - intel_set_plane_visible(to_intel_crtc_state(crtc->base.state), - to_intel_plane_state(primary->base.state), - visible); + intel_set_plane_visible(crtc_state, plane_state, visible); + } } static void intel_modeset_readout_hw_state(struct drm_device *dev) @@ -15193,6 +15207,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev, /* HW state is read out, now we need to sanitize this mess. */ get_encoder_power_domains(dev_priv); + intel_sanitize_plane_mapping(dev_priv); + for_each_intel_encoder(dev, encoder) { intel_sanitize_encoder(encoder); } -- GitLab From ed15030d7ab0cfe395a494f03e5ee2e66ccb8be9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 17 Nov 2017 21:19:10 +0200 Subject: [PATCH 0056/2547] drm/i915: s/enum plane/enum i9xx_plane_id/ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename enum plane to enum i9xx_plane_id to make it clear that it only applies to pre-SKL platforms. enum i9xx_plane_id is a global identifier, whereas enum plane_id is per-pipe. We need the old global identifier to index the primary plane (and the pre-g4x sprite C if we ever expose it) registers on pre-SKL platforms. v2: Reorder patches v3: s/old_plane_id/i9xx_plane_id/ (Daniel) Pimp the commit message a bit Note that i9xx_plane_id doesn't apply to SKL+ v4: Rebase due to power domain handling in plane readout v5: Rebase due to crtc->dspaddr_offset removal v6: s/plane/i9xx_plane/ etc. (James) Cc: James Ausmus Cc: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171117191917.11506-4-ville.syrjala@linux.intel.com Reviewed-by: James Ausmus Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 6 +- drivers/gpu/drm/i915/intel_display.c | 98 ++++++++++++++-------------- drivers/gpu/drm/i915/intel_drv.h | 6 +- drivers/gpu/drm/i915/intel_fbc.c | 12 ++-- drivers/gpu/drm/i915/intel_sprite.c | 2 +- 5 files changed, 62 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9a0654e10a55..d63a731ef60b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -304,9 +304,9 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder) /* * Global legacy plane identifier. Valid only for primary/sprite - * planes on pre-g4x, and only for primary planes on g4x+. + * planes on pre-g4x, and only for primary planes on g4x-bdw. */ -enum plane { +enum i9xx_plane_id { PLANE_A, PLANE_B, PLANE_C, @@ -1144,7 +1144,7 @@ struct intel_fbc { struct { enum pipe pipe; - enum plane plane; + enum i9xx_plane_id i9xx_plane; unsigned int fence_y_offset; } crtc; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 91f74c5373b3..16ac86816f28 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3220,16 +3220,16 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) return 0; } -static void i9xx_update_primary_plane(struct intel_plane *primary, - const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state) +static void i9xx_update_plane(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = to_i915(primary->base.dev); + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->base.fb; - enum plane plane = primary->plane; + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; u32 linear_offset; u32 dspcntr = plane_state->ctl; - i915_reg_t reg = DSPCNTR(plane); + i915_reg_t reg = DSPCNTR(i9xx_plane); int x = plane_state->main.x; int y = plane_state->main.y; unsigned long irqflags; @@ -3248,34 +3248,34 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, /* pipesrc and dspsize control the size that is scaled from, * which should always be the user's requested size. */ - I915_WRITE_FW(DSPSIZE(plane), + I915_WRITE_FW(DSPSIZE(i9xx_plane), ((crtc_state->pipe_src_h - 1) << 16) | (crtc_state->pipe_src_w - 1)); - I915_WRITE_FW(DSPPOS(plane), 0); - } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { - I915_WRITE_FW(PRIMSIZE(plane), + I915_WRITE_FW(DSPPOS(i9xx_plane), 0); + } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { + I915_WRITE_FW(PRIMSIZE(i9xx_plane), ((crtc_state->pipe_src_h - 1) << 16) | (crtc_state->pipe_src_w - 1)); - I915_WRITE_FW(PRIMPOS(plane), 0); - I915_WRITE_FW(PRIMCNSTALPHA(plane), 0); + I915_WRITE_FW(PRIMPOS(i9xx_plane), 0); + I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0); } I915_WRITE_FW(reg, dspcntr); - I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]); + I915_WRITE_FW(DSPSTRIDE(i9xx_plane), fb->pitches[0]); if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - I915_WRITE_FW(DSPSURF(plane), + I915_WRITE_FW(DSPSURF(i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); - I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x); + I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x); } else if (INTEL_GEN(dev_priv) >= 4) { - I915_WRITE_FW(DSPSURF(plane), + I915_WRITE_FW(DSPSURF(i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); - I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x); - I915_WRITE_FW(DSPLINOFF(plane), linear_offset); + I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x); + I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset); } else { - I915_WRITE_FW(DSPADDR(plane), + I915_WRITE_FW(DSPADDR(i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } @@ -3284,32 +3284,31 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } -static void i9xx_disable_primary_plane(struct intel_plane *primary, - struct intel_crtc *crtc) +static void i9xx_disable_plane(struct intel_plane *plane, + struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(primary->base.dev); - enum plane plane = primary->plane; + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; unsigned long irqflags; spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DSPCNTR(plane), 0); - if (INTEL_INFO(dev_priv)->gen >= 4) - I915_WRITE_FW(DSPSURF(plane), 0); + I915_WRITE_FW(DSPCNTR(i9xx_plane), 0); + if (INTEL_GEN(dev_priv) >= 4) + I915_WRITE_FW(DSPSURF(i9xx_plane), 0); else - I915_WRITE_FW(DSPADDR(plane), 0); - POSTING_READ_FW(DSPCNTR(plane)); + I915_WRITE_FW(DSPADDR(i9xx_plane), 0); + POSTING_READ_FW(DSPCNTR(i9xx_plane)); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } -static bool i9xx_plane_get_hw_state(struct intel_plane *primary) +static bool i9xx_plane_get_hw_state(struct intel_plane *plane) { - - struct drm_i915_private *dev_priv = to_i915(primary->base.dev); + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum intel_display_power_domain power_domain; - enum plane plane = primary->plane; - enum pipe pipe = primary->pipe; + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + enum pipe pipe = plane->pipe; bool ret; /* @@ -3321,7 +3320,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *primary) if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) return false; - ret = I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE; + ret = I915_READ(DSPCNTR(i9xx_plane)) & DISPLAY_PLANE_ENABLE; intel_display_power_put(dev_priv, power_domain); @@ -7406,7 +7405,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); u32 val, base, offset; - int pipe = crtc->pipe, plane = crtc->plane; + int pipe = crtc->pipe, plane = crtc->i9xx_plane; int fourcc, pixel_format; unsigned int aligned_height; struct drm_framebuffer *fb; @@ -13272,9 +13271,9 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) * port is hooked to pipe B. Hence we want plane A feeding pipe B. */ if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) - primary->plane = (enum plane) !pipe; + primary->i9xx_plane = (enum i9xx_plane_id) !pipe; else - primary->plane = (enum plane) pipe; + primary->i9xx_plane = (enum i9xx_plane_id) pipe; primary->id = PLANE_PRIMARY; primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); primary->check_plane = intel_check_primary_plane; @@ -13303,16 +13302,16 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) num_formats = ARRAY_SIZE(i965_primary_formats); modifiers = i9xx_format_modifiers; - primary->update_plane = i9xx_update_primary_plane; - primary->disable_plane = i9xx_disable_primary_plane; + primary->update_plane = i9xx_update_plane; + primary->disable_plane = i9xx_disable_plane; primary->get_hw_state = i9xx_plane_get_hw_state; } else { intel_primary_formats = i8xx_primary_formats; num_formats = ARRAY_SIZE(i8xx_primary_formats); modifiers = i9xx_format_modifiers; - primary->update_plane = i9xx_update_primary_plane; - primary->disable_plane = i9xx_disable_primary_plane; + primary->update_plane = i9xx_update_plane; + primary->disable_plane = i9xx_disable_plane; primary->get_hw_state = i9xx_plane_get_hw_state; } @@ -13336,7 +13335,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) intel_primary_formats, num_formats, modifiers, DRM_PLANE_TYPE_PRIMARY, - "plane %c", plane_name(primary->plane)); + "plane %c", + plane_name(primary->i9xx_plane)); if (ret) goto fail; @@ -13396,7 +13396,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, cursor->can_scale = false; cursor->max_downscale = 1; cursor->pipe = pipe; - cursor->plane = pipe; + cursor->i9xx_plane = (enum i9xx_plane_id) pipe; cursor->id = PLANE_CURSOR; cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); @@ -13524,14 +13524,14 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) goto fail; intel_crtc->pipe = pipe; - intel_crtc->plane = primary->plane; + intel_crtc->i9xx_plane = primary->i9xx_plane; /* initialize shared scalers */ intel_crtc_init_scalers(intel_crtc, crtc_state); BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || - dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); - dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; + dev_priv->plane_to_crtc_mapping[intel_crtc->i9xx_plane] != NULL); + dev_priv->plane_to_crtc_mapping[intel_crtc->i9xx_plane] = intel_crtc; dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); @@ -14788,11 +14788,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) } static bool intel_plane_mapping_ok(struct intel_crtc *crtc, - struct intel_plane *primary) + struct intel_plane *plane) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum plane plane = primary->plane; - u32 val = I915_READ(DSPCNTR(plane)); + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + u32 val = I915_READ(DSPCNTR(i9xx_plane)); return (val & DISPLAY_PLANE_ENABLE) == 0 || (val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 99840f3940c7..d1fe7be94b62 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -799,7 +799,7 @@ struct intel_crtc_state { struct intel_crtc { struct drm_crtc base; enum pipe pipe; - enum plane plane; + enum i9xx_plane_id i9xx_plane; /* * Whether the crtc and the connected output pipeline is active. Implies * that crtc->enabled is set, i.e. the current mode configuration has @@ -844,7 +844,7 @@ struct intel_crtc { struct intel_plane { struct drm_plane base; - u8 plane; + enum i9xx_plane_id i9xx_plane; enum plane_id id; enum pipe pipe; bool can_scale; @@ -1130,7 +1130,7 @@ intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) } static inline struct intel_crtc * -intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane) +intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane) { return dev_priv->plane_to_crtc_mapping[plane]; } diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 1a0f5e0c8d10..3133131306a9 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -151,7 +151,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) /* Set it up... */ fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; - fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane); + fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane); I915_WRITE(FBC_CONTROL2, fbc_ctl2); I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset); } @@ -177,7 +177,7 @@ static void g4x_fbc_activate(struct drm_i915_private *dev_priv) struct intel_fbc_reg_params *params = &dev_priv->fbc.params; u32 dpfc_ctl; - dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN; + dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN; if (params->fb.format->cpp[0] == 2) dpfc_ctl |= DPFC_CTL_LIMIT_2X; else @@ -224,7 +224,7 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) u32 dpfc_ctl; int threshold = dev_priv->fbc.threshold; - dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane); + dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane); if (params->fb.format->cpp[0] == 2) threshold++; @@ -306,7 +306,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) dpfc_ctl = 0; if (IS_IVYBRIDGE(dev_priv)) - dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane); + dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane); if (params->fb.format->cpp[0] == 2) threshold++; @@ -890,7 +890,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, params->vma = cache->vma; params->crtc.pipe = crtc->pipe; - params->crtc.plane = crtc->plane; + params->crtc.i9xx_plane = crtc->i9xx_plane; params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc); params->fb.format = cache->fb.format; @@ -1088,7 +1088,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) continue; - if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) + if (fbc_on_plane_a_only(dev_priv) && crtc->i9xx_plane != PLANE_A) continue; intel_crtc_state = to_intel_crtc_state( diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 5baa0023964e..dd485f59eb1d 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1384,7 +1384,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, } intel_plane->pipe = pipe; - intel_plane->plane = plane; + intel_plane->i9xx_plane = plane; intel_plane->id = PLANE_SPRITE0 + plane; intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); intel_plane->check_plane = intel_check_sprite_plane; -- GitLab From bdaf8439ba8176908b1b33e7db724f3de35ee0f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 17 Nov 2017 21:19:11 +0200 Subject: [PATCH 0057/2547] drm/i915: Use enum i9xx_plane_id for the .get_fifo_size() hooks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the 0 and 1 with PLANE_A and PLANE_B in the pre-g4x wm code. v2: s/old_plane_id/i9xx_plane_id/ (Daniel) v3: s/plane/i9xx_plane/ etc. (James) Cc: James Ausmus Cc: Daniel Vetter Reviewed-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171117191917.11506-5-ville.syrjala@linux.intel.com Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 3 ++- drivers/gpu/drm/i915/intel_pm.c | 36 +++++++++++++++++---------------- 2 files changed, 21 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d63a731ef60b..a1268d706c5e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -698,7 +698,8 @@ struct drm_i915_display_funcs { struct intel_cdclk_state *cdclk_state); void (*set_cdclk)(struct drm_i915_private *dev_priv, const struct intel_cdclk_state *cdclk_state); - int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane); + int (*get_fifo_size)(struct drm_i915_private *dev_priv, + enum i9xx_plane_id i9xx_plane); int (*compute_pipe_wm)(struct intel_crtc_state *cstate); int (*compute_intermediate_wm)(struct drm_device *dev, struct intel_crtc *intel_crtc, diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ce5cd75b8130..e445ec174831 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -512,38 +512,41 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) fifo_state->plane[PLANE_CURSOR] = 63; } -static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane) +static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, + enum i9xx_plane_id i9xx_plane) { uint32_t dsparb = I915_READ(DSPARB); int size; size = dsparb & 0x7f; - if (plane) + if (i9xx_plane == PLANE_B) size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; - DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, - plane ? "B" : "A", size); + DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n", + dsparb, plane_name(i9xx_plane), size); return size; } -static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane) +static int i830_get_fifo_size(struct drm_i915_private *dev_priv, + enum i9xx_plane_id i9xx_plane) { uint32_t dsparb = I915_READ(DSPARB); int size; size = dsparb & 0x1ff; - if (plane) + if (i9xx_plane == PLANE_B) size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; size >>= 1; /* Convert to cachelines */ - DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, - plane ? "B" : "A", size); + DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n", + dsparb, plane_name(i9xx_plane), size); return size; } -static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane) +static int i845_get_fifo_size(struct drm_i915_private *dev_priv, + enum i9xx_plane_id i9xx_plane) { uint32_t dsparb = I915_READ(DSPARB); int size; @@ -551,9 +554,8 @@ static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane) size = dsparb & 0x7f; size >>= 2; /* Convert to cachelines */ - DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, - plane ? "B" : "A", - size); + DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n", + dsparb, plane_name(i9xx_plane), size); return size; } @@ -2277,8 +2279,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) else wm_info = &i830_a_wm_info; - fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0); - crtc = intel_get_crtc_for_plane(dev_priv, 0); + fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A); + crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A); if (intel_crtc_active(crtc)) { const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; @@ -2304,8 +2306,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) if (IS_GEN2(dev_priv)) wm_info = &i830_bc_wm_info; - fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1); - crtc = intel_get_crtc_for_plane(dev_priv, 1); + fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B); + crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B); if (intel_crtc_active(crtc)) { const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; @@ -2417,7 +2419,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc) adjusted_mode = &crtc->config->base.adjusted_mode; planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, &i845_wm_info, - dev_priv->display.get_fifo_size(dev_priv, 0), + dev_priv->display.get_fifo_size(dev_priv, PLANE_A), 4, pessimal_latency_ns); fwater_lo = I915_READ(FW_BLC) & ~0xfff; fwater_lo |= (3<<8) | planea_wm; -- GitLab From 282e83ef6289542914697eae633444c7089d4479 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 17 Nov 2017 21:19:12 +0200 Subject: [PATCH 0058/2547] drm/i915: Cleanup enum pipe/enum plane_id/enum i9xx_plane_id in initial fb readout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use enum pipe, enum plane_id, and enum i9xx_plane_id consistently in the initial framebuffe readout. v2: Use old_plane_id in the ilk code v3: s/old_plane_id/i9xx_plane_id/ (Daniel) v4: Rebase due to GLK/CNL PLANE_COLOR_CTL alpha stuff v5: s/plane/i9xx_plane/ etc. (James) Cc: James Ausmus Cc: Daniel Vetter Reviewed-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171117191917.11506-6-ville.syrjala@linux.intel.com Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 60 +++++++++++++++------------- 1 file changed, 33 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 16ac86816f28..0c407cb0e6aa 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7404,14 +7404,16 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_plane *plane = to_intel_plane(crtc->base.primary); + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + enum pipe pipe = crtc->pipe; u32 val, base, offset; - int pipe = crtc->pipe, plane = crtc->i9xx_plane; int fourcc, pixel_format; unsigned int aligned_height; struct drm_framebuffer *fb; struct intel_framebuffer *intel_fb; - val = I915_READ(DSPCNTR(plane)); + val = I915_READ(DSPCNTR(i9xx_plane)); if (!(val & DISPLAY_PLANE_ENABLE)) return; @@ -7438,12 +7440,12 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, if (INTEL_GEN(dev_priv) >= 4) { if (plane_config->tiling) - offset = I915_READ(DSPTILEOFF(plane)); + offset = I915_READ(DSPTILEOFF(i9xx_plane)); else - offset = I915_READ(DSPLINOFF(plane)); - base = I915_READ(DSPSURF(plane)) & 0xfffff000; + offset = I915_READ(DSPLINOFF(i9xx_plane)); + base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; } else { - base = I915_READ(DSPADDR(plane)); + base = I915_READ(DSPADDR(i9xx_plane)); } plane_config->base = base; @@ -7451,15 +7453,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->width = ((val >> 16) & 0xfff) + 1; fb->height = ((val >> 0) & 0xfff) + 1; - val = I915_READ(DSPSTRIDE(pipe)); + val = I915_READ(DSPSTRIDE(i9xx_plane)); fb->pitches[0] = val & 0xffffffc0; aligned_height = intel_fb_align_height(fb, 0, fb->height); plane_config->size = fb->pitches[0] * aligned_height; - DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", - pipe_name(pipe), plane, fb->width, fb->height, + DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", + crtc->base.name, plane->base.name, fb->width, fb->height, fb->format->cpp[0] * 8, base, fb->pitches[0], plane_config->size); @@ -8428,8 +8430,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_plane *plane = to_intel_plane(crtc->base.primary); + enum plane_id plane_id = plane->id; + enum pipe pipe = crtc->pipe; u32 val, base, offset, stride_mult, tiling, alpha; - int pipe = crtc->pipe; int fourcc, pixel_format; unsigned int aligned_height; struct drm_framebuffer *fb; @@ -8445,14 +8449,14 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, fb->dev = dev; - val = I915_READ(PLANE_CTL(pipe, 0)); + val = I915_READ(PLANE_CTL(pipe, plane_id)); if (!(val & PLANE_CTL_ENABLE)) goto error; pixel_format = val & PLANE_CTL_FORMAT_MASK; if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { - alpha = I915_READ(PLANE_COLOR_CTL(pipe, 0)); + alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id)); alpha &= PLANE_COLOR_ALPHA_MASK; } else { alpha = val & PLANE_CTL_ALPHA_MASK; @@ -8488,16 +8492,16 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, goto error; } - base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; + base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000; plane_config->base = base; - offset = I915_READ(PLANE_OFFSET(pipe, 0)); + offset = I915_READ(PLANE_OFFSET(pipe, plane_id)); - val = I915_READ(PLANE_SIZE(pipe, 0)); + val = I915_READ(PLANE_SIZE(pipe, plane_id)); fb->height = ((val >> 16) & 0xfff) + 1; fb->width = ((val >> 0) & 0x1fff) + 1; - val = I915_READ(PLANE_STRIDE(pipe, 0)); + val = I915_READ(PLANE_STRIDE(pipe, plane_id)); stride_mult = intel_fb_stride_alignment(fb, 0); fb->pitches[0] = (val & 0x3ff) * stride_mult; @@ -8505,8 +8509,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, plane_config->size = fb->pitches[0] * aligned_height; - DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", - pipe_name(pipe), fb->width, fb->height, + DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", + crtc->base.name, plane->base.name, fb->width, fb->height, fb->format->cpp[0] * 8, base, fb->pitches[0], plane_config->size); @@ -8547,14 +8551,16 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_plane *plane = to_intel_plane(crtc->base.primary); + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + enum pipe pipe = crtc->pipe; u32 val, base, offset; - int pipe = crtc->pipe; int fourcc, pixel_format; unsigned int aligned_height; struct drm_framebuffer *fb; struct intel_framebuffer *intel_fb; - val = I915_READ(DSPCNTR(pipe)); + val = I915_READ(DSPCNTR(i9xx_plane)); if (!(val & DISPLAY_PLANE_ENABLE)) return; @@ -8579,14 +8585,14 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc, fourcc = i9xx_format_to_fourcc(pixel_format); fb->format = drm_format_info(fourcc); - base = I915_READ(DSPSURF(pipe)) & 0xfffff000; + base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - offset = I915_READ(DSPOFFSET(pipe)); + offset = I915_READ(DSPOFFSET(i9xx_plane)); } else { if (plane_config->tiling) - offset = I915_READ(DSPTILEOFF(pipe)); + offset = I915_READ(DSPTILEOFF(i9xx_plane)); else - offset = I915_READ(DSPLINOFF(pipe)); + offset = I915_READ(DSPLINOFF(i9xx_plane)); } plane_config->base = base; @@ -8594,15 +8600,15 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc, fb->width = ((val >> 16) & 0xfff) + 1; fb->height = ((val >> 0) & 0xfff) + 1; - val = I915_READ(DSPSTRIDE(pipe)); + val = I915_READ(DSPSTRIDE(i9xx_plane)); fb->pitches[0] = val & 0xffffffc0; aligned_height = intel_fb_align_height(fb, 0, fb->height); plane_config->size = fb->pitches[0] * aligned_height; - DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", - pipe_name(pipe), fb->width, fb->height, + DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", + crtc->base.name, plane->base.name, fb->width, fb->height, fb->format->cpp[0] * 8, base, fb->pitches[0], plane_config->size); -- GitLab From 81894b2fb9285f21dc2ca5f4c1ab0c9197d48607 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 17 Nov 2017 21:19:13 +0200 Subject: [PATCH 0059/2547] drm/i915: Nuke ironlake_get_initial_plane_config() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The only relevant difference between i9xx_get_initial_plane_config() and ironlake_get_initial_plane_config() is the HSW/BDW TILEOFF handling. Add that to i9xx_get_initial_plane_config() and nuke ironlake_get_initial_plane_config(). v2: s/plane/i9xx_plane/ etc. (James) Cc: James Ausmus Reviewed-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171117191917.11506-7-ville.syrjala@linux.intel.com Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 79 +++------------------------- 1 file changed, 6 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0c407cb0e6aa..c1d7547c1457 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7438,7 +7438,10 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fourcc = i9xx_format_to_fourcc(pixel_format); fb->format = drm_format_info(fourcc); - if (INTEL_GEN(dev_priv) >= 4) { + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { + offset = I915_READ(DSPOFFSET(i9xx_plane)); + base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; + } else if (INTEL_GEN(dev_priv) >= 4) { if (plane_config->tiling) offset = I915_READ(DSPTILEOFF(i9xx_plane)); else @@ -8545,76 +8548,6 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc, } } -static void -ironlake_get_initial_plane_config(struct intel_crtc *crtc, - struct intel_initial_plane_config *plane_config) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_plane *plane = to_intel_plane(crtc->base.primary); - enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - enum pipe pipe = crtc->pipe; - u32 val, base, offset; - int fourcc, pixel_format; - unsigned int aligned_height; - struct drm_framebuffer *fb; - struct intel_framebuffer *intel_fb; - - val = I915_READ(DSPCNTR(i9xx_plane)); - if (!(val & DISPLAY_PLANE_ENABLE)) - return; - - intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); - if (!intel_fb) { - DRM_DEBUG_KMS("failed to alloc fb\n"); - return; - } - - fb = &intel_fb->base; - - fb->dev = dev; - - if (INTEL_GEN(dev_priv) >= 4) { - if (val & DISPPLANE_TILED) { - plane_config->tiling = I915_TILING_X; - fb->modifier = I915_FORMAT_MOD_X_TILED; - } - } - - pixel_format = val & DISPPLANE_PIXFORMAT_MASK; - fourcc = i9xx_format_to_fourcc(pixel_format); - fb->format = drm_format_info(fourcc); - - base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - offset = I915_READ(DSPOFFSET(i9xx_plane)); - } else { - if (plane_config->tiling) - offset = I915_READ(DSPTILEOFF(i9xx_plane)); - else - offset = I915_READ(DSPLINOFF(i9xx_plane)); - } - plane_config->base = base; - - val = I915_READ(PIPESRC(pipe)); - fb->width = ((val >> 16) & 0xfff) + 1; - fb->height = ((val >> 0) & 0xfff) + 1; - - val = I915_READ(DSPSTRIDE(i9xx_plane)); - fb->pitches[0] = val & 0xffffffc0; - - aligned_height = intel_fb_align_height(fb, 0, fb->height); - - plane_config->size = fb->pitches[0] * aligned_height; - - DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", - crtc->base.name, plane->base.name, fb->width, fb->height, - fb->format->cpp[0] * 8, base, fb->pitches[0], - plane_config->size); - - plane_config->fb = intel_fb; -} - static bool ironlake_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { @@ -14217,7 +14150,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) } else if (HAS_DDI(dev_priv)) { dev_priv->display.get_pipe_config = haswell_get_pipe_config; dev_priv->display.get_initial_plane_config = - ironlake_get_initial_plane_config; + i9xx_get_initial_plane_config; dev_priv->display.crtc_compute_clock = haswell_crtc_compute_clock; dev_priv->display.crtc_enable = haswell_crtc_enable; @@ -14225,7 +14158,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) } else if (HAS_PCH_SPLIT(dev_priv)) { dev_priv->display.get_pipe_config = ironlake_get_pipe_config; dev_priv->display.get_initial_plane_config = - ironlake_get_initial_plane_config; + i9xx_get_initial_plane_config; dev_priv->display.crtc_compute_clock = ironlake_crtc_compute_clock; dev_priv->display.crtc_enable = ironlake_crtc_enable; -- GitLab From dd57602efbce0d4f39770ec253fe6f95a6f0791f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 17 Nov 2017 21:19:14 +0200 Subject: [PATCH 0060/2547] drm/i915: Switch fbc over to for_each_new_intel_plane_in_state() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Stop using the old for_each_intel_plane_in_state() type iteration macro and replace it with for_each_new_intel_plane_in_state(). And similarly replace drm_atomic_get_existing_crtc_state() with intel_atomic_get_new_crtc_state(). Switch over to intel_ types as well to make the code less cluttered. v2: s/plane/i9xx_plane/ etc. (James) Cc: James Ausmus Cc: Maarten Lankhorst Reviewed-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171117191917.11506-8-ville.syrjala@linux.intel.com Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 7 +++---- drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_fbc.c | 23 ++++++++++------------- 4 files changed, 15 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a1268d706c5e..9a890f6ad2df 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -560,13 +560,13 @@ struct i915_hotplug { for_each_power_well_rev(__dev_priv, __power_well) \ for_each_if ((__power_well)->domains & (__domain_mask)) -#define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \ +#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ for ((__i) = 0; \ (__i) < (__state)->base.dev->mode_config.num_total_plane && \ ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ - (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \ + (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ (__i)++) \ - for_each_if (plane_state) + for_each_if (plane) #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ for ((__i) = 0; \ @@ -576,7 +576,6 @@ struct i915_hotplug { (__i)++) \ for_each_if (crtc) - #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ for ((__i) = 0; \ (__i) < (__state)->base.dev->mode_config.num_total_plane && \ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c1d7547c1457..b1ead3f95cde 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12080,7 +12080,7 @@ static int intel_atomic_check(struct drm_device *dev, if (ret) return ret; - intel_fbc_choose_crtc(dev_priv, state); + intel_fbc_choose_crtc(dev_priv, intel_state); return calc_watermark_data(state); } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d1fe7be94b62..3ebe62666108 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1652,7 +1652,7 @@ static inline void intel_fbdev_restore_mode(struct drm_device *dev) /* intel_fbc.c */ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, - struct drm_atomic_state *state); + struct intel_atomic_state *state); bool intel_fbc_is_active(struct drm_i915_private *dev_priv); void intel_fbc_pre_update(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 3133131306a9..474234322b8b 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -1054,11 +1054,11 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv, * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc. */ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, - struct drm_atomic_state *state) + struct intel_atomic_state *state) { struct intel_fbc *fbc = &dev_priv->fbc; - struct drm_plane *plane; - struct drm_plane_state *plane_state; + struct intel_plane *plane; + struct intel_plane_state *plane_state; bool crtc_chosen = false; int i; @@ -1066,7 +1066,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, /* Does this atomic commit involve the CRTC currently tied to FBC? */ if (fbc->crtc && - !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base)) + !intel_atomic_get_new_crtc_state(state, fbc->crtc)) goto out; if (!intel_fbc_can_enable(dev_priv)) @@ -1076,13 +1076,11 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, * plane. We could go for fancier schemes such as checking the plane * size, but this would just affect the few platforms that don't tie FBC * to pipe or plane A. */ - for_each_new_plane_in_state(state, plane, plane_state, i) { - struct intel_plane_state *intel_plane_state = - to_intel_plane_state(plane_state); - struct intel_crtc_state *intel_crtc_state; - struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc); + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + struct intel_crtc_state *crtc_state; + struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc); - if (!intel_plane_state->base.visible) + if (!plane_state->base.visible) continue; if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) @@ -1091,10 +1089,9 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, if (fbc_on_plane_a_only(dev_priv) && crtc->i9xx_plane != PLANE_A) continue; - intel_crtc_state = to_intel_crtc_state( - drm_atomic_get_existing_crtc_state(state, &crtc->base)); + crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - intel_crtc_state->enable_fbc = true; + crtc_state->enable_fbc = true; crtc_chosen = true; break; } -- GitLab From b1558c7ea16038f3c3dcc40dd5c1cf7ad6004ada Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 17 Nov 2017 21:19:15 +0200 Subject: [PATCH 0061/2547] drm/i915: Nuke crtc->plane MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Eliminate crtc->plane since it's pretty much a layering violation. We can always get the plane via crtc->primary if we actually need it. The only ugly thing left is plane_to_crtc_mapping[], but that's still needed by the pre-g4x watermark code. v2: Removed a misplaced comment change (Daniel) v3: Rebase due to fbc crtc->y usage removal v4: s/plane/i9xx_plane/ etc. (James) Cc: James Ausmus Cc: Daniel Vetter Reviewed-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171117191917.11506-9-ville.syrjala@linux.intel.com Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 5 ++--- drivers/gpu/drm/i915/intel_drv.h | 1 - drivers/gpu/drm/i915/intel_fbc.c | 4 ++-- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b1ead3f95cde..62cc2a600205 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13463,14 +13463,13 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) goto fail; intel_crtc->pipe = pipe; - intel_crtc->i9xx_plane = primary->i9xx_plane; /* initialize shared scalers */ intel_crtc_init_scalers(intel_crtc, crtc_state); BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || - dev_priv->plane_to_crtc_mapping[intel_crtc->i9xx_plane] != NULL); - dev_priv->plane_to_crtc_mapping[intel_crtc->i9xx_plane] = intel_crtc; + dev_priv->plane_to_crtc_mapping[primary->i9xx_plane] != NULL); + dev_priv->plane_to_crtc_mapping[primary->i9xx_plane] = intel_crtc; dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 3ebe62666108..635a96fcd788 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -799,7 +799,6 @@ struct intel_crtc_state { struct intel_crtc { struct drm_crtc base; enum pipe pipe; - enum i9xx_plane_id i9xx_plane; /* * Whether the crtc and the connected output pipeline is active. Implies * that crtc->enabled is set, i.e. the current mode configuration has diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 474234322b8b..4aefc658a5cf 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -890,7 +890,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, params->vma = cache->vma; params->crtc.pipe = crtc->pipe; - params->crtc.i9xx_plane = crtc->i9xx_plane; + params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane; params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc); params->fb.format = cache->fb.format; @@ -1086,7 +1086,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) continue; - if (fbc_on_plane_a_only(dev_priv) && crtc->i9xx_plane != PLANE_A) + if (fbc_on_plane_a_only(dev_priv) && plane->i9xx_plane != PLANE_A) continue; crtc_state = intel_atomic_get_new_crtc_state(state, crtc); -- GitLab From 2924b8cc415a950687a890cb6dea8dbc0e930447 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 17 Nov 2017 21:19:16 +0200 Subject: [PATCH 0062/2547] drm/i915: Use plane->get_hw_state() for initial plane fb readout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since we now have a ->get_hw_state() method for planes, let's use that during the initial plane fb readout. v2: s/plane/i9xx_plane/ etc. (James) Cc: James Ausmus Cc: Daniel Vetter Suggested-by: Daniel Vetter Reviewed-by: James Ausmus Link: https://patchwork.freedesktop.org/patch/msgid/20171117191917.11506-10-ville.syrjala@linux.intel.com Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 62cc2a600205..ed58311e8da0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7413,8 +7413,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, struct drm_framebuffer *fb; struct intel_framebuffer *intel_fb; - val = I915_READ(DSPCNTR(i9xx_plane)); - if (!(val & DISPLAY_PLANE_ENABLE)) + if (!plane->get_hw_state(plane)) return; intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); @@ -7427,6 +7426,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->dev = dev; + val = I915_READ(DSPCNTR(i9xx_plane)); + if (INTEL_GEN(dev_priv) >= 4) { if (val & DISPPLANE_TILED) { plane_config->tiling = I915_TILING_X; @@ -8442,6 +8443,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, struct drm_framebuffer *fb; struct intel_framebuffer *intel_fb; + if (!plane->get_hw_state(plane)) + return; + intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); if (!intel_fb) { DRM_DEBUG_KMS("failed to alloc fb\n"); @@ -8453,8 +8457,6 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, fb->dev = dev; val = I915_READ(PLANE_CTL(pipe, plane_id)); - if (!(val & PLANE_CTL_ENABLE)) - goto error; pixel_format = val & PLANE_CTL_FORMAT_MASK; -- GitLab From cff109f06dfebc379a5a36d49b541212caaec607 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 17 Nov 2017 21:19:17 +0200 Subject: [PATCH 0063/2547] drm/i915: Add rudimentary plane state verification MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Check that the planes are in the state we expect them to be. For now we can only check whether each plane is correctly enabled or disabled. In the future we may want to expand the plane state readout to support a more thorough verification. v2: Verify all planes part of the state as long as at least one crtc is doing a modeset (Daniel) v3: Fix typoes (James) Cc: James Ausmus Cc: Daniel Vetter Suggested-by: Daniel Vetter Reviewed-by: James Ausmus Link: https://patchwork.freedesktop.org/patch/msgid/20171117191917.11506-11-ville.syrjala@linux.intel.com Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ed58311e8da0..5ca7b33554ef 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11600,6 +11600,18 @@ verify_crtc_state(struct drm_crtc *crtc, } } +static void +intel_verify_planes(struct intel_atomic_state *state) +{ + struct intel_plane *plane; + const struct intel_plane_state *plane_state; + int i; + + for_each_new_intel_plane_in_state(state, plane, + plane_state, i) + assert_plane(plane, plane_state->base.visible); +} + static void verify_single_dpll_state(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll, @@ -12393,6 +12405,9 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); } + if (intel_state->modeset) + intel_verify_planes(intel_state); + if (intel_state->modeset && intel_can_enable_sagv(state)) intel_enable_sagv(dev_priv); -- GitLab From 542134c0375b5ca2b1d18490c02b8a20bfdd8d74 Mon Sep 17 00:00:00 2001 From: Eudean Sun Date: Tue, 21 Nov 2017 10:43:24 -0800 Subject: [PATCH 0064/2547] HID: cp2112: Fix I2C_BLOCK_DATA transactions The existing driver erroneously treats I2C_BLOCK_DATA and BLOCK_DATA commands the same. For I2C_BLOCK_DATA reads, the length of the read is provided in data->block[0], but the length itself should not be sent to the slave. In contrast, for BLOCK_DATA reads no length is specified since the length will be the first byte returned from the slave. When copying data back to the data buffer, for an I2C_BLOCK_DATA read we have to take care not to overwrite data->block[0] to avoid overwriting the length. A BLOCK_DATA read doesn't have this concern since the first byte returned by the device is the length and belongs in data->block[0]. For I2C_BLOCK_DATA writes, the length is also provided in data->block[0], but the length itself is not sent to the slave (in contrast to BLOCK_DATA writes where the length prefixes the data sent to the slave). This was tested on physical hardware using i2cdump with the i and s flags to test the behavior of I2C_BLOCK_DATA reads and BLOCK_DATA reads, respectively. Writes were not tested but the I2C_BLOCK_DATA write change is pretty simple to verify by inspection. Signed-off-by: Eudean Sun Signed-off-by: Jiri Kosina --- drivers/hid/hid-cp2112.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/hid/hid-cp2112.c b/drivers/hid/hid-cp2112.c index 68cdc962265b..271f31461da4 100644 --- a/drivers/hid/hid-cp2112.c +++ b/drivers/hid/hid-cp2112.c @@ -696,8 +696,16 @@ static int cp2112_xfer(struct i2c_adapter *adap, u16 addr, (u8 *)&word, 2); break; case I2C_SMBUS_I2C_BLOCK_DATA: - size = I2C_SMBUS_BLOCK_DATA; - /* fallthrough */ + if (read_write == I2C_SMBUS_READ) { + read_length = data->block[0]; + count = cp2112_write_read_req(buf, addr, read_length, + command, NULL, 0); + } else { + count = cp2112_write_req(buf, addr, command, + data->block + 1, + data->block[0]); + } + break; case I2C_SMBUS_BLOCK_DATA: if (I2C_SMBUS_READ == read_write) { count = cp2112_write_read_req(buf, addr, @@ -785,6 +793,9 @@ static int cp2112_xfer(struct i2c_adapter *adap, u16 addr, case I2C_SMBUS_WORD_DATA: data->word = le16_to_cpup((__le16 *)buf); break; + case I2C_SMBUS_I2C_BLOCK_DATA: + memcpy(data->block + 1, buf, read_length); + break; case I2C_SMBUS_BLOCK_DATA: if (read_length > I2C_SMBUS_BLOCK_MAX) { ret = -EPROTO; -- GitLab From f9eb63b98c91f4cfaddf54b769f971c77da10917 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 21 Nov 2017 11:06:52 +0000 Subject: [PATCH 0065/2547] drm/i915/selftests: Avoid drm_gem_handle_create under struct_mutex Despite us reloading the module around every selftest, the lockclasses persist and the chains used in selftesting may then dictate how we are allowed to nest locks during runtime testing. As such we have to be just as careful, and in particular it turns out we are not allowed to nest dev->object_name_lock (drm_gem_handle_create) inside dev->struct_mutex. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103830 Signed-off-by: Chris Wilson Cc: Matthew Auld Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20171121110652.1107-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- .../gpu/drm/i915/selftests/i915_gem_context.c | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index 09340b3c1156..ec1eff739e01 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -264,6 +264,23 @@ static int cpu_check(struct drm_i915_gem_object *obj, unsigned int max) return err; } +static int file_add_object(struct drm_file *file, + struct drm_i915_gem_object *obj) +{ + int err; + + GEM_BUG_ON(obj->base.handle_count); + + /* tie the object to the drm_file for easy reaping */ + err = idr_alloc(&file->object_idr, &obj->base, 1, 0, GFP_KERNEL); + if (err < 0) + return err; + + i915_gem_object_get(obj); + obj->base.handle_count++; + return 0; +} + static struct drm_i915_gem_object * create_test_object(struct i915_gem_context *ctx, struct drm_file *file, @@ -273,7 +290,6 @@ create_test_object(struct i915_gem_context *ctx, struct i915_address_space *vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base; u64 size; - u32 handle; int err; size = min(vm->total / 2, 1024ull * DW_PER_PAGE * PAGE_SIZE); @@ -283,8 +299,7 @@ create_test_object(struct i915_gem_context *ctx, if (IS_ERR(obj)) return obj; - /* tie the handle to the drm_file for easy reaping */ - err = drm_gem_handle_create(file, &obj->base, &handle); + err = file_add_object(file, obj); i915_gem_object_put(obj); if (err) return ERR_PTR(err); -- GitLab From 727535903bea924c4f73abb202c4b3e85fff0ca4 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Mon, 20 Nov 2017 08:12:29 -0600 Subject: [PATCH 0066/2547] scsi: ufs: ufshcd: fix potential NULL pointer dereference in ufshcd_config_vreg _vreg_ is being dereferenced before it is null checked, hence there is a potential null pointer dereference. Fix this by moving the pointer dereference after _vreg_ has been null checked. This issue was detected with the help of Coccinelle. Fixes: aa4976130934 ("ufs: Add regulator enable support") Signed-off-by: Gustavo A. R. Silva Reviewed-by: Subhash Jadavani Signed-off-by: Martin K. Petersen --- drivers/scsi/ufs/ufshcd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 011c3369082c..a355d989b414 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -6559,12 +6559,15 @@ static int ufshcd_config_vreg(struct device *dev, struct ufs_vreg *vreg, bool on) { int ret = 0; - struct regulator *reg = vreg->reg; - const char *name = vreg->name; + struct regulator *reg; + const char *name; int min_uV, uA_load; BUG_ON(!vreg); + reg = vreg->reg; + name = vreg->name; + if (regulator_count_voltages(reg) > 0) { min_uV = on ? vreg->min_uV : 0; ret = regulator_set_voltage(reg, min_uV, vreg->max_uV); -- GitLab From 860dd4424f344400b491b212ee4acb3a358ba9d9 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 21 Nov 2017 14:23:37 +0100 Subject: [PATCH 0067/2547] scsi: dma-mapping: always provide dma_get_cache_alignment Provide the dummy version of dma_get_cache_alignment that always returns 1 even if CONFIG_HAS_DMA is not set, so that drivers and subsystems can use it without ifdefs. Cc: stable@vger.kernel.org Signed-off-by: Christoph Hellwig Signed-off-by: Martin K. Petersen --- include/linux/dma-mapping.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index eee1499db396..29cfd18360be 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -710,7 +710,6 @@ static inline void *dma_zalloc_coherent(struct device *dev, size_t size, return ret; } -#ifdef CONFIG_HAS_DMA static inline int dma_get_cache_alignment(void) { #ifdef ARCH_DMA_MINALIGN @@ -718,7 +717,6 @@ static inline int dma_get_cache_alignment(void) #endif return 1; } -#endif /* flags for the coherent memory api */ #define DMA_MEMORY_EXCLUSIVE 0x01 -- GitLab From 90addc6b3c9cda0146fbd62a08e234c2b224a80c Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Tue, 21 Nov 2017 14:23:38 +0100 Subject: [PATCH 0068/2547] scsi: use dma_get_cache_alignment() as minimum DMA alignment In non-coherent DMA mode, kernel uses cache flushing operations to maintain I/O coherency, so scsi's block queue should be aligned to the value returned by dma_get_cache_alignment(). Otherwise, If a DMA buffer and a kernel structure share a same cache line, and if the kernel structure has dirty data, cache_invalidate (no writeback) will cause data corruption. Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen [hch: rebased and updated the comment and changelog] Signed-off-by: Christoph Hellwig Signed-off-by: Martin K. Petersen --- drivers/scsi/scsi_lib.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c index 1cbc497e00bd..00742c50cd44 100644 --- a/drivers/scsi/scsi_lib.c +++ b/drivers/scsi/scsi_lib.c @@ -2148,11 +2148,13 @@ void __scsi_init_queue(struct Scsi_Host *shost, struct request_queue *q) q->limits.cluster = 0; /* - * set a reasonable default alignment on word boundaries: the - * host and device may alter it using - * blk_queue_update_dma_alignment() later. + * Set a reasonable default alignment: The larger of 32-byte (dword), + * which is a common minimum for HBAs, and the minimum DMA alignment, + * which is set by the platform. + * + * Devices that require a bigger alignment can increase it later. */ - blk_queue_dma_alignment(q, 0x03); + blk_queue_dma_alignment(q, max(4, dma_get_cache_alignment()) - 1); } EXPORT_SYMBOL_GPL(__scsi_init_queue); -- GitLab From c2e8fbf908afd81ad502b567a6639598f92c9b9d Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Tue, 21 Nov 2017 14:23:39 +0100 Subject: [PATCH 0069/2547] scsi: libsas: align sata_device's rps_resp on a cacheline The rps_resp buffer in ata_device is a DMA target, but it isn't explicitly cacheline aligned. Due to this, adjacent fields can be overwritten with stale data from memory on non-coherent architectures. As a result, the kernel is sometimes unable to communicate with an SATA device behind a SAS expander. Fix this by ensuring that the rps_resp buffer is cacheline aligned. This issue is similar to that fixed by Commit 84bda12af31f93 ("libata: align ap->sector_buf") and Commit 4ee34ea3a12396f35b26 ("libata: Align ata_device's id on a cacheline"). Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen Signed-off-by: Christoph Hellwig Signed-off-by: Martin K. Petersen --- include/scsi/libsas.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/scsi/libsas.h b/include/scsi/libsas.h index 0f9cbf96c093..6df6fe0c2198 100644 --- a/include/scsi/libsas.h +++ b/include/scsi/libsas.h @@ -159,11 +159,11 @@ struct expander_device { struct sata_device { unsigned int class; - struct smp_resp rps_resp; /* report_phy_sata_resp */ u8 port_no; /* port number, if this is a PM (Port) */ struct ata_port *ap; struct ata_host ata_host; + struct smp_resp rps_resp ____cacheline_aligned; /* report_phy_sata_resp */ u8 fis[ATA_RESP_FIS_SIZE]; }; -- GitLab From c84b27054643db73e56a5e933191bda435b6c46e Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 21 Nov 2017 18:18:44 +0000 Subject: [PATCH 0070/2547] drm/i915: Extract intel_get_cagf Code to be shared between debugfs and the PMU implementation. v2: Checkpatch cleanup. v3: Also consolidate i915_sysfs.c/gt_act_freq_mhz_show. v4: Rebase. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 9 ++------- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_sysfs.c | 11 +++-------- drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++++++++ 4 files changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 41d49a4d25d3..28294470ae31 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1151,13 +1151,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused) rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; - if (INTEL_GEN(dev_priv) >= 9) - cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; - else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; - else - cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; - cagf = intel_gpu_freq(dev_priv, cagf); + cagf = intel_gpu_freq(dev_priv, + intel_get_cagf(dev_priv, rpstat)); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9a890f6ad2df..019117144b3b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -4226,6 +4226,8 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, const i915_reg_t reg); +u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1); + #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 791759f632e1..450ac7d343ad 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -252,14 +252,9 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev, freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff); } else { - u32 rpstat = I915_READ(GEN6_RPSTAT1); - if (INTEL_GEN(dev_priv) >= 9) - ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; - else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; - else - ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; - ret = intel_gpu_freq(dev_priv, ret); + ret = intel_gpu_freq(dev_priv, + intel_get_cagf(dev_priv, + I915_READ(GEN6_RPSTAT1))); } mutex_unlock(&dev_priv->pcu_lock); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e445ec174831..f1dc36c1fd69 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -9468,3 +9468,17 @@ u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, intel_runtime_pm_put(dev_priv); return DIV_ROUND_UP_ULL(time_hw * units, div); } + +u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat) +{ + u32 cagf; + + if (INTEL_GEN(dev_priv) >= 9) + cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; + else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) + cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; + else + cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; + + return cagf; +} -- GitLab From b46a33e271ed81bd765c632b972c49d5b44729c7 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 21 Nov 2017 18:18:45 +0000 Subject: [PATCH 0071/2547] drm/i915/pmu: Expose a PMU interface for perf queries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Chris Wilson From: Tvrtko Ursulin From: Dmitry Rogozhkin The first goal is to be able to measure GPU (and invidual ring) busyness without having to poll registers from userspace. (Which not only incurs holding the forcewake lock indefinitely, perturbing the system, but also runs the risk of hanging the machine.) As an alternative we can use the perf event counter interface to sample the ring registers periodically and send those results to userspace. Functionality we are exporting to userspace is via the existing perf PMU API and can be exercised via the existing tools. For example: perf stat -a -e i915/rcs0-busy/ -I 1000 Will print the render engine busynnes once per second. All the performance counters can be enumerated (perf list) and have their unit of measure correctly reported in sysfs. v1-v2 (Chris Wilson): v2: Use a common timer for the ring sampling. v3: (Tvrtko Ursulin) * Decouple uAPI from i915 engine ids. * Complete uAPI defines. * Refactor some code to helpers for clarity. * Skip sampling disabled engines. * Expose counters in sysfs. * Pass in fake regs to avoid null ptr deref in perf core. * Convert to class/instance uAPI. * Use shared driver code for rc6 residency, power and frequency. v4: (Dmitry Rogozhkin) * Register PMU with .task_ctx_nr=perf_invalid_context * Expose cpumask for the PMU with the single CPU in the mask * Properly support pmu->stop(): it should call pmu->read() * Properly support pmu->del(): it should call stop(event, PERF_EF_UPDATE) * Introduce refcounting of event subscriptions. * Make pmu.busy_stats a refcounter to avoid busy stats going away with some deleted event. * Expose cpumask for i915 PMU to avoid multiple events creation of the same type followed by counter aggregation by perf-stat. * Track CPUs getting online/offline to migrate perf context. If (likely) cpumask will initially set CPU0, CONFIG_BOOTPARAM_HOTPLUG_CPU0 will be needed to see effect of CPU status tracking. * End result is that only global events are supported and perf stat works correctly. * Deny perf driver level sampling - it is prohibited for uncore PMU. v5: (Tvrtko Ursulin) * Don't hardcode number of engine samplers. * Rewrite event ref-counting for correctness and simplicity. * Store initial counter value when starting already enabled events to correctly report values to all listeners. * Fix RC6 residency readout. * Comments, GPL header. v6: * Add missing entry to v4 changelog. * Fix accounting in CPU hotplug case by copying the approach from arch/x86/events/intel/cstate.c. (Dmitry Rogozhkin) v7: * Log failure message only on failure. * Remove CPU hotplug notification state on unregister. v8: * Fix error unwind on failed registration. * Checkpatch cleanup. v9: * Drop the energy metric, it is available via intel_rapl_perf. (Ville Syrjälä) * Use HAS_RC6(p). (Chris Wilson) * Handle unsupported non-engine events. (Dmitry Rogozhkin) * Rebase for intel_rc6_residency_ns needing caller managed runtime pm. * Drop HAS_RC6 checks from the read callback since creating those events will be rejected at init time already. * Add counter units to sysfs so perf stat output is nicer. * Cleanup the attribute tables for brevity and readability. v10: * Fixed queued accounting. v11: * Move intel_engine_lookup_user to intel_engine_cs.c * Commit update. (Joonas Lahtinen) v12: * More accurate sampling. (Chris Wilson) * Store and report frequency in MHz for better usability from perf stat. * Removed metrics: queued, interrupts, rc6 counters. * Sample engine busyness based on seqno difference only for less MMIO (and forcewake) on all platforms. (Chris Wilson) v13: * Comment spelling, use mul_u32_u32 to work around potential GCC issue and somne code alignment changes. (Chris Wilson) v14: * Rebase. v15: * Rebase for RPS refactoring. v16: * Use the dynamic slot in the CPU hotplug state machine so that we are free to setup our state as multi-instance. Previously we were re-using the CPUHP_AP_PERF_X86_UNCORE_ONLINE slot which is neither used as multi-instance, nor owned by our driver to start with. * Register the CPU hotplug handlers after the PMU, otherwise the callback will get called before the PMU is initialized which can end up in perf_pmu_migrate_context with an un-initialized base. * Added workaround for a probable bug in cpuhp core. v17: * Remove workaround for the cpuhp bug. v18: * Rebase for drm_i915_gem_engine_class getting upstream before us. v19: * Rebase. (trivial) Signed-off-by: Chris Wilson Signed-off-by: Tvrtko Ursulin Signed-off-by: Dmitry Rogozhkin Cc: Tvrtko Ursulin Cc: Chris Wilson Cc: Dmitry Rogozhkin Cc: Peter Zijlstra Reviewed-by: Chris Wilson Signed-off-by: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-2-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_drv.c | 3 + drivers/gpu/drm/i915/i915_drv.h | 5 + drivers/gpu/drm/i915/i915_pmu.c | 688 ++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_pmu.h | 104 ++++ drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_engine_cs.c | 33 ++ drivers/gpu/drm/i915/intel_ringbuffer.h | 26 + include/uapi/drm/i915_drm.h | 39 ++ 9 files changed, 902 insertions(+) create mode 100644 drivers/gpu/drm/i915/i915_pmu.c create mode 100644 drivers/gpu/drm/i915/i915_pmu.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index c3649ec5b041..42bc8bd4ff06 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -45,6 +45,7 @@ i915-y := i915_drv.o \ i915-$(CONFIG_COMPAT) += i915_ioc32.o i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o +i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o # GEM code i915-y += i915_cmd_parser.o \ diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 8dbcb03b5f54..0793a27e2b95 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -48,6 +48,7 @@ #include "i915_drv.h" #include "i915_trace.h" +#include "i915_pmu.h" #include "i915_vgpu.h" #include "intel_drv.h" #include "intel_uc.h" @@ -1215,6 +1216,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) struct drm_device *dev = &dev_priv->drm; i915_gem_shrinker_init(dev_priv); + i915_pmu_register(dev_priv); /* * Notify a valid surface after modesetting, @@ -1269,6 +1271,7 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) intel_opregion_unregister(dev_priv); i915_perf_unregister(dev_priv); + i915_pmu_unregister(dev_priv); i915_teardown_sysfs(dev_priv); i915_guc_log_unregister(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 019117144b3b..5bd5ac4cd03e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -2290,6 +2291,8 @@ struct drm_i915_private { struct i915_gem_context *kernel_context; /* Context only to be used for injecting preemption commands */ struct i915_gem_context *preempt_context; + struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1] + [MAX_ENGINE_INSTANCE + 1]; struct drm_dma_handle *status_page_dmah; struct resource mch_res; @@ -2761,6 +2764,8 @@ struct drm_i915_private { int irq; } lpe_audio; + struct i915_pmu pmu; + /* * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch * will be rejected. Instead look for a better place. diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c new file mode 100644 index 000000000000..01b5ee67c1bf --- /dev/null +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -0,0 +1,688 @@ +/* + * Copyright © 2017 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include +#include + +#include "i915_drv.h" +#include "i915_pmu.h" +#include "intel_ringbuffer.h" + +/* Frequency for the sampling timer for events which need it. */ +#define FREQUENCY 200 +#define PERIOD max_t(u64, 10000, NSEC_PER_SEC / FREQUENCY) + +#define ENGINE_SAMPLE_MASK \ + (BIT(I915_SAMPLE_BUSY) | \ + BIT(I915_SAMPLE_WAIT) | \ + BIT(I915_SAMPLE_SEMA)) + +#define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS) + +static cpumask_t i915_pmu_cpumask = CPU_MASK_NONE; + +static u8 engine_config_sample(u64 config) +{ + return config & I915_PMU_SAMPLE_MASK; +} + +static u8 engine_event_sample(struct perf_event *event) +{ + return engine_config_sample(event->attr.config); +} + +static u8 engine_event_class(struct perf_event *event) +{ + return (event->attr.config >> I915_PMU_CLASS_SHIFT) & 0xff; +} + +static u8 engine_event_instance(struct perf_event *event) +{ + return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff; +} + +static bool is_engine_config(u64 config) +{ + return config < __I915_PMU_OTHER(0); +} + +static unsigned int config_enabled_bit(u64 config) +{ + if (is_engine_config(config)) + return engine_config_sample(config); + else + return ENGINE_SAMPLE_BITS + (config - __I915_PMU_OTHER(0)); +} + +static u64 config_enabled_mask(u64 config) +{ + return BIT_ULL(config_enabled_bit(config)); +} + +static bool is_engine_event(struct perf_event *event) +{ + return is_engine_config(event->attr.config); +} + +static unsigned int event_enabled_bit(struct perf_event *event) +{ + return config_enabled_bit(event->attr.config); +} + +static bool grab_forcewake(struct drm_i915_private *i915, bool fw) +{ + if (!fw) + intel_uncore_forcewake_get(i915, FORCEWAKE_ALL); + + return true; +} + +static void +update_sample(struct i915_pmu_sample *sample, u32 unit, u32 val) +{ + /* + * Since we are doing stochastic sampling for these counters, + * average the delta with the previous value for better accuracy. + */ + sample->cur += div_u64(mul_u32_u32(sample->prev + val, unit), 2); + sample->prev = val; +} + +static void engines_sample(struct drm_i915_private *dev_priv) +{ + struct intel_engine_cs *engine; + enum intel_engine_id id; + bool fw = false; + + if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0) + return; + + if (!dev_priv->gt.awake) + return; + + if (!intel_runtime_pm_get_if_in_use(dev_priv)) + return; + + for_each_engine(engine, dev_priv, id) { + u32 current_seqno = intel_engine_get_seqno(engine); + u32 last_seqno = intel_engine_last_submit(engine); + u32 val; + + val = !i915_seqno_passed(current_seqno, last_seqno); + + update_sample(&engine->pmu.sample[I915_SAMPLE_BUSY], + PERIOD, val); + + if (val && (engine->pmu.enable & + (BIT(I915_SAMPLE_WAIT) | BIT(I915_SAMPLE_SEMA)))) { + fw = grab_forcewake(dev_priv, fw); + + val = I915_READ_FW(RING_CTL(engine->mmio_base)); + } else { + val = 0; + } + + update_sample(&engine->pmu.sample[I915_SAMPLE_WAIT], + PERIOD, !!(val & RING_WAIT)); + + update_sample(&engine->pmu.sample[I915_SAMPLE_SEMA], + PERIOD, !!(val & RING_WAIT_SEMAPHORE)); + } + + if (fw) + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + + intel_runtime_pm_put(dev_priv); +} + +static void frequency_sample(struct drm_i915_private *dev_priv) +{ + if (dev_priv->pmu.enable & + config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY)) { + u32 val; + + val = dev_priv->gt_pm.rps.cur_freq; + if (dev_priv->gt.awake && + intel_runtime_pm_get_if_in_use(dev_priv)) { + val = intel_get_cagf(dev_priv, + I915_READ_NOTRACE(GEN6_RPSTAT1)); + intel_runtime_pm_put(dev_priv); + } + + update_sample(&dev_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT], + 1, intel_gpu_freq(dev_priv, val)); + } + + if (dev_priv->pmu.enable & + config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY)) { + update_sample(&dev_priv->pmu.sample[__I915_SAMPLE_FREQ_REQ], 1, + intel_gpu_freq(dev_priv, + dev_priv->gt_pm.rps.cur_freq)); + } +} + +static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) +{ + struct drm_i915_private *i915 = + container_of(hrtimer, struct drm_i915_private, pmu.timer); + + if (i915->pmu.enable == 0) + return HRTIMER_NORESTART; + + engines_sample(i915); + frequency_sample(i915); + + hrtimer_forward_now(hrtimer, ns_to_ktime(PERIOD)); + return HRTIMER_RESTART; +} + +static void i915_pmu_event_destroy(struct perf_event *event) +{ + WARN_ON(event->parent); +} + +static int engine_event_init(struct perf_event *event) +{ + struct drm_i915_private *i915 = + container_of(event->pmu, typeof(*i915), pmu.base); + + if (!intel_engine_lookup_user(i915, engine_event_class(event), + engine_event_instance(event))) + return -ENODEV; + + switch (engine_event_sample(event)) { + case I915_SAMPLE_BUSY: + case I915_SAMPLE_WAIT: + break; + case I915_SAMPLE_SEMA: + if (INTEL_GEN(i915) < 6) + return -ENODEV; + break; + default: + return -ENOENT; + } + + return 0; +} + +static int i915_pmu_event_init(struct perf_event *event) +{ + struct drm_i915_private *i915 = + container_of(event->pmu, typeof(*i915), pmu.base); + int cpu, ret; + + if (event->attr.type != event->pmu->type) + return -ENOENT; + + /* unsupported modes and filters */ + if (event->attr.sample_period) /* no sampling */ + return -EINVAL; + + if (has_branch_stack(event)) + return -EOPNOTSUPP; + + if (event->cpu < 0) + return -EINVAL; + + cpu = cpumask_any_and(&i915_pmu_cpumask, + topology_sibling_cpumask(event->cpu)); + if (cpu >= nr_cpu_ids) + return -ENODEV; + + if (is_engine_event(event)) { + ret = engine_event_init(event); + } else { + ret = 0; + switch (event->attr.config) { + case I915_PMU_ACTUAL_FREQUENCY: + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) + /* Requires a mutex for sampling! */ + ret = -ENODEV; + case I915_PMU_REQUESTED_FREQUENCY: + if (INTEL_GEN(i915) < 6) + ret = -ENODEV; + break; + default: + ret = -ENOENT; + break; + } + } + if (ret) + return ret; + + event->cpu = cpu; + if (!event->parent) + event->destroy = i915_pmu_event_destroy; + + return 0; +} + +static u64 __i915_pmu_event_read(struct perf_event *event) +{ + struct drm_i915_private *i915 = + container_of(event->pmu, typeof(*i915), pmu.base); + u64 val = 0; + + if (is_engine_event(event)) { + u8 sample = engine_event_sample(event); + struct intel_engine_cs *engine; + + engine = intel_engine_lookup_user(i915, + engine_event_class(event), + engine_event_instance(event)); + + if (WARN_ON_ONCE(!engine)) { + /* Do nothing */ + } else { + val = engine->pmu.sample[sample].cur; + } + } else { + switch (event->attr.config) { + case I915_PMU_ACTUAL_FREQUENCY: + val = + div_u64(i915->pmu.sample[__I915_SAMPLE_FREQ_ACT].cur, + FREQUENCY); + break; + case I915_PMU_REQUESTED_FREQUENCY: + val = + div_u64(i915->pmu.sample[__I915_SAMPLE_FREQ_REQ].cur, + FREQUENCY); + break; + } + } + + return val; +} + +static void i915_pmu_event_read(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + u64 prev, new; + +again: + prev = local64_read(&hwc->prev_count); + new = __i915_pmu_event_read(event); + + if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev) + goto again; + + local64_add(new - prev, &event->count); +} + +static void i915_pmu_enable(struct perf_event *event) +{ + struct drm_i915_private *i915 = + container_of(event->pmu, typeof(*i915), pmu.base); + unsigned int bit = event_enabled_bit(event); + unsigned long flags; + + spin_lock_irqsave(&i915->pmu.lock, flags); + + /* + * Start the sampling timer when enabling the first event. + */ + if (i915->pmu.enable == 0) + hrtimer_start_range_ns(&i915->pmu.timer, + ns_to_ktime(PERIOD), 0, + HRTIMER_MODE_REL_PINNED); + + /* + * Update the bitmask of enabled events and increment + * the event reference counter. + */ + GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); + GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0); + i915->pmu.enable |= BIT_ULL(bit); + i915->pmu.enable_count[bit]++; + + /* + * For per-engine events the bitmask and reference counting + * is stored per engine. + */ + if (is_engine_event(event)) { + u8 sample = engine_event_sample(event); + struct intel_engine_cs *engine; + + engine = intel_engine_lookup_user(i915, + engine_event_class(event), + engine_event_instance(event)); + GEM_BUG_ON(!engine); + engine->pmu.enable |= BIT(sample); + + GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); + GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0); + engine->pmu.enable_count[sample]++; + } + + /* + * Store the current counter value so we can report the correct delta + * for all listeners. Even when the event was already enabled and has + * an existing non-zero value. + */ + local64_set(&event->hw.prev_count, __i915_pmu_event_read(event)); + + spin_unlock_irqrestore(&i915->pmu.lock, flags); +} + +static void i915_pmu_disable(struct perf_event *event) +{ + struct drm_i915_private *i915 = + container_of(event->pmu, typeof(*i915), pmu.base); + unsigned int bit = event_enabled_bit(event); + unsigned long flags; + + spin_lock_irqsave(&i915->pmu.lock, flags); + + if (is_engine_event(event)) { + u8 sample = engine_event_sample(event); + struct intel_engine_cs *engine; + + engine = intel_engine_lookup_user(i915, + engine_event_class(event), + engine_event_instance(event)); + GEM_BUG_ON(!engine); + GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); + GEM_BUG_ON(engine->pmu.enable_count[sample] == 0); + /* + * Decrement the reference count and clear the enabled + * bitmask when the last listener on an event goes away. + */ + if (--engine->pmu.enable_count[sample] == 0) + engine->pmu.enable &= ~BIT(sample); + } + + GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); + GEM_BUG_ON(i915->pmu.enable_count[bit] == 0); + /* + * Decrement the reference count and clear the enabled + * bitmask when the last listener on an event goes away. + */ + if (--i915->pmu.enable_count[bit] == 0) + i915->pmu.enable &= ~BIT_ULL(bit); + + spin_unlock_irqrestore(&i915->pmu.lock, flags); +} + +static void i915_pmu_event_start(struct perf_event *event, int flags) +{ + i915_pmu_enable(event); + event->hw.state = 0; +} + +static void i915_pmu_event_stop(struct perf_event *event, int flags) +{ + if (flags & PERF_EF_UPDATE) + i915_pmu_event_read(event); + i915_pmu_disable(event); + event->hw.state = PERF_HES_STOPPED; +} + +static int i915_pmu_event_add(struct perf_event *event, int flags) +{ + if (flags & PERF_EF_START) + i915_pmu_event_start(event, flags); + + return 0; +} + +static void i915_pmu_event_del(struct perf_event *event, int flags) +{ + i915_pmu_event_stop(event, PERF_EF_UPDATE); +} + +static int i915_pmu_event_event_idx(struct perf_event *event) +{ + return 0; +} + +static ssize_t i915_pmu_format_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dev_ext_attribute *eattr; + + eattr = container_of(attr, struct dev_ext_attribute, attr); + return sprintf(buf, "%s\n", (char *)eattr->var); +} + +#define I915_PMU_FORMAT_ATTR(_name, _config) \ + (&((struct dev_ext_attribute[]) { \ + { .attr = __ATTR(_name, 0444, i915_pmu_format_show, NULL), \ + .var = (void *)_config, } \ + })[0].attr.attr) + +static struct attribute *i915_pmu_format_attrs[] = { + I915_PMU_FORMAT_ATTR(i915_eventid, "config:0-20"), + NULL, +}; + +static const struct attribute_group i915_pmu_format_attr_group = { + .name = "format", + .attrs = i915_pmu_format_attrs, +}; + +static ssize_t i915_pmu_event_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dev_ext_attribute *eattr; + + eattr = container_of(attr, struct dev_ext_attribute, attr); + return sprintf(buf, "config=0x%lx\n", (unsigned long)eattr->var); +} + +#define I915_EVENT_ATTR(_name, _config) \ + (&((struct dev_ext_attribute[]) { \ + { .attr = __ATTR(_name, 0444, i915_pmu_event_show, NULL), \ + .var = (void *)_config, } \ + })[0].attr.attr) + +#define I915_EVENT_STR(_name, _str) \ + (&((struct perf_pmu_events_attr[]) { \ + { .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \ + .id = 0, \ + .event_str = _str, } \ + })[0].attr.attr) + +#define I915_EVENT(_name, _config, _unit) \ + I915_EVENT_ATTR(_name, _config), \ + I915_EVENT_STR(_name.unit, _unit) + +#define I915_ENGINE_EVENT(_name, _class, _instance, _sample) \ + I915_EVENT_ATTR(_name, __I915_PMU_ENGINE(_class, _instance, _sample)), \ + I915_EVENT_STR(_name.unit, "ns") + +#define I915_ENGINE_EVENTS(_name, _class, _instance) \ + I915_ENGINE_EVENT(_name##_instance-busy, _class, _instance, I915_SAMPLE_BUSY), \ + I915_ENGINE_EVENT(_name##_instance-sema, _class, _instance, I915_SAMPLE_SEMA), \ + I915_ENGINE_EVENT(_name##_instance-wait, _class, _instance, I915_SAMPLE_WAIT) + +static struct attribute *i915_pmu_events_attrs[] = { + I915_ENGINE_EVENTS(rcs, I915_ENGINE_CLASS_RENDER, 0), + I915_ENGINE_EVENTS(bcs, I915_ENGINE_CLASS_COPY, 0), + I915_ENGINE_EVENTS(vcs, I915_ENGINE_CLASS_VIDEO, 0), + I915_ENGINE_EVENTS(vcs, I915_ENGINE_CLASS_VIDEO, 1), + I915_ENGINE_EVENTS(vecs, I915_ENGINE_CLASS_VIDEO_ENHANCE, 0), + + I915_EVENT(actual-frequency, I915_PMU_ACTUAL_FREQUENCY, "MHz"), + I915_EVENT(requested-frequency, I915_PMU_REQUESTED_FREQUENCY, "MHz"), + + NULL, +}; + +static const struct attribute_group i915_pmu_events_attr_group = { + .name = "events", + .attrs = i915_pmu_events_attrs, +}; + +static ssize_t +i915_pmu_get_attr_cpumask(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return cpumap_print_to_pagebuf(true, buf, &i915_pmu_cpumask); +} + +static DEVICE_ATTR(cpumask, 0444, i915_pmu_get_attr_cpumask, NULL); + +static struct attribute *i915_cpumask_attrs[] = { + &dev_attr_cpumask.attr, + NULL, +}; + +static struct attribute_group i915_pmu_cpumask_attr_group = { + .attrs = i915_cpumask_attrs, +}; + +static const struct attribute_group *i915_pmu_attr_groups[] = { + &i915_pmu_format_attr_group, + &i915_pmu_events_attr_group, + &i915_pmu_cpumask_attr_group, + NULL +}; + +#ifdef CONFIG_HOTPLUG_CPU +static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node) +{ + struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node); + unsigned int target; + + GEM_BUG_ON(!pmu->base.event_init); + + target = cpumask_any_and(&i915_pmu_cpumask, &i915_pmu_cpumask); + /* Select the first online CPU as a designated reader. */ + if (target >= nr_cpu_ids) + cpumask_set_cpu(cpu, &i915_pmu_cpumask); + + return 0; +} + +static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node) +{ + struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node); + unsigned int target; + + GEM_BUG_ON(!pmu->base.event_init); + + if (cpumask_test_and_clear_cpu(cpu, &i915_pmu_cpumask)) { + target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu); + /* Migrate events if there is a valid target */ + if (target < nr_cpu_ids) { + cpumask_set_cpu(target, &i915_pmu_cpumask); + perf_pmu_migrate_context(&pmu->base, cpu, target); + } + } + + return 0; +} + +static enum cpuhp_state cpuhp_slot = CPUHP_INVALID; +#endif + +static int i915_pmu_register_cpuhp_state(struct drm_i915_private *i915) +{ +#ifdef CONFIG_HOTPLUG_CPU + enum cpuhp_state slot; + int ret; + + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/x86/intel/i915:online", + i915_pmu_cpu_online, + i915_pmu_cpu_offline); + if (ret < 0) + return ret; + + slot = ret; + ret = cpuhp_state_add_instance(slot, &i915->pmu.node); + if (ret) { + cpuhp_remove_multi_state(slot); + return ret; + } + + cpuhp_slot = slot; +#endif + return 0; +} + +static void i915_pmu_unregister_cpuhp_state(struct drm_i915_private *i915) +{ +#ifdef CONFIG_HOTPLUG_CPU + WARN_ON(cpuhp_slot == CPUHP_INVALID); + WARN_ON(cpuhp_state_remove_instance(cpuhp_slot, &i915->pmu.node)); + cpuhp_remove_multi_state(cpuhp_slot); +#endif +} + +void i915_pmu_register(struct drm_i915_private *i915) +{ + int ret; + + if (INTEL_GEN(i915) <= 2) { + DRM_INFO("PMU not supported for this GPU."); + return; + } + + i915->pmu.base.attr_groups = i915_pmu_attr_groups; + i915->pmu.base.task_ctx_nr = perf_invalid_context; + i915->pmu.base.event_init = i915_pmu_event_init; + i915->pmu.base.add = i915_pmu_event_add; + i915->pmu.base.del = i915_pmu_event_del; + i915->pmu.base.start = i915_pmu_event_start; + i915->pmu.base.stop = i915_pmu_event_stop; + i915->pmu.base.read = i915_pmu_event_read; + i915->pmu.base.event_idx = i915_pmu_event_event_idx; + + spin_lock_init(&i915->pmu.lock); + hrtimer_init(&i915->pmu.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + i915->pmu.timer.function = i915_sample; + + ret = perf_pmu_register(&i915->pmu.base, "i915", -1); + if (ret) + goto err; + + ret = i915_pmu_register_cpuhp_state(i915); + if (ret) + goto err_unreg; + + return; + +err_unreg: + perf_pmu_unregister(&i915->pmu.base); +err: + i915->pmu.base.event_init = NULL; + DRM_NOTE("Failed to register PMU! (err=%d)\n", ret); +} + +void i915_pmu_unregister(struct drm_i915_private *i915) +{ + if (!i915->pmu.base.event_init) + return; + + WARN_ON(i915->pmu.enable); + + hrtimer_cancel(&i915->pmu.timer); + + i915_pmu_unregister_cpuhp_state(i915); + + perf_pmu_unregister(&i915->pmu.base); + i915->pmu.base.event_init = NULL; +} diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h new file mode 100644 index 000000000000..1ac8b2e34607 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -0,0 +1,104 @@ +/* + * Copyright © 2017 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ +#ifndef __I915_PMU_H__ +#define __I915_PMU_H__ + +enum { + __I915_SAMPLE_FREQ_ACT = 0, + __I915_SAMPLE_FREQ_REQ, + __I915_NUM_PMU_SAMPLERS +}; + +/** + * How many different events we track in the global PMU mask. + * + * It is also used to know to needed number of event reference counters. + */ +#define I915_PMU_MASK_BITS \ + ((1 << I915_PMU_SAMPLE_BITS) + \ + (I915_PMU_LAST + 1 - __I915_PMU_OTHER(0))) + +struct i915_pmu_sample { + u64 cur; + u32 prev; +}; + +struct i915_pmu { + /** + * @node: List node for CPU hotplug handling. + */ + struct hlist_node node; + /** + * @base: PMU base. + */ + struct pmu base; + /** + * @lock: Lock protecting enable mask and ref count handling. + */ + spinlock_t lock; + /** + * @timer: Timer for internal i915 PMU sampling. + */ + struct hrtimer timer; + /** + * @enable: Bitmask of all currently enabled events. + * + * Bits are derived from uAPI event numbers in a way that low 16 bits + * correspond to engine event _sample_ _type_ (I915_SAMPLE_QUEUED is + * bit 0), and higher bits correspond to other events (for instance + * I915_PMU_ACTUAL_FREQUENCY is bit 16 etc). + * + * In other words, low 16 bits are not per engine but per engine + * sampler type, while the upper bits are directly mapped to other + * event types. + */ + u64 enable; + /** + * @enable_count: Reference counts for the enabled events. + * + * Array indices are mapped in the same way as bits in the @enable field + * and they are used to control sampling on/off when multiple clients + * are using the PMU API. + */ + unsigned int enable_count[I915_PMU_MASK_BITS]; + /** + * @sample: Current and previous (raw) counters for sampling events. + * + * These counters are updated from the i915 PMU sampling timer. + * + * Only global counters are held here, while the per-engine ones are in + * struct intel_engine_cs. + */ + struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS]; +}; + +#ifdef CONFIG_PERF_EVENTS +void i915_pmu_register(struct drm_i915_private *i915); +void i915_pmu_unregister(struct drm_i915_private *i915); +#else +static inline void i915_pmu_register(struct drm_i915_private *i915) {} +static inline void i915_pmu_unregister(struct drm_i915_private *i915) {} +#endif + +#endif diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 96c80fa0fcac..09bf043c1c2e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -186,6 +186,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define VIDEO_ENHANCEMENT_CLASS 2 #define COPY_ENGINE_CLASS 3 #define OTHER_CLASS 4 +#define MAX_ENGINE_CLASS 4 + +#define MAX_ENGINE_INSTANCE 1 /* PCI config space */ diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 22c095035539..a5a494210b9e 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -205,6 +205,15 @@ intel_engine_setup(struct drm_i915_private *dev_priv, GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes)); class_info = &intel_engine_classes[info->class]; + if (GEM_WARN_ON(info->class > MAX_ENGINE_CLASS)) + return -EINVAL; + + if (GEM_WARN_ON(info->instance > MAX_ENGINE_INSTANCE)) + return -EINVAL; + + if (GEM_WARN_ON(dev_priv->engine_class[info->class][info->instance])) + return -EINVAL; + GEM_BUG_ON(dev_priv->engine[id]); engine = kzalloc(sizeof(*engine), GFP_KERNEL); if (!engine) @@ -234,6 +243,7 @@ intel_engine_setup(struct drm_i915_private *dev_priv, ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); + dev_priv->engine_class[info->class][info->instance] = engine; dev_priv->engine[id] = engine; return 0; } @@ -1816,6 +1826,29 @@ void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m) drm_printf(m, "\n"); } +static u8 user_class_map[] = { + [I915_ENGINE_CLASS_RENDER] = RENDER_CLASS, + [I915_ENGINE_CLASS_COPY] = COPY_ENGINE_CLASS, + [I915_ENGINE_CLASS_VIDEO] = VIDEO_DECODE_CLASS, + [I915_ENGINE_CLASS_VIDEO_ENHANCE] = VIDEO_ENHANCEMENT_CLASS, +}; + +struct intel_engine_cs * +intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance) +{ + if (class >= ARRAY_SIZE(user_class_map)) + return NULL; + + class = user_class_map[class]; + + GEM_BUG_ON(class > MAX_ENGINE_CLASS); + + if (instance > MAX_ENGINE_INSTANCE) + return NULL; + + return i915->engine_class[class][instance]; +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftests/mock_engine.c" #endif diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 80cd7812ce02..7ee0f18d4179 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -5,6 +5,7 @@ #include "i915_gem_batch_pool.h" #include "i915_gem_request.h" #include "i915_gem_timeline.h" +#include "i915_pmu.h" #include "i915_selftest.h" struct drm_printer; @@ -338,6 +339,28 @@ struct intel_engine_cs { I915_SELFTEST_DECLARE(bool mock : 1); } breadcrumbs; + struct { + /** + * @enable: Bitmask of enable sample events on this engine. + * + * Bits correspond to sample event types, for instance + * I915_SAMPLE_QUEUED is bit 0 etc. + */ + u32 enable; + /** + * @enable_count: Reference count for the enabled samplers. + * + * Index number corresponds to the bit number from @enable. + */ + unsigned int enable_count[I915_PMU_SAMPLE_BITS]; + /** + * @sample: Counter values for sampling events. + * + * Our internal timer stores the current counters in this field. + */ + struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX]; + } pmu; + /* * A pool of objects to use as shadow copies of client batch buffers * when the command parser is enabled. Prevents the client from @@ -926,4 +949,7 @@ bool intel_engine_can_store_dword(struct intel_engine_cs *engine); void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *p); +struct intel_engine_cs * +intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance); + #endif /* _INTEL_RINGBUFFER_H_ */ diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index b57985929553..40e7b438bdaa 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -102,6 +102,45 @@ enum drm_i915_gem_engine_class { I915_ENGINE_CLASS_INVALID = -1 }; +/** + * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 + * + */ + +enum drm_i915_pmu_engine_sample { + I915_SAMPLE_BUSY = 0, + I915_SAMPLE_WAIT = 1, + I915_SAMPLE_SEMA = 2, + I915_ENGINE_SAMPLE_MAX /* non-ABI */ +}; + +#define I915_PMU_SAMPLE_BITS (4) +#define I915_PMU_SAMPLE_MASK (0xf) +#define I915_PMU_SAMPLE_INSTANCE_BITS (8) +#define I915_PMU_CLASS_SHIFT \ + (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) + +#define __I915_PMU_ENGINE(class, instance, sample) \ + ((class) << I915_PMU_CLASS_SHIFT | \ + (instance) << I915_PMU_SAMPLE_BITS | \ + (sample)) + +#define I915_PMU_ENGINE_BUSY(class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) + +#define I915_PMU_ENGINE_WAIT(class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) + +#define I915_PMU_ENGINE_SEMA(class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) + +#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) + +#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) +#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) + +#define I915_PMU_LAST I915_PMU_REQUESTED_FREQUENCY + /* Each region is a minimum of 16k, and there are at most 255 of them. */ #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use -- GitLab From feff0dc6cdc527f8a6fd170d8de7966f56890fc0 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 21 Nov 2017 18:18:46 +0000 Subject: [PATCH 0072/2547] drm/i915/pmu: Suspend sampling when GPU is idle If only a subset of events is enabled we can afford to suspend the sampling timer when the GPU is idle and so save some cycles and power. v2: Rebase and limit timer even more. v3: Rebase. v4: Rebase. v5: Skip action if perf PMU failed to register. v6: Checkpatch cleanup. v7: * Add a common helper to start the timer if needed. (Chris Wilson) * Add comment explaining bitwise logic in pmu_needs_timer. v8: Fix some comments styles. (Chris Wilson) v9: Rebase. v10: Move function declarations to i915_pmu.h. v11: Rename functions to i915_pmu_gt_(un)parked. (Chris Wilson) Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-3-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_gem.c | 1 + drivers/gpu/drm/i915/i915_gem_request.c | 1 + drivers/gpu/drm/i915/i915_pmu.c | 88 ++++++++++++++++++++++--- drivers/gpu/drm/i915/i915_pmu.h | 8 +++ 4 files changed, 88 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 792e6dc7e19b..21ca680e9e63 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3372,6 +3372,7 @@ i915_gem_idle_work_handler(struct work_struct *work) intel_engines_park(dev_priv); i915_gem_timelines_mark_idle(dev_priv); + i915_pmu_gt_parked(dev_priv); GEM_BUG_ON(!dev_priv->gt.awake); dev_priv->gt.awake = false; diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 86e2346357cf..7325469ce754 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -258,6 +258,7 @@ static void mark_busy(struct drm_i915_private *i915) i915_update_gfx_val(i915); if (INTEL_GEN(i915) >= 6) gen6_rps_busy(i915); + i915_pmu_gt_unparked(i915); intel_engines_unpark(i915); diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 01b5ee67c1bf..fb95f0ac30ea 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -90,6 +90,75 @@ static unsigned int event_enabled_bit(struct perf_event *event) return config_enabled_bit(event->attr.config); } +static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active) +{ + u64 enable; + + /* + * Only some counters need the sampling timer. + * + * We start with a bitmask of all currently enabled events. + */ + enable = i915->pmu.enable; + + /* + * Mask out all the ones which do not need the timer, or in + * other words keep all the ones that could need the timer. + */ + enable &= config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY) | + config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY) | + ENGINE_SAMPLE_MASK; + + /* + * When the GPU is idle per-engine counters do not need to be + * running so clear those bits out. + */ + if (!gpu_active) + enable &= ~ENGINE_SAMPLE_MASK; + + /* + * If some bits remain it means we need the sampling timer running. + */ + return enable; +} + +void i915_pmu_gt_parked(struct drm_i915_private *i915) +{ + if (!i915->pmu.base.event_init) + return; + + spin_lock_irq(&i915->pmu.lock); + /* + * Signal sampling timer to stop if only engine events are enabled and + * GPU went idle. + */ + i915->pmu.timer_enabled = pmu_needs_timer(i915, false); + spin_unlock_irq(&i915->pmu.lock); +} + +static void __i915_pmu_maybe_start_timer(struct drm_i915_private *i915) +{ + if (!i915->pmu.timer_enabled && pmu_needs_timer(i915, true)) { + i915->pmu.timer_enabled = true; + hrtimer_start_range_ns(&i915->pmu.timer, + ns_to_ktime(PERIOD), 0, + HRTIMER_MODE_REL_PINNED); + } +} + +void i915_pmu_gt_unparked(struct drm_i915_private *i915) +{ + if (!i915->pmu.base.event_init) + return; + + spin_lock_irq(&i915->pmu.lock); + /* + * Re-enable sampling timer when GPU goes active. + */ + __i915_pmu_maybe_start_timer(i915); + spin_unlock_irq(&i915->pmu.lock); +} + static bool grab_forcewake(struct drm_i915_private *i915, bool fw) { if (!fw) @@ -187,7 +256,7 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) struct drm_i915_private *i915 = container_of(hrtimer, struct drm_i915_private, pmu.timer); - if (i915->pmu.enable == 0) + if (!READ_ONCE(i915->pmu.timer_enabled)) return HRTIMER_NORESTART; engines_sample(i915); @@ -339,14 +408,6 @@ static void i915_pmu_enable(struct perf_event *event) spin_lock_irqsave(&i915->pmu.lock, flags); - /* - * Start the sampling timer when enabling the first event. - */ - if (i915->pmu.enable == 0) - hrtimer_start_range_ns(&i915->pmu.timer, - ns_to_ktime(PERIOD), 0, - HRTIMER_MODE_REL_PINNED); - /* * Update the bitmask of enabled events and increment * the event reference counter. @@ -356,6 +417,11 @@ static void i915_pmu_enable(struct perf_event *event) i915->pmu.enable |= BIT_ULL(bit); i915->pmu.enable_count[bit]++; + /* + * Start the sampling timer if needed and not already enabled. + */ + __i915_pmu_maybe_start_timer(i915); + /* * For per-engine events the bitmask and reference counting * is stored per engine. @@ -418,8 +484,10 @@ static void i915_pmu_disable(struct perf_event *event) * Decrement the reference count and clear the enabled * bitmask when the last listener on an event goes away. */ - if (--i915->pmu.enable_count[bit] == 0) + if (--i915->pmu.enable_count[bit] == 0) { i915->pmu.enable &= ~BIT_ULL(bit); + i915->pmu.timer_enabled &= pmu_needs_timer(i915, true); + } spin_unlock_irqrestore(&i915->pmu.lock, flags); } diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h index 1ac8b2e34607..e209783a4c5f 100644 --- a/drivers/gpu/drm/i915/i915_pmu.h +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -82,6 +82,10 @@ struct i915_pmu { * are using the PMU API. */ unsigned int enable_count[I915_PMU_MASK_BITS]; + /** + * @timer_enabled: Should the internal sampling timer be running. + */ + bool timer_enabled; /** * @sample: Current and previous (raw) counters for sampling events. * @@ -96,9 +100,13 @@ struct i915_pmu { #ifdef CONFIG_PERF_EVENTS void i915_pmu_register(struct drm_i915_private *i915); void i915_pmu_unregister(struct drm_i915_private *i915); +void i915_pmu_gt_parked(struct drm_i915_private *i915); +void i915_pmu_gt_unparked(struct drm_i915_private *i915); #else static inline void i915_pmu_register(struct drm_i915_private *i915) {} static inline void i915_pmu_unregister(struct drm_i915_private *i915) {} +static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {} +static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {} #endif #endif -- GitLab From 73fd9d381693dee6f28bb24de4b81b643d4d6d63 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 21 Nov 2017 18:18:47 +0000 Subject: [PATCH 0073/2547] drm/i915: Wrap context schedule notification No functional change just something which will be handy in the following patch. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-4-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/intel_lrc.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 16d4936e2368..8e3990d5191c 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -379,6 +379,18 @@ execlists_context_status_change(struct drm_i915_gem_request *rq, status, rq); } +static inline void +execlists_context_schedule_in(struct drm_i915_gem_request *rq) +{ + execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); +} + +static inline void +execlists_context_schedule_out(struct drm_i915_gem_request *rq) +{ + execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); +} + static void execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) { @@ -430,7 +442,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine) if (rq) { GEM_BUG_ON(count > !n); if (!count++) - execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); + execlists_context_schedule_in(rq); port_set(&port[n], port_pack(rq, count)); desc = execlists_update_context(rq); GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); @@ -902,8 +914,7 @@ static void execlists_submission_tasklet(unsigned long data) GEM_BUG_ON(port_isset(&port[1]) && !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH)); GEM_BUG_ON(!i915_gem_request_completed(rq)); - execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); - + execlists_context_schedule_out(rq); trace_i915_gem_request_out(rq); i915_gem_request_put(rq); -- GitLab From 30e17b7847f54732a91e5804144d445e9f29493b Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 21 Nov 2017 18:18:48 +0000 Subject: [PATCH 0074/2547] drm/i915: Engine busy time tracking Track total time requests have been executing on the hardware. We add new kernel API to allow software tracking of time GPU engines are spending executing requests. Both per-engine and global API is added with the latter also being exported for use by external users. v2: * Squashed with the internal API. * Dropped static key. * Made per-engine. * Store time in monotonic ktime. v3: Moved stats clearing to disable. v4: * Comments. * Don't export the API just yet. v5: Whitespace cleanup. v6: * Rename ref to active. * Drop engine aggregate stats for now. * Account initial busy period after enabling stats. v7: * Rebase. v8: * Move context in notification after the notifier. (Chris Wilson) v9: In cases where stats tracking is getting disabled while there is an active context on an engine, add up the current value to the total. This also implies we don't clear the total when tracking is disabled any longer. There is no real need to do so because we define the stats as relative while enabled, meaning comparison between two samples while tracking is enabled is the valid usage. However, when busy stats will later be plugged into the perf PMU API, it is beneficial to not reset the total, since the PMU core likes to do some counter disable/enable cycles on startup, and while doing so during a single long context executing on an engine we would lose some accuracy and so make unit testing more difficult than needs to be. v10: * Fix accounting for preemption. v11: * Rebase for i915_modparams.enable_execlists removal. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-5-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/intel_engine_cs.c | 87 +++++++++++++++++++++++ drivers/gpu/drm/i915/intel_lrc.c | 3 + drivers/gpu/drm/i915/intel_ringbuffer.h | 92 +++++++++++++++++++++++++ 3 files changed, 182 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index a5a494210b9e..fede62daf3e1 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -241,6 +241,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv, /* Nothing to do here, execute in order of dependencies */ engine->schedule = NULL; + spin_lock_init(&engine->stats.lock); + ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); dev_priv->engine_class[info->class][info->instance] = engine; @@ -1849,6 +1851,91 @@ intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance) return i915->engine_class[class][instance]; } +/** + * intel_enable_engine_stats() - Enable engine busy tracking on engine + * @engine: engine to enable stats collection + * + * Start collecting the engine busyness data for @engine. + * + * Returns 0 on success or a negative error code. + */ +int intel_enable_engine_stats(struct intel_engine_cs *engine) +{ + unsigned long flags; + + if (INTEL_GEN(engine->i915) < 8) + return -ENODEV; + + spin_lock_irqsave(&engine->stats.lock, flags); + if (engine->stats.enabled == ~0) + goto busy; + if (engine->stats.enabled++ == 0) + engine->stats.enabled_at = ktime_get(); + spin_unlock_irqrestore(&engine->stats.lock, flags); + + return 0; + +busy: + spin_unlock_irqrestore(&engine->stats.lock, flags); + + return -EBUSY; +} + +static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine) +{ + ktime_t total = engine->stats.total; + + /* + * If the engine is executing something at the moment + * add it to the total. + */ + if (engine->stats.active) + total = ktime_add(total, + ktime_sub(ktime_get(), engine->stats.start)); + + return total; +} + +/** + * intel_engine_get_busy_time() - Return current accumulated engine busyness + * @engine: engine to report on + * + * Returns accumulated time @engine was busy since engine stats were enabled. + */ +ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine) +{ + ktime_t total; + unsigned long flags; + + spin_lock_irqsave(&engine->stats.lock, flags); + total = __intel_engine_get_busy_time(engine); + spin_unlock_irqrestore(&engine->stats.lock, flags); + + return total; +} + +/** + * intel_disable_engine_stats() - Disable engine busy tracking on engine + * @engine: engine to disable stats collection + * + * Stops collecting the engine busyness data for @engine. + */ +void intel_disable_engine_stats(struct intel_engine_cs *engine) +{ + unsigned long flags; + + if (INTEL_GEN(engine->i915) < 8) + return; + + spin_lock_irqsave(&engine->stats.lock, flags); + WARN_ON_ONCE(engine->stats.enabled == 0); + if (--engine->stats.enabled == 0) { + engine->stats.total = __intel_engine_get_busy_time(engine); + engine->stats.active = 0; + } + spin_unlock_irqrestore(&engine->stats.lock, flags); +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftests/mock_engine.c" #endif diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 8e3990d5191c..570864583e28 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -383,11 +383,13 @@ static inline void execlists_context_schedule_in(struct drm_i915_gem_request *rq) { execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); + intel_engine_context_in(rq->engine); } static inline void execlists_context_schedule_out(struct drm_i915_gem_request *rq) { + intel_engine_context_out(rq->engine); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); } @@ -705,6 +707,7 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) struct drm_i915_gem_request *rq = port_request(port); GEM_BUG_ON(!execlists->active); + intel_engine_context_out(rq->engine); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_PREEMPTED); i915_gem_request_put(rq); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 7ee0f18d4179..215edfa424d5 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -547,6 +547,38 @@ struct intel_engine_cs { * certain bits to encode the command length in the header). */ u32 (*get_cmd_length_mask)(u32 cmd_header); + + struct { + /** + * @lock: Lock protecting the below fields. + */ + spinlock_t lock; + /** + * @enabled: Reference count indicating number of listeners. + */ + unsigned int enabled; + /** + * @active: Number of contexts currently scheduled in. + */ + unsigned int active; + /** + * @enabled_at: Timestamp when busy stats were enabled. + */ + ktime_t enabled_at; + /** + * @start: Timestamp of the last idle to active transition. + * + * Idle is defined as active == 0, active is active > 0. + */ + ktime_t start; + /** + * @total: Total time this engine was busy. + * + * Accumulated time not counting the most recent block in cases + * where engine is currently busy (active > 0). + */ + ktime_t total; + } stats; }; static inline void @@ -952,4 +984,64 @@ void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *p); struct intel_engine_cs * intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance); +static inline void intel_engine_context_in(struct intel_engine_cs *engine) +{ + unsigned long flags; + + if (READ_ONCE(engine->stats.enabled) == 0) + return; + + spin_lock_irqsave(&engine->stats.lock, flags); + + if (engine->stats.enabled > 0) { + if (engine->stats.active++ == 0) + engine->stats.start = ktime_get(); + GEM_BUG_ON(engine->stats.active == 0); + } + + spin_unlock_irqrestore(&engine->stats.lock, flags); +} + +static inline void intel_engine_context_out(struct intel_engine_cs *engine) +{ + unsigned long flags; + + if (READ_ONCE(engine->stats.enabled) == 0) + return; + + spin_lock_irqsave(&engine->stats.lock, flags); + + if (engine->stats.enabled > 0) { + ktime_t last; + + if (engine->stats.active && --engine->stats.active == 0) { + /* + * Decrement the active context count and in case GPU + * is now idle add up to the running total. + */ + last = ktime_sub(ktime_get(), engine->stats.start); + + engine->stats.total = ktime_add(engine->stats.total, + last); + } else if (engine->stats.active == 0) { + /* + * After turning on engine stats, context out might be + * the first event in which case we account from the + * time stats gathering was turned on. + */ + last = ktime_sub(ktime_get(), engine->stats.enabled_at); + + engine->stats.total = ktime_add(engine->stats.total, + last); + } + } + + spin_unlock_irqrestore(&engine->stats.lock, flags); +} + +int intel_enable_engine_stats(struct intel_engine_cs *engine); +void intel_disable_engine_stats(struct intel_engine_cs *engine); + +ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine); + #endif /* _INTEL_RINGBUFFER_H_ */ -- GitLab From b3add01ee217db8e0da8a6596f03c487ed33b06e Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 21 Nov 2017 18:18:49 +0000 Subject: [PATCH 0075/2547] drm/i915/pmu: Wire up engine busy stats to PMU We can use engine busy stats instead of the sampling timer for better accuracy. By doing this we replace the stohastic sampling with busyness metric derived directly from engine activity. This is context switch interrupt driven, so as accurate as we can get from software tracking. As a secondary benefit, we can also not run the sampling timer in cases only busyness metric is enabled. v2: Rebase. v3: * Rebase, comments. * Leave engine busyness controls out of workers. v4: Checkpatch cleanup. v5: Added comment to pmu_needs_timer change. v6: * Rebase. * Fix style of some comments. (Chris Wilson) v7: Rebase and commit message update. (Chris Wilson) v8: Add delayed stats disabling to improve accuracy in face of CPU hotplug events. v9: Rebase. v10: Rebase - i915_modparams.enable_execlists removal. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-6-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_pmu.c | 78 ++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_ringbuffer.h | 14 +++++ 2 files changed, 90 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index fb95f0ac30ea..6a428e7218d2 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -90,6 +90,11 @@ static unsigned int event_enabled_bit(struct perf_event *event) return config_enabled_bit(event->attr.config); } +static bool supports_busy_stats(struct drm_i915_private *i915) +{ + return INTEL_GEN(i915) >= 8; +} + static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active) { u64 enable; @@ -115,6 +120,12 @@ static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active) */ if (!gpu_active) enable &= ~ENGINE_SAMPLE_MASK; + /* + * Also there is software busyness tracking available we do not + * need the timer for I915_SAMPLE_BUSY counter. + */ + else if (supports_busy_stats(i915)) + enable &= ~BIT(I915_SAMPLE_BUSY); /* * If some bits remain it means we need the sampling timer running. @@ -363,6 +374,9 @@ static u64 __i915_pmu_event_read(struct perf_event *event) if (WARN_ON_ONCE(!engine)) { /* Do nothing */ + } else if (sample == I915_SAMPLE_BUSY && + engine->pmu.busy_stats) { + val = ktime_to_ns(intel_engine_get_busy_time(engine)); } else { val = engine->pmu.sample[sample].cur; } @@ -399,6 +413,12 @@ static void i915_pmu_event_read(struct perf_event *event) local64_add(new - prev, &event->count); } +static bool engine_needs_busy_stats(struct intel_engine_cs *engine) +{ + return supports_busy_stats(engine->i915) && + (engine->pmu.enable & BIT(I915_SAMPLE_BUSY)); +} + static void i915_pmu_enable(struct perf_event *event) { struct drm_i915_private *i915 = @@ -438,7 +458,21 @@ static void i915_pmu_enable(struct perf_event *event) GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0); - engine->pmu.enable_count[sample]++; + if (engine->pmu.enable_count[sample]++ == 0) { + /* + * Enable engine busy stats tracking if needed or + * alternatively cancel the scheduled disable. + * + * If the delayed disable was pending, cancel it and + * in this case do not enable since it already is. + */ + if (engine_needs_busy_stats(engine) && + !engine->pmu.busy_stats) { + engine->pmu.busy_stats = true; + if (!cancel_delayed_work(&engine->pmu.disable_busy_stats)) + intel_enable_engine_stats(engine); + } + } } /* @@ -451,6 +485,14 @@ static void i915_pmu_enable(struct perf_event *event) spin_unlock_irqrestore(&i915->pmu.lock, flags); } +static void __disable_busy_stats(struct work_struct *work) +{ + struct intel_engine_cs *engine = + container_of(work, typeof(*engine), pmu.disable_busy_stats.work); + + intel_disable_engine_stats(engine); +} + static void i915_pmu_disable(struct perf_event *event) { struct drm_i915_private *i915 = @@ -474,8 +516,26 @@ static void i915_pmu_disable(struct perf_event *event) * Decrement the reference count and clear the enabled * bitmask when the last listener on an event goes away. */ - if (--engine->pmu.enable_count[sample] == 0) + if (--engine->pmu.enable_count[sample] == 0) { engine->pmu.enable &= ~BIT(sample); + if (!engine_needs_busy_stats(engine) && + engine->pmu.busy_stats) { + engine->pmu.busy_stats = false; + /* + * We request a delayed disable to handle the + * rapid on/off cycles on events, which can + * happen when tools like perf stat start, in a + * nicer way. + * + * In addition, this also helps with busy stats + * accuracy with background CPU offline/online + * migration events. + */ + queue_delayed_work(system_wq, + &engine->pmu.disable_busy_stats, + round_jiffies_up_relative(HZ)); + } + } } GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); @@ -702,6 +762,8 @@ static void i915_pmu_unregister_cpuhp_state(struct drm_i915_private *i915) void i915_pmu_register(struct drm_i915_private *i915) { + struct intel_engine_cs *engine; + enum intel_engine_id id; int ret; if (INTEL_GEN(i915) <= 2) { @@ -723,6 +785,10 @@ void i915_pmu_register(struct drm_i915_private *i915) hrtimer_init(&i915->pmu.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); i915->pmu.timer.function = i915_sample; + for_each_engine(engine, i915, id) + INIT_DELAYED_WORK(&engine->pmu.disable_busy_stats, + __disable_busy_stats); + ret = perf_pmu_register(&i915->pmu.base, "i915", -1); if (ret) goto err; @@ -742,6 +808,9 @@ void i915_pmu_register(struct drm_i915_private *i915) void i915_pmu_unregister(struct drm_i915_private *i915) { + struct intel_engine_cs *engine; + enum intel_engine_id id; + if (!i915->pmu.base.event_init) return; @@ -749,6 +818,11 @@ void i915_pmu_unregister(struct drm_i915_private *i915) hrtimer_cancel(&i915->pmu.timer); + for_each_engine(engine, i915, id) { + GEM_BUG_ON(engine->pmu.busy_stats); + flush_delayed_work(&engine->pmu.disable_busy_stats); + } + i915_pmu_unregister_cpuhp_state(i915); perf_pmu_unregister(&i915->pmu.base); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 215edfa424d5..43473e6d1a4f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -359,6 +359,20 @@ struct intel_engine_cs { * Our internal timer stores the current counters in this field. */ struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX]; + /** + * @busy_stats: Has enablement of engine stats tracking been + * requested. + */ + bool busy_stats; + /** + * @disable_busy_stats: Work item for busy stats disabling. + * + * Same as with @enable_busy_stats action, with the difference + * that we delay it in case there are rapid enable-disable + * actions, which can happen during tool startup (like perf + * stat). + */ + struct delayed_work disable_busy_stats; } pmu; /* -- GitLab From 0cd4684d6ea9a4ffec33fc19de4dd667bb90d0a5 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 21 Nov 2017 18:18:50 +0000 Subject: [PATCH 0076/2547] drm/i915/pmu: Add interrupt count metric For clients like intel-gpu-overlay it is easier to read the count via the perf API than having to parse /proc. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-7-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_pmu.c | 23 +++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 4 +++- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 6a428e7218d2..fef389ebf92c 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -277,6 +277,22 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) return HRTIMER_RESTART; } +static u64 count_interrupts(struct drm_i915_private *i915) +{ + /* open-coded kstat_irqs() */ + struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq); + u64 sum = 0; + int cpu; + + if (!desc || !desc->kstat_irqs) + return 0; + + for_each_possible_cpu(cpu) + sum += *per_cpu_ptr(desc->kstat_irqs, cpu); + + return sum; +} + static void i915_pmu_event_destroy(struct perf_event *event) { WARN_ON(event->parent); @@ -343,6 +359,8 @@ static int i915_pmu_event_init(struct perf_event *event) if (INTEL_GEN(i915) < 6) ret = -ENODEV; break; + case I915_PMU_INTERRUPTS: + break; default: ret = -ENOENT; break; @@ -392,6 +410,9 @@ static u64 __i915_pmu_event_read(struct perf_event *event) div_u64(i915->pmu.sample[__I915_SAMPLE_FREQ_REQ].cur, FREQUENCY); break; + case I915_PMU_INTERRUPTS: + val = count_interrupts(i915); + break; } } @@ -654,6 +675,8 @@ static struct attribute *i915_pmu_events_attrs[] = { I915_EVENT(actual-frequency, I915_PMU_ACTUAL_FREQUENCY, "MHz"), I915_EVENT(requested-frequency, I915_PMU_REQUESTED_FREQUENCY, "MHz"), + I915_EVENT_ATTR(interrupts, I915_PMU_INTERRUPTS), + NULL, }; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 40e7b438bdaa..d840ff083520 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -139,7 +139,9 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) -#define I915_PMU_LAST I915_PMU_REQUESTED_FREQUENCY +#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) + +#define I915_PMU_LAST I915_PMU_INTERRUPTS /* Each region is a minimum of 16k, and there are at most 255 of them. */ -- GitLab From 36cc8b963f5eb46352dc79d79e4bd5e8dd2ac2d6 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 21 Nov 2017 18:18:51 +0000 Subject: [PATCH 0077/2547] drm/i915: Convert intel_rc6_residency_us to ns Will be used for exposing the PMU counters. v2: * Move intel_runtime_pm_get/put to the callers. (Chris Wilson) * Restore full unit conversion precision. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-8-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_drv.h | 8 +++++++- drivers/gpu/drm/i915/i915_sysfs.c | 9 +++++++-- drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++-------------- 3 files changed, 27 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5bd5ac4cd03e..d575a56fc100 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -4228,11 +4228,17 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder, int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); -u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, +u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, const i915_reg_t reg); u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1); +static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, + const i915_reg_t reg) +{ + return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000); +} + #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 450ac7d343ad..c290cb600eea 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -42,8 +42,13 @@ static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev) static u32 calc_residency(struct drm_i915_private *dev_priv, i915_reg_t reg) { - return DIV_ROUND_CLOSEST_ULL(intel_rc6_residency_us(dev_priv, reg), - 1000); + u64 res; + + intel_runtime_pm_get(dev_priv); + res = intel_rc6_residency_us(dev_priv, reg); + intel_runtime_pm_put(dev_priv); + + return DIV_ROUND_CLOSEST_ULL(res, 1000); } static ssize_t diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f1dc36c1fd69..7d41aad79166 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -9437,36 +9437,35 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv, return lower | (u64)upper << 8; } -u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, +u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, const i915_reg_t reg) { - u64 time_hw, units, div; + u64 time_hw; + u32 mul, div; if (!intel_rc6_enabled()) return 0; - intel_runtime_pm_get(dev_priv); - /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - units = 1000; + mul = 1000000; div = dev_priv->czclk_freq; - time_hw = vlv_residency_raw(dev_priv, reg); - } else if (IS_GEN9_LP(dev_priv)) { - units = 1000; - div = 1200; /* 833.33ns */ - time_hw = I915_READ(reg); } else { - units = 128000; /* 1.28us */ - div = 100000; + /* 833.33ns units on Gen9LP, 1.28us elsewhere. */ + if (IS_GEN9_LP(dev_priv)) { + mul = 10000; + div = 12; + } else { + mul = 1280; + div = 1; + } time_hw = I915_READ(reg); } - intel_runtime_pm_put(dev_priv); - return DIV_ROUND_UP_ULL(time_hw * units, div); + return DIV_ROUND_UP_ULL(time_hw * mul, div); } u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat) -- GitLab From 6060b6aec03c76f9ce0977b70c27429d39d2956e Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 21 Nov 2017 18:18:52 +0000 Subject: [PATCH 0078/2547] drm/i915/pmu: Add RC6 residency metrics For clients like intel-gpu-overlay it is easier to read the counters via the perf API than having to parse sysfs. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-9-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_pmu.c | 31 +++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 6 +++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index fef389ebf92c..1071935bfa67 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -361,6 +361,15 @@ static int i915_pmu_event_init(struct perf_event *event) break; case I915_PMU_INTERRUPTS: break; + case I915_PMU_RC6_RESIDENCY: + if (!HAS_RC6(i915)) + ret = -ENODEV; + break; + case I915_PMU_RC6p_RESIDENCY: + case I915_PMU_RC6pp_RESIDENCY: + if (!HAS_RC6p(i915)) + ret = -ENODEV; + break; default: ret = -ENOENT; break; @@ -413,6 +422,24 @@ static u64 __i915_pmu_event_read(struct perf_event *event) case I915_PMU_INTERRUPTS: val = count_interrupts(i915); break; + case I915_PMU_RC6_RESIDENCY: + intel_runtime_pm_get(i915); + val = intel_rc6_residency_ns(i915, + IS_VALLEYVIEW(i915) ? + VLV_GT_RENDER_RC6 : + GEN6_GT_GFX_RC6); + intel_runtime_pm_put(i915); + break; + case I915_PMU_RC6p_RESIDENCY: + intel_runtime_pm_get(i915); + val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p); + intel_runtime_pm_put(i915); + break; + case I915_PMU_RC6pp_RESIDENCY: + intel_runtime_pm_get(i915); + val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp); + intel_runtime_pm_put(i915); + break; } } @@ -677,6 +704,10 @@ static struct attribute *i915_pmu_events_attrs[] = { I915_EVENT_ATTR(interrupts, I915_PMU_INTERRUPTS), + I915_EVENT(rc6-residency, I915_PMU_RC6_RESIDENCY, "ns"), + I915_EVENT(rc6p-residency, I915_PMU_RC6p_RESIDENCY, "ns"), + I915_EVENT(rc6pp-residency, I915_PMU_RC6pp_RESIDENCY, "ns"), + NULL, }; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index d840ff083520..915a6e85a855 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -141,7 +141,11 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) -#define I915_PMU_LAST I915_PMU_INTERRUPTS +#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) +#define I915_PMU_RC6p_RESIDENCY __I915_PMU_OTHER(4) +#define I915_PMU_RC6pp_RESIDENCY __I915_PMU_OTHER(5) + +#define I915_PMU_LAST I915_PMU_RC6pp_RESIDENCY /* Each region is a minimum of 16k, and there are at most 255 of them. */ -- GitLab From 56986b07d17b4a19416e248aaca9367c241a824b Mon Sep 17 00:00:00 2001 From: Bard Liao Date: Wed, 22 Nov 2017 13:59:19 +0800 Subject: [PATCH 0079/2547] ASoC: rt5645: reset RT5645_AD_DA_MIXER at probe RT5645_AD_DA_MIXER (0x29) register will not be reset to default after SW reset. So we have to write it to its default value in i2c_probe. Signed-off-by: Bard Liao Signed-off-by: Mark Brown --- sound/soc/codecs/rt5645.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c index 5f24df4fae8e..fcd02c2c76f1 100644 --- a/sound/soc/codecs/rt5645.c +++ b/sound/soc/codecs/rt5645.c @@ -3823,6 +3823,8 @@ static int rt5645_i2c_probe(struct i2c_client *i2c, regmap_read(regmap, RT5645_VENDOR_ID, &val); rt5645->v_id = val & 0xff; + regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080); + ret = regmap_register_patch(rt5645->regmap, init_list, ARRAY_SIZE(init_list)); if (ret != 0) -- GitLab From c65c8b0f7a1f90e84c273e111fc9391c50c3c482 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 22 Nov 2017 12:06:00 +0000 Subject: [PATCH 0080/2547] drm/i915/selftests: Use NOWARN for large allocations We may try to do a large kmalloc for the permutation array, falling back to a smaller array/test if the first allocation fails. Since we are intentionally trying a large allocation which may fail, pass __GFP_NOWARN. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103842 Signed-off-by: Chris Wilson Cc: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20171122120600.27025-1-chris@chris-wilson.co.uk Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/selftests/i915_random.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/selftests/i915_random.c b/drivers/gpu/drm/i915/selftests/i915_random.c index b85872cc7fbe..2088ae57aa89 100644 --- a/drivers/gpu/drm/i915/selftests/i915_random.c +++ b/drivers/gpu/drm/i915/selftests/i915_random.c @@ -57,7 +57,7 @@ unsigned int *i915_random_order(unsigned int count, struct rnd_state *state) { unsigned int *order, i; - order = kmalloc_array(count, sizeof(*order), GFP_KERNEL); + order = kmalloc_array(count, sizeof(*order), GFP_KERNEL | __GFP_NOWARN); if (!order) return order; -- GitLab From 62d0fe45297d213ba923e252dcdbcee6f41a3bc6 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 22 Nov 2017 14:56:46 +0000 Subject: [PATCH 0081/2547] drm/i915: Remove success dmesg noise for intel_rotate_pages() During selftesting intel_rotate_pages() is very, very verbose without giving us any information. Suppress the noise. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20171122145646.1859-1-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index e101b9a98957..41a203e0c160 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3737,9 +3737,6 @@ intel_rotate_pages(struct intel_rotation_info *rot_info, rot_info->plane[i].stride, st, sg); } - DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n", - obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); - kvfree(page_addr_list); return st; @@ -3749,8 +3746,8 @@ intel_rotate_pages(struct intel_rotation_info *rot_info, err_st_alloc: kvfree(page_addr_list); - DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", - obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); + DRM_DEBUG_DRIVER("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", + obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); return ERR_PTR(ret); } -- GitLab From ee48700dd57d9ce783ec40f035b324d0b75632e4 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 22 Nov 2017 17:26:21 +0000 Subject: [PATCH 0082/2547] drm/i915: Call i915_gem_init_userptr() before taking struct_mutex We don't need struct_mutex to initialise userptr (it just allocates a workqueue for itself etc), but we do need struct_mutex later on in i915_gem_init() in order to feed requests onto the HW. This should break the chain [ 385.697902] ====================================================== [ 385.697907] WARNING: possible circular locking dependency detected [ 385.697913] 4.14.0-CI-Patchwork_7234+ #1 Tainted: G U [ 385.697917] ------------------------------------------------------ [ 385.697922] perf_pmu/2631 is trying to acquire lock: [ 385.697927] (&mm->mmap_sem){++++}, at: [] __might_fault+0x3e/0x90 [ 385.697941] but task is already holding lock: [ 385.697946] (&cpuctx_mutex){+.+.}, at: [] perf_event_ctx_lock_nested+0xbc/0x1d0 [ 385.697957] which lock already depends on the new lock. [ 385.697963] the existing dependency chain (in reverse order) is: [ 385.697970] -> #4 (&cpuctx_mutex){+.+.}: [ 385.697980] __mutex_lock+0x86/0x9b0 [ 385.697985] perf_event_init_cpu+0x5a/0x90 [ 385.697991] perf_event_init+0x178/0x1a4 [ 385.697997] start_kernel+0x27f/0x3f1 [ 385.698003] verify_cpu+0x0/0xfb [ 385.698006] -> #3 (pmus_lock){+.+.}: [ 385.698015] __mutex_lock+0x86/0x9b0 [ 385.698020] perf_event_init_cpu+0x21/0x90 [ 385.698025] cpuhp_invoke_callback+0xca/0xc00 [ 385.698030] _cpu_up+0xa7/0x170 [ 385.698035] do_cpu_up+0x57/0x70 [ 385.698039] smp_init+0x62/0xa6 [ 385.698044] kernel_init_freeable+0x97/0x193 [ 385.698050] kernel_init+0xa/0x100 [ 385.698055] ret_from_fork+0x27/0x40 [ 385.698058] -> #2 (cpu_hotplug_lock.rw_sem){++++}: [ 385.698068] cpus_read_lock+0x39/0xa0 [ 385.698073] apply_workqueue_attrs+0x12/0x50 [ 385.698078] __alloc_workqueue_key+0x1d8/0x4d8 [ 385.698134] i915_gem_init_userptr+0x5f/0x80 [i915] [ 385.698176] i915_gem_init+0x7c/0x390 [i915] [ 385.698213] i915_driver_load+0x99e/0x15c0 [i915] [ 385.698250] i915_pci_probe+0x33/0x90 [i915] [ 385.698256] pci_device_probe+0xa1/0x130 [ 385.698262] driver_probe_device+0x293/0x440 [ 385.698267] __driver_attach+0xde/0xe0 [ 385.698272] bus_for_each_dev+0x5c/0x90 [ 385.698277] bus_add_driver+0x16d/0x260 [ 385.698282] driver_register+0x57/0xc0 [ 385.698287] do_one_initcall+0x3e/0x160 [ 385.698292] do_init_module+0x5b/0x1fa [ 385.698297] load_module+0x2374/0x2dc0 [ 385.698302] SyS_finit_module+0xaa/0xe0 [ 385.698307] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 385.698311] -> #1 (&dev->struct_mutex){+.+.}: [ 385.698320] __mutex_lock+0x86/0x9b0 [ 385.698361] i915_mutex_lock_interruptible+0x4c/0x130 [i915] [ 385.698403] i915_gem_fault+0x206/0x760 [i915] [ 385.698409] __do_fault+0x1a/0x70 [ 385.698413] __handle_mm_fault+0x7c4/0xdb0 [ 385.698417] handle_mm_fault+0x154/0x300 [ 385.698440] __do_page_fault+0x2d6/0x570 [ 385.698445] page_fault+0x22/0x30 [ 385.698449] -> #0 (&mm->mmap_sem){++++}: [ 385.698459] lock_acquire+0xaf/0x200 [ 385.698464] __might_fault+0x68/0x90 [ 385.698470] _copy_to_user+0x1e/0x70 [ 385.698475] perf_read+0x1aa/0x290 [ 385.698480] __vfs_read+0x23/0x120 [ 385.698484] vfs_read+0xa3/0x150 [ 385.698488] SyS_read+0x45/0xb0 [ 385.698493] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 385.698497] other info that might help us debug this: [ 385.698505] Chain exists of: &mm->mmap_sem --> pmus_lock --> &cpuctx_mutex [ 385.698517] Possible unsafe locking scenario: [ 385.698522] CPU0 CPU1 [ 385.698526] ---- ---- [ 385.698529] lock(&cpuctx_mutex); [ 385.698553] lock(pmus_lock); [ 385.698558] lock(&cpuctx_mutex); [ 385.698564] lock(&mm->mmap_sem); [ 385.698568] *** DEADLOCK *** [ 385.698574] 1 lock held by perf_pmu/2631: [ 385.698578] #0: (&cpuctx_mutex){+.+.}, at: [] perf_event_ctx_lock_nested+0xbc/0x1d0 [ 385.698589] stack backtrace: [ 385.698595] CPU: 3 PID: 2631 Comm: perf_pmu Tainted: G U 4.14.0-CI-Patchwork_7234+ #1 [ 385.698602] Hardware name: /NUC6CAYB, BIOS AYAPLCEL.86A.0040.2017.0619.1722 06/19/2017 [ 385.698609] Call Trace: [ 385.698615] dump_stack+0x5f/0x86 [ 385.698621] print_circular_bug.isra.18+0x1d0/0x2c0 [ 385.698627] __lock_acquire+0x19c3/0x1b60 [ 385.698634] ? generic_exec_single+0x77/0xe0 [ 385.698640] ? lock_acquire+0xaf/0x200 [ 385.698644] lock_acquire+0xaf/0x200 [ 385.698650] ? __might_fault+0x3e/0x90 [ 385.698655] __might_fault+0x68/0x90 [ 385.698660] ? __might_fault+0x3e/0x90 [ 385.698665] _copy_to_user+0x1e/0x70 [ 385.698670] perf_read+0x1aa/0x290 [ 385.698675] __vfs_read+0x23/0x120 [ 385.698682] ? __fget+0x101/0x1f0 [ 385.698686] vfs_read+0xa3/0x150 [ 385.698691] SyS_read+0x45/0xb0 [ 385.698696] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 385.698701] RIP: 0033:0x7ff1c46876ed [ 385.698705] RSP: 002b:00007fff13552f90 EFLAGS: 00000293 ORIG_RAX: 0000000000000000 [ 385.698712] RAX: ffffffffffffffda RBX: ffffc90000647ff0 RCX: 00007ff1c46876ed [ 385.698718] RDX: 0000000000000010 RSI: 00007fff13552fa0 RDI: 0000000000000005 [ 385.698723] RBP: 000056063d300580 R08: 0000000000000000 R09: 0000000000000060 [ 385.698729] R10: 0000000000000000 R11: 0000000000000293 R12: 0000000000000046 [ 385.698734] R13: 00007fff13552c6f R14: 00007ff1c6279d00 R15: 00007ff1c6279a40 Testcase: igt/perf_pmu Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20171122172621.16158-1-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 21ca680e9e63..e03d6c2554e2 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5116,8 +5116,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv) { int ret; - mutex_lock(&dev_priv->drm.struct_mutex); - /* * We need to fallback to 4K pages since gvt gtt handling doesn't * support huge page entries - we will need to check either hypervisor @@ -5137,18 +5135,19 @@ int i915_gem_init(struct drm_i915_private *dev_priv) dev_priv->gt.cleanup_engine = intel_engine_cleanup; } + ret = i915_gem_init_userptr(dev_priv); + if (ret) + return ret; + /* This is just a security blanket to placate dragons. * On some systems, we very sporadically observe that the first TLBs * used by the CS may be stale, despite us poking the TLB reset. If * we hold the forcewake during initialisation these problems * just magically go away. */ + mutex_lock(&dev_priv->drm.struct_mutex); intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); - ret = i915_gem_init_userptr(dev_priv); - if (ret) - goto out_unlock; - ret = i915_gem_init_ggtt(dev_priv); if (ret) goto out_unlock; -- GitLab From b4e3c935b2313b3e557066b630efd0367c7fb34c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 22 Nov 2017 22:25:10 +0000 Subject: [PATCH 0083/2547] drm/i915: Save/restore irq state for vlv_residency_raw() Since commit 6060b6aec03c ("drm/i915/pmu: Add RC6 residency metrics"), vlv_residency_raw() may be called from an irq-disabled context (via perf event sampling on remote cpu). As such, we can no longer assume that we are called from process context and must save/restore the irq state for the spinlock. Fixes: 6060b6aec03c ("drm/i915/pmu: Add RC6 residency metrics") Testcase: igt/perf_pmu/other-init-3 Signed-off-by: Chris Wilson Cc: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171122222510.22627-1-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_pm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7d41aad79166..03d67d8ab647 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -9396,12 +9396,13 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv, const i915_reg_t reg) { u32 lower, upper, tmp; + unsigned long flags; int loop = 2; /* The register accessed do not need forcewake. We borrow * uncore lock to prevent concurrent access to range reg. */ - spin_lock_irq(&dev_priv->uncore.lock); + spin_lock_irqsave(&dev_priv->uncore.lock, flags); /* vlv and chv residency counters are 40 bits in width. * With a control bit, we can choose between upper or lower @@ -9432,7 +9433,7 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv, * now. */ - spin_unlock_irq(&dev_priv->uncore.lock); + spin_unlock_irqrestore(&dev_priv->uncore.lock, flags); return lower | (u64)upper << 8; } @@ -9451,7 +9452,6 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, mul = 1000000; div = dev_priv->czclk_freq; time_hw = vlv_residency_raw(dev_priv, reg); - } else { /* 833.33ns units on Gen9LP, 1.28us elsewhere. */ if (IS_GEN9_LP(dev_priv)) { -- GitLab From 4f0aa1fa3e3849caee450ee5d14fcc289cf16703 Mon Sep 17 00:00:00 2001 From: Anusha Srivatsa Date: Thu, 9 Nov 2017 10:51:43 -0800 Subject: [PATCH 0084/2547] drm/i915/dmc: DMC 1.04 for Kabylake There is a new version of DMC available for KBL. The release notes mentions: 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption. v2: Remove pull request from commit message (Rodrigo). Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa Reviewed-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/1510253503-12634-1-git-send-email-anusha.srivatsa@intel.com --- drivers/gpu/drm/i915/intel_csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 77d8b3d483ca..07e4f7bc4412 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -40,9 +40,9 @@ #define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" #define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6) -#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" +#define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin" MODULE_FIRMWARE(I915_CSR_KBL); -#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1) +#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin" MODULE_FIRMWARE(I915_CSR_SKL); -- GitLab From b552ae444e454eb3254c958e05b69820c0ef346d Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 23 Nov 2017 10:07:01 +0000 Subject: [PATCH 0085/2547] drm/i915/pmu: Drop I915_ENGINE_SAMPLE_MAX from uapi headers We have agreed during the engine classes discussion that fields marked as non-ABI are better left out altogether from uapi headers. v2: Use a local define for maintanability. (Chris Wilson) Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171123100701.18430-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + include/uapi/drm/i915_drm.h | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 43473e6d1a4f..d38d059285dc 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -358,6 +358,7 @@ struct intel_engine_cs { * * Our internal timer stores the current counters in this field. */ +#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SEMA + 1) struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX]; /** * @busy_stats: Has enablement of engine stats tracking been diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 915a6e85a855..239e8633edc9 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -110,8 +110,7 @@ enum drm_i915_gem_engine_class { enum drm_i915_pmu_engine_sample { I915_SAMPLE_BUSY = 0, I915_SAMPLE_WAIT = 1, - I915_SAMPLE_SEMA = 2, - I915_ENGINE_SAMPLE_MAX /* non-ABI */ + I915_SAMPLE_SEMA = 2 }; #define I915_PMU_SAMPLE_BITS (4) -- GitLab From fbba5559d91e812db0fd446fb383a37fde48b1cb Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 23 Nov 2017 10:26:54 +0000 Subject: [PATCH 0086/2547] drm/i915/pmu: Clear the previous sample value when parking When turning off the engines, and the pmu sampling, clear the previous value as the current measurement should be 0. v2: Use a for-loop v3: * Move clearing to timer self-dis-arm to avoid race with parking. * Clear frequency samples as well. v4: * Init frequency to idle_freq. (Chris Wilson) Signed-off-by: Tvrtko Ursulin Suggested-by: Chris Wilson Reviewed-by: Chris Wilson (v3) Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171123102654.29296-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_pmu.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 1071935bfa67..6a42e7f7967d 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -262,13 +262,31 @@ static void frequency_sample(struct drm_i915_private *dev_priv) } } +static void pmu_init_previous_samples(struct drm_i915_private *i915) +{ + struct intel_engine_cs *engine; + enum intel_engine_id id; + unsigned int i; + + for_each_engine(engine, i915, id) { + for (i = 0; i < ARRAY_SIZE(engine->pmu.sample); i++) + engine->pmu.sample[i].prev = 0; + } + + for (i = 0; i < ARRAY_SIZE(i915->pmu.sample); i++) + i915->pmu.sample[i].prev = i915->gt_pm.rps.idle_freq; +} + static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) { struct drm_i915_private *i915 = container_of(hrtimer, struct drm_i915_private, pmu.timer); - if (!READ_ONCE(i915->pmu.timer_enabled)) + if (!READ_ONCE(i915->pmu.timer_enabled)) { + pmu_init_previous_samples(i915); + return HRTIMER_NORESTART; + } engines_sample(i915); frequency_sample(i915); @@ -839,6 +857,8 @@ void i915_pmu_register(struct drm_i915_private *i915) hrtimer_init(&i915->pmu.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); i915->pmu.timer.function = i915_sample; + pmu_init_previous_samples(i915); + for_each_engine(engine, i915, id) INIT_DELAYED_WORK(&engine->pmu.disable_busy_stats, __disable_busy_stats); -- GitLab From 42e5e65765265485ecf2a480c244d76c2c624449 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Mon, 13 Nov 2017 17:01:40 +0100 Subject: [PATCH 0087/2547] drm/i915: sync dp link status checks against atomic commmits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Two bits: - check actual atomic state, the legacy stuff can only be looked at from within the atomic_commit_tail function, since it's only protected by ordering and not by any locks. - Make sure we don't wreak the work an ongoing nonblocking commit is doing. v2: We need the crtc lock too, because a plane update might change it without having to acquire the connection_mutex (Maarten). Use Maarten's changes for this locking, while keeping the logic that uses the connection->commit->hw_done signal for syncing with nonblocking commits. v3: The initial state objects from the hw state readout do not have a commit object. Check for that (spotted by CI). v4: Fix deadlock from jumping to put_power with locks still held. (mlankhorst) Cc: Manasi Navare Cc: Maarten Lankhorst Cc: Ville Syrjälä References: https://bugs.freedesktop.org/show_bug.cgi?id=103336 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99272 Signed-off-by: Daniel Vetter Signed-off-by: Maarten Lankhorst Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171113160140.22679-1-maarten.lankhorst@linux.intel.com --- drivers/gpu/drm/i915/intel_dp.c | 61 +++++++++++++++++++++++++++++---- 1 file changed, 55 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index bc61f38b131d..dd0b3a018792 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4277,6 +4277,8 @@ intel_dp_check_link_status(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; + struct drm_connector_state *conn_state = + intel_dp->attached_connector->base.state; u8 link_status[DP_LINK_STATUS_SIZE]; WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); @@ -4286,10 +4288,16 @@ intel_dp_check_link_status(struct intel_dp *intel_dp) return; } - if (!intel_encoder->base.crtc) + if (!conn_state->crtc) return; - if (!to_intel_crtc(intel_encoder->base.crtc)->active) + WARN_ON(!drm_modeset_is_locked(&conn_state->crtc->mutex)); + + if (!conn_state->crtc->state->active) + return; + + if (conn_state->commit && + !try_wait_for_completion(&conn_state->commit->hw_done)) return; /* @@ -4364,9 +4372,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp) DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); } - drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, NULL); intel_dp_check_link_status(intel_dp); - drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex); + if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { DRM_DEBUG_KMS("Link Training Compliance Test requested\n"); /* Send a Hotplug Uevent to userspace to start modeset */ @@ -4814,8 +4821,19 @@ intel_dp_detect(struct drm_connector *connector, connector->base.id, connector->name); /* If full detect is not performed yet, do a full detect */ - if (!intel_dp->detect_done) + if (!intel_dp->detect_done) { + struct drm_crtc *crtc; + int ret; + + crtc = connector->state->crtc; + if (crtc) { + ret = drm_modeset_lock(&crtc->mutex, ctx); + if (ret) + return ret; + } + status = intel_dp_long_pulse(intel_dp->attached_connector); + } intel_dp->detect_done = false; @@ -5097,7 +5115,38 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) } if (!intel_dp->is_mst) { - if (!intel_dp_short_pulse(intel_dp)) { + struct drm_modeset_acquire_ctx ctx; + struct drm_connector *connector = &intel_dp->attached_connector->base; + struct drm_crtc *crtc; + int iret; + bool handled = false; + + drm_modeset_acquire_init(&ctx, 0); +retry: + iret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx); + if (iret) + goto err; + + crtc = connector->state->crtc; + if (crtc) { + iret = drm_modeset_lock(&crtc->mutex, &ctx); + if (iret) + goto err; + } + + handled = intel_dp_short_pulse(intel_dp); + +err: + if (iret == -EDEADLK) { + drm_modeset_backoff(&ctx); + goto retry; + } + + drm_modeset_drop_locks(&ctx); + drm_modeset_acquire_fini(&ctx); + WARN(iret, "Acquiring modeset locks failed with %i\n", iret); + + if (!handled) { intel_dp->detect_done = false; goto put_power; } -- GitLab From 6a44e1772177ed9f987447bb6c601ee7451eeb52 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 21 Nov 2017 10:42:41 +0100 Subject: [PATCH 0088/2547] drm/i915: remove stale comment from sanitize_encoder MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This goes back to pre-atomic, where due to intermediate dpms states connectors and encoder states might indeed not have matched. With atomic that's all smashed together (and hopefully no bios ever enables a vga output in dpms standby/suspedn state or we're toast). In commit 873ffe69a9097fb241fff2967ea6f0bf2c179195 Author: Maarten Lankhorst Date: Wed Aug 5 12:37:07 2015 +0200 drm/i915: Remove connectors_active from sanitization, v2. sanitize_encoders was changed to disable the encoder in all cases, which made the comment obsolete. Remove the misleading comment. Reported-by: Ville Syrjälä Cc: Ville Syrjälä Cc: Maarten Lankhorst Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171121094241.9129-1-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/intel_display.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5ca7b33554ef..fec267dfc062 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14909,8 +14909,6 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) connector->base.dpms = DRM_MODE_DPMS_OFF; connector->base.encoder = NULL; } - /* Enabled encoders without active connectors will be fixed in - * the crtc fixup. */ } void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) -- GitLab From 621d07b20eb8e7c47381178fc0f5724caa49afcd Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Thu, 23 Nov 2017 13:54:20 +0000 Subject: [PATCH 0089/2547] drm/i915/selftests: rein in igt_write_huge Rather than repeat the test for each engine, which takes a long time, let's try alternating between the engines in some randomized order. v2: fix gen2 blunder fix !order blunder more cunning permutation construction! Suggested-by: Chris Wilson Signed-off-by: Matthew Auld Cc: Chris Wilson Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171123135421.17967-1-matthew.auld@intel.com --- drivers/gpu/drm/i915/selftests/huge_pages.c | 111 ++++++++++++-------- 1 file changed, 66 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c index db7a0a1f2960..83b3a27370a4 100644 --- a/drivers/gpu/drm/i915/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c @@ -27,6 +27,7 @@ #include #include "mock_drm.h" +#include "i915_random.h" static const unsigned int page_sizes[] = { I915_GTT_PAGE_SIZE_2M, @@ -1044,7 +1045,10 @@ static int igt_write_huge(struct i915_gem_context *ctx, { struct drm_i915_private *i915 = to_i915(obj->base.dev); struct i915_address_space *vm = ctx->ppgtt ? &ctx->ppgtt->base : &i915->ggtt.base; + static struct intel_engine_cs *engines[I915_NUM_ENGINES]; struct intel_engine_cs *engine; + I915_RND_STATE(prng); + IGT_TIMEOUT(end_time); struct i915_vma *vma; unsigned int flags = PIN_USER | PIN_OFFSET_FIXED; unsigned int max_page_size; @@ -1052,6 +1056,8 @@ static int igt_write_huge(struct i915_gem_context *ctx, u64 max; u64 num; u64 size; + int *order; + int i, n; int err = 0; GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); @@ -1067,67 +1073,81 @@ static int igt_write_huge(struct i915_gem_context *ctx, if (IS_ERR(vma)) return PTR_ERR(vma); + n = 0; for_each_engine(engine, i915, id) { - IGT_TIMEOUT(end_time); - if (!intel_engine_can_store_dword(engine)) { - pr_info("store-dword-imm not supported on engine=%u\n", - id); + pr_info("store-dword-imm not supported on engine=%u\n", id); continue; } + engines[n++] = engine; + } - /* - * Try various offsets until we timeout -- we want to avoid - * issues hidden by effectively always using offset = 0. - */ - for_each_prime_number_from(num, 0, max) { - u64 offset = num * max_page_size; - u32 dword; + if (!n) + return 0; - err = i915_vma_unbind(vma); - if (err) - goto out_vma_close; + /* + * To keep things interesting when alternating between engines in our + * randomized order, lets also make feeding to the same engine a few + * times in succession a possibility by enlarging the permutation array. + */ + order = i915_random_order(n * I915_NUM_ENGINES, &prng); + if (!order) + return -ENOMEM; - err = i915_vma_pin(vma, size, max_page_size, flags | offset); - if (err) { - /* - * The ggtt may have some pages reserved so - * refrain from erroring out. - */ - if (err == -ENOSPC && i915_is_ggtt(vm)) { - err = 0; - continue; - } + /* + * Try various offsets until we timeout -- we want to avoid + * issues hidden by effectively always using offset = 0. + */ + i = 0; + for_each_prime_number_from(num, 0, max) { + u64 offset = num * max_page_size; + u32 dword; - goto out_vma_close; + err = i915_vma_unbind(vma); + if (err) + goto out_vma_close; + + err = i915_vma_pin(vma, size, max_page_size, flags | offset); + if (err) { + /* + * The ggtt may have some pages reserved so + * refrain from erroring out. + */ + if (err == -ENOSPC && i915_is_ggtt(vm)) { + err = 0; + continue; } - err = igt_check_page_sizes(vma); - if (err) - goto out_vma_unpin; + goto out_vma_close; + } - dword = offset_in_page(num) / 4; + err = igt_check_page_sizes(vma); + if (err) + goto out_vma_unpin; - err = gpu_write(vma, ctx, engine, dword, num + 1); - if (err) { - pr_err("gpu-write failed at offset=%llx", offset); - goto out_vma_unpin; - } + dword = offset_in_page(num) / 4; - err = cpu_check(obj, dword, num + 1); - if (err) { - pr_err("cpu-check failed at offset=%llx", offset); - goto out_vma_unpin; - } + engine = engines[order[i] % n]; + i = (i + 1) % (n * I915_NUM_ENGINES); - i915_vma_unpin(vma); + err = gpu_write(vma, ctx, engine, dword, num + 1); + if (err) { + pr_err("gpu-write failed at offset=%llx", offset); + goto out_vma_unpin; + } - if (num > 0 && - igt_timeout(end_time, - "%s timed out on engine=%u at offset=%llx, max_page_size=%x\n", - __func__, id, offset, max_page_size)) - break; + err = cpu_check(obj, dword, num + 1); + if (err) { + pr_err("cpu-check failed at offset=%llx", offset); + goto out_vma_unpin; } + + i915_vma_unpin(vma); + + if (igt_timeout(end_time, + "%s timed out on engine=%u at offset=%llx, max_page_size=%x\n", + __func__, engine->id, offset, max_page_size)) + break; } out_vma_unpin: @@ -1135,6 +1155,7 @@ static int igt_write_huge(struct i915_gem_context *ctx, i915_vma_unpin(vma); out_vma_close: i915_vma_close(vma); + kfree(order); return err; } -- GitLab From c83a8d4a2ec93c53f78e109dee5e21953485cbfd Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Thu, 23 Nov 2017 13:54:21 +0000 Subject: [PATCH 0090/2547] drm/i915/selftests: test descending addresses For igt_write_huge make sure the higher gtt offsets don't feel left out, which is especially true when dealing with the 48b PPGTT, where we timeout long before we are able exhaust the address space. v2: just use IGT_TIMEOUT Suggested-by: Chris Wilson Signed-off-by: Matthew Auld Cc: Chris Wilson Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171123135421.17967-2-matthew.auld@intel.com --- drivers/gpu/drm/i915/selftests/huge_pages.c | 123 +++++++++++--------- 1 file changed, 70 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c index 83b3a27370a4..df1befe2c793 100644 --- a/drivers/gpu/drm/i915/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c @@ -1040,6 +1040,62 @@ static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val) return err; } +static int __igt_write_huge(struct i915_gem_context *ctx, + struct intel_engine_cs *engine, + struct drm_i915_gem_object *obj, + u64 size, u64 offset, + u32 dword, u32 val) +{ + struct drm_i915_private *i915 = to_i915(obj->base.dev); + struct i915_address_space *vm = ctx->ppgtt ? &ctx->ppgtt->base : &i915->ggtt.base; + unsigned int flags = PIN_USER | PIN_OFFSET_FIXED; + struct i915_vma *vma; + int err; + + vma = i915_vma_instance(obj, vm, NULL); + if (IS_ERR(vma)) + return PTR_ERR(vma); + + err = i915_vma_unbind(vma); + if (err) + goto out_vma_close; + + err = i915_vma_pin(vma, size, 0, flags | offset); + if (err) { + /* + * The ggtt may have some pages reserved so + * refrain from erroring out. + */ + if (err == -ENOSPC && i915_is_ggtt(vm)) + err = 0; + + goto out_vma_close; + } + + err = igt_check_page_sizes(vma); + if (err) + goto out_vma_unpin; + + err = gpu_write(vma, ctx, engine, dword, val); + if (err) { + pr_err("gpu-write failed at offset=%llx\n", offset); + goto out_vma_unpin; + } + + err = cpu_check(obj, dword, val); + if (err) { + pr_err("cpu-check failed at offset=%llx\n", offset); + goto out_vma_unpin; + } + +out_vma_unpin: + i915_vma_unpin(vma); +out_vma_close: + i915_vma_close(vma); + + return err; +} + static int igt_write_huge(struct i915_gem_context *ctx, struct drm_i915_gem_object *obj) { @@ -1049,8 +1105,6 @@ static int igt_write_huge(struct i915_gem_context *ctx, struct intel_engine_cs *engine; I915_RND_STATE(prng); IGT_TIMEOUT(end_time); - struct i915_vma *vma; - unsigned int flags = PIN_USER | PIN_OFFSET_FIXED; unsigned int max_page_size; unsigned int id; u64 max; @@ -1069,10 +1123,6 @@ static int igt_write_huge(struct i915_gem_context *ctx, max_page_size = rounddown_pow_of_two(obj->mm.page_sizes.sg); max = div_u64((vm->total - size), max_page_size); - vma = i915_vma_instance(obj, vm, NULL); - if (IS_ERR(vma)) - return PTR_ERR(vma); - n = 0; for_each_engine(engine, i915, id) { if (!intel_engine_can_store_dword(engine)) { @@ -1095,66 +1145,33 @@ static int igt_write_huge(struct i915_gem_context *ctx, return -ENOMEM; /* - * Try various offsets until we timeout -- we want to avoid - * issues hidden by effectively always using offset = 0. + * Try various offsets in an ascending/descending fashion until we + * timeout -- we want to avoid issues hidden by effectively always using + * offset = 0. */ i = 0; for_each_prime_number_from(num, 0, max) { - u64 offset = num * max_page_size; - u32 dword; - - err = i915_vma_unbind(vma); - if (err) - goto out_vma_close; - - err = i915_vma_pin(vma, size, max_page_size, flags | offset); - if (err) { - /* - * The ggtt may have some pages reserved so - * refrain from erroring out. - */ - if (err == -ENOSPC && i915_is_ggtt(vm)) { - err = 0; - continue; - } - - goto out_vma_close; - } - - err = igt_check_page_sizes(vma); - if (err) - goto out_vma_unpin; - - dword = offset_in_page(num) / 4; + u64 offset_low = num * max_page_size; + u64 offset_high = (max - num) * max_page_size; + u32 dword = offset_in_page(num) / 4; engine = engines[order[i] % n]; i = (i + 1) % (n * I915_NUM_ENGINES); - err = gpu_write(vma, ctx, engine, dword, num + 1); - if (err) { - pr_err("gpu-write failed at offset=%llx", offset); - goto out_vma_unpin; - } - - err = cpu_check(obj, dword, num + 1); - if (err) { - pr_err("cpu-check failed at offset=%llx", offset); - goto out_vma_unpin; - } + err = __igt_write_huge(ctx, engine, obj, size, offset_low, dword, num + 1); + if (err) + break; - i915_vma_unpin(vma); + err = __igt_write_huge(ctx, engine, obj, size, offset_high, dword, num + 1); + if (err) + break; if (igt_timeout(end_time, - "%s timed out on engine=%u at offset=%llx, max_page_size=%x\n", - __func__, engine->id, offset, max_page_size)) + "%s timed out on engine=%u, offset_low=%llx offset_high=%llx, max_page_size=%x\n", + __func__, engine->id, offset_low, offset_high, max_page_size)) break; } -out_vma_unpin: - if (i915_vma_is_pinned(vma)) - i915_vma_unpin(vma); -out_vma_close: - i915_vma_close(vma); kfree(order); return err; -- GitLab From b1c24a6137af11fca49192a42face03cacbd7fc5 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 23 Nov 2017 15:26:30 +0000 Subject: [PATCH 0091/2547] drm/i915: Unwind incomplete legacy context switches The legacy context switch for ringbuffer submission is multistaged, where each of those stages may fail. However, we were updating global state after some stages, and so we had to force the incomplete request to be submitted because we could not unwind. Save the global state before performing the switches, and so enable us to unwind back to the previous global state should any phase fail. We then must cancel the request instead of submitting it should the construction fail. v2: s/saved_ctx/from_ctx/; s/ctx/to_ctx/ etc. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171123152631.31385-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem_context.c | 173 ++++++++---------------- drivers/gpu/drm/i915/i915_gem_request.c | 18 +-- drivers/gpu/drm/i915/intel_ringbuffer.c | 1 + drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + 4 files changed, 65 insertions(+), 128 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 6ca56e482d79..da4a64b3484c 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -507,6 +507,7 @@ void i915_gem_contexts_lost(struct drm_i915_private *dev_priv) for_each_engine(engine, dev_priv, id) { engine->legacy_active_context = NULL; + engine->legacy_active_ppgtt = NULL; if (!engine->last_retired_context) continue; @@ -681,68 +682,49 @@ static int remap_l3(struct drm_i915_gem_request *req, int slice) return 0; } -static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt, - struct intel_engine_cs *engine, - struct i915_gem_context *to) -{ - if (to->remap_slice) - return false; - - if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) - return false; - - return to == engine->legacy_active_context; -} - -static bool -needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, struct intel_engine_cs *engine) -{ - struct i915_gem_context *from = engine->legacy_active_context; - - if (!ppgtt) - return false; - - /* Always load the ppgtt on first use */ - if (!from) - return true; - - /* Same context without new entries, skip */ - if ((!from->ppgtt || from->ppgtt == ppgtt) && - !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) - return false; - - if (engine->id != RCS) - return true; - - return true; -} - -static int do_rcs_switch(struct drm_i915_gem_request *req) +/** + * i915_switch_context() - perform a GPU context switch. + * @rq: request for which we'll execute the context switch + * + * The context life cycle is simple. The context refcount is incremented and + * decremented by 1 on create and destroy. If the context is in use by the GPU, + * it will have a refcount > 1. This allows us to destroy the context abstract + * object while letting the normal object tracking destroy the backing BO. + * + * This function should not be used in execlists mode. Instead the context is + * switched by writing to the ELSP and requests keep a reference to their + * context. + */ +int i915_switch_context(struct drm_i915_gem_request *rq) { - struct i915_gem_context *to = req->ctx; - struct intel_engine_cs *engine = req->engine; - struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; - struct i915_gem_context *from = engine->legacy_active_context; - u32 hw_flags; + struct intel_engine_cs *engine = rq->engine; + struct i915_gem_context *to_ctx = rq->ctx; + struct i915_hw_ppgtt *to_mm = + to_ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; + struct i915_gem_context *from_ctx = engine->legacy_active_context; + struct i915_hw_ppgtt *from_mm = engine->legacy_active_ppgtt; + u32 hw_flags = 0; int ret, i; - GEM_BUG_ON(engine->id != RCS); + lockdep_assert_held(&rq->i915->drm.struct_mutex); + GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); - if (skip_rcs_switch(ppgtt, engine, to)) - return 0; - - if (needs_pd_load_pre(ppgtt, engine)) { - /* Older GENs and non render rings still want the load first, - * "PP_DCLV followed by PP_DIR_BASE register through Load - * Register Immediate commands in Ring Buffer before submitting - * a context."*/ - trace_switch_mm(engine, to); - ret = ppgtt->switch_mm(ppgtt, req); + if (to_mm != from_mm || + (to_mm && intel_engine_flag(engine) & to_mm->pd_dirty_rings)) { + trace_switch_mm(engine, to_ctx); + ret = to_mm->switch_mm(to_mm, rq); if (ret) - return ret; + goto err; + + to_mm->pd_dirty_rings &= ~intel_engine_flag(engine); + engine->legacy_active_ppgtt = to_mm; + hw_flags = MI_FORCE_RESTORE; } - if (i915_gem_context_is_kernel(to)) + if (to_ctx->engine[engine->id].state && + (to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) { + GEM_BUG_ON(engine->id != RCS); + /* * The kernel context(s) is treated as pure scratch and is not * expected to retain any state (as we sacrifice it during @@ -750,78 +732,37 @@ static int do_rcs_switch(struct drm_i915_gem_request *req) * as nothing actually executes using the kernel context; it * is purely used for flushing user contexts. */ - hw_flags = MI_RESTORE_INHIBIT; - else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings) - hw_flags = MI_FORCE_RESTORE; - else - hw_flags = 0; + if (i915_gem_context_is_kernel(to_ctx)) + hw_flags = MI_RESTORE_INHIBIT; - if (to != from || (hw_flags & MI_FORCE_RESTORE)) { - ret = mi_set_context(req, hw_flags); + ret = mi_set_context(rq, hw_flags); if (ret) - return ret; + goto err_mm; - engine->legacy_active_context = to; + engine->legacy_active_context = to_ctx; } - if (ppgtt) - ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); + if (to_ctx->remap_slice) { + for (i = 0; i < MAX_L3_SLICES; i++) { + if (!(to_ctx->remap_slice & BIT(i))) + continue; - for (i = 0; i < MAX_L3_SLICES; i++) { - if (!(to->remap_slice & (1<remap_slice &= ~(1< 1. This allows us to destroy the context abstract - * object while letting the normal object tracking destroy the backing BO. - * - * This function should not be used in execlists mode. Instead the context is - * switched by writing to the ELSP and requests keep a reference to their - * context. - */ -int i915_switch_context(struct drm_i915_gem_request *req) -{ - struct intel_engine_cs *engine = req->engine; - - lockdep_assert_held(&req->i915->drm.struct_mutex); - GEM_BUG_ON(HAS_EXECLISTS(req->i915)); - - if (!req->ctx->engine[engine->id].state) { - struct i915_gem_context *to = req->ctx; - struct i915_hw_ppgtt *ppgtt = - to->ppgtt ?: req->i915->mm.aliasing_ppgtt; - - if (needs_pd_load_pre(ppgtt, engine)) { - int ret; - - trace_switch_mm(engine, to); - ret = ppgtt->switch_mm(ppgtt, req); + ret = remap_l3(rq, i); if (ret) - return ret; - - ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); + goto err_ctx; } - engine->legacy_active_context = to; - return 0; + to_ctx->remap_slice = 0; } - return do_rcs_switch(req); + return 0; + +err_ctx: + engine->legacy_active_context = from_ctx; +err_mm: + engine->legacy_active_ppgtt = from_mm; +err: + return ret; } static bool engine_has_idle_kernel_context(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 7325469ce754..a90bdd26571f 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -719,25 +719,19 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, /* Unconditionally invalidate GPU caches and TLBs. */ ret = engine->emit_flush(req, EMIT_INVALIDATE); if (ret) - goto err_ctx; + goto err_unwind; ret = engine->request_alloc(req); - if (ret) { - /* - * Past the point-of-no-return. Since we may have updated - * global state after partially completing the request alloc, - * we need to commit any commands so far emitted in the - * request to the HW. - */ - __i915_add_request(req, false); - return ERR_PTR(ret); - } + if (ret) + goto err_unwind; /* Check that we didn't interrupt ourselves with a new request */ GEM_BUG_ON(req->timeline->seqno != req->fence.seqno); return req; -err_ctx: +err_unwind: + req->ring->emit = req->head; + /* Make sure we didn't add ourselves to external state before freeing */ GEM_BUG_ON(!list_empty(&req->active_list)); GEM_BUG_ON(!list_empty(&req->priotree.signalers_list)); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index bfa11a84e476..a904b0353bec 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -591,6 +591,7 @@ static void reset_ring_common(struct intel_engine_cs *engine, request->ring->head = request->postfix; } else { engine->legacy_active_context = NULL; + engine->legacy_active_ppgtt = NULL; } } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index d38d059285dc..ef304c99954c 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -531,6 +531,7 @@ struct intel_engine_cs { * stream (ring). */ struct i915_gem_context *legacy_active_context; + struct i915_hw_ppgtt *legacy_active_ppgtt; /* status_notifier: list of callbacks for context-switch changes */ struct atomic_notifier_head context_status_notifier; -- GitLab From 8911a31c813275882fdc15554235a914e678759e Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 23 Nov 2017 15:26:31 +0000 Subject: [PATCH 0092/2547] drm/i915: Move mi_set_context() into the legacy ringbuffer submission The legacy i915_switch_context() is only applicable to the legacy ringbuffer submission method, so move it from the general i915_gem_context.c to intel_ringbuffer.c (rename pending!). Signed-off-by: Chris Wilson Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171123152631.31385-2-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem_context.c | 198 ------------------------ drivers/gpu/drm/i915/intel_ringbuffer.c | 186 +++++++++++++++++++++- 2 files changed, 185 insertions(+), 199 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index da4a64b3484c..aee0f6d72d33 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -567,204 +567,6 @@ void i915_gem_context_close(struct drm_file *file) idr_destroy(&file_priv->context_idr); } -static inline int -mi_set_context(struct drm_i915_gem_request *req, u32 flags) -{ - struct drm_i915_private *dev_priv = req->i915; - struct intel_engine_cs *engine = req->engine; - enum intel_engine_id id; - const int num_rings = - /* Use an extended w/a on gen7 if signalling from other rings */ - (HAS_LEGACY_SEMAPHORES(dev_priv) && IS_GEN7(dev_priv)) ? - INTEL_INFO(dev_priv)->num_rings - 1 : - 0; - int len; - u32 *cs; - - flags |= MI_MM_SPACE_GTT; - if (IS_HASWELL(dev_priv)) - /* These flags are for resource streamer on HSW+ */ - flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; - else - flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; - - len = 4; - if (IS_GEN7(dev_priv)) - len += 2 + (num_rings ? 4*num_rings + 6 : 0); - - cs = intel_ring_begin(req, len); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ - if (IS_GEN7(dev_priv)) { - *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; - if (num_rings) { - struct intel_engine_cs *signaller; - - *cs++ = MI_LOAD_REGISTER_IMM(num_rings); - for_each_engine(signaller, dev_priv, id) { - if (signaller == engine) - continue; - - *cs++ = i915_mmio_reg_offset( - RING_PSMI_CTL(signaller->mmio_base)); - *cs++ = _MASKED_BIT_ENABLE( - GEN6_PSMI_SLEEP_MSG_DISABLE); - } - } - } - - *cs++ = MI_NOOP; - *cs++ = MI_SET_CONTEXT; - *cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags; - /* - * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP - * WaMiSetContext_Hang:snb,ivb,vlv - */ - *cs++ = MI_NOOP; - - if (IS_GEN7(dev_priv)) { - if (num_rings) { - struct intel_engine_cs *signaller; - i915_reg_t last_reg = {}; /* keep gcc quiet */ - - *cs++ = MI_LOAD_REGISTER_IMM(num_rings); - for_each_engine(signaller, dev_priv, id) { - if (signaller == engine) - continue; - - last_reg = RING_PSMI_CTL(signaller->mmio_base); - *cs++ = i915_mmio_reg_offset(last_reg); - *cs++ = _MASKED_BIT_DISABLE( - GEN6_PSMI_SLEEP_MSG_DISABLE); - } - - /* Insert a delay before the next switch! */ - *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; - *cs++ = i915_mmio_reg_offset(last_reg); - *cs++ = i915_ggtt_offset(engine->scratch); - *cs++ = MI_NOOP; - } - *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; - } - - intel_ring_advance(req, cs); - - return 0; -} - -static int remap_l3(struct drm_i915_gem_request *req, int slice) -{ - u32 *cs, *remap_info = req->i915->l3_parity.remap_info[slice]; - int i; - - if (!remap_info) - return 0; - - cs = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* - * Note: We do not worry about the concurrent register cacheline hang - * here because no other code should access these registers other than - * at initialization time. - */ - *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); - for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { - *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); - *cs++ = remap_info[i]; - } - *cs++ = MI_NOOP; - intel_ring_advance(req, cs); - - return 0; -} - -/** - * i915_switch_context() - perform a GPU context switch. - * @rq: request for which we'll execute the context switch - * - * The context life cycle is simple. The context refcount is incremented and - * decremented by 1 on create and destroy. If the context is in use by the GPU, - * it will have a refcount > 1. This allows us to destroy the context abstract - * object while letting the normal object tracking destroy the backing BO. - * - * This function should not be used in execlists mode. Instead the context is - * switched by writing to the ELSP and requests keep a reference to their - * context. - */ -int i915_switch_context(struct drm_i915_gem_request *rq) -{ - struct intel_engine_cs *engine = rq->engine; - struct i915_gem_context *to_ctx = rq->ctx; - struct i915_hw_ppgtt *to_mm = - to_ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; - struct i915_gem_context *from_ctx = engine->legacy_active_context; - struct i915_hw_ppgtt *from_mm = engine->legacy_active_ppgtt; - u32 hw_flags = 0; - int ret, i; - - lockdep_assert_held(&rq->i915->drm.struct_mutex); - GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); - - if (to_mm != from_mm || - (to_mm && intel_engine_flag(engine) & to_mm->pd_dirty_rings)) { - trace_switch_mm(engine, to_ctx); - ret = to_mm->switch_mm(to_mm, rq); - if (ret) - goto err; - - to_mm->pd_dirty_rings &= ~intel_engine_flag(engine); - engine->legacy_active_ppgtt = to_mm; - hw_flags = MI_FORCE_RESTORE; - } - - if (to_ctx->engine[engine->id].state && - (to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) { - GEM_BUG_ON(engine->id != RCS); - - /* - * The kernel context(s) is treated as pure scratch and is not - * expected to retain any state (as we sacrifice it during - * suspend and on resume it may be corrupted). This is ok, - * as nothing actually executes using the kernel context; it - * is purely used for flushing user contexts. - */ - if (i915_gem_context_is_kernel(to_ctx)) - hw_flags = MI_RESTORE_INHIBIT; - - ret = mi_set_context(rq, hw_flags); - if (ret) - goto err_mm; - - engine->legacy_active_context = to_ctx; - } - - if (to_ctx->remap_slice) { - for (i = 0; i < MAX_L3_SLICES; i++) { - if (!(to_ctx->remap_slice & BIT(i))) - continue; - - ret = remap_l3(rq, i); - if (ret) - goto err_ctx; - } - - to_ctx->remap_slice = 0; - } - - return 0; - -err_ctx: - engine->legacy_active_context = from_ctx; -err_mm: - engine->legacy_active_ppgtt = from_mm; -err: - return ret; -} - static bool engine_has_idle_kernel_context(struct intel_engine_cs *engine) { struct i915_gem_timeline *timeline; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a904b0353bec..e2085820b586 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1385,6 +1385,190 @@ void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) intel_ring_reset(engine->buffer, 0); } +static inline int mi_set_context(struct drm_i915_gem_request *rq, u32 flags) +{ + struct drm_i915_private *i915 = rq->i915; + struct intel_engine_cs *engine = rq->engine; + enum intel_engine_id id; + const int num_rings = + /* Use an extended w/a on gen7 if signalling from other rings */ + (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ? + INTEL_INFO(i915)->num_rings - 1 : + 0; + int len; + u32 *cs; + + flags |= MI_MM_SPACE_GTT; + if (IS_HASWELL(i915)) + /* These flags are for resource streamer on HSW+ */ + flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; + else + flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; + + len = 4; + if (IS_GEN7(i915)) + len += 2 + (num_rings ? 4*num_rings + 6 : 0); + + cs = intel_ring_begin(rq, len); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ + if (IS_GEN7(i915)) { + *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; + if (num_rings) { + struct intel_engine_cs *signaller; + + *cs++ = MI_LOAD_REGISTER_IMM(num_rings); + for_each_engine(signaller, i915, id) { + if (signaller == engine) + continue; + + *cs++ = i915_mmio_reg_offset( + RING_PSMI_CTL(signaller->mmio_base)); + *cs++ = _MASKED_BIT_ENABLE( + GEN6_PSMI_SLEEP_MSG_DISABLE); + } + } + } + + *cs++ = MI_NOOP; + *cs++ = MI_SET_CONTEXT; + *cs++ = i915_ggtt_offset(rq->ctx->engine[RCS].state) | flags; + /* + * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP + * WaMiSetContext_Hang:snb,ivb,vlv + */ + *cs++ = MI_NOOP; + + if (IS_GEN7(i915)) { + if (num_rings) { + struct intel_engine_cs *signaller; + i915_reg_t last_reg = {}; /* keep gcc quiet */ + + *cs++ = MI_LOAD_REGISTER_IMM(num_rings); + for_each_engine(signaller, i915, id) { + if (signaller == engine) + continue; + + last_reg = RING_PSMI_CTL(signaller->mmio_base); + *cs++ = i915_mmio_reg_offset(last_reg); + *cs++ = _MASKED_BIT_DISABLE( + GEN6_PSMI_SLEEP_MSG_DISABLE); + } + + /* Insert a delay before the next switch! */ + *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; + *cs++ = i915_mmio_reg_offset(last_reg); + *cs++ = i915_ggtt_offset(engine->scratch); + *cs++ = MI_NOOP; + } + *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; + } + + intel_ring_advance(rq, cs); + + return 0; +} + +static int remap_l3(struct drm_i915_gem_request *rq, int slice) +{ + u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; + int i; + + if (!remap_info) + return 0; + + cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + /* + * Note: We do not worry about the concurrent register cacheline hang + * here because no other code should access these registers other than + * at initialization time. + */ + *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); + for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { + *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); + *cs++ = remap_info[i]; + } + *cs++ = MI_NOOP; + intel_ring_advance(rq, cs); + + return 0; +} + +static int switch_context(struct drm_i915_gem_request *rq) +{ + struct intel_engine_cs *engine = rq->engine; + struct i915_gem_context *to_ctx = rq->ctx; + struct i915_hw_ppgtt *to_mm = + to_ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; + struct i915_gem_context *from_ctx = engine->legacy_active_context; + struct i915_hw_ppgtt *from_mm = engine->legacy_active_ppgtt; + u32 hw_flags = 0; + int ret, i; + + lockdep_assert_held(&rq->i915->drm.struct_mutex); + GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); + + if (to_mm != from_mm || + (to_mm && intel_engine_flag(engine) & to_mm->pd_dirty_rings)) { + trace_switch_mm(engine, to_ctx); + ret = to_mm->switch_mm(to_mm, rq); + if (ret) + goto err; + + to_mm->pd_dirty_rings &= ~intel_engine_flag(engine); + engine->legacy_active_ppgtt = to_mm; + hw_flags = MI_FORCE_RESTORE; + } + + if (to_ctx->engine[engine->id].state && + (to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) { + GEM_BUG_ON(engine->id != RCS); + + /* + * The kernel context(s) is treated as pure scratch and is not + * expected to retain any state (as we sacrifice it during + * suspend and on resume it may be corrupted). This is ok, + * as nothing actually executes using the kernel context; it + * is purely used for flushing user contexts. + */ + if (i915_gem_context_is_kernel(to_ctx)) + hw_flags = MI_RESTORE_INHIBIT; + + ret = mi_set_context(rq, hw_flags); + if (ret) + goto err_mm; + + engine->legacy_active_context = to_ctx; + } + + if (to_ctx->remap_slice) { + for (i = 0; i < MAX_L3_SLICES; i++) { + if (!(to_ctx->remap_slice & BIT(i))) + continue; + + ret = remap_l3(rq, i); + if (ret) + goto err_ctx; + } + + to_ctx->remap_slice = 0; + } + + return 0; + +err_ctx: + engine->legacy_active_context = from_ctx; +err_mm: + engine->legacy_active_ppgtt = from_mm; +err: + return ret; +} + static int ring_request_alloc(struct drm_i915_gem_request *request) { int ret; @@ -1401,7 +1585,7 @@ static int ring_request_alloc(struct drm_i915_gem_request *request) if (ret) return ret; - ret = i915_switch_context(request); + ret = switch_context(request); if (ret) return ret; -- GitLab From b7d3aabf900728b6b13b860157026fd26099208a Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 23 Nov 2017 21:17:51 +0000 Subject: [PATCH 0093/2547] drm/i915/pmu: Hide the (unsigned long)ptr cast We pretend the PMU config id is a pointer value when encoding it into the device parameters for presentation via sysfs. This requires casting of an unsigned long into and out of the pointer member, which annoys smatch: drivers/gpu/drm/i915/i915_pmu.c:684 i915_pmu_event_show() warn: argument 3 to %lx specifier is cast from pointer Instead of abusing a generic dev_ext_attribute, define our own typesafe attributes. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Michal Wajdeczko Link: https://patchwork.freedesktop.org/patch/msgid/20171123211751.2885-1-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_pmu.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 6a42e7f7967d..5170a46893d7 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -650,19 +650,24 @@ static int i915_pmu_event_event_idx(struct perf_event *event) return 0; } +struct i915_str_attribute { + struct device_attribute attr; + const char *str; +}; + static ssize_t i915_pmu_format_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct dev_ext_attribute *eattr; + struct i915_str_attribute *eattr; - eattr = container_of(attr, struct dev_ext_attribute, attr); - return sprintf(buf, "%s\n", (char *)eattr->var); + eattr = container_of(attr, struct i915_str_attribute, attr); + return sprintf(buf, "%s\n", eattr->str); } #define I915_PMU_FORMAT_ATTR(_name, _config) \ - (&((struct dev_ext_attribute[]) { \ + (&((struct i915_str_attribute[]) { \ { .attr = __ATTR(_name, 0444, i915_pmu_format_show, NULL), \ - .var = (void *)_config, } \ + .str = _config, } \ })[0].attr.attr) static struct attribute *i915_pmu_format_attrs[] = { @@ -675,19 +680,24 @@ static const struct attribute_group i915_pmu_format_attr_group = { .attrs = i915_pmu_format_attrs, }; +struct i915_ext_attribute { + struct device_attribute attr; + unsigned long val; +}; + static ssize_t i915_pmu_event_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct dev_ext_attribute *eattr; + struct i915_ext_attribute *eattr; - eattr = container_of(attr, struct dev_ext_attribute, attr); - return sprintf(buf, "config=0x%lx\n", (unsigned long)eattr->var); + eattr = container_of(attr, struct i915_ext_attribute, attr); + return sprintf(buf, "config=0x%lx\n", eattr->val); } #define I915_EVENT_ATTR(_name, _config) \ - (&((struct dev_ext_attribute[]) { \ + (&((struct i915_ext_attribute[]) { \ { .attr = __ATTR(_name, 0444, i915_pmu_event_show, NULL), \ - .var = (void *)_config, } \ + .val = _config, } \ })[0].attr.attr) #define I915_EVENT_STR(_name, _str) \ -- GitLab From e7e5da7127d5c9c076f05d6ed71bdf6826fc536c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 23 Nov 2017 23:37:12 +0000 Subject: [PATCH 0094/2547] drm/i915/selftests: Hold rpm wakeref for request + ggtt usage Since the removal of the delayed rc6 enabling, we now setup and drop the early rpm wakeref during modules initialisation before we start the live selftests. As such, we are now detecting errors in the tests where we were not holding the required wakeref for various actions. As rpm is not the primary goal of the tests involved, take a coarse and convenient rpm wakeref around the tests. Signed-off-by: Chris Wilson Cc: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20171123233712.21836-1-chris@chris-wilson.co.uk Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/selftests/huge_pages.c | 2 ++ drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c index df1befe2c793..e6b31041cc88 100644 --- a/drivers/gpu/drm/i915/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c @@ -1749,6 +1749,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *dev_priv) return PTR_ERR(file); mutex_lock(&dev_priv->drm.struct_mutex); + intel_runtime_pm_get(dev_priv); ctx = live_context(dev_priv, file); if (IS_ERR(ctx)) { @@ -1759,6 +1760,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *dev_priv) err = i915_subtests(tests, ctx); out_unlock: + intel_runtime_pm_put(dev_priv); mutex_unlock(&dev_priv->drm.struct_mutex); mock_file_free(dev_priv, file); diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c index f463105ff48d..e1ddad635d73 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c @@ -355,6 +355,7 @@ static int igt_evict_contexts(void *arg) return 0; mutex_lock(&i915->drm.struct_mutex); + intel_runtime_pm_get(i915); /* Reserve a block so that we know we have enough to fit a few rq */ memset(&hole, 0, sizeof(hole)); @@ -463,6 +464,7 @@ static int igt_evict_contexts(void *arg) } if (drm_mm_node_allocated(&hole)) drm_mm_remove_node(&hole); + intel_runtime_pm_put(i915); mutex_unlock(&i915->drm.struct_mutex); return err; -- GitLab From 141a0895d5ad3d2540c3d08651f2b63443fb8dfd Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 23 Nov 2017 12:34:31 +0000 Subject: [PATCH 0095/2547] drm/i915/pmu: Remove conditional HOTPLUG_CPU registration Even for static CPU configurations, the hotplug CPU framework is still used to determine the CPU topology, and is still being used by the perf event register to check for valid CPUs. Fixes: b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf queries") Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Dmitry Rogozhkin Reviewed-by: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20171123123432.25035-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_pmu.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 5170a46893d7..21006e8065a0 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -40,7 +40,7 @@ #define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS) -static cpumask_t i915_pmu_cpumask = CPU_MASK_NONE; +static cpumask_t i915_pmu_cpumask; static u8 engine_config_sample(u64 config) { @@ -770,7 +770,6 @@ static const struct attribute_group *i915_pmu_attr_groups[] = { NULL }; -#ifdef CONFIG_HOTPLUG_CPU static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node) { struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node); @@ -806,11 +805,9 @@ static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node) } static enum cpuhp_state cpuhp_slot = CPUHP_INVALID; -#endif static int i915_pmu_register_cpuhp_state(struct drm_i915_private *i915) { -#ifdef CONFIG_HOTPLUG_CPU enum cpuhp_state slot; int ret; @@ -829,17 +826,14 @@ static int i915_pmu_register_cpuhp_state(struct drm_i915_private *i915) } cpuhp_slot = slot; -#endif return 0; } static void i915_pmu_unregister_cpuhp_state(struct drm_i915_private *i915) { -#ifdef CONFIG_HOTPLUG_CPU WARN_ON(cpuhp_slot == CPUHP_INVALID); WARN_ON(cpuhp_state_remove_instance(cpuhp_slot, &i915->pmu.node)); cpuhp_remove_multi_state(cpuhp_slot); -#endif } void i915_pmu_register(struct drm_i915_private *i915) -- GitLab From 0426c046546140fc42db5addeb7e2298dd0b6fb1 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 23 Nov 2017 12:34:32 +0000 Subject: [PATCH 0096/2547] drm/i915/pmu: Only allow running on a single CPU We do two things, both of which are purely to simplify and clarify the implementation: 1. Simplify the CPU online callback so it is more obvious that the purpose there is to set a single CPU mask bit for the first CPU which comes online. Using cpumask_weight for this reads more obvious than the trick with cpumask_and_any. 2. Modify the event init so that events can be created only on a single CPU. This removes looking at the requested CPU thread siblings, and only allows creating on the current active CPU. Signed-off-by: Tvrtko Ursulin Cc: Chris Wilson Cc: Dmitry Rogozhkin Tested-by: Chris Wilson Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171123123432.25035-2-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_pmu.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 21006e8065a0..2b7a4779f184 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -344,7 +344,7 @@ static int i915_pmu_event_init(struct perf_event *event) { struct drm_i915_private *i915 = container_of(event->pmu, typeof(*i915), pmu.base); - int cpu, ret; + int ret; if (event->attr.type != event->pmu->type) return -ENOENT; @@ -359,9 +359,8 @@ static int i915_pmu_event_init(struct perf_event *event) if (event->cpu < 0) return -EINVAL; - cpu = cpumask_any_and(&i915_pmu_cpumask, - topology_sibling_cpumask(event->cpu)); - if (cpu >= nr_cpu_ids) + /* only allow running on one cpu at a time */ + if (!cpumask_test_cpu(event->cpu, &i915_pmu_cpumask)) return -ENODEV; if (is_engine_event(event)) { @@ -396,7 +395,6 @@ static int i915_pmu_event_init(struct perf_event *event) if (ret) return ret; - event->cpu = cpu; if (!event->parent) event->destroy = i915_pmu_event_destroy; @@ -773,13 +771,11 @@ static const struct attribute_group *i915_pmu_attr_groups[] = { static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node) { struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node); - unsigned int target; GEM_BUG_ON(!pmu->base.event_init); - target = cpumask_any_and(&i915_pmu_cpumask, &i915_pmu_cpumask); /* Select the first online CPU as a designated reader. */ - if (target >= nr_cpu_ids) + if (!cpumask_weight(&i915_pmu_cpumask)) cpumask_set_cpu(cpu, &i915_pmu_cpumask); return 0; -- GitLab From 95c71769811cb3ca55ecbb9f6a7fc126a35c1500 Mon Sep 17 00:00:00 2001 From: Sagar Arun Kamble Date: Fri, 24 Nov 2017 13:50:50 +0530 Subject: [PATCH 0097/2547] drm/i915/guc: Update header guard name of intel_guc_submission.h While renaming i915_guc_submission.h to intel_guc_submission.h, update of header guard name to _INTEL_GUC_SUBMISSION_H_ was missed. References: a269574489d4 (drm/i915/guc: Rename i915_guc_submission.c|h to intel_guc_submission.c|h) Signed-off-by: Sagar Arun Kamble Cc: Joonas Lahtinen Reviewed-by: Michal Wajdeczko Link: https://patchwork.freedesktop.org/patch/msgid/1511511650-13756-1-git-send-email-sagar.a.kamble@intel.com Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_guc_submission.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.h b/drivers/gpu/drm/i915/intel_guc_submission.h index e901192ee469..021fe85c8f71 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.h +++ b/drivers/gpu/drm/i915/intel_guc_submission.h @@ -22,8 +22,8 @@ * */ -#ifndef _I915_GUC_SUBMISSION_H_ -#define _I915_GUC_SUBMISSION_H_ +#ifndef _INTEL_GUC_SUBMISSION_H_ +#define _INTEL_GUC_SUBMISSION_H_ #include -- GitLab From 3e8f5b0805e5f93770e420e3f455b7d14d08173f Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Fri, 24 Nov 2017 09:53:40 +0000 Subject: [PATCH 0098/2547] drm/i915/guc: Rename i915_guc_reg.h to intel_guc_reg.h We are using intel_ prefix for all file names with hardware related definitions. GuC registers also fall into this category. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Sagar Arun Kamble Reviewed-by: Sagar Arun Kamble Link: https://patchwork.freedesktop.org/patch/msgid/20171124095340.1500-1-michal.wajdeczko@intel.com Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_guc.h | 2 +- drivers/gpu/drm/i915/{i915_guc_reg.h => intel_guc_reg.h} | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) rename drivers/gpu/drm/i915/{i915_guc_reg.h => intel_guc_reg.h} (98%) diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 75c4cfefdaff..59856726d2bc 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -30,8 +30,8 @@ #include "intel_guc_fwif.h" #include "intel_guc_ct.h" #include "intel_guc_log.h" +#include "intel_guc_reg.h" #include "intel_uc_fw.h" -#include "i915_guc_reg.h" #include "i915_vma.h" struct guc_preempt_work { diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h similarity index 98% rename from drivers/gpu/drm/i915/i915_guc_reg.h rename to drivers/gpu/drm/i915/intel_guc_reg.h index bc1ae7d8f424..0a8ff03d026f 100644 --- a/drivers/gpu/drm/i915/i915_guc_reg.h +++ b/drivers/gpu/drm/i915/intel_guc_reg.h @@ -21,8 +21,8 @@ * IN THE SOFTWARE. * */ -#ifndef _I915_GUC_REG_H_ -#define _I915_GUC_REG_H_ +#ifndef _INTEL_GUC_REG_H_ +#define _INTEL_GUC_REG_H_ /* Definitions of GuC H/W registers, bits, etc */ -- GitLab From 1b2b659141cfa7c96c62c79516662a34ad112284 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 12 Oct 2017 10:21:47 +0100 Subject: [PATCH 0099/2547] drm/i915: Select DEBUG_FS for our test suite Ensure that we build our test kernels with DEBUG_FS enabled as many of our igt tests require poking around debugfs/dri. This should also fixup the kbuild complaint that we tried to select SW_SYNC without meeting its dependencies. Reported-by: kbuild-all@01.org Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171012092147.28986-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/Kconfig.debug | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index 9e53edbc713b..fa36491495b1 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -18,6 +18,7 @@ config DRM_I915_WERROR config DRM_I915_DEBUG bool "Enable additional driver debugging" depends on DRM_I915 + select DEBUG_FS select PREEMPT_COUNT select I2C_CHARDEV select DRM_DP_AUX_CHARDEV -- GitLab From 254beff97b4714bac4ec8add5a6888c1adc1ad8f Mon Sep 17 00:00:00 2001 From: "oder_chiou@realtek.com" Date: Fri, 24 Nov 2017 16:11:22 +0800 Subject: [PATCH 0100/2547] ASoC: rt5514: Make sure the DMIC delay will be happened after normal SUPPLY widgets power on The patch makes sure the DMIC delay will be happened after normal SUPPLY widgets power on. If there are some platforms that provide the MCLK using the SUPPLY widget, it will make sure the delay time is helpful. Signed-off-by: Oder Chiou Signed-off-by: Mark Brown --- sound/soc/codecs/rt5514.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/rt5514.c b/sound/soc/codecs/rt5514.c index 2a5b5d74e697..2dd6e9f990a4 100644 --- a/sound/soc/codecs/rt5514.c +++ b/sound/soc/codecs/rt5514.c @@ -496,7 +496,7 @@ static const struct snd_soc_dapm_widget rt5514_dapm_widgets[] = { SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, + SND_SOC_DAPM_SUPPLY_S("DMIC CLK", 1, SND_SOC_NOPM, 0, 0, rt5514_set_dmic_clk, SND_SOC_DAPM_PRE_PMU), SND_SOC_DAPM_SUPPLY("ADC CLK", RT5514_CLK_CTRL1, -- GitLab From 5a1314fa697fc65cefaba64cd4699bfc3e6882a6 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Date: Tue, 21 Nov 2017 10:09:02 +0100 Subject: [PATCH 0101/2547] spi: xilinx: Detect stall with Unknown commands When the core is configured in C_SPI_MODE > 0, it integrates a lookup table that automatically configures the core in dual or quad mode based on the command (first byte on the tx fifo). Unfortunately, that list mode_?_memoy_*.mif does not contain all the supported commands by the flash. Since 4.14 spi-nor automatically tries to probe the flash using SFDP (command 0x5a), and that command is not part of the list_mode table. Whit the right combination of C_SPI_MODE and C_SPI_MEMORY this leads into a stall that can only be recovered with a soft rest. This patch detects this kind of stall and returns -EIO to the caller on those commands. spi-nor can handle this error properly: m25p80 spi0.0: Detected stall. Check C_SPI_MODE and C_SPI_MEMORY. 0x21 0x2404 m25p80 spi0.0: SPI transfer failed: -5 spi_master spi0: failed to transfer one message from queue m25p80 spi0.0: s25sl064p (8192 Kbytes) Signed-off-by: Ricardo Ribalda Delgado Signed-off-by: Mark Brown Cc: stable@vger.kernel.org --- drivers/spi/spi-xilinx.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c index bc7100b93dfc..e0b9fe1d0e37 100644 --- a/drivers/spi/spi-xilinx.c +++ b/drivers/spi/spi-xilinx.c @@ -271,6 +271,7 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) while (remaining_words) { int n_words, tx_words, rx_words; u32 sr; + int stalled; n_words = min(remaining_words, xspi->buffer_size); @@ -299,7 +300,17 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) /* Read out all the data from the Rx FIFO */ rx_words = n_words; + stalled = 10; while (rx_words) { + if (rx_words == n_words && !(stalled--) && + !(sr & XSPI_SR_TX_EMPTY_MASK) && + (sr & XSPI_SR_RX_EMPTY_MASK)) { + dev_err(&spi->dev, + "Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n"); + xspi_init_hw(xspi); + return -EIO; + } + if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) { xilinx_spi_rx(xspi); rx_words--; -- GitLab From 8ee4f19c47031f23340055da4d9f2af537de23f4 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Fri, 24 Nov 2017 09:49:59 +0000 Subject: [PATCH 0102/2547] drm/i915/pmu: Stop averaging with the previous sample Averaging with the previous sample brings a small statistical improvement to sampling counters, but can leek a little bit of state from a current client to the next which mulls the border between past and present for observing clients. This is because on event enable clients record the current counter value and use it as reference, but with rapid off-on event cycles, and due the delayed nature of sampling timer self-disarm, previous sample value does not get cleared under these circumstances. Solution is to stop averaging with the previous sample. This has a small downside of losing some precision with short and spiky signals, but the alternatives look too complicated for the benefit. Signed-off-by: Tvrtko Ursulin Cc: Chris Wilson Cc: Sagar Arun Kamble Reviewed-by: Chris Wilson Tested-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171124094959.10725-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_pmu.c | 29 ++--------------------------- drivers/gpu/drm/i915/i915_pmu.h | 1 - 2 files changed, 2 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 2b7a4779f184..39310cf13c3a 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -181,12 +181,7 @@ static bool grab_forcewake(struct drm_i915_private *i915, bool fw) static void update_sample(struct i915_pmu_sample *sample, u32 unit, u32 val) { - /* - * Since we are doing stochastic sampling for these counters, - * average the delta with the previous value for better accuracy. - */ - sample->cur += div_u64(mul_u32_u32(sample->prev + val, unit), 2); - sample->prev = val; + sample->cur += mul_u32_u32(val, unit); } static void engines_sample(struct drm_i915_private *dev_priv) @@ -262,31 +257,13 @@ static void frequency_sample(struct drm_i915_private *dev_priv) } } -static void pmu_init_previous_samples(struct drm_i915_private *i915) -{ - struct intel_engine_cs *engine; - enum intel_engine_id id; - unsigned int i; - - for_each_engine(engine, i915, id) { - for (i = 0; i < ARRAY_SIZE(engine->pmu.sample); i++) - engine->pmu.sample[i].prev = 0; - } - - for (i = 0; i < ARRAY_SIZE(i915->pmu.sample); i++) - i915->pmu.sample[i].prev = i915->gt_pm.rps.idle_freq; -} - static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) { struct drm_i915_private *i915 = container_of(hrtimer, struct drm_i915_private, pmu.timer); - if (!READ_ONCE(i915->pmu.timer_enabled)) { - pmu_init_previous_samples(i915); - + if (!READ_ONCE(i915->pmu.timer_enabled)) return HRTIMER_NORESTART; - } engines_sample(i915); frequency_sample(i915); @@ -857,8 +834,6 @@ void i915_pmu_register(struct drm_i915_private *i915) hrtimer_init(&i915->pmu.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); i915->pmu.timer.function = i915_sample; - pmu_init_previous_samples(i915); - for_each_engine(engine, i915, id) INIT_DELAYED_WORK(&engine->pmu.disable_busy_stats, __disable_busy_stats); diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h index e209783a4c5f..40c154d13565 100644 --- a/drivers/gpu/drm/i915/i915_pmu.h +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -41,7 +41,6 @@ enum { struct i915_pmu_sample { u64 cur; - u32 prev; }; struct i915_pmu { -- GitLab From c4deb62d7821672265b87952bcd1c808f3bf3e8f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Thu, 23 Nov 2017 21:41:56 +0200 Subject: [PATCH 0103/2547] drm/i915: Don't try indexed reads to alternate slave addresses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We can only specify the one slave address to indexed reads/writes. Make sure the messages we check are destined to the same slave address before deciding to do an indexed transfer. Cc: stable@vger.kernel.org Cc: Daniel Kurtz Cc: Chris Wilson Cc: Daniel Vetter Cc: Sean Paul Fixes: 56f9eac05489 ("drm/i915/intel_i2c: use INDEX cycles for i2c read transactions") Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171123194157.25367-2-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_i2c.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index eb5827110d8f..8affd47b98b8 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -438,6 +438,7 @@ static bool gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) { return (i + 1 < num && + msgs[i].addr == msgs[i + 1].addr && !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && (msgs[i + 1].flags & I2C_M_RD)); } -- GitLab From bb9e0d4bca50f429152e74a459160b41f3d60fb2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Thu, 23 Nov 2017 21:41:57 +0200 Subject: [PATCH 0104/2547] drm/i915: Prevent zero length "index" write MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The hardware always writes one or two bytes in the index portion of an indexed transfer. Make sure the message we send as the index doesn't have a zero length. Cc: stable@vger.kernel.org Cc: Daniel Kurtz Cc: Chris Wilson Cc: Daniel Vetter Cc: Sean Paul Fixes: 56f9eac05489 ("drm/i915/intel_i2c: use INDEX cycles for i2c read transactions") Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171123194157.25367-3-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_i2c.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 8affd47b98b8..49fdf09f9919 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -439,7 +439,8 @@ gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) { return (i + 1 < num && msgs[i].addr == msgs[i + 1].addr && - !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && + !(msgs[i].flags & I2C_M_RD) && + (msgs[i].len == 1 || msgs[i].len == 2) && (msgs[i + 1].flags & I2C_M_RD)); } -- GitLab From aa34a6fc2722f042e372741661c0fae8640245ac Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 24 Nov 2017 13:37:44 +0000 Subject: [PATCH 0105/2547] drm/i915/guc: Advance over port[0] if set and not preempting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Our execlist emulation is intended to only use a maximum of 2 ports per engine, so as to not overflow the wq. (By knowing the limits, we can avoid having to handle the wq exhaustion.) However, upon adding preemption, we lost the skip over the first port if set for the non-preemption path. Restore it. Reported-by: Mika Kuoppala Fixes: c41937fd994a ("drm/i915/guc: Preemption! With GuC") Signed-off-by: Chris Wilson Cc: Michał Winiarski Cc: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171124133745.5173-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala Reviewed-by: Michał Winiarski --- drivers/gpu/drm/i915/intel_guc_submission.c | 29 ++++++++++++--------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index cbf5a96f5806..70e64bdb73dd 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -743,23 +743,26 @@ static void guc_dequeue(struct intel_engine_cs *engine) if (!rb) goto unlock; - if (HAS_LOGICAL_RING_PREEMPTION(engine->i915) && port_isset(port)) { - struct guc_preempt_work *preempt_work = - &engine->i915->guc.preempt_work[engine->id]; - - if (rb_entry(rb, struct i915_priolist, node)->priority > - max(port_request(port)->priotree.priority, 0)) { - execlists_set_active(execlists, - EXECLISTS_ACTIVE_PREEMPT); - queue_work(engine->i915->guc.preempt_wq, - &preempt_work->work); - goto unlock; - } else if (port_isset(last_port)) { - goto unlock; + if (port_isset(port)) { + if (HAS_LOGICAL_RING_PREEMPTION(engine->i915)) { + struct guc_preempt_work *preempt_work = + &engine->i915->guc.preempt_work[engine->id]; + + if (rb_entry(rb, struct i915_priolist, node)->priority > + max(port_request(port)->priotree.priority, 0)) { + execlists_set_active(execlists, + EXECLISTS_ACTIVE_PREEMPT); + queue_work(engine->i915->guc.preempt_wq, + &preempt_work->work); + goto unlock; + } } port++; + if (port_isset(port)) + goto unlock; } + GEM_BUG_ON(port_isset(port)); do { struct i915_priolist *p = rb_entry(rb, typeof(*p), node); -- GitLab From 8c5da3bbcfd9cf763623f2d9515ace8eb3f01307 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 24 Nov 2017 13:00:29 +0000 Subject: [PATCH 0106/2547] drm/i915/guc: Tidy ELSP port assignment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since we know that the port is empty, we do not need to extract the count from the old request it and copy it over to the new request, or attempt to unref the NULL old request pointer. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Michał Winiarski Reviewed-by: Michał Winiarski Link: https://patchwork.freedesktop.org/patch/msgid/20171124130031.20761-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_guc_submission.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index 70e64bdb73dd..cf1cc2cb6722 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -718,12 +718,9 @@ static void guc_submit(struct intel_engine_cs *engine) static void port_assign(struct execlist_port *port, struct drm_i915_gem_request *rq) { - GEM_BUG_ON(rq == port_request(port)); - - if (port_isset(port)) - i915_gem_request_put(port_request(port)); + GEM_BUG_ON(port_isset(port)); - port_set(port, port_pack(i915_gem_request_get(rq), port_count(port))); + port_set(port, i915_gem_request_get(rq)); } static void guc_dequeue(struct intel_engine_cs *engine) -- GitLab From a54b1873c0e3ffec3041cf72cb10d986d6bc4fe5 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 24 Nov 2017 13:00:30 +0000 Subject: [PATCH 0107/2547] drm/i915: Use exponential backoff for wait_for() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of sleeping for a fixed 1ms (roughly, depending on timer slack), start with a small sleep and exponentially increase the sleep on each cycle. A good example of a beneficiary is the guc mmio communication channel. Typically we expect (and so spin) for 10us for a quick response, but this doesn't cover everything and so sometimes we fallback to the millisecond+ sleep. This incurs a significant delay in time-critical operations like preemption (igt/gem_exec_latency), which can be improved significantly by using a small sleep after the spin fails. We've made this suggestion many times, but had little experimental data to support adding the complexity. v2: Bump the minimum usleep to 10us on advice of Documentation/timers/timers-howto.txt (Tvrko) v3: Specify min, max range for usleep intervals -- some code may crucially depend upon and so want to specify the sleep pattern. References: 1758b90e38f5 ("drm/i915: Use a hybrid scheme for fast register waits") Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: John Harrison Cc: Michał Winiarski Cc: Ville Syrjala Reviewed-by: Michał Winiarski Link: https://patchwork.freedesktop.org/patch/msgid/20171124130031.20761-2-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_drv.h | 11 +++++++---- drivers/gpu/drm/i915/intel_pm.c | 2 +- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 635a96fcd788..c00441a3d649 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -48,8 +48,9 @@ * having timed out, since the timeout could be due to preemption or similar and * we've never had a chance to check the condition before the timeout. */ -#define _wait_for(COND, US, W) ({ \ +#define _wait_for(COND, US, Wmin, Wmax) ({ \ unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \ + long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ int ret__; \ might_sleep(); \ for (;;) { \ @@ -62,12 +63,14 @@ ret__ = -ETIMEDOUT; \ break; \ } \ - usleep_range((W), (W) * 2); \ + usleep_range(wait__, wait__ * 2); \ + if (wait__ < (Wmax)) \ + wait__ <<= 1; \ } \ ret__; \ }) -#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000) +#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) @@ -116,7 +119,7 @@ int ret__; \ BUILD_BUG_ON(!__builtin_constant_p(US)); \ if ((US) > 10) \ - ret__ = _wait_for((COND), (US), 10); \ + ret__ = _wait_for((COND), (US), 10, 10); \ else \ ret__ = _wait_for_atomic((COND), (US), 0); \ ret__; \ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 03d67d8ab647..a80c322c5b43 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -9294,7 +9294,7 @@ int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, ret = 0; goto out; } - ret = _wait_for(COND, timeout_base_ms * 1000, 10); + ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10); if (!ret) goto out; -- GitLab From 3452fa3095e91acbcb1f6290e0d70fa7d3695a3a Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Fri, 24 Nov 2017 17:13:31 +0000 Subject: [PATCH 0108/2547] drm/i915/pmu: Aggregate all RC6 states into one counter Chris has discovered that RC6, RC6p and RC6pp counters are mutually exclusive, and even that on some SNB SKUs you get RC6p increasing, and on the others RC6. Furthermore RC6p and RC6pp were only present starting from GEN6 until, GEN7, not including Haswell. All this combined makes it questionable whether we need to reserve new ABI for these counters. One idea was to just combine them all under the RC6 counter to simplify things for userspace. So that is what this patch does. Signed-off-by: Tvrtko Ursulin Suggested-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171124171331.17981-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_pmu.c | 23 ++++++----------------- include/uapi/drm/i915_drm.h | 6 +----- 2 files changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 39310cf13c3a..3357b690ce90 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -359,11 +359,6 @@ static int i915_pmu_event_init(struct perf_event *event) if (!HAS_RC6(i915)) ret = -ENODEV; break; - case I915_PMU_RC6p_RESIDENCY: - case I915_PMU_RC6pp_RESIDENCY: - if (!HAS_RC6p(i915)) - ret = -ENODEV; - break; default: ret = -ENOENT; break; @@ -421,16 +416,12 @@ static u64 __i915_pmu_event_read(struct perf_event *event) IS_VALLEYVIEW(i915) ? VLV_GT_RENDER_RC6 : GEN6_GT_GFX_RC6); - intel_runtime_pm_put(i915); - break; - case I915_PMU_RC6p_RESIDENCY: - intel_runtime_pm_get(i915); - val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p); - intel_runtime_pm_put(i915); - break; - case I915_PMU_RC6pp_RESIDENCY: - intel_runtime_pm_get(i915); - val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp); + if (HAS_RC6p(i915)) { + val += intel_rc6_residency_ns(i915, + GEN6_GT_GFX_RC6p); + val += intel_rc6_residency_ns(i915, + GEN6_GT_GFX_RC6pp); + } intel_runtime_pm_put(i915); break; } @@ -708,8 +699,6 @@ static struct attribute *i915_pmu_events_attrs[] = { I915_EVENT_ATTR(interrupts, I915_PMU_INTERRUPTS), I915_EVENT(rc6-residency, I915_PMU_RC6_RESIDENCY, "ns"), - I915_EVENT(rc6p-residency, I915_PMU_RC6p_RESIDENCY, "ns"), - I915_EVENT(rc6pp-residency, I915_PMU_RC6pp_RESIDENCY, "ns"), NULL, }; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 239e8633edc9..536ee4febd74 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -137,14 +137,10 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) - #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) - #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) -#define I915_PMU_RC6p_RESIDENCY __I915_PMU_OTHER(4) -#define I915_PMU_RC6pp_RESIDENCY __I915_PMU_OTHER(5) -#define I915_PMU_LAST I915_PMU_RC6pp_RESIDENCY +#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY /* Each region is a minimum of 16k, and there are at most 255 of them. */ -- GitLab From 53fa54a6ef4fa5a261468d13dc0f54739adaa456 Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Fri, 24 Nov 2017 17:02:39 +0000 Subject: [PATCH 0109/2547] drm/i915/guc: Use consistent name for scratch register count We should be consistent on naming of similar definitions. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Sagar Arun Kamble Link: https://patchwork.freedesktop.org/patch/msgid/20171124170239.29360-1-michal.wajdeczko@intel.com Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_guc_fw.c | 4 ++-- drivers/gpu/drm/i915/intel_guc_reg.h | 3 ++- drivers/gpu/drm/i915/intel_uc_fw.c | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index 69ba01599575..bbab4e1106f3 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -130,14 +130,14 @@ static int guc_xfer_rsa(struct intel_guc *guc, struct i915_vma *vma) struct drm_i915_private *dev_priv = guc_to_i915(guc); struct intel_uc_fw *guc_fw = &guc->fw; struct sg_table *sg = vma->pages; - u32 rsa[UOS_RSA_SCRATCH_MAX_COUNT]; + u32 rsa[UOS_RSA_SCRATCH_COUNT]; int i; if (sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), guc_fw->rsa_offset) != sizeof(rsa)) return -EINVAL; - for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++) + for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]); return 0; diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h index 0a8ff03d026f..19a9247c5664 100644 --- a/drivers/gpu/drm/i915/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/intel_guc_reg.h @@ -52,7 +52,8 @@ #define SOFT_SCRATCH_COUNT 16 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4) -#define UOS_RSA_SCRATCH_MAX_COUNT 64 +#define UOS_RSA_SCRATCH_COUNT 64 + #define DMA_ADDR_0_LOW _MMIO(0xc300) #define DMA_ADDR_0_HIGH _MMIO(0xc304) #define DMA_ADDR_1_LOW _MMIO(0xc308) diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c index 4bc82d3005ff..b376dd3b28cc 100644 --- a/drivers/gpu/drm/i915/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/intel_uc_fw.c @@ -105,7 +105,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv, } /* now RSA */ - if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) { + if (css->key_size_dw != UOS_RSA_SCRATCH_COUNT) { DRM_WARN("%s: Mismatched firmware RSA key size (%u)\n", intel_uc_fw_type_repr(uc_fw->type), css->key_size_dw); err = -ENOEXEC; -- GitLab From b46cb7d70e77ef5639bf2dcbef27be6e21e07a61 Mon Sep 17 00:00:00 2001 From: Yong Zhao Date: Fri, 24 Nov 2017 18:10:54 -0500 Subject: [PATCH 0110/2547] drm/amdkfd: Delete a useless parameter from create_queue function pointer Signed-off-by: Yong Zhao Reviewed-by: Felix Kuehling Signed-off-by: Oded Gabbay --- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 13 +++---------- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 3 +-- .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 6 ++---- 3 files changed, 6 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 8447810c9a1e..81ec7bb89b04 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -149,8 +149,7 @@ static void deallocate_vmid(struct device_queue_manager *dqm, static int create_queue_nocpsch(struct device_queue_manager *dqm, struct queue *q, - struct qcm_process_device *qpd, - int *allocated_vmid) + struct qcm_process_device *qpd) { int retval; @@ -170,7 +169,6 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, if (retval) goto out_unlock; } - *allocated_vmid = qpd->vmid; q->properties.vmid = qpd->vmid; q->properties.tba_addr = qpd->tba_addr; @@ -184,10 +182,8 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, retval = -EINVAL; if (retval) { - if (list_empty(&qpd->queues_list)) { + if (list_empty(&qpd->queues_list)) deallocate_vmid(dqm, qpd, q); - *allocated_vmid = 0; - } goto out_unlock; } @@ -812,16 +808,13 @@ static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, } static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, - struct qcm_process_device *qpd, int *allocate_vmid) + struct qcm_process_device *qpd) { int retval; struct mqd_manager *mqd; retval = 0; - if (allocate_vmid) - *allocate_vmid = 0; - mutex_lock(&dqm->lock); if (dqm->total_queue_count >= max_num_of_queues_per_device) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 8752edf9cd9b..c61b693bfa8c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -84,8 +84,7 @@ struct device_process_node { struct device_queue_manager_ops { int (*create_queue)(struct device_queue_manager *dqm, struct queue *q, - struct qcm_process_device *qpd, - int *allocate_vmid); + struct qcm_process_device *qpd); int (*destroy_queue)(struct device_queue_manager *dqm, struct qcm_process_device *qpd, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index eeb7726b6299..fbfa2741e2a7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -201,8 +201,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, goto err_create_queue; pqn->q = q; pqn->kq = NULL; - retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, - &q->properties.vmid); + retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd); pr_debug("DQM returned %d for create_queue\n", retval); print_queue(q); break; @@ -222,8 +221,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, goto err_create_queue; pqn->q = q; pqn->kq = NULL; - retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, - &q->properties.vmid); + retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd); pr_debug("DQM returned %d for create_queue\n", retval); print_queue(q); break; -- GitLab From 0c3292ca8025c5aef44dc389ac3a6bf4a325e0be Mon Sep 17 00:00:00 2001 From: Nadav Amit Date: Fri, 24 Nov 2017 19:29:06 -0800 Subject: [PATCH 0111/2547] x86/tlb: Refactor CR4 setting and shadow write Refactor the write to CR4 and its shadow value. This is done in preparation for the addition of an assertion to check that IRQs are disabled during CR4 update. No functional change. Signed-off-by: Nadav Amit Signed-off-by: Thomas Gleixner Cc: nadav.amit@gmail.com Cc: Andy Lutomirski Cc: linux-edac@vger.kernel.org Link: https://lkml.kernel.org/r/20171125032907.2241-2-namit@vmware.com --- arch/x86/include/asm/tlbflush.h | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 509046cfa5ce..e736f7f0ba92 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -173,17 +173,20 @@ static inline void cr4_init_shadow(void) this_cpu_write(cpu_tlbstate.cr4, __read_cr4()); } +static inline void __cr4_set(unsigned long cr4) +{ + this_cpu_write(cpu_tlbstate.cr4, cr4); + __write_cr4(cr4); +} + /* Set in this cpu's CR4. */ static inline void cr4_set_bits(unsigned long mask) { unsigned long cr4; cr4 = this_cpu_read(cpu_tlbstate.cr4); - if ((cr4 | mask) != cr4) { - cr4 |= mask; - this_cpu_write(cpu_tlbstate.cr4, cr4); - __write_cr4(cr4); - } + if ((cr4 | mask) != cr4) + __cr4_set(cr4 | mask); } /* Clear in this cpu's CR4. */ @@ -192,11 +195,8 @@ static inline void cr4_clear_bits(unsigned long mask) unsigned long cr4; cr4 = this_cpu_read(cpu_tlbstate.cr4); - if ((cr4 & ~mask) != cr4) { - cr4 &= ~mask; - this_cpu_write(cpu_tlbstate.cr4, cr4); - __write_cr4(cr4); - } + if ((cr4 & ~mask) != cr4) + __cr4_set(cr4 & ~mask); } static inline void cr4_toggle_bits(unsigned long mask) @@ -204,9 +204,7 @@ static inline void cr4_toggle_bits(unsigned long mask) unsigned long cr4; cr4 = this_cpu_read(cpu_tlbstate.cr4); - cr4 ^= mask; - this_cpu_write(cpu_tlbstate.cr4, cr4); - __write_cr4(cr4); + __cr4_set(cr4 ^ mask); } /* Read the CR4 shadow. */ -- GitLab From 9d0b62328d34c7044114d4f4281981d4c537c4ba Mon Sep 17 00:00:00 2001 From: Nadav Amit Date: Fri, 24 Nov 2017 19:29:07 -0800 Subject: [PATCH 0112/2547] x86/tlb: Disable interrupts when changing CR4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CR4 modifications are implemented as RMW operations which update a shadow variable and write the result to CR4. The RMW operation is protected by preemption disable, but there is no enforcement or debugging mechanism. CR4 modifications happen also in interrupt context via __native_flush_tlb_global(). This implementation does not affect a interrupted thread context CR4 operation, because the CR4 toggle restores the original content and does not modify the shadow variable. So the current situation seems to be safe, but a recent patch tried to add an actual RMW operation in interrupt context, which will cause subtle corruptions. To prevent that and make the CR4 handling future proof: - Add a lockdep assertion to __cr4_set() which will catch interrupt enabled invocations - Disable interrupts in the cr4 manipulator inlines - Rename cr4_toggle_bits() to cr4_toggle_bits_irqsoff(). This is called from __switch_to_xtra() where interrupts are already disabled and performance matters. All other call sites are not performance critical, so the extra overhead of an additional local_irq_save/restore() pair is not a problem. If new call sites care about performance then the necessary _irqsoff() variants can be added. [ tglx: Condensed the patch by moving the irq protection inside the manipulator functions. Updated changelog ] Signed-off-by: Nadav Amit Signed-off-by: Thomas Gleixner Cc: Luck Cc: Radim Krčmář Cc: Andy Lutomirski Cc: Paolo Bonzini Cc: Borislav Petkov Cc: nadav.amit@gmail.com Cc: linux-edac@vger.kernel.org Link: https://lkml.kernel.org/r/20171125032907.2241-3-namit@vmware.com --- arch/x86/include/asm/tlbflush.h | 11 ++++++++--- arch/x86/kernel/process.c | 2 +- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index e736f7f0ba92..877b5c1a1b12 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -175,6 +175,7 @@ static inline void cr4_init_shadow(void) static inline void __cr4_set(unsigned long cr4) { + lockdep_assert_irqs_disabled(); this_cpu_write(cpu_tlbstate.cr4, cr4); __write_cr4(cr4); } @@ -182,24 +183,28 @@ static inline void __cr4_set(unsigned long cr4) /* Set in this cpu's CR4. */ static inline void cr4_set_bits(unsigned long mask) { - unsigned long cr4; + unsigned long cr4, flags; + local_irq_save(flags); cr4 = this_cpu_read(cpu_tlbstate.cr4); if ((cr4 | mask) != cr4) __cr4_set(cr4 | mask); + local_irq_restore(flags); } /* Clear in this cpu's CR4. */ static inline void cr4_clear_bits(unsigned long mask) { - unsigned long cr4; + unsigned long cr4, flags; + local_irq_save(flags); cr4 = this_cpu_read(cpu_tlbstate.cr4); if ((cr4 & ~mask) != cr4) __cr4_set(cr4 & ~mask); + local_irq_restore(flags); } -static inline void cr4_toggle_bits(unsigned long mask) +static inline void cr4_toggle_bits_irqsoff(unsigned long mask) { unsigned long cr4; diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 97fb3e5737f5..bb988a24db92 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -299,7 +299,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, } if ((tifp ^ tifn) & _TIF_NOTSC) - cr4_toggle_bits(X86_CR4_TSD); + cr4_toggle_bits_irqsoff(X86_CR4_TSD); if ((tifp ^ tifn) & _TIF_NOCPUID) set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); -- GitLab From c4e45c84270798b1d51ede9a8c6810378ccfe162 Mon Sep 17 00:00:00 2001 From: Shaul Triebitz Date: Mon, 30 Oct 2017 17:38:43 +0200 Subject: [PATCH 0113/2547] iwlwifi: mvm: set correct chains in Rx status ieee80211_rx_status::chains was always set to zero. That caused rate scaling to always start with the lowest rate possible (rs_get_initial_rate). Set it correctly according to the MPDU response. Signed-off-by: Shaul Triebitz Signed-off-by: Luca Coelho --- drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c b/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c index 76dc58381e1c..20fe23fbf040 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c @@ -213,6 +213,7 @@ static void iwl_mvm_get_signal_strength(struct iwl_mvm *mvm, struct ieee80211_rx_status *rx_status) { int energy_a, energy_b, max_energy; + u32 rate_flags = le32_to_cpu(desc->rate_n_flags); energy_a = desc->energy_a; energy_a = energy_a ? -energy_a : S8_MIN; @@ -224,7 +225,8 @@ static void iwl_mvm_get_signal_strength(struct iwl_mvm *mvm, energy_a, energy_b, max_energy); rx_status->signal = max_energy; - rx_status->chains = 0; /* TODO: phy info */ + rx_status->chains = + (rate_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_POS; rx_status->chain_signal[0] = energy_a; rx_status->chain_signal[1] = energy_b; rx_status->chain_signal[2] = S8_MIN; -- GitLab From 0b9832b712d6767d6c7b01965fd788d1ca84fc92 Mon Sep 17 00:00:00 2001 From: Emmanuel Grumbach Date: Mon, 13 Nov 2017 09:50:47 +0200 Subject: [PATCH 0114/2547] iwlwifi: mvm: don't use transmit queue hang detection when it is not possible When we act as an AP, new firmware versions handle internally the power saving clients and the driver doesn't know that the peers went to sleep. It is, hence, possible that a peer goes to sleep for a long time and stop pulling frames. This will cause its transmit queue to hang which is a condition that triggers the recovery flow in the driver. While this client is certainly buggy (it should have pulled the frame based on the TIM IE in the beacon), we can't blow up because of a buggy client. Change the current implementation to not enable the transmit queue hang detection on queues that serve peers when we act as an AP / GO. We can still enable this mechanism using the debug configuration which can come in handy when we want to debug why the client doesn't wake up. Cc: stable@vger.kernel.org # v4.13 Signed-off-by: Emmanuel Grumbach Signed-off-by: Luca Coelho --- drivers/net/wireless/intel/iwlwifi/mvm/utils.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c index d46115e2d69e..19c1d1f76e15 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c @@ -1134,9 +1134,18 @@ unsigned int iwl_mvm_get_wd_timeout(struct iwl_mvm *mvm, unsigned int default_timeout = cmd_q ? IWL_DEF_WD_TIMEOUT : mvm->cfg->base_params->wd_timeout; - if (!iwl_fw_dbg_trigger_enabled(mvm->fw, FW_DBG_TRIGGER_TXQ_TIMERS)) + if (!iwl_fw_dbg_trigger_enabled(mvm->fw, FW_DBG_TRIGGER_TXQ_TIMERS)) { + /* + * We can't know when the station is asleep or awake, so we + * must disable the queue hang detection. + */ + if (fw_has_capa(&mvm->fw->ucode_capa, + IWL_UCODE_TLV_CAPA_STA_PM_NOTIF) && + vif && vif->type == NL80211_IFTYPE_AP) + return IWL_WATCHDOG_DISABLED; return iwlmvm_mod_params.tfd_q_hang_detect ? default_timeout : IWL_WATCHDOG_DISABLED; + } trigger = iwl_fw_dbg_get_trigger(mvm->fw, FW_DBG_TRIGGER_TXQ_TIMERS); txq_timer = (void *)trigger->data; -- GitLab From d1b275ffec459c5ae12b5c7086c84175696e5a9f Mon Sep 17 00:00:00 2001 From: Emmanuel Grumbach Date: Wed, 15 Nov 2017 14:12:30 +0200 Subject: [PATCH 0115/2547] iwlwifi: mvm: fix the TX queue hang timeout for MONITOR vif type The MONITOR type is missing in the interface type switch. Add it. Signed-off-by: Emmanuel Grumbach Signed-off-by: Luca Coelho --- drivers/net/wireless/intel/iwlwifi/mvm/utils.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c index 19c1d1f76e15..03ffd84786ca 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c @@ -1172,6 +1172,8 @@ unsigned int iwl_mvm_get_wd_timeout(struct iwl_mvm *mvm, return le32_to_cpu(txq_timer->p2p_go); case NL80211_IFTYPE_P2P_DEVICE: return le32_to_cpu(txq_timer->p2p_device); + case NL80211_IFTYPE_MONITOR: + return default_timeout; default: WARN_ON(1); return mvm->cfg->base_params->wd_timeout; -- GitLab From b13f43a48571f0cd0fda271b5046b65f1f268db5 Mon Sep 17 00:00:00 2001 From: Emmanuel Grumbach Date: Sun, 19 Nov 2017 10:35:14 +0200 Subject: [PATCH 0116/2547] iwlwifi: mvm: fix packet injection We need to have a station and a queue for the monitor interface to be able to inject traffic. We used to have this traffic routed to the auxiliary queue, but this queue isn't scheduled for the station we had linked to the monitor vif. Allocate a new queue, link it to the monitor vif's station and make that queue use the BE fifo. This fixes https://bugzilla.kernel.org/show_bug.cgi?id=196715 Cc: stable@vger.kernel.org Signed-off-by: Emmanuel Grumbach Signed-off-by: Luca Coelho --- .../net/wireless/intel/iwlwifi/fw/api/txq.h | 4 ++ .../net/wireless/intel/iwlwifi/mvm/mac-ctxt.c | 2 +- drivers/net/wireless/intel/iwlwifi/mvm/mvm.h | 1 + drivers/net/wireless/intel/iwlwifi/mvm/ops.c | 1 + drivers/net/wireless/intel/iwlwifi/mvm/sta.c | 53 ++++++++++++++----- drivers/net/wireless/intel/iwlwifi/mvm/tx.c | 3 +- 6 files changed, 49 insertions(+), 15 deletions(-) diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/txq.h b/drivers/net/wireless/intel/iwlwifi/fw/api/txq.h index 87b4434224a1..dfa111bb411e 100644 --- a/drivers/net/wireless/intel/iwlwifi/fw/api/txq.h +++ b/drivers/net/wireless/intel/iwlwifi/fw/api/txq.h @@ -68,6 +68,9 @@ * @IWL_MVM_DQA_CMD_QUEUE: a queue reserved for sending HCMDs to the FW * @IWL_MVM_DQA_AUX_QUEUE: a queue reserved for aux frames * @IWL_MVM_DQA_P2P_DEVICE_QUEUE: a queue reserved for P2P device frames + * @IWL_MVM_DQA_INJECT_MONITOR_QUEUE: a queue reserved for injection using + * monitor mode. Note this queue is the same as the queue for P2P device + * but we can't have active monitor mode along with P2P device anyway. * @IWL_MVM_DQA_GCAST_QUEUE: a queue reserved for P2P GO/SoftAP GCAST frames * @IWL_MVM_DQA_BSS_CLIENT_QUEUE: a queue reserved for BSS activity, to ensure * that we are never left without the possibility to connect to an AP. @@ -87,6 +90,7 @@ enum iwl_mvm_dqa_txq { IWL_MVM_DQA_CMD_QUEUE = 0, IWL_MVM_DQA_AUX_QUEUE = 1, IWL_MVM_DQA_P2P_DEVICE_QUEUE = 2, + IWL_MVM_DQA_INJECT_MONITOR_QUEUE = 2, IWL_MVM_DQA_GCAST_QUEUE = 3, IWL_MVM_DQA_BSS_CLIENT_QUEUE = 4, IWL_MVM_DQA_MIN_MGMT_QUEUE = 5, diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c index a2bf530eeae4..2f22e14e00fe 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c @@ -787,7 +787,7 @@ static int iwl_mvm_mac_ctxt_cmd_listener(struct iwl_mvm *mvm, u32 action) { struct iwl_mac_ctx_cmd cmd = {}; - u32 tfd_queue_msk = 0; + u32 tfd_queue_msk = BIT(mvm->snif_queue); int ret; WARN_ON(vif->type != NL80211_IFTYPE_MONITOR); diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h index 4575595ab022..6a9a25beab3f 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h +++ b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h @@ -972,6 +972,7 @@ struct iwl_mvm { /* Tx queues */ u16 aux_queue; + u16 snif_queue; u16 probe_queue; u16 p2p_dev_queue; diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c index 7078b7e458be..45470b6b351a 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c @@ -624,6 +624,7 @@ iwl_op_mode_mvm_start(struct iwl_trans *trans, const struct iwl_cfg *cfg, mvm->fw_restart = iwlwifi_mod_params.fw_restart ? -1 : 0; mvm->aux_queue = IWL_MVM_DQA_AUX_QUEUE; + mvm->snif_queue = IWL_MVM_DQA_INJECT_MONITOR_QUEUE; mvm->probe_queue = IWL_MVM_DQA_AP_PROBE_RESP_QUEUE; mvm->p2p_dev_queue = IWL_MVM_DQA_P2P_DEVICE_QUEUE; diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/sta.c b/drivers/net/wireless/intel/iwlwifi/mvm/sta.c index c19f98489d4e..1add5615fc3a 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/sta.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/sta.c @@ -1709,29 +1709,29 @@ void iwl_mvm_dealloc_int_sta(struct iwl_mvm *mvm, struct iwl_mvm_int_sta *sta) sta->sta_id = IWL_MVM_INVALID_STA; } -static void iwl_mvm_enable_aux_queue(struct iwl_mvm *mvm) +static void iwl_mvm_enable_aux_snif_queue(struct iwl_mvm *mvm, u16 *queue, + u8 sta_id, u8 fifo) { unsigned int wdg_timeout = iwlmvm_mod_params.tfd_q_hang_detect ? mvm->cfg->base_params->wd_timeout : IWL_WATCHDOG_DISABLED; if (iwl_mvm_has_new_tx_api(mvm)) { - int queue = iwl_mvm_tvqm_enable_txq(mvm, mvm->aux_queue, - mvm->aux_sta.sta_id, - IWL_MAX_TID_COUNT, - wdg_timeout); - mvm->aux_queue = queue; + int tvqm_queue = + iwl_mvm_tvqm_enable_txq(mvm, *queue, sta_id, + IWL_MAX_TID_COUNT, + wdg_timeout); + *queue = tvqm_queue; } else { struct iwl_trans_txq_scd_cfg cfg = { - .fifo = IWL_MVM_TX_FIFO_MCAST, - .sta_id = mvm->aux_sta.sta_id, + .fifo = fifo, + .sta_id = sta_id, .tid = IWL_MAX_TID_COUNT, .aggregate = false, .frame_limit = IWL_FRAME_LIMIT, }; - iwl_mvm_enable_txq(mvm, mvm->aux_queue, mvm->aux_queue, 0, &cfg, - wdg_timeout); + iwl_mvm_enable_txq(mvm, *queue, *queue, 0, &cfg, wdg_timeout); } } @@ -1750,7 +1750,9 @@ int iwl_mvm_add_aux_sta(struct iwl_mvm *mvm) /* Map Aux queue to fifo - needs to happen before adding Aux station */ if (!iwl_mvm_has_new_tx_api(mvm)) - iwl_mvm_enable_aux_queue(mvm); + iwl_mvm_enable_aux_snif_queue(mvm, &mvm->aux_queue, + mvm->aux_sta.sta_id, + IWL_MVM_TX_FIFO_MCAST); ret = iwl_mvm_add_int_sta_common(mvm, &mvm->aux_sta, NULL, MAC_INDEX_AUX, 0); @@ -1764,7 +1766,9 @@ int iwl_mvm_add_aux_sta(struct iwl_mvm *mvm) * to firmware so enable queue here - after the station was added */ if (iwl_mvm_has_new_tx_api(mvm)) - iwl_mvm_enable_aux_queue(mvm); + iwl_mvm_enable_aux_snif_queue(mvm, &mvm->aux_queue, + mvm->aux_sta.sta_id, + IWL_MVM_TX_FIFO_MCAST); return 0; } @@ -1772,10 +1776,31 @@ int iwl_mvm_add_aux_sta(struct iwl_mvm *mvm) int iwl_mvm_add_snif_sta(struct iwl_mvm *mvm, struct ieee80211_vif *vif) { struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif); + int ret; lockdep_assert_held(&mvm->mutex); - return iwl_mvm_add_int_sta_common(mvm, &mvm->snif_sta, vif->addr, + + /* Map snif queue to fifo - must happen before adding snif station */ + if (!iwl_mvm_has_new_tx_api(mvm)) + iwl_mvm_enable_aux_snif_queue(mvm, &mvm->snif_queue, + mvm->snif_sta.sta_id, + IWL_MVM_TX_FIFO_BE); + + ret = iwl_mvm_add_int_sta_common(mvm, &mvm->snif_sta, vif->addr, mvmvif->id, 0); + if (ret) + return ret; + + /* + * For 22000 firmware and on we cannot add queue to a station unknown + * to firmware so enable queue here - after the station was added + */ + if (iwl_mvm_has_new_tx_api(mvm)) + iwl_mvm_enable_aux_snif_queue(mvm, &mvm->snif_queue, + mvm->snif_sta.sta_id, + IWL_MVM_TX_FIFO_BE); + + return 0; } int iwl_mvm_rm_snif_sta(struct iwl_mvm *mvm, struct ieee80211_vif *vif) @@ -1784,6 +1809,8 @@ int iwl_mvm_rm_snif_sta(struct iwl_mvm *mvm, struct ieee80211_vif *vif) lockdep_assert_held(&mvm->mutex); + iwl_mvm_disable_txq(mvm, mvm->snif_queue, mvm->snif_queue, + IWL_MAX_TID_COUNT, 0); ret = iwl_mvm_rm_sta_common(mvm, mvm->snif_sta.sta_id); if (ret) IWL_WARN(mvm, "Failed sending remove station\n"); diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/tx.c b/drivers/net/wireless/intel/iwlwifi/mvm/tx.c index 593b7f97b29c..333bcb75b8af 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/tx.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/tx.c @@ -657,7 +657,8 @@ int iwl_mvm_tx_skb_non_sta(struct iwl_mvm *mvm, struct sk_buff *skb) if (ap_sta_id != IWL_MVM_INVALID_STA) sta_id = ap_sta_id; } else if (info.control.vif->type == NL80211_IFTYPE_MONITOR) { - queue = mvm->aux_queue; + queue = mvm->snif_queue; + sta_id = mvm->snif_sta.sta_id; } } -- GitLab From f3402d6d8eb084f6c2563dee1a09385b7c0ea2d5 Mon Sep 17 00:00:00 2001 From: Sara Sharon Date: Mon, 20 Nov 2017 11:37:18 +0200 Subject: [PATCH 0117/2547] iwlwifi: pcie: fix erroneous "Read failed message" Current pci dumping code code is always falling to the error path, resulting with a constant "Read failed" message, also for the successful reads. Fixes: a5c932e41fdd ("iwlwifi: pcie: dump registers when HW becomes inaccessible") Signed-off-by: Sara Sharon Signed-off-by: Luca Coelho --- drivers/net/wireless/intel/iwlwifi/pcie/trans.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c index b7a51603465b..3dee95e6a475 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c @@ -166,6 +166,7 @@ static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); } + goto out; err_read: print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); -- GitLab From 0232d2cd7aa8e1b810fe84fb4059a0bd1eabe2ba Mon Sep 17 00:00:00 2001 From: Sara Sharon Date: Mon, 20 Nov 2017 13:25:05 +0200 Subject: [PATCH 0118/2547] iwlwifi: fix access to prph when transport is stopped When getting HW rfkill we get stop_device being called from two paths. One path is the IRQ calling stop device, and updating op mode and stack. As a result, cfg80211 is running rfkill sync work that shuts down all devices (second path). In the second path, we eventually get to iwl_mvm_stop_device which calls iwl_fw_dump_conf_clear->iwl_fw_dbg_stop_recording, that access periphery registers. The device may be stopped at this point from the first path, which will result with a failure to access those registers. Simply checking for the trans status is insufficient, since the race will still exist, only minimized. Instead, move the stop from iwl_fw_dump_conf_clear (which is getting called only from stop path) to the transport stop device function, where the access is always safe. This has the added value, of actually stopping dbgc before stopping device even when the stop is initiated from the transport. Fixes: 1efc3843a4ee ("iwlwifi: stop dbgc recording before stopping DMA") Signed-off-by: Sara Sharon Signed-off-by: Luca Coelho --- drivers/net/wireless/intel/iwlwifi/fw/dbg.h | 2 -- drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c | 6 ++++++ drivers/net/wireless/intel/iwlwifi/pcie/trans.c | 9 +++++++++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg.h b/drivers/net/wireless/intel/iwlwifi/fw/dbg.h index 9c889a32fe24..223fb77a3aa9 100644 --- a/drivers/net/wireless/intel/iwlwifi/fw/dbg.h +++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg.h @@ -209,8 +209,6 @@ static inline void iwl_fw_dbg_stop_recording(struct iwl_fw_runtime *fwrt) static inline void iwl_fw_dump_conf_clear(struct iwl_fw_runtime *fwrt) { - iwl_fw_dbg_stop_recording(fwrt); - fwrt->dump.conf = FW_DBG_INVALID; } diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c index c59f4581e972..ac05fd1e74c4 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c @@ -49,6 +49,7 @@ * *****************************************************************************/ #include "iwl-trans.h" +#include "iwl-prph.h" #include "iwl-context-info.h" #include "internal.h" @@ -156,6 +157,11 @@ void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power) trans_pcie->is_down = true; + /* Stop dbgc before stopping device */ + iwl_write_prph(trans, DBGC_IN_SAMPLE, 0); + udelay(100); + iwl_write_prph(trans, DBGC_OUT_CTRL, 0); + /* tell the device to stop sending interrupts */ iwl_disable_interrupts(trans); diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c index 3dee95e6a475..4541c86881d6 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c @@ -1227,6 +1227,15 @@ static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) trans_pcie->is_down = true; + /* Stop dbgc before stopping device */ + if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { + iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); + } else { + iwl_write_prph(trans, DBGC_IN_SAMPLE, 0); + udelay(100); + iwl_write_prph(trans, DBGC_OUT_CTRL, 0); + } + /* tell the device to stop sending interrupts */ iwl_disable_interrupts(trans); -- GitLab From ad88d7fc6c032ddfb32b8d496a070ab71de3a64f Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 25 Nov 2017 19:41:55 +0000 Subject: [PATCH 0119/2547] drm/i915/fbdev: Serialise early hotplug events with async fbdev config As both the hotplug event and fbdev configuration run asynchronously, it is possible for them to run concurrently. If configuration fails, we were freeing the fbdev causing a use-after-free in the hotplug event. <7>[ 3069.935211] [drm:intel_fb_initial_config [i915]] Not using firmware configuration <7>[ 3069.935225] [drm:drm_setup_crtcs] looking for cmdline mode on connector 77 <7>[ 3069.935229] [drm:drm_setup_crtcs] looking for preferred mode on connector 77 0 <7>[ 3069.935233] [drm:drm_setup_crtcs] found mode 3200x1800 <7>[ 3069.935236] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config <7>[ 3069.935253] [drm:drm_setup_crtcs] desired mode 3200x1800 set on crtc 43 (0,0) <7>[ 3069.935323] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one <4>[ 3069.967737] general protection fault: 0000 [#1] PREEMPT SMP <0>[ 3069.977453] --------------------------------- <4>[ 3069.977457] Modules linked in: i915(+) vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic x86_pkg_temp_thermal intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm r8169 mei_me mii prime_numbers mei i2c_hid pinctrl_geminilake pinctrl_intel [last unloaded: i915] <4>[ 3069.977492] CPU: 1 PID: 15414 Comm: kworker/1:0 Tainted: G U 4.14.0-CI-CI_DRM_3388+ #1 <4>[ 3069.977497] Hardware name: Intel Corp. Geminilake/GLK RVP1 DDR4 (05), BIOS GELKRVPA.X64.0062.B30.1708222146 08/22/2017 <4>[ 3069.977508] Workqueue: events output_poll_execute <4>[ 3069.977512] task: ffff880177734e40 task.stack: ffffc90001fe4000 <4>[ 3069.977519] RIP: 0010:__lock_acquire+0x109/0x1b60 <4>[ 3069.977523] RSP: 0018:ffffc90001fe7bb0 EFLAGS: 00010002 <4>[ 3069.977526] RAX: 6b6b6b6b6b6b6b6b RBX: 0000000000000282 RCX: 0000000000000000 <4>[ 3069.977530] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffff880170d4efd0 <4>[ 3069.977534] RBP: ffffc90001fe7c70 R08: 0000000000000001 R09: 0000000000000000 <4>[ 3069.977538] R10: 0000000000000000 R11: ffffffff81899609 R12: ffff880170d4efd0 <4>[ 3069.977542] R13: ffff880177734e40 R14: 0000000000000001 R15: 0000000000000000 <4>[ 3069.977547] FS: 0000000000000000(0000) GS:ffff88017fc80000(0000) knlGS:0000000000000000 <4>[ 3069.977551] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4>[ 3069.977555] CR2: 00007f7e8b7bcf04 CR3: 0000000003e0f000 CR4: 00000000003406e0 <4>[ 3069.977559] Call Trace: <4>[ 3069.977565] ? mark_held_locks+0x64/0x90 <4>[ 3069.977571] ? _raw_spin_unlock_irq+0x24/0x50 <4>[ 3069.977575] ? _raw_spin_unlock_irq+0x24/0x50 <4>[ 3069.977579] ? trace_hardirqs_on_caller+0xde/0x1c0 <4>[ 3069.977583] ? _raw_spin_unlock_irq+0x2f/0x50 <4>[ 3069.977588] ? finish_task_switch+0xa5/0x210 <4>[ 3069.977592] ? lock_acquire+0xaf/0x200 <4>[ 3069.977596] lock_acquire+0xaf/0x200 <4>[ 3069.977600] ? __mutex_lock+0x5e9/0x9b0 <4>[ 3069.977604] _raw_spin_lock+0x2a/0x40 <4>[ 3069.977608] ? __mutex_lock+0x5e9/0x9b0 <4>[ 3069.977612] __mutex_lock+0x5e9/0x9b0 <4>[ 3069.977616] ? drm_fb_helper_hotplug_event.part.19+0x16/0xa0 <4>[ 3069.977621] ? drm_fb_helper_hotplug_event.part.19+0x16/0xa0 <4>[ 3069.977625] drm_fb_helper_hotplug_event.part.19+0x16/0xa0 <4>[ 3069.977630] output_poll_execute+0x8d/0x180 <4>[ 3069.977635] process_one_work+0x22e/0x660 <4>[ 3069.977640] worker_thread+0x48/0x3a0 <4>[ 3069.977644] ? _raw_spin_unlock_irqrestore+0x4c/0x60 <4>[ 3069.977649] kthread+0x102/0x140 <4>[ 3069.977653] ? process_one_work+0x660/0x660 <4>[ 3069.977657] ? kthread_create_on_node+0x40/0x40 <4>[ 3069.977662] ret_from_fork+0x27/0x40 <4>[ 3069.977666] Code: 8d 62 f8 c3 49 81 3c 24 e0 fa 3c 82 41 be 00 00 00 00 45 0f 45 f0 83 fe 01 77 86 89 f0 49 8b 44 c4 08 48 85 c0 0f 84 76 ff ff ff ff 80 38 01 00 00 8b 1d 62 f9 e8 01 45 8b 85 b8 08 00 00 85 <1>[ 3069.977707] RIP: __lock_acquire+0x109/0x1b60 RSP: ffffc90001fe7bb0 <4>[ 3069.977712] ---[ end trace 4ad012eb3af62df7 ]--- In order to keep the dev_priv->ifbdev alive after failure, we have to avoid the free and leave it empty until we unload the module (which is less than ideal, but a necessary evil for simplicity). Then we can use intel_fbdev_sync() to serialise the hotplug event with the configuration. The serialisation between the two was removed in commit 934458c2c95d ("Revert "drm/i915: Fix races on fbdev""), but the use after free is much older, commit 366e39b4d2c5 ("drm/i915: Tear down fbdev if initialization fails") Fixes: 366e39b4d2c5 ("drm/i915: Tear down fbdev if initialization fails") Fixes: 934458c2c95d ("Revert "drm/i915: Fix races on fbdev"") Signed-off-by: Chris Wilson Cc: Lukas Wunner Cc: Joonas Lahtinen Cc: Daniel Vetter Cc: stable@vger.kernel.org Reviewed-by: Lukas Wunner Link: https://patchwork.freedesktop.org/patch/msgid/20171125194155.355-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_fbdev.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index b8af35187d22..ea96682568e8 100644 --- a/drivers/gpu/drm/i915/intel_fbdev.c +++ b/drivers/gpu/drm/i915/intel_fbdev.c @@ -697,10 +697,8 @@ static void intel_fbdev_initial_config(void *data, async_cookie_t cookie) /* Due to peculiar init order wrt to hpd handling this is separate. */ if (drm_fb_helper_initial_config(&ifbdev->helper, - ifbdev->preferred_bpp)) { + ifbdev->preferred_bpp)) intel_fbdev_unregister(to_i915(ifbdev->helper.dev)); - intel_fbdev_fini(to_i915(ifbdev->helper.dev)); - } } void intel_fbdev_initial_config_async(struct drm_device *dev) @@ -800,7 +798,11 @@ void intel_fbdev_output_poll_changed(struct drm_device *dev) { struct intel_fbdev *ifbdev = to_i915(dev)->fbdev; - if (ifbdev) + if (!ifbdev) + return; + + intel_fbdev_sync(ifbdev); + if (ifbdev->vma) drm_fb_helper_hotplug_event(&ifbdev->helper); } -- GitLab From 5ddc3c656bfb5c90d0196ff72b908d0343fef85e Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Sat, 25 Nov 2017 15:48:32 -0800 Subject: [PATCH 0120/2547] Input: ims-pcu - fix typo in the error message 1. change "to" to "too". 2. move ")" to the front of "\n", which discovered by Joe Perches. Signed-off-by: Zhen Lei Reviewed-by: Joe Perches Signed-off-by: Dmitry Torokhov --- drivers/input/misc/ims-pcu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/input/misc/ims-pcu.c b/drivers/input/misc/ims-pcu.c index ae473123583b..3d51175c4d72 100644 --- a/drivers/input/misc/ims-pcu.c +++ b/drivers/input/misc/ims-pcu.c @@ -1651,7 +1651,7 @@ ims_pcu_get_cdc_union_desc(struct usb_interface *intf) return union_desc; dev_err(&intf->dev, - "Union descriptor to short (%d vs %zd\n)", + "Union descriptor too short (%d vs %zd)\n", union_desc->bLength, sizeof(*union_desc)); return NULL; } -- GitLab From 10d900303f1c3a821eb0bef4e7b7ece16768fba4 Mon Sep 17 00:00:00 2001 From: Aaron Ma Date: Sat, 25 Nov 2017 16:48:41 -0800 Subject: [PATCH 0121/2547] Input: elantech - add new icbody type 15 The touchpad of Lenovo Thinkpad L480 reports it's version as 15. Cc: stable@vger.kernel.org Signed-off-by: Aaron Ma Signed-off-by: Dmitry Torokhov --- drivers/input/mouse/elantech.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/input/mouse/elantech.c b/drivers/input/mouse/elantech.c index b84cd978fce2..a4aaa748e987 100644 --- a/drivers/input/mouse/elantech.c +++ b/drivers/input/mouse/elantech.c @@ -1613,7 +1613,7 @@ static int elantech_set_properties(struct elantech_data *etd) case 5: etd->hw_version = 3; break; - case 6 ... 14: + case 6 ... 15: etd->hw_version = 4; break; default: -- GitLab From bdfe4cebea11476d278b1b98dd0f7cdac8269d62 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 10 Nov 2017 17:26:54 +0800 Subject: [PATCH 0122/2547] arm64: allwinner: a64: add Ethernet PHY regulator for several boards On several A64 boards the Ethernet PHY is powered by the DC1SW regulator on the AXP803 PMIC. Add phy-handle property to these boards' emac node. Signed-off-by: Icenowy Zheng Acked-by: Corentin LABBE Tested-by: Corentin LABBE Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 1 + arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 1 + arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 45bdbfb96126..4a8d3f83a36e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -75,6 +75,7 @@ pinctrl-0 = <&rgmii_pins>; phy-mode = "rgmii"; phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dc1sw>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index 806442d3e846..604cdaedac38 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -77,6 +77,7 @@ pinctrl-0 = <&rmii_pins>; phy-mode = "rmii"; phy-handle = <&ext_rmii_phy1>; + phy-supply = <®_dc1sw>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 0eb2acedf8c3..a053a6ac5267 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -82,6 +82,7 @@ pinctrl-0 = <&rgmii_pins>; phy-mode = "rgmii"; phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dc1sw>; status = "okay"; }; -- GitLab From c654b21ede93845863597de9ad774fd30db5f2ab Mon Sep 17 00:00:00 2001 From: Sebastian Sjoholm Date: Mon, 20 Nov 2017 19:29:32 +0100 Subject: [PATCH 0123/2547] USB: serial: option: add Quectel BG96 id Quectel BG96 is an Qualcomm MDM9206 based IoT modem, supporting both CAT-M and NB-IoT. Tested hardware is BG96 mounted on Quectel development board (EVB). The USB id is added to option.c to allow DIAG,GPS,AT and modem communication with the BG96. Signed-off-by: Sebastian Sjoholm Cc: stable Signed-off-by: Johan Hovold --- drivers/usb/serial/option.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index aaa7d901a06d..3b3513874cfd 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -238,6 +238,7 @@ static void option_instat_callback(struct urb *urb); /* These Quectel products use Quectel's vendor ID */ #define QUECTEL_PRODUCT_EC21 0x0121 #define QUECTEL_PRODUCT_EC25 0x0125 +#define QUECTEL_PRODUCT_BG96 0x0296 #define CMOTECH_VENDOR_ID 0x16d8 #define CMOTECH_PRODUCT_6001 0x6001 @@ -1182,6 +1183,8 @@ static const struct usb_device_id option_ids[] = { .driver_info = (kernel_ulong_t)&net_intf4_blacklist }, { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC25), .driver_info = (kernel_ulong_t)&net_intf4_blacklist }, + { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), + .driver_info = (kernel_ulong_t)&net_intf4_blacklist }, { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6001) }, { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_CMU_300) }, { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6003), -- GitLab From 30bf90ccdec1da9c8198b161ecbff39ce4e5a9ba Mon Sep 17 00:00:00 2001 From: Vincent Pelletier Date: Sun, 26 Nov 2017 06:52:53 +0000 Subject: [PATCH 0124/2547] usb: gadget: ffs: Forbid usb_ep_alloc_request from sleeping Found using DEBUG_ATOMIC_SLEEP while submitting an AIO read operation: [ 100.853642] BUG: sleeping function called from invalid context at mm/slab.h:421 [ 100.861148] in_atomic(): 1, irqs_disabled(): 1, pid: 1880, name: python [ 100.867954] 2 locks held by python/1880: [ 100.867961] #0: (&epfile->mutex){....}, at: [] ffs_mutex_lock+0x27/0x30 [usb_f_fs] [ 100.868020] #1: (&(&ffs->eps_lock)->rlock){....}, at: [] ffs_epfile_io.isra.17+0x24b/0x590 [usb_f_fs] [ 100.868076] CPU: 1 PID: 1880 Comm: python Not tainted 4.14.0-edison+ #118 [ 100.868085] Hardware name: Intel Corporation Merrifield/BODEGA BAY, BIOS 542 2015.01.21:18.19.48 [ 100.868093] Call Trace: [ 100.868122] dump_stack+0x47/0x62 [ 100.868156] ___might_sleep+0xfd/0x110 [ 100.868182] __might_sleep+0x68/0x70 [ 100.868217] kmem_cache_alloc_trace+0x4b/0x200 [ 100.868248] ? dwc3_gadget_ep_alloc_request+0x24/0xe0 [dwc3] [ 100.868302] dwc3_gadget_ep_alloc_request+0x24/0xe0 [dwc3] [ 100.868343] usb_ep_alloc_request+0x16/0xc0 [udc_core] [ 100.868386] ffs_epfile_io.isra.17+0x444/0x590 [usb_f_fs] [ 100.868424] ? _raw_spin_unlock_irqrestore+0x27/0x40 [ 100.868457] ? kiocb_set_cancel_fn+0x57/0x60 [ 100.868477] ? ffs_ep0_poll+0xc0/0xc0 [usb_f_fs] [ 100.868512] ffs_epfile_read_iter+0xfe/0x157 [usb_f_fs] [ 100.868551] ? security_file_permission+0x9c/0xd0 [ 100.868587] ? rw_verify_area+0xac/0x120 [ 100.868633] aio_read+0x9d/0x100 [ 100.868692] ? __fget+0xa2/0xd0 [ 100.868727] ? __might_sleep+0x68/0x70 [ 100.868763] SyS_io_submit+0x471/0x680 [ 100.868878] do_int80_syscall_32+0x4e/0xd0 [ 100.868921] entry_INT80_32+0x2a/0x2a [ 100.868932] EIP: 0xb7fbb676 [ 100.868941] EFLAGS: 00000292 CPU: 1 [ 100.868951] EAX: ffffffda EBX: b7aa2000 ECX: 00000002 EDX: b7af8368 [ 100.868961] ESI: b7fbb660 EDI: b7aab000 EBP: bfb6c658 ESP: bfb6c638 [ 100.868973] DS: 007b ES: 007b FS: 0000 GS: 0033 SS: 007b Signed-off-by: Vincent Pelletier Signed-off-by: Felipe Balbi --- drivers/usb/gadget/function/f_fs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index 97ea059a7aa4..9aa457b53e01 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -1012,7 +1012,7 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data) else ret = ep->status; goto error_mutex; - } else if (!(req = usb_ep_alloc_request(ep->ep, GFP_KERNEL))) { + } else if (!(req = usb_ep_alloc_request(ep->ep, GFP_ATOMIC))) { ret = -ENOMEM; } else { req->buf = data; -- GitLab From 593e789fd4421635bde09398b8a8fb510b18414a Mon Sep 17 00:00:00 2001 From: Vasyl Gomonovych Date: Wed, 22 Nov 2017 16:28:00 +0100 Subject: [PATCH 0125/2547] usb: bdc: fix platform_no_drv_owner.cocci warnings Remove .owner field if calls are used which set it automatically drivers/usb/gadget/udc/bdc/bdc_core.c:645:3-8: No need to set .owner here. The core will do it. Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Vasyl Gomonovych Signed-off-by: Felipe Balbi --- drivers/usb/gadget/udc/bdc/bdc_core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/gadget/udc/bdc/bdc_core.c b/drivers/usb/gadget/udc/bdc/bdc_core.c index d39f070acbd7..01b44e159623 100644 --- a/drivers/usb/gadget/udc/bdc/bdc_core.c +++ b/drivers/usb/gadget/udc/bdc/bdc_core.c @@ -642,7 +642,6 @@ static const struct of_device_id bdc_of_match[] = { static struct platform_driver bdc_driver = { .driver = { .name = BRCM_BDC_NAME, - .owner = THIS_MODULE, .pm = &bdc_pm_ops, .of_match_table = bdc_of_match, }, -- GitLab From 46e42a303178ca1341d1ab3e0b5c1227b89b60ee Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Nov 2017 08:26:54 -0500 Subject: [PATCH 0126/2547] media: dvb_ca_en50221: fix lots of documentation warnings Building the driver with gcc 7.2.1 and: make ARCH=i386 CF=-D__CHECK_ENDIAN__ CONFIG_DEBUG_SECTION_MISMATCH=y W=1 CHECK='' M=drivers/media now produces a lot of warnings: drivers/media/dvb-core/dvb_ca_en50221.c:233: warning: No description found for parameter 'ca' drivers/media/dvb-core/dvb_ca_en50221.c:233: warning: No description found for parameter 'slot' drivers/media/dvb-core/dvb_ca_en50221.c:284: warning: No description found for parameter 'timeout_hz' drivers/media/dvb-core/dvb_ca_en50221.c:284: warning: Excess function parameter 'timeout_ms' description in 'dvb_ca_en50221_wait_if_status' drivers/media/dvb-core/dvb_ca_en50221.c:409: warning: No description found for parameter 'tuple_type' drivers/media/dvb-core/dvb_ca_en50221.c:409: warning: No description found for parameter 'tuple_length' drivers/media/dvb-core/dvb_ca_en50221.c:409: warning: Excess function parameter 'tupleType' description in 'dvb_ca_en50221_read_tuple' drivers/media/dvb-core/dvb_ca_en50221.c:409: warning: Excess function parameter 'tupleLength' description in 'dvb_ca_en50221_read_tuple' drivers/media/dvb-core/dvb_ca_en50221.c:795: warning: No description found for parameter 'buf' drivers/media/dvb-core/dvb_ca_en50221.c:795: warning: No description found for parameter 'bytes_write' drivers/media/dvb-core/dvb_ca_en50221.c:795: warning: Excess function parameter 'ebuf' description in 'dvb_ca_en50221_write_data' drivers/media/dvb-core/dvb_ca_en50221.c:795: warning: Excess function parameter 'count' description in 'dvb_ca_en50221_write_data' drivers/media/dvb-core/dvb_ca_en50221.c:942: warning: No description found for parameter 'pubca' drivers/media/dvb-core/dvb_ca_en50221.c:942: warning: Excess function parameter 'ca' description in 'dvb_ca_en50221_camchange_irq' drivers/media/dvb-core/dvb_ca_en50221.c:970: warning: No description found for parameter 'pubca' drivers/media/dvb-core/dvb_ca_en50221.c:970: warning: Excess function parameter 'ca' description in 'dvb_ca_en50221_camready_irq' drivers/media/dvb-core/dvb_ca_en50221.c:990: warning: No description found for parameter 'pubca' drivers/media/dvb-core/dvb_ca_en50221.c:990: warning: Excess function parameter 'ca' description in 'dvb_ca_en50221_frda_irq' drivers/media/dvb-core/dvb_ca_en50221.c:1304: warning: No description found for parameter 'data' drivers/media/dvb-core/dvb_ca_en50221.c:1348: warning: No description found for parameter 'parg' drivers/media/dvb-core/dvb_ca_en50221.c:1348: warning: Excess function parameter 'inode' description in 'dvb_ca_en50221_io_do_ioctl' drivers/media/dvb-core/dvb_ca_en50221.c:1348: warning: Excess function parameter 'arg' description in 'dvb_ca_en50221_io_do_ioctl' drivers/media/dvb-core/dvb_ca_en50221.c:1432: warning: Excess function parameter 'inode' description in 'dvb_ca_en50221_io_ioctl' drivers/media/dvb-core/dvb_ca_en50221.c:1544: warning: No description found for parameter 'ca' drivers/media/dvb-core/dvb_ca_en50221.c:1544: warning: No description found for parameter 'result' drivers/media/dvb-core/dvb_ca_en50221.c:1544: warning: No description found for parameter '_slot' drivers/media/dvb-core/dvb_ca_en50221.c:1849: warning: No description found for parameter 'pubca' drivers/media/dvb-core/dvb_ca_en50221.c:1849: warning: Excess function parameter 'ca' description in 'dvb_ca_en50221_init' drivers/media/dvb-core/dvb_ca_en50221.c:1936: warning: No description found for parameter 'pubca' drivers/media/dvb-core/dvb_ca_en50221.c:1936: warning: Excess function parameter 'ca_dev' description in 'dvb_ca_en50221_release' drivers/media/dvb-core/dvb_ca_en50221.c:1936: warning: Excess function parameter 'ca' description in 'dvb_ca_en50221_release' Trivially fix them. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-core/dvb_ca_en50221.c | 68 ++++++++++++------------- 1 file changed, 33 insertions(+), 35 deletions(-) diff --git a/drivers/media/dvb-core/dvb_ca_en50221.c b/drivers/media/dvb-core/dvb_ca_en50221.c index 95b3723282f4..d48b61eb01f4 100644 --- a/drivers/media/dvb-core/dvb_ca_en50221.c +++ b/drivers/media/dvb-core/dvb_ca_en50221.c @@ -206,7 +206,7 @@ static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, * @hlen: Number of bytes in haystack. * @needle: Buffer to find. * @nlen: Number of bytes in needle. - * @return Pointer into haystack needle was found at, or NULL if not found. + * return: Pointer into haystack needle was found at, or NULL if not found. */ static char *findstr(char *haystack, int hlen, char *needle, int nlen) { @@ -226,7 +226,7 @@ static char *findstr(char *haystack, int hlen, char *needle, int nlen) /* ************************************************************************** */ /* EN50221 physical interface functions */ -/** +/* * dvb_ca_en50221_check_camstatus - Check CAM status. */ static int dvb_ca_en50221_check_camstatus(struct dvb_ca_private *ca, int slot) @@ -275,9 +275,9 @@ static int dvb_ca_en50221_check_camstatus(struct dvb_ca_private *ca, int slot) * @ca: CA instance. * @slot: Slot on interface. * @waitfor: Flags to wait for. - * @timeout_ms: Timeout in milliseconds. + * @timeout_hz: Timeout in milliseconds. * - * @return 0 on success, nonzero on error. + * return: 0 on success, nonzero on error. */ static int dvb_ca_en50221_wait_if_status(struct dvb_ca_private *ca, int slot, u8 waitfor, int timeout_hz) @@ -325,7 +325,7 @@ static int dvb_ca_en50221_wait_if_status(struct dvb_ca_private *ca, int slot, * @ca: CA instance. * @slot: Slot id. * - * @return 0 on success, nonzero on failure. + * return: 0 on success, nonzero on failure. */ static int dvb_ca_en50221_link_init(struct dvb_ca_private *ca, int slot) { @@ -397,11 +397,11 @@ static int dvb_ca_en50221_link_init(struct dvb_ca_private *ca, int slot) * @ca: CA instance. * @slot: Slot id. * @address: Address to read from. Updated. - * @tupleType: Tuple id byte. Updated. - * @tupleLength: Tuple length. Updated. + * @tuple_type: Tuple id byte. Updated. + * @tuple_length: Tuple length. Updated. * @tuple: Dest buffer for tuple (must be 256 bytes). Updated. * - * @return 0 on success, nonzero on error. + * return: 0 on success, nonzero on error. */ static int dvb_ca_en50221_read_tuple(struct dvb_ca_private *ca, int slot, int *address, int *tuple_type, @@ -455,7 +455,7 @@ static int dvb_ca_en50221_read_tuple(struct dvb_ca_private *ca, int slot, * @ca: CA instance. * @slot: Slot id. * - * @return 0 on success, <0 on failure. + * return: 0 on success, <0 on failure. */ static int dvb_ca_en50221_parse_attributes(struct dvb_ca_private *ca, int slot) { @@ -632,10 +632,11 @@ static int dvb_ca_en50221_set_configoption(struct dvb_ca_private *ca, int slot) * @ca: CA instance. * @slot: Slot to read from. * @ebuf: If non-NULL, the data will be written to this buffer. If NULL, - * the data will be added into the buffering system as a normal fragment. + * the data will be added into the buffering system as a normal + * fragment. * @ecount: Size of ebuf. Ignored if ebuf is NULL. * - * @return Number of bytes read, or < 0 on error + * return: Number of bytes read, or < 0 on error */ static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot, u8 *ebuf, int ecount) @@ -784,11 +785,11 @@ static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot, * * @ca: CA instance. * @slot: Slot to write to. - * @ebuf: The data in this buffer is treated as a complete link-level packet to - * be written. - * @count: Size of ebuf. + * @buf: The data in this buffer is treated as a complete link-level packet to + * be written. + * @bytes_write: Size of ebuf. * - * @return Number of bytes written, or < 0 on error. + * return: Number of bytes written, or < 0 on error. */ static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, u8 *buf, int bytes_write) @@ -933,7 +934,7 @@ static int dvb_ca_en50221_slot_shutdown(struct dvb_ca_private *ca, int slot) /** * dvb_ca_en50221_camchange_irq - A CAMCHANGE IRQ has occurred. * - * @ca: CA instance. + * @pubca: CA instance. * @slot: Slot concerned. * @change_type: One of the DVB_CA_CAMCHANGE_* values. */ @@ -963,7 +964,7 @@ EXPORT_SYMBOL(dvb_ca_en50221_camchange_irq); /** * dvb_ca_en50221_camready_irq - A CAMREADY IRQ has occurred. * - * @ca: CA instance. + * @pubca: CA instance. * @slot: Slot concerned. */ void dvb_ca_en50221_camready_irq(struct dvb_ca_en50221 *pubca, int slot) @@ -983,7 +984,7 @@ EXPORT_SYMBOL(dvb_ca_en50221_camready_irq); /** * dvb_ca_en50221_frda_irq - An FR or DA IRQ has occurred. * - * @ca: CA instance. + * @pubca: CA instance. * @slot: Slot concerned. */ void dvb_ca_en50221_frda_irq(struct dvb_ca_en50221 *pubca, int slot) @@ -1091,7 +1092,7 @@ static void dvb_ca_en50221_thread_update_delay(struct dvb_ca_private *ca) * * @ca: CA instance. * @slot: Slot to process. - * @return: 0 .. no change + * return:: 0 .. no change * 1 .. CAM state changed */ @@ -1296,7 +1297,7 @@ static void dvb_ca_en50221_thread_state_machine(struct dvb_ca_private *ca, mutex_unlock(&sl->slot_lock); } -/** +/* * Kernel thread which monitors CA slots for CAM changes, and performs data * transfers. */ @@ -1336,12 +1337,11 @@ static int dvb_ca_en50221_thread(void *data) * Real ioctl implementation. * NOTE: CA_SEND_MSG/CA_GET_MSG ioctls have userspace buffers passed to them. * - * @inode: Inode concerned. * @file: File concerned. * @cmd: IOCTL command. - * @arg: Associated argument. + * @parg: Associated argument. * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ static int dvb_ca_en50221_io_do_ioctl(struct file *file, unsigned int cmd, void *parg) @@ -1420,12 +1420,11 @@ static int dvb_ca_en50221_io_do_ioctl(struct file *file, /** * Wrapper for ioctl implementation. * - * @inode: Inode concerned. * @file: File concerned. * @cmd: IOCTL command. * @arg: Associated argument. * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ static long dvb_ca_en50221_io_ioctl(struct file *file, unsigned int cmd, unsigned long arg) @@ -1441,7 +1440,7 @@ static long dvb_ca_en50221_io_ioctl(struct file *file, * @count: Size of source buffer. * @ppos: Position in file (ignored). * - * @return Number of bytes read, or <0 on error. + * return: Number of bytes read, or <0 on error. */ static ssize_t dvb_ca_en50221_io_write(struct file *file, const char __user *buf, size_t count, @@ -1536,7 +1535,7 @@ static ssize_t dvb_ca_en50221_io_write(struct file *file, return status; } -/** +/* * Condition for waking up in dvb_ca_en50221_io_read_condition */ static int dvb_ca_en50221_io_read_condition(struct dvb_ca_private *ca, @@ -1593,7 +1592,7 @@ static int dvb_ca_en50221_io_read_condition(struct dvb_ca_private *ca, * @count: Size of destination buffer. * @ppos: Position in file (ignored). * - * @return Number of bytes read, or <0 on error. + * return: Number of bytes read, or <0 on error. */ static ssize_t dvb_ca_en50221_io_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) @@ -1702,7 +1701,7 @@ static ssize_t dvb_ca_en50221_io_read(struct file *file, char __user *buf, * @inode: Inode concerned. * @file: File concerned. * - * @return 0 on success, <0 on failure. + * return: 0 on success, <0 on failure. */ static int dvb_ca_en50221_io_open(struct inode *inode, struct file *file) { @@ -1752,7 +1751,7 @@ static int dvb_ca_en50221_io_open(struct inode *inode, struct file *file) * @inode: Inode concerned. * @file: File concerned. * - * @return 0 on success, <0 on failure. + * return: 0 on success, <0 on failure. */ static int dvb_ca_en50221_io_release(struct inode *inode, struct file *file) { @@ -1781,7 +1780,7 @@ static int dvb_ca_en50221_io_release(struct inode *inode, struct file *file) * @file: File concerned. * @wait: poll wait table. * - * @return Standard poll mask. + * return: Standard poll mask. */ static unsigned int dvb_ca_en50221_io_poll(struct file *file, poll_table *wait) { @@ -1838,11 +1837,11 @@ static const struct dvb_device dvbdev_ca = { * Initialise a new DVB CA EN50221 interface device. * * @dvb_adapter: DVB adapter to attach the new CA device to. - * @ca: The dvb_ca instance. + * @pubca: The dvb_ca instance. * @flags: Flags describing the CA device (DVB_CA_FLAG_*). * @slot_count: Number of slots supported. * - * @return 0 on success, nonzero on failure + * return: 0 on success, nonzero on failure */ int dvb_ca_en50221_init(struct dvb_adapter *dvb_adapter, struct dvb_ca_en50221 *pubca, int flags, int slot_count) @@ -1929,8 +1928,7 @@ EXPORT_SYMBOL(dvb_ca_en50221_init); /** * Release a DVB CA EN50221 interface device. * - * @ca_dev: The dvb_device_t instance for the CA device. - * @ca: The associated dvb_ca instance. + * @pubca: The associated dvb_ca instance. */ void dvb_ca_en50221_release(struct dvb_ca_en50221 *pubca) { -- GitLab From f67f366c69c8e2287cfe32a3b2406ff706b43075 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Nov 2017 08:35:13 -0500 Subject: [PATCH 0127/2547] media: rc: fix lots of documentation warnings Building the driver with gcc 7.2.1 and: make ARCH=i386 CF=-D__CHECK_ENDIAN__ CONFIG_DEBUG_SECTION_MISMATCH=y W=1 CHECK='' M=drivers/media now produces a lot of warnings: drivers/media/rc/rc-main.c:278: warning: No description found for parameter 'new_keycode' drivers/media/rc/rc-main.c:278: warning: Excess function parameter 'keycode' description in 'ir_update_mapping' drivers/media/rc/rc-main.c:387: warning: No description found for parameter 'ke' drivers/media/rc/rc-main.c:387: warning: No description found for parameter 'old_keycode' drivers/media/rc/rc-main.c:387: warning: Excess function parameter 'scancode' description in 'ir_setkeycode' drivers/media/rc/rc-main.c:387: warning: Excess function parameter 'keycode' description in 'ir_setkeycode' drivers/media/rc/rc-main.c:433: warning: Excess function parameter 'to' description in 'ir_setkeytable' drivers/media/rc/rc-main.c:506: warning: No description found for parameter 'ke' drivers/media/rc/rc-main.c:506: warning: Excess function parameter 'scancode' description in 'ir_getkeycode' drivers/media/rc/rc-main.c:506: warning: Excess function parameter 'keycode' description in 'ir_getkeycode' drivers/media/rc/rc-main.c:634: warning: No description found for parameter 't' drivers/media/rc/rc-main.c:634: warning: Excess function parameter 'cookie' description in 'ir_timer_keyup' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/rc-main.c | 46 +++++++++++++++++++++++--------------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index 17950e29d4e3..c4b0217bd169 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -170,10 +170,11 @@ static struct rc_map_list empty_map = { * @name: name to assign to the table * @rc_proto: ir type to assign to the new table * @size: initial size of the table - * @return: zero on success or a negative error code * * This routine will initialize the rc_map and will allocate * memory to hold at least the specified number of elements. + * + * return: zero on success or a negative error code */ static int ir_create_table(struct rc_map *rc_map, const char *name, u64 rc_proto, size_t size) @@ -216,10 +217,11 @@ static void ir_free_table(struct rc_map *rc_map) * ir_resize_table() - resizes a scancode table if necessary * @rc_map: the rc_map to resize * @gfp_flags: gfp flags to use when allocating memory - * @return: zero on success or a negative error code * * This routine will shrink the rc_map if it has lots of * unused entries and grow it if it is full. + * + * return: zero on success or a negative error code */ static int ir_resize_table(struct rc_map *rc_map, gfp_t gfp_flags) { @@ -265,11 +267,13 @@ static int ir_resize_table(struct rc_map *rc_map, gfp_t gfp_flags) * @dev: the struct rc_dev device descriptor * @rc_map: scancode table to be adjusted * @index: index of the mapping that needs to be updated - * @keycode: the desired keycode - * @return: previous keycode assigned to the mapping + * @new_keycode: the desired keycode * * This routine is used to update scancode->keycode mapping at given * position. + * + * return: previous keycode assigned to the mapping + * */ static unsigned int ir_update_mapping(struct rc_dev *dev, struct rc_map *rc_map, @@ -320,12 +324,13 @@ static unsigned int ir_update_mapping(struct rc_dev *dev, * @scancode: the desired scancode * @resize: controls whether we allowed to resize the table to * accommodate not yet present scancodes - * @return: index of the mapping containing scancode in question - * or -1U in case of failure. * * This routine is used to locate given scancode in rc_map. * If scancode is not yet present the routine will allocate a new slot * for it. + * + * return: index of the mapping containing scancode in question + * or -1U in case of failure. */ static unsigned int ir_establish_scancode(struct rc_dev *dev, struct rc_map *rc_map, @@ -375,11 +380,12 @@ static unsigned int ir_establish_scancode(struct rc_dev *dev, /** * ir_setkeycode() - set a keycode in the scancode->keycode table * @idev: the struct input_dev device descriptor - * @scancode: the desired scancode - * @keycode: result - * @return: -EINVAL if the keycode could not be inserted, otherwise zero. + * @ke: Input keymap entry + * @old_keycode: result * * This routine is used to handle evdev EVIOCSKEY ioctl. + * + * return: -EINVAL if the keycode could not be inserted, otherwise zero. */ static int ir_setkeycode(struct input_dev *idev, const struct input_keymap_entry *ke, @@ -422,11 +428,11 @@ static int ir_setkeycode(struct input_dev *idev, /** * ir_setkeytable() - sets several entries in the scancode->keycode table * @dev: the struct rc_dev device descriptor - * @to: the struct rc_map to copy entries to * @from: the struct rc_map to copy entries from - * @return: -ENOMEM if all keycodes could not be inserted, otherwise zero. * * This routine is used to handle table initialization. + * + * return: -ENOMEM if all keycodes could not be inserted, otherwise zero. */ static int ir_setkeytable(struct rc_dev *dev, const struct rc_map *from) @@ -474,10 +480,11 @@ static int rc_map_cmp(const void *key, const void *elt) * ir_lookup_by_scancode() - locate mapping by scancode * @rc_map: the struct rc_map to search * @scancode: scancode to look for in the table - * @return: index in the table, -1U if not found * * This routine performs binary search in RC keykeymap table for * given scancode. + * + * return: index in the table, -1U if not found */ static unsigned int ir_lookup_by_scancode(const struct rc_map *rc_map, unsigned int scancode) @@ -495,11 +502,11 @@ static unsigned int ir_lookup_by_scancode(const struct rc_map *rc_map, /** * ir_getkeycode() - get a keycode from the scancode->keycode table * @idev: the struct input_dev device descriptor - * @scancode: the desired scancode - * @keycode: used to return the keycode, if found, or KEY_RESERVED - * @return: always returns zero. + * @ke: Input keymap entry * * This routine is used to handle evdev EVIOCGKEY ioctl. + * + * return: always returns zero. */ static int ir_getkeycode(struct input_dev *idev, struct input_keymap_entry *ke) @@ -556,11 +563,12 @@ static int ir_getkeycode(struct input_dev *idev, * rc_g_keycode_from_table() - gets the keycode that corresponds to a scancode * @dev: the struct rc_dev descriptor of the device * @scancode: the scancode to look for - * @return: the corresponding keycode, or KEY_RESERVED * * This routine is used by drivers which need to convert a scancode to a * keycode. Normally it should not be used since drivers should have no * interest in keycodes. + * + * return: the corresponding keycode, or KEY_RESERVED */ u32 rc_g_keycode_from_table(struct rc_dev *dev, u32 scancode) { @@ -625,7 +633,8 @@ EXPORT_SYMBOL_GPL(rc_keyup); /** * ir_timer_keyup() - generates a keyup event after a timeout - * @cookie: a pointer to the struct rc_dev for the device + * + * @t: a pointer to the struct timer_list * * This routine will generate a keyup event some time after a keydown event * is generated when no further activity has been detected. @@ -780,7 +789,8 @@ EXPORT_SYMBOL_GPL(rc_keydown_notimeout); * provides sensible defaults * @dev: the struct rc_dev descriptor of the device * @filter: the scancode and mask - * @return: 0 or -EINVAL if the filter is not valid + * + * return: 0 or -EINVAL if the filter is not valid */ static int rc_validate_filter(struct rc_dev *dev, struct rc_scancode_filter *filter) -- GitLab From 929b99ed9b31c6de984c6cf49763eaed6767ac2e Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Nov 2017 08:38:30 -0500 Subject: [PATCH 0128/2547] media: siano: get rid of documentation warnings The Siano driver doesn't use kernel-doc markups. While it would be wanderful to convert to use it, it is probably not worth the time. So, instead of solving all problems there, just make sure that it won't produce dozens of warnings. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/siano/smscoreapi.c | 66 ++++++++++++------------- drivers/media/usb/siano/smsusb.c | 4 +- 2 files changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/media/common/siano/smscoreapi.c b/drivers/media/common/siano/smscoreapi.c index e4ea2a0c7a24..c5c827e11b64 100644 --- a/drivers/media/common/siano/smscoreapi.c +++ b/drivers/media/common/siano/smscoreapi.c @@ -521,13 +521,13 @@ static void list_add_locked(struct list_head *new, struct list_head *head, spin_unlock_irqrestore(lock, flags); } -/** +/* * register a client callback that called when device plugged in/unplugged * NOTE: if devices exist callback is called immediately for each device * * @param hotplug callback * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ int smscore_register_hotplug(hotplug_t hotplug) { @@ -562,7 +562,7 @@ int smscore_register_hotplug(hotplug_t hotplug) } EXPORT_SYMBOL_GPL(smscore_register_hotplug); -/** +/* * unregister a client callback that called when device plugged in/unplugged * * @param hotplug callback @@ -636,7 +636,7 @@ smscore_buffer_t *smscore_createbuffer(u8 *buffer, void *common_buffer, return cb; } -/** +/* * creates coredev object for a device, prepares buffers, * creates buffer mappings, notifies registered hotplugs about new device. * @@ -644,7 +644,7 @@ smscore_buffer_t *smscore_createbuffer(u8 *buffer, void *common_buffer, * and handlers * @param coredev pointer to a value that receives created coredev object * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ int smscore_register_device(struct smsdevice_params_t *params, struct smscore_device_t **coredev, @@ -764,10 +764,10 @@ static int smscore_sendrequest_and_wait(struct smscore_device_t *coredev, 0 : -ETIME; } -/** +/* * Starts & enables IR operations * - * @return 0 on success, < 0 on error. + * return: 0 on success, < 0 on error. */ static int smscore_init_ir(struct smscore_device_t *coredev) { @@ -812,13 +812,13 @@ static int smscore_init_ir(struct smscore_device_t *coredev) return 0; } -/** +/* * configures device features according to board configuration structure. * * @param coredev pointer to a coredev object returned by * smscore_register_device * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ static int smscore_configure_board(struct smscore_device_t *coredev) { @@ -861,13 +861,13 @@ static int smscore_configure_board(struct smscore_device_t *coredev) return 0; } -/** +/* * sets initial device mode and notifies client hotplugs that device is ready * * @param coredev pointer to a coredev object returned by * smscore_register_device * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ int smscore_start_device(struct smscore_device_t *coredev) { @@ -1087,7 +1087,7 @@ static char *smscore_fw_lkup[][DEVICE_MODE_MAX] = { }, }; -/** +/* * get firmware file name from one of the two mechanisms : sms_boards or * smscore_fw_lkup. * @param coredev pointer to a coredev object returned by @@ -1096,7 +1096,7 @@ static char *smscore_fw_lkup[][DEVICE_MODE_MAX] = { * @param lookup if 1, always get the fw filename from smscore_fw_lkup * table. if 0, try first to get from sms_boards * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ static char *smscore_get_fw_filename(struct smscore_device_t *coredev, int mode) @@ -1125,7 +1125,7 @@ static char *smscore_get_fw_filename(struct smscore_device_t *coredev, return fw[mode]; } -/** +/* * loads specified firmware into a buffer and calls device loadfirmware_handler * * @param coredev pointer to a coredev object returned by @@ -1133,7 +1133,7 @@ static char *smscore_get_fw_filename(struct smscore_device_t *coredev, * @param filename null-terminated string specifies firmware file name * @param loadfirmware_handler device handler that loads firmware * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ static int smscore_load_firmware_from_file(struct smscore_device_t *coredev, int mode, @@ -1182,14 +1182,14 @@ static int smscore_load_firmware_from_file(struct smscore_device_t *coredev, return rc; } -/** +/* * notifies all clients registered with the device, notifies hotplugs, * frees all buffers and coredev object * * @param coredev pointer to a coredev object returned by * smscore_register_device * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ void smscore_unregister_device(struct smscore_device_t *coredev) { @@ -1282,14 +1282,14 @@ static int smscore_detect_mode(struct smscore_device_t *coredev) return rc; } -/** +/* * send init device request and wait for response * * @param coredev pointer to a coredev object returned by * smscore_register_device * @param mode requested mode of operation * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ static int smscore_init_device(struct smscore_device_t *coredev, int mode) { @@ -1315,7 +1315,7 @@ static int smscore_init_device(struct smscore_device_t *coredev, int mode) return rc; } -/** +/* * calls device handler to change mode of operation * NOTE: stellar/usb may disconnect when changing mode * @@ -1323,7 +1323,7 @@ static int smscore_init_device(struct smscore_device_t *coredev, int mode) * smscore_register_device * @param mode requested mode of operation * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ int smscore_set_device_mode(struct smscore_device_t *coredev, int mode) { @@ -1411,13 +1411,13 @@ int smscore_set_device_mode(struct smscore_device_t *coredev, int mode) return rc; } -/** +/* * calls device handler to get current mode of operation * * @param coredev pointer to a coredev object returned by * smscore_register_device * - * @return current mode + * return: current mode */ int smscore_get_device_mode(struct smscore_device_t *coredev) { @@ -1425,7 +1425,7 @@ int smscore_get_device_mode(struct smscore_device_t *coredev) } EXPORT_SYMBOL_GPL(smscore_get_device_mode); -/** +/* * find client by response id & type within the clients list. * return client handle or NULL. * @@ -1462,7 +1462,7 @@ smscore_client_t *smscore_find_client(struct smscore_device_t *coredev, return client; } -/** +/* * find client by response id/type, call clients onresponse handler * return buffer to pool on error * @@ -1615,13 +1615,13 @@ void smscore_onresponse(struct smscore_device_t *coredev, } EXPORT_SYMBOL_GPL(smscore_onresponse); -/** +/* * return pointer to next free buffer descriptor from core pool * * @param coredev pointer to a coredev object returned by * smscore_register_device * - * @return pointer to descriptor on success, NULL on error. + * return: pointer to descriptor on success, NULL on error. */ static struct smscore_buffer_t *get_entry(struct smscore_device_t *coredev) @@ -1648,7 +1648,7 @@ struct smscore_buffer_t *smscore_getbuffer(struct smscore_device_t *coredev) } EXPORT_SYMBOL_GPL(smscore_getbuffer); -/** +/* * return buffer descriptor to a pool * * @param coredev pointer to a coredev object returned by @@ -1693,7 +1693,7 @@ static int smscore_validate_client(struct smscore_device_t *coredev, return 0; } -/** +/* * creates smsclient object, check that id is taken by another client * * @param coredev pointer to a coredev object from clients hotplug @@ -1705,7 +1705,7 @@ static int smscore_validate_client(struct smscore_device_t *coredev, * @param context client-specific context * @param client pointer to a value that receives created smsclient object * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ int smscore_register_client(struct smscore_device_t *coredev, struct smsclient_params_t *params, @@ -1740,7 +1740,7 @@ int smscore_register_client(struct smscore_device_t *coredev, } EXPORT_SYMBOL_GPL(smscore_register_client); -/** +/* * frees smsclient object and all subclients associated with it * * @param client pointer to smsclient object returned by @@ -1771,7 +1771,7 @@ void smscore_unregister_client(struct smscore_client_t *client) } EXPORT_SYMBOL_GPL(smscore_unregister_client); -/** +/* * verifies that source id is not taken by another client, * calls device handler to send requests to the device * @@ -1780,7 +1780,7 @@ EXPORT_SYMBOL_GPL(smscore_unregister_client); * @param buffer pointer to a request buffer * @param size size (in bytes) of request buffer * - * @return 0 on success, <0 on error. + * return: 0 on success, <0 on error. */ int smsclient_sendrequest(struct smscore_client_t *client, void *buffer, size_t size) diff --git a/drivers/media/usb/siano/smsusb.c b/drivers/media/usb/siano/smsusb.c index 8c1f926567ec..d07349cf9489 100644 --- a/drivers/media/usb/siano/smsusb.c +++ b/drivers/media/usb/siano/smsusb.c @@ -74,7 +74,7 @@ struct smsusb_device_t { static int smsusb_submit_urb(struct smsusb_device_t *dev, struct smsusb_urb_t *surb); -/** +/* * Completing URB's callback handler - bottom half (proccess context) * submits the URB prepared on smsusb_onresponse() */ @@ -86,7 +86,7 @@ static void do_submit_urb(struct work_struct *work) smsusb_submit_urb(dev, surb); } -/** +/* * Completing URB's callback handler - top half (interrupt context) * adds completing sms urb to the global surbs list and activtes the worker * thread the surb -- GitLab From 86850b9a0495b10326765f03b9e77fd46e83981c Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Nov 2017 10:09:03 -0500 Subject: [PATCH 0129/2547] media: img-ir-hw: fix one kernel-doc comment Needed to suppress the following warnings: drivers/media/rc/img-ir/img-ir-hw.c:351: warning: No description found for parameter 'reg_timings' drivers/media/rc/img-ir/img-ir-hw.c:351: warning: Excess function parameter 'timings' description in 'img_ir_decoder_convert' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/img-ir/img-ir-hw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/rc/img-ir/img-ir-hw.c b/drivers/media/rc/img-ir/img-ir-hw.c index f54bc5d23893..ec4ded84cd17 100644 --- a/drivers/media/rc/img-ir/img-ir-hw.c +++ b/drivers/media/rc/img-ir/img-ir-hw.c @@ -339,7 +339,7 @@ static void img_ir_decoder_preprocess(struct img_ir_decoder *decoder) /** * img_ir_decoder_convert() - Generate internal timings in decoder. * @decoder: Decoder to be converted to internal timings. - * @timings: Timing register values. + * @reg_timings: Timing register values. * @clock_hz: IR clock rate in Hz. * * Fills out the repeat timings and timing register values for a specific clock -- GitLab From 251c201bf4f8b5bf4f1ccb4f8920eed2e1f57580 Mon Sep 17 00:00:00 2001 From: Maxime Chevallier Date: Mon, 27 Nov 2017 15:16:32 +0100 Subject: [PATCH 0130/2547] spi: a3700: Fix clk prescaling for coefficient over 15 The Armada 3700 SPI controller has 2 ranges of prescaler coefficients. One ranging from 0 to 15 by steps of 1, and one ranging from 0 to 30 by steps of 2. This commit fixes the prescaler coefficients that are over 15 so that it uses the correct range of values. The prescaling coefficient is rounded to the upper value if it is odd. This was tested on Espressobin with spidev and a locigal analyser. Signed-off-by: Maxime Chevallier Signed-off-by: Mark Brown Cc: stable@vger.kernel.org --- drivers/spi/spi-armada-3700.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/spi/spi-armada-3700.c b/drivers/spi/spi-armada-3700.c index 77fe55ce790c..d65345312527 100644 --- a/drivers/spi/spi-armada-3700.c +++ b/drivers/spi/spi-armada-3700.c @@ -79,6 +79,7 @@ #define A3700_SPI_BYTE_LEN BIT(5) #define A3700_SPI_CLK_PRESCALE BIT(0) #define A3700_SPI_CLK_PRESCALE_MASK (0x1f) +#define A3700_SPI_CLK_EVEN_OFFS (0x10) #define A3700_SPI_WFIFO_THRS_BIT 28 #define A3700_SPI_RFIFO_THRS_BIT 24 @@ -220,6 +221,13 @@ static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); + /* For prescaler values over 15, we can only set it by steps of 2. + * Starting from A3700_SPI_CLK_EVEN_OFFS, we set values from 0 up to + * 30. We only use this range from 16 to 30. + */ + if (prescale > 15) + prescale = A3700_SPI_CLK_EVEN_OFFS + DIV_ROUND_UP(prescale, 2); + val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val = val & ~A3700_SPI_CLK_PRESCALE_MASK; -- GitLab From 34eb9751ea8285c7732991a09cb8729d624f6245 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Nov 2017 10:10:28 -0500 Subject: [PATCH 0131/2547] media: drxj and drxk: don't produce kernel-doc warnings Those drivers use a different notation for comments. While it is not worth converting to kernel-doc, removing it is also not an option. So, just replace /** by /* and be happy :-) Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 248 ++++++++++---------- drivers/media/dvb-frontends/drxk_hard.c | 32 +-- 2 files changed, 140 insertions(+), 140 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 499ccff557bf..8cbd8cc21059 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -73,7 +73,7 @@ INCLUDE FILES #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw" -/** +/* * \brief Maximum u32 value. */ #ifndef MAX_U32 @@ -100,8 +100,8 @@ INCLUDE FILES #ifndef OOB_DRX_DRIVE_STRENGTH #define OOB_DRX_DRIVE_STRENGTH 0x02 #endif -/**** START DJCOMBO patches to DRXJ registermap constants *********************/ -/**** registermap 200706071303 from drxj **************************************/ +/*** START DJCOMBO patches to DRXJ registermap constants *********************/ +/*** registermap 200706071303 from drxj **************************************/ #define ATV_TOP_CR_AMP_TH_FM 0x0 #define ATV_TOP_CR_AMP_TH_L 0xA #define ATV_TOP_CR_AMP_TH_LP 0xA @@ -188,7 +188,7 @@ INCLUDE FILES #define IQM_RC_ADJ_SEL_B_OFF 0x0 #define IQM_RC_ADJ_SEL_B_QAM 0x1 #define IQM_RC_ADJ_SEL_B_VSB 0x2 -/**** END DJCOMBO patches to DRXJ registermap *********************************/ +/*** END DJCOMBO patches to DRXJ registermap *********************************/ #include "drx_driver_version.h" @@ -208,25 +208,25 @@ DEFINES #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr) #endif -/** +/* * \def DRXJ_DEF_I2C_ADDR * \brief Default I2C address of a demodulator instance. */ #define DRXJ_DEF_I2C_ADDR (0x52) -/** +/* * \def DRXJ_DEF_DEMOD_DEV_ID * \brief Default device identifier of a demodultor instance. */ #define DRXJ_DEF_DEMOD_DEV_ID (1) -/** +/* * \def DRXJ_SCAN_TIMEOUT * \brief Timeout value for waiting on demod lock during channel scan (millisec). */ #define DRXJ_SCAN_TIMEOUT 1000 -/** +/* * \def HI_I2C_DELAY * \brief HI timing delay for I2C timing (in nano seconds) * @@ -234,7 +234,7 @@ DEFINES */ #define HI_I2C_DELAY 42 -/** +/* * \def HI_I2C_BRIDGE_DELAY * \brief HI timing delay for I2C timing (in nano seconds) * @@ -242,13 +242,13 @@ DEFINES */ #define HI_I2C_BRIDGE_DELAY 750 -/** +/* * \brief Time Window for MER and SER Measurement in Units of Segment duration. */ #define VSB_TOP_MEASUREMENT_PERIOD 64 #define SYMBOLS_PER_SEGMENT 832 -/** +/* * \brief bit rate and segment rate constants used for SER and BER. */ /* values taken from the QAM microcode */ @@ -260,21 +260,21 @@ DEFINES #define DRXJ_QAM_SL_SIG_POWER_QAM64 43008 #define DRXJ_QAM_SL_SIG_POWER_QAM128 20992 #define DRXJ_QAM_SL_SIG_POWER_QAM256 43520 -/** +/* * \brief Min supported symbolrates. */ #ifndef DRXJ_QAM_SYMBOLRATE_MIN #define DRXJ_QAM_SYMBOLRATE_MIN (520000) #endif -/** +/* * \brief Max supported symbolrates. */ #ifndef DRXJ_QAM_SYMBOLRATE_MAX #define DRXJ_QAM_SYMBOLRATE_MAX (7233000) #endif -/** +/* * \def DRXJ_QAM_MAX_WAITTIME * \brief Maximal wait time for QAM auto constellation in ms */ @@ -290,7 +290,7 @@ DEFINES #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200 #endif -/** +/* * \def SCU status and results * \brief SCU */ @@ -299,7 +299,7 @@ DEFINES #define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */ #define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */ -/** +/* * \def DRX_AUD_MAX_DEVIATION * \brief Needed for calculation of prescale feature in AUD */ @@ -307,14 +307,14 @@ DEFINES #define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */ #endif -/** +/* * \brief Needed for calculation of NICAM prescale feature in AUD */ #ifndef DRXJ_AUD_MAX_NICAM_PRESCALE #define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */ #endif -/** +/* * \brief Needed for calculation of NICAM prescale feature in AUD */ #ifndef DRXJ_AUD_MAX_WAITTIME @@ -371,21 +371,21 @@ DEFINES /*============================================================================*/ /*=== GLOBAL VARIABLEs =======================================================*/ /*============================================================================*/ -/** +/* */ -/** +/* * \brief Temporary register definitions. * (register definitions that are not yet available in register master) */ -/******************************************************************************/ +/*****************************************************************************/ /* Audio block 0x103 is write only. To avoid shadowing in driver accessing */ /* RAM adresses directly. This must be READ ONLY to avoid problems. */ /* Writing to the interface adresses is more than only writing the RAM */ /* locations */ -/******************************************************************************/ -/** +/*****************************************************************************/ +/* * \brief RAM location of MODUS registers */ #define AUD_DEM_RAM_MODUS_HI__A 0x10204A3 @@ -394,13 +394,13 @@ DEFINES #define AUD_DEM_RAM_MODUS_LO__A 0x10204A4 #define AUD_DEM_RAM_MODUS_LO__M 0x0FFF -/** +/* * \brief RAM location of I2S config registers */ #define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1 #define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2 -/** +/* * \brief RAM location of DCO config registers */ #define AUD_DEM_RAM_DCO_B_HI__A 0x1020461 @@ -408,20 +408,20 @@ DEFINES #define AUD_DEM_RAM_DCO_A_HI__A 0x1020463 #define AUD_DEM_RAM_DCO_A_LO__A 0x1020464 -/** +/* * \brief RAM location of Threshold registers */ #define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A #define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB #define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6 -/** +/* * \brief RAM location of Carrier Threshold registers */ #define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF #define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0 -/** +/* * \brief FM Matrix register fix */ #ifdef AUD_DEM_WR_FM_MATRIX__A @@ -430,7 +430,7 @@ DEFINES #define AUD_DEM_WR_FM_MATRIX__A 0x105006F /*============================================================================*/ -/** +/* * \brief Defines required for audio */ #define AUD_VOLUME_ZERO_DB 115 @@ -443,14 +443,14 @@ DEFINES #define AUD_I2S_FREQUENCY_MIN 12000UL #define AUD_RDS_ARRAY_SIZE 18 -/** +/* * \brief Needed for calculation of prescale feature in AUD */ #ifndef DRX_AUD_MAX_FM_DEVIATION #define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */ #endif -/** +/* * \brief Needed for calculation of NICAM prescale feature in AUD */ #ifndef DRX_AUD_MAX_NICAM_PRESCALE @@ -478,7 +478,7 @@ DEFINES /*=== REGISTER ACCESS MACROS =================================================*/ /*============================================================================*/ -/** +/* * This macro is used to create byte arrays for block writes. * Block writes speed up I2C traffic between host and demod. * The macro takes care of the required byte order in a 16 bits word. @@ -486,7 +486,7 @@ DEFINES */ #define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ ((u8)((((u16)x)>>8)&0xFF)) -/** +/* * This macro is used to convert byte array to 16 bit register value for block read. * Block read speed up I2C traffic between host and demod. * The macro takes care of the required byte order in a 16 bits word. @@ -501,7 +501,7 @@ DEFINES /*=== HI COMMAND RELATED DEFINES =============================================*/ /*============================================================================*/ -/** +/* * \brief General maximum number of retries for ucode command interfaces */ #define DRXJ_MAX_RETRIES (100) @@ -807,7 +807,7 @@ static struct drxj_data drxj_data_g = { }, }; -/** +/* * \var drxj_default_addr_g * \brief Default I2C address and device identifier. */ @@ -816,7 +816,7 @@ static struct i2c_device_addr drxj_default_addr_g = { DRXJ_DEF_DEMOD_DEV_ID /* device id */ }; -/** +/* * \var drxj_default_comm_attr_g * \brief Default common attributes of a drxj demodulator instance. */ @@ -887,7 +887,7 @@ static struct drx_common_attr drxj_default_comm_attr_g = { 0 /* mfx */ }; -/** +/* * \var drxj_default_demod_g * \brief Default drxj demodulator instance. */ @@ -897,7 +897,7 @@ static struct drx_demod_instance drxj_default_demod_g = { &drxj_data_g /* demod device specific attributes */ }; -/** +/* * \brief Default audio data structure for DRK demodulator instance. * * This structure is DRXK specific. @@ -997,7 +997,7 @@ struct drxj_hi_cmd { /*=== MICROCODE RELATED STRUCTURES ===========================================*/ /*============================================================================*/ -/** +/* * struct drxu_code_block_hdr - Structure of the microcode block headers * * @addr: Destination address of the data in this block @@ -1086,7 +1086,7 @@ static u32 frac28(u32 N, u32 D) return Q1; } -/** +/* * \fn u32 log1_times100( u32 x) * \brief Compute: 100*log10(x) * \param x 32 bits @@ -1198,7 +1198,7 @@ static u32 log1_times100(u32 x) } -/** +/* * \fn u32 frac_times1e6( u16 N, u32 D) * \brief Compute: (N/D) * 1000000. * \param N nominator 16-bits. @@ -1235,7 +1235,7 @@ static u32 frac_times1e6(u32 N, u32 D) /*============================================================================*/ -/** +/* * \brief Values for NICAM prescaler gain. Computed from dB to integer * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20). * @@ -1280,7 +1280,7 @@ static const u16 nicam_presc_table_val[43] = { #define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */ /*============================================================================*/ -/** +/* * \fn bool is_handled_by_aud_tr_if( u32 addr ) * \brief Check if this address is handled by the audio token ring interface. * \param addr @@ -1386,7 +1386,7 @@ int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, /*============================================================================*/ -/****************************** +/***************************** * * int drxdap_fasi_read_block ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1498,7 +1498,7 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, } -/****************************** +/***************************** * * int drxdap_fasi_read_reg16 ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1531,7 +1531,7 @@ static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, return rc; } -/****************************** +/***************************** * * int drxdap_fasi_read_reg32 ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1566,7 +1566,7 @@ static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, return rc; } -/****************************** +/***************************** * * int drxdap_fasi_write_block ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1705,7 +1705,7 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, return first_err; } -/****************************** +/***************************** * * int drxdap_fasi_write_reg16 ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1734,7 +1734,7 @@ static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); } -/****************************** +/***************************** * * int drxdap_fasi_read_modify_write_reg16 ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1778,7 +1778,7 @@ static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, return rc; } -/****************************** +/***************************** * * int drxdap_fasi_write_reg32 ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1811,7 +1811,7 @@ static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, /*============================================================================*/ -/** +/* * \fn int drxj_dap_rm_write_reg16short * \brief Read modify write 16 bits audio register using short format only. * \param dev_addr @@ -1890,7 +1890,7 @@ static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, /*============================================================================*/ -/** +/* * \fn int drxj_dap_read_aud_reg16 * \brief Read 16 bits audio register * \param dev_addr @@ -1997,7 +1997,7 @@ static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, } /*============================================================================*/ -/** +/* * \fn int drxj_dap_write_aud_reg16 * \brief Write 16 bits audio register * \param dev_addr @@ -2086,7 +2086,7 @@ static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, #define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ #define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE -/** +/* * \fn int drxj_dap_atomic_read_write_block() * \brief Basic access routine for atomic read or write access * \param dev_addr pointer to i2c dev address @@ -2168,7 +2168,7 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, /*============================================================================*/ -/** +/* * \fn int drxj_dap_atomic_read_reg32() * \brief Atomic read of 32 bits words */ @@ -2215,7 +2215,7 @@ int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, /*============================================================================*/ /*============================================================================*/ -/** +/* * \fn int hi_cfg_command() * \brief Configure HI with settings stored in the demod structure. * \param demod Demodulator. @@ -2258,7 +2258,7 @@ static int hi_cfg_command(const struct drx_demod_instance *demod) return rc; } -/** +/* * \fn int hi_command() * \brief Configure HI with settings stored in the demod structure. * \param dev_addr I2C address. @@ -2369,7 +2369,7 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 return rc; } -/** +/* * \fn int init_hi( const struct drx_demod_instance *demod ) * \brief Initialise and configurate HI. * \param demod pointer to demod data. @@ -2450,7 +2450,7 @@ static int init_hi(const struct drx_demod_instance *demod) /*============================================================================*/ /*============================================================================*/ -/** +/* * \fn int get_device_capabilities() * \brief Get and store device capabilities. * \param demod Pointer to demodulator instance. @@ -2656,7 +2656,7 @@ static int get_device_capabilities(struct drx_demod_instance *demod) return rc; } -/** +/* * \fn int power_up_device() * \brief Power up device. * \param demod Pointer to demodulator instance. @@ -2710,7 +2710,7 @@ static int power_up_device(struct drx_demod_instance *demod) /*----------------------------------------------------------------------------*/ /* MPEG Output Configuration Functions - begin */ /*----------------------------------------------------------------------------*/ -/** +/* * \fn int ctrl_set_cfg_mpeg_output() * \brief Set MPEG output configuration of the device. * \param devmod Pointer to demodulator instance. @@ -3356,7 +3356,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o /* miscellaneous configurations - begin */ /*----------------------------------------------------------------------------*/ -/** +/* * \fn int set_mpegtei_handling() * \brief Activate MPEG TEI handling settings. * \param devmod Pointer to demodulator instance. @@ -3429,7 +3429,7 @@ static int set_mpegtei_handling(struct drx_demod_instance *demod) } /*----------------------------------------------------------------------------*/ -/** +/* * \fn int bit_reverse_mpeg_output() * \brief Set MPEG output bit-endian settings. * \param devmod Pointer to demodulator instance. @@ -3472,7 +3472,7 @@ static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) } /*----------------------------------------------------------------------------*/ -/** +/* * \fn int set_mpeg_start_width() * \brief Set MPEG start width. * \param devmod Pointer to demodulator instance. @@ -3522,7 +3522,7 @@ static int set_mpeg_start_width(struct drx_demod_instance *demod) /*----------------------------------------------------------------------------*/ /* UIO Configuration Functions - begin */ /*----------------------------------------------------------------------------*/ -/** +/* * \fn int ctrl_set_uio_cfg() * \brief Configure modus oprandi UIO. * \param demod Pointer to demodulator instance. @@ -3659,7 +3659,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg return rc; } -/** +/* * \fn int ctrl_uio_write() * \brief Write to a UIO. * \param demod Pointer to demodulator instance. @@ -3868,7 +3868,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /*----------------------------------------------------------------------------*/ /* I2C Bridge Functions - begin */ /*----------------------------------------------------------------------------*/ -/** +/* * \fn int ctrl_i2c_bridge() * \brief Open or close the I2C switch to tuner. * \param demod Pointer to demodulator instance. @@ -3903,7 +3903,7 @@ ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) /*----------------------------------------------------------------------------*/ /* Smart antenna Functions - begin */ /*----------------------------------------------------------------------------*/ -/** +/* * \fn int smart_ant_init() * \brief Initialize Smart Antenna. * \param pointer to struct drx_demod_instance. @@ -4116,7 +4116,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd return rc; } -/** +/* * \fn int DRXJ_DAP_SCUAtomicReadWriteBlock() * \brief Basic access routine for SCU atomic read or write access * \param dev_addr pointer to i2c dev address @@ -4188,7 +4188,7 @@ int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 a /*============================================================================*/ -/** +/* * \fn int DRXJ_DAP_AtomicReadReg16() * \brief Atomic read of 16 bits words */ @@ -4216,7 +4216,7 @@ int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr, } /*============================================================================*/ -/** +/* * \fn int drxj_dap_scu_atomic_write_reg16() * \brief Atomic read of 16 bits words */ @@ -4237,7 +4237,7 @@ int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr, } /* -------------------------------------------------------------------------- */ -/** +/* * \brief Measure result of ADC synchronisation * \param demod demod instance * \param count (returned) count @@ -4297,7 +4297,7 @@ static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) return rc; } -/** +/* * \brief Synchronize analog and digital clock domains * \param demod demod instance * \return int. @@ -4365,7 +4365,7 @@ static int adc_synchronization(struct drx_demod_instance *demod) /*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/ /*============================================================================*/ /*============================================================================*/ -/** +/* * \fn int init_agc () * \brief Initialize AGC for all standards. * \param demod instance of demodulator. @@ -4741,7 +4741,7 @@ static int init_agc(struct drx_demod_instance *demod) return rc; } -/** +/* * \fn int set_frequency () * \brief Set frequency shift. * \param demod instance of demodulator. @@ -4839,7 +4839,7 @@ set_frequency(struct drx_demod_instance *demod, return rc; } -/** +/* * \fn int get_acc_pkt_err() * \brief Retrieve signal strength for VSB and QAM. * \param demod Pointer to demod instance @@ -4891,7 +4891,7 @@ static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) /*============================================================================*/ -/** +/* * \fn int set_agc_rf () * \brief Configure RF AGC * \param demod instance of demodulator. @@ -5105,7 +5105,7 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, return rc; } -/** +/* * \fn int set_agc_if () * \brief Configure If AGC * \param demod instance of demodulator. @@ -5334,7 +5334,7 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, return rc; } -/** +/* * \fn int set_iqm_af () * \brief Configure IQM AF registers * \param demod instance of demodulator. @@ -5380,7 +5380,7 @@ static int set_iqm_af(struct drx_demod_instance *demod, bool active) /*============================================================================*/ /*============================================================================*/ -/** +/* * \fn int power_down_vsb () * \brief Powr down QAM related blocks. * \param demod instance of demodulator. @@ -5478,7 +5478,7 @@ static int power_down_vsb(struct drx_demod_instance *demod, bool primary) return rc; } -/** +/* * \fn int set_vsb_leak_n_gain () * \brief Set ATSC demod. * \param demod instance of demodulator. @@ -5694,7 +5694,7 @@ static int set_vsb_leak_n_gain(struct drx_demod_instance *demod) return rc; } -/** +/* * \fn int set_vsb() * \brief Set 8VSB demod. * \param demod instance of demodulator. @@ -6200,7 +6200,7 @@ static int set_vsb(struct drx_demod_instance *demod) return rc; } -/** +/* * \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs) * \brief Get the values of packet error in 8VSB mode * \return Error code @@ -6239,7 +6239,7 @@ static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, return rc; } -/** +/* * \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code @@ -6284,7 +6284,7 @@ static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, return rc; } -/** +/* * \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code @@ -6306,7 +6306,7 @@ static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, return 0; } -/** +/* * \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) * \brief Get the values of MER * \return Error code @@ -6340,7 +6340,7 @@ static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) /*============================================================================*/ /*============================================================================*/ -/** +/* * \fn int power_down_qam () * \brief Powr down QAM related blocks. * \param demod instance of demodulator. @@ -6444,7 +6444,7 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) /*============================================================================*/ -/** +/* * \fn int set_qam_measurement () * \brief Setup of the QAM Measuremnt intervals for signal quality * \param demod instance of demod. @@ -6656,7 +6656,7 @@ set_qam_measurement(struct drx_demod_instance *demod, /*============================================================================*/ -/** +/* * \fn int set_qam16 () * \brief QAM16 specific setup * \param demod instance of demod. @@ -6891,7 +6891,7 @@ static int set_qam16(struct drx_demod_instance *demod) /*============================================================================*/ -/** +/* * \fn int set_qam32 () * \brief QAM32 specific setup * \param demod instance of demod. @@ -7126,7 +7126,7 @@ static int set_qam32(struct drx_demod_instance *demod) /*============================================================================*/ -/** +/* * \fn int set_qam64 () * \brief QAM64 specific setup * \param demod instance of demod. @@ -7362,7 +7362,7 @@ static int set_qam64(struct drx_demod_instance *demod) /*============================================================================*/ -/** +/* * \fn int set_qam128 () * \brief QAM128 specific setup * \param demod: instance of demod. @@ -7597,7 +7597,7 @@ static int set_qam128(struct drx_demod_instance *demod) /*============================================================================*/ -/** +/* * \fn int set_qam256 () * \brief QAM256 specific setup * \param demod: instance of demod. @@ -7835,7 +7835,7 @@ static int set_qam256(struct drx_demod_instance *demod) #define QAM_SET_OP_CONSTELLATION 0x2 #define QAM_SET_OP_SPECTRUM 0X4 -/** +/* * \fn int set_qam () * \brief Set QAM demod. * \param demod: instance of demod. @@ -8845,7 +8845,7 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c #define DEMOD_LOCKED 0x1 #define SYNC_FLIPPED 0x2 #define SPEC_MIRRORED 0x4 -/** +/* * \fn int qam64auto () * \brief auto do sync pattern switching and mirroring. * \param demod: instance of demod. @@ -8993,7 +8993,7 @@ qam64auto(struct drx_demod_instance *demod, return rc; } -/** +/* * \fn int qam256auto () * \brief auto do sync pattern switching and mirroring. * \param demod: instance of demod. @@ -9077,7 +9077,7 @@ qam256auto(struct drx_demod_instance *demod, return rc; } -/** +/* * \fn int set_qam_channel () * \brief Set QAM channel according to the requested constellation. * \param demod: instance of demod. @@ -9284,7 +9284,7 @@ set_qam_channel(struct drx_demod_instance *demod, /*============================================================================*/ -/** +/* * \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr) * \brief Get RS error count in QAM mode (used for post RS BER calculation) * \return Error code @@ -9355,7 +9355,7 @@ get_qamrs_err_count(struct i2c_device_addr *dev_addr, /*============================================================================*/ -/** +/* * \fn int get_sig_strength() * \brief Retrieve signal strength for VSB and QAM. * \param demod Pointer to demod instance @@ -9435,7 +9435,7 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) return rc; } -/** +/* * \fn int ctrl_get_qam_sig_quality() * \brief Retrieve QAM signal quality from device. * \param devmod Pointer to demodulator instance. @@ -9721,7 +9721,7 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod) */ /* -------------------------------------------------------------------------- */ -/** +/* * \fn int power_down_atv () * \brief Power down ATV. * \param demod instance of demodulator @@ -9822,7 +9822,7 @@ power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, boo /*============================================================================*/ -/** +/* * \brief Power up AUD. * \param demod instance of demodulator * \return int. @@ -9850,7 +9850,7 @@ static int power_down_aud(struct drx_demod_instance *demod) return rc; } -/** +/* * \fn int set_orx_nsu_aox() * \brief Configure OrxNsuAox for OOB * \param demod instance of demodulator. @@ -9884,7 +9884,7 @@ static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) return rc; } -/** +/* * \fn int ctrl_set_oob() * \brief Set OOB channel to be used. * \param demod instance of demodulator @@ -9986,9 +9986,9 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par 20; } - /*********/ + /********/ /* Stop */ - /*********/ + /********/ rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); @@ -10004,9 +10004,9 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par pr_err("error %d\n", rc); goto rw_error; } - /*********/ + /********/ /* Reset */ - /*********/ + /********/ scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_RESET; scu_cmd.parameter_len = 0; @@ -10017,9 +10017,9 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par pr_err("error %d\n", rc); goto rw_error; } - /***********/ + /**********/ /* SET_ENV */ - /***********/ + /**********/ /* set frequency, spectrum inversion and data rate */ scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; @@ -10376,9 +10376,9 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par pr_err("error %d\n", rc); goto rw_error; } - /*********/ + /********/ /* Start */ - /*********/ + /********/ scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_START; scu_cmd.parameter_len = 0; @@ -10419,7 +10419,7 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /*============================================================================= ===== ctrl_set_channel() ========================================================== ===========================================================================*/ -/** +/* * \fn int ctrl_set_channel() * \brief Select a new transmission channel. * \param demod instance of demod. @@ -10652,7 +10652,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) ===== SigQuality() ========================================================== ===========================================================================*/ -/** +/* * \fn int ctrl_sig_quality() * \brief Retrieve signal quality form device. * \param devmod Pointer to demodulator instance. @@ -10768,7 +10768,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, /*============================================================================*/ -/** +/* * \fn int ctrl_lock_status() * \brief Retrieve lock status . * \param dev_addr Pointer to demodulator device address. @@ -10856,7 +10856,7 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st /*============================================================================*/ -/** +/* * \fn int ctrl_set_standard() * \brief Set modulation standard to be used. * \param standard Modulation standard. @@ -11012,7 +11012,7 @@ static void drxj_reset_mode(struct drxj_data *ext_attr) ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; } -/** +/* * \fn int ctrl_power_mode() * \brief Set the power mode of the device to the specified power mode * \param demod Pointer to demodulator instance. @@ -11171,7 +11171,7 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) /*== CTRL Set/Get Config related functions ===================================*/ /*============================================================================*/ -/** +/* * \fn int ctrl_set_cfg_pre_saw() * \brief Set Pre-saw reference. * \param demod demod instance @@ -11234,7 +11234,7 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * /*============================================================================*/ -/** +/* * \fn int ctrl_set_cfg_afe_gain() * \brief Set AFE Gain. * \param demod demod instance @@ -11324,7 +11324,7 @@ static int drx_ctrl_u_code(struct drx_demod_instance *demod, enum drxu_code_action action); static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state); -/** +/* * \fn drxj_open() * \brief Open the demod instance, configure device, configure drxdriver * \return Status_t Return status. @@ -11543,7 +11543,7 @@ static int drxj_open(struct drx_demod_instance *demod) } /*============================================================================*/ -/** +/* * \fn drxj_close() * \brief Close the demod instance, power down the device * \return Status_t Return status. @@ -11594,7 +11594,7 @@ static int drxj_close(struct drx_demod_instance *demod) * Microcode related functions */ -/** +/* * drx_u_code_compute_crc - Compute CRC of block of microcode data. * @block_data: Pointer to microcode data. * @nr_words: Size of microcode block (number of 16 bits words). @@ -11622,7 +11622,7 @@ static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words) return (u16)(crc_word >> 16); } -/** +/* * drx_check_firmware - checks if the loaded firmware is valid * * @demod: demod structure @@ -11708,7 +11708,7 @@ static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data, return -EINVAL; } -/** +/* * drx_ctrl_u_code - Handle microcode upload or verify. * @dev_addr: Address of device. * @mc_info: Pointer to information about microcode data. diff --git a/drivers/media/dvb-frontends/drxk_hard.c b/drivers/media/dvb-frontends/drxk_hard.c index 48a8aad47a74..f59ac2e91c59 100644 --- a/drivers/media/dvb-frontends/drxk_hard.c +++ b/drivers/media/dvb-frontends/drxk_hard.c @@ -207,9 +207,9 @@ static inline u32 log10times100(u32 value) return (100L * intlog10(value)) >> 24; } -/****************************************************************************/ +/***************************************************************************/ /* I2C **********************************************************************/ -/****************************************************************************/ +/***************************************************************************/ static int drxk_i2c_lock(struct drxk_state *state) { @@ -3444,7 +3444,7 @@ static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state, /*============================================================================*/ -/** +/* * \brief Activate DVBT specific presets * \param demod instance of demodulator. * \return DRXStatus_t. @@ -3484,7 +3484,7 @@ static int dvbt_activate_presets(struct drxk_state *state) /*============================================================================*/ -/** +/* * \brief Initialize channelswitch-independent settings for DVBT. * \param demod instance of demodulator. * \return DRXStatus_t. @@ -3696,7 +3696,7 @@ static int set_dvbt_standard(struct drxk_state *state, } /*============================================================================*/ -/** +/* * \brief start dvbt demodulating for channel. * \param demod instance of demodulator. * \return DRXStatus_t. @@ -3732,7 +3732,7 @@ static int dvbt_start(struct drxk_state *state) /*============================================================================*/ -/** +/* * \brief Set up dvbt demodulator for channel. * \param demod instance of demodulator. * \return DRXStatus_t. @@ -4086,7 +4086,7 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, /*============================================================================*/ -/** +/* * \brief Retrieve lock status . * \param demod Pointer to demodulator instance. * \param lockStat Pointer to lock status structure. @@ -4148,7 +4148,7 @@ static int power_up_qam(struct drxk_state *state) } -/** Power Down QAM */ +/* Power Down QAM */ static int power_down_qam(struct drxk_state *state) { u16 data = 0; @@ -4186,7 +4186,7 @@ static int power_down_qam(struct drxk_state *state) /*============================================================================*/ -/** +/* * \brief Setup of the QAM Measurement intervals for signal quality * \param demod instance of demod. * \param modulation current modulation. @@ -4461,7 +4461,7 @@ static int set_qam16(struct drxk_state *state) /*============================================================================*/ -/** +/* * \brief QAM32 specific setup * \param demod instance of demod. * \return DRXStatus_t. @@ -4657,7 +4657,7 @@ static int set_qam32(struct drxk_state *state) /*============================================================================*/ -/** +/* * \brief QAM64 specific setup * \param demod instance of demod. * \return DRXStatus_t. @@ -4852,7 +4852,7 @@ static int set_qam64(struct drxk_state *state) /*============================================================================*/ -/** +/* * \brief QAM128 specific setup * \param demod: instance of demod. * \return DRXStatus_t. @@ -5049,7 +5049,7 @@ static int set_qam128(struct drxk_state *state) /*============================================================================*/ -/** +/* * \brief QAM256 specific setup * \param demod: instance of demod. * \return DRXStatus_t. @@ -5244,7 +5244,7 @@ static int set_qam256(struct drxk_state *state) /*============================================================================*/ -/** +/* * \brief Reset QAM block. * \param demod: instance of demod. * \param channel: pointer to channel data. @@ -5272,7 +5272,7 @@ static int qam_reset_qam(struct drxk_state *state) /*============================================================================*/ -/** +/* * \brief Set QAM symbolrate. * \param demod: instance of demod. * \param channel: pointer to channel data. @@ -5341,7 +5341,7 @@ static int qam_set_symbolrate(struct drxk_state *state) /*============================================================================*/ -/** +/* * \brief Get QAM lock status. * \param demod: instance of demod. * \param channel: pointer to channel data. -- GitLab From 159308106aa0aa0873ee6e000b05db08a9413f58 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Nov 2017 10:14:25 -0500 Subject: [PATCH 0132/2547] media: vpif: don't generate a kernel-doc warning on a constant Constants documentation is not supported by kernel-doc markups. So, change the comment label to avoid this warning: drivers/media/platform/davinci/vpif.c:54: warning: cannot understand function prototype: 'const struct vpif_channel_config_params vpif_ch_params[] = ' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/davinci/vpif.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/davinci/vpif.c b/drivers/media/platform/davinci/vpif.c index 07e89a4985a6..16352e2263d2 100644 --- a/drivers/media/platform/davinci/vpif.c +++ b/drivers/media/platform/davinci/vpif.c @@ -47,8 +47,9 @@ EXPORT_SYMBOL_GPL(vpif_lock); void __iomem *vpif_base; EXPORT_SYMBOL_GPL(vpif_base); -/** +/* * vpif_ch_params: video standard configuration parameters for vpif + * * The table must include all presets from supported subdevices. */ const struct vpif_channel_config_params vpif_ch_params[] = { -- GitLab From 771a0997ef305cd4a763877a9fd2caa6d4a4276f Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Nov 2017 10:18:02 -0500 Subject: [PATCH 0133/2547] media: dvb_frontend fix kernel_doc markups There were some troubles there: drivers/media/dvb-core/dvb_frontend.c:379: warning: No description found for parameter 'fe' drivers/media/dvb-core/dvb_frontend.c:379: warning: No description found for parameter 'check_wrapped' drivers/media/dvb-core/dvb_frontend.c:1265: warning: No description found for parameter 'p_out' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-core/dvb_frontend.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/media/dvb-core/dvb_frontend.c b/drivers/media/dvb-core/dvb_frontend.c index 3ad83359098b..2afaa8226342 100644 --- a/drivers/media/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb-core/dvb_frontend.c @@ -369,11 +369,14 @@ static void dvb_frontend_swzigzag_update_delay(struct dvb_frontend_private *fepr } /** - * Performs automatic twiddling of frontend parameters. + * dvb_frontend_swzigzag_autotune - Performs automatic twiddling of frontend + * parameters. * - * @param fe The frontend concerned. - * @param check_wrapped Checks if an iteration has completed. DO NOT SET ON THE FIRST ATTEMPT - * @returns Number of complete iterations that have been performed. + * @fe: The frontend concerned. + * @check_wrapped: Checks if an iteration has completed. + * DO NOT SET ON THE FIRST ATTEMPT. + * + * return: Number of complete iterations that have been performed. */ static int dvb_frontend_swzigzag_autotune(struct dvb_frontend *fe, int check_wrapped) { @@ -1253,7 +1256,7 @@ dtv_property_legacy_params_sync(struct dvb_frontend *fe, * dtv_get_frontend - calls a callback for retrieving DTV parameters * @fe: struct dvb_frontend pointer * @c: struct dtv_frontend_properties pointer (DVBv5 cache) - * @p_out struct dvb_frontend_parameters pointer (DVBv3 FE struct) + * @p_out: struct dvb_frontend_parameters pointer (DVBv3 FE struct) * * This routine calls either the DVBv3 or DVBv5 get_frontend call. * If c is not null, it will update the DVBv5 cache struct pointed by it. -- GitLab From c4365922d5cd9720cb114f75089bc290571993a3 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Nov 2017 10:19:38 -0500 Subject: [PATCH 0134/2547] media: rc-ir-raw: cleanup kernel-doc markups Cleanup those warnings: drivers/media/rc/rc-ir-raw.c:141: warning: No description found for parameter 'ev' drivers/media/rc/rc-ir-raw.c:141: warning: Excess function parameter 'type' description in 'ir_raw_event_store_with_filter' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/rc-ir-raw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/rc/rc-ir-raw.c b/drivers/media/rc/rc-ir-raw.c index f6e5ba4fbb49..d78483a504c9 100644 --- a/drivers/media/rc/rc-ir-raw.c +++ b/drivers/media/rc/rc-ir-raw.c @@ -128,7 +128,7 @@ EXPORT_SYMBOL_GPL(ir_raw_event_store_edge); /** * ir_raw_event_store_with_filter() - pass next pulse/space to decoders with some processing * @dev: the struct rc_dev device descriptor - * @type: the type of the event that has occurred + * @ev: the event that has occurred * * This routine (which may be called from an interrupt context) works * in similar manner to ir_raw_event_store_edge. -- GitLab From 461afb273947098b5760fe27ba90f0cfa71578b5 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Nov 2017 10:21:28 -0500 Subject: [PATCH 0135/2547] media: dvb_net: stop abusing /** for comments The comments that start with "/**" aren't kernel-doc stuff. So, just start them with "/*". Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-core/dvb_net.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/media/dvb-core/dvb_net.c b/drivers/media/dvb-core/dvb_net.c index 06b0dcc13695..c018e3c06d5d 100644 --- a/drivers/media/dvb-core/dvb_net.c +++ b/drivers/media/dvb-core/dvb_net.c @@ -125,7 +125,7 @@ struct dvb_net_priv { }; -/** +/* * Determine the packet's protocol ID. The rule here is that we * assume 802.3 if the type field is short enough to be a length. * This is normal practice and works for any 'now in use' protocol. @@ -155,7 +155,7 @@ static __be16 dvb_net_eth_type_trans(struct sk_buff *skb, rawp = skb->data; - /** + /* * This is a magic hack to spot IPX packets. Older Novell breaks * the protocol design and runs IPX over 802.3 without an 802.2 LLC * layer. We look for FFFF which isn't a used 802.2 SSAP/DSAP. This @@ -164,7 +164,7 @@ static __be16 dvb_net_eth_type_trans(struct sk_buff *skb, if (*(unsigned short *)rawp == 0xFFFF) return htons(ETH_P_802_3); - /** + /* * Real 802.2 LLC */ return htons(ETH_P_802_2); @@ -215,7 +215,8 @@ static int ule_exthdr_padding(struct dvb_net_priv *p) return 0; } -/** Handle ULE extension headers. +/* + * Handle ULE extension headers. * Function is called after a successful CRC32 verification of an ULE SNDU to complete its decoding. * Returns: >= 0: nr. of bytes consumed by next extension header * -1: Mandatory extension header that is not recognized or TEST SNDU; discard. @@ -291,7 +292,7 @@ static int handle_ule_extensions( struct dvb_net_priv *p ) } -/** Prepare for a new ULE SNDU: reset the decoder state. */ +/* Prepare for a new ULE SNDU: reset the decoder state. */ static inline void reset_ule( struct dvb_net_priv *p ) { p->ule_skb = NULL; @@ -304,7 +305,7 @@ static inline void reset_ule( struct dvb_net_priv *p ) p->ule_bridged = 0; } -/** +/* * Decode ULE SNDUs according to draft-ietf-ipdvb-ule-03.txt from a sequence of * TS cells of a single PID. */ @@ -1005,7 +1006,7 @@ static int dvb_net_sec_callback(const u8 *buffer1, size_t buffer1_len, { struct net_device *dev = filter->priv; - /** + /* * we rely on the DVB API definition where exactly one complete * section is delivered in buffer1 */ -- GitLab From 64dc6829a0080e3c8e70d52a98e9b0e30d968bd8 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Nov 2017 10:23:07 -0500 Subject: [PATCH 0136/2547] media: ir-nec-decoder: fix kernel-doc parameters Some parameters aren't correctly identified, as noticed by those warnings: drivers/media/rc/ir-nec-decoder.c:49: warning: No description found for parameter 'ev' drivers/media/rc/ir-nec-decoder.c:49: warning: Excess function parameter 'duration' description in 'ir_nec_decode' drivers/media/rc/ir-nec-decoder.c:189: warning: Excess function parameter 'raw' description in 'ir_nec_scancode_to_raw' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/ir-nec-decoder.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/rc/ir-nec-decoder.c b/drivers/media/rc/ir-nec-decoder.c index a95d09acc22a..6880c190dcd2 100644 --- a/drivers/media/rc/ir-nec-decoder.c +++ b/drivers/media/rc/ir-nec-decoder.c @@ -41,7 +41,7 @@ enum nec_state { /** * ir_nec_decode() - Decode one NEC pulse or space * @dev: the struct rc_dev descriptor of the device - * @duration: the struct ir_raw_event descriptor of the pulse/space + * @ev: the struct ir_raw_event descriptor of the pulse/space * * This function returns -EINVAL if the pulse violates the state machine */ @@ -183,7 +183,6 @@ static int ir_nec_decode(struct rc_dev *dev, struct ir_raw_event ev) * ir_nec_scancode_to_raw() - encode an NEC scancode ready for modulation. * @protocol: specific protocol to use * @scancode: a single NEC scancode. - * @raw: raw data to be modulated. */ static u32 ir_nec_scancode_to_raw(enum rc_proto protocol, u32 scancode) { -- GitLab From 255940e642387ffe886fd881ffc9917f31fe0564 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Nov 2017 10:27:54 -0500 Subject: [PATCH 0137/2547] media: imon: don't use kernel-doc "/**" markups The function documentation here doesn't follow kernel-doc, as parameters aren't documented. So, stop abusing on "/**" markups. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/imon.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/media/rc/imon.c b/drivers/media/rc/imon.c index b25b35b3f6da..eb943e862515 100644 --- a/drivers/media/rc/imon.c +++ b/drivers/media/rc/imon.c @@ -492,7 +492,7 @@ static void free_imon_context(struct imon_context *ictx) dev_dbg(dev, "%s: iMON context freed\n", __func__); } -/** +/* * Called when the Display device (e.g. /dev/lcd0) * is opened by the application. */ @@ -542,7 +542,7 @@ static int display_open(struct inode *inode, struct file *file) return retval; } -/** +/* * Called when the display device (e.g. /dev/lcd0) * is closed by the application. */ @@ -575,7 +575,7 @@ static int display_close(struct inode *inode, struct file *file) return retval; } -/** +/* * Sends a packet to the device -- this function must be called with * ictx->lock held, or its unlock/lock sequence while waiting for tx * to complete can/will lead to a deadlock. @@ -664,7 +664,7 @@ static int send_packet(struct imon_context *ictx) return retval; } -/** +/* * Sends an associate packet to the iMON 2.4G. * * This might not be such a good idea, since it has an id collision with @@ -694,7 +694,7 @@ static int send_associate_24g(struct imon_context *ictx) return retval; } -/** +/* * Sends packets to setup and show clock on iMON display * * Arguments: year - last 2 digits of year, month - 1..12, @@ -781,7 +781,7 @@ static int send_set_imon_clock(struct imon_context *ictx, return retval; } -/** +/* * These are the sysfs functions to handle the association on the iMON 2.4G LT. */ static ssize_t show_associate_remote(struct device *d, @@ -823,7 +823,7 @@ static ssize_t store_associate_remote(struct device *d, return count; } -/** +/* * sysfs functions to control internal imon clock */ static ssize_t show_imon_clock(struct device *d, @@ -923,7 +923,7 @@ static const struct attribute_group imon_rf_attr_group = { .attrs = imon_rf_sysfs_entries }; -/** +/* * Writes data to the VFD. The iMON VFD is 2x16 characters * and requires data in 5 consecutive USB interrupt packets, * each packet but the last carrying 7 bytes. @@ -1008,7 +1008,7 @@ static ssize_t vfd_write(struct file *file, const char __user *buf, return (!retval) ? n_bytes : retval; } -/** +/* * Writes data to the LCD. The iMON OEM LCD screen expects 8-byte * packets. We accept data as 16 hexadecimal digits, followed by a * newline (to make it easy to drive the device from a command-line @@ -1066,7 +1066,7 @@ static ssize_t lcd_write(struct file *file, const char __user *buf, return (!retval) ? n_bytes : retval; } -/** +/* * Callback function for USB core API: transmit data */ static void usb_tx_callback(struct urb *urb) @@ -1087,7 +1087,7 @@ static void usb_tx_callback(struct urb *urb) complete(&ictx->tx.finished); } -/** +/* * report touchscreen input */ static void imon_touch_display_timeout(struct timer_list *t) @@ -1103,7 +1103,7 @@ static void imon_touch_display_timeout(struct timer_list *t) input_sync(ictx->touch); } -/** +/* * iMON IR receivers support two different signal sets -- those used by * the iMON remotes, and those used by the Windows MCE remotes (which is * really just RC-6), but only one or the other at a time, as the signals @@ -1191,7 +1191,7 @@ static inline int tv2int(const struct timeval *a, const struct timeval *b) return sec; } -/** +/* * The directional pad behaves a bit differently, depending on whether this is * one of the older ffdc devices or a newer device. Newer devices appear to * have a higher resolution matrix for more precise mouse movement, but it @@ -1543,7 +1543,7 @@ static void imon_pad_to_keys(struct imon_context *ictx, unsigned char *buf) } } -/** +/* * figure out if these is a press or a release. We don't actually * care about repeats, as those will be auto-generated within the IR * subsystem for repeating scancodes. @@ -1592,10 +1592,10 @@ static int imon_parse_press_type(struct imon_context *ictx, return press_type; } -/** +/* * Process the incoming packet */ -/** +/* * Convert bit count to time duration (in us) and submit * the value to lirc_dev. */ @@ -1608,7 +1608,7 @@ static void submit_data(struct imon_context *context) ir_raw_event_store_with_filter(context->rdev, &ev); } -/** +/* * Process the incoming packet */ static void imon_incoming_ir_raw(struct imon_context *context, @@ -1831,7 +1831,7 @@ static void imon_incoming_scancode(struct imon_context *ictx, } } -/** +/* * Callback function for USB core API: receive data */ static void usb_rx_callback_intf0(struct urb *urb) @@ -2485,7 +2485,7 @@ static void imon_init_display(struct imon_context *ictx, } -/** +/* * Callback function for USB core API: Probe */ static int imon_probe(struct usb_interface *interface, @@ -2583,7 +2583,7 @@ static int imon_probe(struct usb_interface *interface, return ret; } -/** +/* * Callback function for USB core API: disconnect */ static void imon_disconnect(struct usb_interface *interface) -- GitLab From 2a87af6ba1b9df4dda91d7e1a7d750f295ce1e57 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Nov 2017 10:38:03 -0500 Subject: [PATCH 0138/2547] media: videobuf2: don't use kernel-doc "/**" markups While it would be very cool to have those functions using kernel-doc markups, the reality right now is that they don't follow kernel-doc rules, as parameters aren't documented. So, stop abusing on "/**" markups. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 56 ++++++++++++------------ drivers/media/v4l2-core/videobuf2-v4l2.c | 10 ++--- 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index cb115ba6a1d2..a8589d96ef72 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -188,7 +188,7 @@ module_param(debug, int, 0644); static void __vb2_queue_cancel(struct vb2_queue *q); static void __enqueue_in_driver(struct vb2_buffer *vb); -/** +/* * __vb2_buf_mem_alloc() - allocate video memory for the given buffer */ static int __vb2_buf_mem_alloc(struct vb2_buffer *vb) @@ -229,7 +229,7 @@ static int __vb2_buf_mem_alloc(struct vb2_buffer *vb) return ret; } -/** +/* * __vb2_buf_mem_free() - free memory of the given buffer */ static void __vb2_buf_mem_free(struct vb2_buffer *vb) @@ -243,7 +243,7 @@ static void __vb2_buf_mem_free(struct vb2_buffer *vb) } } -/** +/* * __vb2_buf_userptr_put() - release userspace memory associated with * a USERPTR buffer */ @@ -258,7 +258,7 @@ static void __vb2_buf_userptr_put(struct vb2_buffer *vb) } } -/** +/* * __vb2_plane_dmabuf_put() - release memory associated with * a DMABUF shared plane */ @@ -277,7 +277,7 @@ static void __vb2_plane_dmabuf_put(struct vb2_buffer *vb, struct vb2_plane *p) p->dbuf_mapped = 0; } -/** +/* * __vb2_buf_dmabuf_put() - release memory associated with * a DMABUF shared buffer */ @@ -289,7 +289,7 @@ static void __vb2_buf_dmabuf_put(struct vb2_buffer *vb) __vb2_plane_dmabuf_put(vb, &vb->planes[plane]); } -/** +/* * __setup_offsets() - setup unique offsets ("cookies") for every plane in * the buffer. */ @@ -317,7 +317,7 @@ static void __setup_offsets(struct vb2_buffer *vb) } } -/** +/* * __vb2_queue_alloc() - allocate videobuf buffer structures and (for MMAP type) * video buffer memory for all buffers/planes on the queue and initializes the * queue @@ -386,7 +386,7 @@ static int __vb2_queue_alloc(struct vb2_queue *q, enum vb2_memory memory, return buffer; } -/** +/* * __vb2_free_mem() - release all video buffer memory for a given queue */ static void __vb2_free_mem(struct vb2_queue *q, unsigned int buffers) @@ -410,7 +410,7 @@ static void __vb2_free_mem(struct vb2_queue *q, unsigned int buffers) } } -/** +/* * __vb2_queue_free() - free buffers at the end of the queue - video memory and * related information, if no buffers are left return the queue to an * uninitialized state. Might be called even if the queue has already been freed. @@ -544,7 +544,7 @@ bool vb2_buffer_in_use(struct vb2_queue *q, struct vb2_buffer *vb) } EXPORT_SYMBOL(vb2_buffer_in_use); -/** +/* * __buffers_in_use() - return true if any buffers on the queue are in use and * the queue cannot be freed (by the means of REQBUFS(0)) call */ @@ -564,7 +564,7 @@ void vb2_core_querybuf(struct vb2_queue *q, unsigned int index, void *pb) } EXPORT_SYMBOL_GPL(vb2_core_querybuf); -/** +/* * __verify_userptr_ops() - verify that all memory operations required for * USERPTR queue type have been provided */ @@ -577,7 +577,7 @@ static int __verify_userptr_ops(struct vb2_queue *q) return 0; } -/** +/* * __verify_mmap_ops() - verify that all memory operations required for * MMAP queue type have been provided */ @@ -590,7 +590,7 @@ static int __verify_mmap_ops(struct vb2_queue *q) return 0; } -/** +/* * __verify_dmabuf_ops() - verify that all memory operations required for * DMABUF queue type have been provided */ @@ -953,7 +953,7 @@ void vb2_discard_done(struct vb2_queue *q) } EXPORT_SYMBOL_GPL(vb2_discard_done); -/** +/* * __prepare_mmap() - prepare an MMAP buffer */ static int __prepare_mmap(struct vb2_buffer *vb, const void *pb) @@ -966,7 +966,7 @@ static int __prepare_mmap(struct vb2_buffer *vb, const void *pb) return ret ? ret : call_vb_qop(vb, buf_prepare, vb); } -/** +/* * __prepare_userptr() - prepare a USERPTR buffer */ static int __prepare_userptr(struct vb2_buffer *vb, const void *pb) @@ -1082,7 +1082,7 @@ static int __prepare_userptr(struct vb2_buffer *vb, const void *pb) return ret; } -/** +/* * __prepare_dmabuf() - prepare a DMABUF buffer */ static int __prepare_dmabuf(struct vb2_buffer *vb, const void *pb) @@ -1215,7 +1215,7 @@ static int __prepare_dmabuf(struct vb2_buffer *vb, const void *pb) return ret; } -/** +/* * __enqueue_in_driver() - enqueue a vb2_buffer in driver for processing */ static void __enqueue_in_driver(struct vb2_buffer *vb) @@ -1298,7 +1298,7 @@ int vb2_core_prepare_buf(struct vb2_queue *q, unsigned int index, void *pb) } EXPORT_SYMBOL_GPL(vb2_core_prepare_buf); -/** +/* * vb2_start_streaming() - Attempt to start streaming. * @q: videobuf2 queue * @@ -1427,7 +1427,7 @@ int vb2_core_qbuf(struct vb2_queue *q, unsigned int index, void *pb) } EXPORT_SYMBOL_GPL(vb2_core_qbuf); -/** +/* * __vb2_wait_for_done_vb() - wait for a buffer to become available * for dequeuing * @@ -1502,7 +1502,7 @@ static int __vb2_wait_for_done_vb(struct vb2_queue *q, int nonblocking) return 0; } -/** +/* * __vb2_get_done_vb() - get a buffer ready for dequeuing * * Will sleep if required for nonblocking == false. @@ -1553,7 +1553,7 @@ int vb2_wait_for_all_buffers(struct vb2_queue *q) } EXPORT_SYMBOL_GPL(vb2_wait_for_all_buffers); -/** +/* * __vb2_dqbuf() - bring back the buffer to the DEQUEUED state */ static void __vb2_dqbuf(struct vb2_buffer *vb) @@ -1625,7 +1625,7 @@ int vb2_core_dqbuf(struct vb2_queue *q, unsigned int *pindex, void *pb, } EXPORT_SYMBOL_GPL(vb2_core_dqbuf); -/** +/* * __vb2_queue_cancel() - cancel and stop (pause) streaming * * Removes all queued buffers from driver's queue and all buffers queued by @@ -1773,7 +1773,7 @@ int vb2_core_streamoff(struct vb2_queue *q, unsigned int type) } EXPORT_SYMBOL_GPL(vb2_core_streamoff); -/** +/* * __find_plane_by_offset() - find plane associated with the given offset off */ static int __find_plane_by_offset(struct vb2_queue *q, unsigned long off, @@ -2104,7 +2104,7 @@ unsigned int vb2_core_poll(struct vb2_queue *q, struct file *file, } EXPORT_SYMBOL_GPL(vb2_core_poll); -/** +/* * struct vb2_fileio_buf - buffer context used by file io emulator * * vb2 provides a compatibility layer and emulator of file io (read and @@ -2118,7 +2118,7 @@ struct vb2_fileio_buf { unsigned int queued:1; }; -/** +/* * struct vb2_fileio_data - queue context used by file io emulator * * @cur_index: the index of the buffer currently being read from or @@ -2155,7 +2155,7 @@ struct vb2_fileio_data { unsigned write_immediately:1; }; -/** +/* * __vb2_init_fileio() - initialize file io emulator * @q: videobuf2 queue * @read: mode selector (1 means read, 0 means write) @@ -2274,7 +2274,7 @@ static int __vb2_init_fileio(struct vb2_queue *q, int read) return ret; } -/** +/* * __vb2_cleanup_fileio() - free resourced used by file io emulator * @q: videobuf2 queue */ @@ -2293,7 +2293,7 @@ static int __vb2_cleanup_fileio(struct vb2_queue *q) return 0; } -/** +/* * __vb2_perform_fileio() - perform a single file io (read or write) operation * @q: videobuf2 queue * @data: pointed to target userspace buffer diff --git a/drivers/media/v4l2-core/videobuf2-v4l2.c b/drivers/media/v4l2-core/videobuf2-v4l2.c index 0c0669976bdc..4075314a6989 100644 --- a/drivers/media/v4l2-core/videobuf2-v4l2.c +++ b/drivers/media/v4l2-core/videobuf2-v4l2.c @@ -49,7 +49,7 @@ module_param(debug, int, 0644); #define V4L2_BUFFER_OUT_FLAGS (V4L2_BUF_FLAG_PFRAME | V4L2_BUF_FLAG_BFRAME | \ V4L2_BUF_FLAG_KEYFRAME | V4L2_BUF_FLAG_TIMECODE) -/** +/* * __verify_planes_array() - verify that the planes array passed in struct * v4l2_buffer from userspace can be safely used */ @@ -78,7 +78,7 @@ static int __verify_planes_array_core(struct vb2_buffer *vb, const void *pb) return __verify_planes_array(vb, pb); } -/** +/* * __verify_length() - Verify that the bytesused value for each plane fits in * the plane length and that the data offset doesn't exceed the bytesused value. */ @@ -181,7 +181,7 @@ static int vb2_queue_or_prepare_buf(struct vb2_queue *q, struct v4l2_buffer *b, return __verify_planes_array(q->bufs[b->index], b); } -/** +/* * __fill_v4l2_buffer() - fill in a struct v4l2_buffer with information to be * returned to userspace */ @@ -286,7 +286,7 @@ static void __fill_v4l2_buffer(struct vb2_buffer *vb, void *pb) q->last_buffer_dequeued = true; } -/** +/* * __fill_vb2_buffer() - fill a vb2_buffer with information provided in a * v4l2_buffer by the userspace. It also verifies that struct * v4l2_buffer has a valid number of planes. @@ -446,7 +446,7 @@ static const struct vb2_buf_ops v4l2_buf_ops = { .copy_timestamp = __copy_timestamp, }; -/** +/* * vb2_querybuf() - query video buffer information * @q: videobuf queue * @b: buffer struct passed from userspace to vidioc_querybuf handler -- GitLab From 2de2d0b063b08becb2c67a2c338c44e37bdcffee Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 27 Nov 2017 16:10:27 +0100 Subject: [PATCH 0139/2547] drm/i915: fix intel_backlight_device_register declaration The alternative intel_backlight_device_register() definition apparently never got used, but I have now run into a case of i915 being compiled without CONFIG_BACKLIGHT_CLASS_DEVICE, resulting in a number of identical warnings: drivers/gpu/drm/i915/intel_drv.h:1739:12: error: 'intel_backlight_device_register' defined but not used [-Werror=unused-function] This marks the function as 'inline', which was surely the original intention here. Fixes: 1ebaa0b9c2d4 ("drm/i915: Move backlight registration to connector registration") Signed-off-by: Arnd Bergmann Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171127151239.1813673-1-arnd@arndb.de --- drivers/gpu/drm/i915/intel_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index c00441a3d649..c679df99d530 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1750,7 +1750,7 @@ extern struct drm_display_mode *intel_find_panel_downclock( int intel_backlight_device_register(struct intel_connector *connector); void intel_backlight_device_unregister(struct intel_connector *connector); #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */ -static int intel_backlight_device_register(struct intel_connector *connector) +static inline int intel_backlight_device_register(struct intel_connector *connector) { return 0; } -- GitLab From fd94d53e55bd487368dfee9f1af24da78b2bb582 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 27 Nov 2017 16:10:28 +0100 Subject: [PATCH 0140/2547] drm/i915: hide unused intel_panel_set_backlight function Building i915 without backlight support results in a harmless warning for intel_panel_set_backlight: drivers/gpu/drm/i915/intel_panel.c:653:13: error: 'intel_panel_set_backlight' defined but not used [-Werror=unused-function] This moves it into the CONFIG_BACKLIGHT_CLASS_DEVICE section that its caller is in. Signed-off-by: Arnd Bergmann Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171127151239.1813673-2-arnd@arndb.de --- drivers/gpu/drm/i915/intel_panel.c | 88 +++++++++++++++--------------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index adc51e452e3e..fa6831f8c004 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -543,25 +543,6 @@ static u32 pwm_get_backlight(struct intel_connector *connector) return DIV_ROUND_UP(duty_ns * 100, CRC_PMIC_PWM_PERIOD_NS); } -static u32 intel_panel_get_backlight(struct intel_connector *connector) -{ - struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_panel *panel = &connector->panel; - u32 val = 0; - - mutex_lock(&dev_priv->backlight_lock); - - if (panel->backlight.enabled) { - val = panel->backlight.get(connector); - val = intel_panel_compute_brightness(connector, val); - } - - mutex_unlock(&dev_priv->backlight_lock); - - DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); - return val; -} - static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); @@ -649,31 +630,6 @@ intel_panel_actually_set_backlight(const struct drm_connector_state *conn_state, panel->backlight.set(conn_state, level); } -/* set backlight brightness to level in range [0..max], scaling wrt hw min */ -static void intel_panel_set_backlight(const struct drm_connector_state *conn_state, - u32 user_level, u32 user_max) -{ - struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_panel *panel = &connector->panel; - u32 hw_level; - - if (!panel->backlight.present) - return; - - mutex_lock(&dev_priv->backlight_lock); - - WARN_ON(panel->backlight.max == 0); - - hw_level = scale_user_to_hw(connector, user_level, user_max); - panel->backlight.level = hw_level; - - if (panel->backlight.enabled) - intel_panel_actually_set_backlight(conn_state, hw_level); - - mutex_unlock(&dev_priv->backlight_lock); -} - /* set backlight brightness to level in range [0..max], assuming hw min is * respected. */ @@ -1182,6 +1138,50 @@ void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state, } #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) +static u32 intel_panel_get_backlight(struct intel_connector *connector) +{ + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_panel *panel = &connector->panel; + u32 val = 0; + + mutex_lock(&dev_priv->backlight_lock); + + if (panel->backlight.enabled) { + val = panel->backlight.get(connector); + val = intel_panel_compute_brightness(connector, val); + } + + mutex_unlock(&dev_priv->backlight_lock); + + DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); + return val; +} + +/* set backlight brightness to level in range [0..max], scaling wrt hw min */ +static void intel_panel_set_backlight(const struct drm_connector_state *conn_state, + u32 user_level, u32 user_max) +{ + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_panel *panel = &connector->panel; + u32 hw_level; + + if (!panel->backlight.present) + return; + + mutex_lock(&dev_priv->backlight_lock); + + WARN_ON(panel->backlight.max == 0); + + hw_level = scale_user_to_hw(connector, user_level, user_max); + panel->backlight.level = hw_level; + + if (panel->backlight.enabled) + intel_panel_actually_set_backlight(conn_state, hw_level); + + mutex_unlock(&dev_priv->backlight_lock); +} + static int intel_backlight_device_update_status(struct backlight_device *bd) { struct intel_connector *connector = bl_get_data(bd); -- GitLab From fdaa451107ce543d345a339b4d5e20e8e4bac396 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Mon, 20 Nov 2017 20:27:56 -0800 Subject: [PATCH 0141/2547] ASoC: amd: Add error checking to probe function The acp_audio_dma does not perform sufficient error checking in its probe function. This can result in crashes if a critical error path is encountered. Fixes: 7c31335a03b6a ("ASoC: AMD: add AMD ASoC ACP 2.x DMA driver") Cc: Alex Deucher Cc: Dominik Behr Cc: Daniel Kurtz Signed-off-by: Guenter Roeck Reviewed-by: Alex Deucher Signed-off-by: Mark Brown --- sound/soc/amd/acp-pcm-dma.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c index 9f521a55d610..b5e41df6bb3a 100644 --- a/sound/soc/amd/acp-pcm-dma.c +++ b/sound/soc/amd/acp-pcm-dma.c @@ -1051,6 +1051,11 @@ static int acp_audio_probe(struct platform_device *pdev) struct resource *res; const u32 *pdata = pdev->dev.platform_data; + if (!pdata) { + dev_err(&pdev->dev, "Missing platform data\n"); + return -ENODEV; + } + audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), GFP_KERNEL); if (audio_drv_data == NULL) @@ -1058,6 +1063,8 @@ static int acp_audio_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(audio_drv_data->acp_mmio)) + return PTR_ERR(audio_drv_data->acp_mmio); /* The following members gets populated in device 'open' * function. Till then interrupts are disabled in 'acp_init' -- GitLab From c82297fcfaff2862686094061772070e6763e00c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sun, 26 Nov 2017 21:48:56 +0000 Subject: [PATCH 0142/2547] drm/i915: Flush everything on switching to the kernel_context Even though all rendering should have been flushed at the end of the previous requests, add an extra flush after switching to the kernel_context. As the switch to the kernel_context is used when idling the gpu (e.g. suspend), having an extra layer of paranoia to ensure everything is flushed to memory seems sensible. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171126214856.23702-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_context.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index aee0f6d72d33..ce3139e5ec4c 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -620,7 +620,14 @@ int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv) GFP_KERNEL); } - i915_add_request(req); + /* + * Force a flush after the switch to ensure that all rendering + * and operations prior to switching to the kernel context hits + * memory. This should be guaranteed by the previous request, + * but an extra layer of paranoia before we declare the system + * idle (on suspend etc) is advisable! + */ + __i915_add_request(req, true); } return 0; -- GitLab From 4e90a6e222720dd0ec529f87eca990c736ba8ede Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sun, 26 Nov 2017 22:09:01 +0000 Subject: [PATCH 0143/2547] drm/i915: Record default HW state in the GPU error state It may be of interest to both compare the active HW context against the default (aka NULL) context, to see what has been changed and if either are corrupt. v2: Rename the fake vma as fake. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171126220901.14735-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d575a56fc100..50a945d3c11d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1009,6 +1009,7 @@ struct i915_gpu_state { long user_bo_count; struct drm_i915_error_object *wa_ctx; + struct drm_i915_error_object *default_state; struct drm_i915_error_request { long jiffies; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 3d18d67d065f..876be8f1d930 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -791,6 +791,9 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, print_error_obj(m, dev_priv->engine[i], "WA batchbuffer", ee->wa_batchbuffer); + + print_error_obj(m, dev_priv->engine[i], + "NULL context", ee->default_state); } if (error->overlay) @@ -1414,6 +1417,23 @@ static void request_record_user_bo(struct drm_i915_gem_request *request, ee->user_bo_count = count; } +static struct drm_i915_error_object * +capture_object(struct drm_i915_private *dev_priv, + struct drm_i915_gem_object *obj) +{ + if (obj && i915_gem_object_has_pages(obj)) { + struct i915_vma fake = { + .node = { .start = U64_MAX, .size = obj->base.size }, + .pages = obj->mm.pages, + .obj = obj, + }; + + return i915_error_object_create(dev_priv, &fake); + } else { + return NULL; + } +} + static void i915_gem_record_rings(struct drm_i915_private *dev_priv, struct i915_gpu_state *error) { @@ -1485,6 +1505,9 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv, ee->wa_ctx = i915_error_object_create(dev_priv, engine->wa_ctx.vma); + + ee->default_state = + capture_object(dev_priv, engine->default_state); } } -- GitLab From 848b365d5d1f0d41d07773c6a69149b2561f29de Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 23 Nov 2017 11:53:37 +0000 Subject: [PATCH 0144/2547] drm/i915: Rename shrinker init/cleanup to match driver initialisation phase Since the shrinker is registered and unregistered during i915_driver_register and i915_driver_unregister, respectively, rename the init/cleanup functions to match. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171123115338.10270-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.c | 4 ++-- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm/i915/i915_gem_shrinker.c | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 0793a27e2b95..9c519aa4f550 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1215,7 +1215,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) { struct drm_device *dev = &dev_priv->drm; - i915_gem_shrinker_init(dev_priv); + i915_gem_shrinker_register(dev_priv); i915_pmu_register(dev_priv); /* @@ -1277,7 +1277,7 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) i915_guc_log_unregister(dev_priv); drm_dev_unregister(&dev_priv->drm); - i915_gem_shrinker_cleanup(dev_priv); + i915_gem_shrinker_unregister(dev_priv); } /** diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 50a945d3c11d..2dd32de47f9a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3921,8 +3921,8 @@ unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, #define I915_SHRINK_ACTIVE 0x8 #define I915_SHRINK_VMAPS 0x10 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); -void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); -void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); +void i915_gem_shrinker_register(struct drm_i915_private *dev_priv); +void i915_gem_shrinker_unregister(struct drm_i915_private *dev_priv); /* i915_gem_tiling.c */ diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c index 3770e3323fc8..7205dc123d92 100644 --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c @@ -494,12 +494,12 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr } /** - * i915_gem_shrinker_init - Initialize i915 shrinker + * i915_gem_shrinker_register - Register the i915 shrinker * @dev_priv: i915 device * * This function registers and sets up the i915 shrinker and OOM handler. */ -void i915_gem_shrinker_init(struct drm_i915_private *dev_priv) +void i915_gem_shrinker_register(struct drm_i915_private *dev_priv) { dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; @@ -515,12 +515,12 @@ void i915_gem_shrinker_init(struct drm_i915_private *dev_priv) } /** - * i915_gem_shrinker_cleanup - Clean up i915 shrinker + * i915_gem_shrinker_unregister - Unregisters the i915 shrinker * @dev_priv: i915 device * * This function unregisters the i915 shrinker and OOM handler. */ -void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv) +void i915_gem_shrinker_unregister(struct drm_i915_private *dev_priv) { WARN_ON(unregister_vmap_purge_notifier(&dev_priv->mm.vmap_notifier)); WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); -- GitLab From 56fa4bf2b2f08405739a9166f306ceaea421447f Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 23 Nov 2017 11:53:38 +0000 Subject: [PATCH 0145/2547] drm/i915: Update shrinker drm_i915_private naming convention Switch over from the non-descript dev_priv locals to i915. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171123115338.10270-2-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.h | 8 +- drivers/gpu/drm/i915/i915_gem_shrinker.c | 134 +++++++++++------------ 2 files changed, 71 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2dd32de47f9a..bddd65839f60 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3911,7 +3911,7 @@ i915_gem_object_create_internal(struct drm_i915_private *dev_priv, phys_addr_t size); /* i915_gem_shrinker.c */ -unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, +unsigned long i915_gem_shrink(struct drm_i915_private *i915, unsigned long target, unsigned long *nr_scanned, unsigned flags); @@ -3920,9 +3920,9 @@ unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, #define I915_SHRINK_BOUND 0x4 #define I915_SHRINK_ACTIVE 0x8 #define I915_SHRINK_VMAPS 0x10 -unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); -void i915_gem_shrinker_register(struct drm_i915_private *dev_priv); -void i915_gem_shrinker_unregister(struct drm_i915_private *dev_priv); +unsigned long i915_gem_shrink_all(struct drm_i915_private *i915); +void i915_gem_shrinker_register(struct drm_i915_private *i915); +void i915_gem_shrinker_unregister(struct drm_i915_private *i915); /* i915_gem_tiling.c */ diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c index 7205dc123d92..9029ed04879c 100644 --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c @@ -35,9 +35,9 @@ #include "i915_drv.h" #include "i915_trace.h" -static bool shrinker_lock(struct drm_i915_private *dev_priv, bool *unlock) +static bool shrinker_lock(struct drm_i915_private *i915, bool *unlock) { - switch (mutex_trylock_recursive(&dev_priv->drm.struct_mutex)) { + switch (mutex_trylock_recursive(&i915->drm.struct_mutex)) { case MUTEX_TRYLOCK_RECURSIVE: *unlock = false; return true; @@ -47,7 +47,7 @@ static bool shrinker_lock(struct drm_i915_private *dev_priv, bool *unlock) preempt_disable(); do { cpu_relax(); - if (mutex_trylock(&dev_priv->drm.struct_mutex)) { + if (mutex_trylock(&i915->drm.struct_mutex)) { *unlock = true; break; } @@ -63,12 +63,12 @@ static bool shrinker_lock(struct drm_i915_private *dev_priv, bool *unlock) BUG(); } -static void shrinker_unlock(struct drm_i915_private *dev_priv, bool unlock) +static void shrinker_unlock(struct drm_i915_private *i915, bool unlock) { if (!unlock) return; - mutex_unlock(&dev_priv->drm.struct_mutex); + mutex_unlock(&i915->drm.struct_mutex); } static bool swap_available(void) @@ -118,7 +118,7 @@ static bool unsafe_drop_pages(struct drm_i915_gem_object *obj) /** * i915_gem_shrink - Shrink buffer object caches - * @dev_priv: i915 device + * @i915: i915 device * @target: amount of memory to make available, in pages * @nr_scanned: optional output for number of pages scanned (incremental) * @flags: control flags for selecting cache types @@ -142,7 +142,7 @@ static bool unsafe_drop_pages(struct drm_i915_gem_object *obj) * The number of pages of backing storage actually released. */ unsigned long -i915_gem_shrink(struct drm_i915_private *dev_priv, +i915_gem_shrink(struct drm_i915_private *i915, unsigned long target, unsigned long *nr_scanned, unsigned flags) @@ -151,15 +151,15 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, struct list_head *list; unsigned int bit; } phases[] = { - { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND }, - { &dev_priv->mm.bound_list, I915_SHRINK_BOUND }, + { &i915->mm.unbound_list, I915_SHRINK_UNBOUND }, + { &i915->mm.bound_list, I915_SHRINK_BOUND }, { NULL, 0 }, }, *phase; unsigned long count = 0; unsigned long scanned = 0; bool unlock; - if (!shrinker_lock(dev_priv, &unlock)) + if (!shrinker_lock(i915, &unlock)) return 0; /* @@ -172,10 +172,10 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, * we will free as much as we can and hope to get a second chance. */ if (flags & I915_SHRINK_ACTIVE) - i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED); + i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED); - trace_i915_gem_shrink(dev_priv, target, flags); - i915_gem_retire_requests(dev_priv); + trace_i915_gem_shrink(i915, target, flags); + i915_gem_retire_requests(i915); /* * Unbinding of objects will require HW access; Let us not wake the @@ -183,7 +183,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, * we will force the wake during oom-notifier. */ if ((flags & I915_SHRINK_BOUND) && - !intel_runtime_pm_get_if_in_use(dev_priv)) + !intel_runtime_pm_get_if_in_use(i915)) flags &= ~I915_SHRINK_BOUND; /* @@ -221,7 +221,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, * to be able to shrink their pages, so they remain on * the unbound/bound list until actually freed. */ - spin_lock(&dev_priv->mm.obj_lock); + spin_lock(&i915->mm.obj_lock); while (count < target && (obj = list_first_entry_or_null(phase->list, typeof(*obj), @@ -244,7 +244,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, if (!can_release_pages(obj)) continue; - spin_unlock(&dev_priv->mm.obj_lock); + spin_unlock(&i915->mm.obj_lock); if (unsafe_drop_pages(obj)) { /* May arrive from get_pages on another bo */ @@ -258,18 +258,18 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, } scanned += obj->base.size >> PAGE_SHIFT; - spin_lock(&dev_priv->mm.obj_lock); + spin_lock(&i915->mm.obj_lock); } list_splice_tail(&still_in_list, phase->list); - spin_unlock(&dev_priv->mm.obj_lock); + spin_unlock(&i915->mm.obj_lock); } if (flags & I915_SHRINK_BOUND) - intel_runtime_pm_put(dev_priv); + intel_runtime_pm_put(i915); - i915_gem_retire_requests(dev_priv); + i915_gem_retire_requests(i915); - shrinker_unlock(dev_priv, unlock); + shrinker_unlock(i915, unlock); if (nr_scanned) *nr_scanned += scanned; @@ -278,7 +278,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, /** * i915_gem_shrink_all - Shrink buffer object caches completely - * @dev_priv: i915 device + * @i915: i915 device * * This is a simple wraper around i915_gem_shrink() to aggressively shrink all * caches completely. It also first waits for and retires all outstanding @@ -290,16 +290,16 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, * Returns: * The number of pages of backing storage actually released. */ -unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv) +unsigned long i915_gem_shrink_all(struct drm_i915_private *i915) { unsigned long freed; - intel_runtime_pm_get(dev_priv); - freed = i915_gem_shrink(dev_priv, -1UL, NULL, + intel_runtime_pm_get(i915); + freed = i915_gem_shrink(i915, -1UL, NULL, I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_ACTIVE); - intel_runtime_pm_put(dev_priv); + intel_runtime_pm_put(i915); return freed; } @@ -347,53 +347,53 @@ i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) { - struct drm_i915_private *dev_priv = + struct drm_i915_private *i915 = container_of(shrinker, struct drm_i915_private, mm.shrinker); unsigned long freed; bool unlock; sc->nr_scanned = 0; - if (!shrinker_lock(dev_priv, &unlock)) + if (!shrinker_lock(i915, &unlock)) return SHRINK_STOP; - freed = i915_gem_shrink(dev_priv, + freed = i915_gem_shrink(i915, sc->nr_to_scan, &sc->nr_scanned, I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE); if (freed < sc->nr_to_scan) - freed += i915_gem_shrink(dev_priv, + freed += i915_gem_shrink(i915, sc->nr_to_scan - sc->nr_scanned, &sc->nr_scanned, I915_SHRINK_BOUND | I915_SHRINK_UNBOUND); if (freed < sc->nr_to_scan && current_is_kswapd()) { - intel_runtime_pm_get(dev_priv); - freed += i915_gem_shrink(dev_priv, + intel_runtime_pm_get(i915); + freed += i915_gem_shrink(i915, sc->nr_to_scan - sc->nr_scanned, &sc->nr_scanned, I915_SHRINK_ACTIVE | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND); - intel_runtime_pm_put(dev_priv); + intel_runtime_pm_put(i915); } - shrinker_unlock(dev_priv, unlock); + shrinker_unlock(i915, unlock); return sc->nr_scanned ? freed : SHRINK_STOP; } static bool -shrinker_lock_uninterruptible(struct drm_i915_private *dev_priv, bool *unlock, +shrinker_lock_uninterruptible(struct drm_i915_private *i915, bool *unlock, int timeout_ms) { unsigned long timeout = jiffies + msecs_to_jiffies_timeout(timeout_ms); do { - if (i915_gem_wait_for_idle(dev_priv, 0) == 0 && - shrinker_lock(dev_priv, unlock)) + if (i915_gem_wait_for_idle(i915, 0) == 0 && + shrinker_lock(i915, unlock)) break; schedule_timeout_killable(1); @@ -412,32 +412,32 @@ shrinker_lock_uninterruptible(struct drm_i915_private *dev_priv, bool *unlock, static int i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) { - struct drm_i915_private *dev_priv = + struct drm_i915_private *i915 = container_of(nb, struct drm_i915_private, mm.oom_notifier); struct drm_i915_gem_object *obj; unsigned long unevictable, bound, unbound, freed_pages; - freed_pages = i915_gem_shrink_all(dev_priv); + freed_pages = i915_gem_shrink_all(i915); /* Because we may be allocating inside our own driver, we cannot * assert that there are no objects with pinned pages that are not * being pointed to by hardware. */ unbound = bound = unevictable = 0; - spin_lock(&dev_priv->mm.obj_lock); - list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) { + spin_lock(&i915->mm.obj_lock); + list_for_each_entry(obj, &i915->mm.unbound_list, mm.link) { if (!can_release_pages(obj)) unevictable += obj->base.size >> PAGE_SHIFT; else unbound += obj->base.size >> PAGE_SHIFT; } - list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) { + list_for_each_entry(obj, &i915->mm.bound_list, mm.link) { if (!can_release_pages(obj)) unevictable += obj->base.size >> PAGE_SHIFT; else bound += obj->base.size >> PAGE_SHIFT; } - spin_unlock(&dev_priv->mm.obj_lock); + spin_unlock(&i915->mm.obj_lock); if (freed_pages || unbound || bound) pr_info("Purging GPU memory, %lu pages freed, " @@ -455,39 +455,39 @@ i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) static int i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr) { - struct drm_i915_private *dev_priv = + struct drm_i915_private *i915 = container_of(nb, struct drm_i915_private, mm.vmap_notifier); struct i915_vma *vma, *next; unsigned long freed_pages = 0; bool unlock; int ret; - if (!shrinker_lock_uninterruptible(dev_priv, &unlock, 5000)) + if (!shrinker_lock_uninterruptible(i915, &unlock, 5000)) return NOTIFY_DONE; /* Force everything onto the inactive lists */ - ret = i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED); + ret = i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED); if (ret) goto out; - intel_runtime_pm_get(dev_priv); - freed_pages += i915_gem_shrink(dev_priv, -1UL, NULL, + intel_runtime_pm_get(i915); + freed_pages += i915_gem_shrink(i915, -1UL, NULL, I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_ACTIVE | I915_SHRINK_VMAPS); - intel_runtime_pm_put(dev_priv); + intel_runtime_pm_put(i915); /* We also want to clear any cached iomaps as they wrap vmap */ list_for_each_entry_safe(vma, next, - &dev_priv->ggtt.base.inactive_list, vm_link) { + &i915->ggtt.base.inactive_list, vm_link) { unsigned long count = vma->node.size >> PAGE_SHIFT; if (vma->iomap && i915_vma_unbind(vma) == 0) freed_pages += count; } out: - shrinker_unlock(dev_priv, unlock); + shrinker_unlock(i915, unlock); *(unsigned long *)ptr += freed_pages; return NOTIFY_DONE; @@ -495,34 +495,34 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr /** * i915_gem_shrinker_register - Register the i915 shrinker - * @dev_priv: i915 device + * @i915: i915 device * * This function registers and sets up the i915 shrinker and OOM handler. */ -void i915_gem_shrinker_register(struct drm_i915_private *dev_priv) +void i915_gem_shrinker_register(struct drm_i915_private *i915) { - dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; - dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; - dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; - dev_priv->mm.shrinker.batch = 4096; - WARN_ON(register_shrinker(&dev_priv->mm.shrinker)); + i915->mm.shrinker.scan_objects = i915_gem_shrinker_scan; + i915->mm.shrinker.count_objects = i915_gem_shrinker_count; + i915->mm.shrinker.seeks = DEFAULT_SEEKS; + i915->mm.shrinker.batch = 4096; + WARN_ON(register_shrinker(&i915->mm.shrinker)); - dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; - WARN_ON(register_oom_notifier(&dev_priv->mm.oom_notifier)); + i915->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; + WARN_ON(register_oom_notifier(&i915->mm.oom_notifier)); - dev_priv->mm.vmap_notifier.notifier_call = i915_gem_shrinker_vmap; - WARN_ON(register_vmap_purge_notifier(&dev_priv->mm.vmap_notifier)); + i915->mm.vmap_notifier.notifier_call = i915_gem_shrinker_vmap; + WARN_ON(register_vmap_purge_notifier(&i915->mm.vmap_notifier)); } /** * i915_gem_shrinker_unregister - Unregisters the i915 shrinker - * @dev_priv: i915 device + * @i915: i915 device * * This function unregisters the i915 shrinker and OOM handler. */ -void i915_gem_shrinker_unregister(struct drm_i915_private *dev_priv) +void i915_gem_shrinker_unregister(struct drm_i915_private *i915) { - WARN_ON(unregister_vmap_purge_notifier(&dev_priv->mm.vmap_notifier)); - WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); - unregister_shrinker(&dev_priv->mm.shrinker); + WARN_ON(unregister_vmap_purge_notifier(&i915->mm.vmap_notifier)); + WARN_ON(unregister_oom_notifier(&i915->mm.oom_notifier)); + unregister_shrinker(&i915->mm.shrinker); } -- GitLab From d02a1d830880b611000aaa0df8a8d7aabf1d8718 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Nov 2017 12:30:54 +0000 Subject: [PATCH 0146/2547] drm/i915: Rename i915_gem_timelines_mark_idle The kerneldoc markup for i915_gem_timelines_mark_idle() was incorrect, so take the opportunity to also convert it from the "mark_idle" to "park" naming scheme. drivers/gpu/drm/i915/i915_gem_timeline.c:120: warning: No description found for parameter 'i915' Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171127123054.20966-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 3 ++- drivers/gpu/drm/i915/i915_gem_timeline.c | 6 +++--- drivers/gpu/drm/i915/i915_gem_timeline.h | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e03d6c2554e2..354b0546a191 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3371,7 +3371,8 @@ i915_gem_idle_work_handler(struct work_struct *work) synchronize_irq(dev_priv->drm.irq); intel_engines_park(dev_priv); - i915_gem_timelines_mark_idle(dev_priv); + i915_gem_timelines_park(dev_priv); + i915_pmu_gt_parked(dev_priv); GEM_BUG_ON(!dev_priv->gt.awake); diff --git a/drivers/gpu/drm/i915/i915_gem_timeline.c b/drivers/gpu/drm/i915/i915_gem_timeline.c index c597ce277a04..c01905d6450c 100644 --- a/drivers/gpu/drm/i915/i915_gem_timeline.c +++ b/drivers/gpu/drm/i915/i915_gem_timeline.c @@ -107,8 +107,8 @@ int i915_gem_timeline_init__global(struct drm_i915_private *i915) } /** - * i915_gem_timelines_mark_idle -- called when the driver idles - * @i915 - the drm_i915_private device + * i915_gem_timelines_park - called when the driver idles + * @i915: the drm_i915_private device * * When the driver is completely idle, we know that all of our sync points * have been signaled and our tracking is then entirely redundant. Any request @@ -116,7 +116,7 @@ int i915_gem_timeline_init__global(struct drm_i915_private *i915) * the fence is signaled and therefore we will not even look them up in the * sync point map. */ -void i915_gem_timelines_mark_idle(struct drm_i915_private *i915) +void i915_gem_timelines_park(struct drm_i915_private *i915) { struct i915_gem_timeline *timeline; int i; diff --git a/drivers/gpu/drm/i915/i915_gem_timeline.h b/drivers/gpu/drm/i915/i915_gem_timeline.h index bfb5eb94c64d..b5a22400a01f 100644 --- a/drivers/gpu/drm/i915/i915_gem_timeline.h +++ b/drivers/gpu/drm/i915/i915_gem_timeline.h @@ -93,7 +93,7 @@ int i915_gem_timeline_init(struct drm_i915_private *i915, struct i915_gem_timeline *tl, const char *name); int i915_gem_timeline_init__global(struct drm_i915_private *i915); -void i915_gem_timelines_mark_idle(struct drm_i915_private *i915); +void i915_gem_timelines_park(struct drm_i915_private *i915); void i915_gem_timeline_fini(struct i915_gem_timeline *tl); static inline int __intel_timeline_sync_set(struct intel_timeline *tl, -- GitLab From 695b78b548d8a26288f041e907ff17758df9e1d5 Mon Sep 17 00:00:00 2001 From: "Maciej S. Szmigiero" Date: Mon, 20 Nov 2017 23:14:55 +0100 Subject: [PATCH 0147/2547] ASoC: fsl_ssi: AC'97 ops need regmap, clock and cleaning up on failure AC'97 ops (register read / write) need SSI regmap and clock, so they have to be set after them. We also need to set these ops back to NULL if we fail the probe. Signed-off-by: Maciej S. Szmigiero Acked-by: Nicolin Chen Signed-off-by: Mark Brown Cc: stable@vger.kernel.org --- sound/soc/fsl/fsl_ssi.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index f2f51e06e22c..c3a83ed0297e 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -1458,12 +1458,6 @@ static int fsl_ssi_probe(struct platform_device *pdev) sizeof(fsl_ssi_ac97_dai)); fsl_ac97_data = ssi_private; - - ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); - if (ret) { - dev_err(&pdev->dev, "could not set AC'97 ops\n"); - return ret; - } } else { /* Initialize this copy of the CPU DAI driver structure */ memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, @@ -1574,6 +1568,14 @@ static int fsl_ssi_probe(struct platform_device *pdev) return ret; } + if (fsl_ssi_is_ac97(ssi_private)) { + ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); + if (ret) { + dev_err(&pdev->dev, "could not set AC'97 ops\n"); + goto error_ac97_ops; + } + } + ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component, &ssi_private->cpu_dai_drv, 1); if (ret) { @@ -1657,6 +1659,10 @@ static int fsl_ssi_probe(struct platform_device *pdev) fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); error_asoc_register: + if (fsl_ssi_is_ac97(ssi_private)) + snd_soc_set_ac97_ops(NULL); + +error_ac97_ops: if (ssi_private->soc->imx) fsl_ssi_imx_clean(pdev, ssi_private); -- GitLab From b880b8056b31288323745a13930bc45cf4c86e9d Mon Sep 17 00:00:00 2001 From: "Maciej S. Szmigiero" Date: Mon, 20 Nov 2017 23:16:07 +0100 Subject: [PATCH 0148/2547] ASoC: fsl_ssi: serialize AC'97 register access operations AC'97 register access operations (both read and write) on SSI use a one, shared set of SSI registers for AC'97 register address and data. This means that only one such access is possible at a time and so all these operations need to be serialized. Since an AC'97 register access operation in this driver takes 100us+ let's use a mutex for this. Use this opportunity to also change a default value returned from AC'97 register read function from -1 to 0, since that's what AC'97 specs require to be returned when unknown / undefined registers are read. Signed-off-by: Maciej S. Szmigiero Signed-off-by: Mark Brown --- sound/soc/fsl/fsl_ssi.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index c3a83ed0297e..424bafaf51ef 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include @@ -265,6 +266,8 @@ struct fsl_ssi_private { u32 fifo_watermark; u32 dma_maxburst; + + struct mutex ac97_reg_lock; }; /* @@ -1260,11 +1263,13 @@ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, if (reg > 0x7f) return; + mutex_lock(&fsl_ac97_data->ac97_reg_lock); + ret = clk_prepare_enable(fsl_ac97_data->clk); if (ret) { pr_err("ac97 write clk_prepare_enable failed: %d\n", ret); - return; + goto ret_unlock; } lreg = reg << 12; @@ -1278,6 +1283,9 @@ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, udelay(100); clk_disable_unprepare(fsl_ac97_data->clk); + +ret_unlock: + mutex_unlock(&fsl_ac97_data->ac97_reg_lock); } static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, @@ -1285,16 +1293,18 @@ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, { struct regmap *regs = fsl_ac97_data->regs; - unsigned short val = -1; + unsigned short val = 0; u32 reg_val; unsigned int lreg; int ret; + mutex_lock(&fsl_ac97_data->ac97_reg_lock); + ret = clk_prepare_enable(fsl_ac97_data->clk); if (ret) { pr_err("ac97 read clk_prepare_enable failed: %d\n", ret); - return -1; + goto ret_unlock; } lreg = (reg & 0x7f) << 12; @@ -1309,6 +1319,8 @@ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, clk_disable_unprepare(fsl_ac97_data->clk); +ret_unlock: + mutex_unlock(&fsl_ac97_data->ac97_reg_lock); return val; } @@ -1569,6 +1581,7 @@ static int fsl_ssi_probe(struct platform_device *pdev) } if (fsl_ssi_is_ac97(ssi_private)) { + mutex_init(&ssi_private->ac97_reg_lock); ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); if (ret) { dev_err(&pdev->dev, "could not set AC'97 ops\n"); @@ -1663,6 +1676,9 @@ static int fsl_ssi_probe(struct platform_device *pdev) snd_soc_set_ac97_ops(NULL); error_ac97_ops: + if (fsl_ssi_is_ac97(ssi_private)) + mutex_destroy(&ssi_private->ac97_reg_lock); + if (ssi_private->soc->imx) fsl_ssi_imx_clean(pdev, ssi_private); @@ -1681,8 +1697,10 @@ static int fsl_ssi_remove(struct platform_device *pdev) if (ssi_private->soc->imx) fsl_ssi_imx_clean(pdev, ssi_private); - if (fsl_ssi_is_ac97(ssi_private)) + if (fsl_ssi_is_ac97(ssi_private)) { snd_soc_set_ac97_ops(NULL); + mutex_destroy(&ssi_private->ac97_reg_lock); + } return 0; } -- GitLab From 346cccf88319344c9f513bd85df6ae2258e8a8ea Mon Sep 17 00:00:00 2001 From: "oder_chiou@realtek.com" Date: Mon, 20 Nov 2017 18:23:19 +0800 Subject: [PATCH 0149/2547] ASoC: rt5514: Add the sanity check for the driver_data in the resume function If the rt5514 spi driver is loaded, but the snd_soc_platform_driver is not loaded by the correct DAI settings, the NULL pointer will be gotten by snd_soc_platform_get_drvdata in the resume function. Signed-off-by: Oder Chiou Signed-off-by: Mark Brown --- sound/soc/codecs/rt5514-spi.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/sound/soc/codecs/rt5514-spi.c b/sound/soc/codecs/rt5514-spi.c index 2df91db765ac..ca6a90d8fc39 100644 --- a/sound/soc/codecs/rt5514-spi.c +++ b/sound/soc/codecs/rt5514-spi.c @@ -482,10 +482,13 @@ static int __maybe_unused rt5514_resume(struct device *dev) if (device_may_wakeup(dev)) disable_irq_wake(irq); - if (rt5514_dsp->substream) { - rt5514_spi_burst_read(RT5514_IRQ_CTRL, (u8 *)&buf, sizeof(buf)); - if (buf[0] & RT5514_IRQ_STATUS_BIT) - rt5514_schedule_copy(rt5514_dsp); + if (rt5514_dsp) { + if (rt5514_dsp->substream) { + rt5514_spi_burst_read(RT5514_IRQ_CTRL, (u8 *)&buf, + sizeof(buf)); + if (buf[0] & RT5514_IRQ_STATUS_BIT) + rt5514_schedule_copy(rt5514_dsp); + } } return 0; -- GitLab From aa24163b2ee5c92120e32e99b5a93143a0f4258e Mon Sep 17 00:00:00 2001 From: Prateek Sood Date: Wed, 15 Nov 2017 19:50:14 +0530 Subject: [PATCH 0150/2547] cgroup/cpuset: remove circular dependency deadlock Remove circular dependency deadlock in a scenario where hotplug of CPU is being done while there is updation in cgroup and cpuset triggered from userspace. Process A => kthreadd => Process B => Process C => Process A Process A cpu_subsys_offline(); cpu_down(); _cpu_down(); percpu_down_write(&cpu_hotplug_lock); //held cpuhp_invoke_callback(); workqueue_offline_cpu(); queue_work_on(); // unbind_work on system_highpri_wq __queue_work(); insert_work(); wake_up_worker(); flush_work(); wait_for_completion(); worker_thread(); manage_workers(); create_worker(); kthread_create_on_node(); wake_up_process(kthreadd_task); kthreadd kthreadd(); kernel_thread(); do_fork(); copy_process(); percpu_down_read(&cgroup_threadgroup_rwsem); __rwsem_down_read_failed_common(); //waiting Process B kernfs_fop_write(); cgroup_file_write(); cgroup_procs_write(); percpu_down_write(&cgroup_threadgroup_rwsem); //held cgroup_attach_task(); cgroup_migrate(); cgroup_migrate_execute(); cpuset_can_attach(); mutex_lock(&cpuset_mutex); //waiting Process C kernfs_fop_write(); cgroup_file_write(); cpuset_write_resmask(); mutex_lock(&cpuset_mutex); //held update_cpumask(); update_cpumasks_hier(); rebuild_sched_domains_locked(); get_online_cpus(); percpu_down_read(&cpu_hotplug_lock); //waiting Eliminating deadlock by reversing the locking order for cpuset_mutex and cpu_hotplug_lock. Signed-off-by: Prateek Sood Signed-off-by: Tejun Heo --- kernel/cgroup/cpuset.c | 53 ++++++++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 23 deletions(-) diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c index f7efa7b4d825..cab5fd1ee767 100644 --- a/kernel/cgroup/cpuset.c +++ b/kernel/cgroup/cpuset.c @@ -812,6 +812,18 @@ static int generate_sched_domains(cpumask_var_t **domains, return ndoms; } +static void cpuset_sched_change_begin(void) +{ + cpus_read_lock(); + mutex_lock(&cpuset_mutex); +} + +static void cpuset_sched_change_end(void) +{ + mutex_unlock(&cpuset_mutex); + cpus_read_unlock(); +} + /* * Rebuild scheduler domains. * @@ -821,16 +833,14 @@ static int generate_sched_domains(cpumask_var_t **domains, * 'cpus' is removed, then call this routine to rebuild the * scheduler's dynamic sched domains. * - * Call with cpuset_mutex held. Takes get_online_cpus(). */ -static void rebuild_sched_domains_locked(void) +static void rebuild_sched_domains_cpuslocked(void) { struct sched_domain_attr *attr; cpumask_var_t *doms; int ndoms; lockdep_assert_held(&cpuset_mutex); - get_online_cpus(); /* * We have raced with CPU hotplug. Don't do anything to avoid @@ -838,27 +848,25 @@ static void rebuild_sched_domains_locked(void) * Anyways, hotplug work item will rebuild sched domains. */ if (!cpumask_equal(top_cpuset.effective_cpus, cpu_active_mask)) - goto out; + return; /* Generate domain masks and attrs */ ndoms = generate_sched_domains(&doms, &attr); /* Have scheduler rebuild the domains */ partition_sched_domains(ndoms, doms, attr); -out: - put_online_cpus(); } #else /* !CONFIG_SMP */ -static void rebuild_sched_domains_locked(void) +static void rebuild_sched_domains_cpuslocked(void) { } #endif /* CONFIG_SMP */ void rebuild_sched_domains(void) { - mutex_lock(&cpuset_mutex); - rebuild_sched_domains_locked(); - mutex_unlock(&cpuset_mutex); + cpuset_sched_change_begin(); + rebuild_sched_domains_cpuslocked(); + cpuset_sched_change_end(); } /** @@ -944,7 +952,7 @@ static void update_cpumasks_hier(struct cpuset *cs, struct cpumask *new_cpus) rcu_read_unlock(); if (need_rebuild_sched_domains) - rebuild_sched_domains_locked(); + rebuild_sched_domains_cpuslocked(); } /** @@ -1276,7 +1284,7 @@ static int update_relax_domain_level(struct cpuset *cs, s64 val) cs->relax_domain_level = val; if (!cpumask_empty(cs->cpus_allowed) && is_sched_load_balance(cs)) - rebuild_sched_domains_locked(); + rebuild_sched_domains_cpuslocked(); } return 0; @@ -1309,7 +1317,6 @@ static void update_tasks_flags(struct cpuset *cs) * * Call with cpuset_mutex held. */ - static int update_flag(cpuset_flagbits_t bit, struct cpuset *cs, int turning_on) { @@ -1342,7 +1349,7 @@ static int update_flag(cpuset_flagbits_t bit, struct cpuset *cs, spin_unlock_irq(&callback_lock); if (!cpumask_empty(trialcs->cpus_allowed) && balance_flag_changed) - rebuild_sched_domains_locked(); + rebuild_sched_domains_cpuslocked(); if (spread_flag_changed) update_tasks_flags(cs); @@ -1610,7 +1617,7 @@ static int cpuset_write_u64(struct cgroup_subsys_state *css, struct cftype *cft, cpuset_filetype_t type = cft->private; int retval = 0; - mutex_lock(&cpuset_mutex); + cpuset_sched_change_begin(); if (!is_cpuset_online(cs)) { retval = -ENODEV; goto out_unlock; @@ -1646,7 +1653,7 @@ static int cpuset_write_u64(struct cgroup_subsys_state *css, struct cftype *cft, break; } out_unlock: - mutex_unlock(&cpuset_mutex); + cpuset_sched_change_end(); return retval; } @@ -1657,7 +1664,7 @@ static int cpuset_write_s64(struct cgroup_subsys_state *css, struct cftype *cft, cpuset_filetype_t type = cft->private; int retval = -ENODEV; - mutex_lock(&cpuset_mutex); + cpuset_sched_change_begin(); if (!is_cpuset_online(cs)) goto out_unlock; @@ -1670,7 +1677,7 @@ static int cpuset_write_s64(struct cgroup_subsys_state *css, struct cftype *cft, break; } out_unlock: - mutex_unlock(&cpuset_mutex); + cpuset_sched_change_end(); return retval; } @@ -1709,7 +1716,7 @@ static ssize_t cpuset_write_resmask(struct kernfs_open_file *of, kernfs_break_active_protection(of->kn); flush_work(&cpuset_hotplug_work); - mutex_lock(&cpuset_mutex); + cpuset_sched_change_begin(); if (!is_cpuset_online(cs)) goto out_unlock; @@ -1733,7 +1740,7 @@ static ssize_t cpuset_write_resmask(struct kernfs_open_file *of, free_trial_cpuset(trialcs); out_unlock: - mutex_unlock(&cpuset_mutex); + cpuset_sched_change_end(); kernfs_unbreak_active_protection(of->kn); css_put(&cs->css); flush_workqueue(cpuset_migrate_mm_wq); @@ -2034,14 +2041,14 @@ static int cpuset_css_online(struct cgroup_subsys_state *css) /* * If the cpuset being removed has its flag 'sched_load_balance' * enabled, then simulate turning sched_load_balance off, which - * will call rebuild_sched_domains_locked(). + * will call rebuild_sched_domains_cpuslocked(). */ static void cpuset_css_offline(struct cgroup_subsys_state *css) { struct cpuset *cs = css_cs(css); - mutex_lock(&cpuset_mutex); + cpuset_sched_change_begin(); if (is_sched_load_balance(cs)) update_flag(CS_SCHED_LOAD_BALANCE, cs, 0); @@ -2049,7 +2056,7 @@ static void cpuset_css_offline(struct cgroup_subsys_state *css) cpuset_dec(); clear_bit(CS_ONLINE, &cs->flags); - mutex_unlock(&cpuset_mutex); + cpuset_sched_change_end(); } static void cpuset_css_free(struct cgroup_subsys_state *css) -- GitLab From 1599a185f0e6113be185b9fb809c621c73865829 Mon Sep 17 00:00:00 2001 From: Prateek Sood Date: Wed, 15 Nov 2017 19:50:15 +0530 Subject: [PATCH 0151/2547] cpuset: Make cpuset hotplug synchronous Convert cpuset_hotplug_workfn() into synchronous call for cpu hotplug path. For memory hotplug path it still gets queued as a work item. Since cpuset_hotplug_workfn() can be made synchronous for cpu hotplug path, it is not required to wait for cpuset hotplug while thawing processes. Signed-off-by: Prateek Sood Signed-off-by: Tejun Heo --- include/linux/cpuset.h | 6 ------ kernel/cgroup/cpuset.c | 41 ++++++++++++++++++++--------------------- kernel/power/process.c | 2 -- kernel/sched/core.c | 1 - 4 files changed, 20 insertions(+), 30 deletions(-) diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h index 1b8e41597ef5..2ab910f85154 100644 --- a/include/linux/cpuset.h +++ b/include/linux/cpuset.h @@ -52,9 +52,7 @@ static inline void cpuset_dec(void) extern int cpuset_init(void); extern void cpuset_init_smp(void); -extern void cpuset_force_rebuild(void); extern void cpuset_update_active_cpus(void); -extern void cpuset_wait_for_hotplug(void); extern void cpuset_cpus_allowed(struct task_struct *p, struct cpumask *mask); extern void cpuset_cpus_allowed_fallback(struct task_struct *p); extern nodemask_t cpuset_mems_allowed(struct task_struct *p); @@ -167,15 +165,11 @@ static inline bool cpusets_enabled(void) { return false; } static inline int cpuset_init(void) { return 0; } static inline void cpuset_init_smp(void) {} -static inline void cpuset_force_rebuild(void) { } - static inline void cpuset_update_active_cpus(void) { partition_sched_domains(1, NULL, NULL); } -static inline void cpuset_wait_for_hotplug(void) { } - static inline void cpuset_cpus_allowed(struct task_struct *p, struct cpumask *mask) { diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c index cab5fd1ee767..227bc25d951d 100644 --- a/kernel/cgroup/cpuset.c +++ b/kernel/cgroup/cpuset.c @@ -2277,15 +2277,8 @@ static void cpuset_hotplug_update_tasks(struct cpuset *cs) mutex_unlock(&cpuset_mutex); } -static bool force_rebuild; - -void cpuset_force_rebuild(void) -{ - force_rebuild = true; -} - /** - * cpuset_hotplug_workfn - handle CPU/memory hotunplug for a cpuset + * cpuset_hotplug - handle CPU/memory hotunplug for a cpuset * * This function is called after either CPU or memory configuration has * changed and updates cpuset accordingly. The top_cpuset is always @@ -2300,7 +2293,7 @@ void cpuset_force_rebuild(void) * Note that CPU offlining during suspend is ignored. We don't modify * cpusets across suspend/resume cycles at all. */ -static void cpuset_hotplug_workfn(struct work_struct *work) +static void cpuset_hotplug(bool use_cpu_hp_lock) { static cpumask_t new_cpus; static nodemask_t new_mems; @@ -2358,25 +2351,31 @@ static void cpuset_hotplug_workfn(struct work_struct *work) } /* rebuild sched domains if cpus_allowed has changed */ - if (cpus_updated || force_rebuild) { - force_rebuild = false; - rebuild_sched_domains(); + if (cpus_updated) { + if (use_cpu_hp_lock) + rebuild_sched_domains(); + else { + /* Acquiring cpu_hotplug_lock is not required. + * When cpuset_hotplug() is called in hotplug path, + * cpu_hotplug_lock is held by the hotplug context + * which is waiting for cpuhp_thread_fun to indicate + * completion of callback. + */ + mutex_lock(&cpuset_mutex); + rebuild_sched_domains_cpuslocked(); + mutex_unlock(&cpuset_mutex); + } } } -void cpuset_update_active_cpus(void) +static void cpuset_hotplug_workfn(struct work_struct *work) { - /* - * We're inside cpu hotplug critical region which usually nests - * inside cgroup synchronization. Bounce actual hotplug processing - * to a work item to avoid reverse locking order. - */ - schedule_work(&cpuset_hotplug_work); + cpuset_hotplug(true); } -void cpuset_wait_for_hotplug(void) +void cpuset_update_active_cpus(void) { - flush_work(&cpuset_hotplug_work); + cpuset_hotplug(false); } /* diff --git a/kernel/power/process.c b/kernel/power/process.c index 7381d49a44db..c326d7235c5f 100644 --- a/kernel/power/process.c +++ b/kernel/power/process.c @@ -204,8 +204,6 @@ void thaw_processes(void) __usermodehelper_set_disable_depth(UMH_FREEZING); thaw_workqueues(); - cpuset_wait_for_hotplug(); - read_lock(&tasklist_lock); for_each_process_thread(g, p) { /* No other threads should have PF_SUSPEND_TASK set */ diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 75554f366fd3..88b3450b29ab 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5624,7 +5624,6 @@ static void cpuset_cpu_active(void) * restore the original sched domains by considering the * cpuset configurations. */ - cpuset_force_rebuild(); } cpuset_update_active_cpus(); } -- GitLab From 7d229c668a114e80d6be62b00e21a73bdd9ba7b3 Mon Sep 17 00:00:00 2001 From: Tal Shorer Date: Fri, 3 Nov 2017 17:27:49 +0200 Subject: [PATCH 0152/2547] main: kernel_start: move housekeeping_init() before workqueue_init_early() This is needed in order to allow the unbound workqueue to take housekeeping cpus into accounty Signed-off-by: Tal Shorer Signed-off-by: Tejun Heo --- init/main.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/init/main.c b/init/main.c index dfec3809e740..e96e3a14533c 100644 --- a/init/main.c +++ b/init/main.c @@ -588,6 +588,12 @@ asmlinkage __visible void __init start_kernel(void) local_irq_disable(); radix_tree_init(); + /* + * Set up housekeeping before setting up workqueues to allow the unbound + * workqueue to take non-housekeeping into account. + */ + housekeeping_init(); + /* * Allow workqueue creation and work item queueing/cancelling * early. Work item execution depends on kthreads and starts after @@ -605,7 +611,6 @@ asmlinkage __visible void __init start_kernel(void) early_irq_init(); init_IRQ(); tick_init(); - housekeeping_init(); rcu_init_nohz(); init_timers(); hrtimers_init(); -- GitLab From c98a9805096460567404799a7bd3149826affde7 Mon Sep 17 00:00:00 2001 From: Tal Shorer Date: Fri, 3 Nov 2017 17:27:50 +0200 Subject: [PATCH 0153/2547] workqueue: respect isolated cpus when queueing an unbound work Initialize wq_unbound_cpumask to exclude cpus that were isolated by the cmdline's isolcpus parameter. Signed-off-by: Tal Shorer Signed-off-by: Tejun Heo --- kernel/workqueue.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/kernel/workqueue.c b/kernel/workqueue.c index 8fdb710bfdd7..6a5658cb46da 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -48,6 +48,7 @@ #include #include #include +#include #include "workqueue_internal.h" @@ -4957,6 +4958,10 @@ int workqueue_set_unbound_cpumask(cpumask_var_t cpumask) if (!zalloc_cpumask_var(&saved_cpumask, GFP_KERNEL)) return -ENOMEM; + /* + * Not excluding isolated cpus on purpose. + * If the user wishes to include them, we allow that. + */ cpumask_and(cpumask, cpumask, cpu_possible_mask); if (!cpumask_empty(cpumask)) { apply_wqattrs_lock(); @@ -5555,7 +5560,7 @@ int __init workqueue_init_early(void) WARN_ON(__alignof__(struct pool_workqueue) < __alignof__(long long)); BUG_ON(!alloc_cpumask_var(&wq_unbound_cpumask, GFP_KERNEL)); - cpumask_copy(wq_unbound_cpumask, cpu_possible_mask); + cpumask_copy(wq_unbound_cpumask, housekeeping_cpumask(HK_FLAG_DOMAIN)); pwq_cache = KMEM_CACHE(pool_workqueue, SLAB_PANIC); -- GitLab From d3b0535216f04e7e149eaebe8e967c46bdf88dc3 Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Fri, 17 Nov 2017 15:09:27 +0000 Subject: [PATCH 0154/2547] ASoC: da7219: Correct IRQ level in DT binding example Current DT binding documentation shows an example where the IRQ for the device is chosen to be ACTIVE_HIGH. This is incorrect as the device only supports ACTIVE_LOW, so this commit fixes that discrepancy. Signed-off-by: Adam Thomson Acked-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/da7219.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/da7219.txt b/Documentation/devicetree/bindings/sound/da7219.txt index cf61681826b6..5b54d2d045c3 100644 --- a/Documentation/devicetree/bindings/sound/da7219.txt +++ b/Documentation/devicetree/bindings/sound/da7219.txt @@ -77,7 +77,7 @@ Example: reg = <0x1a>; interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; VDD-supply = <®_audio>; VDDMIC-supply = <®_audio>; -- GitLab From b7926c464d6479fc62a4297ca4f48a5da5fb0988 Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Fri, 17 Nov 2017 15:09:28 +0000 Subject: [PATCH 0155/2547] ASoC: da7218: Correct IRQ level in DT binding example Current DT binding documentation shows an example where the IRQ for the device is chosen to be ACTIVE_HIGH. This is incorrect as the device only supports ACTIVE_LOW, so this commit fixes that discrepancy. Signed-off-by: Adam Thomson Acked-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/da7218.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/da7218.txt b/Documentation/devicetree/bindings/sound/da7218.txt index 5ca5a709b6aa..3ab9dfef38d1 100644 --- a/Documentation/devicetree/bindings/sound/da7218.txt +++ b/Documentation/devicetree/bindings/sound/da7218.txt @@ -73,7 +73,7 @@ Example: compatible = "dlg,da7218"; reg = <0x1a>; interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; wakeup-source; VDD-supply = <®_audio>; -- GitLab From 77416ab35f5712382e5a792bfa1736ceb70d5bbb Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Nov 2017 10:58:34 -0800 Subject: [PATCH 0156/2547] ARM: dts: NSP: Disable AHCI controller for HR NSP boards The AHCI controller is currently enabled for all of these boards: bcm958623hr and bcm958625hr would result in a hard hang on boot that we cannot get rid of. Since this does not appear to have an easy and simple fix, just disable the AHCI controller for now until this gets resolved. Fixes: 70725d6e97ac ("ARM: dts: NSP: Enable SATA on bcm958625hr") Fixes: d454c3762437 ("ARM: dts: NSP: Add new DT file for bcm958623hr") Acked-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958623hr.dts | 4 ---- arch/arm/boot/dts/bcm958625hr.dts | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index 3bc50849d013..b8bde13de90a 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -141,10 +141,6 @@ status = "okay"; }; -&sata { - status = "okay"; -}; - &qspi { bspi-sel = <0>; flash: m25p80@0 { diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index d94d14b3c745..6a44b8021702 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -177,10 +177,6 @@ status = "okay"; }; -&sata { - status = "okay"; -}; - &srab { compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; status = "okay"; -- GitLab From 5f1aa51c7a1eef1c5a60b8334e32c89904964245 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Nov 2017 11:10:29 -0800 Subject: [PATCH 0157/2547] ARM: dts: NSP: Fix PPI interrupt types Booting a kernel results in the kernel warning us about the following PPI interrupts configuration: [ 0.105127] smp: Bringing up secondary CPUs ... [ 0.110545] GIC: PPI11 is secure or misconfigured [ 0.110551] GIC: PPI13 is secure or misconfigured Fix this by using the appropriate edge configuration for PPI11 and PPI13, this is similar to what was fixed for Northstar (BCM5301X) in commit 0e34079cd1f6 ("ARM: dts: BCM5301X: Correct GIC_PPI interrupt flags"). Fixes: 7b2e987de207 ("ARM: NSP: add minimal Northstar Plus device tree") Fixes: 1a9d53cabaf4 ("ARM: dts: NSP: Add TWD Support to DT") Acked-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 528b9e3bc1da..dcc55aa84583 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -85,7 +85,7 @@ timer@20200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x20200 0x100>; - interrupts = ; + interrupts = ; clocks = <&periph_clk>; }; @@ -93,7 +93,7 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0x20600 0x20>; interrupts = ; + IRQ_TYPE_EDGE_RISING)>; clocks = <&periph_clk>; }; -- GitLab From 16a27dfd218566f9604d5542c6285395cfc6831c Mon Sep 17 00:00:00 2001 From: Albert Pool Date: Mon, 20 Nov 2017 14:20:09 +0100 Subject: [PATCH 0158/2547] ata: mediatek: Fix typo in module description Signed-off-by: Albert Pool Signed-off-by: Tejun Heo --- drivers/ata/ahci_mtk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c index 80854f71559a..489452a64303 100644 --- a/drivers/ata/ahci_mtk.c +++ b/drivers/ata/ahci_mtk.c @@ -1,5 +1,5 @@ /* - * MeidaTek AHCI SATA driver + * MediaTek AHCI SATA driver * * Copyright (c) 2017 MediaTek Inc. * Author: Ryder Lee @@ -192,5 +192,5 @@ static struct platform_driver mtk_ahci_driver = { }; module_platform_driver(mtk_ahci_driver); -MODULE_DESCRIPTION("MeidaTek SATA AHCI Driver"); +MODULE_DESCRIPTION("MediaTek SATA AHCI Driver"); MODULE_LICENSE("GPL v2"); -- GitLab From ddf7005f32212f28669032651e09bd8d2245c35d Mon Sep 17 00:00:00 2001 From: Wang Long Date: Sun, 19 Nov 2017 16:08:37 -0500 Subject: [PATCH 0159/2547] debug cgroup: use task_css_set instead of rcu_dereference This macro `task_css_set` verifies that the caller is inside proper critical section if the kernel set CONFIG_PROVE_RCU=y. Signed-off-by: Wang Long Signed-off-by: Tejun Heo --- kernel/cgroup/debug.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/cgroup/debug.c b/kernel/cgroup/debug.c index 5f780d8f6a9d..9caeda610249 100644 --- a/kernel/cgroup/debug.c +++ b/kernel/cgroup/debug.c @@ -50,7 +50,7 @@ static int current_css_set_read(struct seq_file *seq, void *v) spin_lock_irq(&css_set_lock); rcu_read_lock(); - cset = rcu_dereference(current->cgroups); + cset = task_css_set(current); refcnt = refcount_read(&cset->refcount); seq_printf(seq, "css_set %pK %d", cset, refcnt); if (refcnt > cset->nr_tasks) @@ -96,7 +96,7 @@ static int current_css_set_cg_links_read(struct seq_file *seq, void *v) spin_lock_irq(&css_set_lock); rcu_read_lock(); - cset = rcu_dereference(current->cgroups); + cset = task_css_set(current); list_for_each_entry(link, &cset->cgrp_links, cgrp_link) { struct cgroup *c = link->cgrp; -- GitLab From c1da86c19ad6bfb77ceef3414c82269e8466f410 Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Sat, 25 Nov 2017 15:49:49 +0530 Subject: [PATCH 0160/2547] pata_pdc2027x: Remove unnecessary error check Here, The function pdc_hardware_init always return zero. So it is not necessary to check its return value. Signed-off-by: Arvind Yadav Signed-off-by: Tejun Heo --- drivers/ata/pata_pdc2027x.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c index ffd8d33c6e0f..4a9d532bdbb8 100644 --- a/drivers/ata/pata_pdc2027x.c +++ b/drivers/ata/pata_pdc2027x.c @@ -649,7 +649,7 @@ static long pdc_detect_pll_input_clock(struct ata_host *host) * @host: target ATA host * @board_idx: board identifier */ -static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx) +static void pdc_hardware_init(struct ata_host *host, unsigned int board_idx) { long pll_clock; @@ -665,8 +665,6 @@ static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx) /* Adjust PLL control register */ pdc_adjust_pll(host, pll_clock, board_idx); - - return 0; } /** @@ -753,8 +751,7 @@ static int pdc2027x_init_one(struct pci_dev *pdev, //pci_enable_intx(pdev); /* initialize adapter */ - if (pdc_hardware_init(host, board_idx) != 0) - return -EIO; + pdc_hardware_init(host, board_idx); pci_set_master(pdev); return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, @@ -778,8 +775,7 @@ static int pdc2027x_reinit_one(struct pci_dev *pdev) else board_idx = PDC_UDMA_133; - if (pdc_hardware_init(host, board_idx)) - return -EIO; + pdc_hardware_init(host, board_idx); ata_host_resume(host); return 0; -- GitLab From 20f9ceed72f127e4cc44c0358160e6e0118f823d Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Sat, 25 Nov 2017 16:47:35 +0530 Subject: [PATCH 0161/2547] pata_pdc2027x : make pdc2027x_*_timing structures const Make these pdc2027x_*_timing structures const as it is never modified. Signed-off-by: Arvind Yadav Signed-off-by: Tejun Heo --- drivers/ata/pata_pdc2027x.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c index 4a9d532bdbb8..6db2e34bd52f 100644 --- a/drivers/ata/pata_pdc2027x.c +++ b/drivers/ata/pata_pdc2027x.c @@ -82,7 +82,7 @@ static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed * is issued to the device. However, if the controller clock is 133MHz, * the following tables must be used. */ -static struct pdc2027x_pio_timing { +static const struct pdc2027x_pio_timing { u8 value0, value1, value2; } pdc2027x_pio_timing_tbl[] = { { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */ @@ -92,7 +92,7 @@ static struct pdc2027x_pio_timing { { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ }; -static struct pdc2027x_mdma_timing { +static const struct pdc2027x_mdma_timing { u8 value0, value1; } pdc2027x_mdma_timing_tbl[] = { { 0xdf, 0x5f }, /* MDMA mode 0 */ @@ -100,7 +100,7 @@ static struct pdc2027x_mdma_timing { { 0x69, 0x25 }, /* MDMA mode 2 */ }; -static struct pdc2027x_udma_timing { +static const struct pdc2027x_udma_timing { u8 value0, value1, value2; } pdc2027x_udma_timing_tbl[] = { { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ -- GitLab From 04226916d2360f56d57ad00bc48d2d1854d1e0b0 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 16 Apr 2017 02:51:16 -0400 Subject: [PATCH 0162/2547] media: usbtv: add a new usbid A new usbid of UTV007 is found in a newly bought device. The usbid is 1f71:3301. The ID on the chip is: UTV007 A89029.1 1520L18K1 Both video and audio is tested with the modified usbtv driver. Signed-off-by: Icenowy Zheng Acked-by: Lubomir Rintel Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/usbtv/usbtv-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/usb/usbtv/usbtv-core.c b/drivers/media/usb/usbtv/usbtv-core.c index b55b79b8e921..127f8a0c098b 100644 --- a/drivers/media/usb/usbtv/usbtv-core.c +++ b/drivers/media/usb/usbtv/usbtv-core.c @@ -144,6 +144,7 @@ static void usbtv_disconnect(struct usb_interface *intf) static const struct usb_device_id usbtv_id_table[] = { { USB_DEVICE(0x1b71, 0x3002) }, + { USB_DEVICE(0x1f71, 0x3301) }, {} }; MODULE_DEVICE_TABLE(usb, usbtv_id_table); -- GitLab From abee210500ed15a22787009d9210b9a34911afcc Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Mon, 27 Nov 2017 15:51:04 -0500 Subject: [PATCH 0163/2547] percpu: hack to let the CRIS architecture to boot until they clean up Commit 438a506180 ("percpu: don't forget to free the temporary struct pcpu_alloc_info") uncovered a problem on the CRIS architecture where the bootmem allocator is initialized with virtual addresses. Given it has: #define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) then things just work out because the end result is the same whether you give this a physical or a virtual address. Untill you call memblock_free_early(__pa(address)) that is, because values from __pa() don't match with the virtual addresses stuffed in the bootmem allocator anymore. Avoid freeing the temporary pcpu_alloc_info memory on that architecture until they fix things up to let the kernel boot like it did before. Signed-off-by: Nicolas Pitre Signed-off-by: Tejun Heo Fixes: 438a506180 ("percpu: don't forget to free the temporary struct pcpu_alloc_info") --- mm/percpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/mm/percpu.c b/mm/percpu.c index 79e3549cab0f..50e7fdf84055 100644 --- a/mm/percpu.c +++ b/mm/percpu.c @@ -2719,7 +2719,11 @@ void __init setup_per_cpu_areas(void) if (pcpu_setup_first_chunk(ai, fc) < 0) panic("Failed to initialize percpu areas."); +#ifdef CONFIG_CRIS +#warning "the CRIS architecture has physical and virtual addresses confused" +#else pcpu_free_alloc_info(ai); +#endif } #endif /* CONFIG_SMP */ -- GitLab From a39e17b2d842938e19997d2fdc0443fdd4cd8d10 Mon Sep 17 00:00:00 2001 From: Jakub Kicinski Date: Mon, 27 Nov 2017 12:10:23 -0800 Subject: [PATCH 0164/2547] bpf: offload: add a license header I forgot to add a license on kernel/bpf/offload.c. Luckily I'm still the only author so make it explicitly GPLv2. Signed-off-by: Jakub Kicinski Reviewed-by: Simon Horman Signed-off-by: Daniel Borkmann --- kernel/bpf/offload.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/kernel/bpf/offload.c b/kernel/bpf/offload.c index 68ec884440b7..8455b89d1bbf 100644 --- a/kernel/bpf/offload.c +++ b/kernel/bpf/offload.c @@ -1,3 +1,18 @@ +/* + * Copyright (C) 2017 Netronome Systems, Inc. + * + * This software is licensed under the GNU General License Version 2, + * June 1991 as shown in the file COPYING in the top-level directory of this + * source tree. + * + * THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" + * WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, + * BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE + * OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME + * THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + */ + #include #include #include -- GitLab From 42b3a4cb5609de757f5445fcad18945ba9239a07 Mon Sep 17 00:00:00 2001 From: Juergen Gross Date: Fri, 24 Nov 2017 09:42:21 +0100 Subject: [PATCH 0165/2547] x86/xen: Support early interrupts in xen pv guests Add early interrupt handlers activated by idt_setup_early_handler() to the handlers supported by Xen pv guests. This will allow for early WARN() calls not crashing the guest. Suggested-by: Andy Lutomirski Signed-off-by: Juergen Gross Signed-off-by: Thomas Gleixner Cc: xen-devel@lists.xenproject.org Cc: boris.ostrovsky@oracle.com Link: https://lkml.kernel.org/r/20171124084221.30172-1-jgross@suse.com --- arch/x86/include/asm/segment.h | 12 +++++++++++ arch/x86/mm/extable.c | 4 +++- arch/x86/xen/enlighten_pv.c | 37 ++++++++++++++++++++++------------ arch/x86/xen/xen-asm_64.S | 14 +++++++++++++ 4 files changed, 53 insertions(+), 14 deletions(-) diff --git a/arch/x86/include/asm/segment.h b/arch/x86/include/asm/segment.h index b20f9d623f9c..8f09012b92e7 100644 --- a/arch/x86/include/asm/segment.h +++ b/arch/x86/include/asm/segment.h @@ -236,11 +236,23 @@ */ #define EARLY_IDT_HANDLER_SIZE 9 +/* + * xen_early_idt_handler_array is for Xen pv guests: for each entry in + * early_idt_handler_array it contains a prequel in the form of + * pop %rcx; pop %r11; jmp early_idt_handler_array[i]; summing up to + * max 8 bytes. + */ +#define XEN_EARLY_IDT_HANDLER_SIZE 8 + #ifndef __ASSEMBLY__ extern const char early_idt_handler_array[NUM_EXCEPTION_VECTORS][EARLY_IDT_HANDLER_SIZE]; extern void early_ignore_irq(void); +#if defined(CONFIG_X86_64) && defined(CONFIG_XEN_PV) +extern const char xen_early_idt_handler_array[NUM_EXCEPTION_VECTORS][XEN_EARLY_IDT_HANDLER_SIZE]; +#endif + /* * Load a segment. Fall back on loading the zero segment if something goes * wrong. This variant assumes that loading zero fully clears the segment. diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index 3321b446b66c..88754bfd425f 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -1,6 +1,7 @@ #include #include #include +#include #include #include @@ -212,8 +213,9 @@ void __init early_fixup_exception(struct pt_regs *regs, int trapnr) * Old CPUs leave the high bits of CS on the stack * undefined. I'm not sure which CPUs do this, but at least * the 486 DX works this way. + * Xen pv domains are not using the default __KERNEL_CS. */ - if (regs->cs != __KERNEL_CS) + if (!xen_pv_domain() && regs->cs != __KERNEL_CS) goto fail; /* diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 5b2b3f3f6531..f2414c6c5e7c 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -622,7 +622,7 @@ static struct trap_array_entry trap_array[] = { { simd_coprocessor_error, xen_simd_coprocessor_error, false }, }; -static bool get_trap_addr(void **addr, unsigned int ist) +static bool __ref get_trap_addr(void **addr, unsigned int ist) { unsigned int nr; bool ist_okay = false; @@ -644,6 +644,14 @@ static bool get_trap_addr(void **addr, unsigned int ist) } } + if (nr == ARRAY_SIZE(trap_array) && + *addr >= (void *)early_idt_handler_array[0] && + *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) { + nr = (*addr - (void *)early_idt_handler_array[0]) / + EARLY_IDT_HANDLER_SIZE; + *addr = (void *)xen_early_idt_handler_array[nr]; + } + if (WARN_ON(ist != 0 && !ist_okay)) return false; @@ -1262,6 +1270,21 @@ asmlinkage __visible void __init xen_start_kernel(void) xen_setup_gdt(0); xen_init_irq_ops(); + + /* Let's presume PV guests always boot on vCPU with id 0. */ + per_cpu(xen_vcpu_id, 0) = 0; + + /* + * Setup xen_vcpu early because idt_setup_early_handler needs it for + * local_irq_disable(), irqs_disabled(). + * + * Don't do the full vcpu_info placement stuff until we have + * the cpu_possible_mask and a non-dummy shared_info. + */ + xen_vcpu_info_reset(0); + + idt_setup_early_handler(); + xen_init_capabilities(); #ifdef CONFIG_X86_LOCAL_APIC @@ -1295,18 +1318,6 @@ asmlinkage __visible void __init xen_start_kernel(void) */ acpi_numa = -1; #endif - /* Let's presume PV guests always boot on vCPU with id 0. */ - per_cpu(xen_vcpu_id, 0) = 0; - - /* - * Setup xen_vcpu early because start_kernel needs it for - * local_irq_disable(), irqs_disabled(). - * - * Don't do the full vcpu_info placement stuff until we have - * the cpu_possible_mask and a non-dummy shared_info. - */ - xen_vcpu_info_reset(0); - WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv)); local_irq_disable(); diff --git a/arch/x86/xen/xen-asm_64.S b/arch/x86/xen/xen-asm_64.S index 8a10c9a9e2b5..417b339e5c8e 100644 --- a/arch/x86/xen/xen-asm_64.S +++ b/arch/x86/xen/xen-asm_64.S @@ -15,6 +15,7 @@ #include +#include #include .macro xen_pv_trap name @@ -54,6 +55,19 @@ xen_pv_trap entry_INT80_compat #endif xen_pv_trap hypervisor_callback + __INIT +ENTRY(xen_early_idt_handler_array) + i = 0 + .rept NUM_EXCEPTION_VECTORS + pop %rcx + pop %r11 + jmp early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE + i = i + 1 + .fill xen_early_idt_handler_array + i*XEN_EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc + .endr +END(xen_early_idt_handler_array) + __FINIT + hypercall_iret = hypercall_page + __HYPERVISOR_iret * 32 /* * Xen64 iret frame: -- GitLab From a9efcc19161e20623c285fac967a32842972cebe Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 27 Nov 2017 18:29:43 -0500 Subject: [PATCH 0166/2547] drm/amdgpu: fix get_max_engine_clock_in_mhz Use proper powerplay function. This fixes OpenCL initialization problems. Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 896b16db58aa..01aa851938f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -298,6 +298,9 @@ uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd) { struct amdgpu_device *adev = (struct amdgpu_device *)kgd; - /* The sclk is in quantas of 10kHz */ - return adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100; + /* the sclk is in quantas of 10kHz */ + if (amdgpu_sriov_vf(adev)) + return adev->clock.default_sclk / 100; + + return amdgpu_dpm_get_sclk(adev, false) / 100; } -- GitLab From 3c0b42809071cb6d779b9c4a573edd5d12654f43 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Mon, 27 Nov 2017 18:29:44 -0500 Subject: [PATCH 0167/2547] drm/amdkfd: Add crash protection in debugger register path After debugger is registered, the pqm_destroy_queue fails because is_debug is true, the queue should not be removed from process_queue_list since the count is not reduced. Test application calls debugger unregister without register debugger, add null pointer check protection to avoid crash for this case Signed-off-by: Philip Yang Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index cc61ec289880..62c3d9cd6ef1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -526,7 +526,7 @@ static int kfd_ioctl_dbg_unregister(struct file *filep, long status; dev = kfd_device_by_id(args->gpu_id); - if (!dev) + if (!dev || !dev->dbgmgr) return -EINVAL; if (dev->device_info->asic_family == CHIP_CARRIZO) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index fbfa2741e2a7..991b3bf1e8bc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -311,6 +311,10 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) if (pqn->q) { dqm = pqn->q->device->dqm; retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); + if (retval) { + pr_debug("Destroy queue failed, returned %d\n", retval); + goto err_destroy_queue; + } uninit_queue(pqn->q); } @@ -322,6 +326,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) list_empty(&pdd->qpd.priv_queue_list)) dqm->ops.unregister_process(dqm, &pdd->qpd); +err_destroy_queue: return retval; } -- GitLab From 8f8fb9b9d05c44e452ebefac5f01f8f32ffe306c Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Mon, 4 Dec 2017 06:50:17 -0500 Subject: [PATCH 0168/2547] drm/amdkfd: Fix printing pointer cast Just print a pointer instead of casting v2: Remove the 0x prefix, since %p prints that automatically, and remove it from one other spot as well Signed-off-by: Kent Russell Reviewed-by: Felix Kuehling Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index feb76c235b1a..ebb4da14e3df 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -116,8 +116,7 @@ int kfd_doorbell_init(struct kfd_dev *kfd) pr_debug("doorbell aperture size == 0x%08lX\n", kfd->shared_resources.doorbell_aperture_size); - pr_debug("doorbell kernel address == 0x%08lX\n", - (uintptr_t)kfd->doorbell_kernel_ptr); + pr_debug("doorbell kernel address == %p\n", kfd->doorbell_kernel_ptr); return 0; } @@ -194,8 +193,8 @@ u32 __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, pr_debug("Get kernel queue doorbell\n" " doorbell offset == 0x%08X\n" - " kernel address == 0x%08lX\n", - *doorbell_off, (uintptr_t)(kfd->doorbell_kernel_ptr + inx)); + " kernel address == %p\n", + *doorbell_off, (kfd->doorbell_kernel_ptr + inx)); return kfd->doorbell_kernel_ptr + inx; } @@ -215,7 +214,7 @@ inline void write_kernel_doorbell(u32 __iomem *db, u32 value) { if (db) { writel(value, db); - pr_debug("Writing %d to doorbell address 0x%p\n", value, db); + pr_debug("Writing %d to doorbell address %p\n", value, db); } } -- GitLab From a99c6d4fdc0470c3137d834d578441d057a5ebd0 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 27 Nov 2017 18:29:45 -0500 Subject: [PATCH 0169/2547] drm/amdkfd: map multiple processes to HW scheduler Allow HWS to to execute multiple processes on the hardware concurrently. The number of concurrent processes is limited by the number of VMIDs allocated to the HWS. A module parameter can be used for limiting this further or turn it off altogether (mainly for debugging purposes). Signed-off-by: Yong Zhao Signed-off-by: Jay Cornwall Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 11 +++++++ drivers/gpu/drm/amd/amdkfd/kfd_module.c | 5 ++++ .../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 30 +++++++++++++++++-- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 ++++++ 4 files changed, 53 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 4f05eacca786..a8fa33a08de3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -238,6 +238,17 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd - kfd->vm_info.first_vmid_kfd + 1; + /* Verify module parameters regarding mapped process number*/ + if ((hws_max_conc_proc < 0) + || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { + dev_err(kfd_device, + "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", + hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, + kfd->vm_info.vmid_num_kfd); + kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; + } else + kfd->max_proc_per_quantum = hws_max_conc_proc; + /* calculate max size of mqds needed for queues */ size = max_num_of_queues_per_device * kfd->device_info->mqd_size_aligned; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index ee8adf654cd0..4e060c864c21 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -50,6 +50,11 @@ module_param(sched_policy, int, 0444); MODULE_PARM_DESC(sched_policy, "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); +int hws_max_conc_proc = 8; +module_param(hws_max_conc_proc, int, 0444); +MODULE_PARM_DESC(hws_max_conc_proc, + "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); + int cwsr_enable = 1; module_param(cwsr_enable, int, 0444); MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index 69c147a83591..0b7092e59bf9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -57,13 +57,24 @@ static void pm_calc_rlib_size(struct packet_manager *pm, { unsigned int process_count, queue_count; unsigned int map_queue_size; + unsigned int max_proc_per_quantum = 1; + struct kfd_dev *dev = pm->dqm->dev; process_count = pm->dqm->processes_count; queue_count = pm->dqm->queue_count; - /* check if there is over subscription*/ + /* check if there is over subscription + * Note: the arbitration between the number of VMIDs and + * hws_max_conc_proc has been done in + * kgd2kfd_device_init(). + */ *over_subscription = false; - if ((process_count > 1) || queue_count > get_queues_num(pm->dqm)) { + + if (dev->max_proc_per_quantum > 1) + max_proc_per_quantum = dev->max_proc_per_quantum; + + if ((process_count > max_proc_per_quantum) || + queue_count > get_queues_num(pm->dqm)) { *over_subscription = true; pr_debug("Over subscribed runlist\n"); } @@ -116,10 +127,24 @@ static int pm_create_runlist(struct packet_manager *pm, uint32_t *buffer, uint64_t ib, size_t ib_size_in_dwords, bool chain) { struct pm4_mes_runlist *packet; + int concurrent_proc_cnt = 0; + struct kfd_dev *kfd = pm->dqm->dev; if (WARN_ON(!ib)) return -EFAULT; + /* Determine the number of processes to map together to HW: + * it can not exceed the number of VMIDs available to the + * scheduler, and it is determined by the smaller of the number + * of processes in the runlist and kfd module parameter + * hws_max_conc_proc. + * Note: the arbitration between the number of VMIDs and + * hws_max_conc_proc has been done in + * kgd2kfd_device_init(). + */ + concurrent_proc_cnt = min(pm->dqm->processes_count, + kfd->max_proc_per_quantum); + packet = (struct pm4_mes_runlist *)buffer; memset(buffer, 0, sizeof(struct pm4_mes_runlist)); @@ -130,6 +155,7 @@ static int pm_create_runlist(struct packet_manager *pm, uint32_t *buffer, packet->bitfields4.chain = chain ? 1 : 0; packet->bitfields4.offload_polling = 0; packet->bitfields4.valid = 1; + packet->bitfields4.process_cnt = concurrent_proc_cnt; packet->ordinal2 = lower_32_bits(ib); packet->bitfields3.ib_base_hi = upper_32_bits(ib); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index a66876467995..1edab2199f0b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -88,6 +88,12 @@ extern int max_num_of_queues_per_device; /* Kernel module parameter to specify the scheduling policy */ extern int sched_policy; +/* + * Kernel module parameter to specify the maximum process + * number per HW scheduler + */ +extern int hws_max_conc_proc; + extern int cwsr_enable; /* @@ -214,6 +220,9 @@ struct kfd_dev { /* Debug manager */ struct kfd_dbgmgr *dbgmgr; + /* Maximum process number mapped to HW scheduler */ + unsigned int max_proc_per_quantum; + /* CWSR */ bool cwsr_enabled; const void *cwsr_isa; -- GitLab From 36582fa5165bca6cfab33bbe1d95f1598ab5fb7d Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 27 Nov 2017 18:29:46 -0500 Subject: [PATCH 0170/2547] drm/amdkfd: Fix oversubscription accounting Don't count SDMA queues towards compute HQD oversubscription when deciding whether to create a chained runlist. Signed-off-by: Jay Cornwall Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index 0b7092e59bf9..c3230b96241e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -55,13 +55,14 @@ static void pm_calc_rlib_size(struct packet_manager *pm, unsigned int *rlib_size, bool *over_subscription) { - unsigned int process_count, queue_count; + unsigned int process_count, queue_count, compute_queue_count; unsigned int map_queue_size; unsigned int max_proc_per_quantum = 1; struct kfd_dev *dev = pm->dqm->dev; process_count = pm->dqm->processes_count; queue_count = pm->dqm->queue_count; + compute_queue_count = queue_count - pm->dqm->sdma_queue_count; /* check if there is over subscription * Note: the arbitration between the number of VMIDs and @@ -74,7 +75,7 @@ static void pm_calc_rlib_size(struct packet_manager *pm, max_proc_per_quantum = dev->max_proc_per_quantum; if ((process_count > max_proc_per_quantum) || - queue_count > get_queues_num(pm->dqm)) { + compute_queue_count > get_queues_num(pm->dqm)) { *over_subscription = true; pr_debug("Over subscribed runlist\n"); } -- GitLab From fdcba29c5d9cfc67ba3ff6135d392ea91b6bd61a Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 27 Nov 2017 18:29:47 -0500 Subject: [PATCH 0171/2547] drm/amdgpu: Fix definition of KFD_CIK_SDMA_QUEUE_OFFSET This counts the queue offset in register index, not register address. Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdgpu/cikd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h index 6a9e38a3d2a0..cee6e8a3ad9c 100644 --- a/drivers/gpu/drm/amd/amdgpu/cikd.h +++ b/drivers/gpu/drm/amd/amdgpu/cikd.h @@ -562,7 +562,7 @@ #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ #define SHARED_BASE(x) ((x) << 16) /* LDS */ -#define KFD_CIK_SDMA_QUEUE_OFFSET 0x200 +#define KFD_CIK_SDMA_QUEUE_OFFSET (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL) /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ enum { -- GitLab From 80c195f5c2bd4da139f913b4debc5b75173f6fca Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 27 Nov 2017 18:29:48 -0500 Subject: [PATCH 0172/2547] drm/amdgpu: Add kfd2kgd APIs for dumping HQDs This can be used by KFD for debugging features, such as dumping HQDs in debugfs. Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 71 ++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 80 +++++++++++++++++++ .../gpu/drm/amd/include/kgd_kfd_interface.h | 14 ++++ 3 files changed, 165 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index 14333af92ed9..12feba8091df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c @@ -105,8 +105,14 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm); +static int kgd_hqd_dump(struct kgd_dev *kgd, + uint32_t pipe_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs); static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, uint32_t __user *wptr, struct mm_struct *mm); +static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, + uint32_t engine_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs); static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); @@ -178,6 +184,8 @@ static const struct kfd2kgd_calls kfd2kgd = { .init_interrupts = kgd_init_interrupts, .hqd_load = kgd_hqd_load, .hqd_sdma_load = kgd_hqd_sdma_load, + .hqd_dump = kgd_hqd_dump, + .hqd_sdma_dump = kgd_hqd_sdma_dump, .hqd_is_occupied = kgd_hqd_is_occupied, .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, .hqd_destroy = kgd_hqd_destroy, @@ -376,6 +384,42 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, return 0; } +static int kgd_hqd_dump(struct kgd_dev *kgd, + uint32_t pipe_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs) +{ + struct amdgpu_device *adev = get_amdgpu_device(kgd); + uint32_t i = 0, reg; +#define HQD_N_REGS (35+4) +#define DUMP_REG(addr) do { \ + if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ + break; \ + (*dump)[i][0] = (addr) << 2; \ + (*dump)[i++][1] = RREG32(addr); \ + } while (0) + + *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + if (*dump == NULL) + return -ENOMEM; + + acquire_queue(kgd, pipe_id, queue_id); + + DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0); + DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1); + DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2); + DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3); + + for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) + DUMP_REG(reg); + + release_queue(kgd); + + WARN_ON_ONCE(i != HQD_N_REGS); + *n_regs = i; + + return 0; +} + static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) { @@ -440,6 +484,33 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, return 0; } +static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, + uint32_t engine_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs) +{ + struct amdgpu_device *adev = get_amdgpu_device(kgd); + uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + + queue_id * KFD_CIK_SDMA_QUEUE_OFFSET; + uint32_t i = 0, reg; +#undef HQD_N_REGS +#define HQD_N_REGS (19+4) + + *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + if (*dump == NULL) + return -ENOMEM; + + for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) + DUMP_REG(sdma_offset + reg); + for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK; + reg++) + DUMP_REG(sdma_offset + reg); + + WARN_ON_ONCE(i != HQD_N_REGS); + *n_regs = i; + + return 0; +} + static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index 1d989e4915b1..b38049569264 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -64,8 +64,14 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm); +static int kgd_hqd_dump(struct kgd_dev *kgd, + uint32_t pipe_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs); static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, uint32_t __user *wptr, struct mm_struct *mm); +static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, + uint32_t engine_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs); static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); @@ -137,6 +143,8 @@ static const struct kfd2kgd_calls kfd2kgd = { .init_interrupts = kgd_init_interrupts, .hqd_load = kgd_hqd_load, .hqd_sdma_load = kgd_hqd_sdma_load, + .hqd_dump = kgd_hqd_dump, + .hqd_sdma_dump = kgd_hqd_sdma_dump, .hqd_is_occupied = kgd_hqd_is_occupied, .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, .hqd_destroy = kgd_hqd_destroy, @@ -365,6 +373,42 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, return 0; } +static int kgd_hqd_dump(struct kgd_dev *kgd, + uint32_t pipe_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs) +{ + struct amdgpu_device *adev = get_amdgpu_device(kgd); + uint32_t i = 0, reg; +#define HQD_N_REGS (54+4) +#define DUMP_REG(addr) do { \ + if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ + break; \ + (*dump)[i][0] = (addr) << 2; \ + (*dump)[i++][1] = RREG32(addr); \ + } while (0) + + *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + if (*dump == NULL) + return -ENOMEM; + + acquire_queue(kgd, pipe_id, queue_id); + + DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0); + DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1); + DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2); + DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3); + + for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++) + DUMP_REG(reg); + + release_queue(kgd); + + WARN_ON_ONCE(i != HQD_N_REGS); + *n_regs = i; + + return 0; +} + static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) { @@ -428,6 +472,42 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, return 0; } +static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, + uint32_t engine_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs) +{ + struct amdgpu_device *adev = get_amdgpu_device(kgd); + uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + + queue_id * KFD_VI_SDMA_QUEUE_OFFSET; + uint32_t i = 0, reg; +#undef HQD_N_REGS +#define HQD_N_REGS (19+4+2+3+7) + + *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + if (*dump == NULL) + return -ENOMEM; + + for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) + DUMP_REG(sdma_offset + reg); + for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK; + reg++) + DUMP_REG(sdma_offset + reg); + for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; + reg++) + DUMP_REG(sdma_offset + reg); + for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG; + reg++) + DUMP_REG(sdma_offset + reg); + for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL; + reg++) + DUMP_REG(sdma_offset + reg); + + WARN_ON_ONCE(i != HQD_N_REGS); + *n_regs = i; + + return 0; +} + static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id) { diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index c6d4e64531c7..fe3079a33a3d 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -131,6 +131,12 @@ struct tile_config { * @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot. * used only for no HWS mode. * + * @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs. + * Array is allocated with kmalloc, needs to be freed with kfree by caller. + * + * @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs. + * Array is allocated with kmalloc, needs to be freed with kfree by caller. + * * @hqd_is_occupies: Checks if a hqd slot is occupied. * * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot. @@ -187,6 +193,14 @@ struct kfd2kgd_calls { int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd, uint32_t __user *wptr, struct mm_struct *mm); + int (*hqd_dump)(struct kgd_dev *kgd, + uint32_t pipe_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs); + + int (*hqd_sdma_dump)(struct kgd_dev *kgd, + uint32_t engine_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs); + bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); -- GitLab From 851a645efd0fee7f27819ab30f3b353bace3cd98 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 27 Nov 2017 18:29:49 -0500 Subject: [PATCH 0173/2547] drm/amdkfd: Add debugfs support to KFD This commit adds several debugfs entries for kfd: kfd/hqds: dumps all HQDs on all GPUs for KFD-controlled compute and SDMA RLC queues kfd/mqds: dumps all MQDs of all KFD processes on all GPUs kfd/rls: dumps HWS runlists on all GPUs Signed-off-by: Yong Zhao Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/Makefile | 2 + drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c | 75 +++++++++++++++++++ .../drm/amd/amdkfd/kfd_device_queue_manager.c | 71 ++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_module.c | 3 + drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h | 4 + .../gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 27 +++++++ .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 25 +++++++ .../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 24 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 21 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 29 +++++++ .../amd/amdkfd/kfd_process_queue_manager.c | 63 ++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 55 ++++++++++++++ 12 files changed, 399 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 342c2d937b17..67e2c42a5e65 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -37,4 +37,6 @@ amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \ kfd_interrupt.o kfd_events.o cik_event_interrupt.o \ kfd_dbgdev.o kfd_dbgmgr.o +amdkfd-$(CONFIG_DEBUG_FS) += kfd_debugfs.o + obj-$(CONFIG_HSA_AMD) += amdkfd.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c b/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c new file mode 100644 index 000000000000..4bd6ebfaf425 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c @@ -0,0 +1,75 @@ +/* + * Copyright 2016-2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "kfd_priv.h" + +static struct dentry *debugfs_root; + +static int kfd_debugfs_open(struct inode *inode, struct file *file) +{ + int (*show)(struct seq_file *, void *) = inode->i_private; + + return single_open(file, show, NULL); +} + +static const struct file_operations kfd_debugfs_fops = { + .owner = THIS_MODULE, + .open = kfd_debugfs_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +void kfd_debugfs_init(void) +{ + struct dentry *ent; + + debugfs_root = debugfs_create_dir("kfd", NULL); + if (!debugfs_root || debugfs_root == ERR_PTR(-ENODEV)) { + pr_warn("Failed to create kfd debugfs dir\n"); + return; + } + + ent = debugfs_create_file("mqds", S_IFREG | 0444, debugfs_root, + kfd_debugfs_mqds_by_process, + &kfd_debugfs_fops); + if (!ent) + pr_warn("Failed to create mqds in kfd debugfs\n"); + + ent = debugfs_create_file("hqds", S_IFREG | 0444, debugfs_root, + kfd_debugfs_hqds_by_device, + &kfd_debugfs_fops); + if (!ent) + pr_warn("Failed to create hqds in kfd debugfs\n"); + + ent = debugfs_create_file("rls", S_IFREG | 0444, debugfs_root, + kfd_debugfs_rls_by_device, + &kfd_debugfs_fops); + if (!ent) + pr_warn("Failed to create rls in kfd debugfs\n"); +} + +void kfd_debugfs_fini(void) +{ + debugfs_remove_recursive(debugfs_root); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 81ec7bb89b04..d0693fd8cbf8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1311,3 +1311,74 @@ void device_queue_manager_uninit(struct device_queue_manager *dqm) dqm->ops.uninitialize(dqm); kfree(dqm); } + +#if defined(CONFIG_DEBUG_FS) + +static void seq_reg_dump(struct seq_file *m, + uint32_t (*dump)[2], uint32_t n_regs) +{ + uint32_t i, count; + + for (i = 0, count = 0; i < n_regs; i++) { + if (count == 0 || + dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) { + seq_printf(m, "%s %08x: %08x", + i ? "\n" : "", + dump[i][0], dump[i][1]); + count = 7; + } else { + seq_printf(m, " %08x", dump[i][1]); + count--; + } + } + + seq_puts(m, "\n"); +} + +int dqm_debugfs_hqds(struct seq_file *m, void *data) +{ + struct device_queue_manager *dqm = data; + uint32_t (*dump)[2], n_regs; + int pipe, queue; + int r = 0; + + for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { + int pipe_offset = pipe * get_queues_per_pipe(dqm); + + for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) { + if (!test_bit(pipe_offset + queue, + dqm->dev->shared_resources.queue_bitmap)) + continue; + + r = dqm->dev->kfd2kgd->hqd_dump( + dqm->dev->kgd, pipe, queue, &dump, &n_regs); + if (r) + break; + + seq_printf(m, " CP Pipe %d, Queue %d\n", + pipe, queue); + seq_reg_dump(m, dump, n_regs); + + kfree(dump); + } + } + + for (pipe = 0; pipe < CIK_SDMA_ENGINE_NUM; pipe++) { + for (queue = 0; queue < CIK_SDMA_QUEUES_PER_ENGINE; queue++) { + r = dqm->dev->kfd2kgd->hqd_sdma_dump( + dqm->dev->kgd, pipe, queue, &dump, &n_regs); + if (r) + break; + + seq_printf(m, " SDMA Engine %d, RLC %d\n", + pipe, queue); + seq_reg_dump(m, dump, n_regs); + + kfree(dump); + } + } + + return r; +} + +#endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index 4e060c864c21..f50e4949a2ed 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -123,6 +123,8 @@ static int __init kfd_module_init(void) kfd_process_create_wq(); + kfd_debugfs_init(); + amdkfd_init_completed = 1; dev_info(kfd_device, "Initialized module\n"); @@ -139,6 +141,7 @@ static void __exit kfd_module_exit(void) { amdkfd_init_completed = 0; + kfd_debugfs_fini(); kfd_process_destroy_wq(); kfd_topology_shutdown(); kfd_chardev_exit(); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h index 1f3a6ba7eed2..8972bcfbf701 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h @@ -85,6 +85,10 @@ struct mqd_manager { uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); +#if defined(CONFIG_DEBUG_FS) + int (*debugfs_show_mqd)(struct seq_file *m, void *data); +#endif + struct mutex mqd_mutex; struct kfd_dev *dev; }; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 7aa57abebbcd..f8ef4a051e08 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -365,6 +365,24 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, return 0; } +#if defined(CONFIG_DEBUG_FS) + +static int debugfs_show_mqd(struct seq_file *m, void *data) +{ + seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, + data, sizeof(struct cik_mqd), false); + return 0; +} + +static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) +{ + seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, + data, sizeof(struct cik_sdma_rlc_registers), false); + return 0; +} + +#endif + struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, struct kfd_dev *dev) @@ -389,6 +407,9 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd; mqd->destroy_mqd = destroy_mqd; mqd->is_occupied = is_occupied; +#if defined(CONFIG_DEBUG_FS) + mqd->debugfs_show_mqd = debugfs_show_mqd; +#endif break; case KFD_MQD_TYPE_HIQ: mqd->init_mqd = init_mqd_hiq; @@ -397,6 +418,9 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = destroy_mqd; mqd->is_occupied = is_occupied; +#if defined(CONFIG_DEBUG_FS) + mqd->debugfs_show_mqd = debugfs_show_mqd; +#endif break; case KFD_MQD_TYPE_SDMA: mqd->init_mqd = init_mqd_sdma; @@ -405,6 +429,9 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = destroy_mqd_sdma; mqd->is_occupied = is_occupied_sdma; +#if defined(CONFIG_DEBUG_FS) + mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; +#endif break; default: kfree(mqd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 00e1f1a9728b..971aec0637dc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -358,7 +358,23 @@ static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); } +#if defined(CONFIG_DEBUG_FS) +static int debugfs_show_mqd(struct seq_file *m, void *data) +{ + seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, + data, sizeof(struct vi_mqd), false); + return 0; +} + +static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) +{ + seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, + data, sizeof(struct vi_sdma_mqd), false); + return 0; +} + +#endif struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, struct kfd_dev *dev) @@ -383,6 +399,9 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd; mqd->destroy_mqd = destroy_mqd; mqd->is_occupied = is_occupied; +#if defined(CONFIG_DEBUG_FS) + mqd->debugfs_show_mqd = debugfs_show_mqd; +#endif break; case KFD_MQD_TYPE_HIQ: mqd->init_mqd = init_mqd_hiq; @@ -391,6 +410,9 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = destroy_mqd; mqd->is_occupied = is_occupied; +#if defined(CONFIG_DEBUG_FS) + mqd->debugfs_show_mqd = debugfs_show_mqd; +#endif break; case KFD_MQD_TYPE_SDMA: mqd->init_mqd = init_mqd_sdma; @@ -399,6 +421,9 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = destroy_mqd_sdma; mqd->is_occupied = is_occupied_sdma; +#if defined(CONFIG_DEBUG_FS) + mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; +#endif break; default: kfree(mqd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index c3230b96241e..0ecbd1f9b606 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -278,6 +278,7 @@ static int pm_create_runlist_ib(struct packet_manager *pm, return retval; *rl_size_bytes = alloc_size_bytes; + pm->ib_size_bytes = alloc_size_bytes; pr_debug("Building runlist ib process count: %d queues count %d\n", pm->dqm->processes_count, pm->dqm->queue_count); @@ -591,3 +592,26 @@ void pm_release_ib(struct packet_manager *pm) } mutex_unlock(&pm->lock); } + +#if defined(CONFIG_DEBUG_FS) + +int pm_debugfs_runlist(struct seq_file *m, void *data) +{ + struct packet_manager *pm = data; + + mutex_lock(&pm->lock); + + if (!pm->allocated) { + seq_puts(m, " No active runlist\n"); + goto out; + } + + seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, + pm->ib_buffer_obj->cpu_ptr, pm->ib_size_bytes, false); + +out: + mutex_unlock(&pm->lock); + return 0; +} + +#endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 1edab2199f0b..dca493b4e17d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -33,6 +33,7 @@ #include #include #include +#include #include #include "amd_shared.h" @@ -735,6 +736,7 @@ struct packet_manager { struct mutex lock; bool allocated; struct kfd_mem_obj *ib_buffer_obj; + unsigned int ib_size_bytes; }; int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm); @@ -781,4 +783,23 @@ int kfd_event_destroy(struct kfd_process *p, uint32_t event_id); int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p); +/* Debugfs */ +#if defined(CONFIG_DEBUG_FS) + +void kfd_debugfs_init(void); +void kfd_debugfs_fini(void); +int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data); +int pqm_debugfs_mqds(struct seq_file *m, void *data); +int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data); +int dqm_debugfs_hqds(struct seq_file *m, void *data); +int kfd_debugfs_rls_by_device(struct seq_file *m, void *data); +int pm_debugfs_runlist(struct seq_file *m, void *data); + +#else + +static inline void kfd_debugfs_init(void) {} +static inline void kfd_debugfs_fini(void) {} + +#endif + #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 39f4c19aaf61..99c18ee65a76 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -620,3 +620,32 @@ int kfd_reserved_mem_mmap(struct kfd_process *process, PFN_DOWN(__pa(qpd->cwsr_kaddr)), KFD_CWSR_TBA_TMA_SIZE, vma->vm_page_prot); } + +#if defined(CONFIG_DEBUG_FS) + +int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data) +{ + struct kfd_process *p; + unsigned int temp; + int r = 0; + + int idx = srcu_read_lock(&kfd_processes_srcu); + + hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { + seq_printf(m, "Process %d PASID %d:\n", + p->lead_thread->tgid, p->pasid); + + mutex_lock(&p->mutex); + r = pqm_debugfs_mqds(m, &p->pqm); + mutex_unlock(&p->mutex); + + if (r) + break; + } + + srcu_read_unlock(&kfd_processes_srcu, idx); + + return r; +} + +#endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 991b3bf1e8bc..876380632668 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -368,4 +368,67 @@ struct kernel_queue *pqm_get_kernel_queue( return NULL; } +#if defined(CONFIG_DEBUG_FS) +int pqm_debugfs_mqds(struct seq_file *m, void *data) +{ + struct process_queue_manager *pqm = data; + struct process_queue_node *pqn; + struct queue *q; + enum KFD_MQD_TYPE mqd_type; + struct mqd_manager *mqd_manager; + int r = 0; + + list_for_each_entry(pqn, &pqm->queues, process_queue_list) { + if (pqn->q) { + q = pqn->q; + switch (q->properties.type) { + case KFD_QUEUE_TYPE_SDMA: + seq_printf(m, " SDMA queue on device %x\n", + q->device->id); + mqd_type = KFD_MQD_TYPE_SDMA; + break; + case KFD_QUEUE_TYPE_COMPUTE: + seq_printf(m, " Compute queue on device %x\n", + q->device->id); + mqd_type = KFD_MQD_TYPE_CP; + break; + default: + seq_printf(m, + " Bad user queue type %d on device %x\n", + q->properties.type, q->device->id); + continue; + } + mqd_manager = q->device->dqm->ops.get_mqd_manager( + q->device->dqm, mqd_type); + } else if (pqn->kq) { + q = pqn->kq->queue; + mqd_manager = pqn->kq->mqd; + switch (q->properties.type) { + case KFD_QUEUE_TYPE_DIQ: + seq_printf(m, " DIQ on device %x\n", + pqn->kq->dev->id); + mqd_type = KFD_MQD_TYPE_HIQ; + break; + default: + seq_printf(m, + " Bad kernel queue type %d on device %x\n", + q->properties.type, + pqn->kq->dev->id); + continue; + } + } else { + seq_printf(m, + " Weird: Queue node with neither kernel nor user queue\n"); + continue; + } + + r = mqd_manager->debugfs_show_mqd(m, q->mqd); + if (r != 0) + break; + } + + return r; +} + +#endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 19ce59028d6b..9d03a56fd9c7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -32,6 +32,7 @@ #include "kfd_priv.h" #include "kfd_crat.h" #include "kfd_topology.h" +#include "kfd_device_queue_manager.h" static struct list_head topology_device_list; static int topology_crat_parsed; @@ -1233,3 +1234,57 @@ struct kfd_dev *kfd_topology_enum_kfd_devices(uint8_t idx) return device; } + +#if defined(CONFIG_DEBUG_FS) + +int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data) +{ + struct kfd_topology_device *dev; + unsigned int i = 0; + int r = 0; + + down_read(&topology_lock); + + list_for_each_entry(dev, &topology_device_list, list) { + if (!dev->gpu) { + i++; + continue; + } + + seq_printf(m, "Node %u, gpu_id %x:\n", i++, dev->gpu->id); + r = dqm_debugfs_hqds(m, dev->gpu->dqm); + if (r) + break; + } + + up_read(&topology_lock); + + return r; +} + +int kfd_debugfs_rls_by_device(struct seq_file *m, void *data) +{ + struct kfd_topology_device *dev; + unsigned int i = 0; + int r = 0; + + down_read(&topology_lock); + + list_for_each_entry(dev, &topology_device_list, list) { + if (!dev->gpu) { + i++; + continue; + } + + seq_printf(m, "Node %u, gpu_id %x:\n", i++, dev->gpu->id); + r = pm_debugfs_runlist(m, &dev->gpu->dqm->packets); + if (r) + break; + } + + up_read(&topology_lock); + + return r; +} + +#endif -- GitLab From c7b1243eef128c49aabdfab71cd4f5ecb6602d97 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 27 Nov 2017 18:29:50 -0500 Subject: [PATCH 0174/2547] drm/amdkfd: Get reference to lead_thread task struct Increment the kfd_process.lead_thread's reference counter to make it safe to dereference. This is needed for getting a safe reference to the process' mm_struct. Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 99c18ee65a76..660d8bcb93e0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -191,6 +192,8 @@ static void kfd_process_wq_release(struct work_struct *work) mutex_destroy(&p->mutex); + put_task_struct(p->lead_thread); + kfree(p); kfree(work); @@ -342,6 +345,7 @@ static struct kfd_process *create_process(const struct task_struct *thread) (uintptr_t)process->mm); process->lead_thread = thread->group_leader; + get_task_struct(process->lead_thread); INIT_LIST_HEAD(&process->per_device_data); -- GitLab From 5ce10687ae5ba2aa06aeaaf3fad9ce64dff45a85 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 27 Nov 2017 18:29:51 -0500 Subject: [PATCH 0175/2547] drm/amdkfd: Make kfd_process reference counted This will be used to elliminate the use of the process lock for preventing concurrent process destruction. This will simplify lock dependencies between KFD and KGD. This also simplifies the process destruction in a few ways: * Don't allocate work struct dynamically * Remove unnecessary hack that increments mm reference counter * Remove unnecessary process locking during destruction Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 58 +++++++++--------------- 2 files changed, 26 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index dca493b4e17d..248e4f510824 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -34,6 +34,7 @@ #include #include #include +#include #include #include "amd_shared.h" @@ -537,6 +538,9 @@ struct kfd_process { */ void *mm; + struct kref ref; + struct work_struct release_work; + struct mutex mutex; /* diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 660d8bcb93e0..e02e8a2e7b28 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -48,11 +48,6 @@ DEFINE_STATIC_SRCU(kfd_processes_srcu); static struct workqueue_struct *kfd_process_wq; -struct kfd_process_release_work { - struct work_struct kfd_work; - struct kfd_process *p; -}; - static struct kfd_process *find_process(const struct task_struct *thread); static struct kfd_process *create_process(const struct task_struct *thread); static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep); @@ -151,21 +146,20 @@ static struct kfd_process *find_process(const struct task_struct *thread) return p; } +/* No process locking is needed in this function, because the process + * is not findable any more. We must assume that no other thread is + * using it any more, otherwise we couldn't safely free the process + * structure in the end. + */ static void kfd_process_wq_release(struct work_struct *work) { - struct kfd_process_release_work *my_work; + struct kfd_process *p = container_of(work, struct kfd_process, + release_work); struct kfd_process_device *pdd, *temp; - struct kfd_process *p; - - my_work = (struct kfd_process_release_work *) work; - - p = my_work->p; pr_debug("Releasing process (pasid %d) in workqueue\n", p->pasid); - mutex_lock(&p->mutex); - list_for_each_entry_safe(pdd, temp, &p->per_device_data, per_device_list) { pr_debug("Releasing pdd (topology id %d) for process (pasid %d) in workqueue\n", @@ -188,33 +182,26 @@ static void kfd_process_wq_release(struct work_struct *work) kfd_pasid_free(p->pasid); kfd_free_process_doorbells(p); - mutex_unlock(&p->mutex); - mutex_destroy(&p->mutex); put_task_struct(p->lead_thread); kfree(p); - - kfree(work); } -static void kfd_process_destroy_delayed(struct rcu_head *rcu) +static void kfd_process_ref_release(struct kref *ref) { - struct kfd_process_release_work *work; - struct kfd_process *p; - - p = container_of(rcu, struct kfd_process, rcu); + struct kfd_process *p = container_of(ref, struct kfd_process, ref); - mmdrop(p->mm); + INIT_WORK(&p->release_work, kfd_process_wq_release); + queue_work(kfd_process_wq, &p->release_work); +} - work = kmalloc(sizeof(struct kfd_process_release_work), GFP_ATOMIC); +static void kfd_process_destroy_delayed(struct rcu_head *rcu) +{ + struct kfd_process *p = container_of(rcu, struct kfd_process, rcu); - if (work) { - INIT_WORK((struct work_struct *) work, kfd_process_wq_release); - work->p = p; - queue_work(kfd_process_wq, (struct work_struct *) work); - } + kref_put(&p->ref, kfd_process_ref_release); } static void kfd_process_notifier_release(struct mmu_notifier *mn, @@ -258,15 +245,12 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, kfd_process_dequeue_from_all_devices(p); pqm_uninit(&p->pqm); + /* Indicate to other users that MM is no longer valid */ + p->mm = NULL; + mutex_unlock(&p->mutex); - /* - * Because we drop mm_count inside kfd_process_destroy_delayed - * and because the mmu_notifier_unregister function also drop - * mm_count we need to take an extra count here. - */ - mmgrab(p->mm); - mmu_notifier_unregister_no_release(&p->mmu_notifier, p->mm); + mmu_notifier_unregister_no_release(&p->mmu_notifier, mm); mmu_notifier_call_srcu(&p->rcu, &kfd_process_destroy_delayed); } @@ -331,6 +315,8 @@ static struct kfd_process *create_process(const struct task_struct *thread) if (kfd_alloc_process_doorbells(process) < 0) goto err_alloc_doorbells; + kref_init(&process->ref); + mutex_init(&process->mutex); process->mm = thread->mm; -- GitLab From abb208a8d490bac9d765c45f20cf306757733778 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 27 Nov 2017 18:29:52 -0500 Subject: [PATCH 0176/2547] drm/amdkfd: Use ref count to prevent kfd_process destruction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use a reference counter instead of a lock to prevent process destruction while functions running out of process context are using the kfd_process structure. In many cases these functions don't need the structure to be locked. In the few cases that really do need the process lock, take it explicitly. This helps simplify lock dependencies between the process lock and other locks, particularly amdgpu and mm_struct locks. This will be important when amdgpu calls back to amdkfd for memory evictions. Signed-off-by: Felix Kuehling Acked-by: Christian König Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 14 +++++++------- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 16 +++++++++++++--- 3 files changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index cb92d4b72400..93aae5c1e78b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -441,7 +441,7 @@ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, /* * Because we are called from arbitrary context (workqueue) as opposed * to process context, kfd_process could attempt to exit while we are - * running so the lookup function returns a locked process. + * running so the lookup function increments the process ref count. */ struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); @@ -493,7 +493,7 @@ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, } mutex_unlock(&p->event_mutex); - mutex_unlock(&p->mutex); + kfd_unref_process(p); } static struct kfd_event_waiter *alloc_event_waiters(uint32_t num_events) @@ -847,7 +847,7 @@ void kfd_signal_iommu_event(struct kfd_dev *dev, unsigned int pasid, /* * Because we are called from arbitrary context (workqueue) as opposed * to process context, kfd_process could attempt to exit while we are - * running so the lookup function returns a locked process. + * running so the lookup function increments the process ref count. */ struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); struct mm_struct *mm; @@ -860,7 +860,7 @@ void kfd_signal_iommu_event(struct kfd_dev *dev, unsigned int pasid, */ mm = get_task_mm(p->lead_thread); if (!mm) { - mutex_unlock(&p->mutex); + kfd_unref_process(p); return; /* Process is exiting */ } @@ -903,7 +903,7 @@ void kfd_signal_iommu_event(struct kfd_dev *dev, unsigned int pasid, &memory_exception_data); mutex_unlock(&p->event_mutex); - mutex_unlock(&p->mutex); + kfd_unref_process(p); } void kfd_signal_hw_exception_event(unsigned int pasid) @@ -911,7 +911,7 @@ void kfd_signal_hw_exception_event(unsigned int pasid) /* * Because we are called from arbitrary context (workqueue) as opposed * to process context, kfd_process could attempt to exit while we are - * running so the lookup function returns a locked process. + * running so the lookup function increments the process ref count. */ struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); @@ -924,5 +924,5 @@ void kfd_signal_hw_exception_event(unsigned int pasid) lookup_events_by_type_and_signal(p, KFD_EVENT_TYPE_HW_EXCEPTION, NULL); mutex_unlock(&p->event_mutex); - mutex_unlock(&p->mutex); + kfd_unref_process(p); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 248e4f510824..0c96a6b3a173 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -606,6 +606,7 @@ void kfd_process_destroy_wq(void); struct kfd_process *kfd_create_process(struct file *filep); struct kfd_process *kfd_get_process(const struct task_struct *); struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid); +void kfd_unref_process(struct kfd_process *p); struct kfd_process_device *kfd_bind_process_to_device(struct kfd_dev *dev, struct kfd_process *p); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index e02e8a2e7b28..509f987f4994 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -49,6 +49,7 @@ DEFINE_STATIC_SRCU(kfd_processes_srcu); static struct workqueue_struct *kfd_process_wq; static struct kfd_process *find_process(const struct task_struct *thread); +static void kfd_process_ref_release(struct kref *ref); static struct kfd_process *create_process(const struct task_struct *thread); static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep); @@ -146,6 +147,11 @@ static struct kfd_process *find_process(const struct task_struct *thread) return p; } +void kfd_unref_process(struct kfd_process *p) +{ + kref_put(&p->ref, kfd_process_ref_release); +} + /* No process locking is needed in this function, because the process * is not findable any more. We must assume that no other thread is * using it any more, otherwise we couldn't safely free the process @@ -201,7 +207,7 @@ static void kfd_process_destroy_delayed(struct rcu_head *rcu) { struct kfd_process *p = container_of(rcu, struct kfd_process, rcu); - kref_put(&p->ref, kfd_process_ref_release); + kfd_unref_process(p); } static void kfd_process_notifier_release(struct mmu_notifier *mn, @@ -525,6 +531,8 @@ void kfd_process_iommu_unbind_callback(struct kfd_dev *dev, unsigned int pasid) mutex_unlock(kfd_get_dbgmgr_mutex()); + mutex_lock(&p->mutex); + pdd = kfd_get_process_device_data(dev, p); if (pdd) /* For GPU relying on IOMMU, we need to dequeue here @@ -533,6 +541,8 @@ void kfd_process_iommu_unbind_callback(struct kfd_dev *dev, unsigned int pasid) kfd_process_dequeue_from_device(pdd); mutex_unlock(&p->mutex); + + kfd_unref_process(p); } struct kfd_process_device *kfd_get_first_process_device_data( @@ -557,7 +567,7 @@ bool kfd_has_process_device_data(struct kfd_process *p) return !(list_empty(&p->per_device_data)); } -/* This returns with process->mutex locked. */ +/* This increments the process->ref counter. */ struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid) { struct kfd_process *p; @@ -567,7 +577,7 @@ struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid) hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { if (p->pasid == pasid) { - mutex_lock(&p->mutex); + kref_get(&p->ref); break; } } -- GitLab From 82c16b4280bc42bc035af566e1480d88666126b1 Mon Sep 17 00:00:00 2001 From: Yong Zhao Date: Mon, 27 Nov 2017 18:29:53 -0500 Subject: [PATCH 0177/2547] drm/amdkfd: Return NULL if kfd_lookup_process_by_pasid fails If no matching process is found, return NULL instead of a pointer to the last process in the kfd_processes_table. Signed-off-by: Yong Zhao Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 509f987f4994..93f90191509f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -570,7 +570,7 @@ bool kfd_has_process_device_data(struct kfd_process *p) /* This increments the process->ref counter. */ struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid) { - struct kfd_process *p; + struct kfd_process *p, *ret_p = NULL; unsigned int temp; int idx = srcu_read_lock(&kfd_processes_srcu); @@ -578,13 +578,14 @@ struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid) hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { if (p->pasid == pasid) { kref_get(&p->ref); + ret_p = p; break; } } srcu_read_unlock(&kfd_processes_srcu, idx); - return p; + return ret_p; } int kfd_reserved_mem_mmap(struct kfd_process *process, -- GitLab From 2d9b36f98343624282f81c1886e95bc552d1a9b7 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 27 Nov 2017 18:29:54 -0500 Subject: [PATCH 0178/2547] drm/amdkfd: Reduce nesting in kfd_create_process_device_data Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 93f90191509f..88fc822c9e5a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -390,17 +390,18 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev, struct kfd_process_device *pdd = NULL; pdd = kzalloc(sizeof(*pdd), GFP_KERNEL); - if (pdd != NULL) { - pdd->dev = dev; - INIT_LIST_HEAD(&pdd->qpd.queues_list); - INIT_LIST_HEAD(&pdd->qpd.priv_queue_list); - pdd->qpd.dqm = dev->dqm; - pdd->qpd.pqm = &p->pqm; - pdd->process = p; - pdd->bound = PDD_UNBOUND; - pdd->already_dequeued = false; - list_add(&pdd->per_device_list, &p->per_device_data); - } + if (!pdd) + return NULL; + + pdd->dev = dev; + INIT_LIST_HEAD(&pdd->qpd.queues_list); + INIT_LIST_HEAD(&pdd->qpd.priv_queue_list); + pdd->qpd.dqm = dev->dqm; + pdd->qpd.pqm = &p->pqm; + pdd->process = p; + pdd->bound = PDD_UNBOUND; + pdd->already_dequeued = false; + list_add(&pdd->per_device_list, &p->per_device_data); return pdd; } -- GitLab From de1450a5597a642bdc4987aa31873d8475810aae Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 27 Nov 2017 18:29:55 -0500 Subject: [PATCH 0179/2547] drm/amdkfd: Factor PDD destruction out of kfd_process_wq_release Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 40 ++++++++++++++---------- 1 file changed, 24 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 88fc822c9e5a..096710c3766d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -152,28 +152,15 @@ void kfd_unref_process(struct kfd_process *p) kref_put(&p->ref, kfd_process_ref_release); } -/* No process locking is needed in this function, because the process - * is not findable any more. We must assume that no other thread is - * using it any more, otherwise we couldn't safely free the process - * structure in the end. - */ -static void kfd_process_wq_release(struct work_struct *work) +static void kfd_process_destroy_pdds(struct kfd_process *p) { - struct kfd_process *p = container_of(work, struct kfd_process, - release_work); struct kfd_process_device *pdd, *temp; - pr_debug("Releasing process (pasid %d) in workqueue\n", - p->pasid); - list_for_each_entry_safe(pdd, temp, &p->per_device_data, - per_device_list) { - pr_debug("Releasing pdd (topology id %d) for process (pasid %d) in workqueue\n", + per_device_list) { + pr_debug("Releasing pdd (topology id %d) for process (pasid %d)\n", pdd->dev->id, p->pasid); - if (pdd->bound == PDD_BOUND) - amd_iommu_unbind_pasid(pdd->dev->pdev, p->pasid); - list_del(&pdd->per_device_list); if (pdd->qpd.cwsr_kaddr) @@ -182,6 +169,27 @@ static void kfd_process_wq_release(struct work_struct *work) kfree(pdd); } +} + +/* No process locking is needed in this function, because the process + * is not findable any more. We must assume that no other thread is + * using it any more, otherwise we couldn't safely free the process + * structure in the end. + */ +static void kfd_process_wq_release(struct work_struct *work) +{ + struct kfd_process *p = container_of(work, struct kfd_process, + release_work); + struct kfd_process_device *pdd; + + pr_debug("Releasing process (pasid %d) in workqueue\n", p->pasid); + + list_for_each_entry(pdd, &p->per_device_data, per_device_list) { + if (pdd->bound == PDD_BOUND) + amd_iommu_unbind_pasid(pdd->dev->pdev, p->pasid); + } + + kfd_process_destroy_pdds(p); kfd_event_free_process(p); -- GitLab From c0ede1f8dc3a22464b126f4d54ad7999ebb789a0 Mon Sep 17 00:00:00 2001 From: Yong Zhao Date: Mon, 27 Nov 2017 18:29:56 -0500 Subject: [PATCH 0180/2547] drm/amdkfd: Simplify locking during process creation Also fixes error handling if kfd_process_init_cwsr fails. Signed-off-by: Yong Zhao Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 46 +++++++++++------------- 1 file changed, 21 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 096710c3766d..a22fb0710f15 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -50,7 +50,8 @@ static struct workqueue_struct *kfd_process_wq; static struct kfd_process *find_process(const struct task_struct *thread); static void kfd_process_ref_release(struct kref *ref); -static struct kfd_process *create_process(const struct task_struct *thread); +static struct kfd_process *create_process(const struct task_struct *thread, + struct file *filep); static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep); @@ -80,9 +81,6 @@ struct kfd_process *kfd_create_process(struct file *filep) if (thread->group_leader->mm != thread->mm) return ERR_PTR(-EINVAL); - /* Take mmap_sem because we call __mmu_notifier_register inside */ - down_write(&thread->mm->mmap_sem); - /* * take kfd processes mutex before starting of process creation * so there won't be a case where two threads of the same process @@ -94,16 +92,11 @@ struct kfd_process *kfd_create_process(struct file *filep) process = find_process(thread); if (process) pr_debug("Process already found\n"); - - if (!process) - process = create_process(thread); + else + process = create_process(thread, filep); mutex_unlock(&kfd_processes_mutex); - up_write(&thread->mm->mmap_sem); - - kfd_process_init_cwsr(process, filep); - return process; } @@ -274,15 +267,12 @@ static const struct mmu_notifier_ops kfd_process_mmu_notifier_ops = { static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep) { - int err = 0; unsigned long offset; - struct kfd_process_device *temp, *pdd = NULL; + struct kfd_process_device *pdd = NULL; struct kfd_dev *dev = NULL; struct qcm_process_device *qpd = NULL; - mutex_lock(&p->mutex); - list_for_each_entry_safe(pdd, temp, &p->per_device_data, - per_device_list) { + list_for_each_entry(pdd, &p->per_device_data, per_device_list) { dev = pdd->dev; qpd = &pdd->qpd; if (!dev->cwsr_enabled || qpd->cwsr_kaddr) @@ -293,12 +283,12 @@ static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep) MAP_SHARED, offset); if (IS_ERR_VALUE(qpd->tba_addr)) { - pr_err("Failure to set tba address. error -%d.\n", - (int)qpd->tba_addr); - err = qpd->tba_addr; + int err = qpd->tba_addr; + + pr_err("Failure to set tba address. error %d.\n", err); qpd->tba_addr = 0; qpd->cwsr_kaddr = NULL; - goto out; + return err; } memcpy(qpd->cwsr_kaddr, dev->cwsr_isa, dev->cwsr_isa_size); @@ -307,12 +297,12 @@ static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep) pr_debug("set tba :0x%llx, tma:0x%llx, cwsr_kaddr:%p for pqm.\n", qpd->tba_addr, qpd->tma_addr, qpd->cwsr_kaddr); } -out: - mutex_unlock(&p->mutex); - return err; + + return 0; } -static struct kfd_process *create_process(const struct task_struct *thread) +static struct kfd_process *create_process(const struct task_struct *thread, + struct file *filep) { struct kfd_process *process; int err = -ENOMEM; @@ -337,7 +327,7 @@ static struct kfd_process *create_process(const struct task_struct *thread) /* register notifier */ process->mmu_notifier.ops = &kfd_process_mmu_notifier_ops; - err = __mmu_notifier_register(&process->mmu_notifier, process->mm); + err = mmu_notifier_register(&process->mmu_notifier, process->mm); if (err) goto err_mmu_notifier; @@ -361,8 +351,14 @@ static struct kfd_process *create_process(const struct task_struct *thread) if (err != 0) goto err_init_apertures; + err = kfd_process_init_cwsr(process, filep); + if (err) + goto err_init_cwsr; + return process; +err_init_cwsr: + kfd_process_destroy_pdds(process); err_init_apertures: pqm_uninit(&process->pqm); err_process_pqm_init: -- GitLab From 8b1836c4b64386e9bc580438cae386ed31a43ab9 Mon Sep 17 00:00:00 2001 From: Jay Elliott Date: Wed, 15 Nov 2017 15:01:13 -0800 Subject: [PATCH 0181/2547] netfilter: conntrack: clamp timeouts to INT_MAX When the conntracking code multiplies a timeout by HZ, it can overflow from positive to negative; this causes it to instantly expire. To protect against this the multiplication is done in 64-bit so we can prevent it from exceeding INT_MAX. Signed-off-by: Jay Elliott Acked-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_conntrack_netlink.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c index 59c08997bfdf..66d72a8fa87f 100644 --- a/net/netfilter/nf_conntrack_netlink.c +++ b/net/netfilter/nf_conntrack_netlink.c @@ -1566,9 +1566,11 @@ static int ctnetlink_change_helper(struct nf_conn *ct, static int ctnetlink_change_timeout(struct nf_conn *ct, const struct nlattr * const cda[]) { - u_int32_t timeout = ntohl(nla_get_be32(cda[CTA_TIMEOUT])); + u64 timeout = (u64)ntohl(nla_get_be32(cda[CTA_TIMEOUT])) * HZ; - ct->timeout = nfct_time_stamp + timeout * HZ; + if (timeout > INT_MAX) + timeout = INT_MAX; + ct->timeout = nfct_time_stamp + (u32)timeout; if (test_bit(IPS_DYING_BIT, &ct->status)) return -ETIME; @@ -1768,6 +1770,7 @@ ctnetlink_create_conntrack(struct net *net, int err = -EINVAL; struct nf_conntrack_helper *helper; struct nf_conn_tstamp *tstamp; + u64 timeout; ct = nf_conntrack_alloc(net, zone, otuple, rtuple, GFP_ATOMIC); if (IS_ERR(ct)) @@ -1776,7 +1779,10 @@ ctnetlink_create_conntrack(struct net *net, if (!cda[CTA_TIMEOUT]) goto err1; - ct->timeout = nfct_time_stamp + ntohl(nla_get_be32(cda[CTA_TIMEOUT])) * HZ; + timeout = (u64)ntohl(nla_get_be32(cda[CTA_TIMEOUT])) * HZ; + if (timeout > INT_MAX) + timeout = INT_MAX; + ct->timeout = (u32)timeout + nfct_time_stamp; rcu_read_lock(); if (cda[CTA_HELP]) { -- GitLab From 55d2d0ad2fb4325f615d1950486fbc5e6fba1769 Mon Sep 17 00:00:00 2001 From: Chunyu Hu Date: Mon, 27 Nov 2017 22:21:39 +0800 Subject: [PATCH 0182/2547] x86/idt: Load idt early in start_secondary On a secondary, idt is first loaded in cpu_init() with load_current_idt(), i.e. no exceptions can be handled before that point. The conversion of WARN() to use UD requires the IDT being loaded earlier as any warning between start_secondary() and load_curren_idt() in cpu_init() will result in an unhandled @UD exception and therefore fail the bringup of the CPU. Install the IDT handlers right in start_secondary() before calling cpu_init(). [ tglx: Massaged changelog ] Fixes: 9a93848fe787 ("x86/debug: Implement __WARN() using UD0") Signed-off-by: Chunyu Hu Signed-off-by: Thomas Gleixner Cc: stable@vger.kernel.org Cc: peterz@infradead.org Cc: bp@alien8.de Cc: rostedt@goodmis.org Cc: luto@kernel.org Link: https://lkml.kernel.org/r/1511792499-4073-1-git-send-email-chuhu@redhat.com --- arch/x86/kernel/smpboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 3d01df7d7cf6..05a97d5fe298 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -237,7 +237,7 @@ static void notrace start_secondary(void *unused) load_cr3(swapper_pg_dir); __flush_tlb_all(); #endif - + load_current_idt(); cpu_init(); x86_cpuinit.early_percpu_clock_init(); preempt_disable(); -- GitLab From 762ff4678e89a5e3f8b2237533e04d3ef2737e78 Mon Sep 17 00:00:00 2001 From: Lu Baolu Date: Tue, 28 Nov 2017 12:40:59 +0800 Subject: [PATCH 0183/2547] USB: serial: usb_debug: add new USB device id USB vendor id and product id for Linux USB Debug Target is added. Signed-off-by: Lu Baolu Cc: stable Signed-off-by: Johan Hovold --- drivers/usb/serial/usb_debug.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/serial/usb_debug.c b/drivers/usb/serial/usb_debug.c index ab5a2ac4993a..aaf4813e4971 100644 --- a/drivers/usb/serial/usb_debug.c +++ b/drivers/usb/serial/usb_debug.c @@ -31,12 +31,14 @@ static const struct usb_device_id id_table[] = { }; static const struct usb_device_id dbc_id_table[] = { + { USB_DEVICE(0x1d6b, 0x0010) }, { USB_DEVICE(0x1d6b, 0x0011) }, { }, }; static const struct usb_device_id id_table_combined[] = { { USB_DEVICE(0x0525, 0x127a) }, + { USB_DEVICE(0x1d6b, 0x0010) }, { USB_DEVICE(0x1d6b, 0x0011) }, { }, }; -- GitLab From b2fc059fa549fe6881d4c1f8d698b0f50bcd16ec Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 14 Nov 2017 16:18:28 +0000 Subject: [PATCH 0184/2547] usb: gadget: don't dereference g until after it has been null checked Avoid dereferencing pointer g until after g has been sanity null checked; move the assignment of cdev much later when it is required into a more local scope. Detected by CoverityScan, CID#1222135 ("Dereference before null check") Fixes: b785ea7ce662 ("usb: gadget: composite: fix ep->maxburst initialization") Signed-off-by: Colin Ian King Signed-off-by: Felipe Balbi --- drivers/usb/gadget/composite.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index eec14e6ed20b..77c7ecca816a 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -146,7 +146,6 @@ int config_ep_by_speed(struct usb_gadget *g, struct usb_function *f, struct usb_ep *_ep) { - struct usb_composite_dev *cdev = get_gadget_data(g); struct usb_endpoint_descriptor *chosen_desc = NULL; struct usb_descriptor_header **speed_desc = NULL; @@ -226,8 +225,12 @@ int config_ep_by_speed(struct usb_gadget *g, _ep->maxburst = comp_desc->bMaxBurst + 1; break; default: - if (comp_desc->bMaxBurst != 0) + if (comp_desc->bMaxBurst != 0) { + struct usb_composite_dev *cdev; + + cdev = get_gadget_data(g); ERROR(cdev, "ep0 bMaxBurst must be 0\n"); + } _ep->maxburst = 1; break; } -- GitLab From a58204ab91ad8cae4d8474aa0ba5d1fc504860c9 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 13 Nov 2017 17:59:18 +0900 Subject: [PATCH 0185/2547] usb: gadget: udc: renesas_usb3: fix number of the pipes This controller on R-Car Gen3 has 6 pipes that included PIPE 0 for control actually. But, the datasheet has error in writing as it has 31 pipes. (However, the previous code defined 30 pipes wrongly...) Anyway, this patch fixes it. Fixes: 746bfe63bba3 ("usb: gadget: renesas_usb3: add support for Renesas USB3.0 peripheral controller") Cc: # v4.5+ Signed-off-by: Yoshihiro Shimoda Signed-off-by: Felipe Balbi --- drivers/usb/gadget/udc/renesas_usb3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c index bc37f40baacf..6e87af248367 100644 --- a/drivers/usb/gadget/udc/renesas_usb3.c +++ b/drivers/usb/gadget/udc/renesas_usb3.c @@ -252,7 +252,7 @@ #define USB3_EP0_SS_MAX_PACKET_SIZE 512 #define USB3_EP0_HSFS_MAX_PACKET_SIZE 64 #define USB3_EP0_BUF_SIZE 8 -#define USB3_MAX_NUM_PIPES 30 +#define USB3_MAX_NUM_PIPES 6 /* This includes PIPE 0 */ #define USB3_WAIT_US 3 #define USB3_DMA_NUM_SETTING_AREA 4 /* -- GitLab From 7a9618a22aadffb55027d665491adf466bced61a Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Tue, 31 Oct 2017 11:03:19 -0700 Subject: [PATCH 0186/2547] usb: gadget: allow to enable legacy drivers without USB_ETH Considerable time ago the legacy gadget menu was added inside the USB_ETH choice. I think this was a mistake and that the legacy gadget menu should have been added after "endchoice" instead of before. Hence this patch. Fixes: commit 8443f2d2b778 ("usb: gadget: Gadget directory cleanup - group legacy gadgets") Signed-off-by: Bart Van Assche Reviewed-by: Hannes Reinecke Cc: Nicholas Bellinger Cc: Andrzej Pietrasiewicz Cc: linux-usb@vger.kernel.org Signed-off-by: Felipe Balbi --- drivers/usb/gadget/Kconfig | 4 ++-- drivers/usb/gadget/legacy/Kconfig | 10 ++++++++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 31cce7805eb2..0a19a76645ad 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -508,8 +508,8 @@ choice controller, and the relevant drivers for each function declared by the device. -source "drivers/usb/gadget/legacy/Kconfig" - endchoice +source "drivers/usb/gadget/legacy/Kconfig" + endif # USB_GADGET diff --git a/drivers/usb/gadget/legacy/Kconfig b/drivers/usb/gadget/legacy/Kconfig index a12fb459dbd9..9570bbeced4f 100644 --- a/drivers/usb/gadget/legacy/Kconfig +++ b/drivers/usb/gadget/legacy/Kconfig @@ -13,6 +13,14 @@ # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG). # +menuconfig USB_GADGET_LEGACY + bool "Legacy USB Gadget Support" + help + Legacy USB gadgets are USB gadgets that do not use the USB gadget + configfs interface. + +if USB_GADGET_LEGACY + config USB_ZERO tristate "Gadget Zero (DEVELOPMENT)" select USB_LIBCOMPOSITE @@ -490,3 +498,5 @@ config USB_G_WEBCAM Say "y" to link the driver statically, or "m" to build a dynamically linked module called "g_webcam". + +endif -- GitLab From a4f0927ef588cf62bb864707261482c874352942 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 31 Oct 2017 15:56:29 +0200 Subject: [PATCH 0187/2547] usb: gadget: core: Fix ->udc_set_speed() speed handling Currently UDC core calls ->udc_set_speed() with the speed parameter containing the maximum speed supported by the gadget function driver. This might very well be more than that supported by the UDC controller driver. Select the lesser of the 2 speeds so both UDC and gadget function driver are operating within limits. This fixes PHY Erratic errors and 2 second enumeration delay on TI's AM437x platforms. Fixes: 6099eca796ae ("usb: gadget: core: introduce ->udc_set_speed() method") Cc: # v4.13+ Reported-by: Dylan Howey Signed-off-by: Roger Quadros Signed-off-by: Felipe Balbi --- drivers/usb/gadget/udc/core.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/udc/core.c b/drivers/usb/gadget/udc/core.c index 61422d624ad0..93eff7dec2f5 100644 --- a/drivers/usb/gadget/udc/core.c +++ b/drivers/usb/gadget/udc/core.c @@ -1069,8 +1069,12 @@ static inline void usb_gadget_udc_stop(struct usb_udc *udc) static inline void usb_gadget_udc_set_speed(struct usb_udc *udc, enum usb_device_speed speed) { - if (udc->gadget->ops->udc_set_speed) - udc->gadget->ops->udc_set_speed(udc->gadget, speed); + if (udc->gadget->ops->udc_set_speed) { + enum usb_device_speed s; + + s = min(speed, udc->gadget->max_speed); + udc->gadget->ops->udc_set_speed(udc->gadget, s); + } } /** -- GitLab From a3acc696085e112733d191a77b106e67a4fa110b Mon Sep 17 00:00:00 2001 From: John Keeping Date: Mon, 27 Nov 2017 18:15:40 +0000 Subject: [PATCH 0188/2547] usb: f_fs: Force Reserved1=1 in OS_DESC_EXT_COMPAT The specification says that the Reserved1 field in OS_DESC_EXT_COMPAT must have the value "1", but when this feature was first implemented we rejected any non-zero values. This was adjusted to accept all non-zero values (while now rejecting zero) in commit 53642399aa71 ("usb: gadget: f_fs: Fix wrong check on reserved1 of OS_DESC_EXT_COMPAT"), but that breaks any userspace programs that worked previously by returning EINVAL when Reserved1 == 0 which was previously the only value that succeeded! If we just set the field to "1" ourselves, both old and new userspace programs continue to work correctly and, as a bonus, old programs are now compliant with the specification without having to fix anything themselves. Fixes: 53642399aa71 ("usb: gadget: f_fs: Fix wrong check on reserved1 of OS_DESC_EXT_COMPAT") Cc: Signed-off-by: John Keeping Signed-off-by: Felipe Balbi --- drivers/usb/gadget/function/f_fs.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index 9aa457b53e01..b6cf5ab5a0a1 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -2282,9 +2282,18 @@ static int __ffs_data_do_os_desc(enum ffs_os_desc_type type, int i; if (len < sizeof(*d) || - d->bFirstInterfaceNumber >= ffs->interfaces_count || - !d->Reserved1) + d->bFirstInterfaceNumber >= ffs->interfaces_count) return -EINVAL; + if (d->Reserved1 != 1) { + /* + * According to the spec, Reserved1 must be set to 1 + * but older kernels incorrectly rejected non-zero + * values. We fix it here to avoid returning EINVAL + * in response to values we used to accept. + */ + pr_debug("usb_ext_compat_desc::Reserved1 forced to 1\n"); + d->Reserved1 = 1; + } for (i = 0; i < ARRAY_SIZE(d->Reserved2); ++i) if (d->Reserved2[i]) return -EINVAL; -- GitLab From a91d7fb97092d6b840af5899ded3b389603fd7f1 Mon Sep 17 00:00:00 2001 From: Jiada Wang Date: Tue, 28 Nov 2017 16:05:13 +0900 Subject: [PATCH 0189/2547] ASoC: rsnd: ssiu: clear SSI_MODE for non TDM Extended modes register SSI_MODE is set when SSI works in TDM Extended, but it isn't reset when SSI starts to work in other modes, thus causes issues. This patch clearss SSI_MODE register when SSI works in modes other than TDM Extended. Fixes: 186fadc132f0 ("ASoC: rsnd: add TDM Extend Mode support") Signed-off-by: Jiada Wang Acked-by: Kuninori Morimoto Signed-off-by: Mark Brown --- sound/soc/sh/rcar/ssiu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/sound/soc/sh/rcar/ssiu.c b/sound/soc/sh/rcar/ssiu.c index 4d948757d300..6ff8a36c2c82 100644 --- a/sound/soc/sh/rcar/ssiu.c +++ b/sound/soc/sh/rcar/ssiu.c @@ -125,6 +125,7 @@ static int rsnd_ssiu_init_gen2(struct rsnd_mod *mod, { int hdmi = rsnd_ssi_hdmi_port(io); int ret; + u32 mode = 0; ret = rsnd_ssiu_init(mod, io, priv); if (ret < 0) @@ -136,9 +137,11 @@ static int rsnd_ssiu_init_gen2(struct rsnd_mod *mod, * see * rsnd_ssi_config_init() */ - rsnd_mod_write(mod, SSI_MODE, 0x1); + mode = 0x1; } + rsnd_mod_write(mod, SSI_MODE, mode); + if (rsnd_ssi_use_busif(io)) { rsnd_mod_write(mod, SSI_BUSIF_ADINR, rsnd_get_adinr_bit(mod, io) | -- GitLab From 02d69c0359f7069c626cef6541f94a3a22dc5ed9 Mon Sep 17 00:00:00 2001 From: Matthew Giassa Date: Sat, 18 Nov 2017 08:26:17 -0800 Subject: [PATCH 0190/2547] staging: comedi: ni_atmio: fix license warning. Resolving license check warning for drivers/staging/comedi. Added the license definitions present in the rest of the module and made sure it's aligned with the license (GPL) in the comments for the affected file (ni_atmio.c). Original warning: WARNING: modpost: missing MODULE_LICENSE() in drivers/staging/comedi//drivers/ni_atmio.o see include/linux/module.h for more information. No longer present after change. Signed-off-by: Matthew Giassa Reviewed-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_atmio.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/staging/comedi/drivers/ni_atmio.c b/drivers/staging/comedi/drivers/ni_atmio.c index 2d62a8c57332..ae6ed96d7874 100644 --- a/drivers/staging/comedi/drivers/ni_atmio.c +++ b/drivers/staging/comedi/drivers/ni_atmio.c @@ -361,3 +361,8 @@ static struct comedi_driver ni_atmio_driver = { .detach = ni_atmio_detach, }; module_comedi_driver(ni_atmio_driver); + +MODULE_AUTHOR("Comedi http://www.comedi.org"); +MODULE_DESCRIPTION("Comedi low-level driver"); +MODULE_LICENSE("GPL"); + -- GitLab From c5f39d07860c35e5e4c63188139465af790f86ce Mon Sep 17 00:00:00 2001 From: Gilad Ben-Yossef Date: Thu, 9 Nov 2017 09:16:09 +0000 Subject: [PATCH 0191/2547] staging: ccree: fix leak of import() after init() crypto_ahash_import() may be called either after crypto_ahash_init() or without such call. Right now we always internally call init() as part of import(), thus leaking memory and mappings if the user has already called init() herself. Fix this by only calling init() internally if the state is not already initialized. Fixes: commit 454527d0d94f ("staging: ccree: fix hash import/export") Cc: stable Signed-off-by: Gilad Ben-Yossef Reviewed-by: Dan Carpenter Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ccree/ssi_hash.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c index d79090ed7f9c..1799d3f26a9e 100644 --- a/drivers/staging/ccree/ssi_hash.c +++ b/drivers/staging/ccree/ssi_hash.c @@ -1778,9 +1778,12 @@ static int ssi_ahash_import(struct ahash_request *req, const void *in) } in += sizeof(u32); - rc = ssi_hash_init(state, ctx); - if (rc) - goto out; + /* call init() to allocate bufs if the user hasn't */ + if (!state->digest_buff) { + rc = ssi_hash_init(state, ctx); + if (rc) + goto out; + } dma_sync_single_for_cpu(dev, state->digest_buff_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL); -- GitLab From b77992d2df9e47144354d1b25328b180afa33442 Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Sat, 25 Nov 2017 13:32:38 -0600 Subject: [PATCH 0192/2547] staging: rtl8188eu: Fix incorrect response to SIOCGIWESSID When not associated with an AP, wifi device drivers should respond to the SIOCGIWESSID ioctl with a zero-length string for the SSID, which is the behavior expected by dhcpcd. Currently, this driver returns an error code (-1) from the ioctl call, which causes dhcpcd to assume that the device is not a wireless interface and therefore it fails to work correctly with it thereafter. This problem was reported and tested at https://github.com/lwfinger/rtl8188eu/issues/234. Signed-off-by: Larry Finger Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8188eu/os_dep/ioctl_linux.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/staging/rtl8188eu/os_dep/ioctl_linux.c b/drivers/staging/rtl8188eu/os_dep/ioctl_linux.c index c0664dc80bf2..446310775e90 100644 --- a/drivers/staging/rtl8188eu/os_dep/ioctl_linux.c +++ b/drivers/staging/rtl8188eu/os_dep/ioctl_linux.c @@ -1395,19 +1395,13 @@ static int rtw_wx_get_essid(struct net_device *dev, if ((check_fwstate(pmlmepriv, _FW_LINKED)) || (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))) { len = pcur_bss->Ssid.SsidLength; - - wrqu->essid.length = len; - memcpy(extra, pcur_bss->Ssid.Ssid, len); - - wrqu->essid.flags = 1; } else { - ret = -1; - goto exit; + len = 0; + *extra = 0; } - -exit: - + wrqu->essid.length = len; + wrqu->essid.flags = 1; return ret; } -- GitLab From 0590cdfead8cd6319cc58b5dbe8ab9fbaabae131 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Fri, 17 Nov 2017 09:50:10 +0200 Subject: [PATCH 0193/2547] staging: octeon-usb: use __delay() instead of cvmx_wait() Commit edf188bee1d9 ("MIPS: Octeon: Remove usage of cvmx_wait() everywhere.") deleted cvmx_wait() but forgot to update OCTEON USB staging driver. Fix that to allow driver build. Fixes: edf188bee1d9 ("MIPS: Octeon: Remove usage of cvmx_wait() everywhere.") Signed-off-by: Aaro Koskinen Reviewed-by: James Hogan Signed-off-by: Greg Kroah-Hartman --- drivers/staging/octeon-usb/octeon-hcd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/staging/octeon-usb/octeon-hcd.c b/drivers/staging/octeon-usb/octeon-hcd.c index 068aece25d37..cded30f145aa 100644 --- a/drivers/staging/octeon-usb/octeon-hcd.c +++ b/drivers/staging/octeon-usb/octeon-hcd.c @@ -394,7 +394,7 @@ struct octeon_hcd { result = -1; \ break; \ } else \ - cvmx_wait(100); \ + __delay(100); \ } \ } while (0); \ result; }) @@ -774,7 +774,7 @@ static int cvmx_usb_initialize(struct device *dev, usbn_clk_ctl.s.hclk_rst = 1; cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */ - cvmx_wait(64); + __delay(64); /* * 3. Program the power-on reset field in the USBN clock-control * register: @@ -795,7 +795,7 @@ static int cvmx_usb_initialize(struct device *dev, cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index), usbn_usbp_ctl_status.u64); /* 6. Wait 10 cycles */ - cvmx_wait(10); + __delay(10); /* * 7. Clear ATE_RESET field in the USBN clock-control register: * USBN_USBP_CTL_STATUS[ATE_RESET] = 0 -- GitLab From 46febd37f9c758b05cd25feae8512f22584742fe Mon Sep 17 00:00:00 2001 From: Lai Jiangshan Date: Tue, 28 Nov 2017 21:19:53 +0800 Subject: [PATCH 0194/2547] smp/hotplug: Move step CPUHP_AP_SMPCFD_DYING to the correct place Commit 31487f8328f2 ("smp/cfd: Convert core to hotplug state machine") accidently put this step on the wrong place. The step should be at the cpuhp_ap_states[] rather than the cpuhp_bp_states[]. grep smpcfd /sys/devices/system/cpu/hotplug/states 40: smpcfd:prepare 129: smpcfd:dying "smpcfd:dying" was missing before. So was the invocation of the function smpcfd_dying_cpu(). Fixes: 31487f8328f2 ("smp/cfd: Convert core to hotplug state machine") Signed-off-by: Lai Jiangshan Signed-off-by: Thomas Gleixner Cc: Peter Zijlstra Cc: Richard Weinberger Cc: Sebastian Andrzej Siewior Cc: stable@vger.kernel.org Cc: Boris Ostrovsky Link: https://lkml.kernel.org/r/20171128131954.81229-1-jiangshanlai@gmail.com --- kernel/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/kernel/cpu.c b/kernel/cpu.c index 04892a82f6ac..7891aecc6aec 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -1289,11 +1289,6 @@ static struct cpuhp_step cpuhp_bp_states[] = { .teardown.single = NULL, .cant_stop = true, }, - [CPUHP_AP_SMPCFD_DYING] = { - .name = "smpcfd:dying", - .startup.single = NULL, - .teardown.single = smpcfd_dying_cpu, - }, /* * Handled on controll processor until the plugged processor manages * this itself. @@ -1335,6 +1330,11 @@ static struct cpuhp_step cpuhp_ap_states[] = { .startup.single = NULL, .teardown.single = rcutree_dying_cpu, }, + [CPUHP_AP_SMPCFD_DYING] = { + .name = "smpcfd:dying", + .startup.single = NULL, + .teardown.single = smpcfd_dying_cpu, + }, /* Entry state on starting. Interrupts enabled from here on. Transient * state for synchronsization */ [CPUHP_AP_ONLINE] = { -- GitLab From a7c42106ead7041b99662a125b408deb68a3e6aa Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Tue, 14 Nov 2017 14:45:27 +0300 Subject: [PATCH 0195/2547] usb: add user selectable option for the whole USB Type-C Support It is more clear from user perspective to wrap the whole USB Type-C support under a single option that the user can select, then it is to always ask the user for every USB Type-C and USB Power Delivery driver separately. Reported-by: Linus Torvalds Signed-off-by: Heikki Krogerus Signed-off-by: Greg Kroah-Hartman --- drivers/usb/typec/Kconfig | 54 +++++++++++++++++++++++++++++----- drivers/usb/typec/ucsi/Kconfig | 1 - 2 files changed, 46 insertions(+), 9 deletions(-) diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig index 465d7da849c3..bcb2744c5977 100644 --- a/drivers/usb/typec/Kconfig +++ b/drivers/usb/typec/Kconfig @@ -1,13 +1,53 @@ -menu "USB Power Delivery and Type-C drivers" +menuconfig TYPEC + tristate "USB Type-C Support" + help + USB Type-C Specification defines a cable and connector for USB where + only one type of plug is supported on both ends, i.e. there will not + be Type-A plug on one end of the cable and Type-B plug on the other. + Determination of the host-to-device relationship happens through a + specific Configuration Channel (CC) which goes through the USB Type-C + cable. The Configuration Channel may also be used to detect optional + Accessory Modes - Analog Audio and Debug - and if USB Power Delivery + is supported, the Alternate Modes, where the connector is used for + something else then USB communication. + + USB Power Delivery Specification defines a protocol that can be used + to negotiate the voltage and current levels with the connected + partners. USB Power Delivery allows higher voltages then the normal + 5V, up to 20V, and current up to 5A over the cable. The USB Power + Delivery protocol is also used to negotiate the optional Alternate + Modes when they are supported. USB Power Delivery does not depend on + USB Type-C connector, however it is mostly used together with USB + Type-C connectors. + + USB Type-C and USB Power Delivery Specifications define a set of state + machines that need to be implemented in either software or firmware. + Simple USB Type-C PHYs, for example USB Type-C Port Controller + Interface Specification compliant "Port Controllers" need the state + machines to be handled in the OS, but stand-alone USB Type-C and Power + Delivery controllers handle the state machines inside their firmware. + The USB Type-C and Power Delivery controllers usually function + autonomously, and do not necessarily require drivers. + + Enable this configurations option if you have USB Type-C connectors on + your system and 1) you know your USB Type-C hardware requires OS + control (a driver) to function, or 2) if you need to be able to read + the status of the USB Type-C ports in your system, or 3) if you need + to be able to swap the power role (decide are you supplying or + consuming power over the cable) or data role (host or device) when + both roles are supported. + + For more information, see the kernel documentation for USB Type-C + Connector Class API (Documentation/driver-api/usb/typec.rst) + + and ABI (Documentation/ABI/testing/sysfs-class-typec). -config TYPEC - tristate +if TYPEC config TYPEC_TCPM tristate "USB Type-C Port Controller Manager" depends on USB - select TYPEC help The Type-C Port Controller Manager provides a USB PD and USB Type-C state machine for use with Type-C Port Controllers. @@ -22,7 +62,6 @@ config TYPEC_WCOVE depends on INTEL_SOC_PMIC depends on INTEL_PMC_IPC depends on BXT_WC_PMIC_OPREGION - select TYPEC help This driver adds support for USB Type-C detection on Intel Broxton platforms that have Intel Whiskey Cove PMIC. The driver can detect the @@ -31,14 +70,13 @@ config TYPEC_WCOVE To compile this driver as module, choose M here: the module will be called typec_wcove -endif +endif # TYPEC_TCPM source "drivers/usb/typec/ucsi/Kconfig" config TYPEC_TPS6598X tristate "TI TPS6598x USB Power Delivery controller driver" depends on I2C - select TYPEC help Say Y or M here if your system has TI TPS65982 or TPS65983 USB Power Delivery controller. @@ -46,4 +84,4 @@ config TYPEC_TPS6598X If you choose to build this driver as a dynamically linked module, the module will be called tps6598x.ko. -endmenu +endif # TYPEC diff --git a/drivers/usb/typec/ucsi/Kconfig b/drivers/usb/typec/ucsi/Kconfig index d0c31cee4720..e36d6c73c4a4 100644 --- a/drivers/usb/typec/ucsi/Kconfig +++ b/drivers/usb/typec/ucsi/Kconfig @@ -1,7 +1,6 @@ config TYPEC_UCSI tristate "USB Type-C Connector System Software Interface driver" depends on !CPU_BIG_ENDIAN - select TYPEC help USB Type-C Connector System Software Interface (UCSI) is a specification for an interface that allows the operating system to -- GitLab From 446f666da9f019ce2ffd03800995487e79a91462 Mon Sep 17 00:00:00 2001 From: Oliver Neukum Date: Thu, 23 Nov 2017 16:39:52 +0100 Subject: [PATCH 0196/2547] USB: usbfs: Filter flags passed in from user space USBDEVFS_URB_ISO_ASAP must be accepted only for ISO endpoints. Improve sanity checking. Reported-by: Andrey Konovalov Signed-off-by: Oliver Neukum Cc: stable Acked-by: Alan Stern Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/devio.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c index 705c573d0257..a3fad4ec9870 100644 --- a/drivers/usb/core/devio.c +++ b/drivers/usb/core/devio.c @@ -1442,14 +1442,18 @@ static int proc_do_submiturb(struct usb_dev_state *ps, struct usbdevfs_urb *uurb int number_of_packets = 0; unsigned int stream_id = 0; void *buf; - - if (uurb->flags & ~(USBDEVFS_URB_ISO_ASAP | - USBDEVFS_URB_SHORT_NOT_OK | + unsigned long mask = USBDEVFS_URB_SHORT_NOT_OK | USBDEVFS_URB_BULK_CONTINUATION | USBDEVFS_URB_NO_FSBR | USBDEVFS_URB_ZERO_PACKET | - USBDEVFS_URB_NO_INTERRUPT)) - return -EINVAL; + USBDEVFS_URB_NO_INTERRUPT; + /* USBDEVFS_URB_ISO_ASAP is a special case */ + if (uurb->type == USBDEVFS_URB_TYPE_ISO) + mask |= USBDEVFS_URB_ISO_ASAP; + + if (uurb->flags & ~mask) + return -EINVAL; + if ((unsigned int)uurb->buffer_length >= USBFS_XFER_MAX) return -EINVAL; if (uurb->buffer_length > 0 && !uurb->buffer) -- GitLab From 33c309ebc797b908029fd3a0851aefe697e9b598 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Sat, 11 Nov 2017 16:31:18 +0100 Subject: [PATCH 0197/2547] USB: ulpi: fix bus-node lookup Fix bus-node lookup during registration, which ended up searching the whole device tree depth-first starting at the parent (or grand parent) rather than just matching on its children. To make things worse, the parent (or grand-parent) node could end being prematurely freed as well. Fixes: ef6a7bcfb01c ("usb: ulpi: Support device discovery via DT") Reported-by: Peter Robinson Reported-by: Stephen Boyd Cc: stable # 4.10 Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/common/ulpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/common/ulpi.c b/drivers/usb/common/ulpi.c index 8b351444cc40..9a2ab6751a23 100644 --- a/drivers/usb/common/ulpi.c +++ b/drivers/usb/common/ulpi.c @@ -180,9 +180,9 @@ static int ulpi_of_register(struct ulpi *ulpi) /* Find a ulpi bus underneath the parent or the grandparent */ parent = ulpi->dev.parent; if (parent->of_node) - np = of_find_node_by_name(parent->of_node, "ulpi"); + np = of_get_child_by_name(parent->of_node, "ulpi"); else if (parent->parent && parent->parent->of_node) - np = of_find_node_by_name(parent->parent->of_node, "ulpi"); + np = of_get_child_by_name(parent->parent->of_node, "ulpi"); if (!np) return 0; -- GitLab From 1d5a31582ef046d3b233f0da1a68ae26519b2f0a Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 7 Nov 2017 16:45:04 +0000 Subject: [PATCH 0198/2547] usb: host: fix incorrect updating of offset The variable temp is incorrectly being updated, instead it should be offset otherwise the loop just reads the same capability value and loops forever. Thanks to Alan Stern for pointing out the correct fix to my original fix. Fix also cleans up clang warning: drivers/usb/host/ehci-dbg.c:840:4: warning: Value stored to 'temp' is never read Fixes: d49d43174400 ("USB: misc ehci updates") Cc: stable Signed-off-by: Colin Ian King Acked-by: Alan Stern Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/ehci-dbg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/ehci-dbg.c b/drivers/usb/host/ehci-dbg.c index 19f00424f53e..3ed75aaa09d9 100644 --- a/drivers/usb/host/ehci-dbg.c +++ b/drivers/usb/host/ehci-dbg.c @@ -827,7 +827,7 @@ static ssize_t fill_registers_buffer(struct debug_buffer *buf) default: /* unknown */ break; } - temp = (cap >> 8) & 0xff; + offset = (cap >> 8) & 0xff; } } #endif -- GitLab From 81cf4a45360f70528f1f64ba018d61cb5767249a Mon Sep 17 00:00:00 2001 From: Masakazu Mokuno Date: Fri, 10 Nov 2017 01:25:50 +0900 Subject: [PATCH 0199/2547] USB: core: Add type-specific length check of BOS descriptors As most of BOS descriptors are longer in length than their header 'struct usb_dev_cap_header', comparing solely with it is not sufficient to avoid out-of-bounds access to BOS descriptors. This patch adds descriptor type specific length check in usb_get_bos_descriptor() to fix the issue. Signed-off-by: Masakazu Mokuno Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/config.c | 28 ++++++++++++++++++++++++---- include/uapi/linux/usb/ch9.h | 3 +++ 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/usb/core/config.c b/drivers/usb/core/config.c index da8acd980fc6..55b198ba629b 100644 --- a/drivers/usb/core/config.c +++ b/drivers/usb/core/config.c @@ -905,14 +905,25 @@ void usb_release_bos_descriptor(struct usb_device *dev) } } +static const __u8 bos_desc_len[256] = { + [USB_CAP_TYPE_WIRELESS_USB] = USB_DT_USB_WIRELESS_CAP_SIZE, + [USB_CAP_TYPE_EXT] = USB_DT_USB_EXT_CAP_SIZE, + [USB_SS_CAP_TYPE] = USB_DT_USB_SS_CAP_SIZE, + [USB_SSP_CAP_TYPE] = USB_DT_USB_SSP_CAP_SIZE(1), + [CONTAINER_ID_TYPE] = USB_DT_USB_SS_CONTN_ID_SIZE, + [USB_PTM_CAP_TYPE] = USB_DT_USB_PTM_ID_SIZE, +}; + /* Get BOS descriptor set */ int usb_get_bos_descriptor(struct usb_device *dev) { struct device *ddev = &dev->dev; struct usb_bos_descriptor *bos; struct usb_dev_cap_header *cap; + struct usb_ssp_cap_descriptor *ssp_cap; unsigned char *buffer; - int length, total_len, num, i; + int length, total_len, num, i, ssac; + __u8 cap_type; int ret; bos = kzalloc(sizeof(struct usb_bos_descriptor), GFP_KERNEL); @@ -965,7 +976,13 @@ int usb_get_bos_descriptor(struct usb_device *dev) dev->bos->desc->bNumDeviceCaps = i; break; } + cap_type = cap->bDevCapabilityType; length = cap->bLength; + if (bos_desc_len[cap_type] && length < bos_desc_len[cap_type]) { + dev->bos->desc->bNumDeviceCaps = i; + break; + } + total_len -= length; if (cap->bDescriptorType != USB_DT_DEVICE_CAPABILITY) { @@ -973,7 +990,7 @@ int usb_get_bos_descriptor(struct usb_device *dev) continue; } - switch (cap->bDevCapabilityType) { + switch (cap_type) { case USB_CAP_TYPE_WIRELESS_USB: /* Wireless USB cap descriptor is handled by wusb */ break; @@ -986,8 +1003,11 @@ int usb_get_bos_descriptor(struct usb_device *dev) (struct usb_ss_cap_descriptor *)buffer; break; case USB_SSP_CAP_TYPE: - dev->bos->ssp_cap = - (struct usb_ssp_cap_descriptor *)buffer; + ssp_cap = (struct usb_ssp_cap_descriptor *)buffer; + ssac = (le32_to_cpu(ssp_cap->bmAttributes) & + USB_SSP_SUBLINK_SPEED_ATTRIBS) + 1; + if (length >= USB_DT_USB_SSP_CAP_SIZE(ssac)) + dev->bos->ssp_cap = ssp_cap; break; case CONTAINER_ID_TYPE: dev->bos->ss_id = diff --git a/include/uapi/linux/usb/ch9.h b/include/uapi/linux/usb/ch9.h index 41a0a81b01e6..c4c79aa331bd 100644 --- a/include/uapi/linux/usb/ch9.h +++ b/include/uapi/linux/usb/ch9.h @@ -880,6 +880,8 @@ struct usb_wireless_cap_descriptor { /* Ultra Wide Band */ __u8 bReserved; } __attribute__((packed)); +#define USB_DT_USB_WIRELESS_CAP_SIZE 11 + /* USB 2.0 Extension descriptor */ #define USB_CAP_TYPE_EXT 2 @@ -1072,6 +1074,7 @@ struct usb_ptm_cap_descriptor { __u8 bDevCapabilityType; } __attribute__((packed)); +#define USB_DT_USB_PTM_ID_SIZE 3 /* * The size of the descriptor for the Sublink Speed Attribute Count * (SSAC) specified in bmAttributes[4:0]. -- GitLab From 973593a960ddac0f14f0d8877d2d0abe0afda795 Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Thu, 9 Nov 2017 13:16:46 +0100 Subject: [PATCH 0200/2547] usb: hub: Cycle HUB power when initialization fails Sometimes the USB device gets confused about the state of the initialization and the connection fails. In particular, the device thinks that it's already set up and running while the host thinks the device still needs to be configured. To work around this issue, power-cycle the hub's output to issue a sort of "reset" to the device. This makes the device restart its state machine and then the initialization succeeds. This fixes problems where the kernel reports a list of errors like this: usb 1-1.3: device not accepting address 19, error -71 The end result is a non-functioning device. After this patch, the sequence becomes like this: usb 1-1.3: new high-speed USB device number 18 using ci_hdrc usb 1-1.3: device not accepting address 18, error -71 usb 1-1.3: new high-speed USB device number 19 using ci_hdrc usb 1-1.3: device not accepting address 19, error -71 usb 1-1-port3: attempt power cycle usb 1-1.3: new high-speed USB device number 21 using ci_hdrc usb-storage 1-1.3:1.2: USB Mass Storage device detected Signed-off-by: Mike Looijmans Acked-by: Alan Stern Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/hub.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 7ccdd3d4db84..cf7bbcb9a63c 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -4948,6 +4948,15 @@ static void hub_port_connect(struct usb_hub *hub, int port1, u16 portstatus, usb_put_dev(udev); if ((status == -ENOTCONN) || (status == -ENOTSUPP)) break; + + /* When halfway through our retry count, power-cycle the port */ + if (i == (SET_CONFIG_TRIES / 2) - 1) { + dev_info(&port_dev->dev, "attempt power cycle\n"); + usb_hub_set_port_power(hdev, hub, port1, false); + msleep(2 * hub_power_on_good_delay(hub)); + usb_hub_set_port_power(hdev, hub, port1, true); + msleep(hub_power_on_good_delay(hub)); + } } if (hub->hdev->parent || !hcd->driver->port_handed_over || -- GitLab From c9d24f78268be444e803fb2bb138a2f598de9c23 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Fri, 17 Nov 2017 11:00:45 -0800 Subject: [PATCH 0201/2547] usb: build drivers/usb/common/ when USB_SUPPORT is set PHY drivers can use ULPI interfaces when CONFIG_USB (which is host side support) is not enabled, so also build drivers/usb/ when CONFIG_USB_SUPPORT is enabled so that drivers/usb/common/ is built. ERROR: "ulpi_unregister_driver" [drivers/phy/ti/phy-tusb1210.ko] undefined! ERROR: "__ulpi_register_driver" [drivers/phy/ti/phy-tusb1210.ko] undefined! ERROR: "ulpi_read" [drivers/phy/ti/phy-tusb1210.ko] undefined! ERROR: "ulpi_write" [drivers/phy/ti/phy-tusb1210.ko] undefined! ERROR: "ulpi_unregister_driver" [drivers/phy/qualcomm/phy-qcom-usb-hs.ko] undefined! ERROR: "__ulpi_register_driver" [drivers/phy/qualcomm/phy-qcom-usb-hs.ko] undefined! ERROR: "ulpi_write" [drivers/phy/qualcomm/phy-qcom-usb-hs.ko] undefined! Signed-off-by: Randy Dunlap Signed-off-by: Greg Kroah-Hartman --- drivers/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/Makefile b/drivers/Makefile index 1d034b680431..e06f7f633f73 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -105,6 +105,7 @@ obj-$(CONFIG_TC) += tc/ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_PHY) += usb/ obj-$(CONFIG_USB) += usb/ +obj-$(CONFIG_USB_SUPPORT) += usb/ obj-$(CONFIG_PCI) += usb/ obj-$(CONFIG_USB_GADGET) += usb/ obj-$(CONFIG_OF) += usb/ -- GitLab From e43a12f1793ae1fe006e26fe9327a8840a92233c Mon Sep 17 00:00:00 2001 From: Kai-Heng Feng Date: Tue, 14 Nov 2017 01:31:15 -0500 Subject: [PATCH 0202/2547] usb: quirks: Add no-lpm quirk for KY-688 USB 3.1 Type-C Hub KY-688 USB 3.1 Type-C Hub internally uses a Genesys Logic hub to connect to Realtek r8153. Similar to commit ("7496cfe5431f2 usb: quirks: Add no-lpm quirk for Moshi USB to Ethernet Adapter"), no-lpm can make r8153 ethernet work. Signed-off-by: Kai-Heng Feng Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/quirks.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c index f1dbab6f798f..a10b346b9777 100644 --- a/drivers/usb/core/quirks.c +++ b/drivers/usb/core/quirks.c @@ -146,6 +146,9 @@ static const struct usb_device_id usb_quirk_list[] = { /* appletouch */ { USB_DEVICE(0x05ac, 0x021a), .driver_info = USB_QUIRK_RESET_RESUME }, + /* Genesys Logic hub, internally used by KY-688 USB 3.1 Type-C Hub */ + { USB_DEVICE(0x05e3, 0x0612), .driver_info = USB_QUIRK_NO_LPM }, + /* Genesys Logic hub, internally used by Moshi USB to Ethernet Adapter */ { USB_DEVICE(0x05e3, 0x0616), .driver_info = USB_QUIRK_NO_LPM }, -- GitLab From 7fee72d5e8f1e7b8d8212e28291b1a0243ecf2f1 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 14 Nov 2017 19:27:22 +0100 Subject: [PATCH 0203/2547] uas: Always apply US_FL_NO_ATA_1X quirk to Seagate devices We've been adding this as a quirk on a per device basis hoping that newer disk enclosures would do better, but that has not happened, so simply apply this quirk to all Seagate devices. Signed-off-by: Hans de Goede Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/storage/uas-detect.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/storage/uas-detect.h b/drivers/usb/storage/uas-detect.h index 1fcd758a961f..3734a25e09e5 100644 --- a/drivers/usb/storage/uas-detect.h +++ b/drivers/usb/storage/uas-detect.h @@ -112,6 +112,10 @@ static int uas_use_uas_driver(struct usb_interface *intf, } } + /* All Seagate disk enclosures have broken ATA pass-through support */ + if (le16_to_cpu(udev->descriptor.idVendor) == 0x0bc2) + flags |= US_FL_NO_ATA_1X; + usb_stor_adjust_quirks(udev, &flags); if (flags & US_FL_IGNORE_UAS) { -- GitLab From f50caa9b517a2542ae9769fc17ad84110ae07c8b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 14 Nov 2017 12:40:31 +0100 Subject: [PATCH 0204/2547] debugfs: fix debugfs_real_fops() build error Some drivers use debugfs_real_fops() even when CONFIG_DEBUG_FS is disabled, which now leads to a build error: In file included from include/linux/list.h:9:0, from include/linux/wait.h:7, from include/linux/wait_bit.h:8, from include/linux/fs.h:6, from drivers/net/wireless/broadcom/b43legacy/debugfs.c:26: drivers/net/wireless/broadcom/b43legacy/debugfs.c: In function 'b43legacy_debugfs_read': drivers/net/wireless/broadcom/b43legacy/debugfs.c:224:23: error: implicit declaration of function 'debugfs_real_fops'; did you mean 'debugfs_create_bool'? [-Werror=implicit-function-declaration] My first impulse was to add another 'static inline' dummy function returning NULL for it, which would work fine. However, most callers feed the pointer into container_of(), so it seems a little dangerous here. Since all the callers are inside of a read/write file operation that gets eliminated in this configuration, so having an 'extern' declaration seems better here. If it ever gets used in a dangerous way, that will now result in a link error. Fixes: 7c8d469877b1 ("debugfs: add support for more elaborate ->d_fsdata") Cc: Jakub Kicinski Cc: Simon Horman Signed-off-by: Arnd Bergmann Signed-off-by: Greg Kroah-Hartman --- include/linux/debugfs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/debugfs.h b/include/linux/debugfs.h index f36ecc2a5712..3b0ba54cc4d5 100644 --- a/include/linux/debugfs.h +++ b/include/linux/debugfs.h @@ -216,6 +216,8 @@ static inline void debugfs_remove(struct dentry *dentry) static inline void debugfs_remove_recursive(struct dentry *dentry) { } +const struct file_operations *debugfs_real_fops(const struct file *filp); + static inline int debugfs_file_get(struct dentry *dentry) { return 0; -- GitLab From 448aa9117cfa6591c4e18cb32a0329a66b9cd3b7 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 28 Nov 2017 11:01:47 +0000 Subject: [PATCH 0205/2547] drm/i915: Enable hotplug polling after registering the outputs Previously we would enable hotplug polling on the outputs immediately upon construction. This would allow a very early hotplug event to trigger before we had finishing setting up the driver to handle it. Instead, move the output polling to the last step of registration, after we have set up all handlers, including the fbdev configuration. v2: Symmetrically turnoff the hotplug helper in unregister after the fbdev is first synchronised then finalized. This stops a late hotplug event being processed after the interrupts are disabled. Signed-off-by: Chris Wilson Cc: Daniel Vetter Cc: Ville Syrjala Cc: Maarten Lankhorst Reviewed-by: Maarten Lankhorst #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20171128110147.28654-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_drv.c | 16 ++++++++++++++-- drivers/gpu/drm/i915/intel_display.c | 5 +---- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 9c519aa4f550..1c419893e3a9 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -693,8 +693,6 @@ static int i915_load_modeset_init(struct drm_device *dev) /* Only enable hotplug handling once the fbdev is fully set up. */ intel_hpd_init(dev_priv); - drm_kms_helper_poll_init(dev); - return 0; cleanup_gem: @@ -1255,6 +1253,13 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) * cannot run before the connectors are registered. */ intel_fbdev_initial_config_async(dev); + + /* + * We need to coordinate the hotplugs with the asynchronous fbdev + * configuration, for which we use the fbdev->async_cookie. + */ + if (INTEL_INFO(dev_priv)->num_pipes) + drm_kms_helper_poll_init(dev); } /** @@ -1266,6 +1271,13 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) intel_fbdev_unregister(dev_priv); intel_audio_deinit(dev_priv); + /* + * After flushing the fbdev (incl. a late async config which will + * have delayed queuing of a hotplug event), then flush the hotplug + * events. + */ + drm_kms_helper_poll_fini(&dev_priv->drm); + intel_gpu_ips_teardown(); acpi_video_unregister(); intel_opregion_unregister(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fec267dfc062..76c75d34e799 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -15276,10 +15276,7 @@ static void intel_hpd_poll_fini(struct drm_device *dev) struct intel_connector *connector; struct drm_connector_list_iter conn_iter; - /* First disable polling... */ - drm_kms_helper_poll_fini(dev); - - /* Then kill the work that may have been queued by hpd. */ + /* Kill all the work that may have been queued by hpd. */ drm_connector_list_iter_begin(dev, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) { if (connector->modeset_retry_work.func) -- GitLab From 3bfd1300abfe3adb18e84a89d97a0e82a22124bb Mon Sep 17 00:00:00 2001 From: Matt Wilson Date: Mon, 13 Nov 2017 11:31:31 -0800 Subject: [PATCH 0206/2547] serial: 8250_pci: Add Amazon PCI serial device ID This device will be used in future Amazon EC2 instances as the primary serial port (i.e., data sent to this port will be available via the GetConsoleOuput [1] EC2 API). [1] http://docs.aws.amazon.com/AWSEC2/latest/APIReference/API_GetConsoleOutput.html Cc: stable Signed-off-by: Matt Wilson Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_pci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index b7e0e3416641..54adf8d56350 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -5135,6 +5135,9 @@ static const struct pci_device_id serial_pci_tbl[] = { { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, + /* Amazon PCI serial device */ + { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, + /* * These entries match devices with class COMMUNICATION_SERIAL, * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL -- GitLab From 0ff3ab701963a845d52337ded7eebf2d1a14fe00 Mon Sep 17 00:00:00 2001 From: Matt Redfearn Date: Wed, 22 Nov 2017 09:57:28 +0000 Subject: [PATCH 0207/2547] serial: 8250_early: Only set divisor if valid clk & baud If either uartclk or baud are 0, avoid calculating and setting a divisor based on them since the output will almost certainly be garbage. This also allows platforms such as the MIPS generic kernel, which has no way to know a valid BASE_BASE for the board it is actually booted on at compile time, to set BASE_BAUD to 0 and avoid early_8250 setting a bad divisor. This fixes a regression caused by commit 31cb9a8575ca ("earlycon: initialise baud field of earlycon device structure"), which changed the behavior of of_setup_earlycon such that it sets a baud rate in the earlycon structure where previously it was left as 0. All boards supported by the MIPS generic kernel started outputting garbage from the boot console due to an incorrect divisor being set. Fixes: 31cb9a8575ca ("earlycon: initialise baud field of earlycon device structure") Cc: stable # 4.14 Signed-off-by: Matt Redfearn Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_early.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c index 362c25ff188a..ae6a256524d8 100644 --- a/drivers/tty/serial/8250/8250_early.c +++ b/drivers/tty/serial/8250/8250_early.c @@ -122,12 +122,14 @@ static void __init init_port(struct earlycon_device *device) serial8250_early_out(port, UART_FCR, 0); /* no fifo */ serial8250_early_out(port, UART_MCR, 0x3); /* DTR + RTS */ - divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * device->baud); - c = serial8250_early_in(port, UART_LCR); - serial8250_early_out(port, UART_LCR, c | UART_LCR_DLAB); - serial8250_early_out(port, UART_DLL, divisor & 0xff); - serial8250_early_out(port, UART_DLM, (divisor >> 8) & 0xff); - serial8250_early_out(port, UART_LCR, c & ~UART_LCR_DLAB); + if (port->uartclk && device->baud) { + divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * device->baud); + c = serial8250_early_in(port, UART_LCR); + serial8250_early_out(port, UART_LCR, c | UART_LCR_DLAB); + serial8250_early_out(port, UART_DLL, divisor & 0xff); + serial8250_early_out(port, UART_DLM, (divisor >> 8) & 0xff); + serial8250_early_out(port, UART_LCR, c & ~UART_LCR_DLAB); + } } int __init early_serial8250_setup(struct earlycon_device *device, -- GitLab From eb281683621b71ab9710d9dccbbef0c2e1769c97 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 3 Nov 2017 15:30:52 +0100 Subject: [PATCH 0208/2547] serdev: ttyport: add missing receive_buf sanity checks The receive_buf tty-port callback should return the number of bytes accepted and must specifically never return a negative errno (or a value larger than the buffer size) to the tty layer. A serdev driver not providing a receive_buf callback would currently cause the flush_to_ldisc() worker to spin in a tight loop when the tty buffer pointers are incremented with -EINVAL (-22) after data has been received. A serdev driver occasionally returning a negative errno (or a too large byte count) could cause information leaks or crashes when accessing memory outside the tty buffers in consecutive callbacks. Fixes: cd6484e1830b ("serdev: Introduce new bus for serial attached devices") Cc: stable # 4.11 Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serdev/serdev-ttyport.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serdev/serdev-ttyport.c b/drivers/tty/serdev/serdev-ttyport.c index ce7ad0acee7a..09fbdd52a561 100644 --- a/drivers/tty/serdev/serdev-ttyport.c +++ b/drivers/tty/serdev/serdev-ttyport.c @@ -27,11 +27,22 @@ static int ttyport_receive_buf(struct tty_port *port, const unsigned char *cp, { struct serdev_controller *ctrl = port->client_data; struct serport *serport = serdev_controller_get_drvdata(ctrl); + int ret; if (!test_bit(SERPORT_ACTIVE, &serport->flags)) return 0; - return serdev_controller_receive_buf(ctrl, cp, count); + ret = serdev_controller_receive_buf(ctrl, cp, count); + + dev_WARN_ONCE(&ctrl->dev, ret < 0 || ret > count, + "receive_buf returns %d (count = %zu)\n", + ret, count); + if (ret < 0) + return 0; + else if (ret > count) + return count; + + return ret; } static void ttyport_write_wakeup(struct tty_port *port) -- GitLab From fd00cf81a9a84776ba58e56bd042c726dcf75cf3 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 3 Nov 2017 15:30:53 +0100 Subject: [PATCH 0209/2547] serdev: fix receive_buf return value when no callback The receive_buf callback is supposed to return the number of bytes processed and should specifically not return a negative errno. Due to missing sanity checks in the serdev tty-port controller, a driver not providing a receive_buf callback could cause the flush_to_ldisc() worker to spin in a tight loop when the tty buffer pointers are incremented with -EINVAL (-22). The missing sanity checks have now been added to the tty-port controller, but let's fix up the serdev-controller helper as well. Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- include/linux/serdev.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/serdev.h b/include/linux/serdev.h index e69402d4a8ae..d609e6dc5bad 100644 --- a/include/linux/serdev.h +++ b/include/linux/serdev.h @@ -184,7 +184,7 @@ static inline int serdev_controller_receive_buf(struct serdev_controller *ctrl, struct serdev_device *serdev = ctrl->serdev; if (!serdev || !serdev->ops->receive_buf) - return -EINVAL; + return 0; return serdev->ops->receive_buf(serdev, data, count); } -- GitLab From 8bcd4e6a8decac251d55c4377e2e67f052777ce0 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 3 Nov 2017 15:30:55 +0100 Subject: [PATCH 0210/2547] serdev: ttyport: fix NULL-deref on hangup Make sure to use a properly refcounted tty_struct in write_wake up to avoid dereferencing a NULL-pointer when a port is being hung up. Fixes: bed35c6dfa6a ("serdev: add a tty port controller driver") Cc: stable # 4.11 Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serdev/serdev-ttyport.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serdev/serdev-ttyport.c b/drivers/tty/serdev/serdev-ttyport.c index 09fbdd52a561..12cb9139073e 100644 --- a/drivers/tty/serdev/serdev-ttyport.c +++ b/drivers/tty/serdev/serdev-ttyport.c @@ -49,12 +49,19 @@ static void ttyport_write_wakeup(struct tty_port *port) { struct serdev_controller *ctrl = port->client_data; struct serport *serport = serdev_controller_get_drvdata(ctrl); + struct tty_struct *tty; + + tty = tty_port_tty_get(port); + if (!tty) + return; - if (test_and_clear_bit(TTY_DO_WRITE_WAKEUP, &port->tty->flags) && + if (test_and_clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags) && test_bit(SERPORT_ACTIVE, &serport->flags)) serdev_controller_write_wakeup(ctrl); - wake_up_interruptible_poll(&port->tty->write_wait, POLLOUT); + wake_up_interruptible_poll(&tty->write_wait, POLLOUT); + + tty_kref_put(tty); } static const struct tty_port_client_operations client_ops = { -- GitLab From 90dbad8cd6efccbdce109d5ef0724f8434a6cdde Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 3 Nov 2017 15:30:56 +0100 Subject: [PATCH 0211/2547] serdev: ttyport: fix tty locking in close Make sure to hold the tty lock as required when calling tty-driver close() (e.g. to avoid racing with hangup()). Note that the serport active flag is currently set under the lock at controller open, but really isn't protected by it. Fixes: cd6484e1830b ("serdev: Introduce new bus for serial attached devices") Signed-off-by: Johan Hovold Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serdev/serdev-ttyport.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/tty/serdev/serdev-ttyport.c b/drivers/tty/serdev/serdev-ttyport.c index 12cb9139073e..247788a16f0b 100644 --- a/drivers/tty/serdev/serdev-ttyport.c +++ b/drivers/tty/serdev/serdev-ttyport.c @@ -154,8 +154,10 @@ static void ttyport_close(struct serdev_controller *ctrl) clear_bit(SERPORT_ACTIVE, &serport->flags); + tty_lock(tty); if (tty->ops->close) tty->ops->close(tty, NULL); + tty_unlock(tty); tty_release_struct(tty, serport->tty_idx); } -- GitLab From d09220a887f70368afa79e850c95e74890c0a32d Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 27 Nov 2017 08:57:26 -0800 Subject: [PATCH 0212/2547] ARM: OMAP2+: Fix SRAM virt to phys translation for save_secure_ram_context With the CMA changes from Joonsoo Kim , it was noticed that n900 stopped booting. After investigating it turned out that n900 save_secure_ram_context does some whacky virtual to physical address translation for the SRAM data address. As we now only have minimal parts of omap3 idle code copied to SRAM, running save_secure_ram_context() in SRAM is not needed. It only gets called on PM init. And it seems there's no need to ever call this from SRAM idle code. So let's just keep save_secure_ram_context() in DDR, and pass it the physical address of the parameters. We can do everything else in omap-secure.c like we already do for other secure code. And since we don't have any documentation, I still have no clue what the values for 0, 1 and 1 for the parameters might be. If somebody has figured it out, please do send a patch to add some comments. Debugged-by: Joonsoo Kim Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap-secure.c | 19 +++++++++++++++++++ arch/arm/mach-omap2/omap-secure.h | 4 ++++ arch/arm/mach-omap2/pm.h | 4 ---- arch/arm/mach-omap2/pm34xx.c | 13 ++++--------- arch/arm/mach-omap2/sleep34xx.S | 26 ++++---------------------- 5 files changed, 31 insertions(+), 35 deletions(-) diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index 5ac122e88f67..9ff92050053c 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -73,6 +73,25 @@ phys_addr_t omap_secure_ram_mempool_base(void) return omap_secure_memblock_base; } +u32 omap3_save_secure_ram(void __iomem *addr, int size) +{ + u32 ret; + u32 param[5]; + + if (size != OMAP3_SAVE_SECURE_RAM_SZ) + return OMAP3_SAVE_SECURE_RAM_SZ; + + param[0] = 4; /* Number of arguments */ + param[1] = __pa(addr); /* Physical address for saving */ + param[2] = 0; + param[3] = 1; + param[4] = 1; + + ret = save_secure_ram_context(__pa(param)); + + return ret; +} + /** * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls * @idx: The PPA API index diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index bae263fba640..c509cde71f93 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -31,6 +31,8 @@ /* Maximum Secure memory storage size */ #define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K) +#define OMAP3_SAVE_SECURE_RAM_SZ 0x803F + /* Secure low power HAL API index */ #define OMAP4_HAL_SAVESECURERAM_INDEX 0x1a #define OMAP4_HAL_SAVEHW_INDEX 0x1b @@ -65,6 +67,8 @@ extern u32 omap_smc2(u32 id, u32 falg, u32 pargs); extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs); extern phys_addr_t omap_secure_ram_mempool_base(void); extern int omap_secure_ram_reserve_memblock(void); +extern u32 save_secure_ram_context(u32 args_pa); +extern u32 omap3_save_secure_ram(void __iomem *save_regs, int size); extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, u32 arg1, u32 arg2, u32 arg3, u32 arg4); diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index b668719b9b25..8e30772cfe32 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -81,10 +81,6 @@ extern unsigned int omap3_do_wfi_sz; /* ... and its pointer from SRAM after copy */ extern void (*omap3_do_wfi_sram)(void); -/* save_secure_ram_context function pointer and size, for copy to SRAM */ -extern int save_secure_ram_context(u32 *addr); -extern unsigned int save_secure_ram_context_sz; - extern void omap3_save_scratchpad_contents(void); #define PM_RTA_ERRATUM_i608 (1 << 0) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 841ba19d64a6..36c55547137c 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -48,6 +48,7 @@ #include "prm3xxx.h" #include "pm.h" #include "sdrc.h" +#include "omap-secure.h" #include "sram.h" #include "control.h" #include "vc.h" @@ -66,7 +67,6 @@ struct power_state { static LIST_HEAD(pwrst_list); -static int (*_omap_save_secure_sram)(u32 *addr); void (*omap3_do_wfi_sram)(void); static struct powerdomain *mpu_pwrdm, *neon_pwrdm; @@ -121,8 +121,8 @@ static void omap3_save_secure_ram_context(void) * will hang the system. */ pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); - ret = _omap_save_secure_sram((u32 *)(unsigned long) - __pa(omap3_secure_ram_storage)); + ret = omap3_save_secure_ram(omap3_secure_ram_storage, + OMAP3_SAVE_SECURE_RAM_SZ); pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); /* Following is for error tracking, it should not happen */ if (ret) { @@ -434,15 +434,10 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) * * The minimum set of functions is pushed to SRAM for execution: * - omap3_do_wfi for erratum i581 WA, - * - save_secure_ram_context for security extensions. */ void omap_push_sram_idle(void) { omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); - - if (omap_type() != OMAP2_DEVICE_TYPE_GP) - _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, - save_secure_ram_context_sz); } static void __init pm_errata_configure(void) @@ -553,7 +548,7 @@ int __init omap3_pm_init(void) clkdm_add_wkdep(neon_clkdm, mpu_clkdm); if (omap_type() != OMAP2_DEVICE_TYPE_GP) { omap3_secure_ram_storage = - kmalloc(0x803F, GFP_KERNEL); + kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL); if (!omap3_secure_ram_storage) pr_err("Memory allocation failed when allocating for secure sram context\n"); diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index fa5fd24f524c..22daf4efed68 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -93,20 +93,13 @@ ENTRY(enable_omap3630_toggle_l2_on_restore) ENDPROC(enable_omap3630_toggle_l2_on_restore) /* - * Function to call rom code to save secure ram context. This gets - * relocated to SRAM, so it can be all in .data section. Otherwise - * we need to initialize api_params separately. + * Function to call rom code to save secure ram context. + * + * r0 = physical address of the parameters */ - .data - .align 3 ENTRY(save_secure_ram_context) stmfd sp!, {r4 - r11, lr} @ save registers on stack - adr r3, api_params @ r3 points to parameters - str r0, [r3,#0x4] @ r0 has sdram address - ldr r12, high_mask - and r3, r3, r12 - ldr r12, sram_phy_addr_mask - orr r3, r3, r12 + mov r3, r0 @ physical address of parameters mov r0, #25 @ set service ID for PPA mov r12, r0 @ copy secure service ID in r12 mov r1, #0 @ set task id for ROM code in r1 @@ -120,18 +113,7 @@ ENTRY(save_secure_ram_context) nop nop ldmfd sp!, {r4 - r11, pc} - .align -sram_phy_addr_mask: - .word SRAM_BASE_P -high_mask: - .word 0xffff -api_params: - .word 0x4, 0x0, 0x0, 0x1, 0x1 ENDPROC(save_secure_ram_context) -ENTRY(save_secure_ram_context_sz) - .word . - save_secure_ram_context - - .text /* * ====================== -- GitLab From b6d6af7226465b6d11eac09d0be2ab78a4a9eb62 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Fri, 10 Nov 2017 16:56:52 +0530 Subject: [PATCH 0213/2547] ARM: AM33xx: PRM: Remove am33xx_pwrdm_read_prev_pwrst function Referring TRM Am335X series: http://www.ti.com/lit/ug/spruh73p/spruh73p.pdf The LastPowerStateEntered bitfield is present only for PM_CEFUSE domain. This is not present in any of the other power domains. Hence remove the generic am33xx_pwrdm_read_prev_pwrst hook which wrongly reads the reserved bit fields for all the other power domains. Reading the reserved bits leads to wrongly interpreting the low power transitions for various power domains that do not have the LastPowerStateEntered field. The pm debug counters values are wrong currently as we are incrementing them based on the reserved bits. Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/prm33xx.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c index d2c5bcabdbeb..ebaf80d72a10 100644 --- a/arch/arm/mach-omap2/prm33xx.c +++ b/arch/arm/mach-omap2/prm33xx.c @@ -176,17 +176,6 @@ static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) return v; } -static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); - v &= AM33XX_LASTPOWERSTATEENTERED_MASK; - v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT; - - return v; -} - static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) { am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK, @@ -357,7 +346,6 @@ struct pwrdm_ops am33xx_pwrdm_operations = { .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst, - .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst, .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst, .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst, .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst, -- GitLab From e9a9bb4e4779ca74cb52a6e2f8acbc0881d3bb18 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 14 Nov 2017 09:06:48 +0300 Subject: [PATCH 0214/2547] ARM: OMAP2+: Missing error code in omap_device_build() We need to set the error code if omap_device_alloc() fails. Signed-off-by: Dan Carpenter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_device.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index d45cbfdb4be6..2e91eb8ab33c 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -516,8 +516,10 @@ struct platform_device __init *omap_device_build(const char *pdev_name, goto odbs_exit1; od = omap_device_alloc(pdev, &oh, 1); - if (IS_ERR(od)) + if (IS_ERR(od)) { + ret = PTR_ERR(od); goto odbs_exit1; + } ret = platform_device_add_data(pdev, pdata, pdata_len); if (ret) -- GitLab From cf87634c8b24e24bf379b8c6807c8b0fb5f23567 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 17 Nov 2017 08:56:58 -0800 Subject: [PATCH 0215/2547] ARM: dts: Fix omap4 hang with GPS connected to USB by using wakeupgen There's been a reproducable USB OHCI/EHCI cpuidle related hang on omap4 for a while that happens after about 20 - 40 minutes on an idle system with some data feeding device being connected, like a USB GPS device or a cellular modem. This issue happens in cpuidle states C2 and C3 and does not happen if cpuidle is limited to C1 state only. The symptoms are that the whole system hangs and never wakes up from idle, and if a watchdog is configured the system reboots after a while. Turns out that OHCI/EHCI devices on omap4 are trying to use the GIC interrupt controller directly as a parent instead of the WUGEN. We need to pass the interrupts through WUGEN to GIC to provide the wakeup events for the processor. Let's fix the issue by removing the gic interrupt-parent and use the default interrupt-parent wakeupgen instead. Note that omap5.dtsi had this already fixes earlier by commit 7136d457f365 ("ARM: omap: convert wakeupgen to stacked domains") but we somehow missed omap4 at that point. Fixes: 7136d457f365 ("ARM: omap: convert wakeupgen to stacked domains") Cc: Dave Gerlach Cc: Nishanth Menon Cc: Marc Zyngier Cc: Sebastian Reichel Reviewed-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 1dc5a76b3c71..d24291ed9f6a 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -1081,14 +1081,12 @@ usbhsohci: ohci@4a064800 { compatible = "ti,ohci-omap3"; reg = <0x4a064800 0x400>; - interrupt-parent = <&gic>; interrupts = ; }; usbhsehci: ehci@4a064c00 { compatible = "ti,ehci-omap"; reg = <0x4a064c00 0x400>; - interrupt-parent = <&gic>; interrupts = ; }; }; -- GitLab From 3c18bbf3d11d2005da08b57ff26f44ff1c2b12d0 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 31 Oct 2017 13:42:13 -0500 Subject: [PATCH 0216/2547] ARM: dts: logicpd-som-lv: Fix gpmc addresses for NAND and enet This patch fixes and issue where the NAND and GPMC based ethernet controller stopped working. This also updates the GPMC settings to be consistent with the Logic PD Torpedo development from the commit listed above. Fixes: 44e4716499b8 ("ARM: dts: omap3: Fix NAND device nodes") Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts | 3 ++- arch/arm/boot/dts/logicpd-som-lv.dtsi | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts index 38faa90007d7..2fa5eb4bd402 100644 --- a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts @@ -72,7 +72,8 @@ }; &gpmc { - ranges = <1 0 0x08000000 0x1000000>; /* CS1: 16MB for LAN9221 */ + ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ + 1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */ ethernet@gpmc { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi index 26cce4d18405..c5edc7fe4837 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -37,7 +37,7 @@ }; &gpmc { - ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */ + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { compatible = "ti,omap2-nand"; -- GitLab From 52cf373c37a684f8fc279d541307fad39d206376 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 28 Nov 2017 13:59:25 +0100 Subject: [PATCH 0217/2547] cgroup: properly init u64_stats Lockdep complains that the stats update is trying to register a non-static key. This is because u64_stats are using a seqlock on 32bit arches, which needs to be initialized before usage. Fixes: 041cd640b2f3 (cgroup: Implement cgroup2 basic CPU usage accounting) Signed-off-by: Lucas Stach Signed-off-by: Tejun Heo --- kernel/cgroup/stat.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/kernel/cgroup/stat.c b/kernel/cgroup/stat.c index 133b465691d6..1e111dd455c4 100644 --- a/kernel/cgroup/stat.c +++ b/kernel/cgroup/stat.c @@ -296,8 +296,12 @@ int cgroup_stat_init(struct cgroup *cgrp) } /* ->updated_children list is self terminated */ - for_each_possible_cpu(cpu) - cgroup_cpu_stat(cgrp, cpu)->updated_children = cgrp; + for_each_possible_cpu(cpu) { + struct cgroup_cpu_stat *cstat = cgroup_cpu_stat(cgrp, cpu); + + cstat->updated_children = cgrp; + u64_stats_init(&cstat->sync); + } prev_cputime_init(&cgrp->stat.prev_cputime); -- GitLab From 5a244727f428a06634f22bb890e78024ab0c89f3 Mon Sep 17 00:00:00 2001 From: William Breathitt Gray Date: Wed, 8 Nov 2017 10:23:11 -0500 Subject: [PATCH 0218/2547] isa: Prevent NULL dereference in isa_bus driver callbacks The isa_driver structure for an isa_bus device is stored in the device platform_data member of the respective device structure. This platform_data member may be reset to NULL if isa_driver match callback for the device fails, indicating a device unsupported by the ISA driver. This patch fixes a possible NULL pointer dereference if one of the isa_driver callbacks to attempted for an unsupported device. This error should not occur in practice since ISA devices are typically manually configured and loaded by the users, but we may as well prevent this error from popping up for the 0day testers. Fixes: a5117ba7da37 ("[PATCH] Driver model: add ISA bus") Signed-off-by: William Breathitt Gray Cc: stable Acked-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- drivers/base/isa.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/base/isa.c b/drivers/base/isa.c index cd6ccdcf9df0..372d10af2600 100644 --- a/drivers/base/isa.c +++ b/drivers/base/isa.c @@ -39,7 +39,7 @@ static int isa_bus_probe(struct device *dev) { struct isa_driver *isa_driver = dev->platform_data; - if (isa_driver->probe) + if (isa_driver && isa_driver->probe) return isa_driver->probe(dev, to_isa_dev(dev)->id); return 0; @@ -49,7 +49,7 @@ static int isa_bus_remove(struct device *dev) { struct isa_driver *isa_driver = dev->platform_data; - if (isa_driver->remove) + if (isa_driver && isa_driver->remove) return isa_driver->remove(dev, to_isa_dev(dev)->id); return 0; @@ -59,7 +59,7 @@ static void isa_bus_shutdown(struct device *dev) { struct isa_driver *isa_driver = dev->platform_data; - if (isa_driver->shutdown) + if (isa_driver && isa_driver->shutdown) isa_driver->shutdown(dev, to_isa_dev(dev)->id); } @@ -67,7 +67,7 @@ static int isa_bus_suspend(struct device *dev, pm_message_t state) { struct isa_driver *isa_driver = dev->platform_data; - if (isa_driver->suspend) + if (isa_driver && isa_driver->suspend) return isa_driver->suspend(dev, to_isa_dev(dev)->id, state); return 0; @@ -77,7 +77,7 @@ static int isa_bus_resume(struct device *dev) { struct isa_driver *isa_driver = dev->platform_data; - if (isa_driver->resume) + if (isa_driver && isa_driver->resume) return isa_driver->resume(dev, to_isa_dev(dev)->id); return 0; -- GitLab From 0946b2fb38fdb6585a5ac3ca84ac73924f645952 Mon Sep 17 00:00:00 2001 From: "Robin H. Johnson" Date: Thu, 16 Nov 2017 14:36:12 -0800 Subject: [PATCH 0219/2547] firmware: cleanup FIRMWARE_IN_KERNEL message The help for FIRMWARE_IN_KERNEL still references the firmware_install command that was recently removed by commit 5620a0d1aacd ("firmware: delete in-kernel firmware"). Clean up the message to direct the user to their distribution's linux-firmware package, and remove any reference to firmware being included in the kernel source tree. Fixes: 5620a0d1aacd ("firmware: delete in-kernel firmware"). Cc: Masahiro Yamada Cc: stable Cc: David Woodhouse Signed-off-by: Robin H. Johnson Signed-off-by: Greg Kroah-Hartman --- drivers/base/Kconfig | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig index 2f6614c9a229..bdc87907d6a1 100644 --- a/drivers/base/Kconfig +++ b/drivers/base/Kconfig @@ -91,22 +91,23 @@ config FIRMWARE_IN_KERNEL depends on FW_LOADER default y help - The kernel source tree includes a number of firmware 'blobs' - that are used by various drivers. The recommended way to - use these is to run "make firmware_install", which, after - converting ihex files to binary, copies all of the needed - binary files in firmware/ to /lib/firmware/ on your system so - that they can be loaded by userspace helpers on request. + Various drivers in the kernel source tree may require firmware, + which is generally available in your distribution's linux-firmware + package. + + The linux-firmware package should install firmware into + /lib/firmware/ on your system, so they can be loaded by userspace + helpers on request. Enabling this option will build each required firmware blob - into the kernel directly, where request_firmware() will find - them without having to call out to userspace. This may be - useful if your root file system requires a device that uses - such firmware and do not wish to use an initrd. + specified by EXTRA_FIRMWARE into the kernel directly, where + request_firmware() will find them without having to call out to + userspace. This may be useful if your root file system requires a + device that uses such firmware and you do not wish to use an + initrd. This single option controls the inclusion of firmware for - every driver that uses request_firmware() and ships its - firmware in the kernel source tree, which avoids a + every driver that uses request_firmware(), which avoids a proliferation of 'Include firmware for xxx device' options. Say 'N' and let firmware be loaded from userspace. -- GitLab From c8ec2041f549e7f2dee0c34d25381be6f7805f99 Mon Sep 17 00:00:00 2001 From: Matt Redfearn Date: Tue, 28 Nov 2017 15:22:20 +0000 Subject: [PATCH 0220/2547] MIPS: Add custom serial.h with BASE_BAUD override for generic kernel Add a custom serial.h header for MIPS, allowing platforms to override the asm-generic version if required. The generic platform uses this header to set BASE_BAUD to 0. The generic platform supports multiple boards, which may have different UART clocks. Also one of the boards supported is the Boston FPGA board, where the UART clock depends on the loaded FPGA bitfile. As such there is no way that the generic kernel can set a compile time default BASE_BAUD. Commit 31cb9a8575ca ("earlycon: initialise baud field of earlycon device structure") changed the behavior of of_setup_earlycon such that any baud rate set in the device tree is now set in the earlycon structure. The UART driver will then calculate a divisor based on BASE_BAUD and set it. With MIPS generic kernels this resulted in garbage output due to the incorrect uart clock rate being used to calculate a divisor. This commit, combined with "serial: 8250_early: Only set divisor if valid clk & baud" prevents the earlycon code setting a bad divisor and restores earlycon output. Fixes: 31cb9a8575ca ("earlycon: initialise baud field of earlycon device structure") Cc: stable # 4.14 Signed-off-by: Matt Redfearn Signed-off-by: Greg Kroah-Hartman --- arch/mips/include/asm/Kbuild | 1 - arch/mips/include/asm/serial.h | 22 ++++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 arch/mips/include/asm/serial.h diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild index 7c8aab23bce8..b1f66699677d 100644 --- a/arch/mips/include/asm/Kbuild +++ b/arch/mips/include/asm/Kbuild @@ -16,7 +16,6 @@ generic-y += qrwlock.h generic-y += qspinlock.h generic-y += sections.h generic-y += segment.h -generic-y += serial.h generic-y += trace_clock.h generic-y += unaligned.h generic-y += user.h diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h new file mode 100644 index 000000000000..1d830c6666c2 --- /dev/null +++ b/arch/mips/include/asm/serial.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2017 MIPS Tech, LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef __ASM__SERIAL_H +#define __ASM__SERIAL_H + +#ifdef CONFIG_MIPS_GENERIC +/* + * Generic kernels cannot know a correct value for all platforms at + * compile time. Set it to 0 to prevent 8250_early using it + */ +#define BASE_BAUD 0 +#else +#include +#endif + +#endif /* __ASM__SERIAL_H */ -- GitLab From fb2c445277e7b0b4ffe10de8114bad4eccaca948 Mon Sep 17 00:00:00 2001 From: Martijn Coenen Date: Mon, 13 Nov 2017 10:06:08 +0100 Subject: [PATCH 0221/2547] ANDROID: binder: fix transaction leak. If a call to put_user() fails, we failed to properly free a transaction and send a failed reply (if necessary). Signed-off-by: Martijn Coenen Cc: stable # 4.14 Signed-off-by: Greg Kroah-Hartman --- drivers/android/binder.c | 40 +++++++++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 9 deletions(-) diff --git a/drivers/android/binder.c b/drivers/android/binder.c index a73596a4f804..bccec9de0533 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -1947,6 +1947,26 @@ static void binder_send_failed_reply(struct binder_transaction *t, } } +/** + * binder_cleanup_transaction() - cleans up undelivered transaction + * @t: transaction that needs to be cleaned up + * @reason: reason the transaction wasn't delivered + * @error_code: error to return to caller (if synchronous call) + */ +static void binder_cleanup_transaction(struct binder_transaction *t, + const char *reason, + uint32_t error_code) +{ + if (t->buffer->target_node && !(t->flags & TF_ONE_WAY)) { + binder_send_failed_reply(t, error_code); + } else { + binder_debug(BINDER_DEBUG_DEAD_TRANSACTION, + "undelivered transaction %d, %s\n", + t->debug_id, reason); + binder_free_transaction(t); + } +} + /** * binder_validate_object() - checks for a valid metadata object in a buffer. * @buffer: binder_buffer that we're parsing. @@ -4015,12 +4035,20 @@ static int binder_thread_read(struct binder_proc *proc, if (put_user(cmd, (uint32_t __user *)ptr)) { if (t_from) binder_thread_dec_tmpref(t_from); + + binder_cleanup_transaction(t, "put_user failed", + BR_FAILED_REPLY); + return -EFAULT; } ptr += sizeof(uint32_t); if (copy_to_user(ptr, &tr, sizeof(tr))) { if (t_from) binder_thread_dec_tmpref(t_from); + + binder_cleanup_transaction(t, "copy_to_user failed", + BR_FAILED_REPLY); + return -EFAULT; } ptr += sizeof(tr); @@ -4090,15 +4118,9 @@ static void binder_release_work(struct binder_proc *proc, struct binder_transaction *t; t = container_of(w, struct binder_transaction, work); - if (t->buffer->target_node && - !(t->flags & TF_ONE_WAY)) { - binder_send_failed_reply(t, BR_DEAD_REPLY); - } else { - binder_debug(BINDER_DEBUG_DEAD_TRANSACTION, - "undelivered transaction %d\n", - t->debug_id); - binder_free_transaction(t); - } + + binder_cleanup_transaction(t, "process died.", + BR_DEAD_REPLY); } break; case BINDER_WORK_RETURN_ERROR: { struct binder_error *e = container_of( -- GitLab From 7fa32e5ec28b1609abc0b797b58267f725fc3964 Mon Sep 17 00:00:00 2001 From: "K. Y. Srinivasan" Date: Tue, 14 Nov 2017 06:53:33 -0700 Subject: [PATCH 0222/2547] Drivers: hv: vmbus: Fix a rescind issue The current rescind processing code will not correctly handle the case where the host immediately rescinds a channel that has been offerred. In this case, we could be blocked in the open call and since the channel is rescinded, the host will not respond and we could be blocked forever in the vmbus open call.i Fix this problem. Signed-off-by: K. Y. Srinivasan Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/hv/channel.c | 10 ++++++++-- drivers/hv/channel_mgmt.c | 7 ++++--- include/linux/hyperv.h | 1 + 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/hv/channel.c b/drivers/hv/channel.c index 19f0cf37e0ed..ba0a092ae085 100644 --- a/drivers/hv/channel.c +++ b/drivers/hv/channel.c @@ -659,22 +659,28 @@ void vmbus_close(struct vmbus_channel *channel) */ return; } - mutex_lock(&vmbus_connection.channel_mutex); /* * Close all the sub-channels first and then close the * primary channel. */ list_for_each_safe(cur, tmp, &channel->sc_list) { cur_channel = list_entry(cur, struct vmbus_channel, sc_list); - vmbus_close_internal(cur_channel); if (cur_channel->rescind) { + wait_for_completion(&cur_channel->rescind_event); + mutex_lock(&vmbus_connection.channel_mutex); + vmbus_close_internal(cur_channel); hv_process_channel_removal( cur_channel->offermsg.child_relid); + } else { + mutex_lock(&vmbus_connection.channel_mutex); + vmbus_close_internal(cur_channel); } + mutex_unlock(&vmbus_connection.channel_mutex); } /* * Now close the primary. */ + mutex_lock(&vmbus_connection.channel_mutex); vmbus_close_internal(channel); mutex_unlock(&vmbus_connection.channel_mutex); } diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c index ec5454f3f4a6..c21020b69114 100644 --- a/drivers/hv/channel_mgmt.c +++ b/drivers/hv/channel_mgmt.c @@ -333,6 +333,7 @@ static struct vmbus_channel *alloc_channel(void) return NULL; spin_lock_init(&channel->lock); + init_completion(&channel->rescind_event); INIT_LIST_HEAD(&channel->sc_list); INIT_LIST_HEAD(&channel->percpu_list); @@ -898,6 +899,7 @@ static void vmbus_onoffer_rescind(struct vmbus_channel_message_header *hdr) /* * Now wait for offer handling to complete. */ + vmbus_rescind_cleanup(channel); while (READ_ONCE(channel->probe_done) == false) { /* * We wait here until any channel offer is currently @@ -913,7 +915,6 @@ static void vmbus_onoffer_rescind(struct vmbus_channel_message_header *hdr) if (channel->device_obj) { if (channel->chn_rescind_callback) { channel->chn_rescind_callback(channel); - vmbus_rescind_cleanup(channel); return; } /* @@ -922,7 +923,6 @@ static void vmbus_onoffer_rescind(struct vmbus_channel_message_header *hdr) */ dev = get_device(&channel->device_obj->device); if (dev) { - vmbus_rescind_cleanup(channel); vmbus_device_unregister(channel->device_obj); put_device(dev); } @@ -936,13 +936,14 @@ static void vmbus_onoffer_rescind(struct vmbus_channel_message_header *hdr) * 2. Then close the primary channel. */ mutex_lock(&vmbus_connection.channel_mutex); - vmbus_rescind_cleanup(channel); if (channel->state == CHANNEL_OPEN_STATE) { /* * The channel is currently not open; * it is safe for us to cleanup the channel. */ hv_process_channel_removal(rescind->child_relid); + } else { + complete(&channel->rescind_event); } mutex_unlock(&vmbus_connection.channel_mutex); } diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index f3e97c5f94c9..6c9336626592 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -708,6 +708,7 @@ struct vmbus_channel { u8 monitor_bit; bool rescind; /* got rescind msg */ + struct completion rescind_event; u32 ringbuffer_gpadlhandle; -- GitLab From 297d6b6e56c2977fc504c61bbeeaa21296923f89 Mon Sep 17 00:00:00 2001 From: Paul Meyer Date: Tue, 14 Nov 2017 13:06:47 -0700 Subject: [PATCH 0223/2547] hv: kvp: Avoid reading past allocated blocks from KVP file While reading in more than one block (50) of KVP records, the allocation goes per block, but the reads used the total number of allocated records (without resetting the pointer/stream). This causes the records buffer to overrun when the refresh reads more than one block over the previous capacity (e.g. reading more than 100 KVP records whereas the in-memory database was empty before). Fix this by reading the correct number of KVP records from file each time. Signed-off-by: Paul Meyer Signed-off-by: Long Li Cc: stable@vger.kernel.org Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- tools/hv/hv_kvp_daemon.c | 70 ++++++++-------------------------------- 1 file changed, 14 insertions(+), 56 deletions(-) diff --git a/tools/hv/hv_kvp_daemon.c b/tools/hv/hv_kvp_daemon.c index eaa3bec273c8..4c99c57736ce 100644 --- a/tools/hv/hv_kvp_daemon.c +++ b/tools/hv/hv_kvp_daemon.c @@ -193,11 +193,14 @@ static void kvp_update_mem_state(int pool) for (;;) { readp = &record[records_read]; records_read += fread(readp, sizeof(struct kvp_record), - ENTRIES_PER_BLOCK * num_blocks, - filep); + ENTRIES_PER_BLOCK * num_blocks - records_read, + filep); if (ferror(filep)) { - syslog(LOG_ERR, "Failed to read file, pool: %d", pool); + syslog(LOG_ERR, + "Failed to read file, pool: %d; error: %d %s", + pool, errno, strerror(errno)); + kvp_release_lock(pool); exit(EXIT_FAILURE); } @@ -210,6 +213,7 @@ static void kvp_update_mem_state(int pool) if (record == NULL) { syslog(LOG_ERR, "malloc failed"); + kvp_release_lock(pool); exit(EXIT_FAILURE); } continue; @@ -224,15 +228,11 @@ static void kvp_update_mem_state(int pool) fclose(filep); kvp_release_lock(pool); } + static int kvp_file_init(void) { int fd; - FILE *filep; - size_t records_read; char *fname; - struct kvp_record *record; - struct kvp_record *readp; - int num_blocks; int i; int alloc_unit = sizeof(struct kvp_record) * ENTRIES_PER_BLOCK; @@ -246,61 +246,19 @@ static int kvp_file_init(void) for (i = 0; i < KVP_POOL_COUNT; i++) { fname = kvp_file_info[i].fname; - records_read = 0; - num_blocks = 1; sprintf(fname, "%s/.kvp_pool_%d", KVP_CONFIG_LOC, i); fd = open(fname, O_RDWR | O_CREAT | O_CLOEXEC, 0644 /* rw-r--r-- */); if (fd == -1) return 1; - - filep = fopen(fname, "re"); - if (!filep) { - close(fd); - return 1; - } - - record = malloc(alloc_unit * num_blocks); - if (record == NULL) { - fclose(filep); - close(fd); - return 1; - } - for (;;) { - readp = &record[records_read]; - records_read += fread(readp, sizeof(struct kvp_record), - ENTRIES_PER_BLOCK, - filep); - - if (ferror(filep)) { - syslog(LOG_ERR, "Failed to read file, pool: %d", - i); - exit(EXIT_FAILURE); - } - - if (!feof(filep)) { - /* - * We have more data to read. - */ - num_blocks++; - record = realloc(record, alloc_unit * - num_blocks); - if (record == NULL) { - fclose(filep); - close(fd); - return 1; - } - continue; - } - break; - } kvp_file_info[i].fd = fd; - kvp_file_info[i].num_blocks = num_blocks; - kvp_file_info[i].records = record; - kvp_file_info[i].num_records = records_read; - fclose(filep); - + kvp_file_info[i].num_blocks = 1; + kvp_file_info[i].records = malloc(alloc_unit); + if (kvp_file_info[i].records == NULL) + return 1; + kvp_file_info[i].num_records = 0; + kvp_update_mem_state(i); } return 0; -- GitLab From 811d7e0215fb738fb9a9f0bcb1276516ad161ed1 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Wed, 15 Nov 2017 13:00:43 -0800 Subject: [PATCH 0224/2547] firmware: vpd: Destroy vpd sections in remove function vpd sections are initialized during probe and thus should be destroyed in the remove function. Fixes: 049a59db34eb ("firmware: Google VPD sysfs driver") Cc: stable Signed-off-by: Guenter Roeck Reviewed-by: Dmitry Torokhov Tested-by: Randy Dunlap Signed-off-by: Greg Kroah-Hartman --- drivers/firmware/google/vpd.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/google/vpd.c b/drivers/firmware/google/vpd.c index 35e553b3b190..84217172297b 100644 --- a/drivers/firmware/google/vpd.c +++ b/drivers/firmware/google/vpd.c @@ -298,8 +298,17 @@ static int vpd_probe(struct platform_device *pdev) return vpd_sections_init(entry.cbmem_addr); } +static int vpd_remove(struct platform_device *pdev) +{ + vpd_section_destroy(&ro_vpd); + vpd_section_destroy(&rw_vpd); + + return 0; +} + static struct platform_driver vpd_driver = { .probe = vpd_probe, + .remove = vpd_remove, .driver = { .name = "vpd", }, @@ -324,8 +333,6 @@ static int __init vpd_platform_init(void) static void __exit vpd_platform_exit(void) { - vpd_section_destroy(&ro_vpd); - vpd_section_destroy(&rw_vpd); kobject_put(vpd_kobj); } -- GitLab From e4b28b3c3a405b251fa25db58abe1512814a680a Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Wed, 15 Nov 2017 13:00:44 -0800 Subject: [PATCH 0225/2547] firmware: vpd: Tie firmware kobject to device lifetime It doesn't make sense to have /sys/firmware/vpd if the device is not instantiated, so tie its lifetime to the device. Fixes: 049a59db34eb ("firmware: Google VPD sysfs driver") Signed-off-by: Guenter Roeck Cc: stable Reviewed-by: Dmitry Torokhov Tested-by: Randy Dunlap Signed-off-by: Greg Kroah-Hartman --- drivers/firmware/google/vpd.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/firmware/google/vpd.c b/drivers/firmware/google/vpd.c index 84217172297b..942e358efa60 100644 --- a/drivers/firmware/google/vpd.c +++ b/drivers/firmware/google/vpd.c @@ -295,7 +295,17 @@ static int vpd_probe(struct platform_device *pdev) if (ret) return ret; - return vpd_sections_init(entry.cbmem_addr); + vpd_kobj = kobject_create_and_add("vpd", firmware_kobj); + if (!vpd_kobj) + return -ENOMEM; + + ret = vpd_sections_init(entry.cbmem_addr); + if (ret) { + kobject_put(vpd_kobj); + return ret; + } + + return 0; } static int vpd_remove(struct platform_device *pdev) @@ -303,6 +313,8 @@ static int vpd_remove(struct platform_device *pdev) vpd_section_destroy(&ro_vpd); vpd_section_destroy(&rw_vpd); + kobject_put(vpd_kobj); + return 0; } @@ -322,10 +334,6 @@ static int __init vpd_platform_init(void) if (IS_ERR(pdev)) return PTR_ERR(pdev); - vpd_kobj = kobject_create_and_add("vpd", firmware_kobj); - if (!vpd_kobj) - return -ENOMEM; - platform_driver_register(&vpd_driver); return 0; @@ -333,7 +341,6 @@ static int __init vpd_platform_init(void) static void __exit vpd_platform_exit(void) { - kobject_put(vpd_kobj); } module_init(vpd_platform_init); -- GitLab From 0631fb8b027f5968c2f5031f0b3ff7be3e4bebcc Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Wed, 15 Nov 2017 13:00:45 -0800 Subject: [PATCH 0226/2547] firmware: vpd: Fix platform driver and device registration/unregistration The driver exit function needs to unregister both platform device and driver. Also, during registration, register driver first and perform error checks. Fixes: 049a59db34eb ("firmware: Google VPD sysfs driver") Signed-off-by: Guenter Roeck Cc: stable Tested-by: Randy Dunlap Reviewed-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/firmware/google/vpd.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/firmware/google/vpd.c b/drivers/firmware/google/vpd.c index 942e358efa60..e4b40f2b4627 100644 --- a/drivers/firmware/google/vpd.c +++ b/drivers/firmware/google/vpd.c @@ -326,21 +326,29 @@ static struct platform_driver vpd_driver = { }, }; +static struct platform_device *vpd_pdev; + static int __init vpd_platform_init(void) { - struct platform_device *pdev; + int ret; - pdev = platform_device_register_simple("vpd", -1, NULL, 0); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); + ret = platform_driver_register(&vpd_driver); + if (ret) + return ret; - platform_driver_register(&vpd_driver); + vpd_pdev = platform_device_register_simple("vpd", -1, NULL, 0); + if (IS_ERR(vpd_pdev)) { + platform_driver_unregister(&vpd_driver); + return PTR_ERR(vpd_pdev); + } return 0; } static void __exit vpd_platform_exit(void) { + platform_device_unregister(vpd_pdev); + platform_driver_unregister(&vpd_driver); } module_init(vpd_platform_init); -- GitLab From cd7594ac3281722cb8f10d6f6c7e4287747c7a9d Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 31 Oct 2017 13:45:59 -0500 Subject: [PATCH 0227/2547] ARM: dts: logicpd-somlv: Fix wl127x pinmux The pin assignment for the wl127x interrupt was incorrect. I am not sure how this every worked. This also eliminates a conflict with the SMC911x ethernet driver and properly moves pinmuxes for the related gpio to omap3_pmx_wkup from omap3_pmx_core. Fixes: ab8dd3aed011 ("ARM: DTS: Add minimal Support for Logic PD DM3730 SOM-LV") Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/logicpd-som-lv.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi index c5edc7fe4837..4f2c5ec75714 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -121,7 +121,7 @@ &mmc3 { interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>; - pinctrl-0 = <&mmc3_pins>; + pinctrl-0 = <&mmc3_pins &wl127x_gpio>; pinctrl-names = "default"; vmmc-supply = <&wl12xx_vmmc>; non-removable; @@ -132,8 +132,8 @@ wlcore: wlcore@2 { compatible = "ti,wl1273"; reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */ + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 2 */ ref-clock-frequency = <26000000>; }; }; @@ -157,8 +157,6 @@ OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ - OMAP3_CORE1_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ >; @@ -228,6 +226,12 @@ OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ >; }; + wl127x_gpio: pinmux_wl127x_gpio_pin { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ + >; + }; }; &omap3_pmx_core2 { -- GitLab From 627395a6f8091c0aa18f49dca7df59ba3ec147ef Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 1 Nov 2017 11:03:31 +0200 Subject: [PATCH 0228/2547] ARM: dts: am4372: Correct the interrupts_properties of McASP Fixes the following warnings: arch/arm/boot/dts/am437x-cm-t43.dtb: Warning (interrupts_property): interrupts size is (8), expected multiple of 12 in /ocp@44000000/mcasp@48038000 arch/arm/boot/dts/am437x-cm-t43.dtb: Warning (interrupts_property): interrupts size is (8), expected multiple of 12 in /ocp@44000000/mcasp@4803C000 Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index e5b061469bf8..4714a59fd86d 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -927,7 +927,8 @@ reg = <0x48038000 0x2000>, <0x46000000 0x400000>; reg-names = "mpu", "dat"; - interrupts = <80>, <81>; + interrupts = , + ; interrupt-names = "tx", "rx"; status = "disabled"; dmas = <&edma 8 2>, @@ -941,7 +942,8 @@ reg = <0x4803C000 0x2000>, <0x46400000 0x400000>; reg-names = "mpu", "dat"; - interrupts = <82>, <83>; + interrupts = , + ; interrupt-names = "tx", "rx"; status = "disabled"; dmas = <&edma 10 2>, -- GitLab From ca41e244517d6d3f1600c229ff7ca615049c1e9c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 1 Nov 2017 11:03:40 +0200 Subject: [PATCH 0229/2547] ARM: dts: am437x-cm-t43: Correct the dmas property of spi0 The DMA binding for eDMA needs 2 parameters, not 1. The second, missing parameter is the tptc to be used for the channel. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-cm-t43.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index 9e92d480576b..3b9a94c274a7 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -301,8 +301,8 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - dmas = <&edma 16 - &edma 17>; + dmas = <&edma 16 0 + &edma 17 0>; dma-names = "tx0", "rx0"; flash: w25q64cvzpig@0 { -- GitLab From 00a797225e53a4f488ab725e0b438c2970aa41d7 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 28 Nov 2017 10:55:15 +0000 Subject: [PATCH 0230/2547] drm/i915/pmu: Return -EINVAL when selecting the inactive CPU In commit 0426c0465461 ("drm/i915/pmu: Only allow running on a single CPU") I attempted to clarify the CPU hotplug logic in our PMU implementation, but missed that a more logical error to return, when attempting to initialize an event on a currently inactive CPU, is -EINVAL rather than -ENODEV. This is because i915 PMU explicitly disallows running counters on more than one CPU at a time, and is not reporting that the requested CPU does not exist, or is off-line. Signed-off-by: Tvrtko Ursulin Reported-by: Chris Wilson Cc: Chris Wilson Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171128105515.21998-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 3357b690ce90..1c0ee9d68b04 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -338,7 +338,7 @@ static int i915_pmu_event_init(struct perf_event *event) /* only allow running on one cpu at a time */ if (!cpumask_test_cpu(event->cpu, &i915_pmu_cpumask)) - return -ENODEV; + return -EINVAL; if (is_engine_event(event)) { ret = engine_event_init(event); -- GitLab From 555b4ec4d589eb0fcdf9d7b4b05a71984dbcaeee Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Fri, 3 Nov 2017 15:13:29 -0300 Subject: [PATCH 0231/2547] perf evlist: Set the correct idx when adding dummy events The evsel->idx field is used mainly to access the right bucket in per-event arrays such as the annotation ones, but also to set evsel->tracking, that in turn will decide what of the events will ask for PERF_RECORD_{MMAP,COMM,EXEC} to be generated, i.e. which perf_event_attr will have its mmap, etc fields set. When we were adding the "dummy" event using perf_evlist__add_dummy() we were not setting it correctly, which could result in multiple tracking events. Now that I'll try using a dummy event to be the tracking one when using 'perf record --delay', i.e. when we process the --delay setting we may already have the evlist set up, like with: perf record -e cycles,instructions --delay 1000 ./workload We will need to add a "dummy" event, then reset evsel->tracking for the first event, "cycles", and set it instead to the dummy one, and also setting its attr.enable_on_exec, so that we get the PERF_RECORD_MMAP, etc metadata events while waiting to enable the explicitely requested events, so lets get this straight and set the right evsel->idx. Cc: Adrian Hunter Cc: Bram Stolk Cc: David Ahern Cc: Jiri Olsa Cc: Namhyung Kim Cc: Wang Nan Link: http://lkml.kernel.org/n/tip-nrdfchshqxf7diszhxcecqb9@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evlist.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c index c6c891e154a6..ccb749f9a83f 100644 --- a/tools/perf/util/evlist.c +++ b/tools/perf/util/evlist.c @@ -257,7 +257,7 @@ int perf_evlist__add_dummy(struct perf_evlist *evlist) .config = PERF_COUNT_SW_DUMMY, .size = sizeof(attr), /* to capture ABI version */ }; - struct perf_evsel *evsel = perf_evsel__new(&attr); + struct perf_evsel *evsel = perf_evsel__new_idx(&attr, evlist->nr_entries); if (evsel == NULL) return -ENOMEM; -- GitLab From dffdcbdbb0205ac10daec64f7fa519f1904f5481 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Fri, 3 Nov 2017 15:34:34 -0300 Subject: [PATCH 0232/2547] perf record: Generate PERF_RECORD_{MMAP,COMM,EXEC} with --delay When we use an initial delay, e.g.: 'perf record --delay 1000', we do not enable the events until that delay has passed after we started the workload, including the tracking event, i.e. the one for which we have attr.mmap, etc, enabled to ask the kernel to generate the PERF_RECORD_{MMAP,COMM,EXEC} metadata events that will then allow us to resolve addresses in samples to the map, dso and symbol. There will be a shadow that even synthesizing samples won't cover, i.e. the workload that we start and other processes forking while we wait for the initial delay to expire. So use a dummy event to be the tracking one and make it be enabled on exec. Before: # perf record --delay 1000 stress --cpu 1 --timeout 5 stress: info: [9029] dispatching hogs: 1 cpu, 0 io, 0 vm, 0 hdd stress: info: [9029] successful run completed in 5s [ perf record: Woken up 3 times to write data ] [ perf record: Captured and wrote 0.624 MB perf.data (15908 samples) ] # perf script | head :9031 9031 32001.826888: 1 cycles:ppp: ffffffff831aa30d event_function (/lib/modules/4.14.0-rc6+/build/vmlinux) :9031 9031 32001.826893: 1 cycles:ppp: ffffffff8300d1a0 intel_bts_enable_local (/lib/modules/4.14.0-rc6+/build/vmlinux) :9031 9031 32001.826895: 7 cycles:ppp: ffffffff83023870 sched_clock (/lib/modules/4.14.0-rc6+/build/vmlinux) :9031 9031 32001.826897: 103 cycles:ppp: ffffffff8300c331 intel_pmu_handle_irq (/lib/modules/4.14.0-rc6+/build/vmlinux) :9031 9031 32001.826899: 1615 cycles:ppp: ffffffff830231f8 native_sched_clock (/lib/modules/4.14.0-rc6+/build/vmlinux) :9031 9031 32001.826902: 26724 cycles:ppp: ffffffff8384c6a7 native_irq_return_iret (/lib/modules/4.14.0-rc6+/build/vmlinux) :9031 9031 32001.826913: 329739 cycles:ppp: 7fb2a5410932 [unknown] ([unknown]) :9031 9031 32001.827033: 1225451 cycles:ppp: 7fb2a5410930 [unknown] ([unknown]) :9031 9031 32001.827474: 1391725 cycles:ppp: 7fb2a5410930 [unknown] ([unknown]) :9031 9031 32001.827978: 1233697 cycles:ppp: 7fb2a5410928 [unknown] ([unknown]) # After: # perf record --delay 1000 stress --cpu 1 --timeout 5 stress: info: [9741] dispatching hogs: 1 cpu, 0 io, 0 vm, 0 hdd stress: info: [9741] successful run completed in 5s [ perf record: Woken up 3 times to write data ] [ perf record: Captured and wrote 0.751 MB perf.data (15976 samples) ] # perf script | head stress 9742 32110.959106: 1 cycles:ppp: ffffffff831b26f6 __perf_event_task_sched_in (/lib/modules/4.14.0-rc6+/build/vmlinux) stress 9742 32110.959110: 1 cycles:ppp: ffffffff8300c2e9 intel_pmu_handle_irq (/lib/modules/4.14.0-rc6+/build/vmlinux) stress 9742 32110.959112: 7 cycles:ppp: ffffffff830231e0 native_sched_clock (/lib/modules/4.14.0-rc6+/build/vmlinux) stress 9742 32110.959115: 101 cycles:ppp: ffffffff83023870 sched_clock (/lib/modules/4.14.0-rc6+/build/vmlinux) stress 9742 32110.959117: 1533 cycles:ppp: ffffffff830231f8 native_sched_clock (/lib/modules/4.14.0-rc6+/build/vmlinux) stress 9742 32110.959119: 23992 cycles:ppp: ffffffff831b0900 ctx_sched_in (/lib/modules/4.14.0-rc6+/build/vmlinux) stress 9742 32110.959129: 329406 cycles:ppp: 7f4b1b661930 __random_r (/usr/lib64/libc-2.25.so) stress 9742 32110.959249: 1288322 cycles:ppp: 5566e1e7cbc9 hogcpu (/usr/bin/stress) stress 9742 32110.959712: 1464046 cycles:ppp: 7f4b1b66179e __random (/usr/lib64/libc-2.25.so) stress 9742 32110.960241: 1266918 cycles:ppp: 7f4b1b66195b __random_r (/usr/lib64/libc-2.25.so) # Reported-by: Bram Stolk Tested-by: Bram Stolk Cc: Adrian Hunter Cc: Andi Kleen Cc: David Ahern Cc: Jiri Olsa Cc: Namhyung Kim Cc: Wang Nan Fixes: 6619a53ef757 ("perf record: Add --initial-delay option") Link: http://lkml.kernel.org/n/tip-nrdfchshqxf7diszhxcecqb9@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-record.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index 3d7f33e19df2..5f78ce943407 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -339,6 +339,22 @@ static int record__open(struct record *rec) struct perf_evsel_config_term *err_term; int rc = 0; + /* + * For initial_delay we need to add a dummy event so that we can track + * PERF_RECORD_MMAP while we wait for the initial delay to enable the + * real events, the ones asked by the user. + */ + if (opts->initial_delay) { + if (perf_evlist__add_dummy(evlist)) + return -ENOMEM; + + pos = perf_evlist__first(evlist); + pos->tracking = 0; + pos = perf_evlist__last(evlist); + pos->tracking = 1; + pos->attr.enable_on_exec = 1; + } + perf_evlist__config(evlist, opts, &callchain_param); evlist__for_each_entry(evlist, pos) { -- GitLab From 59622fd496a3175c7bf549046e091d81c303ecff Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Fri, 20 Oct 2017 13:27:55 -0700 Subject: [PATCH 0233/2547] perf record: Fix -c/-F options for cpu event aliases The Intel PMU event aliases have a implicit period= specifier to set the default period. Unfortunately this breaks overriding these periods with -c or -F, because the alias terms look like they are user specified to the internal parser, and user specified event qualifiers override the command line options. Track that they are coming from aliases by adding a "weak" state to the term. Any weak terms don't override command line options. I only did it for -c/-F for now, I think that's the only case that's broken currently. Before: $ perf record -c 1000 -vv -e uops_issued.any ... { sample_period, sample_freq } 2000003 After: $ perf record -c 1000 -vv -e uops_issued.any ... { sample_period, sample_freq } 1000 Signed-off-by: Andi Kleen Acked-by: Jiri Olsa Link: http://lkml.kernel.org/r/20171020202755.21410-2-andi@firstfloor.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evsel.c | 12 ++++++++---- tools/perf/util/evsel.h | 1 + tools/perf/util/parse-events.c | 2 ++ tools/perf/util/parse-events.h | 3 +++ tools/perf/util/pmu.c | 5 +++++ 5 files changed, 19 insertions(+), 4 deletions(-) diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index f894893c203d..bfde6a7a80f2 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -733,12 +733,16 @@ static void apply_config_terms(struct perf_evsel *evsel, list_for_each_entry(term, config_terms, list) { switch (term->type) { case PERF_EVSEL__CONFIG_TERM_PERIOD: - attr->sample_period = term->val.period; - attr->freq = 0; + if (!(term->weak && opts->user_interval != ULLONG_MAX)) { + attr->sample_period = term->val.period; + attr->freq = 0; + } break; case PERF_EVSEL__CONFIG_TERM_FREQ: - attr->sample_freq = term->val.freq; - attr->freq = 1; + if (!(term->weak && opts->user_freq != UINT_MAX)) { + attr->sample_freq = term->val.freq; + attr->freq = 1; + } break; case PERF_EVSEL__CONFIG_TERM_TIME: if (term->val.time) diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index 9277df96ffda..157f49e8a772 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -67,6 +67,7 @@ struct perf_evsel_config_term { bool overwrite; char *branch; } val; + bool weak; }; struct perf_stat_evsel; diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index a7fcd95961ef..170316795a18 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1116,6 +1116,7 @@ do { \ INIT_LIST_HEAD(&__t->list); \ __t->type = PERF_EVSEL__CONFIG_TERM_ ## __type; \ __t->val.__name = __val; \ + __t->weak = term->weak; \ list_add_tail(&__t->list, head_terms); \ } while (0) @@ -2410,6 +2411,7 @@ static int new_term(struct parse_events_term **_term, *term = *temp; INIT_LIST_HEAD(&term->list); + term->weak = false; switch (term->type_val) { case PARSE_EVENTS__TERM_TYPE_NUM: diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index be337c266697..88108cd11b4c 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -101,6 +101,9 @@ struct parse_events_term { /* error string indexes for within parsed string */ int err_term; int err_val; + + /* Coming from implicit alias */ + bool weak; }; struct parse_events_error { diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 07cb2ac041d7..80fb1593913a 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -405,6 +405,11 @@ static int pmu_alias_terms(struct perf_pmu_alias *alias, parse_events_terms__purge(&list); return ret; } + /* + * Weak terms don't override command line options, + * which we don't want for implicit terms in aliases. + */ + cloned->weak = true; list_add_tail(&cloned->list, &list); } list_splice(&list, terms); -- GitLab From 35c33633abc14b906e84b7b0115ede6df6830120 Mon Sep 17 00:00:00 2001 From: Andrei Vagin Date: Tue, 7 Nov 2017 16:22:46 -0800 Subject: [PATCH 0234/2547] perf trace: Fix an exit code of trace__symbols_init Currently if trace_event__register_resolver() fails, we return -errno, but we can't be sure that errno isn't zero in this case. Signed-off-by: Andrei Vagin Reviewed-by: Jiri Olsa Cc: Alexander Shishkin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Vasily Averin Link: http://lkml.kernel.org/r/20171108002246.8924-2-avagin@openvz.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-trace.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c index f2757d38c7d7..84debdbad327 100644 --- a/tools/perf/builtin-trace.c +++ b/tools/perf/builtin-trace.c @@ -1152,12 +1152,14 @@ static int trace__symbols_init(struct trace *trace, struct perf_evlist *evlist) if (trace->host == NULL) return -ENOMEM; - if (trace_event__register_resolver(trace->host, trace__machine__resolve_kernel_addr) < 0) - return -errno; + err = trace_event__register_resolver(trace->host, trace__machine__resolve_kernel_addr); + if (err < 0) + goto out; err = __machine__synthesize_threads(trace->host, &trace->tool, &trace->opts.target, evlist->threads, trace__tool_process, false, trace->opts.proc_map_timeout, 1); +out: if (err) symbol__exit(); -- GitLab From 8e2d8e204247aa9eeb87893f6b8bf0cf29428b31 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Thu, 9 Nov 2017 12:03:40 -0300 Subject: [PATCH 0235/2547] perf evsel: Fix up leftover perf_evsel_stat usage via evsel->priv I forgot one conversion, which got noticed by Thomas when running: $ perf stat -e '{cpu-clock,instructions}' kill kill: not enough arguments Segmentation fault (core dumped) $ Fix it, those stats are in evsel->stats, not anymore in evsel->priv. Reported-by: Thomas-Mich Richter Tested-by: Thomas-Mich Richter Cc: Adrian Hunter Cc: Andi Kleen Cc: David Ahern Cc: Hendrik Brueckner Cc: Jiri Olsa Cc: Namhyung Kim Cc: Wang Nan Fixes: e669e833da8d ("perf evsel: Restore evsel->priv as a tool private area") Link: http://lkml.kernel.org/r/20171109150046.GN4333@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evsel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index bfde6a7a80f2..d5fbcf8c7aa7 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -1375,7 +1375,7 @@ perf_evsel__process_group_data(struct perf_evsel *leader, static int perf_evsel__read_group(struct perf_evsel *leader, int cpu, int thread) { - struct perf_stat_evsel *ps = leader->priv; + struct perf_stat_evsel *ps = leader->stats; u64 read_format = leader->attr.read_format; int size = perf_evsel__read_size(leader); u64 *data = ps->group_data; -- GitLab From 501e5bbec3c19498fa520fd3ffd68bd907f31bf7 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Thu, 9 Nov 2017 16:04:26 -0300 Subject: [PATCH 0236/2547] perf script: Fix --per-event-dump for auxtrace synth evsels When processing PERF_RECORD_AUXTRACE_INFO several perf_evsel entries will be synthesized and inserted into session->evlist, eventually ending in perf_script.tool.sample(), which ends up calling builtin-script.c's process_event(), that expects evsel->priv to be a perf_evsel_script object with a valid FILE pointer in fp. So we need to intercept the processing of PERF_RECORD_AUXTRACE_INFO and then setup evsel->priv for these newly created perf_evsel instances, do it to fix the segfault in process_event() trying to use a NULL for that FILE pointer. Reported-by: Alexander Shishkin Cc: Adrian Hunter Cc: David Ahern Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Wang Nan Cc: yuzhoujian Fixes: a14390fde64e ("perf script: Allow creating per-event dump files") Link: http://lkml.kernel.org/n/tip-bthnur8r8de01gxvn2qayx6e@git.kernel.org [ Merge fix by Ravi Bangoria before pushing upstream to preserv bisectability ] Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-script.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index 68f36dc0344f..9b43bda45a41 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -1955,6 +1955,16 @@ static int perf_script__fopen_per_event_dump(struct perf_script *script) struct perf_evsel *evsel; evlist__for_each_entry(script->session->evlist, evsel) { + /* + * Already setup? I.e. we may be called twice in cases like + * Intel PT, one for the intel_pt// and dummy events, then + * for the evsels syntheized from the auxtrace info. + * + * Ses perf_script__process_auxtrace_info. + */ + if (evsel->priv != NULL) + continue; + evsel->priv = perf_evsel_script__new(evsel, script->session->data); if (evsel->priv == NULL) goto out_err_fclose; @@ -2838,6 +2848,25 @@ int process_cpu_map_event(struct perf_tool *tool __maybe_unused, return set_maps(script); } +#ifdef HAVE_AUXTRACE_SUPPORT +static int perf_script__process_auxtrace_info(struct perf_tool *tool, + union perf_event *event, + struct perf_session *session) +{ + int ret = perf_event__process_auxtrace_info(tool, event, session); + + if (ret == 0) { + struct perf_script *script = container_of(tool, struct perf_script, tool); + + ret = perf_script__setup_per_event_dump(script); + } + + return ret; +} +#else +#define perf_script__process_auxtrace_info 0 +#endif + int cmd_script(int argc, const char **argv) { bool show_full_info = false; @@ -2866,7 +2895,7 @@ int cmd_script(int argc, const char **argv) .feature = perf_event__process_feature, .build_id = perf_event__process_build_id, .id_index = perf_event__process_id_index, - .auxtrace_info = perf_event__process_auxtrace_info, + .auxtrace_info = perf_script__process_auxtrace_info, .auxtrace = perf_event__process_auxtrace, .auxtrace_error = perf_event__process_auxtrace_error, .stat = perf_event__process_stat_event, -- GitLab From 4a2233b194c77ae1ea8304cb7c00b551de4313f0 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 13 Nov 2017 16:06:29 -0300 Subject: [PATCH 0237/2547] perf machine: Guard against NULL in machine__exit() A recent fix for 'perf trace' introduced a bug where machine__exit(trace->host) could be called while trace->host was still NULL, so make this more robust by guarding against NULL, just like free() does. The problem happens, for instance, when !root users try to run 'perf trace': [acme@jouet linux]$ trace Error: No permissions to read /sys/kernel/debug/tracing/events/raw_syscalls/sys_(enter|exit) Hint: Try 'sudo mount -o remount,mode=755 /sys/kernel/debug/tracing' perf: Segmentation fault Obtained 7 stack frames. [0x4f1b2e] /lib64/libc.so.6(+0x3671f) [0x7f43a1dd971f] [0x4f3fec] [0x47468b] [0x42a2db] /lib64/libc.so.6(__libc_start_main+0xe9) [0x7f43a1dc3509] [0x42a6c9] Segmentation fault (core dumped) [acme@jouet linux]$ Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andrei Vagin Cc: David Ahern Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Vasily Averin Cc: Wang Nan Fixes: 33974a414ce2 ("perf trace: Call machine__exit() at exit") Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/machine.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 6a8d03c3d9b7..270f3223c6df 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -172,6 +172,9 @@ void machine__exit(struct machine *machine) { int i; + if (machine == NULL) + return; + machine__destroy_kernel_maps(machine); map_groups__exit(&machine->kmaps); dsos__exit(&machine->dsos); -- GitLab From af98f2273fd0af31ce327cd1406b67c7be0b6734 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Tue, 14 Nov 2017 09:15:42 +0900 Subject: [PATCH 0238/2547] perf help: Fix a bug during strstart() conversion The commit 8e99b6d4533c changed prefixcmp() to strstart() but missed to change the return value in some place. It makes perf help print annoying output even for sane config items like below: $ perf help '.root': unsupported man viewer sub key. ... Reported-by: Arnaldo Carvalho de Melo Signed-off-by: Namhyung Kim Tested-by: Arnaldo Carvalho de Melo Tested-by: Taeung Song Cc: Jiri Olsa Cc: Sihyeon Jang Cc: kernel-team@lge.com Link: http://lkml.kernel.org/r/20171114001542.GA16464@sejong Fixes: 8e99b6d4533c ("tools include: Adopt strstarts() from the kernel") Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-help.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/perf/builtin-help.c b/tools/perf/builtin-help.c index bd1fedef3d1c..a0f7ed2b869b 100644 --- a/tools/perf/builtin-help.c +++ b/tools/perf/builtin-help.c @@ -284,7 +284,7 @@ static int perf_help_config(const char *var, const char *value, void *cb) add_man_viewer(value); return 0; } - if (!strstarts(var, "man.")) + if (strstarts(var, "man.")) return add_man_viewer_info(var, value); return 0; @@ -314,7 +314,7 @@ static const char *cmd_to_page(const char *perf_cmd) if (!perf_cmd) return "perf"; - else if (!strstarts(perf_cmd, "perf")) + else if (strstarts(perf_cmd, "perf")) return perf_cmd; return asprintf(&s, "perf-%s", perf_cmd) < 0 ? NULL : s; -- GitLab From 05d0e62d9fa0f1002cf82009ef31b36174da5472 Mon Sep 17 00:00:00 2001 From: Ravi Bangoria Date: Tue, 14 Nov 2017 08:55:40 +0530 Subject: [PATCH 0239/2547] perf annotate: Do not truncate instruction names at 6 chars There are many instructions, esp on PowerPC, whose mnemonics are longer than 6 characters. Using precision limit causes truncation of such mnemonics. Fix this by removing precision limit. Note that, 'width' is still 6, so alignment won't get affected for length <= 6. Before: li r11,-1 xscvdp vs1,vs1 add. r10,r10,r11 After: li r11,-1 xscvdpsxds vs1,vs1 add. r10,r10,r11 Reported-by: Donald Stence Signed-off-by: Ravi Bangoria Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Taeung Song Link: http://lkml.kernel.org/r/20171114032540.4564-1-ravi.bangoria@linux.vnet.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/annotate.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index da1c4c4a0dd8..3369c7830260 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -165,7 +165,7 @@ static void ins__delete(struct ins_operands *ops) static int ins__raw_scnprintf(struct ins *ins, char *bf, size_t size, struct ins_operands *ops) { - return scnprintf(bf, size, "%-6.6s %s", ins->name, ops->raw); + return scnprintf(bf, size, "%-6s %s", ins->name, ops->raw); } int ins__scnprintf(struct ins *ins, char *bf, size_t size, @@ -230,12 +230,12 @@ static int call__scnprintf(struct ins *ins, char *bf, size_t size, struct ins_operands *ops) { if (ops->target.name) - return scnprintf(bf, size, "%-6.6s %s", ins->name, ops->target.name); + return scnprintf(bf, size, "%-6s %s", ins->name, ops->target.name); if (ops->target.addr == 0) return ins__raw_scnprintf(ins, bf, size, ops); - return scnprintf(bf, size, "%-6.6s *%" PRIx64, ins->name, ops->target.addr); + return scnprintf(bf, size, "%-6s *%" PRIx64, ins->name, ops->target.addr); } static struct ins_ops call_ops = { @@ -299,7 +299,7 @@ static int jump__scnprintf(struct ins *ins, char *bf, size_t size, c++; } - return scnprintf(bf, size, "%-6.6s %.*s%" PRIx64, + return scnprintf(bf, size, "%-6s %.*s%" PRIx64, ins->name, c ? c - ops->raw : 0, ops->raw, ops->target.offset); } @@ -372,7 +372,7 @@ static int lock__scnprintf(struct ins *ins, char *bf, size_t size, if (ops->locked.ins.ops == NULL) return ins__raw_scnprintf(ins, bf, size, ops); - printed = scnprintf(bf, size, "%-6.6s ", ins->name); + printed = scnprintf(bf, size, "%-6s ", ins->name); return printed + ins__scnprintf(&ops->locked.ins, bf + printed, size - printed, ops->locked.ops); } @@ -448,7 +448,7 @@ static int mov__parse(struct arch *arch, struct ins_operands *ops, struct map *m static int mov__scnprintf(struct ins *ins, char *bf, size_t size, struct ins_operands *ops) { - return scnprintf(bf, size, "%-6.6s %s,%s", ins->name, + return scnprintf(bf, size, "%-6s %s,%s", ins->name, ops->source.name ?: ops->source.raw, ops->target.name ?: ops->target.raw); } @@ -488,7 +488,7 @@ static int dec__parse(struct arch *arch __maybe_unused, struct ins_operands *ops static int dec__scnprintf(struct ins *ins, char *bf, size_t size, struct ins_operands *ops) { - return scnprintf(bf, size, "%-6.6s %s", ins->name, + return scnprintf(bf, size, "%-6s %s", ins->name, ops->target.name ?: ops->target.raw); } @@ -500,7 +500,7 @@ static struct ins_ops dec_ops = { static int nop__scnprintf(struct ins *ins __maybe_unused, char *bf, size_t size, struct ins_operands *ops __maybe_unused) { - return scnprintf(bf, size, "%-6.6s", "nop"); + return scnprintf(bf, size, "%-6s", "nop"); } static struct ins_ops nop_ops = { @@ -924,7 +924,7 @@ void disasm_line__free(struct disasm_line *dl) int disasm_line__scnprintf(struct disasm_line *dl, char *bf, size_t size, bool raw) { if (raw || !dl->ins.ops) - return scnprintf(bf, size, "%-6.6s %s", dl->ins.name, dl->ops.raw); + return scnprintf(bf, size, "%-6s %s", dl->ins.name, dl->ops.raw); return ins__scnprintf(&dl->ins, bf, size, &dl->ops); } -- GitLab From ccafc38f1c778847ab6d53dd7933260426731cf3 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Tue, 14 Nov 2017 08:18:46 +0100 Subject: [PATCH 0240/2547] perf test shell: Fix check open filename arg using 'perf trace' on s390x This 'perf test' case fails on s390x. The 'touch' command on s390x uses the 'openat' system call to open the file named on the command line: [root@s35lp76 perf]# perf probe -l probe:vfs_getname (on getname_flags:72@fs/namei.c with pathname) [root@s35lp76 perf]# perf trace -e open touch /tmp/abc 0.400 ( 0.015 ms): touch/27542 open(filename: /usr/lib/locale/locale-archive, flags: CLOEXEC) = 3 [root@s35lp76 perf]# There is no 'open' system call for file '/tmp/abc'. Instead the 'openat' system call is used: [root@s35lp76 perf]# strace touch /tmp/abc execve("/usr/bin/touch", ["touch", "/tmp/abc"], 0x3ffd547ec98 /* 30 vars */) = 0 [...] openat(AT_FDCWD, "/tmp/abc", O_WRONLY|O_CREAT|O_NOCTTY|O_NONBLOCK, 0666) = 3 [...] On s390x the 'egrep' command does not find a matching pattern and returns an error. Fix this for s390x create a platform dependent command line to enable the 'perf probe' call to listen to the 'openat' system call and get the expected output. Signed-off-by: Thomas-Mich Richter Tested-by: Arnaldo Carvalho de Melo Cc: Hendrik Brueckner Cc: Thomas-Mich Richter LPU-Reference: 20171114071847.2381-1-tmricht@linux.vnet.ibm.com Link: http://lkml.kernel.org/n/tip-3qf38jk0prz54rhmhyu871my@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/shell/trace+probe_vfs_getname.sh | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tools/perf/tests/shell/trace+probe_vfs_getname.sh b/tools/perf/tests/shell/trace+probe_vfs_getname.sh index 2e68c5f120da..2a9ef080efd0 100755 --- a/tools/perf/tests/shell/trace+probe_vfs_getname.sh +++ b/tools/perf/tests/shell/trace+probe_vfs_getname.sh @@ -17,8 +17,10 @@ skip_if_no_perf_probe || exit 2 file=$(mktemp /tmp/temporary_file.XXXXX) trace_open_vfs_getname() { - perf trace -e open touch $file 2>&1 | \ - egrep " +[0-9]+\.[0-9]+ +\( +[0-9]+\.[0-9]+ ms\): +touch\/[0-9]+ open\(filename: +${file}, +flags: CREAT\|NOCTTY\|NONBLOCK\|WRONLY, +mode: +IRUGO\|IWUGO\) += +[0-9]+$" + test "$(uname -m)" = s390x && { svc="openat"; txt="dfd: +CWD, +"; } + + perf trace -e ${svc:-open} touch $file 2>&1 | \ + egrep " +[0-9]+\.[0-9]+ +\( +[0-9]+\.[0-9]+ ms\): +touch\/[0-9]+ ${svc:-open}\(${txt}filename: +${file}, +flags: CREAT\|NOCTTY\|NONBLOCK\|WRONLY, +mode: +IRUGO\|IWUGO\) += +[0-9]+$" } -- GitLab From d5c5e46aa7a2b256a526f9ce832ffbf622c3c19a Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Tue, 14 Nov 2017 08:18:47 +0100 Subject: [PATCH 0241/2547] perf test shell: Fix test case probe libc's inet_pton on s390x MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The 'perf test' case "probe libc's inet_pton & backtrace it with ping" fails on s390x. The reason is the 'realpath /lib64/ld*.so.* | uniq' line which returns 2 libraries: root@s35lp76 shell]# realpath /lib64/ld*.so.* | uniq /usr/lib64/ld-2.26.so /usr/lib64/ld_pre_smc.so.1.0.1 [root@s35lp76 shell] This output makes the "perf probe" command lines invalid. Use ldd tool to find out the libraries required by "bash" and check if symbol "inet_pton" is part of the "libc" library. Some distros do not have a /lib64 directory. I have also added a check for the existence of an IPv6 network interface before it is being used. Committer changes: We can't really use ldd for libc, as in some systems, such as x86_64, it has hardlinks and then ldd sees one and the kernel the other, so grep for libc in /proc/self/maps to get the one we'll receive from PERF_RECORD_MMAP. Thomas checked this change and acked it. Signed-off-by: Thomas-Mich Richter Tested-by: Arnaldo Carvalho de Melo Suggested-by: Hendrik Brückner Reviewed-by: Hendrik Brückner Link: http://lkml.kernel.org/r/20171114133409.GN8836@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/shell/trace+probe_libc_inet_pton.sh | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tools/perf/tests/shell/trace+probe_libc_inet_pton.sh b/tools/perf/tests/shell/trace+probe_libc_inet_pton.sh index 7a84d73324e3..8b3da21a08f1 100755 --- a/tools/perf/tests/shell/trace+probe_libc_inet_pton.sh +++ b/tools/perf/tests/shell/trace+probe_libc_inet_pton.sh @@ -10,8 +10,8 @@ . $(dirname $0)/lib/probe.sh -ld=$(realpath /lib64/ld*.so.* | uniq) -libc=$(echo $ld | sed 's/ld/libc/g') +libc=$(grep -w libc /proc/self/maps | head -1 | sed -r 's/.*[[:space:]](\/.*)/\1/g') +nm -g $libc 2>/dev/null | fgrep -q inet_pton || exit 254 trace_libc_inet_pton_backtrace() { idx=0 @@ -37,6 +37,9 @@ trace_libc_inet_pton_backtrace() { done } +# Check for IPv6 interface existence +ip a sh lo | fgrep -q inet6 || exit 2 + skip_if_no_perf_probe && \ perf probe -q $libc inet_pton && \ trace_libc_inet_pton_backtrace -- GitLab From 5b0d1cb40698056f3df8ed579dde4b80c6b7508d Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 14 Nov 2017 11:01:06 -0300 Subject: [PATCH 0242/2547] perf evlist: Add helper to check if attr.exclude_kernel is set in all evsels The warning about kptr_restrict needs to be emitted only when it is set and we ask for kernel space samples, so add a helper to help with that. Cc: Adrian Hunter Cc: David Ahern Cc: Jiri Olsa Cc: Linus Torvalds Cc: Namhyung Kim Cc: Wang Nan Link: http://lkml.kernel.org/n/tip-fh7drty6yljei9gxxzer6eup@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evlist.c | 12 ++++++++++++ tools/perf/util/evlist.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c index ccb749f9a83f..b62e523a7035 100644 --- a/tools/perf/util/evlist.c +++ b/tools/perf/util/evlist.c @@ -1786,3 +1786,15 @@ void perf_evlist__toggle_bkw_mmap(struct perf_evlist *evlist, state_err: return; } + +bool perf_evlist__exclude_kernel(struct perf_evlist *evlist) +{ + struct perf_evsel *evsel; + + evlist__for_each_entry(evlist, evsel) { + if (!evsel->attr.exclude_kernel) + return false; + } + + return true; +} diff --git a/tools/perf/util/evlist.h b/tools/perf/util/evlist.h index e72ae64c11ac..491f69542920 100644 --- a/tools/perf/util/evlist.h +++ b/tools/perf/util/evlist.h @@ -312,4 +312,6 @@ perf_evlist__find_evsel_by_str(struct perf_evlist *evlist, const char *str); struct perf_evsel *perf_evlist__event2evsel(struct perf_evlist *evlist, union perf_event *event); + +bool perf_evlist__exclude_kernel(struct perf_evlist *evlist); #endif /* __PERF_EVLIST_H */ -- GitLab From 3f0a4c873cb341d0cb61493d8dec7662bcaa7ca7 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 14 Nov 2017 11:12:11 -0300 Subject: [PATCH 0243/2547] perf report: Ignore kptr_restrict when not sampling the kernel If none of the evsels has attr.exclude_kernel set to zero, no kernel samples, so no point in warning the user about problems in processing kernel samples, as there will be none. Cc: Adrian Hunter Cc: David Ahern Cc: Jiri Olsa Cc: Linus Torvalds Cc: Namhyung Kim Cc: Wang Nan Link: http://lkml.kernel.org/n/tip-7dn926v3at8txxkky92aesz2@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-report.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index 1394cd8d96f7..af5dd038195e 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -441,6 +441,9 @@ static void report__warn_kptr_restrict(const struct report *rep) struct map *kernel_map = machine__kernel_map(&rep->session->machines.host); struct kmap *kernel_kmap = kernel_map ? map__kmap(kernel_map) : NULL; + if (perf_evlist__exclude_kernel(rep->session->evlist)) + return; + if (kernel_map == NULL || (kernel_map->dso->hit && (kernel_kmap->ref_reloc_sym == NULL || -- GitLab From b0ebd811af889721d3fbef3657092cf028c16b7c Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 14 Nov 2017 11:03:19 -0300 Subject: [PATCH 0244/2547] perf record: Ignore kptr_restrict when not sampling the kernel If we're not sampling the kernel, we shouldn't care about kptr_restrict neither synthesize anything for assisting in resolving kernel samples, like the reference relocation symbol or kernel modules information. Before: $ cat /proc/sys/kernel/kptr_restrict /proc/sys/kernel/perf_event_paranoid 2 2 $ perf record sleep 1 WARNING: Kernel address maps (/proc/{kallsyms,modules}) are restricted, check /proc/sys/kernel/kptr_restrict. Samples in kernel functions may not be resolved if a suitable vmlinux file is not found in the buildid cache or in the vmlinux path. Samples in kernel modules won't be resolved at all. If some relocation was applied (e.g. kexec) symbols may be misresolved even with a suitable vmlinux or kallsyms file. Couldn't record kernel reference relocation symbol Symbol resolution may be skewed if relocation was used (e.g. kexec). Check /proc/kallsyms permission or run as root. [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.001 MB perf.data (8 samples) ] $ perf evlist -v cycles:uppp: size: 112, { sample_period, sample_freq }: 4000, sample_type: IP|TID|TIME|PERIOD, disabled: 1, inherit: 1, exclude_kernel: 1, mmap: 1, comm: 1, freq: 1, enable_on_exec: 1, task: 1, precise_ip: 3, sample_id_all: 1, exclude_guest: 1, mmap2: 1, comm_exec: 1 $ After: $ perf record sleep 1 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.001 MB perf.data (10 samples) ] $ Cc: Adrian Hunter Cc: David Ahern Cc: Jiri Olsa Cc: Linus Torvalds Cc: Namhyung Kim Cc: Wang Nan Link: http://lkml.kernel.org/n/tip-t025e9zftbx2b8cq2w01g5e5@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-record.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index 5f78ce943407..003255910c05 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -765,17 +765,19 @@ static int record__synthesize(struct record *rec, bool tail) goto out; } - err = perf_event__synthesize_kernel_mmap(tool, process_synthesized_event, - machine); - WARN_ONCE(err < 0, "Couldn't record kernel reference relocation symbol\n" - "Symbol resolution may be skewed if relocation was used (e.g. kexec).\n" - "Check /proc/kallsyms permission or run as root.\n"); - - err = perf_event__synthesize_modules(tool, process_synthesized_event, - machine); - WARN_ONCE(err < 0, "Couldn't record kernel module information.\n" - "Symbol resolution may be skewed if relocation was used (e.g. kexec).\n" - "Check /proc/modules permission or run as root.\n"); + if (!perf_evlist__exclude_kernel(rec->evlist)) { + err = perf_event__synthesize_kernel_mmap(tool, process_synthesized_event, + machine); + WARN_ONCE(err < 0, "Couldn't record kernel reference relocation symbol\n" + "Symbol resolution may be skewed if relocation was used (e.g. kexec).\n" + "Check /proc/kallsyms permission or run as root.\n"); + + err = perf_event__synthesize_modules(tool, process_synthesized_event, + machine); + WARN_ONCE(err < 0, "Couldn't record kernel module information.\n" + "Symbol resolution may be skewed if relocation was used (e.g. kexec).\n" + "Check /proc/modules permission or run as root.\n"); + } if (perf_guest) { machines__process_guests(&session->machines, @@ -1709,7 +1711,7 @@ int cmd_record(int argc, const char **argv) err = -ENOMEM; - if (symbol_conf.kptr_restrict) + if (symbol_conf.kptr_restrict && !perf_evlist__exclude_kernel(rec->evlist)) pr_warning( "WARNING: Kernel address maps (/proc/{kallsyms,modules}) are restricted,\n" "check /proc/sys/kernel/kptr_restrict.\n\n" -- GitLab From df7ccfa21ef343c602ae4aa1eb7893da4408b219 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 14 Nov 2017 13:30:19 -0300 Subject: [PATCH 0245/2547] perf top: Ignore kptr_restrict when not sampling the kernel If all events have attr.exclude_kernel set, no need to look at kptr_restrict. Cc: Adrian Hunter Cc: David Ahern Cc: Jiri Olsa Cc: Linus Torvalds Cc: Namhyung Kim Cc: Wang Nan Link: http://lkml.kernel.org/n/tip-yegpzg5bf2im69g0tfizqaqz@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-top.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index 477a8699f0b5..1b01c277bab9 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -732,14 +732,16 @@ static void perf_event__process_sample(struct perf_tool *tool, if (!machine->kptr_restrict_warned && symbol_conf.kptr_restrict && al.cpumode == PERF_RECORD_MISC_KERNEL) { - ui__warning( + if (!perf_evlist__exclude_kernel(top->session->evlist)) { + ui__warning( "Kernel address maps (/proc/{kallsyms,modules}) are restricted.\n\n" "Check /proc/sys/kernel/kptr_restrict.\n\n" "Kernel%s samples will not be resolved.\n", al.map && !RB_EMPTY_ROOT(&al.map->dso->symbols[MAP__FUNCTION]) ? " modules" : ""); - if (use_browser <= 0) - sleep(5); + if (use_browser <= 0) + sleep(5); + } machine->kptr_restrict_warned = true; } -- GitLab From 34900ec5c9577cc1b0f22887ac7349f458ba8ac2 Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Wed, 9 Aug 2017 18:14:06 +0200 Subject: [PATCH 0246/2547] perf: Fix header.size for namespace events Reset header size for namespace events, otherwise it only gets bigger in ctx iterations. Signed-off-by: Jiri Olsa Acked-by: Peter Zijlstra (Intel) Fixes: e422267322cd ("perf: Add PERF_RECORD_NAMESPACES to include namespaces related info") Link: http://lkml.kernel.org/n/tip-nlo4gonz9d4guyb8153ukzt0@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- kernel/events/core.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/kernel/events/core.c b/kernel/events/core.c index 4c39c05e029a..799bb352d99f 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -6640,6 +6640,7 @@ static void perf_event_namespaces_output(struct perf_event *event, struct perf_namespaces_event *namespaces_event = data; struct perf_output_handle handle; struct perf_sample_data sample; + u16 header_size = namespaces_event->event_id.header.size; int ret; if (!perf_event_namespaces_match(event)) @@ -6650,7 +6651,7 @@ static void perf_event_namespaces_output(struct perf_event *event, ret = perf_output_begin(&handle, event, namespaces_event->event_id.header.size); if (ret) - return; + goto out; namespaces_event->event_id.pid = perf_event_pid(event, namespaces_event->task); @@ -6662,6 +6663,8 @@ static void perf_event_namespaces_output(struct perf_event *event, perf_event__output_id_sample(event, &handle, &sample); perf_output_end(&handle); +out: + namespaces_event->event_id.header.size = header_size; } static void perf_fill_ns_link_info(struct perf_ns_link_info *ns_link_info, -- GitLab From 89d0aeab4252adc2a7ea693637dd21c588bfa2d1 Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Tue, 14 Nov 2017 10:23:39 +0100 Subject: [PATCH 0247/2547] perf top: Fix window dimensions change handling The stdio perf top crashes when we change the terminal window size. The reason is that we assumed we get the perf_top pointer as a signal handler argument which is not the case. Changing the SIGWINCH handler logic to change global resize variable, which is checked in the main thread loop. Signed-off-by: Jiri Olsa Tested-by: Arnaldo Carvalho de Melo Tested-by: Ravi Bangoria Cc: Adrian Hunter Cc: Andi Kleen Cc: David Ahern Cc: Namhyung Kim Cc: Wang Nan Link: http://lkml.kernel.org/n/tip-ysuzwz77oev1ftgvdscn9bpu@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-top.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index 1b01c277bab9..489573883936 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -77,6 +77,7 @@ #include "sane_ctype.h" static volatile int done; +static volatile int resize; #define HEADER_LINE_NR 5 @@ -86,10 +87,13 @@ static void perf_top__update_print_entries(struct perf_top *top) } static void perf_top__sig_winch(int sig __maybe_unused, - siginfo_t *info __maybe_unused, void *arg) + siginfo_t *info __maybe_unused, void *arg __maybe_unused) { - struct perf_top *top = arg; + resize = 1; +} +static void perf_top__resize(struct perf_top *top) +{ get_term_dimensions(&top->winsize); perf_top__update_print_entries(top); } @@ -477,7 +481,7 @@ static bool perf_top__handle_keypress(struct perf_top *top, int c) .sa_sigaction = perf_top__sig_winch, .sa_flags = SA_SIGINFO, }; - perf_top__sig_winch(SIGWINCH, NULL, top); + perf_top__resize(top); sigaction(SIGWINCH, &act, NULL); } else { signal(SIGWINCH, SIG_DFL); @@ -1032,6 +1036,11 @@ static int __cmd_top(struct perf_top *top) if (hits == top->samples) ret = perf_evlist__poll(top->evlist, 100); + + if (resize) { + perf_top__resize(top); + resize = 0; + } } ret = 0; -- GitLab From bdaab8c4b3db820b0946ed4516bc5ec811e0cc82 Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Wed, 15 Nov 2017 14:30:57 +0100 Subject: [PATCH 0248/2547] perf top: Use signal interface for SIGWINCH handler There's no need for SA_SIGINFO data in SIGWINCH handler, switching it to register the handler via signal interface as we do for the rest of the signals in perf top. Signed-off-by: Jiri Olsa Tested-by: Ravi Bangoria Tested-by: Arnaldo Carvalho de Melo Cc: Adrian Hunter Cc: Andi Kleen Cc: David Ahern Cc: Namhyung Kim Cc: Wang Nan Link: http://lkml.kernel.org/n/tip-elxp1vdnaog1scaj13cx7cu0@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-top.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index 489573883936..9e0d2645ae13 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -86,8 +86,7 @@ static void perf_top__update_print_entries(struct perf_top *top) top->print_entries = top->winsize.ws_row - HEADER_LINE_NR; } -static void perf_top__sig_winch(int sig __maybe_unused, - siginfo_t *info __maybe_unused, void *arg __maybe_unused) +static void winch_sig(int sig __maybe_unused) { resize = 1; } @@ -477,12 +476,8 @@ static bool perf_top__handle_keypress(struct perf_top *top, int c) case 'e': prompt_integer(&top->print_entries, "Enter display entries (lines)"); if (top->print_entries == 0) { - struct sigaction act = { - .sa_sigaction = perf_top__sig_winch, - .sa_flags = SA_SIGINFO, - }; perf_top__resize(top); - sigaction(SIGWINCH, &act, NULL); + signal(SIGWINCH, winch_sig); } else { signal(SIGWINCH, SIG_DFL); } @@ -1363,12 +1358,8 @@ int cmd_top(int argc, const char **argv) get_term_dimensions(&top.winsize); if (top.print_entries == 0) { - struct sigaction act = { - .sa_sigaction = perf_top__sig_winch, - .sa_flags = SA_SIGINFO, - }; perf_top__update_print_entries(&top); - sigaction(SIGWINCH, &act, NULL); + signal(SIGWINCH, winch_sig); } status = __cmd_top(&top); -- GitLab From 321a7c35c90cc834851ceda18a8ee18f1d032b92 Mon Sep 17 00:00:00 2001 From: Satheesh Rajendran Date: Wed, 22 Nov 2017 22:13:53 +0530 Subject: [PATCH 0249/2547] perf bench numa: Fixup discontiguous/sparse numa nodes Certain systems are designed to have sparse/discontiguous nodes. On such systems, 'perf bench numa' hangs, shows wrong number of nodes and shows values for non-existent nodes. Handle this by only taking nodes that are exposed by kernel to userspace. Signed-off-by: Satheesh Rajendran Reviewed-by: Srikar Dronamraju Acked-by: Naveen N. Rao Link: http://lkml.kernel.org/r/1edbcd353c009e109e93d78f2f46381930c340fe.1511368645.git.sathnaga@linux.vnet.ibm.com Signed-off-by: Balamuruhan S Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/bench/numa.c | 56 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 5 deletions(-) diff --git a/tools/perf/bench/numa.c b/tools/perf/bench/numa.c index d95fdcc26f4b..944070e98a2c 100644 --- a/tools/perf/bench/numa.c +++ b/tools/perf/bench/numa.c @@ -216,6 +216,47 @@ static const char * const numa_usage[] = { NULL }; +/* + * To get number of numa nodes present. + */ +static int nr_numa_nodes(void) +{ + int i, nr_nodes = 0; + + for (i = 0; i < g->p.nr_nodes; i++) { + if (numa_bitmask_isbitset(numa_nodes_ptr, i)) + nr_nodes++; + } + + return nr_nodes; +} + +/* + * To check if given numa node is present. + */ +static int is_node_present(int node) +{ + return numa_bitmask_isbitset(numa_nodes_ptr, node); +} + +/* + * To check given numa node has cpus. + */ +static bool node_has_cpus(int node) +{ + struct bitmask *cpu = numa_allocate_cpumask(); + unsigned int i; + + if (cpu && !numa_node_to_cpus(node, cpu)) { + for (i = 0; i < cpu->size; i++) { + if (numa_bitmask_isbitset(cpu, i)) + return true; + } + } + + return false; /* lets fall back to nocpus safely */ +} + static cpu_set_t bind_to_cpu(int target_cpu) { cpu_set_t orig_mask, mask; @@ -244,12 +285,12 @@ static cpu_set_t bind_to_cpu(int target_cpu) static cpu_set_t bind_to_node(int target_node) { - int cpus_per_node = g->p.nr_cpus/g->p.nr_nodes; + int cpus_per_node = g->p.nr_cpus / nr_numa_nodes(); cpu_set_t orig_mask, mask; int cpu; int ret; - BUG_ON(cpus_per_node*g->p.nr_nodes != g->p.nr_cpus); + BUG_ON(cpus_per_node * nr_numa_nodes() != g->p.nr_cpus); BUG_ON(!cpus_per_node); ret = sched_getaffinity(0, sizeof(orig_mask), &orig_mask); @@ -649,7 +690,7 @@ static int parse_setup_node_list(void) int i; for (i = 0; i < mul; i++) { - if (t >= g->p.nr_tasks) { + if (t >= g->p.nr_tasks || !node_has_cpus(bind_node)) { printf("\n# NOTE: ignoring bind NODEs starting at NODE#%d\n", bind_node); goto out; } @@ -964,6 +1005,8 @@ static void calc_convergence(double runtime_ns_max, double *convergence) sum = 0; for (node = 0; node < g->p.nr_nodes; node++) { + if (!is_node_present(node)) + continue; nr = nodes[node]; nr_min = min(nr, nr_min); nr_max = max(nr, nr_max); @@ -984,8 +1027,11 @@ static void calc_convergence(double runtime_ns_max, double *convergence) process_groups = 0; for (node = 0; node < g->p.nr_nodes; node++) { - int processes = count_node_processes(node); + int processes; + if (!is_node_present(node)) + continue; + processes = count_node_processes(node); nr = nodes[node]; tprintf(" %2d/%-2d", nr, processes); @@ -1291,7 +1337,7 @@ static void print_summary(void) printf("\n ###\n"); printf(" # %d %s will execute (on %d nodes, %d CPUs):\n", - g->p.nr_tasks, g->p.nr_tasks == 1 ? "task" : "tasks", g->p.nr_nodes, g->p.nr_cpus); + g->p.nr_tasks, g->p.nr_tasks == 1 ? "task" : "tasks", nr_numa_nodes(), g->p.nr_cpus); printf(" # %5dx %5ldMB global shared mem operations\n", g->p.nr_loops, g->p.bytes_global/1024/1024); printf(" # %5dx %5ldMB process shared mem operations\n", -- GitLab From 996548499df61babae5306544c7daf5fd39db31c Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Thu, 23 Nov 2017 12:46:11 +0100 Subject: [PATCH 0250/2547] perf test: Fix test 21 for s390x Test case 21 (Number of exit events of a simple workload) fails on s390x. The reason is the invalid sample frequency supplied for this test. On s390x the minimum sample frequency is much higher (see output of /proc/service_levels). Supply a save sample frequency value for s390x to fix this. The value will be adjusted by the s390x CPUMF frequency convertion function to a value well below the sysctl kernel.perf_event_max_sample_rate value. Signed-off-by: Thomas Richter Reviewed-by: Hendrik Brueckner Cc: Martin Schwidefsky LPU-Reference: 20171123114611.93397-1-tmricht@linux.vnet.ibm.com Link: https://lkml.kernel.org/n/tip-1ynblyhi1n81idpido59nt1y@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/task-exit.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/perf/tests/task-exit.c b/tools/perf/tests/task-exit.c index bc4a7344e274..89c8e1604ca7 100644 --- a/tools/perf/tests/task-exit.c +++ b/tools/perf/tests/task-exit.c @@ -84,7 +84,11 @@ int test__task_exit(struct test *test __maybe_unused, int subtest __maybe_unused evsel = perf_evlist__first(evlist); evsel->attr.task = 1; +#ifdef __s390x__ + evsel->attr.sample_freq = 1000000; +#else evsel->attr.sample_freq = 1; +#endif evsel->attr.inherit = 0; evsel->attr.watermark = 0; evsel->attr.wakeup_events = 1; -- GitLab From 51cacdc89852e91448518c616758c4421c83e057 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Tue, 21 Nov 2017 10:35:26 +0200 Subject: [PATCH 0251/2547] perf intel-pt: Bring instruction decoder files into line with the kernel There are just a few new defines which do not affect perf tools. Signed-off-by: Adrian Hunter Link: http://lkml.kernel.org/r/1511253326-22308-3-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/intel-pt-decoder/inat.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/perf/util/intel-pt-decoder/inat.h b/tools/perf/util/intel-pt-decoder/inat.h index 125ecd2a300d..52dc8d911173 100644 --- a/tools/perf/util/intel-pt-decoder/inat.h +++ b/tools/perf/util/intel-pt-decoder/inat.h @@ -97,6 +97,16 @@ #define INAT_MAKE_GROUP(grp) ((grp << INAT_GRP_OFFS) | INAT_MODRM) #define INAT_MAKE_IMM(imm) (imm << INAT_IMM_OFFS) +/* Identifiers for segment registers */ +#define INAT_SEG_REG_IGNORE 0 +#define INAT_SEG_REG_DEFAULT 1 +#define INAT_SEG_REG_CS 2 +#define INAT_SEG_REG_SS 3 +#define INAT_SEG_REG_DS 4 +#define INAT_SEG_REG_ES 5 +#define INAT_SEG_REG_FS 6 +#define INAT_SEG_REG_GS 7 + /* Attribute search APIs */ extern insn_attr_t inat_get_opcode_attribute(insn_byte_t opcode); extern int inat_get_last_prefix_id(insn_byte_t last_pfx); -- GitLab From 0b44cfb8e40f64cd72520be223414a7ef79c5d90 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Sat, 18 Nov 2017 09:00:46 +0100 Subject: [PATCH 0252/2547] tools/headers: Synchronize kernel x86 UAPI headers Two x86 headers got modified in this merge window: arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/disabled-features.h To support x86 UMIP feature, to add new AVX instructions, plus cleanups. None of those changes have an effect on tooling, so do a plain copy. Cc: Arnaldo Carvalho de Melo Cc: Greg Kroah-Hartman Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Peter Zijlstra Cc: Namhyung Kim Cc: Jiri Olsa Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- tools/arch/x86/include/asm/cpufeatures.h | 537 +++++++++--------- .../arch/x86/include/asm/disabled-features.h | 8 +- 2 files changed, 281 insertions(+), 264 deletions(-) diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index 793690fbda36..c0b0e9e8aa66 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -13,173 +13,176 @@ /* * Defines x86 CPU feature bits */ -#define NCAPINTS 18 /* N 32-bit words worth of info */ -#define NBUGINTS 1 /* N 32-bit bug flags */ +#define NCAPINTS 18 /* N 32-bit words worth of info */ +#define NBUGINTS 1 /* N 32-bit bug flags */ /* * Note: If the comment begins with a quoted string, that string is used * in /proc/cpuinfo instead of the macro name. If the string is "", * this feature bit is not displayed in /proc/cpuinfo at all. + * + * When adding new features here that depend on other features, + * please update the table in kernel/cpu/cpuid-deps.c as well. */ -/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ -#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ -#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ -#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ -#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ -#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ -#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ -#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ -#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ -#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ -#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ -#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ -#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ -#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ -#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ -#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ - /* (plus FCMOVcc, FCOMI with FPU) */ -#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ -#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ -#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ -#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ -#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ -#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ -#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ -#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ -#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ -#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ -#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ -#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ -#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ -#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ -#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ +/* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */ +#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ +#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ +#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ +#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ +#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ +#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ +#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ +#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ +#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ +#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ +#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ +#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ +#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ +#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ +#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */ +#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ +#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ +#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ +#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ +#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ +#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ +#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ +#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ +#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ +#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ +#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ +#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ +#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ +#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ +#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ /* Don't duplicate feature flags which are redundant with Intel! */ -#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ -#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ -#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ -#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ -#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ -#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ -#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ -#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ -#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ -#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ +#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ +#define X86_FEATURE_MP ( 1*32+19) /* MP Capable */ +#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ +#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ +#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ +#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ +#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ +#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64, 64-bit support) */ +#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow extensions */ +#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow */ /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ -#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ -#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ -#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ +#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ +#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ +#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ /* Other features, Linux-defined mapping, word 3 */ /* This range is used for feature bits which conflict or are synthesized */ -#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ -#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ -#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ -#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ -/* cpu types for specific tunings: */ -#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ -#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ -#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ -#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ -#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ -#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ -#define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */ -#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ -#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ -#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ -#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ -#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ -#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ -#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ -#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ -#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ -#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ -#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ -#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ -#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ -#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ -#define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ -#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ -#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ -#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ -#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ -#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ +#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ +#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ +#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ +#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ + +/* CPU types for specific tunings: */ +#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ +#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ +#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ +#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ +#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ +#define X86_FEATURE_UP ( 3*32+ 9) /* SMP kernel running on UP */ +#define X86_FEATURE_ART ( 3*32+10) /* Always running timer (ART) */ +#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ +#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ +#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ +#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ +#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ +#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ +#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" MFENCE synchronizes RDTSC */ +#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ +#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ +#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ +#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ +#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* CPU topology enum extensions */ +#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ +#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ +#define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ +#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */ +#define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */ +#define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */ +#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ +#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ -/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ -#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ -#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ -#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ -#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ -#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ -#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ -#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ -#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ -#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ -#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ -#define X86_FEATURE_CID ( 4*32+10) /* Context ID */ -#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ -#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ -#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ -#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ -#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ -#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ -#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ -#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ -#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ -#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ -#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ -#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ -#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ -#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ -#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ -#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ -#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ -#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ -#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ -#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ +/* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */ +#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ +#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ +#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ +#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */ +#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */ +#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ +#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer Mode eXtensions */ +#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ +#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ +#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ +#define X86_FEATURE_CID ( 4*32+10) /* Context ID */ +#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ +#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ +#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B instruction */ +#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ +#define X86_FEATURE_PDCM ( 4*32+15) /* Perf/Debug Capabilities MSR */ +#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ +#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ +#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ +#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ +#define X86_FEATURE_X2APIC ( 4*32+21) /* X2APIC */ +#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ +#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ +#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* TSC deadline timer */ +#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ +#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV instructions */ +#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE instruction enabled in the OS */ +#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ +#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit FP conversions */ +#define X86_FEATURE_RDRAND ( 4*32+30) /* RDRAND instruction */ +#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ -#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ -#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ -#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ -#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ -#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ -#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ -#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ -#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ -#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ -#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ +#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ +#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ +#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ +#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ +#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ +#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ +#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ +#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ +#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ +#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ -/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ -#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ -#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ -#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ -#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ -#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ -#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ -#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ -#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ -#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ -#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ -#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ -#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ -#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ -#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ -#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ -#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ -#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ -#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ -#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ -#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ -#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ -#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ -#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ -#define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */ -#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ -#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ +/* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */ +#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ +#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ +#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure Virtual Machine */ +#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ +#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ +#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ +#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ +#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ +#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ +#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ +#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ +#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ +#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ +#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ +#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ +#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ +#define X86_FEATURE_TCE ( 6*32+17) /* Translation Cache Extension */ +#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ +#define X86_FEATURE_TBM ( 6*32+21) /* Trailing Bit Manipulations */ +#define X86_FEATURE_TOPOEXT ( 6*32+22) /* Topology extensions CPUID leafs */ +#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* Core performance counter extensions */ +#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ +#define X86_FEATURE_BPEXT ( 6*32+26) /* Data breakpoint extension */ +#define X86_FEATURE_PTSC ( 6*32+27) /* Performance time-stamp counter */ +#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ +#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX instructions) */ /* * Auxiliary flags: Linux defined - For features scattered in various @@ -187,146 +190,154 @@ * * Reuse free bits when adding new feature flags! */ -#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */ -#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ -#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ -#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ -#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ -#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */ -#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */ +#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT instructions */ +#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ +#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ +#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ +#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ +#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */ +#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */ -#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ -#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ -#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ +#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ +#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ +#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ -#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ -#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ -#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */ -#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */ +#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ +#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ +#define X86_FEATURE_AVX512_4VNNIW ( 7*32+16) /* AVX-512 Neural Network Instructions */ +#define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */ -#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ +#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ /* Virtualization flags: Linux defined, word 8 */ -#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ -#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ -#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ -#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ -#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ +#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ +#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ +#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ +#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ +#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ -#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ -#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ +#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */ +#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ -/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ -#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ -#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ -#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ -#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ -#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ -#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ -#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ -#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ -#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ -#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ -#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ -#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ -#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ -#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ -#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ -#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ -#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ -#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ -#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ -#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ -#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ -#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ -#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ -#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ -#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ -#define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ -#define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ +/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ +#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/ +#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */ +#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ +#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ +#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ +#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ +#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ +#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */ +#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ +#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ +#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ +#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ +#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ +#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ +#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ +#define X86_FEATURE_RDSEED ( 9*32+18) /* RDSEED instruction */ +#define X86_FEATURE_ADX ( 9*32+19) /* ADCX and ADOX instructions */ +#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ +#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ +#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ +#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ +#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ +#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ +#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ +#define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ +#define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ -/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ -#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ -#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ -#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ +/* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */ +#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT instruction */ +#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC instruction */ +#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */ +#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */ -/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ -#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ +/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */ +#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ -/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ -#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ -#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ -#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ +/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */ +#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring */ +#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ +#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ -/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ -#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ -#define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */ +/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ +#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ +#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ -/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ -#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ -#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ -#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ -#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ -#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ -#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ -#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ -#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ -#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ -#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ +/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ +#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ +#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ +#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ +#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ +#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ +#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ +#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ +#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ +#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ +#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ -/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ -#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ -#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ -#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ -#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ -#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ -#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ -#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ -#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ -#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ -#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ -#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ -#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ -#define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ +/* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ +#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ +#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ +#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ +#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ +#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ +#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ +#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ +#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ +#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ +#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ +#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ +#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ +#define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ -/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ -#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ -#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ -#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ -#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ -#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ -#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ +/* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ +#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ +#define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ +#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ +#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ +#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ +#define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ +#define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ +#define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */ +#define X86_FEATURE_AVX512_VNNI (16*32+11) /* Vector Neural Network Instructions */ +#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */ +#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ +#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ +#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ -/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */ -#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */ -#define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */ -#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ +/* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */ +#define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */ +#define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */ +#define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */ /* * BUG word(s) */ -#define X86_BUG(x) (NCAPINTS*32 + (x)) +#define X86_BUG(x) (NCAPINTS*32 + (x)) -#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ -#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ -#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ -#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ -#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ -#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ -#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ -#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ -#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ +#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ +#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ +#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ +#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ +#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ +#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ +#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ +#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ +#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ #ifdef CONFIG_X86_32 /* * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional * to avoid confusion. */ -#define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */ +#define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */ #endif -#define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */ -#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ -#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ -#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ +#define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */ +#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ +#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ +#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ + #endif /* _ASM_X86_CPUFEATURES_H */ diff --git a/tools/arch/x86/include/asm/disabled-features.h b/tools/arch/x86/include/asm/disabled-features.h index c10c9128f54e..14d6d5007314 100644 --- a/tools/arch/x86/include/asm/disabled-features.h +++ b/tools/arch/x86/include/asm/disabled-features.h @@ -16,6 +16,12 @@ # define DISABLE_MPX (1<<(X86_FEATURE_MPX & 31)) #endif +#ifdef CONFIG_X86_INTEL_UMIP +# define DISABLE_UMIP 0 +#else +# define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) +#endif + #ifdef CONFIG_X86_64 # define DISABLE_VME (1<<(X86_FEATURE_VME & 31)) # define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31)) @@ -63,7 +69,7 @@ #define DISABLED_MASK13 0 #define DISABLED_MASK14 0 #define DISABLED_MASK15 0 -#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57) +#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP) #define DISABLED_MASK17 0 #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) -- GitLab From 85369131895643c6510416fdcb215a855d39afb1 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 7 Nov 2017 13:41:35 -0300 Subject: [PATCH 0253/2547] tools headers: Synchronize kernel ABI headers wrt SPDX tags Two more, that were just in perf/core and thus weren't covered by Ingo's latest headers synch, kcmp.h and prctl.h, silencing this: Warning: Kernel ABI header at 'tools/include/uapi/linux/kcmp.h' differs from latest version at 'include/uapi/linux/kcmp.h' Warning: Kernel ABI header at 'tools/include/uapi/linux/prctl.h' differs from latest version at 'include/uapi/linux/prctl.h' Cc: Adrian Hunter Cc: David Ahern Cc: Jiri Olsa Cc: Namhyung Kim Cc: Wang Nan Link: http://lkml.kernel.org/n/tip-2a0r7iybyqpkftllyy5t9hfk@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/include/uapi/linux/kcmp.h | 1 + tools/include/uapi/linux/prctl.h | 1 + 2 files changed, 2 insertions(+) diff --git a/tools/include/uapi/linux/kcmp.h b/tools/include/uapi/linux/kcmp.h index 481e103da78e..ef1305010925 100644 --- a/tools/include/uapi/linux/kcmp.h +++ b/tools/include/uapi/linux/kcmp.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _UAPI_LINUX_KCMP_H #define _UAPI_LINUX_KCMP_H diff --git a/tools/include/uapi/linux/prctl.h b/tools/include/uapi/linux/prctl.h index a8d0759a9e40..b640071421f7 100644 --- a/tools/include/uapi/linux/prctl.h +++ b/tools/include/uapi/linux/prctl.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _LINUX_PRCTL_H #define _LINUX_PRCTL_H -- GitLab From 0f1aabeb4932e48ce067cb8c88322277dd7af371 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 27 Nov 2017 11:35:52 -0300 Subject: [PATCH 0254/2547] tools headers: Synchronize perf_event.h header To get the changes in the 085b30625e39 ("perf/core: Add PERF_AUX_FLAG_COLLISION to report colliding samples") commit, that will be eventually used by perf to handle the ARM SPE architecture. Cc: Adrian Hunter Cc: David Ahern Cc: Jiri Olsa Cc: Namhyung Kim Cc: Wang Nan Cc: Will Deacon Link: https://lkml.kernel.org/n/tip-178ohv0oy0csq3kzfdk8ky4n@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/include/uapi/linux/perf_event.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h index 362493a2f950..b9a4953018ed 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -942,6 +942,7 @@ enum perf_callchain_context { #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ +#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ #define PERF_FLAG_FD_NO_GROUP (1UL << 0) #define PERF_FLAG_FD_OUTPUT (1UL << 1) -- GitLab From 8ce6d5eb01cba83db9077c88a533bfeff39c679c Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 27 Nov 2017 11:43:00 -0300 Subject: [PATCH 0255/2547] tools headers uapi: Synchronize drm/drm.h To pick up the new ioctls added in these csets: 3064abfa932b ("drm: Add CRTC_GET_SEQUENCE and CRTC_QUEUE_SEQUENCE ioctls [v3]") 62884cd386b8 ("drm: Add four ioctls for managing drm mode object leases [v7]") That will be automatically decoded (the ioctl cmd parameter, the structs will be supported when we start using eBPF for that, which is in the works). This silences this warning when building tools/perf: Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h' Cc: Adrian Hunter Cc: Dave Airlie Cc: David Ahern Cc: Jiri Olsa Cc: Keith Packard Cc: Namhyung Kim Cc: Wang Nan Link: https://lkml.kernel.org/n/tip-bivwf1pkfmi1ugpswbsxd9e9@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/include/uapi/drm/drm.h | 41 ++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/tools/include/uapi/drm/drm.h b/tools/include/uapi/drm/drm.h index 97677cd6964d..6fdff5945c8a 100644 --- a/tools/include/uapi/drm/drm.h +++ b/tools/include/uapi/drm/drm.h @@ -737,6 +737,28 @@ struct drm_syncobj_array { __u32 pad; }; +/* Query current scanout sequence number */ +struct drm_crtc_get_sequence { + __u32 crtc_id; /* requested crtc_id */ + __u32 active; /* return: crtc output is active */ + __u64 sequence; /* return: most recent vblank sequence */ + __s64 sequence_ns; /* return: most recent time of first pixel out */ +}; + +/* Queue event to be delivered at specified sequence. Time stamp marks + * when the first pixel of the refresh cycle leaves the display engine + * for the display + */ +#define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */ +#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */ + +struct drm_crtc_queue_sequence { + __u32 crtc_id; + __u32 flags; + __u64 sequence; /* on input, target sequence. on output, actual sequence */ + __u64 user_data; /* user data passed to event */ +}; + #if defined(__cplusplus) } #endif @@ -819,6 +841,9 @@ extern "C" { #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) +#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) +#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) + #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) @@ -863,6 +888,11 @@ extern "C" { #define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) #define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) +#define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease) +#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees) +#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) +#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) + /** * Device specific ioctls should only be in their respective headers * The device specific ioctl range is from 0x40 to 0x9f. @@ -893,6 +923,7 @@ struct drm_event { #define DRM_EVENT_VBLANK 0x01 #define DRM_EVENT_FLIP_COMPLETE 0x02 +#define DRM_EVENT_CRTC_SEQUENCE 0x03 struct drm_event_vblank { struct drm_event base; @@ -903,6 +934,16 @@ struct drm_event_vblank { __u32 crtc_id; /* 0 on older kernels that do not support this */ }; +/* Event delivered at sequence. Time stamp marks when the first pixel + * of the refresh cycle leaves the display engine for the display + */ +struct drm_event_crtc_sequence { + struct drm_event base; + __u64 user_data; + __s64 time_ns; + __u64 sequence; +}; + /* typedef area */ #ifndef __KERNEL__ typedef struct drm_clip_rect drm_clip_rect_t; -- GitLab From 485be0cb0c71da167cb7f27c20130dc04fec33ff Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 27 Nov 2017 11:50:07 -0300 Subject: [PATCH 0256/2547] tools headers: Synchronize drm/i915_drm.h To pick up the changes from these csets: bf64e0b00e1f ("drm/i915: Expand I915_PARAM_HAS_SCHEDULER into a capability bitmask") ac14fbd460d0 ("drm/i915/scheduler: Support user-defined priorities") 822a4b673284 ("drm/i915: Don't use BIT() in UAPI section") 3fd3a6ffe279 ("drm/i915: Simplify i915_reg_read_ioctl") None of them affects how the tools are built, this os done just to silence this perf build warning: Warning: Kernel ABI header at 'tools/include/uapi/drm/i915_drm.h' differs from latest version at 'include/uapi/drm/i915_drm.h' Cc: Adrian Hunter Cc: Chris Wilson Cc: David Ahern Cc: Jiri Olsa Cc: Joonas Lahtinen Cc: Namhyung Kim Cc: Wang Nan Link: https://lkml.kernel.org/n/tip-d2gor8brpcowe7bcxovjhqwm@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/include/uapi/drm/i915_drm.h | 33 +++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/tools/include/uapi/drm/i915_drm.h b/tools/include/uapi/drm/i915_drm.h index 9816590d3ad2..ac3c6503ca27 100644 --- a/tools/include/uapi/drm/i915_drm.h +++ b/tools/include/uapi/drm/i915_drm.h @@ -397,10 +397,20 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_MIN_EU_IN_POOL 39 #define I915_PARAM_MMAP_GTT_VERSION 40 -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution +/* + * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution * priorities and the driver will attempt to execute batches in priority order. + * The param returns a capability bitmask, nonzero implies that the scheduler + * is enabled, with different features present according to the mask. + * + * The initial priority for each batch is supplied by the context and is + * controlled via I915_CONTEXT_PARAM_PRIORITY. */ #define I915_PARAM_HAS_SCHEDULER 41 +#define I915_SCHEDULER_CAP_ENABLED (1ul << 0) +#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) +#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) + #define I915_PARAM_HUC_STATUS 42 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of @@ -1309,14 +1319,16 @@ struct drm_i915_reg_read { * be specified */ __u64 offset; +#define I915_REG_READ_8B_WA (1ul << 0) + __u64 val; /* Return value */ }; /* Known registers: * * Render engine timestamp - 0x2358 + 64bit - gen7+ * - Note this register returns an invalid value if using the default - * single instruction 8byte read, in order to workaround that use - * offset (0x2538 | 1) instead. + * single instruction 8byte read, in order to workaround that pass + * flag I915_REG_READ_8B_WA in offset field. * */ @@ -1359,6 +1371,10 @@ struct drm_i915_gem_context_param { #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 #define I915_CONTEXT_PARAM_BANNABLE 0x5 +#define I915_CONTEXT_PARAM_PRIORITY 0x6 +#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ +#define I915_CONTEXT_DEFAULT_PRIORITY 0 +#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ __u64 value; }; @@ -1510,9 +1526,14 @@ struct drm_i915_perf_oa_config { __u32 n_boolean_regs; __u32 n_flex_regs; - __u64 __user mux_regs_ptr; - __u64 __user boolean_regs_ptr; - __u64 __user flex_regs_ptr; + /* + * These fields are pointers to tuples of u32 values (register + * address, value). For example the expected length of the buffer + * pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs). + */ + __u64 mux_regs_ptr; + __u64 boolean_regs_ptr; + __u64 flex_regs_ptr; }; #if defined(__cplusplus) -- GitLab From 374fbe56068c36126fc6903aaaa78f1ae8a95f91 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 27 Nov 2017 12:04:21 -0300 Subject: [PATCH 0257/2547] tools headers: Synchronize KVM arch ABI headers To pick up changes from these csets: da9a1446d248 ("KVM: s390: provide a capability for AIS state migration") 5c5196da4e96 ("KVM: arm/arm64: Support EL1 phys timer register access in set/get reg") None of which affects buildint tools/perf/. Cc: Adrian Hunter Cc: Christian Borntraeger Cc: Christoffer Dall Cc: David Ahern Cc: Jiri Olsa Cc: Namhyung Kim Cc: Wang Nan Link: https://lkml.kernel.org/n/tip-dd72s6izo4qdzt1isowlz8ji@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/arch/arm/include/uapi/asm/kvm.h | 7 +++++++ tools/arch/arm64/include/uapi/asm/kvm.h | 7 +++++++ tools/include/uapi/linux/kvm.h | 1 + 3 files changed, 15 insertions(+) diff --git a/tools/arch/arm/include/uapi/asm/kvm.h b/tools/arch/arm/include/uapi/asm/kvm.h index 1f57bbe82b6f..6edd177bb1c7 100644 --- a/tools/arch/arm/include/uapi/asm/kvm.h +++ b/tools/arch/arm/include/uapi/asm/kvm.h @@ -152,6 +152,12 @@ struct kvm_arch_memory_slot { (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64) #define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__) +/* PL1 Physical Timer Registers */ +#define KVM_REG_ARM_PTIMER_CTL ARM_CP15_REG32(0, 14, 2, 1) +#define KVM_REG_ARM_PTIMER_CNT ARM_CP15_REG64(0, 14) +#define KVM_REG_ARM_PTIMER_CVAL ARM_CP15_REG64(2, 14) + +/* Virtual Timer Registers */ #define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1) #define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14) #define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14) @@ -216,6 +222,7 @@ struct kvm_arch_memory_slot { #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 +#define KVM_DEV_ARM_ITS_CTRL_RESET 4 /* KVM_IRQ_LINE irq field index values */ #define KVM_ARM_IRQ_TYPE_SHIFT 24 diff --git a/tools/arch/arm64/include/uapi/asm/kvm.h b/tools/arch/arm64/include/uapi/asm/kvm.h index 51149ec75fe4..9abbf3044654 100644 --- a/tools/arch/arm64/include/uapi/asm/kvm.h +++ b/tools/arch/arm64/include/uapi/asm/kvm.h @@ -196,6 +196,12 @@ struct kvm_arch_memory_slot { #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) +/* Physical Timer EL0 Registers */ +#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) +#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) +#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) + +/* EL0 Virtual Timer Registers */ #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) @@ -228,6 +234,7 @@ struct kvm_arch_memory_slot { #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 +#define KVM_DEV_ARM_ITS_CTRL_RESET 4 /* Device Control API on vcpu fd */ #define KVM_ARM_VCPU_PMU_V3_CTRL 0 diff --git a/tools/include/uapi/linux/kvm.h b/tools/include/uapi/linux/kvm.h index 7e99999d6236..282d7613fce8 100644 --- a/tools/include/uapi/linux/kvm.h +++ b/tools/include/uapi/linux/kvm.h @@ -931,6 +931,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_PPC_SMT_POSSIBLE 147 #define KVM_CAP_HYPERV_SYNIC2 148 #define KVM_CAP_HYPERV_VP_INDEX 149 +#define KVM_CAP_S390_AIS_MIGRATION 150 #ifdef KVM_CAP_IRQ_ROUTING -- GitLab From d9744f940923ea341a289d1920a55e3a3de7fc9a Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 27 Nov 2017 12:11:02 -0300 Subject: [PATCH 0258/2547] tools headers: Synchronize prctl.h ABI header To pick up changes from: 2d2123bc7c7f ("arm64/sve: Add prctl controls for userspace vector length management") 7582e22038a2 ("arm64/sve: Backend logic for setting the vector length") That showed a limitation of the regexp used in tools/perf/trace/beauty/prctl_option.sh, that matches only PR_{SET,GET}_, but should match a few more, like PR_MPX_*, PR_CAP_* and the one added by the above commit, PR_SVE_SET_*. This silences this warning when building tools/perf: Warning: Kernel ABI header at 'tools/include/uapi/linux/prctl.h' differs from latest version at 'include/uapi/linux/prctl.h' Support for those extra prctl options should be left for the next merge window tho. Cc: Adrian Hunter Cc: Dave Martin Cc: David Ahern Cc: Jiri Olsa Cc: Namhyung Kim Cc: Wang Nan Cc: Will Deacon Link: https://lkml.kernel.org/n/tip-r52dsyuzy04qzqyfcifjs35t@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/include/uapi/linux/prctl.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tools/include/uapi/linux/prctl.h b/tools/include/uapi/linux/prctl.h index b640071421f7..af5f8c2df87a 100644 --- a/tools/include/uapi/linux/prctl.h +++ b/tools/include/uapi/linux/prctl.h @@ -198,4 +198,13 @@ struct prctl_mm_map { # define PR_CAP_AMBIENT_LOWER 3 # define PR_CAP_AMBIENT_CLEAR_ALL 4 +/* arm64 Scalable Vector Extension controls */ +/* Flag values must be kept in sync with ptrace NT_ARM_SVE interface */ +#define PR_SVE_SET_VL 50 /* set task vector length */ +# define PR_SVE_SET_VL_ONEXEC (1 << 18) /* defer effect until exec */ +#define PR_SVE_GET_VL 51 /* get task vector length */ +/* Bits common to PR_SVE_SET_VL and PR_SVE_GET_VL */ +# define PR_SVE_VL_LEN_MASK 0xffff +# define PR_SVE_VL_INHERIT (1 << 17) /* inherit across exec */ + #endif /* _LINUX_PRCTL_H */ -- GitLab From 1b3b5219abfd6a214e99018747e9fe98514b43ca Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 27 Nov 2017 12:18:23 -0300 Subject: [PATCH 0259/2547] tools headers: Syncronize mman.h ABI header To add support for the MAP_SYNC flag introduced in: b6fb293f2497 ("mm: Define MAP_SYNC and VM_SYNC flags") Update tools/perf/trace/beauty/mmap.c to support that flag. This silences this perf build warning: Warning: Kernel ABI header at 'tools/include/uapi/asm-generic/mman.h' differs from latest version at 'include/uapi/asm-generic/mman.h' Cc: Adrian Hunter Cc: Dan Williams Cc: David Ahern Cc: Jan Kara Cc: Jiri Olsa Cc: Namhyung Kim Cc: Wang Nan Link: https://lkml.kernel.org/n/tip-14zyk3iywrj37c7g1eagmzbo@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/include/uapi/asm-generic/mman.h | 1 + tools/perf/trace/beauty/mmap.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/tools/include/uapi/asm-generic/mman.h b/tools/include/uapi/asm-generic/mman.h index 2dffcbf705b3..653687d9771b 100644 --- a/tools/include/uapi/asm-generic/mman.h +++ b/tools/include/uapi/asm-generic/mman.h @@ -13,6 +13,7 @@ #define MAP_NONBLOCK 0x10000 /* do not block on IO */ #define MAP_STACK 0x20000 /* give out an address that is best suited for process/thread stacks */ #define MAP_HUGETLB 0x40000 /* create a huge page mapping */ +#define MAP_SYNC 0x80000 /* perform synchronous page faults for the mapping */ /* Bits [26:31] are reserved, see mman-common.h for MAP_HUGETLB usage */ diff --git a/tools/perf/trace/beauty/mmap.c b/tools/perf/trace/beauty/mmap.c index 9e1668b2c5d7..417e3ecfe9d7 100644 --- a/tools/perf/trace/beauty/mmap.c +++ b/tools/perf/trace/beauty/mmap.c @@ -62,6 +62,9 @@ static size_t syscall_arg__scnprintf_mmap_flags(char *bf, size_t size, P_MMAP_FLAG(POPULATE); P_MMAP_FLAG(STACK); P_MMAP_FLAG(UNINITIALIZED); +#ifdef MAP_SYNC + P_MMAP_FLAG(SYNC); +#endif #undef P_MMAP_FLAG if (flags) -- GitLab From 329b4130bc5eb2a1b123a652b985dbdb08d6b9a8 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Thu, 23 Nov 2017 13:21:55 +0300 Subject: [PATCH 0260/2547] ARC: Fix detection of dual-issue enabled As per PRM bit #0 ("D") in EXEC_CTRL enables dual-issue if set to 0, otherwise if set to 1 all instructions are executed one at a time, i.e. dual-issue is disabled. Signed-off-by: Alexey Brodkin Signed-off-by: Vineet Gupta --- arch/arc/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c index 7ef7d9a8ff89..9d27331fe69a 100644 --- a/arch/arc/kernel/setup.c +++ b/arch/arc/kernel/setup.c @@ -199,7 +199,7 @@ static void read_arc_build_cfg_regs(void) unsigned int exec_ctrl; READ_BCR(AUX_EXEC_CTRL, exec_ctrl); - cpu->extn.dual_enb = exec_ctrl & 1; + cpu->extn.dual_enb = !(exec_ctrl & 1); /* dual issue always present for this core */ cpu->extn.dual = 1; -- GitLab From f006ed726a5e1f8c94cf2ad7545eeb9a11f3c694 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 5 Nov 2017 10:18:32 -0200 Subject: [PATCH 0261/2547] ARM: dts: vf610-zii-dev-rev-c: Fix the I2C EEPROM address at24mac602 should be at the I2C address 0x50, so that it matches the 'reg' property. Fixes: d4cd158176c3 ("ARM: dts: vf610-zii-dev: Add .dts file for rev. C") Signed-off-by: Fabio Estevam Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev-rev-c.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts index 02a6227c717c..fbb3758ca2e3 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts @@ -359,7 +359,7 @@ }; &i2c1 { - at24mac602@0 { + at24mac602@50 { compatible = "atmel,24c02"; reg = <0x50>; read-only; -- GitLab From e501506d3ea00eefa64463ebd9e5c13ee70990bd Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 15 Nov 2017 10:03:53 -0200 Subject: [PATCH 0262/2547] Revert "ARM: dts: imx53: add srtc node" This reverts commit 5b725054147deaf966b3919e10a86c6bfe946a18. The rtc block on i.MX53 is a completely different hardware than the one found on i.MX25. Cc: #4.14 Reported-by: Noel Vellemans Suggested-by: Juergen Borleis Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 589a67c5f796..84f17f7abb71 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -433,15 +433,6 @@ clock-names = "ipg", "per"; }; - srtc: srtc@53fa4000 { - compatible = "fsl,imx53-rtc", "fsl,imx25-rtc"; - reg = <0x53fa4000 0x4000>; - interrupts = <24>; - interrupt-parent = <&tzic>; - clocks = <&clks IMX5_CLK_SRTC_GATE>; - clock-names = "ipg"; - }; - iomuxc: iomuxc@53fa8000 { compatible = "fsl,imx53-iomuxc"; reg = <0x53fa8000 0x4000>; -- GitLab From d2890c3778b164fde587bc16583f3a1c87233ec5 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Sun, 26 Nov 2017 23:16:49 -0800 Subject: [PATCH 0263/2547] crypto: rsa - fix buffer overread when stripping leading zeroes In rsa_get_n(), if the buffer contained all 0's and "FIPS mode" is enabled, we would read one byte past the end of the buffer while scanning the leading zeroes. Fix it by checking 'n_sz' before '!*ptr'. This bug was reachable by adding a specially crafted key of type "asymmetric" (requires CONFIG_RSA and CONFIG_X509_CERTIFICATE_PARSER). KASAN report: BUG: KASAN: slab-out-of-bounds in rsa_get_n+0x19e/0x1d0 crypto/rsa_helper.c:33 Read of size 1 at addr ffff88003501a708 by task keyctl/196 CPU: 1 PID: 196 Comm: keyctl Not tainted 4.14.0-09238-g1d3b78bbc6e9 #26 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.11.0-20171110_100015-anatol 04/01/2014 Call Trace: rsa_get_n+0x19e/0x1d0 crypto/rsa_helper.c:33 asn1_ber_decoder+0x82a/0x1fd0 lib/asn1_decoder.c:328 rsa_set_pub_key+0xd3/0x320 crypto/rsa.c:278 crypto_akcipher_set_pub_key ./include/crypto/akcipher.h:364 [inline] pkcs1pad_set_pub_key+0xae/0x200 crypto/rsa-pkcs1pad.c:117 crypto_akcipher_set_pub_key ./include/crypto/akcipher.h:364 [inline] public_key_verify_signature+0x270/0x9d0 crypto/asymmetric_keys/public_key.c:106 x509_check_for_self_signed+0x2ea/0x480 crypto/asymmetric_keys/x509_public_key.c:141 x509_cert_parse+0x46a/0x620 crypto/asymmetric_keys/x509_cert_parser.c:129 x509_key_preparse+0x61/0x750 crypto/asymmetric_keys/x509_public_key.c:174 asymmetric_key_preparse+0xa4/0x150 crypto/asymmetric_keys/asymmetric_type.c:388 key_create_or_update+0x4d4/0x10a0 security/keys/key.c:850 SYSC_add_key security/keys/keyctl.c:122 [inline] SyS_add_key+0xe8/0x290 security/keys/keyctl.c:62 entry_SYSCALL_64_fastpath+0x1f/0x96 Allocated by task 196: __do_kmalloc mm/slab.c:3711 [inline] __kmalloc_track_caller+0x118/0x2e0 mm/slab.c:3726 kmemdup+0x17/0x40 mm/util.c:118 kmemdup ./include/linux/string.h:414 [inline] x509_cert_parse+0x2cb/0x620 crypto/asymmetric_keys/x509_cert_parser.c:106 x509_key_preparse+0x61/0x750 crypto/asymmetric_keys/x509_public_key.c:174 asymmetric_key_preparse+0xa4/0x150 crypto/asymmetric_keys/asymmetric_type.c:388 key_create_or_update+0x4d4/0x10a0 security/keys/key.c:850 SYSC_add_key security/keys/keyctl.c:122 [inline] SyS_add_key+0xe8/0x290 security/keys/keyctl.c:62 entry_SYSCALL_64_fastpath+0x1f/0x96 Fixes: 5a7de97309f5 ("crypto: rsa - return raw integers for the ASN.1 parser") Cc: # v4.8+ Cc: Tudor Ambarus Signed-off-by: Eric Biggers Reviewed-by: James Morris Reviewed-by: David Howells Signed-off-by: Herbert Xu --- crypto/rsa_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/crypto/rsa_helper.c b/crypto/rsa_helper.c index 0b66dc824606..cad395d70d78 100644 --- a/crypto/rsa_helper.c +++ b/crypto/rsa_helper.c @@ -30,7 +30,7 @@ int rsa_get_n(void *context, size_t hdrlen, unsigned char tag, return -EINVAL; if (fips_enabled) { - while (!*ptr && n_sz) { + while (n_sz && !*ptr) { ptr++; n_sz--; } -- GitLab From b32a7dc8aef1882fbf983eb354837488cc9d54dc Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Mon, 27 Nov 2017 23:23:05 -0800 Subject: [PATCH 0264/2547] crypto: algif_aead - fix reference counting of null skcipher In the AEAD interface for AF_ALG, the reference to the "null skcipher" held by each tfm was being dropped in the wrong place -- when each af_alg_ctx was freed instead of when the aead_tfm was freed. As discovered by syzkaller, a specially crafted program could use this to cause the null skcipher to be freed while it is still in use. Fix it by dropping the reference in the right place. Fixes: 72548b093ee3 ("crypto: algif_aead - copy AAD from src to dst") Reported-by: syzbot Cc: # v4.14+ Signed-off-by: Eric Biggers Reviewed-by: Stephan Mueller Signed-off-by: Herbert Xu --- crypto/algif_aead.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/crypto/algif_aead.c b/crypto/algif_aead.c index aacae0837aff..9d73be28cf01 100644 --- a/crypto/algif_aead.c +++ b/crypto/algif_aead.c @@ -487,6 +487,7 @@ static void aead_release(void *private) struct aead_tfm *tfm = private; crypto_free_aead(tfm->aead); + crypto_put_default_null_skcipher2(); kfree(tfm); } @@ -519,7 +520,6 @@ static void aead_sock_destruct(struct sock *sk) unsigned int ivlen = crypto_aead_ivsize(tfm); af_alg_pull_tsgl(sk, ctx->used, NULL, 0); - crypto_put_default_null_skcipher2(); sock_kzfree_s(sk, ctx->iv, ivlen); sock_kfree_s(sk, ctx, ctx->len); af_alg_release_parent(sk); -- GitLab From 887207ed9e5812ed9239b6d07185a2d35dda91db Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Tue, 28 Nov 2017 00:46:24 -0800 Subject: [PATCH 0265/2547] crypto: af_alg - fix NULL pointer dereference in af_alg_free_areq_sgls() If allocating the ->tsgl member of 'struct af_alg_async_req' failed, during cleanup we dereferenced the NULL ->tsgl pointer in af_alg_free_areq_sgls(), because ->tsgl_entries was nonzero. Fix it by only freeing the ->tsgl list if it is non-NULL. This affected both algif_skcipher and algif_aead. Fixes: e870456d8e7c ("crypto: algif_skcipher - overhaul memory management") Fixes: d887c52d6ae4 ("crypto: algif_aead - overhaul memory management") Reported-by: syzbot Cc: # v4.14+ Signed-off-by: Eric Biggers Reviewed-by: Stephan Mueller Signed-off-by: Herbert Xu --- crypto/af_alg.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/crypto/af_alg.c b/crypto/af_alg.c index 85cea9de324a..1e5353f62067 100644 --- a/crypto/af_alg.c +++ b/crypto/af_alg.c @@ -672,14 +672,15 @@ void af_alg_free_areq_sgls(struct af_alg_async_req *areq) } tsgl = areq->tsgl; - for_each_sg(tsgl, sg, areq->tsgl_entries, i) { - if (!sg_page(sg)) - continue; - put_page(sg_page(sg)); - } + if (tsgl) { + for_each_sg(tsgl, sg, areq->tsgl_entries, i) { + if (!sg_page(sg)) + continue; + put_page(sg_page(sg)); + } - if (areq->tsgl && areq->tsgl_entries) sock_kfree_s(sk, tsgl, areq->tsgl_entries * sizeof(*tsgl)); + } } EXPORT_SYMBOL_GPL(af_alg_free_areq_sgls); -- GitLab From af3ff8045bbf3e32f1a448542e73abb4c8ceb6f1 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Tue, 28 Nov 2017 18:01:38 -0800 Subject: [PATCH 0266/2547] crypto: hmac - require that the underlying hash algorithm is unkeyed Because the HMAC template didn't check that its underlying hash algorithm is unkeyed, trying to use "hmac(hmac(sha3-512-generic))" through AF_ALG or through KEYCTL_DH_COMPUTE resulted in the inner HMAC being used without having been keyed, resulting in sha3_update() being called without sha3_init(), causing a stack buffer overflow. This is a very old bug, but it seems to have only started causing real problems when SHA-3 support was added (requires CONFIG_CRYPTO_SHA3) because the innermost hash's state is ->import()ed from a zeroed buffer, and it just so happens that other hash algorithms are fine with that, but SHA-3 is not. However, there could be arch or hardware-dependent hash algorithms also affected; I couldn't test everything. Fix the bug by introducing a function crypto_shash_alg_has_setkey() which tests whether a shash algorithm is keyed. Then update the HMAC template to require that its underlying hash algorithm is unkeyed. Here is a reproducer: #include #include int main() { int algfd; struct sockaddr_alg addr = { .salg_type = "hash", .salg_name = "hmac(hmac(sha3-512-generic))", }; char key[4096] = { 0 }; algfd = socket(AF_ALG, SOCK_SEQPACKET, 0); bind(algfd, (const struct sockaddr *)&addr, sizeof(addr)); setsockopt(algfd, SOL_ALG, ALG_SET_KEY, key, sizeof(key)); } Here was the KASAN report from syzbot: BUG: KASAN: stack-out-of-bounds in memcpy include/linux/string.h:341 [inline] BUG: KASAN: stack-out-of-bounds in sha3_update+0xdf/0x2e0 crypto/sha3_generic.c:161 Write of size 4096 at addr ffff8801cca07c40 by task syzkaller076574/3044 CPU: 1 PID: 3044 Comm: syzkaller076574 Not tainted 4.14.0-mm1+ #25 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 Call Trace: __dump_stack lib/dump_stack.c:17 [inline] dump_stack+0x194/0x257 lib/dump_stack.c:53 print_address_description+0x73/0x250 mm/kasan/report.c:252 kasan_report_error mm/kasan/report.c:351 [inline] kasan_report+0x25b/0x340 mm/kasan/report.c:409 check_memory_region_inline mm/kasan/kasan.c:260 [inline] check_memory_region+0x137/0x190 mm/kasan/kasan.c:267 memcpy+0x37/0x50 mm/kasan/kasan.c:303 memcpy include/linux/string.h:341 [inline] sha3_update+0xdf/0x2e0 crypto/sha3_generic.c:161 crypto_shash_update+0xcb/0x220 crypto/shash.c:109 shash_finup_unaligned+0x2a/0x60 crypto/shash.c:151 crypto_shash_finup+0xc4/0x120 crypto/shash.c:165 hmac_finup+0x182/0x330 crypto/hmac.c:152 crypto_shash_finup+0xc4/0x120 crypto/shash.c:165 shash_digest_unaligned+0x9e/0xd0 crypto/shash.c:172 crypto_shash_digest+0xc4/0x120 crypto/shash.c:186 hmac_setkey+0x36a/0x690 crypto/hmac.c:66 crypto_shash_setkey+0xad/0x190 crypto/shash.c:64 shash_async_setkey+0x47/0x60 crypto/shash.c:207 crypto_ahash_setkey+0xaf/0x180 crypto/ahash.c:200 hash_setkey+0x40/0x90 crypto/algif_hash.c:446 alg_setkey crypto/af_alg.c:221 [inline] alg_setsockopt+0x2a1/0x350 crypto/af_alg.c:254 SYSC_setsockopt net/socket.c:1851 [inline] SyS_setsockopt+0x189/0x360 net/socket.c:1830 entry_SYSCALL_64_fastpath+0x1f/0x96 Reported-by: syzbot Cc: Signed-off-by: Eric Biggers Signed-off-by: Herbert Xu --- crypto/hmac.c | 6 +++++- crypto/shash.c | 5 +++-- include/crypto/internal/hash.h | 8 ++++++++ 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/crypto/hmac.c b/crypto/hmac.c index 92871dc2a63e..e74730224f0a 100644 --- a/crypto/hmac.c +++ b/crypto/hmac.c @@ -195,11 +195,15 @@ static int hmac_create(struct crypto_template *tmpl, struct rtattr **tb) salg = shash_attr_alg(tb[1], 0, 0); if (IS_ERR(salg)) return PTR_ERR(salg); + alg = &salg->base; + /* The underlying hash algorithm must be unkeyed */ err = -EINVAL; + if (crypto_shash_alg_has_setkey(salg)) + goto out_put_alg; + ds = salg->digestsize; ss = salg->statesize; - alg = &salg->base; if (ds > alg->cra_blocksize || ss < alg->cra_blocksize) goto out_put_alg; diff --git a/crypto/shash.c b/crypto/shash.c index 325a14da5827..e849d3ee2e27 100644 --- a/crypto/shash.c +++ b/crypto/shash.c @@ -25,11 +25,12 @@ static const struct crypto_type crypto_shash_type; -static int shash_no_setkey(struct crypto_shash *tfm, const u8 *key, - unsigned int keylen) +int shash_no_setkey(struct crypto_shash *tfm, const u8 *key, + unsigned int keylen) { return -ENOSYS; } +EXPORT_SYMBOL_GPL(shash_no_setkey); static int shash_setkey_unaligned(struct crypto_shash *tfm, const u8 *key, unsigned int keylen) diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h index f0b44c16e88f..c2bae8da642c 100644 --- a/include/crypto/internal/hash.h +++ b/include/crypto/internal/hash.h @@ -82,6 +82,14 @@ int ahash_register_instance(struct crypto_template *tmpl, struct ahash_instance *inst); void ahash_free_instance(struct crypto_instance *inst); +int shash_no_setkey(struct crypto_shash *tfm, const u8 *key, + unsigned int keylen); + +static inline bool crypto_shash_alg_has_setkey(struct shash_alg *alg) +{ + return alg->setkey != shash_no_setkey; +} + int crypto_init_ahash_spawn(struct crypto_ahash_spawn *spawn, struct hash_alg_common *alg, struct crypto_instance *inst); -- GitLab From 9816ef6ecbc102b9bcbb1d83e12c7fb19924f38c Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 22 Nov 2017 11:58:03 +0300 Subject: [PATCH 0267/2547] scsi: lpfc: Use after free in lpfc_rq_buf_free() The error message dereferences "rqb_entry" so we need to print it first and then free the buffer. Fixes: 6c621a2229b0 ("scsi: lpfc: Separate NVMET RQ buffer posting from IO resources SGL/iocbq/context") Signed-off-by: Dan Carpenter Acked-by: Dick Kennedy Signed-off-by: Martin K. Petersen --- drivers/scsi/lpfc/lpfc_mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/scsi/lpfc/lpfc_mem.c b/drivers/scsi/lpfc/lpfc_mem.c index 56faeb049b4a..87c08ff37ddd 100644 --- a/drivers/scsi/lpfc/lpfc_mem.c +++ b/drivers/scsi/lpfc/lpfc_mem.c @@ -753,12 +753,12 @@ lpfc_rq_buf_free(struct lpfc_hba *phba, struct lpfc_dmabuf *mp) drqe.address_hi = putPaddrHigh(rqb_entry->dbuf.phys); rc = lpfc_sli4_rq_put(rqb_entry->hrq, rqb_entry->drq, &hrqe, &drqe); if (rc < 0) { - (rqbp->rqb_free_buffer)(phba, rqb_entry); lpfc_printf_log(phba, KERN_ERR, LOG_INIT, "6409 Cannot post to RQ %d: %x %x\n", rqb_entry->hrq->queue_id, rqb_entry->hrq->host_index, rqb_entry->hrq->hba_index); + (rqbp->rqb_free_buffer)(phba, rqb_entry); } else { list_add_tail(&rqb_entry->hbuf.list, &rqbp->rqb_buffer_list); rqbp->buffer_count++; -- GitLab From fe55e79536a37348dcb0b7177ee5fda6deccb99a Mon Sep 17 00:00:00 2001 From: Martin Wilck Date: Sat, 25 Nov 2017 19:38:10 +0100 Subject: [PATCH 0268/2547] scsi: libfc: fix ELS request handling The modification of fc_lport_recv_els_req() in commit fcabb09e59a7 ("scsi: libfc: directly call ELS request handlers") caused certain requests not to be handled at all. Fix that. Fixes: fcabb09e59a7 ("scsi: libfc: directly call ELS request handlers") Signed-off-by: Martin Wilck Reviewed-by: Johannes Thumshirn Signed-off-by: Martin K. Petersen --- drivers/scsi/libfc/fc_lport.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/scsi/libfc/fc_lport.c b/drivers/scsi/libfc/fc_lport.c index 5da46052e179..21be672679fb 100644 --- a/drivers/scsi/libfc/fc_lport.c +++ b/drivers/scsi/libfc/fc_lport.c @@ -904,10 +904,14 @@ static void fc_lport_recv_els_req(struct fc_lport *lport, case ELS_FLOGI: if (!lport->point_to_multipoint) fc_lport_recv_flogi_req(lport, fp); + else + fc_rport_recv_req(lport, fp); break; case ELS_LOGO: if (fc_frame_sid(fp) == FC_FID_FLOGI) fc_lport_recv_logo_req(lport, fp); + else + fc_rport_recv_req(lport, fp); break; case ELS_RSCN: lport->tt.disc_recv_req(lport, fp); -- GitLab From d18539754d97876503275efc7d00a1901bb0cfad Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 28 Nov 2017 14:25:25 +0100 Subject: [PATCH 0269/2547] scsi: aacraid: address UBSAN warning regression As reported by Meelis Roos, my previous patch causes an incorrect calculation of the timeout, through an undefined signed integer overflow: [ 12.228155] UBSAN: Undefined behaviour in drivers/scsi/aacraid/commsup.c:2514:49 [ 12.228229] signed integer overflow: [ 12.228283] 964297611 * 250 cannot be represented in type 'long int' The problem is that doing a multiplication with HZ first and then dividing by USEC_PER_SEC worked correctly for 32-bit microseconds, but not for 32-bit nanoseconds, which would require up to 41 bits. This reworks the calculation to first convert the nanoseconds into jiffies, which should give us the same result as before and not overflow. Unfortunately I did not understand the exact intention of the algorithm, in particular the part where we add half a second, so it's possible that there is still a preexisting problem in this function. I added a comment that this would be handled more nicely using usleep_range(), which generally works better for waking up at a particular time than the current schedule_timeout() based implementation. I did not feel comfortable trying to implement that without being sure what the intent is here though. Fixes: 820f18865912 ("scsi: aacraid: use timespec64 instead of timeval") Tested-by: Meelis Roos Signed-off-by: Arnd Bergmann Signed-off-by: Martin K. Petersen --- drivers/scsi/aacraid/commsup.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/aacraid/commsup.c b/drivers/scsi/aacraid/commsup.c index bec9f3193f60..80a8cb26cdea 100644 --- a/drivers/scsi/aacraid/commsup.c +++ b/drivers/scsi/aacraid/commsup.c @@ -2482,8 +2482,8 @@ int aac_command_thread(void *data) /* Synchronize our watches */ if (((NSEC_PER_SEC - (NSEC_PER_SEC / HZ)) > now.tv_nsec) && (now.tv_nsec > (NSEC_PER_SEC / HZ))) - difference = (((NSEC_PER_SEC - now.tv_nsec) * HZ) - + NSEC_PER_SEC / 2) / NSEC_PER_SEC; + difference = HZ + HZ / 2 - + now.tv_nsec / (NSEC_PER_SEC / HZ); else { if (now.tv_nsec > NSEC_PER_SEC / 2) ++now.tv_sec; @@ -2507,6 +2507,10 @@ int aac_command_thread(void *data) if (kthread_should_stop()) break; + /* + * we probably want usleep_range() here instead of the + * jiffies computation + */ schedule_timeout(difference); if (kthread_should_stop()) -- GitLab From 45349821ab3a8d378b8f37e52c6fe1aa1b870c47 Mon Sep 17 00:00:00 2001 From: Johannes Thumshirn Date: Tue, 28 Nov 2017 16:26:57 +0100 Subject: [PATCH 0270/2547] scsi: bfa: fix access to bfad_im_port_s MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 'cd21c605b2cf ("scsi: fc: provide fc_bsg_to_shost() helper")' changed access to bfa's 'struct bfad_im_port_s' by using shost_priv() instead of shost->hostdata[0]. This lead to crashes like in the following back-trace: task: ffff880046375300 ti: ffff8800a2ef8000 task.ti: ffff8800a2ef8000 RIP: e030:[] [] bfa_fcport_get_attr+0x82/0x260 [bfa] RSP: e02b:ffff8800a2efba10 EFLAGS: 00010046 RAX: 575f415441536432 RBX: ffff8800a2efba28 RCX: 0000000000000000 RDX: 0000000000000000 RSI: ffff8800a2efba28 RDI: ffff880004dc31d8 RBP: ffff880004dc31d8 R08: 0000000000000000 R09: 0000000000000001 R10: ffff88011fadc468 R11: 0000000000000001 R12: ffff880004dc31f0 R13: 0000000000000200 R14: ffff880004dc61d0 R15: ffff880004947a10 FS: 00007feb1e489700(0000) GS:ffff88011fac0000(0000) knlGS:0000000000000000 CS: e033 DS: 0000 ES: 0000 CR0: 000000008005003b CR2: 00007ffe14e46c10 CR3: 00000000957b8000 CR4: 0000000000000660 Stack: ffff88001d4da000 ffff880004dc31c0 ffffffffa048a9df ffffffff81e56380 0000000000000000 0000000000000000 0000000000000000 0000000000000000 [] bfad_iocmd_ioc_get_info+0x4f/0x220 [bfa] [] bfad_iocmd_handler+0xa00/0xd40 [bfa] [] bfad_im_bsg_request+0xee/0x1b0 [bfa] [] fc_bsg_dispatch+0x10b/0x1b0 [scsi_transport_fc] [] bsg_request_fn+0x11d/0x1c0 [] __blk_run_queue+0x2f/0x40 [] blk_execute_rq_nowait+0xa8/0x160 [] blk_execute_rq+0x77/0x120 [] bsg_ioctl+0x1b6/0x200 [] do_vfs_ioctl+0x2cd/0x4a0 [] SyS_ioctl+0x74/0x80 [] entry_SYSCALL_64_fastpath+0x12/0x6d Fixes: cd21c605b2cf ("scsi: fc: provide fc_bsg_to_shost() helper") Signed-off-by: Johannes Thumshirn Cc: Michal Koutný Reviewed-by: Hannes Reinecke Signed-off-by: Martin K. Petersen --- drivers/scsi/bfa/bfad_bsg.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/bfa/bfad_bsg.c b/drivers/scsi/bfa/bfad_bsg.c index 72ca2a2e08e2..09ef68c8225f 100644 --- a/drivers/scsi/bfa/bfad_bsg.c +++ b/drivers/scsi/bfa/bfad_bsg.c @@ -3135,7 +3135,8 @@ bfad_im_bsg_vendor_request(struct bsg_job *job) struct fc_bsg_request *bsg_request = job->request; struct fc_bsg_reply *bsg_reply = job->reply; uint32_t vendor_cmd = bsg_request->rqst_data.h_vendor.vendor_cmd[0]; - struct bfad_im_port_s *im_port = shost_priv(fc_bsg_to_shost(job)); + struct Scsi_Host *shost = fc_bsg_to_shost(job); + struct bfad_im_port_s *im_port = shost->hostdata[0]; struct bfad_s *bfad = im_port->bfad; void *payload_kbuf; int rc = -EINVAL; @@ -3350,7 +3351,8 @@ int bfad_im_bsg_els_ct_request(struct bsg_job *job) { struct bfa_bsg_data *bsg_data; - struct bfad_im_port_s *im_port = shost_priv(fc_bsg_to_shost(job)); + struct Scsi_Host *shost = fc_bsg_to_shost(job); + struct bfad_im_port_s *im_port = shost->hostdata[0]; struct bfad_s *bfad = im_port->bfad; bfa_bsg_fcpt_t *bsg_fcpt; struct bfad_fcxp *drv_fcxp; -- GitLab From ecaaab5649781c5a0effdaf298a925063020500e Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Tue, 28 Nov 2017 20:56:59 -0800 Subject: [PATCH 0271/2547] crypto: salsa20 - fix blkcipher_walk API usage When asked to encrypt or decrypt 0 bytes, both the generic and x86 implementations of Salsa20 crash in blkcipher_walk_done(), either when doing 'kfree(walk->buffer)' or 'free_page((unsigned long)walk->page)', because walk->buffer and walk->page have not been initialized. The bug is that Salsa20 is calling blkcipher_walk_done() even when nothing is in 'walk.nbytes'. But blkcipher_walk_done() is only meant to be called when a nonzero number of bytes have been provided. The broken code is part of an optimization that tries to make only one call to salsa20_encrypt_bytes() to process inputs that are not evenly divisible by 64 bytes. To fix the bug, just remove this "optimization" and use the blkcipher_walk API the same way all the other users do. Reproducer: #include #include #include int main() { int algfd, reqfd; struct sockaddr_alg addr = { .salg_type = "skcipher", .salg_name = "salsa20", }; char key[16] = { 0 }; algfd = socket(AF_ALG, SOCK_SEQPACKET, 0); bind(algfd, (void *)&addr, sizeof(addr)); reqfd = accept(algfd, 0, 0); setsockopt(algfd, SOL_ALG, ALG_SET_KEY, key, sizeof(key)); read(reqfd, key, sizeof(key)); } Reported-by: syzbot Fixes: eb6f13eb9f81 ("[CRYPTO] salsa20_generic: Fix multi-page processing") Cc: # v2.6.25+ Signed-off-by: Eric Biggers Signed-off-by: Herbert Xu --- arch/x86/crypto/salsa20_glue.c | 7 ------- crypto/salsa20_generic.c | 7 ------- 2 files changed, 14 deletions(-) diff --git a/arch/x86/crypto/salsa20_glue.c b/arch/x86/crypto/salsa20_glue.c index 399a29d067d6..cb91a64a99e7 100644 --- a/arch/x86/crypto/salsa20_glue.c +++ b/arch/x86/crypto/salsa20_glue.c @@ -59,13 +59,6 @@ static int encrypt(struct blkcipher_desc *desc, salsa20_ivsetup(ctx, walk.iv); - if (likely(walk.nbytes == nbytes)) - { - salsa20_encrypt_bytes(ctx, walk.src.virt.addr, - walk.dst.virt.addr, nbytes); - return blkcipher_walk_done(desc, &walk, 0); - } - while (walk.nbytes >= 64) { salsa20_encrypt_bytes(ctx, walk.src.virt.addr, walk.dst.virt.addr, diff --git a/crypto/salsa20_generic.c b/crypto/salsa20_generic.c index f550b5d94630..d7da0eea5622 100644 --- a/crypto/salsa20_generic.c +++ b/crypto/salsa20_generic.c @@ -188,13 +188,6 @@ static int encrypt(struct blkcipher_desc *desc, salsa20_ivsetup(ctx, walk.iv); - if (likely(walk.nbytes == nbytes)) - { - salsa20_encrypt_bytes(ctx, walk.dst.virt.addr, - walk.src.virt.addr, nbytes); - return blkcipher_walk_done(desc, &walk, 0); - } - while (walk.nbytes >= 64) { salsa20_encrypt_bytes(ctx, walk.dst.virt.addr, walk.src.virt.addr, -- GitLab From 9987da4b5dcfc8b94b702d4bb94b30955eb73c75 Mon Sep 17 00:00:00 2001 From: Joonas Lahtinen Date: Mon, 27 Nov 2017 11:12:33 +0200 Subject: [PATCH 0272/2547] drm/i915: Disable THP until we have a GPU read BW W/A We seem to be missing some W/A for 2M pages and are getting a hit on raw GPU read bandwidths (even 30%) even though the GPU write bandwidths improve (even 10%). For now, disable THP, which is our only practical source of 2M pages until we have a W/A for the issue. v2: - Be explicit that we talk about GPU bandwidths (Eero) - s/deny/never/ because that's why (Chris) Reported-by: Valtteri Rantala Fixes: b901bb89324a ("drm/i915/gemfs: enable THP") Signed-off-by: Joonas Lahtinen Cc: Matthew Auld Cc: Chris Wilson Cc: Jani Nikula Cc: Rodrigo Vivi Cc: Valtteri Rantala Cc: Eero Tamminen Reviewed-by: Chris Wilson Reviewed-by: Matthew Auld Tested-by: Valtteri Rantala Link: https://patchwork.freedesktop.org/patch/msgid/20171127091233.7001-1-joonas.lahtinen@linux.intel.com --- drivers/gpu/drm/i915/i915_gemfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gemfs.c b/drivers/gpu/drm/i915/i915_gemfs.c index e2993857df37..888b7d3f04c3 100644 --- a/drivers/gpu/drm/i915/i915_gemfs.c +++ b/drivers/gpu/drm/i915/i915_gemfs.c @@ -52,7 +52,8 @@ int i915_gemfs_init(struct drm_i915_private *i915) if (has_transparent_hugepage()) { struct super_block *sb = gemfs->mnt_sb; - char options[] = "huge=within_size"; + /* FIXME: Disabled until we get W/A for read BW issue. */ + char options[] = "huge=never"; int flags = 0; int err; -- GitLab From 6a53b7593233ab9e4f96873ebacc0f653a55c3e1 Mon Sep 17 00:00:00 2001 From: Cong Wang Date: Mon, 27 Nov 2017 11:15:16 -0800 Subject: [PATCH 0273/2547] xfrm: check id proto in validate_tmpl() syzbot reported a kernel warning in xfrm_state_fini(), which indicates that we have entries left in the list net->xfrm.state_all whose proto is zero. And xfrm_id_proto_match() doesn't consider them as a match with IPSEC_PROTO_ANY in this case. Proto with value 0 is probably not a valid value, at least verify_newsa_info() doesn't consider it valid either. This patch fixes it by checking the proto value in validate_tmpl() and rejecting invalid ones, like what iproute2 does in xfrm_xfrmproto_getbyname(). Reported-by: syzbot Cc: Steffen Klassert Cc: Herbert Xu Signed-off-by: Cong Wang Signed-off-by: Steffen Klassert --- net/xfrm/xfrm_user.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c index 983b0233767b..c2cfcc6fdb34 100644 --- a/net/xfrm/xfrm_user.c +++ b/net/xfrm/xfrm_user.c @@ -1445,6 +1445,21 @@ static int validate_tmpl(int nr, struct xfrm_user_tmpl *ut, u16 family) default: return -EINVAL; } + + switch (ut[i].id.proto) { + case IPPROTO_AH: + case IPPROTO_ESP: + case IPPROTO_COMP: +#if IS_ENABLED(CONFIG_IPV6) + case IPPROTO_ROUTING: + case IPPROTO_DSTOPTS: +#endif + case IPSEC_PROTO_ANY: + break; + default: + return -EINVAL; + } + } return 0; -- GitLab From f044113113dd95ba73916bde10e804d3cdfa2662 Mon Sep 17 00:00:00 2001 From: Jens Wiklander Date: Mon, 9 Oct 2017 11:11:49 +0200 Subject: [PATCH 0274/2547] optee: fix invalid of_node_put() in optee_driver_init() The first node supplied to of_find_matching_node() has its reference counter decreased as part of call to that function. In optee_driver_init() after calling of_find_matching_node() it's invalid to call of_node_put() on the supplied node again. So remove the invalid call to of_node_put(). Reported-by: Alex Shi Signed-off-by: Jens Wiklander --- drivers/tee/optee/core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index 7952357df9c8..edb6e4e9ef3a 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -590,7 +590,6 @@ static int __init optee_driver_init(void) return -ENODEV; np = of_find_matching_node(fw_np, optee_match); - of_node_put(fw_np); if (!np) return -ENODEV; -- GitLab From 4bd6683da2e64590bdc27ecf7e61ad8376861768 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 10 Nov 2017 19:55:18 +0200 Subject: [PATCH 0275/2547] pinctrl: denverton: Fix UART2 RTS pin mode UART2 RTS is mode 2 of the pin. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg Signed-off-by: Linus Walleij --- drivers/pinctrl/intel/pinctrl-denverton.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-denverton.c b/drivers/pinctrl/intel/pinctrl-denverton.c index 4500880240f2..6572550cfe78 100644 --- a/drivers/pinctrl/intel/pinctrl-denverton.c +++ b/drivers/pinctrl/intel/pinctrl-denverton.c @@ -207,7 +207,7 @@ static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 }; static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 }; static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 }; static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 }; -static const unsigned int dnv_uart2_modes[] = { 1, 1, 2, 2 }; +static const unsigned int dnv_uart2_modes[] = { 1, 2, 2, 2 }; static const unsigned int dnv_emmc_pins[] = { 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, }; -- GitLab From b89b6925bb9d48926d7ba713d3f13b14fc35c544 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Thu, 16 Nov 2017 11:55:18 -0800 Subject: [PATCH 0276/2547] ASoC: fsl_asrc: Fix typo in a field define ASRFSTi_IAEi has an 11-bit offset as its _SHIFT macro defines. So this patch just fixes that. Reported-by: Laurent Charpentier Signed-off-by: Nicolin Chen Reviewed-by: Fabio Estevam Signed-off-by: Mark Brown --- sound/soc/fsl/fsl_asrc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/fsl/fsl_asrc.h b/sound/soc/fsl/fsl_asrc.h index 0f163abe4ba3..52c27a358933 100644 --- a/sound/soc/fsl/fsl_asrc.h +++ b/sound/soc/fsl/fsl_asrc.h @@ -260,8 +260,8 @@ #define ASRFSTi_OUTPUT_FIFO_SHIFT 12 #define ASRFSTi_OUTPUT_FIFO_MASK (((1 << ASRFSTi_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTi_OUTPUT_FIFO_SHIFT) #define ASRFSTi_IAEi_SHIFT 11 -#define ASRFSTi_IAEi_MASK (1 << ASRFSTi_OAFi_SHIFT) -#define ASRFSTi_IAEi (1 << ASRFSTi_OAFi_SHIFT) +#define ASRFSTi_IAEi_MASK (1 << ASRFSTi_IAEi_SHIFT) +#define ASRFSTi_IAEi (1 << ASRFSTi_IAEi_SHIFT) #define ASRFSTi_INPUT_FIFO_WIDTH 7 #define ASRFSTi_INPUT_FIFO_SHIFT 0 #define ASRFSTi_INPUT_FIFO_MASK ((1 << ASRFSTi_INPUT_FIFO_WIDTH) - 1) -- GitLab From 439e2ee4ca520e72870e4fa44aa0076060ad6857 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Wed, 29 Nov 2017 08:24:09 +0000 Subject: [PATCH 0277/2547] drm/i915: Move engine->needs_cmd_parser to engine->flags Will be adding a new per-engine flags shortly so it makes sense to consolidate. v2: Keep the original code flow in intel_engine_cleanup_cmd_parser. (Joonas Lahtinen) Signed-off-by: Tvrtko Ursulin Suggested-by: Chris Wilson Reviewed-by: Chris Wilson Reviewed-by: Sagar Arun Kamble Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171129082409.18189-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_cmd_parser.c | 7 ++++--- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.h | 8 +++++++- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index b11629beeb63..ccb5ba043b63 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -26,6 +26,7 @@ */ #include "i915_drv.h" +#include "intel_ringbuffer.h" /** * DOC: batch buffer command parser @@ -940,7 +941,7 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine) return; } - engine->needs_cmd_parser = true; + engine->flags |= I915_ENGINE_NEEDS_CMD_PARSER; } /** @@ -952,7 +953,7 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine) */ void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine) { - if (!engine->needs_cmd_parser) + if (!intel_engine_needs_cmd_parser(engine)) return; fini_hash_table(engine); @@ -1350,7 +1351,7 @@ int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) /* If the command parser is not enabled, report 0 - unsupported */ for_each_engine(engine, dev_priv, id) { - if (engine->needs_cmd_parser) { + if (intel_engine_needs_cmd_parser(engine)) { active = true; break; } diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 14d9e61a1e06..70ccd63cbf8e 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -271,7 +271,7 @@ static inline u64 gen8_noncanonical_addr(u64 address) static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) { - return eb->engine->needs_cmd_parser && eb->batch_len; + return intel_engine_needs_cmd_parser(eb->engine) && eb->batch_len; } static int eb_create(struct i915_execbuffer *eb) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index ef304c99954c..2b978b363c0b 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -538,7 +538,8 @@ struct intel_engine_cs { struct intel_engine_hangcheck hangcheck; - bool needs_cmd_parser; +#define I915_ENGINE_NEEDS_CMD_PARSER BIT(0) + unsigned int flags; /* * Table of commands the command parser needs to know about @@ -597,6 +598,11 @@ struct intel_engine_cs { } stats; }; +static inline bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine) +{ + return engine->flags & I915_ENGINE_NEEDS_CMD_PARSER; +} + static inline void execlists_set_active(struct intel_engine_execlists *execlists, unsigned int bit) -- GitLab From cf669b4e9fdce4cf1a7bef4e7ab8b3db0da021a2 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Wed, 29 Nov 2017 10:28:05 +0000 Subject: [PATCH 0278/2547] drm/i915: Consolidate checks for engine stats availability Sagar noticed the check can be consolidated between the engine stats implementation and the PMU. My first choice was a static inline helper but that got into include ordering mess quickly fast so I went with a macro instead. At some point we should perhaps looking into taking out the non-ringubffer bits from intel_ringbuffer.h into a new intel_engine.h or something. v2: Use engine->flags. (Chris Wilson) v3: Rebase and mark GuC as not yet supported. (Chris Wilson) v4: Move flag setting to intel_engines_reset_default_submission. (Chris Wilson) v5: Move flag setting to logical_ring_setup. v6: intel_engines_reset_default_submission is the wrong place to set the flag - it needs to be in execlists_set_default_submission. (Sagar) v7: Flag setting in logical_ring_setup is not required. (Chris) Signed-off-by: Tvrtko Ursulin Suggested-by: Sagar Arun Kamble Cc: Sagar Arun Kamble Reviewed-by: Chris Wilson Reviewed-by: Sagar Arun Kamble (v6) Link: https://patchwork.freedesktop.org/patch/msgid/20171129102805.22690-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_pmu.c | 11 ++++------- drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++-- drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++ drivers/gpu/drm/i915/intel_lrc.c | 2 ++ drivers/gpu/drm/i915/intel_ringbuffer.h | 6 ++++++ 5 files changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 1c0ee9d68b04..e8e2faf4982f 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -90,11 +90,6 @@ static unsigned int event_enabled_bit(struct perf_event *event) return config_enabled_bit(event->attr.config); } -static bool supports_busy_stats(struct drm_i915_private *i915) -{ - return INTEL_GEN(i915) >= 8; -} - static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active) { u64 enable; @@ -123,8 +118,10 @@ static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active) /* * Also there is software busyness tracking available we do not * need the timer for I915_SAMPLE_BUSY counter. + * + * Use RCS as proxy for all engines. */ - else if (supports_busy_stats(i915)) + else if (intel_engine_supports_stats(i915->engine[RCS])) enable &= ~BIT(I915_SAMPLE_BUSY); /* @@ -447,7 +444,7 @@ static void i915_pmu_event_read(struct perf_event *event) static bool engine_needs_busy_stats(struct intel_engine_cs *engine) { - return supports_busy_stats(engine->i915) && + return intel_engine_supports_stats(engine) && (engine->pmu.enable & BIT(I915_SAMPLE_BUSY)); } diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index fede62daf3e1..cffd0c812b7e 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1863,7 +1863,7 @@ int intel_enable_engine_stats(struct intel_engine_cs *engine) { unsigned long flags; - if (INTEL_GEN(engine->i915) < 8) + if (!intel_engine_supports_stats(engine)) return -ENODEV; spin_lock_irqsave(&engine->stats.lock, flags); @@ -1924,7 +1924,7 @@ void intel_disable_engine_stats(struct intel_engine_cs *engine) { unsigned long flags; - if (INTEL_GEN(engine->i915) < 8) + if (!intel_engine_supports_stats(engine)) return; spin_lock_irqsave(&engine->stats.lock, flags); diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index cf1cc2cb6722..912ff143d531 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -1453,6 +1453,8 @@ int intel_guc_submission_enable(struct intel_guc *guc) execlists->tasklet.func = guc_submission_tasklet; engine->park = guc_submission_park; engine->unpark = guc_submission_unpark; + + engine->flags &= ~I915_ENGINE_SUPPORTS_STATS; } return 0; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 570864583e28..2a8160f603ab 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1919,6 +1919,8 @@ static void execlists_set_default_submission(struct intel_engine_cs *engine) engine->park = NULL; engine->unpark = NULL; + + engine->flags |= I915_ENGINE_SUPPORTS_STATS; } static void diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 2b978b363c0b..3d097bbeb2d9 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -539,6 +539,7 @@ struct intel_engine_cs { struct intel_engine_hangcheck hangcheck; #define I915_ENGINE_NEEDS_CMD_PARSER BIT(0) +#define I915_ENGINE_SUPPORTS_STATS BIT(1) unsigned int flags; /* @@ -603,6 +604,11 @@ static inline bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine) return engine->flags & I915_ENGINE_NEEDS_CMD_PARSER; } +static inline bool intel_engine_supports_stats(struct intel_engine_cs *engine) +{ + return engine->flags & I915_ENGINE_SUPPORTS_STATS; +} + static inline void execlists_set_active(struct intel_engine_execlists *execlists, unsigned int bit) -- GitLab From 6702abb3bf2394f250af0ee04070227bb5dda788 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 14 Nov 2017 17:51:50 +0100 Subject: [PATCH 0279/2547] pinctrl: armada-37xx: Fix direction_output() callback behavior The direction_output callback of the gpio_chip structure is supposed to set the output direction but also to set the value of the gpio. For the armada-37xx driver this callback acted as the gpio_set_direction callback for the pinctrl. This patch fixes the behavior of the direction_output callback by also applying the value received as parameter. Cc: stable@vger.kernel.org Fixes: 5715092a458c ("pinctrl: armada-37xx: Add gpio support") Reported-by: Alexandre Belloni Signed-off-by: Gregory CLEMENT Signed-off-by: Linus Walleij --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index d45af31b86b4..bdb8d174efef 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -408,12 +408,21 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip, { struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); unsigned int reg = OUTPUT_EN; - unsigned int mask; + unsigned int mask, val, ret; armada_37xx_update_reg(®, offset); mask = BIT(offset); - return regmap_update_bits(info->regmap, reg, mask, mask); + ret = regmap_update_bits(info->regmap, reg, mask, mask); + + if (ret) + return ret; + + reg = OUTPUT_VAL; + val = value ? mask : 0; + regmap_update_bits(info->regmap, reg, mask, val); + + return 0; } static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset) -- GitLab From 6af9bd453112bd0ee8f69e2c5c2e27bd725b1cb0 Mon Sep 17 00:00:00 2001 From: Dai Okamura Date: Tue, 28 Nov 2017 19:41:32 +0900 Subject: [PATCH 0280/2547] arm64: dts: uniphier: correct on-board device IRQ number for PXs3 Commit ba5b5034bd29 ("arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3") has incorrect update. Fixes: ba5b5034bd29 ("arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3") Signed-off-by: Dai Okamura Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts index 864feeb35180..6b5b6c285964 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts @@ -39,7 +39,7 @@ ðsc { interrupt-parent = <&gpio>; - interrupts = <0 8>; + interrupts = <4 8>; }; &serial0 { -- GitLab From 897281bac45c83c493d8dc1906dbee97950ad625 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Nov 2017 14:24:46 +0900 Subject: [PATCH 0281/2547] arm64: dts: uniphier: remove unnecessary interrupt-parent These were added to make the ARM64 branch self-contained because updates for ARM and ARM64 are supposed to be sent as separate pull requests. Now, they were merged together in Linus' tree and interrupt-parent from the arch/arm/boot/dts/uniphier-support-card.dtsi is visible from ARM64 DT files by the cross-arch reference. Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts | 1 - arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts | 1 - arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts index dd7193acc7df..6bdefb26b329 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts @@ -40,7 +40,6 @@ }; ðsc { - interrupt-parent = <&gpio>; interrupts = <0 8>; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts index d99e3731358c..254d6795c67e 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts @@ -40,7 +40,6 @@ }; ðsc { - interrupt-parent = <&gpio>; interrupts = <0 8>; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts index 6b5b6c285964..f9f06fcfb94a 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts @@ -38,7 +38,6 @@ }; ðsc { - interrupt-parent = <&gpio>; interrupts = <4 8>; }; -- GitLab From 0308cadcec379e510f498c48c34aafe582f1af88 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 28 Nov 2017 12:13:53 +0900 Subject: [PATCH 0282/2547] MAINTAINERS: exclude other Socionext SoC DT files from ARM/UNIPHIER entry MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are several product lines in Socionext. I maintain only DT files prefixed with "uniphier". Signed-off-by: Masahiro Yamada Reviewed-by: Andreas Färber --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index aa71ab52fd76..cbb89bb82d77 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2046,7 +2046,7 @@ F: arch/arm/boot/dts/uniphier* F: arch/arm/include/asm/hardware/cache-uniphier.h F: arch/arm/mach-uniphier/ F: arch/arm/mm/cache-uniphier.c -F: arch/arm64/boot/dts/socionext/ +F: arch/arm64/boot/dts/socionext/uniphier* F: drivers/bus/uniphier-system-bus.c F: drivers/clk/uniphier/ F: drivers/gpio/gpio-uniphier.c -- GitLab From 5c9afbda911ce20b3f2181d1e440a0222e1027dd Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Fri, 17 Nov 2017 22:37:53 +0100 Subject: [PATCH 0283/2547] dmaengine: ioat: Fix error handling path If the last test in 'ioat_dma_self_test()' fails, we must release all the allocated resources and not just part of them. Signed-off-by: Christophe JAILLET Acked-by: Dave Jiang Signed-off-by: Vinod Koul --- drivers/dma/ioat/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/ioat/init.c b/drivers/dma/ioat/init.c index 2f31d3d0caa6..7792a9186f9c 100644 --- a/drivers/dma/ioat/init.c +++ b/drivers/dma/ioat/init.c @@ -390,7 +390,7 @@ static int ioat_dma_self_test(struct ioatdma_device *ioat_dma) if (memcmp(src, dest, IOAT_TEST_SIZE)) { dev_err(dev, "Self-test copy failed compare, disabling\n"); err = -ENODEV; - goto free_resources; + goto unmap_dma; } unmap_dma: -- GitLab From 62a277d43d47e74972de44d33bd3763e31992414 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Mon, 20 Nov 2017 08:28:14 -0600 Subject: [PATCH 0284/2547] dmaengine: at_hdmac: fix potential NULL pointer dereference in atc_prep_dma_interleaved _xt_ is being dereferenced before it is null checked, hence there is a potential null pointer dereference. Fix this by moving the pointer dereference after _xt_ has been null checked. This issue was detected with the help of Coccinelle. Fixes: 4483320e241c ("dmaengine: Use Pointer xt after NULL check.") Signed-off-by: Gustavo A. R. Silva Acked-by: Ludovic Desroches Signed-off-by: Vinod Koul --- drivers/dma/at_hdmac.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index fbab271b3bf9..a861b5b4d443 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -708,7 +708,7 @@ atc_prep_dma_interleaved(struct dma_chan *chan, unsigned long flags) { struct at_dma_chan *atchan = to_at_dma_chan(chan); - struct data_chunk *first = xt->sgl; + struct data_chunk *first; struct at_desc *desc = NULL; size_t xfer_count; unsigned int dwidth; @@ -720,6 +720,8 @@ atc_prep_dma_interleaved(struct dma_chan *chan, if (unlikely(!xt || xt->numf != 1 || !xt->frame_size)) return NULL; + first = xt->sgl; + dev_info(chan2dev(chan), "%s: src=%pad, dest=%pad, numf=%d, frame_size=%d, flags=0x%lx\n", __func__, &xt->src_start, &xt->dst_start, xt->numf, -- GitLab From 3d7682af228fd78dc46bc6bf40e0268ad04521ec Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 29 Nov 2017 14:25:50 +0000 Subject: [PATCH 0285/2547] rxrpc: Clean up whitespace Clean up some whitespace from rxrpc. Signed-off-by: David Howells --- net/rxrpc/call_event.c | 2 +- net/rxrpc/conn_object.c | 2 +- net/rxrpc/input.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/net/rxrpc/call_event.c b/net/rxrpc/call_event.c index bda952ffe6a6..555274ddc514 100644 --- a/net/rxrpc/call_event.c +++ b/net/rxrpc/call_event.c @@ -426,7 +426,7 @@ void rxrpc_process_call(struct work_struct *work) next = call->expect_rx_by; #define set(T) { t = READ_ONCE(T); if (time_before(t, next)) next = t; } - + set(call->expect_req_by); set(call->expect_term_by); set(call->ack_at); diff --git a/net/rxrpc/conn_object.c b/net/rxrpc/conn_object.c index 1aad04a32d5e..c628351eb900 100644 --- a/net/rxrpc/conn_object.c +++ b/net/rxrpc/conn_object.c @@ -424,7 +424,7 @@ void rxrpc_service_connection_reaper(struct work_struct *work) if (earliest != now + MAX_JIFFY_OFFSET) { _debug("reschedule reaper %ld", (long)earliest - (long)now); ASSERT(time_after(earliest, now)); - rxrpc_set_service_reap_timer(rxnet, earliest); + rxrpc_set_service_reap_timer(rxnet, earliest); } while (!list_empty(&graveyard)) { diff --git a/net/rxrpc/input.c b/net/rxrpc/input.c index 23a5e61d8f79..6fc61400337f 100644 --- a/net/rxrpc/input.c +++ b/net/rxrpc/input.c @@ -976,7 +976,7 @@ static void rxrpc_input_call_packet(struct rxrpc_call *call, rxrpc_reduce_call_timer(call, expect_rx_by, now, rxrpc_timer_set_for_normal); } - + switch (sp->hdr.type) { case RXRPC_PACKET_TYPE_DATA: rxrpc_input_data(call, skb, skew); @@ -1213,7 +1213,7 @@ void rxrpc_data_ready(struct sock *udp_sk) goto reupgrade; conn->service_id = sp->hdr.serviceId; } - + if (sp->hdr.callNumber == 0) { /* Connection-level packet */ _debug("CONN %p {%d}", conn, conn->debug_id); -- GitLab From 5fc62f6a139a7b06b027bf442cd4205619506f59 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 29 Nov 2017 14:40:41 +0000 Subject: [PATCH 0286/2547] rxrpc: Fix ACK generation from the connection event processor Repeat terminal ACKs and now terminal ACKs are now generated from the connection event processor rather from call handling as this allows us to discard client call structures as soon as possible and free up the channel for a follow on call. However, in ACKs so generated, the additional information trailer is malformed because the padding that's meant to be in the middle isn't included in what's transmitted. Fix it so that the 3 bytes of padding are included in the transmission. Further, the trailer is misaligned because of the padding, so assigment to the u16 and u32 fields inside it might cause problems on some arches, so fix this by breaking the padding and the trailer out of the packed struct. (This also deals with potential compiler weirdies where some of the nested structs are packed and some aren't). The symptoms can be seen in wireshark as terminal DUPLICATE or IDLE ACK packets in which the Max MTU, Interface MTU and rwind fields have weird values and the Max Packets field is apparently missing. Reported-by: Jeffrey Altman Signed-off-by: David Howells --- net/rxrpc/conn_event.c | 50 ++++++++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/net/rxrpc/conn_event.c b/net/rxrpc/conn_event.c index 9e9a8db1bc9c..4ca11be6be3c 100644 --- a/net/rxrpc/conn_event.c +++ b/net/rxrpc/conn_event.c @@ -30,22 +30,18 @@ static void rxrpc_conn_retransmit_call(struct rxrpc_connection *conn, struct rxrpc_skb_priv *sp = skb ? rxrpc_skb(skb) : NULL; struct rxrpc_channel *chan; struct msghdr msg; - struct kvec iov; + struct kvec iov[3]; struct { struct rxrpc_wire_header whdr; union { - struct { - __be32 code; - } abort; - struct { - struct rxrpc_ackpacket ack; - u8 padding[3]; - struct rxrpc_ackinfo info; - }; + __be32 abort_code; + struct rxrpc_ackpacket ack; }; } __attribute__((packed)) pkt; + struct rxrpc_ackinfo ack_info; size_t len; - u32 serial, mtu, call_id; + int ioc; + u32 serial, mtu, call_id, padding; _enter("%d", conn->debug_id); @@ -66,6 +62,13 @@ static void rxrpc_conn_retransmit_call(struct rxrpc_connection *conn, msg.msg_controllen = 0; msg.msg_flags = 0; + iov[0].iov_base = &pkt; + iov[0].iov_len = sizeof(pkt.whdr); + iov[1].iov_base = &padding; + iov[1].iov_len = 3; + iov[2].iov_base = &ack_info; + iov[2].iov_len = sizeof(ack_info); + pkt.whdr.epoch = htonl(conn->proto.epoch); pkt.whdr.cid = htonl(conn->proto.cid); pkt.whdr.callNumber = htonl(call_id); @@ -80,8 +83,10 @@ static void rxrpc_conn_retransmit_call(struct rxrpc_connection *conn, len = sizeof(pkt.whdr); switch (chan->last_type) { case RXRPC_PACKET_TYPE_ABORT: - pkt.abort.code = htonl(chan->last_abort); - len += sizeof(pkt.abort); + pkt.abort_code = htonl(chan->last_abort); + iov[0].iov_len += sizeof(pkt.abort_code); + len += sizeof(pkt.abort_code); + ioc = 1; break; case RXRPC_PACKET_TYPE_ACK: @@ -94,13 +99,19 @@ static void rxrpc_conn_retransmit_call(struct rxrpc_connection *conn, pkt.ack.serial = htonl(skb ? sp->hdr.serial : 0); pkt.ack.reason = skb ? RXRPC_ACK_DUPLICATE : RXRPC_ACK_IDLE; pkt.ack.nAcks = 0; - pkt.info.rxMTU = htonl(rxrpc_rx_mtu); - pkt.info.maxMTU = htonl(mtu); - pkt.info.rwind = htonl(rxrpc_rx_window_size); - pkt.info.jumbo_max = htonl(rxrpc_rx_jumbo_max); + ack_info.rxMTU = htonl(rxrpc_rx_mtu); + ack_info.maxMTU = htonl(mtu); + ack_info.rwind = htonl(rxrpc_rx_window_size); + ack_info.jumbo_max = htonl(rxrpc_rx_jumbo_max); pkt.whdr.flags |= RXRPC_SLOW_START_OK; - len += sizeof(pkt.ack) + sizeof(pkt.info); + padding = 0; + iov[0].iov_len += sizeof(pkt.ack); + len += sizeof(pkt.ack) + 3 + sizeof(ack_info); + ioc = 3; break; + + default: + return; } /* Resync with __rxrpc_disconnect_call() and check that the last call @@ -110,9 +121,6 @@ static void rxrpc_conn_retransmit_call(struct rxrpc_connection *conn, if (READ_ONCE(chan->last_call) != call_id) return; - iov.iov_base = &pkt; - iov.iov_len = len; - serial = atomic_inc_return(&conn->serial); pkt.whdr.serial = htonl(serial); @@ -127,7 +135,7 @@ static void rxrpc_conn_retransmit_call(struct rxrpc_connection *conn, break; } - kernel_sendmsg(conn->params.local->socket, &msg, &iov, 1, len); + kernel_sendmsg(conn->params.local->socket, &msg, iov, ioc, len); _leave(""); return; } -- GitLab From 282ef4729195c8503f7101d574acfb5e7c8a8209 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Tue, 28 Nov 2017 11:28:52 -0600 Subject: [PATCH 0287/2547] rxrpc: Fix variable overwrite Values assigned to both variable resend_at and ack_at are overwritten before they can be used. The correct fix here is to add 'now' to the previously computed value in resend_at and ack_at. Addresses-Coverity-ID: 1462262 Addresses-Coverity-ID: 1462263 Addresses-Coverity-ID: 1462264 Fixes: beb8e5e4f38c ("rxrpc: Express protocol timeouts in terms of RTT") Link: https://marc.info/?i=17004.1511808959%40warthog.procyon.org.uk Signed-off-by: Gustavo A. R. Silva Signed-off-by: David Howells --- net/rxrpc/call_event.c | 2 +- net/rxrpc/sendmsg.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/net/rxrpc/call_event.c b/net/rxrpc/call_event.c index 555274ddc514..ad2ab1103189 100644 --- a/net/rxrpc/call_event.c +++ b/net/rxrpc/call_event.c @@ -123,7 +123,7 @@ static void __rxrpc_propose_ACK(struct rxrpc_call *call, u8 ack_reason, else ack_at = expiry; - ack_at = jiffies + expiry; + ack_at += now; if (time_before(ack_at, call->ack_at)) { WRITE_ONCE(call->ack_at, ack_at); rxrpc_reduce_call_timer(call, ack_at, now, diff --git a/net/rxrpc/sendmsg.c b/net/rxrpc/sendmsg.c index a1c53ac066a1..09f2a3e05221 100644 --- a/net/rxrpc/sendmsg.c +++ b/net/rxrpc/sendmsg.c @@ -233,7 +233,7 @@ static void rxrpc_queue_packet(struct rxrpc_sock *rx, struct rxrpc_call *call, if (resend_at < 1) resend_at = 1; - resend_at = now + rxrpc_resend_timeout; + resend_at += now; WRITE_ONCE(call->resend_at, resend_at); rxrpc_reduce_call_timer(call, resend_at, now, rxrpc_timer_set_for_send); -- GitLab From ec6449a9c2296b1c04f6219f7473e0c2fedecfed Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Mon, 20 Nov 2017 12:10:15 +0100 Subject: [PATCH 0288/2547] KVM: arm/arm64: Don't enable/disable physical timer access on VHE After the timer optimization rework we accidentally end up calling physical timer enable/disable functions on VHE systems, which is neither needed nor correct, since the CNTHCTL_EL2 register format is different when HCR_EL2.E2H is set. The CNTHCTL_EL2 is initialized when CPUs become online in kvm_timer_init_vhe() and we don't have to call these functions on VHE systems, which also allows us to inline the non-VHE functionality. Reported-by: Jintack Lim Signed-off-by: Christoffer Dall --- include/kvm/arm_arch_timer.h | 3 --- virt/kvm/arm/arch_timer.c | 6 ----- virt/kvm/arm/hyp/timer-sr.c | 48 +++++++++++++++--------------------- 3 files changed, 20 insertions(+), 37 deletions(-) diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index 01ee473517e2..6e45608b2399 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -93,7 +93,4 @@ void kvm_timer_init_vhe(void); #define vcpu_vtimer(v) (&(v)->arch.timer_cpu.vtimer) #define vcpu_ptimer(v) (&(v)->arch.timer_cpu.ptimer) -void enable_el1_phys_timer_access(void); -void disable_el1_phys_timer_access(void); - #endif diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index 4151250ce8da..190c99ed1b73 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -479,9 +479,6 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu) vtimer_restore_state(vcpu); - if (has_vhe()) - disable_el1_phys_timer_access(); - /* Set the background timer for the physical timer emulation. */ phys_timer_emulate(vcpu); } @@ -510,9 +507,6 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu) if (unlikely(!timer->enabled)) return; - if (has_vhe()) - enable_el1_phys_timer_access(); - vtimer_save_state(vcpu); /* diff --git a/virt/kvm/arm/hyp/timer-sr.c b/virt/kvm/arm/hyp/timer-sr.c index f39861639f08..f24404b3c8df 100644 --- a/virt/kvm/arm/hyp/timer-sr.c +++ b/virt/kvm/arm/hyp/timer-sr.c @@ -27,42 +27,34 @@ void __hyp_text __kvm_timer_set_cntvoff(u32 cntvoff_low, u32 cntvoff_high) write_sysreg(cntvoff, cntvoff_el2); } -void __hyp_text enable_el1_phys_timer_access(void) -{ - u64 val; - - /* Allow physical timer/counter access for the host */ - val = read_sysreg(cnthctl_el2); - val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN; - write_sysreg(val, cnthctl_el2); -} - -void __hyp_text disable_el1_phys_timer_access(void) -{ - u64 val; - - /* - * Disallow physical timer access for the guest - * Physical counter access is allowed - */ - val = read_sysreg(cnthctl_el2); - val &= ~CNTHCTL_EL1PCEN; - val |= CNTHCTL_EL1PCTEN; - write_sysreg(val, cnthctl_el2); -} - void __hyp_text __timer_disable_traps(struct kvm_vcpu *vcpu) { /* * We don't need to do this for VHE since the host kernel runs in EL2 * with HCR_EL2.TGE ==1, which makes those bits have no impact. */ - if (!has_vhe()) - enable_el1_phys_timer_access(); + if (!has_vhe()) { + u64 val; + + /* Allow physical timer/counter access for the host */ + val = read_sysreg(cnthctl_el2); + val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN; + write_sysreg(val, cnthctl_el2); + } } void __hyp_text __timer_enable_traps(struct kvm_vcpu *vcpu) { - if (!has_vhe()) - disable_el1_phys_timer_access(); + if (!has_vhe()) { + u64 val; + + /* + * Disallow physical timer access for the guest + * Physical counter access is allowed + */ + val = read_sysreg(cnthctl_el2); + val &= ~CNTHCTL_EL1PCEN; + val |= CNTHCTL_EL1PCTEN; + write_sysreg(val, cnthctl_el2); + } } -- GitLab From 285a90e36b138b707c4a9850f2500774b7191c99 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 17 Nov 2017 17:58:21 +0000 Subject: [PATCH 0289/2547] KVM: arm/arm64: VGIC: extend !vgic_is_initialized guard Commit f39d16cbabf9 ("KVM: arm/arm64: Guard kvm_vgic_map_is_active against !vgic_initialized") introduced a check whether the VGIC has been initialized before accessing the spinlock and the VGIC data structure. However the vgic_get_irq() call in the variable declaration sneaked through the net, so lets make sure that this also gets called only after we actually allocated the arrays this function accesses. Reviewed-by: Eric Auger Signed-off-by: Andre Przywara Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic/vgic.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c index b168a328a9e0..786cce7bd2ec 100644 --- a/virt/kvm/arm/vgic/vgic.c +++ b/virt/kvm/arm/vgic/vgic.c @@ -823,13 +823,14 @@ void vgic_kick_vcpus(struct kvm *kvm) bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid) { - struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, vintid); + struct vgic_irq *irq; bool map_is_active; unsigned long flags; if (!vgic_initialized(vcpu->kvm)) return false; + irq = vgic_get_irq(vcpu->kvm, vcpu, vintid); spin_lock_irqsave(&irq->irq_lock, flags); map_is_active = irq->hw && irq->active; spin_unlock_irqrestore(&irq->irq_lock, flags); -- GitLab From 150009e2c70cc3c6e97f00e7595055765d32fb85 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 16 Nov 2017 17:58:15 +0000 Subject: [PATCH 0290/2547] KVM: arm/arm64: vgic-irqfd: Fix MSI entry allocation Using the size of the structure we're allocating is a good idea and avoids any surprise... In this case, we're happilly confusing kvm_kernel_irq_routing_entry and kvm_irq_routing_entry... Fixes: 95b110ab9a09 ("KVM: arm/arm64: Enable irqchip routing") Cc: stable@vger.kernel.org # 4.8 Reported-by: AKASHI Takahiro Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic/vgic-irqfd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/virt/kvm/arm/vgic/vgic-irqfd.c b/virt/kvm/arm/vgic/vgic-irqfd.c index b7baf581611a..99e026d2dade 100644 --- a/virt/kvm/arm/vgic/vgic-irqfd.c +++ b/virt/kvm/arm/vgic/vgic-irqfd.c @@ -112,8 +112,7 @@ int kvm_vgic_setup_default_irq_routing(struct kvm *kvm) u32 nr = dist->nr_spis; int i, ret; - entries = kcalloc(nr, sizeof(struct kvm_kernel_irq_routing_entry), - GFP_KERNEL); + entries = kcalloc(nr, sizeof(*entries), GFP_KERNEL); if (!entries) return -ENOMEM; -- GitLab From ddb4b0102cb9cdd2398d98b3e1e024e08a2f4239 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 16 Nov 2017 17:58:16 +0000 Subject: [PATCH 0291/2547] KVM: arm/arm64: vgic: Preserve the revious read from the pending table The current pending table parsing code assumes that we keep the previous read of the pending bits, but keep that variable in the current block, making sure it is discarded on each loop. We end-up using whatever is on the stack. Who knows, it might just be the right thing... Fixes: 280771252c1ba ("KVM: arm64: vgic-v3: KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES") Cc: stable@vger.kernel.org # 4.12 Reported-by: AKASHI Takahiro Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic/vgic-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c index 2f05f732d3fd..f47e8481fa45 100644 --- a/virt/kvm/arm/vgic/vgic-v3.c +++ b/virt/kvm/arm/vgic/vgic-v3.c @@ -327,13 +327,13 @@ int vgic_v3_save_pending_tables(struct kvm *kvm) int last_byte_offset = -1; struct vgic_irq *irq; int ret; + u8 val; list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) { int byte_offset, bit_nr; struct kvm_vcpu *vcpu; gpa_t pendbase, ptr; bool stored; - u8 val; vcpu = irq->target_vcpu; if (!vcpu) -- GitLab From 64afe6e9eb4841f35317da4393de21a047a883b3 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 16 Nov 2017 17:58:17 +0000 Subject: [PATCH 0292/2547] KVM: arm/arm64: vgic-its: Preserve the revious read from the pending table The current pending table parsing code assumes that we keep the previous read of the pending bits, but keep that variable in the current block, making sure it is discarded on each loop. We end-up using whatever is on the stack. Who knows, it might just be the right thing... Fixes: 33d3bc9556a7d ("KVM: arm64: vgic-its: Read initial LPI pending table") Cc: stable@vger.kernel.org # 4.8 Reported-by: AKASHI Takahiro Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic/vgic-its.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c index 1f761a9991e7..cb2d0a2dbe5a 100644 --- a/virt/kvm/arm/vgic/vgic-its.c +++ b/virt/kvm/arm/vgic/vgic-its.c @@ -421,6 +421,7 @@ static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu) u32 *intids; int nr_irqs, i; unsigned long flags; + u8 pendmask; nr_irqs = vgic_copy_lpi_list(vcpu, &intids); if (nr_irqs < 0) @@ -428,7 +429,6 @@ static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu) for (i = 0; i < nr_irqs; i++) { int byte_offset, bit_nr; - u8 pendmask; byte_offset = intids[i] / BITS_PER_BYTE; bit_nr = intids[i] % BITS_PER_BYTE; -- GitLab From 686f294f2f1ae40705283dd413ca1e4c14f20f93 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 16 Nov 2017 17:58:18 +0000 Subject: [PATCH 0293/2547] KVM: arm/arm64: vgic-its: Check result of allocation before use We miss a test against NULL after allocation. Fixes: 6d03a68f8054 ("KVM: arm64: vgic-its: Turn device_id validation into generic ID validation") Cc: stable@vger.kernel.org # 4.8 Reported-by: AKASHI Takahiro Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic/vgic-its.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c index cb2d0a2dbe5a..8e633bd9cc1e 100644 --- a/virt/kvm/arm/vgic/vgic-its.c +++ b/virt/kvm/arm/vgic/vgic-its.c @@ -821,6 +821,8 @@ static int vgic_its_alloc_collection(struct vgic_its *its, return E_ITS_MAPC_COLLECTION_OOR; collection = kzalloc(sizeof(*collection), GFP_KERNEL); + if (!collection) + return -ENOMEM; collection->collection_id = coll_id; collection->target_addr = COLLECTION_NOT_MAPPED; -- GitLab From a05d1c0d03fd60ed487991e73850421e735c0135 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 16 Nov 2017 17:58:19 +0000 Subject: [PATCH 0294/2547] KVM: arm/arm64: vgic-v4: Only perform an unmap for valid vLPIs Before performing an unmap, let's check that what we have was really mapped the first place. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic/vgic-v4.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/virt/kvm/arm/vgic/vgic-v4.c b/virt/kvm/arm/vgic/vgic-v4.c index 53c324aa44ef..4a37292855bc 100644 --- a/virt/kvm/arm/vgic/vgic-v4.c +++ b/virt/kvm/arm/vgic/vgic-v4.c @@ -337,8 +337,10 @@ int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int virq, goto out; WARN_ON(!(irq->hw && irq->host_irq == virq)); - irq->hw = false; - ret = its_unmap_vlpi(virq); + if (irq->hw) { + irq->hw = false; + ret = its_unmap_vlpi(virq); + } out: mutex_unlock(&its->its_lock); -- GitLab From 26aa7b3b1c0fb3f1a6176a0c1847204ef4355693 Mon Sep 17 00:00:00 2001 From: Kristina Martsenko Date: Thu, 16 Nov 2017 17:58:20 +0000 Subject: [PATCH 0295/2547] arm64: KVM: fix VTTBR_BADDR_MASK BUG_ON off-by-one VTTBR_BADDR_MASK is used to sanity check the size and alignment of the VTTBR address. It seems to currently be off by one, thereby only allowing up to 47-bit addresses (instead of 48-bit) and also insufficiently checking the alignment. This patch fixes it. As an example, with 4k pages, before this patch we have: PHYS_MASK_SHIFT = 48 VTTBR_X = 37 - 24 = 13 VTTBR_BADDR_SHIFT = 13 - 1 = 12 VTTBR_BADDR_MASK = ((1 << 35) - 1) << 12 = 0x00007ffffffff000 Which is wrong, because the mask doesn't allow bit 47 of the VTTBR address to be set, and only requires the address to be 12-bit (4k) aligned, while it actually needs to be 13-bit (8k) aligned because we concatenate two 4k tables. With this patch, the mask becomes 0x0000ffffffffe000, which is what we want. Fixes: 0369f6a34b9f ("arm64: KVM: EL2 register definitions") Cc: # 3.11.x Reviewed-by: Suzuki K Poulose Reviewed-by: Christoffer Dall Signed-off-by: Kristina Martsenko Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm64/include/asm/kvm_arm.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 7f069ff37f06..715d395ef45b 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -170,8 +170,7 @@ #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS) #define VTTBR_X (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA) -#define VTTBR_BADDR_SHIFT (VTTBR_X - 1) -#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT) +#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X) #define VTTBR_VMID_SHIFT (UL(48)) #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) -- GitLab From 5553b142be11e794ebc0805950b2e8313f93d718 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 16 Nov 2017 17:58:21 +0000 Subject: [PATCH 0296/2547] arm: KVM: Fix VTTBR_BADDR_MASK BUG_ON off-by-one VTTBR_BADDR_MASK is used to sanity check the size and alignment of the VTTBR address. It seems to currently be off by one, thereby only allowing up to 39-bit addresses (instead of 40-bit) and also insufficiently checking the alignment. This patch fixes it. This patch is the 32bit pendent of Kristina's arm64 fix, and she deserves the actual kudos for pinpointing that one. Fixes: f7ed45be3ba52 ("KVM: ARM: World-switch implementation") Cc: # 3.9 Reported-by: Kristina Martsenko Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm/include/asm/kvm_arm.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h index c8781450905b..3ab8b3781bfe 100644 --- a/arch/arm/include/asm/kvm_arm.h +++ b/arch/arm/include/asm/kvm_arm.h @@ -161,8 +161,7 @@ #else #define VTTBR_X (5 - KVM_T0SZ) #endif -#define VTTBR_BADDR_SHIFT (VTTBR_X - 1) -#define VTTBR_BADDR_MASK (((_AC(1, ULL) << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT) +#define VTTBR_BADDR_MASK (((_AC(1, ULL) << (40 - VTTBR_X)) - 1) << VTTBR_X) #define VTTBR_VMID_SHIFT _AC(48, ULL) #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) -- GitLab From 696673d192f52c2c5a702224ee21f005318a844b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 16 Nov 2017 15:39:19 +0000 Subject: [PATCH 0297/2547] KVM: arm/arm64: debug: Introduce helper for single-step MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After emulating instructions we may want return to user-space to handle single-step debugging. Introduce a helper function, which, if single-step is enabled, sets the run structure for return and returns true. Signed-off-by: Alex Bennée Reviewed-by: Julien Thierry Signed-off-by: Christoffer Dall --- arch/arm/include/asm/kvm_host.h | 5 +++++ arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/debug.c | 21 +++++++++++++++++++++ 3 files changed, 27 insertions(+) diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index 242151ea6908..a9f7d3f47134 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -285,6 +285,11 @@ static inline void kvm_arm_init_debug(void) {} static inline void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) {} static inline void kvm_arm_clear_debug(struct kvm_vcpu *vcpu) {} static inline void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu) {} +static inline bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu, + struct kvm_run *run) +{ + return false; +} int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 674912d7a571..ea6cb5b24258 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -370,6 +370,7 @@ void kvm_arm_init_debug(void); void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); +bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index dbadfaf850a7..fa63b28c65e0 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -221,3 +221,24 @@ void kvm_arm_clear_debug(struct kvm_vcpu *vcpu) } } } + + +/* + * After successfully emulating an instruction, we might want to + * return to user space with a KVM_EXIT_DEBUG. We can only do this + * once the emulation is complete, though, so for userspace emulations + * we have to wait until we have re-entered KVM before calling this + * helper. + * + * Return true (and set exit_reason) to return to userspace or false + * if no further action is required. + */ +bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { + run->exit_reason = KVM_EXIT_DEBUG; + run->debug.arch.hsr = ESR_ELx_EC_SOFTSTP_LOW << ESR_ELx_EC_SHIFT; + return true; + } + return false; +} -- GitLab From 7226bc2e126dfb6d81e85a75f373ea4cc3619406 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 16 Nov 2017 15:39:20 +0000 Subject: [PATCH 0298/2547] kvm: arm64: handle single-stepping trapped instructions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If we are using guest debug to single-step the guest, we need to ensure that we exit after emulating the instruction. This only affects instructions completely emulated by the kernel. For instructions emulated in userspace, we need to exit and return to complete the emulation. The kvm_arm_handle_step_debug() helper sets up the necessary exit state if needed. Signed-off-by: Alex Bennée Reviewed-by: Julien Thierry Signed-off-by: Christoffer Dall --- arch/arm64/kvm/handle_exit.c | 49 +++++++++++++++++++++++++----------- 1 file changed, 35 insertions(+), 14 deletions(-) diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index b71247995469..029c28dd25e9 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -186,6 +186,40 @@ static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu) return arm_exit_handlers[hsr_ec]; } +/* + * We may be single-stepping an emulated instruction. If the emulation + * has been completed in the kernel, we can return to userspace with a + * KVM_EXIT_DEBUG, otherwise userspace needs to complete its + * emulation first. + */ +static int handle_trap_exceptions(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + int handled; + + /* + * See ARM ARM B1.14.1: "Hyp traps on instructions + * that fail their condition code check" + */ + if (!kvm_condition_valid(vcpu)) { + kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); + handled = 1; + } else { + exit_handle_fn exit_handler; + + exit_handler = kvm_get_exit_handler(vcpu); + handled = exit_handler(vcpu, run); + } + + /* + * kvm_arm_handle_step_debug() sets the exit_reason on the kvm_run + * structure if we need to return to userspace. + */ + if (handled > 0 && kvm_arm_handle_step_debug(vcpu, run)) + handled = 0; + + return handled; +} + /* * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on * proper exit to userspace. @@ -193,8 +227,6 @@ static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu) int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, int exception_index) { - exit_handle_fn exit_handler; - if (ARM_SERROR_PENDING(exception_index)) { u8 hsr_ec = ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu)); @@ -222,18 +254,7 @@ int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, kvm_inject_vabt(vcpu); return 1; case ARM_EXCEPTION_TRAP: - /* - * See ARM ARM B1.14.1: "Hyp traps on instructions - * that fail their condition code check" - */ - if (!kvm_condition_valid(vcpu)) { - kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); - return 1; - } - - exit_handler = kvm_get_exit_handler(vcpu); - - return exit_handler(vcpu, run); + return handle_trap_exceptions(vcpu, run); case ARM_EXCEPTION_HYP_GONE: /* * EL2 has been reset to the hyp-stub. This happens when a guest -- GitLab From 1eb591288b956bdd75e464e69b6b8207ffa6e5e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 16 Nov 2017 15:39:21 +0000 Subject: [PATCH 0299/2547] kvm: arm64: handle single-step of userspace mmio instructions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The system state of KVM when using userspace emulation is not complete until we return into KVM_RUN. To handle mmio related updates we wait until they have been committed and then schedule our KVM_EXIT_DEBUG. The kvm_arm_handle_step_debug() helper tells us if we need to return and sets up the exit_reason for us. Signed-off-by: Alex Bennée Signed-off-by: Christoffer Dall --- virt/kvm/arm/arm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index a6524ff27de4..322c570d211e 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -628,6 +628,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) ret = kvm_handle_mmio_return(vcpu, vcpu->run); if (ret) return ret; + if (kvm_arm_handle_step_debug(vcpu, vcpu->run)) + return 0; + } if (run->immediate_exit) -- GitLab From 15d8374874ded0bec37ef27f8301a6d54032c0e5 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 14 Nov 2017 14:43:27 +0000 Subject: [PATCH 0300/2547] mfd: cros ec: spi: Don't send first message too soon On the Tegra124 Nyan-Big chromebook the very first SPI message sent to the EC is failing. The Tegra SPI driver configures the SPI chip-selects to be active-high by default (and always has for many years). The EC SPI requires an active-low chip-select and so the Tegra chip-select is reconfigured to be active-low when the EC SPI driver calls spi_setup(). The problem is that if the first SPI message to the EC is sent too soon after reconfiguring the SPI chip-select, it fails. The EC SPI driver prevents back-to-back SPI messages being sent too soon by keeping track of the time the last transfer was sent via the variable 'last_transfer_ns'. To prevent the very first transfer being sent too soon, initialise the 'last_transfer_ns' variable after calling spi_setup() and before sending the first SPI message. Cc: Signed-off-by: Jon Hunter Reviewed-by: Brian Norris Reviewed-by: Douglas Anderson Acked-by: Benson Leung Signed-off-by: Lee Jones --- drivers/mfd/cros_ec_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/cros_ec_spi.c b/drivers/mfd/cros_ec_spi.c index c9714072e224..a14196e95e9b 100644 --- a/drivers/mfd/cros_ec_spi.c +++ b/drivers/mfd/cros_ec_spi.c @@ -667,6 +667,7 @@ static int cros_ec_spi_probe(struct spi_device *spi) sizeof(struct ec_response_get_protocol_info); ec_dev->dout_size = sizeof(struct ec_host_request); + ec_spi->last_transfer_ns = ktime_get_ns(); err = cros_ec_register(ec_dev); if (err) { -- GitLab From 0a423772de2f3d7b00899987884f62f63ae00dcb Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Sat, 11 Nov 2017 16:38:43 +0100 Subject: [PATCH 0301/2547] mfd: twl4030-audio: Fix sibling-node lookup A helper purported to look up a child node based on its name was using the wrong of-helper and ended up prematurely freeing the parent of-node while leaking any matching node. To make things worse, any matching node would not even necessarily be a child node as the whole device tree was searched depth-first starting at the parent. Fixes: 019a7e6b7b31 ("mfd: twl4030-audio: Add DT support") Cc: stable # 3.7 Signed-off-by: Johan Hovold Acked-by: Peter Ujfalusi Signed-off-by: Lee Jones --- drivers/mfd/twl4030-audio.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c index da16bf45fab4..dc94ffc6321a 100644 --- a/drivers/mfd/twl4030-audio.c +++ b/drivers/mfd/twl4030-audio.c @@ -159,13 +159,18 @@ unsigned int twl4030_audio_get_mclk(void) EXPORT_SYMBOL_GPL(twl4030_audio_get_mclk); static bool twl4030_audio_has_codec(struct twl4030_audio_data *pdata, - struct device_node *node) + struct device_node *parent) { + struct device_node *node; + if (pdata && pdata->codec) return true; - if (of_find_node_by_name(node, "codec")) + node = of_get_child_by_name(parent, "codec"); + if (node) { + of_node_put(node); return true; + } return false; } -- GitLab From 85e9b13cbb130a3209f21bd7933933399c389ffe Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Sat, 11 Nov 2017 16:38:44 +0100 Subject: [PATCH 0302/2547] mfd: twl6040: Fix child-node lookup Fix child-node lookup during probe, which ended up searching the whole device tree depth-first starting at the parent rather than just matching on its children. To make things worse, the parent node was prematurely freed, while the child node was leaked. Note that the CONFIG_OF compile guard can be removed as of_get_child_by_name() provides a !CONFIG_OF implementation which always fails. Cc: stable # 3.5 Fixes: 37e13cecaa14 ("mfd: Add support for Device Tree to twl6040") Fixes: ca2cad6ae38e ("mfd: Fix twl6040 build failure") Signed-off-by: Johan Hovold Acked-by: Peter Ujfalusi Signed-off-by: Lee Jones --- drivers/mfd/twl6040.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/twl6040.c b/drivers/mfd/twl6040.c index d66502d36ba0..dd19f17a1b63 100644 --- a/drivers/mfd/twl6040.c +++ b/drivers/mfd/twl6040.c @@ -97,12 +97,16 @@ static struct reg_sequence twl6040_patch[] = { }; -static bool twl6040_has_vibra(struct device_node *node) +static bool twl6040_has_vibra(struct device_node *parent) { -#ifdef CONFIG_OF - if (of_find_node_by_name(node, "vibra")) + struct device_node *node; + + node = of_get_child_by_name(parent, "vibra"); + if (node) { + of_node_put(node); return true; -#endif + } + return false; } -- GitLab From 001dde9400d5c3e9e2ce2abe06c1efa70a25dfde Mon Sep 17 00:00:00 2001 From: Shawn Nematbakhsh Date: Wed, 27 Sep 2017 14:35:27 -0700 Subject: [PATCH 0303/2547] mfd: cros ec: spi: Fix "in progress" error signaling For host commands that take a long time to process, cros ec can return early by signaling a EC_RES_IN_PROGRESS result. The host must then poll status with EC_CMD_GET_COMMS_STATUS until completion of the command. None of the above applies when data link errors are encountered. When errors such as EC_SPI_PAST_END are encountered during command transmission, it usually means the command was not received by the EC. Treating such errors as if they were 'EC_RES_IN_PROGRESS' results is almost always the wrong decision, and can result in host commands silently being lost. Reported-by: Jon Hunter Signed-off-by: Shawn Nematbakhsh Reviewed-by: Brian Norris Tested-by: Jon Hunter Signed-off-by: Lee Jones --- drivers/mfd/cros_ec_spi.c | 52 ++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/drivers/mfd/cros_ec_spi.c b/drivers/mfd/cros_ec_spi.c index a14196e95e9b..59c82cdcf48d 100644 --- a/drivers/mfd/cros_ec_spi.c +++ b/drivers/mfd/cros_ec_spi.c @@ -377,6 +377,7 @@ static int cros_ec_pkt_xfer_spi(struct cros_ec_device *ec_dev, u8 *ptr; u8 *rx_buf; u8 sum; + u8 rx_byte; int ret = 0, final_ret; len = cros_ec_prepare_tx(ec_dev, ec_msg); @@ -421,25 +422,22 @@ static int cros_ec_pkt_xfer_spi(struct cros_ec_device *ec_dev, if (!ret) { /* Verify that EC can process command */ for (i = 0; i < len; i++) { - switch (rx_buf[i]) { - case EC_SPI_PAST_END: - case EC_SPI_RX_BAD_DATA: - case EC_SPI_NOT_READY: - ret = -EAGAIN; - ec_msg->result = EC_RES_IN_PROGRESS; - default: + rx_byte = rx_buf[i]; + if (rx_byte == EC_SPI_PAST_END || + rx_byte == EC_SPI_RX_BAD_DATA || + rx_byte == EC_SPI_NOT_READY) { + ret = -EREMOTEIO; break; } - if (ret) - break; } - if (!ret) - ret = cros_ec_spi_receive_packet(ec_dev, - ec_msg->insize + sizeof(*response)); - } else { - dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret); } + if (!ret) + ret = cros_ec_spi_receive_packet(ec_dev, + ec_msg->insize + sizeof(*response)); + else + dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret); + final_ret = terminate_request(ec_dev); spi_bus_unlock(ec_spi->spi->master); @@ -508,6 +506,7 @@ static int cros_ec_cmd_xfer_spi(struct cros_ec_device *ec_dev, int i, len; u8 *ptr; u8 *rx_buf; + u8 rx_byte; int sum; int ret = 0, final_ret; @@ -544,25 +543,22 @@ static int cros_ec_cmd_xfer_spi(struct cros_ec_device *ec_dev, if (!ret) { /* Verify that EC can process command */ for (i = 0; i < len; i++) { - switch (rx_buf[i]) { - case EC_SPI_PAST_END: - case EC_SPI_RX_BAD_DATA: - case EC_SPI_NOT_READY: - ret = -EAGAIN; - ec_msg->result = EC_RES_IN_PROGRESS; - default: + rx_byte = rx_buf[i]; + if (rx_byte == EC_SPI_PAST_END || + rx_byte == EC_SPI_RX_BAD_DATA || + rx_byte == EC_SPI_NOT_READY) { + ret = -EREMOTEIO; break; } - if (ret) - break; } - if (!ret) - ret = cros_ec_spi_receive_response(ec_dev, - ec_msg->insize + EC_MSG_TX_PROTO_BYTES); - } else { - dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret); } + if (!ret) + ret = cros_ec_spi_receive_response(ec_dev, + ec_msg->insize + EC_MSG_TX_PROTO_BYTES); + else + dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret); + final_ret = terminate_request(ec_dev); spi_bus_unlock(ec_spi->spi->master); -- GitLab From e70dce73befcf96607bc6e24c2c8f84229d6721e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 23 Nov 2017 12:11:33 +0000 Subject: [PATCH 0304/2547] kvm: arm64: handle single-step during SError exceptions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When an SError arrives during single-step both the SError and debug exceptions may be pending when the step is completed, and the architecture doesn't define the ordering of the two. This means that we can observe en SError even though we've just completed a step, without receiving a debug exception. In that case the DBG_SPSR_SS bit will have flipped as the instruction executed. After handling the abort in handle_exit() we test to see if the bit is clear and we were single-stepping before deciding if we need to exit to user space. Acked-by: Marc Zyngier Reviewed-by: Christoffer Dall Signed-off-by: Alex Bennée Signed-off-by: Christoffer Dall --- arch/arm64/kvm/handle_exit.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 029c28dd25e9..304203fa9e33 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -28,6 +28,7 @@ #include #include #include +#include #define CREATE_TRACE_POINTS #include "trace.h" @@ -252,7 +253,12 @@ int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, return 1; case ARM_EXCEPTION_EL1_SERROR: kvm_inject_vabt(vcpu); - return 1; + /* We may still need to return for single-step */ + if (!(*vcpu_cpsr(vcpu) & DBG_SPSR_SS) + && kvm_arm_handle_step_debug(vcpu, run)) + return 0; + else + return 1; case ARM_EXCEPTION_TRAP: return handle_trap_exceptions(vcpu, run); case ARM_EXCEPTION_HYP_GONE: -- GitLab From e3feebf81744acd8b581e5eb58a93e8fdcf042a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 23 Nov 2017 12:11:34 +0000 Subject: [PATCH 0305/2547] kvm: arm64: handle single-step of hyp emulated mmio instructions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is a fast-path of MMIO emulation inside hyp mode. The handling of single-step is broadly the same as kvm_arm_handle_step_debug() except we just setup ESR/HSR so handle_exit() does the correct thing as we exit. For the case of an emulated illegal access causing an SError we will exit via the ARM_EXCEPTION_EL1_SERROR path in handle_exit(). We behave as we would during a real SError and clear the DBG_SPSR_SS bit for the emulated instruction. Acked-by: Marc Zyngier Reviewed-by: Christoffer Dall Signed-off-by: Alex Bennée Signed-off-by: Christoffer Dall --- arch/arm64/kvm/hyp/switch.c | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 525c01f48867..f7c651f3a8c0 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -22,6 +22,7 @@ #include #include #include +#include static bool __hyp_text __fpsimd_enabled_nvhe(void) { @@ -269,7 +270,11 @@ static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu) return true; } -static void __hyp_text __skip_instr(struct kvm_vcpu *vcpu) +/* Skip an instruction which has been emulated. Returns true if + * execution can continue or false if we need to exit hyp mode because + * single-step was in effect. + */ +static bool __hyp_text __skip_instr(struct kvm_vcpu *vcpu) { *vcpu_pc(vcpu) = read_sysreg_el2(elr); @@ -282,6 +287,14 @@ static void __hyp_text __skip_instr(struct kvm_vcpu *vcpu) } write_sysreg_el2(*vcpu_pc(vcpu), elr); + + if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { + vcpu->arch.fault.esr_el2 = + (ESR_ELx_EC_SOFTSTP_LOW << ESR_ELx_EC_SHIFT) | 0x22; + return false; + } else { + return true; + } } int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu) @@ -342,13 +355,21 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu) int ret = __vgic_v2_perform_cpuif_access(vcpu); if (ret == 1) { - __skip_instr(vcpu); - goto again; + if (__skip_instr(vcpu)) + goto again; + else + exit_code = ARM_EXCEPTION_TRAP; } if (ret == -1) { - /* Promote an illegal access to an SError */ - __skip_instr(vcpu); + /* Promote an illegal access to an + * SError. If we would be returning + * due to single-step clear the SS + * bit so handle_exit knows what to + * do after dealing with the error. + */ + if (!__skip_instr(vcpu)) + *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS; exit_code = ARM_EXCEPTION_EL1_SERROR; } @@ -363,8 +384,10 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu) int ret = __vgic_v3_perform_cpuif_access(vcpu); if (ret == 1) { - __skip_instr(vcpu); - goto again; + if (__skip_instr(vcpu)) + goto again; + else + exit_code = ARM_EXCEPTION_TRAP; } /* 0 falls through to be handled out of EL2 */ -- GitLab From 22601127c0faa5db70ab88f23af11cb23c8f6cdf Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Wed, 29 Nov 2017 17:05:16 +0100 Subject: [PATCH 0306/2547] KVM: arm/arm64: Avoid attempting to load timer vgic state without a vgic The timer optimization patches inadvertendly changed the logic to always load the timer state as if we have a vgic, even if we don't have a vgic. Fix this by doing the usual irqchip_in_kernel() check and call the appropriate load function. Signed-off-by: Christoffer Dall --- virt/kvm/arm/arch_timer.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index 190c99ed1b73..f9555b1e7f15 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -835,7 +835,10 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) no_vgic: preempt_disable(); timer->enabled = 1; - kvm_timer_vcpu_load_vgic(vcpu); + if (!irqchip_in_kernel(vcpu->kvm)) + kvm_timer_vcpu_load_user(vcpu); + else + kvm_timer_vcpu_load_vgic(vcpu); preempt_enable(); return 0; -- GitLab From 58d0d19a204604ca0da26058828a53558b265da3 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 28 Nov 2017 15:18:19 +0000 Subject: [PATCH 0307/2547] kvm: arm: don't treat unavailable HYP mode as an error Since it is perfectly legal to run the kernel at EL1, it is not actually an error if HYP mode is not available when attempting to initialize KVM, given that KVM support cannot be built as a module. So demote the kvm_err() to kvm_info(), which prevents the error from appearing on an otherwise 'quiet' console. Acked-by: Marc Zyngier Acked-by: Christoffer Dall Signed-off-by: Ard Biesheuvel Signed-off-by: Christoffer Dall --- virt/kvm/arm/arm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index 322c570d211e..ca65d06b38a8 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -1507,7 +1507,7 @@ int kvm_arch_init(void *opaque) bool in_hyp_mode; if (!is_hyp_mode_available()) { - kvm_err("HYP mode not available\n"); + kvm_info("HYP mode not available\n"); return -ENODEV; } -- GitLab From 580b9d05a34ef81ecab6a55e068ab269b148b32e Mon Sep 17 00:00:00 2001 From: Sagar Arun Kamble Date: Wed, 29 Nov 2017 21:49:09 +0530 Subject: [PATCH 0308/2547] drm/i915/guc: Change default GuC FW for SKL to v9.33 This patch makes v9.33 firmware as default firmware for SKL. Note: GuC logging control is changed with this firmware. GuC is expecting i915 to set control bit to enable "default logging" while using GuC action UK_LOG_ENABLE_LOGGING. However i915 is currently not doing this because it is version specific change and can be handled entirely in GuC. It will need to be fixed in future firmwares. This update includes (since v6.1): - HuC RSA Keys updated. - Adding per engine preemption support in GuC scheduler - Minor bug fixes. - Added support to log media reset count for host to read it - Sub-feature level control for power management features. - Minor clean-up for power management interface. - Unified power management interface and scheduler interface into 1 file using same version. - Bug Fix for multi context scheduler flag. - DCC spec changes for BXT + DCT enabling - SB based Pre-ETM/ETM flow enabling for debug signed GuC/HuC - Moving GuC non_critical r/w data to lower SRAM 64KB - Media engine Reset fix. Correctly marking context for resubmission in Media Reset case. - ABT Disable bug fix. Disabled Evaluation mode on context change. - Async FW in Engine Schedule feature (not enabled from KMD) - GuC clean up to align developer build in line to production build. - DCC consistency fix for SKL - Disable ARAT interrupt before programming ARAT delta. - Memory range check in Parse to avoid failure due to overflow. - Enabled WA for MSGCH hang issue - Clear forcewake in CSB when SQ is empty. - Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder. - This is file location change.No functional change done as part of this check in. - Enable decoupled freq for SKL GT4 - 3 tries of wake request needed from GuC2CSME for ME to wake up. Request has come from ME spec - During reset one parameter was not getting accounted - Enabling Guc Log changes for ultra low logging for OCA - Enabling build failure check to catch critical section overflow. - Disable build.bat redundant prints. - Move few least used functions to non-critical section. - Rearrange GuC documentation folder structure. - Synchronize SLPC internal debug interface with other branches. - Fixing Issue with Default Guc Log changes for OCA using special Control Bit v2: Rebase. Updated commit message. Signed-off-by: Jeff McGee Signed-off-by: Sagar Arun Kamble Cc: Spotswood John A Cc: Anusha Srivatsa Cc: Michal Wajdeczko Cc: Rodrigo Vivi Cc: Joonas Lahtinen Reviewed-by: Anusha Srivatsa Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1511972351-574-2-git-send-email-sagar.a.kamble@intel.com --- drivers/gpu/drm/i915/intel_guc_fw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index bbab4e1106f3..631e932c9953 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -30,8 +30,8 @@ #include "intel_guc_fw.h" #include "i915_drv.h" -#define SKL_FW_MAJOR 6 -#define SKL_FW_MINOR 1 +#define SKL_FW_MAJOR 9 +#define SKL_FW_MINOR 33 #define BXT_FW_MAJOR 8 #define BXT_FW_MINOR 7 -- GitLab From d416ac780eecc76511fcf15974f54f5e9520cea6 Mon Sep 17 00:00:00 2001 From: Sagar Arun Kamble Date: Wed, 29 Nov 2017 21:49:10 +0530 Subject: [PATCH 0309/2547] drm/i915/guc: Change default GuC FW for BXT to v9.29 This patch makes v9.29 firmware as default firmware for BXT. Note: GuC logging control is changed with this firmware. GuC is expecting i915 to set control bit to enable "default logging" while using GuC action UK_LOG_ENABLE_LOGGING. However i915 is currently not doing this because it is version specific change and can be handled entirely in GuC. It will need to be fixed in future firmwares. This update includes (since v8.7): - Added support to log media reset count for host to read it - BXT WA for fixing MTP hangs. WaDisableDOPRenderClkGatingAtSubmit - Sub-feature level control for power management features. - Minor clean-up for power management interface. - Unified power management interface and scheduler interface into 1 file using same version. - Bug Fix for multi context scheduler flag. - DCC spec changes for BXT + DCT enabling - Springboard based Pre-ETM/ETM flow enabling for debug signed GuC/HuC - Moving GuC non_critical r/w data to lower SRAM 64KB - Enabled IBC for BXT - Media engine Reset fix. Correctly marking context for resubmission in Media Reset case. - SLPC Dynamic RPe fix to resolve issues where incorrect frequency was set. - ABT Disable bug fix. Disabled Evaluation mode on context change. - GuC clean up to align developer build in line to production build. - Disable ARAT interrupt before programming ARAT delta. - Memory range check in Parse to avoid failure due to overflow. - Clear forcewake in CSB when SQ is empty. - SLPC IBC 1.6 for APL to ensure multiplier does not cap IA below Pe. - Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder. - This is file location change. No functional change done as part of this check in. - 3 tries of wake request needed from GuC2CSME for ME to wake up. Request has come from ME spec - During reset one parameter was not getting accounted - Enabling Guc Log changes for ultra low logging for OCA - Disable build.bat redundant prints. - Move few least used functions to non-critical section. - Rearrange GuC documentation folder structure. - Fixing Issue with Default Guc Log changes for OCA using special Control Bit v2: Rebase. Updated commit message. Signed-off-by: Jeff McGee Signed-off-by: Sagar Arun Kamble Cc: Spotswood John A Cc: Anusha Srivatsa Cc: Michal Wajdeczko Cc: Rodrigo Vivi Cc: Joonas Lahtinen Reviewed-by: Anusha Srivatsa Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1511972351-574-3-git-send-email-sagar.a.kamble@intel.com --- drivers/gpu/drm/i915/intel_guc_fw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index 631e932c9953..df2ff965655a 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -33,8 +33,8 @@ #define SKL_FW_MAJOR 9 #define SKL_FW_MINOR 33 -#define BXT_FW_MAJOR 8 -#define BXT_FW_MINOR 7 +#define BXT_FW_MAJOR 9 +#define BXT_FW_MINOR 29 #define KBL_FW_MAJOR 9 #define KBL_FW_MINOR 14 -- GitLab From cc44085616a94a998dc8f708e37ec9df2df97a87 Mon Sep 17 00:00:00 2001 From: Sagar Arun Kamble Date: Wed, 29 Nov 2017 21:49:11 +0530 Subject: [PATCH 0310/2547] drm/i915/guc: Change default GuC FW for KBL to v9.39 This patch makes v9.39 firmware as default firmware for KBL. Note: GuC logging control is changed with this firmware. GuC is expecting i915 to set control bit to enable "default logging" while using GuC action UK_LOG_ENABLE_LOGGING. However i915 is currently not doing this because it is version specific change and can be handled entirely in GuC. It will need to be fixed in future firmwares. This update includes (since v9.14): - DCC spec changes for BXT + DCT enabling - Bug Fix for power conservation feature SLPC_DCC - Scheduler 1-element submission during DCC cycles. - SB based Pre-ETM/ETM flow enabling for debug signed GuC/HuC - Moving GuC non_critical r/w data to lower SRAM 64KB - Media engine Reset fix. Correctly marking context for resubmission in Media Reset case. - ABT Disable bug fix. Disabled Evaluation mode on context change. - Async FW in Engine Schedule feature (not enabled from KMD) - GuC clean up to align developer build in line to production build. - Disable ARAT interrupt before programming ARAT delta. - Memory range check in Parse to avoid failure due to overflow. - GuC Msg Channel Hang WA - Stall GUC for mmio access when IDI is low during CPD flow. - Fix for submit queue over flow issue - Enabling IBC on KBL GT3 15W, GT4 45W - Disabling wrong device ID WA in production signed kernel - Enabling WA for MSGCH hang issue upto required KBL stepping - Clear forcewake in CSB when SQ is empty. - 3Tries of GuC2CSME wake request - During reset one parameter was not getting accounted - Disable DCC 1-elem mode submission - Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder. - This is file location change.No functional change done as part of this check in. - Enabling Guc Log changes for ultra low logging for OCA - Enabling Dynamic Render Power Well Hysteresis Programming for Compute Worklaods - Enabling build failure check to catch critical section overflow. - Disable build.bat redundant prints. - Move few least used functions to non-critical section. - Rearrange GuC documentation folder structure. - Synchronize SLPC internal debug interface with other branches. - Fixing Issue with Default Guc Log changes for OCA using special Control Bit - Aggressive DCC implementation for supported platforms. v2: Rebase. Updated commit message. Signed-off-by: Jeff McGee Signed-off-by: Sagar Arun Kamble Cc: Spotswood John A Cc: Anusha Srivatsa Cc: Michal Wajdeczko Cc: Rodrigo Vivi Cc: Joonas Lahtinen Reviewed-by: Anusha Srivatsa Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1511972351-574-4-git-send-email-sagar.a.kamble@intel.com --- drivers/gpu/drm/i915/intel_guc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index df2ff965655a..89862fa8ab42 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -37,7 +37,7 @@ #define BXT_FW_MINOR 29 #define KBL_FW_MAJOR 9 -#define KBL_FW_MINOR 14 +#define KBL_FW_MINOR 39 #define GLK_FW_MAJOR 10 #define GLK_FW_MINOR 56 -- GitLab From 9b85c2d4508563f4bb1de0d971ed02fea0d0d757 Mon Sep 17 00:00:00 2001 From: Quentin Monnet Date: Tue, 28 Nov 2017 17:44:28 -0800 Subject: [PATCH 0311/2547] tools: bpftool: fix crash on bad parameters with JSON If bad or unrecognised parameters are specified after JSON output is requested, `usage()` will try to output null JSON object before the writer is created. To prevent this, create the writer as soon as the `--json` option is parsed. Fixes: 004b45c0e51a ("tools: bpftool: provide JSON output for all possible commands") Reported-by: Jakub Kicinski Signed-off-by: Quentin Monnet Acked-by: Jakub Kicinski Signed-off-by: Daniel Borkmann --- tools/bpf/bpftool/main.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/tools/bpf/bpftool/main.c b/tools/bpf/bpftool/main.c index d6e4762170a4..14ad54a1c404 100644 --- a/tools/bpf/bpftool/main.c +++ b/tools/bpf/bpftool/main.c @@ -291,7 +291,15 @@ int main(int argc, char **argv) pretty_output = true; /* fall through */ case 'j': - json_output = true; + if (!json_output) { + json_wtr = jsonw_new(stdout); + if (!json_wtr) { + p_err("failed to create JSON writer"); + return -1; + } + json_output = true; + } + jsonw_pretty(json_wtr, pretty_output); break; case 'f': show_pinned = true; @@ -306,15 +314,6 @@ int main(int argc, char **argv) if (argc < 0) usage(); - if (json_output) { - json_wtr = jsonw_new(stdout); - if (!json_wtr) { - p_err("failed to create JSON writer"); - return -1; - } - jsonw_pretty(json_wtr, pretty_output); - } - bfd_init(); ret = cmd_select(cmds, argc, argv, do_help); -- GitLab From 7868620a3c15dbc661fb5d849de403ac04624c50 Mon Sep 17 00:00:00 2001 From: Quentin Monnet Date: Tue, 28 Nov 2017 17:44:29 -0800 Subject: [PATCH 0312/2547] tools: bpftool: clean up the JSON writer before exiting in usage() The writer is cleaned at the end of the main function, but not if the program exits sooner in usage(). Let's keep it clean and destroy the writer before exiting. Destruction and actual call to exit() are moved to another function so that clean exit can also be performed without printing usage() hints. Fixes: d35efba99d92 ("tools: bpftool: introduce --json and --pretty options") Signed-off-by: Quentin Monnet Acked-by: Jakub Kicinski Signed-off-by: Daniel Borkmann --- tools/bpf/bpftool/main.c | 10 +++++++++- tools/bpf/bpftool/main.h | 3 ++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/tools/bpf/bpftool/main.c b/tools/bpf/bpftool/main.c index 14ad54a1c404..d72dd73a4016 100644 --- a/tools/bpf/bpftool/main.c +++ b/tools/bpf/bpftool/main.c @@ -58,11 +58,19 @@ bool show_pinned; struct pinned_obj_table prog_table; struct pinned_obj_table map_table; +static void __noreturn clean_and_exit(int i) +{ + if (json_output) + jsonw_destroy(&json_wtr); + + exit(i); +} + void usage(void) { last_do_help(last_argc - 1, last_argv + 1); - exit(-1); + clean_and_exit(-1); } static int do_help(int argc, char **argv) diff --git a/tools/bpf/bpftool/main.h b/tools/bpf/bpftool/main.h index 9c191e222d6f..0b60ddfb2b93 100644 --- a/tools/bpf/bpftool/main.h +++ b/tools/bpf/bpftool/main.h @@ -41,6 +41,7 @@ #include #include #include +#include #include #include @@ -80,7 +81,7 @@ void p_info(const char *fmt, ...); bool is_prefix(const char *pfx, const char *str); void fprint_hex(FILE *f, void *arg, unsigned int n, const char *sep); -void usage(void) __attribute__((noreturn)); +void usage(void) __noreturn; struct pinned_obj_table { DECLARE_HASHTABLE(table, 16); -- GitLab From 146882a37da7aa566c7ec088b42c6495d769f2ba Mon Sep 17 00:00:00 2001 From: Quentin Monnet Date: Tue, 28 Nov 2017 17:44:30 -0800 Subject: [PATCH 0313/2547] tools: bpftool: make error message from getopt_long() JSON-friendly If `getopt_long()` meets an unknown option, it prints its own error message to standard error output. While this does not strictly break JSON output, it is the only case bpftool prints something to standard error output if JSON output is required. All other errors are printed on standard output as JSON objects, so that an external program does not have to parse stderr. This is changed by setting the global variable `opterr` to 0. Furthermore, p_err() is used to reproduce the error message in a more JSON-friendly way, so that users still get to know what the erroneous option is. Signed-off-by: Quentin Monnet Acked-by: Jakub Kicinski Signed-off-by: Daniel Borkmann --- tools/bpf/bpftool/main.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tools/bpf/bpftool/main.c b/tools/bpf/bpftool/main.c index d72dd73a4016..d294bc8168be 100644 --- a/tools/bpf/bpftool/main.c +++ b/tools/bpf/bpftool/main.c @@ -288,6 +288,7 @@ int main(int argc, char **argv) hash_init(prog_table.table); hash_init(map_table.table); + opterr = 0; while ((opt = getopt_long(argc, argv, "Vhpjf", options, NULL)) >= 0) { switch (opt) { @@ -313,7 +314,11 @@ int main(int argc, char **argv) show_pinned = true; break; default: - usage(); + p_err("unrecognized option '%s'", argv[optind - 1]); + if (json_output) + clean_and_exit(-1); + else + usage(); } } -- GitLab From 0d954eeb99eee63964a07a68fcac61e1df8488e7 Mon Sep 17 00:00:00 2001 From: Quentin Monnet Date: Tue, 28 Nov 2017 17:44:31 -0800 Subject: [PATCH 0314/2547] tools: bpftool: remove spurious line break from error message The end-of-line character inside the string would break JSON compliance. Remove it, `p_err()` already adds a '\n' character for plain output anyway. Fixes: 9a5ab8bf1d6d ("tools: bpftool: turn err() and info() macros into functions") Reported-by: Jakub Kicinski Signed-off-by: Quentin Monnet Acked-by: Jakub Kicinski Signed-off-by: Daniel Borkmann --- tools/bpf/bpftool/main.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/bpf/bpftool/main.h b/tools/bpf/bpftool/main.h index 0b60ddfb2b93..bff330b49791 100644 --- a/tools/bpf/bpftool/main.h +++ b/tools/bpf/bpftool/main.h @@ -51,7 +51,7 @@ #define NEXT_ARG() ({ argc--; argv++; if (argc < 0) usage(); }) #define NEXT_ARGP() ({ (*argc)--; (*argv)++; if (*argc < 0) usage(); }) -#define BAD_ARG() ({ p_err("what is '%s'?\n", *argv); -1; }) +#define BAD_ARG() ({ p_err("what is '%s'?", *argv); -1; }) #define ERR_MAX_LEN 1024 -- GitLab From 507e590da398a0e3438d563b5e736c3f2a7749d7 Mon Sep 17 00:00:00 2001 From: Quentin Monnet Date: Tue, 28 Nov 2017 17:44:32 -0800 Subject: [PATCH 0315/2547] tools: bpftool: unify installation directories Programs and documentation not managed by package manager are generally installed under /usr/local/, instead of the user's home directory. In particular, `man` is generally able to find manual pages under `/usr/local/share/man`. bpftool generally follows perf's example, and perf installs to home directory. However bpftool requires root credentials, so it seems sensible to follow the more common convention of installing files under /usr/local instead. So, make /usr/local the default prefix for installing the binary with `make install`, and the documentation with `make doc-install`. Also, create /usr/local/sbin if it does not exist. Note that the bash-completion file, however, is still installed under /usr/share/bash-completion/completions, as the default setup for bash does not attempt to load completion files under /usr/local/. Reported-by: David Beckett Signed-off-by: Quentin Monnet Acked-by: Jakub Kicinski Signed-off-by: Daniel Borkmann --- tools/bpf/bpftool/Documentation/Makefile | 2 +- tools/bpf/bpftool/Makefile | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/tools/bpf/bpftool/Documentation/Makefile b/tools/bpf/bpftool/Documentation/Makefile index bde77d7c4390..37292bb5ce60 100644 --- a/tools/bpf/bpftool/Documentation/Makefile +++ b/tools/bpf/bpftool/Documentation/Makefile @@ -6,7 +6,7 @@ RM ?= rm -f # Make the path relative to DESTDIR, not prefix ifndef DESTDIR -prefix?=$(HOME) +prefix ?= /usr/local endif mandir ?= $(prefix)/share/man man8dir = $(mandir)/man8 diff --git a/tools/bpf/bpftool/Makefile b/tools/bpf/bpftool/Makefile index 813826c50936..c5b21f2cbca5 100644 --- a/tools/bpf/bpftool/Makefile +++ b/tools/bpf/bpftool/Makefile @@ -45,8 +45,8 @@ $(LIBBPF)-clean: $(call QUIET_CLEAN, libbpf) $(Q)$(MAKE) -C $(BPF_DIR) OUTPUT=$(OUTPUT) clean >/dev/null -prefix = /usr -bash_compdir ?= $(prefix)/share/bash-completion/completions +prefix = /usr/local +bash_compdir ?= /usr/share/bash-completion/completions CC = gcc @@ -76,6 +76,7 @@ clean: $(LIBBPF)-clean $(Q)rm -rf $(OUTPUT)bpftool $(OUTPUT)*.o $(OUTPUT)*.d install: + install -m 0755 -d $(prefix)/sbin install $(OUTPUT)bpftool $(prefix)/sbin/bpftool install -m 0755 -d $(bash_compdir) install -m 0644 bash-completion/bpftool $(bash_compdir) -- GitLab From ad3cda064402b69148faf5f7cd1ac8c2eee52645 Mon Sep 17 00:00:00 2001 From: Quentin Monnet Date: Tue, 28 Nov 2017 17:44:33 -0800 Subject: [PATCH 0316/2547] tools: bpftool: declare phony targets as such In the Makefile, targets install, doc and doc-install should be added to .PHONY. Let's fix this. Fixes: 71bb428fe2c1 ("tools: bpf: add bpftool") Signed-off-by: Quentin Monnet Acked-by: Jakub Kicinski Signed-off-by: Daniel Borkmann --- tools/bpf/bpftool/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/bpf/bpftool/Makefile b/tools/bpf/bpftool/Makefile index c5b21f2cbca5..ec3052c0b004 100644 --- a/tools/bpf/bpftool/Makefile +++ b/tools/bpf/bpftool/Makefile @@ -89,5 +89,5 @@ doc-install: FORCE: -.PHONY: all clean FORCE +.PHONY: all clean FORCE install doc doc-install .DEFAULT_GOAL := all -- GitLab From 23721a755f98ac846897a013c92cccb281c1bcc8 Mon Sep 17 00:00:00 2001 From: Xie XiuQi Date: Thu, 30 Nov 2017 09:41:29 +0800 Subject: [PATCH 0317/2547] trace/xdp: fix compile warning: 'struct bpf_map' declared inside parameter list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We meet this compile warning, which caused by missing bpf.h in xdp.h. In file included from ./include/trace/events/xdp.h:10:0, from ./include/linux/bpf_trace.h:6, from drivers/net/ethernet/intel/i40e/i40e_txrx.c:29: ./include/trace/events/xdp.h:93:17: warning: ‘struct bpf_map’ declared inside parameter list will not be visible outside of this definition or declaration const struct bpf_map *map, u32 map_index), ^ ./include/linux/tracepoint.h:187:34: note: in definition of macro ‘__DECLARE_TRACE’ static inline void trace_##name(proto) \ ^~~~~ ./include/linux/tracepoint.h:352:24: note: in expansion of macro ‘PARAMS’ __DECLARE_TRACE(name, PARAMS(proto), PARAMS(args), \ ^~~~~~ ./include/linux/tracepoint.h:477:2: note: in expansion of macro ‘DECLARE_TRACE’ DECLARE_TRACE(name, PARAMS(proto), PARAMS(args)) ^~~~~~~~~~~~~ ./include/linux/tracepoint.h:477:22: note: in expansion of macro ‘PARAMS’ DECLARE_TRACE(name, PARAMS(proto), PARAMS(args)) ^~~~~~ ./include/trace/events/xdp.h:89:1: note: in expansion of macro ‘DEFINE_EVENT’ DEFINE_EVENT(xdp_redirect_template, xdp_redirect, ^~~~~~~~~~~~ ./include/trace/events/xdp.h:90:2: note: in expansion of macro ‘TP_PROTO’ TP_PROTO(const struct net_device *dev, ^~~~~~~~ ./include/trace/events/xdp.h:93:17: warning: ‘struct bpf_map’ declared inside parameter list will not be visible outside of this definition or declaration const struct bpf_map *map, u32 map_index), ^ ./include/linux/tracepoint.h:203:38: note: in definition of macro ‘__DECLARE_TRACE’ register_trace_##name(void (*probe)(data_proto), void *data) \ ^~~~~~~~~~ ./include/linux/tracepoint.h:354:4: note: in expansion of macro ‘PARAMS’ PARAMS(void *__data, proto), \ ^~~~~~ Reported-by: Huang Daode Cc: Hanjun Guo Fixes: 8d3b778ff544 ("xdp: tracepoint xdp_redirect also need a map argument") Signed-off-by: Xie XiuQi Acked-by: Jesper Dangaard Brouer Acked-by: Steven Rostedt (VMware) Signed-off-by: Daniel Borkmann --- include/trace/events/xdp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/trace/events/xdp.h b/include/trace/events/xdp.h index 4cd0f05d0113..8989a92c571a 100644 --- a/include/trace/events/xdp.h +++ b/include/trace/events/xdp.h @@ -8,6 +8,7 @@ #include #include #include +#include #define __XDP_ACT_MAP(FN) \ FN(ABORTED) \ -- GitLab From da8df83957b179e5edc1029f637e5b69eff44967 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Wed, 29 Nov 2017 22:48:11 -0800 Subject: [PATCH 0318/2547] Input: joystick/analog - riscv has get_cycles() Fixes: drivers/input/joystick/analog.c:176:2: warning: #warning Precise timer not defined for this architecture. [-Wcpp] Signed-off-by: Olof Johansson Signed-off-by: Dmitry Torokhov --- drivers/input/joystick/analog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/input/joystick/analog.c b/drivers/input/joystick/analog.c index 3d8ff09eba57..c868a878c84f 100644 --- a/drivers/input/joystick/analog.c +++ b/drivers/input/joystick/analog.c @@ -163,7 +163,7 @@ static unsigned int get_time_pit(void) #define GET_TIME(x) do { x = (unsigned int)rdtsc(); } while (0) #define DELTA(x,y) ((y)-(x)) #define TIME_NAME "TSC" -#elif defined(__alpha__) || defined(CONFIG_MN10300) || defined(CONFIG_ARM) || defined(CONFIG_ARM64) || defined(CONFIG_TILE) +#elif defined(__alpha__) || defined(CONFIG_MN10300) || defined(CONFIG_ARM) || defined(CONFIG_ARM64) || defined(CONFIG_RISCV) || defined(CONFIG_TILE) #define GET_TIME(x) do { x = get_cycles(); } while (0) #define DELTA(x,y) ((y)-(x)) #define TIME_NAME "get_cycles" -- GitLab From 4c83c071b7849ca3e8072284a8587669d8ba6a3d Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Thu, 16 Nov 2017 16:09:29 -0800 Subject: [PATCH 0319/2547] Input: elants_i2c - do not clobber interrupt trigger on x86 This is similar to commit a4b0a58bb142 ("Input: elan_i2c - do not clobber interrupt trigger on x86") On x86 we historically used falling edge interrupts in the driver because that's how first Chrome devices were configured. They also did not use ACPI to enumerate I2C devices (because back then there was no kernel support for that), so trigger was hard-coded in the driver. However the controller behavior is much more reliable if we use level triggers, and that is how we configured ARM devices, and how want to configure newer x86 devices as well. All newer x86 boxes have their I2C devices enumerated in ACPI. Let's see if platform code (ACPI, DT) described interrupt and specified particular trigger type, and if so, let's use it instead of always clobbering trigger with IRQF_TRIGGER_FALLING. We will still use this trigger type as a fallback if platform code left interrupt trigger unconfigured. Reviewed-by: Guenter Roeck Signed-off-by: Dmitry Torokhov --- drivers/input/touchscreen/elants_i2c.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/input/touchscreen/elants_i2c.c b/drivers/input/touchscreen/elants_i2c.c index e102d7764bc2..a458e5ec9e41 100644 --- a/drivers/input/touchscreen/elants_i2c.c +++ b/drivers/input/touchscreen/elants_i2c.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -1261,10 +1262,13 @@ static int elants_i2c_probe(struct i2c_client *client, } /* - * Systems using device tree should set up interrupt via DTS, - * the rest will use the default falling edge interrupts. + * Platform code (ACPI, DTS) should normally set up interrupt + * for us, but in case it did not let's fall back to using falling + * edge to be compatible with older Chromebooks. */ - irqflags = client->dev.of_node ? 0 : IRQF_TRIGGER_FALLING; + irqflags = irq_get_trigger_type(client->irq); + if (!irqflags) + irqflags = IRQF_TRIGGER_FALLING; error = devm_request_threaded_irq(&client->dev, client->irq, NULL, elants_i2c_irq, -- GitLab From 43a3542870328601be02fcc9d27b09db467336ef Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Thu, 30 Nov 2017 10:08:28 +0100 Subject: [PATCH 0320/2547] ALSA: seq: Remove spurious WARN_ON() at timer check The use of snd_BUG_ON() in ALSA sequencer timer may lead to a spurious WARN_ON() when a slave timer is deployed as its backend and a corresponding master timer stops meanwhile. The symptom was triggered by syzkaller spontaneously. Since the NULL timer is valid there, rip off snd_BUG_ON(). Reported-by: syzbot Cc: Signed-off-by: Takashi Iwai --- sound/core/seq/seq_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/core/seq/seq_timer.c b/sound/core/seq/seq_timer.c index 37d9cfbc29f9..b80985fbc334 100644 --- a/sound/core/seq/seq_timer.c +++ b/sound/core/seq/seq_timer.c @@ -355,7 +355,7 @@ static int initialize_timer(struct snd_seq_timer *tmr) unsigned long freq; t = tmr->timeri->timer; - if (snd_BUG_ON(!t)) + if (!t) return -EINVAL; freq = tmr->preferred_resolution; -- GitLab From d929fb4e16b9635dfefa95afe77462de68557af0 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 03:16:17 -0500 Subject: [PATCH 0321/2547] media: atomisp: stop producing hundreds of kernel-doc warnings A recent change on Kernel 4.15-rc1 causes all tags with /** to be handled as kernel-doc markups. Well, several atomisp modules, it doesn't use kernel-doc, but some other documentation markup (doxygen?). So, suppress all those warns by: - replacing /**< by /**. - replacing /** by /*. The core changes were done with: for i in $(find drivers/staging/media/atomisp -type f); do sed 's,/\*\* ,/\*, ' -i $i; done for i in $(find drivers/staging/media/atomisp -type f); do sed 's,/\*\*<,/\**,' -i $i; done for i in drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/src/ia_css_debug.c drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_sp.c drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr_vbuf.c; do perl -ne 's,\/\*\*$,/*,g; print $_' $i > a && mv a $i; done; A few manual adjustments were made, where needed. Signed-off-by: Mauro Carvalho Chehab Acked-by: Sakari Ailus --- .../media/atomisp/include/linux/atomisp.h | 34 +-- .../media/atomisp/pci/atomisp2/atomisp_cmd.c | 2 +- .../pci/atomisp2/atomisp_compat_css20.c | 2 +- .../pci/atomisp2/atomisp_compat_ioctl32.h | 16 +- .../atomisp/pci/atomisp2/atomisp_subdev.h | 2 +- .../css2400/base/circbuf/src/circbuf.c | 26 +- .../pipe/interface/ia_css_pipe_binarydesc.h | 34 +-- .../camera/pipe/interface/ia_css_pipe_util.h | 2 +- .../camera/util/interface/ia_css_util.h | 18 +- .../host/csi_rx_private.h | 2 +- .../host/ibuf_ctrl_private.h | 4 +- .../css_2401_csi2p_system/host/isys_irq.c | 2 +- .../host/isys_irq_private.h | 4 +- .../host/isys_stream2mmio_private.h | 4 +- .../host/pixelgen_private.h | 2 +- .../css_2401_csi2p_system/isys_dma_global.h | 4 +- .../css_2401_csi2p_system/pixelgen_global.h | 2 +- .../css_2401_csi2p_system/system_global.h | 8 +- .../pci/atomisp2/css2400/css_api_version.h | 2 +- .../hive_isp_css_common/host/gp_timer.c | 2 +- .../hive_isp_css_include/host/csi_rx_public.h | 4 +- .../host/ibuf_ctrl_public.h | 4 +- .../hive_isp_css_include/host/isp_op1w.h | 98 +++---- .../hive_isp_css_include/host/isp_op2w.h | 78 +++--- .../host/isys_stream2mmio_public.h | 4 +- .../host/pixelgen_public.h | 4 +- .../host/ref_vector_func.h | 144 +++++----- .../hive_isp_css_include/math_support.h | 2 +- .../hive_isp_css_include/string_support.h | 8 +- .../css2400/hive_isp_css_shared/host/tag.c | 4 +- .../atomisp/pci/atomisp2/css2400/ia_css.h | 2 +- .../atomisp/pci/atomisp2/css2400/ia_css_3a.h | 38 +-- .../pci/atomisp2/css2400/ia_css_acc_types.h | 216 +++++++-------- .../pci/atomisp2/css2400/ia_css_buffer.h | 32 +-- .../pci/atomisp2/css2400/ia_css_control.h | 22 +- .../atomisp2/css2400/ia_css_device_access.h | 2 +- .../atomisp/pci/atomisp2/css2400/ia_css_dvs.h | 52 ++-- .../atomisp/pci/atomisp2/css2400/ia_css_env.h | 40 +-- .../atomisp/pci/atomisp2/css2400/ia_css_err.h | 18 +- .../atomisp2/css2400/ia_css_event_public.h | 68 ++--- .../pci/atomisp2/css2400/ia_css_firmware.h | 14 +- .../pci/atomisp2/css2400/ia_css_frac.h | 10 +- .../atomisp2/css2400/ia_css_frame_format.h | 62 ++--- .../atomisp2/css2400/ia_css_frame_public.h | 120 ++++---- .../pci/atomisp2/css2400/ia_css_input_port.h | 32 +-- .../atomisp/pci/atomisp2/css2400/ia_css_irq.h | 112 ++++---- .../pci/atomisp2/css2400/ia_css_metadata.h | 24 +- .../pci/atomisp2/css2400/ia_css_mipi.h | 10 +- .../atomisp/pci/atomisp2/css2400/ia_css_mmu.h | 4 +- .../pci/atomisp2/css2400/ia_css_morph.h | 6 +- .../pci/atomisp2/css2400/ia_css_pipe_public.h | 128 ++++----- .../pci/atomisp2/css2400/ia_css_prbs.h | 12 +- .../pci/atomisp2/css2400/ia_css_properties.h | 6 +- .../pci/atomisp2/css2400/ia_css_shading.h | 6 +- .../pci/atomisp2/css2400/ia_css_stream.h | 4 +- .../atomisp2/css2400/ia_css_stream_format.h | 90 +++--- .../atomisp2/css2400/ia_css_stream_public.h | 148 +++++----- .../pci/atomisp2/css2400/ia_css_timer.h | 30 +- .../atomisp/pci/atomisp2/css2400/ia_css_tpg.h | 8 +- .../pci/atomisp2/css2400/ia_css_types.h | 258 +++++++++--------- .../pci/atomisp2/css2400/ia_css_version.h | 6 +- .../isp/kernels/aa/aa_2/ia_css_aa2_types.h | 6 +- .../kernels/anr/anr_1.0/ia_css_anr_types.h | 6 +- .../isp/kernels/anr/anr_2/ia_css_anr2_types.h | 4 +- .../isp/kernels/anr/anr_2/ia_css_anr_param.h | 2 +- .../bayer_ls_1.0/ia_css_bayer_ls_param.h | 2 +- .../isp/kernels/bh/bh_2/ia_css_bh_types.h | 4 +- .../isp/kernels/bnlm/ia_css_bnlm_types.h | 36 +-- .../kernels/bnr/bnr2_2/ia_css_bnr2_2_types.h | 34 +-- .../isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h | 20 +- .../conversion_1.0/ia_css_conversion_types.h | 8 +- .../kernels/crop/crop_1.0/ia_css_crop_param.h | 2 +- .../kernels/crop/crop_1.0/ia_css_crop_types.h | 2 +- .../kernels/csc/csc_1.0/ia_css_csc_types.h | 8 +- .../isp/kernels/ctc/ctc2/ia_css_ctc2_param.h | 12 +- .../isp/kernels/ctc/ctc2/ia_css_ctc2_types.h | 10 +- .../kernels/ctc/ctc_1.0/ia_css_ctc_types.h | 38 +-- .../isp/kernels/de/de_1.0/ia_css_de_types.h | 10 +- .../isp/kernels/de/de_2/ia_css_de2_types.h | 10 +- .../isp/kernels/dp/dp_1.0/ia_css_dp_types.h | 8 +- .../isp/kernels/dpc2/ia_css_dpc2_types.h | 6 +- .../kernels/dvs/dvs_1.0/ia_css_dvs_param.h | 2 +- .../kernels/dvs/dvs_1.0/ia_css_dvs_types.h | 2 +- .../isp/kernels/eed1_8/ia_css_eed1_8_types.h | 82 +++--- .../kernels/fc/fc_1.0/ia_css_formats_types.h | 6 +- .../kernels/fpn/fpn_1.0/ia_css_fpn_types.h | 14 +- .../isp/kernels/gc/gc_1.0/ia_css_gc_types.h | 32 +-- .../isp/kernels/gc/gc_2/ia_css_gc2_types.h | 14 +- .../isp/kernels/hdr/ia_css_hdr_types.h | 26 +- .../bayer_io_ls/ia_css_bayer_io.host.c | 2 +- .../yuv444_io_ls/ia_css_yuv444_io.host.c | 2 +- .../macc/macc1_5/ia_css_macc1_5_types.h | 16 +- .../kernels/macc/macc_1.0/ia_css_macc_types.h | 12 +- .../isp/kernels/ob/ob2/ia_css_ob2_types.h | 12 +- .../isp/kernels/ob/ob_1.0/ia_css_ob_types.h | 26 +- .../output/output_1.0/ia_css_output_param.h | 2 +- .../output/output_1.0/ia_css_output_types.h | 8 +- .../qplane/qplane_2/ia_css_qplane_types.h | 2 +- .../kernels/raw/raw_1.0/ia_css_raw_types.h | 2 +- .../kernels/ref/ref_1.0/ia_css_ref_param.h | 2 +- .../kernels/ref/ref_1.0/ia_css_ref_types.h | 2 +- .../kernels/s3a/s3a_1.0/ia_css_s3a_types.h | 98 +++---- .../s3a_stat_ls/ia_css_s3a_stat_ls_param.h | 2 +- .../isp/kernels/sc/sc_1.0/ia_css_sc.host.h | 4 +- .../isp/kernels/sc/sc_1.0/ia_css_sc_types.h | 42 +-- .../sdis/common/ia_css_sdis_common_types.h | 104 +++---- .../kernels/sdis/sdis_1.0/ia_css_sdis_types.h | 20 +- .../kernels/sdis/sdis_2/ia_css_sdis2_types.h | 40 +-- .../kernels/tdf/tdf_1.0/ia_css_tdf_types.h | 38 +-- .../isp/kernels/tnr/tnr3/ia_css_tnr3_types.h | 26 +- .../kernels/tnr/tnr_1.0/ia_css_tnr_types.h | 10 +- .../isp/kernels/vf/vf_1.0/ia_css_vf_param.h | 4 +- .../isp/kernels/vf/vf_1.0/ia_css_vf_types.h | 4 +- .../isp/kernels/wb/wb_1.0/ia_css_wb_types.h | 14 +- .../isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.c | 2 +- .../kernels/xnr/xnr_1.0/ia_css_xnr_param.h | 2 +- .../kernels/xnr/xnr_1.0/ia_css_xnr_types.h | 20 +- .../kernels/xnr/xnr_3.0/ia_css_xnr3_types.h | 30 +- .../kernels/ynr/ynr_1.0/ia_css_ynr_types.h | 28 +- .../isp/kernels/ynr/ynr_2/ia_css_ynr2_types.h | 40 +-- .../yuv_ls/yuv_ls_1.0/ia_css_yuv_ls_param.h | 2 +- .../pci/atomisp2/css2400/memory_realloc.c | 2 +- .../runtime/binary/interface/ia_css_binary.h | 2 +- .../css2400/runtime/binary/src/binary.c | 2 +- .../atomisp2/css2400/runtime/bufq/src/bufq.c | 2 +- .../runtime/debug/interface/ia_css_debug.h | 30 +- .../css2400/runtime/debug/src/ia_css_debug.c | 10 +- .../css2400/runtime/event/src/event.c | 4 +- .../css2400/runtime/eventq/src/eventq.c | 2 +- .../runtime/frame/interface/ia_css_frame.h | 22 +- .../css2400/runtime/frame/src/frame.c | 2 +- .../css2400/runtime/ifmtr/src/ifmtr.c | 2 +- .../css2400/runtime/inputfifo/src/inputfifo.c | 2 +- .../interface/ia_css_isp_param_types.h | 6 +- .../css2400/runtime/isp_param/src/isp_param.c | 2 +- .../runtime/isys/interface/ia_css_isys.h | 6 +- .../css2400/runtime/isys/src/csi_rx_rmgr.c | 2 +- .../css2400/runtime/isys/src/ibuf_ctrl_rmgr.c | 2 +- .../css2400/runtime/isys/src/isys_dma_rmgr.c | 2 +- .../css2400/runtime/isys/src/isys_init.c | 2 +- .../runtime/isys/src/isys_stream2mmio_rmgr.c | 2 +- .../atomisp2/css2400/runtime/isys/src/rx.c | 2 +- .../css2400/runtime/isys/src/virtual_isys.c | 8 +- .../pipeline/interface/ia_css_pipeline.h | 28 +- .../css2400/runtime/pipeline/src/pipeline.c | 8 +- .../runtime/queue/interface/ia_css_queue.h | 22 +- .../css2400/runtime/queue/src/queue_access.c | 2 +- .../atomisp2/css2400/runtime/rmgr/src/rmgr.c | 4 +- .../css2400/runtime/rmgr/src/rmgr_vbuf.c | 26 +- .../runtime/spctrl/interface/ia_css_spctrl.h | 20 +- .../spctrl/interface/ia_css_spctrl_comm.h | 14 +- .../css2400/runtime/spctrl/src/spctrl.c | 4 +- .../css2400/runtime/timer/src/timer.c | 2 +- .../atomisp/pci/atomisp2/css2400/sh_css.c | 68 ++--- .../pci/atomisp2/css2400/sh_css_internal.h | 22 +- .../pci/atomisp2/css2400/sh_css_legacy.h | 2 +- .../pci/atomisp2/css2400/sh_css_mipi.c | 4 +- .../pci/atomisp2/css2400/sh_css_params.h | 4 +- .../atomisp/pci/atomisp2/css2400/sh_css_sp.c | 18 +- .../pci/atomisp2/css2400/sh_css_struct.h | 2 +- 160 files changed, 1746 insertions(+), 1746 deletions(-) diff --git a/drivers/staging/media/atomisp/include/linux/atomisp.h b/drivers/staging/media/atomisp/include/linux/atomisp.h index b5533197226d..15fa5679bae7 100644 --- a/drivers/staging/media/atomisp/include/linux/atomisp.h +++ b/drivers/staging/media/atomisp/include/linux/atomisp.h @@ -208,14 +208,14 @@ struct atomisp_dis_vector { }; -/** DVS 2.0 Coefficient types. This structure contains 4 pointers to +/* DVS 2.0 Coefficient types. This structure contains 4 pointers to * arrays that contain the coeffients for each type. */ struct atomisp_dvs2_coef_types { - short __user *odd_real; /**< real part of the odd coefficients*/ - short __user *odd_imag; /**< imaginary part of the odd coefficients*/ - short __user *even_real;/**< real part of the even coefficients*/ - short __user *even_imag;/**< imaginary part of the even coefficients*/ + short __user *odd_real; /** real part of the odd coefficients*/ + short __user *odd_imag; /** imaginary part of the odd coefficients*/ + short __user *even_real;/** real part of the even coefficients*/ + short __user *even_imag;/** imaginary part of the even coefficients*/ }; /* @@ -223,10 +223,10 @@ struct atomisp_dvs2_coef_types { * arrays that contain the statistics for each type. */ struct atomisp_dvs2_stat_types { - int __user *odd_real; /**< real part of the odd statistics*/ - int __user *odd_imag; /**< imaginary part of the odd statistics*/ - int __user *even_real;/**< real part of the even statistics*/ - int __user *even_imag;/**< imaginary part of the even statistics*/ + int __user *odd_real; /** real part of the odd statistics*/ + int __user *odd_imag; /** imaginary part of the odd statistics*/ + int __user *even_real;/** real part of the even statistics*/ + int __user *even_imag;/** imaginary part of the even statistics*/ }; struct atomisp_dis_coefficients { @@ -390,16 +390,16 @@ struct atomisp_metadata_config { * Generic resolution structure. */ struct atomisp_resolution { - uint32_t width; /**< Width */ - uint32_t height; /**< Height */ + uint32_t width; /** Width */ + uint32_t height; /** Height */ }; /* * This specifies the coordinates (x,y) */ struct atomisp_zoom_point { - int32_t x; /**< x coordinate */ - int32_t y; /**< y coordinate */ + int32_t x; /** x coordinate */ + int32_t y; /** y coordinate */ }; /* @@ -411,9 +411,9 @@ struct atomisp_zoom_region { }; struct atomisp_dz_config { - uint32_t dx; /**< Horizontal zoom factor */ - uint32_t dy; /**< Vertical zoom factor */ - struct atomisp_zoom_region zoom_region; /**< region for zoom */ + uint32_t dx; /** Horizontal zoom factor */ + uint32_t dy; /** Vertical zoom factor */ + struct atomisp_zoom_region zoom_region; /** region for zoom */ }; struct atomisp_parm { @@ -758,7 +758,7 @@ enum atomisp_acc_arg_type { ATOMISP_ACC_ARG_FRAME /* Frame argument */ }; -/** ISP memories, isp2400 */ +/* ISP memories, isp2400 */ enum atomisp_acc_memory { ATOMISP_ACC_MEMORY_PMEM0 = 0, ATOMISP_ACC_MEMORY_DMEM0, diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.c index 8a18c528cad4..debf0e3853ff 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.c @@ -5187,7 +5187,7 @@ int get_frame_info_nop(struct atomisp_sub_device *asd, return 0; } -/** +/* * Resets CSS parameters that depend on input resolution. * * Update params like CSS RAW binning, 2ppc mode and pp_input diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.c index 6e87aa5aab4c..b7f9da014641 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.c @@ -4051,7 +4051,7 @@ int atomisp_css_get_formats_config(struct atomisp_sub_device *asd, int atomisp_css_get_zoom_factor(struct atomisp_sub_device *asd, unsigned int *zoom) { - struct ia_css_dz_config dz_config; /**< Digital Zoom */ + struct ia_css_dz_config dz_config; /** Digital Zoom */ struct ia_css_isp_config isp_config; struct atomisp_device *isp = asd->isp; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.h index 685da0f48bab..95669eedaad1 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.h @@ -28,17 +28,17 @@ struct atomisp_histogram32 { }; struct atomisp_dvs2_stat_types32 { - compat_uptr_t odd_real; /**< real part of the odd statistics*/ - compat_uptr_t odd_imag; /**< imaginary part of the odd statistics*/ - compat_uptr_t even_real;/**< real part of the even statistics*/ - compat_uptr_t even_imag;/**< imaginary part of the even statistics*/ + compat_uptr_t odd_real; /** real part of the odd statistics*/ + compat_uptr_t odd_imag; /** imaginary part of the odd statistics*/ + compat_uptr_t even_real;/** real part of the even statistics*/ + compat_uptr_t even_imag;/** imaginary part of the even statistics*/ }; struct atomisp_dvs2_coef_types32 { - compat_uptr_t odd_real; /**< real part of the odd coefficients*/ - compat_uptr_t odd_imag; /**< imaginary part of the odd coefficients*/ - compat_uptr_t even_real;/**< real part of the even coefficients*/ - compat_uptr_t even_imag;/**< imaginary part of the even coefficients*/ + compat_uptr_t odd_real; /** real part of the odd coefficients*/ + compat_uptr_t odd_imag; /** imaginary part of the odd coefficients*/ + compat_uptr_t even_real;/** real part of the even coefficients*/ + compat_uptr_t even_imag;/** imaginary part of the even coefficients*/ }; struct atomisp_dvs2_statistics32 { diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.h index f3d61827ae8c..c3eba675da06 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.h @@ -223,7 +223,7 @@ struct atomisp_subdev_params { bool dis_proj_data_valid; - struct ia_css_dz_config dz_config; /**< Digital Zoom */ + struct ia_css_dz_config dz_config; /** Digital Zoom */ struct ia_css_capture_config capture_config; struct atomisp_css_isp_config config; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/src/circbuf.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/src/circbuf.c index 19bae1610fb6..050d60f0894f 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/src/circbuf.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/src/circbuf.c @@ -21,7 +21,7 @@ * Forward declarations. * **********************************************************************/ -/** +/* * @brief Read the oldest element from the circular buffer. * Read the oldest element WITHOUT checking whehter the * circular buffer is empty or not. The oldest element is @@ -34,7 +34,7 @@ static inline ia_css_circbuf_elem_t ia_css_circbuf_read(ia_css_circbuf_t *cb); -/** +/* * @brief Shift a chunk of elements in the circular buffer. * A chunk of elements (i.e. the ones from the "start" position * to the "chunk_src" position) are shifted in the circular buffer, @@ -48,7 +48,7 @@ static inline void ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb, uint32_t chunk_src, uint32_t chunk_dest); -/** +/* * @brief Get the "val" field in the element. * * @param elem The pointer to the element. @@ -63,7 +63,7 @@ ia_css_circbuf_elem_get_val(ia_css_circbuf_elem_t *elem); * Non-inline functions. * **********************************************************************/ -/** +/* * @brief Create the circular buffer. * Refer to "ia_css_circbuf.h" for details. */ @@ -88,7 +88,7 @@ ia_css_circbuf_create(ia_css_circbuf_t *cb, cb->elems = elems; } -/** +/* * @brief Destroy the circular buffer. * Refer to "ia_css_circbuf.h" for details. */ @@ -99,7 +99,7 @@ void ia_css_circbuf_destroy(ia_css_circbuf_t *cb) cb->elems = NULL; } -/** +/* * @brief Pop a value out of the circular buffer. * Refer to "ia_css_circbuf.h" for details. */ @@ -116,7 +116,7 @@ uint32_t ia_css_circbuf_pop(ia_css_circbuf_t *cb) return ret; } -/** +/* * @brief Extract a value out of the circular buffer. * Refer to "ia_css_circbuf.h" for details. */ @@ -166,7 +166,7 @@ uint32_t ia_css_circbuf_extract(ia_css_circbuf_t *cb, int offset) return val; } -/** +/* * @brief Peek an element from the circular buffer. * Refer to "ia_css_circbuf.h" for details. */ @@ -180,7 +180,7 @@ uint32_t ia_css_circbuf_peek(ia_css_circbuf_t *cb, int offset) return cb->elems[pos].val; } -/** +/* * @brief Get the value of an element from the circular buffer. * Refer to "ia_css_circbuf.h" for details. */ @@ -194,7 +194,7 @@ uint32_t ia_css_circbuf_peek_from_start(ia_css_circbuf_t *cb, int offset) return cb->elems[pos].val; } -/** @brief increase size of a circular buffer. +/* @brief increase size of a circular buffer. * Use 'CAUTION' before using this function. This was added to * support / fix issue with increasing size for tagger only * Please refer to "ia_css_circbuf.h" for details. @@ -252,7 +252,7 @@ bool ia_css_circbuf_increase_size( * Inline functions. * ****************************************************************/ -/** +/* * @brief Get the "val" field in the element. * Refer to "Forward declarations" for details. */ @@ -262,7 +262,7 @@ ia_css_circbuf_elem_get_val(ia_css_circbuf_elem_t *elem) return elem->val; } -/** +/* * @brief Read the oldest element from the circular buffer. * Refer to "Forward declarations" for details. */ @@ -282,7 +282,7 @@ ia_css_circbuf_read(ia_css_circbuf_t *cb) return elem; } -/** +/* * @brief Shift a chunk of elements in the circular buffer. * Refer to "Forward declarations" for details. */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_binarydesc.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_binarydesc.h index 616789d9b3f6..a6d650a9a1f4 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_binarydesc.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_binarydesc.h @@ -19,7 +19,7 @@ #include /* ia_css_frame_info */ #include /* ia_css_binary_descr */ -/** @brief Get a binary descriptor for copy. +/* @brief Get a binary descriptor for copy. * * @param[in] pipe * @param[out] copy_desc @@ -36,7 +36,7 @@ extern void ia_css_pipe_get_copy_binarydesc( struct ia_css_frame_info *out_info, struct ia_css_frame_info *vf_info); -/** @brief Get a binary descriptor for vfpp. +/* @brief Get a binary descriptor for vfpp. * * @param[in] pipe * @param[out] vfpp_descr @@ -51,7 +51,7 @@ extern void ia_css_pipe_get_vfpp_binarydesc( struct ia_css_frame_info *in_info, struct ia_css_frame_info *out_info); -/** @brief Get numerator and denominator of bayer downscaling factor. +/* @brief Get numerator and denominator of bayer downscaling factor. * * @param[in] bds_factor: The bayer downscaling factor. * (= The bds_factor member in the sh_css_bds_factor structure.) @@ -67,7 +67,7 @@ extern enum ia_css_err sh_css_bds_factor_get_numerator_denominator( unsigned int *bds_factor_numerator, unsigned int *bds_factor_denominator); -/** @brief Get a binary descriptor for preview stage. +/* @brief Get a binary descriptor for preview stage. * * @param[in] pipe * @param[out] preview_descr @@ -86,7 +86,7 @@ extern enum ia_css_err ia_css_pipe_get_preview_binarydesc( struct ia_css_frame_info *out_info, struct ia_css_frame_info *vf_info); -/** @brief Get a binary descriptor for video stage. +/* @brief Get a binary descriptor for video stage. * * @param[in/out] pipe * @param[out] video_descr @@ -105,7 +105,7 @@ extern enum ia_css_err ia_css_pipe_get_video_binarydesc( struct ia_css_frame_info *vf_info, int stream_config_left_padding); -/** @brief Get a binary descriptor for yuv scaler stage. +/* @brief Get a binary descriptor for yuv scaler stage. * * @param[in/out] pipe * @param[out] yuv_scaler_descr @@ -124,7 +124,7 @@ void ia_css_pipe_get_yuvscaler_binarydesc( struct ia_css_frame_info *internal_out_info, struct ia_css_frame_info *vf_info); -/** @brief Get a binary descriptor for capture pp stage. +/* @brief Get a binary descriptor for capture pp stage. * * @param[in/out] pipe * @param[out] capture_pp_descr @@ -140,7 +140,7 @@ extern void ia_css_pipe_get_capturepp_binarydesc( struct ia_css_frame_info *out_info, struct ia_css_frame_info *vf_info); -/** @brief Get a binary descriptor for primary capture. +/* @brief Get a binary descriptor for primary capture. * * @param[in] pipe * @param[out] prim_descr @@ -158,7 +158,7 @@ extern void ia_css_pipe_get_primary_binarydesc( struct ia_css_frame_info *vf_info, unsigned int stage_idx); -/** @brief Get a binary descriptor for pre gdc stage. +/* @brief Get a binary descriptor for pre gdc stage. * * @param[in] pipe * @param[out] pre_gdc_descr @@ -173,7 +173,7 @@ extern void ia_css_pipe_get_pre_gdc_binarydesc( struct ia_css_frame_info *in_info, struct ia_css_frame_info *out_info); -/** @brief Get a binary descriptor for gdc stage. +/* @brief Get a binary descriptor for gdc stage. * * @param[in] pipe * @param[out] gdc_descr @@ -188,7 +188,7 @@ extern void ia_css_pipe_get_gdc_binarydesc( struct ia_css_frame_info *in_info, struct ia_css_frame_info *out_info); -/** @brief Get a binary descriptor for post gdc. +/* @brief Get a binary descriptor for post gdc. * * @param[in] pipe * @param[out] post_gdc_descr @@ -205,7 +205,7 @@ extern void ia_css_pipe_get_post_gdc_binarydesc( struct ia_css_frame_info *out_info, struct ia_css_frame_info *vf_info); -/** @brief Get a binary descriptor for de. +/* @brief Get a binary descriptor for de. * * @param[in] pipe * @param[out] pre_de_descr @@ -220,7 +220,7 @@ extern void ia_css_pipe_get_pre_de_binarydesc( struct ia_css_frame_info *in_info, struct ia_css_frame_info *out_info); -/** @brief Get a binary descriptor for pre anr stage. +/* @brief Get a binary descriptor for pre anr stage. * * @param[in] pipe * @param[out] pre_anr_descr @@ -235,7 +235,7 @@ extern void ia_css_pipe_get_pre_anr_binarydesc( struct ia_css_frame_info *in_info, struct ia_css_frame_info *out_info); -/** @brief Get a binary descriptor for ANR stage. +/* @brief Get a binary descriptor for ANR stage. * * @param[in] pipe * @param[out] anr_descr @@ -250,7 +250,7 @@ extern void ia_css_pipe_get_anr_binarydesc( struct ia_css_frame_info *in_info, struct ia_css_frame_info *out_info); -/** @brief Get a binary descriptor for post anr stage. +/* @brief Get a binary descriptor for post anr stage. * * @param[in] pipe * @param[out] post_anr_descr @@ -267,7 +267,7 @@ extern void ia_css_pipe_get_post_anr_binarydesc( struct ia_css_frame_info *out_info, struct ia_css_frame_info *vf_info); -/** @brief Get a binary descriptor for ldc stage. +/* @brief Get a binary descriptor for ldc stage. * * @param[in/out] pipe * @param[out] capture_pp_descr @@ -282,7 +282,7 @@ extern void ia_css_pipe_get_ldc_binarydesc( struct ia_css_frame_info *in_info, struct ia_css_frame_info *out_info); -/** @brief Calculates the required BDS factor +/* @brief Calculates the required BDS factor * * @param[in] input_res * @param[in] output_res diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_util.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_util.h index ba8858759b30..155b6fb4722b 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_util.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_util.h @@ -18,7 +18,7 @@ #include #include -/** @brief Get Input format bits per pixel based on stream configuration of this +/* @brief Get Input format bits per pixel based on stream configuration of this * pipe. * * @param[in] pipe diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/interface/ia_css_util.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/interface/ia_css_util.h index f8b2e458f876..a8c27676a38b 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/interface/ia_css_util.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/interface/ia_css_util.h @@ -22,7 +22,7 @@ #include #include -/** @brief convert "errno" error code to "ia_css_err" error code +/* @brief convert "errno" error code to "ia_css_err" error code * * @param[in] "errno" error code * @return "ia_css_err" error code @@ -31,7 +31,7 @@ enum ia_css_err ia_css_convert_errno( int in_err); -/** @brief check vf frame info. +/* @brief check vf frame info. * * @param[in] info * @return IA_CSS_SUCCESS or error code upon error. @@ -40,7 +40,7 @@ enum ia_css_err ia_css_convert_errno( extern enum ia_css_err ia_css_util_check_vf_info( const struct ia_css_frame_info * const info); -/** @brief check input configuration. +/* @brief check input configuration. * * @param[in] stream_config * @param[in] must_be_raw @@ -52,7 +52,7 @@ extern enum ia_css_err ia_css_util_check_input( bool must_be_raw, bool must_be_yuv); -/** @brief check vf and out frame info. +/* @brief check vf and out frame info. * * @param[in] out_info * @param[in] vf_info @@ -63,7 +63,7 @@ extern enum ia_css_err ia_css_util_check_vf_out_info( const struct ia_css_frame_info * const out_info, const struct ia_css_frame_info * const vf_info); -/** @brief check width and height +/* @brief check width and height * * @param[in] width * @param[in] height @@ -75,7 +75,7 @@ extern enum ia_css_err ia_css_util_check_res( unsigned int height); #ifdef ISP2401 -/** @brief compare resolutions (less or equal) +/* @brief compare resolutions (less or equal) * * @param[in] a resolution * @param[in] b resolution @@ -108,7 +108,7 @@ extern bool ia_css_util_resolution_is_even( const struct ia_css_resolution resolution); #endif -/** @brief check width and height +/* @brief check width and height * * @param[in] stream_format * @param[in] two_ppc @@ -119,7 +119,7 @@ extern unsigned int ia_css_util_input_format_bpp( enum ia_css_stream_format stream_format, bool two_ppc); -/** @brief check if input format it raw +/* @brief check if input format it raw * * @param[in] stream_format * @return true if the input format is raw or false otherwise @@ -128,7 +128,7 @@ extern unsigned int ia_css_util_input_format_bpp( extern bool ia_css_util_is_input_format_raw( enum ia_css_stream_format stream_format); -/** @brief check if input format it yuv +/* @brief check if input format it yuv * * @param[in] stream_format * @return true if the input format is yuv or false otherwise diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_private.h index 6720ab55d6f5..9c0cb4a63862 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_private.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_private.h @@ -277,6 +277,6 @@ static inline void csi_rx_be_ctrl_reg_store( ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); } -/** end of DLI */ +/* end of DLI */ #endif /* __CSI_RX_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_private.h index 470c92d287fe..4d07c2fe1469 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_private.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_private.h @@ -192,7 +192,7 @@ STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_dump_state( ia_css_print("IBUF controller ID %d Process ID %d isp_sync_state 0x%x\n", ID, i, state->proc_state[i].isp_sync_state); } } -/** end of NCI */ +/* end of NCI */ /***************************************************** * @@ -227,7 +227,7 @@ STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_reg_store( ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); } -/** end of DLI */ +/* end of DLI */ #endif /* __IBUF_CTRL_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq.c index 14d1d3b627a9..842ae340ae13 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq.c @@ -26,7 +26,7 @@ #include "isys_irq_private.h" #endif -/** Public interface */ +/* Public interface */ STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_status_enable( const isys_irq_ID_t isys_irqc_id) { diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_private.h index c17ce131c9e1..e69f39893bd2 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_private.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_private.h @@ -59,7 +59,7 @@ STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_state_dump( state->status, state->edge, state->mask, state->enable, state->level_no); } -/** end of NCI */ +/* end of NCI */ /* -------------------------------------------------------+ | Device level interface (DLI) | @@ -101,7 +101,7 @@ STORAGE_CLASS_ISYS2401_IRQ_C hrt_data isys_irqc_reg_load( return value; } -/** end of DLI */ +/* end of DLI */ #endif /* defined(USE_INPUT_SYSTEM_VERSION_2401) */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_private.h index 1603a09b621a..f946105ddf43 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_private.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_private.h @@ -122,7 +122,7 @@ STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_dump_state( stream2mmio_print_sid_state(&(state->sid_state[i])); } } -/** end of NCI */ +/* end of NCI */ /***************************************************** * @@ -163,6 +163,6 @@ STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_reg_store( ia_css_device_store_uint32(STREAM2MMIO_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); } -/** end of DLI */ +/* end of DLI */ #endif /* __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_private.h index 3f34b508f0bf..c5bf540eadf1 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_private.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_private.h @@ -160,5 +160,5 @@ STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_reg_store( ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); } -/** end of DLI */ +/* end of DLI */ #endif /* __PIXELGEN_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_dma_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_dma_global.h index e7a734a9fc43..1be5c6956d65 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_dma_global.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_dma_global.h @@ -46,7 +46,7 @@ struct isys2401_dma_port_cfg_s { uint32_t cropping; uint32_t width; }; -/** end of DMA Port */ +/* end of DMA Port */ /************************************************ * @@ -79,7 +79,7 @@ struct isys2401_dma_cfg_s { isys2401_dma_extension extension; uint32_t height; }; -/** end of DMA Device */ +/* end of DMA Device */ /* isys2401_dma_channel limits per DMA ID */ extern const isys2401_dma_channel N_ISYS2401_DMA_CHANNEL_PROCS[N_ISYS2401_DMA_ID]; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/pixelgen_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/pixelgen_global.h index 216813e42a0a..0bf2feb8bbfb 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/pixelgen_global.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/pixelgen_global.h @@ -86,6 +86,6 @@ struct pixelgen_prbs_cfg_s { sync_generator_cfg_t sync_gen_cfg; }; -/** end of Pixel-generator: TPG. ("pixelgen_global.h") */ +/* end of Pixel-generator: TPG. ("pixelgen_global.h") */ #endif /* __PIXELGEN_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/system_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/system_global.h index 9f7ecac46273..d2e3a2deea2e 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/system_global.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/system_global.h @@ -331,7 +331,7 @@ typedef enum { IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */ N_IBUF_CTRL_ID } ibuf_ctrl_ID_t; -/** end of Input-buffer Controller */ +/* end of Input-buffer Controller */ /* * Stream2MMIO. @@ -364,7 +364,7 @@ typedef enum { STREAM2MMIO_SID7_ID, N_STREAM2MMIO_SID_ID } stream2mmio_sid_ID_t; -/** end of Stream2MMIO */ +/* end of Stream2MMIO */ /** * Input System 2401: CSI-MIPI recevier. @@ -390,7 +390,7 @@ typedef enum { CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */ N_CSI_RX_DLANE_ID } csi_rx_fe_dlane_ID_t; -/** end of CSI-MIPI receiver */ +/* end of CSI-MIPI receiver */ typedef enum { ISYS2401_DMA0_ID = 0, @@ -406,7 +406,7 @@ typedef enum { PIXELGEN2_ID, N_PIXELGEN_ID } pixelgen_ID_t; -/** end of pixel-generator. ("system_global.h") */ +/* end of pixel-generator. ("system_global.h") */ typedef enum { INPUT_SYSTEM_CSI_PORT0_ID = 0, diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_api_version.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_api_version.h index 1f6a55ff5db8..efcd6e1679e8 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_api_version.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_api_version.h @@ -31,7 +31,7 @@ more details. #ifndef __CSS_API_VERSION_H #define __CSS_API_VERSION_H -/** @file +/* @file * CSS API version file. This file contains the version number of the CSS-API. * * This file is generated from a set of input files describing the CSS-API diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer.c index 5a4eabf79ee2..bcfd443f5202 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer.c @@ -21,7 +21,7 @@ #endif /* __INLINE_GP_TIMER__ */ #include "system_local.h" -/** FIXME: not sure if reg_load(), reg_store() should be API. +/* FIXME: not sure if reg_load(), reg_store() should be API. */ static uint32_t gp_timer_reg_load(uint32_t reg); diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/csi_rx_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/csi_rx_public.h index 3b5df85fc510..426d022d3a26 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/csi_rx_public.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/csi_rx_public.h @@ -73,7 +73,7 @@ extern void csi_rx_be_ctrl_get_state( extern void csi_rx_be_ctrl_dump_state( const csi_rx_backend_ID_t ID, csi_rx_be_ctrl_state_t *state); -/** end of NCI */ +/* end of NCI */ /***************************************************** * @@ -130,6 +130,6 @@ extern void csi_rx_be_ctrl_reg_store( const csi_rx_backend_ID_t ID, const hrt_address reg, const hrt_data value); -/** end of DLI */ +/* end of DLI */ #endif /* USE_INPUT_SYSTEM_VERSION_2401 */ #endif /* __CSI_RX_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ibuf_ctrl_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ibuf_ctrl_public.h index 1ac0e64e539c..98ee9947fb8e 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ibuf_ctrl_public.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ibuf_ctrl_public.h @@ -54,7 +54,7 @@ STORAGE_CLASS_IBUF_CTRL_H void ibuf_ctrl_get_proc_state( STORAGE_CLASS_IBUF_CTRL_H void ibuf_ctrl_dump_state( const ibuf_ctrl_ID_t ID, ibuf_ctrl_state_t *state); -/** end of NCI */ +/* end of NCI */ /***************************************************** * @@ -87,7 +87,7 @@ STORAGE_CLASS_IBUF_CTRL_H void ibuf_ctrl_reg_store( const ibuf_ctrl_ID_t ID, const hrt_address reg, const hrt_data value); -/** end of DLI */ +/* end of DLI */ #endif /* USE_INPUT_SYSTEM_VERSION_2401 */ #endif /* __IBUF_CTRL_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op1w.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op1w.h index a025ad562bd2..0d978e5911c0 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op1w.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op1w.h @@ -49,7 +49,7 @@ /* Arithmetic */ -/** @brief bitwise AND +/* @brief bitwise AND * * @param[in] _a first argument * @param[in] _b second argument @@ -63,7 +63,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_and( const tvector1w _a, const tvector1w _b); -/** @brief bitwise OR +/* @brief bitwise OR * * @param[in] _a first argument * @param[in] _b second argument @@ -77,7 +77,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_or( const tvector1w _a, const tvector1w _b); -/** @brief bitwise XOR +/* @brief bitwise XOR * * @param[in] _a first argument * @param[in] _b second argument @@ -91,7 +91,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_xor( const tvector1w _a, const tvector1w _b); -/** @brief bitwise inverse +/* @brief bitwise inverse * * @param[in] _a first argument * @@ -105,7 +105,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_inv( /* Additive */ -/** @brief addition +/* @brief addition * * @param[in] _a first argument * @param[in] _b second argument @@ -120,7 +120,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_add( const tvector1w _a, const tvector1w _b); -/** @brief subtraction +/* @brief subtraction * * @param[in] _a first argument * @param[in] _b second argument @@ -135,7 +135,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_sub( const tvector1w _a, const tvector1w _b); -/** @brief saturated addition +/* @brief saturated addition * * @param[in] _a first argument * @param[in] _b second argument @@ -150,7 +150,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_addsat( const tvector1w _a, const tvector1w _b); -/** @brief saturated subtraction +/* @brief saturated subtraction * * @param[in] _a first argument * @param[in] _b second argument @@ -166,7 +166,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_subsat( const tvector1w _b); #ifdef ISP2401 -/** @brief Unsigned saturated subtraction +/* @brief Unsigned saturated subtraction * * @param[in] _a first argument * @param[in] _b second argument @@ -182,7 +182,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w_unsigned OP_1w_subsat_u( const tvector1w_unsigned _b); #endif -/** @brief subtraction with shift right and rounding +/* @brief subtraction with shift right and rounding * * @param[in] _a first argument * @param[in] _b second argument @@ -202,7 +202,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_subasr1( const tvector1w _a, const tvector1w _b); -/** @brief Subtraction with shift right and rounding +/* @brief Subtraction with shift right and rounding * * @param[in] _a first operand * @param[in] _b second operand @@ -217,7 +217,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_subhalfrnd( const tvector1w _a, const tvector1w _b); -/** @brief Subtraction with shift right and no rounding +/* @brief Subtraction with shift right and no rounding * * @param[in] _a first operand * @param[in] _b second operand @@ -233,7 +233,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_subhalf( const tvector1w _b); -/** @brief saturated absolute value +/* @brief saturated absolute value * * @param[in] _a input * @@ -247,7 +247,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_subhalf( STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_abs( const tvector1w _a); -/** @brief saturated absolute difference +/* @brief saturated absolute difference * * @param[in] _a first argument * @param[in] _b second argument @@ -264,7 +264,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_subabssat( /* Multiplicative */ -/** @brief doubling multiply +/* @brief doubling multiply * * @param[in] _a first argument * @param[in] _b second argument @@ -281,7 +281,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector2w OP_1w_muld( const tvector1w _a, const tvector1w _b); -/** @brief integer multiply +/* @brief integer multiply * * @param[in] _a first argument * @param[in] _b second argument @@ -298,7 +298,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_mul( const tvector1w _a, const tvector1w _b); -/** @brief fractional saturating multiply +/* @brief fractional saturating multiply * * @param[in] _a first argument * @param[in] _b second argument @@ -316,7 +316,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_qmul( const tvector1w _a, const tvector1w _b); -/** @brief fractional saturating multiply with rounding +/* @brief fractional saturating multiply with rounding * * @param[in] _a first argument * @param[in] _b second argument @@ -337,7 +337,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_qrmul( /* Comparative */ -/** @brief equal +/* @brief equal * * @param[in] _a first argument * @param[in] _b second argument @@ -351,7 +351,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tflags OP_1w_eq( const tvector1w _a, const tvector1w _b); -/** @brief not equal +/* @brief not equal * * @param[in] _a first argument * @param[in] _b second argument @@ -365,7 +365,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tflags OP_1w_ne( const tvector1w _a, const tvector1w _b); -/** @brief less or equal +/* @brief less or equal * * @param[in] _a first argument * @param[in] _b second argument @@ -379,7 +379,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tflags OP_1w_le( const tvector1w _a, const tvector1w _b); -/** @brief less then +/* @brief less then * * @param[in] _a first argument * @param[in] _b second argument @@ -393,7 +393,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tflags OP_1w_lt( const tvector1w _a, const tvector1w _b); -/** @brief greater or equal +/* @brief greater or equal * * @param[in] _a first argument * @param[in] _b second argument @@ -407,7 +407,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tflags OP_1w_ge( const tvector1w _a, const tvector1w _b); -/** @brief greater than +/* @brief greater than * * @param[in] _a first argument * @param[in] _b second argument @@ -423,7 +423,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tflags OP_1w_gt( /* Shift */ -/** @brief aritmetic shift right +/* @brief aritmetic shift right * * @param[in] _a input * @param[in] _b shift amount @@ -441,7 +441,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_asr( const tvector1w _a, const tvector1w _b); -/** @brief aritmetic shift right with rounding +/* @brief aritmetic shift right with rounding * * @param[in] _a input * @param[in] _b shift amount @@ -460,7 +460,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_asrrnd( const tvector1w _a, const tvector1w _b); -/** @brief saturating arithmetic shift left +/* @brief saturating arithmetic shift left * * @param[in] _a input * @param[in] _b shift amount @@ -480,7 +480,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_asl( const tvector1w _a, const tvector1w _b); -/** @brief saturating aritmetic shift left +/* @brief saturating aritmetic shift left * * @param[in] _a input * @param[in] _b shift amount @@ -493,7 +493,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_aslsat( const tvector1w _a, const tvector1w _b); -/** @brief logical shift left +/* @brief logical shift left * * @param[in] _a input * @param[in] _b shift amount @@ -510,7 +510,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_lsl( const tvector1w _a, const tvector1w _b); -/** @brief logical shift right +/* @brief logical shift right * * @param[in] _a input * @param[in] _b shift amount @@ -528,7 +528,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_lsr( const tvector1w _b); #ifdef ISP2401 -/** @brief bidirectional saturating arithmetic shift +/* @brief bidirectional saturating arithmetic shift * * @param[in] _a input * @param[in] _b shift amount @@ -546,7 +546,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_ashift_sat( const tvector1w _a, const tvector1w _b); -/** @brief bidirectional non-saturating arithmetic shift +/* @brief bidirectional non-saturating arithmetic shift * * @param[in] _a input * @param[in] _b shift amount @@ -565,7 +565,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_ashift( const tvector1w _b); -/** @brief bidirectional logical shift +/* @brief bidirectional logical shift * * @param[in] _a input * @param[in] _b shift amount @@ -588,7 +588,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_lshift( #endif /* Cast */ -/** @brief Cast from int to 1w +/* @brief Cast from int to 1w * * @param[in] _a input * @@ -601,7 +601,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_lshift( STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_int_cast_to_1w( const int _a); -/** @brief Cast from 1w to int +/* @brief Cast from 1w to int * * @param[in] _a input * @@ -614,7 +614,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_int_cast_to_1w( STORAGE_CLASS_ISP_OP1W_FUNC_H int OP_1w_cast_to_int( const tvector1w _a); -/** @brief Cast from 1w to 2w +/* @brief Cast from 1w to 2w * * @param[in] _a input * @@ -627,7 +627,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H int OP_1w_cast_to_int( STORAGE_CLASS_ISP_OP1W_FUNC_H tvector2w OP_1w_cast_to_2w( const tvector1w _a); -/** @brief Cast from 2w to 1w +/* @brief Cast from 2w to 1w * * @param[in] _a input * @@ -641,7 +641,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_2w_cast_to_1w( const tvector2w _a); -/** @brief Cast from 2w to 1w with saturation +/* @brief Cast from 2w to 1w with saturation * * @param[in] _a input * @@ -657,7 +657,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_2w_sat_cast_to_1w( /* clipping */ -/** @brief Clip asymmetrical +/* @brief Clip asymmetrical * * @param[in] _a first argument * @param[in] _b second argument @@ -673,7 +673,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_clip_asym( const tvector1w _a, const tvector1w _b); -/** @brief Clip zero +/* @brief Clip zero * * @param[in] _a first argument * @param[in] _b second argument @@ -691,7 +691,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_clipz( /* division */ -/** @brief Truncated division +/* @brief Truncated division * * @param[in] _a first argument * @param[in] _b second argument @@ -708,7 +708,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_div( const tvector1w _a, const tvector1w _b); -/** @brief Fractional saturating divide +/* @brief Fractional saturating divide * * @param[in] _a first argument * @param[in] _b second argument @@ -726,7 +726,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_qdiv( const tvector1w _a, const tvector1w _b); -/** @brief Modulo +/* @brief Modulo * * @param[in] _a first argument * @param[in] _b second argument @@ -741,7 +741,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_mod( const tvector1w _a, const tvector1w _b); -/** @brief Unsigned integer Square root +/* @brief Unsigned integer Square root * * @param[in] _a input * @@ -754,7 +754,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w_unsigned OP_1w_sqrt_u( /* Miscellaneous */ -/** @brief Multiplexer +/* @brief Multiplexer * * @param[in] _a first argument * @param[in] _b second argument @@ -770,7 +770,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_mux( const tvector1w _b, const tflags _c); -/** @brief Average without rounding +/* @brief Average without rounding * * @param[in] _a first operand * @param[in] _b second operand @@ -786,7 +786,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_avg( const tvector1w _a, const tvector1w _b); -/** @brief Average with rounding +/* @brief Average with rounding * * @param[in] _a first argument * @param[in] _b second argument @@ -802,7 +802,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_avgrnd( const tvector1w _a, const tvector1w _b); -/** @brief Minimum +/* @brief Minimum * * @param[in] _a first argument * @param[in] _b second argument @@ -816,7 +816,7 @@ STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_min( const tvector1w _a, const tvector1w _b); -/** @brief Maximum +/* @brief Maximum * * @param[in] _a first argument * @param[in] _b second argument diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op2w.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op2w.h index cf7e7314842d..7575d260b837 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op2w.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op2w.h @@ -48,7 +48,7 @@ /* Arithmetic */ -/** @brief bitwise AND +/* @brief bitwise AND * * @param[in] _a first argument * @param[in] _b second argument @@ -62,7 +62,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_and( const tvector2w _a, const tvector2w _b); -/** @brief bitwise OR +/* @brief bitwise OR * * @param[in] _a first argument * @param[in] _b second argument @@ -76,7 +76,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_or( const tvector2w _a, const tvector2w _b); -/** @brief bitwise XOR +/* @brief bitwise XOR * * @param[in] _a first argument * @param[in] _b second argument @@ -90,7 +90,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_xor( const tvector2w _a, const tvector2w _b); -/** @brief bitwise inverse +/* @brief bitwise inverse * * @param[in] _a first argument * @@ -104,7 +104,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_inv( /* Additive */ -/** @brief addition +/* @brief addition * * @param[in] _a first argument * @param[in] _b second argument @@ -119,7 +119,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_add( const tvector2w _a, const tvector2w _b); -/** @brief subtraction +/* @brief subtraction * * @param[in] _a first argument * @param[in] _b second argument @@ -134,7 +134,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_sub( const tvector2w _a, const tvector2w _b); -/** @brief saturated addition +/* @brief saturated addition * * @param[in] _a first argument * @param[in] _b second argument @@ -149,7 +149,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_addsat( const tvector2w _a, const tvector2w _b); -/** @brief saturated subtraction +/* @brief saturated subtraction * * @param[in] _a first argument * @param[in] _b second argument @@ -164,7 +164,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_subsat( const tvector2w _a, const tvector2w _b); -/** @brief subtraction with shift right and rounding +/* @brief subtraction with shift right and rounding * * @param[in] _a first argument * @param[in] _b second argument @@ -184,7 +184,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_subasr1( const tvector2w _a, const tvector2w _b); -/** @brief Subtraction with shift right and rounding +/* @brief Subtraction with shift right and rounding * * @param[in] _a first operand * @param[in] _b second operand @@ -199,7 +199,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_subhalfrnd( const tvector2w _a, const tvector2w _b); -/** @brief Subtraction with shift right and no rounding +/* @brief Subtraction with shift right and no rounding * * @param[in] _a first operand * @param[in] _b second operand @@ -214,7 +214,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_subhalf( const tvector2w _a, const tvector2w _b); -/** @brief saturated absolute value +/* @brief saturated absolute value * * @param[in] _a input * @@ -228,7 +228,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_subhalf( STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_abs( const tvector2w _a); -/** @brief saturated absolute difference +/* @brief saturated absolute difference * * @param[in] _a first argument * @param[in] _b second argument @@ -245,7 +245,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_subabssat( /* Multiplicative */ -/** @brief integer multiply +/* @brief integer multiply * * @param[in] _a first argument * @param[in] _b second argument @@ -262,7 +262,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_mul( const tvector2w _a, const tvector2w _b); -/** @brief fractional saturating multiply +/* @brief fractional saturating multiply * * @param[in] _a first argument * @param[in] _b second argument @@ -279,7 +279,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_qmul( const tvector2w _a, const tvector2w _b); -/** @brief fractional saturating multiply with rounding +/* @brief fractional saturating multiply with rounding * * @param[in] _a first argument * @param[in] _b second argument @@ -301,7 +301,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_qrmul( /* Comparative */ -/** @brief equal +/* @brief equal * * @param[in] _a first argument * @param[in] _b second argument @@ -315,7 +315,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tflags OP_2w_eq( const tvector2w _a, const tvector2w _b); -/** @brief not equal +/* @brief not equal * * @param[in] _a first argument * @param[in] _b second argument @@ -329,7 +329,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tflags OP_2w_ne( const tvector2w _a, const tvector2w _b); -/** @brief less or equal +/* @brief less or equal * * @param[in] _a first argument * @param[in] _b second argument @@ -343,7 +343,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tflags OP_2w_le( const tvector2w _a, const tvector2w _b); -/** @brief less then +/* @brief less then * * @param[in] _a first argument * @param[in] _b second argument @@ -357,7 +357,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tflags OP_2w_lt( const tvector2w _a, const tvector2w _b); -/** @brief greater or equal +/* @brief greater or equal * * @param[in] _a first argument * @param[in] _b second argument @@ -371,7 +371,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tflags OP_2w_ge( const tvector2w _a, const tvector2w _b); -/** @brief greater than +/* @brief greater than * * @param[in] _a first argument * @param[in] _b second argument @@ -387,7 +387,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tflags OP_2w_gt( /* Shift */ -/** @brief aritmetic shift right +/* @brief aritmetic shift right * * @param[in] _a input * @param[in] _b shift amount @@ -404,7 +404,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_asr( const tvector2w _a, const tvector2w _b); -/** @brief aritmetic shift right with rounding +/* @brief aritmetic shift right with rounding * * @param[in] _a input * @param[in] _b shift amount @@ -423,7 +423,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_asrrnd( const tvector2w _a, const tvector2w _b); -/** @brief saturating aritmetic shift left +/* @brief saturating aritmetic shift left * * @param[in] _a input * @param[in] _b shift amount @@ -443,7 +443,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_asl( const tvector2w _a, const tvector2w _b); -/** @brief saturating aritmetic shift left +/* @brief saturating aritmetic shift left * * @param[in] _a input * @param[in] _b shift amount @@ -456,7 +456,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_aslsat( const tvector2w _a, const tvector2w _b); -/** @brief logical shift left +/* @brief logical shift left * * @param[in] _a input * @param[in] _b shift amount @@ -473,7 +473,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_lsl( const tvector2w _a, const tvector2w _b); -/** @brief logical shift right +/* @brief logical shift right * * @param[in] _a input * @param[in] _b shift amount @@ -492,7 +492,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_lsr( /* clipping */ -/** @brief Clip asymmetrical +/* @brief Clip asymmetrical * * @param[in] _a first argument * @param[in] _b second argument @@ -507,7 +507,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_clip_asym( const tvector2w _a, const tvector2w _b); -/** @brief Clip zero +/* @brief Clip zero * * @param[in] _a first argument * @param[in] _b second argument @@ -524,7 +524,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_clipz( /* division */ -/** @brief Truncated division +/* @brief Truncated division * * @param[in] _a first argument * @param[in] _b second argument @@ -541,7 +541,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_div( const tvector2w _a, const tvector2w _b); -/** @brief Saturating truncated division +/* @brief Saturating truncated division * * @param[in] _a first argument * @param[in] _b second argument @@ -559,7 +559,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector1w OP_2w_divh( const tvector2w _a, const tvector1w _b); -/** @brief Modulo +/* @brief Modulo * * @param[in] _a first argument * @param[in] _b second argument @@ -572,7 +572,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_mod( const tvector2w _a, const tvector2w _b); -/** @brief Unsigned Integer Square root +/* @brief Unsigned Integer Square root * * @param[in] _a input * @@ -585,7 +585,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector1w_unsigned OP_2w_sqrt_u( /* Miscellaneous */ -/** @brief Multiplexer +/* @brief Multiplexer * * @param[in] _a first argument * @param[in] _b second argument @@ -601,7 +601,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_mux( const tvector2w _b, const tflags _c); -/** @brief Average without rounding +/* @brief Average without rounding * * @param[in] _a first operand * @param[in] _b second operand @@ -617,7 +617,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_avg( const tvector2w _a, const tvector2w _b); -/** @brief Average with rounding +/* @brief Average with rounding * * @param[in] _a first argument * @param[in] _b second argument @@ -633,7 +633,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_avgrnd( const tvector2w _a, const tvector2w _b); -/** @brief Minimum +/* @brief Minimum * * @param[in] _a first argument * @param[in] _b second argument @@ -647,7 +647,7 @@ STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_min( const tvector2w _a, const tvector2w _b); -/** @brief Maximum +/* @brief Maximum * * @param[in] _a first argument * @param[in] _b second argument diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isys_stream2mmio_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isys_stream2mmio_public.h index 5624cfcfa015..6c53ca9df96c 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isys_stream2mmio_public.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isys_stream2mmio_public.h @@ -43,7 +43,7 @@ STORAGE_CLASS_STREAM2MMIO_H void stream2mmio_get_sid_state( const stream2mmio_ID_t ID, const stream2mmio_sid_ID_t sid_id, stream2mmio_sid_state_t *state); -/** end of NCI */ +/* end of NCI */ /***************************************************** * @@ -96,6 +96,6 @@ STORAGE_CLASS_STREAM2MMIO_H void stream2mmio_reg_store( const stream2mmio_ID_t ID, const hrt_address reg, const hrt_data value); -/** end of DLI */ +/* end of DLI */ #endif /* __ISYS_STREAM2MMIO_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/pixelgen_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/pixelgen_public.h index c0f3f3ea32d7..f597e07d7c4f 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/pixelgen_public.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/pixelgen_public.h @@ -41,7 +41,7 @@ STORAGE_CLASS_PIXELGEN_H void pixelgen_ctrl_get_state( STORAGE_CLASS_PIXELGEN_H void pixelgen_ctrl_dump_state( const pixelgen_ID_t ID, pixelgen_ctrl_state_t *state); -/** end of NCI */ +/* end of NCI */ /***************************************************** * @@ -73,7 +73,7 @@ STORAGE_CLASS_PIXELGEN_H void pixelgen_ctrl_reg_store( const pixelgen_ID_t ID, const hrt_address reg, const hrt_data value); -/** end of DLI */ +/* end of DLI */ #endif /* USE_INPUT_SYSTEM_VERSION_2401 */ #endif /* __PIXELGEN_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ref_vector_func.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ref_vector_func.h index a202d6dce106..c1638c06407d 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ref_vector_func.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ref_vector_func.h @@ -27,7 +27,7 @@ #include "ref_vector_func_types.h" -/** @brief Doubling multiply accumulate with saturation +/* @brief Doubling multiply accumulate with saturation * * @param[in] acc accumulator * @param[in] a multiply input @@ -44,7 +44,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector2w OP_1w_maccd_sat( tvector1w a, tvector1w b ); -/** @brief Doubling multiply accumulate +/* @brief Doubling multiply accumulate * * @param[in] acc accumulator * @param[in] a multiply input @@ -61,7 +61,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector2w OP_1w_maccd( tvector1w a, tvector1w b ); -/** @brief Re-aligning multiply +/* @brief Re-aligning multiply * * @param[in] a multiply input * @param[in] b multiply input @@ -78,7 +78,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_mul_realigning( tvector1w b, tscalar1w shift ); -/** @brief Leading bit index +/* @brief Leading bit index * * @param[in] a input * @@ -92,7 +92,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_mul_realigning( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_lod( tvector1w a); -/** @brief Config Unit Input Processing +/* @brief Config Unit Input Processing * * @param[in] a input * @param[in] input_scale input scaling factor @@ -111,7 +111,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_input_scaling_offset_clamping( tscalar1w_5bit_signed input_scale, tscalar1w_5bit_signed input_offset); -/** @brief Config Unit Output Processing +/* @brief Config Unit Output Processing * * @param[in] a output * @param[in] output_scale output scaling factor @@ -127,7 +127,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_output_scaling_clamping( tvector1w a, tscalar1w_5bit_signed output_scale); -/** @brief Config Unit Piecewiselinear estimation +/* @brief Config Unit Piecewiselinear estimation * * @param[in] a input * @param[in] config_points config parameter structure @@ -143,7 +143,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_piecewise_estimation( tvector1w a, ref_config_points config_points); -/** @brief Fast Config Unit +/* @brief Fast Config Unit * * @param[in] x input * @param[in] init_vectors LUT data structure @@ -161,7 +161,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_XCU( xcu_ref_init_vectors init_vectors); -/** @brief LXCU +/* @brief LXCU * * @param[in] x input * @param[in] init_vectors LUT data structure @@ -180,7 +180,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_LXCU( tvector1w x, xcu_ref_init_vectors init_vectors); -/** @brief Coring +/* @brief Coring * * @param[in] coring_vec Amount of coring based on brightness level * @param[in] filt_input Vector of input pixels on which Coring is applied @@ -196,7 +196,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w coring( tvector1w filt_input, tscalar1w m_CnrCoring0 ); -/** @brief Normalised FIR with coefficients [3,4,1] +/* @brief Normalised FIR with coefficients [3,4,1] * * @param[in] m 1x3 matrix with pixels * @@ -209,7 +209,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w coring( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_5dB_m90_nrm ( const s_1w_1x3_matrix m); -/** @brief Normalised FIR with coefficients [1,4,3] +/* @brief Normalised FIR with coefficients [1,4,3] * * @param[in] m 1x3 matrix with pixels * @@ -222,7 +222,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_5dB_m90_nrm ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_5dB_p90_nrm ( const s_1w_1x3_matrix m); -/** @brief Normalised FIR with coefficients [1,2,1] +/* @brief Normalised FIR with coefficients [1,2,1] * * @param[in] m 1x3 matrix with pixels * @@ -234,7 +234,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_5dB_p90_nrm ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm ( const s_1w_1x3_matrix m); -/** @brief Normalised FIR with coefficients [13,16,3] +/* @brief Normalised FIR with coefficients [13,16,3] * * @param[in] m 1x3 matrix with pixels * @@ -246,7 +246,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_ph0 ( const s_1w_1x3_matrix m); -/** @brief Normalised FIR with coefficients [9,16,7] +/* @brief Normalised FIR with coefficients [9,16,7] * * @param[in] m 1x3 matrix with pixels * @@ -258,7 +258,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_ph0 ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_ph1 ( const s_1w_1x3_matrix m); -/** @brief Normalised FIR with coefficients [5,16,11] +/* @brief Normalised FIR with coefficients [5,16,11] * * @param[in] m 1x3 matrix with pixels * @@ -270,7 +270,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_ph1 ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_ph2 ( const s_1w_1x3_matrix m); -/** @brief Normalised FIR with coefficients [1,16,15] +/* @brief Normalised FIR with coefficients [1,16,15] * * @param[in] m 1x3 matrix with pixels * @@ -282,7 +282,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_ph2 ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_ph3 ( const s_1w_1x3_matrix m); -/** @brief Normalised FIR with programable phase shift +/* @brief Normalised FIR with programable phase shift * * @param[in] m 1x3 matrix with pixels * @param[in] coeff phase shift @@ -295,7 +295,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_ph3 ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_calc_coeff ( const s_1w_1x3_matrix m, tscalar1w_3bit coeff); -/** @brief 3 tap FIR with coefficients [1,1,1] +/* @brief 3 tap FIR with coefficients [1,1,1] * * @param[in] m 1x3 matrix with pixels * @@ -308,7 +308,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_9dB_nrm ( const s_1w_1x3_matrix m); #ifdef ISP2401 -/** @brief symmetric 3 tap FIR acts as LPF or BSF +/* @brief symmetric 3 tap FIR acts as LPF or BSF * * @param[in] m 1x3 matrix with pixels * @param[in] k filter coefficient shift @@ -336,7 +336,7 @@ sym_fir1x3m_lpf_bsf(s_1w_1x3_matrix m, tscalar_bool bsf_flag); #endif -/** @brief Normalised 2D FIR with coefficients [1;2;1] * [1,2,1] +/* @brief Normalised 2D FIR with coefficients [1;2;1] * [1,2,1] * * @param[in] m 3x3 matrix with pixels * @@ -353,7 +353,7 @@ sym_fir1x3m_lpf_bsf(s_1w_1x3_matrix m, STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir3x3m_6dB_nrm ( const s_1w_3x3_matrix m); -/** @brief Normalised 2D FIR with coefficients [1;1;1] * [1,1,1] +/* @brief Normalised 2D FIR with coefficients [1;1;1] * [1,1,1] * * @param[in] m 3x3 matrix with pixels * @@ -371,7 +371,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir3x3m_6dB_nrm ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir3x3m_9dB_nrm ( const s_1w_3x3_matrix m); -/** @brief Normalised dual output 2D FIR with coefficients [1;2;1] * [1,2,1] +/* @brief Normalised dual output 2D FIR with coefficients [1;2;1] * [1,2,1] * * @param[in] m 4x3 matrix with pixels * @@ -391,7 +391,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir3x3m_9dB_nrm ( STORAGE_CLASS_REF_VECTOR_FUNC_H s_1w_2x1_matrix fir3x3m_6dB_out2x1_nrm ( const s_1w_4x3_matrix m); -/** @brief Normalised dual output 2D FIR with coefficients [1;1;1] * [1,1,1] +/* @brief Normalised dual output 2D FIR with coefficients [1;1;1] * [1,1,1] * * @param[in] m 4x3 matrix with pixels * @@ -411,7 +411,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir3x3m_9dB_nrm ( STORAGE_CLASS_REF_VECTOR_FUNC_H s_1w_2x1_matrix fir3x3m_9dB_out2x1_nrm ( const s_1w_4x3_matrix m); -/** @brief Normalised 2D FIR 5x5 +/* @brief Normalised 2D FIR 5x5 * * @param[in] m 5x5 matrix with pixels * @@ -429,7 +429,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H s_1w_2x1_matrix fir3x3m_9dB_out2x1_nrm ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir5x5m_15dB_nrm ( const s_1w_5x5_matrix m); -/** @brief Normalised FIR 1x5 +/* @brief Normalised FIR 1x5 * * @param[in] m 1x5 matrix with pixels * @@ -447,7 +447,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir5x5m_15dB_nrm ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x5m_12dB_nrm ( const s_1w_1x5_matrix m); -/** @brief Normalised 2D FIR 5x5 +/* @brief Normalised 2D FIR 5x5 * * @param[in] m 5x5 matrix with pixels * @@ -465,7 +465,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x5m_12dB_nrm ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir5x5m_12dB_nrm ( const s_1w_5x5_matrix m); -/** @brief Approximate averaging FIR 1x5 +/* @brief Approximate averaging FIR 1x5 * * @param[in] m 1x5 matrix with pixels * @@ -479,7 +479,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir5x5m_12dB_nrm ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x5m_box ( s_1w_1x5_matrix m); -/** @brief Approximate averaging FIR 1x9 +/* @brief Approximate averaging FIR 1x9 * * @param[in] m 1x9 matrix with pixels * @@ -493,7 +493,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x5m_box ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x9m_box ( s_1w_1x9_matrix m); -/** @brief Approximate averaging FIR 1x11 +/* @brief Approximate averaging FIR 1x11 * * @param[in] m 1x11 matrix with pixels * @@ -507,7 +507,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x9m_box ( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x11m_box ( s_1w_1x11_matrix m); -/** @brief Symmetric 7 tap filter with normalization +/* @brief Symmetric 7 tap filter with normalization * * @param[in] in 1x7 matrix with pixels * @param[in] coeff 1x4 matrix with coefficients @@ -528,7 +528,7 @@ fir1x7m_sym_nrm(s_1w_1x7_matrix in, s_1w_1x4_matrix coeff, tvector1w out_shift); -/** @brief Symmetric 7 tap filter with normalization at input side +/* @brief Symmetric 7 tap filter with normalization at input side * * @param[in] in 1x7 matrix with pixels * @param[in] coeff 1x4 matrix with coefficients @@ -549,7 +549,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x7m_sym_innrm_approx(s_1w_1x7_matrix in, s_1w_1x4_matrix coeff); -/** @brief Symmetric 7 tap filter with normalization at output side +/* @brief Symmetric 7 tap filter with normalization at output side * * @param[in] in 1x7 matrix with pixels * @param[in] coeff 1x4 matrix with coefficients @@ -571,7 +571,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x7m_sym_outnrm_approx(s_1w_1x7_matrix in, s_1w_1x4_matrix coeff); -/** @brief 4 tap filter with normalization +/* @brief 4 tap filter with normalization * * @param[in] in 1x4 matrix with pixels * @param[in] coeff 1x4 matrix with coefficients @@ -588,7 +588,7 @@ fir1x4m_nrm(s_1w_1x4_matrix in, s_1w_1x4_matrix coeff, tvector1w out_shift); -/** @brief 4 tap filter with normalization for half pixel interpolation +/* @brief 4 tap filter with normalization for half pixel interpolation * * @param[in] in 1x4 matrix with pixels * @@ -604,7 +604,7 @@ fir1x4m_nrm(s_1w_1x4_matrix in, STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x4m_bicubic_bezier_half(s_1w_1x4_matrix in); -/** @brief 4 tap filter with normalization for quarter pixel interpolation +/* @brief 4 tap filter with normalization for quarter pixel interpolation * * @param[in] in 1x4 matrix with pixels * @param[in] coeff 1x4 matrix with coefficients @@ -626,7 +626,7 @@ fir1x4m_bicubic_bezier_quarter(s_1w_1x4_matrix in, s_1w_1x4_matrix coeff); -/** @brief Symmetric 3 tap filter with normalization +/* @brief Symmetric 3 tap filter with normalization * * @param[in] in 1x3 matrix with pixels * @param[in] coeff 1x2 matrix with coefficients @@ -646,7 +646,7 @@ fir1x3m_sym_nrm(s_1w_1x3_matrix in, s_1w_1x2_matrix coeff, tvector1w out_shift); -/** @brief Symmetric 3 tap filter with normalization +/* @brief Symmetric 3 tap filter with normalization * * @param[in] in 1x3 matrix with pixels * @param[in] coeff 1x2 matrix with coefficients @@ -666,7 +666,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_sym_nrm_approx(s_1w_1x3_matrix in, s_1w_1x2_matrix coeff); -/** @brief Mean of 1x3 matrix +/* @brief Mean of 1x3 matrix * * @param[in] m 1x3 matrix with pixels * @@ -678,7 +678,7 @@ fir1x3m_sym_nrm_approx(s_1w_1x3_matrix in, STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean1x3m( s_1w_1x3_matrix m); -/** @brief Mean of 3x3 matrix +/* @brief Mean of 3x3 matrix * * @param[in] m 3x3 matrix with pixels * @@ -690,7 +690,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean1x3m( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean3x3m( s_1w_3x3_matrix m); -/** @brief Mean of 1x4 matrix +/* @brief Mean of 1x4 matrix * * @param[in] m 1x4 matrix with pixels * @@ -701,7 +701,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean3x3m( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean1x4m( s_1w_1x4_matrix m); -/** @brief Mean of 4x4 matrix +/* @brief Mean of 4x4 matrix * * @param[in] m 4x4 matrix with pixels * @@ -712,7 +712,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean1x4m( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean4x4m( s_1w_4x4_matrix m); -/** @brief Mean of 2x3 matrix +/* @brief Mean of 2x3 matrix * * @param[in] m 2x3 matrix with pixels * @@ -724,7 +724,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean4x4m( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean2x3m( s_1w_2x3_matrix m); -/** @brief Mean of 1x5 matrix +/* @brief Mean of 1x5 matrix * * @param[in] m 1x5 matrix with pixels * @@ -735,7 +735,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean2x3m( */ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean1x5m(s_1w_1x5_matrix m); -/** @brief Mean of 1x6 matrix +/* @brief Mean of 1x6 matrix * * @param[in] m 1x6 matrix with pixels * @@ -747,7 +747,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean1x5m(s_1w_1x5_matrix m); STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean1x6m( s_1w_1x6_matrix m); -/** @brief Mean of 5x5 matrix +/* @brief Mean of 5x5 matrix * * @param[in] m 5x5 matrix with pixels * @@ -759,7 +759,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean1x6m( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean5x5m( s_1w_5x5_matrix m); -/** @brief Mean of 6x6 matrix +/* @brief Mean of 6x6 matrix * * @param[in] m 6x6 matrix with pixels * @@ -771,7 +771,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean5x5m( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean6x6m( s_1w_6x6_matrix m); -/** @brief Minimum of 4x4 matrix +/* @brief Minimum of 4x4 matrix * * @param[in] m 4x4 matrix with pixels * @@ -783,7 +783,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean6x6m( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w min4x4m( s_1w_4x4_matrix m); -/** @brief Maximum of 4x4 matrix +/* @brief Maximum of 4x4 matrix * * @param[in] m 4x4 matrix with pixels * @@ -795,7 +795,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w min4x4m( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w max4x4m( s_1w_4x4_matrix m); -/** @brief SAD between two 3x3 matrices +/* @brief SAD between two 3x3 matrices * * @param[in] a 3x3 matrix with pixels * @@ -813,7 +813,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w sad3x3m_precise( s_1w_3x3_matrix a, s_1w_3x3_matrix b); -/** @brief SAD between two 3x3 matrices +/* @brief SAD between two 3x3 matrices * * @param[in] a 3x3 matrix with pixels * @@ -833,7 +833,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w sad3x3m( s_1w_3x3_matrix a, s_1w_3x3_matrix b); -/** @brief SAD between two 5x5 matrices +/* @brief SAD between two 5x5 matrices * * @param[in] a 5x5 matrix with pixels * @@ -847,7 +847,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w sad5x5m( s_1w_5x5_matrix a, s_1w_5x5_matrix b); -/** @brief Absolute gradient between two sets of 1x5 matrices +/* @brief Absolute gradient between two sets of 1x5 matrices * * @param[in] m0 first set of 1x5 matrix with pixels * @param[in] m1 second set of 1x5 matrix with pixels @@ -860,7 +860,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w sad5x5m( STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w absgrad1x5m(s_1w_1x5_matrix m0, s_1w_1x5_matrix m1); -/** @brief Bi-linear Interpolation optimized(approximate) +/* @brief Bi-linear Interpolation optimized(approximate) * * @param[in] a input0 * @param[in] b input1 @@ -882,7 +882,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_bilinear_interpol_approx_c( tvector1w b, tscalar1w_weight c); -/** @brief Bi-linear Interpolation optimized(approximate) +/* @brief Bi-linear Interpolation optimized(approximate) * * @param[in] a input0 * @param[in] b input1 @@ -904,7 +904,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_bilinear_interpol_approx( tvector1w b, tvector1w_weight c); -/** @brief Bi-linear Interpolation +/* @brief Bi-linear Interpolation * * @param[in] a input0 * @param[in] b input1 @@ -925,7 +925,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_bilinear_interpol( tvector1w b, tscalar1w_weight c); -/** @brief Generic Block Matching Algorithm +/* @brief Generic Block Matching Algorithm * @param[in] search_window pointer to input search window of 16x16 pixels * @param[in] ref_block pointer to input reference block of 8x8 pixels, where N<=M * @param[in] output pointer to output sads @@ -954,9 +954,9 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H int generic_block_matching_algorithm( tscalar1w_4bit_bma_shift shift); #ifndef ISP2401 -/** @brief OP_1w_asp_bma_16_1_32way +/* @brief OP_1w_asp_bma_16_1_32way #else -/** @brief OP_1w_asp_bma_16_1_32way_nomask +/* @brief OP_1w_asp_bma_16_1_32way_nomask #endif * * @param[in] search_area input search window of 16x16 pixels @@ -984,9 +984,9 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H bma_output_16_1 OP_1w_asp_bma_16_1_32way_nomask( tscalar1w_4bit_bma_shift shift); #ifndef ISP2401 -/** @brief OP_1w_asp_bma_16_2_32way +/* @brief OP_1w_asp_bma_16_2_32way #else -/** @brief OP_1w_asp_bma_16_2_32way_nomask +/* @brief OP_1w_asp_bma_16_2_32way_nomask #endif * * @param[in] search_area input search window of 16x16 pixels @@ -1011,9 +1011,9 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H bma_output_16_2 OP_1w_asp_bma_16_2_32way_nomask( ref_block_8x8 input_block, tscalar1w_4bit_bma_shift shift); #ifndef ISP2401 -/** @brief OP_1w_asp_bma_14_1_32way +/* @brief OP_1w_asp_bma_14_1_32way #else -/** @brief OP_1w_asp_bma_14_1_32way_nomask +/* @brief OP_1w_asp_bma_14_1_32way_nomask #endif * * @param[in] search_area input search block of 16x16 pixels with search window of 14x14 pixels @@ -1041,9 +1041,9 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H bma_output_14_1 OP_1w_asp_bma_14_1_32way_nomask( tscalar1w_4bit_bma_shift shift); #ifndef ISP2401 -/** @brief OP_1w_asp_bma_14_2_32way +/* @brief OP_1w_asp_bma_14_2_32way #else -/** @brief OP_1w_asp_bma_14_2_32way_nomask +/* @brief OP_1w_asp_bma_14_2_32way_nomask #endif * * @param[in] search_area input search block of 16x16 pixels with search window of 14x14 pixels @@ -1069,7 +1069,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H bma_output_14_2 OP_1w_asp_bma_14_2_32way_nomask( tscalar1w_4bit_bma_shift shift); #ifdef ISP2401 -/** @brief multiplex addition and passing +/* @brief multiplex addition and passing * * @param[in] _a first pixel * @param[in] _b second pixel @@ -1087,7 +1087,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_cond_add( #endif #ifdef HAS_bfa_unit -/** @brief OP_1w_single_bfa_7x7 +/* @brief OP_1w_single_bfa_7x7 * * @param[in] weights - spatial and range weight lut * @param[in] threshold - threshold plane, for range weight scaling @@ -1115,7 +1115,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H bfa_7x7_output OP_1w_single_bfa_7x7( tvector1w central_pix, s_1w_7x7_matrix src_plane); -/** @brief OP_1w_joint_bfa_7x7 +/* @brief OP_1w_joint_bfa_7x7 * * @param[in] weights - spatial and range weight lut * @param[in] threshold0 - 1st threshold plane, for range weight scaling @@ -1149,7 +1149,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H bfa_7x7_output OP_1w_joint_bfa_7x7( tvector1w central_pix1, s_1w_7x7_matrix src1_plane); -/** @brief bbb_bfa_gen_spatial_weight_lut +/* @brief bbb_bfa_gen_spatial_weight_lut * * @param[in] in - 7x7 matrix of spatial weights * @param[in] out - generated LUT @@ -1163,7 +1163,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H void bbb_bfa_gen_spatial_weight_lut( s_1w_7x7_matrix in, tvector1w out[BFA_MAX_KWAY]); -/** @brief bbb_bfa_gen_range_weight_lut +/* @brief bbb_bfa_gen_range_weight_lut * * @param[in] in - input range weight, * @param[in] out - generated LUT @@ -1184,7 +1184,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H void bbb_bfa_gen_range_weight_lut( #endif #ifdef ISP2401 -/** @brief OP_1w_imax32 +/* @brief OP_1w_imax32 * * @param[in] src - structure that holds an array of 32 elements. * @@ -1195,7 +1195,7 @@ STORAGE_CLASS_REF_VECTOR_FUNC_H void bbb_bfa_gen_range_weight_lut( STORAGE_CLASS_REF_VECTOR_FUNC_H int OP_1w_imax32( imax32_ref_in_vector src); -/** @brief OP_1w_imaxidx32 +/* @brief OP_1w_imaxidx32 * * @param[in] src - structure that holds a vector of elements. * diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/math_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/math_support.h index e85e5c889c15..6436dae0007e 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/math_support.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/math_support.h @@ -168,7 +168,7 @@ static inline unsigned int round_half_down_mul(unsigned int a, unsigned int b) } #endif -/** @brief Next Power of Two +/* @brief Next Power of Two * * @param[in] unsigned number * diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/string_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/string_support.h index d80437c58bde..f4d9674cdab6 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/string_support.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/string_support.h @@ -23,7 +23,7 @@ */ -/** @brief Copy from src_buf to dest_buf. +/* @brief Copy from src_buf to dest_buf. * * @param[out] dest_buf. Destination buffer to copy to * @param[in] dest_size. The size of the destination buffer in bytes @@ -53,7 +53,7 @@ static inline int memcpy_s( return 0; } -/** @brief Get the length of the string, excluding the null terminator +/* @brief Get the length of the string, excluding the null terminator * * @param[in] src_str. The source string * @param[in] max_len. Look only for max_len bytes in the string @@ -78,7 +78,7 @@ static size_t strnlen_s( return ix; } -/** @brief Copy string from src_str to dest_str +/* @brief Copy string from src_str to dest_str * * @param[out] dest_str. Destination buffer to copy to * @param[in] dest_size. The size of the destination buffer in bytes @@ -120,7 +120,7 @@ static inline int strncpy_s( return 0; } -/** @brief Copy string from src_str to dest_str +/* @brief Copy string from src_str to dest_str * * @param[out] dest_str. Destination buffer to copy to * @param[in] dest_size. The size of the destination buffer in bytes diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag.c index 9aa8c168a803..2cf1d58941bf 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag.c @@ -17,7 +17,7 @@ #include #include "tag_local.h" -/** +/* * @brief Creates the tag description from the given parameters. * @param[in] num_captures * @param[in] skip @@ -39,7 +39,7 @@ sh_css_create_tag_descr(int num_captures, tag_descr->exp_id = exp_id; } -/** +/* * @brief Encodes the members of tag description into a 32-bit value. * @param[in] tag Pointer to the tag description * @return (unsigned int) Encoded 32-bit tag-info diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css.h index 2458b3767c90..e44df6916d90 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css.h @@ -16,7 +16,7 @@ #ifndef _IA_CSS_H_ #define _IA_CSS_H_ -/** @file +/* @file * This file is the starting point of the CSS-API. It includes all CSS-API * header files. */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_3a.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_3a.h index a80a7dbaf712..080198796ad0 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_3a.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_3a.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_3A_H #define __IA_CSS_3A_H -/** @file +/* @file * This file contains types used for 3A statistics */ @@ -31,7 +31,7 @@ enum ia_css_3a_tables { IA_CSS_NUM_3A_TABLES }; -/** Structure that holds 3A statistics in the ISP internal +/* Structure that holds 3A statistics in the ISP internal * format. Use ia_css_get_3a_statistics() to translate * this to the format used on the host (3A library). * */ @@ -48,13 +48,13 @@ struct ia_css_isp_3a_statistics { struct { ia_css_ptr rgby_tbl; } data_hmem; - uint32_t exp_id; /**< exposure id, to match statistics to a frame, + uint32_t exp_id; /** exposure id, to match statistics to a frame, see ia_css_event_public.h for more detail. */ - uint32_t isp_config_id;/**< Unique ID to track which config was actually applied to a particular frame */ - ia_css_ptr data_ptr; /**< pointer to base of all data */ - uint32_t size; /**< total size of all data */ + uint32_t isp_config_id;/** Unique ID to track which config was actually applied to a particular frame */ + ia_css_ptr data_ptr; /** pointer to base of all data */ + uint32_t size; /** total size of all data */ uint32_t dmem_size; - uint32_t vmem_size; /**< both lo and hi have this size */ + uint32_t vmem_size; /** both lo and hi have this size */ uint32_t hmem_size; }; #define SIZE_OF_DMEM_STRUCT \ @@ -77,7 +77,7 @@ struct ia_css_isp_3a_statistics { SIZE_OF_IA_CSS_PTR + \ 4 * sizeof(uint32_t)) -/** Map with host-side pointers to ISP-format statistics. +/* Map with host-side pointers to ISP-format statistics. * These pointers can either be copies of ISP data or memory mapped * ISP pointers. * All of the data behind these pointers is allocated contiguously, the @@ -85,17 +85,17 @@ struct ia_css_isp_3a_statistics { * point into this one block of data. */ struct ia_css_isp_3a_statistics_map { - void *data_ptr; /**< Pointer to start of memory */ + void *data_ptr; /** Pointer to start of memory */ struct ia_css_3a_output *dmem_stats; uint16_t *vmem_stats_hi; uint16_t *vmem_stats_lo; struct ia_css_bh_table *hmem_stats; - uint32_t size; /**< total size in bytes of data_ptr */ - uint32_t data_allocated; /**< indicate whether data_ptr + uint32_t size; /** total size in bytes of data_ptr */ + uint32_t data_allocated; /** indicate whether data_ptr was allocated or not. */ }; -/** @brief Copy and translate 3A statistics from an ISP buffer to a host buffer +/* @brief Copy and translate 3A statistics from an ISP buffer to a host buffer * @param[out] host_stats Host buffer. * @param[in] isp_stats ISP buffer. * @return error value if temporary memory cannot be allocated @@ -109,7 +109,7 @@ enum ia_css_err ia_css_get_3a_statistics(struct ia_css_3a_statistics *host_stats, const struct ia_css_isp_3a_statistics *isp_stats); -/** @brief Translate 3A statistics from ISP format to host format. +/* @brief Translate 3A statistics from ISP format to host format. * @param[out] host_stats host-format statistics * @param[in] isp_stats ISP-format statistics * @return None @@ -125,35 +125,35 @@ ia_css_translate_3a_statistics( /* Convenience functions for alloc/free of certain datatypes */ -/** @brief Allocate memory for the 3a statistics on the ISP +/* @brief Allocate memory for the 3a statistics on the ISP * @param[in] grid The grid. * @return Pointer to the allocated 3a statistics buffer on the ISP */ struct ia_css_isp_3a_statistics * ia_css_isp_3a_statistics_allocate(const struct ia_css_3a_grid_info *grid); -/** @brief Free the 3a statistics memory on the isp +/* @brief Free the 3a statistics memory on the isp * @param[in] me Pointer to the 3a statistics buffer on the ISP. * @return None */ void ia_css_isp_3a_statistics_free(struct ia_css_isp_3a_statistics *me); -/** @brief Allocate memory for the 3a statistics on the host +/* @brief Allocate memory for the 3a statistics on the host * @param[in] grid The grid. * @return Pointer to the allocated 3a statistics buffer on the host */ struct ia_css_3a_statistics * ia_css_3a_statistics_allocate(const struct ia_css_3a_grid_info *grid); -/** @brief Free the 3a statistics memory on the host +/* @brief Free the 3a statistics memory on the host * @param[in] me Pointer to the 3a statistics buffer on the host. * @return None */ void ia_css_3a_statistics_free(struct ia_css_3a_statistics *me); -/** @brief Allocate a 3a statistics map structure +/* @brief Allocate a 3a statistics map structure * @param[in] isp_stats pointer to ISP 3a statistis struct * @param[in] data_ptr host-side pointer to ISP 3a statistics. * @return Pointer to the allocated 3a statistics map @@ -174,7 +174,7 @@ ia_css_isp_3a_statistics_map_allocate( const struct ia_css_isp_3a_statistics *isp_stats, void *data_ptr); -/** @brief Free the 3a statistics map +/* @brief Free the 3a statistics map * @param[in] me Pointer to the 3a statistics map * @return None * diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_acc_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_acc_types.h index a2a1873aca83..138bc3bb4627 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_acc_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_acc_types.h @@ -15,7 +15,7 @@ #ifndef _IA_CSS_ACC_TYPES_H #define _IA_CSS_ACC_TYPES_H -/** @file +/* @file * This file contains types used for acceleration */ @@ -40,16 +40,16 @@ * in the kernel and HAL. */ -/** Type of acceleration. +/* Type of acceleration. */ enum ia_css_acc_type { - IA_CSS_ACC_NONE, /**< Normal binary */ - IA_CSS_ACC_OUTPUT, /**< Accelerator stage on output frame */ - IA_CSS_ACC_VIEWFINDER, /**< Accelerator stage on viewfinder frame */ - IA_CSS_ACC_STANDALONE, /**< Stand-alone acceleration */ + IA_CSS_ACC_NONE, /** Normal binary */ + IA_CSS_ACC_OUTPUT, /** Accelerator stage on output frame */ + IA_CSS_ACC_VIEWFINDER, /** Accelerator stage on viewfinder frame */ + IA_CSS_ACC_STANDALONE, /** Stand-alone acceleration */ }; -/** Cells types +/* Cells types */ enum ia_css_cell_type { IA_CSS_SP0 = 0, @@ -58,45 +58,45 @@ enum ia_css_cell_type { MAX_NUM_OF_CELLS }; -/** Firmware types. +/* Firmware types. */ enum ia_css_fw_type { - ia_css_sp_firmware, /**< Firmware for the SP */ - ia_css_isp_firmware, /**< Firmware for the ISP */ - ia_css_bootloader_firmware, /**< Firmware for the BootLoader */ - ia_css_acc_firmware /**< Firmware for accelrations */ + ia_css_sp_firmware, /** Firmware for the SP */ + ia_css_isp_firmware, /** Firmware for the ISP */ + ia_css_bootloader_firmware, /** Firmware for the BootLoader */ + ia_css_acc_firmware /** Firmware for accelrations */ }; struct ia_css_blob_descr; -/** Blob descriptor. +/* Blob descriptor. * This structure describes an SP or ISP blob. * It describes the test, data and bss sections as well as position in a * firmware file. * For convenience, it contains dynamic data after loading. */ struct ia_css_blob_info { - /**< Static blob data */ - uint32_t offset; /**< Blob offset in fw file */ - struct ia_css_isp_param_memory_offsets memory_offsets; /**< offset wrt hdr in bytes */ - uint32_t prog_name_offset; /**< offset wrt hdr in bytes */ - uint32_t size; /**< Size of blob */ - uint32_t padding_size; /**< total cummulative of bytes added due to section alignment */ - uint32_t icache_source; /**< Position of icache in blob */ - uint32_t icache_size; /**< Size of icache section */ - uint32_t icache_padding;/**< bytes added due to icache section alignment */ - uint32_t text_source; /**< Position of text in blob */ - uint32_t text_size; /**< Size of text section */ - uint32_t text_padding; /**< bytes added due to text section alignment */ - uint32_t data_source; /**< Position of data in blob */ - uint32_t data_target; /**< Start of data in SP dmem */ - uint32_t data_size; /**< Size of text section */ - uint32_t data_padding; /**< bytes added due to data section alignment */ - uint32_t bss_target; /**< Start position of bss in SP dmem */ - uint32_t bss_size; /**< Size of bss section */ - /**< Dynamic data filled by loader */ - CSS_ALIGN(const void *code, 8); /**< Code section absolute pointer within fw, code = icache + text */ - CSS_ALIGN(const void *data, 8); /**< Data section absolute pointer within fw, data = data + bss */ + /** Static blob data */ + uint32_t offset; /** Blob offset in fw file */ + struct ia_css_isp_param_memory_offsets memory_offsets; /** offset wrt hdr in bytes */ + uint32_t prog_name_offset; /** offset wrt hdr in bytes */ + uint32_t size; /** Size of blob */ + uint32_t padding_size; /** total cummulative of bytes added due to section alignment */ + uint32_t icache_source; /** Position of icache in blob */ + uint32_t icache_size; /** Size of icache section */ + uint32_t icache_padding;/** bytes added due to icache section alignment */ + uint32_t text_source; /** Position of text in blob */ + uint32_t text_size; /** Size of text section */ + uint32_t text_padding; /** bytes added due to text section alignment */ + uint32_t data_source; /** Position of data in blob */ + uint32_t data_target; /** Start of data in SP dmem */ + uint32_t data_size; /** Size of text section */ + uint32_t data_padding; /** bytes added due to data section alignment */ + uint32_t bss_target; /** Start position of bss in SP dmem */ + uint32_t bss_size; /** Size of bss section */ + /** Dynamic data filled by loader */ + CSS_ALIGN(const void *code, 8); /** Code section absolute pointer within fw, code = icache + text */ + CSS_ALIGN(const void *data, 8); /** Data section absolute pointer within fw, data = data + bss */ }; struct ia_css_binary_input_info { @@ -140,9 +140,9 @@ struct ia_css_binary_s3a_info { uint32_t fixed_s3a_deci_log; }; -/** DPC related binary info */ +/* DPC related binary info */ struct ia_css_binary_dpc_info { - uint32_t bnr_lite; /**< bnr lite enable flag */ + uint32_t bnr_lite; /** bnr lite enable flag */ }; struct ia_css_binary_iterator_info { @@ -193,7 +193,7 @@ struct ia_css_binary_block_info { uint32_t output_block_height; }; -/** Structure describing an ISP binary. +/* Structure describing an ISP binary. * It describes the capabilities of a binary, like the maximum resolution, * support features, dma channels, uds features, etc. * This part is to be used by the SP. @@ -210,7 +210,7 @@ struct ia_css_binary_info { struct ia_css_binary_dvs_info dvs; struct ia_css_binary_vf_dec_info vf_dec; struct ia_css_binary_s3a_info s3a; - struct ia_css_binary_dpc_info dpc_bnr; /**< DPC related binary info */ + struct ia_css_binary_dpc_info dpc_bnr; /** DPC related binary info */ struct ia_css_binary_iterator_info iterator; struct ia_css_binary_address_info addresses; struct ia_css_binary_uds_info uds; @@ -269,7 +269,7 @@ struct ia_css_binary_info { } dma; }; -/** Structure describing an ISP binary. +/* Structure describing an ISP binary. * It describes the capabilities of a binary, like the maximum resolution, * support features, dma channels, uds features, etc. */ @@ -281,8 +281,8 @@ struct ia_css_binary_xinfo { enum ia_css_acc_type type; CSS_ALIGN(int32_t num_output_formats, 8); enum ia_css_frame_format output_formats[IA_CSS_FRAME_FORMAT_NUM]; - CSS_ALIGN(int32_t num_vf_formats, 8); /**< number of supported vf formats */ - enum ia_css_frame_format vf_formats[IA_CSS_FRAME_FORMAT_NUM]; /**< types of supported vf formats */ + CSS_ALIGN(int32_t num_vf_formats, 8); /** number of supported vf formats */ + enum ia_css_frame_format vf_formats[IA_CSS_FRAME_FORMAT_NUM]; /** types of supported vf formats */ uint8_t num_output_pins; ia_css_ptr xmem_addr; CSS_ALIGN(const struct ia_css_blob_descr *blob, 8); @@ -291,55 +291,55 @@ struct ia_css_binary_xinfo { CSS_ALIGN(struct ia_css_binary_xinfo *next, 8); }; -/** Structure describing the Bootloader (an ISP binary). +/* Structure describing the Bootloader (an ISP binary). * It contains several address, either in ddr, isp_dmem or * the entry function in icache. */ struct ia_css_bl_info { - uint32_t num_dma_cmds; /**< Number of cmds sent by CSS */ - uint32_t dma_cmd_list; /**< Dma command list sent by CSS */ - uint32_t sw_state; /**< Polled from css */ + uint32_t num_dma_cmds; /** Number of cmds sent by CSS */ + uint32_t dma_cmd_list; /** Dma command list sent by CSS */ + uint32_t sw_state; /** Polled from css */ /* Entry functions */ - uint32_t bl_entry; /**< The SP entry function */ + uint32_t bl_entry; /** The SP entry function */ }; -/** Structure describing the SP binary. +/* Structure describing the SP binary. * It contains several address, either in ddr, sp_dmem or * the entry function in pmem. */ struct ia_css_sp_info { - uint32_t init_dmem_data; /**< data sect config, stored to dmem */ - uint32_t per_frame_data; /**< Per frame data, stored to dmem */ - uint32_t group; /**< Per pipeline data, loaded by dma */ - uint32_t output; /**< SP output data, loaded by dmem */ - uint32_t host_sp_queue; /**< Host <-> SP queues */ - uint32_t host_sp_com;/**< Host <-> SP commands */ - uint32_t isp_started; /**< Polled from sensor thread, csim only */ - uint32_t sw_state; /**< Polled from css */ - uint32_t host_sp_queues_initialized; /**< Polled from the SP */ - uint32_t sleep_mode; /**< different mode to halt SP */ - uint32_t invalidate_tlb; /**< inform SP to invalidate mmu TLB */ + uint32_t init_dmem_data; /** data sect config, stored to dmem */ + uint32_t per_frame_data; /** Per frame data, stored to dmem */ + uint32_t group; /** Per pipeline data, loaded by dma */ + uint32_t output; /** SP output data, loaded by dmem */ + uint32_t host_sp_queue; /** Host <-> SP queues */ + uint32_t host_sp_com;/** Host <-> SP commands */ + uint32_t isp_started; /** Polled from sensor thread, csim only */ + uint32_t sw_state; /** Polled from css */ + uint32_t host_sp_queues_initialized; /** Polled from the SP */ + uint32_t sleep_mode; /** different mode to halt SP */ + uint32_t invalidate_tlb; /** inform SP to invalidate mmu TLB */ #ifndef ISP2401 - uint32_t stop_copy_preview; /**< suspend copy and preview pipe when capture */ + uint32_t stop_copy_preview; /** suspend copy and preview pipe when capture */ #endif - uint32_t debug_buffer_ddr_address; /**< inform SP the address + uint32_t debug_buffer_ddr_address; /** inform SP the address of DDR debug queue */ - uint32_t perf_counter_input_system_error; /**< input system perf + uint32_t perf_counter_input_system_error; /** input system perf counter array */ #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG - uint32_t debug_wait; /**< thread/pipe post mortem debug */ - uint32_t debug_stage; /**< thread/pipe post mortem debug */ - uint32_t debug_stripe; /**< thread/pipe post mortem debug */ + uint32_t debug_wait; /** thread/pipe post mortem debug */ + uint32_t debug_stage; /** thread/pipe post mortem debug */ + uint32_t debug_stripe; /** thread/pipe post mortem debug */ #endif - uint32_t threads_stack; /**< sp thread's stack pointers */ - uint32_t threads_stack_size; /**< sp thread's stack sizes */ - uint32_t curr_binary_id; /**< current binary id */ - uint32_t raw_copy_line_count; /**< raw copy line counter */ - uint32_t ddr_parameter_address; /**< acc param ddrptr, sp dmem */ - uint32_t ddr_parameter_size; /**< acc param size, sp dmem */ + uint32_t threads_stack; /** sp thread's stack pointers */ + uint32_t threads_stack_size; /** sp thread's stack sizes */ + uint32_t curr_binary_id; /** current binary id */ + uint32_t raw_copy_line_count; /** raw copy line counter */ + uint32_t ddr_parameter_address; /** acc param ddrptr, sp dmem */ + uint32_t ddr_parameter_size; /** acc param size, sp dmem */ /* Entry functions */ - uint32_t sp_entry; /**< The SP entry function */ - uint32_t tagger_frames_addr; /**< Base address of tagger state */ + uint32_t sp_entry; /** The SP entry function */ + uint32_t tagger_frames_addr; /** Base address of tagger state */ }; /* The following #if is there because this header file is also included @@ -348,37 +348,37 @@ struct ia_css_sp_info { More permanent solution will be to refactor this include. */ #if !defined(__ISP) -/** Accelerator firmware information. +/* Accelerator firmware information. */ struct ia_css_acc_info { - uint32_t per_frame_data; /**< Dummy for now */ + uint32_t per_frame_data; /** Dummy for now */ }; -/** Firmware information. +/* Firmware information. */ union ia_css_fw_union { - struct ia_css_binary_xinfo isp; /**< ISP info */ - struct ia_css_sp_info sp; /**< SP info */ - struct ia_css_bl_info bl; /**< Bootloader info */ - struct ia_css_acc_info acc; /**< Accelerator info */ + struct ia_css_binary_xinfo isp; /** ISP info */ + struct ia_css_sp_info sp; /** SP info */ + struct ia_css_bl_info bl; /** Bootloader info */ + struct ia_css_acc_info acc; /** Accelerator info */ }; -/** Firmware information. +/* Firmware information. */ struct ia_css_fw_info { - size_t header_size; /**< size of fw header */ + size_t header_size; /** size of fw header */ CSS_ALIGN(uint32_t type, 8); - union ia_css_fw_union info; /**< Binary info */ - struct ia_css_blob_info blob; /**< Blob info */ + union ia_css_fw_union info; /** Binary info */ + struct ia_css_blob_info blob; /** Blob info */ /* Dynamic part */ struct ia_css_fw_info *next; - CSS_ALIGN(uint32_t loaded, 8); /**< Firmware has been loaded */ - CSS_ALIGN(const uint8_t *isp_code, 8); /**< ISP pointer to code */ - /**< Firmware handle between user space and kernel */ + CSS_ALIGN(uint32_t loaded, 8); /** Firmware has been loaded */ + CSS_ALIGN(const uint8_t *isp_code, 8); /** ISP pointer to code */ + /** Firmware handle between user space and kernel */ CSS_ALIGN(uint32_t handle, 8); - /**< Sections to copy from/to ISP */ + /** Sections to copy from/to ISP */ struct ia_css_isp_param_css_segments mem_initializers; - /**< Initializer for local ISP memories */ + /** Initializer for local ISP memories */ }; struct ia_css_blob_descr { @@ -390,39 +390,39 @@ struct ia_css_blob_descr { struct ia_css_acc_fw; -/** Structure describing the SP binary of a stand-alone accelerator. +/* Structure describing the SP binary of a stand-alone accelerator. */ struct ia_css_acc_sp { - void (*init)(struct ia_css_acc_fw *); /**< init for crun */ - uint32_t sp_prog_name_offset; /**< program name offset wrt hdr in bytes */ - uint32_t sp_blob_offset; /**< blob offset wrt hdr in bytes */ - void *entry; /**< Address of sp entry point */ - uint32_t *css_abort; /**< SP dmem abort flag */ - void *isp_code; /**< SP dmem address holding xmem + void (*init)(struct ia_css_acc_fw *); /** init for crun */ + uint32_t sp_prog_name_offset; /** program name offset wrt hdr in bytes */ + uint32_t sp_blob_offset; /** blob offset wrt hdr in bytes */ + void *entry; /** Address of sp entry point */ + uint32_t *css_abort; /** SP dmem abort flag */ + void *isp_code; /** SP dmem address holding xmem address of isp code */ - struct ia_css_fw_info fw; /**< SP fw descriptor */ - const uint8_t *code; /**< ISP pointer of allocated SP code */ + struct ia_css_fw_info fw; /** SP fw descriptor */ + const uint8_t *code; /** ISP pointer of allocated SP code */ }; -/** Acceleration firmware descriptor. +/* Acceleration firmware descriptor. * This descriptor descibes either SP code (stand-alone), or * ISP code (a separate pipeline stage). */ struct ia_css_acc_fw_hdr { - enum ia_css_acc_type type; /**< Type of accelerator */ - uint32_t isp_prog_name_offset; /**< program name offset wrt + enum ia_css_acc_type type; /** Type of accelerator */ + uint32_t isp_prog_name_offset; /** program name offset wrt header in bytes */ - uint32_t isp_blob_offset; /**< blob offset wrt header + uint32_t isp_blob_offset; /** blob offset wrt header in bytes */ - uint32_t isp_size; /**< Size of isp blob */ - const uint8_t *isp_code; /**< ISP pointer to code */ - struct ia_css_acc_sp sp; /**< Standalone sp code */ - /**< Firmware handle between user space and kernel */ + uint32_t isp_size; /** Size of isp blob */ + const uint8_t *isp_code; /** ISP pointer to code */ + struct ia_css_acc_sp sp; /** Standalone sp code */ + /** Firmware handle between user space and kernel */ uint32_t handle; - struct ia_css_data parameters; /**< Current SP parameters */ + struct ia_css_data parameters; /** Current SP parameters */ }; -/** Firmware structure. +/* Firmware structure. * This contains the header and actual blobs. * For standalone, it contains SP and ISP blob. * For a pipeline stage accelerator, it contains ISP code only. @@ -430,7 +430,7 @@ struct ia_css_acc_fw_hdr { * header and computed using the access macros below. */ struct ia_css_acc_fw { - struct ia_css_acc_fw_hdr header; /**< firmware header */ + struct ia_css_acc_fw_hdr header; /** firmware header */ /* int8_t isp_progname[]; **< ISP program name int8_t sp_progname[]; **< SP program name, stand-alone only diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_buffer.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_buffer.h index b2ecf3618c15..a0058eac7d5a 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_buffer.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_buffer.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_BUFFER_H #define __IA_CSS_BUFFER_H -/** @file +/* @file * This file contains datastructures and types for buffers used in CSS */ @@ -23,7 +23,7 @@ #include "ia_css_types.h" #include "ia_css_timer.h" -/** Enumeration of buffer types. Buffers can be queued and de-queued +/* Enumeration of buffer types. Buffers can be queued and de-queued * to hand them over between IA and ISP. */ enum ia_css_buffer_type { @@ -48,28 +48,28 @@ enum ia_css_buffer_type { /* Driver API is not SP/ISP visible, 64 bit types not supported on hivecc */ #if !defined(__ISP) -/** Buffer structure. This is a container structure that enables content +/* Buffer structure. This is a container structure that enables content * independent buffer queues and access functions. */ struct ia_css_buffer { - enum ia_css_buffer_type type; /**< Buffer type. */ + enum ia_css_buffer_type type; /** Buffer type. */ unsigned int exp_id; - /**< exposure id for this buffer; 0 = not available + /** exposure id for this buffer; 0 = not available see ia_css_event_public.h for more detail. */ union { - struct ia_css_isp_3a_statistics *stats_3a; /**< 3A statistics & optionally RGBY statistics. */ - struct ia_css_isp_dvs_statistics *stats_dvs; /**< DVS statistics. */ - struct ia_css_isp_skc_dvs_statistics *stats_skc_dvs; /**< SKC DVS statistics. */ - struct ia_css_frame *frame; /**< Frame buffer. */ - struct ia_css_acc_param *custom_data; /**< Custom buffer. */ - struct ia_css_metadata *metadata; /**< Sensor metadata. */ - } data; /**< Buffer data pointer. */ - uint64_t driver_cookie; /**< cookie for the driver */ - struct ia_css_time_meas timing_data; /**< timing data (readings from the timer) */ - struct ia_css_clock_tick isys_eof_clock_tick; /**< ISYS's end of frame timer tick*/ + struct ia_css_isp_3a_statistics *stats_3a; /** 3A statistics & optionally RGBY statistics. */ + struct ia_css_isp_dvs_statistics *stats_dvs; /** DVS statistics. */ + struct ia_css_isp_skc_dvs_statistics *stats_skc_dvs; /** SKC DVS statistics. */ + struct ia_css_frame *frame; /** Frame buffer. */ + struct ia_css_acc_param *custom_data; /** Custom buffer. */ + struct ia_css_metadata *metadata; /** Sensor metadata. */ + } data; /** Buffer data pointer. */ + uint64_t driver_cookie; /** cookie for the driver */ + struct ia_css_time_meas timing_data; /** timing data (readings from the timer) */ + struct ia_css_clock_tick isys_eof_clock_tick; /** ISYS's end of frame timer tick*/ }; -/** @brief Dequeue param buffers from sp2host_queue +/* @brief Dequeue param buffers from sp2host_queue * * @return None * diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_control.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_control.h index a15d3e368341..021a313fab85 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_control.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_control.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_CONTROL_H #define __IA_CSS_CONTROL_H -/** @file +/* @file * This file contains functionality for starting and controlling CSS */ @@ -24,7 +24,7 @@ #include #include -/** @brief Initialize the CSS API. +/* @brief Initialize the CSS API. * @param[in] env Environment, provides functions to access the * environment in which the CSS code runs. This is * used for host side memory access and message @@ -51,7 +51,7 @@ enum ia_css_err ia_css_init( uint32_t l1_base, enum ia_css_irq_type irq_type); -/** @brief Un-initialize the CSS API. +/* @brief Un-initialize the CSS API. * @return None * * This function deallocates all memory that has been allocated by the CSS API @@ -66,7 +66,7 @@ enum ia_css_err ia_css_init( void ia_css_uninit(void); -/** @brief Suspend CSS API for power down +/* @brief Suspend CSS API for power down * @return success or faulure code * * suspend shuts down the system by: @@ -80,7 +80,7 @@ ia_css_uninit(void); enum ia_css_err ia_css_suspend(void); -/** @brief Resume CSS API from power down +/* @brief Resume CSS API from power down * @return success or failure code * * After a power cycle, this function will bring the CSS API back into @@ -91,7 +91,7 @@ ia_css_suspend(void); enum ia_css_err ia_css_resume(void); -/** @brief Enable use of a separate queue for ISYS events. +/* @brief Enable use of a separate queue for ISYS events. * * @param[in] enable: enable or disable use of separate ISYS event queues. * @return error if called when SP is running. @@ -105,7 +105,7 @@ ia_css_resume(void); enum ia_css_err ia_css_enable_isys_event_queue(bool enable); -/** @brief Test whether the ISP has started. +/* @brief Test whether the ISP has started. * * @return Boolean flag true if the ISP has started or false otherwise. * @@ -114,7 +114,7 @@ ia_css_enable_isys_event_queue(bool enable); bool ia_css_isp_has_started(void); -/** @brief Test whether the SP has initialized. +/* @brief Test whether the SP has initialized. * * @return Boolean flag true if the SP has initialized or false otherwise. * @@ -123,7 +123,7 @@ ia_css_isp_has_started(void); bool ia_css_sp_has_initialized(void); -/** @brief Test whether the SP has terminated. +/* @brief Test whether the SP has terminated. * * @return Boolean flag true if the SP has terminated or false otherwise. * @@ -132,7 +132,7 @@ ia_css_sp_has_initialized(void); bool ia_css_sp_has_terminated(void); -/** @brief start SP hardware +/* @brief start SP hardware * * @return IA_CSS_SUCCESS or error code upon error. * @@ -144,7 +144,7 @@ enum ia_css_err ia_css_start_sp(void); -/** @brief stop SP hardware +/* @brief stop SP hardware * * @return IA_CSS_SUCCESS or error code upon error. * diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_device_access.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_device_access.h index 59459f7a9876..84a960b7abbc 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_device_access.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_device_access.h @@ -15,7 +15,7 @@ #ifndef _IA_CSS_DEVICE_ACCESS_H #define _IA_CSS_DEVICE_ACCESS_H -/** @file +/* @file * File containing internal functions for the CSS-API to access the CSS device. */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_dvs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_dvs.h index 147bf81959d3..1f01534964e3 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_dvs.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_dvs.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_DVS_H #define __IA_CSS_DVS_H -/** @file +/* @file * This file contains types for DVS statistics */ @@ -31,7 +31,7 @@ enum dvs_statistics_type { }; -/** Structure that holds DVS statistics in the ISP internal +/* Structure that holds DVS statistics in the ISP internal * format. Use ia_css_get_dvs_statistics() to translate * this to the format used on the host (DVS engine). * */ @@ -40,12 +40,12 @@ struct ia_css_isp_dvs_statistics { ia_css_ptr ver_proj; uint32_t hor_size; uint32_t ver_size; - uint32_t exp_id; /**< see ia_css_event_public.h for more detail */ + uint32_t exp_id; /** see ia_css_event_public.h for more detail */ ia_css_ptr data_ptr; /* base pointer containing all memory */ uint32_t size; /* size of allocated memory in data_ptr */ }; -/** Structure that holds SKC DVS statistics in the ISP internal +/* Structure that holds SKC DVS statistics in the ISP internal * format. Use ia_css_dvs_statistics_get() to translate this to * the format used on the host. * */ @@ -82,7 +82,7 @@ union ia_css_dvs_statistics_host { struct ia_css_skc_dvs_statistics *p_skc_dvs_statistics_host; }; -/** @brief Copy DVS statistics from an ISP buffer to a host buffer. +/* @brief Copy DVS statistics from an ISP buffer to a host buffer. * @param[in] host_stats Host buffer * @param[in] isp_stats ISP buffer * @return error value if temporary memory cannot be allocated @@ -100,7 +100,7 @@ enum ia_css_err ia_css_get_dvs_statistics(struct ia_css_dvs_statistics *host_stats, const struct ia_css_isp_dvs_statistics *isp_stats); -/** @brief Translate DVS statistics from ISP format to host format +/* @brief Translate DVS statistics from ISP format to host format * @param[in] host_stats Host buffer * @param[in] isp_stats ISP buffer * @return None @@ -116,7 +116,7 @@ ia_css_translate_dvs_statistics( struct ia_css_dvs_statistics *host_stats, const struct ia_css_isp_dvs_statistics_map *isp_stats); -/** @brief Copy DVS 2.0 statistics from an ISP buffer to a host buffer. +/* @brief Copy DVS 2.0 statistics from an ISP buffer to a host buffer. * @param[in] host_stats Host buffer * @param[in] isp_stats ISP buffer * @return error value if temporary memory cannot be allocated @@ -134,7 +134,7 @@ enum ia_css_err ia_css_get_dvs2_statistics(struct ia_css_dvs2_statistics *host_stats, const struct ia_css_isp_dvs_statistics *isp_stats); -/** @brief Translate DVS2 statistics from ISP format to host format +/* @brief Translate DVS2 statistics from ISP format to host format * @param[in] host_stats Host buffer * @param[in] isp_stats ISP buffer * @return None @@ -150,7 +150,7 @@ ia_css_translate_dvs2_statistics( struct ia_css_dvs2_statistics *host_stats, const struct ia_css_isp_dvs_statistics_map *isp_stats); -/** @brief Copy DVS statistics from an ISP buffer to a host buffer. +/* @brief Copy DVS statistics from an ISP buffer to a host buffer. * @param[in] type - DVS statistics type * @param[in] host_stats Host buffer * @param[in] isp_stats ISP buffer @@ -161,105 +161,105 @@ ia_css_dvs_statistics_get(enum dvs_statistics_type type, union ia_css_dvs_statistics_host *host_stats, const union ia_css_dvs_statistics_isp *isp_stats); -/** @brief Allocate the DVS statistics memory on the ISP +/* @brief Allocate the DVS statistics memory on the ISP * @param[in] grid The grid. * @return Pointer to the allocated DVS statistics buffer on the ISP */ struct ia_css_isp_dvs_statistics * ia_css_isp_dvs_statistics_allocate(const struct ia_css_dvs_grid_info *grid); -/** @brief Free the DVS statistics memory on the ISP +/* @brief Free the DVS statistics memory on the ISP * @param[in] me Pointer to the DVS statistics buffer on the ISP. * @return None */ void ia_css_isp_dvs_statistics_free(struct ia_css_isp_dvs_statistics *me); -/** @brief Allocate the DVS 2.0 statistics memory +/* @brief Allocate the DVS 2.0 statistics memory * @param[in] grid The grid. * @return Pointer to the allocated DVS statistics buffer on the ISP */ struct ia_css_isp_dvs_statistics * ia_css_isp_dvs2_statistics_allocate(const struct ia_css_dvs_grid_info *grid); -/** @brief Free the DVS 2.0 statistics memory +/* @brief Free the DVS 2.0 statistics memory * @param[in] me Pointer to the DVS statistics buffer on the ISP. * @return None */ void ia_css_isp_dvs2_statistics_free(struct ia_css_isp_dvs_statistics *me); -/** @brief Allocate the DVS statistics memory on the host +/* @brief Allocate the DVS statistics memory on the host * @param[in] grid The grid. * @return Pointer to the allocated DVS statistics buffer on the host */ struct ia_css_dvs_statistics * ia_css_dvs_statistics_allocate(const struct ia_css_dvs_grid_info *grid); -/** @brief Free the DVS statistics memory on the host +/* @brief Free the DVS statistics memory on the host * @param[in] me Pointer to the DVS statistics buffer on the host. * @return None */ void ia_css_dvs_statistics_free(struct ia_css_dvs_statistics *me); -/** @brief Allocate the DVS coefficients memory +/* @brief Allocate the DVS coefficients memory * @param[in] grid The grid. * @return Pointer to the allocated DVS coefficients buffer */ struct ia_css_dvs_coefficients * ia_css_dvs_coefficients_allocate(const struct ia_css_dvs_grid_info *grid); -/** @brief Free the DVS coefficients memory +/* @brief Free the DVS coefficients memory * @param[in] me Pointer to the DVS coefficients buffer. * @return None */ void ia_css_dvs_coefficients_free(struct ia_css_dvs_coefficients *me); -/** @brief Allocate the DVS 2.0 statistics memory on the host +/* @brief Allocate the DVS 2.0 statistics memory on the host * @param[in] grid The grid. * @return Pointer to the allocated DVS 2.0 statistics buffer on the host */ struct ia_css_dvs2_statistics * ia_css_dvs2_statistics_allocate(const struct ia_css_dvs_grid_info *grid); -/** @brief Free the DVS 2.0 statistics memory +/* @brief Free the DVS 2.0 statistics memory * @param[in] me Pointer to the DVS 2.0 statistics buffer on the host. * @return None */ void ia_css_dvs2_statistics_free(struct ia_css_dvs2_statistics *me); -/** @brief Allocate the DVS 2.0 coefficients memory +/* @brief Allocate the DVS 2.0 coefficients memory * @param[in] grid The grid. * @return Pointer to the allocated DVS 2.0 coefficients buffer */ struct ia_css_dvs2_coefficients * ia_css_dvs2_coefficients_allocate(const struct ia_css_dvs_grid_info *grid); -/** @brief Free the DVS 2.0 coefficients memory +/* @brief Free the DVS 2.0 coefficients memory * @param[in] me Pointer to the DVS 2.0 coefficients buffer. * @return None */ void ia_css_dvs2_coefficients_free(struct ia_css_dvs2_coefficients *me); -/** @brief Allocate the DVS 2.0 6-axis config memory +/* @brief Allocate the DVS 2.0 6-axis config memory * @param[in] stream The stream. * @return Pointer to the allocated DVS 6axis configuration buffer */ struct ia_css_dvs_6axis_config * ia_css_dvs2_6axis_config_allocate(const struct ia_css_stream *stream); -/** @brief Free the DVS 2.0 6-axis config memory +/* @brief Free the DVS 2.0 6-axis config memory * @param[in] dvs_6axis_config Pointer to the DVS 6axis configuration buffer * @return None */ void ia_css_dvs2_6axis_config_free(struct ia_css_dvs_6axis_config *dvs_6axis_config); -/** @brief Allocate a dvs statistics map structure +/* @brief Allocate a dvs statistics map structure * @param[in] isp_stats pointer to ISP dvs statistis struct * @param[in] data_ptr host-side pointer to ISP dvs statistics. * @return Pointer to the allocated dvs statistics map @@ -280,7 +280,7 @@ ia_css_isp_dvs_statistics_map_allocate( const struct ia_css_isp_dvs_statistics *isp_stats, void *data_ptr); -/** @brief Free the dvs statistics map +/* @brief Free the dvs statistics map * @param[in] me Pointer to the dvs statistics map * @return None * @@ -291,7 +291,7 @@ ia_css_isp_dvs_statistics_map_allocate( void ia_css_isp_dvs_statistics_map_free(struct ia_css_isp_dvs_statistics_map *me); -/** @brief Allocate memory for the SKC DVS statistics on the ISP +/* @brief Allocate memory for the SKC DVS statistics on the ISP * @return Pointer to the allocated ACC DVS statistics buffer on the ISP */ struct ia_css_isp_skc_dvs_statistics *ia_css_skc_dvs_statistics_allocate(void); diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_env.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_env.h index 1ae9daf0be76..8b0218ee658d 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_env.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_env.h @@ -20,12 +20,12 @@ #include "ia_css_types.h" #include "ia_css_acc_types.h" -/** @file +/* @file * This file contains prototypes for functions that need to be provided to the * CSS-API host-code by the environment in which the CSS-API code runs. */ -/** Memory allocation attributes, for use in ia_css_css_mem_env. */ +/* Memory allocation attributes, for use in ia_css_css_mem_env. */ enum ia_css_mem_attr { IA_CSS_MEM_ATTR_CACHED = 1 << 0, IA_CSS_MEM_ATTR_ZEROED = 1 << 1, @@ -33,62 +33,62 @@ enum ia_css_mem_attr { IA_CSS_MEM_ATTR_CONTIGUOUS = 1 << 3, }; -/** Environment with function pointers for local IA memory allocation. +/* Environment with function pointers for local IA memory allocation. * This provides the CSS code with environment specific functionality * for memory allocation of small local buffers such as local data structures. * This is never expected to allocate more than one page of memory (4K bytes). */ struct ia_css_cpu_mem_env { void (*flush)(struct ia_css_acc_fw *fw); - /**< Flush function to flush the cache for given accelerator. */ + /** Flush function to flush the cache for given accelerator. */ }; -/** Environment with function pointers to access the CSS hardware. This includes +/* Environment with function pointers to access the CSS hardware. This includes * registers and local memories. */ struct ia_css_hw_access_env { void (*store_8)(hrt_address addr, uint8_t data); - /**< Store an 8 bit value into an address in the CSS HW address space. + /** Store an 8 bit value into an address in the CSS HW address space. The address must be an 8 bit aligned address. */ void (*store_16)(hrt_address addr, uint16_t data); - /**< Store a 16 bit value into an address in the CSS HW address space. + /** Store a 16 bit value into an address in the CSS HW address space. The address must be a 16 bit aligned address. */ void (*store_32)(hrt_address addr, uint32_t data); - /**< Store a 32 bit value into an address in the CSS HW address space. + /** Store a 32 bit value into an address in the CSS HW address space. The address must be a 32 bit aligned address. */ uint8_t (*load_8)(hrt_address addr); - /**< Load an 8 bit value from an address in the CSS HW address + /** Load an 8 bit value from an address in the CSS HW address space. The address must be an 8 bit aligned address. */ uint16_t (*load_16)(hrt_address addr); - /**< Load a 16 bit value from an address in the CSS HW address + /** Load a 16 bit value from an address in the CSS HW address space. The address must be a 16 bit aligned address. */ uint32_t (*load_32)(hrt_address addr); - /**< Load a 32 bit value from an address in the CSS HW address + /** Load a 32 bit value from an address in the CSS HW address space. The address must be a 32 bit aligned address. */ void (*store)(hrt_address addr, const void *data, uint32_t bytes); - /**< Store a number of bytes into a byte-aligned address in the CSS HW address space. */ + /** Store a number of bytes into a byte-aligned address in the CSS HW address space. */ void (*load)(hrt_address addr, void *data, uint32_t bytes); - /**< Load a number of bytes from a byte-aligned address in the CSS HW address space. */ + /** Load a number of bytes from a byte-aligned address in the CSS HW address space. */ }; -/** Environment with function pointers to print error and debug messages. +/* Environment with function pointers to print error and debug messages. */ struct ia_css_print_env { int (*debug_print)(const char *fmt, va_list args); - /**< Print a debug message. */ + /** Print a debug message. */ int (*error_print)(const char *fmt, va_list args); - /**< Print an error message.*/ + /** Print an error message.*/ }; -/** Environment structure. This includes function pointers to access several +/* Environment structure. This includes function pointers to access several * features provided by the environment in which the CSS API is used. * This is used to run the camera IP in multiple platforms such as Linux, * Windows and several simulation environments. */ struct ia_css_env { - struct ia_css_cpu_mem_env cpu_mem_env; /**< local flush. */ - struct ia_css_hw_access_env hw_access_env; /**< CSS HW access functions */ - struct ia_css_print_env print_env; /**< Message printing env. */ + struct ia_css_cpu_mem_env cpu_mem_env; /** local flush. */ + struct ia_css_hw_access_env hw_access_env; /** CSS HW access functions */ + struct ia_css_print_env print_env; /** Message printing env. */ }; #endif /* __IA_CSS_ENV_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_err.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_err.h index 572e4e55c69e..cf895815ea31 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_err.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_err.h @@ -15,12 +15,12 @@ #ifndef __IA_CSS_ERR_H #define __IA_CSS_ERR_H -/** @file +/* @file * This file contains possible return values for most * functions in the CSS-API. */ -/** Errors, these values are used as the return value for most +/* Errors, these values are used as the return value for most * functions in this API. */ enum ia_css_err { @@ -41,22 +41,22 @@ enum ia_css_err { IA_CSS_ERR_NOT_SUPPORTED }; -/** FW warnings. This enum contains a value for each warning that +/* FW warnings. This enum contains a value for each warning that * the SP FW could indicate potential performance issue */ enum ia_css_fw_warning { IA_CSS_FW_WARNING_NONE, - IA_CSS_FW_WARNING_ISYS_QUEUE_FULL, /** < CSS system delayed because of insufficient space in the ISys queue. + IA_CSS_FW_WARNING_ISYS_QUEUE_FULL, /* < CSS system delayed because of insufficient space in the ISys queue. This warning can be avoided by de-queing ISYS buffers more timely. */ - IA_CSS_FW_WARNING_PSYS_QUEUE_FULL, /** < CSS system delayed because of insufficient space in the PSys queue. + IA_CSS_FW_WARNING_PSYS_QUEUE_FULL, /* < CSS system delayed because of insufficient space in the PSys queue. This warning can be avoided by de-queing PSYS buffers more timely. */ - IA_CSS_FW_WARNING_CIRCBUF_ALL_LOCKED, /** < CSS system delayed because of insufficient available buffers. + IA_CSS_FW_WARNING_CIRCBUF_ALL_LOCKED, /* < CSS system delayed because of insufficient available buffers. This warning can be avoided by unlocking locked frame-buffers more timely. */ - IA_CSS_FW_WARNING_EXP_ID_LOCKED, /** < Exposure ID skipped because the frame associated to it was still locked. + IA_CSS_FW_WARNING_EXP_ID_LOCKED, /* < Exposure ID skipped because the frame associated to it was still locked. This warning can be avoided by unlocking locked frame-buffers more timely. */ - IA_CSS_FW_WARNING_TAG_EXP_ID_FAILED, /** < Exposure ID cannot be found on the circular buffer. + IA_CSS_FW_WARNING_TAG_EXP_ID_FAILED, /* < Exposure ID cannot be found on the circular buffer. This warning can be avoided by unlocking locked frame-buffers more timely. */ - IA_CSS_FW_WARNING_FRAME_PARAM_MISMATCH, /** < Frame and param pair mismatched in tagger. + IA_CSS_FW_WARNING_FRAME_PARAM_MISMATCH, /* < Frame and param pair mismatched in tagger. This warning can be avoided by providing a param set for each frame. */ }; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_event_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_event_public.h index aaf349772abe..036a2f03d3bd 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_event_public.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_event_public.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_EVENT_PUBLIC_H #define __IA_CSS_EVENT_PUBLIC_H -/** @file +/* @file * This file contains CSS-API events functionality */ @@ -24,7 +24,7 @@ #include /* ia_css_pipe */ #include /* ia_css_timer */ -/** The event type, distinguishes the kind of events that +/* The event type, distinguishes the kind of events that * can are generated by the CSS system. * * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC: @@ -35,43 +35,43 @@ */ enum ia_css_event_type { IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE = 1 << 0, - /**< Output frame ready. */ + /** Output frame ready. */ IA_CSS_EVENT_TYPE_SECOND_OUTPUT_FRAME_DONE = 1 << 1, - /**< Second output frame ready. */ + /** Second output frame ready. */ IA_CSS_EVENT_TYPE_VF_OUTPUT_FRAME_DONE = 1 << 2, - /**< Viewfinder Output frame ready. */ + /** Viewfinder Output frame ready. */ IA_CSS_EVENT_TYPE_SECOND_VF_OUTPUT_FRAME_DONE = 1 << 3, - /**< Second viewfinder Output frame ready. */ + /** Second viewfinder Output frame ready. */ IA_CSS_EVENT_TYPE_3A_STATISTICS_DONE = 1 << 4, - /**< Indication that 3A statistics are available. */ + /** Indication that 3A statistics are available. */ IA_CSS_EVENT_TYPE_DIS_STATISTICS_DONE = 1 << 5, - /**< Indication that DIS statistics are available. */ + /** Indication that DIS statistics are available. */ IA_CSS_EVENT_TYPE_PIPELINE_DONE = 1 << 6, - /**< Pipeline Done event, sent after last pipeline stage. */ + /** Pipeline Done event, sent after last pipeline stage. */ IA_CSS_EVENT_TYPE_FRAME_TAGGED = 1 << 7, - /**< Frame tagged. */ + /** Frame tagged. */ IA_CSS_EVENT_TYPE_INPUT_FRAME_DONE = 1 << 8, - /**< Input frame ready. */ + /** Input frame ready. */ IA_CSS_EVENT_TYPE_METADATA_DONE = 1 << 9, - /**< Metadata ready. */ + /** Metadata ready. */ IA_CSS_EVENT_TYPE_LACE_STATISTICS_DONE = 1 << 10, - /**< Indication that LACE statistics are available. */ + /** Indication that LACE statistics are available. */ IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE = 1 << 11, - /**< Extension stage complete. */ + /** Extension stage complete. */ IA_CSS_EVENT_TYPE_TIMER = 1 << 12, - /**< Timer event for measuring the SP side latencies. It contains the + /** Timer event for measuring the SP side latencies. It contains the 32-bit timer value from the SP */ IA_CSS_EVENT_TYPE_PORT_EOF = 1 << 13, - /**< End Of Frame event, sent when in buffered sensor mode. */ + /** End Of Frame event, sent when in buffered sensor mode. */ IA_CSS_EVENT_TYPE_FW_WARNING = 1 << 14, - /**< Performance warning encounter by FW */ + /** Performance warning encounter by FW */ IA_CSS_EVENT_TYPE_FW_ASSERT = 1 << 15, - /**< Assertion hit by FW */ + /** Assertion hit by FW */ }; #define IA_CSS_EVENT_TYPE_NONE 0 -/** IA_CSS_EVENT_TYPE_ALL is a mask for all pipe related events. +/* IA_CSS_EVENT_TYPE_ALL is a mask for all pipe related events. * The other events (such as PORT_EOF) cannot be enabled/disabled * and are hence excluded from this macro. */ @@ -89,7 +89,7 @@ enum ia_css_event_type { IA_CSS_EVENT_TYPE_LACE_STATISTICS_DONE | \ IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE) -/** The event struct, container for the event type and its related values. +/* The event struct, container for the event type and its related values. * Depending on the event type, either pipe or port will be filled. * Pipeline related events (like buffer/frame events) will return a valid and filled pipe handle. * For non pipeline related events (but i.e. stream specific, like EOF event), the port will be @@ -97,14 +97,14 @@ enum ia_css_event_type { */ struct ia_css_event { struct ia_css_pipe *pipe; - /**< Pipe handle on which event happened, NULL for non pipe related + /** Pipe handle on which event happened, NULL for non pipe related events. */ enum ia_css_event_type type; - /**< Type of Event, always valid/filled. */ + /** Type of Event, always valid/filled. */ uint8_t port; - /**< Port number for EOF event (not valid for other events). */ + /** Port number for EOF event (not valid for other events). */ uint8_t exp_id; - /**< Exposure id for EOF/FRAME_TAGGED/FW_WARNING event (not valid for other events) + /** Exposure id for EOF/FRAME_TAGGED/FW_WARNING event (not valid for other events) The exposure ID is unique only within a logical stream and it is only generated on systems that have an input system (such as 2400 and 2401). @@ -120,26 +120,26 @@ struct ia_css_event { in the exposure IDs. Therefor applications should not use this to detect frame drops. */ uint32_t fw_handle; - /**< Firmware Handle for ACC_STAGE_COMPLETE event (not valid for other + /** Firmware Handle for ACC_STAGE_COMPLETE event (not valid for other events). */ enum ia_css_fw_warning fw_warning; - /**< Firmware warning code, only for WARNING events. */ + /** Firmware warning code, only for WARNING events. */ uint8_t fw_assert_module_id; - /**< Firmware module id, only for ASSERT events, should be logged by driver. */ + /** Firmware module id, only for ASSERT events, should be logged by driver. */ uint16_t fw_assert_line_no; - /**< Firmware line number, only for ASSERT events, should be logged by driver. */ + /** Firmware line number, only for ASSERT events, should be logged by driver. */ clock_value_t timer_data; - /**< For storing the full 32-bit of the timer value. Valid only for TIMER + /** For storing the full 32-bit of the timer value. Valid only for TIMER event */ uint8_t timer_code; - /**< For storing the code of the TIMER event. Valid only for + /** For storing the code of the TIMER event. Valid only for TIMER event */ uint8_t timer_subcode; - /**< For storing the subcode of the TIMER event. Valid only + /** For storing the subcode of the TIMER event. Valid only for TIMER event */ }; -/** @brief Dequeue a PSYS event from the CSS system. +/* @brief Dequeue a PSYS event from the CSS system. * * @param[out] event Pointer to the event struct which will be filled by * this function if an event is available. @@ -156,7 +156,7 @@ struct ia_css_event { enum ia_css_err ia_css_dequeue_psys_event(struct ia_css_event *event); -/** @brief Dequeue an event from the CSS system. +/* @brief Dequeue an event from the CSS system. * * @param[out] event Pointer to the event struct which will be filled by * this function if an event is available. @@ -171,7 +171,7 @@ ia_css_dequeue_psys_event(struct ia_css_event *event); enum ia_css_err ia_css_dequeue_event(struct ia_css_event *event); -/** @brief Dequeue an ISYS event from the CSS system. +/* @brief Dequeue an ISYS event from the CSS system. * * @param[out] event Pointer to the event struct which will be filled by * this function if an event is available. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_firmware.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_firmware.h index 06d375a09be2..d7d7f0a995e5 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_firmware.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_firmware.h @@ -15,21 +15,21 @@ #ifndef __IA_CSS_FIRMWARE_H #define __IA_CSS_FIRMWARE_H -/** @file +/* @file * This file contains firmware loading/unloading support functionality */ #include "ia_css_err.h" #include "ia_css_env.h" -/** CSS firmware package structure. +/* CSS firmware package structure. */ struct ia_css_fw { - void *data; /**< pointer to the firmware data */ - unsigned int bytes; /**< length in bytes of firmware data */ + void *data; /** pointer to the firmware data */ + unsigned int bytes; /** length in bytes of firmware data */ }; -/** @brief Loads the firmware +/* @brief Loads the firmware * @param[in] env Environment, provides functions to access the * environment in which the CSS code runs. This is * used for host side memory access and message @@ -51,7 +51,7 @@ enum ia_css_err ia_css_load_firmware(const struct ia_css_env *env, const struct ia_css_fw *fw); -/** @brief Unloads the firmware +/* @brief Unloads the firmware * @return None * * This function unloads the firmware loaded by ia_css_load_firmware. @@ -61,7 +61,7 @@ ia_css_load_firmware(const struct ia_css_env *env, void ia_css_unload_firmware(void); -/** @brief Checks firmware version +/* @brief Checks firmware version * @param[in] fw Firmware package containing the firmware for all * predefined ISP binaries. * @return Returns true when the firmware version matches with the CSS diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frac.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frac.h index da9c60144c6d..e5ffc579aef1 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frac.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frac.h @@ -15,7 +15,7 @@ #ifndef _IA_CSS_FRAC_H #define _IA_CSS_FRAC_H -/** @file +/* @file * This file contains typedefs used for fractional numbers */ @@ -25,13 +25,13 @@ * NOTE: the 16 bit fixed point types actually occupy 32 bits * to save on extension operations in the ISP code. */ -/** Unsigned fixed point value, 0 integer bits, 16 fractional bits */ +/* Unsigned fixed point value, 0 integer bits, 16 fractional bits */ typedef uint32_t ia_css_u0_16; -/** Unsigned fixed point value, 5 integer bits, 11 fractional bits */ +/* Unsigned fixed point value, 5 integer bits, 11 fractional bits */ typedef uint32_t ia_css_u5_11; -/** Unsigned fixed point value, 8 integer bits, 8 fractional bits */ +/* Unsigned fixed point value, 8 integer bits, 8 fractional bits */ typedef uint32_t ia_css_u8_8; -/** Signed fixed point value, 0 integer bits, 15 fractional bits */ +/* Signed fixed point value, 0 integer bits, 15 fractional bits */ typedef int32_t ia_css_s0_15; #endif /* _IA_CSS_FRAC_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_format.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_format.h index d534fbd91380..2f177edc36ac 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_format.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_format.h @@ -15,11 +15,11 @@ #ifndef __IA_CSS_FRAME_FORMAT_H #define __IA_CSS_FRAME_FORMAT_H -/** @file +/* @file * This file contains information about formats supported in the ISP */ -/** Frame formats, some of these come from fourcc.org, others are +/* Frame formats, some of these come from fourcc.org, others are better explained by video4linux2. The NV11 seems to be described only on MSDN pages, but even those seem to be gone now. Frames can come in many forms, the main categories are RAW, RGB and YUV @@ -48,45 +48,45 @@ - css/bxt_sandbox/isysapi/interface/ia_css_isysapi_fw_types.h */ enum ia_css_frame_format { - IA_CSS_FRAME_FORMAT_NV11 = 0, /**< 12 bit YUV 411, Y, UV plane */ - IA_CSS_FRAME_FORMAT_NV12, /**< 12 bit YUV 420, Y, UV plane */ - IA_CSS_FRAME_FORMAT_NV12_16, /**< 16 bit YUV 420, Y, UV plane */ - IA_CSS_FRAME_FORMAT_NV12_TILEY, /**< 12 bit YUV 420, Intel proprietary tiled format, TileY */ - IA_CSS_FRAME_FORMAT_NV16, /**< 16 bit YUV 422, Y, UV plane */ - IA_CSS_FRAME_FORMAT_NV21, /**< 12 bit YUV 420, Y, VU plane */ - IA_CSS_FRAME_FORMAT_NV61, /**< 16 bit YUV 422, Y, VU plane */ - IA_CSS_FRAME_FORMAT_YV12, /**< 12 bit YUV 420, Y, V, U plane */ - IA_CSS_FRAME_FORMAT_YV16, /**< 16 bit YUV 422, Y, V, U plane */ - IA_CSS_FRAME_FORMAT_YUV420, /**< 12 bit YUV 420, Y, U, V plane */ - IA_CSS_FRAME_FORMAT_YUV420_16, /**< yuv420, 16 bits per subpixel */ - IA_CSS_FRAME_FORMAT_YUV422, /**< 16 bit YUV 422, Y, U, V plane */ - IA_CSS_FRAME_FORMAT_YUV422_16, /**< yuv422, 16 bits per subpixel */ - IA_CSS_FRAME_FORMAT_UYVY, /**< 16 bit YUV 422, UYVY interleaved */ - IA_CSS_FRAME_FORMAT_YUYV, /**< 16 bit YUV 422, YUYV interleaved */ - IA_CSS_FRAME_FORMAT_YUV444, /**< 24 bit YUV 444, Y, U, V plane */ - IA_CSS_FRAME_FORMAT_YUV_LINE, /**< Internal format, 2 y lines followed + IA_CSS_FRAME_FORMAT_NV11 = 0, /** 12 bit YUV 411, Y, UV plane */ + IA_CSS_FRAME_FORMAT_NV12, /** 12 bit YUV 420, Y, UV plane */ + IA_CSS_FRAME_FORMAT_NV12_16, /** 16 bit YUV 420, Y, UV plane */ + IA_CSS_FRAME_FORMAT_NV12_TILEY, /** 12 bit YUV 420, Intel proprietary tiled format, TileY */ + IA_CSS_FRAME_FORMAT_NV16, /** 16 bit YUV 422, Y, UV plane */ + IA_CSS_FRAME_FORMAT_NV21, /** 12 bit YUV 420, Y, VU plane */ + IA_CSS_FRAME_FORMAT_NV61, /** 16 bit YUV 422, Y, VU plane */ + IA_CSS_FRAME_FORMAT_YV12, /** 12 bit YUV 420, Y, V, U plane */ + IA_CSS_FRAME_FORMAT_YV16, /** 16 bit YUV 422, Y, V, U plane */ + IA_CSS_FRAME_FORMAT_YUV420, /** 12 bit YUV 420, Y, U, V plane */ + IA_CSS_FRAME_FORMAT_YUV420_16, /** yuv420, 16 bits per subpixel */ + IA_CSS_FRAME_FORMAT_YUV422, /** 16 bit YUV 422, Y, U, V plane */ + IA_CSS_FRAME_FORMAT_YUV422_16, /** yuv422, 16 bits per subpixel */ + IA_CSS_FRAME_FORMAT_UYVY, /** 16 bit YUV 422, UYVY interleaved */ + IA_CSS_FRAME_FORMAT_YUYV, /** 16 bit YUV 422, YUYV interleaved */ + IA_CSS_FRAME_FORMAT_YUV444, /** 24 bit YUV 444, Y, U, V plane */ + IA_CSS_FRAME_FORMAT_YUV_LINE, /** Internal format, 2 y lines followed by a uvinterleaved line */ - IA_CSS_FRAME_FORMAT_RAW, /**< RAW, 1 plane */ - IA_CSS_FRAME_FORMAT_RGB565, /**< 16 bit RGB, 1 plane. Each 3 sub + IA_CSS_FRAME_FORMAT_RAW, /** RAW, 1 plane */ + IA_CSS_FRAME_FORMAT_RGB565, /** 16 bit RGB, 1 plane. Each 3 sub pixels are packed into one 16 bit value, 5 bits for R, 6 bits for G and 5 bits for B. */ - IA_CSS_FRAME_FORMAT_PLANAR_RGB888, /**< 24 bit RGB, 3 planes */ - IA_CSS_FRAME_FORMAT_RGBA888, /**< 32 bit RGBA, 1 plane, A=Alpha + IA_CSS_FRAME_FORMAT_PLANAR_RGB888, /** 24 bit RGB, 3 planes */ + IA_CSS_FRAME_FORMAT_RGBA888, /** 32 bit RGBA, 1 plane, A=Alpha (alpha is unused) */ - IA_CSS_FRAME_FORMAT_QPLANE6, /**< Internal, for advanced ISP */ - IA_CSS_FRAME_FORMAT_BINARY_8, /**< byte stream, used for jpeg. For + IA_CSS_FRAME_FORMAT_QPLANE6, /** Internal, for advanced ISP */ + IA_CSS_FRAME_FORMAT_BINARY_8, /** byte stream, used for jpeg. For frames of this type, we set the height to 1 and the width to the number of allocated bytes. */ - IA_CSS_FRAME_FORMAT_MIPI, /**< MIPI frame, 1 plane */ - IA_CSS_FRAME_FORMAT_RAW_PACKED, /**< RAW, 1 plane, packed */ - IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8, /**< 8 bit per Y/U/V. + IA_CSS_FRAME_FORMAT_MIPI, /** MIPI frame, 1 plane */ + IA_CSS_FRAME_FORMAT_RAW_PACKED, /** RAW, 1 plane, packed */ + IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8, /** 8 bit per Y/U/V. Y odd line; UYVY interleaved even line */ - IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8, /**< Legacy YUV420. UY odd + IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8, /** Legacy YUV420. UY odd line; VY even line */ - IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10 /**< 10 bit per Y/U/V. Y odd + IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10 /** 10 bit per Y/U/V. Y odd line; UYVY interleaved even line */ }; @@ -95,7 +95,7 @@ enum ia_css_frame_format { /* because of issues this would cause with the Clockwork code checking tool. */ #define IA_CSS_FRAME_FORMAT_NUM (IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10 + 1) -/** Number of valid output frame formats for ISP **/ +/* Number of valid output frame formats for ISP **/ #define IA_CSS_FRAME_OUT_FORMAT_NUM (IA_CSS_FRAME_FORMAT_RGBA888 + 1) #endif /* __IA_CSS_FRAME_FORMAT_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_public.h index 92f2389176b2..ba7a076c3afa 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_public.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_public.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_FRAME_PUBLIC_H #define __IA_CSS_FRAME_PUBLIC_H -/** @file +/* @file * This file contains structs to describe various frame-formats supported by the ISP. */ @@ -25,73 +25,73 @@ #include "ia_css_frame_format.h" #include "ia_css_buffer.h" -/** For RAW input, the bayer order needs to be specified separately. There +/* For RAW input, the bayer order needs to be specified separately. There * are 4 possible orders. The name is constructed by taking the first two * colors on the first line and the first two colors from the second line. */ enum ia_css_bayer_order { - IA_CSS_BAYER_ORDER_GRBG, /**< GRGRGRGRGR .. BGBGBGBGBG */ - IA_CSS_BAYER_ORDER_RGGB, /**< RGRGRGRGRG .. GBGBGBGBGB */ - IA_CSS_BAYER_ORDER_BGGR, /**< BGBGBGBGBG .. GRGRGRGRGR */ - IA_CSS_BAYER_ORDER_GBRG, /**< GBGBGBGBGB .. RGRGRGRGRG */ + IA_CSS_BAYER_ORDER_GRBG, /** GRGRGRGRGR .. BGBGBGBGBG */ + IA_CSS_BAYER_ORDER_RGGB, /** RGRGRGRGRG .. GBGBGBGBGB */ + IA_CSS_BAYER_ORDER_BGGR, /** BGBGBGBGBG .. GRGRGRGRGR */ + IA_CSS_BAYER_ORDER_GBRG, /** GBGBGBGBGB .. RGRGRGRGRG */ }; #define IA_CSS_BAYER_ORDER_NUM (IA_CSS_BAYER_ORDER_GBRG + 1) -/** Frame plane structure. This describes one plane in an image +/* Frame plane structure. This describes one plane in an image * frame buffer. */ struct ia_css_frame_plane { - unsigned int height; /**< height of a plane in lines */ - unsigned int width; /**< width of a line, in DMA elements, note that + unsigned int height; /** height of a plane in lines */ + unsigned int width; /** width of a line, in DMA elements, note that for RGB565 the three subpixels are stored in one element. For all other formats this is the number of subpixels per line. */ - unsigned int stride; /**< stride of a line in bytes */ - unsigned int offset; /**< offset in bytes to start of frame data. + unsigned int stride; /** stride of a line in bytes */ + unsigned int offset; /** offset in bytes to start of frame data. offset is wrt data field in ia_css_frame */ }; -/** Binary "plane". This is used to story binary streams such as jpeg +/* Binary "plane". This is used to story binary streams such as jpeg * images. This is not actually a real plane. */ struct ia_css_frame_binary_plane { - unsigned int size; /**< number of bytes in the stream */ - struct ia_css_frame_plane data; /**< plane */ + unsigned int size; /** number of bytes in the stream */ + struct ia_css_frame_plane data; /** plane */ }; -/** Container for planar YUV frames. This contains 3 planes. +/* Container for planar YUV frames. This contains 3 planes. */ struct ia_css_frame_yuv_planes { - struct ia_css_frame_plane y; /**< Y plane */ - struct ia_css_frame_plane u; /**< U plane */ - struct ia_css_frame_plane v; /**< V plane */ + struct ia_css_frame_plane y; /** Y plane */ + struct ia_css_frame_plane u; /** U plane */ + struct ia_css_frame_plane v; /** V plane */ }; -/** Container for semi-planar YUV frames. +/* Container for semi-planar YUV frames. */ struct ia_css_frame_nv_planes { - struct ia_css_frame_plane y; /**< Y plane */ - struct ia_css_frame_plane uv; /**< UV plane */ + struct ia_css_frame_plane y; /** Y plane */ + struct ia_css_frame_plane uv; /** UV plane */ }; -/** Container for planar RGB frames. Each color has its own plane. +/* Container for planar RGB frames. Each color has its own plane. */ struct ia_css_frame_rgb_planes { - struct ia_css_frame_plane r; /**< Red plane */ - struct ia_css_frame_plane g; /**< Green plane */ - struct ia_css_frame_plane b; /**< Blue plane */ + struct ia_css_frame_plane r; /** Red plane */ + struct ia_css_frame_plane g; /** Green plane */ + struct ia_css_frame_plane b; /** Blue plane */ }; -/** Container for 6-plane frames. These frames are used internally +/* Container for 6-plane frames. These frames are used internally * in the advanced ISP only. */ struct ia_css_frame_plane6_planes { - struct ia_css_frame_plane r; /**< Red plane */ - struct ia_css_frame_plane r_at_b; /**< Red at blue plane */ - struct ia_css_frame_plane gr; /**< Red-green plane */ - struct ia_css_frame_plane gb; /**< Blue-green plane */ - struct ia_css_frame_plane b; /**< Blue plane */ - struct ia_css_frame_plane b_at_r; /**< Blue at red plane */ + struct ia_css_frame_plane r; /** Red plane */ + struct ia_css_frame_plane r_at_b; /** Red at blue plane */ + struct ia_css_frame_plane gr; /** Red-green plane */ + struct ia_css_frame_plane gb; /** Blue-green plane */ + struct ia_css_frame_plane b; /** Blue plane */ + struct ia_css_frame_plane b_at_r; /** Blue at red plane */ }; /* Crop info struct - stores the lines to be cropped in isp */ @@ -103,15 +103,15 @@ struct ia_css_crop_info { unsigned int start_line; }; -/** Frame info struct. This describes the contents of an image frame buffer. +/* Frame info struct. This describes the contents of an image frame buffer. */ struct ia_css_frame_info { - struct ia_css_resolution res; /**< Frame resolution (valid data) */ - unsigned int padded_width; /**< stride of line in memory (in pixels) */ - enum ia_css_frame_format format; /**< format of the frame data */ - unsigned int raw_bit_depth; /**< number of valid bits per pixel, + struct ia_css_resolution res; /** Frame resolution (valid data) */ + unsigned int padded_width; /** stride of line in memory (in pixels) */ + enum ia_css_frame_format format; /** format of the frame data */ + unsigned int raw_bit_depth; /** number of valid bits per pixel, only valid for RAW bayer frames */ - enum ia_css_bayer_order raw_bayer_order; /**< bayer order, only valid + enum ia_css_bayer_order raw_bayer_order; /** bayer order, only valid for RAW bayer frames */ /* the params below are computed based on bayer_order * we can remove the raw_bayer_order if it is redundant @@ -136,9 +136,9 @@ struct ia_css_frame_info { * Specifies the DVS loop delay in "frame periods" */ enum ia_css_frame_delay { - IA_CSS_FRAME_DELAY_0, /**< Frame delay = 0 */ - IA_CSS_FRAME_DELAY_1, /**< Frame delay = 1 */ - IA_CSS_FRAME_DELAY_2 /**< Frame delay = 2 */ + IA_CSS_FRAME_DELAY_0, /** Frame delay = 0 */ + IA_CSS_FRAME_DELAY_1, /** Frame delay = 1 */ + IA_CSS_FRAME_DELAY_2 /** Frame delay = 2 */ }; enum ia_css_frame_flash_state { @@ -147,13 +147,13 @@ enum ia_css_frame_flash_state { IA_CSS_FRAME_FLASH_STATE_FULL }; -/** Frame structure. This structure describes an image buffer or frame. +/* Frame structure. This structure describes an image buffer or frame. * This is the main structure used for all input and output images. */ struct ia_css_frame { - struct ia_css_frame_info info; /**< info struct describing the frame */ - ia_css_ptr data; /**< pointer to start of image data */ - unsigned int data_bytes; /**< size of image data in bytes */ + struct ia_css_frame_info info; /** info struct describing the frame */ + ia_css_ptr data; /** pointer to start of image data */ + unsigned int data_bytes; /** size of image data in bytes */ /* LA: move this to ia_css_buffer */ /* * -1 if data address is static during life time of pipeline @@ -171,10 +171,10 @@ struct ia_css_frame { enum ia_css_buffer_type buf_type; enum ia_css_frame_flash_state flash_state; unsigned int exp_id; - /**< exposure id, see ia_css_event_public.h for more detail */ - uint32_t isp_config_id; /**< Unique ID to track which config was actually applied to a particular frame */ - bool valid; /**< First video output frame is not valid */ - bool contiguous; /**< memory is allocated physically contiguously */ + /** exposure id, see ia_css_event_public.h for more detail */ + uint32_t isp_config_id; /** Unique ID to track which config was actually applied to a particular frame */ + bool valid; /** First video output frame is not valid */ + bool contiguous; /** memory is allocated physically contiguously */ union { unsigned int _initialisation_dummy; struct ia_css_frame_plane raw; @@ -185,7 +185,7 @@ struct ia_css_frame { struct ia_css_frame_nv_planes nv; struct ia_css_frame_plane6_planes plane6; struct ia_css_frame_binary_plane binary; - } planes; /**< frame planes, select the right one based on + } planes; /** frame planes, select the right one based on info.format */ }; @@ -204,7 +204,7 @@ struct ia_css_frame { { 0 } /* planes */ \ } -/** @brief Fill a frame with zeros +/* @brief Fill a frame with zeros * * @param frame The frame. * @return None @@ -213,7 +213,7 @@ struct ia_css_frame { */ void ia_css_frame_zero(struct ia_css_frame *frame); -/** @brief Allocate a CSS frame structure +/* @brief Allocate a CSS frame structure * * @param frame The allocated frame. * @param width The width (in pixels) of the frame. @@ -234,7 +234,7 @@ ia_css_frame_allocate(struct ia_css_frame **frame, unsigned int stride, unsigned int raw_bit_depth); -/** @brief Allocate a CSS frame structure using a frame info structure. +/* @brief Allocate a CSS frame structure using a frame info structure. * * @param frame The allocated frame. * @param[in] info The frame info structure. @@ -247,7 +247,7 @@ ia_css_frame_allocate(struct ia_css_frame **frame, enum ia_css_err ia_css_frame_allocate_from_info(struct ia_css_frame **frame, const struct ia_css_frame_info *info); -/** @brief Free a CSS frame structure. +/* @brief Free a CSS frame structure. * * @param[in] frame Pointer to the frame. * @return None @@ -258,7 +258,7 @@ ia_css_frame_allocate_from_info(struct ia_css_frame **frame, void ia_css_frame_free(struct ia_css_frame *frame); -/** @brief Allocate a contiguous CSS frame structure +/* @brief Allocate a contiguous CSS frame structure * * @param frame The allocated frame. * @param width The width (in pixels) of the frame. @@ -280,7 +280,7 @@ ia_css_frame_allocate_contiguous(struct ia_css_frame **frame, unsigned int stride, unsigned int raw_bit_depth); -/** @brief Allocate a contiguous CSS frame from a frame info structure. +/* @brief Allocate a contiguous CSS frame from a frame info structure. * * @param frame The allocated frame. * @param[in] info The frame info structure. @@ -296,7 +296,7 @@ enum ia_css_err ia_css_frame_allocate_contiguous_from_info(struct ia_css_frame **frame, const struct ia_css_frame_info *info); -/** @brief Allocate a CSS frame structure using a frame info structure. +/* @brief Allocate a CSS frame structure using a frame info structure. * * @param frame The allocated frame. * @param[in] info The frame info structure. @@ -309,7 +309,7 @@ enum ia_css_err ia_css_frame_create_from_info(struct ia_css_frame **frame, const struct ia_css_frame_info *info); -/** @brief Set a mapped data buffer to a CSS frame +/* @brief Set a mapped data buffer to a CSS frame * * @param[in] frame Valid CSS frame pointer * @param[in] mapped_data Mapped data buffer to be assigned to the CSS frame @@ -327,7 +327,7 @@ ia_css_frame_set_data(struct ia_css_frame *frame, const ia_css_ptr mapped_data, size_t data_size_bytes); -/** @brief Map an existing frame data pointer to a CSS frame. +/* @brief Map an existing frame data pointer to a CSS frame. * * @param frame Pointer to the frame to be initialized * @param[in] info The frame info. @@ -350,7 +350,7 @@ ia_css_frame_map(struct ia_css_frame **frame, uint16_t attribute, void *context); -/** @brief Unmap a CSS frame structure. +/* @brief Unmap a CSS frame structure. * * @param[in] frame Pointer to the CSS frame. * @return None diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_input_port.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_input_port.h index 8a17c3346caa..f415570a3da9 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_input_port.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_input_port.h @@ -15,11 +15,11 @@ #ifndef __IA_CSS_INPUT_PORT_H #define __IA_CSS_INPUT_PORT_H -/** @file +/* @file * This file contains information about the possible input ports for CSS */ -/** Enumeration of the physical input ports on the CSS hardware. +/* Enumeration of the physical input ports on the CSS hardware. * There are 3 MIPI CSI-2 ports. */ enum ia_css_csi2_port { @@ -28,39 +28,39 @@ enum ia_css_csi2_port { IA_CSS_CSI2_PORT2 /* Implicitly map to MIPI_PORT2_ID */ }; -/** Backward compatible for CSS API 2.0 only +/* Backward compatible for CSS API 2.0 only * TO BE REMOVED when all drivers move to CSS API 2.1 */ #define IA_CSS_CSI2_PORT_4LANE IA_CSS_CSI2_PORT0 #define IA_CSS_CSI2_PORT_1LANE IA_CSS_CSI2_PORT1 #define IA_CSS_CSI2_PORT_2LANE IA_CSS_CSI2_PORT2 -/** The CSI2 interface supports 2 types of compression or can +/* The CSI2 interface supports 2 types of compression or can * be run without compression. */ enum ia_css_csi2_compression_type { - IA_CSS_CSI2_COMPRESSION_TYPE_NONE, /**< No compression */ - IA_CSS_CSI2_COMPRESSION_TYPE_1, /**< Compression scheme 1 */ - IA_CSS_CSI2_COMPRESSION_TYPE_2 /**< Compression scheme 2 */ + IA_CSS_CSI2_COMPRESSION_TYPE_NONE, /** No compression */ + IA_CSS_CSI2_COMPRESSION_TYPE_1, /** Compression scheme 1 */ + IA_CSS_CSI2_COMPRESSION_TYPE_2 /** Compression scheme 2 */ }; struct ia_css_csi2_compression { enum ia_css_csi2_compression_type type; - /**< Compression used */ + /** Compression used */ unsigned int compressed_bits_per_pixel; - /**< Compressed bits per pixel (only when compression is enabled) */ + /** Compressed bits per pixel (only when compression is enabled) */ unsigned int uncompressed_bits_per_pixel; - /**< Uncompressed bits per pixel (only when compression is enabled) */ + /** Uncompressed bits per pixel (only when compression is enabled) */ }; -/** Input port structure. +/* Input port structure. */ struct ia_css_input_port { - enum ia_css_csi2_port port; /**< Physical CSI-2 port */ - unsigned int num_lanes; /**< Number of lanes used (4-lane port only) */ - unsigned int timeout; /**< Timeout value */ - unsigned int rxcount; /**< Register value, should include all lanes */ - struct ia_css_csi2_compression compression; /**< Compression used */ + enum ia_css_csi2_port port; /** Physical CSI-2 port */ + unsigned int num_lanes; /** Number of lanes used (4-lane port only) */ + unsigned int timeout; /** Timeout value */ + unsigned int rxcount; /** Register value, should include all lanes */ + struct ia_css_csi2_compression compression; /** Compression used */ }; #endif /* __IA_CSS_INPUT_PORT_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_irq.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_irq.h index 416ca4d28732..10ef61178bb2 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_irq.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_irq.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_IRQ_H #define __IA_CSS_IRQ_H -/** @file +/* @file * This file contains information for Interrupts/IRQs from CSS */ @@ -23,14 +23,14 @@ #include "ia_css_pipe_public.h" #include "ia_css_input_port.h" -/** Interrupt types, these enumerate all supported interrupt types. +/* Interrupt types, these enumerate all supported interrupt types. */ enum ia_css_irq_type { - IA_CSS_IRQ_TYPE_EDGE, /**< Edge (level) sensitive interrupt */ - IA_CSS_IRQ_TYPE_PULSE /**< Pulse-shaped interrupt */ + IA_CSS_IRQ_TYPE_EDGE, /** Edge (level) sensitive interrupt */ + IA_CSS_IRQ_TYPE_PULSE /** Pulse-shaped interrupt */ }; -/** Interrupt request type. +/* Interrupt request type. * When the CSS hardware generates an interrupt, a function in this API * needs to be called to retrieve information about the interrupt. * This interrupt type is part of this information and indicates what @@ -46,55 +46,55 @@ enum ia_css_irq_type { */ enum ia_css_irq_info { IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR = 1 << 0, - /**< the css receiver has encountered an error */ + /** the css receiver has encountered an error */ IA_CSS_IRQ_INFO_CSS_RECEIVER_FIFO_OVERFLOW = 1 << 1, - /**< the FIFO in the csi receiver has overflown */ + /** the FIFO in the csi receiver has overflown */ IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF = 1 << 2, - /**< the css receiver received the start of frame */ + /** the css receiver received the start of frame */ IA_CSS_IRQ_INFO_CSS_RECEIVER_EOF = 1 << 3, - /**< the css receiver received the end of frame */ + /** the css receiver received the end of frame */ IA_CSS_IRQ_INFO_CSS_RECEIVER_SOL = 1 << 4, - /**< the css receiver received the start of line */ + /** the css receiver received the start of line */ IA_CSS_IRQ_INFO_PSYS_EVENTS_READY = 1 << 5, - /**< One or more events are available in the PSYS event queue */ + /** One or more events are available in the PSYS event queue */ IA_CSS_IRQ_INFO_EVENTS_READY = IA_CSS_IRQ_INFO_PSYS_EVENTS_READY, - /**< deprecated{obsolete version of IA_CSS_IRQ_INFO_PSYS_EVENTS_READY, + /** deprecated{obsolete version of IA_CSS_IRQ_INFO_PSYS_EVENTS_READY, * same functionality.} */ IA_CSS_IRQ_INFO_CSS_RECEIVER_EOL = 1 << 6, - /**< the css receiver received the end of line */ + /** the css receiver received the end of line */ IA_CSS_IRQ_INFO_CSS_RECEIVER_SIDEBAND_CHANGED = 1 << 7, - /**< the css receiver received a change in side band signals */ + /** the css receiver received a change in side band signals */ IA_CSS_IRQ_INFO_CSS_RECEIVER_GEN_SHORT_0 = 1 << 8, - /**< generic short packets (0) */ + /** generic short packets (0) */ IA_CSS_IRQ_INFO_CSS_RECEIVER_GEN_SHORT_1 = 1 << 9, - /**< generic short packets (1) */ + /** generic short packets (1) */ IA_CSS_IRQ_INFO_IF_PRIM_ERROR = 1 << 10, - /**< the primary input formatter (A) has encountered an error */ + /** the primary input formatter (A) has encountered an error */ IA_CSS_IRQ_INFO_IF_PRIM_B_ERROR = 1 << 11, - /**< the primary input formatter (B) has encountered an error */ + /** the primary input formatter (B) has encountered an error */ IA_CSS_IRQ_INFO_IF_SEC_ERROR = 1 << 12, - /**< the secondary input formatter has encountered an error */ + /** the secondary input formatter has encountered an error */ IA_CSS_IRQ_INFO_STREAM_TO_MEM_ERROR = 1 << 13, - /**< the stream-to-memory device has encountered an error */ + /** the stream-to-memory device has encountered an error */ IA_CSS_IRQ_INFO_SW_0 = 1 << 14, - /**< software interrupt 0 */ + /** software interrupt 0 */ IA_CSS_IRQ_INFO_SW_1 = 1 << 15, - /**< software interrupt 1 */ + /** software interrupt 1 */ IA_CSS_IRQ_INFO_SW_2 = 1 << 16, - /**< software interrupt 2 */ + /** software interrupt 2 */ IA_CSS_IRQ_INFO_ISP_BINARY_STATISTICS_READY = 1 << 17, - /**< ISP binary statistics are ready */ + /** ISP binary statistics are ready */ IA_CSS_IRQ_INFO_INPUT_SYSTEM_ERROR = 1 << 18, - /**< the input system in in error */ + /** the input system in in error */ IA_CSS_IRQ_INFO_IF_ERROR = 1 << 19, - /**< the input formatter in in error */ + /** the input formatter in in error */ IA_CSS_IRQ_INFO_DMA_ERROR = 1 << 20, - /**< the dma in in error */ + /** the dma in in error */ IA_CSS_IRQ_INFO_ISYS_EVENTS_READY = 1 << 21, - /**< end-of-frame events are ready in the isys_event queue */ + /** end-of-frame events are ready in the isys_event queue */ }; -/** CSS receiver error types. Whenever the CSS receiver has encountered +/* CSS receiver error types. Whenever the CSS receiver has encountered * an error, this enumeration is used to indicate which errors have occurred. * * Note that multiple error flags can be enabled at once and that this is in @@ -105,39 +105,39 @@ enum ia_css_irq_info { * different receiver types, or possibly none in case of tests systems. */ enum ia_css_rx_irq_info { - IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN = 1U << 0, /**< buffer overrun */ - IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE = 1U << 1, /**< entering sleep mode */ - IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE = 1U << 2, /**< exited sleep mode */ - IA_CSS_RX_IRQ_INFO_ECC_CORRECTED = 1U << 3, /**< ECC corrected */ + IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN = 1U << 0, /** buffer overrun */ + IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE = 1U << 1, /** entering sleep mode */ + IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE = 1U << 2, /** exited sleep mode */ + IA_CSS_RX_IRQ_INFO_ECC_CORRECTED = 1U << 3, /** ECC corrected */ IA_CSS_RX_IRQ_INFO_ERR_SOT = 1U << 4, - /**< Start of transmission */ - IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC = 1U << 5, /**< SOT sync (??) */ - IA_CSS_RX_IRQ_INFO_ERR_CONTROL = 1U << 6, /**< Control (??) */ - IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE = 1U << 7, /**< Double ECC */ - IA_CSS_RX_IRQ_INFO_ERR_CRC = 1U << 8, /**< CRC error */ - IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID = 1U << 9, /**< Unknown ID */ - IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC = 1U << 10,/**< Frame sync error */ - IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA = 1U << 11,/**< Frame data error */ - IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT = 1U << 12,/**< Timeout occurred */ - IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC = 1U << 13,/**< Unknown escape seq. */ - IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC = 1U << 14,/**< Line Sync error */ + /** Start of transmission */ + IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC = 1U << 5, /** SOT sync (??) */ + IA_CSS_RX_IRQ_INFO_ERR_CONTROL = 1U << 6, /** Control (??) */ + IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE = 1U << 7, /** Double ECC */ + IA_CSS_RX_IRQ_INFO_ERR_CRC = 1U << 8, /** CRC error */ + IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID = 1U << 9, /** Unknown ID */ + IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC = 1U << 10,/** Frame sync error */ + IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA = 1U << 11,/** Frame data error */ + IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT = 1U << 12,/** Timeout occurred */ + IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC = 1U << 13,/** Unknown escape seq. */ + IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC = 1U << 14,/** Line Sync error */ IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT = 1U << 15, }; -/** Interrupt info structure. This structure contains information about an +/* Interrupt info structure. This structure contains information about an * interrupt. This needs to be used after an interrupt is received on the IA * to perform the correct action. */ struct ia_css_irq { - enum ia_css_irq_info type; /**< Interrupt type. */ - unsigned int sw_irq_0_val; /**< In case of SW interrupt 0, value. */ - unsigned int sw_irq_1_val; /**< In case of SW interrupt 1, value. */ - unsigned int sw_irq_2_val; /**< In case of SW interrupt 2, value. */ + enum ia_css_irq_info type; /** Interrupt type. */ + unsigned int sw_irq_0_val; /** In case of SW interrupt 0, value. */ + unsigned int sw_irq_1_val; /** In case of SW interrupt 1, value. */ + unsigned int sw_irq_2_val; /** In case of SW interrupt 2, value. */ struct ia_css_pipe *pipe; - /**< The image pipe that generated the interrupt. */ + /** The image pipe that generated the interrupt. */ }; -/** @brief Obtain interrupt information. +/* @brief Obtain interrupt information. * * @param[out] info Pointer to the interrupt info. The interrupt * information wil be written to this info. @@ -154,7 +154,7 @@ struct ia_css_irq { enum ia_css_err ia_css_irq_translate(unsigned int *info); -/** @brief Get CSI receiver error info. +/* @brief Get CSI receiver error info. * * @param[out] irq_bits Pointer to the interrupt bits. The interrupt * bits will be written this info. @@ -172,7 +172,7 @@ ia_css_irq_translate(unsigned int *info); void ia_css_rx_get_irq_info(unsigned int *irq_bits); -/** @brief Get CSI receiver error info. +/* @brief Get CSI receiver error info. * * @param[in] port Input port identifier. * @param[out] irq_bits Pointer to the interrupt bits. The interrupt @@ -188,7 +188,7 @@ ia_css_rx_get_irq_info(unsigned int *irq_bits); void ia_css_rx_port_get_irq_info(enum ia_css_csi2_port port, unsigned int *irq_bits); -/** @brief Clear CSI receiver error info. +/* @brief Clear CSI receiver error info. * * @param[in] irq_bits The bits that should be cleared from the CSI receiver * interrupt bits register. @@ -205,7 +205,7 @@ ia_css_rx_port_get_irq_info(enum ia_css_csi2_port port, unsigned int *irq_bits); void ia_css_rx_clear_irq_info(unsigned int irq_bits); -/** @brief Clear CSI receiver error info. +/* @brief Clear CSI receiver error info. * * @param[in] port Input port identifier. * @param[in] irq_bits The bits that should be cleared from the CSI receiver @@ -220,7 +220,7 @@ ia_css_rx_clear_irq_info(unsigned int irq_bits); void ia_css_rx_port_clear_irq_info(enum ia_css_csi2_port port, unsigned int irq_bits); -/** @brief Enable or disable specific interrupts. +/* @brief Enable or disable specific interrupts. * * @param[in] type The interrupt type that will be enabled/disabled. * @param[in] enable enable or disable. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_metadata.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_metadata.h index c40c5a19bfe1..8b674c98224c 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_metadata.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_metadata.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_METADATA_H #define __IA_CSS_METADATA_H -/** @file +/* @file * This file contains structure for processing sensor metadata. */ @@ -23,32 +23,32 @@ #include "ia_css_types.h" #include "ia_css_stream_format.h" -/** Metadata configuration. This data structure contains necessary info +/* Metadata configuration. This data structure contains necessary info * to process sensor metadata. */ struct ia_css_metadata_config { - enum ia_css_stream_format data_type; /**< Data type of CSI-2 embedded + enum ia_css_stream_format data_type; /** Data type of CSI-2 embedded data. The default value is IA_CSS_STREAM_FORMAT_EMBEDDED. For certain sensors, user can choose non-default data type for embedded data. */ - struct ia_css_resolution resolution; /**< Resolution */ + struct ia_css_resolution resolution; /** Resolution */ }; struct ia_css_metadata_info { - struct ia_css_resolution resolution; /**< Resolution */ - uint32_t stride; /**< Stride in bytes */ - uint32_t size; /**< Total size in bytes */ + struct ia_css_resolution resolution; /** Resolution */ + uint32_t stride; /** Stride in bytes */ + uint32_t size; /** Total size in bytes */ }; struct ia_css_metadata { - struct ia_css_metadata_info info; /**< Layout info */ - ia_css_ptr address; /**< CSS virtual address */ + struct ia_css_metadata_info info; /** Layout info */ + ia_css_ptr address; /** CSS virtual address */ uint32_t exp_id; - /**< Exposure ID, see ia_css_event_public.h for more detail */ + /** Exposure ID, see ia_css_event_public.h for more detail */ }; #define SIZE_OF_IA_CSS_METADATA_STRUCT sizeof(struct ia_css_metadata) -/** @brief Allocate a metadata buffer. +/* @brief Allocate a metadata buffer. * @param[in] metadata_info Metadata info struct, contains details on metadata buffers. * @return Pointer of metadata buffer or NULL (if error) * @@ -58,7 +58,7 @@ struct ia_css_metadata { struct ia_css_metadata * ia_css_metadata_allocate(const struct ia_css_metadata_info *metadata_info); -/** @brief Free a metadata buffer. +/* @brief Free a metadata buffer. * * @param[in] metadata Pointer of metadata buffer. * @return None diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mipi.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mipi.h index fd2c01b60b28..f9c9cd76be97 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mipi.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mipi.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_MIPI_H #define __IA_CSS_MIPI_H -/** @file +/* @file * This file contains MIPI support functionality */ @@ -24,10 +24,10 @@ #include "ia_css_stream_format.h" #include "ia_css_input_port.h" -/** Backward compatible for CSS API 2.0 only +/* Backward compatible for CSS API 2.0 only * TO BE REMOVED when all drivers move to CSS API 2.1. */ -/** @brief Specify a CSS MIPI frame buffer. +/* @brief Specify a CSS MIPI frame buffer. * * @param[in] size_mem_words The frame size in memory words (32B). * @param[in] contiguous Allocate memory physically contiguously or not. @@ -42,7 +42,7 @@ ia_css_mipi_frame_specify(const unsigned int size_mem_words, const bool contiguous); #if !defined(HAS_NO_INPUT_SYSTEM) -/** @brief Register size of a CSS MIPI frame for check during capturing. +/* @brief Register size of a CSS MIPI frame for check during capturing. * * @param[in] port CSI-2 port this check is registered. * @param[in] size_mem_words The frame size in memory words (32B). @@ -59,7 +59,7 @@ ia_css_mipi_frame_enable_check_on_size(const enum ia_css_csi2_port port, const unsigned int size_mem_words); #endif -/** @brief Calculate the size of a mipi frame. +/* @brief Calculate the size of a mipi frame. * * @param[in] width The width (in pixels) of the frame. * @param[in] height The height (in lines) of the frame. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mmu.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mmu.h index 48f8855d61f6..13c21056bfbf 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mmu.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mmu.h @@ -15,11 +15,11 @@ #ifndef __IA_CSS_MMU_H #define __IA_CSS_MMU_H -/** @file +/* @file * This file contains one support function for invalidating the CSS MMU cache */ -/** @brief Invalidate the MMU internal cache. +/* @brief Invalidate the MMU internal cache. * @return None * * This function triggers an invalidation of the translate-look-aside diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_morph.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_morph.h index 969840da52b2..de409638d009 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_morph.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_morph.h @@ -15,13 +15,13 @@ #ifndef __IA_CSS_MORPH_H #define __IA_CSS_MORPH_H -/** @file +/* @file * This file contains supporting for morphing table */ #include -/** @brief Morphing table +/* @brief Morphing table * @param[in] width Width of the morphing table. * @param[in] height Height of the morphing table. * @return Pointer to the morphing table @@ -29,7 +29,7 @@ struct ia_css_morph_table * ia_css_morph_table_allocate(unsigned int width, unsigned int height); -/** @brief Free the morph table +/* @brief Free the morph table * @param[in] me Pointer to the morph table. * @return None */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_pipe_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_pipe_public.h index 733e0ef3afe8..df0aad9a6ab9 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_pipe_public.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_pipe_public.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_PIPE_PUBLIC_H #define __IA_CSS_PIPE_PUBLIC_H -/** @file +/* @file * This file contains the public interface for CSS pipes. */ @@ -34,7 +34,7 @@ enum { IA_CSS_PIPE_MAX_OUTPUT_STAGE, }; -/** Enumeration of pipe modes. This mode can be used to create +/* Enumeration of pipe modes. This mode can be used to create * an image pipe for this mode. These pipes can be combined * to configure and run streams on the ISP. * @@ -42,12 +42,12 @@ enum { * create a continuous capture stream. */ enum ia_css_pipe_mode { - IA_CSS_PIPE_MODE_PREVIEW, /**< Preview pipe */ - IA_CSS_PIPE_MODE_VIDEO, /**< Video pipe */ - IA_CSS_PIPE_MODE_CAPTURE, /**< Still capture pipe */ - IA_CSS_PIPE_MODE_ACC, /**< Accelerated pipe */ - IA_CSS_PIPE_MODE_COPY, /**< Copy pipe, only used for embedded/image data copying */ - IA_CSS_PIPE_MODE_YUVPP, /**< YUV post processing pipe, used for all use cases with YUV input, + IA_CSS_PIPE_MODE_PREVIEW, /** Preview pipe */ + IA_CSS_PIPE_MODE_VIDEO, /** Video pipe */ + IA_CSS_PIPE_MODE_CAPTURE, /** Still capture pipe */ + IA_CSS_PIPE_MODE_ACC, /** Accelerated pipe */ + IA_CSS_PIPE_MODE_COPY, /** Copy pipe, only used for embedded/image data copying */ + IA_CSS_PIPE_MODE_YUVPP, /** YUV post processing pipe, used for all use cases with YUV input, for SoC sensor and external ISP */ }; /* Temporary define */ @@ -58,10 +58,10 @@ enum ia_css_pipe_mode { * the order should match with definition in sh_css_defs.h */ enum ia_css_pipe_version { - IA_CSS_PIPE_VERSION_1 = 1, /**< ISP1.0 pipe */ - IA_CSS_PIPE_VERSION_2_2 = 2, /**< ISP2.2 pipe */ - IA_CSS_PIPE_VERSION_2_6_1 = 3, /**< ISP2.6.1 pipe */ - IA_CSS_PIPE_VERSION_2_7 = 4 /**< ISP2.7 pipe */ + IA_CSS_PIPE_VERSION_1 = 1, /** ISP1.0 pipe */ + IA_CSS_PIPE_VERSION_2_2 = 2, /** ISP2.2 pipe */ + IA_CSS_PIPE_VERSION_2_6_1 = 3, /** ISP2.6.1 pipe */ + IA_CSS_PIPE_VERSION_2_7 = 4 /** ISP2.7 pipe */ }; /** @@ -71,79 +71,79 @@ enum ia_css_pipe_version { */ struct ia_css_pipe_config { enum ia_css_pipe_mode mode; - /**< mode, indicates which mode the pipe should use. */ + /** mode, indicates which mode the pipe should use. */ enum ia_css_pipe_version isp_pipe_version; - /**< pipe version, indicates which imaging pipeline the pipe should use. */ + /** pipe version, indicates which imaging pipeline the pipe should use. */ struct ia_css_resolution input_effective_res; - /**< input effective resolution */ + /** input effective resolution */ struct ia_css_resolution bayer_ds_out_res; - /**< bayer down scaling */ + /** bayer down scaling */ struct ia_css_resolution capt_pp_in_res; #ifndef ISP2401 - /**< bayer down scaling */ + /** bayer down scaling */ #else - /**< capture post processing input resolution */ + /** capture post processing input resolution */ #endif struct ia_css_resolution vf_pp_in_res; #ifndef ISP2401 - /**< bayer down scaling */ + /** bayer down scaling */ #else - /**< view finder post processing input resolution */ + /** view finder post processing input resolution */ struct ia_css_resolution output_system_in_res; - /**< For IPU3 only: use output_system_in_res to specify what input resolution + /** For IPU3 only: use output_system_in_res to specify what input resolution will OSYS receive, this resolution is equal to the output resolution of GDC if not determined CSS will set output_system_in_res with main osys output pin resolution All other IPUs may ignore this property */ #endif struct ia_css_resolution dvs_crop_out_res; - /**< dvs crop, video only, not in use yet. Use dvs_envelope below. */ + /** dvs crop, video only, not in use yet. Use dvs_envelope below. */ struct ia_css_frame_info output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; - /**< output of YUV scaling */ + /** output of YUV scaling */ struct ia_css_frame_info vf_output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; - /**< output of VF YUV scaling */ + /** output of VF YUV scaling */ struct ia_css_fw_info *acc_extension; - /**< Pipeline extension accelerator */ + /** Pipeline extension accelerator */ struct ia_css_fw_info **acc_stages; - /**< Standalone accelerator stages */ + /** Standalone accelerator stages */ uint32_t num_acc_stages; - /**< Number of standalone accelerator stages */ + /** Number of standalone accelerator stages */ struct ia_css_capture_config default_capture_config; - /**< Default capture config for initial capture pipe configuration. */ - struct ia_css_resolution dvs_envelope; /**< temporary */ + /** Default capture config for initial capture pipe configuration. */ + struct ia_css_resolution dvs_envelope; /** temporary */ enum ia_css_frame_delay dvs_frame_delay; - /**< indicates the DVS loop delay in frame periods */ + /** indicates the DVS loop delay in frame periods */ int acc_num_execs; - /**< For acceleration pipes only: determine how many times the pipe + /** For acceleration pipes only: determine how many times the pipe should be run. Setting this to -1 means it will run until stopped. */ bool enable_dz; - /**< Disabling digital zoom for a pipeline, if this is set to false, + /** Disabling digital zoom for a pipeline, if this is set to false, then setting a zoom factor will have no effect. In some use cases this provides better performance. */ bool enable_dpc; - /**< Disabling "Defect Pixel Correction" for a pipeline, if this is set + /** Disabling "Defect Pixel Correction" for a pipeline, if this is set to false. In some use cases this provides better performance. */ bool enable_vfpp_bci; - /**< Enabling BCI mode will cause yuv_scale binary to be picked up + /** Enabling BCI mode will cause yuv_scale binary to be picked up instead of vf_pp. This only applies to viewfinder post processing stages. */ #ifdef ISP2401 bool enable_luma_only; - /**< Enabling of monochrome mode for a pipeline. If enabled only luma processing + /** Enabling of monochrome mode for a pipeline. If enabled only luma processing will be done. */ bool enable_tnr; - /**< Enabling of TNR (temporal noise reduction). This is only applicable to video + /** Enabling of TNR (temporal noise reduction). This is only applicable to video pipes. Non video-pipes should always set this parameter to false. */ #endif struct ia_css_isp_config *p_isp_config; - /**< Pointer to ISP configuration */ + /** Pointer to ISP configuration */ struct ia_css_resolution gdc_in_buffer_res; - /**< GDC in buffer resolution. */ + /** GDC in buffer resolution. */ struct ia_css_point gdc_in_buffer_offset; - /**< GDC in buffer offset - indicates the pixel coordinates of the first valid pixel inside the buffer */ + /** GDC in buffer offset - indicates the pixel coordinates of the first valid pixel inside the buffer */ #ifdef ISP2401 struct ia_css_coordinate internal_frame_origin_bqs_on_sctbl; - /**< Origin of internal frame positioned on shading table at shading correction in ISP. + /** Origin of internal frame positioned on shading table at shading correction in ISP. NOTE: Shading table is larger than or equal to internal frame. Shading table has shading gains and internal frame has bayer data. The origin of internal frame is used in shading correction in ISP @@ -228,20 +228,20 @@ struct ia_css_pipe_config { #endif -/** Pipe info, this struct describes properties of a pipe after it's stream has +/* Pipe info, this struct describes properties of a pipe after it's stream has * been created. * ~~~** DO NOT ADD NEW FIELD **~~~ This structure will be deprecated. * - On the Behalf of CSS-API Committee. */ struct ia_css_pipe_info { struct ia_css_frame_info output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; - /**< Info about output resolution. This contains the stride which + /** Info about output resolution. This contains the stride which should be used for memory allocation. */ struct ia_css_frame_info vf_output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; - /**< Info about viewfinder output resolution (optional). This contains + /** Info about viewfinder output resolution (optional). This contains the stride that should be used for memory allocation. */ struct ia_css_frame_info raw_output_info; - /**< Raw output resolution. This indicates the resolution of the + /** Raw output resolution. This indicates the resolution of the RAW bayer output for pipes that support this. Currently, only the still capture pipes support this feature. When this resolution is smaller than the input resolution, cropping will be performed by @@ -252,17 +252,17 @@ struct ia_css_pipe_info { the input resolution - 8x8. */ #ifdef ISP2401 struct ia_css_resolution output_system_in_res_info; - /**< For IPU3 only. Info about output system in resolution which is considered + /** For IPU3 only. Info about output system in resolution which is considered as gdc out resolution. */ #endif struct ia_css_shading_info shading_info; - /**< After an image pipe is created, this field will contain the info + /** After an image pipe is created, this field will contain the info for the shading correction. */ struct ia_css_grid_info grid_info; - /**< After an image pipe is created, this field will contain the grid + /** After an image pipe is created, this field will contain the grid info for 3A and DVS. */ int num_invalid_frames; - /**< The very first frames in a started stream do not contain valid data. + /** The very first frames in a started stream do not contain valid data. In this field, the CSS-firmware communicates to the host-driver how many initial frames will contain invalid data; this allows the host-driver to discard those initial invalid frames and start it's @@ -299,7 +299,7 @@ struct ia_css_pipe_info { #endif -/** @brief Load default pipe configuration +/* @brief Load default pipe configuration * @param[out] pipe_config The pipe configuration. * @return None * @@ -334,7 +334,7 @@ struct ia_css_pipe_info { */ void ia_css_pipe_config_defaults(struct ia_css_pipe_config *pipe_config); -/** @brief Create a pipe +/* @brief Create a pipe * @param[in] config The pipe configuration. * @param[out] pipe The pipe. * @return IA_CSS_SUCCESS or the error code. @@ -346,7 +346,7 @@ enum ia_css_err ia_css_pipe_create(const struct ia_css_pipe_config *config, struct ia_css_pipe **pipe); -/** @brief Destroy a pipe +/* @brief Destroy a pipe * @param[in] pipe The pipe. * @return IA_CSS_SUCCESS or the error code. * @@ -355,7 +355,7 @@ ia_css_pipe_create(const struct ia_css_pipe_config *config, enum ia_css_err ia_css_pipe_destroy(struct ia_css_pipe *pipe); -/** @brief Provides information about a pipe +/* @brief Provides information about a pipe * @param[in] pipe The pipe. * @param[out] pipe_info The pipe information. * @return IA_CSS_SUCCESS or IA_CSS_ERR_INVALID_ARGUMENTS. @@ -366,7 +366,7 @@ enum ia_css_err ia_css_pipe_get_info(const struct ia_css_pipe *pipe, struct ia_css_pipe_info *pipe_info); -/** @brief Configure a pipe with filter coefficients. +/* @brief Configure a pipe with filter coefficients. * @param[in] pipe The pipe. * @param[in] config The pointer to ISP configuration. * @return IA_CSS_SUCCESS or error code upon error. @@ -378,7 +378,7 @@ enum ia_css_err ia_css_pipe_set_isp_config(struct ia_css_pipe *pipe, struct ia_css_isp_config *config); -/** @brief Controls when the Event generator raises an IRQ to the Host. +/* @brief Controls when the Event generator raises an IRQ to the Host. * * @param[in] pipe The pipe. * @param[in] or_mask Binary or of enum ia_css_event_irq_mask_type. Each pipe @@ -455,7 +455,7 @@ ia_css_pipe_set_irq_mask(struct ia_css_pipe *pipe, unsigned int or_mask, unsigned int and_mask); -/** @brief Reads the current event IRQ mask from the CSS. +/* @brief Reads the current event IRQ mask from the CSS. * * @param[in] pipe The pipe. * @param[out] or_mask Current or_mask. The bits in this mask are a binary or @@ -476,7 +476,7 @@ ia_css_event_get_irq_mask(const struct ia_css_pipe *pipe, unsigned int *or_mask, unsigned int *and_mask); -/** @brief Queue a buffer for an image pipe. +/* @brief Queue a buffer for an image pipe. * * @param[in] pipe The pipe that will own the buffer. * @param[in] buffer Pointer to the buffer. @@ -498,7 +498,7 @@ enum ia_css_err ia_css_pipe_enqueue_buffer(struct ia_css_pipe *pipe, const struct ia_css_buffer *buffer); -/** @brief Dequeue a buffer from an image pipe. +/* @brief Dequeue a buffer from an image pipe. * * @param[in] pipe The pipeline that the buffer queue belongs to. * @param[in,out] buffer The buffer is used to lookup the type which determines @@ -519,7 +519,7 @@ ia_css_pipe_dequeue_buffer(struct ia_css_pipe *pipe, struct ia_css_buffer *buffer); -/** @brief Set the state (Enable or Disable) of the Extension stage in the +/* @brief Set the state (Enable or Disable) of the Extension stage in the * given pipe. * @param[in] pipe Pipe handle. * @param[in] fw_handle Extension firmware Handle (ia_css_fw_info.handle) @@ -546,7 +546,7 @@ ia_css_pipe_set_qos_ext_state (struct ia_css_pipe *pipe, uint32_t fw_handle, bool enable); -/** @brief Get the state (Enable or Disable) of the Extension stage in the +/* @brief Get the state (Enable or Disable) of the Extension stage in the * given pipe. * @param[in] pipe Pipe handle. * @param[in] fw_handle Extension firmware Handle (ia_css_fw_info.handle) @@ -573,7 +573,7 @@ ia_css_pipe_get_qos_ext_state (struct ia_css_pipe *pipe, bool * enable); #ifdef ISP2401 -/** @brief Update mapped CSS and ISP arguments for QoS pipe during SP runtime. +/* @brief Update mapped CSS and ISP arguments for QoS pipe during SP runtime. * @param[in] pipe Pipe handle. * @param[in] fw_handle Extension firmware Handle (ia_css_fw_info.handle). * @param[in] css_seg Parameter memory descriptors for CSS segments. @@ -595,7 +595,7 @@ ia_css_pipe_update_qos_ext_mapped_arg(struct ia_css_pipe *pipe, uint32_t fw_hand struct ia_css_isp_param_isp_segments *isp_seg); #endif -/** @brief Get selected configuration settings +/* @brief Get selected configuration settings * @param[in] pipe The pipe. * @param[out] config Configuration settings. * @return None @@ -604,7 +604,7 @@ void ia_css_pipe_get_isp_config(struct ia_css_pipe *pipe, struct ia_css_isp_config *config); -/** @brief Set the scaler lut on this pipe. A copy of lut is made in the inuit +/* @brief Set the scaler lut on this pipe. A copy of lut is made in the inuit * address space. So the LUT can be freed by caller. * @param[in] pipe Pipe handle. * @param[in] lut Look up tabel @@ -623,7 +623,7 @@ ia_css_pipe_get_isp_config(struct ia_css_pipe *pipe, enum ia_css_err ia_css_pipe_set_bci_scaler_lut( struct ia_css_pipe *pipe, const void *lut); -/** @brief Checking of DVS statistics ability +/* @brief Checking of DVS statistics ability * @param[in] pipe_info The pipe info. * @return true - has DVS statistics ability * false - otherwise @@ -631,7 +631,7 @@ ia_css_pipe_set_bci_scaler_lut( struct ia_css_pipe *pipe, bool ia_css_pipe_has_dvs_stats(struct ia_css_pipe_info *pipe_info); #ifdef ISP2401 -/** @brief Override the frameformat set on the output pins. +/* @brief Override the frameformat set on the output pins. * @param[in] pipe Pipe handle. * @param[in] output_pin Pin index to set the format on * 0 - main output pin diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_prbs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_prbs.h index 9b0eeb08ca04..6f24656b6cb4 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_prbs.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_prbs.h @@ -15,11 +15,11 @@ #ifndef __IA_CSS_PRBS_H #define __IA_CSS_PRBS_H -/** @file +/* @file * This file contains support for Pseudo Random Bit Sequence (PRBS) inputs */ -/** Enumerate the PRBS IDs. +/* Enumerate the PRBS IDs. */ enum ia_css_prbs_id { IA_CSS_PRBS_ID0, @@ -44,10 +44,10 @@ enum ia_css_prbs_id { */ struct ia_css_prbs_config { enum ia_css_prbs_id id; - unsigned int h_blank; /**< horizontal blank */ - unsigned int v_blank; /**< vertical blank */ - int seed; /**< random seed for the 1st 2-pixel-components/clock */ - int seed1; /**< random seed for the 2nd 2-pixel-components/clock */ + unsigned int h_blank; /** horizontal blank */ + unsigned int v_blank; /** vertical blank */ + int seed; /** random seed for the 1st 2-pixel-components/clock */ + int seed1; /** random seed for the 2nd 2-pixel-components/clock */ }; #endif /* __IA_CSS_PRBS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_properties.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_properties.h index 19af4021b24c..9a167306611c 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_properties.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_properties.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_PROPERTIES_H #define __IA_CSS_PROPERTIES_H -/** @file +/* @file * This file contains support for retrieving properties of some hardware the CSS system */ @@ -24,12 +24,12 @@ struct ia_css_properties { int gdc_coord_one; - bool l1_base_is_index; /**< Indicate whether the L1 page base + bool l1_base_is_index; /** Indicate whether the L1 page base is a page index or a byte address. */ enum ia_css_vamem_type vamem_type; }; -/** @brief Get hardware properties +/* @brief Get hardware properties * @param[in,out] properties The hardware properties * @return None * diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_shading.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_shading.h index cb0f249e98c8..588f53d32b72 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_shading.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_shading.h @@ -15,13 +15,13 @@ #ifndef __IA_CSS_SHADING_H #define __IA_CSS_SHADING_H -/** @file +/* @file * This file contains support for setting the shading table for CSS */ #include -/** @brief Shading table +/* @brief Shading table * @param[in] width Width of the shading table. * @param[in] height Height of the shading table. * @return Pointer to the shading table @@ -30,7 +30,7 @@ struct ia_css_shading_table * ia_css_shading_table_alloc(unsigned int width, unsigned int height); -/** @brief Free shading table +/* @brief Free shading table * @param[in] table Pointer to the shading table. * @return None */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream.h index 453fe4db0133..fb6e8c2ca8bf 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream.h @@ -48,7 +48,7 @@ struct ia_css_stream { bool started; }; -/** @brief Get a binary in the stream, which binary has the shading correction. +/* @brief Get a binary in the stream, which binary has the shading correction. * * @param[in] stream: The stream. * @return The binary which has the shading correction. @@ -76,7 +76,7 @@ sh_css_invalidate_params(struct ia_css_stream *stream); const struct ia_css_fpn_table * ia_css_get_fpn_table(struct ia_css_stream *stream); -/** @brief Get a pointer to the shading table. +/* @brief Get a pointer to the shading table. * * @param[in] stream: The stream. * @return The pointer to the shading table. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_format.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_format.h index ae608a9c9051..f7e9020a86e1 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_format.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_format.h @@ -15,74 +15,74 @@ #ifndef __IA_CSS_STREAM_FORMAT_H #define __IA_CSS_STREAM_FORMAT_H -/** @file +/* @file * This file contains formats usable for ISP streaming input */ #include /* bool */ -/** The ISP streaming input interface supports the following formats. +/* The ISP streaming input interface supports the following formats. * These match the corresponding MIPI formats. */ enum ia_css_stream_format { - IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY, /**< 8 bits per subpixel */ - IA_CSS_STREAM_FORMAT_YUV420_8, /**< 8 bits per subpixel */ - IA_CSS_STREAM_FORMAT_YUV420_10, /**< 10 bits per subpixel */ - IA_CSS_STREAM_FORMAT_YUV420_16, /**< 16 bits per subpixel */ - IA_CSS_STREAM_FORMAT_YUV422_8, /**< UYVY..UYVY, 8 bits per subpixel */ - IA_CSS_STREAM_FORMAT_YUV422_10, /**< UYVY..UYVY, 10 bits per subpixel */ - IA_CSS_STREAM_FORMAT_YUV422_16, /**< UYVY..UYVY, 16 bits per subpixel */ - IA_CSS_STREAM_FORMAT_RGB_444, /**< BGR..BGR, 4 bits per subpixel */ - IA_CSS_STREAM_FORMAT_RGB_555, /**< BGR..BGR, 5 bits per subpixel */ - IA_CSS_STREAM_FORMAT_RGB_565, /**< BGR..BGR, 5 bits B and R, 6 bits G */ - IA_CSS_STREAM_FORMAT_RGB_666, /**< BGR..BGR, 6 bits per subpixel */ - IA_CSS_STREAM_FORMAT_RGB_888, /**< BGR..BGR, 8 bits per subpixel */ - IA_CSS_STREAM_FORMAT_RAW_6, /**< RAW data, 6 bits per pixel */ - IA_CSS_STREAM_FORMAT_RAW_7, /**< RAW data, 7 bits per pixel */ - IA_CSS_STREAM_FORMAT_RAW_8, /**< RAW data, 8 bits per pixel */ - IA_CSS_STREAM_FORMAT_RAW_10, /**< RAW data, 10 bits per pixel */ - IA_CSS_STREAM_FORMAT_RAW_12, /**< RAW data, 12 bits per pixel */ - IA_CSS_STREAM_FORMAT_RAW_14, /**< RAW data, 14 bits per pixel */ - IA_CSS_STREAM_FORMAT_RAW_16, /**< RAW data, 16 bits per pixel, which is + IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY, /** 8 bits per subpixel */ + IA_CSS_STREAM_FORMAT_YUV420_8, /** 8 bits per subpixel */ + IA_CSS_STREAM_FORMAT_YUV420_10, /** 10 bits per subpixel */ + IA_CSS_STREAM_FORMAT_YUV420_16, /** 16 bits per subpixel */ + IA_CSS_STREAM_FORMAT_YUV422_8, /** UYVY..UYVY, 8 bits per subpixel */ + IA_CSS_STREAM_FORMAT_YUV422_10, /** UYVY..UYVY, 10 bits per subpixel */ + IA_CSS_STREAM_FORMAT_YUV422_16, /** UYVY..UYVY, 16 bits per subpixel */ + IA_CSS_STREAM_FORMAT_RGB_444, /** BGR..BGR, 4 bits per subpixel */ + IA_CSS_STREAM_FORMAT_RGB_555, /** BGR..BGR, 5 bits per subpixel */ + IA_CSS_STREAM_FORMAT_RGB_565, /** BGR..BGR, 5 bits B and R, 6 bits G */ + IA_CSS_STREAM_FORMAT_RGB_666, /** BGR..BGR, 6 bits per subpixel */ + IA_CSS_STREAM_FORMAT_RGB_888, /** BGR..BGR, 8 bits per subpixel */ + IA_CSS_STREAM_FORMAT_RAW_6, /** RAW data, 6 bits per pixel */ + IA_CSS_STREAM_FORMAT_RAW_7, /** RAW data, 7 bits per pixel */ + IA_CSS_STREAM_FORMAT_RAW_8, /** RAW data, 8 bits per pixel */ + IA_CSS_STREAM_FORMAT_RAW_10, /** RAW data, 10 bits per pixel */ + IA_CSS_STREAM_FORMAT_RAW_12, /** RAW data, 12 bits per pixel */ + IA_CSS_STREAM_FORMAT_RAW_14, /** RAW data, 14 bits per pixel */ + IA_CSS_STREAM_FORMAT_RAW_16, /** RAW data, 16 bits per pixel, which is not specified in CSI-MIPI standard*/ - IA_CSS_STREAM_FORMAT_BINARY_8, /**< Binary byte stream, which is target at + IA_CSS_STREAM_FORMAT_BINARY_8, /** Binary byte stream, which is target at JPEG. */ - /** CSI2-MIPI specific format: Generic short packet data. It is used to + /* CSI2-MIPI specific format: Generic short packet data. It is used to * keep the timing information for the opening/closing of shutters, * triggering of flashes and etc. */ - IA_CSS_STREAM_FORMAT_GENERIC_SHORT1, /**< Generic Short Packet Code 1 */ - IA_CSS_STREAM_FORMAT_GENERIC_SHORT2, /**< Generic Short Packet Code 2 */ - IA_CSS_STREAM_FORMAT_GENERIC_SHORT3, /**< Generic Short Packet Code 3 */ - IA_CSS_STREAM_FORMAT_GENERIC_SHORT4, /**< Generic Short Packet Code 4 */ - IA_CSS_STREAM_FORMAT_GENERIC_SHORT5, /**< Generic Short Packet Code 5 */ - IA_CSS_STREAM_FORMAT_GENERIC_SHORT6, /**< Generic Short Packet Code 6 */ - IA_CSS_STREAM_FORMAT_GENERIC_SHORT7, /**< Generic Short Packet Code 7 */ - IA_CSS_STREAM_FORMAT_GENERIC_SHORT8, /**< Generic Short Packet Code 8 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT1, /** Generic Short Packet Code 1 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT2, /** Generic Short Packet Code 2 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT3, /** Generic Short Packet Code 3 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT4, /** Generic Short Packet Code 4 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT5, /** Generic Short Packet Code 5 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT6, /** Generic Short Packet Code 6 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT7, /** Generic Short Packet Code 7 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT8, /** Generic Short Packet Code 8 */ - /** CSI2-MIPI specific format: YUV data. + /* CSI2-MIPI specific format: YUV data. */ - IA_CSS_STREAM_FORMAT_YUV420_8_SHIFT, /**< YUV420 8-bit (Chroma Shifted Pixel Sampling) */ - IA_CSS_STREAM_FORMAT_YUV420_10_SHIFT, /**< YUV420 8-bit (Chroma Shifted Pixel Sampling) */ + IA_CSS_STREAM_FORMAT_YUV420_8_SHIFT, /** YUV420 8-bit (Chroma Shifted Pixel Sampling) */ + IA_CSS_STREAM_FORMAT_YUV420_10_SHIFT, /** YUV420 8-bit (Chroma Shifted Pixel Sampling) */ - /** CSI2-MIPI specific format: Generic long packet data + /* CSI2-MIPI specific format: Generic long packet data */ - IA_CSS_STREAM_FORMAT_EMBEDDED, /**< Embedded 8-bit non Image Data */ + IA_CSS_STREAM_FORMAT_EMBEDDED, /** Embedded 8-bit non Image Data */ - /** CSI2-MIPI specific format: User defined byte-based data. For example, + /* CSI2-MIPI specific format: User defined byte-based data. For example, * the data transmitter (e.g. the SoC sensor) can keep the JPEG data as * the User Defined Data Type 4 and the MPEG data as the * User Defined Data Type 7. */ - IA_CSS_STREAM_FORMAT_USER_DEF1, /**< User defined 8-bit data type 1 */ - IA_CSS_STREAM_FORMAT_USER_DEF2, /**< User defined 8-bit data type 2 */ - IA_CSS_STREAM_FORMAT_USER_DEF3, /**< User defined 8-bit data type 3 */ - IA_CSS_STREAM_FORMAT_USER_DEF4, /**< User defined 8-bit data type 4 */ - IA_CSS_STREAM_FORMAT_USER_DEF5, /**< User defined 8-bit data type 5 */ - IA_CSS_STREAM_FORMAT_USER_DEF6, /**< User defined 8-bit data type 6 */ - IA_CSS_STREAM_FORMAT_USER_DEF7, /**< User defined 8-bit data type 7 */ - IA_CSS_STREAM_FORMAT_USER_DEF8, /**< User defined 8-bit data type 8 */ + IA_CSS_STREAM_FORMAT_USER_DEF1, /** User defined 8-bit data type 1 */ + IA_CSS_STREAM_FORMAT_USER_DEF2, /** User defined 8-bit data type 2 */ + IA_CSS_STREAM_FORMAT_USER_DEF3, /** User defined 8-bit data type 3 */ + IA_CSS_STREAM_FORMAT_USER_DEF4, /** User defined 8-bit data type 4 */ + IA_CSS_STREAM_FORMAT_USER_DEF5, /** User defined 8-bit data type 5 */ + IA_CSS_STREAM_FORMAT_USER_DEF6, /** User defined 8-bit data type 6 */ + IA_CSS_STREAM_FORMAT_USER_DEF7, /** User defined 8-bit data type 7 */ + IA_CSS_STREAM_FORMAT_USER_DEF8, /** User defined 8-bit data type 8 */ }; #define IA_CSS_STREAM_FORMAT_NUM IA_CSS_STREAM_FORMAT_USER_DEF8 diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_public.h index 2c8d9de10a59..ca3203357ff5 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_public.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_public.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_STREAM_PUBLIC_H #define __IA_CSS_STREAM_PUBLIC_H -/** @file +/* @file * This file contains support for configuring and controlling streams */ @@ -27,26 +27,26 @@ #include "ia_css_prbs.h" #include "ia_css_input_port.h" -/** Input modes, these enumerate all supported input modes. +/* Input modes, these enumerate all supported input modes. * Note that not all ISP modes support all input modes. */ enum ia_css_input_mode { - IA_CSS_INPUT_MODE_SENSOR, /**< data from sensor */ - IA_CSS_INPUT_MODE_FIFO, /**< data from input-fifo */ - IA_CSS_INPUT_MODE_TPG, /**< data from test-pattern generator */ - IA_CSS_INPUT_MODE_PRBS, /**< data from pseudo-random bit stream */ - IA_CSS_INPUT_MODE_MEMORY, /**< data from a frame in memory */ - IA_CSS_INPUT_MODE_BUFFERED_SENSOR /**< data is sent through mipi buffer */ + IA_CSS_INPUT_MODE_SENSOR, /** data from sensor */ + IA_CSS_INPUT_MODE_FIFO, /** data from input-fifo */ + IA_CSS_INPUT_MODE_TPG, /** data from test-pattern generator */ + IA_CSS_INPUT_MODE_PRBS, /** data from pseudo-random bit stream */ + IA_CSS_INPUT_MODE_MEMORY, /** data from a frame in memory */ + IA_CSS_INPUT_MODE_BUFFERED_SENSOR /** data is sent through mipi buffer */ }; -/** Structure of the MIPI buffer configuration +/* Structure of the MIPI buffer configuration */ struct ia_css_mipi_buffer_config { - unsigned int size_mem_words; /**< The frame size in the system memory + unsigned int size_mem_words; /** The frame size in the system memory words (32B) */ - bool contiguous; /**< Allocated memory physically + bool contiguous; /** Allocated memory physically contiguously or not. \deprecated{Will be false always.}*/ - unsigned int nof_mipi_buffers; /**< The number of MIPI buffers required for this + unsigned int nof_mipi_buffers; /** The number of MIPI buffers required for this stream */ }; @@ -57,44 +57,44 @@ enum { IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH }; -/** This is input data configuration for one MIPI data type. We can have +/* This is input data configuration for one MIPI data type. We can have * multiple of this in one virtual channel. */ struct ia_css_stream_isys_stream_config { - struct ia_css_resolution input_res; /**< Resolution of input data */ - enum ia_css_stream_format format; /**< Format of input stream. This data + struct ia_css_resolution input_res; /** Resolution of input data */ + enum ia_css_stream_format format; /** Format of input stream. This data format will be mapped to MIPI data type internally. */ - int linked_isys_stream_id; /**< default value is -1, other value means + int linked_isys_stream_id; /** default value is -1, other value means current isys_stream shares the same buffer with indicated isys_stream*/ - bool valid; /**< indicate whether other fields have valid value */ + bool valid; /** indicate whether other fields have valid value */ }; struct ia_css_stream_input_config { - struct ia_css_resolution input_res; /**< Resolution of input data */ - struct ia_css_resolution effective_res; /**< Resolution of input data. + struct ia_css_resolution input_res; /** Resolution of input data */ + struct ia_css_resolution effective_res; /** Resolution of input data. Used for CSS 2400/1 System and deprecated for other systems (replaced by input_effective_res in ia_css_pipe_config) */ - enum ia_css_stream_format format; /**< Format of input stream. This data + enum ia_css_stream_format format; /** Format of input stream. This data format will be mapped to MIPI data type internally. */ - enum ia_css_bayer_order bayer_order; /**< Bayer order for RAW streams */ + enum ia_css_bayer_order bayer_order; /** Bayer order for RAW streams */ }; -/** Input stream description. This describes how input will flow into the +/* Input stream description. This describes how input will flow into the * CSS. This is used to program the CSS hardware. */ struct ia_css_stream_config { - enum ia_css_input_mode mode; /**< Input mode */ + enum ia_css_input_mode mode; /** Input mode */ union { - struct ia_css_input_port port; /**< Port, for sensor only. */ - struct ia_css_tpg_config tpg; /**< TPG configuration */ - struct ia_css_prbs_config prbs; /**< PRBS configuration */ - } source; /**< Source of input data */ - unsigned int channel_id; /**< Channel on which input data + struct ia_css_input_port port; /** Port, for sensor only. */ + struct ia_css_tpg_config tpg; /** TPG configuration */ + struct ia_css_prbs_config prbs; /** PRBS configuration */ + } source; /** Source of input data */ + unsigned int channel_id; /** Channel on which input data will arrive. Use this field to specify virtual channel id. Valid values are: 0, 1, 2, 3 */ @@ -110,29 +110,29 @@ struct ia_css_stream_config { * and will be deprecated. In the future,all platforms will use the N*N method */ #endif - unsigned int sensor_binning_factor; /**< Binning factor used by sensor + unsigned int sensor_binning_factor; /** Binning factor used by sensor to produce image data. This is used for shading correction. */ - unsigned int pixels_per_clock; /**< Number of pixels per clock, which can be + unsigned int pixels_per_clock; /** Number of pixels per clock, which can be 1, 2 or 4. */ - bool online; /**< offline will activate RAW copy on SP, use this for + bool online; /** offline will activate RAW copy on SP, use this for continuous capture. */ /* ISYS2401 usage: ISP receives data directly from sensor, no copy. */ - unsigned init_num_cont_raw_buf; /**< initial number of raw buffers to + unsigned init_num_cont_raw_buf; /** initial number of raw buffers to allocate */ - unsigned target_num_cont_raw_buf; /**< total number of raw buffers to + unsigned target_num_cont_raw_buf; /** total number of raw buffers to allocate */ - bool pack_raw_pixels; /**< Pack pixels in the raw buffers */ - bool continuous; /**< Use SP copy feature to continuously capture frames + bool pack_raw_pixels; /** Pack pixels in the raw buffers */ + bool continuous; /** Use SP copy feature to continuously capture frames to system memory and run pipes in offline mode */ - bool disable_cont_viewfinder; /**< disable continous viewfinder for ZSL use case */ - int32_t flash_gpio_pin; /**< pin on which the flash is connected, -1 for no flash */ - int left_padding; /**< The number of input-formatter left-paddings, -1 for default from binary.*/ - struct ia_css_mipi_buffer_config mipi_buffer_config; /**< mipi buffer configuration */ - struct ia_css_metadata_config metadata_config; /**< Metadata configuration. */ - bool ia_css_enable_raw_buffer_locking; /**< Enable Raw Buffer Locking for HALv3 Support */ + bool disable_cont_viewfinder; /** disable continous viewfinder for ZSL use case */ + int32_t flash_gpio_pin; /** pin on which the flash is connected, -1 for no flash */ + int left_padding; /** The number of input-formatter left-paddings, -1 for default from binary.*/ + struct ia_css_mipi_buffer_config mipi_buffer_config; /** mipi buffer configuration */ + struct ia_css_metadata_config metadata_config; /** Metadata configuration. */ + bool ia_css_enable_raw_buffer_locking; /** Enable Raw Buffer Locking for HALv3 Support */ bool lock_all; - /**< Lock all RAW buffers (true) or lock only buffers processed by + /** Lock all RAW buffers (true) or lock only buffers processed by video or preview pipe (false). This setting needs to be enabled to allow raw buffer locking without continuous viewfinder. */ @@ -140,15 +140,15 @@ struct ia_css_stream_config { struct ia_css_stream; -/** Stream info, this struct describes properties of a stream after it has been +/* Stream info, this struct describes properties of a stream after it has been * created. */ struct ia_css_stream_info { struct ia_css_metadata_info metadata_info; - /**< Info about the metadata layout, this contains the stride. */ + /** Info about the metadata layout, this contains the stride. */ }; -/** @brief Load default stream configuration +/* @brief Load default stream configuration * @param[in,out] stream_config The stream configuration. * @return None * @@ -165,7 +165,7 @@ void ia_css_stream_config_defaults(struct ia_css_stream_config *stream_config); * create the internal structures and fill in the configuration data and pipes */ - /** @brief Creates a stream + /* @brief Creates a stream * @param[in] stream_config The stream configuration. * @param[in] num_pipes The number of pipes to incorporate in the stream. * @param[in] pipes The pipes. @@ -180,7 +180,7 @@ ia_css_stream_create(const struct ia_css_stream_config *stream_config, struct ia_css_pipe *pipes[], struct ia_css_stream **stream); -/** @brief Destroys a stream +/* @brief Destroys a stream * @param[in] stream The stream. * @return IA_CSS_SUCCESS or the error code. * @@ -189,7 +189,7 @@ ia_css_stream_create(const struct ia_css_stream_config *stream_config, enum ia_css_err ia_css_stream_destroy(struct ia_css_stream *stream); -/** @brief Provides information about a stream +/* @brief Provides information about a stream * @param[in] stream The stream. * @param[out] stream_info The information about the stream. * @return IA_CSS_SUCCESS or the error code. @@ -200,7 +200,7 @@ enum ia_css_err ia_css_stream_get_info(const struct ia_css_stream *stream, struct ia_css_stream_info *stream_info); -/** @brief load (rebuild) a stream that was unloaded. +/* @brief load (rebuild) a stream that was unloaded. * @param[in] stream The stream * @return IA_CSS_SUCCESS or the error code * @@ -210,7 +210,7 @@ ia_css_stream_get_info(const struct ia_css_stream *stream, enum ia_css_err ia_css_stream_load(struct ia_css_stream *stream); -/** @brief Starts the stream. +/* @brief Starts the stream. * @param[in] stream The stream. * @return IA_CSS_SUCCESS or the error code. * @@ -223,7 +223,7 @@ ia_css_stream_load(struct ia_css_stream *stream); enum ia_css_err ia_css_stream_start(struct ia_css_stream *stream); -/** @brief Stop the stream. +/* @brief Stop the stream. * @param[in] stream The stream. * @return IA_CSS_SUCCESS or the error code. * @@ -233,7 +233,7 @@ ia_css_stream_start(struct ia_css_stream *stream); enum ia_css_err ia_css_stream_stop(struct ia_css_stream *stream); -/** @brief Check if a stream has stopped +/* @brief Check if a stream has stopped * @param[in] stream The stream. * @return boolean flag * @@ -242,7 +242,7 @@ ia_css_stream_stop(struct ia_css_stream *stream); bool ia_css_stream_has_stopped(struct ia_css_stream *stream); -/** @brief destroy a stream according to the stream seed previosly saved in the seed array. +/* @brief destroy a stream according to the stream seed previosly saved in the seed array. * @param[in] stream The stream. * @return IA_CSS_SUCCESS (no other errors are generated now) * @@ -251,7 +251,7 @@ ia_css_stream_has_stopped(struct ia_css_stream *stream); enum ia_css_err ia_css_stream_unload(struct ia_css_stream *stream); -/** @brief Returns stream format +/* @brief Returns stream format * @param[in] stream The stream. * @return format of the string * @@ -260,7 +260,7 @@ ia_css_stream_unload(struct ia_css_stream *stream); enum ia_css_stream_format ia_css_stream_get_format(const struct ia_css_stream *stream); -/** @brief Check if the stream is configured for 2 pixels per clock +/* @brief Check if the stream is configured for 2 pixels per clock * @param[in] stream The stream. * @return boolean flag * @@ -270,7 +270,7 @@ ia_css_stream_get_format(const struct ia_css_stream *stream); bool ia_css_stream_get_two_pixels_per_clock(const struct ia_css_stream *stream); -/** @brief Sets the output frame stride (at the last pipe) +/* @brief Sets the output frame stride (at the last pipe) * @param[in] stream The stream * @param[in] output_padded_width - the output buffer stride. * @return ia_css_err @@ -280,7 +280,7 @@ ia_css_stream_get_two_pixels_per_clock(const struct ia_css_stream *stream); enum ia_css_err ia_css_stream_set_output_padded_width(struct ia_css_stream *stream, unsigned int output_padded_width); -/** @brief Return max number of continuous RAW frames. +/* @brief Return max number of continuous RAW frames. * @param[in] stream The stream. * @param[out] buffer_depth The maximum number of continuous RAW frames. * @return IA_CSS_SUCCESS or IA_CSS_ERR_INVALID_ARGUMENTS @@ -291,7 +291,7 @@ ia_css_stream_set_output_padded_width(struct ia_css_stream *stream, unsigned int enum ia_css_err ia_css_stream_get_max_buffer_depth(struct ia_css_stream *stream, int *buffer_depth); -/** @brief Set nr of continuous RAW frames to use. +/* @brief Set nr of continuous RAW frames to use. * * @param[in] stream The stream. * @param[in] buffer_depth Number of frames to set. @@ -302,7 +302,7 @@ ia_css_stream_get_max_buffer_depth(struct ia_css_stream *stream, int *buffer_dep enum ia_css_err ia_css_stream_set_buffer_depth(struct ia_css_stream *stream, int buffer_depth); -/** @brief Get number of continuous RAW frames to use. +/* @brief Get number of continuous RAW frames to use. * @param[in] stream The stream. * @param[out] buffer_depth The number of frames to use * @return IA_CSS_SUCCESS or IA_CSS_ERR_INVALID_ARGUMENTS @@ -315,7 +315,7 @@ ia_css_stream_get_buffer_depth(struct ia_css_stream *stream, int *buffer_depth); /* ===== CAPTURE ===== */ -/** @brief Configure the continuous capture +/* @brief Configure the continuous capture * * @param[in] stream The stream. * @param[in] num_captures The number of RAW frames to be processed to @@ -347,7 +347,7 @@ ia_css_stream_capture(struct ia_css_stream *stream, unsigned int skip, int offset); -/** @brief Specify which raw frame to tag based on exp_id found in frame info +/* @brief Specify which raw frame to tag based on exp_id found in frame info * * @param[in] stream The stream. * @param[in] exp_id The exposure id of the raw frame to tag. @@ -363,7 +363,7 @@ ia_css_stream_capture_frame(struct ia_css_stream *stream, /* ===== VIDEO ===== */ -/** @brief Send streaming data into the css input FIFO +/* @brief Send streaming data into the css input FIFO * * @param[in] stream The stream. * @param[in] data Pointer to the pixels to be send. @@ -395,7 +395,7 @@ ia_css_stream_send_input_frame(const struct ia_css_stream *stream, unsigned int width, unsigned int height); -/** @brief Start an input frame on the CSS input FIFO. +/* @brief Start an input frame on the CSS input FIFO. * * @param[in] stream The stream. * @return None @@ -411,7 +411,7 @@ ia_css_stream_send_input_frame(const struct ia_css_stream *stream, void ia_css_stream_start_input_frame(const struct ia_css_stream *stream); -/** @brief Send a line of input data into the CSS input FIFO. +/* @brief Send a line of input data into the CSS input FIFO. * * @param[in] stream The stream. * @param[in] data Array of the first line of image data. @@ -435,7 +435,7 @@ ia_css_stream_send_input_line(const struct ia_css_stream *stream, const unsigned short *data2, unsigned int width2); -/** @brief Send a line of input embedded data into the CSS input FIFO. +/* @brief Send a line of input embedded data into the CSS input FIFO. * * @param[in] stream Pointer of the stream. * @param[in] format Format of the embedded data. @@ -457,7 +457,7 @@ ia_css_stream_send_input_embedded_line(const struct ia_css_stream *stream, const unsigned short *data, unsigned int width); -/** @brief End an input frame on the CSS input FIFO. +/* @brief End an input frame on the CSS input FIFO. * * @param[in] stream The stream. * @return None @@ -467,7 +467,7 @@ ia_css_stream_send_input_embedded_line(const struct ia_css_stream *stream, void ia_css_stream_end_input_frame(const struct ia_css_stream *stream); -/** @brief send a request flash command to SP +/* @brief send a request flash command to SP * * @param[in] stream The stream. * @return None @@ -481,7 +481,7 @@ ia_css_stream_end_input_frame(const struct ia_css_stream *stream); void ia_css_stream_request_flash(struct ia_css_stream *stream); -/** @brief Configure a stream with filter coefficients. +/* @brief Configure a stream with filter coefficients. * @deprecated {Replaced by * ia_css_pipe_set_isp_config_on_pipe()} * @@ -503,7 +503,7 @@ ia_css_stream_set_isp_config_on_pipe(struct ia_css_stream *stream, const struct ia_css_isp_config *config, struct ia_css_pipe *pipe); -/** @brief Configure a stream with filter coefficients. +/* @brief Configure a stream with filter coefficients. * @deprecated {Replaced by * ia_css_pipe_set_isp_config()} * @param[in] stream The stream. @@ -523,7 +523,7 @@ ia_css_stream_set_isp_config( struct ia_css_stream *stream, const struct ia_css_isp_config *config); -/** @brief Get selected configuration settings +/* @brief Get selected configuration settings * @param[in] stream The stream. * @param[out] config Configuration settings. * @return None @@ -532,7 +532,7 @@ void ia_css_stream_get_isp_config(const struct ia_css_stream *stream, struct ia_css_isp_config *config); -/** @brief allocate continuous raw frames for continuous capture +/* @brief allocate continuous raw frames for continuous capture * @param[in] stream The stream. * @return IA_CSS_SUCCESS or error code. * @@ -544,7 +544,7 @@ ia_css_stream_get_isp_config(const struct ia_css_stream *stream, enum ia_css_err ia_css_alloc_continuous_frame_remain(struct ia_css_stream *stream); -/** @brief allocate continuous raw frames for continuous capture +/* @brief allocate continuous raw frames for continuous capture * @param[in] stream The stream. * @return IA_CSS_SUCCESS or error code. * @@ -555,7 +555,7 @@ ia_css_alloc_continuous_frame_remain(struct ia_css_stream *stream); enum ia_css_err ia_css_update_continuous_frames(struct ia_css_stream *stream); -/** @brief ia_css_unlock_raw_frame . unlock a raw frame (HALv3 Support) +/* @brief ia_css_unlock_raw_frame . unlock a raw frame (HALv3 Support) * @param[in] stream The stream. * @param[in] exp_id exposure id that uniquely identifies the locked Raw Frame Buffer * @return ia_css_err IA_CSS_SUCCESS or error code @@ -567,7 +567,7 @@ ia_css_update_continuous_frames(struct ia_css_stream *stream); enum ia_css_err ia_css_unlock_raw_frame(struct ia_css_stream *stream, uint32_t exp_id); -/** @brief ia_css_en_dz_capt_pipe . Enable/Disable digital zoom for capture pipe +/* @brief ia_css_en_dz_capt_pipe . Enable/Disable digital zoom for capture pipe * @param[in] stream The stream. * @param[in] enable - true, disable - false * @return None diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_timer.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_timer.h index 575bb28b4bec..b256d7c88716 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_timer.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_timer.h @@ -31,47 +31,47 @@ more details. #ifndef __IA_CSS_TIMER_H #define __IA_CSS_TIMER_H -/** @file +/* @file * Timer interface definitions */ #include /* for uint32_t */ #include "ia_css_err.h" -/** @brief timer reading definition */ +/* @brief timer reading definition */ typedef uint32_t clock_value_t; -/** @brief 32 bit clock tick,(timestamp based on timer-value of CSS-internal timer)*/ +/* @brief 32 bit clock tick,(timestamp based on timer-value of CSS-internal timer)*/ struct ia_css_clock_tick { - clock_value_t ticks; /**< measured time in ticks.*/ + clock_value_t ticks; /** measured time in ticks.*/ }; -/** @brief TIMER event codes */ +/* @brief TIMER event codes */ enum ia_css_tm_event { IA_CSS_TM_EVENT_AFTER_INIT, - /**< Timer Event after Initialization */ + /** Timer Event after Initialization */ IA_CSS_TM_EVENT_MAIN_END, - /**< Timer Event after end of Main */ + /** Timer Event after end of Main */ IA_CSS_TM_EVENT_THREAD_START, - /**< Timer Event after thread start */ + /** Timer Event after thread start */ IA_CSS_TM_EVENT_FRAME_PROC_START, - /**< Timer Event after Frame Process Start */ + /** Timer Event after Frame Process Start */ IA_CSS_TM_EVENT_FRAME_PROC_END - /**< Timer Event after Frame Process End */ + /** Timer Event after Frame Process End */ }; -/** @brief code measurement common struct */ +/* @brief code measurement common struct */ struct ia_css_time_meas { - clock_value_t start_timer_value; /**< measured time in ticks */ - clock_value_t end_timer_value; /**< measured time in ticks */ + clock_value_t start_timer_value; /** measured time in ticks */ + clock_value_t end_timer_value; /** measured time in ticks */ }; /**@brief SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT checks to ensure correct alignment for struct ia_css_clock_tick. */ #define SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT sizeof(clock_value_t) -/** @brief checks to ensure correct alignment for ia_css_time_meas. */ +/* @brief checks to ensure correct alignment for ia_css_time_meas. */ #define SIZE_OF_IA_CSS_TIME_MEAS_STRUCT (sizeof(clock_value_t) \ + sizeof(clock_value_t)) -/** @brief API to fetch timer count directly +/* @brief API to fetch timer count directly * * @param curr_ts [out] measured count value * @return IA_CSS_SUCCESS if success diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_tpg.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_tpg.h index 9238a3317a46..81498bd7485b 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_tpg.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_tpg.h @@ -15,11 +15,11 @@ #ifndef __IA_CSS_TPG_H #define __IA_CSS_TPG_H -/** @file +/* @file * This file contains support for the test pattern generator (TPG) */ -/** Enumerate the TPG IDs. +/* Enumerate the TPG IDs. */ enum ia_css_tpg_id { IA_CSS_TPG_ID0, @@ -35,7 +35,7 @@ enum ia_css_tpg_id { */ #define N_CSS_TPG_IDS (IA_CSS_TPG_ID2+1) -/** Enumerate the TPG modes. +/* Enumerate the TPG modes. */ enum ia_css_tpg_mode { IA_CSS_TPG_MODE_RAMP, @@ -44,7 +44,7 @@ enum ia_css_tpg_mode { IA_CSS_TPG_MODE_MONO }; -/** @brief Configure the test pattern generator. +/* @brief Configure the test pattern generator. * * Configure the Test Pattern Generator, the way these values are used to * generate the pattern can be seen in the HRT extension for the test pattern diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_types.h index 5fec3d5c89d8..725b90072cfe 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_types.h @@ -16,7 +16,7 @@ #ifndef _IA_CSS_TYPES_H #define _IA_CSS_TYPES_H -/** @file +/* @file * This file contains types used for the ia_css parameters. * These types are in a separate file because they are expected * to be used in software layers that do not access the CSS API @@ -58,7 +58,7 @@ #include "isp/kernels/output/output_1.0/ia_css_output_types.h" #define IA_CSS_DVS_STAT_GRID_INFO_SUPPORTED -/**< Should be removed after Driver adaptation will be done */ +/** Should be removed after Driver adaptation will be done */ #define IA_CSS_VERSION_MAJOR 2 #define IA_CSS_VERSION_MINOR 0 @@ -69,8 +69,8 @@ /* Min and max exposure IDs. These macros are here to allow * the drivers to get this information. Changing these macros * constitutes a CSS API change. */ -#define IA_CSS_ISYS_MIN_EXPOSURE_ID 1 /**< Minimum exposure ID */ -#define IA_CSS_ISYS_MAX_EXPOSURE_ID 250 /**< Maximum exposure ID */ +#define IA_CSS_ISYS_MIN_EXPOSURE_ID 1 /** Minimum exposure ID */ +#define IA_CSS_ISYS_MAX_EXPOSURE_ID 250 /** Maximum exposure ID */ /* opaque types */ struct ia_css_isp_parameters; @@ -79,72 +79,72 @@ struct ia_css_memory_offsets; struct ia_css_config_memory_offsets; struct ia_css_state_memory_offsets; -/** Virtual address within the CSS address space. */ +/* Virtual address within the CSS address space. */ typedef uint32_t ia_css_ptr; -/** Generic resolution structure. +/* Generic resolution structure. */ struct ia_css_resolution { - uint32_t width; /**< Width */ - uint32_t height; /**< Height */ + uint32_t width; /** Width */ + uint32_t height; /** Height */ }; -/** Generic coordinate structure. +/* Generic coordinate structure. */ struct ia_css_coordinate { - int32_t x; /**< Value of a coordinate on the horizontal axis */ - int32_t y; /**< Value of a coordinate on the vertical axis */ + int32_t x; /** Value of a coordinate on the horizontal axis */ + int32_t y; /** Value of a coordinate on the vertical axis */ }; -/** Vector with signed values. This is used to indicate motion for +/* Vector with signed values. This is used to indicate motion for * Digital Image Stabilization. */ struct ia_css_vector { - int32_t x; /**< horizontal motion (in pixels) */ - int32_t y; /**< vertical motion (in pixels) */ + int32_t x; /** horizontal motion (in pixels) */ + int32_t y; /** vertical motion (in pixels) */ }; /* Short hands */ #define IA_CSS_ISP_DMEM IA_CSS_ISP_DMEM0 #define IA_CSS_ISP_VMEM IA_CSS_ISP_VMEM0 -/** CSS data descriptor */ +/* CSS data descriptor */ struct ia_css_data { - ia_css_ptr address; /**< CSS virtual address */ - uint32_t size; /**< Disabled if 0 */ + ia_css_ptr address; /** CSS virtual address */ + uint32_t size; /** Disabled if 0 */ }; -/** Host data descriptor */ +/* Host data descriptor */ struct ia_css_host_data { - char *address; /**< Host address */ - uint32_t size; /**< Disabled if 0 */ + char *address; /** Host address */ + uint32_t size; /** Disabled if 0 */ }; -/** ISP data descriptor */ +/* ISP data descriptor */ struct ia_css_isp_data { - uint32_t address; /**< ISP address */ - uint32_t size; /**< Disabled if 0 */ + uint32_t address; /** ISP address */ + uint32_t size; /** Disabled if 0 */ }; -/** Shading Correction types. */ +/* Shading Correction types. */ enum ia_css_shading_correction_type { #ifndef ISP2401 - IA_CSS_SHADING_CORRECTION_TYPE_1 /**< Shading Correction 1.0 (pipe 1.0 on ISP2300, pipe 2.2 on ISP2400) */ + IA_CSS_SHADING_CORRECTION_TYPE_1 /** Shading Correction 1.0 (pipe 1.0 on ISP2300, pipe 2.2 on ISP2400) */ #else - IA_CSS_SHADING_CORRECTION_NONE, /**< Shading Correction is not processed in the pipe. */ - IA_CSS_SHADING_CORRECTION_TYPE_1 /**< Shading Correction 1.0 (pipe 1.0 on ISP2300, pipe 2.2 on ISP2400/2401) */ + IA_CSS_SHADING_CORRECTION_NONE, /** Shading Correction is not processed in the pipe. */ + IA_CSS_SHADING_CORRECTION_TYPE_1 /** Shading Correction 1.0 (pipe 1.0 on ISP2300, pipe 2.2 on ISP2400/2401) */ #endif - /**< More shading correction types can be added in the future. */ + /** More shading correction types can be added in the future. */ }; -/** Shading Correction information. */ +/* Shading Correction information. */ struct ia_css_shading_info { - enum ia_css_shading_correction_type type; /**< Shading Correction type. */ + enum ia_css_shading_correction_type type; /** Shading Correction type. */ - union { /** Shading Correction information of each Shading Correction types. */ + union { /* Shading Correction information of each Shading Correction types. */ - /** Shading Correction information of IA_CSS_SHADING_CORRECTION_TYPE_1. + /* Shading Correction information of IA_CSS_SHADING_CORRECTION_TYPE_1. * * This structure contains the information necessary to generate * the shading table required in the isp. @@ -288,20 +288,20 @@ struct ia_css_shading_info { */ struct { #ifndef ISP2401 - uint32_t enable; /**< Shading correction enabled. + uint32_t enable; /** Shading correction enabled. 0:disabled, 1:enabled */ - uint32_t num_hor_grids; /**< Number of data points per line + uint32_t num_hor_grids; /** Number of data points per line per color on shading table. */ - uint32_t num_ver_grids; /**< Number of lines of data points + uint32_t num_ver_grids; /** Number of lines of data points per color on shading table. */ - uint32_t bqs_per_grid_cell; /**< Grid cell size + uint32_t bqs_per_grid_cell; /** Grid cell size in BQ(Bayer Quad) unit. (1BQ means {Gr,R,B,Gb}(2x2 pixels).) Valid values are 8,16,32,64. */ #else - uint32_t num_hor_grids; /**< Number of data points per line per color on shading table. */ - uint32_t num_ver_grids; /**< Number of lines of data points per color on shading table. */ - uint32_t bqs_per_grid_cell; /**< Grid cell size in BQ unit. + uint32_t num_hor_grids; /** Number of data points per line per color on shading table. */ + uint32_t num_ver_grids; /** Number of lines of data points per color on shading table. */ + uint32_t bqs_per_grid_cell; /** Grid cell size in BQ unit. NOTE: bqs = size in BQ(Bayer Quad) unit. 1BQ means {Gr,R,B,Gb} (2x2 pixels). Horizontal 1 bqs corresponds to horizontal 2 pixels. @@ -310,13 +310,13 @@ struct ia_css_shading_info { uint32_t bayer_scale_hor_ratio_in; uint32_t bayer_scale_hor_ratio_out; #ifndef ISP2401 - /**< Horizontal ratio of bayer scaling + /** Horizontal ratio of bayer scaling between input width and output width, for the scaling which should be done before shading correction. output_width = input_width * bayer_scale_hor_ratio_out / bayer_scale_hor_ratio_in */ #else - /**< Horizontal ratio of bayer scaling between input width and output width, + /** Horizontal ratio of bayer scaling between input width and output width, for the scaling which should be done before shading correction. output_width = input_width * bayer_scale_hor_ratio_out / bayer_scale_hor_ratio_in + 0.5 */ @@ -324,30 +324,30 @@ struct ia_css_shading_info { uint32_t bayer_scale_ver_ratio_in; uint32_t bayer_scale_ver_ratio_out; #ifndef ISP2401 - /**< Vertical ratio of bayer scaling + /** Vertical ratio of bayer scaling between input height and output height, for the scaling which should be done before shading correction. output_height = input_height * bayer_scale_ver_ratio_out / bayer_scale_ver_ratio_in */ uint32_t sc_bayer_origin_x_bqs_on_shading_table; - /**< X coordinate (in bqs) of bayer origin on shading table. + /** X coordinate (in bqs) of bayer origin on shading table. This indicates the left-most pixel of bayer (not include margin) inputted to the shading correction. This corresponds to the left-most pixel of bayer inputted to isp from sensor. */ uint32_t sc_bayer_origin_y_bqs_on_shading_table; - /**< Y coordinate (in bqs) of bayer origin on shading table. + /** Y coordinate (in bqs) of bayer origin on shading table. This indicates the top pixel of bayer (not include margin) inputted to the shading correction. This corresponds to the top pixel of bayer inputted to isp from sensor. */ #else - /**< Vertical ratio of bayer scaling between input height and output height, + /** Vertical ratio of bayer scaling between input height and output height, for the scaling which should be done before shading correction. output_height = input_height * bayer_scale_ver_ratio_out / bayer_scale_ver_ratio_in + 0.5 */ struct ia_css_resolution isp_input_sensor_data_res_bqs; - /**< Sensor data size (in bqs) inputted to ISP. This is the size BEFORE bayer scaling. + /** Sensor data size (in bqs) inputted to ISP. This is the size BEFORE bayer scaling. NOTE: This is NOT the size of the physical sensor size. CSS requests the driver that ISP inputs sensor data by the size of isp_input_sensor_data_res_bqs. @@ -357,22 +357,22 @@ struct ia_css_shading_info { ISP assumes the area of isp_input_sensor_data_res_bqs is centered on the physical sensor. */ struct ia_css_resolution sensor_data_res_bqs; - /**< Sensor data size (in bqs) at shading correction. + /** Sensor data size (in bqs) at shading correction. This is the size AFTER bayer scaling. */ struct ia_css_coordinate sensor_data_origin_bqs_on_sctbl; - /**< Origin of sensor data area positioned on shading table at shading correction. + /** Origin of sensor data area positioned on shading table at shading correction. The coordinate x,y should be positive values. */ #endif } type_1; - /**< More structures can be added here when more shading correction types will be added + /** More structures can be added here when more shading correction types will be added in the future. */ } info; }; #ifndef ISP2401 -/** Default Shading Correction information of Shading Correction Type 1. */ +/* Default Shading Correction information of Shading Correction Type 1. */ #define DEFAULT_SHADING_INFO_TYPE_1 \ { \ IA_CSS_SHADING_CORRECTION_TYPE_1, /* type */ \ @@ -394,7 +394,7 @@ struct ia_css_shading_info { #else -/** Default Shading Correction information of Shading Correction Type 1. */ +/* Default Shading Correction information of Shading Correction Type 1. */ #define DEFAULT_SHADING_INFO_TYPE_1 \ { \ IA_CSS_SHADING_CORRECTION_TYPE_1, /* type */ \ @@ -416,27 +416,27 @@ struct ia_css_shading_info { #endif -/** Default Shading Correction information. */ +/* Default Shading Correction information. */ #define DEFAULT_SHADING_INFO DEFAULT_SHADING_INFO_TYPE_1 -/** structure that describes the 3A and DIS grids */ +/* structure that describes the 3A and DIS grids */ struct ia_css_grid_info { - /** \name ISP input size + /* \name ISP input size * that is visible for user * @{ */ uint32_t isp_in_width; uint32_t isp_in_height; - /** @}*/ + /* @}*/ - struct ia_css_3a_grid_info s3a_grid; /**< 3A grid info */ + struct ia_css_3a_grid_info s3a_grid; /** 3A grid info */ union ia_css_dvs_grid_u dvs_grid; - /**< All types of DVS statistics grid info union */ + /** All types of DVS statistics grid info union */ enum ia_css_vamem_type vamem_type; }; -/** defaults for ia_css_grid_info structs */ +/* defaults for ia_css_grid_info structs */ #define DEFAULT_GRID_INFO \ { \ 0, /* isp_in_width */ \ @@ -446,25 +446,25 @@ struct ia_css_grid_info { IA_CSS_VAMEM_TYPE_1 /* vamem_type */ \ } -/** Morphing table, used for geometric distortion and chromatic abberration +/* Morphing table, used for geometric distortion and chromatic abberration * correction (GDCAC, also called GDC). * This table describes the imperfections introduced by the lens, the * advanced ISP can correct for these imperfections using this table. */ struct ia_css_morph_table { - uint32_t enable; /**< To disable GDC, set this field to false. The + uint32_t enable; /** To disable GDC, set this field to false. The coordinates fields can be set to NULL in this case. */ - uint32_t height; /**< Table height */ - uint32_t width; /**< Table width */ + uint32_t height; /** Table height */ + uint32_t width; /** Table width */ uint16_t *coordinates_x[IA_CSS_MORPH_TABLE_NUM_PLANES]; - /**< X coordinates that describe the sensor imperfection */ + /** X coordinates that describe the sensor imperfection */ uint16_t *coordinates_y[IA_CSS_MORPH_TABLE_NUM_PLANES]; - /**< Y coordinates that describe the sensor imperfection */ + /** Y coordinates that describe the sensor imperfection */ }; struct ia_css_dvs_6axis_config { unsigned int exp_id; - /**< Exposure ID, see ia_css_event_public.h for more detail */ + /** Exposure ID, see ia_css_event_public.h for more detail */ uint32_t width_y; uint32_t height_y; uint32_t width_uv; @@ -479,16 +479,16 @@ struct ia_css_dvs_6axis_config { * This specifies the coordinates (x,y) */ struct ia_css_point { - int32_t x; /**< x coordinate */ - int32_t y; /**< y coordinate */ + int32_t x; /** x coordinate */ + int32_t y; /** y coordinate */ }; /** * This specifies the region */ struct ia_css_region { - struct ia_css_point origin; /**< Starting point coordinates for the region */ - struct ia_css_resolution resolution; /**< Region resolution */ + struct ia_css_point origin; /** Starting point coordinates for the region */ + struct ia_css_resolution resolution; /** Region resolution */ }; /** @@ -509,30 +509,30 @@ struct ia_css_region { * y + height <= effective input height */ struct ia_css_dz_config { - uint32_t dx; /**< Horizontal zoom factor */ - uint32_t dy; /**< Vertical zoom factor */ - struct ia_css_region zoom_region; /**< region for zoom */ + uint32_t dx; /** Horizontal zoom factor */ + uint32_t dy; /** Vertical zoom factor */ + struct ia_css_region zoom_region; /** region for zoom */ }; -/** The still capture mode, this can be RAW (simply copy sensor input to DDR), +/* The still capture mode, this can be RAW (simply copy sensor input to DDR), * Primary ISP, the Advanced ISP (GDC) or the low-light ISP (ANR). */ enum ia_css_capture_mode { - IA_CSS_CAPTURE_MODE_RAW, /**< no processing, copy data only */ - IA_CSS_CAPTURE_MODE_BAYER, /**< bayer processing, up to demosaic */ - IA_CSS_CAPTURE_MODE_PRIMARY, /**< primary ISP */ - IA_CSS_CAPTURE_MODE_ADVANCED, /**< advanced ISP (GDC) */ - IA_CSS_CAPTURE_MODE_LOW_LIGHT /**< low light ISP (ANR) */ + IA_CSS_CAPTURE_MODE_RAW, /** no processing, copy data only */ + IA_CSS_CAPTURE_MODE_BAYER, /** bayer processing, up to demosaic */ + IA_CSS_CAPTURE_MODE_PRIMARY, /** primary ISP */ + IA_CSS_CAPTURE_MODE_ADVANCED, /** advanced ISP (GDC) */ + IA_CSS_CAPTURE_MODE_LOW_LIGHT /** low light ISP (ANR) */ }; struct ia_css_capture_config { - enum ia_css_capture_mode mode; /**< Still capture mode */ - uint32_t enable_xnr; /**< Enable/disable XNR */ + enum ia_css_capture_mode mode; /** Still capture mode */ + uint32_t enable_xnr; /** Enable/disable XNR */ uint32_t enable_raw_output; - bool enable_capture_pp_bli; /**< Enable capture_pp_bli mode */ + bool enable_capture_pp_bli; /** Enable capture_pp_bli mode */ }; -/** default settings for ia_css_capture_config structs */ +/* default settings for ia_css_capture_config structs */ #define DEFAULT_CAPTURE_CONFIG \ { \ IA_CSS_CAPTURE_MODE_PRIMARY, /* mode (capture) */ \ @@ -542,7 +542,7 @@ struct ia_css_capture_config { } -/** ISP filter configuration. This is a collection of configurations +/* ISP filter configuration. This is a collection of configurations * for each of the ISP filters (modules). * * NOTE! The contents of all pointers is copied when get or set with the @@ -557,98 +557,98 @@ struct ia_css_capture_config { * ["ISP block", 2only] : ISP block is used only for ISP2. */ struct ia_css_isp_config { - struct ia_css_wb_config *wb_config; /**< White Balance + struct ia_css_wb_config *wb_config; /** White Balance [WB1, 1&2] */ - struct ia_css_cc_config *cc_config; /**< Color Correction + struct ia_css_cc_config *cc_config; /** Color Correction [CSC1, 1only] */ - struct ia_css_tnr_config *tnr_config; /**< Temporal Noise Reduction + struct ia_css_tnr_config *tnr_config; /** Temporal Noise Reduction [TNR1, 1&2] */ - struct ia_css_ecd_config *ecd_config; /**< Eigen Color Demosaicing + struct ia_css_ecd_config *ecd_config; /** Eigen Color Demosaicing [DE2, 2only] */ - struct ia_css_ynr_config *ynr_config; /**< Y(Luma) Noise Reduction + struct ia_css_ynr_config *ynr_config; /** Y(Luma) Noise Reduction [YNR2&YEE2, 2only] */ - struct ia_css_fc_config *fc_config; /**< Fringe Control + struct ia_css_fc_config *fc_config; /** Fringe Control [FC2, 2only] */ - struct ia_css_formats_config *formats_config; /**< Formats Control for main output + struct ia_css_formats_config *formats_config; /** Formats Control for main output [FORMATS, 1&2] */ - struct ia_css_cnr_config *cnr_config; /**< Chroma Noise Reduction + struct ia_css_cnr_config *cnr_config; /** Chroma Noise Reduction [CNR2, 2only] */ - struct ia_css_macc_config *macc_config; /**< MACC + struct ia_css_macc_config *macc_config; /** MACC [MACC2, 2only] */ - struct ia_css_ctc_config *ctc_config; /**< Chroma Tone Control + struct ia_css_ctc_config *ctc_config; /** Chroma Tone Control [CTC2, 2only] */ - struct ia_css_aa_config *aa_config; /**< YUV Anti-Aliasing + struct ia_css_aa_config *aa_config; /** YUV Anti-Aliasing [AA2, 2only] (not used currently) */ - struct ia_css_aa_config *baa_config; /**< Bayer Anti-Aliasing + struct ia_css_aa_config *baa_config; /** Bayer Anti-Aliasing [BAA2, 1&2] */ - struct ia_css_ce_config *ce_config; /**< Chroma Enhancement + struct ia_css_ce_config *ce_config; /** Chroma Enhancement [CE1, 1only] */ struct ia_css_dvs_6axis_config *dvs_6axis_config; - struct ia_css_ob_config *ob_config; /**< Objective Black + struct ia_css_ob_config *ob_config; /** Objective Black [OB1, 1&2] */ - struct ia_css_dp_config *dp_config; /**< Defect Pixel Correction + struct ia_css_dp_config *dp_config; /** Defect Pixel Correction [DPC1/DPC2, 1&2] */ - struct ia_css_nr_config *nr_config; /**< Noise Reduction + struct ia_css_nr_config *nr_config; /** Noise Reduction [BNR1&YNR1&CNR1, 1&2]*/ - struct ia_css_ee_config *ee_config; /**< Edge Enhancement + struct ia_css_ee_config *ee_config; /** Edge Enhancement [YEE1, 1&2] */ - struct ia_css_de_config *de_config; /**< Demosaic + struct ia_css_de_config *de_config; /** Demosaic [DE1, 1only] */ - struct ia_css_gc_config *gc_config; /**< Gamma Correction (for YUV) + struct ia_css_gc_config *gc_config; /** Gamma Correction (for YUV) [GC1, 1only] */ - struct ia_css_anr_config *anr_config; /**< Advanced Noise Reduction */ - struct ia_css_3a_config *s3a_config; /**< 3A Statistics config */ - struct ia_css_xnr_config *xnr_config; /**< eXtra Noise Reduction */ - struct ia_css_dz_config *dz_config; /**< Digital Zoom */ - struct ia_css_cc_config *yuv2rgb_cc_config; /**< Color Correction + struct ia_css_anr_config *anr_config; /** Advanced Noise Reduction */ + struct ia_css_3a_config *s3a_config; /** 3A Statistics config */ + struct ia_css_xnr_config *xnr_config; /** eXtra Noise Reduction */ + struct ia_css_dz_config *dz_config; /** Digital Zoom */ + struct ia_css_cc_config *yuv2rgb_cc_config; /** Color Correction [CCM2, 2only] */ - struct ia_css_cc_config *rgb2yuv_cc_config; /**< Color Correction + struct ia_css_cc_config *rgb2yuv_cc_config; /** Color Correction [CSC2, 2only] */ - struct ia_css_macc_table *macc_table; /**< MACC + struct ia_css_macc_table *macc_table; /** MACC [MACC1/MACC2, 1&2]*/ - struct ia_css_gamma_table *gamma_table; /**< Gamma Correction (for YUV) + struct ia_css_gamma_table *gamma_table; /** Gamma Correction (for YUV) [GC1, 1only] */ - struct ia_css_ctc_table *ctc_table; /**< Chroma Tone Control + struct ia_css_ctc_table *ctc_table; /** Chroma Tone Control [CTC1, 1only] */ - /** \deprecated */ - struct ia_css_xnr_table *xnr_table; /**< eXtra Noise Reduction + /* \deprecated */ + struct ia_css_xnr_table *xnr_table; /** eXtra Noise Reduction [XNR1, 1&2] */ - struct ia_css_rgb_gamma_table *r_gamma_table;/**< sRGB Gamma Correction + struct ia_css_rgb_gamma_table *r_gamma_table;/** sRGB Gamma Correction [GC2, 2only] */ - struct ia_css_rgb_gamma_table *g_gamma_table;/**< sRGB Gamma Correction + struct ia_css_rgb_gamma_table *g_gamma_table;/** sRGB Gamma Correction [GC2, 2only] */ - struct ia_css_rgb_gamma_table *b_gamma_table;/**< sRGB Gamma Correction + struct ia_css_rgb_gamma_table *b_gamma_table;/** sRGB Gamma Correction [GC2, 2only] */ - struct ia_css_vector *motion_vector; /**< For 2-axis DVS */ + struct ia_css_vector *motion_vector; /** For 2-axis DVS */ struct ia_css_shading_table *shading_table; struct ia_css_morph_table *morph_table; - struct ia_css_dvs_coefficients *dvs_coefs; /**< DVS 1.0 coefficients */ - struct ia_css_dvs2_coefficients *dvs2_coefs; /**< DVS 2.0 coefficients */ + struct ia_css_dvs_coefficients *dvs_coefs; /** DVS 1.0 coefficients */ + struct ia_css_dvs2_coefficients *dvs2_coefs; /** DVS 2.0 coefficients */ struct ia_css_capture_config *capture_config; struct ia_css_anr_thres *anr_thres; - /** @deprecated{Old shading settings, see bugzilla bz675 for details} */ + /* @deprecated{Old shading settings, see bugzilla bz675 for details} */ struct ia_css_shading_settings *shading_settings; - struct ia_css_xnr3_config *xnr3_config; /**< eXtreme Noise Reduction v3 */ - /** comment from Lasse: Be aware how this feature will affect coordinate + struct ia_css_xnr3_config *xnr3_config; /** eXtreme Noise Reduction v3 */ + /* comment from Lasse: Be aware how this feature will affect coordinate * normalization in different parts of the system. (e.g. face detection, * touch focus, 3A statistics and windows of interest, shading correction, * DVS, GDC) from IQ tool level and application level down-to ISP FW level. * the risk for regression is not in the individual blocks, but how they * integrate together. */ - struct ia_css_output_config *output_config; /**< Main Output Mirroring, flipping */ + struct ia_css_output_config *output_config; /** Main Output Mirroring, flipping */ #ifdef ISP2401 - struct ia_css_tnr3_kernel_config *tnr3_config; /**< TNR3 config */ + struct ia_css_tnr3_kernel_config *tnr3_config; /** TNR3 config */ #endif - struct ia_css_scaler_config *scaler_config; /**< Skylake: scaler config (optional) */ - struct ia_css_formats_config *formats_config_display;/**< Formats control for viewfinder/display output (optional) + struct ia_css_scaler_config *scaler_config; /** Skylake: scaler config (optional) */ + struct ia_css_formats_config *formats_config_display;/** Formats control for viewfinder/display output (optional) [OSYS, n/a] */ - struct ia_css_output_config *output_config_display; /**< Viewfinder/display output mirroring, flipping (optional) */ + struct ia_css_output_config *output_config_display; /** Viewfinder/display output mirroring, flipping (optional) */ - struct ia_css_frame *output_frame; /**< Output frame the config is to be applied to (optional) */ - uint32_t isp_config_id; /**< Unique ID to track which config was actually applied to a particular frame */ + struct ia_css_frame *output_frame; /** Output frame the config is to be applied to (optional) */ + uint32_t isp_config_id; /** Unique ID to track which config was actually applied to a particular frame */ }; #endif /* _IA_CSS_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_version.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_version.h index 48c59896e847..1e88901e0b82 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_version.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_version.h @@ -15,16 +15,16 @@ #ifndef __IA_CSS_VERSION_H #define __IA_CSS_VERSION_H -/** @file +/* @file * This file contains functions to retrieve CSS-API version information */ #include -/** a common size for the version arrays */ +/* a common size for the version arrays */ #define MAX_VERSION_SIZE 500 -/** @brief Retrieves the current CSS version +/* @brief Retrieves the current CSS version * @param[out] version A pointer to a buffer where to put the generated * version string. NULL is ignored. * @param[in] max_size Size of the version buffer. If version string diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_types.h index 834eedbbeeff..0b95bf9b9aaf 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_types.h @@ -15,12 +15,12 @@ #ifndef __IA_CSS_AA2_TYPES_H #define __IA_CSS_AA2_TYPES_H -/** @file +/* @file * CSS-API header file for Anti-Aliasing parameters. */ -/** Anti-Aliasing configuration. +/* Anti-Aliasing configuration. * * This structure is used both for YUV AA and Bayer AA. * @@ -39,7 +39,7 @@ * ISP2: BAA2 is used. */ struct ia_css_aa_config { - uint16_t strength; /**< Strength of the filter. + uint16_t strength; /** Strength of the filter. u0.13, [0,8191], default/ineffective 0 */ }; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr_types.h index e205574098f2..dc317a857369 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr_types.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_ANR_TYPES_H #define __IA_CSS_ANR_TYPES_H -/** @file +/* @file * CSS-API header file for Advanced Noise Reduction kernel v1 */ @@ -23,11 +23,11 @@ #define ANR_BPP 10 #define ANR_ELEMENT_BITS ((CEIL_DIV(ANR_BPP, 8))*8) -/** Advanced Noise Reduction configuration. +/* Advanced Noise Reduction configuration. * This is also known as Low-Light. */ struct ia_css_anr_config { - int32_t threshold; /**< Threshold */ + int32_t threshold; /** Threshold */ int32_t thresholds[4*4*4]; int32_t factors[3]; }; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_types.h index 3832ada433ec..9b611315392c 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_types.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_ANR2_TYPES_H #define __IA_CSS_ANR2_TYPES_H -/** @file +/* @file * CSS-API header file for Advanced Noise Reduction kernel v2 */ @@ -23,7 +23,7 @@ #define ANR_PARAM_SIZE 13 -/** Advanced Noise Reduction (ANR) thresholds */ +/* Advanced Noise Reduction (ANR) thresholds */ struct ia_css_anr_thres { int16_t data[13*64]; }; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr_param.h index 4a289853367a..312141793fd2 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr_param.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr_param.h @@ -18,7 +18,7 @@ #include "vmem.h" #include "ia_css_anr2_types.h" -/** Advanced Noise Reduction (ANR) thresholds */ +/* Advanced Noise Reduction (ANR) thresholds */ struct ia_css_isp_anr2_params { VMEM_ARRAY(data, ANR_PARAM_SIZE*ISP_VEC_NELEMS); diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_ls_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_ls_param.h index 75ca7606b95c..a0d355454aa3 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_ls_param.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_ls_param.h @@ -27,7 +27,7 @@ #define BAYER_QUAD_HEIGHT 2 #define NOF_BAYER_VECTORS 4 -/** bayer load/store */ +/* bayer load/store */ struct sh_css_isp_bayer_ls_isp_config { uint32_t base_address[NUM_BAYER_LS]; uint32_t width[NUM_BAYER_LS]; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh_types.h index 9ae27a9e0baa..ec1688e7352d 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh_types.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_BH_TYPES_H #define __IA_CSS_BH_TYPES_H -/** Number of elements in the BH table. +/* Number of elements in the BH table. * Should be consistent with hmem.h */ #define IA_CSS_HMEM_BH_TABLE_SIZE ISP_HIST_DEPTH @@ -27,7 +27,7 @@ #define BH_COLOR_Y (3) #define BH_COLOR_NUM (4) -/** BH table */ +/* BH table */ struct ia_css_bh_table { uint32_t hmem[ISP_HIST_COMPONENTS][IA_CSS_HMEM_BH_UNIT_SIZE]; }; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_types.h index 219fb835cb26..87e0f19c856b 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_types.h @@ -15,13 +15,13 @@ #ifndef __IA_CSS_BNLM_TYPES_H #define __IA_CSS_BNLM_TYPES_H -/** @file +/* @file * CSS-API header file for Bayer Non-Linear Mean parameters. */ #include "type_support.h" /* int32_t */ -/** Bayer Non-Linear Mean configuration +/* Bayer Non-Linear Mean configuration * * \brief BNLM public parameters. * \details Struct with all parameters for the BNLM kernel that can be set @@ -30,16 +30,16 @@ * ISP2.6.1: BNLM is used. */ struct ia_css_bnlm_config { - bool rad_enable; /**< Enable a radial dependency in a weight calculation */ - int32_t rad_x_origin; /**< Initial x coordinate for a radius calculation */ - int32_t rad_y_origin; /**< Initial x coordinate for a radius calculation */ + bool rad_enable; /** Enable a radial dependency in a weight calculation */ + int32_t rad_x_origin; /** Initial x coordinate for a radius calculation */ + int32_t rad_y_origin; /** Initial x coordinate for a radius calculation */ /* a threshold for average of weights if this < Th, do not denoise pixel */ int32_t avg_min_th; /* minimum weight for denoising if max < th, do not denoise pixel */ int32_t max_min_th; /**@{*/ - /** Coefficient for approximation, in the form of (1 + x / N)^N, + /* Coefficient for approximation, in the form of (1 + x / N)^N, * that fits the first-order exp() to default exp_lut in BNLM sheet * */ int32_t exp_coeff_a; @@ -48,55 +48,55 @@ struct ia_css_bnlm_config { uint32_t exp_exponent; /**@}*/ - int32_t nl_th[3]; /**< Detail thresholds */ + int32_t nl_th[3]; /** Detail thresholds */ - /** Index for n-th maximum candidate weight for each detail group */ + /* Index for n-th maximum candidate weight for each detail group */ int32_t match_quality_max_idx[4]; /**@{*/ - /** A lookup table for 1/sqrt(1+mu) approximation */ + /* A lookup table for 1/sqrt(1+mu) approximation */ int32_t mu_root_lut_thr[15]; int32_t mu_root_lut_val[16]; /**@}*/ /**@{*/ - /** A lookup table for SAD normalization */ + /* A lookup table for SAD normalization */ int32_t sad_norm_lut_thr[15]; int32_t sad_norm_lut_val[16]; /**@}*/ /**@{*/ - /** A lookup table that models a weight's dependency on textures */ + /* A lookup table that models a weight's dependency on textures */ int32_t sig_detail_lut_thr[15]; int32_t sig_detail_lut_val[16]; /**@}*/ /**@{*/ - /** A lookup table that models a weight's dependency on a pixel's radial distance */ + /* A lookup table that models a weight's dependency on a pixel's radial distance */ int32_t sig_rad_lut_thr[15]; int32_t sig_rad_lut_val[16]; /**@}*/ /**@{*/ - /** A lookup table to control denoise power depending on a pixel's radial distance */ + /* A lookup table to control denoise power depending on a pixel's radial distance */ int32_t rad_pow_lut_thr[15]; int32_t rad_pow_lut_val[16]; /**@}*/ /**@{*/ - /** Non linear transfer functions to calculate the blending coefficient depending on detail group */ - /** detail group 0 */ + /* Non linear transfer functions to calculate the blending coefficient depending on detail group */ + /* detail group 0 */ /**@{*/ int32_t nl_0_lut_thr[15]; int32_t nl_0_lut_val[16]; /**@}*/ /**@{*/ - /** detail group 1 */ + /* detail group 1 */ int32_t nl_1_lut_thr[15]; int32_t nl_1_lut_val[16]; /**@}*/ /**@{*/ - /** detail group 2 */ + /* detail group 2 */ int32_t nl_2_lut_thr[15]; int32_t nl_2_lut_val[16]; /**@}*/ /**@{*/ - /** detail group 3 */ + /* detail group 3 */ int32_t nl_3_lut_thr[15]; int32_t nl_3_lut_val[16]; /**@}*/ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_types.h index be80f705d8a1..551bd0ed3bac 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_types.h @@ -15,13 +15,13 @@ #ifndef __IA_CSS_BNR2_2_TYPES_H #define __IA_CSS_BNR2_2_TYPES_H -/** @file +/* @file * CSS-API header file for Bayer Noise Reduction parameters. */ #include "type_support.h" /* int32_t */ -/** Bayer Noise Reduction 2.2 configuration +/* Bayer Noise Reduction 2.2 configuration * * \brief BNR2_2 public parameters. * \details Struct with all parameters for the BNR2.2 kernel that can be set @@ -31,41 +31,41 @@ */ struct ia_css_bnr2_2_config { /**@{*/ - /** Directional variance gain for R/G/B components in dark region */ + /* Directional variance gain for R/G/B components in dark region */ int32_t d_var_gain_r; int32_t d_var_gain_g; int32_t d_var_gain_b; /**@}*/ /**@{*/ - /** Slope of Directional variance gain between dark and bright region */ + /* Slope of Directional variance gain between dark and bright region */ int32_t d_var_gain_slope_r; int32_t d_var_gain_slope_g; int32_t d_var_gain_slope_b; /**@}*/ /**@{*/ - /** Non-Directional variance gain for R/G/B components in dark region */ + /* Non-Directional variance gain for R/G/B components in dark region */ int32_t n_var_gain_r; int32_t n_var_gain_g; int32_t n_var_gain_b; /**@}*/ /**@{*/ - /** Slope of Non-Directional variance gain between dark and bright region */ + /* Slope of Non-Directional variance gain between dark and bright region */ int32_t n_var_gain_slope_r; int32_t n_var_gain_slope_g; int32_t n_var_gain_slope_b; /**@}*/ - int32_t dir_thres; /**< Threshold for directional filtering */ - int32_t dir_thres_w; /**< Threshold width for directional filtering */ - int32_t var_offset_coef; /**< Variance offset coefficient */ - int32_t dir_gain; /**< Gain for directional coefficient */ - int32_t detail_gain; /**< Gain for low contrast texture control */ - int32_t detail_gain_divisor; /**< Gain divisor for low contrast texture control */ - int32_t detail_level_offset; /**< Bias value for low contrast texture control */ - int32_t d_var_th_min; /**< Minimum clipping value for directional variance*/ - int32_t d_var_th_max; /**< Maximum clipping value for diretional variance*/ - int32_t n_var_th_min; /**< Minimum clipping value for non-directional variance*/ - int32_t n_var_th_max; /**< Maximum clipping value for non-directional variance*/ + int32_t dir_thres; /** Threshold for directional filtering */ + int32_t dir_thres_w; /** Threshold width for directional filtering */ + int32_t var_offset_coef; /** Variance offset coefficient */ + int32_t dir_gain; /** Gain for directional coefficient */ + int32_t detail_gain; /** Gain for low contrast texture control */ + int32_t detail_gain_divisor; /** Gain divisor for low contrast texture control */ + int32_t detail_level_offset; /** Bias value for low contrast texture control */ + int32_t d_var_th_min; /** Minimum clipping value for directional variance*/ + int32_t d_var_th_max; /** Maximum clipping value for diretional variance*/ + int32_t n_var_th_min; /** Minimum clipping value for non-directional variance*/ + int32_t n_var_th_max; /** Maximum clipping value for non-directional variance*/ }; #endif /* __IA_CSS_BNR2_2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h index 6df6c2be9a70..3ebc069d8ada 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h @@ -15,11 +15,11 @@ #ifndef __IA_CSS_CNR2_TYPES_H #define __IA_CSS_CNR2_TYPES_H -/** @file +/* @file * CSS-API header file for Chroma Noise Reduction (CNR) parameters */ -/** Chroma Noise Reduction configuration. +/* Chroma Noise Reduction configuration. * * Small sensitivity of edge means strong smoothness and NR performance. * If you see blurred color on vertical edges, @@ -33,21 +33,21 @@ * ISP2: CNR2 is used for Still. */ struct ia_css_cnr_config { - uint16_t coring_u; /**< Coring level of U. + uint16_t coring_u; /** Coring level of U. u0.13, [0,8191], default/ineffective 0 */ - uint16_t coring_v; /**< Coring level of V. + uint16_t coring_v; /** Coring level of V. u0.13, [0,8191], default/ineffective 0 */ - uint16_t sense_gain_vy; /**< Sensitivity of horizontal edge of Y. + uint16_t sense_gain_vy; /** Sensitivity of horizontal edge of Y. u13.0, [0,8191], default 100, ineffective 8191 */ - uint16_t sense_gain_vu; /**< Sensitivity of horizontal edge of U. + uint16_t sense_gain_vu; /** Sensitivity of horizontal edge of U. u13.0, [0,8191], default 100, ineffective 8191 */ - uint16_t sense_gain_vv; /**< Sensitivity of horizontal edge of V. + uint16_t sense_gain_vv; /** Sensitivity of horizontal edge of V. u13.0, [0,8191], default 100, ineffective 8191 */ - uint16_t sense_gain_hy; /**< Sensitivity of vertical edge of Y. + uint16_t sense_gain_hy; /** Sensitivity of vertical edge of Y. u13.0, [0,8191], default 50, ineffective 8191 */ - uint16_t sense_gain_hu; /**< Sensitivity of vertical edge of U. + uint16_t sense_gain_hu; /** Sensitivity of vertical edge of U. u13.0, [0,8191], default 50, ineffective 8191 */ - uint16_t sense_gain_hv; /**< Sensitivity of vertical edge of V. + uint16_t sense_gain_hv; /** Sensitivity of vertical edge of V. u13.0, [0,8191], default 50, ineffective 8191 */ }; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion_types.h index 3f11442500f0..47a38fd65950 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion_types.h @@ -23,10 +23,10 @@ * */ struct ia_css_conversion_config { - uint32_t en; /**< en parameter */ - uint32_t dummy0; /**< dummy0 dummy parameter 0 */ - uint32_t dummy1; /**< dummy1 dummy parameter 1 */ - uint32_t dummy2; /**< dummy2 dummy parameter 2 */ + uint32_t en; /** en parameter */ + uint32_t dummy0; /** dummy0 dummy parameter 0 */ + uint32_t dummy1; /** dummy1 dummy parameter 1 */ + uint32_t dummy2; /** dummy2 dummy parameter 2 */ }; #endif /* __IA_CSS_CONVERSION_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_param.h index 8bfc8dad37a8..0f1812cdd92a 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_param.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_param.h @@ -19,7 +19,7 @@ #include "dma.h" #include "sh_css_internal.h" /* sh_css_crop_pos */ -/** Crop frame */ +/* Crop frame */ struct sh_css_isp_crop_isp_config { uint32_t width_a_over_b; struct dma_port_config port_b; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_types.h index 8091ad4d4602..b5d454225f89 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_types.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_CROP_TYPES_H #define __IA_CSS_CROP_TYPES_H -/** Crop frame +/* Crop frame * * ISP block: crop frame */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc_types.h index 54ced072467f..10404380c637 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc_types.h @@ -15,11 +15,11 @@ #ifndef __IA_CSS_CSC_TYPES_H #define __IA_CSS_CSC_TYPES_H -/** @file +/* @file * CSS-API header file for Color Space Conversion parameters. */ -/** Color Correction configuration. +/* Color Correction configuration. * * This structure is used for 3 cases. * ("YCgCo" is the output format of Demosaic.) @@ -68,9 +68,9 @@ * 4096 -3430 -666 */ struct ia_css_cc_config { - uint32_t fraction_bits;/**< Fractional bits of matrix. + uint32_t fraction_bits;/** Fractional bits of matrix. u8.0, [0,13] */ - int32_t matrix[3 * 3]; /**< Conversion matrix. + int32_t matrix[3 * 3]; /** Conversion matrix. s[13-fraction_bits].[fraction_bits], [-8192,8191] */ }; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_param.h index c66e823618f6..ad7040c9d7cb 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_param.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_param.h @@ -22,11 +22,11 @@ /*VMEM Luma params*/ struct ia_css_isp_ctc2_vmem_params { - /**< Gains by Y(Luma) at Y = 0.0,Y_X1, Y_X2, Y_X3, Y_X4*/ + /** Gains by Y(Luma) at Y = 0.0,Y_X1, Y_X2, Y_X3, Y_X4*/ VMEM_ARRAY(y_x, ISP_VEC_NELEMS); - /** kneepoints by Y(Luma) 0.0, y_x1, y_x2, y _x3, y_x4*/ + /* kneepoints by Y(Luma) 0.0, y_x1, y_x2, y _x3, y_x4*/ VMEM_ARRAY(y_y, ISP_VEC_NELEMS); - /** Slopes of lines interconnecting + /* Slopes of lines interconnecting * 0.0 -> y_x1 -> y_x2 -> y _x3 -> y_x4 -> 1.0*/ VMEM_ARRAY(e_y_slope, ISP_VEC_NELEMS); }; @@ -34,15 +34,15 @@ struct ia_css_isp_ctc2_vmem_params { /*DMEM Chroma params*/ struct ia_css_isp_ctc2_dmem_params { - /** Gains by UV(Chroma) under kneepoints uv_x0 and uv_x1*/ + /* Gains by UV(Chroma) under kneepoints uv_x0 and uv_x1*/ int32_t uv_y0; int32_t uv_y1; - /** Kneepoints by UV(Chroma)- uv_x0 and uv_x1*/ + /* Kneepoints by UV(Chroma)- uv_x0 and uv_x1*/ int32_t uv_x0; int32_t uv_x1; - /** Slope of line interconnecting uv_x0 -> uv_x1*/ + /* Slope of line interconnecting uv_x0 -> uv_x1*/ int32_t uv_dydx; }; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_types.h index 7b75f01e2ad2..1222cf33e851 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_types.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_CTC2_TYPES_H #define __IA_CSS_CTC2_TYPES_H -/** Chroma Tone Control configuration. +/* Chroma Tone Control configuration. * * ISP block: CTC2 (CTC by polygonal approximation) * (ISP1: CTC1 (CTC by look-up table) is used.) @@ -24,7 +24,7 @@ */ struct ia_css_ctc2_config { - /**< Gains by Y(Luma) at Y =0.0,Y_X1, Y_X2, Y_X3, Y_X4 and Y_X5 + /** Gains by Y(Luma) at Y =0.0,Y_X1, Y_X2, Y_X3, Y_X4 and Y_X5 * --default/ineffective value: 4096(0.5f) */ int32_t y_y0; @@ -33,19 +33,19 @@ struct ia_css_ctc2_config { int32_t y_y3; int32_t y_y4; int32_t y_y5; - /** 1st-4th kneepoints by Y(Luma) --default/ineffective value:n/a + /* 1st-4th kneepoints by Y(Luma) --default/ineffective value:n/a * requirement: 0.0 < y_x1 < y_x2 #include "sh_css_internal.h" -/** qplane frame +/* qplane frame * * ISP block: qplane frame */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw_types.h index 54f8c299d227..5c0b8febd79a 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw_types.h @@ -18,7 +18,7 @@ #include #include "sh_css_internal.h" -/** Raw frame +/* Raw frame * * ISP block: Raw frame */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_param.h index 1f1b72a417d1..026443b999a6 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_param.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_param.h @@ -19,7 +19,7 @@ #include "sh_css_defs.h" #include "dma.h" -/** Reference frame */ +/* Reference frame */ struct ia_css_ref_configuration { const struct ia_css_frame *ref_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; uint32_t dvs_frame_delay; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_types.h index ce0eaeeee9c6..4750fba268b9 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_types.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_REF_TYPES_H #define __IA_CSS_REF_TYPES_H -/** Reference frame +/* Reference frame * * ISP block: reference frame */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h index f57ed1ec5981..8d674d2c6427 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_S3A_TYPES_H #define __IA_CSS_S3A_TYPES_H -/** @file +/* @file * CSS-API header file for 3A statistics parameters. */ @@ -25,11 +25,11 @@ #include "../../../../components/stats_3a/src/stats_3a_public.h" #endif -/** 3A configuration. This configures the 3A statistics collection +/* 3A configuration. This configures the 3A statistics collection * module. */ -/** 3A statistics grid +/* 3A statistics grid * * ISP block: S3A1 (3A Support for 3A ver.1 (Histogram is not used for AE)) * S3A2 (3A Support for 3A ver.2 (Histogram is used for AE)) @@ -39,23 +39,23 @@ struct ia_css_3a_grid_info { #if defined(SYSTEM_css_skycam_c0_system) - uint32_t ae_enable; /**< ae enabled in binary, + uint32_t ae_enable; /** ae enabled in binary, 0:disabled, 1:enabled */ - struct ae_public_config_grid_config ae_grd_info; /**< see description in ae_public.h*/ + struct ae_public_config_grid_config ae_grd_info; /** see description in ae_public.h*/ - uint32_t awb_enable; /**< awb enabled in binary, + uint32_t awb_enable; /** awb enabled in binary, 0:disabled, 1:enabled */ - struct awb_public_config_grid_config awb_grd_info; /**< see description in awb_public.h*/ + struct awb_public_config_grid_config awb_grd_info; /** see description in awb_public.h*/ - uint32_t af_enable; /**< af enabled in binary, + uint32_t af_enable; /** af enabled in binary, 0:disabled, 1:enabled */ - struct af_public_grid_config af_grd_info; /**< see description in af_public.h*/ + struct af_public_grid_config af_grd_info; /** see description in af_public.h*/ - uint32_t awb_fr_enable; /**< awb_fr enabled in binary, + uint32_t awb_fr_enable; /** awb_fr enabled in binary, 0:disabled, 1:enabled */ - struct awb_fr_public_grid_config awb_fr_grd_info;/**< see description in awb_fr_public.h*/ + struct awb_fr_public_grid_config awb_fr_grd_info;/** see description in awb_fr_public.h*/ - uint32_t elem_bit_depth; /**< TODO:Taken from BYT - need input from AIQ + uint32_t elem_bit_depth; /** TODO:Taken from BYT - need input from AIQ if needed for SKC Bit depth of element used to calculate 3A statistics. @@ -63,34 +63,34 @@ struct ia_css_3a_grid_info { bayer bit depth in DSP. */ #else - uint32_t enable; /**< 3A statistics enabled. + uint32_t enable; /** 3A statistics enabled. 0:disabled, 1:enabled */ - uint32_t use_dmem; /**< DMEM or VMEM determines layout. + uint32_t use_dmem; /** DMEM or VMEM determines layout. 0:3A statistics are stored to VMEM, 1:3A statistics are stored to DMEM */ - uint32_t has_histogram; /**< Statistics include histogram. + uint32_t has_histogram; /** Statistics include histogram. 0:no histogram, 1:has histogram */ - uint32_t width; /**< Width of 3A grid table. + uint32_t width; /** Width of 3A grid table. (= Horizontal number of grid cells in table, which cells have effective statistics.) */ - uint32_t height; /**< Height of 3A grid table. + uint32_t height; /** Height of 3A grid table. (= Vertical number of grid cells in table, which cells have effective statistics.) */ - uint32_t aligned_width; /**< Horizontal stride (for alloc). + uint32_t aligned_width; /** Horizontal stride (for alloc). (= Horizontal number of grid cells in table, which means the allocated width.) */ - uint32_t aligned_height; /**< Vertical stride (for alloc). + uint32_t aligned_height; /** Vertical stride (for alloc). (= Vertical number of grid cells in table, which means the allocated height.) */ - uint32_t bqs_per_grid_cell; /**< Grid cell size in BQ(Bayer Quad) unit. + uint32_t bqs_per_grid_cell; /** Grid cell size in BQ(Bayer Quad) unit. (1BQ means {Gr,R,B,Gb}(2x2 pixels).) Valid values are 8,16,32,64. */ - uint32_t deci_factor_log2; /**< log2 of bqs_per_grid_cell. */ - uint32_t elem_bit_depth; /**< Bit depth of element used + uint32_t deci_factor_log2; /** log2 of bqs_per_grid_cell. */ + uint32_t elem_bit_depth; /** Bit depth of element used to calculate 3A statistics. This is 13, which is the normalized bayer bit depth in DSP. */ @@ -148,7 +148,7 @@ struct ia_css_3a_grid_info { * However, that will require driver/ 3A lib modifications. */ -/** 3A configuration. This configures the 3A statistics collection +/* 3A configuration. This configures the 3A statistics collection * module. * * ae_y_*: Coefficients to calculate luminance from bayer. @@ -167,38 +167,38 @@ struct ia_css_3a_grid_info { * ISP2: S3A2 and SDVS2 are used. */ struct ia_css_3a_config { - ia_css_u0_16 ae_y_coef_r; /**< Weight of R for Y. + ia_css_u0_16 ae_y_coef_r; /** Weight of R for Y. u0.16, [0,65535], default/ineffective 25559 */ - ia_css_u0_16 ae_y_coef_g; /**< Weight of G for Y. + ia_css_u0_16 ae_y_coef_g; /** Weight of G for Y. u0.16, [0,65535], default/ineffective 32768 */ - ia_css_u0_16 ae_y_coef_b; /**< Weight of B for Y. + ia_css_u0_16 ae_y_coef_b; /** Weight of B for Y. u0.16, [0,65535], default/ineffective 7209 */ - ia_css_u0_16 awb_lg_high_raw; /**< AWB level gate high for raw. + ia_css_u0_16 awb_lg_high_raw; /** AWB level gate high for raw. u0.16, [0,65535], default 65472(=1023*64), ineffective 65535 */ - ia_css_u0_16 awb_lg_low; /**< AWB level gate low. + ia_css_u0_16 awb_lg_low; /** AWB level gate low. u0.16, [0,65535], default 64(=1*64), ineffective 0 */ - ia_css_u0_16 awb_lg_high; /**< AWB level gate high. + ia_css_u0_16 awb_lg_high; /** AWB level gate high. u0.16, [0,65535], default 65535, ineffective 65535 */ - ia_css_s0_15 af_fir1_coef[7]; /**< AF FIR coefficients of fir1. + ia_css_s0_15 af_fir1_coef[7]; /** AF FIR coefficients of fir1. s0.15, [-32768,32767], default/ineffective -6689,-12207,-32768,32767,12207,6689,0 */ - ia_css_s0_15 af_fir2_coef[7]; /**< AF FIR coefficients of fir2. + ia_css_s0_15 af_fir2_coef[7]; /** AF FIR coefficients of fir2. s0.15, [-32768,32767], default/ineffective 2053,0,-18437,32767,-18437,2053,0 */ }; -/** 3A statistics. This structure describes the data stored +/* 3A statistics. This structure describes the data stored * in each 3A grid point. * * ISP block: S3A1 (3A Support for 3A ver.1) (Histogram is not used for AE) @@ -209,43 +209,43 @@ struct ia_css_3a_config { * ISP2: S3A2 is used. */ struct ia_css_3a_output { - int32_t ae_y; /**< Sum of Y in a statistics window, for AE. + int32_t ae_y; /** Sum of Y in a statistics window, for AE. (u19.13) */ - int32_t awb_cnt; /**< Number of effective pixels + int32_t awb_cnt; /** Number of effective pixels in a statistics window. Pixels passed by the AWB level gate check are judged as "effective". (u32) */ - int32_t awb_gr; /**< Sum of Gr in a statistics window, for AWB. + int32_t awb_gr; /** Sum of Gr in a statistics window, for AWB. All Gr pixels (not only for effective pixels) are summed. (u19.13) */ - int32_t awb_r; /**< Sum of R in a statistics window, for AWB. + int32_t awb_r; /** Sum of R in a statistics window, for AWB. All R pixels (not only for effective pixels) are summed. (u19.13) */ - int32_t awb_b; /**< Sum of B in a statistics window, for AWB. + int32_t awb_b; /** Sum of B in a statistics window, for AWB. All B pixels (not only for effective pixels) are summed. (u19.13) */ - int32_t awb_gb; /**< Sum of Gb in a statistics window, for AWB. + int32_t awb_gb; /** Sum of Gb in a statistics window, for AWB. All Gb pixels (not only for effective pixels) are summed. (u19.13) */ - int32_t af_hpf1; /**< Sum of |Y| following high pass filter af_fir1 + int32_t af_hpf1; /** Sum of |Y| following high pass filter af_fir1 within a statistics window, for AF. (u19.13) */ - int32_t af_hpf2; /**< Sum of |Y| following high pass filter af_fir2 + int32_t af_hpf2; /** Sum of |Y| following high pass filter af_fir2 within a statistics window, for AF. (u19.13) */ }; -/** 3A Statistics. This structure describes the statistics that are generated +/* 3A Statistics. This structure describes the statistics that are generated * using the provided configuration (ia_css_3a_config). */ struct ia_css_3a_statistics { - struct ia_css_3a_grid_info grid; /**< grid info contains the dimensions of the 3A grid */ - struct ia_css_3a_output *data; /**< the pointer to 3a_output[grid.width * grid.height] + struct ia_css_3a_grid_info grid; /** grid info contains the dimensions of the 3A grid */ + struct ia_css_3a_output *data; /** the pointer to 3a_output[grid.width * grid.height] containing the 3A statistics */ - struct ia_css_3a_rgby_output *rgby_data;/**< the pointer to 3a_rgby_output[256] + struct ia_css_3a_rgby_output *rgby_data;/** the pointer to 3a_rgby_output[256] containing the histogram */ }; -/** Histogram (Statistics for AE). +/* Histogram (Statistics for AE). * * 4 histograms(r,g,b,y), * 256 bins for each histogram, unsigned 24bit value for each bin. @@ -256,10 +256,10 @@ struct ia_css_3a_statistics { * ISP2: HIST2 is used. */ struct ia_css_3a_rgby_output { - uint32_t r; /**< Number of R of one bin of the histogram R. (u24) */ - uint32_t g; /**< Number of G of one bin of the histogram G. (u24) */ - uint32_t b; /**< Number of B of one bin of the histogram B. (u24) */ - uint32_t y; /**< Number of Y of one bin of the histogram Y. (u24) */ + uint32_t r; /** Number of R of one bin of the histogram R. (u24) */ + uint32_t g; /** Number of G of one bin of the histogram G. (u24) */ + uint32_t b; /** Number of B of one bin of the histogram B. (u24) */ + uint32_t y; /** Number of Y of one bin of the histogram Y. (u24) */ }; #endif /* __IA_CSS_S3A_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a_stat_ls/ia_css_s3a_stat_ls_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a_stat_ls/ia_css_s3a_stat_ls_param.h index 8b2b56b0310b..9aa019539f47 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a_stat_ls/ia_css_s3a_stat_ls_param.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a_stat_ls/ia_css_s3a_stat_ls_param.h @@ -22,7 +22,7 @@ #define NUM_S3A_LS 1 -/** s3a statistics store */ +/* s3a statistics store */ #ifdef ISP2401 struct ia_css_s3a_stat_ls_configuration { uint32_t s3a_grid_size_log2; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.h index 44e3c43a5d4a..b35ac3e4009b 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.h @@ -32,7 +32,7 @@ ia_css_sc_dump( unsigned level); #ifdef ISP2401 -/** @brief Configure the shading correction. +/* @brief Configure the shading correction. * @param[out] to Parameters used in the shading correction kernel in the isp. * @param[in] from Parameters passed from the host. * @param[in] size Size of the sh_css_isp_sc_isp_config structure. @@ -45,7 +45,7 @@ ia_css_sc_config( const struct ia_css_sc_configuration *from, unsigned size); -/** @brief Configure the shading correction. +/* @brief Configure the shading correction. * @param[in] binary The binary, which has the shading correction. * @param[in] internal_frame_origin_x_bqs_on_sctbl * X coordinate (in bqs) of the origin of the internal frame on the shading table. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc_types.h index 5a833bc48af1..30ce499ac8cf 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc_types.h @@ -15,25 +15,25 @@ #ifndef __IA_CSS_SC_TYPES_H #define __IA_CSS_SC_TYPES_H -/** @file +/* @file * CSS-API header file for Lens Shading Correction (SC) parameters. */ -/** Number of color planes in the shading table. */ +/* Number of color planes in the shading table. */ #define IA_CSS_SC_NUM_COLORS 4 -/** The 4 colors that a shading table consists of. +/* The 4 colors that a shading table consists of. * For each color we store a grid of values. */ enum ia_css_sc_color { - IA_CSS_SC_COLOR_GR, /**< Green on a green-red line */ - IA_CSS_SC_COLOR_R, /**< Red */ - IA_CSS_SC_COLOR_B, /**< Blue */ - IA_CSS_SC_COLOR_GB /**< Green on a green-blue line */ + IA_CSS_SC_COLOR_GR, /** Green on a green-red line */ + IA_CSS_SC_COLOR_R, /** Red */ + IA_CSS_SC_COLOR_B, /** Blue */ + IA_CSS_SC_COLOR_GB /** Green on a green-blue line */ }; -/** Lens Shading Correction table. +/* Lens Shading Correction table. * * This describes the color shading artefacts * introduced by lens imperfections. To correct artefacts, @@ -64,39 +64,39 @@ enum ia_css_sc_color { * ISP2: SC1 is used. */ struct ia_css_shading_table { - uint32_t enable; /**< Set to false for no shading correction. + uint32_t enable; /** Set to false for no shading correction. The data field can be NULL when enable == true */ /* ------ deprecated(bz675) : from ------ */ - uint32_t sensor_width; /**< Native sensor width in pixels. */ - uint32_t sensor_height; /**< Native sensor height in lines. + uint32_t sensor_width; /** Native sensor width in pixels. */ + uint32_t sensor_height; /** Native sensor height in lines. When shading_settings.enable_shading_table_conversion is set as 0, sensor_width and sensor_height are NOT used. These are used only in the legacy shading table conversion in the css, when shading_settings. enable_shading_table_conversion is set as 1. */ /* ------ deprecated(bz675) : to ------ */ - uint32_t width; /**< Number of data points per line per color. + uint32_t width; /** Number of data points per line per color. u8.0, [0,81] */ - uint32_t height; /**< Number of lines of data points per color. + uint32_t height; /** Number of lines of data points per color. u8.0, [0,61] */ - uint32_t fraction_bits; /**< Bits of fractional part in the data + uint32_t fraction_bits; /** Bits of fractional part in the data points. u8.0, [0,13] */ uint16_t *data[IA_CSS_SC_NUM_COLORS]; - /**< Table data, one array for each color. + /** Table data, one array for each color. Use ia_css_sc_color to index this array. u[13-fraction_bits].[fraction_bits], [0,8191] */ }; /* ------ deprecated(bz675) : from ------ */ -/** Shading Correction settings. +/* Shading Correction settings. * * NOTE: * This structure should be removed when the shading table conversion is * removed from the css. */ struct ia_css_shading_settings { - uint32_t enable_shading_table_conversion; /**< Set to 0, + uint32_t enable_shading_table_conversion; /** Set to 0, if the conversion of the shading table should be disabled in the css. (default 1) 0: The shading table is directly sent to the isp. @@ -119,14 +119,14 @@ struct ia_css_shading_settings { #ifdef ISP2401 -/** Shading Correction configuration. +/* Shading Correction configuration. * * NOTE: The shading table size is larger than or equal to the internal frame size. */ struct ia_css_sc_configuration { - uint32_t internal_frame_origin_x_bqs_on_sctbl; /**< Origin X (in bqs) of internal frame on shading table. */ - uint32_t internal_frame_origin_y_bqs_on_sctbl; /**< Origin Y (in bqs) of internal frame on shading table. */ - /**< NOTE: bqs = size in BQ(Bayer Quad) unit. + uint32_t internal_frame_origin_x_bqs_on_sctbl; /** Origin X (in bqs) of internal frame on shading table. */ + uint32_t internal_frame_origin_y_bqs_on_sctbl; /** Origin Y (in bqs) of internal frame on shading table. */ + /** NOTE: bqs = size in BQ(Bayer Quad) unit. 1BQ means {Gr,R,B,Gb}(2x2 pixels). Horizontal 1 bqs corresponds to horizontal 2 pixels. Vertical 1 bqs corresponds to vertical 2 pixels. */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common_types.h index 295dc60b778c..031983c357e4 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common_types.h @@ -15,21 +15,21 @@ #ifndef __IA_CSS_SDIS_COMMON_TYPES_H #define __IA_CSS_SDIS_COMMON_TYPES_H -/** @file +/* @file * CSS-API header file for DVS statistics parameters. */ #include -/** DVS statistics grid dimensions in number of cells. +/* DVS statistics grid dimensions in number of cells. */ struct ia_css_dvs_grid_dim { - uint32_t width; /**< Width of DVS grid table in cells */ - uint32_t height; /**< Height of DVS grid table in cells */ + uint32_t width; /** Width of DVS grid table in cells */ + uint32_t height; /** Height of DVS grid table in cells */ }; -/** DVS statistics dimensions in number of cells for +/* DVS statistics dimensions in number of cells for * grid, coeffieicient and projection. */ @@ -55,7 +55,7 @@ struct ia_css_sdis_info { 0, /* dis_deci_factor_log2 */ \ } -/** DVS statistics grid +/* DVS statistics grid * * ISP block: SDVS1 (DIS/DVS Support for DIS/DVS ver.1 (2-axes)) * SDVS2 (DVS Support for DVS ver.2 (6-axes)) @@ -63,23 +63,23 @@ struct ia_css_sdis_info { * ISP2: SDVS2 is used. */ struct ia_css_dvs_grid_res { - uint32_t width; /**< Width of DVS grid table. + uint32_t width; /** Width of DVS grid table. (= Horizontal number of grid cells in table, which cells have effective statistics.) For DVS1, this is equal to the number of vertical statistics. */ - uint32_t aligned_width; /**< Stride of each grid line. + uint32_t aligned_width; /** Stride of each grid line. (= Horizontal number of grid cells in table, which means the allocated width.) */ - uint32_t height; /**< Height of DVS grid table. + uint32_t height; /** Height of DVS grid table. (= Vertical number of grid cells in table, which cells have effective statistics.) For DVS1, This is equal to the number of horizontal statistics. */ - uint32_t aligned_height;/**< Stride of each grid column. + uint32_t aligned_height;/** Stride of each grid column. (= Vertical number of grid cells in table, which means the allocated height.) */ @@ -89,125 +89,125 @@ struct ia_css_dvs_grid_res { * However, that implies driver I/F changes */ struct ia_css_dvs_grid_info { - uint32_t enable; /**< DVS statistics enabled. + uint32_t enable; /** DVS statistics enabled. 0:disabled, 1:enabled */ - uint32_t width; /**< Width of DVS grid table. + uint32_t width; /** Width of DVS grid table. (= Horizontal number of grid cells in table, which cells have effective statistics.) For DVS1, this is equal to the number of vertical statistics. */ - uint32_t aligned_width; /**< Stride of each grid line. + uint32_t aligned_width; /** Stride of each grid line. (= Horizontal number of grid cells in table, which means the allocated width.) */ - uint32_t height; /**< Height of DVS grid table. + uint32_t height; /** Height of DVS grid table. (= Vertical number of grid cells in table, which cells have effective statistics.) For DVS1, This is equal to the number of horizontal statistics. */ - uint32_t aligned_height;/**< Stride of each grid column. + uint32_t aligned_height;/** Stride of each grid column. (= Vertical number of grid cells in table, which means the allocated height.) */ - uint32_t bqs_per_grid_cell; /**< Grid cell size in BQ(Bayer Quad) unit. + uint32_t bqs_per_grid_cell; /** Grid cell size in BQ(Bayer Quad) unit. (1BQ means {Gr,R,B,Gb}(2x2 pixels).) For DVS1, valid value is 64. For DVS2, valid value is only 64, currently. */ - uint32_t num_hor_coefs; /**< Number of horizontal coefficients. */ - uint32_t num_ver_coefs; /**< Number of vertical coefficients. */ + uint32_t num_hor_coefs; /** Number of horizontal coefficients. */ + uint32_t num_ver_coefs; /** Number of vertical coefficients. */ }; -/** Number of DVS statistics levels +/* Number of DVS statistics levels */ #define IA_CSS_DVS_STAT_NUM_OF_LEVELS 3 -/** DVS statistics generated by accelerator global configuration +/* DVS statistics generated by accelerator global configuration */ struct dvs_stat_public_dvs_global_cfg { unsigned char kappa; - /**< DVS statistics global configuration - kappa */ + /** DVS statistics global configuration - kappa */ unsigned char match_shift; - /**< DVS statistics global configuration - match_shift */ + /** DVS statistics global configuration - match_shift */ unsigned char ybin_mode; - /**< DVS statistics global configuration - y binning mode */ + /** DVS statistics global configuration - y binning mode */ }; -/** DVS statistics generated by accelerator level grid +/* DVS statistics generated by accelerator level grid * configuration */ struct dvs_stat_public_dvs_level_grid_cfg { unsigned char grid_width; - /**< DVS statistics grid width */ + /** DVS statistics grid width */ unsigned char grid_height; - /**< DVS statistics grid height */ + /** DVS statistics grid height */ unsigned char block_width; - /**< DVS statistics block width */ + /** DVS statistics block width */ unsigned char block_height; - /**< DVS statistics block height */ + /** DVS statistics block height */ }; -/** DVS statistics generated by accelerator level grid start +/* DVS statistics generated by accelerator level grid start * configuration */ struct dvs_stat_public_dvs_level_grid_start { unsigned short x_start; - /**< DVS statistics level x start */ + /** DVS statistics level x start */ unsigned short y_start; - /**< DVS statistics level y start */ + /** DVS statistics level y start */ unsigned char enable; - /**< DVS statistics level enable */ + /** DVS statistics level enable */ }; -/** DVS statistics generated by accelerator level grid end +/* DVS statistics generated by accelerator level grid end * configuration */ struct dvs_stat_public_dvs_level_grid_end { unsigned short x_end; - /**< DVS statistics level x end */ + /** DVS statistics level x end */ unsigned short y_end; - /**< DVS statistics level y end */ + /** DVS statistics level y end */ }; -/** DVS statistics generated by accelerator Feature Extraction +/* DVS statistics generated by accelerator Feature Extraction * Region Of Interest (FE-ROI) configuration */ struct dvs_stat_public_dvs_level_fe_roi_cfg { unsigned char x_start; - /**< DVS statistics fe-roi level x start */ + /** DVS statistics fe-roi level x start */ unsigned char y_start; - /**< DVS statistics fe-roi level y start */ + /** DVS statistics fe-roi level y start */ unsigned char x_end; - /**< DVS statistics fe-roi level x end */ + /** DVS statistics fe-roi level x end */ unsigned char y_end; - /**< DVS statistics fe-roi level y end */ + /** DVS statistics fe-roi level y end */ }; -/** DVS statistics generated by accelerator public configuration +/* DVS statistics generated by accelerator public configuration */ struct dvs_stat_public_dvs_grd_cfg { struct dvs_stat_public_dvs_level_grid_cfg grd_cfg; - /**< DVS statistics level grid configuration */ + /** DVS statistics level grid configuration */ struct dvs_stat_public_dvs_level_grid_start grd_start; - /**< DVS statistics level grid start configuration */ + /** DVS statistics level grid start configuration */ struct dvs_stat_public_dvs_level_grid_end grd_end; - /**< DVS statistics level grid end configuration */ + /** DVS statistics level grid end configuration */ }; -/** DVS statistics grid generated by accelerator +/* DVS statistics grid generated by accelerator */ struct ia_css_dvs_stat_grid_info { struct dvs_stat_public_dvs_global_cfg dvs_gbl_cfg; - /**< DVS statistics global configuration (kappa, match, binning) */ + /** DVS statistics global configuration (kappa, match, binning) */ struct dvs_stat_public_dvs_grd_cfg grd_cfg[IA_CSS_DVS_STAT_NUM_OF_LEVELS]; - /**< DVS statistics grid configuration (blocks and grids) */ + /** DVS statistics grid configuration (blocks and grids) */ struct dvs_stat_public_dvs_level_fe_roi_cfg fe_roi_cfg[IA_CSS_DVS_STAT_NUM_OF_LEVELS]; - /**< DVS statistics FE ROI (region of interest) configuration */ + /** DVS statistics FE ROI (region of interest) configuration */ }; -/** DVS statistics generated by accelerator default grid info +/* DVS statistics generated by accelerator default grid info */ #define DEFAULT_DVS_GRID_INFO { \ { \ @@ -219,14 +219,14 @@ struct ia_css_dvs_stat_grid_info { } -/** Union that holds all types of DVS statistics grid info in +/* Union that holds all types of DVS statistics grid info in * CSS format * */ union ia_css_dvs_grid_u { struct ia_css_dvs_stat_grid_info dvs_stat_grid_info; - /**< DVS statistics produced by accelerator grid info */ + /** DVS statistics produced by accelerator grid info */ struct ia_css_dvs_grid_info dvs_grid_info; - /**< DVS (DVS1/DVS2) grid info */ + /** DVS (DVS1/DVS2) grid info */ }; #endif /* __IA_CSS_SDIS_COMMON_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis_types.h index d408b58a027d..d2ee57008fb6 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis_types.h @@ -15,38 +15,38 @@ #ifndef __IA_CSS_SDIS_TYPES_H #define __IA_CSS_SDIS_TYPES_H -/** @file +/* @file * CSS-API header file for DVS statistics parameters. */ -/** Number of DVS coefficient types */ +/* Number of DVS coefficient types */ #define IA_CSS_DVS_NUM_COEF_TYPES 6 #ifndef PIPE_GENERATION #include "isp/kernels/sdis/common/ia_css_sdis_common_types.h" #endif -/** DVS 1.0 Coefficients. +/* DVS 1.0 Coefficients. * This structure describes the coefficients that are needed for the dvs statistics. */ struct ia_css_dvs_coefficients { - struct ia_css_dvs_grid_info grid;/**< grid info contains the dimensions of the dvs grid */ - int16_t *hor_coefs; /**< the pointer to int16_t[grid.num_hor_coefs * IA_CSS_DVS_NUM_COEF_TYPES] + struct ia_css_dvs_grid_info grid;/** grid info contains the dimensions of the dvs grid */ + int16_t *hor_coefs; /** the pointer to int16_t[grid.num_hor_coefs * IA_CSS_DVS_NUM_COEF_TYPES] containing the horizontal coefficients */ - int16_t *ver_coefs; /**< the pointer to int16_t[grid.num_ver_coefs * IA_CSS_DVS_NUM_COEF_TYPES] + int16_t *ver_coefs; /** the pointer to int16_t[grid.num_ver_coefs * IA_CSS_DVS_NUM_COEF_TYPES] containing the vertical coefficients */ }; -/** DVS 1.0 Statistics. +/* DVS 1.0 Statistics. * This structure describes the statistics that are generated using the provided coefficients. */ struct ia_css_dvs_statistics { - struct ia_css_dvs_grid_info grid;/**< grid info contains the dimensions of the dvs grid */ - int32_t *hor_proj; /**< the pointer to int16_t[grid.height * IA_CSS_DVS_NUM_COEF_TYPES] + struct ia_css_dvs_grid_info grid;/** grid info contains the dimensions of the dvs grid */ + int32_t *hor_proj; /** the pointer to int16_t[grid.height * IA_CSS_DVS_NUM_COEF_TYPES] containing the horizontal projections */ - int32_t *ver_proj; /**< the pointer to int16_t[grid.width * IA_CSS_DVS_NUM_COEF_TYPES] + int32_t *ver_proj; /** the pointer to int16_t[grid.width * IA_CSS_DVS_NUM_COEF_TYPES] containing the vertical projections */ }; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2_types.h index 7db7dd10fe00..2a0bc4031746 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2_types.h @@ -15,55 +15,55 @@ #ifndef __IA_CSS_SDIS2_TYPES_H #define __IA_CSS_SDIS2_TYPES_H -/** @file +/* @file * CSS-API header file for DVS statistics parameters. */ -/** Number of DVS coefficient types */ +/* Number of DVS coefficient types */ #define IA_CSS_DVS2_NUM_COEF_TYPES 4 #ifndef PIPE_GENERATION #include "isp/kernels/sdis/common/ia_css_sdis_common_types.h" #endif -/** DVS 2.0 Coefficient types. This structure contains 4 pointers to +/* DVS 2.0 Coefficient types. This structure contains 4 pointers to * arrays that contain the coeffients for each type. */ struct ia_css_dvs2_coef_types { - int16_t *odd_real; /**< real part of the odd coefficients*/ - int16_t *odd_imag; /**< imaginary part of the odd coefficients*/ - int16_t *even_real;/**< real part of the even coefficients*/ - int16_t *even_imag;/**< imaginary part of the even coefficients*/ + int16_t *odd_real; /** real part of the odd coefficients*/ + int16_t *odd_imag; /** imaginary part of the odd coefficients*/ + int16_t *even_real;/** real part of the even coefficients*/ + int16_t *even_imag;/** imaginary part of the even coefficients*/ }; -/** DVS 2.0 Coefficients. This structure describes the coefficients that are needed for the dvs statistics. +/* DVS 2.0 Coefficients. This structure describes the coefficients that are needed for the dvs statistics. * e.g. hor_coefs.odd_real is the pointer to int16_t[grid.num_hor_coefs] containing the horizontal odd real * coefficients. */ struct ia_css_dvs2_coefficients { - struct ia_css_dvs_grid_info grid; /**< grid info contains the dimensions of the dvs grid */ - struct ia_css_dvs2_coef_types hor_coefs; /**< struct with pointers that contain the horizontal coefficients */ - struct ia_css_dvs2_coef_types ver_coefs; /**< struct with pointers that contain the vertical coefficients */ + struct ia_css_dvs_grid_info grid; /** grid info contains the dimensions of the dvs grid */ + struct ia_css_dvs2_coef_types hor_coefs; /** struct with pointers that contain the horizontal coefficients */ + struct ia_css_dvs2_coef_types ver_coefs; /** struct with pointers that contain the vertical coefficients */ }; -/** DVS 2.0 Statistic types. This structure contains 4 pointers to +/* DVS 2.0 Statistic types. This structure contains 4 pointers to * arrays that contain the statistics for each type. */ struct ia_css_dvs2_stat_types { - int32_t *odd_real; /**< real part of the odd statistics*/ - int32_t *odd_imag; /**< imaginary part of the odd statistics*/ - int32_t *even_real;/**< real part of the even statistics*/ - int32_t *even_imag;/**< imaginary part of the even statistics*/ + int32_t *odd_real; /** real part of the odd statistics*/ + int32_t *odd_imag; /** imaginary part of the odd statistics*/ + int32_t *even_real;/** real part of the even statistics*/ + int32_t *even_imag;/** imaginary part of the even statistics*/ }; -/** DVS 2.0 Statistics. This structure describes the statistics that are generated using the provided coefficients. +/* DVS 2.0 Statistics. This structure describes the statistics that are generated using the provided coefficients. * e.g. hor_prod.odd_real is the pointer to int16_t[grid.aligned_height][grid.aligned_width] containing * the horizontal odd real statistics. Valid statistics data area is int16_t[0..grid.height-1][0..grid.width-1] */ struct ia_css_dvs2_statistics { - struct ia_css_dvs_grid_info grid; /**< grid info contains the dimensions of the dvs grid */ - struct ia_css_dvs2_stat_types hor_prod; /**< struct with pointers that contain the horizontal statistics */ - struct ia_css_dvs2_stat_types ver_prod; /**< struct with pointers that contain the vertical statistics */ + struct ia_css_dvs_grid_info grid; /** grid info contains the dimensions of the dvs grid */ + struct ia_css_dvs2_stat_types hor_prod; /** struct with pointers that contain the horizontal statistics */ + struct ia_css_dvs2_stat_types ver_prod; /** struct with pointers that contain the vertical statistics */ }; #endif /* __IA_CSS_SDIS2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_types.h index cc47a50e5ad5..91ea8dd4651d 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_types.h @@ -15,13 +15,13 @@ #ifndef __IA_CSS_TDF_TYPES_H #define __IA_CSS_TDF_TYPES_H -/** @file +/* @file * CSS-API header file for Transform Domain Filter parameters. */ #include "type_support.h" -/** Transform Domain Filter configuration +/* Transform Domain Filter configuration * * \brief TDF public parameters. * \details Struct with all parameters for the TDF kernel that can be set @@ -30,23 +30,23 @@ * ISP2.6.1: TDF is used. */ struct ia_css_tdf_config { - int32_t thres_flat_table[64]; /**< Final optimized strength table of NR for flat region. */ - int32_t thres_detail_table[64]; /**< Final optimized strength table of NR for detail region. */ - int32_t epsilon_0; /**< Coefficient to control variance for dark area (for flat region). */ - int32_t epsilon_1; /**< Coefficient to control variance for bright area (for flat region). */ - int32_t eps_scale_text; /**< Epsilon scaling coefficient for texture region. */ - int32_t eps_scale_edge; /**< Epsilon scaling coefficient for edge region. */ - int32_t sepa_flat; /**< Threshold to judge flat (edge < m_Flat_thre). */ - int32_t sepa_edge; /**< Threshold to judge edge (edge > m_Edge_thre). */ - int32_t blend_flat; /**< Blending ratio at flat region. */ - int32_t blend_text; /**< Blending ratio at texture region. */ - int32_t blend_edge; /**< Blending ratio at edge region. */ - int32_t shading_gain; /**< Gain of Shading control. */ - int32_t shading_base_gain; /**< Base Gain of Shading control. */ - int32_t local_y_gain; /**< Gain of local luminance control. */ - int32_t local_y_base_gain; /**< Base gain of local luminance control. */ - int32_t rad_x_origin; /**< Initial x coord. for radius computation. */ - int32_t rad_y_origin; /**< Initial y coord. for radius computation. */ + int32_t thres_flat_table[64]; /** Final optimized strength table of NR for flat region. */ + int32_t thres_detail_table[64]; /** Final optimized strength table of NR for detail region. */ + int32_t epsilon_0; /** Coefficient to control variance for dark area (for flat region). */ + int32_t epsilon_1; /** Coefficient to control variance for bright area (for flat region). */ + int32_t eps_scale_text; /** Epsilon scaling coefficient for texture region. */ + int32_t eps_scale_edge; /** Epsilon scaling coefficient for edge region. */ + int32_t sepa_flat; /** Threshold to judge flat (edge < m_Flat_thre). */ + int32_t sepa_edge; /** Threshold to judge edge (edge > m_Edge_thre). */ + int32_t blend_flat; /** Blending ratio at flat region. */ + int32_t blend_text; /** Blending ratio at texture region. */ + int32_t blend_edge; /** Blending ratio at edge region. */ + int32_t shading_gain; /** Gain of Shading control. */ + int32_t shading_base_gain; /** Base Gain of Shading control. */ + int32_t local_y_gain; /** Gain of local luminance control. */ + int32_t local_y_base_gain; /** Base gain of local luminance control. */ + int32_t rad_x_origin; /** Initial x coord. for radius computation. */ + int32_t rad_y_origin; /** Initial y coord. for radius computation. */ }; #endif /* __IA_CSS_TDF_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr3/ia_css_tnr3_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr3/ia_css_tnr3_types.h index 135563f52174..223423f8c40b 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr3/ia_css_tnr3_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr3/ia_css_tnr3_types.h @@ -16,7 +16,7 @@ more details. #ifndef _IA_CSS_TNR3_TYPES_H #define _IA_CSS_TNR3_TYPES_H -/** @file +/* @file * CSS-API header file for Temporal Noise Reduction v3 (TNR3) kernel */ @@ -27,7 +27,7 @@ more details. */ #define TNR3_NUM_SEGMENTS 3 -/** Temporal Noise Reduction v3 (TNR3) configuration. +/* Temporal Noise Reduction v3 (TNR3) configuration. * The parameter to this kernel is fourfold * 1. Three piecewise linear graphs (one for each plane) with three segments * each. Each line graph has Luma values on the x axis and sigma values for @@ -44,17 +44,17 @@ more details. * 4. Selection of the reference frame buffer to be used for noise reduction. */ struct ia_css_tnr3_kernel_config { - unsigned int maxfb_y; /**< Maximum Feedback Gain for Y */ - unsigned int maxfb_u; /**< Maximum Feedback Gain for U */ - unsigned int maxfb_v; /**< Maximum Feedback Gain for V */ - unsigned int round_adj_y; /**< Rounding Adjust for Y */ - unsigned int round_adj_u; /**< Rounding Adjust for U */ - unsigned int round_adj_v; /**< Rounding Adjust for V */ - unsigned int knee_y[TNR3_NUM_SEGMENTS - 1]; /**< Knee points */ - unsigned int sigma_y[TNR3_NUM_SEGMENTS + 1]; /**< Standard deviation for Y at points Y0, Y1, Y2, Y3 */ - unsigned int sigma_u[TNR3_NUM_SEGMENTS + 1]; /**< Standard deviation for U at points U0, U1, U2, U3 */ - unsigned int sigma_v[TNR3_NUM_SEGMENTS + 1]; /**< Standard deviation for V at points V0, V1, V2, V3 */ - unsigned int ref_buf_select; /**< Selection of the reference buffer */ + unsigned int maxfb_y; /** Maximum Feedback Gain for Y */ + unsigned int maxfb_u; /** Maximum Feedback Gain for U */ + unsigned int maxfb_v; /** Maximum Feedback Gain for V */ + unsigned int round_adj_y; /** Rounding Adjust for Y */ + unsigned int round_adj_u; /** Rounding Adjust for U */ + unsigned int round_adj_v; /** Rounding Adjust for V */ + unsigned int knee_y[TNR3_NUM_SEGMENTS - 1]; /** Knee points */ + unsigned int sigma_y[TNR3_NUM_SEGMENTS + 1]; /** Standard deviation for Y at points Y0, Y1, Y2, Y3 */ + unsigned int sigma_u[TNR3_NUM_SEGMENTS + 1]; /** Standard deviation for U at points U0, U1, U2, U3 */ + unsigned int sigma_v[TNR3_NUM_SEGMENTS + 1]; /** Standard deviation for V at points V0, V1, V2, V3 */ + unsigned int ref_buf_select; /** Selection of the reference buffer */ }; #endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_types.h index 4fd35e6ccd70..9bbc9ab2e6c0 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_types.h @@ -15,11 +15,11 @@ #ifndef __IA_CSS_TNR_TYPES_H #define __IA_CSS_TNR_TYPES_H -/** @file +/* @file * CSS-API header file for Temporal Noise Reduction (TNR) parameters. */ -/** Temporal Noise Reduction (TNR) configuration. +/* Temporal Noise Reduction (TNR) configuration. * * When difference between current frame and previous frame is less than or * equal to threshold, TNR works and current frame is mixed @@ -36,18 +36,18 @@ struct ia_css_tnr_config { - ia_css_u0_16 gain; /**< Interpolation ratio of current frame + ia_css_u0_16 gain; /** Interpolation ratio of current frame and previous frame. gain=0.0 -> previous frame is outputted. gain=1.0 -> current frame is outputted. u0.16, [0,65535], default 32768(0.5), ineffective 65535(almost 1.0) */ - ia_css_u0_16 threshold_y; /**< Threshold to enable interpolation of Y. + ia_css_u0_16 threshold_y; /** Threshold to enable interpolation of Y. If difference between current frame and previous frame is greater than threshold_y, TNR for Y is disabled. u0.16, [0,65535], default/ineffective 0 */ - ia_css_u0_16 threshold_uv; /**< Threshold to enable interpolation of + ia_css_u0_16 threshold_uv; /** Threshold to enable interpolation of U/V. If difference between current frame and previous frame is greater than threshold_uv, diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_param.h index df5d37c8c946..9df4e12f6c2c 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_param.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_param.h @@ -23,9 +23,9 @@ #define VFDEC_BITS_PER_PIXEL GAMMA_OUTPUT_BITS -/** Viewfinder decimation */ +/* Viewfinder decimation */ struct sh_css_isp_vf_isp_config { - uint32_t vf_downscale_bits; /**< Log VF downscale value */ + uint32_t vf_downscale_bits; /** Log VF downscale value */ uint32_t enable; struct ia_css_frame_sp_info info; struct { diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_types.h index d8cfdfbc8c0b..e3efafa279ff 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_types.h @@ -15,7 +15,7 @@ #ifndef __IA_CSS_VF_TYPES_H #define __IA_CSS_VF_TYPES_H -/** Viewfinder decimation +/* Viewfinder decimation * * ISP block: vfeven_horizontal_downscale */ @@ -24,7 +24,7 @@ #include struct ia_css_vf_configuration { - uint32_t vf_downscale_bits; /**< Log VF downscale value */ + uint32_t vf_downscale_bits; /** Log VF downscale value */ const struct ia_css_frame_info *info; }; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb_types.h index 6bcfa274be88..bf98734d057e 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb_types.h @@ -15,31 +15,31 @@ #ifndef __IA_CSS_WB_TYPES_H #define __IA_CSS_WB_TYPES_H -/** @file +/* @file * CSS-API header file for White Balance parameters. */ -/** White Balance configuration (Gain Adjust). +/* White Balance configuration (Gain Adjust). * * ISP block: WB1 * ISP1: WB1 is used. * ISP2: WB1 is used. */ struct ia_css_wb_config { - uint32_t integer_bits; /**< Common exponent of gains. + uint32_t integer_bits; /** Common exponent of gains. u8.0, [0,3], default 1, ineffective 1 */ - uint32_t gr; /**< Significand of Gr gain. + uint32_t gr; /** Significand of Gr gain. u[integer_bits].[16-integer_bits], [0,65535], default/ineffective 32768(u1.15, 1.0) */ - uint32_t r; /**< Significand of R gain. + uint32_t r; /** Significand of R gain. u[integer_bits].[16-integer_bits], [0,65535], default/ineffective 32768(u1.15, 1.0) */ - uint32_t b; /**< Significand of B gain. + uint32_t b; /** Significand of B gain. u[integer_bits].[16-integer_bits], [0,65535], default/ineffective 32768(u1.15, 1.0) */ - uint32_t gb; /**< Significand of Gb gain. + uint32_t gb; /** Significand of Gb gain. u[integer_bits].[16-integer_bits], [0,65535], default/ineffective 32768(u1.15, 1.0) */ }; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.c index 3018100f6f76..abcb531f51cc 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.c @@ -21,7 +21,7 @@ #include "ia_css_xnr.host.h" const struct ia_css_xnr_config default_xnr_config = { - /** default threshold 6400 translates to 25 on ISP. */ + /* default threshold 6400 translates to 25 on ISP. */ 6400 }; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_param.h index 806c9f8f0e2e..a5caebbe2f84 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_param.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_param.h @@ -41,7 +41,7 @@ struct sh_css_isp_xnr_vamem_params { }; struct sh_css_isp_xnr_params { - /** XNR threshold. + /* XNR threshold. * type:u0.16 but actual valid range is:[0,255] * valid range is dependent on SH_CSS_ISP_YUV_BITS (currently 8bits) * default: 25 */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_types.h index 89e8b0f17e8c..d2b634211a3f 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_types.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_types.h @@ -15,11 +15,11 @@ #ifndef __IA_CSS_XNR_TYPES_H #define __IA_CSS_XNR_TYPES_H -/** @file +/* @file * CSS-API header file for Extra Noise Reduction (XNR) parameters. */ -/** XNR table. +/* XNR table. * * NOTE: The driver does not need to set this table, * because the default values are set inside the css. @@ -36,23 +36,23 @@ * */ -/** Number of elements in the xnr table. */ +/* Number of elements in the xnr table. */ #define IA_CSS_VAMEM_1_XNR_TABLE_SIZE_LOG2 6 -/** Number of elements in the xnr table. */ +/* Number of elements in the xnr table. */ #define IA_CSS_VAMEM_1_XNR_TABLE_SIZE (1U<)parameters, etc. */ uint32_t size; /* Disabled if 0 */ @@ -77,10 +77,10 @@ struct ia_css_isp_param_isp_segments { /* Memory offsets in binary info */ struct ia_css_isp_param_memory_offsets { - uint32_t offsets[IA_CSS_NUM_PARAM_CLASSES]; /**< offset wrt hdr in bytes */ + uint32_t offsets[IA_CSS_NUM_PARAM_CLASSES]; /** offset wrt hdr in bytes */ }; -/** Offsets for ISP kernel parameters per isp memory. +/* Offsets for ISP kernel parameters per isp memory. * Only relevant for standard ISP binaries, not ACC or SP. */ union ia_css_all_memory_offsets { diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/src/isp_param.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/src/isp_param.c index 832d9e16edeb..f793ce125f02 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/src/isp_param.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/src/isp_param.c @@ -13,7 +13,7 @@ * more details. */ #else -/** +/* Support for Intel Camera Imaging ISP subsystem. Copyright (c) 2010 - 2015, Intel Corporation. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/interface/ia_css_isys.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/interface/ia_css_isys.h index 02bf908d94e6..4cf2defe9ef0 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/interface/ia_css_isys.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/interface/ia_css_isys.h @@ -44,7 +44,7 @@ more details. * Virtual Input System. (Input System 2401) */ typedef input_system_cfg_t ia_css_isys_descr_t; -/** end of Virtual Input System */ +/* end of Virtual Input System */ #endif #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) @@ -112,7 +112,7 @@ unsigned int ia_css_isys_rx_translate_irq_infos(unsigned int bits); #endif /* #if !defined(USE_INPUT_SYSTEM_VERSION_2401) */ -/** @brief Translate format and compression to format type. +/* @brief Translate format and compression to format type. * * @param[in] input_format The input format. * @param[in] compression The compression scheme. @@ -195,7 +195,7 @@ extern void ia_css_isys_stream2mmio_sid_rmgr_release( stream2mmio_ID_t stream2mmio, stream2mmio_sid_ID_t *sid); -/** end of Virtual Input System */ +/* end of Virtual Input System */ #endif #endif /* __IA_CSS_ISYS_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/csi_rx_rmgr.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/csi_rx_rmgr.c index d1d4f79c00f1..3b04dc51335a 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/csi_rx_rmgr.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/csi_rx_rmgr.c @@ -13,7 +13,7 @@ * more details. */ #else -/** +/* Support for Intel Camera Imaging ISP subsystem. Copyright (c) 2010 - 2015, Intel Corporation. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/ibuf_ctrl_rmgr.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/ibuf_ctrl_rmgr.c index faef97672eac..d8c3b75d7fac 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/ibuf_ctrl_rmgr.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/ibuf_ctrl_rmgr.c @@ -13,7 +13,7 @@ * more details. */ #else -/** +/* * Support for Intel Camera Imaging ISP subsystem. * Copyright (c) 2010 - 2015, Intel Corporation. * diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_dma_rmgr.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_dma_rmgr.c index 5032627342d9..4def4a542b7d 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_dma_rmgr.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_dma_rmgr.c @@ -13,7 +13,7 @@ * more details. */ #else -/** +/* Support for Intel Camera Imaging ISP subsystem. Copyright (c) 2010 - 2015, Intel Corporation. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_init.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_init.c index 239ef310bdeb..4122084fd237 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_init.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_init.c @@ -13,7 +13,7 @@ * more details. */ #else -/** +/* Support for Intel Camera Imaging ISP subsystem. Copyright (c) 2010 - 2015, Intel Corporation. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_stream2mmio_rmgr.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_stream2mmio_rmgr.c index a93c7f44ff12..222b294c0ab0 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_stream2mmio_rmgr.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_stream2mmio_rmgr.c @@ -13,7 +13,7 @@ * more details. */ #else -/** +/* Support for Intel Camera Imaging ISP subsystem. Copyright (c) 2010 - 2015, Intel Corporation. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/rx.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/rx.c index 46a157f64343..70f6cb5e5918 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/rx.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/rx.c @@ -13,7 +13,7 @@ * more details. */ #else -/** +/* Support for Intel Camera Imaging ISP subsystem. Copyright (c) 2010 - 2015, Intel Corporation. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/virtual_isys.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/virtual_isys.c index 0f1e8a2f6b10..90922a7acefd 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/virtual_isys.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/virtual_isys.c @@ -13,7 +13,7 @@ * more details. */ #else -/** +/* Support for Intel Camera Imaging ISP subsystem. Copyright (c) 2010 - 2015, Intel Corporation. @@ -166,7 +166,7 @@ static int32_t calculate_stride( bool raw_packed, int32_t align_in_bytes); -/** end of Forwarded Declaration */ +/* end of Forwarded Declaration */ /************************************************** * @@ -292,7 +292,7 @@ ia_css_isys_error_t ia_css_isys_stream_calculate_cfg( return rc; } -/** end of Public Methods */ +/* end of Public Methods */ /************************************************** * @@ -894,5 +894,5 @@ static csi_mipi_packet_type_t get_csi_mipi_packet_type( return packet_type; } -/** end of Private Methods */ +/* end of Private Methods */ #endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/interface/ia_css_pipeline.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/interface/ia_css_pipeline.h index 90646f5f8885..e64936e2d46e 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/interface/ia_css_pipeline.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/interface/ia_css_pipeline.h @@ -103,7 +103,7 @@ struct ia_css_pipeline_stage_desc { struct ia_css_frame *vf_frame; }; -/** @brief initialize the pipeline module +/* @brief initialize the pipeline module * * @return None * @@ -112,7 +112,7 @@ struct ia_css_pipeline_stage_desc { */ void ia_css_pipeline_init(void); -/** @brief initialize the pipeline structure with default values +/* @brief initialize the pipeline structure with default values * * @param[out] pipeline structure to be initialized with defaults * @param[in] pipe_id @@ -129,7 +129,7 @@ enum ia_css_err ia_css_pipeline_create( unsigned int pipe_num, unsigned int dvs_frame_delay); -/** @brief destroy a pipeline +/* @brief destroy a pipeline * * @param[in] pipeline * @return None @@ -138,7 +138,7 @@ enum ia_css_err ia_css_pipeline_create( void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline); -/** @brief Starts a pipeline +/* @brief Starts a pipeline * * @param[in] pipe_id * @param[in] pipeline @@ -148,7 +148,7 @@ void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline); void ia_css_pipeline_start(enum ia_css_pipe_id pipe_id, struct ia_css_pipeline *pipeline); -/** @brief Request to stop a pipeline +/* @brief Request to stop a pipeline * * @param[in] pipeline * @return IA_CSS_SUCCESS or error code upon error. @@ -156,7 +156,7 @@ void ia_css_pipeline_start(enum ia_css_pipe_id pipe_id, */ enum ia_css_err ia_css_pipeline_request_stop(struct ia_css_pipeline *pipeline); -/** @brief Check whether pipeline has stopped +/* @brief Check whether pipeline has stopped * * @param[in] pipeline * @return true if the pipeline has stopped @@ -164,7 +164,7 @@ enum ia_css_err ia_css_pipeline_request_stop(struct ia_css_pipeline *pipeline); */ bool ia_css_pipeline_has_stopped(struct ia_css_pipeline *pipe); -/** @brief clean all the stages pipeline and make it as new +/* @brief clean all the stages pipeline and make it as new * * @param[in] pipeline * @return None @@ -172,7 +172,7 @@ bool ia_css_pipeline_has_stopped(struct ia_css_pipeline *pipe); */ void ia_css_pipeline_clean(struct ia_css_pipeline *pipeline); -/** @brief Add a stage to pipeline. +/* @brief Add a stage to pipeline. * * @param pipeline Pointer to the pipeline to be added to. * @param[in] stage_desc The description of the stage @@ -188,7 +188,7 @@ enum ia_css_err ia_css_pipeline_create_and_add_stage( struct ia_css_pipeline_stage_desc *stage_desc, struct ia_css_pipeline_stage **stage); -/** @brief Finalize the stages in a pipeline +/* @brief Finalize the stages in a pipeline * * @param pipeline Pointer to the pipeline to be added to. * @return None @@ -198,7 +198,7 @@ enum ia_css_err ia_css_pipeline_create_and_add_stage( void ia_css_pipeline_finalize_stages(struct ia_css_pipeline *pipeline, bool continuous); -/** @brief gets a stage from the pipeline +/* @brief gets a stage from the pipeline * * @param[in] pipeline * @return IA_CSS_SUCCESS or error code upon error. @@ -208,7 +208,7 @@ enum ia_css_err ia_css_pipeline_get_stage(struct ia_css_pipeline *pipeline, int mode, struct ia_css_pipeline_stage **stage); -/** @brief Gets a pipeline stage corresponding Firmware handle from the pipeline +/* @brief Gets a pipeline stage corresponding Firmware handle from the pipeline * * @param[in] pipeline * @param[in] fw_handle @@ -221,7 +221,7 @@ enum ia_css_err ia_css_pipeline_get_stage_from_fw(struct ia_css_pipeline *pipeli uint32_t fw_handle, struct ia_css_pipeline_stage **stage); -/** @brief Gets the Firmware handle correponding the stage num from the pipeline +/* @brief Gets the Firmware handle correponding the stage num from the pipeline * * @param[in] pipeline * @param[in] stage_num @@ -234,7 +234,7 @@ enum ia_css_err ia_css_pipeline_get_fw_from_stage(struct ia_css_pipeline *pipeli uint32_t stage_num, uint32_t *fw_handle); -/** @brief gets the output stage from the pipeline +/* @brief gets the output stage from the pipeline * * @param[in] pipeline * @return IA_CSS_SUCCESS or error code upon error. @@ -245,7 +245,7 @@ enum ia_css_err ia_css_pipeline_get_output_stage( int mode, struct ia_css_pipeline_stage **stage); -/** @brief Checks whether the pipeline uses params +/* @brief Checks whether the pipeline uses params * * @param[in] pipeline * @return true if the pipeline uses params diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/src/pipeline.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/src/pipeline.c index 62d13978475d..8f93d29d1c51 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/src/pipeline.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/src/pipeline.c @@ -13,7 +13,7 @@ * more details. */ #else -/** +/* Support for Intel Camera Imaging ISP subsystem. Copyright (c) 2010 - 2015, Intel Corporation. @@ -114,7 +114,7 @@ void ia_css_pipeline_map(unsigned int pipe_num, bool map) IA_CSS_LEAVE_PRIVATE("void"); } -/** @brief destroy a pipeline +/* @brief destroy a pipeline * * @param[in] pipeline * @return None @@ -187,7 +187,7 @@ void ia_css_pipeline_start(enum ia_css_pipe_id pipe_id, "ia_css_pipeline_start() leave: return_void\n"); } -/** +/* * @brief Query the SP thread ID. * Refer to "sh_css_internal.h" for details. */ @@ -285,7 +285,7 @@ void ia_css_pipeline_clean(struct ia_css_pipeline *pipeline) IA_CSS_LEAVE_PRIVATE("void"); } -/** @brief Add a stage to pipeline. +/* @brief Add a stage to pipeline. * * @param pipeline Pointer to the pipeline to be added to. * @param[in] stage_desc The description of the stage diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/interface/ia_css_queue.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/interface/ia_css_queue.h index e50a0f813753..aaf2e247cafb 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/interface/ia_css_queue.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/interface/ia_css_queue.h @@ -51,7 +51,7 @@ typedef struct ia_css_queue ia_css_queue_t; /***************************************************************************** * Queue Public APIs *****************************************************************************/ -/** @brief Initialize a local queue instance. +/* @brief Initialize a local queue instance. * * @param[out] qhandle. Handle to queue instance for use with API * @param[in] desc. Descriptor with queue properties filled-in @@ -63,7 +63,7 @@ extern int ia_css_queue_local_init( ia_css_queue_t *qhandle, ia_css_queue_local_t *desc); -/** @brief Initialize a remote queue instance +/* @brief Initialize a remote queue instance * * @param[out] qhandle. Handle to queue instance for use with API * @param[in] desc. Descriptor with queue properties filled-in @@ -74,7 +74,7 @@ extern int ia_css_queue_remote_init( ia_css_queue_t *qhandle, ia_css_queue_remote_t *desc); -/** @brief Uninitialize a queue instance +/* @brief Uninitialize a queue instance * * @param[in] qhandle. Handle to queue instance * @return 0 - Successful uninit. @@ -83,7 +83,7 @@ extern int ia_css_queue_remote_init( extern int ia_css_queue_uninit( ia_css_queue_t *qhandle); -/** @brief Enqueue an item in the queue instance +/* @brief Enqueue an item in the queue instance * * @param[in] qhandle. Handle to queue instance * @param[in] item. Object to be enqueued. @@ -96,7 +96,7 @@ extern int ia_css_queue_enqueue( ia_css_queue_t *qhandle, uint32_t item); -/** @brief Dequeue an item from the queue instance +/* @brief Dequeue an item from the queue instance * * @param[in] qhandle. Handle to queue instance * @param[out] item. Object to be dequeued into this item. @@ -110,7 +110,7 @@ extern int ia_css_queue_dequeue( ia_css_queue_t *qhandle, uint32_t *item); -/** @brief Check if the queue is empty +/* @brief Check if the queue is empty * * @param[in] qhandle. Handle to queue instance * @param[in] is_empty True if empty, False if not. @@ -123,7 +123,7 @@ extern int ia_css_queue_is_empty( ia_css_queue_t *qhandle, bool *is_empty); -/** @brief Check if the queue is full +/* @brief Check if the queue is full * * @param[in] qhandle. Handle to queue instance * @param[in] is_full True if Full, False if not. @@ -136,7 +136,7 @@ extern int ia_css_queue_is_full( ia_css_queue_t *qhandle, bool *is_full); -/** @brief Get used space in the queue +/* @brief Get used space in the queue * * @param[in] qhandle. Handle to queue instance * @param[in] size Number of available elements in the queue @@ -148,7 +148,7 @@ extern int ia_css_queue_get_used_space( ia_css_queue_t *qhandle, uint32_t *size); -/** @brief Get free space in the queue +/* @brief Get free space in the queue * * @param[in] qhandle. Handle to queue instance * @param[in] size Number of free elements in the queue @@ -160,7 +160,7 @@ extern int ia_css_queue_get_free_space( ia_css_queue_t *qhandle, uint32_t *size); -/** @brief Peek at an element in the queue +/* @brief Peek at an element in the queue * * @param[in] qhandle. Handle to queue instance * @param[in] offset Offset of element to peek, @@ -175,7 +175,7 @@ extern int ia_css_queue_peek( uint32_t offset, uint32_t *element); -/** @brief Get the usable size for the queue +/* @brief Get the usable size for the queue * * @param[in] qhandle. Handle to queue instance * @param[out] size Size value to be returned here. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue_access.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue_access.c index 946d4f2d2108..7bb2b494836e 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue_access.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue_access.c @@ -13,7 +13,7 @@ * more details. */ #else -/** +/* Support for Intel Camera Imaging ISP subsystem. Copyright (c) 2010 - 2015, Intel Corporation. diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr.c index efa9c140484f..370ff3816dbe 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr.c @@ -13,7 +13,7 @@ * more details. */ #else -/** +/* Support for Intel Camera Imaging ISP subsystem. Copyright (c) 2010 - 2015, Intel Corporation. @@ -44,7 +44,7 @@ enum ia_css_err ia_css_rmgr_init(void) return err; } -/** +/* * @brief Uninitialize resource pool (host) */ void ia_css_rmgr_uninit(void) diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr_vbuf.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr_vbuf.c index e56006c07ee8..54239ac9d7c9 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr_vbuf.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr_vbuf.c @@ -20,13 +20,13 @@ #include /* mmmgr_malloc, mhmm_free */ #include -/** +/* * @brief VBUF resource handles */ #define NUM_HANDLES 1000 struct ia_css_rmgr_vbuf_handle handle_table[NUM_HANDLES]; -/** +/* * @brief VBUF resource pool - refpool */ struct ia_css_rmgr_vbuf_pool refpool = { @@ -37,7 +37,7 @@ struct ia_css_rmgr_vbuf_pool refpool = { NULL, /* handles */ }; -/** +/* * @brief VBUF resource pool - writepool */ struct ia_css_rmgr_vbuf_pool writepool = { @@ -48,7 +48,7 @@ struct ia_css_rmgr_vbuf_pool writepool = { NULL, /* handles */ }; -/** +/* * @brief VBUF resource pool - hmmbufferpool */ struct ia_css_rmgr_vbuf_pool hmmbufferpool = { @@ -63,7 +63,7 @@ struct ia_css_rmgr_vbuf_pool *vbuf_ref = &refpool; struct ia_css_rmgr_vbuf_pool *vbuf_write = &writepool; struct ia_css_rmgr_vbuf_pool *hmm_buffer_pool = &hmmbufferpool; -/** +/* * @brief Initialize the reference count (host, vbuf) */ static void rmgr_refcount_init_vbuf(void) @@ -72,7 +72,7 @@ static void rmgr_refcount_init_vbuf(void) memset(&handle_table, 0, sizeof(handle_table)); } -/** +/* * @brief Retain the reference count for a handle (host, vbuf) * * @param handle The pointer to the handle @@ -109,7 +109,7 @@ void ia_css_rmgr_refcount_retain_vbuf(struct ia_css_rmgr_vbuf_handle **handle) (*handle)->count++; } -/** +/* * @brief Release the reference count for a handle (host, vbuf) * * @param handle The pointer to the handle @@ -131,7 +131,7 @@ void ia_css_rmgr_refcount_release_vbuf(struct ia_css_rmgr_vbuf_handle **handle) } } -/** +/* * @brief Initialize the resource pool (host, vbuf) * * @param pool The pointer to the pool @@ -163,7 +163,7 @@ enum ia_css_err ia_css_rmgr_init_vbuf(struct ia_css_rmgr_vbuf_pool *pool) return err; } -/** +/* * @brief Uninitialize the resource pool (host, vbuf) * * @param pool The pointer to the pool @@ -197,7 +197,7 @@ void ia_css_rmgr_uninit_vbuf(struct ia_css_rmgr_vbuf_pool *pool) } } -/** +/* * @brief Push a handle to the pool * * @param pool The pointer to the pool @@ -224,7 +224,7 @@ void rmgr_push_handle(struct ia_css_rmgr_vbuf_pool *pool, assert(succes); } -/** +/* * @brief Pop a handle from the pool * * @param pool The pointer to the pool @@ -254,7 +254,7 @@ void rmgr_pop_handle(struct ia_css_rmgr_vbuf_pool *pool, } } -/** +/* * @brief Acquire a handle from the pool (host, vbuf) * * @param pool The pointer to the pool @@ -302,7 +302,7 @@ void ia_css_rmgr_acq_vbuf(struct ia_css_rmgr_vbuf_pool *pool, ia_css_rmgr_refcount_retain_vbuf(handle); } -/** +/* * @brief Release a handle to the pool (host, vbuf) * * @param pool The pointer to the pool diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/spctrl/interface/ia_css_spctrl.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/spctrl/interface/ia_css_spctrl.h index 27e9eb1e2102..bc4b1723369e 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/spctrl/interface/ia_css_spctrl.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/spctrl/interface/ia_css_spctrl.h @@ -37,17 +37,17 @@ more details. typedef struct { - uint32_t ddr_data_offset; /**< posistion of data in DDR */ - uint32_t dmem_data_addr; /**< data segment address in dmem */ - uint32_t dmem_bss_addr; /**< bss segment address in dmem */ - uint32_t data_size; /**< data segment size */ - uint32_t bss_size; /**< bss segment size */ - uint32_t spctrl_config_dmem_addr; /** mode; IA_CSS_ENTER_PRIVATE("main_pipe_id=%d", main_pipe_id); - /** + /* * Check if every "ia_css_pipe" instance in this target * "ia_css_stream" instance has stopped. */ @@ -5229,7 +5229,7 @@ sh_css_pipes_have_stopped(struct ia_css_stream *stream) rval); } - /** + /* * In the CSS firmware use scenario "Continuous Preview" * as well as "Continuous Video", the "ia_css_pipe" instance * "Copy Pipe" is activated. This "Copy Pipe" is private to @@ -5474,7 +5474,7 @@ sh_css_pipe_get_grid_info(struct ia_css_pipe *pipe, } #ifdef ISP2401 -/** +/* * @brief Check if a format is supported by the pipe. * */ @@ -8626,7 +8626,7 @@ sh_css_pipeline_add_acc_stage(struct ia_css_pipeline *pipeline, return err; } -/** +/* * @brief Tag a specific frame in continuous capture. * Refer to "sh_css_internal.h" for details. */ @@ -8666,7 +8666,7 @@ enum ia_css_err ia_css_stream_capture_frame(struct ia_css_stream *stream, return err; } -/** +/* * @brief Configure the continuous capture. * Refer to "sh_css_internal.h" for details. */ @@ -8822,7 +8822,7 @@ sh_css_init_host_sp_control_vars(void) "sh_css_init_host_sp_control_vars() leave: return_void\n"); } -/** +/* * create the internal structures and fill in the configuration data */ void ia_css_pipe_config_defaults(struct ia_css_pipe_config *pipe_config) @@ -10435,7 +10435,7 @@ ia_css_start_sp(void) return err; } -/** +/* * Time to wait SP for termincate. Only condition when this can happen * is a fatal hw failure, but we must be able to detect this and emit * a proper error trace. @@ -10713,7 +10713,7 @@ ia_css_unlock_raw_frame(struct ia_css_stream *stream, uint32_t exp_id) return ret; } -/** @brief Set the state (Enable or Disable) of the Extension stage in the +/* @brief Set the state (Enable or Disable) of the Extension stage in the * given pipe. */ enum ia_css_err @@ -10758,7 +10758,7 @@ ia_css_pipe_set_qos_ext_state(struct ia_css_pipe *pipe, uint32_t fw_handle, bool return err; } -/** @brief Get the state (Enable or Disable) of the Extension stage in the +/* @brief Get the state (Enable or Disable) of the Extension stage in the * given pipe. */ enum ia_css_err diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_internal.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_internal.h index 0910021286a4..161122e1bcbc 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_internal.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_internal.h @@ -188,7 +188,7 @@ enum host2sp_commands { N_host2sp_cmd }; -/** Enumeration used to indicate the events that are produced by +/* Enumeration used to indicate the events that are produced by * the SP and consumed by the Host. * * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC: @@ -274,10 +274,10 @@ struct sh_css_ddr_address_map_compound { }; struct ia_css_isp_parameter_set_info { - struct sh_css_ddr_address_map mem_map;/**< pointers to Parameters in ISP format IMPT: + struct sh_css_ddr_address_map mem_map;/** pointers to Parameters in ISP format IMPT: This should be first member of this struct */ - uint32_t isp_parameters_id;/**< Unique ID to track which config was actually applied to a particular frame */ - ia_css_ptr output_frame_ptr;/**< Output frame to which this config has to be applied (optional) */ + uint32_t isp_parameters_id;/** Unique ID to track which config was actually applied to a particular frame */ + ia_css_ptr output_frame_ptr;/** Output frame to which this config has to be applied (optional) */ }; /* this struct contains all arguments that can be passed to @@ -398,9 +398,9 @@ struct sh_css_sp_input_formatter_set { /* SP configuration information */ struct sh_css_sp_config { uint8_t no_isp_sync; /* Signal host immediately after start */ - uint8_t enable_raw_pool_locking; /**< Enable Raw Buffer Locking for HALv3 Support */ + uint8_t enable_raw_pool_locking; /** Enable Raw Buffer Locking for HALv3 Support */ uint8_t lock_all; - /**< If raw buffer locking is enabled, this flag indicates whether raw + /** If raw buffer locking is enabled, this flag indicates whether raw frames are locked when their EOF event is successfully sent to the host (true) or when they are passed to the preview/video pipe (false). */ @@ -458,13 +458,13 @@ struct sh_css_sp_pipeline_io { /*struct sh_css_sp_pipeline_terminal output;*/ }; -/** This struct tracks how many streams are registered per CSI port. +/* This struct tracks how many streams are registered per CSI port. * This is used to track which streams have already been configured. * Only when all streams are configured, the CSI RX is started for that port. */ struct sh_css_sp_pipeline_io_status { - uint32_t active[N_INPUT_SYSTEM_CSI_PORT]; /**< registered streams */ - uint32_t running[N_INPUT_SYSTEM_CSI_PORT]; /**< configured streams */ + uint32_t active[N_INPUT_SYSTEM_CSI_PORT]; /** registered streams */ + uint32_t running[N_INPUT_SYSTEM_CSI_PORT]; /** configured streams */ }; #endif @@ -500,7 +500,7 @@ enum sh_css_port_type { #define SH_CSS_METADATA_OFFLINE_MODE 0x04 #define SH_CSS_METADATA_WAIT_INPUT 0x08 -/** @brief Free an array of metadata buffers. +/* @brief Free an array of metadata buffers. * * @param[in] num_bufs Number of metadata buffers to be freed. * @param[in] bufs Pointer of array of metadata buffers. @@ -764,7 +764,7 @@ struct sh_css_hmm_buffer { hrt_vaddress frame_data; uint32_t flashed; uint32_t exp_id; - uint32_t isp_parameters_id; /**< Unique ID to track which config was + uint32_t isp_parameters_id; /** Unique ID to track which config was actually applied to a particular frame */ #if CONFIG_ON_FRAME_ENQUEUE() struct sh_css_config_on_frame_enqueue config_on_frame_enqueue; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_legacy.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_legacy.h index e12789236bb9..4bcc35d219f8 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_legacy.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_legacy.h @@ -22,7 +22,7 @@ #include #include -/** The pipe id type, distinguishes the kind of pipes that +/* The pipe id type, distinguishes the kind of pipes that * can be run in parallel. */ enum ia_css_pipe_id { diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mipi.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mipi.c index 36aaa3019a15..883474e90c81 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mipi.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mipi.c @@ -321,7 +321,7 @@ calculate_mipi_buff_size( height = stream_cfg->input_config.input_res.height; format = stream_cfg->input_config.format; pack_raw_pixels = stream_cfg->pack_raw_pixels; - /** end of NOTE */ + /* end of NOTE */ /** #ifndef ISP2401 @@ -341,7 +341,7 @@ calculate_mipi_buff_size( * in the non-continuous use scenario. */ width_padded = width + (2 * ISP_VEC_NELEMS); - /** end of NOTE */ + /* end of NOTE */ IA_CSS_ENTER("padded_width=%d, height=%d, format=%d\n", width_padded, height, format); diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params.h index a7ffe6d8331b..270ec2b60a3e 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params.h @@ -144,8 +144,8 @@ struct ia_css_isp_parameters { struct sh_css_ddr_address_map_size pipe_ddr_ptrs_size[IA_CSS_PIPE_ID_NUM]; struct sh_css_ddr_address_map ddr_ptrs; struct sh_css_ddr_address_map_size ddr_ptrs_size; - struct ia_css_frame *output_frame; /**< Output frame the config is to be applied to (optional) */ - uint32_t isp_parameters_id; /**< Unique ID to track which config was actually applied to a particular frame */ + struct ia_css_frame *output_frame; /** Output frame the config is to be applied to (optional) */ + uint32_t isp_parameters_id; /** Unique ID to track which config was actually applied to a particular frame */ }; void diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_sp.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_sp.c index e6a345979ff1..6fc00fc402b1 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_sp.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_sp.c @@ -261,7 +261,7 @@ sh_css_sp_start_raw_copy(struct ia_css_frame *out_frame, assert(out_frame != NULL); { - /** + /* * Clear sh_css_sp_stage for easy debugging. * program_input_circuit must be saved as it is set outside * this function. @@ -335,7 +335,7 @@ sh_css_sp_start_isys_copy(struct ia_css_frame *out_frame, assert(out_frame != NULL); { - /** + /* * Clear sh_css_sp_stage for easy debugging. * program_input_circuit must be saved as it is set outside * this function. @@ -909,7 +909,7 @@ sh_css_sp_init_stage(struct ia_css_binary *binary, xinfo = binary->info; info = &xinfo->sp; { - /** + /* * Clear sh_css_sp_stage for easy debugging. * program_input_circuit must be saved as it is set outside * this function. @@ -980,7 +980,7 @@ sh_css_sp_init_stage(struct ia_css_binary *binary, sh_css_isp_stage.binary_name[SH_CSS_MAX_BINARY_NAME - 1] = 0; sh_css_isp_stage.mem_initializers = *isp_mem_if; - /** + /* * Even when a stage does not need uds and does not params, * ia_css_uds_sp_scale_params() seems to be called (needs * further investigation). This function can not deal with @@ -1429,7 +1429,7 @@ sh_css_init_host2sp_frame_data(void) } -/** +/* * @brief Update the offline frame information in host_sp_communication. * Refer to "sh_css_sp.h" for more details. */ @@ -1461,7 +1461,7 @@ sh_css_update_host2sp_offline_frame( } #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) -/** +/* * @brief Update the mipi frame information in host_sp_communication. * Refer to "sh_css_sp.h" for more details. */ @@ -1488,7 +1488,7 @@ sh_css_update_host2sp_mipi_frame( frame ? frame->data : 0); } -/** +/* * @brief Update the mipi metadata information in host_sp_communication. * Refer to "sh_css_sp.h" for more details. */ @@ -1735,7 +1735,7 @@ ia_css_isp_has_started(void) } -/** +/* * @brief Initialize the DMA software-mask in the debug mode. * Refer to "sh_css_sp.h" for more details. */ @@ -1761,7 +1761,7 @@ sh_css_sp_init_dma_sw_reg(int dma_id) return true; } -/** +/* * @brief Set the DMA software-mask in the debug mode. * Refer to "sh_css_sp.h" for more details. */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_struct.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_struct.h index e49e478ab354..0b8e3d872069 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_struct.h +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_struct.h @@ -61,7 +61,7 @@ struct sh_css { #endif hrt_vaddress sp_bin_addr; hrt_data page_table_base_index; - unsigned int size_mem_words; /** \deprecated{Use ia_css_mipi_buffer_config instead.}*/ + unsigned int size_mem_words; /* \deprecated{Use ia_css_mipi_buffer_config instead.}*/ enum ia_css_irq_type irq_type; unsigned int pipe_counter; -- GitLab From 1855e9884cb410cdc4d2b1244420d8056db1c76b Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 03:46:30 -0500 Subject: [PATCH 0322/2547] media: rc: fix kernel-doc parameter names There are several parameters there that are named wrong, as reported by those warnings: drivers/media/rc/ir-sharp-decoder.c:47: warning: No description found for parameter 'ev' drivers/media/rc/ir-sharp-decoder.c:47: warning: Excess function parameter 'duration' description in 'ir_sharp_decode' drivers/media/rc/ir-sanyo-decoder.c:56: warning: No description found for parameter 'ev' drivers/media/rc/ir-sanyo-decoder.c:56: warning: Excess function parameter 'duration' description in 'ir_sanyo_decode' drivers/media/rc/ir-xmp-decoder.c:43: warning: No description found for parameter 'ev' drivers/media/rc/ir-xmp-decoder.c:43: warning: Excess function parameter 'duration' description in 'ir_xmp_decode' drivers/media/rc/ir-jvc-decoder.c:47: warning: No description found for parameter 'ev' drivers/media/rc/ir-jvc-decoder.c:47: warning: Excess function parameter 'duration' description in 'ir_jvc_decode' drivers/media/rc/ir-lirc-codec.c:34: warning: No description found for parameter 'dev' drivers/media/rc/ir-lirc-codec.c:34: warning: No description found for parameter 'ev' drivers/media/rc/ir-lirc-codec.c:34: warning: Excess function parameter 'input_dev' description in 'ir_lirc_decode' drivers/media/rc/ir-lirc-codec.c:34: warning: Excess function parameter 'duration' description in 'ir_lirc_decode' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/ir-jvc-decoder.c | 2 +- drivers/media/rc/ir-lirc-codec.c | 4 ++-- drivers/media/rc/ir-sanyo-decoder.c | 2 +- drivers/media/rc/ir-sharp-decoder.c | 2 +- drivers/media/rc/ir-xmp-decoder.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/media/rc/ir-jvc-decoder.c b/drivers/media/rc/ir-jvc-decoder.c index e2bd68c42edf..22c8aee3df4f 100644 --- a/drivers/media/rc/ir-jvc-decoder.c +++ b/drivers/media/rc/ir-jvc-decoder.c @@ -39,7 +39,7 @@ enum jvc_state { /** * ir_jvc_decode() - Decode one JVC pulse or space * @dev: the struct rc_dev descriptor of the device - * @duration: the struct ir_raw_event descriptor of the pulse/space + * @ev: the struct ir_raw_event descriptor of the pulse/space * * This function returns -EINVAL if the pulse violates the state machine */ diff --git a/drivers/media/rc/ir-lirc-codec.c b/drivers/media/rc/ir-lirc-codec.c index 8f2f37412fc5..4fd4521693d9 100644 --- a/drivers/media/rc/ir-lirc-codec.c +++ b/drivers/media/rc/ir-lirc-codec.c @@ -25,8 +25,8 @@ /** * ir_lirc_decode() - Send raw IR data to lirc_dev to be relayed to the * lircd userspace daemon for decoding. - * @input_dev: the struct rc_dev descriptor of the device - * @duration: the struct ir_raw_event descriptor of the pulse/space + * @dev: the struct rc_dev descriptor of the device + * @ev: the struct ir_raw_event descriptor of the pulse/space * * This function returns -EINVAL if the lirc interfaces aren't wired up. */ diff --git a/drivers/media/rc/ir-sanyo-decoder.c b/drivers/media/rc/ir-sanyo-decoder.c index 758c60956850..d94e07b02f3b 100644 --- a/drivers/media/rc/ir-sanyo-decoder.c +++ b/drivers/media/rc/ir-sanyo-decoder.c @@ -48,7 +48,7 @@ enum sanyo_state { /** * ir_sanyo_decode() - Decode one SANYO pulse or space * @dev: the struct rc_dev descriptor of the device - * @duration: the struct ir_raw_event descriptor of the pulse/space + * @ev: the struct ir_raw_event descriptor of the pulse/space * * This function returns -EINVAL if the pulse violates the state machine */ diff --git a/drivers/media/rc/ir-sharp-decoder.c b/drivers/media/rc/ir-sharp-decoder.c index 129b558acc92..7140dd6160ee 100644 --- a/drivers/media/rc/ir-sharp-decoder.c +++ b/drivers/media/rc/ir-sharp-decoder.c @@ -39,7 +39,7 @@ enum sharp_state { /** * ir_sharp_decode() - Decode one Sharp pulse or space * @dev: the struct rc_dev descriptor of the device - * @duration: the struct ir_raw_event descriptor of the pulse/space + * @ev: the struct ir_raw_event descriptor of the pulse/space * * This function returns -EINVAL if the pulse violates the state machine */ diff --git a/drivers/media/rc/ir-xmp-decoder.c b/drivers/media/rc/ir-xmp-decoder.c index 6f464be1c8d7..712bc6d76e92 100644 --- a/drivers/media/rc/ir-xmp-decoder.c +++ b/drivers/media/rc/ir-xmp-decoder.c @@ -35,7 +35,7 @@ enum xmp_state { /** * ir_xmp_decode() - Decode one XMP pulse or space * @dev: the struct rc_dev descriptor of the device - * @duration: the struct ir_raw_event descriptor of the pulse/space + * @ev: the struct ir_raw_event descriptor of the pulse/space * * This function returns -EINVAL if the pulse violates the state machine */ -- GitLab From d28b2cf969b1e887450700191c22df8085574e9b Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 03:56:18 -0500 Subject: [PATCH 0323/2547] media: v4l2-core: Fix kernel-doc markups There are some troubles on kernel-doc markups, as warned: drivers/media/v4l2-core/v4l2-dv-timings.c:259: warning: No description found for parameter 't1' drivers/media/v4l2-core/v4l2-dv-timings.c:259: warning: No description found for parameter 't2' drivers/media/v4l2-core/v4l2-dv-timings.c:259: warning: No description found for parameter 'pclock_delta' drivers/media/v4l2-core/v4l2-dv-timings.c:259: warning: No description found for parameter 'match_reduced_fps' drivers/media/v4l2-core/tuner-core.c:242: warning: bad line: internal parameters, like LNA mode drivers/media/v4l2-core/tuner-core.c:765: warning: No description found for parameter 'mode' drivers/media/v4l2-core/videobuf2-memops.c:127: warning: cannot understand function prototype: 'const struct vm_operations_struct vb2_common_vm_ops = ' drivers/media/v4l2-core/v4l2-mem2mem.c:190: warning: No description found for parameter 'm2m_dev' drivers/media/v4l2-core/v4l2-mem2mem.c:291: warning: No description found for parameter 'm2m_ctx' drivers/media/v4l2-core/videobuf-core.c:233: warning: No description found for parameter 'q' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/tuner-core.c | 4 +++- drivers/media/v4l2-core/v4l2-dv-timings.c | 10 +++++----- drivers/media/v4l2-core/v4l2-mem2mem.c | 2 ++ drivers/media/v4l2-core/videobuf-core.c | 2 +- drivers/media/v4l2-core/videobuf2-memops.c | 2 +- 5 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/media/v4l2-core/tuner-core.c b/drivers/media/v4l2-core/tuner-core.c index 8db45dfc271b..82852f23a3b6 100644 --- a/drivers/media/v4l2-core/tuner-core.c +++ b/drivers/media/v4l2-core/tuner-core.c @@ -239,7 +239,7 @@ static const struct analog_demod_ops tuner_analog_ops = { * @type: type of the tuner (e. g. tuner number) * @new_mode_mask: Indicates if tuner supports TV and/or Radio * @new_config: an optional parameter used by a few tuners to adjust - internal parameters, like LNA mode + * internal parameters, like LNA mode * @tuner_callback: an optional function to be called when switching * to analog mode * @@ -750,6 +750,7 @@ static int tuner_remove(struct i2c_client *client) /** * check_mode - Verify if tuner supports the requested mode * @t: a pointer to the module's internal struct_tuner + * @mode: mode of the tuner, as defined by &enum v4l2_tuner_type. * * This function checks if the tuner is capable of tuning analog TV, * digital TV or radio, depending on what the caller wants. If the @@ -757,6 +758,7 @@ static int tuner_remove(struct i2c_client *client) * returns 0. * This function is needed for boards that have a separate tuner for * radio (like devices with tea5767). + * * NOTE: mt20xx uses V4L2_TUNER_DIGITAL_TV and calls set_tv_freq to * select a TV frequency. So, t_mode = T_ANALOG_TV could actually * be used to represent a Digital TV too. diff --git a/drivers/media/v4l2-core/v4l2-dv-timings.c b/drivers/media/v4l2-core/v4l2-dv-timings.c index 5c8c49d240d1..930f9c53a64e 100644 --- a/drivers/media/v4l2-core/v4l2-dv-timings.c +++ b/drivers/media/v4l2-core/v4l2-dv-timings.c @@ -245,11 +245,11 @@ EXPORT_SYMBOL_GPL(v4l2_find_dv_timings_cea861_vic); /** * v4l2_match_dv_timings - check if two timings match - * @t1 - compare this v4l2_dv_timings struct... - * @t2 - with this struct. - * @pclock_delta - the allowed pixelclock deviation. - * @match_reduced_fps - if true, then fail if V4L2_DV_FL_REDUCED_FPS does not - * match. + * @t1: compare this v4l2_dv_timings struct... + * @t2: with this struct. + * @pclock_delta: the allowed pixelclock deviation. + * @match_reduced_fps: if true, then fail if V4L2_DV_FL_REDUCED_FPS does not + * match. * * Compare t1 with t2 with a given margin of error for the pixelclock. */ diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c index f62e68aa04c4..bc580fbe18fa 100644 --- a/drivers/media/v4l2-core/v4l2-mem2mem.c +++ b/drivers/media/v4l2-core/v4l2-mem2mem.c @@ -183,6 +183,7 @@ EXPORT_SYMBOL(v4l2_m2m_get_curr_priv); /** * v4l2_m2m_try_run() - select next job to perform and run it if possible + * @m2m_dev: per-device context * * Get next transaction (if present) from the waiting jobs list and run it. */ @@ -281,6 +282,7 @@ EXPORT_SYMBOL_GPL(v4l2_m2m_try_schedule); /** * v4l2_m2m_cancel_job() - cancel pending jobs for the context + * @m2m_ctx: m2m context with jobs to be canceled * * In case of streamoff or release called on any context, * 1] If the context is currently running, then abort job will be called diff --git a/drivers/media/v4l2-core/videobuf-core.c b/drivers/media/v4l2-core/videobuf-core.c index 1dbf6f7785bb..e87fb13b22dc 100644 --- a/drivers/media/v4l2-core/videobuf-core.c +++ b/drivers/media/v4l2-core/videobuf-core.c @@ -222,7 +222,7 @@ int videobuf_queue_is_busy(struct videobuf_queue *q) } EXPORT_SYMBOL_GPL(videobuf_queue_is_busy); -/** +/* * __videobuf_free() - free all the buffers and their control structures * * This function can only be called if streaming/reading is off, i.e. no buffers diff --git a/drivers/media/v4l2-core/videobuf2-memops.c b/drivers/media/v4l2-core/videobuf2-memops.c index 4bb8424114ce..89e51989332b 100644 --- a/drivers/media/v4l2-core/videobuf2-memops.c +++ b/drivers/media/v4l2-core/videobuf2-memops.c @@ -120,7 +120,7 @@ static void vb2_common_vm_close(struct vm_area_struct *vma) h->put(h->arg); } -/** +/* * vb2_common_vm_ops - common vm_ops used for tracking refcount of mmaped * video buffers */ -- GitLab From 389a455d61cbc796994332e6a87616c4d34200e2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 04:20:45 -0500 Subject: [PATCH 0324/2547] media: davinci: fix kernel-doc warnings There are several of kernel-doc warnings: drivers/media/platform/davinci/vpif_display.c:114: warning: No description found for parameter 'sizes' drivers/media/platform/davinci/vpif_display.c:165: warning: No description found for parameter 'vq' drivers/media/platform/davinci/vpif_display.c:165: warning: Excess function parameter 'vb' description in 'vpif_start_streaming' drivers/media/platform/davinci/vpif_display.c:780: warning: No description found for parameter 'vpif_cfg' drivers/media/platform/davinci/vpif_display.c:780: warning: No description found for parameter 'chan_cfg' drivers/media/platform/davinci/vpif_display.c:780: warning: No description found for parameter 'index' drivers/media/platform/davinci/vpif_display.c:813: warning: No description found for parameter 'vpif_cfg' drivers/media/platform/davinci/vpif_display.c:813: warning: No description found for parameter 'ch' drivers/media/platform/davinci/vpif_display.c:813: warning: No description found for parameter 'index' drivers/media/platform/davinci/vpif_capture.c:121: warning: No description found for parameter 'sizes' drivers/media/platform/davinci/vpif_capture.c:174: warning: No description found for parameter 'vq' drivers/media/platform/davinci/vpif_capture.c:174: warning: Excess function parameter 'vb' description in 'vpif_start_streaming' drivers/media/platform/davinci/vpif_capture.c:636: warning: No description found for parameter 'iface' drivers/media/platform/davinci/vpif_capture.c:647: warning: No description found for parameter 'ch' drivers/media/platform/davinci/vpif_capture.c:647: warning: No description found for parameter 'muxmode' drivers/media/platform/davinci/vpif_capture.c:676: warning: No description found for parameter 'vpif_cfg' drivers/media/platform/davinci/vpif_capture.c:676: warning: No description found for parameter 'chan_cfg' drivers/media/platform/davinci/vpif_capture.c:676: warning: No description found for parameter 'input_index' drivers/media/platform/davinci/vpif_capture.c:712: warning: No description found for parameter 'vpif_cfg' drivers/media/platform/davinci/vpif_capture.c:712: warning: No description found for parameter 'ch' drivers/media/platform/davinci/vpif_capture.c:712: warning: No description found for parameter 'index' drivers/media/platform/davinci/vpif_capture.c:798: warning: No description found for parameter 'std' drivers/media/platform/davinci/vpif_capture.c:798: warning: Excess function parameter 'std_id' description in 'vpif_g_std' drivers/media/platform/davinci/vpif_capture.c:940: warning: No description found for parameter 'fmt' drivers/media/platform/davinci/vpif_capture.c:940: warning: Excess function parameter 'index' description in 'vpif_enum_fmt_vid_cap' drivers/media/platform/davinci/vpif_capture.c:1750: warning: No description found for parameter 'dev' Fix them. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/davinci/vpif_capture.c | 27 ++++++++++--------- drivers/media/platform/davinci/vpif_display.c | 16 +++++------ 2 files changed, 22 insertions(+), 21 deletions(-) diff --git a/drivers/media/platform/davinci/vpif_capture.c b/drivers/media/platform/davinci/vpif_capture.c index a89367ab1e06..fca4dc829f73 100644 --- a/drivers/media/platform/davinci/vpif_capture.c +++ b/drivers/media/platform/davinci/vpif_capture.c @@ -109,7 +109,7 @@ static int vpif_buffer_prepare(struct vb2_buffer *vb) * @vq: vb2_queue ptr * @nbuffers: ptr to number of buffers requested by application * @nplanes:: contains number of distinct video planes needed to hold a frame - * @sizes[]: contains the size (in bytes) of each plane. + * @sizes: contains the size (in bytes) of each plane. * @alloc_devs: ptr to allocation context * * This callback function is called when reqbuf() is called to adjust @@ -167,7 +167,7 @@ static void vpif_buffer_queue(struct vb2_buffer *vb) /** * vpif_start_streaming : Starts the DMA engine for streaming - * @vb: ptr to vb2_buffer + * @vq: ptr to vb2_buffer * @count: number of buffers */ static int vpif_start_streaming(struct vb2_queue *vq, unsigned int count) @@ -629,7 +629,7 @@ static void vpif_calculate_offsets(struct channel_obj *ch) /** * vpif_get_default_field() - Get default field type based on interface - * @vpif_params - ptr to vpif params + * @iface: ptr to vpif interface */ static inline enum v4l2_field vpif_get_default_field( struct vpif_interface *iface) @@ -640,8 +640,8 @@ static inline enum v4l2_field vpif_get_default_field( /** * vpif_config_addr() - function to configure buffer address in vpif - * @ch - channel ptr - * @muxmode - channel mux mode + * @ch: channel ptr + * @muxmode: channel mux mode */ static void vpif_config_addr(struct channel_obj *ch, int muxmode) { @@ -661,9 +661,9 @@ static void vpif_config_addr(struct channel_obj *ch, int muxmode) /** * vpif_input_to_subdev() - Maps input to sub device - * @vpif_cfg - global config ptr - * @chan_cfg - channel config ptr - * @input_index - Given input index from application + * @vpif_cfg: global config ptr + * @chan_cfg: channel config ptr + * @input_index: Given input index from application * * lookup the sub device information for a given input index. * we report all the inputs to application. inputs table also @@ -699,9 +699,9 @@ static int vpif_input_to_subdev( /** * vpif_set_input() - Select an input - * @vpif_cfg - global config ptr - * @ch - channel - * @_index - Given input index from application + * @vpif_cfg: global config ptr + * @ch: channel + * @index: Given input index from application * * Select the given input. */ @@ -792,7 +792,7 @@ static int vpif_querystd(struct file *file, void *priv, v4l2_std_id *std_id) * vpif_g_std() - get STD handler * @file: file ptr * @priv: file handle - * @std_id: ptr to std id + * @std: ptr to std id */ static int vpif_g_std(struct file *file, void *priv, v4l2_std_id *std) { @@ -933,7 +933,7 @@ static int vpif_s_input(struct file *file, void *priv, unsigned int index) * vpif_enum_fmt_vid_cap() - ENUM_FMT handler * @file: file ptr * @priv: file handle - * @index: input index + * @fmt: ptr to V4L2 format descriptor */ static int vpif_enum_fmt_vid_cap(struct file *file, void *priv, struct v4l2_fmtdesc *fmt) @@ -1745,6 +1745,7 @@ static int vpif_remove(struct platform_device *device) #ifdef CONFIG_PM_SLEEP /** * vpif_suspend: vpif device suspend + * @dev: pointer to &struct device */ static int vpif_suspend(struct device *dev) { diff --git a/drivers/media/platform/davinci/vpif_display.c b/drivers/media/platform/davinci/vpif_display.c index ff2f75a328c9..7be636237acf 100644 --- a/drivers/media/platform/davinci/vpif_display.c +++ b/drivers/media/platform/davinci/vpif_display.c @@ -102,7 +102,7 @@ static int vpif_buffer_prepare(struct vb2_buffer *vb) * @vq: vb2_queue ptr * @nbuffers: ptr to number of buffers requested by application * @nplanes:: contains number of distinct video planes needed to hold a frame - * @sizes[]: contains the size (in bytes) of each plane. + * @sizes: contains the size (in bytes) of each plane. * @alloc_devs: ptr to allocation context * * This callback function is called when reqbuf() is called to adjust @@ -158,7 +158,7 @@ static void vpif_buffer_queue(struct vb2_buffer *vb) /** * vpif_start_streaming : Starts the DMA engine for streaming - * @vb: ptr to vb2_buffer + * @vq: ptr to vb2_buffer * @count: number of buffers */ static int vpif_start_streaming(struct vb2_queue *vq, unsigned int count) @@ -766,9 +766,9 @@ static int vpif_enum_output(struct file *file, void *fh, /** * vpif_output_to_subdev() - Maps output to sub device - * @vpif_cfg - global config ptr - * @chan_cfg - channel config ptr - * @index - Given output index from application + * @vpif_cfg: global config ptr + * @chan_cfg: channel config ptr + * @index: Given output index from application * * lookup the sub device information for a given output index. * we report all the output to application. output table also @@ -802,9 +802,9 @@ vpif_output_to_subdev(struct vpif_display_config *vpif_cfg, /** * vpif_set_output() - Select an output - * @vpif_cfg - global config ptr - * @ch - channel - * @index - Given output index from application + * @vpif_cfg: global config ptr + * @ch: channel + * @index: Given output index from application * * Select the given output. */ -- GitLab From 440568f8508528278efb9b944e8856484bbc7edd Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 04:22:37 -0500 Subject: [PATCH 0325/2547] media: venc: don't use kernel-doc for undescribed enums There are no descriptions for some enums, with produces lots of warnings: drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_LUMA' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_LUMA2' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_LUMA3' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_CHROMA' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_CHROMA2' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_CHROMA3' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_MV_INFO' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_BS_HEADER' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_PROB_BUF' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_RC_INFO' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_RC_CODE' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_RC_CODE2' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_RC_CODE3' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c:55: warning: Enum value 'VENC_VP8_VPU_WORK_BUF_MAX' not described in enum 'venc_vp8_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:51: warning: Enum value 'VENC_H264_VPU_WORK_BUF_RC_INFO' not described in enum 'venc_h264_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:51: warning: Enum value 'VENC_H264_VPU_WORK_BUF_RC_CODE' not described in enum 'venc_h264_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:51: warning: Enum value 'VENC_H264_VPU_WORK_BUF_REC_LUMA' not described in enum 'venc_h264_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:51: warning: Enum value 'VENC_H264_VPU_WORK_BUF_REC_CHROMA' not described in enum 'venc_h264_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:51: warning: Enum value 'VENC_H264_VPU_WORK_BUF_REF_LUMA' not described in enum 'venc_h264_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:51: warning: Enum value 'VENC_H264_VPU_WORK_BUF_REF_CHROMA' not described in enum 'venc_h264_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:51: warning: Enum value 'VENC_H264_VPU_WORK_BUF_MV_INFO_1' not described in enum 'venc_h264_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:51: warning: Enum value 'VENC_H264_VPU_WORK_BUF_MV_INFO_2' not described in enum 'venc_h264_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:51: warning: Enum value 'VENC_H264_VPU_WORK_BUF_SKIP_FRAME' not described in enum 'venc_h264_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:51: warning: Enum value 'VENC_H264_VPU_WORK_BUF_MAX' not described in enum 'venc_h264_vpu_work_buf' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:60: warning: Enum value 'H264_BS_MODE_SPS' not described in enum 'venc_h264_bs_mode' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:60: warning: Enum value 'H264_BS_MODE_PPS' not described in enum 'venc_h264_bs_mode' drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c:60: warning: Enum value 'H264_BS_MODE_FRAME' not described in enum 'venc_h264_bs_mode' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c | 4 ++-- drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c b/drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c index 4eb3be37ba14..6cf31b366aad 100644 --- a/drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c +++ b/drivers/media/platform/mtk-vcodec/venc/venc_h264_if.c @@ -34,7 +34,7 @@ static const char h264_filler_marker[] = {0x0, 0x0, 0x0, 0x1, 0xc}; #define H264_FILLER_MARKER_SIZE ARRAY_SIZE(h264_filler_marker) #define VENC_PIC_BITSTREAM_BYTE_CNT 0x0098 -/** +/* * enum venc_h264_vpu_work_buf - h264 encoder buffer index */ enum venc_h264_vpu_work_buf { @@ -50,7 +50,7 @@ enum venc_h264_vpu_work_buf { VENC_H264_VPU_WORK_BUF_MAX, }; -/** +/* * enum venc_h264_bs_mode - for bs_mode argument in h264_enc_vpu_encode */ enum venc_h264_bs_mode { diff --git a/drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c b/drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c index acb639c4abd2..957420dd60de 100644 --- a/drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c +++ b/drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c @@ -34,7 +34,7 @@ /* This ac_tag is vp8 frame tag. */ #define MAX_AC_TAG_SIZE 10 -/** +/* * enum venc_vp8_vpu_work_buf - vp8 encoder buffer index */ enum venc_vp8_vpu_work_buf { -- GitLab From 3b060ba0eb9a0d435b562a6f7b3cc2844a2df941 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 04:32:51 -0500 Subject: [PATCH 0326/2547] media: exynos4-is: fix kernel-doc warnings Fix those kernel-doc warnings: drivers/media/platform/exynos4-is/mipi-csis.c:229: warning: No description found for parameter 'clk_frequency' drivers/media/platform/exynos4-is/mipi-csis.c:229: warning: Excess struct member 'clock_frequency' description in 'csis_state' drivers/media/platform/exynos4-is/media-dev.c:69: warning: No description found for parameter 'p' drivers/media/platform/exynos4-is/media-dev.c:160: warning: No description found for parameter 'p' drivers/media/platform/exynos4-is/media-dev.c:160: warning: No description found for parameter 'on' drivers/media/platform/exynos4-is/media-dev.c:160: warning: Excess function parameter 'fimc' description in 'fimc_pipeline_s_power' drivers/media/platform/exynos4-is/media-dev.c:160: warning: Excess function parameter 'state' description in 'fimc_pipeline_s_power' drivers/media/platform/exynos4-is/media-dev.c:229: warning: No description found for parameter 'ep' drivers/media/platform/exynos4-is/media-dev.c:260: warning: No description found for parameter 'ep' drivers/media/platform/exynos4-is/media-dev.c:260: warning: Excess function parameter 'fimc' description in '__fimc_pipeline_close' drivers/media/platform/exynos4-is/media-dev.c:288: warning: No description found for parameter 'ep' drivers/media/platform/exynos4-is/media-dev.c:288: warning: Excess function parameter 'pipeline' description in '__fimc_pipeline_s_stream' drivers/media/platform/exynos4-is/media-dev.c:916: warning: No description found for parameter 'fmd' drivers/media/platform/exynos4-is/fimc-capture.c:155: warning: No description found for parameter 'ctx' drivers/media/platform/exynos4-is/fimc-capture.c:868: warning: No description found for parameter 'num_planes' drivers/media/platform/exynos4-is/fimc-capture.c:1108: warning: No description found for parameter 'fimc' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/exynos4-is/fimc-capture.c | 3 +++ drivers/media/platform/exynos4-is/media-dev.c | 11 +++++++---- drivers/media/platform/exynos4-is/mipi-csis.c | 2 +- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/exynos4-is/fimc-capture.c b/drivers/media/platform/exynos4-is/fimc-capture.c index 948fe01f6c96..ed9302caa004 100644 --- a/drivers/media/platform/exynos4-is/fimc-capture.c +++ b/drivers/media/platform/exynos4-is/fimc-capture.c @@ -146,6 +146,7 @@ static int fimc_stop_capture(struct fimc_dev *fimc, bool suspend) /** * fimc_capture_config_update - apply the camera interface configuration + * @ctx: FIMC capture context * * To be called from within the interrupt handler with fimc.slock * spinlock held. It updates the camera pixel crop, rotation and @@ -858,6 +859,7 @@ static int fimc_pipeline_try_format(struct fimc_ctx *ctx, * fimc_get_sensor_frame_desc - query the sensor for media bus frame parameters * @sensor: pointer to the sensor subdev * @plane_fmt: provides plane sizes corresponding to the frame layout entries + * @num_planes: number of planes * @try: true to set the frame parameters, false to query only * * This function is used by this driver only for compressed/blob data formats. @@ -1101,6 +1103,7 @@ static int fimc_cap_g_input(struct file *file, void *priv, unsigned int *i) /** * fimc_pipeline_validate - check for formats inconsistencies * between source and sink pad of each link + * @fimc: the FIMC device this context applies to * * Return 0 if all formats match or -EPIPE otherwise. */ diff --git a/drivers/media/platform/exynos4-is/media-dev.c b/drivers/media/platform/exynos4-is/media-dev.c index c15596b56dc9..0ef583cfc424 100644 --- a/drivers/media/platform/exynos4-is/media-dev.c +++ b/drivers/media/platform/exynos4-is/media-dev.c @@ -60,6 +60,7 @@ static void __setup_sensor_notification(struct fimc_md *fmd, /** * fimc_pipeline_prepare - update pipeline information with subdevice pointers + * @p: fimc pipeline * @me: media entity terminating the pipeline * * Caller holds the graph mutex. @@ -151,8 +152,8 @@ static int __subdev_set_power(struct v4l2_subdev *sd, int on) /** * fimc_pipeline_s_power - change power state of all pipeline subdevs - * @fimc: fimc device terminating the pipeline - * @state: true to power on, false to power off + * @p: fimc device terminating the pipeline + * @on: true to power on, false to power off * * Needs to be called with the graph mutex held. */ @@ -219,6 +220,7 @@ static int __fimc_pipeline_enable(struct exynos_media_pipeline *ep, /** * __fimc_pipeline_open - update the pipeline information, enable power * of all pipeline subdevs and the sensor clock + * @ep: fimc device terminating the pipeline * @me: media entity to start graph walk with * @prepare: true to walk the current pipeline and acquire all subdevs * @@ -252,7 +254,7 @@ static int __fimc_pipeline_open(struct exynos_media_pipeline *ep, /** * __fimc_pipeline_close - disable the sensor clock and pipeline power - * @fimc: fimc device terminating the pipeline + * @ep: fimc device terminating the pipeline * * Disable power of all subdevs and turn the external sensor clock off. */ @@ -281,7 +283,7 @@ static int __fimc_pipeline_close(struct exynos_media_pipeline *ep) /** * __fimc_pipeline_s_stream - call s_stream() on pipeline subdevs - * @pipeline: video pipeline structure + * @ep: video pipeline structure * @on: passed as the s_stream() callback argument */ static int __fimc_pipeline_s_stream(struct exynos_media_pipeline *ep, bool on) @@ -902,6 +904,7 @@ static int __fimc_md_create_fimc_is_links(struct fimc_md *fmd) /** * fimc_md_create_links - create default links between registered entities + * @fmd: fimc media device * * Parallel interface sensor entities are connected directly to FIMC capture * entities. The sensors using MIPI CSIS bus are connected through immutable diff --git a/drivers/media/platform/exynos4-is/mipi-csis.c b/drivers/media/platform/exynos4-is/mipi-csis.c index 560aadabcb11..cba46a656338 100644 --- a/drivers/media/platform/exynos4-is/mipi-csis.c +++ b/drivers/media/platform/exynos4-is/mipi-csis.c @@ -189,7 +189,7 @@ struct csis_drvdata { * @irq: requested s5p-mipi-csis irq number * @interrupt_mask: interrupt mask of the all used interrupts * @flags: the state variable for power and streaming control - * @clock_frequency: device bus clock frequency + * @clk_frequency: device bus clock frequency * @hs_settle: HS-RX settle time * @num_lanes: number of MIPI-CSI data lanes used * @max_num_lanes: maximum number of MIPI-CSI data lanes supported -- GitLab From 897aa67a47ac1379a479f42c4c84b828fe5f64a1 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 04:08:14 -0500 Subject: [PATCH 0327/2547] media: m5mols: fix some kernel-doc markups Fix those warnings: drivers/media/i2c/m5mols/m5mols_capture.c:42: warning: No description found for parameter 'sd' drivers/media/i2c/m5mols/m5mols_capture.c:42: warning: No description found for parameter 'addr_num' drivers/media/i2c/m5mols/m5mols_capture.c:42: warning: No description found for parameter 'addr_den' drivers/media/i2c/m5mols/m5mols_capture.c:42: warning: No description found for parameter 'val' drivers/media/i2c/m5mols/m5mols_capture.c:60: warning: No description found for parameter 'info' drivers/media/i2c/m5mols/m5mols_controls.c:134: warning: No description found for parameter 'info' drivers/media/i2c/m5mols/m5mols_core.c:124: warning: No description found for parameter 'data' drivers/media/i2c/m5mols/m5mols_core.c:124: warning: No description found for parameter 'length' drivers/media/i2c/m5mols/m5mols_core.c:124: warning: Excess function parameter 'size' description in 'm5mols_swap_byte' drivers/media/i2c/m5mols/m5mols_core.c:142: warning: No description found for parameter 'sd' drivers/media/i2c/m5mols/m5mols_core.c:241: warning: No description found for parameter 'sd' drivers/media/i2c/m5mols/m5mols_core.c:299: warning: No description found for parameter 'sd' drivers/media/i2c/m5mols/m5mols_core.c:324: warning: No description found for parameter 'sd' drivers/media/i2c/m5mols/m5mols_core.c:324: warning: No description found for parameter 'reg' drivers/media/i2c/m5mols/m5mols_core.c:357: warning: No description found for parameter 'sd' drivers/media/i2c/m5mols/m5mols_core.c:357: warning: No description found for parameter 'mode' drivers/media/i2c/m5mols/m5mols_core.c:374: warning: No description found for parameter 'info' drivers/media/i2c/m5mols/m5mols_core.c:429: warning: No description found for parameter 'sd' drivers/media/i2c/m5mols/m5mols_core.c:503: warning: No description found for parameter 'sd' drivers/media/i2c/m5mols/m5mols_core.c:671: warning: No description found for parameter 'info' drivers/media/i2c/m5mols/m5mols_core.c:694: warning: No description found for parameter 'info' drivers/media/i2c/m5mols/m5mols_core.c:798: warning: No description found for parameter 'sd' drivers/media/i2c/m5mols/m5mols_core.c:853: warning: No description found for parameter 'sd' drivers/media/i2c/m5mols/m5mols_core.c:853: warning: No description found for parameter 'on' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/m5mols/m5mols_capture.c | 5 +++++ drivers/media/i2c/m5mols/m5mols_controls.c | 1 + drivers/media/i2c/m5mols/m5mols_core.c | 20 ++++++++++++++++++-- 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/m5mols/m5mols_capture.c b/drivers/media/i2c/m5mols/m5mols_capture.c index a0cd6dc32eb0..0fb457f57995 100644 --- a/drivers/media/i2c/m5mols/m5mols_capture.c +++ b/drivers/media/i2c/m5mols/m5mols_capture.c @@ -33,6 +33,10 @@ /** * m5mols_read_rational - I2C read of a rational number + * @sd: sub-device, as pointed by struct v4l2_subdev + * @addr_num: numerator register + * @addr_den: denominator register + * @val: place to store the division result * * Read numerator and denominator from registers @addr_num and @addr_den * respectively and return the division result in @val. @@ -53,6 +57,7 @@ static int m5mols_read_rational(struct v4l2_subdev *sd, u32 addr_num, /** * m5mols_capture_info - Gather captured image information + * @info: M-5MOLS driver data structure * * For now it gathers only EXIF information and file size. */ diff --git a/drivers/media/i2c/m5mols/m5mols_controls.c b/drivers/media/i2c/m5mols/m5mols_controls.c index c2218c0a9e6f..82eab7c2bc8c 100644 --- a/drivers/media/i2c/m5mols/m5mols_controls.c +++ b/drivers/media/i2c/m5mols/m5mols_controls.c @@ -126,6 +126,7 @@ static struct m5mols_scenemode m5mols_default_scenemode[] = { /** * m5mols_do_scenemode() - Change current scenemode + * @info: M-5MOLS driver data structure * @mode: Desired mode of the scenemode * * WARNING: The execution order is important. Do not change the order. diff --git a/drivers/media/i2c/m5mols/m5mols_core.c b/drivers/media/i2c/m5mols/m5mols_core.c index 463534d44756..12e79f9e32d5 100644 --- a/drivers/media/i2c/m5mols/m5mols_core.c +++ b/drivers/media/i2c/m5mols/m5mols_core.c @@ -114,7 +114,8 @@ static const struct m5mols_resolution m5mols_reg_res[] = { /** * m5mols_swap_byte - an byte array to integer conversion function - * @size: size in bytes of I2C packet defined in the M-5MOLS datasheet + * @data: byte array + * @length: size in bytes of I2C packet defined in the M-5MOLS datasheet * * Convert I2C data byte array with performing any required byte * reordering to assure proper values for each data type, regardless @@ -132,8 +133,9 @@ static u32 m5mols_swap_byte(u8 *data, u8 length) /** * m5mols_read - I2C read function - * @reg: combination of size, category and command for the I2C packet + * @sd: sub-device, as pointed by struct v4l2_subdev * @size: desired size of I2C packet + * @reg: combination of size, category and command for the I2C packet * @val: read value * * Returns 0 on success, or else negative errno. @@ -232,6 +234,7 @@ int m5mols_read_u32(struct v4l2_subdev *sd, u32 reg, u32 *val) /** * m5mols_write - I2C command write function + * @sd: sub-device, as pointed by struct v4l2_subdev * @reg: combination of size, category and command for the I2C packet * @val: value to write * @@ -284,6 +287,7 @@ int m5mols_write(struct v4l2_subdev *sd, u32 reg, u32 val) /** * m5mols_busy_wait - Busy waiting with I2C register polling + * @sd: sub-device, as pointed by struct v4l2_subdev * @reg: the I2C_REG() address of an 8-bit status register to check * @value: expected status register value * @mask: bit mask for the read status register value @@ -316,6 +320,8 @@ int m5mols_busy_wait(struct v4l2_subdev *sd, u32 reg, u32 value, u32 mask, /** * m5mols_enable_interrupt - Clear interrupt pending bits and unmask interrupts + * @sd: sub-device, as pointed by struct v4l2_subdev + * @reg: combination of size, category and command for the I2C packet * * Before writing desired interrupt value the INT_FACTOR register should * be read to clear pending interrupts. @@ -349,6 +355,8 @@ int m5mols_wait_interrupt(struct v4l2_subdev *sd, u8 irq_mask, u32 timeout) /** * m5mols_reg_mode - Write the mode and check busy status + * @sd: sub-device, as pointed by struct v4l2_subdev + * @mode: the required operation mode * * It always accompanies a little delay changing the M-5MOLS mode, so it is * needed checking current busy status to guarantee right mode. @@ -364,6 +372,7 @@ static int m5mols_reg_mode(struct v4l2_subdev *sd, u8 mode) /** * m5mols_set_mode - set the M-5MOLS controller mode + * @info: M-5MOLS driver data structure * @mode: the required operation mode * * The commands of M-5MOLS are grouped into specific modes. Each functionality @@ -421,6 +430,7 @@ int m5mols_set_mode(struct m5mols_info *info, u8 mode) /** * m5mols_get_version - retrieve full revisions information of M-5MOLS + * @sd: sub-device, as pointed by struct v4l2_subdev * * The version information includes revisions of hardware and firmware, * AutoFocus alghorithm version and the version string. @@ -489,6 +499,7 @@ static enum m5mols_restype __find_restype(u32 code) /** * __find_resolution - Lookup preset and type of M-5MOLS's resolution + * @sd: sub-device, as pointed by struct v4l2_subdev * @mf: pixel format to find/negotiate the resolution preset for * @type: M-5MOLS resolution type * @resolution: M-5MOLS resolution preset register value @@ -662,6 +673,7 @@ static const struct v4l2_subdev_pad_ops m5mols_pad_ops = { /** * m5mols_restore_controls - Apply current control values to the registers + * @info: M-5MOLS driver data structure * * m5mols_do_scenemode() handles all parameters for which there is yet no * individual control. It should be replaced at some point by setting each @@ -686,6 +698,7 @@ int m5mols_restore_controls(struct m5mols_info *info) /** * m5mols_start_monitor - Start the monitor mode + * @info: M-5MOLS driver data structure * * Before applying the controls setup the resolution and frame rate * in PARAMETER mode, and then switch over to MONITOR mode. @@ -789,6 +802,7 @@ int __attribute__ ((weak)) m5mols_update_fw(struct v4l2_subdev *sd, /** * m5mols_fw_start - M-5MOLS internal ARM controller initialization + * @sd: sub-device, as pointed by struct v4l2_subdev * * Execute the M-5MOLS internal ARM controller initialization sequence. * This function should be called after the supply voltage has been @@ -844,6 +858,8 @@ static int m5mols_auto_focus_stop(struct m5mols_info *info) /** * m5mols_s_power - Main sensor power control function + * @sd: sub-device, as pointed by struct v4l2_subdev + * @on: if true, powers on the device; powers off otherwise. * * To prevent breaking the lens when the sensor is powered off the Soft-Landing * algorithm is called where available. The Soft-Landing algorithm availability -- GitLab From 9ec2b40259f91627bf852f7708a90357e0db1870 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 05:54:29 -0500 Subject: [PATCH 0328/2547] media: sta2x11: document missing function parameters As warned: drivers/media/pci/sta2x11/sta2x11_vip.c:414: warning: No description found for parameter 'priv' drivers/media/pci/sta2x11/sta2x11_vip.c:442: warning: No description found for parameter 'priv' drivers/media/pci/sta2x11/sta2x11_vip.c:476: warning: No description found for parameter 'priv' drivers/media/pci/sta2x11/sta2x11_vip.c:493: warning: No description found for parameter 'priv' drivers/media/pci/sta2x11/sta2x11_vip.c:524: warning: No description found for parameter 'priv' drivers/media/pci/sta2x11/sta2x11_vip.c:548: warning: No description found for parameter 'priv' drivers/media/pci/sta2x11/sta2x11_vip.c:566: warning: No description found for parameter 'file' drivers/media/pci/sta2x11/sta2x11_vip.c:566: warning: No description found for parameter 'priv' drivers/media/pci/sta2x11/sta2x11_vip.c:594: warning: No description found for parameter 'priv' drivers/media/pci/sta2x11/sta2x11_vip.c:651: warning: No description found for parameter 'priv' drivers/media/pci/sta2x11/sta2x11_vip.c:717: warning: No description found for parameter 'priv' Most of the above are for the unused priv argument. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/pci/sta2x11/sta2x11_vip.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/media/pci/sta2x11/sta2x11_vip.c b/drivers/media/pci/sta2x11/sta2x11_vip.c index eb5a9eae7c8e..dd199bfc1d45 100644 --- a/drivers/media/pci/sta2x11/sta2x11_vip.c +++ b/drivers/media/pci/sta2x11/sta2x11_vip.c @@ -404,6 +404,7 @@ static const struct v4l2_file_operations vip_fops = { * vidioc_querycap - return capabilities of device * @file: descriptor of device * @cap: contains return values + * @priv: unused * * the capabilities of the device are returned * @@ -429,6 +430,7 @@ static int vidioc_querycap(struct file *file, void *priv, * vidioc_s_std - set video standard * @file: descriptor of device * @std: contains standard to be set + * @priv: unused * * the video standard is set * @@ -466,6 +468,7 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id std) /** * vidioc_g_std - get video standard * @file: descriptor of device + * @priv: unused * @std: contains return values * * the current video standard is returned @@ -483,6 +486,7 @@ static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *std) /** * vidioc_querystd - get possible video standards * @file: descriptor of device + * @priv: unused * @std: contains return values * * all possible video standards are returned @@ -512,6 +516,7 @@ static int vidioc_enum_input(struct file *file, void *priv, /** * vidioc_s_input - set input line * @file: descriptor of device + * @priv: unused * @i: new input line number * * the current active input line is set @@ -538,6 +543,7 @@ static int vidioc_s_input(struct file *file, void *priv, unsigned int i) /** * vidioc_g_input - return input line * @file: descriptor of device + * @priv: unused * @i: returned input line number * * the current active input line is returned @@ -554,6 +560,8 @@ static int vidioc_g_input(struct file *file, void *priv, unsigned int *i) /** * vidioc_enum_fmt_vid_cap - return video capture format + * @file: descriptor of device + * @priv: unused * @f: returned format information * * returns name and format of video capture @@ -577,6 +585,7 @@ static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, /** * vidioc_try_fmt_vid_cap - set video capture format * @file: descriptor of device + * @priv: unused * @f: new format * * new video format is set which includes width and @@ -639,6 +648,7 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, /** * vidioc_s_fmt_vid_cap - set current video format parameters * @file: descriptor of device + * @priv: unused * @f: returned format information * * set new capture format @@ -706,6 +716,7 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, /** * vidioc_g_fmt_vid_cap - get current video format parameters * @file: descriptor of device + * @priv: unused * @f: contains format information * * returns current video format parameters -- GitLab From 8fd87479251925dedd6c524bc592541fefde2332 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 06:00:09 -0500 Subject: [PATCH 0329/2547] media: pxa_camera: get rid of kernel_doc warnings Get rid of the following warnings: drivers/media/platform/pxa_camera.c:247: warning: No description found for parameter 'layout' drivers/media/platform/pxa_camera.c:867: warning: No description found for parameter 'buf' drivers/media/platform/pxa_camera.c:867: warning: No description found for parameter 'sg' drivers/media/platform/pxa_camera.c:867: warning: No description found for parameter 'sglen' drivers/media/platform/pxa_camera.c:867: warning: Excess function parameter 'vb' description in 'pxa_init_dma_channel' drivers/media/platform/pxa_camera.c:867: warning: Excess function parameter 'dma' description in 'pxa_init_dma_channel' drivers/media/platform/pxa_camera.c:867: warning: Excess function parameter 'cibr' description in 'pxa_init_dma_channel' drivers/media/platform/pxa_camera.c:1029: warning: No description found for parameter 'last_submitted' drivers/media/platform/pxa_camera.c:1029: warning: No description found for parameter 'last_issued' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/pxa_camera.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/pxa_camera.c b/drivers/media/platform/pxa_camera.c index 9d3f0cb1d95a..295f34ad1080 100644 --- a/drivers/media/platform/pxa_camera.c +++ b/drivers/media/platform/pxa_camera.c @@ -235,6 +235,7 @@ enum pxa_mbus_layout { * stored in memory in the following way: * @packing: Type of sample-packing, that has to be used * @order: Sample order when storing in memory + * @layout: Planes layout in memory * @bits_per_sample: How many bits the bridge has to sample */ struct pxa_mbus_pixelfmt { @@ -852,10 +853,10 @@ static void pxa_camera_dma_irq_v(void *data) /** * pxa_init_dma_channel - init dma descriptors * @pcdev: pxa camera device - * @vb: videobuffer2 buffer - * @dma: dma video buffer + * @buf: pxa camera buffer * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') - * @cibr: camera Receive Buffer Register + * @sg: dma scatter list + * @sglen: dma scatter list length * * Prepares the pxa dma descriptors to transfer one camera channel. * @@ -1010,6 +1011,8 @@ static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, /** * pxa_camera_check_link_miss - check missed DMA linking * @pcdev: camera device + * @last_submitted: an opaque DMA cookie for last submitted + * @last_issued: an opaque DMA cookie for last issued * * The DMA chaining is done with DMA running. This means a tiny temporal window * remains, where a buffer is queued on the chain, while the chain is already -- GitLab From ef69f8d2ff09518657c3ecaf2db8408c16549829 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 06:03:52 -0500 Subject: [PATCH 0330/2547] media: tw68: fix kernel-doc markups There are a few mistakes on the existing markups: drivers/media/pci/tw68/tw68-risc.c:32: warning: Cannot understand * @rp pointer to current risc program position on line 32 - I thought it was a doc line drivers/media/pci/tw68/tw68-risc.c:144: warning: No description found for parameter 'pci' drivers/media/pci/tw68/tw68-risc.c:144: warning: No description found for parameter 'buf' drivers/media/pci/tw68/tw68-risc.c:144: warning: No description found for parameter 'sglist' drivers/media/pci/tw68/tw68-risc.c:144: warning: No description found for parameter 'top_offset' drivers/media/pci/tw68/tw68-risc.c:144: warning: No description found for parameter 'bottom_offset' drivers/media/pci/tw68/tw68-risc.c:144: warning: No description found for parameter 'bpl' drivers/media/pci/tw68/tw68-risc.c:144: warning: No description found for parameter 'padding' drivers/media/pci/tw68/tw68-risc.c:144: warning: No description found for parameter 'lines' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/pci/tw68/tw68-risc.c | 33 +++++++++++++++--------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/media/pci/tw68/tw68-risc.c b/drivers/media/pci/tw68/tw68-risc.c index 7439db212a69..82ff9c9494f3 100644 --- a/drivers/media/pci/tw68/tw68-risc.c +++ b/drivers/media/pci/tw68/tw68-risc.c @@ -29,14 +29,15 @@ #include "tw68.h" /** - * @rp pointer to current risc program position - * @sglist pointer to "scatter-gather list" of buffer pointers - * @offset offset to target memory buffer - * @sync_line 0 -> no sync, 1 -> odd sync, 2 -> even sync - * @bpl number of bytes per scan line - * @padding number of bytes of padding to add - * @lines number of lines in field - * @jump insert a jump at the start + * tw68_risc_field + * @rp: pointer to current risc program position + * @sglist: pointer to "scatter-gather list" of buffer pointers + * @offset: offset to target memory buffer + * @sync_line: 0 -> no sync, 1 -> odd sync, 2 -> even sync + * @bpl: number of bytes per scan line + * @padding: number of bytes of padding to add + * @lines: number of lines in field + * @jump: insert a jump at the start */ static __le32 *tw68_risc_field(__le32 *rp, struct scatterlist *sglist, unsigned int offset, u32 sync_line, @@ -120,18 +121,18 @@ static __le32 *tw68_risc_field(__le32 *rp, struct scatterlist *sglist, * memory for the dma controller "program" and then fills in that * memory with the appropriate "instructions". * - * @pci_dev structure with info about the pci + * @pci: structure with info about the pci * slot which our device is in. - * @risc structure with info about the memory + * @buf: structure with info about the memory * used for our controller program. - * @sglist scatter-gather list entry - * @top_offset offset within the risc program area for the + * @sglist: scatter-gather list entry + * @top_offset: offset within the risc program area for the * first odd frame line - * @bottom_offset offset within the risc program area for the + * @bottom_offset: offset within the risc program area for the * first even frame line - * @bpl number of data bytes per scan line - * @padding number of extra bytes to add at end of line - * @lines number of scan lines + * @bpl: number of data bytes per scan line + * @padding: number of extra bytes to add at end of line + * @lines: number of scan lines */ int tw68_risc_buffer(struct pci_dev *pci, struct tw68_buf *buf, -- GitLab From 4521af781190848f4d7f499b9f946a8d86f6df4f Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 08:19:13 -0500 Subject: [PATCH 0331/2547] media: ix2505v: get rid of /** comments As warned: drivers/media/dvb-frontends/ix2505v.c:24: warning: cannot understand function prototype: 'int ix2505v_debug; ' drivers/media/dvb-frontends/ix2505v.c:59: warning: No description found for parameter 'state' drivers/media/dvb-frontends/ix2505v.c:128: warning: No description found for parameter 'fe' None of the comments there are kernel-doc. So, remove them with: perl -pi -e 's,\/\*\*,/*,g' drivers/media/dvb-frontends/ix2505v.c Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/ix2505v.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/dvb-frontends/ix2505v.c b/drivers/media/dvb-frontends/ix2505v.c index 534b24fa2b95..965012ad5c59 100644 --- a/drivers/media/dvb-frontends/ix2505v.c +++ b/drivers/media/dvb-frontends/ix2505v.c @@ -1,4 +1,4 @@ -/** +/* * Driver for Sharp IX2505V (marked B0017) DVB-S silicon tuner * * Copyright (C) 2010 Malcolm Priestley @@ -36,7 +36,7 @@ struct ix2505v_state { u32 frequency; }; -/** +/* * Data read format of the Sharp IX2505V B0017 * * byte1: 1 | 1 | 0 | 0 | 0 | MA1 | MA0 | 1 @@ -99,7 +99,7 @@ static void ix2505v_release(struct dvb_frontend *fe) } -/** +/* * Data write format of the Sharp IX2505V B0017 * * byte1: 1 | 1 | 0 | 0 | 0 | 0(MA1)| 0(MA0)| 0 -- GitLab From d156f2935b6389ec3bd75c69c055c5ac84e14558 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 08:33:30 -0500 Subject: [PATCH 0332/2547] media: radio-si476x: fix kernel-doc markups get rid of the following warnings: drivers/media/radio/radio-si476x.c:317: warning: No description found for parameter 'v4l2dev' drivers/media/radio/radio-si476x.c:317: warning: No description found for parameter 'ctrl_handler' drivers/media/radio/radio-si476x.c:317: warning: No description found for parameter 'debugfs' drivers/media/radio/radio-si476x.c:317: warning: No description found for parameter 'audmode' drivers/media/radio/radio-si476x.c:317: warning: Excess struct member 'kref' description in 'si476x_radio' drivers/media/radio/radio-si476x.c:317: warning: Excess struct member 'core_lock' description in 'si476x_radio' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/radio/radio-si476x.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/media/radio/radio-si476x.c b/drivers/media/radio/radio-si476x.c index 271f725b17e8..540ac887a63c 100644 --- a/drivers/media/radio/radio-si476x.c +++ b/drivers/media/radio/radio-si476x.c @@ -158,7 +158,7 @@ enum si476x_ctrl_idx { }; static struct v4l2_ctrl_config si476x_ctrls[] = { - /** + /* * SI476X during its station seeking(or tuning) process uses several * parameters to detrmine if "the station" is valid: * @@ -197,7 +197,7 @@ static struct v4l2_ctrl_config si476x_ctrls[] = { .step = 2, }, - /** + /* * #V4L2_CID_SI476X_HARMONICS_COUNT -- number of harmonics * built-in power-line noise supression filter is to reject * during AM-mode operation. @@ -213,7 +213,7 @@ static struct v4l2_ctrl_config si476x_ctrls[] = { .step = 1, }, - /** + /* * #V4L2_CID_SI476X_DIVERSITY_MODE -- configuration which * two tuners working in diversity mode are to work in. * @@ -237,7 +237,7 @@ static struct v4l2_ctrl_config si476x_ctrls[] = { .max = ARRAY_SIZE(phase_diversity_modes) - 1, }, - /** + /* * #V4L2_CID_SI476X_INTERCHIP_LINK -- inter-chip link in * diversity mode indicator. Allows user to determine if two * chips working in diversity mode have established a link @@ -296,11 +296,15 @@ struct si476x_radio_ops { /** * struct si476x_radio - radio device * - * @core: Pointer to underlying core device + * @v4l2dev: Pointer to V4L2 device created by V4L2 subsystem * @videodev: Pointer to video device created by V4L2 subsystem + * @ctrl_handler: V4L2 controls handler + * @core: Pointer to underlying core device * @ops: Vtable of functions. See struct si476x_radio_ops for details - * @kref: Reference counter - * @core_lock: An r/w semaphore to brebvent the deletion of underlying + * @debugfs: pointer to &strucd dentry for debugfs + * @audmode: audio mode, as defined for the rxsubchans field + * at videodev2.h + * * core structure is the radio device is being used */ struct si476x_radio { -- GitLab From 7cd183696ec67a6741cf7db45eb0bce14da60767 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 08:41:06 -0500 Subject: [PATCH 0333/2547] media: s5k6a3: document some fields at struct s5k6a3 drivers/media/i2c/s5k6a3.c:68: warning: No description found for parameter 'clock' drivers/media/i2c/s5k6a3.c:68: warning: No description found for parameter 'clock_frequency' drivers/media/i2c/s5k6a3.c:68: warning: No description found for parameter 'power_count' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/s5k6a3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/i2c/s5k6a3.c b/drivers/media/i2c/s5k6a3.c index 67dcca76f981..2e140272794b 100644 --- a/drivers/media/i2c/s5k6a3.c +++ b/drivers/media/i2c/s5k6a3.c @@ -53,6 +53,9 @@ enum { * @gpio_reset: GPIO connected to the sensor's reset pin * @lock: mutex protecting the structure's members below * @format: media bus format at the sensor's source pad + * @clock: pointer to &struct clk. + * @clock_frequency: clock frequency + * @power_count: stores state if device is powered */ struct s5k6a3 { struct device *dev; -- GitLab From 070250a1715cee2297de0d9e7e2cea58be999d37 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 08:44:41 -0500 Subject: [PATCH 0334/2547] media: s5k6aa: describe some function parameters as warned: drivers/media/i2c/s5k6aa.c:429: warning: No description found for parameter 's5k6aa' drivers/media/i2c/s5k6aa.c:679: warning: No description found for parameter 's5k6aa' drivers/media/i2c/s5k6aa.c:733: warning: No description found for parameter 's5k6aa' drivers/media/i2c/s5k6aa.c:733: warning: No description found for parameter 'preset' drivers/media/i2c/s5k6aa.c:787: warning: No description found for parameter 'sd' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/s5k6aa.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/media/i2c/s5k6aa.c b/drivers/media/i2c/s5k6aa.c index 9fd254a8e20d..13c10b5e2b45 100644 --- a/drivers/media/i2c/s5k6aa.c +++ b/drivers/media/i2c/s5k6aa.c @@ -421,6 +421,7 @@ static int s5k6aa_set_ahb_address(struct i2c_client *client) /** * s5k6aa_configure_pixel_clock - apply ISP main clock/PLL configuration + * @s5k6aa: pointer to &struct s5k6aa describing the device * * Configure the internal ISP PLL for the required output frequency. * Locking: called with s5k6aa.lock mutex held. @@ -669,6 +670,7 @@ static int s5k6aa_set_input_params(struct s5k6aa *s5k6aa) /** * s5k6aa_configure_video_bus - configure the video output interface + * @s5k6aa: pointer to &struct s5k6aa describing the device * @bus_type: video bus type: parallel or MIPI-CSI * @nlanes: number of MIPI lanes to be used (MIPI-CSI only) * @@ -724,6 +726,8 @@ static int s5k6aa_new_config_sync(struct i2c_client *client, int timeout, /** * s5k6aa_set_prev_config - write user preview register set + * @s5k6aa: pointer to &struct s5k6aa describing the device + * @preset: s5kaa preset to be applied * * Configure output resolution and color fromat, pixel clock * frequency range, device frame rate type and frame period range. @@ -777,6 +781,7 @@ static int s5k6aa_set_prev_config(struct s5k6aa *s5k6aa, /** * s5k6aa_initialize_isp - basic ISP MCU initialization + * @sd: pointer to V4L2 sub-device descriptor * * Configure AHB addresses for registers read/write; configure PLLs for * required output pixel clock. The ISP power supply needs to be already -- GitLab From b5a21f8a8555b03433f5b2aa65adfd996da469f5 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 09:10:03 -0500 Subject: [PATCH 0335/2547] media: netup_unidvb: fix a bad kernel-doc markup There is a bad kernel-doc markup, producing the following warnings: drivers/media/pci/netup_unidvb/netup_unidvb_core.c:85: warning: bad line: Bits [0-7]: DMA packet size, 188 bytes drivers/media/pci/netup_unidvb/netup_unidvb_core.c:86: warning: bad line: Bits [16-23]: packets count in block, 128 packets drivers/media/pci/netup_unidvb/netup_unidvb_core.c:87: warning: bad line: Bits [24-31]: blocks count, 8 blocks drivers/media/pci/netup_unidvb/netup_unidvb_core.c:89: warning: bad line: For example, value of 375000000 equals to 3 sec Fix that, and use a list for the bits option, in order for it to be better format, if we add it to a driver's documentation file. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/pci/netup_unidvb/netup_unidvb_core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/pci/netup_unidvb/netup_unidvb_core.c b/drivers/media/pci/netup_unidvb/netup_unidvb_core.c index 11829c0fa138..509d69e6ca4a 100644 --- a/drivers/media/pci/netup_unidvb/netup_unidvb_core.c +++ b/drivers/media/pci/netup_unidvb/netup_unidvb_core.c @@ -82,11 +82,11 @@ DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); * @start_addr_lo: DMA ring buffer start address, lower part * @start_addr_hi: DMA ring buffer start address, higher part * @size: DMA ring buffer size register - Bits [0-7]: DMA packet size, 188 bytes - Bits [16-23]: packets count in block, 128 packets - Bits [24-31]: blocks count, 8 blocks + * * Bits [0-7]: DMA packet size, 188 bytes + * * Bits [16-23]: packets count in block, 128 packets + * * Bits [24-31]: blocks count, 8 blocks * @timeout: DMA timeout in units of 8ns - For example, value of 375000000 equals to 3 sec + * For example, value of 375000000 equals to 3 sec * @curr_addr_lo: Current ring buffer head address, lower part * @curr_addr_hi: Current ring buffer head address, higher part * @stat_pkt_received: Statistic register, not tested -- GitLab From c5bb831854d7a710ca84cb9a120ac7b89b2f6d57 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 09:26:20 -0500 Subject: [PATCH 0336/2547] media: tvp514x: fix kernel-doc parameters There are some struct fields that aren't documented, and some consts whose comments start with /**, but they aren't kernel-doc annotations. So, fix it: drivers/media/i2c/tvp514x.c:127: warning: No description found for parameter 'hdl' drivers/media/i2c/tvp514x.c:127: warning: No description found for parameter 'pad' drivers/media/i2c/tvp514x.c:127: warning: No description found for parameter 'format' drivers/media/i2c/tvp514x.c:127: warning: No description found for parameter 'int_seq' drivers/media/i2c/tvp514x.c:219: warning: cannot understand function prototype: 'const struct v4l2_fmtdesc tvp514x_fmt_list[] = ' drivers/media/i2c/tvp514x.c:235: warning: cannot understand function prototype: 'const struct tvp514x_std_info tvp514x_std_list[] = ' drivers/media/i2c/tvp514x.c:941: warning: No description found for parameter 'fmt' drivers/media/i2c/tvp514x.c:941: warning: Excess function parameter 'format' description in 'tvp514x_set_pad_format' drivers/media/i2c/tvp514x.c:1208: warning: cannot understand function prototype: 'const struct i2c_device_id tvp514x_id[] = ' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/tvp514x.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/media/i2c/tvp514x.c b/drivers/media/i2c/tvp514x.c index ad2df998f9c5..d575b3e7e835 100644 --- a/drivers/media/i2c/tvp514x.c +++ b/drivers/media/i2c/tvp514x.c @@ -86,6 +86,7 @@ static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable); /** * struct tvp514x_decoder - TVP5146/47 decoder object * @sd: Subdevice Slave handle + * @hdl: embedded &struct v4l2_ctrl_handler * @tvp514x_regs: copy of hw's regs with preset values. * @pdata: Board specific * @ver: Chip version @@ -98,6 +99,9 @@ static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable); * @std_list: Standards list * @input: Input routing at chip level * @output: Output routing at chip level + * @pad: subdev media pad associated with the decoder + * @format: media bus frame format + * @int_seq: driver's register init sequence */ struct tvp514x_decoder { struct v4l2_subdev sd; @@ -211,7 +215,7 @@ static struct tvp514x_reg tvp514x_reg_list_default[] = { {TOK_TERM, 0, 0}, }; -/** +/* * List of image formats supported by TVP5146/47 decoder * Currently we are using 8 bit mode only, but can be * extended to 10/20 bit mode. @@ -226,7 +230,7 @@ static const struct v4l2_fmtdesc tvp514x_fmt_list[] = { }, }; -/** +/* * Supported standards - * * Currently supports two standards only, need to add support for rest of the @@ -931,7 +935,7 @@ static int tvp514x_get_pad_format(struct v4l2_subdev *sd, * tvp514x_set_pad_format() - V4L2 decoder interface handler for set pad format * @sd: pointer to standard V4L2 sub-device structure * @cfg: pad configuration - * @format: pointer to v4l2_subdev_format structure + * @fmt: pointer to v4l2_subdev_format structure * * Set pad format for the output pad */ @@ -1199,7 +1203,7 @@ static const struct tvp514x_reg tvp514xm_init_reg_seq[] = { {TOK_TERM, 0, 0}, }; -/** +/* * I2C Device Table - * * name - Name of the actual device/chip. -- GitLab From d714a755d5c48f21f1ffa32ac1fade65db93f34d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 09:36:39 -0500 Subject: [PATCH 0337/2547] media: vdec: fix some kernel-doc warnings Fix those warnings: drivers/media/platform/mtk-vcodec/vdec/vdec_h264_if.c:69: warning: No description found for parameter 'reserved' drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c:175: warning: Excess struct member 'dev' description in 'vdec_vp8_inst' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/mtk-vcodec/vdec/vdec_h264_if.c | 1 + drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_if.c b/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_if.c index b7731b18ecae..aa3ce41898bc 100644 --- a/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_if.c @@ -59,6 +59,7 @@ struct h264_fb { * @read_idx : read index * @write_idx : write index * @count : buffer count in list + * @reserved : for 8 bytes alignment */ struct h264_ring_fb_list { struct h264_fb fb_list[H264_MAX_FB_NUM]; diff --git a/drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c b/drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c index b9fad6a48879..3e84a761db3a 100644 --- a/drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c @@ -155,7 +155,6 @@ struct vdec_vp8_vpu_inst { * @reg_base : HW register base address * @frm_cnt : decode frame count * @ctx : V4L2 context - * @dev : platform device * @vpu : VPU instance for decoder * @vsi : VPU share information */ -- GitLab From 98156359596779d425ee14ff07ffc1735842bf9a Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 09:58:09 -0500 Subject: [PATCH 0338/2547] media: mtk-vpu: add description for wdt fields at struct mtk_vpu Fix those warnings: drivers/media/platform/mtk-vpu/mtk_vpu.c:223: warning: No description found for parameter 'wdt' drivers/media/platform/mtk-vpu/mtk_vpu.c:223: warning: No description found for parameter 'wdt_refcnt' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/mtk-vpu/mtk_vpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mtk-vpu/mtk_vpu.c b/drivers/media/platform/mtk-vpu/mtk_vpu.c index 853d598937f6..1ff6a93262b7 100644 --- a/drivers/media/platform/mtk-vpu/mtk_vpu.c +++ b/drivers/media/platform/mtk-vpu/mtk_vpu.c @@ -181,6 +181,7 @@ struct share_obj { * @extmem: VPU extended memory information * @reg: VPU TCM and configuration registers * @run: VPU initialization status + * @wdt: VPU watchdog workqueue * @ipi_desc: VPU IPI descriptor * @recv_buf: VPU DTCM share buffer for receiving. The * receive buffer is only accessed in interrupt context. @@ -194,7 +195,7 @@ struct share_obj { * suppose a client is using VPU to decode VP8. * If the other client wants to encode VP8, * it has to wait until VP8 decode completes. - * @wdt_refcnt WDT reference count to make sure the watchdog can be + * @wdt_refcnt: WDT reference count to make sure the watchdog can be * disabled if no other client is using VPU service * @ack_wq: The wait queue for each codec and mdp. When sleeping * processes wake up, they will check the condition -- GitLab From fa7871255fe4bb63bb8f4f96f0584f5a07e0936d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 09:59:55 -0500 Subject: [PATCH 0339/2547] media: s3c-camif: add missing description at s3c_camif_find_format() Fix this warning: drivers/media/platform/s3c-camif/camif-core.c:112: warning: No description found for parameter 'vp' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/s3c-camif/camif-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/s3c-camif/camif-core.c b/drivers/media/platform/s3c-camif/camif-core.c index c4ab63986c8f..79bc0ef6bb41 100644 --- a/drivers/media/platform/s3c-camif/camif-core.c +++ b/drivers/media/platform/s3c-camif/camif-core.c @@ -103,6 +103,7 @@ static const struct camif_fmt camif_formats[] = { /** * s3c_camif_find_format() - lookup camif color format by fourcc or an index + * @vp: video path (DMA) description (codec/preview) * @pixelformat: fourcc to match, ignored if null * @index: index to the camif_formats array, ignored if negative */ -- GitLab From 5bef1c0bd53abb80613f901c4ac50131d035604f Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 10:00:58 -0500 Subject: [PATCH 0340/2547] media: radio-wl1273: fix a parameter name at kernel-doc macro Solve those warnings: drivers/media/radio/radio-wl1273.c:1337: warning: No description found for parameter 'radio' drivers/media/radio/radio-wl1273.c:1337: warning: Excess function parameter 'core' description in 'wl1273_fm_set_tx_power' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/radio/radio-wl1273.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/radio/radio-wl1273.c b/drivers/media/radio/radio-wl1273.c index 903fcd5e99c0..3cbdc085c65d 100644 --- a/drivers/media/radio/radio-wl1273.c +++ b/drivers/media/radio/radio-wl1273.c @@ -1330,7 +1330,7 @@ static int wl1273_fm_vidioc_s_input(struct file *file, void *priv, /** * wl1273_fm_set_tx_power() - Set the transmission power value. - * @core: A pointer to the device struct. + * @radio: A pointer to the device struct. * @power: The new power value. */ static int wl1273_fm_set_tx_power(struct wl1273_device *radio, u16 power) -- GitLab From 69a52ad3196a98616c333194a2c1295a294e3b51 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 10:01:56 -0500 Subject: [PATCH 0341/2547] media: mt2063: fix some kernel-doc warnings Fix those warnings: drivers/media/tuners/mt2063.c:1413: warning: No description found for parameter 'f_ref' drivers/media/tuners/mt2063.c:1413: warning: Excess function parameter 'f_Ref' description in 'MT2063_fLO_FractionalTerm' drivers/media/tuners/mt2063.c:1476: warning: Excess function parameter 'f_Avoid' description in 'MT2063_CalcLO2Mult' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/tuners/mt2063.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/media/tuners/mt2063.c b/drivers/media/tuners/mt2063.c index 8b39d8dc97a0..5c87c5c6a455 100644 --- a/drivers/media/tuners/mt2063.c +++ b/drivers/media/tuners/mt2063.c @@ -1397,9 +1397,9 @@ static u32 MT2063_Round_fLO(u32 f_LO, u32 f_LO_Step, u32 f_ref) * risk of overflow. It accurately calculates * f_ref * num / denom to within 1 HZ with fixed math. * - * @num : Fractional portion of the multiplier + * @f_ref: SRO frequency. + * @num: Fractional portion of the multiplier * @denom: denominator portion of the ratio - * @f_Ref: SRO frequency. * * This calculation handles f_ref as two separate 14-bit fields. * Therefore, a maximum value of 2^28-1 may safely be used for f_ref. @@ -1464,8 +1464,6 @@ static u32 MT2063_CalcLO1Mult(u32 *Div, * @f_LO: desired LO frequency. * @f_LO_Step: Minimum step size for the LO (in Hz). * @f_Ref: SRO frequency. - * @f_Avoid: Range of PLL frequencies to avoid near - * integer multiples of f_Ref (in Hz). * * Returns: Recalculated LO frequency. */ -- GitLab From bd98f7a16d3a7c98157585ef406b727982db18cf Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 10:05:57 -0500 Subject: [PATCH 0342/2547] media: soc_camera: fix a kernel-doc markup Remove this warning: drivers/media/platform/soc_camera/soc_scale_crop.c:309: warning: Cannot understand * @icd - soc-camera device on line 309 - I thought it was a doc line Signed-off-by: Mauro Carvalho Chehab Acked-by: Guennadi Liakhovetski --- .../platform/soc_camera/soc_scale_crop.c | 21 ++++++++++--------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/soc_camera/soc_scale_crop.c b/drivers/media/platform/soc_camera/soc_scale_crop.c index 0116097c0c0f..270ec613c27c 100644 --- a/drivers/media/platform/soc_camera/soc_scale_crop.c +++ b/drivers/media/platform/soc_camera/soc_scale_crop.c @@ -306,16 +306,17 @@ static int client_set_fmt(struct soc_camera_device *icd, } /** - * @icd - soc-camera device - * @rect - camera cropping window - * @subrect - part of rect, sent to the user - * @mf - in- / output camera output window - * @width - on input: max host input width - * on output: user width, mapped back to input - * @height - on input: max host input height - * on output: user height, mapped back to input - * @host_can_scale - host can scale this pixel format - * @shift - shift, used for scaling + * soc_camera_client_scale + * @icd: soc-camera device + * @rect: camera cropping window + * @subrect: part of rect, sent to the user + * @mf: in- / output camera output window + * @width: on input: max host input width; + * on output: user width, mapped back to input + * @height: on input: max host input height; + * on output: user height, mapped back to input + * @host_can_scale: host can scale this pixel format + * @shift: shift, used for scaling */ int soc_camera_client_scale(struct soc_camera_device *icd, struct v4l2_rect *rect, struct v4l2_rect *subrect, -- GitLab From 2afe216d3d88b729c40d83abce5b2d4b72d289c5 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 10:11:04 -0500 Subject: [PATCH 0343/2547] media: vsp1: add a missing kernel-doc parameter Fix this warning: drivers/media/platform/vsp1/vsp1_dl.c:87: warning: No description found for parameter 'has_chain' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/vsp1/vsp1_dl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c index 8b5cbb6b7a70..4257451f1bd8 100644 --- a/drivers/media/platform/vsp1/vsp1_dl.c +++ b/drivers/media/platform/vsp1/vsp1_dl.c @@ -70,6 +70,7 @@ struct vsp1_dl_body { * @dma: DMA address for the header * @body0: first display list body * @fragments: list of extra display list bodies + * @has_chain: if true, indicates that there's a partition chain * @chain: entry in the display list partition chain */ struct vsp1_dl_list { -- GitLab From 538cf6437af951f84cc816d63aafeafc61eb40c1 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 10:15:53 -0500 Subject: [PATCH 0344/2547] media: rcar_jpu: fix two kernel-doc markups On kernel-doc, struct declarations should be declared as "struct foo". Fix the following warnings: drivers/media/platform/rcar_jpu.c:265: warning: cannot understand function prototype: 'struct jpu_q_data ' drivers/media/platform/rcar_jpu.c:281: warning: cannot understand function prototype: 'struct jpu_ctx ' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/rcar_jpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/rcar_jpu.c b/drivers/media/platform/rcar_jpu.c index 070bac36d766..f6092ae45912 100644 --- a/drivers/media/platform/rcar_jpu.c +++ b/drivers/media/platform/rcar_jpu.c @@ -257,7 +257,7 @@ struct jpu_fmt { }; /** - * jpu_q_data - parameters of one queue + * struct jpu_q_data - parameters of one queue * @fmtinfo: driver-specific format of this queue * @format: multiplanar format of this queue * @sequence: sequence number @@ -269,7 +269,7 @@ struct jpu_q_data { }; /** - * jpu_ctx - the device context data + * struct jpu_ctx - the device context data * @jpu: JPEG IP device for this context * @encoder: compression (encode) operation or decompression (decode) * @compr_quality: destination image quality in compression (encode) mode -- GitLab From ed050c21801566db25a907798fb4e189589ca8c8 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 10:17:33 -0500 Subject: [PATCH 0345/2547] media: lm3560: add a missing kernel-doc parameter Fix this warning: drivers/media/i2c/lm3560.c:69: warning: No description found for parameter 'dev' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/lm3560.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/i2c/lm3560.c b/drivers/media/i2c/lm3560.c index 251a2aaf98c3..b600e03aa94b 100644 --- a/drivers/media/i2c/lm3560.c +++ b/drivers/media/i2c/lm3560.c @@ -50,6 +50,7 @@ enum led_enable { /** * struct lm3560_flash * + * @dev: pointer to &struct device * @pdata: platform data * @regmap: reg. map for i2c * @lock: muxtex for serial access. -- GitLab From cba862dc7301d62f90393f2bbb181834a3125308 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 08:33:45 -0500 Subject: [PATCH 0346/2547] media: drivers: remove "/**" from non-kernel-doc comments Several comments are wrongly tagged as kernel-doc, causing those warnings: drivers/media/rc/st_rc.c:98: warning: No description found for parameter 'irq' drivers/media/rc/st_rc.c:98: warning: No description found for parameter 'data' drivers/media/pci/solo6x10/solo6x10-enc.c:183: warning: No description found for parameter 'solo_dev' drivers/media/pci/solo6x10/solo6x10-enc.c:183: warning: No description found for parameter 'ch' drivers/media/pci/solo6x10/solo6x10-enc.c:183: warning: No description found for parameter 'qp' drivers/media/usb/pwc/pwc-dec23.c:652: warning: Cannot understand * on line 652 - I thought it was a doc line drivers/media/usb/dvb-usb/cinergyT2-fe.c:40: warning: No description found for parameter 'op' drivers/media/usb/dvb-usb/friio-fe.c:301: warning: Cannot understand * (reg, val) commad list to initialize this module. on line 301 - I thought it was a doc line drivers/media/rc/streamzap.c:201: warning: No description found for parameter 'urb' drivers/media/rc/streamzap.c:333: warning: No description found for parameter 'intf' drivers/media/rc/streamzap.c:333: warning: No description found for parameter 'id' drivers/media/rc/streamzap.c:464: warning: No description found for parameter 'interface' drivers/media/i2c/ov5647.c:432: warning: Cannot understand * @short Subdev core operations registration on line 432 - I thought it was a doc line drivers/media/usb/dvb-usb/friio.c:35: warning: No description found for parameter 'd' drivers/media/usb/dvb-usb/friio.c:35: warning: No description found for parameter 'addr' drivers/media/usb/dvb-usb/friio.c:35: warning: No description found for parameter 'wbuf' drivers/media/usb/dvb-usb/friio.c:35: warning: No description found for parameter 'wlen' drivers/media/usb/dvb-usb/friio.c:35: warning: No description found for parameter 'rbuf' drivers/media/usb/dvb-usb/friio.c:35: warning: No description found for parameter 'rlen' drivers/media/platform/vim2m.c:350: warning: No description found for parameter 'priv' drivers/media/dvb-frontends/tua6100.c:34: warning: cannot understand function prototype: 'struct tua6100_priv ' drivers/media/platform/sti/hva/hva-h264.c:140: warning: cannot understand function prototype: 'struct hva_h264_stereo_video_sei ' drivers/media/platform/sti/hva/hva-h264.c:150: warning: Cannot understand * @frame_width: width in pixels of the buffer containing the input frame on line 150 - I thought it was a doc line drivers/media/platform/sti/hva/hva-h264.c:356: warning: Cannot understand * @ slice_size: slice size on line 356 - I thought it was a doc line drivers/media/platform/sti/hva/hva-h264.c:369: warning: Cannot understand * @ bitstream_size: bitstream size on line 369 - I thought it was a doc line drivers/media/platform/sti/hva/hva-h264.c:395: warning: Cannot understand * @seq_info: sequence information buffer on line 395 - I thought it was a doc line drivers/media/dvb-frontends/sp887x.c:137: warning: No description found for parameter 'fe' drivers/media/dvb-frontends/sp887x.c:137: warning: No description found for parameter 'fw' drivers/media/dvb-frontends/sp887x.c:287: warning: No description found for parameter 'n' drivers/media/dvb-frontends/sp887x.c:287: warning: No description found for parameter 'd' drivers/media/dvb-frontends/sp887x.c:287: warning: No description found for parameter 'quotient_i' drivers/media/dvb-frontends/sp887x.c:287: warning: No description found for parameter 'quotient_f' drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c:83: warning: cannot understand function prototype: 'struct ttusb ' drivers/media/platform/sh_veu.c:277: warning: No description found for parameter 'priv' drivers/media/dvb-frontends/zl10036.c:33: warning: cannot understand function prototype: 'int zl10036_debug; ' drivers/media/dvb-frontends/zl10036.c:179: warning: No description found for parameter 'state' drivers/media/dvb-frontends/zl10036.c:179: warning: No description found for parameter 'frequency' drivers/media/platform/rcar_fdp1.c:1139: warning: No description found for parameter 'priv' drivers/media/platform/ti-vpe/vpe.c:933: warning: No description found for parameter 'priv' drivers/media/usb/gspca/ov519.c:36: warning: No description found for parameter 'fmt' drivers/media/usb/dvb-usb/dib0700_devices.c:3367: warning: No description found for parameter 'adap' Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/sp887x.c | 6 +++--- drivers/media/dvb-frontends/tua6100.c | 2 +- drivers/media/dvb-frontends/zl10036.c | 8 ++++---- drivers/media/i2c/ov5647.c | 4 ++-- drivers/media/pci/solo6x10/solo6x10-enc.c | 2 +- drivers/media/platform/rcar_fdp1.c | 2 +- drivers/media/platform/sh_veu.c | 2 +- drivers/media/platform/sti/hva/hva-h264.c | 18 +++++++++++++----- drivers/media/platform/ti-vpe/vpe.c | 2 +- drivers/media/platform/vim2m.c | 2 +- drivers/media/rc/st_rc.c | 6 +++--- drivers/media/rc/streamzap.c | 6 +++--- drivers/media/usb/dvb-usb/cinergyT2-fe.c | 2 +- drivers/media/usb/dvb-usb/dib0700_devices.c | 8 ++++---- drivers/media/usb/dvb-usb/friio-fe.c | 2 +- drivers/media/usb/dvb-usb/friio.c | 2 +- drivers/media/usb/gspca/ov519.c | 2 +- drivers/media/usb/pwc/pwc-dec23.c | 7 +++---- .../media/usb/ttusb-budget/dvb-ttusb-budget.c | 6 +++--- 19 files changed, 48 insertions(+), 41 deletions(-) diff --git a/drivers/media/dvb-frontends/sp887x.c b/drivers/media/dvb-frontends/sp887x.c index 7c511c3cd4ca..d2c402b52c6e 100644 --- a/drivers/media/dvb-frontends/sp887x.c +++ b/drivers/media/dvb-frontends/sp887x.c @@ -57,7 +57,7 @@ static int sp887x_writereg (struct sp887x_state* state, u16 reg, u16 data) int ret; if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) { - /** + /* * in case of soft reset we ignore ACK errors... */ if (!(reg == 0xf1a && data == 0x000 && @@ -130,7 +130,7 @@ static void sp887x_setup_agc (struct sp887x_state* state) #define BLOCKSIZE 30 #define FW_SIZE 0x4000 -/** +/* * load firmware and setup MPEG interface... */ static int sp887x_initial_setup (struct dvb_frontend* fe, const struct firmware *fw) @@ -279,7 +279,7 @@ static int configure_reg0xc05(struct dtv_frontend_properties *p, u16 *reg0xc05) return 0; } -/** +/* * estimates division of two 24bit numbers, * derived from the ves1820/stv0299 driver code */ diff --git a/drivers/media/dvb-frontends/tua6100.c b/drivers/media/dvb-frontends/tua6100.c index 18e6d4c5be21..1d41abd47f04 100644 --- a/drivers/media/dvb-frontends/tua6100.c +++ b/drivers/media/dvb-frontends/tua6100.c @@ -1,4 +1,4 @@ -/** +/* * Driver for Infineon tua6100 pll. * * (c) 2006 Andrew de Quincey diff --git a/drivers/media/dvb-frontends/zl10036.c b/drivers/media/dvb-frontends/zl10036.c index 062282739ce5..89dd65ae88ad 100644 --- a/drivers/media/dvb-frontends/zl10036.c +++ b/drivers/media/dvb-frontends/zl10036.c @@ -1,4 +1,4 @@ -/** +/* * Driver for Zarlink zl10036 DVB-S silicon tuner * * Copyright (C) 2006 Tino Reichardt @@ -157,7 +157,7 @@ static int zl10036_sleep(struct dvb_frontend *fe) return ret; } -/** +/* * register map of the ZL10036/ZL10038 * * reg[default] content @@ -219,7 +219,7 @@ static int zl10036_set_bandwidth(struct zl10036_state *state, u32 fbw) if (fbw <= 28820) { br = _BR_MAXIMUM; } else { - /** + /* * f(bw)=34,6MHz f(xtal)=10.111MHz * br = (10111/34600) * 63 * 1/K = 14; */ @@ -315,7 +315,7 @@ static int zl10036_set_params(struct dvb_frontend *fe) || (frequency > fe->ops.info.frequency_max)) return -EINVAL; - /** + /* * alpha = 1.35 for dvb-s * fBW = (alpha*symbolrate)/(2*0.8) * 1.35 / (2*0.8) = 27 / 32 diff --git a/drivers/media/i2c/ov5647.c b/drivers/media/i2c/ov5647.c index 34179d232a35..da39c49de503 100644 --- a/drivers/media/i2c/ov5647.c +++ b/drivers/media/i2c/ov5647.c @@ -428,8 +428,8 @@ static int ov5647_sensor_set_register(struct v4l2_subdev *sd, } #endif -/** - * @short Subdev core operations registration +/* + * Subdev core operations registration */ static const struct v4l2_subdev_core_ops ov5647_subdev_core_ops = { .s_power = ov5647_sensor_power, diff --git a/drivers/media/pci/solo6x10/solo6x10-enc.c b/drivers/media/pci/solo6x10/solo6x10-enc.c index d28211bb9674..58d6b5131dd0 100644 --- a/drivers/media/pci/solo6x10/solo6x10-enc.c +++ b/drivers/media/pci/solo6x10/solo6x10-enc.c @@ -175,7 +175,7 @@ int solo_osd_print(struct solo_enc_dev *solo_enc) return 0; } -/** +/* * Set channel Quality Profile (0-3). */ void solo_s_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch, diff --git a/drivers/media/platform/rcar_fdp1.c b/drivers/media/platform/rcar_fdp1.c index 3245bc45f4a0..b13dec3081e5 100644 --- a/drivers/media/platform/rcar_fdp1.c +++ b/drivers/media/platform/rcar_fdp1.c @@ -1132,7 +1132,7 @@ static int fdp1_device_process(struct fdp1_ctx *ctx) * mem2mem callbacks */ -/** +/* * job_ready() - check whether an instance is ready to be scheduled to run */ static int fdp1_m2m_job_ready(void *priv) diff --git a/drivers/media/platform/sh_veu.c b/drivers/media/platform/sh_veu.c index 15a562af13c7..dedc1b024f6f 100644 --- a/drivers/media/platform/sh_veu.c +++ b/drivers/media/platform/sh_veu.c @@ -267,7 +267,7 @@ static void sh_veu_process(struct sh_veu_dev *veu, sh_veu_reg_write(veu, VEU_EIER, 1); /* enable interrupt in VEU */ } -/** +/* * sh_veu_device_run() - prepares and starts the device * * This will be called by the framework when it decides to schedule a particular diff --git a/drivers/media/platform/sti/hva/hva-h264.c b/drivers/media/platform/sti/hva/hva-h264.c index a7e5eed17ada..17f1eb0ba957 100644 --- a/drivers/media/platform/sti/hva/hva-h264.c +++ b/drivers/media/platform/sti/hva/hva-h264.c @@ -134,7 +134,7 @@ enum hva_h264_sei_payload_type { SEI_FRAME_PACKING_ARRANGEMENT = 45 }; -/** +/* * stereo Video Info struct */ struct hva_h264_stereo_video_sei { @@ -146,7 +146,9 @@ struct hva_h264_stereo_video_sei { u8 right_view_self_contained_flag; }; -/** +/* + * struct hva_h264_td + * * @frame_width: width in pixels of the buffer containing the input frame * @frame_height: height in pixels of the buffer containing the input frame * @frame_num: the parameter to be written in the slice header @@ -352,7 +354,9 @@ struct hva_h264_td { u32 addr_brc_in_out_parameter; }; -/** +/* + * struct hva_h264_slice_po + * * @ slice_size: slice size * @ slice_start_time: start time * @ slice_stop_time: stop time @@ -365,7 +369,9 @@ struct hva_h264_slice_po { u32 slice_num; }; -/** +/* + * struct hva_h264_po + * * @ bitstream_size: bitstream size * @ dct_bitstream_size: dtc bitstream size * @ stuffing_bits: number of stuffing bits inserted by the encoder @@ -391,7 +397,9 @@ struct hva_h264_task { struct hva_h264_po po; }; -/** +/* + * struct hva_h264_ctx + * * @seq_info: sequence information buffer * @ref_frame: reference frame buffer * @rec_frame: reconstructed frame buffer diff --git a/drivers/media/platform/ti-vpe/vpe.c b/drivers/media/platform/ti-vpe/vpe.c index 45bd10544189..e395aa85c8ad 100644 --- a/drivers/media/platform/ti-vpe/vpe.c +++ b/drivers/media/platform/ti-vpe/vpe.c @@ -926,7 +926,7 @@ static struct vpe_ctx *file2ctx(struct file *file) * mem2mem callbacks */ -/** +/* * job_ready() - check whether an instance is ready to be scheduled to run */ static int job_ready(void *priv) diff --git a/drivers/media/platform/vim2m.c b/drivers/media/platform/vim2m.c index 7bf9fa2f8534..065483e62db4 100644 --- a/drivers/media/platform/vim2m.c +++ b/drivers/media/platform/vim2m.c @@ -343,7 +343,7 @@ static void schedule_irq(struct vim2m_dev *dev, int msec_timeout) * mem2mem callbacks */ -/** +/* * job_ready() - check whether an instance is ready to be scheduled to run */ static int job_ready(void *priv) diff --git a/drivers/media/rc/st_rc.c b/drivers/media/rc/st_rc.c index a8e39c635f34..d2efd7b2c3bc 100644 --- a/drivers/media/rc/st_rc.c +++ b/drivers/media/rc/st_rc.c @@ -49,7 +49,7 @@ struct st_rc_device { #define IRB_RX_NOISE_SUPPR 0x5c /* noise suppression */ #define IRB_RX_POLARITY_INV 0x68 /* polarity inverter */ -/** +/* * IRQ set: Enable full FIFO 1 -> bit 3; * Enable overrun IRQ 1 -> bit 2; * Enable last symbol IRQ 1 -> bit 1: @@ -72,7 +72,7 @@ static void st_rc_send_lirc_timeout(struct rc_dev *rdev) ir_raw_event_store(rdev, &ev); } -/** +/* * RX graphical example to better understand the difference between ST IR block * output and standard definition used by LIRC (and most of the world!) * @@ -317,7 +317,7 @@ static int st_rc_probe(struct platform_device *pdev) device_init_wakeup(dev, true); dev_pm_set_wake_irq(dev, rc_dev->irq); - /** + /* * for LIRC_MODE_MODE2 or LIRC_MODE_PULSE or LIRC_MODE_RAW * lircd expects a long space first before a signal train to sync. */ diff --git a/drivers/media/rc/streamzap.c b/drivers/media/rc/streamzap.c index 4eebfcfc10f3..c9a70fda88a8 100644 --- a/drivers/media/rc/streamzap.c +++ b/drivers/media/rc/streamzap.c @@ -191,7 +191,7 @@ static void sz_push_half_space(struct streamzap_ir *sz, sz_push_full_space(sz, value & SZ_SPACE_MASK); } -/** +/* * streamzap_callback - usb IRQ handler callback * * This procedure is invoked on reception of data from @@ -321,7 +321,7 @@ static struct rc_dev *streamzap_init_rc_dev(struct streamzap_ir *sz) return NULL; } -/** +/* * streamzap_probe * * Called by usb-core to associated with a candidate device @@ -450,7 +450,7 @@ static int streamzap_probe(struct usb_interface *intf, return retval; } -/** +/* * streamzap_disconnect * * Called by the usb core when the device is removed from the system. diff --git a/drivers/media/usb/dvb-usb/cinergyT2-fe.c b/drivers/media/usb/dvb-usb/cinergyT2-fe.c index f9772ad0a2a5..5a2f81311fb7 100644 --- a/drivers/media/usb/dvb-usb/cinergyT2-fe.c +++ b/drivers/media/usb/dvb-usb/cinergyT2-fe.c @@ -26,7 +26,7 @@ #include "cinergyT2.h" -/** +/* * convert linux-dvb frontend parameter set into TPS. * See ETSI ETS-300744, section 4.6.2, table 9 for details. * diff --git a/drivers/media/usb/dvb-usb/dib0700_devices.c b/drivers/media/usb/dvb-usb/dib0700_devices.c index 92098c1b78e5..366b05529915 100644 --- a/drivers/media/usb/dvb-usb/dib0700_devices.c +++ b/drivers/media/usb/dvb-usb/dib0700_devices.c @@ -1677,10 +1677,10 @@ static int dib8096_set_param_override(struct dvb_frontend *fe) return -EINVAL; } - /** Update PLL if needed ratio **/ + /* Update PLL if needed ratio */ state->dib8000_ops.update_pll(fe, &dib8090_pll_config_12mhz, fe->dtv_property_cache.bandwidth_hz / 1000, 0); - /** Get optimize PLL ratio to remove spurious **/ + /* Get optimize PLL ratio to remove spurious */ pll_ratio = dib8090_compute_pll_parameters(fe); if (pll_ratio == 17) timf = 21387946; @@ -1691,7 +1691,7 @@ static int dib8096_set_param_override(struct dvb_frontend *fe) else timf = 18179756; - /** Update ratio **/ + /* Update ratio */ state->dib8000_ops.update_pll(fe, &dib8090_pll_config_12mhz, fe->dtv_property_cache.bandwidth_hz / 1000, pll_ratio); state->dib8000_ops.ctrl_timf(fe, DEMOD_TIMF_SET, timf); @@ -3357,7 +3357,7 @@ static int novatd_sleep_override(struct dvb_frontend* fe) return state->sleep(fe); } -/** +/* * novatd_frontend_attach - Nova-TD specific attach * * Nova-TD has GPIO0, 1 and 2 for LEDs. So do not fiddle with them except for diff --git a/drivers/media/usb/dvb-usb/friio-fe.c b/drivers/media/usb/dvb-usb/friio-fe.c index 41261317bd5c..b6046e0e07f6 100644 --- a/drivers/media/usb/dvb-usb/friio-fe.c +++ b/drivers/media/usb/dvb-usb/friio-fe.c @@ -297,7 +297,7 @@ static int jdvbt90502_set_frontend(struct dvb_frontend *fe) } -/** +/* * (reg, val) commad list to initialize this module. * captured on a Windows box. */ diff --git a/drivers/media/usb/dvb-usb/friio.c b/drivers/media/usb/dvb-usb/friio.c index 62abe6c43a32..16875945e662 100644 --- a/drivers/media/usb/dvb-usb/friio.c +++ b/drivers/media/usb/dvb-usb/friio.c @@ -21,7 +21,7 @@ MODULE_PARM_DESC(debug, DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); -/** +/* * Indirect I2C access to the PLL via FE. * whole I2C protocol data to the PLL is sent via the FE's I2C register. * This is done by a control msg to the FE with the I2C data accompanied, and diff --git a/drivers/media/usb/gspca/ov519.c b/drivers/media/usb/gspca/ov519.c index f1537daf4e2e..1b30434b72ef 100644 --- a/drivers/media/usb/gspca/ov519.c +++ b/drivers/media/usb/gspca/ov519.c @@ -1,4 +1,4 @@ -/** +/* * OV519 driver * * Copyright (C) 2008-2011 Jean-François Moine diff --git a/drivers/media/usb/pwc/pwc-dec23.c b/drivers/media/usb/pwc/pwc-dec23.c index 3792fedff951..1283b3bd9800 100644 --- a/drivers/media/usb/pwc/pwc-dec23.c +++ b/drivers/media/usb/pwc/pwc-dec23.c @@ -649,11 +649,10 @@ static void DecompressBand23(struct pwc_dec23_private *pdec, } /** - * * Uncompress a pwc23 buffer. - * - * src: raw data - * dst: image output + * @pdev: pointer to pwc device's internal struct + * @src: raw data + * @dst: image output */ void pwc_dec23_decompress(struct pwc_device *pdev, const void *src, diff --git a/drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c b/drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c index b842f367249f..a142b9dc0feb 100644 --- a/drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c +++ b/drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c @@ -76,7 +76,7 @@ DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); #define TTUSB_REV_2_2 0x22 #define TTUSB_BUDGET_NAME "ttusb_stc_fw" -/** +/* * since we're casting (struct ttusb*) <-> (struct dvb_demux*) around * the dvb_demux field must be the first in struct!! */ @@ -713,7 +713,7 @@ static void ttusb_process_frame(struct ttusb *ttusb, u8 * data, int len) } } - /** + /* * if length is valid and we reached the end: * goto next muxpack */ @@ -729,7 +729,7 @@ static void ttusb_process_frame(struct ttusb *ttusb, u8 * data, int len) /* maximum bytes, until we know the length */ ttusb->muxpack_len = 2; - /** + /* * no muxpacks left? * return to search-sync state */ -- GitLab From b95b0c98f52883f9b907836f3421341af6f0145f Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 12:39:19 -0500 Subject: [PATCH 0347/2547] media: dvb_frontends: fix kernel-doc macros Now, the Kernel checks for kernel_doc format issues. Weird enough, it didn't get any of those troubles. Shssst! Well, let's fix it, as a preventive way to avoid having hundreds of new warnings on some next Linux version. Tested by adding all files under dvb-frontends that have "/**" on them. Signed-off-by: Mauro Carvalho Chehab --- .../media/dvb-frontends/drx39xyj/bsp_i2c.h | 12 +- .../media/dvb-frontends/drx39xyj/drx_driver.h | 878 +++++++++--------- drivers/media/dvb-frontends/drx39xyj/drxj.h | 220 ++--- drivers/media/dvb-frontends/drxk.h | 5 +- drivers/media/dvb-frontends/dvb-pll.h | 11 +- drivers/media/dvb-frontends/helene.h | 1 + drivers/media/dvb-frontends/ix2505v.h | 17 +- drivers/media/dvb-frontends/l64781.c | 2 +- drivers/media/dvb-frontends/mn88472.h | 16 +- drivers/media/dvb-frontends/rtl2832_sdr.h | 6 +- drivers/media/dvb-frontends/stb6000.h | 9 +- drivers/media/dvb-frontends/stv0299.c | 2 +- drivers/media/dvb-frontends/tda826x.h | 11 +- drivers/media/dvb-frontends/tua6100.h | 2 +- drivers/media/dvb-frontends/zd1301_demod.h | 7 +- drivers/media/dvb-frontends/zl10036.h | 16 +- 16 files changed, 607 insertions(+), 608 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h index 5b5421f70388..2b3af247a1f1 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -52,7 +52,7 @@ struct i2c_device_addr { }; -/** +/* * \def IS_I2C_10BIT( addr ) * \brief Determine if I2C address 'addr' is a 10 bits address or not. * \param addr The I2C address. @@ -67,7 +67,7 @@ struct i2c_device_addr { Exported FUNCTIONS ------------------------------------------------------------------------------*/ -/** +/* * \fn drxbsp_i2c_init() * \brief Initialize I2C communication module. * \return drx_status_t Return status. @@ -76,7 +76,7 @@ Exported FUNCTIONS */ drx_status_t drxbsp_i2c_init(void); -/** +/* * \fn drxbsp_i2c_term() * \brief Terminate I2C communication module. * \return drx_status_t Return status. @@ -85,7 +85,7 @@ Exported FUNCTIONS */ drx_status_t drxbsp_i2c_term(void); -/** +/* * \fn drx_status_t drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, * u16 w_count, * u8 *wData, @@ -121,7 +121,7 @@ Exported FUNCTIONS struct i2c_device_addr *r_dev_addr, u16 r_count, u8 *r_data); -/** +/* * \fn drxbsp_i2c_error_text() * \brief Returns a human readable error. * Counter part of numerical drx_i2c_error_g. @@ -130,7 +130,7 @@ Exported FUNCTIONS */ char *drxbsp_i2c_error_text(void); -/** +/* * \var drx_i2c_error_g; * \brief I2C specific error codes, platform dependent. */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index cd69e187ba7a..855685b6b386 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -46,7 +46,7 @@ struct i2c_device_addr { void *user_data; /* User data pointer */ }; -/** +/* * \def IS_I2C_10BIT( addr ) * \brief Determine if I2C address 'addr' is a 10 bits address or not. * \param addr The I2C address. @@ -61,7 +61,7 @@ struct i2c_device_addr { Exported FUNCTIONS ------------------------------------------------------------------------------*/ -/** +/* * \fn drxbsp_i2c_init() * \brief Initialize I2C communication module. * \return int Return status. @@ -70,7 +70,7 @@ Exported FUNCTIONS */ int drxbsp_i2c_init(void); -/** +/* * \fn drxbsp_i2c_term() * \brief Terminate I2C communication module. * \return int Return status. @@ -79,7 +79,7 @@ int drxbsp_i2c_init(void); */ int drxbsp_i2c_term(void); -/** +/* * \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, * u16 w_count, * u8 * wData, @@ -115,7 +115,7 @@ int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, struct i2c_device_addr *r_dev_addr, u16 r_count, u8 *r_data); -/** +/* * \fn drxbsp_i2c_error_text() * \brief Returns a human readable error. * Counter part of numerical drx_i2c_error_g. @@ -124,7 +124,7 @@ int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, */ char *drxbsp_i2c_error_text(void); -/** +/* * \var drx_i2c_error_g; * \brief I2C specific error codes, platform dependent. */ @@ -241,13 +241,13 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, struct i2c_device_addr *r_dev_addr, u16 r_count, u8 *r_data); -/************** +/************* * * This section configures the DRX Data Access Protocols (DAPs). * **************/ -/** +/* * \def DRXDAP_SINGLE_MASTER * \brief Enable I2C single or I2C multimaster mode on host. * @@ -262,7 +262,7 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, #define DRXDAP_SINGLE_MASTER 1 #endif -/** +/* * \def DRXDAP_MAX_WCHUNKSIZE * \brief Defines maximum chunksize of an i2c write action by host. * @@ -282,7 +282,7 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, #define DRXDAP_MAX_WCHUNKSIZE 60 #endif -/** +/* * \def DRXDAP_MAX_RCHUNKSIZE * \brief Defines maximum chunksize of an i2c read action by host. * @@ -297,13 +297,13 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, #define DRXDAP_MAX_RCHUNKSIZE 60 #endif -/************** +/************* * * This section describes drxdriver defines. * **************/ -/** +/* * \def DRX_UNKNOWN * \brief Generic UNKNOWN value for DRX enumerated types. * @@ -313,7 +313,7 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, #define DRX_UNKNOWN (254) #endif -/** +/* * \def DRX_AUTO * \brief Generic AUTO value for DRX enumerated types. * @@ -324,104 +324,104 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, #define DRX_AUTO (255) #endif -/************** +/************* * * This section describes flag definitions for the device capbilities. * **************/ -/** +/* * \brief LNA capability flag * * Device has a Low Noise Amplifier * */ #define DRX_CAPABILITY_HAS_LNA (1UL << 0) -/** +/* * \brief OOB-RX capability flag * * Device has OOB-RX * */ #define DRX_CAPABILITY_HAS_OOBRX (1UL << 1) -/** +/* * \brief ATV capability flag * * Device has ATV * */ #define DRX_CAPABILITY_HAS_ATV (1UL << 2) -/** +/* * \brief DVB-T capability flag * * Device has DVB-T * */ #define DRX_CAPABILITY_HAS_DVBT (1UL << 3) -/** +/* * \brief ITU-B capability flag * * Device has ITU-B * */ #define DRX_CAPABILITY_HAS_ITUB (1UL << 4) -/** +/* * \brief Audio capability flag * * Device has Audio * */ #define DRX_CAPABILITY_HAS_AUD (1UL << 5) -/** +/* * \brief SAW switch capability flag * * Device has SAW switch * */ #define DRX_CAPABILITY_HAS_SAWSW (1UL << 6) -/** +/* * \brief GPIO1 capability flag * * Device has GPIO1 * */ #define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7) -/** +/* * \brief GPIO2 capability flag * * Device has GPIO2 * */ #define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8) -/** +/* * \brief IRQN capability flag * * Device has IRQN * */ #define DRX_CAPABILITY_HAS_IRQN (1UL << 9) -/** +/* * \brief 8VSB capability flag * * Device has 8VSB * */ #define DRX_CAPABILITY_HAS_8VSB (1UL << 10) -/** +/* * \brief SMA-TX capability flag * * Device has SMATX * */ #define DRX_CAPABILITY_HAS_SMATX (1UL << 11) -/** +/* * \brief SMA-RX capability flag * * Device has SMARX * */ #define DRX_CAPABILITY_HAS_SMARX (1UL << 12) -/** +/* * \brief ITU-A/C capability flag * * Device has ITU-A/C @@ -439,7 +439,7 @@ MACROS DRX_VERSIONSTRING_HELP(PATCH) #define DRX_VERSIONSTRING_HELP(NUM) #NUM -/** +/* * \brief Macro to create byte array elements from 16 bit integers. * This macro is used to create byte arrays for block writes. * Block writes speed up I2C traffic between host and demod. @@ -449,7 +449,7 @@ MACROS #define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ ((u8)((((u16)x)>>8)&0xFF)) -/** +/* * \brief Macro to convert 16 bit register value to a s32 */ #define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \ @@ -461,191 +461,191 @@ MACROS ENUM -------------------------------------------------------------------------*/ -/** +/* * \enum enum drx_standard * \brief Modulation standards. */ enum drx_standard { - DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */ - DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */ - DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */ + DRX_STANDARD_DVBT = 0, /*< Terrestrial DVB-T. */ + DRX_STANDARD_8VSB, /*< Terrestrial 8VSB. */ + DRX_STANDARD_NTSC, /*< Terrestrial\Cable analog NTSC. */ DRX_STANDARD_PAL_SECAM_BG, - /**< Terrestrial analog PAL/SECAM B/G */ + /*< Terrestrial analog PAL/SECAM B/G */ DRX_STANDARD_PAL_SECAM_DK, - /**< Terrestrial analog PAL/SECAM D/K */ + /*< Terrestrial analog PAL/SECAM D/K */ DRX_STANDARD_PAL_SECAM_I, - /**< Terrestrial analog PAL/SECAM I */ + /*< Terrestrial analog PAL/SECAM I */ DRX_STANDARD_PAL_SECAM_L, - /**< Terrestrial analog PAL/SECAM L + /*< Terrestrial analog PAL/SECAM L with negative modulation */ DRX_STANDARD_PAL_SECAM_LP, - /**< Terrestrial analog PAL/SECAM L + /*< Terrestrial analog PAL/SECAM L with positive modulation */ - DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */ - DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */ - DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */ - DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */ - DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */ - DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/ + DRX_STANDARD_ITU_A, /*< Cable ITU ANNEX A. */ + DRX_STANDARD_ITU_B, /*< Cable ITU ANNEX B. */ + DRX_STANDARD_ITU_C, /*< Cable ITU ANNEX C. */ + DRX_STANDARD_ITU_D, /*< Cable ITU ANNEX D. */ + DRX_STANDARD_FM, /*< Terrestrial\Cable FM radio */ + DRX_STANDARD_DTMB, /*< Terrestrial DTMB standard (China)*/ DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, - /**< Standard unknown. */ + /*< Standard unknown. */ DRX_STANDARD_AUTO = DRX_AUTO - /**< Autodetect standard. */ + /*< Autodetect standard. */ }; -/** +/* * \enum enum drx_standard * \brief Modulation sub-standards. */ enum drx_substandard { - DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */ + DRX_SUBSTANDARD_MAIN = 0, /*< Main subvariant of standard */ DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, DRX_SUBSTANDARD_ATV_DK_POLAND, DRX_SUBSTANDARD_ATV_DK_CHINA, DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, - /**< Sub-standard unknown. */ + /*< Sub-standard unknown. */ DRX_SUBSTANDARD_AUTO = DRX_AUTO - /**< Auto (default) sub-standard */ + /*< Auto (default) sub-standard */ }; -/** +/* * \enum enum drx_bandwidth * \brief Channel bandwidth or channel spacing. */ enum drx_bandwidth { - DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */ - DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */ - DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */ + DRX_BANDWIDTH_8MHZ = 0, /*< Bandwidth 8 MHz. */ + DRX_BANDWIDTH_7MHZ, /*< Bandwidth 7 MHz. */ + DRX_BANDWIDTH_6MHZ, /*< Bandwidth 6 MHz. */ DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, - /**< Bandwidth unknown. */ + /*< Bandwidth unknown. */ DRX_BANDWIDTH_AUTO = DRX_AUTO - /**< Auto Set Bandwidth */ + /*< Auto Set Bandwidth */ }; -/** +/* * \enum enum drx_mirror * \brief Indicate if channel spectrum is mirrored or not. */ enum drx_mirror { - DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ - DRX_MIRROR_YES, /**< Spectrum is mirrored. */ + DRX_MIRROR_NO = 0, /*< Spectrum is not mirrored. */ + DRX_MIRROR_YES, /*< Spectrum is mirrored. */ DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, - /**< Unknown if spectrum is mirrored. */ + /*< Unknown if spectrum is mirrored. */ DRX_MIRROR_AUTO = DRX_AUTO - /**< Autodetect if spectrum is mirrored. */ + /*< Autodetect if spectrum is mirrored. */ }; -/** +/* * \enum enum drx_modulation * \brief Constellation type of the channel. */ enum drx_modulation { - DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */ - DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */ - DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */ - DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */ - DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */ - DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */ - DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */ - DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */ - DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */ - DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */ - DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */ + DRX_CONSTELLATION_BPSK = 0, /*< Modulation is BPSK. */ + DRX_CONSTELLATION_QPSK, /*< Constellation is QPSK. */ + DRX_CONSTELLATION_PSK8, /*< Constellation is PSK8. */ + DRX_CONSTELLATION_QAM16, /*< Constellation is QAM16. */ + DRX_CONSTELLATION_QAM32, /*< Constellation is QAM32. */ + DRX_CONSTELLATION_QAM64, /*< Constellation is QAM64. */ + DRX_CONSTELLATION_QAM128, /*< Constellation is QAM128. */ + DRX_CONSTELLATION_QAM256, /*< Constellation is QAM256. */ + DRX_CONSTELLATION_QAM512, /*< Constellation is QAM512. */ + DRX_CONSTELLATION_QAM1024, /*< Constellation is QAM1024. */ + DRX_CONSTELLATION_QPSK_NR, /*< Constellation is QPSK_NR */ DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, - /**< Constellation unknown. */ + /*< Constellation unknown. */ DRX_CONSTELLATION_AUTO = DRX_AUTO - /**< Autodetect constellation. */ + /*< Autodetect constellation. */ }; -/** +/* * \enum enum drx_hierarchy * \brief Hierarchy of the channel. */ enum drx_hierarchy { - DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */ - DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */ - DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */ - DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */ + DRX_HIERARCHY_NONE = 0, /*< None hierarchical channel. */ + DRX_HIERARCHY_ALPHA1, /*< Hierarchical channel, alpha=1. */ + DRX_HIERARCHY_ALPHA2, /*< Hierarchical channel, alpha=2. */ + DRX_HIERARCHY_ALPHA4, /*< Hierarchical channel, alpha=4. */ DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, - /**< Hierarchy unknown. */ + /*< Hierarchy unknown. */ DRX_HIERARCHY_AUTO = DRX_AUTO - /**< Autodetect hierarchy. */ + /*< Autodetect hierarchy. */ }; -/** +/* * \enum enum drx_priority * \brief Channel priority in case of hierarchical transmission. */ enum drx_priority { - DRX_PRIORITY_LOW = 0, /**< Low priority channel. */ - DRX_PRIORITY_HIGH, /**< High priority channel. */ + DRX_PRIORITY_LOW = 0, /*< Low priority channel. */ + DRX_PRIORITY_HIGH, /*< High priority channel. */ DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN - /**< Priority unknown. */ + /*< Priority unknown. */ }; -/** +/* * \enum enum drx_coderate * \brief Channel priority in case of hierarchical transmission. */ enum drx_coderate { - DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */ - DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */ - DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */ - DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */ - DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */ + DRX_CODERATE_1DIV2 = 0, /*< Code rate 1/2nd. */ + DRX_CODERATE_2DIV3, /*< Code rate 2/3nd. */ + DRX_CODERATE_3DIV4, /*< Code rate 3/4nd. */ + DRX_CODERATE_5DIV6, /*< Code rate 5/6nd. */ + DRX_CODERATE_7DIV8, /*< Code rate 7/8nd. */ DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, - /**< Code rate unknown. */ + /*< Code rate unknown. */ DRX_CODERATE_AUTO = DRX_AUTO - /**< Autodetect code rate. */ + /*< Autodetect code rate. */ }; -/** +/* * \enum enum drx_guard * \brief Guard interval of a channel. */ enum drx_guard { - DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */ - DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */ - DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */ - DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */ + DRX_GUARD_1DIV32 = 0, /*< Guard interval 1/32nd. */ + DRX_GUARD_1DIV16, /*< Guard interval 1/16th. */ + DRX_GUARD_1DIV8, /*< Guard interval 1/8th. */ + DRX_GUARD_1DIV4, /*< Guard interval 1/4th. */ DRX_GUARD_UNKNOWN = DRX_UNKNOWN, - /**< Guard interval unknown. */ + /*< Guard interval unknown. */ DRX_GUARD_AUTO = DRX_AUTO - /**< Autodetect guard interval. */ + /*< Autodetect guard interval. */ }; -/** +/* * \enum enum drx_fft_mode * \brief FFT mode. */ enum drx_fft_mode { - DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */ - DRX_FFTMODE_4K, /**< 4K FFT mode. */ - DRX_FFTMODE_8K, /**< 8K FFT mode. */ + DRX_FFTMODE_2K = 0, /*< 2K FFT mode. */ + DRX_FFTMODE_4K, /*< 4K FFT mode. */ + DRX_FFTMODE_8K, /*< 8K FFT mode. */ DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, - /**< FFT mode unknown. */ + /*< FFT mode unknown. */ DRX_FFTMODE_AUTO = DRX_AUTO - /**< Autodetect FFT mode. */ + /*< Autodetect FFT mode. */ }; -/** +/* * \enum enum drx_classification * \brief Channel classification. */ enum drx_classification { - DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */ - DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */ - DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */ - DRX_CLASSIFICATION_STATIC, /**< Static echo. */ - DRX_CLASSIFICATION_MOVING, /**< Moving echo. */ - DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */ + DRX_CLASSIFICATION_GAUSS = 0, /*< Gaussion noise. */ + DRX_CLASSIFICATION_HVY_GAUSS, /*< Heavy Gaussion noise. */ + DRX_CLASSIFICATION_COCHANNEL, /*< Co-channel. */ + DRX_CLASSIFICATION_STATIC, /*< Static echo. */ + DRX_CLASSIFICATION_MOVING, /*< Moving echo. */ + DRX_CLASSIFICATION_ZERODB, /*< Zero dB echo. */ DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, - /**< Unknown classification */ + /*< Unknown classification */ DRX_CLASSIFICATION_AUTO = DRX_AUTO - /**< Autodetect classification. */ + /*< Autodetect classification. */ }; -/** +/* * /enum enum drx_interleave_mode * /brief Interleave modes */ @@ -673,80 +673,80 @@ enum drx_interleave_mode { DRX_INTERLEAVEMODE_B52_M48, DRX_INTERLEAVEMODE_B52_M0, DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, - /**< Unknown interleave mode */ + /*< Unknown interleave mode */ DRX_INTERLEAVEMODE_AUTO = DRX_AUTO - /**< Autodetect interleave mode */ + /*< Autodetect interleave mode */ }; -/** +/* * \enum enum drx_carrier_mode * \brief Channel Carrier Mode. */ enum drx_carrier_mode { - DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ - DRX_CARRIER_SINGLE, /**< Single carrier mode */ + DRX_CARRIER_MULTI = 0, /*< Multi carrier mode */ + DRX_CARRIER_SINGLE, /*< Single carrier mode */ DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, - /**< Carrier mode unknown. */ - DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */ + /*< Carrier mode unknown. */ + DRX_CARRIER_AUTO = DRX_AUTO /*< Autodetect carrier mode */ }; -/** +/* * \enum enum drx_frame_mode * \brief Channel Frame Mode. */ enum drx_frame_mode { - DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ - DRX_FRAMEMODE_595, /**< 595 */ - DRX_FRAMEMODE_945, /**< 945 with variable PN */ + DRX_FRAMEMODE_420 = 0, /*< 420 with variable PN */ + DRX_FRAMEMODE_595, /*< 595 */ + DRX_FRAMEMODE_945, /*< 945 with variable PN */ DRX_FRAMEMODE_420_FIXED_PN, - /**< 420 with fixed PN */ + /*< 420 with fixed PN */ DRX_FRAMEMODE_945_FIXED_PN, - /**< 945 with fixed PN */ + /*< 945 with fixed PN */ DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, - /**< Frame mode unknown. */ + /*< Frame mode unknown. */ DRX_FRAMEMODE_AUTO = DRX_AUTO - /**< Autodetect frame mode */ + /*< Autodetect frame mode */ }; -/** +/* * \enum enum drx_tps_frame * \brief Frame number in current super-frame. */ enum drx_tps_frame { - DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ - DRX_TPS_FRAME2, /**< TPS frame 2. */ - DRX_TPS_FRAME3, /**< TPS frame 3. */ - DRX_TPS_FRAME4, /**< TPS frame 4. */ + DRX_TPS_FRAME1 = 0, /*< TPS frame 1. */ + DRX_TPS_FRAME2, /*< TPS frame 2. */ + DRX_TPS_FRAME3, /*< TPS frame 3. */ + DRX_TPS_FRAME4, /*< TPS frame 4. */ DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN - /**< TPS frame unknown. */ + /*< TPS frame unknown. */ }; -/** +/* * \enum enum drx_ldpc * \brief TPS LDPC . */ enum drx_ldpc { - DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ - DRX_LDPC_0_6, /**< LDPC 0.6 */ - DRX_LDPC_0_8, /**< LDPC 0.8 */ + DRX_LDPC_0_4 = 0, /*< LDPC 0.4 */ + DRX_LDPC_0_6, /*< LDPC 0.6 */ + DRX_LDPC_0_8, /*< LDPC 0.8 */ DRX_LDPC_UNKNOWN = DRX_UNKNOWN, - /**< LDPC unknown. */ - DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */ + /*< LDPC unknown. */ + DRX_LDPC_AUTO = DRX_AUTO /*< Autodetect LDPC */ }; -/** +/* * \enum enum drx_pilot_mode * \brief Pilot modes in DTMB. */ enum drx_pilot_mode { - DRX_PILOT_ON = 0, /**< Pilot On */ - DRX_PILOT_OFF, /**< Pilot Off */ + DRX_PILOT_ON = 0, /*< Pilot On */ + DRX_PILOT_OFF, /*< Pilot Off */ DRX_PILOT_UNKNOWN = DRX_UNKNOWN, - /**< Pilot unknown. */ - DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ + /*< Pilot unknown. */ + DRX_PILOT_AUTO = DRX_AUTO /*< Autodetect Pilot */ }; -/** +/* * enum drxu_code_action - indicate if firmware has to be uploaded or verified. * @UCODE_UPLOAD: Upload the microcode image to device * @UCODE_VERIFY: Compare microcode image with code on device @@ -756,7 +756,7 @@ enum drxu_code_action { UCODE_VERIFY }; -/** +/* * \enum enum drx_lock_status * \brief Used to reflect current lock status of demodulator. * * The generic lock states have device dependent semantics. @@ -801,7 +801,7 @@ enum drx_lock_status { DRX_LOCKED }; -/** +/* * \enum enum drx_uio* \brief Used to address a User IO (UIO). */ enum drx_uio { @@ -840,7 +840,7 @@ enum drx_uio { DRX_UIO_MAX = DRX_UIO32 }; -/** +/* * \enum enum drxuio_mode * \brief Used to configure the modus oprandi of a UIO. * * DRX_UIO_MODE_FIRMWARE is an old uio mode. @@ -850,37 +850,37 @@ enum drx_uio { */ enum drxuio_mode { DRX_UIO_MODE_DISABLE = 0x01, - /**< not used, pin is configured as input */ + /*< not used, pin is configured as input */ DRX_UIO_MODE_READWRITE = 0x02, - /**< used for read/write by application */ + /*< used for read/write by application */ DRX_UIO_MODE_FIRMWARE = 0x04, - /**< controlled by firmware, function 0 */ + /*< controlled by firmware, function 0 */ DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE, - /**< same as above */ + /*< same as above */ DRX_UIO_MODE_FIRMWARE1 = 0x08, - /**< controlled by firmware, function 1 */ + /*< controlled by firmware, function 1 */ DRX_UIO_MODE_FIRMWARE2 = 0x10, - /**< controlled by firmware, function 2 */ + /*< controlled by firmware, function 2 */ DRX_UIO_MODE_FIRMWARE3 = 0x20, - /**< controlled by firmware, function 3 */ + /*< controlled by firmware, function 3 */ DRX_UIO_MODE_FIRMWARE4 = 0x40, - /**< controlled by firmware, function 4 */ + /*< controlled by firmware, function 4 */ DRX_UIO_MODE_FIRMWARE5 = 0x80 - /**< controlled by firmware, function 5 */ + /*< controlled by firmware, function 5 */ }; -/** +/* * \enum enum drxoob_downstream_standard * \brief Used to select OOB standard. * * Based on ANSI 55-1 and 55-2 */ enum drxoob_downstream_standard { DRX_OOB_MODE_A = 0, - /**< ANSI 55-1 */ + /*< ANSI 55-1 */ DRX_OOB_MODE_B_GRADE_A, - /**< ANSI 55-2 A */ + /*< ANSI 55-2 A */ DRX_OOB_MODE_B_GRADE_B - /**< ANSI 55-2 B */ + /*< ANSI 55-2 B */ }; /*------------------------------------------------------------------------- @@ -924,7 +924,7 @@ STRUCTS /*============================================================================*/ /*============================================================================*/ -/** +/* * struct drxu_code_info Parameters for microcode upload and verfiy. * * @mc_file: microcode file name @@ -935,7 +935,7 @@ struct drxu_code_info { char *mc_file; }; -/** +/* * \struct drx_mc_version_rec_t * \brief Microcode version record * Version numbers are stored in BCD format, as usual: @@ -963,7 +963,7 @@ struct drx_mc_version_rec { /*========================================*/ -/** +/* * \struct drx_filter_info_t * \brief Parameters for loading filter coefficients * @@ -971,18 +971,18 @@ struct drx_mc_version_rec { */ struct drx_filter_info { u8 *data_re; - /**< pointer to coefficients for RE */ + /*< pointer to coefficients for RE */ u8 *data_im; - /**< pointer to coefficients for IM */ + /*< pointer to coefficients for IM */ u16 size_re; - /**< size of coefficients for RE */ + /*< size of coefficients for RE */ u16 size_im; - /**< size of coefficients for IM */ + /*< size of coefficients for IM */ }; /*========================================*/ -/** +/* * \struct struct drx_channel * \brief The set of parameters describing a single channel. * * Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. @@ -991,29 +991,29 @@ struct drx_filter_info { */ struct drx_channel { s32 frequency; - /**< frequency in kHz */ + /*< frequency in kHz */ enum drx_bandwidth bandwidth; - /**< bandwidth */ - enum drx_mirror mirror; /**< mirrored or not on RF */ + /*< bandwidth */ + enum drx_mirror mirror; /*< mirrored or not on RF */ enum drx_modulation constellation; - /**< constellation */ + /*< constellation */ enum drx_hierarchy hierarchy; - /**< hierarchy */ - enum drx_priority priority; /**< priority */ - enum drx_coderate coderate; /**< coderate */ - enum drx_guard guard; /**< guard interval */ - enum drx_fft_mode fftmode; /**< fftmode */ + /*< hierarchy */ + enum drx_priority priority; /*< priority */ + enum drx_coderate coderate; /*< coderate */ + enum drx_guard guard; /*< guard interval */ + enum drx_fft_mode fftmode; /*< fftmode */ enum drx_classification classification; - /**< classification */ + /*< classification */ u32 symbolrate; - /**< symbolrate in symbols/sec */ + /*< symbolrate in symbols/sec */ enum drx_interleave_mode interleavemode; - /**< interleaveMode QAM */ - enum drx_ldpc ldpc; /**< ldpc */ - enum drx_carrier_mode carrier; /**< carrier */ + /*< interleaveMode QAM */ + enum drx_ldpc ldpc; /*< ldpc */ + enum drx_carrier_mode carrier; /*< carrier */ enum drx_frame_mode framemode; - /**< frame mode */ - enum drx_pilot_mode pilot; /**< pilot mode */ + /*< frame mode */ + enum drx_pilot_mode pilot; /*< pilot mode */ }; /*========================================*/ @@ -1027,74 +1027,74 @@ enum drx_cfg_sqi_speed { /*========================================*/ -/** +/* * \struct struct drx_complex * A complex number. * * Used by DRX_CTRL_CONSTEL. */ struct drx_complex { s16 im; - /**< Imaginary part. */ + /*< Imaginary part. */ s16 re; - /**< Real part. */ + /*< Real part. */ }; /*========================================*/ -/** +/* * \struct struct drx_frequency_plan * Array element of a frequency plan. * * Used by DRX_CTRL_SCAN_INIT. */ struct drx_frequency_plan { s32 first; - /**< First centre frequency in this band */ + /*< First centre frequency in this band */ s32 last; - /**< Last centre frequency in this band */ + /*< Last centre frequency in this band */ s32 step; - /**< Stepping frequency in this band */ + /*< Stepping frequency in this band */ enum drx_bandwidth bandwidth; - /**< Bandwidth within this frequency band */ + /*< Bandwidth within this frequency band */ u16 ch_number; - /**< First channel number in this band, or first + /*< First channel number in this band, or first index in ch_names */ char **ch_names; - /**< Optional list of channel names in this + /*< Optional list of channel names in this band */ }; /*========================================*/ -/** +/* * \struct struct drx_scan_param * Parameters for channel scan. * * Used by DRX_CTRL_SCAN_INIT. */ struct drx_scan_param { struct drx_frequency_plan *frequency_plan; - /**< Frequency plan (array)*/ - u16 frequency_plan_size; /**< Number of bands */ - u32 num_tries; /**< Max channels tried */ - s32 skip; /**< Minimum frequency step to take + /*< Frequency plan (array)*/ + u16 frequency_plan_size; /*< Number of bands */ + u32 num_tries; /*< Max channels tried */ + s32 skip; /*< Minimum frequency step to take after a channel is found */ - void *ext_params; /**< Standard specific params */ + void *ext_params; /*< Standard specific params */ }; /*========================================*/ -/** +/* * \brief Scan commands. * Used by scanning algorithms. */ enum drx_scan_command { - DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */ - DRX_SCAN_COMMAND_NEXT, /**< Next scan */ - DRX_SCAN_COMMAND_STOP /**< Stop scanning */ + DRX_SCAN_COMMAND_INIT = 0,/*< Initialize scanning */ + DRX_SCAN_COMMAND_NEXT, /*< Next scan */ + DRX_SCAN_COMMAND_STOP /*< Stop scanning */ }; /*========================================*/ -/** +/* * \brief Inner scan function prototype. */ typedef int(*drx_scan_func_t) (void *scan_context, @@ -1104,77 +1104,77 @@ typedef int(*drx_scan_func_t) (void *scan_context, /*========================================*/ -/** +/* * \struct struct drxtps_info * TPS information, DVB-T specific. * * Used by DRX_CTRL_TPS_INFO. */ struct drxtps_info { - enum drx_fft_mode fftmode; /**< Fft mode */ - enum drx_guard guard; /**< Guard interval */ + enum drx_fft_mode fftmode; /*< Fft mode */ + enum drx_guard guard; /*< Guard interval */ enum drx_modulation constellation; - /**< Constellation */ + /*< Constellation */ enum drx_hierarchy hierarchy; - /**< Hierarchy */ + /*< Hierarchy */ enum drx_coderate high_coderate; - /**< High code rate */ + /*< High code rate */ enum drx_coderate low_coderate; - /**< Low cod rate */ - enum drx_tps_frame frame; /**< Tps frame */ - u8 length; /**< Length */ - u16 cell_id; /**< Cell id */ + /*< Low cod rate */ + enum drx_tps_frame frame; /*< Tps frame */ + u8 length; /*< Length */ + u16 cell_id; /*< Cell id */ }; /*========================================*/ -/** +/* * \brief Power mode of device. * * Used by DRX_CTRL_SET_POWER_MODE. */ enum drx_power_mode { DRX_POWER_UP = 0, - /**< Generic , Power Up Mode */ + /*< Generic , Power Up Mode */ DRX_POWER_MODE_1, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_2, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_3, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_4, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_5, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_6, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_7, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_8, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_9, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_10, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_11, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_12, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_13, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_14, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_15, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_16, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_DOWN = 255 - /**< Generic , Power Down Mode */ + /*< Generic , Power Down Mode */ }; /*========================================*/ -/** +/* * \enum enum drx_module * \brief Software module identification. * * Used by DRX_CTRL_VERSION. @@ -1191,93 +1191,93 @@ typedef int(*drx_scan_func_t) (void *scan_context, DRX_MODULE_UNKNOWN }; -/** +/* * \enum struct drx_version * \brief Version information of one software module. * * Used by DRX_CTRL_VERSION. */ struct drx_version { enum drx_module module_type; - /**< Type identifier of the module */ + /*< Type identifier of the module */ char *module_name; - /**< Name or description of module */ - u16 v_major; /**< Major version number */ - u16 v_minor; /**< Minor version number */ - u16 v_patch; /**< Patch version number */ - char *v_string; /**< Version as text string */ + /*< Name or description of module */ + u16 v_major; /*< Major version number */ + u16 v_minor; /*< Minor version number */ + u16 v_patch; /*< Patch version number */ + char *v_string; /*< Version as text string */ }; -/** +/* * \enum struct drx_version_list * \brief List element of NULL terminated, linked list for version information. * * Used by DRX_CTRL_VERSION. */ struct drx_version_list { - struct drx_version *version;/**< Version information */ + struct drx_version *version;/*< Version information */ struct drx_version_list *next; - /**< Next list element */ + /*< Next list element */ }; /*========================================*/ -/** +/* * \brief Parameters needed to confiugure a UIO. * * Used by DRX_CTRL_UIO_CFG. */ struct drxuio_cfg { enum drx_uio uio; - /**< UIO identifier */ + /*< UIO identifier */ enum drxuio_mode mode; - /**< UIO operational mode */ + /*< UIO operational mode */ }; /*========================================*/ -/** +/* * \brief Parameters needed to read from or write to a UIO. * * Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. */ struct drxuio_data { enum drx_uio uio; - /**< UIO identifier */ + /*< UIO identifier */ bool value; - /**< UIO value (true=1, false=0) */ + /*< UIO value (true=1, false=0) */ }; /*========================================*/ -/** +/* * \brief Parameters needed to configure OOB. * * Used by DRX_CTRL_SET_OOB. */ struct drxoob { - s32 frequency; /**< Frequency in kHz */ + s32 frequency; /*< Frequency in kHz */ enum drxoob_downstream_standard standard; - /**< OOB standard */ - bool spectrum_inverted; /**< If true, then spectrum + /*< OOB standard */ + bool spectrum_inverted; /*< If true, then spectrum is inverted */ }; /*========================================*/ -/** +/* * \brief Metrics from OOB. * * Used by DRX_CTRL_GET_OOB. */ struct drxoob_status { - s32 frequency; /**< Frequency in Khz */ - enum drx_lock_status lock; /**< Lock status */ - u32 mer; /**< MER */ - s32 symbol_rate_offset; /**< Symbolrate offset in ppm */ + s32 frequency; /*< Frequency in Khz */ + enum drx_lock_status lock; /*< Lock status */ + u32 mer; /*< MER */ + s32 symbol_rate_offset; /*< Symbolrate offset in ppm */ }; /*========================================*/ -/** +/* * \brief Device dependent configuration data. * * Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. @@ -1285,14 +1285,14 @@ struct drx_version_list { */ struct drx_cfg { u32 cfg_type; - /**< Function identifier */ + /*< Function identifier */ void *cfg_data; - /**< Function data */ + /*< Function data */ }; /*========================================*/ -/** +/* * /struct DRXMpegStartWidth_t * MStart width [nr MCLK cycles] for serial MPEG output. */ @@ -1303,7 +1303,7 @@ struct drx_version_list { }; /* CTRL CFG MPEG output */ -/** +/* * \struct struct drx_cfg_mpeg_output * \brief Configuration parameters for MPEG output control. * * Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and @@ -1311,29 +1311,29 @@ struct drx_version_list { */ struct drx_cfg_mpeg_output { - bool enable_mpeg_output;/**< If true, enable MPEG output */ - bool insert_rs_byte; /**< If true, insert RS byte */ - bool enable_parallel; /**< If true, parallel out otherwise + bool enable_mpeg_output;/*< If true, enable MPEG output */ + bool insert_rs_byte; /*< If true, insert RS byte */ + bool enable_parallel; /*< If true, parallel out otherwise serial */ - bool invert_data; /**< If true, invert DATA signals */ - bool invert_err; /**< If true, invert ERR signal */ - bool invert_str; /**< If true, invert STR signals */ - bool invert_val; /**< If true, invert VAL signals */ - bool invert_clk; /**< If true, invert CLK signals */ - bool static_clk; /**< If true, static MPEG clockrate + bool invert_data; /*< If true, invert DATA signals */ + bool invert_err; /*< If true, invert ERR signal */ + bool invert_str; /*< If true, invert STR signals */ + bool invert_val; /*< If true, invert VAL signals */ + bool invert_clk; /*< If true, invert CLK signals */ + bool static_clk; /*< If true, static MPEG clockrate will be used, otherwise clockrate will adapt to the bitrate of the TS */ - u32 bitrate; /**< Maximum bitrate in b/s in case + u32 bitrate; /*< Maximum bitrate in b/s in case static clockrate is selected */ enum drxmpeg_str_width width_str; - /**< MPEG start width */ + /*< MPEG start width */ }; /*========================================*/ -/** +/* * \struct struct drxi2c_data * \brief Data for I2C via 2nd or 3rd or etc I2C port. * * Used by DRX_CTRL_I2C_READWRITE. @@ -1341,187 +1341,187 @@ struct drx_version_list { * */ struct drxi2c_data { - u16 port_nr; /**< I2C port number */ + u16 port_nr; /*< I2C port number */ struct i2c_device_addr *w_dev_addr; - /**< Write device address */ - u16 w_count; /**< Size of write data in bytes */ - u8 *wData; /**< Pointer to write data */ + /*< Write device address */ + u16 w_count; /*< Size of write data in bytes */ + u8 *wData; /*< Pointer to write data */ struct i2c_device_addr *r_dev_addr; - /**< Read device address */ - u16 r_count; /**< Size of data to read in bytes */ - u8 *r_data; /**< Pointer to read buffer */ + /*< Read device address */ + u16 r_count; /*< Size of data to read in bytes */ + u8 *r_data; /*< Pointer to read buffer */ }; /*========================================*/ -/** +/* * \enum enum drx_aud_standard * \brief Audio standard identifier. * * Used by DRX_CTRL_SET_AUD. */ enum drx_aud_standard { - DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */ - DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */ - DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */ - DRX_AUD_STANDARD_FM_STEREO,/**< set to FM-Stereo Radio */ - DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */ - DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */ - DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */ - DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */ - DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */ - DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */ + DRX_AUD_STANDARD_BTSC, /*< set BTSC standard (USA) */ + DRX_AUD_STANDARD_A2, /*< set A2-Korea FM Stereo */ + DRX_AUD_STANDARD_EIAJ, /*< set to Japanese FM Stereo */ + DRX_AUD_STANDARD_FM_STEREO,/*< set to FM-Stereo Radio */ + DRX_AUD_STANDARD_M_MONO, /*< for 4.5 MHz mono detected */ + DRX_AUD_STANDARD_D_K_MONO, /*< for 6.5 MHz mono detected */ + DRX_AUD_STANDARD_BG_FM, /*< set BG_FM standard */ + DRX_AUD_STANDARD_D_K1, /*< set D_K1 standard */ + DRX_AUD_STANDARD_D_K2, /*< set D_K2 standard */ + DRX_AUD_STANDARD_D_K3, /*< set D_K3 standard */ DRX_AUD_STANDARD_BG_NICAM_FM, - /**< set BG_NICAM_FM standard */ + /*< set BG_NICAM_FM standard */ DRX_AUD_STANDARD_L_NICAM_AM, - /**< set L_NICAM_AM standard */ + /*< set L_NICAM_AM standard */ DRX_AUD_STANDARD_I_NICAM_FM, - /**< set I_NICAM_FM standard */ + /*< set I_NICAM_FM standard */ DRX_AUD_STANDARD_D_K_NICAM_FM, - /**< set D_K_NICAM_FM standard */ - DRX_AUD_STANDARD_NOT_READY,/**< used to detect audio standard */ + /*< set D_K_NICAM_FM standard */ + DRX_AUD_STANDARD_NOT_READY,/*< used to detect audio standard */ DRX_AUD_STANDARD_AUTO = DRX_AUTO, - /**< Automatic Standard Detection */ + /*< Automatic Standard Detection */ DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN - /**< used as auto and for readback */ + /*< used as auto and for readback */ }; /* CTRL_AUD_GET_STATUS - struct drx_aud_status */ -/** +/* * \enum enum drx_aud_nicam_status * \brief Status of NICAM carrier. */ enum drx_aud_nicam_status { DRX_AUD_NICAM_DETECTED = 0, - /**< NICAM carrier detected */ + /*< NICAM carrier detected */ DRX_AUD_NICAM_NOT_DETECTED, - /**< NICAM carrier not detected */ - DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */ + /*< NICAM carrier not detected */ + DRX_AUD_NICAM_BAD /*< NICAM carrier bad quality */ }; -/** +/* * \struct struct drx_aud_status * \brief Audio status characteristics. */ struct drx_aud_status { - bool stereo; /**< stereo detection */ - bool carrier_a; /**< carrier A detected */ - bool carrier_b; /**< carrier B detected */ - bool sap; /**< sap / bilingual detection */ - bool rds; /**< RDS data array present */ + bool stereo; /*< stereo detection */ + bool carrier_a; /*< carrier A detected */ + bool carrier_b; /*< carrier B detected */ + bool sap; /*< sap / bilingual detection */ + bool rds; /*< RDS data array present */ enum drx_aud_nicam_status nicam_status; - /**< status of NICAM carrier */ - s8 fm_ident; /**< FM Identification value */ + /*< status of NICAM carrier */ + s8 fm_ident; /*< FM Identification value */ }; /* CTRL_AUD_READ_RDS - DRXRDSdata_t */ -/** +/* * \struct DRXRDSdata_t * \brief Raw RDS data array. */ struct drx_cfg_aud_rds { - bool valid; /**< RDS data validation */ - u16 data[18]; /**< data from one RDS data array */ + bool valid; /*< RDS data validation */ + u16 data[18]; /*< data from one RDS data array */ }; /* DRX_CFG_AUD_VOLUME - struct drx_cfg_aud_volume - set/get */ -/** +/* * \enum DRXAudAVCDecayTime_t * \brief Automatic volume control configuration. */ enum drx_aud_avc_mode { - DRX_AUD_AVC_OFF, /**< Automatic volume control off */ - DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */ - DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */ - DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */ - DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */ + DRX_AUD_AVC_OFF, /*< Automatic volume control off */ + DRX_AUD_AVC_DECAYTIME_8S, /*< level volume in 8 seconds */ + DRX_AUD_AVC_DECAYTIME_4S, /*< level volume in 4 seconds */ + DRX_AUD_AVC_DECAYTIME_2S, /*< level volume in 2 seconds */ + DRX_AUD_AVC_DECAYTIME_20MS/*< level volume in 20 millisec */ }; -/** +/* * /enum DRXAudMaxAVCGain_t * /brief Automatic volume control max gain in audio baseband. */ enum drx_aud_avc_max_gain { - DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */ - DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */ - DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */ + DRX_AUD_AVC_MAX_GAIN_0DB, /*< maximum AVC gain 0 dB */ + DRX_AUD_AVC_MAX_GAIN_6DB, /*< maximum AVC gain 6 dB */ + DRX_AUD_AVC_MAX_GAIN_12DB /*< maximum AVC gain 12 dB */ }; -/** +/* * /enum DRXAudMaxAVCAtten_t * /brief Automatic volume control max attenuation in audio baseband. */ enum drx_aud_avc_max_atten { DRX_AUD_AVC_MAX_ATTEN_12DB, - /**< maximum AVC attenuation 12 dB */ + /*< maximum AVC attenuation 12 dB */ DRX_AUD_AVC_MAX_ATTEN_18DB, - /**< maximum AVC attenuation 18 dB */ - DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */ + /*< maximum AVC attenuation 18 dB */ + DRX_AUD_AVC_MAX_ATTEN_24DB/*< maximum AVC attenuation 24 dB */ }; -/** +/* * \struct struct drx_cfg_aud_volume * \brief Audio volume configuration. */ struct drx_cfg_aud_volume { - bool mute; /**< mute overrides volume setting */ - s16 volume; /**< volume, range -114 to 12 dB */ - enum drx_aud_avc_mode avc_mode; /**< AVC auto volume control mode */ - u16 avc_ref_level; /**< AVC reference level */ + bool mute; /*< mute overrides volume setting */ + s16 volume; /*< volume, range -114 to 12 dB */ + enum drx_aud_avc_mode avc_mode; /*< AVC auto volume control mode */ + u16 avc_ref_level; /*< AVC reference level */ enum drx_aud_avc_max_gain avc_max_gain; - /**< AVC max gain selection */ + /*< AVC max gain selection */ enum drx_aud_avc_max_atten avc_max_atten; - /**< AVC max attenuation selection */ - s16 strength_left; /**< quasi-peak, left speaker */ - s16 strength_right; /**< quasi-peak, right speaker */ + /*< AVC max attenuation selection */ + s16 strength_left; /*< quasi-peak, left speaker */ + s16 strength_right; /*< quasi-peak, right speaker */ }; /* DRX_CFG_I2S_OUTPUT - struct drx_cfg_i2s_output - set/get */ -/** +/* * \enum enum drxi2s_mode * \brief I2S output mode. */ enum drxi2s_mode { - DRX_I2S_MODE_MASTER, /**< I2S is in master mode */ - DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */ + DRX_I2S_MODE_MASTER, /*< I2S is in master mode */ + DRX_I2S_MODE_SLAVE /*< I2S is in slave mode */ }; -/** +/* * \enum enum drxi2s_word_length * \brief Width of I2S data. */ enum drxi2s_word_length { - DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */ - DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */ + DRX_I2S_WORDLENGTH_32 = 0,/*< I2S data is 32 bit wide */ + DRX_I2S_WORDLENGTH_16 = 1 /*< I2S data is 16 bit wide */ }; -/** +/* * \enum enum drxi2s_format * \brief Data wordstrobe alignment for I2S. */ enum drxi2s_format { DRX_I2S_FORMAT_WS_WITH_DATA, - /**< I2S data and wordstrobe are aligned */ + /*< I2S data and wordstrobe are aligned */ DRX_I2S_FORMAT_WS_ADVANCED - /**< I2S data one cycle after wordstrobe */ + /*< I2S data one cycle after wordstrobe */ }; -/** +/* * \enum enum drxi2s_polarity * \brief Polarity of I2S data. */ enum drxi2s_polarity { - DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */ - DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */ + DRX_I2S_POLARITY_RIGHT,/*< wordstrobe - right high, left low */ + DRX_I2S_POLARITY_LEFT /*< wordstrobe - right low, left high */ }; -/** +/* * \struct struct drx_cfg_i2s_output * \brief I2S output configuration. */ struct drx_cfg_i2s_output { - bool output_enable; /**< I2S output enable */ - u32 frequency; /**< range from 8000-48000 Hz */ - enum drxi2s_mode mode; /**< I2S mode, master or slave */ + bool output_enable; /*< I2S output enable */ + u32 frequency; /*< range from 8000-48000 Hz */ + enum drxi2s_mode mode; /*< I2S mode, master or slave */ enum drxi2s_word_length word_length; - /**< I2S wordlength, 16 or 32 bits */ - enum drxi2s_polarity polarity;/**< I2S wordstrobe polarity */ - enum drxi2s_format format; /**< I2S wordstrobe delay to data */ + /*< I2S wordlength, 16 or 32 bits */ + enum drxi2s_polarity polarity;/*< I2S wordstrobe polarity */ + enum drxi2s_format format; /*< I2S wordstrobe delay to data */ }; /* ------------------------------expert interface-----------------------------*/ -/** +/* * /enum enum drx_aud_fm_deemphasis * setting for FM-Deemphasis in audio demodulator. * */ @@ -1531,7 +1531,7 @@ struct drx_version_list { DRX_AUD_FM_DEEMPH_OFF }; -/** +/* * /enum DRXAudDeviation_t * setting for deviation mode in audio demodulator. * @@ -1541,7 +1541,7 @@ struct drx_version_list { DRX_AUD_DEVIATION_HIGH }; -/** +/* * /enum enum drx_no_carrier_option * setting for carrier, mute/noise. * */ @@ -1550,7 +1550,7 @@ struct drx_version_list { DRX_NO_CARRIER_NOISE }; -/** +/* * \enum DRXAudAutoSound_t * \brief Automatic Sound */ @@ -1560,7 +1560,7 @@ struct drx_version_list { DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF }; -/** +/* * \enum DRXAudASSThres_t * \brief Automatic Sound Select Thresholds */ @@ -1570,7 +1570,7 @@ struct drx_version_list { u16 nicam; /* Nicam Threshold for ASS configuration */ }; -/** +/* * \struct struct drx_aud_carrier * \brief Carrier detection related parameters */ struct drx_aud_carrier { @@ -1580,7 +1580,7 @@ struct drx_version_list { s32 dco; /* frequency adjustment (A) */ }; -/** +/* * \struct struct drx_cfg_aud_carriers * \brief combining carrier A & B to one struct */ struct drx_cfg_aud_carriers { @@ -1588,7 +1588,7 @@ struct drx_version_list { struct drx_aud_carrier b; }; -/** +/* * /enum enum drx_aud_i2s_src * Selection of audio source */ enum drx_aud_i2s_src { @@ -1597,19 +1597,19 @@ struct drx_version_list { DRX_AUD_SRC_STEREO_OR_A, DRX_AUD_SRC_STEREO_OR_B}; -/** +/* * \enum enum drx_aud_i2s_matrix * \brief Used for selecting I2S output. */ enum drx_aud_i2s_matrix { DRX_AUD_I2S_MATRIX_A_MONO, - /**< A sound only, stereo or mono */ + /*< A sound only, stereo or mono */ DRX_AUD_I2S_MATRIX_B_MONO, - /**< B sound only, stereo or mono */ + /*< B sound only, stereo or mono */ DRX_AUD_I2S_MATRIX_STEREO, - /**< A+B sound, transparant */ - DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */}; + /*< A+B sound, transparant */ + DRX_AUD_I2S_MATRIX_MONO /*< A+B mixed to mono sum, (L+R)/2 */}; -/** +/* * /enum enum drx_aud_fm_matrix * setting for FM-Matrix in audio demodulator. * */ @@ -1620,7 +1620,7 @@ struct drx_version_list { DRX_AUD_FM_MATRIX_SOUND_A, DRX_AUD_FM_MATRIX_SOUND_B}; -/** +/* * \struct DRXAudMatrices_t * \brief Mixer settings */ @@ -1630,22 +1630,22 @@ struct drx_cfg_aud_mixer { enum drx_aud_fm_matrix matrix_fm; }; -/** +/* * \enum DRXI2SVidSync_t * \brief Audio/video synchronization, interacts with I2S mode. * AUTO_1 and AUTO_2 are for automatic video standard detection with preference * for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) */ enum drx_cfg_aud_av_sync { - DRX_AUD_AVSYNC_OFF,/**< audio/video synchronization is off */ + DRX_AUD_AVSYNC_OFF,/*< audio/video synchronization is off */ DRX_AUD_AVSYNC_NTSC, - /**< it is an NTSC system */ + /*< it is an NTSC system */ DRX_AUD_AVSYNC_MONOCHROME, - /**< it is a MONOCHROME system */ + /*< it is a MONOCHROME system */ DRX_AUD_AVSYNC_PAL_SECAM - /**< it is a PAL/SECAM system */}; + /*< it is a PAL/SECAM system */}; -/** +/* * \struct struct drx_cfg_aud_prescale * \brief Prescalers */ struct drx_cfg_aud_prescale { @@ -1653,7 +1653,7 @@ struct drx_cfg_aud_prescale { s16 nicam_gain; }; -/** +/* * \struct struct drx_aud_beep * \brief Beep */ struct drx_aud_beep { @@ -1662,14 +1662,14 @@ struct drx_aud_beep { bool mute; }; -/** +/* * \enum enum drx_aud_btsc_detect * \brief BTSC detetcion mode */ enum drx_aud_btsc_detect { DRX_BTSC_STEREO, DRX_BTSC_MONO_AND_SAP}; -/** +/* * \struct struct drx_aud_data * \brief Audio data structure */ struct drx_aud_data { @@ -1692,7 +1692,7 @@ struct drx_aud_data { bool rds_data_present; }; -/** +/* * \enum enum drx_qam_lock_range * \brief QAM lock range mode */ enum drx_qam_lock_range { @@ -1782,7 +1782,7 @@ struct drx_aud_data { u32 wdata, /* data to write */ u32 *rdata); /* data to read */ -/** +/* * \struct struct drx_access_func * \brief Interface to an access protocol. */ struct drx_access_func { @@ -1811,85 +1811,85 @@ struct drx_reg_dump { /*============================================================================*/ /*============================================================================*/ -/** +/* * \struct struct drx_common_attr * \brief Set of common attributes, shared by all DRX devices. */ struct drx_common_attr { /* Microcode (firmware) attributes */ - char *microcode_file; /**< microcode filename */ + char *microcode_file; /*< microcode filename */ bool verify_microcode; - /**< Use microcode verify or not. */ + /*< Use microcode verify or not. */ struct drx_mc_version_rec mcversion; - /**< Version record of microcode from file */ + /*< Version record of microcode from file */ /* Clocks and tuner attributes */ s32 intermediate_freq; - /**< IF,if tuner instance not used. (kHz)*/ + /*< IF,if tuner instance not used. (kHz)*/ s32 sys_clock_freq; - /**< Systemclock frequency. (kHz) */ + /*< Systemclock frequency. (kHz) */ s32 osc_clock_freq; - /**< Oscillator clock frequency. (kHz) */ + /*< Oscillator clock frequency. (kHz) */ s16 osc_clock_deviation; - /**< Oscillator clock deviation. (ppm) */ + /*< Oscillator clock deviation. (ppm) */ bool mirror_freq_spect; - /**< Mirror IF frequency spectrum or not.*/ + /*< Mirror IF frequency spectrum or not.*/ /* Initial MPEG output attributes */ struct drx_cfg_mpeg_output mpeg_cfg; - /**< MPEG configuration */ + /*< MPEG configuration */ - bool is_opened; /**< if true instance is already opened. */ + bool is_opened; /*< if true instance is already opened. */ /* Channel scan */ struct drx_scan_param *scan_param; - /**< scan parameters */ + /*< scan parameters */ u16 scan_freq_plan_index; - /**< next index in freq plan */ + /*< next index in freq plan */ s32 scan_next_frequency; - /**< next freq to scan */ - bool scan_ready; /**< scan ready flag */ - u32 scan_max_channels;/**< number of channels in freqplan */ + /*< next freq to scan */ + bool scan_ready; /*< scan ready flag */ + u32 scan_max_channels;/*< number of channels in freqplan */ u32 scan_channels_scanned; - /**< number of channels scanned */ + /*< number of channels scanned */ /* Channel scan - inner loop: demod related */ drx_scan_func_t scan_function; - /**< function to check channel */ + /*< function to check channel */ /* Channel scan - inner loop: SYSObj related */ - void *scan_context; /**< Context Pointer of SYSObj */ + void *scan_context; /*< Context Pointer of SYSObj */ /* Channel scan - parameters for default DTV scan function in core driver */ u16 scan_demod_lock_timeout; - /**< millisecs to wait for lock */ + /*< millisecs to wait for lock */ enum drx_lock_status scan_desired_lock; - /**< lock requirement for channel found */ + /*< lock requirement for channel found */ /* scan_active can be used by SetChannel to decide how to program the tuner, fast or slow (but stable). Usually fast during scan. */ - bool scan_active; /**< true when scan routines are active */ + bool scan_active; /*< true when scan routines are active */ /* Power management */ enum drx_power_mode current_power_mode; - /**< current power management mode */ + /*< current power management mode */ /* Tuner */ - u8 tuner_port_nr; /**< nr of I2C port to wich tuner is */ + u8 tuner_port_nr; /*< nr of I2C port to wich tuner is */ s32 tuner_min_freq_rf; - /**< minimum RF input frequency, in kHz */ + /*< minimum RF input frequency, in kHz */ s32 tuner_max_freq_rf; - /**< maximum RF input frequency, in kHz */ - bool tuner_rf_agc_pol; /**< if true invert RF AGC polarity */ - bool tuner_if_agc_pol; /**< if true invert IF AGC polarity */ - bool tuner_slow_mode; /**< if true invert IF AGC polarity */ + /*< maximum RF input frequency, in kHz */ + bool tuner_rf_agc_pol; /*< if true invert RF AGC polarity */ + bool tuner_if_agc_pol; /*< if true invert IF AGC polarity */ + bool tuner_slow_mode; /*< if true invert IF AGC polarity */ struct drx_channel current_channel; - /**< current channel parameters */ + /*< current channel parameters */ enum drx_standard current_standard; - /**< current standard selection */ + /*< current standard selection */ enum drx_standard prev_standard; - /**< previous standard selection */ + /*< previous standard selection */ enum drx_standard di_cache_standard; - /**< standard in DI cache if available */ - bool use_bootloader; /**< use bootloader in open */ - u32 capabilities; /**< capabilities flags */ - u32 product_id; /**< product ID inc. metal fix number */}; + /*< standard in DI cache if available */ + bool use_bootloader; /*< use bootloader in open */ + u32 capabilities; /*< capabilities flags */ + u32 product_id; /*< product ID inc. metal fix number */}; /* * Generic functions for DRX devices. @@ -1897,16 +1897,16 @@ struct drx_reg_dump { struct drx_demod_instance; -/** +/* * \struct struct drx_demod_instance * \brief Top structure of demodulator instance. */ struct drx_demod_instance { - /**< data access protocol functions */ + /*< data access protocol functions */ struct i2c_device_addr *my_i2c_dev_addr; - /**< i2c address and device identifier */ + /*< i2c address and device identifier */ struct drx_common_attr *my_common_attr; - /**< common DRX attributes */ - void *my_ext_attr; /**< device specific attributes */ + /*< common DRX attributes */ + void *my_ext_attr; /*< device specific attributes */ /* generic demodulator data */ struct i2c_adapter *i2c; @@ -2195,7 +2195,7 @@ Conversion from enum values to human readable form. Access macros -------------------------------------------------------------------------*/ -/** +/* * \brief Create a compilable reference to the microcode attribute * \param d pointer to demod instance * @@ -2229,7 +2229,7 @@ Access macros #define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id) #define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) -/**************************/ +/*************************/ /* Macros with device-specific handling are converted to CFG functions */ @@ -2285,7 +2285,7 @@ Access macros #define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \ DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN) -/** +/* * \brief Macro to check if std is an ATV standard * \retval true std is an ATV standard * \retval false std is an ATV standard @@ -2298,7 +2298,7 @@ Access macros ((std) == DRX_STANDARD_NTSC) || \ ((std) == DRX_STANDARD_FM)) -/** +/* * \brief Macro to check if std is an QAM standard * \retval true std is an QAM standards * \retval false std is an QAM standards @@ -2308,14 +2308,14 @@ Access macros ((std) == DRX_STANDARD_ITU_C) || \ ((std) == DRX_STANDARD_ITU_D)) -/** +/* * \brief Macro to check if std is VSB standard * \retval true std is VSB standard * \retval false std is not VSB standard */ #define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB) -/** +/* * \brief Macro to check if std is DVBT standard * \retval true std is DVBT standard * \retval false std is not DVBT standard diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index 6c5b8f78f9f6..d3ee1c23bb2f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -69,15 +69,15 @@ TYPEDEFS struct drxjscu_cmd { u16 command; - /**< Command number */ + /*< Command number */ u16 parameter_len; - /**< Data length in byte */ + /*< Data length in byte */ u16 result_len; - /**< result length in byte */ + /*< result length in byte */ u16 *parameter; - /**< General purpous param */ + /*< General purpous param */ u16 *result; - /**< General purpous param */}; + /*< General purpous param */}; /*============================================================================*/ /*============================================================================*/ @@ -130,7 +130,7 @@ TYPEDEFS DRXJ_CFG_MAX /* dummy, never to be used */}; -/** +/* * /struct enum drxj_cfg_smart_ant_io * smart antenna i/o. */ enum drxj_cfg_smart_ant_io { @@ -138,7 +138,7 @@ enum drxj_cfg_smart_ant_io { DRXJ_SMT_ANT_INPUT }; -/** +/* * /struct struct drxj_cfg_smart_ant * Set smart antenna. */ struct drxj_cfg_smart_ant { @@ -146,7 +146,7 @@ enum drxj_cfg_smart_ant_io { u16 ctrl_data; }; -/** +/* * /struct DRXJAGCSTATUS_t * AGC status information from the DRXJ-IQM-AF. */ @@ -158,7 +158,7 @@ struct drxj_agc_status { /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ -/** +/* * /struct enum drxj_agc_ctrl_mode * Available AGCs modes in the DRXJ. */ enum drxj_agc_ctrl_mode { @@ -166,7 +166,7 @@ struct drxj_agc_status { DRX_AGC_CTRL_USER, DRX_AGC_CTRL_OFF}; -/** +/* * /struct struct drxj_cfg_agc * Generic interface for all AGCs present on the DRXJ. */ struct drxj_cfg_agc { @@ -182,7 +182,7 @@ struct drxj_agc_status { /* DRXJ_CFG_PRE_SAW */ -/** +/* * /struct struct drxj_cfg_pre_saw * Interface to configure pre SAW sense. */ struct drxj_cfg_pre_saw { @@ -192,14 +192,14 @@ struct drxj_agc_status { /* DRXJ_CFG_AFE_GAIN */ -/** +/* * /struct struct drxj_cfg_afe_gain * Interface to configure gain of AFE (LNA + PGA). */ struct drxj_cfg_afe_gain { enum drx_standard standard; /* standard to which these settings apply */ u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */}; -/** +/* * /struct drxjrs_errors * Available failure information in DRXJ_FEC_RS. * @@ -208,25 +208,25 @@ struct drxj_agc_status { */ struct drxjrs_errors { u16 nr_bit_errors; - /**< no of pre RS bit errors */ + /*< no of pre RS bit errors */ u16 nr_symbol_errors; - /**< no of pre RS symbol errors */ + /*< no of pre RS symbol errors */ u16 nr_packet_errors; - /**< no of pre RS packet errors */ + /*< no of pre RS packet errors */ u16 nr_failures; - /**< no of post RS failures to decode */ + /*< no of post RS failures to decode */ u16 nr_snc_par_fail_count; - /**< no of post RS bit erros */ + /*< no of post RS bit erros */ }; -/** +/* * /struct struct drxj_cfg_vsb_misc * symbol error rate */ struct drxj_cfg_vsb_misc { u32 symb_error; - /**< symbol error rate sps */}; + /*< symbol error rate sps */}; -/** +/* * /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. * */ @@ -234,7 +234,7 @@ struct drxj_agc_status { DRXJ_MPEG_START_WIDTH_1CLKCYC, DRXJ_MPEG_START_WIDTH_8CLKCYC}; -/** +/* * /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. * */ @@ -247,20 +247,20 @@ struct drxj_agc_status { DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K}; -/** +/* * /struct DRXJCfgMisc_t * Change TEI bit of MPEG output * reverse MPEG output bit order * set MPEG output clock rate */ struct drxj_cfg_mpeg_output_misc { - bool disable_tei_handling; /**< if true pass (not change) TEI bit */ - bool bit_reverse_mpeg_outout; /**< if true, parallel: msb on MD0; serial: lsb out first */ + bool disable_tei_handling; /*< if true pass (not change) TEI bit */ + bool bit_reverse_mpeg_outout; /*< if true, parallel: msb on MD0; serial: lsb out first */ enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; - /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ - enum drxj_mpeg_start_width mpeg_start_width; /**< set MPEG output start width */}; + /*< set MPEG output clock rate that overwirtes the derived one from symbol rate */ + enum drxj_mpeg_start_width mpeg_start_width; /*< set MPEG output start width */}; -/** +/* * /enum enum drxj_xtal_freq * Supported external crystal reference frequency. */ enum drxj_xtal_freq { @@ -269,21 +269,21 @@ struct drxj_agc_status { DRXJ_XTAL_FREQ_20P25MHZ, DRXJ_XTAL_FREQ_4MHZ}; -/** +/* * /enum enum drxj_xtal_freq * Supported external crystal reference frequency. */ enum drxji2c_speed { DRXJ_I2C_SPEED_400KBPS, DRXJ_I2C_SPEED_100KBPS}; -/** +/* * /struct struct drxj_cfg_hw_cfg * Get hw configuration, such as crystal reference frequency, I2C speed, etc... */ struct drxj_cfg_hw_cfg { enum drxj_xtal_freq xtal_freq; - /**< crystal reference frequency */ + /*< crystal reference frequency */ enum drxji2c_speed i2c_speed; - /**< 100 or 400 kbps */}; + /*< 100 or 400 kbps */}; /* * DRXJ_CFG_ATV_MISC @@ -352,7 +352,7 @@ struct drxj_cfg_oob_misc { * DRXJ_CFG_ATV_OUTPUT */ -/** +/* * /enum DRXJAttenuation_t * Attenuation setting for SIF AGC. * @@ -363,7 +363,7 @@ struct drxj_cfg_oob_misc { DRXJ_SIF_ATTENUATION_6DB, DRXJ_SIF_ATTENUATION_9DB}; -/** +/* * /struct struct drxj_cfg_atv_output * SIF attenuation setting. * */ @@ -398,7 +398,7 @@ struct drxj_cfg_atv_output { /*============================================================================*/ /*========================================*/ -/** +/* * /struct struct drxj_data * DRXJ specific attributes. * * Global data container for DRXJ specific data. @@ -406,93 +406,93 @@ struct drxj_cfg_atv_output { */ struct drxj_data { /* device capabilties (determined during drx_open()) */ - bool has_lna; /**< true if LNA (aka PGA) present */ - bool has_oob; /**< true if OOB supported */ - bool has_ntsc; /**< true if NTSC supported */ - bool has_btsc; /**< true if BTSC supported */ - bool has_smatx; /**< true if mat_tx is available */ - bool has_smarx; /**< true if mat_rx is available */ - bool has_gpio; /**< true if GPIO is available */ - bool has_irqn; /**< true if IRQN is available */ + bool has_lna; /*< true if LNA (aka PGA) present */ + bool has_oob; /*< true if OOB supported */ + bool has_ntsc; /*< true if NTSC supported */ + bool has_btsc; /*< true if BTSC supported */ + bool has_smatx; /*< true if mat_tx is available */ + bool has_smarx; /*< true if mat_rx is available */ + bool has_gpio; /*< true if GPIO is available */ + bool has_irqn; /*< true if IRQN is available */ /* A1/A2/A... */ - u8 mfx; /**< metal fix */ + u8 mfx; /*< metal fix */ /* tuner settings */ - bool mirror_freq_spect_oob;/**< tuner inversion (true = tuner mirrors the signal */ + bool mirror_freq_spect_oob;/*< tuner inversion (true = tuner mirrors the signal */ /* standard/channel settings */ - enum drx_standard standard; /**< current standard information */ + enum drx_standard standard; /*< current standard information */ enum drx_modulation constellation; - /**< current constellation */ - s32 frequency; /**< center signal frequency in KHz */ + /*< current constellation */ + s32 frequency; /*< center signal frequency in KHz */ enum drx_bandwidth curr_bandwidth; - /**< current channel bandwidth */ - enum drx_mirror mirror; /**< current channel mirror */ + /*< current channel bandwidth */ + enum drx_mirror mirror; /*< current channel mirror */ /* signal quality information */ - u32 fec_bits_desired; /**< BER accounting period */ - u16 fec_vd_plen; /**< no of trellis symbols: VD SER measurement period */ - u16 qam_vd_prescale; /**< Viterbi Measurement Prescale */ - u16 qam_vd_period; /**< Viterbi Measurement period */ - u16 fec_rs_plen; /**< defines RS BER measurement period */ - u16 fec_rs_prescale; /**< ReedSolomon Measurement Prescale */ - u16 fec_rs_period; /**< ReedSolomon Measurement period */ - bool reset_pkt_err_acc; /**< Set a flag to reset accumulated packet error */ - u16 pkt_err_acc_start; /**< Set a flag to reset accumulated packet error */ + u32 fec_bits_desired; /*< BER accounting period */ + u16 fec_vd_plen; /*< no of trellis symbols: VD SER measurement period */ + u16 qam_vd_prescale; /*< Viterbi Measurement Prescale */ + u16 qam_vd_period; /*< Viterbi Measurement period */ + u16 fec_rs_plen; /*< defines RS BER measurement period */ + u16 fec_rs_prescale; /*< ReedSolomon Measurement Prescale */ + u16 fec_rs_period; /*< ReedSolomon Measurement period */ + bool reset_pkt_err_acc; /*< Set a flag to reset accumulated packet error */ + u16 pkt_err_acc_start; /*< Set a flag to reset accumulated packet error */ /* HI configuration */ - u16 hi_cfg_timing_div; /**< HI Configure() parameter 2 */ - u16 hi_cfg_bridge_delay; /**< HI Configure() parameter 3 */ - u16 hi_cfg_wake_up_key; /**< HI Configure() parameter 4 */ - u16 hi_cfg_ctrl; /**< HI Configure() parameter 5 */ - u16 hi_cfg_transmit; /**< HI Configure() parameter 6 */ + u16 hi_cfg_timing_div; /*< HI Configure() parameter 2 */ + u16 hi_cfg_bridge_delay; /*< HI Configure() parameter 3 */ + u16 hi_cfg_wake_up_key; /*< HI Configure() parameter 4 */ + u16 hi_cfg_ctrl; /*< HI Configure() parameter 5 */ + u16 hi_cfg_transmit; /*< HI Configure() parameter 6 */ /* UIO configuration */ - enum drxuio_mode uio_sma_rx_mode;/**< current mode of SmaRx pin */ - enum drxuio_mode uio_sma_tx_mode;/**< current mode of SmaTx pin */ - enum drxuio_mode uio_gpio_mode; /**< current mode of ASEL pin */ - enum drxuio_mode uio_irqn_mode; /**< current mode of IRQN pin */ + enum drxuio_mode uio_sma_rx_mode;/*< current mode of SmaRx pin */ + enum drxuio_mode uio_sma_tx_mode;/*< current mode of SmaTx pin */ + enum drxuio_mode uio_gpio_mode; /*< current mode of ASEL pin */ + enum drxuio_mode uio_irqn_mode; /*< current mode of IRQN pin */ /* IQM fs frequecy shift and inversion */ - u32 iqm_fs_rate_ofs; /**< frequency shifter setting after setchannel */ - bool pos_image; /**< Ture: positive image */ + u32 iqm_fs_rate_ofs; /*< frequency shifter setting after setchannel */ + bool pos_image; /*< Ture: positive image */ /* IQM RC frequecy shift */ - u32 iqm_rc_rate_ofs; /**< frequency shifter setting after setchannel */ + u32 iqm_rc_rate_ofs; /*< frequency shifter setting after setchannel */ /* ATV configuration */ - u32 atv_cfg_changed_flags; /**< flag: flags cfg changes */ - s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ - s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ - s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ - s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ - bool phase_correction_bypass;/**< flag: true=bypass */ - s16 atv_top_vid_peak; /**< shadow of ATV_TOP_VID_PEAK__A */ - u16 atv_top_noise_th; /**< shadow of ATV_TOP_NOISE_TH__A */ - bool enable_cvbs_output; /**< flag CVBS ouput enable */ - bool enable_sif_output; /**< flag SIF ouput enable */ + u32 atv_cfg_changed_flags; /*< flag: flags cfg changes */ + s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU0__A */ + s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU1__A */ + s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU2__A */ + s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU3__A */ + bool phase_correction_bypass;/*< flag: true=bypass */ + s16 atv_top_vid_peak; /*< shadow of ATV_TOP_VID_PEAK__A */ + u16 atv_top_noise_th; /*< shadow of ATV_TOP_NOISE_TH__A */ + bool enable_cvbs_output; /*< flag CVBS ouput enable */ + bool enable_sif_output; /*< flag SIF ouput enable */ enum drxjsif_attenuation sif_attenuation; - /**< current SIF att setting */ + /*< current SIF att setting */ /* Agc configuration for QAM and VSB */ - struct drxj_cfg_agc qam_rf_agc_cfg; /**< qam RF AGC config */ - struct drxj_cfg_agc qam_if_agc_cfg; /**< qam IF AGC config */ - struct drxj_cfg_agc vsb_rf_agc_cfg; /**< vsb RF AGC config */ - struct drxj_cfg_agc vsb_if_agc_cfg; /**< vsb IF AGC config */ + struct drxj_cfg_agc qam_rf_agc_cfg; /*< qam RF AGC config */ + struct drxj_cfg_agc qam_if_agc_cfg; /*< qam IF AGC config */ + struct drxj_cfg_agc vsb_rf_agc_cfg; /*< vsb RF AGC config */ + struct drxj_cfg_agc vsb_if_agc_cfg; /*< vsb IF AGC config */ /* PGA gain configuration for QAM and VSB */ - u16 qam_pga_cfg; /**< qam PGA config */ - u16 vsb_pga_cfg; /**< vsb PGA config */ + u16 qam_pga_cfg; /*< qam PGA config */ + u16 vsb_pga_cfg; /*< vsb PGA config */ /* Pre SAW configuration for QAM and VSB */ struct drxj_cfg_pre_saw qam_pre_saw_cfg; - /**< qam pre SAW config */ + /*< qam pre SAW config */ struct drxj_cfg_pre_saw vsb_pre_saw_cfg; - /**< qam pre SAW config */ + /*< qam pre SAW config */ /* Version information */ - char v_text[2][12]; /**< allocated text versions */ - struct drx_version v_version[2]; /**< allocated versions structs */ + char v_text[2][12]; /*< allocated text versions */ + struct drx_version v_version[2]; /*< allocated versions structs */ struct drx_version_list v_list_elements[2]; - /**< allocated version list */ + /*< allocated version list */ /* smart antenna configuration */ bool smart_ant_inverted; @@ -502,25 +502,25 @@ struct drxj_cfg_atv_output { bool oob_power_on; /* MPEG static bitrate setting */ - u32 mpeg_ts_static_bitrate; /**< bitrate static MPEG output */ - bool disable_te_ihandling; /**< MPEG TS TEI handling */ - bool bit_reverse_mpeg_outout;/**< MPEG output bit order */ + u32 mpeg_ts_static_bitrate; /*< bitrate static MPEG output */ + bool disable_te_ihandling; /*< MPEG TS TEI handling */ + bool bit_reverse_mpeg_outout;/*< MPEG output bit order */ enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; - /**< MPEG output clock rate */ + /*< MPEG output clock rate */ enum drxj_mpeg_start_width mpeg_start_width; - /**< MPEG Start width */ + /*< MPEG Start width */ /* Pre SAW & Agc configuration for ATV */ struct drxj_cfg_pre_saw atv_pre_saw_cfg; - /**< atv pre SAW config */ - struct drxj_cfg_agc atv_rf_agc_cfg; /**< atv RF AGC config */ - struct drxj_cfg_agc atv_if_agc_cfg; /**< atv IF AGC config */ - u16 atv_pga_cfg; /**< atv pga config */ + /*< atv pre SAW config */ + struct drxj_cfg_agc atv_rf_agc_cfg; /*< atv RF AGC config */ + struct drxj_cfg_agc atv_if_agc_cfg; /*< atv IF AGC config */ + u16 atv_pga_cfg; /*< atv pga config */ u32 curr_symbol_rate; /* pin-safe mode */ - bool pdr_safe_mode; /**< PDR safe mode activated */ + bool pdr_safe_mode; /*< PDR safe mode activated */ u16 pdr_safe_restore_val_gpio; u16 pdr_safe_restore_val_v_sync; u16 pdr_safe_restore_val_sma_rx; @@ -531,12 +531,12 @@ struct drxj_cfg_atv_output { enum drxj_cfg_oob_lo_power oob_lo_pow; struct drx_aud_data aud_data; - /**< audio storage */}; + /*< audio storage */}; /*------------------------------------------------------------------------- Access MACROS -------------------------------------------------------------------------*/ -/** +/* * \brief Compilable references to attributes * \param d pointer to demod instance * @@ -554,7 +554,7 @@ Access MACROS DEFINES -------------------------------------------------------------------------*/ -/** +/* * \def DRXJ_NTSC_CARRIER_FREQ_OFFSET * \brief Offset from picture carrier to centre frequency in kHz, in RF domain * @@ -569,7 +569,7 @@ DEFINES */ #define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750)) -/** +/* * \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET * \brief Offset from picture carrier to centre frequency in kHz, in RF domain * @@ -585,7 +585,7 @@ DEFINES */ #define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375)) -/** +/* * \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET * \brief Offset from picture carrier to centre frequency in kHz, in RF domain * @@ -601,7 +601,7 @@ DEFINES */ #define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775)) -/** +/* * \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET * \brief Offset from picture carrier to centre frequency in kHz, in RF domain * @@ -616,7 +616,7 @@ DEFINES */ #define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255)) -/** +/* * \def DRXJ_FM_CARRIER_FREQ_OFFSET * \brief Offset from sound carrier to centre frequency in kHz, in RF domain * diff --git a/drivers/media/dvb-frontends/drxk.h b/drivers/media/dvb-frontends/drxk.h index eb9bdc9f59c4..c936142367fb 100644 --- a/drivers/media/dvb-frontends/drxk.h +++ b/drivers/media/dvb-frontends/drxk.h @@ -20,17 +20,18 @@ * @antenna_dvbt: GPIO bit for changing antenna to DVB-C. A value of 1 * means that 1=DVBC, 0 = DVBT. Zero means the opposite. * @mpeg_out_clk_strength: DRXK Mpeg output clock drive strength. + * @chunk_size: maximum size for I2C messages * @microcode_name: Name of the firmware file with the microcode * @qam_demod_parameter_count: The number of parameters used for the command * to set the demodulator parameters. All * firmwares are using the 2-parameter commmand. - * An exception is the "drxk_a3.mc" firmware, + * An exception is the ``drxk_a3.mc`` firmware, * which uses the 4-parameter command. * A value of 0 (default) or lower indicates that * the correct number of parameters will be * automatically detected. * - * On the *_gpio vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is + * On the ``*_gpio`` vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is * UIO-3. */ struct drxk_config { diff --git a/drivers/media/dvb-frontends/dvb-pll.h b/drivers/media/dvb-frontends/dvb-pll.h index 6aaa9c6bff9c..01dbcc4d9550 100644 --- a/drivers/media/dvb-frontends/dvb-pll.h +++ b/drivers/media/dvb-frontends/dvb-pll.h @@ -33,11 +33,12 @@ /** * Attach a dvb-pll to the supplied frontend structure. * - * @param fe Frontend to attach to. - * @param pll_addr i2c address of the PLL (if used). - * @param i2c i2c adapter to use (set to NULL if not used). - * @param pll_desc_id dvb_pll_desc to use. - * @return Frontend pointer on success, NULL on failure + * @fe: Frontend to attach to. + * @pll_addr: i2c address of the PLL (if used). + * @i2c: i2c adapter to use (set to NULL if not used). + * @pll_desc_id: dvb_pll_desc to use. + * + * return: Frontend pointer on success, NULL on failure */ #if IS_REACHABLE(CONFIG_DVB_PLL) extern struct dvb_frontend *dvb_pll_attach(struct dvb_frontend *fe, diff --git a/drivers/media/dvb-frontends/helene.h b/drivers/media/dvb-frontends/helene.h index 333615491d9e..3f504f5d1d4f 100644 --- a/drivers/media/dvb-frontends/helene.h +++ b/drivers/media/dvb-frontends/helene.h @@ -38,6 +38,7 @@ enum helene_xtal { * @set_tuner_priv: Callback function private context * @set_tuner_callback: Callback function that notifies the parent driver * which tuner is active now + * @xtal: Cristal frequency as described by &enum helene_xtal */ struct helene_config { u8 i2c_address; diff --git a/drivers/media/dvb-frontends/ix2505v.h b/drivers/media/dvb-frontends/ix2505v.h index 0b0a431c74f6..31ca03a7b827 100644 --- a/drivers/media/dvb-frontends/ix2505v.h +++ b/drivers/media/dvb-frontends/ix2505v.h @@ -19,14 +19,6 @@ #include #include "dvb_frontend.h" -/** - * Attach a ix2505v tuner to the supplied frontend structure. - * - * @param fe Frontend to attach to. - * @param config ix2505v_config structure - * @return FE pointer on success, NULL on failure. - */ - struct ix2505v_config { u8 tuner_address; @@ -45,6 +37,15 @@ struct ix2505v_config { }; #if IS_REACHABLE(CONFIG_DVB_IX2505V) +/** + * Attach a ix2505v tuner to the supplied frontend structure. + * + * @fe: Frontend to attach to. + * @config: pointer to &struct ix2505v_config + * @i2c: pointer to &struct i2c_adapter. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *ix2505v_attach(struct dvb_frontend *fe, const struct ix2505v_config *config, struct i2c_adapter *i2c); #else diff --git a/drivers/media/dvb-frontends/l64781.c b/drivers/media/dvb-frontends/l64781.c index 68923c84679a..e5a6c1766664 100644 --- a/drivers/media/dvb-frontends/l64781.c +++ b/drivers/media/dvb-frontends/l64781.c @@ -517,7 +517,7 @@ struct dvb_frontend* l64781_attach(const struct l64781_config* config, state->i2c = i2c; state->first = 1; - /** + /* * the L64781 won't show up before we send the reset_and_configure() * broadcast. If nothing responds there is no L64781 on the bus... */ diff --git a/drivers/media/dvb-frontends/mn88472.h b/drivers/media/dvb-frontends/mn88472.h index 323632523876..8cd5ef61903b 100644 --- a/drivers/media/dvb-frontends/mn88472.h +++ b/drivers/media/dvb-frontends/mn88472.h @@ -19,21 +19,21 @@ #include +/* Define old names for backward compatibility */ +#define VARIABLE_TS_CLOCK MN88472_TS_CLK_VARIABLE +#define FIXED_TS_CLOCK MN88472_TS_CLK_FIXED +#define SERIAL_TS_MODE MN88472_TS_MODE_SERIAL +#define PARALLEL_TS_MODE MN88472_TS_MODE_PARALLEL + /** * struct mn88472_config - Platform data for the mn88472 driver * @xtal: Clock frequency. * @ts_mode: TS mode. * @ts_clock: TS clock config. * @i2c_wr_max: Max number of bytes driver writes to I2C at once. - * @get_dvb_frontend: Get DVB frontend. + * @fe: pointer to a frontend pointer + * @get_dvb_frontend: Get DVB frontend callback. */ - -/* Define old names for backward compatibility */ -#define VARIABLE_TS_CLOCK MN88472_TS_CLK_VARIABLE -#define FIXED_TS_CLOCK MN88472_TS_CLK_FIXED -#define SERIAL_TS_MODE MN88472_TS_MODE_SERIAL -#define PARALLEL_TS_MODE MN88472_TS_MODE_PARALLEL - struct mn88472_config { unsigned int xtal; diff --git a/drivers/media/dvb-frontends/rtl2832_sdr.h b/drivers/media/dvb-frontends/rtl2832_sdr.h index d8fc7e7212e3..8f88c2fb8627 100644 --- a/drivers/media/dvb-frontends/rtl2832_sdr.h +++ b/drivers/media/dvb-frontends/rtl2832_sdr.h @@ -33,15 +33,11 @@ * struct rtl2832_sdr_platform_data - Platform data for the rtl2832_sdr driver * @clk: Clock frequency (4000000, 16000000, 25000000, 28800000). * @tuner: Used tuner model. - * @i2c_client: rtl2832 demod driver I2C client. - * @bulk_read: rtl2832 driver private I/O interface. - * @bulk_write: rtl2832 driver private I/O interface. - * @update_bits: rtl2832 driver private I/O interface. + * @regmap: pointer to &struct regmap. * @dvb_frontend: rtl2832 DVB frontend. * @v4l2_subdev: Tuner v4l2 controls. * @dvb_usb_device: DVB USB interface for USB streaming. */ - struct rtl2832_sdr_platform_data { u32 clk; /* diff --git a/drivers/media/dvb-frontends/stb6000.h b/drivers/media/dvb-frontends/stb6000.h index 78e75dfc317f..3c4d51dd5415 100644 --- a/drivers/media/dvb-frontends/stb6000.h +++ b/drivers/media/dvb-frontends/stb6000.h @@ -29,10 +29,11 @@ /** * Attach a stb6000 tuner to the supplied frontend structure. * - * @param fe Frontend to attach to. - * @param addr i2c address of the tuner. - * @param i2c i2c adapter to use. - * @return FE pointer on success, NULL on failure. + * @fe: Frontend to attach to. + * @addr: i2c address of the tuner. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. */ #if IS_REACHABLE(CONFIG_DVB_STB6000) extern struct dvb_frontend *stb6000_attach(struct dvb_frontend *fe, int addr, diff --git a/drivers/media/dvb-frontends/stv0299.c b/drivers/media/dvb-frontends/stv0299.c index b36b21a13201..b1f3d675d316 100644 --- a/drivers/media/dvb-frontends/stv0299.c +++ b/drivers/media/dvb-frontends/stv0299.c @@ -368,7 +368,7 @@ static int stv0299_set_voltage(struct dvb_frontend *fe, reg0x08 = stv0299_readreg (state, 0x08); reg0x0c = stv0299_readreg (state, 0x0c); - /** + /* * H/V switching over OP0, OP1 and OP2 are LNB power enable bits */ reg0x0c &= 0x0f; diff --git a/drivers/media/dvb-frontends/tda826x.h b/drivers/media/dvb-frontends/tda826x.h index 81abe1aebe9f..6a7bed12e741 100644 --- a/drivers/media/dvb-frontends/tda826x.h +++ b/drivers/media/dvb-frontends/tda826x.h @@ -29,11 +29,12 @@ /** * Attach a tda826x tuner to the supplied frontend structure. * - * @param fe Frontend to attach to. - * @param addr i2c address of the tuner. - * @param i2c i2c adapter to use. - * @param has_loopthrough Set to 1 if the card has a loopthrough RF connector. - * @return FE pointer on success, NULL on failure. + * @fe: Frontend to attach to. + * @addr: i2c address of the tuner. + * @i2c: i2c adapter to use. + * @has_loopthrough: Set to 1 if the card has a loopthrough RF connector. + * + * return: FE pointer on success, NULL on failure. */ #if IS_REACHABLE(CONFIG_DVB_TDA826X) extern struct dvb_frontend* tda826x_attach(struct dvb_frontend *fe, int addr, diff --git a/drivers/media/dvb-frontends/tua6100.h b/drivers/media/dvb-frontends/tua6100.h index 9f15cbdfdeca..6c098a894ea6 100644 --- a/drivers/media/dvb-frontends/tua6100.h +++ b/drivers/media/dvb-frontends/tua6100.h @@ -1,4 +1,4 @@ -/** +/* * Driver for Infineon tua6100 PLL. * * (c) 2006 Andrew de Quincey diff --git a/drivers/media/dvb-frontends/zd1301_demod.h b/drivers/media/dvb-frontends/zd1301_demod.h index ceb2e05e873c..9496f7e8b4dd 100644 --- a/drivers/media/dvb-frontends/zd1301_demod.h +++ b/drivers/media/dvb-frontends/zd1301_demod.h @@ -27,7 +27,6 @@ * @reg_read: Register read callback. * @reg_write: Register write callback. */ - struct zd1301_demod_platform_data { void *reg_priv; int (*reg_read)(void *, u16, u8 *); @@ -41,8 +40,7 @@ struct zd1301_demod_platform_data { * * Return: Pointer to DVB frontend which given platform device owns. */ - -struct dvb_frontend *zd1301_demod_get_dvb_frontend(struct platform_device *); +struct dvb_frontend *zd1301_demod_get_dvb_frontend(struct platform_device *pdev); /** * zd1301_demod_get_i2c_adapter() - Get pointer to I2C adapter @@ -50,8 +48,7 @@ struct dvb_frontend *zd1301_demod_get_dvb_frontend(struct platform_device *); * * Return: Pointer to I2C adapter which given platform device owns. */ - -struct i2c_adapter *zd1301_demod_get_i2c_adapter(struct platform_device *); +struct i2c_adapter *zd1301_demod_get_i2c_adapter(struct platform_device *pdev); #else diff --git a/drivers/media/dvb-frontends/zl10036.h b/drivers/media/dvb-frontends/zl10036.h index 88751adfecf7..ec90ca927739 100644 --- a/drivers/media/dvb-frontends/zl10036.h +++ b/drivers/media/dvb-frontends/zl10036.h @@ -20,20 +20,20 @@ #include #include "dvb_frontend.h" -/** - * Attach a zl10036 tuner to the supplied frontend structure. - * - * @param fe Frontend to attach to. - * @param config zl10036_config structure - * @return FE pointer on success, NULL on failure. - */ - struct zl10036_config { u8 tuner_address; int rf_loop_enable; }; #if IS_REACHABLE(CONFIG_DVB_ZL10036) +/** + * Attach a zl10036 tuner to the supplied frontend structure. + * + * @fe: Frontend to attach to. + * @config: zl10036_config structure. + * @i2c: pointer to struct i2c_adapter. + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe, const struct zl10036_config *config, struct i2c_adapter *i2c); #else -- GitLab From e61edeb155ca20cf30009196738d4a7a8365ac9f Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 12:46:12 -0500 Subject: [PATCH 0348/2547] media: docs: add documentation for frontend attach info Add to the media book the attachment kAPI for the DVB frontend drivers that have already some kernel-doc markup. Signed-off-by: Mauro Carvalho Chehab --- Documentation/media/dvb-drivers/frontends.rst | 30 +++++++++++++++++++ Documentation/media/dvb-drivers/index.rst | 1 + 2 files changed, 31 insertions(+) create mode 100644 Documentation/media/dvb-drivers/frontends.rst diff --git a/Documentation/media/dvb-drivers/frontends.rst b/Documentation/media/dvb-drivers/frontends.rst new file mode 100644 index 000000000000..1f5f57989196 --- /dev/null +++ b/Documentation/media/dvb-drivers/frontends.rst @@ -0,0 +1,30 @@ +**************** +Frontend drivers +**************** + +Frontend attach headers +*********************** + +.. Keep it on alphabetic order + +.. kernel-doc:: drivers/media/dvb-frontends/a8293.h +.. kernel-doc:: drivers/media/dvb-frontends/af9013.h +.. kernel-doc:: drivers/media/dvb-frontends/ascot2e.h +.. kernel-doc:: drivers/media/dvb-frontends/cxd2820r.h +.. kernel-doc:: drivers/media/dvb-frontends/drxk.h +.. kernel-doc:: drivers/media/dvb-frontends/dvb-pll.h +.. kernel-doc:: drivers/media/dvb-frontends/helene.h +.. kernel-doc:: drivers/media/dvb-frontends/horus3a.h +.. kernel-doc:: drivers/media/dvb-frontends/ix2505v.h +.. kernel-doc:: drivers/media/dvb-frontends/m88ds3103.h +.. kernel-doc:: drivers/media/dvb-frontends/mb86a20s.h +.. kernel-doc:: drivers/media/dvb-frontends/mn88472.h +.. kernel-doc:: drivers/media/dvb-frontends/rtl2830.h +.. kernel-doc:: drivers/media/dvb-frontends/rtl2832.h +.. kernel-doc:: drivers/media/dvb-frontends/rtl2832_sdr.h +.. kernel-doc:: drivers/media/dvb-frontends/stb6000.h +.. kernel-doc:: drivers/media/dvb-frontends/tda10071.h +.. kernel-doc:: drivers/media/dvb-frontends/tda826x.h +.. kernel-doc:: drivers/media/dvb-frontends/zd1301_demod.h +.. kernel-doc:: drivers/media/dvb-frontends/zl10036.h + diff --git a/Documentation/media/dvb-drivers/index.rst b/Documentation/media/dvb-drivers/index.rst index 376141143ae9..314e127d82e3 100644 --- a/Documentation/media/dvb-drivers/index.rst +++ b/Documentation/media/dvb-drivers/index.rst @@ -41,4 +41,5 @@ For more details see the file COPYING in the source distribution of Linux. technisat ttusb-dec udev + frontends contributors -- GitLab From be9b53c83792e3898755dce90f8c632d40e7c83e Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 29 Nov 2017 14:02:22 -0500 Subject: [PATCH 0349/2547] media: dvb-frontends: complete kernel-doc markups For the dvb-frontends that are now part of the documentation, complete the kernel-doc markups, in order for them to be properly used at the driver's kAPI documentation. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/af9013.h | 24 ++-- drivers/media/dvb-frontends/ascot2e.h | 9 ++ drivers/media/dvb-frontends/cxd2820r.h | 24 +++- drivers/media/dvb-frontends/drxk.h | 8 ++ drivers/media/dvb-frontends/dvb-pll.h | 2 +- drivers/media/dvb-frontends/helene.h | 29 +++- drivers/media/dvb-frontends/horus3a.h | 9 ++ drivers/media/dvb-frontends/ix2505v.h | 17 +-- drivers/media/dvb-frontends/m88ds3103.h | 155 +++++++++------------ drivers/media/dvb-frontends/mb86a20s.h | 17 +-- drivers/media/dvb-frontends/rtl2830.h | 1 - drivers/media/dvb-frontends/rtl2832.h | 1 - drivers/media/dvb-frontends/stb6000.h | 2 +- drivers/media/dvb-frontends/tda10071.h | 1 - drivers/media/dvb-frontends/zd1301_demod.h | 6 + 15 files changed, 177 insertions(+), 128 deletions(-) diff --git a/drivers/media/dvb-frontends/af9013.h b/drivers/media/dvb-frontends/af9013.h index 353274524f1b..a290722c04fd 100644 --- a/drivers/media/dvb-frontends/af9013.h +++ b/drivers/media/dvb-frontends/af9013.h @@ -38,6 +38,13 @@ * @api_version: Firmware API version. * @gpio: GPIOs. * @get_dvb_frontend: Get DVB frontend callback. + * + * AF9013/5 GPIOs (mostly guessed): + * * demod#1-gpio#0 - set demod#2 i2c-addr for dual devices + * * demod#1-gpio#1 - xtal setting (?) + * * demod#1-gpio#3 - tuner#1 + * * demod#2-gpio#0 - tuner#2 + * * demod#2-gpio#1 - xtal setting (?) */ struct af9013_platform_data { /* @@ -89,16 +96,15 @@ struct af9013_platform_data { #define AF9013_TS_PARALLEL AF9013_TS_MODE_PARALLEL #define AF9013_TS_SERIAL AF9013_TS_MODE_SERIAL -/* - * AF9013/5 GPIOs (mostly guessed) - * demod#1-gpio#0 - set demod#2 i2c-addr for dual devices - * demod#1-gpio#1 - xtal setting (?) - * demod#1-gpio#3 - tuner#1 - * demod#2-gpio#0 - tuner#2 - * demod#2-gpio#1 - xtal setting (?) - */ - #if IS_REACHABLE(CONFIG_DVB_AF9013) +/** + * Attach an af9013 demod + * + * @config: pointer to &struct af9013_config with demod configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *af9013_attach(const struct af9013_config *config, struct i2c_adapter *i2c); #else diff --git a/drivers/media/dvb-frontends/ascot2e.h b/drivers/media/dvb-frontends/ascot2e.h index dc61bf7d1b09..418c565baf83 100644 --- a/drivers/media/dvb-frontends/ascot2e.h +++ b/drivers/media/dvb-frontends/ascot2e.h @@ -41,6 +41,15 @@ struct ascot2e_config { }; #if IS_REACHABLE(CONFIG_DVB_ASCOT2E) +/** + * Attach an ascot2e tuner + * + * @fe: frontend to be attached + * @config: pointer to &struct ascot2e_config with tuner configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *ascot2e_attach(struct dvb_frontend *fe, const struct ascot2e_config *config, struct i2c_adapter *i2c); diff --git a/drivers/media/dvb-frontends/cxd2820r.h b/drivers/media/dvb-frontends/cxd2820r.h index f3ff8f6eb3bb..a49400c0e28e 100644 --- a/drivers/media/dvb-frontends/cxd2820r.h +++ b/drivers/media/dvb-frontends/cxd2820r.h @@ -49,7 +49,6 @@ * @gpio_chip_base: GPIO. * @get_dvb_frontend: Get DVB frontend. */ - struct cxd2820r_platform_data { u8 ts_mode; bool ts_clk_inv; @@ -62,6 +61,17 @@ struct cxd2820r_platform_data { bool attach_in_use; }; +/** + * struct cxd2820r_config - configuration for cxd2020r demod + * + * @i2c_address: Demodulator I2C address. Driver determines DVB-C slave I2C + * address automatically from master address. + * Default: none, must set. Values: 0x6c, 0x6d. + * @ts_mode: TS output mode. Default: none, must set. Values: FIXME? + * @ts_clock_inv: TS clock inverted. Default: 0. Values: 0, 1. + * @if_agc_polarity: Default: 0. Values: 0, 1 + * @spec_inv: Spectrum inversion. Default: 0. Values: 0, 1. + */ struct cxd2820r_config { /* Demodulator I2C address. * Driver determines DVB-C slave I2C address automatically from master @@ -98,6 +108,18 @@ struct cxd2820r_config { #if IS_REACHABLE(CONFIG_DVB_CXD2820R) +/** + * Attach a cxd2820r demod + * + * @config: pointer to &struct cxd2820r_config with demod configuration. + * @i2c: i2c adapter to use. + * @gpio_chip_base: if zero, disables GPIO setting. Otherwise, if + * CONFIG_GPIOLIB is set dynamically allocate + * gpio base; if is not set, use its value to + * setup the GPIO pins. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *cxd2820r_attach( const struct cxd2820r_config *config, struct i2c_adapter *i2c, diff --git a/drivers/media/dvb-frontends/drxk.h b/drivers/media/dvb-frontends/drxk.h index c936142367fb..b16fedbb53a3 100644 --- a/drivers/media/dvb-frontends/drxk.h +++ b/drivers/media/dvb-frontends/drxk.h @@ -53,6 +53,14 @@ struct drxk_config { }; #if IS_REACHABLE(CONFIG_DVB_DRXK) +/** + * Attach a drxk demod + * + * @config: pointer to &struct drxk_config with demod configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *drxk_attach(const struct drxk_config *config, struct i2c_adapter *i2c); #else diff --git a/drivers/media/dvb-frontends/dvb-pll.h b/drivers/media/dvb-frontends/dvb-pll.h index 01dbcc4d9550..212e0730f154 100644 --- a/drivers/media/dvb-frontends/dvb-pll.h +++ b/drivers/media/dvb-frontends/dvb-pll.h @@ -30,6 +30,7 @@ #define DVB_PLL_TDEE4 18 #define DVB_PLL_THOMSON_DTT7520X 19 +#if IS_REACHABLE(CONFIG_DVB_PLL) /** * Attach a dvb-pll to the supplied frontend structure. * @@ -40,7 +41,6 @@ * * return: Frontend pointer on success, NULL on failure */ -#if IS_REACHABLE(CONFIG_DVB_PLL) extern struct dvb_frontend *dvb_pll_attach(struct dvb_frontend *fe, int pll_addr, struct i2c_adapter *i2c, diff --git a/drivers/media/dvb-frontends/helene.h b/drivers/media/dvb-frontends/helene.h index 3f504f5d1d4f..c9fc81c7e4e7 100644 --- a/drivers/media/dvb-frontends/helene.h +++ b/drivers/media/dvb-frontends/helene.h @@ -49,9 +49,31 @@ struct helene_config { }; #if IS_REACHABLE(CONFIG_DVB_HELENE) +/** + * Attach a helene tuner (terrestrial and cable standards) + * + * @fe: frontend to be attached + * @config: pointer to &struct helene_config with tuner configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *helene_attach(struct dvb_frontend *fe, const struct helene_config *config, struct i2c_adapter *i2c); + +/** + * Attach a helene tuner (satellite standards) + * + * @fe: frontend to be attached + * @config: pointer to &struct helene_config with tuner configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ +extern struct dvb_frontend *helene_attach_s(struct dvb_frontend *fe, + const struct helene_config *config, + struct i2c_adapter *i2c); #else static inline struct dvb_frontend *helene_attach(struct dvb_frontend *fe, const struct helene_config *config, @@ -60,13 +82,6 @@ static inline struct dvb_frontend *helene_attach(struct dvb_frontend *fe, pr_warn("%s: driver disabled by Kconfig\n", __func__); return NULL; } -#endif - -#if IS_REACHABLE(CONFIG_DVB_HELENE) -extern struct dvb_frontend *helene_attach_s(struct dvb_frontend *fe, - const struct helene_config *config, - struct i2c_adapter *i2c); -#else static inline struct dvb_frontend *helene_attach_s(struct dvb_frontend *fe, const struct helene_config *config, struct i2c_adapter *i2c) diff --git a/drivers/media/dvb-frontends/horus3a.h b/drivers/media/dvb-frontends/horus3a.h index 672a556df71a..9157fd037e2f 100644 --- a/drivers/media/dvb-frontends/horus3a.h +++ b/drivers/media/dvb-frontends/horus3a.h @@ -41,6 +41,15 @@ struct horus3a_config { }; #if IS_REACHABLE(CONFIG_DVB_HORUS3A) +/** + * Attach a horus3a tuner + * + * @fe: frontend to be attached + * @config: pointer to &struct helene_config with tuner configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *horus3a_attach(struct dvb_frontend *fe, const struct horus3a_config *config, struct i2c_adapter *i2c); diff --git a/drivers/media/dvb-frontends/ix2505v.h b/drivers/media/dvb-frontends/ix2505v.h index 31ca03a7b827..49ed93e754ed 100644 --- a/drivers/media/dvb-frontends/ix2505v.h +++ b/drivers/media/dvb-frontends/ix2505v.h @@ -19,19 +19,20 @@ #include #include "dvb_frontend.h" +/** + * struct ix2505v_config - ix2505 attachment configuration + * + * @tuner_address: tuner address + * @tuner_gain: Baseband AMP gain control 0/1=0dB(default) 2=-2bB 3=-4dB + * @tuner_chargepump: Charge pump output +/- 0=120 1=260 2=555 3=1200(default) + * @min_delay_ms: delay after tune + * @tuner_write_only: disables reads + */ struct ix2505v_config { u8 tuner_address; - - /*Baseband AMP gain control 0/1=0dB(default) 2=-2bB 3=-4dB */ u8 tuner_gain; - - /*Charge pump output +/- 0=120 1=260 2=555 3=1200(default) */ u8 tuner_chargepump; - - /* delay after tune */ int min_delay_ms; - - /* disables reads*/ u8 tuner_write_only; }; diff --git a/drivers/media/dvb-frontends/m88ds3103.h b/drivers/media/dvb-frontends/m88ds3103.h index 04b355a005fb..1a8964a2265d 100644 --- a/drivers/media/dvb-frontends/m88ds3103.h +++ b/drivers/media/dvb-frontends/m88ds3103.h @@ -24,6 +24,34 @@ * 0x68, */ +/** + * enum m88ds3103_ts_mode - TS connection mode + * @M88DS3103_TS_SERIAL: TS output pin D0, normal + * @M88DS3103_TS_SERIAL_D7: TS output pin D7 + * @M88DS3103_TS_PARALLEL: TS Parallel mode + * @M88DS3103_TS_CI: TS CI Mode + */ +enum m88ds3103_ts_mode { + M88DS3103_TS_SERIAL, + M88DS3103_TS_SERIAL_D7, + M88DS3103_TS_PARALLEL, + M88DS3103_TS_CI +}; + +/** + * enum m88ds3103_clock_out + * @M88DS3103_CLOCK_OUT_DISABLED: Clock output is disabled + * @M88DS3103_CLOCK_OUT_ENABLED: Clock output is enabled with crystal + * clock. + * @M88DS3103_CLOCK_OUT_ENABLED_DIV2: Clock output is enabled with half + * crystal clock. + */ +enum m88ds3103_clock_out { + M88DS3103_CLOCK_OUT_DISABLED, + M88DS3103_CLOCK_OUT_ENABLED, + M88DS3103_CLOCK_OUT_ENABLED_DIV2 +}; + /** * struct m88ds3103_platform_data - Platform data for the m88ds3103 driver * @clk: Clock frequency. @@ -44,24 +72,16 @@ * @get_dvb_frontend: Get DVB frontend. * @get_i2c_adapter: Get I2C adapter. */ - struct m88ds3103_platform_data { u32 clk; u16 i2c_wr_max; -#define M88DS3103_TS_SERIAL 0 /* TS output pin D0, normal */ -#define M88DS3103_TS_SERIAL_D7 1 /* TS output pin D7 */ -#define M88DS3103_TS_PARALLEL 2 /* TS Parallel mode */ -#define M88DS3103_TS_CI 3 /* TS CI Mode */ - u8 ts_mode:2; + enum m88ds3103_ts_mode ts_mode; u32 ts_clk; + enum m88ds3103_clock_out clk_out; u8 ts_clk_pol:1; u8 spec_inv:1; u8 agc; u8 agc_inv:1; -#define M88DS3103_CLOCK_OUT_DISABLED 0 -#define M88DS3103_CLOCK_OUT_ENABLED 1 -#define M88DS3103_CLOCK_OUT_ENABLED_DIV2 2 - u8 clk_out:2; u8 envelope_mode:1; u8 lnb_hv_pol:1; u8 lnb_en_pol:1; @@ -73,105 +93,60 @@ struct m88ds3103_platform_data { u8 attach_in_use:1; }; -/* - * Do not add new m88ds3103_attach() users! Use I2C bindings instead. +/** + * struct m88ds3103_config - m88ds3102 configuration + * + * @i2c_addr: I2C address. Default: none, must set. Example: 0x68, ... + * @clock: Device's clock. Default: none, must set. Example: 27000000 + * @i2c_wr_max: Max bytes I2C provider is asked to write at once. + * Default: none, must set. Example: 33, 65, ... + * @ts_mode: TS output mode, as defined by &enum m88ds3103_ts_mode. + * Default: M88DS3103_TS_SERIAL. + * @ts_clk: TS clk in KHz. Default: 0. + * @ts_clk_pol: TS clk polarity.Default: 0. + * 1-active at falling edge; 0-active at rising edge. + * @spec_inv: Spectrum inversion. Default: 0. + * @agc_inv: AGC polarity. Default: 0. + * @clock_out: Clock output, as defined by &enum m88ds3103_clock_out. + * Default: M88DS3103_CLOCK_OUT_DISABLED. + * @envelope_mode: DiSEqC envelope mode. Default: 0. + * @agc: AGC configuration. Default: none, must set. + * @lnb_hv_pol: LNB H/V pin polarity. Default: 0. Values: + * 1: pin high set to VOLTAGE_13, pin low to set VOLTAGE_18; + * 0: pin high set to VOLTAGE_18, pin low to set VOLTAGE_13. + * @lnb_en_pol: LNB enable pin polarity. Default: 0. Values: + * 1: pin high to enable, pin low to disable; + * 0: pin high to disable, pin low to enable. */ struct m88ds3103_config { - /* - * I2C address - * Default: none, must set - * 0x68, ... - */ u8 i2c_addr; - - /* - * clock - * Default: none, must set - * 27000000 - */ u32 clock; - - /* - * max bytes I2C provider is asked to write at once - * Default: none, must set - * 33, 65, ... - */ u16 i2c_wr_max; - - /* - * TS output mode - * Default: M88DS3103_TS_SERIAL - */ -#define M88DS3103_TS_SERIAL 0 /* TS output pin D0, normal */ -#define M88DS3103_TS_SERIAL_D7 1 /* TS output pin D7 */ -#define M88DS3103_TS_PARALLEL 2 /* TS Parallel mode */ -#define M88DS3103_TS_CI 3 /* TS CI Mode */ u8 ts_mode; - - /* - * TS clk in KHz - * Default: 0. - */ u32 ts_clk; - - /* - * TS clk polarity. - * Default: 0. 1-active at falling edge; 0-active at rising edge. - */ u8 ts_clk_pol:1; - - /* - * spectrum inversion - * Default: 0 - */ u8 spec_inv:1; - - /* - * AGC polarity - * Default: 0 - */ u8 agc_inv:1; - - /* - * clock output - * Default: M88DS3103_CLOCK_OUT_DISABLED - */ -#define M88DS3103_CLOCK_OUT_DISABLED 0 -#define M88DS3103_CLOCK_OUT_ENABLED 1 -#define M88DS3103_CLOCK_OUT_ENABLED_DIV2 2 u8 clock_out; - - /* - * DiSEqC envelope mode - * Default: 0 - */ u8 envelope_mode:1; - - /* - * AGC configuration - * Default: none, must set - */ u8 agc; - - /* - * LNB H/V pin polarity - * Default: 0. - * 1: pin high set to VOLTAGE_13, pin low to set VOLTAGE_18. - * 0: pin high set to VOLTAGE_18, pin low to set VOLTAGE_13. - */ u8 lnb_hv_pol:1; - - /* - * LNB enable pin polarity - * Default: 0. - * 1: pin high to enable, pin low to disable. - * 0: pin high to disable, pin low to enable. - */ u8 lnb_en_pol:1; }; #if defined(CONFIG_DVB_M88DS3103) || \ (defined(CONFIG_DVB_M88DS3103_MODULE) && defined(MODULE)) +/** + * Attach a m88ds3103 demod + * + * @config: pointer to &struct m88ds3103_config with demod configuration. + * @i2c: i2c adapter to use. + * @tuner_i2c: on success, returns the I2C adapter associated with + * m88ds3103 tuner. + * + * return: FE pointer on success, NULL on failure. + * Note: Do not add new m88ds3103_attach() users! Use I2C bindings instead. + */ extern struct dvb_frontend *m88ds3103_attach( const struct m88ds3103_config *config, struct i2c_adapter *i2c, diff --git a/drivers/media/dvb-frontends/mb86a20s.h b/drivers/media/dvb-frontends/mb86a20s.h index dfb02db2126c..05c9725d1c5f 100644 --- a/drivers/media/dvb-frontends/mb86a20s.h +++ b/drivers/media/dvb-frontends/mb86a20s.h @@ -26,7 +26,6 @@ * @demod_address: the demodulator's i2c address * @is_serial: if true, TS is serial. Otherwise, TS is parallel */ - struct mb86a20s_config { u32 fclk; u8 demod_address; @@ -34,9 +33,17 @@ struct mb86a20s_config { }; #if IS_REACHABLE(CONFIG_DVB_MB86A20S) +/** + * Attach a mb86a20s demod + * + * @config: pointer to &struct mb86a20s_config with demod configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, struct i2c_adapter *i2c); -extern struct i2c_adapter *mb86a20s_get_tuner_i2c_adapter(struct dvb_frontend *); + #else static inline struct dvb_frontend *mb86a20s_attach( const struct mb86a20s_config *config, struct i2c_adapter *i2c) @@ -44,12 +51,6 @@ static inline struct dvb_frontend *mb86a20s_attach( printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; } -static inline struct i2c_adapter * - mb86a20s_get_tuner_i2c_adapter(struct dvb_frontend *fe) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} #endif #endif /* MB86A20S */ diff --git a/drivers/media/dvb-frontends/rtl2830.h b/drivers/media/dvb-frontends/rtl2830.h index 0cde151e6608..458ac94e8a8b 100644 --- a/drivers/media/dvb-frontends/rtl2830.h +++ b/drivers/media/dvb-frontends/rtl2830.h @@ -32,7 +32,6 @@ * @pid_filter: Set PID to PID filter. * @pid_filter_ctrl: Control PID filter. */ - struct rtl2830_platform_data { u32 clk; bool spec_inv; diff --git a/drivers/media/dvb-frontends/rtl2832.h b/drivers/media/dvb-frontends/rtl2832.h index 03c0de039fa9..6a124ff71c2b 100644 --- a/drivers/media/dvb-frontends/rtl2832.h +++ b/drivers/media/dvb-frontends/rtl2832.h @@ -35,7 +35,6 @@ * @pid_filter: Set PID to PID filter. * @pid_filter_ctrl: Control PID filter. */ - struct rtl2832_platform_data { u32 clk; /* diff --git a/drivers/media/dvb-frontends/stb6000.h b/drivers/media/dvb-frontends/stb6000.h index 3c4d51dd5415..e94a3d5facf6 100644 --- a/drivers/media/dvb-frontends/stb6000.h +++ b/drivers/media/dvb-frontends/stb6000.h @@ -26,6 +26,7 @@ #include #include "dvb_frontend.h" +#if IS_REACHABLE(CONFIG_DVB_STB6000) /** * Attach a stb6000 tuner to the supplied frontend structure. * @@ -35,7 +36,6 @@ * * return: FE pointer on success, NULL on failure. */ -#if IS_REACHABLE(CONFIG_DVB_STB6000) extern struct dvb_frontend *stb6000_attach(struct dvb_frontend *fe, int addr, struct i2c_adapter *i2c); #else diff --git a/drivers/media/dvb-frontends/tda10071.h b/drivers/media/dvb-frontends/tda10071.h index 8f184026ee11..da1a87bc1603 100644 --- a/drivers/media/dvb-frontends/tda10071.h +++ b/drivers/media/dvb-frontends/tda10071.h @@ -38,7 +38,6 @@ * @tuner_i2c_addr: CX24118A tuner I2C address (0x14, 0x54, ...). * @get_dvb_frontend: Get DVB frontend. */ - struct tda10071_platform_data { u32 clk; u16 i2c_wr_max; diff --git a/drivers/media/dvb-frontends/zd1301_demod.h b/drivers/media/dvb-frontends/zd1301_demod.h index 9496f7e8b4dd..6cd8f6f9c415 100644 --- a/drivers/media/dvb-frontends/zd1301_demod.h +++ b/drivers/media/dvb-frontends/zd1301_demod.h @@ -52,6 +52,12 @@ struct i2c_adapter *zd1301_demod_get_i2c_adapter(struct platform_device *pdev); #else +/** + * zd1301_demod_get_dvb_frontend() - Attach a zd1301 frontend + * @dev: Pointer to platform device + * + * Return: Pointer to %struct dvb_frontend or NULL if attach fails. + */ static inline struct dvb_frontend *zd1301_demod_get_dvb_frontend(struct platform_device *dev) { printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); -- GitLab From 6d33377f2abbf9f0e561b116dd468d1c3ff36a6a Mon Sep 17 00:00:00 2001 From: Laurent Caumont Date: Sat, 11 Nov 2017 12:44:46 -0500 Subject: [PATCH 0350/2547] media: dvb: i2c transfers over usb cannot be done from stack Cc: stable@vger.kernel.org Signed-off-by: Laurent Caumont Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb/dibusb-common.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/media/usb/dvb-usb/dibusb-common.c b/drivers/media/usb/dvb-usb/dibusb-common.c index 8207e6900656..bcacb0f22028 100644 --- a/drivers/media/usb/dvb-usb/dibusb-common.c +++ b/drivers/media/usb/dvb-usb/dibusb-common.c @@ -223,8 +223,20 @@ EXPORT_SYMBOL(dibusb_i2c_algo); int dibusb_read_eeprom_byte(struct dvb_usb_device *d, u8 offs, u8 *val) { - u8 wbuf[1] = { offs }; - return dibusb_i2c_msg(d, 0x50, wbuf, 1, val, 1); + u8 *buf; + int rc; + + buf = kmalloc(2, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + buf[0] = offs; + + rc = dibusb_i2c_msg(d, 0x50, &buf[0], 1, &buf[1], 1); + *val = buf[1]; + kfree(buf); + + return rc; } EXPORT_SYMBOL(dibusb_read_eeprom_byte); -- GitLab From 67f0f15ad5c47490e19f2526f8f9cea97c5ce1a6 Mon Sep 17 00:00:00 2001 From: Sean Young Date: Sun, 19 Nov 2017 16:57:27 -0500 Subject: [PATCH 0351/2547] media: rc: partial revert of "media: rc: per-protocol repeat period" Since commit d57ea877af38 ("media: rc: per-protocol repeat period"), most IR protocols have a lower keyup timeout. This causes problems on the ite-cir, which has default IR timeout of 200ms. Since the IR decoders read the trailing space, with a IR timeout of 200ms, the last keydown will have at least a delay of 200ms. This is more than the protocol timeout of e.g. rc-6 (which is 164ms). As a result the last IR will be interpreted as a new keydown event, and we get two keypresses. Revert the protocol timeout to 250ms, except for cec which needs a timeout of 550ms. Fixes: d57ea877af38 ("media: rc: per-protocol repeat period") Cc: # 4.14 Reported-by: Matthias Reichl Signed-off-by: Sean Young Tested-by: Matthias Reichl Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/rc-main.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index c4b0217bd169..c144b77eac98 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -39,41 +39,41 @@ static const struct { [RC_PROTO_UNKNOWN] = { .name = "unknown", .repeat_period = 250 }, [RC_PROTO_OTHER] = { .name = "other", .repeat_period = 250 }, [RC_PROTO_RC5] = { .name = "rc-5", - .scancode_bits = 0x1f7f, .repeat_period = 164 }, + .scancode_bits = 0x1f7f, .repeat_period = 250 }, [RC_PROTO_RC5X_20] = { .name = "rc-5x-20", - .scancode_bits = 0x1f7f3f, .repeat_period = 164 }, + .scancode_bits = 0x1f7f3f, .repeat_period = 250 }, [RC_PROTO_RC5_SZ] = { .name = "rc-5-sz", - .scancode_bits = 0x2fff, .repeat_period = 164 }, + .scancode_bits = 0x2fff, .repeat_period = 250 }, [RC_PROTO_JVC] = { .name = "jvc", .scancode_bits = 0xffff, .repeat_period = 250 }, [RC_PROTO_SONY12] = { .name = "sony-12", - .scancode_bits = 0x1f007f, .repeat_period = 100 }, + .scancode_bits = 0x1f007f, .repeat_period = 250 }, [RC_PROTO_SONY15] = { .name = "sony-15", - .scancode_bits = 0xff007f, .repeat_period = 100 }, + .scancode_bits = 0xff007f, .repeat_period = 250 }, [RC_PROTO_SONY20] = { .name = "sony-20", - .scancode_bits = 0x1fff7f, .repeat_period = 100 }, + .scancode_bits = 0x1fff7f, .repeat_period = 250 }, [RC_PROTO_NEC] = { .name = "nec", - .scancode_bits = 0xffff, .repeat_period = 160 }, + .scancode_bits = 0xffff, .repeat_period = 250 }, [RC_PROTO_NECX] = { .name = "nec-x", - .scancode_bits = 0xffffff, .repeat_period = 160 }, + .scancode_bits = 0xffffff, .repeat_period = 250 }, [RC_PROTO_NEC32] = { .name = "nec-32", - .scancode_bits = 0xffffffff, .repeat_period = 160 }, + .scancode_bits = 0xffffffff, .repeat_period = 250 }, [RC_PROTO_SANYO] = { .name = "sanyo", .scancode_bits = 0x1fffff, .repeat_period = 250 }, [RC_PROTO_MCIR2_KBD] = { .name = "mcir2-kbd", - .scancode_bits = 0xffff, .repeat_period = 150 }, + .scancode_bits = 0xffff, .repeat_period = 250 }, [RC_PROTO_MCIR2_MSE] = { .name = "mcir2-mse", - .scancode_bits = 0x1fffff, .repeat_period = 150 }, + .scancode_bits = 0x1fffff, .repeat_period = 250 }, [RC_PROTO_RC6_0] = { .name = "rc-6-0", - .scancode_bits = 0xffff, .repeat_period = 164 }, + .scancode_bits = 0xffff, .repeat_period = 250 }, [RC_PROTO_RC6_6A_20] = { .name = "rc-6-6a-20", - .scancode_bits = 0xfffff, .repeat_period = 164 }, + .scancode_bits = 0xfffff, .repeat_period = 250 }, [RC_PROTO_RC6_6A_24] = { .name = "rc-6-6a-24", - .scancode_bits = 0xffffff, .repeat_period = 164 }, + .scancode_bits = 0xffffff, .repeat_period = 250 }, [RC_PROTO_RC6_6A_32] = { .name = "rc-6-6a-32", - .scancode_bits = 0xffffffff, .repeat_period = 164 }, + .scancode_bits = 0xffffffff, .repeat_period = 250 }, [RC_PROTO_RC6_MCE] = { .name = "rc-6-mce", - .scancode_bits = 0xffff7fff, .repeat_period = 164 }, + .scancode_bits = 0xffff7fff, .repeat_period = 250 }, [RC_PROTO_SHARP] = { .name = "sharp", .scancode_bits = 0x1fff, .repeat_period = 250 }, [RC_PROTO_XMP] = { .name = "xmp", .repeat_period = 250 }, -- GitLab From fce8ba670b7418319da14a6fc6668db1f1a96267 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Sun, 5 Nov 2017 17:51:00 -0500 Subject: [PATCH 0352/2547] media: ov13858: Select V4L2_FWNODE The ov13858 driver depends on the V4L2 fwnode, thus add that to Kconfig. Fixes: 5fcf092e0c9f ("[media] ov13858: add support for OV13858 sensor") Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 3c6d6428f525..cb5d7ff82915 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -676,6 +676,7 @@ config VIDEO_OV13858 tristate "OmniVision OV13858 sensor support" depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API depends on MEDIA_CAMERA_SUPPORT + select V4L2_FWNODE ---help--- This is a Video4Linux2 sensor-level driver for the OmniVision OV13858 camera. -- GitLab From 2aa4d4985fc526ce076bef68b3efe6013c20b975 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 13 Nov 2017 08:56:45 -0500 Subject: [PATCH 0353/2547] media: et8ek8: select V4L2_FWNODE v4l2_async_register_subdev_sensor_common() is only provided when CONFIG_V4L2_FWNODE is enabled, otherwise we get a link failure: drivers/media/i2c/et8ek8/et8ek8_driver.o: In function `et8ek8_probe': et8ek8_driver.c:(.text+0x884): undefined reference to `v4l2_async_register_subdev_sensor_common' This adds a Kconfig 'select' statement like all the other users of this interface have. Fixes: d8932f38c10f ("media: et8ek8: Add support for flash and lens devices") Signed-off-by: Arnd Bergmann Reviewed-by: Sebastian Reichel Acked-by: Pavel Machek Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/et8ek8/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/i2c/et8ek8/Kconfig b/drivers/media/i2c/et8ek8/Kconfig index 14399365ad7f..9fe409e95666 100644 --- a/drivers/media/i2c/et8ek8/Kconfig +++ b/drivers/media/i2c/et8ek8/Kconfig @@ -1,6 +1,7 @@ config VIDEO_ET8EK8 tristate "ET8EK8 camera sensor support" depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE ---help--- This is a driver for the Toshiba ET8EK8 5 MP camera sensor. It is used for example in Nokia N900 (RX-51). -- GitLab From 3bf393860f6efc41ce268f5c21a457df1e8e6e00 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 15 Nov 2017 06:55:22 -0500 Subject: [PATCH 0354/2547] media: v4l2-fwnode: Check subdev count after checking port Current implementation of __v4l2_async_notifier_parse_fwnode_endpoints() checks first whether subdev_count >= subdev_max and only then whether the port being parsed matches the given port index. This triggers an error in otherwise valid cases of skipping ports that do not match. Fix this by moving the check below the port index check. Fixes: 9ca465312132 ("media: v4l: fwnode: Support generic parsing of graph endpoints in a device") Signed-off-by: Tomasz Figa Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-fwnode.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c index 681b192420d9..fb72c7ac04d4 100644 --- a/drivers/media/v4l2-core/v4l2-fwnode.c +++ b/drivers/media/v4l2-core/v4l2-fwnode.c @@ -458,11 +458,6 @@ static int __v4l2_async_notifier_parse_fwnode_endpoints( if (!is_available) continue; - if (WARN_ON(notifier->num_subdevs >= notifier->max_subdevs)) { - ret = -EINVAL; - break; - } - if (has_port) { struct fwnode_endpoint ep; @@ -474,6 +469,11 @@ static int __v4l2_async_notifier_parse_fwnode_endpoints( continue; } + if (WARN_ON(notifier->num_subdevs >= notifier->max_subdevs)) { + ret = -EINVAL; + break; + } + ret = v4l2_async_notifier_fwnode_parse_endpoint( dev, notifier, fwnode, asd_struct_size, parse_endpoint); if (ret < 0) -- GitLab From 487cc857851f6ca7850636bd111e7a4bfadab4da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Wed, 15 Nov 2017 10:43:58 -0500 Subject: [PATCH 0355/2547] media: v4l: async: use the v4l2_dev from the root notifier when matching sub-devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When matching and registering a sub-device from a sub-notifier use the v4l2_device from the root parent notifier. Using the v4l2_dev stored in the sub-notifier itself is incorrect as it might not be set. This can be demonstrated by unbinding and rebinding the adv748x driver and observing that it fails to probe due to the check !v4l2_dev in v4l2_device_register_subdev(). # echo 4-0070 > /sys/bus/i2c/drivers/adv748x/unbind # echo 4-0070 > /sys/bus/i2c/drivers/adv748x/bind adv748x 4-0070: chip found @ 0xe0 revision 2143 adv748x 4-0070: Failed to probe TXA adv748x: probe of 4-0070 failed with error -22 Looking at the commit which adds sub-notifiers to V4L2 it looks like this is the intended behavior of the original commit. With this fix the adv748x can be re-bound and still function properly. Fixes: 2cab00bb076b9f0e ("media: v4l: async: Allow binding notifiers to sub-devices") Signed-off-by: Niklas Söderlund Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-async.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c index a7c3464976f2..e5acfab470a5 100644 --- a/drivers/media/v4l2-core/v4l2-async.c +++ b/drivers/media/v4l2-core/v4l2-async.c @@ -558,8 +558,7 @@ int v4l2_async_register_subdev(struct v4l2_subdev *sd) if (!asd) continue; - ret = v4l2_async_match_notify(notifier, notifier->v4l2_dev, sd, - asd); + ret = v4l2_async_match_notify(notifier, v4l2_dev, sd, asd); if (ret) goto err_unbind; -- GitLab From 781b045baefdabf7e0bc9f33672ca830d3db9f27 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Wed, 1 Nov 2017 05:40:58 -0400 Subject: [PATCH 0356/2547] media: imx274: Fix error handling, add MAINTAINERS entry Add the missing MAINTAINERS entry for imx274, fix error handling in driver probe and unregister the correct control handler in driver remove. Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 8 ++++++++ drivers/media/i2c/imx274.c | 5 ++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index aa71ab52fd76..7a52a66aa991 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12630,6 +12630,14 @@ S: Maintained F: drivers/ssb/ F: include/linux/ssb/ +SONY IMX274 SENSOR DRIVER +M: Leon Luo +L: linux-media@vger.kernel.org +T: git git://linuxtv.org/media_tree.git +S: Maintained +F: drivers/media/i2c/imx274.c +F: Documentation/devicetree/bindings/media/i2c/imx274.txt + SONY MEMORYSTICK CARD SUPPORT M: Alex Dubov W: http://tifmxx.berlios.de/ diff --git a/drivers/media/i2c/imx274.c b/drivers/media/i2c/imx274.c index 800b9bf9cdd3..2f71af2f90bf 100644 --- a/drivers/media/i2c/imx274.c +++ b/drivers/media/i2c/imx274.c @@ -1770,8 +1770,7 @@ static int imx274_probe(struct i2c_client *client, return 0; err_ctrls: - v4l2_async_unregister_subdev(sd); - v4l2_ctrl_handler_free(sd->ctrl_handler); + v4l2_ctrl_handler_free(&imx274->ctrls.handler); err_me: media_entity_cleanup(&sd->entity); err_regmap: @@ -1788,7 +1787,7 @@ static int imx274_remove(struct i2c_client *client) imx274_write_table(imx274, mode_table[IMX274_MODE_STOP_STREAM]); v4l2_async_unregister_subdev(sd); - v4l2_ctrl_handler_free(sd->ctrl_handler); + v4l2_ctrl_handler_free(&imx274->ctrls.handler); media_entity_cleanup(&sd->entity); mutex_destroy(&imx274->lock); return 0; -- GitLab From 51f493ae71adc2c49a317a13c38e54e1cdf46005 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 30 Nov 2017 10:15:02 +0000 Subject: [PATCH 0357/2547] ASoC: codecs: msm8916-wcd: Fix supported formats This codec is configurable for only 16 bit and 32 bit samples, so reflect this in the supported formats also remove 24bit sample from supported list. Signed-off-by: Srinivas Kandagatla Signed-off-by: Mark Brown Cc: stable@vger.kernel.org --- sound/soc/codecs/msm8916-wcd-analog.c | 2 +- sound/soc/codecs/msm8916-wcd-digital.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/msm8916-wcd-analog.c b/sound/soc/codecs/msm8916-wcd-analog.c index 5f3c42c4f74a..066ea2f4ce7b 100644 --- a/sound/soc/codecs/msm8916-wcd-analog.c +++ b/sound/soc/codecs/msm8916-wcd-analog.c @@ -267,7 +267,7 @@ #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ - SNDRV_PCM_FMTBIT_S24_LE) + SNDRV_PCM_FMTBIT_S32_LE) static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4; diff --git a/sound/soc/codecs/msm8916-wcd-digital.c b/sound/soc/codecs/msm8916-wcd-digital.c index a10a724eb448..13354d6304a8 100644 --- a/sound/soc/codecs/msm8916-wcd-digital.c +++ b/sound/soc/codecs/msm8916-wcd-digital.c @@ -194,7 +194,7 @@ SNDRV_PCM_RATE_32000 | \ SNDRV_PCM_RATE_48000) #define MSM8916_WCD_DIGITAL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ - SNDRV_PCM_FMTBIT_S24_LE) + SNDRV_PCM_FMTBIT_S32_LE) struct msm8916_wcd_digital_priv { struct clk *ahbclk, *mclk; @@ -645,7 +645,7 @@ static int msm8916_wcd_digital_hw_params(struct snd_pcm_substream *substream, RX_I2S_CTL_RX_I2S_MODE_MASK, RX_I2S_CTL_RX_I2S_MODE_16); break; - case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S32_LE: snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_TX_I2S_CTL, TX_I2S_CTL_TX_I2S_MODE_MASK, TX_I2S_CTL_TX_I2S_MODE_32); -- GitLab From 7436830c8d1a3aab61d131d5e0494e2dbb9e55bd Mon Sep 17 00:00:00 2001 From: Valtteri Rantala Date: Tue, 28 Nov 2017 16:45:05 +0200 Subject: [PATCH 0358/2547] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too Testing the texture read performance shows that the same tuning for the SQ credits is needed on GLK as on BXT/APL. This has been also confirmed by Altug from the HW team. V4: Rebase + fix Signed-off-by: Valtteri Rantala Reviewed-by: David Weinehall (v1) Reviewed-by: Rodrigo Vivi Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/1511880305-12166-1-git-send-email-valtteri.rantala@intel.com --- drivers/gpu/drm/i915/intel_engine_cs.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index cffd0c812b7e..86d4c85c8725 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1067,6 +1067,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); + /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ + if (IS_GEN9_LP(dev_priv)) { + u32 val = I915_READ(GEN8_L3SQCREG1); + + val &= ~L3_PRIO_CREDITS_MASK; + val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2); + I915_WRITE(GEN8_L3SQCREG1, val); + } + /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | GEN8_LQSC_FLUSH_COHERENT_LINES)); @@ -1184,7 +1193,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine) static int bxt_init_workarounds(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; - u32 val; int ret; ret = gen9_init_workarounds(engine); @@ -1199,12 +1207,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) I915_WRITE(FF_SLICE_CS_CHICKEN2, _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE)); - /* WaProgramL3SqcReg1DefaultForPerf:bxt */ - val = I915_READ(GEN8_L3SQCREG1); - val &= ~L3_PRIO_CREDITS_MASK; - val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2); - I915_WRITE(GEN8_L3SQCREG1, val); - /* WaToEnableHwFixForPushConstHWBug:bxt */ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); -- GitLab From ecf73eb2d27d43b2153bb80671768a06d35521f1 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 30 Nov 2017 10:29:51 +0000 Subject: [PATCH 0359/2547] drm/i915: Skip switch-to-kernel-context on suspend when wedged If the HW is already wedged, attempting to submit a request will generate an -EIO. If we tried this during suspend, we would abort whereas all we want to do is to go sleep and throw away the corrupt state. Fixes: 5ab57c702069 ("drm/i915: Flush logical context image out to memory upon suspend") Testcase: igt/gem_eio/suspend Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171130102951.14965-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 354b0546a191..e083f242b8dc 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4774,17 +4774,19 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv) * state. Fortunately, the kernel_context is disposable and we do * not rely on its state. */ - ret = i915_gem_switch_to_kernel_context(dev_priv); - if (ret) - goto err_unlock; + if (!i915_terminally_wedged(&dev_priv->gpu_error)) { + ret = i915_gem_switch_to_kernel_context(dev_priv); + if (ret) + goto err_unlock; - ret = i915_gem_wait_for_idle(dev_priv, - I915_WAIT_INTERRUPTIBLE | - I915_WAIT_LOCKED); - if (ret && ret != -EIO) - goto err_unlock; + ret = i915_gem_wait_for_idle(dev_priv, + I915_WAIT_INTERRUPTIBLE | + I915_WAIT_LOCKED); + if (ret && ret != -EIO) + goto err_unlock; - assert_kernel_context_is_current(dev_priv); + assert_kernel_context_is_current(dev_priv); + } i915_gem_contexts_lost(dev_priv); mutex_unlock(&dev->struct_mutex); -- GitLab From 5643205c6340b565a3be0fe0e7305dc4aa551c74 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Wed, 29 Nov 2017 19:51:37 +0200 Subject: [PATCH 0360/2547] drm/i915: Avoid PPS HW/SW state mismatch due to rounding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We store a SW state of the t11_t12 timing in 100usec units but have to program it in 100msec as required by HW. The rounding used during programming means there will be a mismatch between the SW and HW states of this value triggering a "PPS state mismatch" error. Avoid this by storing the already rounded-up value in the SW state. Note that we still calculate panel_power_cycle_delay with the finer 100usec granularity to avoid any needless waits using that version of the delay. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103903 Cc: joks Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171129175137.2889-1-imre.deak@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index dd0b3a018792..c603d4c903e1 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5355,6 +5355,12 @@ intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) */ final->t8 = 1; final->t9 = 1; + + /* + * HW has only a 100msec granularity for t11_t12 so round it up + * accordingly. + */ + final->t11_t12 = roundup(final->t11_t12, 100 * 10); } static void -- GitLab From 737e0b7b67bdfe24090fab2852044bb283282fc5 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Wed, 29 Nov 2017 15:32:46 -0600 Subject: [PATCH 0361/2547] ASoC: tlv320aic31xx: Fix GPIO1 register definition GPIO1 control register is number 51, fix this here. Fixes: bafcbfe429eb ("ASoC: tlv320aic31xx: Make the register values human readable") Signed-off-by: Andrew F. Davis Signed-off-by: Mark Brown Cc: stable@vger.kernel.org --- sound/soc/codecs/tlv320aic31xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/tlv320aic31xx.h b/sound/soc/codecs/tlv320aic31xx.h index 730fb2058869..1ff3edb7bbb6 100644 --- a/sound/soc/codecs/tlv320aic31xx.h +++ b/sound/soc/codecs/tlv320aic31xx.h @@ -116,7 +116,7 @@ struct aic31xx_pdata { /* INT2 interrupt control */ #define AIC31XX_INT2CTRL AIC31XX_REG(0, 49) /* GPIO1 control */ -#define AIC31XX_GPIO1 AIC31XX_REG(0, 50) +#define AIC31XX_GPIO1 AIC31XX_REG(0, 51) #define AIC31XX_DACPRB AIC31XX_REG(0, 60) /* ADC Instruction Set Register */ -- GitLab From a154f8e399a063137fc42b961f437248d55ece29 Mon Sep 17 00:00:00 2001 From: Yan Markman Date: Thu, 30 Nov 2017 10:49:46 +0100 Subject: [PATCH 0362/2547] net: mvpp2: allocate zeroed tx descriptors Reserved and unused fields in the Tx descriptors should be 0. The PPv2 driver doesn't clear them at run-time (for performance reasons) but these descriptors aren't zeroed when allocated, which can lead to unpredictable behaviors. This patch fixes this by using dma_zalloc_coherent instead of dma_alloc_coherent. Fixes: 3f518509dedc ("ethernet: Add new driver for Marvell Armada 375 network unit") Signed-off-by: Yan Markman [Antoine: commit message] Signed-off-by: Antoine Tenart Signed-off-by: David S. Miller --- drivers/net/ethernet/marvell/mvpp2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index d83a78be98a2..fed2b2f909fc 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -5598,7 +5598,7 @@ static int mvpp2_aggr_txq_init(struct platform_device *pdev, u32 txq_dma; /* Allocate memory for TX descriptors */ - aggr_txq->descs = dma_alloc_coherent(&pdev->dev, + aggr_txq->descs = dma_zalloc_coherent(&pdev->dev, MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, &aggr_txq->descs_dma, GFP_KERNEL); if (!aggr_txq->descs) -- GitLab From f8821f96ae97260d68228fe53f81848b2ede44d7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 30 Nov 2017 14:33:56 +0100 Subject: [PATCH 0363/2547] skbuff: Grammar s/are can/can/, s/change/changes/ Signed-off-by: Geert Uytterhoeven Signed-off-by: David S. Miller --- include/linux/skbuff.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index bc486ef23f20..a38c80e9f91e 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -1406,8 +1406,7 @@ static inline struct sk_buff *skb_get(struct sk_buff *skb) } /* - * If users == 1, we are the only owner and are can avoid redundant - * atomic change. + * If users == 1, we are the only owner and can avoid redundant atomic changes. */ /** -- GitLab From a158531f3c92467df0e93e000d58185acae78a6e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 21 Nov 2017 15:18:10 +0100 Subject: [PATCH 0364/2547] gpio: 74x164: Fix crash during .remove() Commit 7ebc194d0fd4bb0f ("gpio: 74x164: Introduce 'enable-gpios' property") added a new member gpiod_oe to the end of the struct gen_74x164_chip, after the zero-length buffer array. However, this buffer is a flexible array, allocated together with the structure during .probe(). As the buffer is no longer the last member, writing to it corrupts the newly added member after it. During device removal, the corrupted member will be used as a pointer, leading to a crash. This went unnoticed, as the flexible array was declared as "buffer[0]" instead of "buffer[]", and thus did not trigger a "flexible array member not at end of struct" error from gcc. Move the gpiod_oe field up to fix this, and drop the zero from the array size to prevent future similar bugs. Fixes: 7ebc194d0fd4bb0f ("gpio: 74x164: Introduce 'enable-gpios' property") Signed-off-by: Geert Uytterhoeven Reviewed-by: Fabio Estevam Signed-off-by: Linus Walleij --- drivers/gpio/gpio-74x164.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-74x164.c b/drivers/gpio/gpio-74x164.c index 6b535ec858cc..15a1f4b348c4 100644 --- a/drivers/gpio/gpio-74x164.c +++ b/drivers/gpio/gpio-74x164.c @@ -23,6 +23,7 @@ struct gen_74x164_chip { struct gpio_chip gpio_chip; struct mutex lock; + struct gpio_desc *gpiod_oe; u32 registers; /* * Since the registers are chained, every byte sent will make @@ -31,8 +32,7 @@ struct gen_74x164_chip { * register at the end of the transfer. So, to have a logical * numbering, store the bytes in reverse order. */ - u8 buffer[0]; - struct gpio_desc *gpiod_oe; + u8 buffer[]; }; static int __gen_74x164_write_config(struct gen_74x164_chip *chip) -- GitLab From 793b9184047f3d7fe4fe234a46951dabfc3cfeeb Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 22 Nov 2017 21:04:14 +0100 Subject: [PATCH 0365/2547] pinctrl: gemini: Fix usage of 3512 groups The pin config lookup function was still hardcoding the 3516 pin set, which is obviously wrong. Use the pointer in the state container. Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-gemini.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c index e9b83e291edf..c11b8f14d841 100644 --- a/drivers/pinctrl/pinctrl-gemini.c +++ b/drivers/pinctrl/pinctrl-gemini.c @@ -2322,7 +2322,7 @@ static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx, int i; for (i = 0; i < pmx->nconfs; i++) { - retconf = &gemini_confs_3516[i]; + retconf = &pmx->confs[i]; if (retconf->pin == pin) return retconf; } -- GitLab From 7f8e2a85c1b0bd440ffe87be82c79fdc319e8291 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Fri, 10 Nov 2017 16:43:17 +0530 Subject: [PATCH 0366/2547] gpio: davinci: Assign first bank regs for unbanked case As per the re-design assign the first bank regs for unbanked irq case. This was missed out in the original patch. Signed-off-by: Keerthy Fixes: b5cf3fd827d2e1 ("gpio: davinci: Redesign driver to accommodate ngpios in one gpio chip") Signed-off-by: Linus Walleij --- drivers/gpio/gpio-davinci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index f75d8443ecaf..e4b3d7db68c9 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -383,7 +383,7 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) u32 mask; d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); - g = (struct davinci_gpio_regs __iomem *)d->regs; + g = (struct davinci_gpio_regs __iomem *)d->regs[0]; mask = __gpio_mask(data->irq - d->base_irq); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) -- GitLab From 1c08ac0c4bd8e9d66c4dde29bc496c3b430dd028 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Tue, 28 Nov 2017 17:48:22 +0100 Subject: [PATCH 0367/2547] net: stmmac: dwmac-sun8i: fix allwinner,leds-active-low handling The driver expect "allwinner,leds-active-low" to be in PHY node, but the binding doc expect it to be in MAC node. Since all board DT use it also in MAC node, the driver need to search allwinner,leds-active-low in MAC node. Signed-off-by: Corentin Labbe Signed-off-by: David S. Miller --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index e5ff734d4f9b..9eb7f65d8000 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -808,8 +808,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) val, reg); if (gmac->variant->soc_has_internal_phy) { - if (of_property_read_bool(priv->plat->phy_node, - "allwinner,leds-active-low")) + if (of_property_read_bool(node, "allwinner,leds-active-low")) reg |= H3_EPHY_LED_POL; else reg &= ~H3_EPHY_LED_POL; -- GitLab From 90a6ec85351b31449c2c6b5406b5396ac96f191d Mon Sep 17 00:00:00 2001 From: Cong Wang Date: Wed, 29 Nov 2017 16:07:51 -0800 Subject: [PATCH 0368/2547] act_sample: get rid of tcf_sample_cleanup_rcu() Similar to commit d7fb60b9cafb ("net_sched: get rid of tcfa_rcu"), TC actions don't need to respect RCU grace period, because it is either just detached from tc filter (standalone case) or it is removed together with tc filter (bound case) in which case RCU grace period is already respected at filter layer. Fixes: 5c5670fae430 ("net/sched: Introduce sample tc action") Reported-by: Eric Dumazet Cc: Jamal Hadi Salim Cc: Jiri Pirko Cc: Yotam Gigi Signed-off-by: Cong Wang Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller --- include/net/tc_act/tc_sample.h | 1 - net/sched/act_sample.c | 14 +++----------- 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/include/net/tc_act/tc_sample.h b/include/net/tc_act/tc_sample.h index 524cee4f4c81..01dbfea32672 100644 --- a/include/net/tc_act/tc_sample.h +++ b/include/net/tc_act/tc_sample.h @@ -14,7 +14,6 @@ struct tcf_sample { struct psample_group __rcu *psample_group; u32 psample_group_num; struct list_head tcfm_list; - struct rcu_head rcu; }; #define to_sample(a) ((struct tcf_sample *)a) diff --git a/net/sched/act_sample.c b/net/sched/act_sample.c index 8b5abcd2f32f..9438969290a6 100644 --- a/net/sched/act_sample.c +++ b/net/sched/act_sample.c @@ -96,23 +96,16 @@ static int tcf_sample_init(struct net *net, struct nlattr *nla, return ret; } -static void tcf_sample_cleanup_rcu(struct rcu_head *rcu) +static void tcf_sample_cleanup(struct tc_action *a, int bind) { - struct tcf_sample *s = container_of(rcu, struct tcf_sample, rcu); + struct tcf_sample *s = to_sample(a); struct psample_group *psample_group; - psample_group = rcu_dereference_protected(s->psample_group, 1); + psample_group = rtnl_dereference(s->psample_group); RCU_INIT_POINTER(s->psample_group, NULL); psample_group_put(psample_group); } -static void tcf_sample_cleanup(struct tc_action *a, int bind) -{ - struct tcf_sample *s = to_sample(a); - - call_rcu(&s->rcu, tcf_sample_cleanup_rcu); -} - static bool tcf_sample_dev_ok_push(struct net_device *dev) { switch (dev->type) { @@ -264,7 +257,6 @@ static int __init sample_init_module(void) static void __exit sample_cleanup_module(void) { - rcu_barrier(); tcf_unregister_action(&act_sample_ops, &sample_net_ops); } -- GitLab From 3016dad75b48279e579117ee3ed566ba90a3b023 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 29 Nov 2017 17:43:57 -0800 Subject: [PATCH 0369/2547] tcp: remove buggy call to tcp_v6_restore_cb() tcp_v6_send_reset() expects to receive an skb with skb->cb[] layout as used in TCP stack. MD5 lookup uses tcp_v6_iif() and tcp_v6_sdif() and thus TCP_SKB_CB(skb)->header.h6 This patch probably fixes RST packets sent on behalf of a timewait md5 ipv6 socket. Before Florian patch, tcp_v6_restore_cb() was needed before jumping to no_tcp_socket label. Fixes: 271c3b9b7bda ("tcp: honour SO_BINDTODEVICE for TW_RST case too") Signed-off-by: Eric Dumazet Cc: Florian Westphal Acked-by: Florian Westphal Signed-off-by: David S. Miller --- net/ipv6/tcp_ipv6.c | 1 - 1 file changed, 1 deletion(-) diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c index 6bb98c93edfe..be11dc13aa70 100644 --- a/net/ipv6/tcp_ipv6.c +++ b/net/ipv6/tcp_ipv6.c @@ -1590,7 +1590,6 @@ static int tcp_v6_rcv(struct sk_buff *skb) tcp_v6_timewait_ack(sk, skb); break; case TCP_TW_RST: - tcp_v6_restore_cb(skb); tcp_v6_send_reset(sk, skb); inet_twsk_deschedule_put(inet_twsk(sk)); goto discard_it; -- GitLab From f859b4af1c52493ec21173ccc73d0b60029b5b88 Mon Sep 17 00:00:00 2001 From: Hangbin Liu Date: Thu, 30 Nov 2017 10:41:14 +0800 Subject: [PATCH 0370/2547] sit: update frag_off info After parsing the sit netlink change info, we forget to update frag_off in ipip6_tunnel_update(). Fix it by assigning frag_off with new value. Reported-by: Jianlin Shi Signed-off-by: Hangbin Liu Acked-by: Nicolas Dichtel Signed-off-by: David S. Miller --- net/ipv6/sit.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/ipv6/sit.c b/net/ipv6/sit.c index d60ddcb0bfe2..d7dc23c1b2ca 100644 --- a/net/ipv6/sit.c +++ b/net/ipv6/sit.c @@ -1098,6 +1098,7 @@ static void ipip6_tunnel_update(struct ip_tunnel *t, struct ip_tunnel_parm *p, ipip6_tunnel_link(sitn, t); t->parms.iph.ttl = p->iph.ttl; t->parms.iph.tos = p->iph.tos; + t->parms.iph.frag_off = p->iph.frag_off; if (t->parms.link != p->link || t->fwmark != fwmark) { t->parms.link = p->link; t->fwmark = fwmark; -- GitLab From 6ad4cc8d1ac483e0fd33f605fb2788b0ecf51ed4 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sat, 25 Nov 2017 12:19:48 +0000 Subject: [PATCH 0371/2547] pinctrl: sunxi: Fix A80 interrupt pin bank On the A80 the pins on port B can trigger interrupts, and those are assigned to the second interrupt bank. Having two pins assigned to the same interrupt bank/pin combination does not look healthy (instead more like a copy&paste bug from pins PA14-PA16), so fix the interrupt bank for pins PB14-PB16, which is actually 1. I don't have any A80 board, so could not test this. Fixes: d5e9fb31baa2 ("pinctrl: sunxi: Add A80 pinctrl muxing options") Signed-off-by: Andre Przywara Acked-by: Chen-Yu Tsai Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c index 472ef0d91b99..5553c0eb0f41 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c @@ -145,19 +145,19 @@ static const struct sunxi_desc_pin sun9i_a80_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x3, "mcsi"), /* MCLK */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PB_EINT14 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PB_EINT14 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x3, "mcsi"), /* SCK */ SUNXI_FUNCTION(0x4, "i2c4"), /* SCK */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PB_EINT15 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PB_EINT15 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x3, "mcsi"), /* SDA */ SUNXI_FUNCTION(0x4, "i2c4"), /* SDA */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PB_EINT16 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PB_EINT16 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), -- GitLab From 7c5c2c2d18d778e51fd8b899965097168306031c Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sat, 25 Nov 2017 12:12:30 +0000 Subject: [PATCH 0372/2547] pinctrl: sunxi: Fix A64 UART mux value To use pin PF4 as the RX signal of UART0, we have to write 0b011 into the respective pin controller register. Fix the wrong value we had in our table so far. Fixes: 96851d391d02 ("drivers: pinctrl: add driver for Allwinner A64 SoC") Signed-off-by: Andre Przywara Acked-by: Chen-Yu Tsai Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c index 4f2a726bbaeb..f5f77432ce6f 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c @@ -428,7 +428,7 @@ static const struct sunxi_desc_pin a64_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_FUNCTION(0x3, "uart0")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), -- GitLab From 24f2845056892b297fa95edbddceefd38acc0e62 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Wed, 22 Nov 2017 19:39:01 +0100 Subject: [PATCH 0373/2547] drm/i915: Make ips_enabled a property depending on whether IPS is enabled, v3. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ips_enabled was used as a variable of whether IPS can be enabled or not, but should be used to test whether IPS is actually enabled. Changes since v1: - Call needs_modeset on new crtc state. (Ville) - IPS can be enabled with sprite plane enabled too. (Ville) - Fix CDCLK vs IPS workaround. (Ville) Changes since v2: - Only re-enable fastset when inheriting mode. (Ville) - Put the conditions for enabling and disabling IPS in a helper. Changes since v3: - Keep the max_cdclk workaround working. (Ville) - Also check logical cdclk out of paranoia. - Remove planes check from IPS disable function for initial disable. - Remove assert_plane_enabled/disabled checks and use crtc_state->active_planes for hsw_enable_ips only, always allow calling hsw_disable_ips to disable it initially in hw. Signed-off-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20171122183901.47720-1-maarten.lankhorst@linux.intel.com [mlankhorst: pipe_config -> crtc_state (Ville)] Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 168 ++++++++++++++++---------- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pipe_crc.c | 2 - 4 files changed, 109 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index e8884c2ade98..9c5ceb98d48f 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -1896,7 +1896,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) + if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 76c75d34e799..68f101c0e909 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -489,7 +489,7 @@ static const struct intel_limit intel_limits_bxt = { }; static bool -needs_modeset(struct drm_crtc_state *state) +needs_modeset(const struct drm_crtc_state *state) { return drm_atomic_crtc_needs_modeset(state); } @@ -4833,7 +4833,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - if (!crtc->config->ips_enabled) + if (!crtc_state->ips_enabled) return; /* @@ -4841,8 +4841,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) * This function is called from post_plane_update, which is run after * a vblank wait. */ - - assert_plane_enabled(to_intel_plane(crtc->base.primary)); + WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); if (IS_BROADWELL(dev_priv)) { mutex_lock(&dev_priv->pcu_lock); @@ -4877,8 +4876,6 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state) if (!crtc_state->ips_enabled) return; - assert_plane_enabled(to_intel_plane(crtc->base.primary)); - if (IS_BROADWELL(dev_priv)) { mutex_lock(&dev_priv->pcu_lock); WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); @@ -4931,14 +4928,6 @@ intel_post_enable_primary(struct drm_crtc *crtc, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int pipe = intel_crtc->pipe; - /* - * FIXME IPS should be fine as long as one plane is - * enabled, but in practice it seems to have problems - * when going from primary only to sprite only and vice - * versa. - */ - hsw_enable_ips(new_crtc_state); - /* * Gen2 reports pipe underruns whenever all planes are disabled. * So don't enable underrun reporting before at least some planes @@ -4954,10 +4943,9 @@ intel_post_enable_primary(struct drm_crtc *crtc, intel_check_pch_fifo_underruns(dev_priv); } -/* FIXME move all this to pre_plane_update() with proper state tracking */ +/* FIXME get rid of this and use pre_plane_update */ static void -intel_pre_disable_primary(struct drm_crtc *crtc, - const struct intel_crtc_state *old_crtc_state) +intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -4966,32 +4954,12 @@ intel_pre_disable_primary(struct drm_crtc *crtc, /* * Gen2 reports pipe underruns whenever all planes are disabled. - * So diasble underrun reporting before all the planes get disabled. - * FIXME: Need to fix the logic to work when we turn off all planes - * but leave the pipe running. + * So disable underrun reporting before all the planes get disabled. */ if (IS_GEN2(dev_priv)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); - /* - * FIXME IPS should be fine as long as one plane is - * enabled, but in practice it seems to have problems - * when going from primary only to sprite only and vice - * versa. - */ - hsw_disable_ips(old_crtc_state); -} - -/* FIXME get rid of this and use pre_plane_update */ -static void -intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - int pipe = intel_crtc->pipe; - - intel_pre_disable_primary(crtc, to_intel_crtc_state(crtc->state)); + hsw_disable_ips(to_intel_crtc_state(crtc->state)); /* * Vblank time updates from the shadow to live plane control register @@ -5007,6 +4975,38 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) intel_wait_for_vblank(dev_priv, pipe); } +static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!old_crtc_state->ips_enabled) + return false; + + if (needs_modeset(&new_crtc_state->base)) + return true; + + return !new_crtc_state->ips_enabled; +} + +static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!new_crtc_state->ips_enabled) + return false; + + if (needs_modeset(&new_crtc_state->base)) + return true; + + /* + * We can't read out IPS on broadwell, assume the worst and + * forcibly enable IPS on the first fastset. + */ + if (new_crtc_state->update_pipe && + old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED) + return true; + + return !old_crtc_state->ips_enabled; +} + static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) { struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); @@ -5023,6 +5023,9 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) if (pipe_config->update_wm_post && pipe_config->base.active) intel_update_watermarks(crtc); + if (hsw_post_update_enable_ips(old_crtc_state, pipe_config)) + hsw_enable_ips(pipe_config); + if (old_pri_state) { struct intel_plane_state *primary_state = intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state), @@ -5053,6 +5056,9 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, struct intel_atomic_state *old_intel_state = to_intel_atomic_state(old_state); + if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config)) + hsw_disable_ips(old_crtc_state); + if (old_pri_state) { struct intel_plane_state *primary_state = intel_atomic_get_new_plane_state(old_intel_state, @@ -5061,10 +5067,13 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, to_intel_plane_state(old_pri_state); intel_fbc_pre_update(crtc, pipe_config, primary_state); - - if (old_primary_state->base.visible && + /* + * Gen2 reports pipe underruns whenever all planes are disabled. + * So disable underrun reporting before all the planes get disabled. + */ + if (IS_GEN2(dev_priv) && old_primary_state->base.visible && (modeset || !primary_state->base.visible)) - intel_pre_disable_primary(&crtc->base, old_crtc_state); + intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); } /* @@ -6195,18 +6204,20 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, return ret; } -static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, - struct intel_crtc_state *pipe_config) +bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) { - if (pipe_config->ips_force_disable) + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + + /* IPS only exists on ULT machines and is tied to pipe A. */ + if (!hsw_crtc_supports_ips(crtc)) return false; - if (pipe_config->pipe_bpp > 24) + if (!i915_modparams.enable_ips) return false; - /* HSW can handle pixel rate up to cdclk? */ - if (IS_HASWELL(dev_priv)) - return true; + if (crtc_state->pipe_bpp > 24) + return false; /* * We compare against max which means we must take @@ -6215,19 +6226,41 @@ static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, * * Should measure whether using a lower cdclk w/o IPS */ - return pipe_config->pixel_rate <= - dev_priv->max_cdclk_freq * 95 / 100; + if (IS_BROADWELL(dev_priv) && + crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100) + return false; + + return true; } -static void hsw_compute_ips_config(struct intel_crtc *crtc, - struct intel_crtc_state *pipe_config) +static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = + to_i915(crtc_state->base.crtc->dev); + struct intel_atomic_state *intel_state = + to_intel_atomic_state(crtc_state->base.state); - pipe_config->ips_enabled = i915_modparams.enable_ips && - hsw_crtc_supports_ips(crtc) && - pipe_config_supports_ips(dev_priv, pipe_config); + if (!hsw_crtc_state_ips_capable(crtc_state)) + return false; + + if (crtc_state->ips_force_disable) + return false; + + /* + * FIXME IPS should be fine as long as one plane is + * enabled, but in practice it seems to have problems + * when going from primary only to sprite only and vice + * versa. + */ + if (!(crtc_state->active_planes & BIT(PLANE_PRIMARY))) + return false; + + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ + if (IS_BROADWELL(dev_priv) && + crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100) + return false; + + return true; } static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) @@ -6345,9 +6378,6 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, intel_crtc_compute_pixel_rate(pipe_config); - if (HAS_IPS(dev_priv)) - hsw_compute_ips_config(crtc, pipe_config); - if (pipe_config->has_pch_encoder) return ironlake_fdi_compute_config(crtc, pipe_config); @@ -9183,6 +9213,19 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, ironlake_get_pfit_config(crtc, pipe_config); } + if (hsw_crtc_supports_ips(crtc)) { + if (IS_HASWELL(dev_priv)) + pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE; + else { + /* + * We cannot readout IPS state on broadwell, set to + * true so we can set it to a defined state on first + * commit. + */ + pipe_config->ips_enabled = true; + } + } + if (pipe_config->cpu_transcoder != TRANSCODER_EDP && !transcoder_is_dsi(pipe_config->cpu_transcoder)) { pipe_config->pixel_multiplier = @@ -10435,6 +10478,9 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, pipe_config); } + if (HAS_IPS(dev_priv)) + pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config); + return ret; } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index c679df99d530..64426d3e078e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1488,6 +1488,7 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); bool intel_crtc_active(struct intel_crtc *crtc); +bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); void hsw_enable_ips(const struct intel_crtc_state *crtc_state); void hsw_disable_ips(const struct intel_crtc_state *crtc_state); enum intel_display_power_domain intel_port_to_power_domain(enum port port); diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c index 61641d479b93..1f5cd572a7ff 100644 --- a/drivers/gpu/drm/i915/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c @@ -541,8 +541,6 @@ static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv, * completely disable it. */ pipe_config->ips_force_disable = enable; - if (pipe_config->ips_enabled == enable) - pipe_config->base.connectors_changed = true; } if (IS_HASWELL(dev_priv)) { -- GitLab From adbe5c5cd32c732a4ea1d4c5f41714fa836d69b6 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Wed, 22 Nov 2017 19:39:06 +0100 Subject: [PATCH 0374/2547] drm/i915: Enable IPS with only sprite plane visible too, v4. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This comment predates atomic, and I think with the way we currently track IPS, it's safe to enable this for the case we switch too. Changes since v1: - Keep IPS enabled when switching planes. Changes since v2: - Enable IPS when at least one plane is enabled. (Ville) Changes since v3: - Actually do what was advertised in v3, sigh! (Ville, CI) Signed-off-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20171122183906.47767-1-maarten.lankhorst@linux.intel.com Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 68f101c0e909..601c23be8264 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6246,13 +6246,8 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state) if (crtc_state->ips_force_disable) return false; - /* - * FIXME IPS should be fine as long as one plane is - * enabled, but in practice it seems to have problems - * when going from primary only to sprite only and vice - * versa. - */ - if (!(crtc_state->active_planes & BIT(PLANE_PRIMARY))) + /* IPS should be fine as long as at least one plane is enabled. */ + if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))) return false; /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ -- GitLab From 07c43a382d7de3db01cc28bf2e17ed151cde2046 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sat, 25 Nov 2017 12:02:00 +0000 Subject: [PATCH 0375/2547] pinctrl: sunxi: Disable strict mode for H5 driver All of the H5 boards in the kernel reference the MMC0 CD pin twice in their DT, so strict mode will make the MMC driver fail to load. To keep existing DTs working, disable strict mode in the H5 driver. Signed-off-by: Andre Przywara Reported-by: Chris Obbard Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c index 97b48336f84a..a78d7b922ef4 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c @@ -535,14 +535,16 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = { .pins = sun50i_h5_pins, .npins = ARRAY_SIZE(sun50i_h5_pins), .irq_banks = 2, - .irq_read_needs_mux = true + .irq_read_needs_mux = true, + .disable_strict_mode = true, }; static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = { .pins = sun50i_h5_pins, .npins = ARRAY_SIZE(sun50i_h5_pins), .irq_banks = 3, - .irq_read_needs_mux = true + .irq_read_needs_mux = true, + .disable_strict_mode = true, }; static int sun50i_h5_pinctrl_probe(struct platform_device *pdev) -- GitLab From 770b2edece42fa55bbe7d4cbe53347a07b8968d4 Mon Sep 17 00:00:00 2001 From: Yuyang Du Date: Thu, 30 Nov 2017 10:22:40 +0800 Subject: [PATCH 0376/2547] usbip: Fix USB device hang due to wrong enabling of scatter-gather The previous USB3 SuperSpeed enabling patches mistakenly enabled URB scatter-gather chaining, which is actually not supported by the VHCI HCD. This patch fixes that. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=197867 Fixes: 03cd00d538a6feb ("usbip: vhci-hcd: Set the vhci structure up to work") Reported-by: Juan Zea Signed-off-by: Yuyang Du Cc: stable Acked-by: Shuah Khan Signed-off-by: Greg Kroah-Hartman --- drivers/usb/usbip/vhci_hcd.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/usbip/vhci_hcd.c b/drivers/usb/usbip/vhci_hcd.c index 713e94170963..6b3278c4b72a 100644 --- a/drivers/usb/usbip/vhci_hcd.c +++ b/drivers/usb/usbip/vhci_hcd.c @@ -1098,7 +1098,6 @@ static int hcd_name_to_id(const char *name) static int vhci_setup(struct usb_hcd *hcd) { struct vhci *vhci = *((void **)dev_get_platdata(hcd->self.controller)); - hcd->self.sg_tablesize = ~0; if (usb_hcd_is_primary_hcd(hcd)) { vhci->vhci_hcd_hs = hcd_to_vhci_hcd(hcd); vhci->vhci_hcd_hs->vhci = vhci; -- GitLab From 1ac7c8a78be85f84b019d3d2742d1a9f07255cc5 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Wed, 29 Nov 2017 15:24:22 -0700 Subject: [PATCH 0377/2547] usbip: fix usbip attach to find a port that matches the requested speed usbip attach fails to find a free port when the device on the first port is a USB_SPEED_SUPER device and non-super speed device is being attached. It keeps checking the first port and returns without a match getting stuck in a loop. Fix it check to find the first port with matching speed. Reported-by: Juan Zea Signed-off-by: Shuah Khan Cc: stable Signed-off-by: Greg Kroah-Hartman --- tools/usb/usbip/libsrc/vhci_driver.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/tools/usb/usbip/libsrc/vhci_driver.c b/tools/usb/usbip/libsrc/vhci_driver.c index 5727dfb15a83..8a1cd1616de4 100644 --- a/tools/usb/usbip/libsrc/vhci_driver.c +++ b/tools/usb/usbip/libsrc/vhci_driver.c @@ -329,9 +329,17 @@ int usbip_vhci_refresh_device_list(void) int usbip_vhci_get_free_port(uint32_t speed) { for (int i = 0; i < vhci_driver->nports; i++) { - if (speed == USB_SPEED_SUPER && - vhci_driver->idev[i].hub != HUB_SPEED_SUPER) - continue; + + switch (speed) { + case USB_SPEED_SUPER: + if (vhci_driver->idev[i].hub != HUB_SPEED_SUPER) + continue; + break; + default: + if (vhci_driver->idev[i].hub != HUB_SPEED_HIGH) + continue; + break; + } if (vhci_driver->idev[i].status == VDEV_ST_NULL) return vhci_driver->idev[i].port; -- GitLab From 8d26fdfcb45dc420115b267ac9d6b3ac13457f1b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 30 Nov 2017 14:35:08 +0100 Subject: [PATCH 0378/2547] spi: Fix double "when" Signed-off-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- include/linux/spi/spi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 7b2170bfd6e7..bc6bb325d1bf 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -126,7 +126,7 @@ void spi_statistics_add_transfer_stats(struct spi_statistics *stats, * for that name. This appears in the sysfs "modalias" attribute * for driver coldplugging, and in uevents used for hotplugging * @cs_gpio: gpio number of the chipselect line (optional, -ENOENT when - * when not using a GPIO line) + * not using a GPIO line) * * @statistics: statistics for the spi_device * -- GitLab From 8bd099a71db660f3bd000dd2256032dbf49a6e84 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 30 Nov 2017 12:52:53 +0000 Subject: [PATCH 0379/2547] drm/i915: Tidy up signed/unsigned comparison MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/i915/i915_irq.c|3096 col 29| error: comparison between signed and unsigned integer expressions [-Werror=sign-compare] Signed-off-by: Chris Wilson Cc: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171130125253.21405-1-chris@chris-wilson.co.uk Reviewed-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_irq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 4fb183ae7a07..7cac07db89b9 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3068,7 +3068,7 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) i9xx_pipestat_irq_reset(dev_priv); GEN3_IRQ_RESET(VLV_); - dev_priv->irq_mask = ~0; + dev_priv->irq_mask = ~0u; } static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) @@ -3093,7 +3093,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | I915_LPE_PIPE_C_INTERRUPT; - WARN_ON(dev_priv->irq_mask != ~0); + WARN_ON(dev_priv->irq_mask != ~0u); dev_priv->irq_mask = ~enable_mask; -- GitLab From 2b279419567105d63f1e524bb1ac34ae8f918e5d Mon Sep 17 00:00:00 2001 From: Yonghong Song Date: Thu, 30 Nov 2017 08:52:42 -0800 Subject: [PATCH 0380/2547] tools/bpf: adjust rlimit RLIMIT_MEMLOCK for test_verifier_log The default rlimit RLIMIT_MEMLOCK is 64KB. In certain cases, e.g. in a test machine mimicking our production system, this test may fail due to unable to charge the required memory for prog load: # ./test_verifier_log Test log_level 0... ERROR: Program load returned: ret:-1/errno:1, expected ret:-1/errno:22 Changing the default rlimit RLIMIT_MEMLOCK to unlimited makes the test always pass. Signed-off-by: Yonghong Song Signed-off-by: Daniel Borkmann --- tools/testing/selftests/bpf/test_verifier_log.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tools/testing/selftests/bpf/test_verifier_log.c b/tools/testing/selftests/bpf/test_verifier_log.c index 3cc0b561489e..e9626cf5607a 100644 --- a/tools/testing/selftests/bpf/test_verifier_log.c +++ b/tools/testing/selftests/bpf/test_verifier_log.c @@ -3,6 +3,8 @@ #include #include #include +#include +#include #include #include @@ -131,11 +133,16 @@ static void test_log_bad(char *log, size_t log_len, int log_level) int main(int argc, char **argv) { + struct rlimit limit = { RLIM_INFINITY, RLIM_INFINITY }; char full_log[LOG_SIZE]; char log[LOG_SIZE]; size_t want_len; int i; + /* allow unlimited locked memory to have more consistent error code */ + if (setrlimit(RLIMIT_MEMLOCK, &limit) < 0) + perror("Unable to lift memlock rlimit"); + memset(log, 1, LOG_SIZE); /* Test incorrect attr */ -- GitLab From 6fef90c6b3f6a2b52018e66c0886944ea0c03fcc Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 30 Nov 2017 10:45:26 -0800 Subject: [PATCH 0381/2547] net: dsa: bcm_sf2: Set correct CHAIN_ID and slice number mask When configuring an IPv6 address mask, we should use SLICE_NUM_MASK as the mask in order to make sure all bits are masked by the hardware. Also, we want matching entries to have a CHAIN_ID value set to the same value as the rule index we return to user-space for convenience, so fix that too. Fixes: ba0696c22e7c ("net: dsa: bcm_sf2: Add support for IPv6 CFP rules") Fixes: dd8eff68343d ("net: dsa: bcm_sf2: Allow matching arbitrary IPv6 masks/lengths") Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller --- drivers/net/dsa/bcm_sf2_cfp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/bcm_sf2_cfp.c b/drivers/net/dsa/bcm_sf2_cfp.c index b721a2009b50..23b45da784cb 100644 --- a/drivers/net/dsa/bcm_sf2_cfp.c +++ b/drivers/net/dsa/bcm_sf2_cfp.c @@ -625,7 +625,7 @@ static int bcm_sf2_cfp_ipv6_rule_set(struct bcm_sf2_priv *priv, int port, bcm_sf2_cfp_slice_ipv6(priv, v6_spec->ip6src, v6_spec->psrc, slice_num, false); bcm_sf2_cfp_slice_ipv6(priv, v6_m_spec->ip6src, v6_m_spec->psrc, - slice_num, true); + SLICE_NUM_MASK, true); /* Insert into TCAM now because we need to insert a second rule */ bcm_sf2_cfp_rule_addr_set(priv, rule_index[0]); @@ -699,7 +699,7 @@ static int bcm_sf2_cfp_ipv6_rule_set(struct bcm_sf2_priv *priv, int port, /* Insert into Action and policer RAMs now, set chain ID to * the one we are chained to */ - ret = bcm_sf2_cfp_act_pol_set(priv, rule_index[0], port_num, + ret = bcm_sf2_cfp_act_pol_set(priv, rule_index[1], port_num, queue_num, true); if (ret) goto out_err; -- GitLab From 8935780b9f7bbad0f2eb5dd43f61ba7b509a1575 Mon Sep 17 00:00:00 2001 From: Dennis Dalessandro Date: Tue, 14 Nov 2017 04:34:23 -0800 Subject: [PATCH 0382/2547] IB/hfi1: Initialize bth1 in 16B rc ack builder It is possible the bth1 variable could be used uninitialized so going ahead and giving it a default value. Otherwise we leak stack memory to the network. Fixes: 5b6cabb0db77 ("IB/hfi1: Add 16B RC/UC support") Reviewed-by: Don Hiatt Signed-off-by: Dennis Dalessandro Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/hfi1/rc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/hfi1/rc.c b/drivers/infiniband/hw/hfi1/rc.c index fd01a760259f..af5f7936f7e5 100644 --- a/drivers/infiniband/hw/hfi1/rc.c +++ b/drivers/infiniband/hw/hfi1/rc.c @@ -814,7 +814,7 @@ static inline void hfi1_make_rc_ack_16B(struct rvt_qp *qp, struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); struct hfi1_16b_header *hdr = &opa_hdr->opah; struct ib_other_headers *ohdr; - u32 bth0, bth1; + u32 bth0, bth1 = 0; u16 len, pkey; u8 becn = !!is_fecn; u8 l4 = OPA_16B_L4_IB_LOCAL; -- GitLab From db0acbc475f06c775682ba969ab338e1efa2ae96 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Sun, 19 Nov 2017 19:58:30 +0100 Subject: [PATCH 0383/2547] IB: INFINIBAND should depend on HAS_DMA If NO_DMA=y: ERROR: "bad_dma_ops" [net/sunrpc/xprtrdma/rpcrdma.ko] undefined! ERROR: "bad_dma_ops" [net/smc/smc.ko] undefined! ERROR: "bad_dma_ops" [net/rds/rds_rdma.ko] undefined! ERROR: "bad_dma_ops" [net/9p/9pnet_rdma.ko] undefined! ERROR: "bad_dma_ops" [drivers/nvme/target/nvmet-rdma.ko] undefined! ERROR: "bad_dma_ops" [drivers/nvme/host/nvme-rdma.ko] undefined! ERROR: "bad_dma_ops" [drivers/infiniband/ulp/srpt/ib_srpt.ko] undefined! ERROR: "bad_dma_ops" [drivers/infiniband/ulp/srp/ib_srp.ko] undefined! ERROR: "bad_dma_ops" [drivers/infiniband/ulp/isert/ib_isert.ko] undefined! ERROR: "bad_dma_ops" [drivers/infiniband/ulp/iser/ib_iser.ko] undefined! ERROR: "bad_dma_ops" [drivers/infiniband/ulp/ipoib/ib_ipoib.ko] undefined! ERROR: "bad_dma_ops" [drivers/infiniband/core/ib_core.ko] undefined! Before, this was handled implicitly by the dependency on PCI. Add an explicit dependency on HAS_DMA to fix this. Fixes: 931bc0d91639f8fb ("IB: Move PCI dependency from root KConfig to HW's KConfigs") Signed-off-by: Geert Uytterhoeven Reviewed-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe --- drivers/infiniband/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/Kconfig b/drivers/infiniband/Kconfig index 98ac46ed7214..cbf186522016 100644 --- a/drivers/infiniband/Kconfig +++ b/drivers/infiniband/Kconfig @@ -1,6 +1,6 @@ menuconfig INFINIBAND tristate "InfiniBand support" - depends on HAS_IOMEM + depends on HAS_IOMEM && HAS_DMA depends on NET depends on INET depends on m || IPV6 != m -- GitLab From 208e4ea61437930bbf8785c864ee7af1c693a561 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 30 Oct 2017 00:17:14 +0100 Subject: [PATCH 0384/2547] ARM: dts: meson: correct the sort order for the the gpio_intc node Nodes are sorted by their register start address. Move gpio_intc to the correct position. No functional changes intended. Fixes: 7d32bc03bcfb ("ARM: dts: meson8b: enable gpio interrupt controller") Signed-off-by: Martin Blumenstingl Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 4926133077b3..b750c837ec39 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -85,15 +85,6 @@ reg = <0x7c00 0x200>; }; - gpio_intc: interrupt-controller@9880 { - compatible = "amlogic,meson-gpio-intc"; - reg = <0xc1109880 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - status = "disabled"; - }; - hwrng: rng@8100 { compatible = "amlogic,meson-rng"; reg = <0x8100 0x8>; @@ -191,6 +182,15 @@ status = "disabled"; }; + gpio_intc: interrupt-controller@9880 { + compatible = "amlogic,meson-gpio-intc"; + reg = <0xc1109880 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + status = "disabled"; + }; + wdt: watchdog@9900 { compatible = "amlogic,meson6-wdt"; reg = <0x9900 0x8>; -- GitLab From 9fd7a2e063993a9d47f444147520b9e7fcea4c99 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 30 Oct 2017 00:17:15 +0100 Subject: [PATCH 0385/2547] ARM: dts: meson: fix the memory region of the GPIO interrupt controller commit 200a575b68d2 ("ARM: dts: meson: organize devices in their corresponding busses") organized all peripherals in busses so that the base register offset of the bus doesn't have to be included in all child-nodes anymore. The GPIO interrupt controller however specifies the register offset without subtracting the "cbus" base address. This leads to a problem where of_iomap inside the irq-meson-gpio driver fails because it actually tries to map 0x182209880 (cbus base = 0xc1100000 + 0xc1109880 for the GPIO interrupt controller). Fix this by using 0x9880 as register offset. Fixes: 7d32bc03bcfb ("ARM: dts: meson8b: enable gpio interrupt controller") Signed-off-by: Martin Blumenstingl Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index b750c837ec39..0d9faf1a51ea 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -184,7 +184,7 @@ gpio_intc: interrupt-controller@9880 { compatible = "amlogic,meson-gpio-intc"; - reg = <0xc1109880 0x10>; + reg = <0x9880 0x10>; interrupt-controller; #interrupt-cells = <2>; amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; -- GitLab From 0f0e290a662a89067f7c251d24ad6f63ceb1f2d6 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 2 Nov 2017 09:27:37 +0000 Subject: [PATCH 0386/2547] ARM: meson: fix spelling mistake: "Couln't" -> "Couldn't" Trivial fix to spelling mistake in pr_err error message Signed-off-by: Colin Ian King Acked-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/mach-meson/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c index 2555f9056a33..cad7ee8f0d6b 100644 --- a/arch/arm/mach-meson/platsmp.c +++ b/arch/arm/mach-meson/platsmp.c @@ -102,7 +102,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible, scu_base = of_iomap(node, 0); if (!scu_base) { - pr_err("Couln't map SCU registers\n"); + pr_err("Couldn't map SCU registers\n"); return; } -- GitLab From 044d71bc6cdee8980d0fdc35ec79a0d5818b2ce3 Mon Sep 17 00:00:00 2001 From: Arnaud Patard Date: Wed, 29 Nov 2017 16:09:46 +0100 Subject: [PATCH 0387/2547] meson-gx-socinfo: Fix package id parsing I've noticed the following message while booting a S905X based board: soc soc0: Amlogic Meson GXL (S905D) Revision 21:82 (b:2) Detected The S905D string is obviously wrong. The vendor code does: ... ver = (readl(assist_hw_rev) >> 8) & 0xff; meson_cpu_version[MESON_CPU_VERSION_LVL_MINOR] = ver; ver = (readl(assist_hw_rev) >> 16) & 0xff; meson_cpu_version[MESON_CPU_VERSION_LVL_PACK] = ver; ... while the current code does: ... ... This means that the current mainline code has package id and minor version reversed. Fixes: a9daaba2965e8 ("soc: Add Amlogic SoC Information driver") Signed-off-by: Arnaud Patard Acked-by: Neil Armstrong Signed-off-by: Kevin Hilman --- drivers/soc/amlogic/meson-gx-socinfo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c index 89f4cf507be6..f2d8c3c53ea4 100644 --- a/drivers/soc/amlogic/meson-gx-socinfo.c +++ b/drivers/soc/amlogic/meson-gx-socinfo.c @@ -20,8 +20,8 @@ #define AO_SEC_SOCINFO_OFFSET AO_SEC_SD_CFG8 #define SOCINFO_MAJOR GENMASK(31, 24) -#define SOCINFO_MINOR GENMASK(23, 16) -#define SOCINFO_PACK GENMASK(15, 8) +#define SOCINFO_PACK GENMASK(23, 16) +#define SOCINFO_MINOR GENMASK(15, 8) #define SOCINFO_MISC GENMASK(7, 0) static const struct meson_gx_soc_id { -- GitLab From c8c088ba0edf65044c254b96fc438c91914aaab0 Mon Sep 17 00:00:00 2001 From: Yonghong Song Date: Thu, 30 Nov 2017 13:47:54 -0800 Subject: [PATCH 0388/2547] bpf: set maximum number of attached progs to 64 for a single perf tp cgropu+bpf prog array has a maximum number of 64 programs. Let us apply the same limit here. Fixes: e87c6bc3852b ("bpf: permit multiple bpf attachments for a single perf event") Signed-off-by: Yonghong Song Signed-off-by: Daniel Borkmann --- kernel/bpf/core.c | 3 ++- kernel/trace/bpf_trace.c | 8 ++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c index b9f8686a84cf..86b50aa26ee8 100644 --- a/kernel/bpf/core.c +++ b/kernel/bpf/core.c @@ -1447,7 +1447,8 @@ int bpf_prog_array_length(struct bpf_prog_array __rcu *progs) rcu_read_lock(); prog = rcu_dereference(progs)->progs; for (; *prog; prog++) - cnt++; + if (*prog != &dummy_bpf_prog.prog) + cnt++; rcu_read_unlock(); return cnt; } diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index 27d1f4ffa3de..0ce99c379c30 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -759,6 +759,8 @@ const struct bpf_prog_ops perf_event_prog_ops = { static DEFINE_MUTEX(bpf_event_mutex); +#define BPF_TRACE_MAX_PROGS 64 + int perf_event_attach_bpf_prog(struct perf_event *event, struct bpf_prog *prog) { @@ -772,6 +774,12 @@ int perf_event_attach_bpf_prog(struct perf_event *event, goto unlock; old_array = event->tp_event->prog_array; + if (old_array && + bpf_prog_array_length(old_array) >= BPF_TRACE_MAX_PROGS) { + ret = -E2BIG; + goto unlock; + } + ret = bpf_prog_array_copy(old_array, NULL, prog, &new_array); if (ret < 0) goto unlock; -- GitLab From 0ec9552b43b98deb882bf48efd347be4bd7afc9f Mon Sep 17 00:00:00 2001 From: Yonghong Song Date: Thu, 30 Nov 2017 13:47:55 -0800 Subject: [PATCH 0389/2547] samples/bpf: add error checking for perf ioctl calls in bpf loader load_bpf_file() should fail if ioctl with command PERF_EVENT_IOC_ENABLE and PERF_EVENT_IOC_SET_BPF fails. When they do fail, proper error messages are printed. With this change, the below "syscall_tp" run shows that the maximum number of bpf progs attaching to the same perf tracepoint is indeed enforced. $ ./syscall_tp -i 64 prog #0: map ids 4 5 ... prog #63: map ids 382 383 $ ./syscall_tp -i 65 prog #0: map ids 4 5 ... prog #64: map ids 388 389 ioctl PERF_EVENT_IOC_SET_BPF failed err Argument list too long Signed-off-by: Yonghong Song Signed-off-by: Daniel Borkmann --- samples/bpf/bpf_load.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/samples/bpf/bpf_load.c b/samples/bpf/bpf_load.c index 522ca9252d6c..242631aa4ea2 100644 --- a/samples/bpf/bpf_load.c +++ b/samples/bpf/bpf_load.c @@ -193,8 +193,18 @@ static int load_and_attach(const char *event, struct bpf_insn *prog, int size) return -1; } event_fd[prog_cnt - 1] = efd; - ioctl(efd, PERF_EVENT_IOC_ENABLE, 0); - ioctl(efd, PERF_EVENT_IOC_SET_BPF, fd); + err = ioctl(efd, PERF_EVENT_IOC_ENABLE, 0); + if (err < 0) { + printf("ioctl PERF_EVENT_IOC_ENABLE failed err %s\n", + strerror(errno)); + return -1; + } + err = ioctl(efd, PERF_EVENT_IOC_SET_BPF, fd); + if (err < 0) { + printf("ioctl PERF_EVENT_IOC_SET_BPF failed err %s\n", + strerror(errno)); + return -1; + } return 0; } -- GitLab From e719135881f00c01ca400abb8a5dadaf297a24f9 Mon Sep 17 00:00:00 2001 From: Michal Kubecek Date: Wed, 29 Nov 2017 18:23:56 +0100 Subject: [PATCH 0390/2547] xfrm: fix XFRMA_OUTPUT_MARK policy entry This seems to be an obvious typo, NLA_U32 is type of the attribute, not its (minimal) length. Fixes: 077fbac405bf ("net: xfrm: support setting an output mark.") Signed-off-by: Michal Kubecek Signed-off-by: Steffen Klassert --- net/xfrm/xfrm_user.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c index c2cfcc6fdb34..ff58c37469d6 100644 --- a/net/xfrm/xfrm_user.c +++ b/net/xfrm/xfrm_user.c @@ -2485,7 +2485,7 @@ static const struct nla_policy xfrma_policy[XFRMA_MAX+1] = { [XFRMA_PROTO] = { .type = NLA_U8 }, [XFRMA_ADDRESS_FILTER] = { .len = sizeof(struct xfrm_address_filter) }, [XFRMA_OFFLOAD_DEV] = { .len = sizeof(struct xfrm_user_offload) }, - [XFRMA_OUTPUT_MARK] = { .len = NLA_U32 }, + [XFRMA_OUTPUT_MARK] = { .type = NLA_U32 }, }; static const struct nla_policy xfrma_spd_policy[XFRMA_SPD_MAX+1] = { -- GitLab From 4ce3dbe397d7b6b15f272ae757c78c35e9e4b61d Mon Sep 17 00:00:00 2001 From: Aviv Heller Date: Tue, 28 Nov 2017 19:55:40 +0200 Subject: [PATCH 0391/2547] xfrm: Fix xfrm_input() to verify state is valid when (encap_type < 0) Code path when (encap_type < 0) does not verify the state is valid before progressing. This will result in a crash if, for instance, x->km.state == XFRM_STATE_ACQ. Fixes: 7785bba299a8 ("esp: Add a software GRO codepath") Signed-off-by: Aviv Heller Signed-off-by: Yevgeny Kliteynik Signed-off-by: Steffen Klassert --- net/xfrm/xfrm_input.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/net/xfrm/xfrm_input.c b/net/xfrm/xfrm_input.c index 347ab31574d5..da6447389ffb 100644 --- a/net/xfrm/xfrm_input.c +++ b/net/xfrm/xfrm_input.c @@ -207,7 +207,7 @@ int xfrm_input(struct sk_buff *skb, int nexthdr, __be32 spi, int encap_type) xfrm_address_t *daddr; struct xfrm_mode *inner_mode; u32 mark = skb->mark; - unsigned int family; + unsigned int family = AF_UNSPEC; int decaps = 0; int async = 0; bool xfrm_gro = false; @@ -216,6 +216,16 @@ int xfrm_input(struct sk_buff *skb, int nexthdr, __be32 spi, int encap_type) if (encap_type < 0) { x = xfrm_input_state(skb); + + if (unlikely(x->km.state != XFRM_STATE_VALID)) { + if (x->km.state == XFRM_STATE_ACQ) + XFRM_INC_STATS(net, LINUX_MIB_XFRMACQUIREERROR); + else + XFRM_INC_STATS(net, + LINUX_MIB_XFRMINSTATEINVALID); + goto drop; + } + family = x->outer_mode->afinfo->family; /* An encap_type of -1 indicates async resumption. */ -- GitLab From ddc47e4404b58f03e98345398fb12d38fe291512 Mon Sep 17 00:00:00 2001 From: Steffen Klassert Date: Wed, 29 Nov 2017 06:53:55 +0100 Subject: [PATCH 0392/2547] xfrm: Fix stack-out-of-bounds read on socket policy lookup. When we do tunnel or beet mode, we pass saddr and daddr from the template to xfrm_state_find(), this is ok. On transport mode, we pass the addresses from the flowi, assuming that the IP addresses (and address family) don't change during transformation. This assumption is wrong in the IPv4 mapped IPv6 case, packet is IPv4 and template is IPv6. Fix this by catching address family missmatches of the policy and the flow already before we do the lookup. Reported-by: syzbot Signed-off-by: Steffen Klassert --- net/xfrm/xfrm_policy.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c index 9542975eb2f9..038ec68f6901 100644 --- a/net/xfrm/xfrm_policy.c +++ b/net/xfrm/xfrm_policy.c @@ -1168,9 +1168,15 @@ static struct xfrm_policy *xfrm_sk_policy_lookup(const struct sock *sk, int dir, again: pol = rcu_dereference(sk->sk_policy[dir]); if (pol != NULL) { - bool match = xfrm_selector_match(&pol->selector, fl, family); + bool match; int err = 0; + if (pol->family != family) { + pol = NULL; + goto out; + } + + match = xfrm_selector_match(&pol->selector, fl, family); if (match) { if ((sk->sk_mark & pol->mark.m) != pol->mark.v) { pol = NULL; -- GitLab From 7465894e90e5a47e0e52aa5f1f708653fc40020f Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 30 Nov 2017 17:00:30 +0000 Subject: [PATCH 0393/2547] KVM: arm/arm64: Fix spinlock acquisition in vgic_set_owner vgic_set_owner acquires the irq lock without disabling interrupts, resulting in a lockdep splat (an interrupt could fire and result in the same lock being taken if the same virtual irq is to be injected). In practice, it is almost impossible to trigger this bug, but better safe than sorry. Convert the lock acquisition to a spin_lock_irqsave() and keep lockdep happy. Reported-by: James Morse Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic/vgic.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c index 786cce7bd2ec..ecb8e25f5fe5 100644 --- a/virt/kvm/arm/vgic/vgic.c +++ b/virt/kvm/arm/vgic/vgic.c @@ -492,6 +492,7 @@ int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid) int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner) { struct vgic_irq *irq; + unsigned long flags; int ret = 0; if (!vgic_initialized(vcpu->kvm)) @@ -502,12 +503,12 @@ int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner) return -EINVAL; irq = vgic_get_irq(vcpu->kvm, vcpu, intid); - spin_lock(&irq->irq_lock); + spin_lock_irqsave(&irq->irq_lock, flags); if (irq->owner && irq->owner != owner) ret = -EEXIST; else irq->owner = owner; - spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&irq->irq_lock, flags); return ret; } -- GitLab From 6b2ad81bcfedaf36ceb8e6e71a58ad4ebd716313 Mon Sep 17 00:00:00 2001 From: Andrew Jones Date: Mon, 27 Nov 2017 19:17:18 +0100 Subject: [PATCH 0394/2547] KVM: arm/arm64: kvm_arch_destroy_vm cleanups kvm_vgic_vcpu_destroy already gets called from kvm_vgic_destroy for each vcpu, so we don't have to call it from kvm_arch_vcpu_free. Additionally the other architectures set kvm->online_vcpus to zero after freeing them. We might as well do that for ARM too. Signed-off-by: Andrew Jones Signed-off-by: Christoffer Dall --- virt/kvm/arm/arm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index ca65d06b38a8..675844c2174a 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -188,6 +188,7 @@ void kvm_arch_destroy_vm(struct kvm *kvm) kvm->vcpus[i] = NULL; } } + atomic_set(&kvm->online_vcpus, 0); } int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) @@ -296,7 +297,6 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) { kvm_mmu_free_memory_caches(vcpu); kvm_timer_vcpu_terminate(vcpu); - kvm_vgic_vcpu_destroy(vcpu); kvm_pmu_vcpu_destroy(vcpu); kvm_vcpu_uninit(vcpu); kmem_cache_free(kvm_vcpu_cache, vcpu); -- GitLab From 56075f6072e7fdac302cff4e1b4c93b64ced99ab Mon Sep 17 00:00:00 2001 From: Daniel Axtens Date: Sun, 26 Nov 2017 15:34:04 +1100 Subject: [PATCH 0395/2547] HID: holtekff: move MODULE_* parameters out of #ifdef block If you compile with: CONFIG_HID_HOLTEK=m CONFIG_HOLTEK_FF is not set You get the following warning: WARNING: modpost: missing MODULE_LICENSE() in drivers/hid/hid-holtekff.o see include/linux/module.h for more information Fix this by moving the module info out of the #ifdef CONFIG_HOLTEK_FF block and into the un-guarded part of the file. Signed-off-by: Daniel Axtens Acked-by: Anssi Hannula Reviewed-by: Benjamin Tissoires Signed-off-by: Jiri Kosina --- drivers/hid/hid-holtekff.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/hid/hid-holtekff.c b/drivers/hid/hid-holtekff.c index 9325545fc3ae..edc0f64bb584 100644 --- a/drivers/hid/hid-holtekff.c +++ b/drivers/hid/hid-holtekff.c @@ -32,10 +32,6 @@ #ifdef CONFIG_HOLTEK_FF -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Anssi Hannula "); -MODULE_DESCRIPTION("Force feedback support for Holtek On Line Grip based devices"); - /* * These commands and parameters are currently known: * @@ -223,3 +219,7 @@ static struct hid_driver holtek_driver = { .probe = holtek_probe, }; module_hid_driver(holtek_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Anssi Hannula "); +MODULE_DESCRIPTION("Force feedback support for Holtek On Line Grip based devices"); -- GitLab From b5e0a9418e09a7b6df1728a26832c7c34aa1adf8 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 1 Dec 2017 00:15:36 +0000 Subject: [PATCH 0396/2547] drm/i915: Set fake_vma.size as well as fake_vma.node.size for capture When capturing the bo, we allocate an error object with an array of min(vma->size, vma->node.size) pages, plus a bit for compression overhead. However, when creating the fake vma to describe the bo, only one of the sizes was filled in, resulting in a too small array. Through my and CI testing, this was sufficient for the mostly empty NULL context as it compressed well (or the out-of-bounds access simply didn't cause an issue). However, in real workloads on Cannonlake, we were overflowing that array and causing havoc with the random memory corruption. Reported-by: Rafael Antognolli Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103964 Fixes: 4e90a6e22272 ("drm/i915: Record default HW state in the GPU error state") Signed-off-by: Chris Wilson Cc: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Tested-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20171201001536.13941-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gpu_error.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 876be8f1d930..48418fb81066 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1424,6 +1424,7 @@ capture_object(struct drm_i915_private *dev_priv, if (obj && i915_gem_object_has_pages(obj)) { struct i915_vma fake = { .node = { .start = U64_MAX, .size = obj->base.size }, + .size = obj->base.size, .pages = obj->mm.pages, .obj = obj, }; -- GitLab From 435019b48033138581a6171093b181fc6b4d3d30 Mon Sep 17 00:00:00 2001 From: Jimmy Assarsson Date: Tue, 21 Nov 2017 08:22:26 +0100 Subject: [PATCH 0397/2547] can: kvaser_usb: free buf in error paths The allocated buffer was not freed if usb_submit_urb() failed. Signed-off-by: Jimmy Assarsson Cc: linux-stable Signed-off-by: Marc Kleine-Budde --- drivers/net/can/usb/kvaser_usb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/can/usb/kvaser_usb.c b/drivers/net/can/usb/kvaser_usb.c index 9b18d96ef526..075644591498 100644 --- a/drivers/net/can/usb/kvaser_usb.c +++ b/drivers/net/can/usb/kvaser_usb.c @@ -813,6 +813,7 @@ static int kvaser_usb_simple_msg_async(struct kvaser_usb_net_priv *priv, if (err) { netdev_err(netdev, "Error transmitting URB\n"); usb_unanchor_urb(urb); + kfree(buf); usb_free_urb(urb); return err; } @@ -1768,6 +1769,7 @@ static netdev_tx_t kvaser_usb_start_xmit(struct sk_buff *skb, spin_unlock_irqrestore(&priv->tx_contexts_lock, flags); usb_unanchor_urb(urb); + kfree(buf); stats->tx_dropped++; -- GitLab From e84f44eb5523401faeb9cc1c97895b68e3cfb78d Mon Sep 17 00:00:00 2001 From: Jimmy Assarsson Date: Tue, 21 Nov 2017 08:22:27 +0100 Subject: [PATCH 0398/2547] can: kvaser_usb: Fix comparison bug in kvaser_usb_read_bulk_callback() The conditon in the while-loop becomes true when actual_length is less than 2 (MSG_HEADER_LEN). In best case we end up with a former, already dispatched msg, that got msg->len greater than actual_length. This will result in a "Format error" error printout. Problem seen when unplugging a Kvaser USB device connected to a vbox guest. warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Signed-off-by: Jimmy Assarsson Cc: linux-stable Signed-off-by: Marc Kleine-Budde --- drivers/net/can/usb/kvaser_usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/can/usb/kvaser_usb.c b/drivers/net/can/usb/kvaser_usb.c index 075644591498..d87e330a20b3 100644 --- a/drivers/net/can/usb/kvaser_usb.c +++ b/drivers/net/can/usb/kvaser_usb.c @@ -1334,7 +1334,7 @@ static void kvaser_usb_read_bulk_callback(struct urb *urb) goto resubmit_urb; } - while (pos <= urb->actual_length - MSG_HEADER_LEN) { + while (pos <= (int)(urb->actual_length - MSG_HEADER_LEN)) { msg = urb->transfer_buffer + pos; /* The Kvaser firmware can only read and write messages that -- GitLab From 8bd13bd522ff7dfa0eb371921aeb417155f7a3be Mon Sep 17 00:00:00 2001 From: Jimmy Assarsson Date: Tue, 21 Nov 2017 08:22:28 +0100 Subject: [PATCH 0399/2547] can: kvaser_usb: ratelimit errors if incomplete messages are received Avoid flooding the kernel log with "Formate error", if incomplete message are received. Signed-off-by: Jimmy Assarsson Cc: linux-stable Signed-off-by: Marc Kleine-Budde --- drivers/net/can/usb/kvaser_usb.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/can/usb/kvaser_usb.c b/drivers/net/can/usb/kvaser_usb.c index d87e330a20b3..f95945915d20 100644 --- a/drivers/net/can/usb/kvaser_usb.c +++ b/drivers/net/can/usb/kvaser_usb.c @@ -609,8 +609,8 @@ static int kvaser_usb_wait_msg(const struct kvaser_usb *dev, u8 id, } if (pos + tmp->len > actual_len) { - dev_err(dev->udev->dev.parent, - "Format error\n"); + dev_err_ratelimited(dev->udev->dev.parent, + "Format error\n"); break; } @@ -1353,7 +1353,8 @@ static void kvaser_usb_read_bulk_callback(struct urb *urb) } if (pos + msg->len > urb->actual_length) { - dev_err(dev->udev->dev.parent, "Format error\n"); + dev_err_ratelimited(dev->udev->dev.parent, + "Format error\n"); break; } -- GitLab From f6c23b174c3c96616514827407769cbcfc8005cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Oliver=20St=C3=A4bler?= Date: Mon, 20 Nov 2017 14:45:15 +0100 Subject: [PATCH 0400/2547] can: ti_hecc: Fix napi poll return value for repoll MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After commit d75b1ade567f ("net: less interrupt masking in NAPI") napi repoll is done only when work_done == budget. So we need to return budget if there are still packets to receive. Signed-off-by: Oliver Stäbler Cc: linux-stable Signed-off-by: Marc Kleine-Budde --- drivers/net/can/ti_hecc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/can/ti_hecc.c b/drivers/net/can/ti_hecc.c index 4d4941469cfc..db6ea936dc3f 100644 --- a/drivers/net/can/ti_hecc.c +++ b/drivers/net/can/ti_hecc.c @@ -637,6 +637,9 @@ static int ti_hecc_rx_poll(struct napi_struct *napi, int quota) mbx_mask = hecc_read(priv, HECC_CANMIM); mbx_mask |= HECC_TX_MBOX_MASK; hecc_write(priv, HECC_CANMIM, mbx_mask); + } else { + /* repoll is done only if whole budget is used */ + num_pkts = quota; } return num_pkts; -- GitLab From 5c2cb02edf79ad79d9b8d07c6d52243a948c4c9f Mon Sep 17 00:00:00 2001 From: Stephane Grosjean Date: Thu, 23 Nov 2017 15:44:35 +0100 Subject: [PATCH 0401/2547] can: peak/pci: fix potential bug when probe() fails PCI/PCIe drivers for PEAK-System CAN/CAN-FD interfaces do some access to the PCI config during probing. In case one of these accesses fails, a POSITIVE PCIBIOS_xxx error code is returned back. This POSITIVE error code MUST be converted into a NEGATIVE errno for the probe() function to indicate it failed. Using the pcibios_err_to_errno() function, we make sure that the return code will always be negative. Signed-off-by: Stephane Grosjean Cc: linux-stable Signed-off-by: Marc Kleine-Budde --- drivers/net/can/peak_canfd/peak_pciefd_main.c | 5 ++++- drivers/net/can/sja1000/peak_pci.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/can/peak_canfd/peak_pciefd_main.c b/drivers/net/can/peak_canfd/peak_pciefd_main.c index b4efd711f824..788c3464a3b0 100644 --- a/drivers/net/can/peak_canfd/peak_pciefd_main.c +++ b/drivers/net/can/peak_canfd/peak_pciefd_main.c @@ -825,7 +825,10 @@ static int peak_pciefd_probe(struct pci_dev *pdev, err_disable_pci: pci_disable_device(pdev); - return err; + /* pci_xxx_config_word() return positive PCIBIOS_xxx error codes while + * the probe() function must return a negative errno in case of failure + * (err is unchanged if negative) */ + return pcibios_err_to_errno(err); } /* free the board structure object, as well as its resources: */ diff --git a/drivers/net/can/sja1000/peak_pci.c b/drivers/net/can/sja1000/peak_pci.c index 131026fbc2d7..5adc95c922ee 100644 --- a/drivers/net/can/sja1000/peak_pci.c +++ b/drivers/net/can/sja1000/peak_pci.c @@ -717,7 +717,10 @@ static int peak_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) failure_disable_pci: pci_disable_device(pdev); - return err; + /* pci_xxx_config_word() return positive PCIBIOS_xxx error codes while + * the probe() function must return a negative errno in case of failure + * (err is unchanged if negative) */ + return pcibios_err_to_errno(err); } static void peak_pci_remove(struct pci_dev *pdev) -- GitLab From 658f534c036352a06584c8b2e71a547915173ba9 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 22 Nov 2017 13:01:08 +0100 Subject: [PATCH 0402/2547] can: flexcan: Update IRQ Err Passive information The flexcan IP cores used on MX25 and MX35 do not generate Error Passive IRQs. Update the IP core overview table in the driver accordingly. Suggested-by: ZHU Yi (ST-FIR/ENG1-Zhu) Signed-off-by: Marc Kleine-Budde --- drivers/net/can/flexcan.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c index a13a4896a8bd..eefddae2e99a 100644 --- a/drivers/net/can/flexcan.c +++ b/drivers/net/can/flexcan.c @@ -184,9 +184,9 @@ * Below is some version info we got: * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re- * Filter? connected? Passive detection ception in MB - * MX25 FlexCAN2 03.00.00.00 no no ? no no + * MX25 FlexCAN2 03.00.00.00 no no no no no * MX28 FlexCAN2 03.00.04.00 yes yes no no no - * MX35 FlexCAN2 03.00.00.00 no no ? no no + * MX35 FlexCAN2 03.00.00.00 no no no no no * MX53 FlexCAN2 03.00.00.00 yes no no no no * MX6s FlexCAN3 10.00.12.00 yes yes no no yes * VF610 FlexCAN3 ? no yes ? yes yes? -- GitLab From 29c64b17a0bc72232acc45e9533221d88a262efb Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Mon, 27 Nov 2017 09:18:21 +0100 Subject: [PATCH 0403/2547] can: flexcan: fix VF610 state transition issue Enable FLEXCAN_QUIRK_BROKEN_PERR_STATE for VF610 to report correct state transitions. Tested-by: Mirza Krak Cc: linux-stable # >= v4.11 Signed-off-by: Marc Kleine-Budde --- drivers/net/can/flexcan.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c index eefddae2e99a..0626dcfd1f3d 100644 --- a/drivers/net/can/flexcan.c +++ b/drivers/net/can/flexcan.c @@ -189,7 +189,7 @@ * MX35 FlexCAN2 03.00.00.00 no no no no no * MX53 FlexCAN2 03.00.00.00 yes no no no no * MX6s FlexCAN3 10.00.12.00 yes yes no no yes - * VF610 FlexCAN3 ? no yes ? yes yes? + * VF610 FlexCAN3 ? no yes no yes yes? * * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. */ @@ -297,7 +297,8 @@ static const struct flexcan_devtype_data fsl_imx6q_devtype_data = { static const struct flexcan_devtype_data fsl_vf610_devtype_data = { .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | - FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP, + FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | + FLEXCAN_QUIRK_BROKEN_PERR_STATE, }; static const struct can_bittiming_const flexcan_bittiming_const = { -- GitLab From 3fed8dbbc42c0639ac03d2361ab5f0606dd49e28 Mon Sep 17 00:00:00 2001 From: Martin Kelly Date: Mon, 27 Nov 2017 15:49:15 -0800 Subject: [PATCH 0404/2547] can: mcba_usb: fix typo Fix typo "analizer" --> "Analyzer". Signed-off-by: Martin Kelly Signed-off-by: Marc Kleine-Budde --- drivers/net/can/usb/mcba_usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/can/usb/mcba_usb.c b/drivers/net/can/usb/mcba_usb.c index 7f0272558bef..c4355f0a20d5 100644 --- a/drivers/net/can/usb/mcba_usb.c +++ b/drivers/net/can/usb/mcba_usb.c @@ -862,7 +862,7 @@ static int mcba_usb_probe(struct usb_interface *intf, goto cleanup_unregister_candev; } - dev_info(&intf->dev, "Microchip CAN BUS analizer connected\n"); + dev_info(&intf->dev, "Microchip CAN BUS Analyzer connected\n"); return 0; -- GitLab From 1cb35a33a28394fd711bb26ddf3a564f4e9d9125 Mon Sep 17 00:00:00 2001 From: Martin Kelly Date: Mon, 27 Nov 2017 15:49:16 -0800 Subject: [PATCH 0405/2547] can: mcba_usb: fix device disconnect bug Currently, when you disconnect the device, the driver infinitely resubmits all URBs, so you see: Rx URB aborted (-32) in an infinite loop. Fix this by catching -EPIPE (what we get in urb->status when the device disconnects) and not resubmitting. With this patch, I can plug and unplug many times and the driver recovers correctly. Signed-off-by: Martin Kelly Cc: linux-stable Signed-off-by: Marc Kleine-Budde --- drivers/net/can/usb/mcba_usb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/can/usb/mcba_usb.c b/drivers/net/can/usb/mcba_usb.c index c4355f0a20d5..ef417dcddbf7 100644 --- a/drivers/net/can/usb/mcba_usb.c +++ b/drivers/net/can/usb/mcba_usb.c @@ -592,6 +592,7 @@ static void mcba_usb_read_bulk_callback(struct urb *urb) break; case -ENOENT: + case -EPIPE: case -ESHUTDOWN: return; -- GitLab From b37aef5f1b5a4788eca662de6cb33e1521a7e404 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 30 Nov 2017 09:42:31 +0000 Subject: [PATCH 0406/2547] drm/i915/selftests: Wake the device before executing requests on the GPU To execute a requests requires us to have first woken the device, using the rpm wakeref (as the request needs to write to hardware to setup the context/ppGTT and execute on the GPU). So call intel_runtime_pm_get() around queuing the request; the request itself will then carry a wakeref until completion. References: https://bugs.freedesktop.org/show_bug.cgi?id=103994 Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20171130094231.10405-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/selftests/i915_gem_context.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index ec1eff739e01..56a803d11916 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -376,7 +376,9 @@ static int igt_ctx_exec(void *arg) } } + intel_runtime_pm_get(i915); err = gpu_fill(obj, ctx, engine, dw); + intel_runtime_pm_put(i915); if (err) { pr_err("Failed to fill dword %lu [%lu/%lu] with gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n", ndwords, dw, max_dwords(obj), -- GitLab From fe77d8257c4d838c5976557ddb87bd789f312412 Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Wed, 29 Nov 2017 10:25:02 +0100 Subject: [PATCH 0407/2547] batman-adv: Always initialize fragment header priority The batman-adv unuicast fragment header contains 3 bits for the priority of the packet. These bits will be initialized when the skb->priority contains a value between 256 and 263. But otherwise, the uninitialized bits from the stack will be used. Fixes: c0f25c802b33 ("batman-adv: Include frame priority in fragment header") Signed-off-by: Sven Eckelmann Signed-off-by: Simon Wunderlich --- net/batman-adv/fragmentation.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/batman-adv/fragmentation.c b/net/batman-adv/fragmentation.c index a98cf1104a30..ebe6e38934e4 100644 --- a/net/batman-adv/fragmentation.c +++ b/net/batman-adv/fragmentation.c @@ -499,6 +499,8 @@ int batadv_frag_send_packet(struct sk_buff *skb, */ if (skb->priority >= 256 && skb->priority <= 263) frag_header.priority = skb->priority - 256; + else + frag_header.priority = 0; ether_addr_copy(frag_header.orig, primary_if->net_dev->dev_addr); ether_addr_copy(frag_header.dest, orig_node->orig); -- GitLab From 198a62ddffa4a4ffaeb741f642b7b52f2d91ae9b Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Wed, 29 Nov 2017 10:50:42 +0100 Subject: [PATCH 0408/2547] batman-adv: Fix check of retrieved orig_gw in batadv_v_gw_is_eligible The batadv_v_gw_is_eligible function already assumes that orig_node is not NULL. But batadv_gw_node_get may have failed to find the originator. It must therefore be checked whether the batadv_gw_node_get failed and not whether orig_node is NULL to detect this error. Fixes: 50164d8f500f ("batman-adv: B.A.T.M.A.N. V - implement GW selection logic") Signed-off-by: Sven Eckelmann Acked-by: Antonio Quartulli Signed-off-by: Simon Wunderlich --- net/batman-adv/bat_v.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/batman-adv/bat_v.c b/net/batman-adv/bat_v.c index 341ceab8338d..e0e2bfcd6b3e 100644 --- a/net/batman-adv/bat_v.c +++ b/net/batman-adv/bat_v.c @@ -814,7 +814,7 @@ static bool batadv_v_gw_is_eligible(struct batadv_priv *bat_priv, } orig_gw = batadv_gw_node_get(bat_priv, orig_node); - if (!orig_node) + if (!orig_gw) goto out; if (batadv_v_gw_throughput_get(orig_gw, &orig_throughput) < 0) -- GitLab From 23f1b8d938c861ee0bbb786162f7ce0685f722ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Date: Mon, 20 Nov 2017 10:55:15 +0100 Subject: [PATCH 0409/2547] fw_cfg: fix driver remove MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On driver remove(), all objects created during probe() should be removed, but sysfs qemu_fw_cfg/rev file was left. Also reorder functions to match probe() error cleanup code. Cc: stable@vger.kernel.org Signed-off-by: Marc-André Lureau Signed-off-by: Michael S. Tsirkin --- drivers/firmware/qemu_fw_cfg.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/qemu_fw_cfg.c b/drivers/firmware/qemu_fw_cfg.c index 5cfe39f7a45f..deb483064f53 100644 --- a/drivers/firmware/qemu_fw_cfg.c +++ b/drivers/firmware/qemu_fw_cfg.c @@ -582,9 +582,10 @@ static int fw_cfg_sysfs_remove(struct platform_device *pdev) { pr_debug("fw_cfg: unloading.\n"); fw_cfg_sysfs_cache_cleanup(); + sysfs_remove_file(fw_cfg_top_ko, &fw_cfg_rev_attr.attr); + fw_cfg_io_cleanup(); fw_cfg_kset_unregister_recursive(fw_cfg_fname_kset); fw_cfg_kobj_cleanup(fw_cfg_sel_ko); - fw_cfg_io_cleanup(); return 0; } -- GitLab From e60ea67bb60459b95a50a156296041a13e0e380e Mon Sep 17 00:00:00 2001 From: weiping zhang Date: Wed, 29 Nov 2017 09:23:01 +0800 Subject: [PATCH 0410/2547] virtio: release virtio index when fail to device_register index can be reused by other virtio device. Cc: stable@vger.kernel.org Signed-off-by: weiping zhang Reviewed-by: Cornelia Huck Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/virtio/virtio.c b/drivers/virtio/virtio.c index 48230a5e12f2..bf7ff3934d7f 100644 --- a/drivers/virtio/virtio.c +++ b/drivers/virtio/virtio.c @@ -333,6 +333,8 @@ int register_virtio_device(struct virtio_device *dev) /* device_register() causes the bus infrastructure to look for a * matching driver. */ err = device_register(&dev->dev); + if (err) + ida_simple_remove(&virtio_index_ida, dev->index); out: if (err) virtio_add_status(dev, VIRTIO_CONFIG_S_FAILED); -- GitLab From d9e427f6ab8142d6868eb719e6a7851aafea56b6 Mon Sep 17 00:00:00 2001 From: Jan Stancek Date: Fri, 1 Dec 2017 10:50:28 +0100 Subject: [PATCH 0411/2547] virtio_balloon: fix increment of vb->num_pfns in fill_balloon() commit c7cdff0e8647 ("virtio_balloon: fix deadlock on OOM") changed code to increment vb->num_pfns before call to set_page_pfns(), which used to happen only after. This patch fixes boot hang for me on ppc64le KVM guests. Fixes: c7cdff0e8647 ("virtio_balloon: fix deadlock on OOM") Cc: Michael S. Tsirkin Cc: Tetsuo Handa Cc: Michal Hocko Cc: Wei Wang Cc: stable@vger.kernel.org Signed-off-by: Jan Stancek Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_balloon.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/virtio/virtio_balloon.c b/drivers/virtio/virtio_balloon.c index 7960746f7597..a1fb52cb3f0a 100644 --- a/drivers/virtio/virtio_balloon.c +++ b/drivers/virtio/virtio_balloon.c @@ -174,13 +174,12 @@ static unsigned fill_balloon(struct virtio_balloon *vb, size_t num) while ((page = balloon_page_pop(&pages))) { balloon_page_enqueue(&vb->vb_dev_info, page); - vb->num_pfns += VIRTIO_BALLOON_PAGES_PER_PAGE; - set_page_pfns(vb, vb->pfns + vb->num_pfns, page); vb->num_pages += VIRTIO_BALLOON_PAGES_PER_PAGE; if (!virtio_has_feature(vb->vdev, VIRTIO_BALLOON_F_DEFLATE_ON_OOM)) adjust_managed_page_count(page, -1); + vb->num_pfns += VIRTIO_BALLOON_PAGES_PER_PAGE; } num_allocated_pages = vb->num_pfns; -- GitLab From 20ff39fa4312dfaee8d1314a208e6a5a3ee51cbc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 29 Nov 2017 18:43:01 +0200 Subject: [PATCH 0412/2547] drm/i915: Disable DP audio for g4x MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Apparently g4x doesn't support audio over DP. Bspec lists the bit as "Reserved for Audio Output Enable", and empirical evidence tells us that the bit won't stick. So stop trying to enable DP audio on g4x. Link: https://patchwork.freedesktop.org/patch/msgid/20171129164303.18793-1-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103989 Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c603d4c903e1..01c848bbd795 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1643,7 +1643,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, pipe_config->has_pch_encoder = true; pipe_config->has_drrs = false; - if (port == PORT_A) + if (IS_G4X(dev_priv) || port == PORT_A) pipe_config->has_audio = false; else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) pipe_config->has_audio = intel_dp->has_audio; -- GitLab From 68ec0736a00d38f2ac4907ffe8ad141ead15c075 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 29 Nov 2017 18:43:02 +0200 Subject: [PATCH 0413/2547] drm/i915: Don't add the "force audio" property to DP connectors that don't support audio MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No point in adding the "force audio" property to DP connectors that don't support audio (g4x or port A). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171129164303.18793-2-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 01c848bbd795..bf93991c2fcc 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5180,8 +5180,11 @@ static void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->dev); + enum port port = dp_to_dig_port(intel_dp)->base.port; + + if (!IS_G4X(dev_priv) && port != PORT_A) + intel_attach_force_audio_property(connector); - intel_attach_force_audio_property(connector); intel_attach_broadcast_rgb_property(connector); if (intel_dp_is_edp(intel_dp)) { -- GitLab From 2085cc5d3ccdc804eb320d1403be31cf28650552 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 29 Nov 2017 18:43:03 +0200 Subject: [PATCH 0414/2547] drm/i915: Fix has_audio readout for DDI A MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Transcoder EDP does not support audio. Let's not try to read the state of the audio enable bit HSW_AUD_PIN_ELD_CP_VLD based on the pipe when using transcoder EDP. While at it make the function static and flatten it. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171129164303.18793-3-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++---------- drivers/gpu/drm/i915/intel_drv.h | 2 -- 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index eff3b51872eb..48ba9b7fdc78 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2513,17 +2513,17 @@ void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) udelay(600); } -bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, - struct intel_crtc *intel_crtc) +static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder) { - u32 temp; + if (cpu_transcoder == TRANSCODER_EDP) + return false; - if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { - temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); - if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) - return true; - } - return false; + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) + return false; + + return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) & + AUDIO_OUTPUT_ENABLE(cpu_transcoder); } void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, @@ -2616,7 +2616,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, } pipe_config->has_audio = - intel_ddi_is_audio_enabled(dev_priv, intel_crtc); + intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 64426d3e078e..82d637d20d5d 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1288,8 +1288,6 @@ intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state); void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state); void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp); bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); -bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, - struct intel_crtc *intel_crtc); void intel_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config); -- GitLab From 5816d9cbc0a0fbf232fe297cefcb85361a3cde90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 29 Nov 2017 14:54:11 +0200 Subject: [PATCH 0415/2547] drm/i915: Fix deadlock in i830_disable_pipe() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit i830_disable_pipe() gets called from the power well code, and thus we're already holding the power domain mutex. That means we can't call plane->get_hw_state() as it will also try to grab the same mutex and will thus deadlock. Replace the assert_plane() calls (which calls ->get_hw_state()) with just raw register reads in i830_disable_pipe(). As a bonus we can now get a warning if plane C is enabled even though we don't even expose it as a drm plane. v2: Do a separate WARN_ON() for each plane (Chris) Cc: Chris Wilson Reviewed-by: Chris Wilson Fixes: 51f5a0963984 ("drm/i915: Add .get_hw_state() method for planes") Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171129125411.29055-1-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 601c23be8264..7a1f60869b24 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14770,8 +14770,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n", pipe_name(pipe)); - assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_A)); - assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_B)); + WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE); + WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE); + WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE); + WARN_ON(I915_READ(CURCNTR(PIPE_A)) & CURSOR_MODE); + WARN_ON(I915_READ(CURCNTR(PIPE_B)) & CURSOR_MODE); I915_WRITE(PIPECONF(pipe), 0); POSTING_READ(PIPECONF(pipe)); -- GitLab From 8fedd64dabc86d0f31a0d1e152be3aa23c323553 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 29 Nov 2017 17:37:30 +0200 Subject: [PATCH 0416/2547] drm/i915: Fix vblank timestamp/frame counter jumps on gen2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Previously I was under the impression that the scanline counter reads 0 when the pipe is off. Turns out that's not correct, and instead the scanline counter simply stops when the pipe stops, and it retains it's last value until the pipe starts up again, at which point the scanline counter jumps to vblank start. These jumps can cause the timestamp to jump backwards by one frame. Since we use the timestamps to guesstimage also the frame counter value on gen2, that would cause the frame counter to also jump backwards, which leads to a massice difference from the previous value. The end result is that flips/vblank events don't appear to complete as they're stuck waiting for the frame counter to catch up to that massive difference. Fix the problem properly by actually making sure the scanline counter has started to move before we assume that it's safe to enable vblank processing. v2: Less pointless duplication in the code (Chris) Cc: stable@vger.kernel.org Cc: Daniel Vetter Cc: Chris Wilson Reviewed-by: Chris Wilson Fixes: b7792d8b54cc ("drm/i915: Wait for pipe to start before sampling vblank timestamps on gen2") Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171129153732.3612-1-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 51 +++++++++++++++++++--------- 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7a1f60869b24..f712418594ed 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -998,7 +998,8 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, return crtc->config->cpu_transcoder; } -static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) +static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, + enum pipe pipe) { i915_reg_t reg = PIPEDSL(pipe); u32 line1, line2; @@ -1013,7 +1014,28 @@ static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) msleep(5); line2 = I915_READ(reg) & line_mask; - return line1 == line2; + return line1 != line2; +} + +static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + + /* Wait for the display line to settle/start moving */ + if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) + DRM_ERROR("pipe %c scanline %s wait timed out\n", + pipe_name(pipe), onoff(state)); +} + +static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) +{ + wait_for_pipe_scanline_moving(crtc, false); +} + +static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) +{ + wait_for_pipe_scanline_moving(crtc, true); } /* @@ -1036,7 +1058,6 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; - enum pipe pipe = crtc->pipe; if (INTEL_GEN(dev_priv) >= 4) { i915_reg_t reg = PIPECONF(cpu_transcoder); @@ -1047,9 +1068,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) 100)) WARN(1, "pipe_off wait timed out\n"); } else { - /* Wait for the display line to settle */ - if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) - WARN(1, "pipe_off wait timed out\n"); + intel_wait_for_pipe_scanline_stopped(crtc); } } @@ -1862,15 +1881,14 @@ static void intel_enable_pipe(struct intel_crtc *crtc) POSTING_READ(reg); /* - * Until the pipe starts DSL will read as 0, which would cause - * an apparent vblank timestamp jump, which messes up also the - * frame count when it's derived from the timestamps. So let's - * wait for the pipe to start properly before we call - * drm_crtc_vblank_on() + * Until the pipe starts PIPEDSL reads will return a stale value, + * which causes an apparent vblank timestamp jump when PIPEDSL + * resets to its proper value. That also messes up the frame count + * when it's derived from the timestamps. So let's wait for the + * pipe to start properly before we call drm_crtc_vblank_on() */ - if (dev->max_vblank_count == 0 && - wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) - DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); + if (dev->max_vblank_count == 0) + intel_wait_for_pipe_scanline_moving(crtc); } /** @@ -14767,6 +14785,8 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); + DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n", pipe_name(pipe)); @@ -14779,8 +14799,7 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) I915_WRITE(PIPECONF(pipe), 0); POSTING_READ(PIPECONF(pipe)); - if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) - DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe)); + intel_wait_for_pipe_scanline_stopped(crtc); I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); POSTING_READ(DPLL(pipe)); -- GitLab From d5fb43cb7fffc8f6863d68456252bcf3f06a070a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 29 Nov 2017 17:37:31 +0200 Subject: [PATCH 0417/2547] drm/i915: Wait for pipe to start on i830 as well MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We should make sure the pipe has fully started when we enable it from the i830 "power well". Otherwise theoretically i830 could also hit problems with vblank timestamps jumping around (since we skip the wait during modeset on i830). Additionally moving planes between the pipes etc. might not work correctly until both pipes are actually up and running. v2: Less pointless duplication in the code (Chris) Cc: Chris Wilson Reviewed-by: Chris Wilson Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171129153732.3612-2-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f712418594ed..7678caa81727 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14718,6 +14718,7 @@ int intel_modeset_init(struct drm_device *dev) void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); /* 640x480@60Hz, ~25175 kHz */ struct dpll clock = { .m1 = 18, @@ -14781,6 +14782,8 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE); POSTING_READ(PIPECONF(pipe)); + + intel_wait_for_pipe_scanline_moving(crtc); } void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) -- GitLab From 4972f70a202eeb3c270e182c8b83fc271288076c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 29 Nov 2017 17:37:32 +0200 Subject: [PATCH 0418/2547] drm/i915: Pass crtc state to intel_pipe_{enable,disable}() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Get rid of the crtc->config usages from within intel_pipe_{enable,disable}() by passing in the appropriate crtc state. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171129153732.3612-3-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 76 +++++++++------------------- 1 file changed, 23 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7678caa81727..47a2f6acee50 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1038,28 +1038,14 @@ static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) wait_for_pipe_scanline_moving(crtc, true); } -/* - * intel_wait_for_pipe_off - wait for pipe to turn off - * @crtc: crtc whose pipe to wait for - * - * After disabling a pipe, we can't wait for vblank in the usual way, - * spinning on the vblank interrupt status bit, since we won't actually - * see an interrupt when the pipe is disabled. - * - * On Gen4 and above: - * wait for the pipe register state bit to turn off - * - * Otherwise: - * wait for the display line value to settle (it usually - * ends up stopping at the start of the next frame). - * - */ -static void intel_wait_for_pipe_off(struct intel_crtc *crtc) +static void +intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; if (INTEL_GEN(dev_priv) >= 4) { + enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; i915_reg_t reg = PIPECONF(cpu_transcoder); /* Wait for the Pipe State to go off */ @@ -1828,19 +1814,12 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) return crtc->pipe; } -/** - * intel_enable_pipe - enable a pipe, asserting requirements - * @crtc: crtc responsible for the pipe - * - * Enable @crtc's pipe, making sure that various hardware specific requirements - * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. - */ -static void intel_enable_pipe(struct intel_crtc *crtc) +static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; enum pipe pipe = crtc->pipe; - enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; i915_reg_t reg; u32 val; @@ -1854,12 +1833,12 @@ static void intel_enable_pipe(struct intel_crtc *crtc) * need the check. */ if (HAS_GMCH_DISPLAY(dev_priv)) { - if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) + if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) assert_dsi_pll_enabled(dev_priv); else assert_pll_enabled(dev_priv, pipe); } else { - if (crtc->config->has_pch_encoder) { + if (new_crtc_state->has_pch_encoder) { /* if driving the PCH, we need FDI enabled */ assert_fdi_rx_pll_enabled(dev_priv, intel_crtc_pch_transcoder(crtc)); @@ -1887,24 +1866,15 @@ static void intel_enable_pipe(struct intel_crtc *crtc) * when it's derived from the timestamps. So let's wait for the * pipe to start properly before we call drm_crtc_vblank_on() */ - if (dev->max_vblank_count == 0) + if (dev_priv->drm.max_vblank_count == 0) intel_wait_for_pipe_scanline_moving(crtc); } -/** - * intel_disable_pipe - disable a pipe, asserting requirements - * @crtc: crtc whose pipes is to be disabled - * - * Disable the pipe of @crtc, making sure that various hardware - * specific requirements are met, if applicable, e.g. plane - * disabled, panel fitter off, etc. - * - * Will wait until the pipe has shut down before returning. - */ -static void intel_disable_pipe(struct intel_crtc *crtc) +static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; + enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; enum pipe pipe = crtc->pipe; i915_reg_t reg; u32 val; @@ -1926,7 +1896,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc) * Double wide has implications for planes * so best keep it disabled when not needed. */ - if (crtc->config->double_wide) + if (old_crtc_state->double_wide) val &= ~PIPECONF_DOUBLE_WIDE; /* Don't disable pipe or pipe PLLs if needed */ @@ -1935,7 +1905,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc) I915_WRITE(reg, val); if ((val & PIPECONF_ENABLE) == 0) - intel_wait_for_pipe_off(crtc); + intel_wait_for_pipe_off(old_crtc_state); } static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) @@ -5354,7 +5324,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, if (dev_priv->display.initial_watermarks != NULL) dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); - intel_enable_pipe(intel_crtc); + intel_enable_pipe(pipe_config); if (intel_crtc->config->has_pch_encoder) ironlake_pch_enable(pipe_config); @@ -5473,7 +5443,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, /* XXX: Do the pipe assertions at the right place for BXT DSI. */ if (!transcoder_is_dsi(cpu_transcoder)) - intel_enable_pipe(intel_crtc); + intel_enable_pipe(pipe_config); if (intel_crtc->config->has_pch_encoder) lpt_pch_enable(pipe_config); @@ -5539,7 +5509,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, drm_crtc_vblank_off(crtc); assert_vblank_disabled(crtc); - intel_disable_pipe(intel_crtc); + intel_disable_pipe(old_crtc_state); ironlake_pfit_disable(intel_crtc, false); @@ -5591,7 +5561,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, /* XXX: Do the pipe assertions at the right place for BXT DSI. */ if (!transcoder_is_dsi(cpu_transcoder)) - intel_disable_pipe(intel_crtc); + intel_disable_pipe(old_crtc_state); if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); @@ -5769,7 +5739,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, dev_priv->display.initial_watermarks(old_intel_state, pipe_config); - intel_enable_pipe(intel_crtc); + intel_enable_pipe(pipe_config); assert_vblank_disabled(crtc); drm_crtc_vblank_on(crtc); @@ -5828,7 +5798,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, intel_crtc->config); else intel_update_watermarks(intel_crtc); - intel_enable_pipe(intel_crtc); + intel_enable_pipe(pipe_config); assert_vblank_disabled(crtc); drm_crtc_vblank_on(crtc); @@ -5872,7 +5842,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, drm_crtc_vblank_off(crtc); assert_vblank_disabled(crtc); - intel_disable_pipe(intel_crtc); + intel_disable_pipe(old_crtc_state); i9xx_pfit_disable(intel_crtc); -- GitLab From 050213893307e661933a315a3c6e82658a68ffee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 29 Nov 2017 20:08:47 +0200 Subject: [PATCH 0419/2547] drm/i915: Interlaced DP output doesn't work on VLV/CHV MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reject interlaced modes on VLV/CHV DP outputs. This simply does not work correctly in the hardware. We do get some output, but it's quite corrupted. The available documentation fails to mention this fact. I contacted some hardware people who eventually managed to locate the relevant HSD for VLV, which was resolved by declaring interlaced DP output as not supported. The HSD was never cloned for CHV even though it inherited most of the hardware and thus has the same problems with interlaced DP output. Cc: Dennis Vshivkov Reported-by: Dennis Vshivkov Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103922 Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171129180847.30613-1-ville.syrjala@linux.intel.com Acked-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_dp.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index bf93991c2fcc..90e8f35cc886 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1677,6 +1677,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, conn_state->scaling_mode); } + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) + return false; + if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) return false; @@ -6093,7 +6097,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); - connector->interlace_allowed = true; + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) + connector->interlace_allowed = true; connector->doublescan_allowed = 0; intel_dp_init_connector_port_info(intel_dig_port); -- GitLab From f7096d40eea84d32eb1e3b0f2b4407167aae9a83 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 1 Dec 2017 12:20:11 +0000 Subject: [PATCH 0420/2547] drm/i915: Sleep and retry a GPU reset if at first we don't succeed As we declare the GPU wedged if the reset fails, such a failure is quite terminal. Before taking that drastic action, let's sleep first and try active, in the hope that the hardware has quietened down and is then able to reset. After a few such attempts, it is fair to say that the HW is truly wedged. v2: Always print the failure message now, we precheck whether resets are disabled. References: https://bugs.freedesktop.org/show_bug.cgi?id=104007 Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171201122011.16841-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 1c419893e3a9..43fbff48a133 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1877,7 +1877,9 @@ void i915_reset(struct drm_i915_private *i915, unsigned int flags) { struct i915_gpu_error *error = &i915->gpu_error; int ret; + int i; + might_sleep(); lockdep_assert_held(&i915->drm.struct_mutex); GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags)); @@ -1900,12 +1902,20 @@ void i915_reset(struct drm_i915_private *i915, unsigned int flags) goto error; } - ret = intel_gpu_reset(i915, ALL_ENGINES); + if (!intel_has_gpu_reset(i915)) { + DRM_DEBUG_DRIVER("GPU reset disabled\n"); + goto error; + } + + for (i = 0; i < 3; i++) { + ret = intel_gpu_reset(i915, ALL_ENGINES); + if (ret == 0) + break; + + msleep(100); + } if (ret) { - if (ret != -ENODEV) - DRM_ERROR("Failed to reset chip: %i\n", ret); - else - DRM_DEBUG_DRIVER("GPU reset disabled\n"); + dev_err(i915->drm.dev, "Failed to reset chip\n"); goto error; } -- GitLab From fb6db0f5bf1d4d3a4af6242e287fa795221ec5b8 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 1 Dec 2017 11:30:30 +0000 Subject: [PATCH 0421/2547] drm/i915: Remove unsafe i915.enable_rc6 It has been many years since the last confirmed sighting (and fix) of an RC6 related bug (usually a system hang). Remove the parameter to stop users from setting dangerous values, as they often set it during triage and end up disabling the entire runtime pm instead (the option is not a fine scalpel!). Furthermore, it allows users to set known dangerous values which were intended for testing and not for production use. For testing, we can always patch in the required setting without having to expose ourselves to random abuse. v2: Fixup NEEDS_WaRsDisableCoarsePowerGating fumble, and document the lack of ilk support better. v3: Clear intel_info->rc6p if we don't support rc6 itself. Signed-off-by: Chris Wilson Cc: Rodrigo Vivi Cc: Joonas Lahtinen Cc: Jani Nikula Cc: Imre Deak Cc: Daniel Vetter Acked-by: Daniel Vetter Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171201113030.18360-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_params.c | 7 -- drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/i915_pci.c | 2 + drivers/gpu/drm/i915/i915_pmu.c | 4 +- drivers/gpu/drm/i915/i915_sysfs.c | 13 ++- drivers/gpu/drm/i915/intel_drv.h | 5 - drivers/gpu/drm/i915/intel_guc.c | 3 +- drivers/gpu/drm/i915/intel_pm.c | 142 +++++++++------------------- drivers/gpu/drm/i915/intel_uncore.c | 3 - 11 files changed, 64 insertions(+), 120 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 43fbff48a133..962d7c7c799c 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -2527,7 +2527,7 @@ static int intel_runtime_suspend(struct device *kdev) struct drm_i915_private *dev_priv = to_i915(dev); int ret; - if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && intel_rc6_enabled()))) + if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv)))) return -ENODEV; if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index bddd65839f60..e8dc7b77ac96 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3213,8 +3213,10 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi) #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr) + #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) +#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 3328147b4863..7bc538687871 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -46,13 +46,6 @@ i915_param_named_unsafe(panel_ignore_lid, int, 0600, "Override lid status (0=autodetect, 1=autodetect disabled [default], " "-1=force lid closed, -2=force lid open)"); -i915_param_named_unsafe(enable_rc6, int, 0400, - "Enable power-saving render C-state 6. " - "Different stages can be selected via bitmask values " - "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " - "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " - "default: -1 (use per-chip default)"); - i915_param_named_unsafe(enable_dc, int, 0400, "Enable power-saving display C-states. " "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)"); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 8321bd86cba5..c48c88bb95e8 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -34,7 +34,6 @@ param(int, lvds_channel_mode, 0) \ param(int, panel_use_ssc, -1) \ param(int, vbt_sdvo_panel_type, -1) \ - param(int, enable_rc6, -1) \ param(int, enable_dc, -1) \ param(int, enable_fbc, -1) \ param(int, enable_ppgtt, -1) \ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 6458c309c039..fa67d3dde20e 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -209,6 +209,8 @@ static const struct intel_device_info intel_gm45_info __initconst = { .has_hotplug = 1, \ .ring_mask = RENDER_RING | BSD_RING, \ .has_snoop = true, \ + /* ilk does support rc6, but we do not implement [power] contexts */ \ + .has_rc6 = 0, \ GEN_DEFAULT_PIPEOFFSETS, \ GEN_DEFAULT_PAGE_SIZES, \ CURSOR_OFFSETS diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index e8e2faf4982f..55a8a1e29424 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -413,12 +413,12 @@ static u64 __i915_pmu_event_read(struct perf_event *event) IS_VALLEYVIEW(i915) ? VLV_GT_RENDER_RC6 : GEN6_GT_GFX_RC6); - if (HAS_RC6p(i915)) { + if (HAS_RC6p(i915)) val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p); + if (HAS_RC6pp(i915)) val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp); - } intel_runtime_pm_put(i915); break; } diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index c290cb600eea..c74a20b80182 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -54,7 +54,18 @@ static u32 calc_residency(struct drm_i915_private *dev_priv, static ssize_t show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf) { - return snprintf(buf, PAGE_SIZE, "%x\n", intel_rc6_enabled()); + struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); + unsigned int mask; + + mask = 0; + if (HAS_RC6(dev_priv)) + mask |= BIT(0); + if (HAS_RC6p(dev_priv)) + mask |= BIT(1); + if (HAS_RC6pp(dev_priv)) + mask |= BIT(2); + + return snprintf(buf, PAGE_SIZE, "%x\n", mask); } static ssize_t diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 82d637d20d5d..30f791f89d64 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1908,15 +1908,10 @@ bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv, const struct skl_ddb_entry *ddb, int ignore); bool ilk_disable_lp_wm(struct drm_device *dev); -int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6); int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, struct intel_crtc_state *cstate); void intel_init_ipc(struct drm_i915_private *dev_priv); void intel_enable_ipc(struct drm_i915_private *dev_priv); -static inline int intel_rc6_enabled(void) -{ - return i915_modparams.enable_rc6; -} /* intel_sdvo.c */ bool intel_sdvo_init(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 823d0c2e9ad2..d08e760252d4 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -231,8 +231,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc) action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE; /* WaRsDisableCoarsePowerGating:skl,bxt */ - if (!intel_rc6_enabled() || - NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) + if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) action[1] = 0; else /* bit 0 and 1 are for Render and Media domain separately */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a80c322c5b43..67f326230a7e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -52,9 +52,6 @@ * which brings the most power savings; deeper states save more power, but * require higher latency to switch to and wake up. */ -#define INTEL_RC6_ENABLE (1<<0) -#define INTEL_RC6p_ENABLE (1<<1) -#define INTEL_RC6pp_ENABLE (1<<2) static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) { @@ -6417,26 +6414,6 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_RP_CONTROL, 0); } -static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode) -{ - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) - mode = GEN6_RC_CTL_RC6_ENABLE; - else - mode = 0; - } - if (HAS_RC6p(dev_priv)) - DRM_DEBUG_DRIVER("Enabling RC6 states: " - "RC6 %s RC6p %s RC6pp %s\n", - onoff(mode & GEN6_RC_CTL_RC6_ENABLE), - onoff(mode & GEN6_RC_CTL_RC6p_ENABLE), - onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE)); - - else - DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n", - onoff(mode & GEN6_RC_CTL_RC6_ENABLE)); -} - static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv) { struct i915_ggtt *ggtt = &dev_priv->ggtt; @@ -6499,42 +6476,30 @@ static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv) return enable_rc6; } -int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6) +static bool sanitize_rc6(struct drm_i915_private *i915) { - /* No RC6 before Ironlake and code is gone for ilk. */ - if (INTEL_INFO(dev_priv)->gen < 6) - return 0; + struct intel_device_info *info = mkwrite_device_info(i915); - if (!enable_rc6) - return 0; + /* Powersaving is controlled by the host when inside a VM */ + if (intel_vgpu_active(i915)) + info->has_rc6 = 0; - if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) { + if (info->has_rc6 && + IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) { DRM_INFO("RC6 disabled by BIOS\n"); - return 0; + info->has_rc6 = 0; } - /* Respect the kernel parameter if it is set */ - if (enable_rc6 >= 0) { - int mask; - - if (HAS_RC6p(dev_priv)) - mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | - INTEL_RC6pp_ENABLE; - else - mask = INTEL_RC6_ENABLE; - - if ((enable_rc6 & mask) != enable_rc6) - DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d " - "(requested %d, valid %d)\n", - enable_rc6 & mask, enable_rc6, mask); - - return enable_rc6 & mask; - } - - if (IS_IVYBRIDGE(dev_priv)) - return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); + /* + * We assume that we do not have any deep rc6 levels if we don't have + * have the previous rc6 level supported, i.e. we use HAS_RC6() + * as the initial coarse check for rc6 in general, moving on to + * progressively finer/deeper levels. + */ + if (!info->has_rc6 && info->has_rc6p) + info->has_rc6p = 0; - return INTEL_RC6_ENABLE; + return info->has_rc6; } static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) @@ -6627,7 +6592,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv) { struct intel_engine_cs *engine; enum intel_engine_id id; - u32 rc6_mode, rc6_mask = 0; + u32 rc6_mode; /* 1a: Software RC state - RC0 */ I915_WRITE(GEN6_RC_STATE, 0); @@ -6668,9 +6633,6 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv) I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); /* 3a: Enable RC6 */ - if (intel_rc6_enabled() & INTEL_RC6_ENABLE) - rc6_mask = GEN6_RC_CTL_RC6_ENABLE; - DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE)); I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ /* WaRsUseTimeoutMode:cnl (pre-prod) */ @@ -6680,7 +6642,9 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv) rc6_mode = GEN6_RC_CTL_EI_MODE(1); I915_WRITE(GEN6_RC_CONTROL, - GEN6_RC_CTL_HW_ENABLE | rc6_mode | rc6_mask); + GEN6_RC_CTL_HW_ENABLE | + GEN6_RC_CTL_RC6_ENABLE | + rc6_mode); /* * 3b: Enable Coarse Power Gating only when RC6 is enabled. @@ -6689,8 +6653,8 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv) if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) I915_WRITE(GEN9_PG_ENABLE, 0); else - I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? - (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); + I915_WRITE(GEN9_PG_ENABLE, + GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } @@ -6699,7 +6663,6 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv) { struct intel_engine_cs *engine; enum intel_engine_id id; - uint32_t rc6_mask = 0; /* 1a: Software RC state - RC0 */ I915_WRITE(GEN6_RC_STATE, 0); @@ -6721,13 +6684,11 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ /* 3: Enable RC6 */ - if (intel_rc6_enabled() & INTEL_RC6_ENABLE) - rc6_mask = GEN6_RC_CTL_RC6_ENABLE; - intel_print_rc6_info(dev_priv, rc6_mask); - I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | - GEN7_RC_CTL_TO_MODE | - rc6_mask); + I915_WRITE(GEN6_RC_CONTROL, + GEN6_RC_CTL_HW_ENABLE | + GEN7_RC_CTL_TO_MODE | + GEN6_RC_CTL_RC6_ENABLE); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } @@ -6776,9 +6737,8 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv) { struct intel_engine_cs *engine; enum intel_engine_id id; - u32 rc6vids, rc6_mask = 0; + u32 rc6vids, rc6_mask; u32 gtfifodbg; - int rc6_mode; int ret; I915_WRITE(GEN6_RC_STATE, 0); @@ -6813,22 +6773,12 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ - /* Check if we are enabling RC6 */ - rc6_mode = intel_rc6_enabled(); - if (rc6_mode & INTEL_RC6_ENABLE) - rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; - /* We don't use those on Haswell */ - if (!IS_HASWELL(dev_priv)) { - if (rc6_mode & INTEL_RC6p_ENABLE) - rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; - - if (rc6_mode & INTEL_RC6pp_ENABLE) - rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; - } - - intel_print_rc6_info(dev_priv, rc6_mask); - + rc6_mask = GEN6_RC_CTL_RC6_ENABLE; + if (HAS_RC6p(dev_priv)) + rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; + if (HAS_RC6pp(dev_priv)) + rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; I915_WRITE(GEN6_RC_CONTROL, rc6_mask | GEN6_RC_CTL_EI_MODE(1) | @@ -7271,7 +7221,7 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv) { struct intel_engine_cs *engine; enum intel_engine_id id; - u32 gtfifodbg, rc6_mode = 0, pcbr; + u32 gtfifodbg, rc6_mode, pcbr; gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV | GT_FIFO_FREE_ENTRIES_CHV); @@ -7312,10 +7262,9 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv) pcbr = I915_READ(VLV_PCBR); /* 3: Enable RC6 */ - if ((intel_rc6_enabled() & INTEL_RC6_ENABLE) && - (pcbr >> VLV_PCBR_ADDR_SHIFT)) + rc6_mode = 0; + if (pcbr >> VLV_PCBR_ADDR_SHIFT) rc6_mode = GEN7_RC_CTL_TO_MODE; - I915_WRITE(GEN6_RC_CONTROL, rc6_mode); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); @@ -7367,7 +7316,7 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv) { struct intel_engine_cs *engine; enum intel_engine_id id; - u32 gtfifodbg, rc6_mode = 0; + u32 gtfifodbg; valleyview_check_pctx(dev_priv); @@ -7400,12 +7349,8 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv) VLV_MEDIA_RC6_COUNT_EN | VLV_RENDER_RC6_COUNT_EN)); - if (intel_rc6_enabled() & INTEL_RC6_ENABLE) - rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; - - intel_print_rc6_info(dev_priv, rc6_mode); - - I915_WRITE(GEN6_RC_CONTROL, rc6_mode); + I915_WRITE(GEN6_RC_CONTROL, + GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } @@ -7932,7 +7877,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv) * RPM depends on RC6 to save restore the GT HW context, so make RC6 a * requirement. */ - if (!i915_modparams.enable_rc6) { + if (!sanitize_rc6(dev_priv)) { DRM_INFO("RC6 disabled, disabling runtime PM support\n"); intel_runtime_pm_get(dev_priv); } @@ -7985,7 +7930,7 @@ void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv) if (IS_VALLEYVIEW(dev_priv)) valleyview_cleanup_gt_powersave(dev_priv); - if (!i915_modparams.enable_rc6) + if (!HAS_RC6(dev_priv)) intel_runtime_pm_put(dev_priv); } @@ -8152,7 +8097,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) mutex_lock(&dev_priv->pcu_lock); - intel_enable_rc6(dev_priv); + if (HAS_RC6(dev_priv)) + intel_enable_rc6(dev_priv); intel_enable_rps(dev_priv); if (HAS_LLC(dev_priv)) intel_enable_llc_pstate(dev_priv); @@ -9444,7 +9390,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, u64 time_hw; u32 mul, div; - if (!intel_rc6_enabled()) + if (!HAS_RC6(dev_priv)) return 0; /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index b4621271e7a2..89547b614aa6 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -565,9 +565,6 @@ void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv) void intel_uncore_sanitize(struct drm_i915_private *dev_priv) { - i915_modparams.enable_rc6 = - sanitize_rc6_option(dev_priv, i915_modparams.enable_rc6); - /* BIOS often leaves RC6 enabled, but disable it for hw init */ intel_sanitize_gt_powersave(dev_priv); } -- GitLab From e4ec40ec4b260efcca15089de4285a0a3411259b Mon Sep 17 00:00:00 2001 From: Mathias Nyman Date: Fri, 1 Dec 2017 13:41:19 +0200 Subject: [PATCH 0422/2547] xhci: Don't show incorrect WARN message about events for empty rings xHC can generate two events for a short transfer if the short TRB and last TRB in the TD are not the same TRB. The driver will handle the TD after the first short event, and remove it from its internal list. Driver then incorrectly prints a warning for the second event: "WARN Event TRB for slot x ep y with no TDs queued" Fix this by not printing a warning if we get a event on a empty list if the previous event was a short event. Cc: Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-ring.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index c239c688076c..6eb87c6e4d24 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -2477,12 +2477,16 @@ static int handle_tx_event(struct xhci_hcd *xhci, */ if (list_empty(&ep_ring->td_list)) { /* - * A stopped endpoint may generate an extra completion - * event if the device was suspended. Don't print - * warnings. + * Don't print wanings if it's due to a stopped endpoint + * generating an extra completion event if the device + * was suspended. Or, a event for the last TRB of a + * short TD we already got a short event for. + * The short TD is already removed from the TD list. */ + if (!(trb_comp_code == COMP_STOPPED || - trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { + trb_comp_code == COMP_STOPPED_LENGTH_INVALID || + ep_ring->last_td_was_short)) { xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), ep_index); -- GitLab From 80e457699a8dbdd70f2d26911e46f538645c55fc Mon Sep 17 00:00:00 2001 From: Yu Chen Date: Fri, 1 Dec 2017 13:41:20 +0200 Subject: [PATCH 0423/2547] usb: xhci: fix panic in xhci_free_virt_devices_depth_first Check vdev->real_port 0 to avoid panic [ 9.261347] [] xhci_free_virt_devices_depth_first+0x58/0x108 [ 9.261352] [] xhci_mem_cleanup+0x1bc/0x570 [ 9.261355] [] xhci_stop+0x140/0x1c8 [ 9.261365] [] usb_remove_hcd+0xfc/0x1d0 [ 9.261369] [] xhci_plat_remove+0x6c/0xa8 [ 9.261377] [] platform_drv_remove+0x2c/0x70 [ 9.261384] [] __device_release_driver+0x80/0x108 [ 9.261387] [] device_release_driver+0x2c/0x40 [ 9.261392] [] bus_remove_device+0xe0/0x120 [ 9.261396] [] device_del+0x114/0x210 [ 9.261399] [] platform_device_del+0x30/0xa0 [ 9.261403] [] dwc3_otg_work+0x204/0x488 [ 9.261407] [] event_work+0x304/0x5b8 [ 9.261414] [] process_one_work+0x148/0x490 [ 9.261417] [] worker_thread+0x50/0x4a0 [ 9.261421] [] kthread+0xe8/0x100 [ 9.261427] [] ret_from_fork+0x10/0x50 The problem can occur if xhci_plat_remove() is called shortly after xhci_plat_probe(). While xhci_free_virt_devices_depth_first been called before the device has been setup and get real_port initialized. The problem occurred on Hikey960 and was reproduced by Guenter Roeck on Kevin with chromeos-4.4. Fixes: ee8665e28e8d ("xhci: free xhci virtual devices with leaf nodes first") Cc: Guenter Roeck Cc: # v4.10+ Reviewed-by: Guenter Roeck Tested-by: Guenter Roeck Signed-off-by: Fan Ning Signed-off-by: Li Rui Signed-off-by: yangdi Signed-off-by: Yu Chen Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-mem.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index e1fba4688509..15f7d422885f 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -934,6 +934,12 @@ void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id) if (!vdev) return; + if (vdev->real_port == 0 || + vdev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) { + xhci_dbg(xhci, "Bad vdev->real_port.\n"); + goto out; + } + tt_list_head = &(xhci->rh_bw[vdev->real_port - 1].tts); list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) { /* is this a hub device that added a tt_info to the tts list */ @@ -947,6 +953,7 @@ void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id) } } } +out: /* we are now at a leaf device */ xhci_debugfs_remove_slot(xhci, slot_id); xhci_free_virt_device(xhci, slot_id); -- GitLab From b6047ebaf7b3fb63c3ad49ec9c381a0e0b9fb82a Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Thu, 19 Oct 2017 10:40:54 +0200 Subject: [PATCH 0424/2547] drm/etnaviv: add sensitive state for occlusion query address Add GL.OCCLUSION_QUERY_ADDR (0x03824): address where GPU stores the occlusion query result. Signed-off-by: Christian Gmeiner Signed-off-by: Lucas Stach --- drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c b/drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c index 6e3bbcf24160..68e6d3772ad8 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c @@ -78,6 +78,7 @@ static const struct { ST(0x17c0, 8), ST(0x17e0, 8), ST(0x2400, 14 * 16), + ST(0x3824, 1), ST(0x10800, 32 * 16), ST(0x14600, 16), ST(0x14800, 8 * 8), -- GitLab From ff9815957768b6e76d6895a0597d1ede05b4378b Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Mon, 23 Oct 2017 21:27:30 +0200 Subject: [PATCH 0425/2547] drm/etnaviv: Improve unlocking of a mutex in etnaviv_iommu_map_gem() Add a jump target so that a call of the function "mutex_unlock" is stored only once at the end of this function implementation. Replace three calls by goto statements. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring Signed-off-by: Lucas Stach --- drivers/gpu/drm/etnaviv/etnaviv_mmu.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c index 35074b944778..d113fe06e6b5 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c @@ -263,18 +263,16 @@ int etnaviv_iommu_map_gem(struct etnaviv_iommu *mmu, if (iova < 0x80000000 - sg_dma_len(sgt->sgl)) { mapping->iova = iova; list_add_tail(&mapping->mmu_node, &mmu->mappings); - mutex_unlock(&mmu->lock); - return 0; + ret = 0; + goto unlock; } } node = &mapping->vram_node; ret = etnaviv_iommu_find_iova(mmu, node, etnaviv_obj->base.size); - if (ret < 0) { - mutex_unlock(&mmu->lock); - return ret; - } + if (ret < 0) + goto unlock; mmu->last_iova = node->start + etnaviv_obj->base.size; mapping->iova = node->start; @@ -283,12 +281,12 @@ int etnaviv_iommu_map_gem(struct etnaviv_iommu *mmu, if (ret < 0) { drm_mm_remove_node(node); - mutex_unlock(&mmu->lock); - return ret; + goto unlock; } list_add_tail(&mapping->mmu_node, &mmu->mappings); mmu->need_flush = true; +unlock: mutex_unlock(&mmu->lock); return ret; -- GitLab From 49b82c389d2a40eaef1355aaa35868b367aec9d1 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 1 Dec 2017 16:00:41 +0100 Subject: [PATCH 0426/2547] drm/etnaviv: make THERMAL selectable The etnaviv driver causes a link failure if it is built-in but THERMAL is built as a module: drivers/gpu/drm/etnaviv/etnaviv_gpu.o: In function `etnaviv_gpu_bind': etnaviv_gpu.c:(.text+0x4c4): undefined reference to `thermal_of_cooling_device_register' etnaviv_gpu.c:(.text+0x600): undefined reference to `thermal_cooling_device_unregister' drivers/gpu/drm/etnaviv/etnaviv_gpu.o: In function `etnaviv_gpu_unbind': etnaviv_gpu.c:(.text+0x2aac): undefined reference to `thermal_cooling_device_unregister' Adding a Kconfig dependency on THERMAL || !THERMAL to avoid this causes a dependency loop on x86_64: drivers/gpu/drm/tve200/Kconfig:1:error: recursive dependency detected! For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpu/drm/tve200/Kconfig:1: symbol DRM_TVE200 depends on CMA For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" mm/Kconfig:489: symbol CMA is selected by DRM_ETNAVIV For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpu/drm/etnaviv/Kconfig:2: symbol DRM_ETNAVIV depends on THERMAL For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/thermal/Kconfig:5: symbol THERMAL is selected by ACPI_VIDEO For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/acpi/Kconfig:189: symbol ACPI_VIDEO is selected by BACKLIGHT_CLASS_DEVICE For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/video/backlight/Kconfig:158: symbol BACKLIGHT_CLASS_DEVICE is selected by DRM_PARADE_PS8622 For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpu/drm/bridge/Kconfig:62: symbol DRM_PARADE_PS8622 depends on DRM_BRIDGE For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpu/drm/bridge/Kconfig:1: symbol DRM_BRIDGE is selected by DRM_TVE200 To work around this, add a new option DRM_ETNAVIV_THERMAL to optionally enable thermal throttling support and make DRM_ETNAVIV select THERMAL at the same time. Reported-by: Stephen Rothwell Signed-off-by: Philipp Zabel Signed-off-by: Lucas Stach --- drivers/gpu/drm/etnaviv/Kconfig | 9 +++++++++ drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 8 +++++--- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/Kconfig b/drivers/gpu/drm/etnaviv/Kconfig index a29b8f59eb15..3f58b4077767 100644 --- a/drivers/gpu/drm/etnaviv/Kconfig +++ b/drivers/gpu/drm/etnaviv/Kconfig @@ -6,6 +6,7 @@ config DRM_ETNAVIV depends on MMU select SHMEM select SYNC_FILE + select THERMAL if DRM_ETNAVIV_THERMAL select TMPFS select WANT_DEV_COREDUMP select CMA if HAVE_DMA_CONTIGUOUS @@ -13,6 +14,14 @@ config DRM_ETNAVIV help DRM driver for Vivante GPUs. +config DRM_ETNAVIV_THERMAL + bool "enable ETNAVIV thermal throttling" + depends on DRM_ETNAVIV + default y + help + Compile in support for thermal throttling. + Say Y unless you want to risk burning your SoC. + config DRM_ETNAVIV_REGISTER_LOGGING bool "enable ETNAVIV register logging" depends on DRM_ETNAVIV diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index e19cbe05da2a..968cbc2be9c4 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1738,7 +1738,7 @@ static int etnaviv_gpu_bind(struct device *dev, struct device *master, struct etnaviv_gpu *gpu = dev_get_drvdata(dev); int ret; - if (IS_ENABLED(CONFIG_THERMAL)) { + if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) { gpu->cooling = thermal_of_cooling_device_register(dev->of_node, (char *)dev_name(dev), gpu, &cooling_ops); if (IS_ERR(gpu->cooling)) @@ -1751,7 +1751,8 @@ static int etnaviv_gpu_bind(struct device *dev, struct device *master, ret = etnaviv_gpu_clk_enable(gpu); #endif if (ret < 0) { - thermal_cooling_device_unregister(gpu->cooling); + if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) + thermal_cooling_device_unregister(gpu->cooling); return ret; } @@ -1808,7 +1809,8 @@ static void etnaviv_gpu_unbind(struct device *dev, struct device *master, gpu->drm = NULL; - thermal_cooling_device_unregister(gpu->cooling); + if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) + thermal_cooling_device_unregister(gpu->cooling); gpu->cooling = NULL; } -- GitLab From 23a7068ec581fcc6fb61039448632d25987b1fae Mon Sep 17 00:00:00 2001 From: James Ausmus Date: Thu, 30 Nov 2017 18:17:00 -0800 Subject: [PATCH 0427/2547] drm/i915/cnl: Mask previous DDI - PLL mapping Without masking out the old value, we can end up pointing the DDI to a disabled PLL, which makes the system fall over. Mask out the previous value before setting the PLL to DDI mapping. This can be observed by running igt/testdisplay with both an eDP and HDMI/DP output active. v2: Add the Bugzilla link Fixes: 555e38d273172 ("drm/i915/cnl: DDI - PLL mapping") Testcase: igt/testdisplay Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103997 Cc: Rodrigo Vivi Cc: Matt Atwood Signed-off-by: James Ausmus Reviewed-by: Rodrigo Vivi Tested-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20171201021700.13504-1-james.ausmus@intel.com --- drivers/gpu/drm/i915/intel_ddi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 48ba9b7fdc78..369f780588fb 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2098,6 +2098,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, if (IS_CANNONLAKE(dev_priv)) { /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ val = I915_READ(DPCLKA_CFGCR0); + val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port); I915_WRITE(DPCLKA_CFGCR0, val); -- GitLab From 100d6de2ced538c539d923dc14a1b5cbae234503 Mon Sep 17 00:00:00 2001 From: Chien Tin Tung Date: Tue, 21 Nov 2017 16:18:30 -0600 Subject: [PATCH 0428/2547] i40iw: Allocate a sdbuf per CQP WQE Currently there is only one sdbuf per Control QP (CQP) for programming Segment Descriptor (SD). If multiple SD work requests are posted simultaneously, the sdbuf is reused by all WQEs and new WQEs can corrupt previous WQEs sdbuf leading to incorrect SD programming. Fix this by allocating one sdbuf per CQP SQ WQE. When an SD command is posted, it will use the corresponding sdbuf for the WQE. Fixes: 86dbcd0f12e9 ("i40iw: add file to handle cqp calls") Signed-off-by: Chien Tin Tung Signed-off-by: Shiraz Saleem Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/i40iw/i40iw_ctrl.c | 43 +++++++++++++++++------- drivers/infiniband/hw/i40iw/i40iw_d.h | 4 ++- 2 files changed, 33 insertions(+), 14 deletions(-) diff --git a/drivers/infiniband/hw/i40iw/i40iw_ctrl.c b/drivers/infiniband/hw/i40iw/i40iw_ctrl.c index d88c6cf47cf2..da9821a10e0d 100644 --- a/drivers/infiniband/hw/i40iw/i40iw_ctrl.c +++ b/drivers/infiniband/hw/i40iw/i40iw_ctrl.c @@ -513,7 +513,7 @@ static enum i40iw_status_code i40iw_sc_cqp_create(struct i40iw_sc_cqp *cqp, ret_code = i40iw_allocate_dma_mem(cqp->dev->hw, &cqp->sdbuf, - 128, + I40IW_UPDATE_SD_BUF_SIZE * cqp->sq_size, I40IW_SD_BUF_ALIGNMENT); if (ret_code) @@ -596,14 +596,15 @@ void i40iw_sc_cqp_post_sq(struct i40iw_sc_cqp *cqp) } /** - * i40iw_sc_cqp_get_next_send_wqe - get next wqe on cqp sq - * @cqp: struct for cqp hw - * @wqe_idx: we index of cqp ring + * i40iw_sc_cqp_get_next_send_wqe_idx - get next WQE on CQP SQ and pass back the index + * @cqp: pointer to CQP structure + * @scratch: private data for CQP WQE + * @wqe_idx: WQE index for next WQE on CQP SQ */ -u64 *i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp *cqp, u64 scratch) +static u64 *i40iw_sc_cqp_get_next_send_wqe_idx(struct i40iw_sc_cqp *cqp, + u64 scratch, u32 *wqe_idx) { u64 *wqe = NULL; - u32 wqe_idx; enum i40iw_status_code ret_code; if (I40IW_RING_FULL_ERR(cqp->sq_ring)) { @@ -616,20 +617,32 @@ u64 *i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp *cqp, u64 scratch) cqp->sq_ring.size); return NULL; } - I40IW_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, wqe_idx, ret_code); + I40IW_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, *wqe_idx, ret_code); cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS]++; if (ret_code) return NULL; - if (!wqe_idx) + if (!*wqe_idx) cqp->polarity = !cqp->polarity; - wqe = cqp->sq_base[wqe_idx].elem; - cqp->scratch_array[wqe_idx] = scratch; + wqe = cqp->sq_base[*wqe_idx].elem; + cqp->scratch_array[*wqe_idx] = scratch; I40IW_CQP_INIT_WQE(wqe); return wqe; } +/** + * i40iw_sc_cqp_get_next_send_wqe - get next wqe on cqp sq + * @cqp: struct for cqp hw + * @scratch: private data for CQP WQE + */ +u64 *i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp *cqp, u64 scratch) +{ + u32 wqe_idx; + + return i40iw_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx); +} + /** * i40iw_sc_cqp_destroy - destroy cqp during close * @cqp: struct for cqp hw @@ -3587,8 +3600,10 @@ static enum i40iw_status_code cqp_sds_wqe_fill(struct i40iw_sc_cqp *cqp, u64 *wqe; int mem_entries, wqe_entries; struct i40iw_dma_mem *sdbuf = &cqp->sdbuf; + u64 offset; + u32 wqe_idx; - wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); + wqe = i40iw_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx); if (!wqe) return I40IW_ERR_RING_FULL; @@ -3601,8 +3616,10 @@ static enum i40iw_status_code cqp_sds_wqe_fill(struct i40iw_sc_cqp *cqp, LS_64(mem_entries, I40IW_CQPSQ_UPESD_ENTRY_COUNT); if (mem_entries) { - memcpy(sdbuf->va, &info->entry[3], (mem_entries << 4)); - data = sdbuf->pa; + offset = wqe_idx * I40IW_UPDATE_SD_BUF_SIZE; + memcpy((char *)sdbuf->va + offset, &info->entry[3], + mem_entries << 4); + data = (u64)sdbuf->pa + offset; } else { data = 0; } diff --git a/drivers/infiniband/hw/i40iw/i40iw_d.h b/drivers/infiniband/hw/i40iw/i40iw_d.h index 65ec39e3746b..1077b78f7754 100644 --- a/drivers/infiniband/hw/i40iw/i40iw_d.h +++ b/drivers/infiniband/hw/i40iw/i40iw_d.h @@ -1526,7 +1526,7 @@ enum i40iw_alignment { I40IW_AEQ_ALIGNMENT = 0x100, I40IW_CEQ_ALIGNMENT = 0x100, I40IW_CQ0_ALIGNMENT = 0x100, - I40IW_SD_BUF_ALIGNMENT = 0x100 + I40IW_SD_BUF_ALIGNMENT = 0x80 }; #define I40IW_WQE_SIZE_64 64 @@ -1534,6 +1534,8 @@ enum i40iw_alignment { #define I40IW_QP_WQE_MIN_SIZE 32 #define I40IW_QP_WQE_MAX_SIZE 128 +#define I40IW_UPDATE_SD_BUF_SIZE 128 + #define I40IW_CQE_QTYPE_RQ 0 #define I40IW_CQE_QTYPE_SQ 1 -- GitLab From 10499986dbd8778e1acf9f9d2e166800dfee44b4 Mon Sep 17 00:00:00 2001 From: Mustafa Ismail Date: Tue, 21 Nov 2017 16:18:31 -0600 Subject: [PATCH 0429/2547] i40iw: Do not free sqbuf when event is I40IW_TIMER_TYPE_CLOSE When the event type is I40IW_TIMER_TYPE_CLOSE, there is no sqbuf and it should not be freed as one in i40iw_schedule_cm_timer(). Fixes: f27b4746f378 ("i40iw: add connection management code") Signed-off-by: Mustafa Ismail Signed-off-by: Shiraz Saleem Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/i40iw/i40iw_cm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/i40iw/i40iw_cm.c b/drivers/infiniband/hw/i40iw/i40iw_cm.c index 493d6ef3d2d5..e1454174e3d9 100644 --- a/drivers/infiniband/hw/i40iw/i40iw_cm.c +++ b/drivers/infiniband/hw/i40iw/i40iw_cm.c @@ -1043,7 +1043,7 @@ static int i40iw_parse_mpa(struct i40iw_cm_node *cm_node, u8 *buffer, u32 *type, * i40iw_schedule_cm_timer * @@cm_node: connection's node * @sqbuf: buffer to send - * @type: if it es send ot close + * @type: if it is send or close * @send_retrans: if rexmits to be done * @close_when_complete: is cm_node to be removed * @@ -1067,7 +1067,8 @@ int i40iw_schedule_cm_timer(struct i40iw_cm_node *cm_node, new_send = kzalloc(sizeof(*new_send), GFP_ATOMIC); if (!new_send) { - i40iw_free_sqbuf(vsi, (void *)sqbuf); + if (type != I40IW_TIMER_TYPE_CLOSE) + i40iw_free_sqbuf(vsi, (void *)sqbuf); return -ENOMEM; } new_send->retrycount = I40IW_DEFAULT_RETRYS; @@ -1082,7 +1083,6 @@ int i40iw_schedule_cm_timer(struct i40iw_cm_node *cm_node, new_send->timetosend += (HZ / 10); if (cm_node->close_entry) { kfree(new_send); - i40iw_free_sqbuf(vsi, (void *)sqbuf); i40iw_pr_err("already close entry\n"); return -EINVAL; } -- GitLab From a283cdc4d3670700182c820b59078387f9a01a30 Mon Sep 17 00:00:00 2001 From: Mustafa Ismail Date: Tue, 21 Nov 2017 16:18:32 -0600 Subject: [PATCH 0430/2547] i40iw: Correct ARP index mask The ARP table entry indexes are aliased to 12bits instead of the intended 16bits when uploaded to the QP Context. This will present an issue when the number of connections exceeds 4096 as ARP entries are reused. Fix this by adjusting the mask to account for the full 16bits. Fixes: 4e9042e647ff ("i40iw: add hw and utils files") Signed-off-by: Mustafa Ismail Signed-off-by: Shiraz Saleem Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/i40iw/i40iw_d.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/i40iw/i40iw_d.h b/drivers/infiniband/hw/i40iw/i40iw_d.h index 1077b78f7754..029083cb81d5 100644 --- a/drivers/infiniband/hw/i40iw/i40iw_d.h +++ b/drivers/infiniband/hw/i40iw/i40iw_d.h @@ -1114,7 +1114,7 @@ #define I40IWQPC_VLANTAG_MASK (0xffffULL << I40IWQPC_VLANTAG_SHIFT) #define I40IWQPC_ARPIDX_SHIFT 48 -#define I40IWQPC_ARPIDX_MASK (0xfffULL << I40IWQPC_ARPIDX_SHIFT) +#define I40IWQPC_ARPIDX_MASK (0xffffULL << I40IWQPC_ARPIDX_SHIFT) #define I40IWQPC_FLOWLABEL_SHIFT 0 #define I40IWQPC_FLOWLABEL_MASK (0xfffffUL << I40IWQPC_FLOWLABEL_SHIFT) -- GitLab From 8bb45252bb5108485f590a08291d1f4641abc77e Mon Sep 17 00:00:00 2001 From: Tatyana Nikolova Date: Tue, 21 Nov 2017 16:18:33 -0600 Subject: [PATCH 0431/2547] i40iw: Move MPA request event for loopback after connect For loopback, a MPA request event is generated when cm_node is initialized, which allows applications to act on the connect request before i40iw_connect() has completed. In some cases, the reject flow executes in parallel with the connect flow and doesn't delete an APBVT entry, because the apbvt_set variable is still not set by the connect flow. Move the MPA request event to the end of i40iw_connect() to notify application for a connect request, after connect has completed. Fixes: f27b4746f378 ("i40iw: add connection management code") Signed-off-by: Tatyana Nikolova Signed-off-by: Henry Orosco Signed-off-by: Shiraz Saleem Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/i40iw/i40iw_cm.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/hw/i40iw/i40iw_cm.c b/drivers/infiniband/hw/i40iw/i40iw_cm.c index e1454174e3d9..57cf40733800 100644 --- a/drivers/infiniband/hw/i40iw/i40iw_cm.c +++ b/drivers/infiniband/hw/i40iw/i40iw_cm.c @@ -2947,8 +2947,6 @@ static struct i40iw_cm_node *i40iw_create_cm_node( loopback_remotenode->tcp_cntxt.snd_wnd = cm_node->tcp_cntxt.rcv_wnd; cm_node->tcp_cntxt.snd_wscale = loopback_remotenode->tcp_cntxt.rcv_wscale; loopback_remotenode->tcp_cntxt.snd_wscale = cm_node->tcp_cntxt.rcv_wscale; - loopback_remotenode->state = I40IW_CM_STATE_MPAREQ_RCVD; - i40iw_create_event(loopback_remotenode, I40IW_CM_EVENT_MPA_REQ); } return cm_node; } @@ -3864,6 +3862,12 @@ int i40iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param) goto err; } + if (cm_node->loopbackpartner) { + cm_node->loopbackpartner->state = I40IW_CM_STATE_MPAREQ_RCVD; + i40iw_create_event(cm_node->loopbackpartner, + I40IW_CM_EVENT_MPA_REQ); + } + i40iw_debug(cm_node->dev, I40IW_DEBUG_CM, "Api - connect(): port=0x%04x, cm_node=%p, cm_id = %p.\n", -- GitLab From a7c6dfe215a7f85c6195f09c1b9474a2ba7fea9c Mon Sep 17 00:00:00 2001 From: Henry Orosco Date: Tue, 21 Nov 2017 16:18:34 -0600 Subject: [PATCH 0432/2547] i40iw: Notify user of established connection after QP in RTS Established CM event is sent prior to modifying QP to RTS state. This can result in application closing the connection before the QP is actually in RTS state. Move sending of established CM event to after modify QP to RTS. Fixes: f27b4746f378 ("i40iw: add connection management code") Signed-off-by: Henry Orosco Signed-off-by: Shiraz Saleem Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/i40iw/i40iw_cm.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/infiniband/hw/i40iw/i40iw_cm.c b/drivers/infiniband/hw/i40iw/i40iw_cm.c index 57cf40733800..77870f9e1736 100644 --- a/drivers/infiniband/hw/i40iw/i40iw_cm.c +++ b/drivers/infiniband/hw/i40iw/i40iw_cm.c @@ -3687,11 +3687,16 @@ int i40iw_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param) cm_id->add_ref(cm_id); i40iw_add_ref(&iwqp->ibqp); - i40iw_send_cm_event(cm_node, cm_id, IW_CM_EVENT_ESTABLISHED, 0); - attr.qp_state = IB_QPS_RTS; cm_node->qhash_set = false; i40iw_modify_qp(&iwqp->ibqp, &attr, IB_QP_STATE, NULL); + + cm_node->accelerated = 1; + status = + i40iw_send_cm_event(cm_node, cm_id, IW_CM_EVENT_ESTABLISHED, 0); + if (status) + i40iw_debug(dev, I40IW_DEBUG_CM, "error sending cm event - ESTABLISHED\n"); + if (cm_node->loopbackpartner) { cm_node->loopbackpartner->pdata.size = conn_param->private_data_len; @@ -3702,7 +3707,6 @@ int i40iw_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param) i40iw_create_event(cm_node->loopbackpartner, I40IW_CM_EVENT_CONNECTED); } - cm_node->accelerated = 1; if (cm_node->accept_pend) { atomic_dec(&cm_node->listener->pend_accepts_cnt); cm_node->accept_pend = 0; @@ -4048,9 +4052,6 @@ static void i40iw_cm_event_connected(struct i40iw_cm_event *event) dev->iw_priv_qp_ops->qp_send_rtt(&iwqp->sc_qp, read0); if (iwqp->page) kunmap(iwqp->page); - status = i40iw_send_cm_event(cm_node, cm_id, IW_CM_EVENT_CONNECT_REPLY, 0); - if (status) - i40iw_pr_err("send cm event\n"); memset(&attr, 0, sizeof(attr)); attr.qp_state = IB_QPS_RTS; @@ -4058,6 +4059,10 @@ static void i40iw_cm_event_connected(struct i40iw_cm_event *event) i40iw_modify_qp(&iwqp->ibqp, &attr, IB_QP_STATE, NULL); cm_node->accelerated = 1; + status = i40iw_send_cm_event(cm_node, cm_id, IW_CM_EVENT_CONNECT_REPLY, + 0); + if (status) + i40iw_debug(dev, I40IW_DEBUG_CM, "error sending cm event - CONNECT_REPLY\n"); return; -- GitLab From 23a9cd2ad90543e9da3786878d2b2729c095439d Mon Sep 17 00:00:00 2001 From: Moni Shoua Date: Sun, 26 Nov 2017 20:23:54 +0200 Subject: [PATCH 0433/2547] RDMA/cma: Make sure that PSN is not over max allowed This patch limits the initial value for PSN to 24 bits as spec requires. Signed-off-by: Moni Shoua Signed-off-by: Mukesh Kacker Signed-off-by: Daniel Jurgens Reviewed-by: Parav Pandit Signed-off-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe --- drivers/infiniband/core/cma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/infiniband/core/cma.c b/drivers/infiniband/core/cma.c index 1fdb473b5df7..f6983357145d 100644 --- a/drivers/infiniband/core/cma.c +++ b/drivers/infiniband/core/cma.c @@ -801,6 +801,7 @@ struct rdma_cm_id *rdma_create_id(struct net *net, INIT_LIST_HEAD(&id_priv->mc_list); get_random_bytes(&id_priv->seq_num, sizeof id_priv->seq_num); id_priv->id.route.addr.dev_addr.net = get_net(net); + id_priv->seq_num &= 0x00ffffff; return &id_priv->id; } -- GitLab From a9cd1a673737dd81332fce1145801bfacfb90d90 Mon Sep 17 00:00:00 2001 From: Dmitry Monakhov Date: Mon, 27 Nov 2017 13:39:05 +0000 Subject: [PATCH 0434/2547] IB/core: Init subsys if compiled to vmlinuz-core Once infiniband is compiled as a core component its subsystem must be enabled before device initialization. Otherwise there is a NULL pointer dereference during mlx4_core init, calltrace: ->device_add if (dev->class) { deref dev->class->p =>NULLPTR #Config CONFIG_NET_DEVLINK=y CONFIG_MAY_USE_DEVLINK=y CONFIG_MLX4_EN=y Signed-off-by: Dmitry Monakhov Reviewed-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe --- drivers/infiniband/core/device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/core/device.c b/drivers/infiniband/core/device.c index 84fc32a2c8b3..5e1be4949d5f 100644 --- a/drivers/infiniband/core/device.c +++ b/drivers/infiniband/core/device.c @@ -1253,5 +1253,5 @@ static void __exit ib_core_cleanup(void) MODULE_ALIAS_RDMA_NETLINK(RDMA_NL_LS, 4); -module_init(ib_core_init); +subsys_initcall(ib_core_init); module_exit(ib_core_cleanup); -- GitLab From db270c41900d39a388990701da3ee2971094ebaa Mon Sep 17 00:00:00 2001 From: "Wei Hu\\(Xavier\\)" Date: Tue, 28 Nov 2017 15:10:26 +0800 Subject: [PATCH 0435/2547] RDMA/hns: Fix the issue of IOVA not page continuous in hip08 If the smmu is enabled, the length of sg obtained from __iommu_map_sg_attrs is not 4kB. When the IOVA is set with the sg dma address, the IOVA will not be page continuous. so, the current code has MTPT configuration error that probably cause dma operation failure. In order to fix this issue, the IOVA should be calculated based on the sg length. Fixes: 3958cc5("RDMA/hns: Configure the MTPT in hip08") Signed-off-by: Wei Hu (Xavier) Signed-off-by: Shaobo Xu Signed-off-by: Lijun Ou Signed-off-by: Yixian Liu Signed-off-by: Xiping Zhang (Francis) Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index 8f719c00467b..8e18445714a9 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -1126,9 +1126,11 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, { struct hns_roce_v2_mpt_entry *mpt_entry; struct scatterlist *sg; + u64 page_addr; u64 *pages; + int i, j; + int len; int entry; - int i; mpt_entry = mb_buf; memset(mpt_entry, 0, sizeof(*mpt_entry)); @@ -1186,14 +1188,20 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, i = 0; for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) { - pages[i] = ((u64)sg_dma_address(sg)) >> 6; - - /* Record the first 2 entry directly to MTPT table */ - if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1) - break; - i++; + len = sg_dma_len(sg) >> PAGE_SHIFT; + for (j = 0; j < len; ++j) { + page_addr = sg_dma_address(sg) + + (j << mr->umem->page_shift); + pages[i] = page_addr >> 6; + + /* Record the first 2 entry directly to MTPT table */ + if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1) + goto found; + i++; + } } +found: mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, V2_MPT_BYTE_56_PA0_H_S, -- GitLab From b1c158350968d6717ec1889f07ea3a89432e8574 Mon Sep 17 00:00:00 2001 From: "Wei Hu\\(Xavier\\)" Date: Tue, 28 Nov 2017 15:10:27 +0800 Subject: [PATCH 0436/2547] RDMA/hns: Get rid of virt_to_page and vmap calls after dma_alloc_coherent In general dma_alloc_coherent() returns a CPU virtual address and a DMA address, and we have no guarantee that the virtual address is either in the linear map or vmalloc. It could be in some other special place. We have no guarantee that the underlying memory even has an associated struct page at all. In current code, there are incorrect usage as below: dma_alloc_coherent + virt_to_page + vmap. There will probably introduce coherency problem. This patch fixes it to get rid of virt_to_page and vmap calls at Leon's suggestion. The related link: https://lkml.org/lkml/2017/11/7/34 Fixes: 9a44353("IB/hns: Add driver files for hns RoCE driver") Signed-off-by: Wei Hu (Xavier) Signed-off-by: Shaobo Xu Signed-off-by: Lijun Ou Signed-off-by: Yixian Liu Signed-off-by: Xiping Zhang (Francis) Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/hns/hns_roce_alloc.c | 23 --------------------- drivers/infiniband/hw/hns/hns_roce_device.h | 4 +--- 2 files changed, 1 insertion(+), 26 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_alloc.c b/drivers/infiniband/hw/hns/hns_roce_alloc.c index 3e4c5253ab5c..a40ec939ece5 100644 --- a/drivers/infiniband/hw/hns/hns_roce_alloc.c +++ b/drivers/infiniband/hw/hns/hns_roce_alloc.c @@ -162,14 +162,10 @@ void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size, { int i; struct device *dev = hr_dev->dev; - u32 bits_per_long = BITS_PER_LONG; if (buf->nbufs == 1) { dma_free_coherent(dev, size, buf->direct.buf, buf->direct.map); } else { - if (bits_per_long == 64 && buf->page_shift == PAGE_SHIFT) - vunmap(buf->direct.buf); - for (i = 0; i < buf->nbufs; ++i) if (buf->page_list[i].buf) dma_free_coherent(dev, 1 << buf->page_shift, @@ -185,9 +181,7 @@ int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, { int i = 0; dma_addr_t t; - struct page **pages; struct device *dev = hr_dev->dev; - u32 bits_per_long = BITS_PER_LONG; u32 page_size = 1 << page_shift; u32 order; @@ -236,23 +230,6 @@ int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, buf->page_list[i].map = t; memset(buf->page_list[i].buf, 0, page_size); } - if (bits_per_long == 64 && page_shift == PAGE_SHIFT) { - pages = kmalloc_array(buf->nbufs, sizeof(*pages), - GFP_KERNEL); - if (!pages) - goto err_free; - - for (i = 0; i < buf->nbufs; ++i) - pages[i] = virt_to_page(buf->page_list[i].buf); - - buf->direct.buf = vmap(pages, buf->nbufs, VM_MAP, - PAGE_KERNEL); - kfree(pages); - if (!buf->direct.buf) - goto err_free; - } else { - buf->direct.buf = NULL; - } } return 0; diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index 01d3d695cbba..b154ce40cded 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -726,11 +726,9 @@ static inline struct hns_roce_qp static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset) { - u32 bits_per_long_val = BITS_PER_LONG; u32 page_size = 1 << buf->page_shift; - if ((bits_per_long_val == 64 && buf->page_shift == PAGE_SHIFT) || - buf->nbufs == 1) + if (buf->nbufs == 1) return (char *)(buf->direct.buf) + offset; else return (char *)(buf->page_list[offset >> buf->page_shift].buf) + -- GitLab From 378efe798ecf0e7d9730a595ef3419b046e34fb4 Mon Sep 17 00:00:00 2001 From: "Wei Hu\\(Xavier\\)" Date: Tue, 28 Nov 2017 15:10:28 +0800 Subject: [PATCH 0437/2547] RDMA/hns: Get rid of page operation after dma_alloc_coherent In general, dma_alloc_coherent() returns a CPU virtual address and a DMA address, and we have no guarantee that the underlying memory even has an associated struct page at all. This patch gets rid of the page operation after dma_alloc_coherent, and records the VA returned form dma_alloc_coherent in the struct of hem in hns RoCE driver. Fixes: 9a44353("IB/hns: Add driver files for hns RoCE driver") Signed-off-by: Wei Hu (Xavier) Signed-off-by: Shaobo Xu Signed-off-by: Lijun Ou Signed-off-by: Yixian Liu Signed-off-by: Xiping Zhang (Francis) Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/hns/hns_roce_hem.c | 25 ++++++++++++------------ drivers/infiniband/hw/hns/hns_roce_hem.h | 1 + 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_hem.c b/drivers/infiniband/hw/hns/hns_roce_hem.c index 8b733a66fae5..0eeabfbee192 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hem.c +++ b/drivers/infiniband/hw/hns/hns_roce_hem.c @@ -224,6 +224,7 @@ static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev, sg_init_table(chunk->mem, HNS_ROCE_HEM_CHUNK_LEN); chunk->npages = 0; chunk->nsg = 0; + memset(chunk->buf, 0, sizeof(chunk->buf)); list_add_tail(&chunk->list, &hem->chunk_list); } @@ -240,8 +241,7 @@ static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev, if (!buf) goto fail; - sg_set_buf(mem, buf, PAGE_SIZE << order); - WARN_ON(mem->offset); + chunk->buf[chunk->npages] = buf; sg_dma_len(mem) = PAGE_SIZE << order; ++chunk->npages; @@ -267,8 +267,8 @@ void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem) list_for_each_entry_safe(chunk, tmp, &hem->chunk_list, list) { for (i = 0; i < chunk->npages; ++i) dma_free_coherent(hr_dev->dev, - chunk->mem[i].length, - lowmem_page_address(sg_page(&chunk->mem[i])), + sg_dma_len(&chunk->mem[i]), + chunk->buf[i], sg_dma_address(&chunk->mem[i])); kfree(chunk); } @@ -722,11 +722,12 @@ void *hns_roce_table_find(struct hns_roce_dev *hr_dev, struct hns_roce_hem_chunk *chunk; struct hns_roce_hem_mhop mhop; struct hns_roce_hem *hem; - struct page *page = NULL; + void *addr = NULL; unsigned long mhop_obj = obj; unsigned long obj_per_chunk; unsigned long idx_offset; int offset, dma_offset; + int length; int i, j; u32 hem_idx = 0; @@ -763,25 +764,25 @@ void *hns_roce_table_find(struct hns_roce_dev *hr_dev, list_for_each_entry(chunk, &hem->chunk_list, list) { for (i = 0; i < chunk->npages; ++i) { + length = sg_dma_len(&chunk->mem[i]); if (dma_handle && dma_offset >= 0) { - if (sg_dma_len(&chunk->mem[i]) > - (u32)dma_offset) + if (length > (u32)dma_offset) *dma_handle = sg_dma_address( &chunk->mem[i]) + dma_offset; - dma_offset -= sg_dma_len(&chunk->mem[i]); + dma_offset -= length; } - if (chunk->mem[i].length > (u32)offset) { - page = sg_page(&chunk->mem[i]); + if (length > (u32)offset) { + addr = chunk->buf[i] + offset; goto out; } - offset -= chunk->mem[i].length; + offset -= length; } } out: mutex_unlock(&table->mutex); - return page ? lowmem_page_address(page) + offset : NULL; + return addr; } EXPORT_SYMBOL_GPL(hns_roce_table_find); diff --git a/drivers/infiniband/hw/hns/hns_roce_hem.h b/drivers/infiniband/hw/hns/hns_roce_hem.h index db66db12075e..e8850d59e780 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hem.h +++ b/drivers/infiniband/hw/hns/hns_roce_hem.h @@ -78,6 +78,7 @@ struct hns_roce_hem_chunk { int npages; int nsg; struct scatterlist mem[HNS_ROCE_HEM_CHUNK_LEN]; + void *buf[HNS_ROCE_HEM_CHUNK_LEN]; }; struct hns_roce_hem { -- GitLab From 315d160c5a4e034a576a13aa21e7235d5c9ec609 Mon Sep 17 00:00:00 2001 From: Daniel Jurgens Date: Wed, 29 Nov 2017 20:10:39 +0200 Subject: [PATCH 0438/2547] IB/core: Only enforce security for InfiniBand For now the only LSM security enforcement mechanism available is specific to InfiniBand. Bypass enforcement for non-IB link types. This fixes a regression where modify_qp fails for iWARP because querying the PKEY returns -EINVAL. Cc: Paul Moore Cc: Don Dutile Cc: stable@vger.kernel.org Reported-by: Potnuri Bharat Teja Fixes: d291f1a65232("IB/core: Enforce PKey security on QPs") Fixes: 47a2b338fe63("IB/core: Enforce security on management datagrams") Signed-off-by: Daniel Jurgens Reviewed-by: Parav Pandit Tested-by: Potnuri Bharat Teja Signed-off-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe --- drivers/infiniband/core/security.c | 50 +++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 4 deletions(-) diff --git a/drivers/infiniband/core/security.c b/drivers/infiniband/core/security.c index 23278ed5be45..a337386652b0 100644 --- a/drivers/infiniband/core/security.c +++ b/drivers/infiniband/core/security.c @@ -417,8 +417,17 @@ void ib_close_shared_qp_security(struct ib_qp_security *sec) int ib_create_qp_security(struct ib_qp *qp, struct ib_device *dev) { + u8 i = rdma_start_port(dev); + bool is_ib = false; int ret; + while (i <= rdma_end_port(dev) && !is_ib) + is_ib = rdma_protocol_ib(dev, i++); + + /* If this isn't an IB device don't create the security context */ + if (!is_ib) + return 0; + qp->qp_sec = kzalloc(sizeof(*qp->qp_sec), GFP_KERNEL); if (!qp->qp_sec) return -ENOMEM; @@ -441,6 +450,10 @@ EXPORT_SYMBOL(ib_create_qp_security); void ib_destroy_qp_security_begin(struct ib_qp_security *sec) { + /* Return if not IB */ + if (!sec) + return; + mutex_lock(&sec->mutex); /* Remove the QP from the lists so it won't get added to @@ -470,6 +483,10 @@ void ib_destroy_qp_security_abort(struct ib_qp_security *sec) int ret; int i; + /* Return if not IB */ + if (!sec) + return; + /* If a concurrent cache update is in progress this * QP security could be marked for an error state * transition. Wait for this to complete. @@ -505,6 +522,10 @@ void ib_destroy_qp_security_end(struct ib_qp_security *sec) { int i; + /* Return if not IB */ + if (!sec) + return; + /* If a concurrent cache update is occurring we must * wait until this QP security structure is processed * in the QP to error flow before destroying it because @@ -557,7 +578,7 @@ int ib_security_modify_qp(struct ib_qp *qp, { int ret = 0; struct ib_ports_pkeys *tmp_pps; - struct ib_ports_pkeys *new_pps; + struct ib_ports_pkeys *new_pps = NULL; struct ib_qp *real_qp = qp->real_qp; bool special_qp = (real_qp->qp_type == IB_QPT_SMI || real_qp->qp_type == IB_QPT_GSI || @@ -565,18 +586,27 @@ int ib_security_modify_qp(struct ib_qp *qp, bool pps_change = ((qp_attr_mask & (IB_QP_PKEY_INDEX | IB_QP_PORT)) || (qp_attr_mask & IB_QP_ALT_PATH)); + WARN_ONCE((qp_attr_mask & IB_QP_PORT && + rdma_protocol_ib(real_qp->device, qp_attr->port_num) && + !real_qp->qp_sec), + "%s: QP security is not initialized for IB QP: %d\n", + __func__, real_qp->qp_num); + /* The port/pkey settings are maintained only for the real QP. Open * handles on the real QP will be in the shared_qp_list. When * enforcing security on the real QP all the shared QPs will be * checked as well. */ - if (pps_change && !special_qp) { + if (pps_change && !special_qp && real_qp->qp_sec) { mutex_lock(&real_qp->qp_sec->mutex); new_pps = get_new_pps(real_qp, qp_attr, qp_attr_mask); - + if (!new_pps) { + mutex_unlock(&real_qp->qp_sec->mutex); + return -ENOMEM; + } /* Add this QP to the lists for the new port * and pkey settings before checking for permission * in case there is a concurrent cache update @@ -600,7 +630,7 @@ int ib_security_modify_qp(struct ib_qp *qp, qp_attr_mask, udata); - if (pps_change && !special_qp) { + if (new_pps) { /* Clean up the lists and free the appropriate * ports_pkeys structure. */ @@ -631,6 +661,9 @@ int ib_security_pkey_access(struct ib_device *dev, u16 pkey; int ret; + if (!rdma_protocol_ib(dev, port_num)) + return 0; + ret = ib_get_cached_pkey(dev, port_num, pkey_index, &pkey); if (ret) return ret; @@ -665,6 +698,9 @@ int ib_mad_agent_security_setup(struct ib_mad_agent *agent, { int ret; + if (!rdma_protocol_ib(agent->device, agent->port_num)) + return 0; + ret = security_ib_alloc_security(&agent->security); if (ret) return ret; @@ -690,6 +726,9 @@ int ib_mad_agent_security_setup(struct ib_mad_agent *agent, void ib_mad_agent_security_cleanup(struct ib_mad_agent *agent) { + if (!rdma_protocol_ib(agent->device, agent->port_num)) + return; + security_ib_free_security(agent->security); if (agent->lsm_nb_reg) unregister_lsm_notifier(&agent->lsm_nb); @@ -697,6 +736,9 @@ void ib_mad_agent_security_cleanup(struct ib_mad_agent *agent) int ib_mad_enforce_security(struct ib_mad_agent_private *map, u16 pkey_index) { + if (!rdma_protocol_ib(map->agent.device, map->agent.port_num)) + return 0; + if (map->agent.qp->qp_type == IB_QPT_SMI && !map->agent.smp_allowed) return -EACCES; -- GitLab From aff69d89bdebc39235cddb4445371eb979b49685 Mon Sep 17 00:00:00 2001 From: bingjingc Date: Fri, 17 Nov 2017 10:57:44 +0800 Subject: [PATCH 0439/2547] md/raid5: correct degraded calculation in raid5_error When disk failure occurs on new disks for reshape, mddev->degraded is not calculated correctly. Faulty bit of the failure device is not set before raid5_calc_degraded(conf). mdadm --create /dev/md0 --level=5 --raid-devices=3 /dev/loop[012] mdadm /dev/md0 -a /dev/loop3 mdadm /dev/md0 --grow -n4 mdadm /dev/md0 -f /dev/loop3 # simulating disk failure cat /sys/block/md0/md/degraded # it outputs 0, but it should be 1. However, mdadm -D /dev/md0 will show that it is degraded. It's a bug. It can be fixed by moving the resources raid5_calc_degraded() depends on before it. Reported-by: Roy Chung Reviewed-by: Alex Wu Signed-off-by: BingJing Chang Signed-off-by: Shaohua Li --- drivers/md/raid5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 31dc25e2871a..98ce4272ace9 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -2677,13 +2677,13 @@ static void raid5_error(struct mddev *mddev, struct md_rdev *rdev) pr_debug("raid456: error called\n"); spin_lock_irqsave(&conf->device_lock, flags); + set_bit(Faulty, &rdev->flags); clear_bit(In_sync, &rdev->flags); mddev->degraded = raid5_calc_degraded(conf); spin_unlock_irqrestore(&conf->device_lock, flags); set_bit(MD_RECOVERY_INTR, &mddev->recovery); set_bit(Blocked, &rdev->flags); - set_bit(Faulty, &rdev->flags); set_mask_bits(&mddev->sb_flags, 0, BIT(MD_SB_CHANGE_DEVS) | BIT(MD_SB_CHANGE_PENDING)); pr_crit("md/raid:%s: Disk failure on %s, disabling device.\n" -- GitLab From ff35f58e8f8eb520367879a0ccc6f2ec4b62b17b Mon Sep 17 00:00:00 2001 From: Song Liu Date: Sun, 19 Nov 2017 22:17:00 -0800 Subject: [PATCH 0440/2547] md/r5cache: move mddev_lock() out of r5c_journal_mode_set() r5c_journal_mode_set() is called by r5c_journal_mode_store() and raid_ctr() in dm-raid. We don't need mddev_lock() when calling from raid_ctr(). This patch fixes this by moves the mddev_lock() to r5c_journal_mode_store(). Cc: stable@vger.kernel.org (v4.13+) Signed-off-by: Song Liu Signed-off-by: Shaohua Li --- drivers/md/raid5-cache.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/md/raid5-cache.c b/drivers/md/raid5-cache.c index f1c86d938502..39f31f07ffe9 100644 --- a/drivers/md/raid5-cache.c +++ b/drivers/md/raid5-cache.c @@ -2577,31 +2577,22 @@ static ssize_t r5c_journal_mode_show(struct mddev *mddev, char *page) int r5c_journal_mode_set(struct mddev *mddev, int mode) { struct r5conf *conf; - int err; if (mode < R5C_JOURNAL_MODE_WRITE_THROUGH || mode > R5C_JOURNAL_MODE_WRITE_BACK) return -EINVAL; - err = mddev_lock(mddev); - if (err) - return err; conf = mddev->private; - if (!conf || !conf->log) { - mddev_unlock(mddev); + if (!conf || !conf->log) return -ENODEV; - } if (raid5_calc_degraded(conf) > 0 && - mode == R5C_JOURNAL_MODE_WRITE_BACK) { - mddev_unlock(mddev); + mode == R5C_JOURNAL_MODE_WRITE_BACK) return -EINVAL; - } mddev_suspend(mddev); conf->log->r5c_journal_mode = mode; mddev_resume(mddev); - mddev_unlock(mddev); pr_debug("md/raid:%s: setting r5c cache mode to %d: %s\n", mdname(mddev), mode, r5c_journal_mode_str[mode]); @@ -2614,6 +2605,7 @@ static ssize_t r5c_journal_mode_store(struct mddev *mddev, { int mode = ARRAY_SIZE(r5c_journal_mode_str); size_t len = length; + int ret; if (len < 2) return -EINVAL; @@ -2625,8 +2617,12 @@ static ssize_t r5c_journal_mode_store(struct mddev *mddev, if (strlen(r5c_journal_mode_str[mode]) == len && !strncmp(page, r5c_journal_mode_str[mode], len)) break; - - return r5c_journal_mode_set(mddev, mode) ?: length; + ret = mddev_lock(mddev); + if (ret) + return ret; + ret = r5c_journal_mode_set(mddev, mode); + mddev_unlock(mddev); + return ret ?: length; } struct md_sysfs_entry -- GitLab From d30fc5126efb0c33b7adf5966d3051db2c3d7721 Mon Sep 17 00:00:00 2001 From: Xin Long Date: Sat, 25 Nov 2017 21:18:34 +0800 Subject: [PATCH 0441/2547] sctp: only update outstanding_bytes for transmitted queue when doing prsctp_prune Now outstanding_bytes is only increased when appending chunks into one packet and sending it at 1st time, while decreased when it is about to move into retransmit queue. It means outstanding_bytes value is already decreased for all chunks in retransmit queue. However sctp_prsctp_prune_sent is a common function to check the chunks in both transmitted and retransmit queue, it decrease outstanding_bytes when moving a chunk into abandoned queue from either of them. It could cause outstanding_bytes underflow, as it also decreases it's value for the chunks in retransmit queue. This patch fixes it by only updating outstanding_bytes for transmitted queue when pruning queues for prsctp prio policy, the same fix is also needed in sctp_check_transmitted. Fixes: 8dbdf1f5b09c ("sctp: implement prsctp PRIO policy") Signed-off-by: Xin Long Acked-by: Marcelo Ricardo Leitner Signed-off-by: David S. Miller --- net/sctp/outqueue.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/net/sctp/outqueue.c b/net/sctp/outqueue.c index 4db012aa25f7..7029f8b99063 100644 --- a/net/sctp/outqueue.c +++ b/net/sctp/outqueue.c @@ -377,7 +377,8 @@ static int sctp_prsctp_prune_sent(struct sctp_association *asoc, asoc->abandoned_sent[SCTP_PR_INDEX(PRIO)]++; streamout->ext->abandoned_sent[SCTP_PR_INDEX(PRIO)]++; - if (!chk->tsn_gap_acked) { + if (queue != &asoc->outqueue.retransmit && + !chk->tsn_gap_acked) { if (chk->transport) chk->transport->flight_size -= sctp_data_size(chk); @@ -1434,7 +1435,8 @@ static void sctp_check_transmitted(struct sctp_outq *q, /* If this chunk has not been acked, stop * considering it as 'outstanding'. */ - if (!tchunk->tsn_gap_acked) { + if (transmitted_queue != &q->retransmit && + !tchunk->tsn_gap_acked) { if (tchunk->transport) tchunk->transport->flight_size -= sctp_data_size(tchunk); -- GitLab From e5f612969c6f965e3bd1158598e0a3b1c4f389b9 Mon Sep 17 00:00:00 2001 From: Xin Long Date: Sat, 25 Nov 2017 21:18:35 +0800 Subject: [PATCH 0442/2547] sctp: abandon the whole msg if one part of a fragmented message is abandoned As rfc3758#section-3.1 demands: A3) When a TSN is "abandoned", if it is part of a fragmented message, all other TSN's within that fragmented message MUST be abandoned at the same time. Besides, if it couldn't handle this, the rest frags would never get assembled in peer side. This patch supports it by adding abandoned flag in sctp_datamsg, when one chunk is being abandoned, set chunk->msg->abandoned as well. Next time when checking for abandoned, go checking chunk->msg->abandoned first. Signed-off-by: Xin Long Acked-by: Marcelo Ricardo Leitner Signed-off-by: David S. Miller --- include/net/sctp/structs.h | 3 ++- net/sctp/chunk.c | 7 +++++++ net/sctp/outqueue.c | 12 ++++++++---- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h index 16f949eef52f..2f8f93da5dc2 100644 --- a/include/net/sctp/structs.h +++ b/include/net/sctp/structs.h @@ -503,7 +503,8 @@ struct sctp_datamsg { /* Did the messenge fail to send? */ int send_error; u8 send_failed:1, - can_delay; /* should this message be Nagle delayed */ + can_delay:1, /* should this message be Nagle delayed */ + abandoned:1; /* should this message be abandoned */ }; struct sctp_datamsg *sctp_datamsg_from_user(struct sctp_association *, diff --git a/net/sctp/chunk.c b/net/sctp/chunk.c index 7b261afc47b9..9213805b558d 100644 --- a/net/sctp/chunk.c +++ b/net/sctp/chunk.c @@ -53,6 +53,7 @@ static void sctp_datamsg_init(struct sctp_datamsg *msg) msg->send_failed = 0; msg->send_error = 0; msg->can_delay = 1; + msg->abandoned = 0; msg->expires_at = 0; INIT_LIST_HEAD(&msg->chunks); } @@ -304,6 +305,9 @@ int sctp_chunk_abandoned(struct sctp_chunk *chunk) if (!chunk->asoc->peer.prsctp_capable) return 0; + if (chunk->msg->abandoned) + return 1; + if (SCTP_PR_TTL_ENABLED(chunk->sinfo.sinfo_flags) && time_after(jiffies, chunk->msg->expires_at)) { struct sctp_stream_out *streamout = @@ -316,6 +320,7 @@ int sctp_chunk_abandoned(struct sctp_chunk *chunk) chunk->asoc->abandoned_unsent[SCTP_PR_INDEX(TTL)]++; streamout->ext->abandoned_unsent[SCTP_PR_INDEX(TTL)]++; } + chunk->msg->abandoned = 1; return 1; } else if (SCTP_PR_RTX_ENABLED(chunk->sinfo.sinfo_flags) && chunk->sent_count > chunk->sinfo.sinfo_timetolive) { @@ -324,10 +329,12 @@ int sctp_chunk_abandoned(struct sctp_chunk *chunk) chunk->asoc->abandoned_sent[SCTP_PR_INDEX(RTX)]++; streamout->ext->abandoned_sent[SCTP_PR_INDEX(RTX)]++; + chunk->msg->abandoned = 1; return 1; } else if (!SCTP_PR_POLICY(chunk->sinfo.sinfo_flags) && chunk->msg->expires_at && time_after(jiffies, chunk->msg->expires_at)) { + chunk->msg->abandoned = 1; return 1; } /* PRIO policy is processed by sendmsg, not here */ diff --git a/net/sctp/outqueue.c b/net/sctp/outqueue.c index 7029f8b99063..4ab164b5aad0 100644 --- a/net/sctp/outqueue.c +++ b/net/sctp/outqueue.c @@ -364,10 +364,12 @@ static int sctp_prsctp_prune_sent(struct sctp_association *asoc, list_for_each_entry_safe(chk, temp, queue, transmitted_list) { struct sctp_stream_out *streamout; - if (!SCTP_PR_PRIO_ENABLED(chk->sinfo.sinfo_flags) || - chk->sinfo.sinfo_timetolive <= sinfo->sinfo_timetolive) + if (!chk->msg->abandoned && + (!SCTP_PR_PRIO_ENABLED(chk->sinfo.sinfo_flags) || + chk->sinfo.sinfo_timetolive <= sinfo->sinfo_timetolive)) continue; + chk->msg->abandoned = 1; list_del_init(&chk->transmitted_list); sctp_insert_list(&asoc->outqueue.abandoned, &chk->transmitted_list); @@ -404,10 +406,12 @@ static int sctp_prsctp_prune_unsent(struct sctp_association *asoc, q->sched->unsched_all(&asoc->stream); list_for_each_entry_safe(chk, temp, &q->out_chunk_list, list) { - if (!SCTP_PR_PRIO_ENABLED(chk->sinfo.sinfo_flags) || - chk->sinfo.sinfo_timetolive <= sinfo->sinfo_timetolive) + if (!chk->msg->abandoned && + (!SCTP_PR_PRIO_ENABLED(chk->sinfo.sinfo_flags) || + chk->sinfo.sinfo_timetolive <= sinfo->sinfo_timetolive)) continue; + chk->msg->abandoned = 1; sctp_sched_dequeue_common(q, chk); asoc->sent_cnt_removable--; asoc->abandoned_unsent[SCTP_PR_INDEX(PRIO)]++; -- GitLab From 779edd7348878a7376c0e3d0f96485c30b5f1b7d Mon Sep 17 00:00:00 2001 From: Xin Long Date: Sat, 25 Nov 2017 21:18:36 +0800 Subject: [PATCH 0443/2547] sctp: do not abandon the other frags in unsent outq if one msg has outstanding frags Now for the abandoned chunks in unsent outq, it would just free the chunks. Because no tsn is assigned to them yet, there's no need to send fwd tsn to peer, unlike for the abandoned chunks in sent outq. The problem is when parts of the msg have been sent and the other frags are still in unsent outq, if they are abandoned/dropped, the peer would never get this msg reassembled. So these frags in unsent outq can't be dropped if this msg already has outstanding frags. This patch does the check in sctp_chunk_abandoned and sctp_prsctp_prune_unsent. Signed-off-by: Xin Long Acked-by: Marcelo Ricardo Leitner Signed-off-by: David S. Miller --- net/sctp/chunk.c | 4 ++++ net/sctp/outqueue.c | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/net/sctp/chunk.c b/net/sctp/chunk.c index 9213805b558d..7f8baa48e7c2 100644 --- a/net/sctp/chunk.c +++ b/net/sctp/chunk.c @@ -308,6 +308,10 @@ int sctp_chunk_abandoned(struct sctp_chunk *chunk) if (chunk->msg->abandoned) return 1; + if (!chunk->has_tsn && + !(chunk->chunk_hdr->flags & SCTP_DATA_FIRST_FRAG)) + return 0; + if (SCTP_PR_TTL_ENABLED(chunk->sinfo.sinfo_flags) && time_after(jiffies, chunk->msg->expires_at)) { struct sctp_stream_out *streamout = diff --git a/net/sctp/outqueue.c b/net/sctp/outqueue.c index 4ab164b5aad0..7d67feeeffc1 100644 --- a/net/sctp/outqueue.c +++ b/net/sctp/outqueue.c @@ -407,7 +407,8 @@ static int sctp_prsctp_prune_unsent(struct sctp_association *asoc, list_for_each_entry_safe(chk, temp, &q->out_chunk_list, list) { if (!chk->msg->abandoned && - (!SCTP_PR_PRIO_ENABLED(chk->sinfo.sinfo_flags) || + (!(chk->chunk_hdr->flags & SCTP_DATA_FIRST_FRAG) || + !SCTP_PR_PRIO_ENABLED(chk->sinfo.sinfo_flags) || chk->sinfo.sinfo_timetolive <= sinfo->sinfo_timetolive)) continue; -- GitLab From cfac7f836a715b91f08c851df915d401a4d52783 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 1 Dec 2017 10:06:56 -0800 Subject: [PATCH 0444/2547] tcp/dccp: block bh before arming time_wait timer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Maciej Żenczykowski reported some panics in tcp_twsk_destructor() that might be caused by the following bug. timewait timer is pinned to the cpu, because we want to transition timwewait refcount from 0 to 4 in one go, once everything has been initialized. At the time commit ed2e92394589 ("tcp/dccp: fix timewait races in timer handling") was merged, TCP was always running from BH habdler. After commit 5413d1babe8f ("net: do not block BH while processing socket backlog") we definitely can run tcp_time_wait() from process context. We need to block BH in the critical section so that the pinned timer has still its purpose. This bug is more likely to happen under stress and when very small RTO are used in datacenter flows. Fixes: 5413d1babe8f ("net: do not block BH while processing socket backlog") Signed-off-by: Eric Dumazet Reported-by: Maciej Żenczykowski Acked-by: Maciej Żenczykowski Signed-off-by: David S. Miller --- net/dccp/minisocks.c | 6 ++++++ net/ipv4/tcp_minisocks.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/net/dccp/minisocks.c b/net/dccp/minisocks.c index abd07a443219..178bb9833311 100644 --- a/net/dccp/minisocks.c +++ b/net/dccp/minisocks.c @@ -57,10 +57,16 @@ void dccp_time_wait(struct sock *sk, int state, int timeo) if (state == DCCP_TIME_WAIT) timeo = DCCP_TIMEWAIT_LEN; + /* tw_timer is pinned, so we need to make sure BH are disabled + * in following section, otherwise timer handler could run before + * we complete the initialization. + */ + local_bh_disable(); inet_twsk_schedule(tw, timeo); /* Linkage updates. */ __inet_twsk_hashdance(tw, sk, &dccp_hashinfo); inet_twsk_put(tw); + local_bh_enable(); } else { /* Sorry, if we're out of memory, just CLOSE this * socket up. We've got bigger problems than diff --git a/net/ipv4/tcp_minisocks.c b/net/ipv4/tcp_minisocks.c index e36eff0403f4..b079b619b60c 100644 --- a/net/ipv4/tcp_minisocks.c +++ b/net/ipv4/tcp_minisocks.c @@ -310,10 +310,16 @@ void tcp_time_wait(struct sock *sk, int state, int timeo) if (state == TCP_TIME_WAIT) timeo = TCP_TIMEWAIT_LEN; + /* tw_timer is pinned, so we need to make sure BH are disabled + * in following section, otherwise timer handler could run before + * we complete the initialization. + */ + local_bh_disable(); inet_twsk_schedule(tw, timeo); /* Linkage updates. */ __inet_twsk_hashdance(tw, sk, &tcp_hashinfo); inet_twsk_put(tw); + local_bh_enable(); } else { /* Sorry, if we're out of memory, just CLOSE this * socket up. We've got bigger problems than -- GitLab From c7799c067c2ae33e348508c8afec354f3257ff25 Mon Sep 17 00:00:00 2001 From: Tommi Rantala Date: Wed, 29 Nov 2017 12:48:42 +0200 Subject: [PATCH 0445/2547] tipc: call tipc_rcv() only if bearer is up in tipc_udp_recv() Remove the second tipc_rcv() call in tipc_udp_recv(). We have just checked that the bearer is not up, and calling tipc_rcv() with a bearer that is not up leads to a TIPC div-by-zero crash in tipc_node_calculate_timer(). The crash is rare in practice, but can happen like this: We're enabling a bearer, but it's not yet up and fully initialized. At the same time we receive a discovery packet, and in tipc_udp_recv() we end up calling tipc_rcv() with the not-yet-initialized bearer, causing later the div-by-zero crash in tipc_node_calculate_timer(). Jon Maloy explains the impact of removing the second tipc_rcv() call: "link setup in the worst case will be delayed until the next arriving discovery messages, 1 sec later, and this is an acceptable delay." As the tipc_rcv() call is removed, just leave the function via the rcu_out label, so that we will kfree_skb(). [ 12.590450] Own node address <1.1.1>, network identity 1 [ 12.668088] divide error: 0000 [#1] SMP [ 12.676952] CPU: 2 PID: 0 Comm: swapper/2 Not tainted 4.14.2-dirty #1 [ 12.679225] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.10.2-2.fc27 04/01/2014 [ 12.682095] task: ffff8c2a761edb80 task.stack: ffffa41cc0cac000 [ 12.684087] RIP: 0010:tipc_node_calculate_timer.isra.12+0x45/0x60 [tipc] [ 12.686486] RSP: 0018:ffff8c2a7fc838a0 EFLAGS: 00010246 [ 12.688451] RAX: 0000000000000000 RBX: ffff8c2a5b382600 RCX: 0000000000000000 [ 12.691197] RDX: 0000000000000000 RSI: ffff8c2a5b382600 RDI: ffff8c2a5b382600 [ 12.693945] RBP: ffff8c2a7fc838b0 R08: 0000000000000001 R09: 0000000000000001 [ 12.696632] R10: 0000000000000000 R11: 0000000000000000 R12: ffff8c2a5d8949d8 [ 12.699491] R13: ffffffff95ede400 R14: 0000000000000000 R15: ffff8c2a5d894800 [ 12.702338] FS: 0000000000000000(0000) GS:ffff8c2a7fc80000(0000) knlGS:0000000000000000 [ 12.705099] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 12.706776] CR2: 0000000001bb9440 CR3: 00000000bd009001 CR4: 00000000003606e0 [ 12.708847] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 12.711016] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 12.712627] Call Trace: [ 12.713390] [ 12.714011] tipc_node_check_dest+0x2e8/0x350 [tipc] [ 12.715286] tipc_disc_rcv+0x14d/0x1d0 [tipc] [ 12.716370] tipc_rcv+0x8b0/0xd40 [tipc] [ 12.717396] ? minmax_running_min+0x2f/0x60 [ 12.718248] ? dst_alloc+0x4c/0xa0 [ 12.718964] ? tcp_ack+0xaf1/0x10b0 [ 12.719658] ? tipc_udp_is_known_peer+0xa0/0xa0 [tipc] [ 12.720634] tipc_udp_recv+0x71/0x1d0 [tipc] [ 12.721459] ? dst_alloc+0x4c/0xa0 [ 12.722130] udp_queue_rcv_skb+0x264/0x490 [ 12.722924] __udp4_lib_rcv+0x21e/0x990 [ 12.723670] ? ip_route_input_rcu+0x2dd/0xbf0 [ 12.724442] ? tcp_v4_rcv+0x958/0xa40 [ 12.725039] udp_rcv+0x1a/0x20 [ 12.725587] ip_local_deliver_finish+0x97/0x1d0 [ 12.726323] ip_local_deliver+0xaf/0xc0 [ 12.726959] ? ip_route_input_noref+0x19/0x20 [ 12.727689] ip_rcv_finish+0xdd/0x3b0 [ 12.728307] ip_rcv+0x2ac/0x360 [ 12.728839] __netif_receive_skb_core+0x6fb/0xa90 [ 12.729580] ? udp4_gro_receive+0x1a7/0x2c0 [ 12.730274] __netif_receive_skb+0x1d/0x60 [ 12.730953] ? __netif_receive_skb+0x1d/0x60 [ 12.731637] netif_receive_skb_internal+0x37/0xd0 [ 12.732371] napi_gro_receive+0xc7/0xf0 [ 12.732920] receive_buf+0x3c3/0xd40 [ 12.733441] virtnet_poll+0xb1/0x250 [ 12.733944] net_rx_action+0x23e/0x370 [ 12.734476] __do_softirq+0xc5/0x2f8 [ 12.734922] irq_exit+0xfa/0x100 [ 12.735315] do_IRQ+0x4f/0xd0 [ 12.735680] common_interrupt+0xa2/0xa2 [ 12.736126] [ 12.736416] RIP: 0010:native_safe_halt+0x6/0x10 [ 12.736925] RSP: 0018:ffffa41cc0cafe90 EFLAGS: 00000246 ORIG_RAX: ffffffffffffff4d [ 12.737756] RAX: 0000000000000000 RBX: ffff8c2a761edb80 RCX: 0000000000000000 [ 12.738504] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000 [ 12.739258] RBP: ffffa41cc0cafe90 R08: 0000014b5b9795e5 R09: ffffa41cc12c7e88 [ 12.740118] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000002 [ 12.740964] R13: ffff8c2a761edb80 R14: 0000000000000000 R15: 0000000000000000 [ 12.741831] default_idle+0x2a/0x100 [ 12.742323] arch_cpu_idle+0xf/0x20 [ 12.742796] default_idle_call+0x28/0x40 [ 12.743312] do_idle+0x179/0x1f0 [ 12.743761] cpu_startup_entry+0x1d/0x20 [ 12.744291] start_secondary+0x112/0x120 [ 12.744816] secondary_startup_64+0xa5/0xa5 [ 12.745367] Code: b9 f4 01 00 00 48 89 c2 48 c1 ea 02 48 3d d3 07 00 00 48 0f 47 d1 49 8b 0c 24 48 39 d1 76 07 49 89 14 24 48 89 d1 31 d2 48 89 df <48> f7 f1 89 c6 e8 81 6e ff ff 5b 41 5c 5d c3 66 90 66 2e 0f 1f [ 12.747527] RIP: tipc_node_calculate_timer.isra.12+0x45/0x60 [tipc] RSP: ffff8c2a7fc838a0 [ 12.748555] ---[ end trace 1399ab83390650fd ]--- [ 12.749296] Kernel panic - not syncing: Fatal exception in interrupt [ 12.750123] Kernel Offset: 0x13200000 from 0xffffffff82000000 (relocation range: 0xffffffff80000000-0xffffffffbfffffff) [ 12.751215] Rebooting in 60 seconds.. Fixes: c9b64d492b1f ("tipc: add replicast peer discovery") Signed-off-by: Tommi Rantala Cc: Jon Maloy Signed-off-by: David S. Miller --- net/tipc/udp_media.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/net/tipc/udp_media.c b/net/tipc/udp_media.c index ecca64fc6a6f..3deabcab4882 100644 --- a/net/tipc/udp_media.c +++ b/net/tipc/udp_media.c @@ -371,10 +371,6 @@ static int tipc_udp_recv(struct sock *sk, struct sk_buff *skb) goto rcu_out; } - tipc_rcv(sock_net(sk), skb, b); - rcu_read_unlock(); - return 0; - rcu_out: rcu_read_unlock(); out: -- GitLab From a0da456bbf95d2a9294799bb05c61bfb24736bb7 Mon Sep 17 00:00:00 2001 From: Max Uvarov Date: Thu, 30 Nov 2017 13:08:29 +0300 Subject: [PATCH 0446/2547] net: phy-micrel: check return code in flp center function Fix obvious typo that first return value is set but not checked. Signed-off-by: Max Uvarov Signed-off-by: David S. Miller --- drivers/net/phy/micrel.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index fdb43dd9b5cd..ab4614113403 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -496,16 +496,18 @@ static int ksz9031_of_load_skew_values(struct phy_device *phydev, return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); } +/* Center KSZ9031RNX FLP timing at 16ms. */ static int ksz9031_center_flp_timing(struct phy_device *phydev) { int result; - /* Center KSZ9031RNX FLP timing at 16ms. */ result = ksz9031_extended_write(phydev, OP_DATA, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006); + if (result) + return result; + result = ksz9031_extended_write(phydev, OP_DATA, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80); - if (result) return result; -- GitLab From acf1c02f023926b8b04672a9e81b1711ae681619 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 30 Nov 2017 13:59:11 +0000 Subject: [PATCH 0447/2547] sfp: fix RX_LOS signal handling The options word is a be16 quantity, so we need to test the flags having converted the endian-ness. Convert the flag bits to be16, which can be optimised by the compiler, rather than converting a variable at runtime. Reported-by: Florian Fainelli Signed-off-by: Russell King Signed-off-by: David S. Miller --- drivers/net/phy/sfp.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c index e381811e5f11..3355141688a6 100644 --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c @@ -355,7 +355,7 @@ static void sfp_sm_link_check_los(struct sfp *sfp) * SFP_OPTIONS_LOS_NORMAL are set? For now, we assume * the same as SFP_OPTIONS_LOS_NORMAL set. */ - if (sfp->id.ext.options & SFP_OPTIONS_LOS_INVERTED) + if (sfp->id.ext.options & cpu_to_be16(SFP_OPTIONS_LOS_INVERTED)) los ^= SFP_F_LOS; if (los) @@ -582,7 +582,8 @@ static void sfp_sm_event(struct sfp *sfp, unsigned int event) if (event == SFP_E_TX_FAULT) sfp_sm_fault(sfp, true); else if (event == - (sfp->id.ext.options & SFP_OPTIONS_LOS_INVERTED ? + (sfp->id.ext.options & + cpu_to_be16(SFP_OPTIONS_LOS_INVERTED) ? SFP_E_LOS_HIGH : SFP_E_LOS_LOW)) sfp_sm_link_up(sfp); break; @@ -592,7 +593,8 @@ static void sfp_sm_event(struct sfp *sfp, unsigned int event) sfp_sm_link_down(sfp); sfp_sm_fault(sfp, true); } else if (event == - (sfp->id.ext.options & SFP_OPTIONS_LOS_INVERTED ? + (sfp->id.ext.options & + cpu_to_be16(SFP_OPTIONS_LOS_INVERTED) ? SFP_E_LOS_LOW : SFP_E_LOS_HIGH)) { sfp_sm_link_down(sfp); sfp_sm_next(sfp, SFP_S_WAIT_LOS, 0); -- GitLab From 710dfbb01a8ac0fc8d0cc191131bd84dc3796497 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 30 Nov 2017 13:59:16 +0000 Subject: [PATCH 0448/2547] sfp: improve RX_LOS handling There are two bits in the option word for the RX_LOS signal. One reports that the RX_LOS signal is active high, the other reports that it is active low. When both or neither are set, the result is not well defined in the specification. Rather than assuming that neither set means normal RX_LOS, take this as meaning no RX_LOS signal available, thereby ignoring the signal. Signed-off-by: Russell King Signed-off-by: David S. Miller --- drivers/net/phy/sfp.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c index 3355141688a6..c1aab6a81ce9 100644 --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c @@ -351,12 +351,13 @@ static void sfp_sm_link_check_los(struct sfp *sfp) { unsigned int los = sfp->state & SFP_F_LOS; - /* FIXME: what if neither SFP_OPTIONS_LOS_INVERTED nor - * SFP_OPTIONS_LOS_NORMAL are set? For now, we assume - * the same as SFP_OPTIONS_LOS_NORMAL set. + /* If neither SFP_OPTIONS_LOS_INVERTED nor SFP_OPTIONS_LOS_NORMAL + * are set, we assume that no LOS signal is available. */ if (sfp->id.ext.options & cpu_to_be16(SFP_OPTIONS_LOS_INVERTED)) los ^= SFP_F_LOS; + else if (!(sfp->id.ext.options & cpu_to_be16(SFP_OPTIONS_LOS_NORMAL))) + los = 0; if (los) sfp_sm_next(sfp, SFP_S_WAIT_LOS, 0); @@ -364,6 +365,22 @@ static void sfp_sm_link_check_los(struct sfp *sfp) sfp_sm_link_up(sfp); } +static bool sfp_los_event_active(struct sfp *sfp, unsigned int event) +{ + return (sfp->id.ext.options & cpu_to_be16(SFP_OPTIONS_LOS_INVERTED) && + event == SFP_E_LOS_LOW) || + (sfp->id.ext.options & cpu_to_be16(SFP_OPTIONS_LOS_NORMAL) && + event == SFP_E_LOS_HIGH); +} + +static bool sfp_los_event_inactive(struct sfp *sfp, unsigned int event) +{ + return (sfp->id.ext.options & cpu_to_be16(SFP_OPTIONS_LOS_INVERTED) && + event == SFP_E_LOS_HIGH) || + (sfp->id.ext.options & cpu_to_be16(SFP_OPTIONS_LOS_NORMAL) && + event == SFP_E_LOS_LOW); +} + static void sfp_sm_fault(struct sfp *sfp, bool warn) { if (sfp->sm_retries && !--sfp->sm_retries) { @@ -581,10 +598,7 @@ static void sfp_sm_event(struct sfp *sfp, unsigned int event) case SFP_S_WAIT_LOS: if (event == SFP_E_TX_FAULT) sfp_sm_fault(sfp, true); - else if (event == - (sfp->id.ext.options & - cpu_to_be16(SFP_OPTIONS_LOS_INVERTED) ? - SFP_E_LOS_HIGH : SFP_E_LOS_LOW)) + else if (sfp_los_event_inactive(sfp, event)) sfp_sm_link_up(sfp); break; @@ -592,10 +606,7 @@ static void sfp_sm_event(struct sfp *sfp, unsigned int event) if (event == SFP_E_TX_FAULT) { sfp_sm_link_down(sfp); sfp_sm_fault(sfp, true); - } else if (event == - (sfp->id.ext.options & - cpu_to_be16(SFP_OPTIONS_LOS_INVERTED) ? - SFP_E_LOS_LOW : SFP_E_LOS_HIGH)) { + } else if (sfp_los_event_active(sfp, event)) { sfp_sm_link_down(sfp); sfp_sm_next(sfp, SFP_S_WAIT_LOS, 0); } -- GitLab From ec7681bde6d0e53ea5ef564477c8656fc318023a Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 30 Nov 2017 13:59:21 +0000 Subject: [PATCH 0449/2547] sfp: warn about modules requiring address change sequence We do not support SFP modules which require the address change sequence as detailed by SFF 8472 revision 1.22 section 8.9. Warn when these modules are inserted, and treat them as SFF8079 modules for ethtool. Signed-off-by: Russell King Signed-off-by: David S. Miller --- drivers/net/phy/sfp.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c index c1aab6a81ce9..9dfc1c4c954f 100644 --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c @@ -487,6 +487,11 @@ static int sfp_sm_mod_probe(struct sfp *sfp) return -EINVAL; } + /* If the module requires address swap mode, warn about it */ + if (sfp->id.ext.diagmon & SFP_DIAGMON_ADDRMODE) + dev_warn(sfp->dev, + "module address swap to access page 0xA2 is not supported.\n"); + return sfp_module_insert(sfp->sfp_bus, &sfp->id); } @@ -652,7 +657,8 @@ static int sfp_module_info(struct sfp *sfp, struct ethtool_modinfo *modinfo) { /* locking... and check module is present */ - if (sfp->id.ext.sff8472_compliance) { + if (sfp->id.ext.sff8472_compliance && + !(sfp->id.ext.diagmon & SFP_DIAGMON_ADDRMODE)) { modinfo->type = ETH_MODULE_SFF_8472; modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; } else { -- GitLab From 2012b7d6b2868c532f22d9172c8b24611637eb48 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 30 Nov 2017 13:59:26 +0000 Subject: [PATCH 0450/2547] phylink: ensure we take the link down when phylink_stop() is called Ensure that we tell the MAC to take the link down when phylink_stop() is called, and that this completes prior to phylink_stop() returns. Reported-by: Florian Fainelli Tested-by: Florian Fainelli Signed-off-by: Russell King Signed-off-by: David S. Miller --- drivers/net/phy/phylink.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index e3bbc70372d3..5dc9668dde34 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -773,6 +773,7 @@ void phylink_stop(struct phylink *pl) sfp_upstream_stop(pl->sfp_bus); set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state); + queue_work(system_power_efficient_wq, &pl->resolve); flush_work(&pl->resolve); } EXPORT_SYMBOL_GPL(phylink_stop); -- GitLab From d2e2ec8222b4cb49c59f6dc6f5c4fe6fb4c80de9 Mon Sep 17 00:00:00 2001 From: Nate Dailey Date: Thu, 30 Nov 2017 11:33:30 -0500 Subject: [PATCH 0451/2547] md: limit mdstat resync progress to max_sectors There is a small window near the end of md_do_sync where mddev->curr_resync can be equal to MaxSector. If status_resync is called during this window, the resulting /proc/mdstat output contains a HUGE number of = signs due to the very large curr_resync: Personalities : [raid1] md123 : active raid1 sdd3[2] sdb3[0] 204736 blocks super 1.0 [2/1] [U_] [===================================================================== ... (82 MB more) ... ================>] recovery =429496729.3% (9223372036854775807/204736) finish=0.2min speed=12796K/sec bitmap: 0/1 pages [0KB], 65536KB chunk Modify status_resync to ensure the resync variable doesn't exceed the array's max_sectors. Signed-off-by: Nate Dailey Acked-by: Guoqing Jiang Signed-off-by: Shaohua Li --- drivers/md/md.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/md/md.c b/drivers/md/md.c index 41c050b59ec4..4e4dee0ec2de 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c @@ -7605,7 +7605,9 @@ static int status_resync(struct seq_file *seq, struct mddev *mddev) if (test_bit(MD_RECOVERY_DONE, &mddev->recovery)) /* Still cleaning up */ resync = max_sectors; - } else + } else if (resync > max_sectors) + resync = max_sectors; + else resync -= atomic_read(&mddev->recovery_active); if (resync == 0) { -- GitLab From 18022a1bd3709b74ca31ef0b28fccd52bcd6c504 Mon Sep 17 00:00:00 2001 From: Shaohua Li Date: Fri, 1 Dec 2017 12:12:34 -0800 Subject: [PATCH 0452/2547] md/raid1/10: add missed blk plug flush_pending_writes isn't always called with block plug, so add it, and plug works in nested way. Signed-off-by: Shaohua Li --- drivers/md/raid1.c | 4 ++++ drivers/md/raid10.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c index cc9d337a1ed3..6df398e3a008 100644 --- a/drivers/md/raid1.c +++ b/drivers/md/raid1.c @@ -809,11 +809,15 @@ static void flush_pending_writes(struct r1conf *conf) spin_lock_irq(&conf->device_lock); if (conf->pending_bio_list.head) { + struct blk_plug plug; struct bio *bio; + bio = bio_list_get(&conf->pending_bio_list); conf->pending_count = 0; spin_unlock_irq(&conf->device_lock); + blk_start_plug(&plug); flush_bio_list(conf, bio); + blk_finish_plug(&plug); } else spin_unlock_irq(&conf->device_lock); } diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c index b9edbc747a95..c131835cf008 100644 --- a/drivers/md/raid10.c +++ b/drivers/md/raid10.c @@ -894,10 +894,13 @@ static void flush_pending_writes(struct r10conf *conf) spin_lock_irq(&conf->device_lock); if (conf->pending_bio_list.head) { + struct blk_plug plug; struct bio *bio; + bio = bio_list_get(&conf->pending_bio_list); conf->pending_count = 0; spin_unlock_irq(&conf->device_lock); + blk_start_plug(&plug); /* flush any pending bitmap writes to disk * before proceeding w/ I/O */ bitmap_unplug(conf->mddev->bitmap); @@ -918,6 +921,7 @@ static void flush_pending_writes(struct r10conf *conf) generic_make_request(bio); bio = next; } + blk_finish_plug(&plug); } else spin_unlock_irq(&conf->device_lock); } -- GitLab From d65efe7c951371fbad2c426b59bbac8bf2e60662 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Fri, 1 Dec 2017 17:07:19 -0800 Subject: [PATCH 0453/2547] drm/i915: Update DRIVER_DATE to 20171201 Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e8dc7b77ac96..594fd14e66c5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -80,8 +80,8 @@ #define DRIVER_NAME "i915" #define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20171117" -#define DRIVER_TIMESTAMP 1510958822 +#define DRIVER_DATE "20171201" +#define DRIVER_TIMESTAMP 1512176839 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and * WARN_ON()) for hw state sanity checks to check for unexpected conditions -- GitLab From 974a6b20518602310637bd8ac9ad348bf8a864d6 Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Fri, 1 Dec 2017 11:47:56 +0100 Subject: [PATCH 0454/2547] batman-adv: Fix kernel-doc for timer functions The commit e99e88a9d2b0 ("treewide: setup_timer() -> timer_setup()") changed the argument name and type of the timer function but didn't adjust the kernel-doc of these functions. Signed-off-by: Sven Eckelmann Acked-by: Kees Cook Signed-off-by: Simon Wunderlich --- net/batman-adv/tp_meter.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/batman-adv/tp_meter.c b/net/batman-adv/tp_meter.c index 15cd2139381e..ebc4e2241c77 100644 --- a/net/batman-adv/tp_meter.c +++ b/net/batman-adv/tp_meter.c @@ -482,7 +482,7 @@ static void batadv_tp_reset_sender_timer(struct batadv_tp_vars *tp_vars) /** * batadv_tp_sender_timeout - timer that fires in case of packet loss - * @arg: address of the related tp_vars + * @t: address to timer_list inside tp_vars * * If fired it means that there was packet loss. * Switch to Slow Start, set the ss_threshold to half of the current cwnd and @@ -1106,7 +1106,7 @@ static void batadv_tp_reset_receiver_timer(struct batadv_tp_vars *tp_vars) /** * batadv_tp_receiver_shutdown - stop a tp meter receiver when timeout is * reached without received ack - * @arg: address of the related tp_vars + * @t: address to timer_list inside tp_vars */ static void batadv_tp_receiver_shutdown(struct timer_list *t) { -- GitLab From 81b039ec36a41a5451e1e36f05bb055eceab1dc8 Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Mon, 13 Nov 2017 00:01:20 +0800 Subject: [PATCH 0455/2547] iio: adc: cpcap: fix incorrect validation Function platform_get_irq_byname() returns a negative error code on failure, and a zero or positive number on success. However, in function cpcap_adc_probe(), positive IRQ numbers are also taken as error cases. Use "if (ddata->irq < 0)" instead of "if (!ddata->irq)" to validate the return value of platform_get_irq_byname(). Signed-off-by: Pan Bian Fixes: 25ec249632d50 ("iio: adc: cpcap: Add minimal support for CPCAP PMIC ADC") Reviewed-by: Sebastian Reichel Acked-by: Tony Lindgren Cc: Signed-off-by: Jonathan Cameron --- drivers/iio/adc/cpcap-adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/cpcap-adc.c b/drivers/iio/adc/cpcap-adc.c index 3576ec73ec23..9ad60421d360 100644 --- a/drivers/iio/adc/cpcap-adc.c +++ b/drivers/iio/adc/cpcap-adc.c @@ -1011,7 +1011,7 @@ static int cpcap_adc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, indio_dev); ddata->irq = platform_get_irq_byname(pdev, "adcdone"); - if (!ddata->irq) + if (ddata->irq < 0) return -ENODEV; error = devm_request_threaded_irq(&pdev->dev, ddata->irq, NULL, -- GitLab From e53111ad5deaef98d8c18a9933ef1f5624c5979d Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 3 Nov 2017 15:03:36 +0200 Subject: [PATCH 0456/2547] iio: proximity: sx9500: Assign interrupt from GpioIo() The commit 0f0796509c07 ("iio: remove gpio interrupt probing from drivers that use a single interrupt") removed custom IRQ assignment for the drivers which are enumerated via ACPI or OF. Unfortunately, some ACPI tables have IRQ line defined as GpioIo() resource and thus automatic IRQ allocation will fail. Partially revert the commit 0f0796509c07 to restore original behaviour. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg Signed-off-by: Jonathan Cameron --- drivers/iio/proximity/sx9500.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/iio/proximity/sx9500.c b/drivers/iio/proximity/sx9500.c index 53c5d653e780..df23dbcc030a 100644 --- a/drivers/iio/proximity/sx9500.c +++ b/drivers/iio/proximity/sx9500.c @@ -869,6 +869,7 @@ static int sx9500_init_device(struct iio_dev *indio_dev) static void sx9500_gpio_probe(struct i2c_client *client, struct sx9500_data *data) { + struct gpio_desc *gpiod_int; struct device *dev; if (!client) @@ -876,6 +877,14 @@ static void sx9500_gpio_probe(struct i2c_client *client, dev = &client->dev; + if (client->irq <= 0) { + gpiod_int = devm_gpiod_get(dev, SX9500_GPIO_INT, GPIOD_IN); + if (IS_ERR(gpiod_int)) + dev_err(dev, "gpio get irq failed\n"); + else + client->irq = gpiod_to_irq(gpiod_int); + } + data->gpiod_rst = devm_gpiod_get(dev, SX9500_GPIO_RESET, GPIOD_OUT_HIGH); if (IS_ERR(data->gpiod_rst)) { dev_warn(dev, "gpio get reset pin failed\n"); -- GitLab From 7a6b0420d2fe4ce59437bd318826fe468f0d71ae Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 31 Oct 2017 21:01:43 +0100 Subject: [PATCH 0457/2547] iio: adc: meson-saradc: fix the bit_idx of the adc_en clock Meson8 and Meson8b SoCs use the the SAR ADC gate clock provided by the MESON_SAR_ADC_REG3 register within the SAR ADC register area. According to the datasheet (and the existing MESON_SAR_ADC_REG3_CLK_EN definition) the gate is on bit 30. The fls() function returns the last set bit, which is "bit index + 1" (fls(MESON_SAR_ADC_REG3_CLK_EN) returns 31). Fix this by switching to __ffs() which returns the first set bit, which is bit 30 in our case. This off by one error results in the ADC not being usable on devices where the bootloader did not enable the clock. Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs") Signed-off-by: Martin Blumenstingl Cc: Signed-off-by: Jonathan Cameron --- drivers/iio/adc/meson_saradc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 9c6932ffc0af..1d25c78b74d2 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -600,7 +600,7 @@ static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, init.num_parents = 1; priv->clk_gate.reg = base + MESON_SAR_ADC_REG3; - priv->clk_gate.bit_idx = fls(MESON_SAR_ADC_REG3_CLK_EN); + priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN); priv->clk_gate.hw.init = &init; priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw); -- GitLab From d85eed9f576369bc90322659de96b7dbea1f9a57 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 31 Oct 2017 21:01:44 +0100 Subject: [PATCH 0458/2547] iio: adc: meson-saradc: initialize the bandgap correctly on older SoCs Meson8 and Meson8b do not have the MESON_SAR_ADC_REG11 register. The bandgap setting for these SoCs is configured in the MESON_SAR_ADC_DELTA_10 register instead. Make the driver aware of this difference and use the correct bandgap register depending on the SoC. This has worked fine on Meson8 and Meson8b because the bootloader is already initializing the bandgap setting. Fixes: 6c76ed31cd05 ("iio: adc: meson-saradc: add Meson8b SoC compatibility") Signed-off-by: Martin Blumenstingl Cc: Signed-off-by: Jonathan Cameron --- drivers/iio/adc/meson_saradc.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 1d25c78b74d2..a220d07d890f 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -221,6 +221,7 @@ enum meson_sar_adc_chan7_mux_sel { struct meson_sar_adc_data { bool has_bl30_integration; + u32 bandgap_reg; unsigned int resolution; const char *name; }; @@ -685,6 +686,20 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) return 0; } +static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off) +{ + struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + u32 enable_mask; + + if (priv->data->bandgap_reg == MESON_SAR_ADC_REG11) + enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN; + else + enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN; + + regmap_update_bits(priv->regmap, priv->data->bandgap_reg, enable_mask, + on_off ? enable_mask : 0); +} + static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); @@ -717,9 +732,9 @@ static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1); regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval); - regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, - MESON_SAR_ADC_REG11_BANDGAP_EN, - MESON_SAR_ADC_REG11_BANDGAP_EN); + + meson_sar_adc_set_bandgap(indio_dev, true); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, MESON_SAR_ADC_REG3_ADC_EN, MESON_SAR_ADC_REG3_ADC_EN); @@ -739,8 +754,7 @@ static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) err_adc_clk: regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, MESON_SAR_ADC_REG3_ADC_EN, 0); - regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, - MESON_SAR_ADC_REG11_BANDGAP_EN, 0); + meson_sar_adc_set_bandgap(indio_dev, false); clk_disable_unprepare(priv->sana_clk); err_sana_clk: clk_disable_unprepare(priv->core_clk); @@ -765,8 +779,8 @@ static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, MESON_SAR_ADC_REG3_ADC_EN, 0); - regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, - MESON_SAR_ADC_REG11_BANDGAP_EN, 0); + + meson_sar_adc_set_bandgap(indio_dev, false); clk_disable_unprepare(priv->sana_clk); clk_disable_unprepare(priv->core_clk); @@ -844,30 +858,35 @@ static const struct iio_info meson_sar_adc_iio_info = { static const struct meson_sar_adc_data meson_sar_adc_meson8_data = { .has_bl30_integration = false, + .bandgap_reg = MESON_SAR_ADC_DELTA_10, .resolution = 10, .name = "meson-meson8-saradc", }; static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = { .has_bl30_integration = false, + .bandgap_reg = MESON_SAR_ADC_DELTA_10, .resolution = 10, .name = "meson-meson8b-saradc", }; static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = { .has_bl30_integration = true, + .bandgap_reg = MESON_SAR_ADC_REG11, .resolution = 10, .name = "meson-gxbb-saradc", }; static const struct meson_sar_adc_data meson_sar_adc_gxl_data = { .has_bl30_integration = true, + .bandgap_reg = MESON_SAR_ADC_REG11, .resolution = 12, .name = "meson-gxl-saradc", }; static const struct meson_sar_adc_data meson_sar_adc_gxm_data = { .has_bl30_integration = true, + .bandgap_reg = MESON_SAR_ADC_REG11, .resolution = 12, .name = "meson-gxm-saradc", }; -- GitLab From 96748823c483c6eed8321f78bd128dd33f09c55c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 31 Oct 2017 21:01:45 +0100 Subject: [PATCH 0459/2547] iio: adc: meson-saradc: Meson8 and Meson8b do not have REG11 and REG13 The Meson GXBB and newer SoCs have a few more registers than the older Meson8 and Meson8b SoCs. Use a separate regmap config to limit the older SoCs to the DELTA_10 register. Fixes: 6c76ed31cd05 ("iio: adc: meson-saradc: add Meson8b SoC compatibility") Signed-off-by: Martin Blumenstingl Cc: Signed-off-by: Jonathan Cameron --- drivers/iio/adc/meson_saradc.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index a220d07d890f..36047147ce7c 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -224,6 +224,7 @@ struct meson_sar_adc_data { u32 bandgap_reg; unsigned int resolution; const char *name; + const struct regmap_config *regmap_config; }; struct meson_sar_adc_priv { @@ -243,13 +244,20 @@ struct meson_sar_adc_priv { int calibscale; }; -static const struct regmap_config meson_sar_adc_regmap_config = { +static const struct regmap_config meson_sar_adc_regmap_config_gxbb = { .reg_bits = 8, .val_bits = 32, .reg_stride = 4, .max_register = MESON_SAR_ADC_REG13, }; +static const struct regmap_config meson_sar_adc_regmap_config_meson8 = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .max_register = MESON_SAR_ADC_DELTA_10, +}; + static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); @@ -859,6 +867,7 @@ static const struct iio_info meson_sar_adc_iio_info = { static const struct meson_sar_adc_data meson_sar_adc_meson8_data = { .has_bl30_integration = false, .bandgap_reg = MESON_SAR_ADC_DELTA_10, + .regmap_config = &meson_sar_adc_regmap_config_meson8, .resolution = 10, .name = "meson-meson8-saradc", }; @@ -866,6 +875,7 @@ static const struct meson_sar_adc_data meson_sar_adc_meson8_data = { static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = { .has_bl30_integration = false, .bandgap_reg = MESON_SAR_ADC_DELTA_10, + .regmap_config = &meson_sar_adc_regmap_config_meson8, .resolution = 10, .name = "meson-meson8b-saradc", }; @@ -873,6 +883,7 @@ static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = { static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = { .has_bl30_integration = true, .bandgap_reg = MESON_SAR_ADC_REG11, + .regmap_config = &meson_sar_adc_regmap_config_gxbb, .resolution = 10, .name = "meson-gxbb-saradc", }; @@ -880,6 +891,7 @@ static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = { static const struct meson_sar_adc_data meson_sar_adc_gxl_data = { .has_bl30_integration = true, .bandgap_reg = MESON_SAR_ADC_REG11, + .regmap_config = &meson_sar_adc_regmap_config_gxbb, .resolution = 12, .name = "meson-gxl-saradc", }; @@ -887,6 +899,7 @@ static const struct meson_sar_adc_data meson_sar_adc_gxl_data = { static const struct meson_sar_adc_data meson_sar_adc_gxm_data = { .has_bl30_integration = true, .bandgap_reg = MESON_SAR_ADC_REG11, + .regmap_config = &meson_sar_adc_regmap_config_gxbb, .resolution = 12, .name = "meson-gxm-saradc", }; @@ -964,7 +977,7 @@ static int meson_sar_adc_probe(struct platform_device *pdev) return ret; priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, - &meson_sar_adc_regmap_config); + priv->data->regmap_config); if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); -- GitLab From c175cb7cd953782bbf4e8bdf088ad61440d6dde5 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 29 Oct 2017 17:06:01 -0700 Subject: [PATCH 0460/2547] iio: fix kernel-doc build errors Fix build errors in kernel-doc notation. Symbols that end in '_' have a special meaning, but adding a '*' makes them OK. ../drivers/iio/industrialio-core.c:635: ERROR: Unknown target name: "iio_val". ../drivers/iio/industrialio-core.c:642: ERROR: Unknown target name: "iio_val". Signed-off-by: Randy Dunlap Cc: Signed-off-by: Jonathan Cameron --- drivers/iio/industrialio-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 9c4cfd19b739..2f0998ebeed2 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -631,7 +631,7 @@ static ssize_t __iio_format_value(char *buf, size_t len, unsigned int type, * iio_format_value() - Formats a IIO value into its string representation * @buf: The buffer to which the formatted value gets written * which is assumed to be big enough (i.e. PAGE_SIZE). - * @type: One of the IIO_VAL_... constants. This decides how the val + * @type: One of the IIO_VAL_* constants. This decides how the val * and val2 parameters are formatted. * @size: Number of IIO value entries contained in vals * @vals: Pointer to the values, exact meaning depends on the @@ -639,7 +639,7 @@ static ssize_t __iio_format_value(char *buf, size_t len, unsigned int type, * * Return: 0 by default, a negative number on failure or the * total number of characters written for a type that belongs - * to the IIO_VAL_... constant. + * to the IIO_VAL_* constant. */ ssize_t iio_format_value(char *buf, unsigned int type, int size, int *vals) { -- GitLab From ad44a9f804c1591ba2a2ec0ac8d916a515d2790c Mon Sep 17 00:00:00 2001 From: Peter Meerwald-Stadler Date: Fri, 27 Oct 2017 21:45:31 +0200 Subject: [PATCH 0461/2547] iio: health: max30102: Temperature should be in milli Celsius As per ABI temperature should be in milli Celsius after scaling, not Celsius Note on stable cc. This driver is breaking the standard IIO ABI. (JC) Signed-off-by: Peter Meerwald-Stadler Acked-by: Matt Ranostay Cc: Signed-off-by: Jonathan Cameron --- drivers/iio/health/max30102.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/health/max30102.c b/drivers/iio/health/max30102.c index 203ffb9cad6a..147a8c14235f 100644 --- a/drivers/iio/health/max30102.c +++ b/drivers/iio/health/max30102.c @@ -371,7 +371,7 @@ static int max30102_read_raw(struct iio_dev *indio_dev, mutex_unlock(&indio_dev->mlock); break; case IIO_CHAN_INFO_SCALE: - *val = 1; /* 0.0625 */ + *val = 1000; /* 62.5 */ *val2 = 16; ret = IIO_VAL_FRACTIONAL; break; -- GitLab From 6d745ee8b5e81f3a33791e3c854fbbfd6f3e585e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 6 Sep 2017 14:56:50 +0200 Subject: [PATCH 0462/2547] iio: stm32: fix adc/trigger link error The ADC driver can trigger on either the timer or the lptim trigger, but it only uses a Kconfig 'select' statement to ensure that the first of the two is present. When the lptim trigger is enabled as a loadable module, and the adc driver is built-in, we now get a link error: drivers/iio/adc/stm32-adc.o: In function `stm32_adc_get_trig_extsel': stm32-adc.c:(.text+0x4e0): undefined reference to `is_stm32_lptim_trigger' We could use a second 'select' statement and always have both trigger drivers enabled when the adc driver is, but it seems that the lptimer trigger was intentionally left optional, so it seems better to keep it that way. This adds a hack to use 'IS_REACHABLE()' rather than 'IS_ENABLED()', which avoids the link error, but instead leads to the lptimer trigger not being used in the broken configuration. I've added a runtime warning for this case to help users figure out what they did wrong if this should ever be done by accident. Fixes: f0b638a7f6db ("iio: adc: stm32: add support for lptimer triggers") Signed-off-by: Arnd Bergmann Cc: Signed-off-by: Jonathan Cameron --- include/linux/iio/timer/stm32-lptim-trigger.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/linux/iio/timer/stm32-lptim-trigger.h b/include/linux/iio/timer/stm32-lptim-trigger.h index 34d59bfdce2d..464458d20b16 100644 --- a/include/linux/iio/timer/stm32-lptim-trigger.h +++ b/include/linux/iio/timer/stm32-lptim-trigger.h @@ -16,11 +16,14 @@ #define LPTIM2_OUT "lptim2_out" #define LPTIM3_OUT "lptim3_out" -#if IS_ENABLED(CONFIG_IIO_STM32_LPTIMER_TRIGGER) +#if IS_REACHABLE(CONFIG_IIO_STM32_LPTIMER_TRIGGER) bool is_stm32_lptim_trigger(struct iio_trigger *trig); #else static inline bool is_stm32_lptim_trigger(struct iio_trigger *trig) { +#if IS_ENABLED(CONFIG_IIO_STM32_LPTIMER_TRIGGER) + pr_warn_once("stm32 lptim_trigger not linked in\n"); +#endif return false; } #endif -- GitLab From 5c3de777bdaf48bd0cfb43097c0d0fb85056cab7 Mon Sep 17 00:00:00 2001 From: Arend Van Spriel Date: Sat, 25 Nov 2017 21:39:25 +0100 Subject: [PATCH 0463/2547] brcmfmac: change driver unbind order of the sdio function devices In the function brcmf_sdio_firmware_callback() the driver is unbound from the sdio function devices in the error path. However, the order in which it is done resulted in a use-after-free issue (see brcmf_ops_sdio_remove() in bcmsdh.c). Hence change the order and first unbind sdio function #2 device and then unbind sdio function #1 device. Cc: stable@vger.kernel.org # v4.12.x Fixes: 7a51461fc2da ("brcmfmac: unbind all devices upon failure in firmware callback") Reported-by: Stefan Wahren Reviewed-by: Hante Meuleman Reviewed-by: Pieter-Paul Giesberts Reviewed-by: Franky Lin Signed-off-by: Arend van Spriel Signed-off-by: Kalle Valo --- drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c index 310c4e2746aa..adf180f338ca 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c @@ -4121,8 +4121,8 @@ static void brcmf_sdio_firmware_callback(struct device *dev, int err, sdio_release_host(sdiodev->func[1]); fail: brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err); - device_release_driver(dev); device_release_driver(&sdiodev->func[2]->dev); + device_release_driver(dev); } struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) -- GitLab From e814bccbafece52a24e152d2395b5d49eef55841 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 29 Nov 2017 15:20:03 +0000 Subject: [PATCH 0464/2547] scripts/kernel-doc: Don't fail with status != 0 if error encountered with -none My bisect scripts starting running into build failures when trying to compile 4.15-rc1 with the builds failing with things like: drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c:2078: error: Cannot parse struct or union! The line in question is actually just a #define, but after some digging it turns out that my scripts pass W=1 and since commit 3a025e1d1c2ea ("Add optional check for bad kernel-doc comments") that results in kernel-doc running on each source file. The file in question has a badly formatted comment immediately before the #define: /** * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for * bus layer usage. */ which causes the regex in dump_struct to fail (lack of braces following struct declaration) and kernel-doc returns 1, which causes the build to fail. Fix the issue by always returning 0 from kernel-doc when invoked with -none. It successfully generates no documentation, and prints out any issues. Cc: Matthew Wilcox Cc: Jonathan Corbet Signed-off-by: Will Deacon Signed-off-by: Jonathan Corbet --- scripts/kernel-doc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/kernel-doc b/scripts/kernel-doc index bd29a92b4b48..df0f045a9a89 100755 --- a/scripts/kernel-doc +++ b/scripts/kernel-doc @@ -3248,4 +3248,4 @@ if ($verbose && $warnings) { print STDERR "$warnings warnings\n"; } -exit($errors); +exit($output_mode eq "none" ? 0 : $errors); -- GitLab From e50806a9fd0132402a62cb3161d786335662072f Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Wed, 29 Nov 2017 00:16:56 +0900 Subject: [PATCH 0465/2547] dmaengine: doc : Fix warning "Title underline too short" while make xmldocs This patch fix following warning during 'make xmldocs' Documentation/driver-api/dmaengine/client.rst:188: WARNING: Title underline too short. Further APIs: ------------ Signed-off-by: Masanari Iida Signed-off-by: Jonathan Corbet --- Documentation/driver-api/dmaengine/client.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/driver-api/dmaengine/client.rst b/Documentation/driver-api/dmaengine/client.rst index 6245c99af8c1..fbbb2831f29f 100644 --- a/Documentation/driver-api/dmaengine/client.rst +++ b/Documentation/driver-api/dmaengine/client.rst @@ -185,7 +185,7 @@ The details of these operations are: void dma_async_issue_pending(struct dma_chan *chan); Further APIs: ------------- +------------- 1. Terminate APIs -- GitLab From 0f83aaa3c07a46b41b2d5d8ee6b88617eb2c2f09 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Tue, 28 Nov 2017 06:16:21 +0100 Subject: [PATCH 0466/2547] genericirq.rst: Remove :c:func:`...` in code blocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In code blocks, :c:func:`...` annotations don't result in cross-references. Instead, they are rendered verbatim. Remove these broken annotations, and mark function calls with parentheses() again. Fixes: 76d40fae1351 ("genericirq.rst: add cross-reference links and use monospaced fonts") Signed-off-by: Jonathan Neuschäfer Signed-off-by: Jonathan Corbet --- Documentation/core-api/genericirq.rst | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/core-api/genericirq.rst b/Documentation/core-api/genericirq.rst index 0054bd48be84..4da67b65cecf 100644 --- a/Documentation/core-api/genericirq.rst +++ b/Documentation/core-api/genericirq.rst @@ -225,9 +225,9 @@ interrupts. The following control flow is implemented (simplified excerpt):: - :c:func:`desc->irq_data.chip->irq_mask_ack`; + desc->irq_data.chip->irq_mask_ack(); handle_irq_event(desc->action); - :c:func:`desc->irq_data.chip->irq_unmask`; + desc->irq_data.chip->irq_unmask(); Default Fast EOI IRQ flow handler @@ -239,7 +239,7 @@ which only need an EOI at the end of the handler. The following control flow is implemented (simplified excerpt):: handle_irq_event(desc->action); - :c:func:`desc->irq_data.chip->irq_eoi`; + desc->irq_data.chip->irq_eoi(); Default Edge IRQ flow handler @@ -251,15 +251,15 @@ interrupts. The following control flow is implemented (simplified excerpt):: if (desc->status & running) { - :c:func:`desc->irq_data.chip->irq_mask_ack`; + desc->irq_data.chip->irq_mask_ack(); desc->status |= pending | masked; return; } - :c:func:`desc->irq_data.chip->irq_ack`; + desc->irq_data.chip->irq_ack(); desc->status |= running; do { if (desc->status & masked) - :c:func:`desc->irq_data.chip->irq_unmask`; + desc->irq_data.chip->irq_unmask(); desc->status &= ~pending; handle_irq_event(desc->action); } while (status & pending); @@ -293,10 +293,10 @@ simplified version without locking. The following control flow is implemented (simplified excerpt):: if (desc->irq_data.chip->irq_ack) - :c:func:`desc->irq_data.chip->irq_ack`; + desc->irq_data.chip->irq_ack(); handle_irq_event(desc->action); if (desc->irq_data.chip->irq_eoi) - :c:func:`desc->irq_data.chip->irq_eoi`; + desc->irq_data.chip->irq_eoi(); EOI Edge IRQ flow handler -- GitLab From a08415ea2a8b3f0173fd0612317d5cba5b57fedb Mon Sep 17 00:00:00 2001 From: John Pittman Date: Wed, 22 Nov 2017 12:56:22 -0500 Subject: [PATCH 0467/2547] scsi: documentation: Fix case of 'scsi_device' struct mention(s) In scsi_mid_low_api.txt a the scsi_device structure is mentioned several times, but the leading 's' is uppercase (Scsi_device) and should be lowercase (scsi_device). Fixed by this commit. Signed-off-by: John Pittman Signed-off-by: Jonathan Corbet --- Documentation/scsi/scsi_mid_low_api.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/scsi/scsi_mid_low_api.txt b/Documentation/scsi/scsi_mid_low_api.txt index 6338400eed73..2c31d9ee6776 100644 --- a/Documentation/scsi/scsi_mid_low_api.txt +++ b/Documentation/scsi/scsi_mid_low_api.txt @@ -319,12 +319,12 @@ struct Scsi_Host: instance. If the reference count reaches 0 then the given instance is freed -The Scsi_device structure has had reference counting infrastructure added. -This effectively spreads the ownership of struct Scsi_device instances +The scsi_device structure has had reference counting infrastructure added. +This effectively spreads the ownership of struct scsi_device instances across the various SCSI layers which use them. Previously such instances were exclusively owned by the mid level. See the access functions declared towards the end of include/scsi/scsi_device.h . If an LLD wants to keep -a copy of a pointer to a Scsi_device instance it should use scsi_device_get() +a copy of a pointer to a scsi_device instance it should use scsi_device_get() to bump its reference count. When it is finished with the pointer it can use scsi_device_put() to decrement its reference count (and potentially delete it). -- GitLab From 741f5afbba70ff3cddcc5bba2595d9a44fa722e5 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 2 Dec 2017 17:36:45 +0100 Subject: [PATCH 0468/2547] ARM: dts: rockchip: add cpu0-regulator on rk3066a-marsboard The rk3066 also has operating points now, but without adjusting the cpu-regulator will break once higher voltages are needed for a specific frequency, so add the needed cpu0-regulator. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-marsboard.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index c6d92c25df42..d23ee6d911ac 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -83,6 +83,10 @@ }; }; +&cpu0 { + cpu0-supply = <&vdd_arm>; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; -- GitLab From 8a64e557f399090f5d1917b2f32a065da2b12be1 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 16 Nov 2017 23:18:32 +0300 Subject: [PATCH 0469/2547] gpio: pca953x: fix vendor prefix for PCA9654 Despite commit 55020c8056a8 ("of: Add vendor prefix for ON Semiconductor Corp.") was made long ago, the latter commit 9f49f6dd0473 ("gpio: pca953x: add onsemi,pca9654 id") made use of another, undocumented vendor prefix. Since such prefix doesn't seem to be used in any device trees, I think we can just fix the "compatible" string in the driver and the bindings and be done with that... Fixes: 9f49f6dd0473 ("gpio: pca953x: add onsemi,pca9654 id") Signed-off-by: Sergei Shtylyov Acked-by: Rob Herring Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/gpio-pca953x.txt | 2 +- drivers/gpio/gpio-pca953x.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt index 7f57271df2bc..0d0158728f89 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt @@ -27,7 +27,7 @@ Required properties: ti,tca6424 ti,tca9539 ti,tca9554 - onsemi,pca9654 + onnn,pca9654 exar,xra1202 Optional properties: diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index babb7bd2ba59..a0a5f9730aa7 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -947,7 +947,7 @@ static const struct of_device_id pca953x_dt_ids[] = { { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, - { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), }, + { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, { } -- GitLab From cbbde59b29d7c4cf4228efcb964b683ad83f8c03 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 18 Nov 2017 12:10:03 +0900 Subject: [PATCH 0470/2547] arm64: dts: sort vendor subdirectories in Makefile alphabetically The list is almost sorted. Move "lg" up to complete it. Signed-off-by: Masahiro Yamada Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index d7c22d51bc50..4aa50b9b26bc 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -12,6 +12,7 @@ subdir-y += cavium subdir-y += exynos subdir-y += freescale subdir-y += hisilicon +subdir-y += lg subdir-y += marvell subdir-y += mediatek subdir-y += nvidia @@ -22,5 +23,4 @@ subdir-y += rockchip subdir-y += socionext subdir-y += sprd subdir-y += xilinx -subdir-y += lg subdir-y += zte -- GitLab From 44e5dced2ef6e7adb2bf53227f3e4283e4d8f8f1 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 9 Nov 2017 16:26:11 -0600 Subject: [PATCH 0471/2547] arm: dts: marvell: Add missing #phy-cells to usb-nop-xceiv "usb-nop-xceiv" is using the phy binding, but is missing #phy-cells property. This is probably because the binding was the precursor to the phy binding. Fixes the following warning in Marvell dts files: Warning (phys_property): Missing property '#phy-cells' in node ... Signed-off-by: Rob Herring Cc: Jason Cooper Cc: Sebastian Hesselbarth Reviewed-by: Andrew Lunn Acked-by: Gregory CLEMENT Signed-off-by: Olof Johansson --- arch/arm/boot/dts/armada-385-db-ap.dts | 1 + arch/arm/boot/dts/armada-385-linksys.dtsi | 1 + arch/arm/boot/dts/armada-385-synology-ds116.dts | 2 ++ arch/arm/boot/dts/armada-388-gp.dts | 2 ++ 4 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts index 25d2d720dc0e..678aa023335d 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -236,6 +236,7 @@ usb3_phy: usb3_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_xhci0_vbus>; + #phy-cells = <0>; }; reg_xhci0_vbus: xhci0-vbus { diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index e1f355ffc8f7..434dc9aaa5e4 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -66,6 +66,7 @@ usb3_1_phy: usb3_1-phy { compatible = "usb-nop-xceiv"; vcc-supply = <&usb3_1_vbus>; + #phy-cells = <0>; }; usb3_1_vbus: usb3_1-vbus { diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/armada-385-synology-ds116.dts index 36ad571e76f3..0a3552ebda3b 100644 --- a/arch/arm/boot/dts/armada-385-synology-ds116.dts +++ b/arch/arm/boot/dts/armada-385-synology-ds116.dts @@ -191,11 +191,13 @@ usb3_0_phy: usb3_0_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_usb3_0_vbus>; + #phy-cells = <0>; }; usb3_1_phy: usb3_1_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_usb3_1_vbus>; + #phy-cells = <0>; }; reg_usb3_0_vbus: usb3-vbus0 { diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts index f503955dbd3b..51b4ee6df130 100644 --- a/arch/arm/boot/dts/armada-388-gp.dts +++ b/arch/arm/boot/dts/armada-388-gp.dts @@ -276,11 +276,13 @@ usb2_1_phy: usb2_1_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_usb2_1_vbus>; + #phy-cells = <0>; }; usb3_phy: usb3_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_usb3_vbus>; + #phy-cells = <0>; }; reg_usb3_vbus: usb3-vbus { -- GitLab From a7f3f939dd7d8398acebecd1ceb2e9e7ffbe91d2 Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Fri, 1 Dec 2017 03:13:02 -0500 Subject: [PATCH 0472/2547] bnxt_en: Need to unconditionally shut down RoCE in bnxt_shutdown The current 'bnxt_shutdown' implementation only invokes 'bnxt_ulp_shutdown' to shut down RoCE in the case when the system is in the path of power off (SYSTEM_POWER_OFF). While this may work in most cases, it does not work in the smart NIC case, when Linux 'reboot' command is initiated from the Linux that runs on the ARM cores of the NIC card. In this particular case, Linux 'reboot' results in a system 'L3' level reset where the entire ARM and associated subsystems are being reset, but at the same time, Nitro core is being kept in sane state (to allow external PCIe connected servers to continue to work). Without properly shutting down RoCE and freeing all associated resources, it results in the ARM core to hang immediately after the 'reboot' By always invoking 'bnxt_ulp_shutdown' in 'bnxt_shutdown', it fixes the above issue Fixes: 0efd2fc65c92 ("bnxt_en: Add a callback to inform RDMA driver during PCI shutdown.") Signed-off-by: Ray Jui Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index c5c38d4b7d1c..7f173eb42aa2 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -8263,8 +8263,9 @@ static void bnxt_shutdown(struct pci_dev *pdev) if (netif_running(dev)) dev_close(dev); + bnxt_ulp_shutdown(bp); + if (system_state == SYSTEM_POWER_OFF) { - bnxt_ulp_shutdown(bp); bnxt_clear_int_mode(bp); pci_wake_from_d3(pdev, bp->wol); pci_set_power_state(pdev, PCI_D3hot); -- GitLab From c8fb7b8259c67b86cd93a71c85e78b34d2c96fdc Mon Sep 17 00:00:00 2001 From: Sunil Challa Date: Fri, 1 Dec 2017 03:13:03 -0500 Subject: [PATCH 0473/2547] bnxt_en: wildcard smac while creating tunnel decap filter While creating a decap filter the tunnel smac need not (and must not) be specified as we cannot ascertain the neighbor in the recv path. 'ttl' match is also not needed for the decap filter and must be wild-carded. Fixes: f484f6782e01 ("bnxt_en: add hwrm FW cmds for cfa_encap_record and decap_filter") Signed-off-by: Sunil Challa Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c index d5031f436f83..96bff48af971 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c @@ -532,10 +532,8 @@ static int hwrm_cfa_decap_filter_alloc(struct bnxt *bp, } if (flow->flags & BNXT_TC_FLOW_FLAGS_TUNL_ETH_ADDRS) { - enables |= CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR | - CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR; + enables |= CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR; ether_addr_copy(req.dst_macaddr, l2_info->dmac); - ether_addr_copy(req.src_macaddr, l2_info->smac); } if (l2_info->num_vlans) { enables |= CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID; @@ -1012,10 +1010,9 @@ static int bnxt_tc_get_decap_handle(struct bnxt *bp, struct bnxt_tc_flow *flow, if (rc) goto put_decap; - decap_key->ttl = tun_key.ttl; decap_l2_info = &decap_node->l2_info; + /* decap smac is wildcarded */ ether_addr_copy(decap_l2_info->dmac, l2_info.smac); - ether_addr_copy(decap_l2_info->smac, l2_info.dmac); if (l2_info.num_vlans) { decap_l2_info->num_vlans = l2_info.num_vlans; decap_l2_info->inner_vlan_tpid = l2_info.inner_vlan_tpid; -- GitLab From e9ecc731a87912d209d6e9b4ed20ed70451c08cb Mon Sep 17 00:00:00 2001 From: Sathya Perla Date: Fri, 1 Dec 2017 03:13:04 -0500 Subject: [PATCH 0474/2547] bnxt_en: fix dst/src fid for vxlan encap/decap actions For flows that involve a vxlan encap action, the vxlan sock interface may be specified as the outgoing interface. The driver must resolve the outgoing PF interface used by this socket and use the dst_fid of the PF in the hwrm_cfa_encap_record_alloc cmd. Similarily for flows that have a vxlan decap action, the fid of the incoming PF interface must be used as the src_fid in the hwrm_cfa_decap_filter_alloc cmd. Fixes: 8c95f773b4a3 ("bnxt_en: add support for Flower based vxlan encap/decap offload") Signed-off-by: Sathya Perla Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c | 48 +++++++++++--------- 1 file changed, 26 insertions(+), 22 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c index 96bff48af971..3d201d7324bd 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c @@ -56,7 +56,6 @@ static int bnxt_tc_parse_redir(struct bnxt *bp, { int ifindex = tcf_mirred_ifindex(tc_act); struct net_device *dev; - u16 dst_fid; dev = __dev_get_by_index(dev_net(bp->dev), ifindex); if (!dev) { @@ -64,15 +63,7 @@ static int bnxt_tc_parse_redir(struct bnxt *bp, return -EINVAL; } - /* find the FID from dev */ - dst_fid = bnxt_flow_get_dst_fid(bp, dev); - if (dst_fid == BNXT_FID_INVALID) { - netdev_info(bp->dev, "can't get fid for ifindex=%d", ifindex); - return -EINVAL; - } - actions->flags |= BNXT_TC_ACTION_FLAG_FWD; - actions->dst_fid = dst_fid; actions->dst_dev = dev; return 0; } @@ -160,13 +151,17 @@ static int bnxt_tc_parse_actions(struct bnxt *bp, if (rc) return rc; - /* Tunnel encap/decap action must be accompanied by a redirect action */ - if ((actions->flags & BNXT_TC_ACTION_FLAG_TUNNEL_ENCAP || - actions->flags & BNXT_TC_ACTION_FLAG_TUNNEL_DECAP) && - !(actions->flags & BNXT_TC_ACTION_FLAG_FWD)) { - netdev_info(bp->dev, - "error: no redir action along with encap/decap"); - return -EINVAL; + if (actions->flags & BNXT_TC_ACTION_FLAG_FWD) { + if (actions->flags & BNXT_TC_ACTION_FLAG_TUNNEL_ENCAP) { + /* dst_fid is PF's fid */ + actions->dst_fid = bp->pf.fw_fid; + } else { + /* find the FID from dst_dev */ + actions->dst_fid = + bnxt_flow_get_dst_fid(bp, actions->dst_dev); + if (actions->dst_fid == BNXT_FID_INVALID) + return -EINVAL; + } } return rc; @@ -899,10 +894,10 @@ static void bnxt_tc_put_decap_handle(struct bnxt *bp, static int bnxt_tc_resolve_tunnel_hdrs(struct bnxt *bp, struct ip_tunnel_key *tun_key, - struct bnxt_tc_l2_key *l2_info, - struct net_device *real_dst_dev) + struct bnxt_tc_l2_key *l2_info) { #ifdef CONFIG_INET + struct net_device *real_dst_dev = bp->dev; struct flowi4 flow = { {0} }; struct net_device *dst_dev; struct neighbour *nbr; @@ -1006,7 +1001,7 @@ static int bnxt_tc_get_decap_handle(struct bnxt *bp, struct bnxt_tc_flow *flow, */ tun_key.u.ipv4.dst = flow->tun_key.u.ipv4.src; tun_key.tp_dst = flow->tun_key.tp_dst; - rc = bnxt_tc_resolve_tunnel_hdrs(bp, &tun_key, &l2_info, bp->dev); + rc = bnxt_tc_resolve_tunnel_hdrs(bp, &tun_key, &l2_info); if (rc) goto put_decap; @@ -1092,8 +1087,7 @@ static int bnxt_tc_get_encap_handle(struct bnxt *bp, struct bnxt_tc_flow *flow, if (encap_node->tunnel_handle != INVALID_TUNNEL_HANDLE) goto done; - rc = bnxt_tc_resolve_tunnel_hdrs(bp, encap_key, &encap_node->l2_info, - flow->actions.dst_dev); + rc = bnxt_tc_resolve_tunnel_hdrs(bp, encap_key, &encap_node->l2_info); if (rc) goto put_encap; @@ -1166,6 +1160,15 @@ static int __bnxt_tc_del_flow(struct bnxt *bp, return 0; } +static void bnxt_tc_set_src_fid(struct bnxt *bp, struct bnxt_tc_flow *flow, + u16 src_fid) +{ + if (flow->actions.flags & BNXT_TC_ACTION_FLAG_TUNNEL_DECAP) + flow->src_fid = bp->pf.fw_fid; + else + flow->src_fid = src_fid; +} + /* Add a new flow or replace an existing flow. * Notes on locking: * There are essentially two critical sections here. @@ -1201,7 +1204,8 @@ static int bnxt_tc_add_flow(struct bnxt *bp, u16 src_fid, rc = bnxt_tc_parse_flow(bp, tc_flow_cmd, flow); if (rc) goto free_node; - flow->src_fid = src_fid; + + bnxt_tc_set_src_fid(bp, flow, src_fid); if (!bnxt_tc_can_offload(bp, flow)) { rc = -ENOSPC; -- GitLab From ebd5818cc5d4847897d7fe872e2d9799d7b7fcbb Mon Sep 17 00:00:00 2001 From: Vasundhara Volam Date: Fri, 1 Dec 2017 03:13:05 -0500 Subject: [PATCH 0475/2547] bnxt_en: Fix a variable scoping in bnxt_hwrm_do_send_msg() short_input variable is assigned to another data pointer which is referred out of its scope. Fix it by moving short_input definition to the beginning of bnxt_hwrm_do_send_msg() function. No failure has been reported so far due to this issue. Fixes: e605db801bde ("bnxt_en: Support for Short Firmware Message") Signed-off-by: Vasundhara Volam Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index 7f173eb42aa2..28f5e94274ee 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -3368,6 +3368,7 @@ static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, u16 cp_ring_id, len = 0; struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; + struct hwrm_short_input short_input = {0}; req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++); memset(resp, 0, PAGE_SIZE); @@ -3376,7 +3377,6 @@ static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, if (bp->flags & BNXT_FLAG_SHORT_CMD) { void *short_cmd_req = bp->hwrm_short_cmd_req_addr; - struct hwrm_short_input short_input = {0}; memcpy(short_cmd_req, req, msg_len); memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN - -- GitLab From 6e474083f3daf3a3546737f5d7d502ad12eb257c Mon Sep 17 00:00:00 2001 From: Wei Xu Date: Fri, 1 Dec 2017 05:10:36 -0500 Subject: [PATCH 0476/2547] vhost: fix skb leak in handle_rx() Matthew found a roughly 40% tcp throughput regression with commit c67df11f(vhost_net: try batch dequing from skb array) as discussed in the following thread: https://www.mail-archive.com/netdev@vger.kernel.org/msg187936.html Eventually we figured out that it was a skb leak in handle_rx() when sending packets to the VM. This usually happens when a guest can not drain out vq as fast as vhost fills in, afterwards it sets off the traffic jam and leaks skb(s) which occurs as no headcount to send on the vq from vhost side. This can be avoided by making sure we have got enough headcount before actually consuming a skb from the batched rx array while transmitting, which is simply done by moving checking the zero headcount a bit ahead. Signed-off-by: Wei Xu Reported-by: Matthew Rosato Acked-by: Michael S. Tsirkin Signed-off-by: David S. Miller --- drivers/vhost/net.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/vhost/net.c b/drivers/vhost/net.c index 8d626d7c2e7e..c7bdeb655646 100644 --- a/drivers/vhost/net.c +++ b/drivers/vhost/net.c @@ -778,16 +778,6 @@ static void handle_rx(struct vhost_net *net) /* On error, stop handling until the next kick. */ if (unlikely(headcount < 0)) goto out; - if (nvq->rx_array) - msg.msg_control = vhost_net_buf_consume(&nvq->rxq); - /* On overrun, truncate and discard */ - if (unlikely(headcount > UIO_MAXIOV)) { - iov_iter_init(&msg.msg_iter, READ, vq->iov, 1, 1); - err = sock->ops->recvmsg(sock, &msg, - 1, MSG_DONTWAIT | MSG_TRUNC); - pr_debug("Discarded rx packet: len %zd\n", sock_len); - continue; - } /* OK, now we need to know about added descriptors. */ if (!headcount) { if (unlikely(vhost_enable_notify(&net->dev, vq))) { @@ -800,6 +790,16 @@ static void handle_rx(struct vhost_net *net) * they refilled. */ goto out; } + if (nvq->rx_array) + msg.msg_control = vhost_net_buf_consume(&nvq->rxq); + /* On overrun, truncate and discard */ + if (unlikely(headcount > UIO_MAXIOV)) { + iov_iter_init(&msg.msg_iter, READ, vq->iov, 1, 1); + err = sock->ops->recvmsg(sock, &msg, + 1, MSG_DONTWAIT | MSG_TRUNC); + pr_debug("Discarded rx packet: len %zd\n", sock_len); + continue; + } /* We don't need to be notified again. */ iov_iter_init(&msg.msg_iter, READ, vq->iov, in, vhost_len); fixup = msg.msg_iter; -- GitLab From c33ee15b3820a03cf8229ba9415084197b827f8c Mon Sep 17 00:00:00 2001 From: Wei Xu Date: Fri, 1 Dec 2017 05:10:37 -0500 Subject: [PATCH 0477/2547] tun: free skb in early errors tun_recvmsg() supports accepting skb by msg_control after commit ac77cfd4258f ("tun: support receiving skb through msg_control"), the skb if presented should be freed no matter how far it can go along, otherwise it would be leaked. This patch fixes several missed cases. Signed-off-by: Wei Xu Reported-by: Matthew Rosato Acked-by: Michael S. Tsirkin Signed-off-by: David S. Miller --- drivers/net/tun.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 95749006d687..4f4a842a1c9c 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -1952,8 +1952,11 @@ static ssize_t tun_do_read(struct tun_struct *tun, struct tun_file *tfile, tun_debug(KERN_INFO, tun, "tun_do_read\n"); - if (!iov_iter_count(to)) + if (!iov_iter_count(to)) { + if (skb) + kfree_skb(skb); return 0; + } if (!skb) { /* Read frames from ring */ @@ -2069,22 +2072,24 @@ static int tun_recvmsg(struct socket *sock, struct msghdr *m, size_t total_len, { struct tun_file *tfile = container_of(sock, struct tun_file, socket); struct tun_struct *tun = tun_get(tfile); + struct sk_buff *skb = m->msg_control; int ret; - if (!tun) - return -EBADFD; + if (!tun) { + ret = -EBADFD; + goto out_free_skb; + } if (flags & ~(MSG_DONTWAIT|MSG_TRUNC|MSG_ERRQUEUE)) { ret = -EINVAL; - goto out; + goto out_put_tun; } if (flags & MSG_ERRQUEUE) { ret = sock_recv_errqueue(sock->sk, m, total_len, SOL_PACKET, TUN_TX_TIMESTAMP); goto out; } - ret = tun_do_read(tun, tfile, &m->msg_iter, flags & MSG_DONTWAIT, - m->msg_control); + ret = tun_do_read(tun, tfile, &m->msg_iter, flags & MSG_DONTWAIT, skb); if (ret > (ssize_t)total_len) { m->msg_flags |= MSG_TRUNC; ret = flags & MSG_TRUNC ? ret : total_len; @@ -2092,6 +2097,13 @@ static int tun_recvmsg(struct socket *sock, struct msghdr *m, size_t total_len, out: tun_put(tun); return ret; + +out_put_tun: + tun_put(tun); +out_free_skb: + if (skb) + kfree_skb(skb); + return ret; } static int tun_peek_len(struct socket *sock) -- GitLab From 61d78537843e676e7f56ac6db333db0c0529b892 Mon Sep 17 00:00:00 2001 From: Wei Xu Date: Fri, 1 Dec 2017 05:10:38 -0500 Subject: [PATCH 0478/2547] tap: free skb if flags error tap_recvmsg() supports accepting skb by msg_control after commit 3b4ba04acca8 ("tap: support receiving skb from msg_control"), the skb if presented should be freed within the function, otherwise it would be leaked. Signed-off-by: Wei Xu Reported-by: Matthew Rosato Acked-by: Michael S. Tsirkin Signed-off-by: David S. Miller --- drivers/net/tap.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/net/tap.c b/drivers/net/tap.c index e9489b88407c..0a886fda0129 100644 --- a/drivers/net/tap.c +++ b/drivers/net/tap.c @@ -829,8 +829,11 @@ static ssize_t tap_do_read(struct tap_queue *q, DEFINE_WAIT(wait); ssize_t ret = 0; - if (!iov_iter_count(to)) + if (!iov_iter_count(to)) { + if (skb) + kfree_skb(skb); return 0; + } if (skb) goto put; @@ -1154,11 +1157,14 @@ static int tap_recvmsg(struct socket *sock, struct msghdr *m, size_t total_len, int flags) { struct tap_queue *q = container_of(sock, struct tap_queue, sock); + struct sk_buff *skb = m->msg_control; int ret; - if (flags & ~(MSG_DONTWAIT|MSG_TRUNC)) + if (flags & ~(MSG_DONTWAIT|MSG_TRUNC)) { + if (skb) + kfree_skb(skb); return -EINVAL; - ret = tap_do_read(q, &m->msg_iter, flags & MSG_DONTWAIT, - m->msg_control); + } + ret = tap_do_read(q, &m->msg_iter, flags & MSG_DONTWAIT, skb); if (ret > total_len) { m->msg_flags |= MSG_TRUNC; ret = flags & MSG_TRUNC ? ret : total_len; -- GitLab From bc3ab70584696cb798b9e1e0ac8e6ced5fd4c3b8 Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Fri, 1 Dec 2017 10:14:49 +0100 Subject: [PATCH 0479/2547] s390/qeth: fix thinko in IPv4 multicast address tracking Commit 5f78e29ceebf ("qeth: optimize IP handling in rx_mode callback") reworked how secondary addresses are managed for qeth devices. Instead of dropping & subsequently re-adding all addresses on every ndo_set_rx_mode() call, qeth now keeps track of the addresses that are currently registered with the HW. On a ndo_set_rx_mode(), we thus only need to do (de-)registration requests for the addresses that have actually changed. On L3 devices, the lookup for IPv4 Multicast addresses checks the wrong hashtable - and thus never finds a match. As a result, we first delete *all* such addresses, and then re-add them again. So each set_rx_mode() causes a short period where the IPv4 Multicast addresses are not registered, and the card stops forwarding inbound traffic for them. Fix this by setting the ->is_multicast flag on the lookup object, thus enabling qeth_l3_ip_from_hash() to search the correct hashtable and find a match there. Fixes: 5f78e29ceebf ("qeth: optimize IP handling in rx_mode callback") Signed-off-by: Julian Wiedmann Signed-off-by: David S. Miller --- drivers/s390/net/qeth_l3_main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/s390/net/qeth_l3_main.c b/drivers/s390/net/qeth_l3_main.c index aadd384316a3..e79936b50698 100644 --- a/drivers/s390/net/qeth_l3_main.c +++ b/drivers/s390/net/qeth_l3_main.c @@ -1376,6 +1376,7 @@ qeth_l3_add_mc_to_hash(struct qeth_card *card, struct in_device *in4_dev) tmp->u.a4.addr = be32_to_cpu(im4->multiaddr); memcpy(tmp->mac, buf, sizeof(tmp->mac)); + tmp->is_multicast = 1; ipm = qeth_l3_ip_from_hash(card, tmp); if (ipm) { -- GitLab From 6d69b1f1eb7a2edf8a3547f361c61f2538e054bb Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Fri, 1 Dec 2017 10:14:50 +0100 Subject: [PATCH 0480/2547] s390/qeth: fix GSO throughput regression Using GSO with small MTUs currently results in a substantial throughput regression - which is caused by how qeth needs to map non-linear skbs into its IO buffer elements: compared to a linear skb, each GSO-segmented skb effectively consumes twice as many buffer elements (ie two instead of one) due to the additional header-only part. This causes the Output Queue to be congested with low-utilized IO buffers. Fix this as follows: If the MSS is low enough so that a non-SG GSO segmentation produces order-0 skbs (currently ~3500 byte), opt out from NETIF_F_SG. This is where we anticipate the biggest savings, since an SG-enabled GSO segmentation produces skbs that always consume at least two buffer elements. Larger MSS values continue to get a SG-enabled GSO segmentation, since 1) the relative overhead of the additional header-only buffer element becomes less noticeable, and 2) the linearization overhead increases. With the throughput regression fixed, re-enable NETIF_F_SG by default to reap the significant CPU savings of GSO. Fixes: 5722963a8e83 ("qeth: do not turn on SG per default") Reported-by: Nils Hoppmann Signed-off-by: Julian Wiedmann Signed-off-by: David S. Miller --- drivers/s390/net/qeth_core.h | 3 +++ drivers/s390/net/qeth_core_main.c | 31 +++++++++++++++++++++++++++++++ drivers/s390/net/qeth_l2_main.c | 2 ++ drivers/s390/net/qeth_l3_main.c | 2 ++ 4 files changed, 38 insertions(+) diff --git a/drivers/s390/net/qeth_core.h b/drivers/s390/net/qeth_core.h index 9cd569ef43ec..15015a24f8ad 100644 --- a/drivers/s390/net/qeth_core.h +++ b/drivers/s390/net/qeth_core.h @@ -987,6 +987,9 @@ struct qeth_cmd_buffer *qeth_get_setassparms_cmd(struct qeth_card *, int qeth_set_features(struct net_device *, netdev_features_t); void qeth_recover_features(struct net_device *dev); netdev_features_t qeth_fix_features(struct net_device *, netdev_features_t); +netdev_features_t qeth_features_check(struct sk_buff *skb, + struct net_device *dev, + netdev_features_t features); int qeth_vm_request_mac(struct qeth_card *card); int qeth_push_hdr(struct sk_buff *skb, struct qeth_hdr **hdr, unsigned int len); diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c index 49b9efeba1bd..d9b0e07d4fa7 100644 --- a/drivers/s390/net/qeth_core_main.c +++ b/drivers/s390/net/qeth_core_main.c @@ -19,6 +19,11 @@ #include #include #include +#include +#include +#include +#include + #include #include @@ -6438,6 +6443,32 @@ netdev_features_t qeth_fix_features(struct net_device *dev, } EXPORT_SYMBOL_GPL(qeth_fix_features); +netdev_features_t qeth_features_check(struct sk_buff *skb, + struct net_device *dev, + netdev_features_t features) +{ + /* GSO segmentation builds skbs with + * a (small) linear part for the headers, and + * page frags for the data. + * Compared to a linear skb, the header-only part consumes an + * additional buffer element. This reduces buffer utilization, and + * hurts throughput. So compress small segments into one element. + */ + if (netif_needs_gso(skb, features)) { + /* match skb_segment(): */ + unsigned int doffset = skb->data - skb_mac_header(skb); + unsigned int hsize = skb_shinfo(skb)->gso_size; + unsigned int hroom = skb_headroom(skb); + + /* linearize only if resulting skb allocations are order-0: */ + if (SKB_DATA_ALIGN(hroom + doffset + hsize) <= SKB_MAX_HEAD(0)) + features &= ~NETIF_F_SG; + } + + return vlan_features_check(skb, features); +} +EXPORT_SYMBOL_GPL(qeth_features_check); + static int __init qeth_core_init(void) { int rc; diff --git a/drivers/s390/net/qeth_l2_main.c b/drivers/s390/net/qeth_l2_main.c index d2537c09126d..85162712d207 100644 --- a/drivers/s390/net/qeth_l2_main.c +++ b/drivers/s390/net/qeth_l2_main.c @@ -960,6 +960,7 @@ static const struct net_device_ops qeth_l2_netdev_ops = { .ndo_stop = qeth_l2_stop, .ndo_get_stats = qeth_get_stats, .ndo_start_xmit = qeth_l2_hard_start_xmit, + .ndo_features_check = qeth_features_check, .ndo_validate_addr = eth_validate_addr, .ndo_set_rx_mode = qeth_l2_set_rx_mode, .ndo_do_ioctl = qeth_do_ioctl, @@ -1010,6 +1011,7 @@ static int qeth_l2_setup_netdev(struct qeth_card *card) if (card->info.type == QETH_CARD_TYPE_OSD && !card->info.guestlan) { card->dev->hw_features = NETIF_F_SG; card->dev->vlan_features = NETIF_F_SG; + card->dev->features |= NETIF_F_SG; /* OSA 3S and earlier has no RX/TX support */ if (qeth_is_supported(card, IPA_OUTBOUND_CHECKSUM)) { card->dev->hw_features |= NETIF_F_IP_CSUM; diff --git a/drivers/s390/net/qeth_l3_main.c b/drivers/s390/net/qeth_l3_main.c index e79936b50698..46a841258fc8 100644 --- a/drivers/s390/net/qeth_l3_main.c +++ b/drivers/s390/net/qeth_l3_main.c @@ -2918,6 +2918,7 @@ static const struct net_device_ops qeth_l3_osa_netdev_ops = { .ndo_stop = qeth_l3_stop, .ndo_get_stats = qeth_get_stats, .ndo_start_xmit = qeth_l3_hard_start_xmit, + .ndo_features_check = qeth_features_check, .ndo_validate_addr = eth_validate_addr, .ndo_set_rx_mode = qeth_l3_set_multicast_list, .ndo_do_ioctl = qeth_do_ioctl, @@ -2958,6 +2959,7 @@ static int qeth_l3_setup_netdev(struct qeth_card *card) card->dev->vlan_features = NETIF_F_SG | NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_TSO; + card->dev->features |= NETIF_F_SG; } } } else if (card->info.type == QETH_CARD_TYPE_IQD) { -- GitLab From 0cbff6d4546613330a1c5f139f5c368e4ce33ca1 Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Fri, 1 Dec 2017 10:14:51 +0100 Subject: [PATCH 0481/2547] s390/qeth: build max size GSO skbs on L2 devices The current GSO skb size limit was copy&pasted over from the L3 path, where it is needed due to a TSO limitation. As L2 devices don't offer TSO support (and thus all GSO skbs are segmented before they reach the driver), there's no reason to restrict the stack in how large it may build the GSO skbs. Fixes: d52aec97e5bc ("qeth: enable scatter/gather in layer 2 mode") Signed-off-by: Julian Wiedmann Signed-off-by: David S. Miller --- drivers/s390/net/qeth_l2_main.c | 2 -- drivers/s390/net/qeth_l3_main.c | 4 ++-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/s390/net/qeth_l2_main.c b/drivers/s390/net/qeth_l2_main.c index 85162712d207..f21c94810373 100644 --- a/drivers/s390/net/qeth_l2_main.c +++ b/drivers/s390/net/qeth_l2_main.c @@ -1030,8 +1030,6 @@ static int qeth_l2_setup_netdev(struct qeth_card *card) card->info.broadcast_capable = 1; qeth_l2_request_initial_mac(card); - card->dev->gso_max_size = (QETH_MAX_BUFFER_ELEMENTS(card) - 1) * - PAGE_SIZE; SET_NETDEV_DEV(card->dev, &card->gdev->dev); netif_napi_add(card->dev, &card->napi, qeth_poll, QETH_NAPI_WEIGHT); netif_carrier_off(card->dev); diff --git a/drivers/s390/net/qeth_l3_main.c b/drivers/s390/net/qeth_l3_main.c index 46a841258fc8..2a25f20566d8 100644 --- a/drivers/s390/net/qeth_l3_main.c +++ b/drivers/s390/net/qeth_l3_main.c @@ -2987,8 +2987,8 @@ static int qeth_l3_setup_netdev(struct qeth_card *card) NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER; netif_keep_dst(card->dev); - card->dev->gso_max_size = (QETH_MAX_BUFFER_ELEMENTS(card) - 1) * - PAGE_SIZE; + netif_set_gso_max_size(card->dev, (QETH_MAX_BUFFER_ELEMENTS(card) - 1) * + PAGE_SIZE); SET_NETDEV_DEV(card->dev, &card->gdev->dev); netif_napi_add(card->dev, &card->napi, qeth_poll, QETH_NAPI_WEIGHT); -- GitLab From a98a4ebc8c61d20f0150d6be66e0e65223a347af Mon Sep 17 00:00:00 2001 From: Gao Feng Date: Fri, 1 Dec 2017 09:58:42 +0800 Subject: [PATCH 0482/2547] ipvlan: Add the skb->mark as flow4's member to lookup route Current codes don't use skb->mark to assign flowi4_mark, it would make the policy route rule with fwmark doesn't work as expected. Signed-off-by: Gao Feng Signed-off-by: David S. Miller --- drivers/net/ipvlan/ipvlan_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ipvlan/ipvlan_core.c b/drivers/net/ipvlan/ipvlan_core.c index 11c1e7950fe5..77cc4fbaeace 100644 --- a/drivers/net/ipvlan/ipvlan_core.c +++ b/drivers/net/ipvlan/ipvlan_core.c @@ -393,6 +393,7 @@ static int ipvlan_process_v4_outbound(struct sk_buff *skb) .flowi4_oif = dev->ifindex, .flowi4_tos = RT_TOS(ip4h->tos), .flowi4_flags = FLOWI_FLAG_ANYSRC, + .flowi4_mark = skb->mark, .daddr = ip4h->daddr, .saddr = ip4h->saddr, }; -- GitLab From 45ab4b13e46325d00f4acdb365d406e941a15f81 Mon Sep 17 00:00:00 2001 From: Lars Persson Date: Fri, 1 Dec 2017 11:12:44 +0100 Subject: [PATCH 0483/2547] stmmac: reset last TSO segment size after device open The mss variable tracks the last max segment size sent to the TSO engine. We do not update the hardware as long as we receive skb:s with the same value in gso_size. During a network device down/up cycle (mapped to stmmac_release() and stmmac_open() callbacks) we issue a reset to the hardware and it forgets the setting for mss. However we did not zero out our mss variable so the next transmission of a gso packet happens with an undefined hardware setting. This triggers a hang in the TSO engine and eventuelly the netdev watchdog will bark. Fixes: f748be531d70 ("stmmac: support new GMAC4") Signed-off-by: Lars Persson Signed-off-by: David S. Miller --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index f63c2ddced3c..d7250539d0bd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -2588,6 +2588,7 @@ static int stmmac_open(struct net_device *dev) priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); priv->rx_copybreak = STMMAC_RX_COPYBREAK; + priv->mss = 0; ret = alloc_dma_desc_resources(priv); if (ret < 0) { -- GitLab From 886afc1dc489436bf2c4fadf0f3aecacd7269234 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Fri, 1 Dec 2017 12:38:11 +0000 Subject: [PATCH 0484/2547] liquidio: fix incorrect indentation of assignment statement Remove one extraneous level of indentation on assignment statement. Signed-off-by: Colin Ian King Signed-off-by: David S. Miller --- drivers/net/ethernet/cavium/liquidio/lio_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/cavium/liquidio/lio_main.c b/drivers/net/ethernet/cavium/liquidio/lio_main.c index 6aa0eee88ea5..a5eecd895a82 100644 --- a/drivers/net/ethernet/cavium/liquidio/lio_main.c +++ b/drivers/net/ethernet/cavium/liquidio/lio_main.c @@ -1113,7 +1113,7 @@ static int liquidio_watchdog(void *param) dev_err(&oct->pci_dev->dev, "ERROR: Octeon core %d crashed or got stuck! See oct-fwdump for details.\n", core); - err_msg_was_printed[core] = true; + err_msg_was_printed[core] = true; } } -- GitLab From c501256406fb19c306504ee1fe41a4ea208d4245 Mon Sep 17 00:00:00 2001 From: David Howells Date: Fri, 1 Dec 2017 11:09:53 +0000 Subject: [PATCH 0485/2547] rxrpc: Use correct netns source in rxrpc_release_sock() In rxrpc_release_sock() there may be no rx->local value to access, so we can't unconditionally follow it to the rxrpc network namespace information to poke the connection reapers. Instead, use the socket's namespace pointer to find the namespace. This unfixed code causes the following static checker warning: net/rxrpc/af_rxrpc.c:898 rxrpc_release_sock() error: we previously assumed 'rx->local' could be null (see line 887) Fixes: 3d18cbb7fd0c ("rxrpc: Fix conn expiry timers") Reported-by: Dan Carpenter Signed-off-by: David Howells Signed-off-by: David S. Miller --- net/rxrpc/af_rxrpc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/net/rxrpc/af_rxrpc.c b/net/rxrpc/af_rxrpc.c index 8f7cf4c042be..dcd818fa837e 100644 --- a/net/rxrpc/af_rxrpc.c +++ b/net/rxrpc/af_rxrpc.c @@ -860,6 +860,7 @@ static void rxrpc_sock_destructor(struct sock *sk) static int rxrpc_release_sock(struct sock *sk) { struct rxrpc_sock *rx = rxrpc_sk(sk); + struct rxrpc_net *rxnet = rxrpc_net(sock_net(&rx->sk)); _enter("%p{%d,%d}", sk, sk->sk_state, refcount_read(&sk->sk_refcnt)); @@ -895,8 +896,8 @@ static int rxrpc_release_sock(struct sock *sk) rxrpc_release_calls_on_socket(rx); flush_workqueue(rxrpc_workqueue); rxrpc_purge_queue(&sk->sk_receive_queue); - rxrpc_queue_work(&rx->local->rxnet->service_conn_reaper); - rxrpc_queue_work(&rx->local->rxnet->client_conn_reaper); + rxrpc_queue_work(&rxnet->service_conn_reaper); + rxrpc_queue_work(&rxnet->client_conn_reaper); rxrpc_put_local(rx->local); rx->local = NULL; -- GitLab From bcd1d601e5cc760bf5743a59e4716603490e281c Mon Sep 17 00:00:00 2001 From: David Howells Date: Fri, 1 Dec 2017 11:10:37 +0000 Subject: [PATCH 0486/2547] rxrpc: Fix the MAINTAINERS record Fix the MAINTAINERS record so that it's more obvious who the maintainer for AF_RXRPC is. Reported-by: Joe Perches Reported-by: David Miller Signed-off-by: David Howells Signed-off-by: David S. Miller --- MAINTAINERS | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 77d819b458a9..511b858405bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -554,13 +554,13 @@ S: Orphan F: Documentation/filesystems/affs.txt F: fs/affs/ -AFS FILESYSTEM & AF_RXRPC SOCKET DOMAIN +AFS FILESYSTEM M: David Howells L: linux-afs@lists.infradead.org S: Supported F: fs/afs/ -F: include/net/af_rxrpc.h -F: net/rxrpc/af_rxrpc.c +F: include/trace/events/afs.h +F: Documentation/filesystems/afs.txt W: https://www.infradead.org/~dhowells/kafs/ AGPGART DRIVER @@ -11777,6 +11777,18 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/jes/linux.git rtl8xxxu-deve S: Maintained F: drivers/net/wireless/realtek/rtl8xxxu/ +RXRPC SOCKETS (AF_RXRPC) +M: David Howells +L: linux-afs@lists.infradead.org +S: Supported +F: net/rxrpc/ +F: include/keys/rxrpc-type.h +F: include/net/af_rxrpc.h +F: include/trace/events/rxrpc.h +F: include/uapi/linux/rxrpc.h +F: Documentation/networking/rxrpc.txt +W: https://www.infradead.org/~dhowells/kafs/ + S3 SAVAGE FRAMEBUFFER DRIVER M: Antonino Daplas L: linux-fbdev@vger.kernel.org -- GitLab From eeea10b83a139451130df1594f26710c8fa390c8 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Sun, 3 Dec 2017 09:32:59 -0800 Subject: [PATCH 0487/2547] tcp: add tcp_v4_fill_cb()/tcp_v4_restore_cb() James Morris reported kernel stack corruption bug [1] while running the SELinux testsuite, and bisected to a recent commit bffa72cf7f9d ("net: sk_buff rbnode reorg") We believe this commit is fine, but exposes an older bug. SELinux code runs from tcp_filter() and might send an ICMP, expecting IP options to be found in skb->cb[] using regular IPCB placement. We need to defer TCP mangling of skb->cb[] after tcp_filter() calls. This patch adds tcp_v4_fill_cb()/tcp_v4_restore_cb() in a very similar way we added them for IPv6. [1] [ 339.806024] SELinux: failure in selinux_parse_skb(), unable to parse packet [ 339.822505] Kernel panic - not syncing: stack-protector: Kernel stack is corrupted in: ffffffff81745af5 [ 339.822505] [ 339.852250] CPU: 4 PID: 3642 Comm: client Not tainted 4.15.0-rc1-test #15 [ 339.868498] Hardware name: LENOVO 10FGS0VA1L/30BC, BIOS FWKT68A 01/19/2017 [ 339.885060] Call Trace: [ 339.896875] [ 339.908103] dump_stack+0x63/0x87 [ 339.920645] panic+0xe8/0x248 [ 339.932668] ? ip_push_pending_frames+0x33/0x40 [ 339.946328] ? icmp_send+0x525/0x530 [ 339.958861] ? kfree_skbmem+0x60/0x70 [ 339.971431] __stack_chk_fail+0x1b/0x20 [ 339.984049] icmp_send+0x525/0x530 [ 339.996205] ? netlbl_skbuff_err+0x36/0x40 [ 340.008997] ? selinux_netlbl_err+0x11/0x20 [ 340.021816] ? selinux_socket_sock_rcv_skb+0x211/0x230 [ 340.035529] ? security_sock_rcv_skb+0x3b/0x50 [ 340.048471] ? sk_filter_trim_cap+0x44/0x1c0 [ 340.061246] ? tcp_v4_inbound_md5_hash+0x69/0x1b0 [ 340.074562] ? tcp_filter+0x2c/0x40 [ 340.086400] ? tcp_v4_rcv+0x820/0xa20 [ 340.098329] ? ip_local_deliver_finish+0x71/0x1a0 [ 340.111279] ? ip_local_deliver+0x6f/0xe0 [ 340.123535] ? ip_rcv_finish+0x3a0/0x3a0 [ 340.135523] ? ip_rcv_finish+0xdb/0x3a0 [ 340.147442] ? ip_rcv+0x27c/0x3c0 [ 340.158668] ? inet_del_offload+0x40/0x40 [ 340.170580] ? __netif_receive_skb_core+0x4ac/0x900 [ 340.183285] ? rcu_accelerate_cbs+0x5b/0x80 [ 340.195282] ? __netif_receive_skb+0x18/0x60 [ 340.207288] ? process_backlog+0x95/0x140 [ 340.218948] ? net_rx_action+0x26c/0x3b0 [ 340.230416] ? __do_softirq+0xc9/0x26a [ 340.241625] ? do_softirq_own_stack+0x2a/0x40 [ 340.253368] [ 340.262673] ? do_softirq+0x50/0x60 [ 340.273450] ? __local_bh_enable_ip+0x57/0x60 [ 340.285045] ? ip_finish_output2+0x175/0x350 [ 340.296403] ? ip_finish_output+0x127/0x1d0 [ 340.307665] ? nf_hook_slow+0x3c/0xb0 [ 340.318230] ? ip_output+0x72/0xe0 [ 340.328524] ? ip_fragment.constprop.54+0x80/0x80 [ 340.340070] ? ip_local_out+0x35/0x40 [ 340.350497] ? ip_queue_xmit+0x15c/0x3f0 [ 340.361060] ? __kmalloc_reserve.isra.40+0x31/0x90 [ 340.372484] ? __skb_clone+0x2e/0x130 [ 340.382633] ? tcp_transmit_skb+0x558/0xa10 [ 340.393262] ? tcp_connect+0x938/0xad0 [ 340.403370] ? ktime_get_with_offset+0x4c/0xb0 [ 340.414206] ? tcp_v4_connect+0x457/0x4e0 [ 340.424471] ? __inet_stream_connect+0xb3/0x300 [ 340.435195] ? inet_stream_connect+0x3b/0x60 [ 340.445607] ? SYSC_connect+0xd9/0x110 [ 340.455455] ? __audit_syscall_entry+0xaf/0x100 [ 340.466112] ? syscall_trace_enter+0x1d0/0x2b0 [ 340.476636] ? __audit_syscall_exit+0x209/0x290 [ 340.487151] ? SyS_connect+0xe/0x10 [ 340.496453] ? do_syscall_64+0x67/0x1b0 [ 340.506078] ? entry_SYSCALL64_slow_path+0x25/0x25 Fixes: 971f10eca186 ("tcp: better TCP_SKB_CB layout to reduce cache line misses") Signed-off-by: Eric Dumazet Reported-by: James Morris Tested-by: James Morris Tested-by: Casey Schaufler Signed-off-by: David S. Miller --- net/ipv4/tcp_ipv4.c | 59 ++++++++++++++++++++++++++++++--------------- net/ipv6/tcp_ipv6.c | 10 +++++--- 2 files changed, 46 insertions(+), 23 deletions(-) diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c index c6bc0c4d19c6..77ea45da0fe9 100644 --- a/net/ipv4/tcp_ipv4.c +++ b/net/ipv4/tcp_ipv4.c @@ -1591,6 +1591,34 @@ int tcp_filter(struct sock *sk, struct sk_buff *skb) } EXPORT_SYMBOL(tcp_filter); +static void tcp_v4_restore_cb(struct sk_buff *skb) +{ + memmove(IPCB(skb), &TCP_SKB_CB(skb)->header.h4, + sizeof(struct inet_skb_parm)); +} + +static void tcp_v4_fill_cb(struct sk_buff *skb, const struct iphdr *iph, + const struct tcphdr *th) +{ + /* This is tricky : We move IPCB at its correct location into TCP_SKB_CB() + * barrier() makes sure compiler wont play fool^Waliasing games. + */ + memmove(&TCP_SKB_CB(skb)->header.h4, IPCB(skb), + sizeof(struct inet_skb_parm)); + barrier(); + + TCP_SKB_CB(skb)->seq = ntohl(th->seq); + TCP_SKB_CB(skb)->end_seq = (TCP_SKB_CB(skb)->seq + th->syn + th->fin + + skb->len - th->doff * 4); + TCP_SKB_CB(skb)->ack_seq = ntohl(th->ack_seq); + TCP_SKB_CB(skb)->tcp_flags = tcp_flag_byte(th); + TCP_SKB_CB(skb)->tcp_tw_isn = 0; + TCP_SKB_CB(skb)->ip_dsfield = ipv4_get_dsfield(iph); + TCP_SKB_CB(skb)->sacked = 0; + TCP_SKB_CB(skb)->has_rxtstamp = + skb->tstamp || skb_hwtstamps(skb)->hwtstamp; +} + /* * From tcp_input.c */ @@ -1631,24 +1659,6 @@ int tcp_v4_rcv(struct sk_buff *skb) th = (const struct tcphdr *)skb->data; iph = ip_hdr(skb); - /* This is tricky : We move IPCB at its correct location into TCP_SKB_CB() - * barrier() makes sure compiler wont play fool^Waliasing games. - */ - memmove(&TCP_SKB_CB(skb)->header.h4, IPCB(skb), - sizeof(struct inet_skb_parm)); - barrier(); - - TCP_SKB_CB(skb)->seq = ntohl(th->seq); - TCP_SKB_CB(skb)->end_seq = (TCP_SKB_CB(skb)->seq + th->syn + th->fin + - skb->len - th->doff * 4); - TCP_SKB_CB(skb)->ack_seq = ntohl(th->ack_seq); - TCP_SKB_CB(skb)->tcp_flags = tcp_flag_byte(th); - TCP_SKB_CB(skb)->tcp_tw_isn = 0; - TCP_SKB_CB(skb)->ip_dsfield = ipv4_get_dsfield(iph); - TCP_SKB_CB(skb)->sacked = 0; - TCP_SKB_CB(skb)->has_rxtstamp = - skb->tstamp || skb_hwtstamps(skb)->hwtstamp; - lookup: sk = __inet_lookup_skb(&tcp_hashinfo, skb, __tcp_hdrlen(th), th->source, th->dest, sdif, &refcounted); @@ -1679,14 +1689,19 @@ int tcp_v4_rcv(struct sk_buff *skb) sock_hold(sk); refcounted = true; nsk = NULL; - if (!tcp_filter(sk, skb)) + if (!tcp_filter(sk, skb)) { + th = (const struct tcphdr *)skb->data; + iph = ip_hdr(skb); + tcp_v4_fill_cb(skb, iph, th); nsk = tcp_check_req(sk, skb, req, false); + } if (!nsk) { reqsk_put(req); goto discard_and_relse; } if (nsk == sk) { reqsk_put(req); + tcp_v4_restore_cb(skb); } else if (tcp_child_process(sk, nsk, skb)) { tcp_v4_send_reset(nsk, skb); goto discard_and_relse; @@ -1712,6 +1727,7 @@ int tcp_v4_rcv(struct sk_buff *skb) goto discard_and_relse; th = (const struct tcphdr *)skb->data; iph = ip_hdr(skb); + tcp_v4_fill_cb(skb, iph, th); skb->dev = NULL; @@ -1742,6 +1758,8 @@ int tcp_v4_rcv(struct sk_buff *skb) if (!xfrm4_policy_check(NULL, XFRM_POLICY_IN, skb)) goto discard_it; + tcp_v4_fill_cb(skb, iph, th); + if (tcp_checksum_complete(skb)) { csum_error: __TCP_INC_STATS(net, TCP_MIB_CSUMERRORS); @@ -1768,6 +1786,8 @@ int tcp_v4_rcv(struct sk_buff *skb) goto discard_it; } + tcp_v4_fill_cb(skb, iph, th); + if (tcp_checksum_complete(skb)) { inet_twsk_put(inet_twsk(sk)); goto csum_error; @@ -1784,6 +1804,7 @@ int tcp_v4_rcv(struct sk_buff *skb) if (sk2) { inet_twsk_deschedule_put(inet_twsk(sk)); sk = sk2; + tcp_v4_restore_cb(skb); refcounted = false; goto process; } diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c index be11dc13aa70..1f04ec0e4a7a 100644 --- a/net/ipv6/tcp_ipv6.c +++ b/net/ipv6/tcp_ipv6.c @@ -1454,7 +1454,6 @@ static int tcp_v6_rcv(struct sk_buff *skb) struct sock *nsk; sk = req->rsk_listener; - tcp_v6_fill_cb(skb, hdr, th); if (tcp_v6_inbound_md5_hash(sk, skb)) { sk_drops_add(sk, skb); reqsk_put(req); @@ -1467,8 +1466,12 @@ static int tcp_v6_rcv(struct sk_buff *skb) sock_hold(sk); refcounted = true; nsk = NULL; - if (!tcp_filter(sk, skb)) + if (!tcp_filter(sk, skb)) { + th = (const struct tcphdr *)skb->data; + hdr = ipv6_hdr(skb); + tcp_v6_fill_cb(skb, hdr, th); nsk = tcp_check_req(sk, skb, req, false); + } if (!nsk) { reqsk_put(req); goto discard_and_relse; @@ -1492,8 +1495,6 @@ static int tcp_v6_rcv(struct sk_buff *skb) if (!xfrm6_policy_check(sk, XFRM_POLICY_IN, skb)) goto discard_and_relse; - tcp_v6_fill_cb(skb, hdr, th); - if (tcp_v6_inbound_md5_hash(sk, skb)) goto discard_and_relse; @@ -1501,6 +1502,7 @@ static int tcp_v6_rcv(struct sk_buff *skb) goto discard_and_relse; th = (const struct tcphdr *)skb->data; hdr = ipv6_hdr(skb); + tcp_v6_fill_cb(skb, hdr, th); skb->dev = NULL; -- GitLab From b4d1605a8ea608fd7dc45b926a05d75d340bde4b Mon Sep 17 00:00:00 2001 From: David Ahern Date: Sun, 3 Dec 2017 09:33:00 -0800 Subject: [PATCH 0488/2547] tcp: use IPCB instead of TCP_SKB_CB in inet_exact_dif_match() After this fix : ("tcp: add tcp_v4_fill_cb()/tcp_v4_restore_cb()"), socket lookups happen while skb->cb[] has not been mangled yet by TCP. Fixes: a04a480d4392 ("net: Require exact match for TCP socket lookups if dif is l3mdev") Signed-off-by: David Ahern Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller --- include/net/tcp.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/net/tcp.h b/include/net/tcp.h index 4e09398009c1..6998707e81f3 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -844,12 +844,11 @@ static inline int tcp_v6_sdif(const struct sk_buff *skb) } #endif -/* TCP_SKB_CB reference means this can not be used from early demux */ static inline bool inet_exact_dif_match(struct net *net, struct sk_buff *skb) { #if IS_ENABLED(CONFIG_NET_L3_MASTER_DEV) if (!net->ipv4.sysctl_tcp_l3mdev_accept && - skb && ipv4_l3mdev_skb(TCP_SKB_CB(skb)->header.h4.flags)) + skb && ipv4_l3mdev_skb(IPCB(skb)->flags)) return true; #endif return false; -- GitLab From f9ecc83f8d723372976df8eda3193726d7a24fcb Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 1 Dec 2017 13:37:12 -0500 Subject: [PATCH 0489/2547] eeprom: at24: fix I2C device selection for runtime PM The at24 driver creates dummy I2C devices to access offsets in the chip that are outside the area supported using a single I2C address. It is not meaningful to use runtime PM to such devices; the system firmware (ACPI) does not know about these devices nor runtime PM was enabled for them. Always use the real device instead of the dummy ones. Fixes: 98e8201039af ("eeprom: at24: enable runtime pm support") Signed-off-by: Sakari Ailus Tested-by: Sven Van Asbroeck on a 24AA16/24LC16B [Bartosz: rebased on top of previous fixes for 4.15, tweaked the commit message] [Sven: fixed Bartosz's rebase] Signed-off-by: Sven Van Asbroeck Signed-off-by: Bartosz Golaszewski --- drivers/misc/eeprom/at24.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c index 305a7a464d09..20b4f26d30d7 100644 --- a/drivers/misc/eeprom/at24.c +++ b/drivers/misc/eeprom/at24.c @@ -562,7 +562,7 @@ static ssize_t at24_eeprom_write_i2c(struct at24_data *at24, const char *buf, static int at24_read(void *priv, unsigned int off, void *val, size_t count) { struct at24_data *at24 = priv; - struct i2c_client *client; + struct device *dev = &at24->client[0]->dev; char *buf = val; int ret; @@ -572,11 +572,9 @@ static int at24_read(void *priv, unsigned int off, void *val, size_t count) if (off + count > at24->chip.byte_len) return -EINVAL; - client = at24_translate_offset(at24, &off); - - ret = pm_runtime_get_sync(&client->dev); + ret = pm_runtime_get_sync(dev); if (ret < 0) { - pm_runtime_put_noidle(&client->dev); + pm_runtime_put_noidle(dev); return ret; } @@ -592,7 +590,7 @@ static int at24_read(void *priv, unsigned int off, void *val, size_t count) status = at24->read_func(at24, buf, off, count); if (status < 0) { mutex_unlock(&at24->lock); - pm_runtime_put(&client->dev); + pm_runtime_put(dev); return status; } buf += status; @@ -602,7 +600,7 @@ static int at24_read(void *priv, unsigned int off, void *val, size_t count) mutex_unlock(&at24->lock); - pm_runtime_put(&client->dev); + pm_runtime_put(dev); return 0; } @@ -610,7 +608,7 @@ static int at24_read(void *priv, unsigned int off, void *val, size_t count) static int at24_write(void *priv, unsigned int off, void *val, size_t count) { struct at24_data *at24 = priv; - struct i2c_client *client; + struct device *dev = &at24->client[0]->dev; char *buf = val; int ret; @@ -620,11 +618,9 @@ static int at24_write(void *priv, unsigned int off, void *val, size_t count) if (off + count > at24->chip.byte_len) return -EINVAL; - client = at24_translate_offset(at24, &off); - - ret = pm_runtime_get_sync(&client->dev); + ret = pm_runtime_get_sync(dev); if (ret < 0) { - pm_runtime_put_noidle(&client->dev); + pm_runtime_put_noidle(dev); return ret; } @@ -640,7 +636,7 @@ static int at24_write(void *priv, unsigned int off, void *val, size_t count) status = at24->write_func(at24, buf, off, count); if (status < 0) { mutex_unlock(&at24->lock); - pm_runtime_put(&client->dev); + pm_runtime_put(dev); return status; } buf += status; @@ -650,7 +646,7 @@ static int at24_write(void *priv, unsigned int off, void *val, size_t count) mutex_unlock(&at24->lock); - pm_runtime_put(&client->dev); + pm_runtime_put(dev); return 0; } -- GitLab From 9956cfef3409177d9e24ea4b7910148a18073a6f Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 3 Dec 2017 13:15:39 -0800 Subject: [PATCH 0490/2547] Documentation: fix docs build error after source file removed The pci/htirq.c file was removed so remove it from the documentation file also. Error: Cannot open file ../drivers/pci/htirq.c WARNING: kernel-doc '../scripts/kernel-doc -rst -enable-lineno -export ../drivers/pci/htirq.c' failed with return code 2 Fixes: fd2fa6c18b72 ("x86/PCI: Remove unused HyperTransport interrupt support") Signed-off-by: Randy Dunlap Signed-off-by: Jonathan Corbet --- Documentation/driver-api/pci.rst | 3 --- 1 file changed, 3 deletions(-) diff --git a/Documentation/driver-api/pci.rst b/Documentation/driver-api/pci.rst index 01a6c8b7d3a7..ca85e5e78b2c 100644 --- a/Documentation/driver-api/pci.rst +++ b/Documentation/driver-api/pci.rst @@ -25,9 +25,6 @@ PCI Support Library .. kernel-doc:: drivers/pci/irq.c :export: -.. kernel-doc:: drivers/pci/htirq.c - :export: - .. kernel-doc:: drivers/pci/probe.c :export: -- GitLab From 969de0988b77e5a57aac2f7270191a3c50540c52 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 14 Nov 2017 11:50:07 +1000 Subject: [PATCH 0491/2547] m68k: add missing SOFTIRQENTRY_TEXT linker section Commit be7635e7287e ("arch, ftrace: for KASAN put hard/soft IRQ entries into separate sections") added a new linker section, SOFTIRQENTRY_TEXT, to the linker scripts for most architectures. It didn't add it to any of the linker scripts for the m68k architecture. This was not really a problem because it is only defined if either of CONFIG_FUNCTION_GRAPH_TRACER or CONFIG_KASAN are enabled - which can never be true for m68k. However commit 229a71860547 ("irq: Make the irqentry text section unconditional") means that SOFTIRQENTRY_TEXT is now always defined. So on m68k we now end up with a separate ELF section for .softirqentry.text instead of it being part of the .text section. On some m68k targets in some configurations this can also cause a fatal link error: LD vmlinux /usr/local/bin/../m68k-uclinux/bin/ld.real: section .softirqentry.text loaded at [0000000010de10c0,0000000010de12dd] overlaps section .rodata loaded at [0000000010de10c0,0000000010e0fd67] To fix add in the missing SOFTIRQENTRY_TEXT section into the m68k linker scripts. I noticed that m68k is also missing the IRQENTRY_TEXT section, so this patch also adds an entry for that too. Signed-off-by: Greg Ungerer --- arch/m68k/kernel/vmlinux-nommu.lds | 2 ++ arch/m68k/kernel/vmlinux-std.lds | 2 ++ arch/m68k/kernel/vmlinux-sun3.lds | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/m68k/kernel/vmlinux-nommu.lds b/arch/m68k/kernel/vmlinux-nommu.lds index 3aa571a513b5..cf6edda38971 100644 --- a/arch/m68k/kernel/vmlinux-nommu.lds +++ b/arch/m68k/kernel/vmlinux-nommu.lds @@ -45,6 +45,8 @@ SECTIONS { .text : { HEAD_TEXT TEXT_TEXT + IRQENTRY_TEXT + SOFTIRQENTRY_TEXT SCHED_TEXT CPUIDLE_TEXT LOCK_TEXT diff --git a/arch/m68k/kernel/vmlinux-std.lds b/arch/m68k/kernel/vmlinux-std.lds index 89172b8974b9..625a5785804f 100644 --- a/arch/m68k/kernel/vmlinux-std.lds +++ b/arch/m68k/kernel/vmlinux-std.lds @@ -16,6 +16,8 @@ SECTIONS .text : { HEAD_TEXT TEXT_TEXT + IRQENTRY_TEXT + SOFTIRQENTRY_TEXT SCHED_TEXT CPUIDLE_TEXT LOCK_TEXT diff --git a/arch/m68k/kernel/vmlinux-sun3.lds b/arch/m68k/kernel/vmlinux-sun3.lds index 293990efc917..9868270b0984 100644 --- a/arch/m68k/kernel/vmlinux-sun3.lds +++ b/arch/m68k/kernel/vmlinux-sun3.lds @@ -16,6 +16,8 @@ SECTIONS .text : { HEAD_TEXT TEXT_TEXT + IRQENTRY_TEXT + SOFTIRQENTRY_TEXT SCHED_TEXT CPUIDLE_TEXT LOCK_TEXT -- GitLab From fc82228a5e3860502dbf3bfa4a9570cb7093cf7f Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Sun, 3 Dec 2017 20:38:01 -0500 Subject: [PATCH 0492/2547] ext4: support fast symlinks from ext3 file systems 407cd7fb83c0 (ext4: change fast symlink test to not rely on i_blocks) broke ~10 years old ext3 file systems created by 2.6.17. Any ELF executable fails because the /lib/ld-linux.so.2 fast symlink cannot be read anymore. The patch assumed fast symlinks were created in a specific way, but that's not true on these really old file systems. The new behavior is apparently needed only with the large EA inode feature. Revert to the old behavior if the large EA inode feature is not set. This makes my old VM boot again. Fixes: 407cd7fb83c0 (ext4: change fast symlink test to not rely on i_blocks) Signed-off-by: Andi Kleen Signed-off-by: Theodore Ts'o Reviewed-by: Andreas Dilger Cc: stable@vger.kernel.org --- fs/ext4/inode.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index 7df2c5644e59..534a9130f625 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -149,6 +149,15 @@ static int ext4_meta_trans_blocks(struct inode *inode, int lblocks, */ int ext4_inode_is_fast_symlink(struct inode *inode) { + if (!(EXT4_I(inode)->i_flags & EXT4_EA_INODE_FL)) { + int ea_blocks = EXT4_I(inode)->i_file_acl ? + EXT4_CLUSTER_SIZE(inode->i_sb) >> 9 : 0; + + if (ext4_has_inline_data(inode)) + return 0; + + return (S_ISLNK(inode->i_mode) && inode->i_blocks - ea_blocks == 0); + } return S_ISLNK(inode->i_mode) && inode->i_size && (inode->i_size < EXT4_N_BLOCKS * 4); } -- GitLab From ea26c96d59b27e878fe61e8ef0fed840d2281a2f Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 4 Dec 2017 11:23:44 +0800 Subject: [PATCH 0493/2547] drm/i915/gvt: Fix out-of-bounds buffer write into opregion->signature[] sparse spots drivers/gpu/drm/i915/gvt/opregion.c:234 alloc_and_init_virt_opregion() error: memcpy() 'header->signature' too small (16 vs 17) as gvt is indeed trying to memcpy a string longer than the signature[]. Fixes: b2d6ef70614e ("drm/i915/gvt: Let each vgpu has separate opregion memory") Signed-off-by: Chris Wilson Cc: Xiong Zhang Cc: Zhenyu Wang Cc: Zhi Wang Cc: intel-gvt-dev@lists.freedesktop.org Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/opregion.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/opregion.c b/drivers/gpu/drm/i915/gvt/opregion.c index 80720e59723a..bf8e5c49a64a 100644 --- a/drivers/gpu/drm/i915/gvt/opregion.c +++ b/drivers/gpu/drm/i915/gvt/opregion.c @@ -218,6 +218,7 @@ static int alloc_and_init_virt_opregion(struct intel_vgpu *vgpu) u8 *buf; struct opregion_header *header; struct vbt v; + const char opregion_signature[16] = OPREGION_SIGNATURE; gvt_dbg_core("init vgpu%d opregion\n", vgpu->id); vgpu_opregion(vgpu)->va = (void *)__get_free_pages(GFP_KERNEL | @@ -231,8 +232,8 @@ static int alloc_and_init_virt_opregion(struct intel_vgpu *vgpu) /* emulated opregion with VBT mailbox only */ buf = (u8 *)vgpu_opregion(vgpu)->va; header = (struct opregion_header *)buf; - memcpy(header->signature, OPREGION_SIGNATURE, - sizeof(OPREGION_SIGNATURE)); + memcpy(header->signature, opregion_signature, + sizeof(opregion_signature)); header->size = 0x8; header->opregion_ver = 0x02000000; header->mboxes = MBOX_VBT; -- GitLab From 4dff110b15aea2f7653957a70921a7be1f45d59b Mon Sep 17 00:00:00 2001 From: Xiong Zhang Date: Mon, 20 Nov 2017 15:31:15 +0800 Subject: [PATCH 0494/2547] drm/i915/gvt: Alloc and Init guest opregion at vgpu creation Currently guest opregion is allocated and initialised when guest write opregion base register. This is too late for kvmgt, so move it to vgpu_create time. Signed-off-by: Xiong Zhang Tested-by: Tina Zhang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/cfg_space.c | 3 +- drivers/gpu/drm/i915/gvt/gvt.h | 4 +- drivers/gpu/drm/i915/gvt/opregion.c | 90 +++++++++++++--------------- drivers/gpu/drm/i915/gvt/vgpu.c | 8 ++- 4 files changed, 53 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c index 4ce2e6bd0680..97bfc00d2a82 100644 --- a/drivers/gpu/drm/i915/gvt/cfg_space.c +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c @@ -335,7 +335,8 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, case INTEL_GVT_PCI_OPREGION: if (WARN_ON(!IS_ALIGNED(offset, 4))) return -EINVAL; - ret = intel_vgpu_init_opregion(vgpu, *(u32 *)p_data); + ret = intel_vgpu_opregion_base_write_handler(vgpu, + *(u32 *)p_data); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 393066726993..07d3ba0f7277 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -123,6 +123,7 @@ struct intel_vgpu_irq { }; struct intel_vgpu_opregion { + bool mapped; void *va; u32 gfn[INTEL_GVT_OPREGION_PAGES]; }; @@ -505,7 +506,8 @@ static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar) } void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); -int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa); +int intel_vgpu_init_opregion(struct intel_vgpu *vgpu); +int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa); int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); void populate_pvinfo_page(struct intel_vgpu *vgpu); diff --git a/drivers/gpu/drm/i915/gvt/opregion.c b/drivers/gpu/drm/i915/gvt/opregion.c index bf8e5c49a64a..36172f33bd51 100644 --- a/drivers/gpu/drm/i915/gvt/opregion.c +++ b/drivers/gpu/drm/i915/gvt/opregion.c @@ -213,7 +213,15 @@ static void virt_vbt_generation(struct vbt *v) v->driver_features.lvds_config = BDB_DRIVER_FEATURE_NO_LVDS; } -static int alloc_and_init_virt_opregion(struct intel_vgpu *vgpu) +/** + * intel_vgpu_init_opregion - initialize the stuff used to emulate opregion + * @vgpu: a vGPU + * @gpa: guest physical address of opregion + * + * Returns: + * Zero on success, negative error code if failed. + */ +int intel_vgpu_init_opregion(struct intel_vgpu *vgpu) { u8 *buf; struct opregion_header *header; @@ -251,25 +259,6 @@ static int alloc_and_init_virt_opregion(struct intel_vgpu *vgpu) return 0; } -static int init_vgpu_opregion(struct intel_vgpu *vgpu, u32 gpa) -{ - int i, ret; - - if (WARN((vgpu_opregion(vgpu)->va), - "vgpu%d: opregion has been initialized already.\n", - vgpu->id)) - return -EINVAL; - - ret = alloc_and_init_virt_opregion(vgpu); - if (ret < 0) - return ret; - - for (i = 0; i < INTEL_GVT_OPREGION_PAGES; i++) - vgpu_opregion(vgpu)->gfn[i] = (gpa >> PAGE_SHIFT) + i; - - return 0; -} - static int map_vgpu_opregion(struct intel_vgpu *vgpu, bool map) { u64 mfn; @@ -291,59 +280,62 @@ static int map_vgpu_opregion(struct intel_vgpu *vgpu, bool map) return ret; } } + + vgpu_opregion(vgpu)->mapped = map; + return 0; } /** - * intel_vgpu_clean_opregion - clean the stuff used to emulate opregion + * intel_vgpu_opregion_base_write_handler - Opregion base register write handler + * * @vgpu: a vGPU + * @gpa: guest physical address of opregion * + * Returns: + * Zero on success, negative error code if failed. */ -void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu) +int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa) { - gvt_dbg_core("vgpu%d: clean vgpu opregion\n", vgpu->id); - - if (!vgpu_opregion(vgpu)->va) - return; + int i, ret; - if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_XEN) { + /** + * Wins guest on Xengt will write this register twice: xen hvmloader and + * windows graphic driver. + */ + if (vgpu_opregion(vgpu)->mapped) map_vgpu_opregion(vgpu, false); - free_pages((unsigned long)vgpu_opregion(vgpu)->va, - get_order(INTEL_GVT_OPREGION_SIZE)); - vgpu_opregion(vgpu)->va = NULL; - } + for (i = 0; i < INTEL_GVT_OPREGION_PAGES; i++) + vgpu_opregion(vgpu)->gfn[i] = (gpa >> PAGE_SHIFT) + i; + + ret = map_vgpu_opregion(vgpu, true); + + return ret; } /** - * intel_vgpu_init_opregion - initialize the stuff used to emulate opregion + * intel_vgpu_clean_opregion - clean the stuff used to emulate opregion * @vgpu: a vGPU - * @gpa: guest physical address of opregion * - * Returns: - * Zero on success, negative error code if failed. */ -int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa) +void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu) { - int ret; - - gvt_dbg_core("vgpu%d: init vgpu opregion\n", vgpu->id); + gvt_dbg_core("vgpu%d: clean vgpu opregion\n", vgpu->id); - if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_XEN) { - gvt_dbg_core("emulate opregion from kernel\n"); + if (!vgpu_opregion(vgpu)->va) + return; - ret = init_vgpu_opregion(vgpu, gpa); - if (ret) - return ret; + if (vgpu_opregion(vgpu)->mapped) + map_vgpu_opregion(vgpu, false); - ret = map_vgpu_opregion(vgpu, true); - if (ret) - return ret; - } + free_pages((unsigned long)vgpu_opregion(vgpu)->va, + get_order(INTEL_GVT_OPREGION_SIZE)); - return 0; + vgpu_opregion(vgpu)->va = NULL; } + #define GVT_OPREGION_FUNC(scic) \ ({ \ u32 __ret; \ diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index c6b82d1ba7de..2896aafc9520 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -370,10 +370,14 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt, if (ret) goto out_detach_hypervisor_vgpu; - ret = intel_vgpu_init_display(vgpu, param->resolution); + ret = intel_vgpu_init_opregion(vgpu); if (ret) goto out_clean_gtt; + ret = intel_vgpu_init_display(vgpu, param->resolution); + if (ret) + goto out_clean_opregion; + ret = intel_vgpu_setup_submission(vgpu); if (ret) goto out_clean_display; @@ -396,6 +400,8 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt, intel_vgpu_clean_submission(vgpu); out_clean_display: intel_vgpu_clean_display(vgpu); +out_clean_opregion: + intel_vgpu_clean_opregion(vgpu); out_clean_gtt: intel_vgpu_clean_gtt(vgpu); out_detach_hypervisor_vgpu: -- GitLab From b851adeac0858c7d257b32eee2142b1519d45ccf Mon Sep 17 00:00:00 2001 From: Tina Zhang Date: Mon, 20 Nov 2017 15:31:16 +0800 Subject: [PATCH 0495/2547] drm/i915/gvt: Add opregion support Windows guest driver needs vbt in opregion, to configure the setting for display. Without opregion support, the display registers won't be set and this blocks display model to get the correct information of the guest display plane. This patch is to provide a virtual opregion for guest. The original author of this patch is Xiaoguang Chen. This patch is split from the "Dma-buf support for GVT-g" patch set, with being rebased to the latest gvt-staging branch. v3: - add checking region index during intel_vgpu_rw. (Xiong) v2: - refine intel_vgpu_reg_release_opregion. (Xiong) Here are the previous version comments: v18: - unmap vgpu's opregion when destroying vgpu. v16: - rebase to 4.14.0-rc6. Signed-off-by: Bing Niu Signed-off-by: Tina Zhang Tested-by: Xiong Zhang Cc: Zhenyu Wang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/gvt.h | 1 + drivers/gpu/drm/i915/gvt/hypercall.h | 1 + drivers/gpu/drm/i915/gvt/kvmgt.c | 108 ++++++++++++++++++++++++++- drivers/gpu/drm/i915/gvt/mpt.h | 15 ++++ drivers/gpu/drm/i915/gvt/opregion.c | 74 ++++++++++++++---- drivers/gpu/drm/i915/gvt/vgpu.c | 4 + 6 files changed, 184 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 07d3ba0f7277..f3999f251cd5 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -125,6 +125,7 @@ struct intel_vgpu_irq { struct intel_vgpu_opregion { bool mapped; void *va; + void *va_gopregion; u32 gfn[INTEL_GVT_OPREGION_PAGES]; }; diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h b/drivers/gpu/drm/i915/gvt/hypercall.h index df7f33abd393..32c345c3fa27 100644 --- a/drivers/gpu/drm/i915/gvt/hypercall.h +++ b/drivers/gpu/drm/i915/gvt/hypercall.h @@ -55,6 +55,7 @@ struct intel_gvt_mpt { unsigned long mfn, unsigned int nr, bool map); int (*set_trap_area)(unsigned long handle, u64 start, u64 end, bool map); + int (*set_opregion)(void *vgpu); }; extern struct intel_gvt_mpt xengt_mpt; diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index 110f07e8bcfb..e0cda45ac6c2 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -53,11 +53,23 @@ static const struct intel_gvt_ops *intel_gvt_ops; #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT) #define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1) +#define OPREGION_SIGNATURE "IntelGraphicsMem" + +struct vfio_region; +struct intel_vgpu_regops { + size_t (*rw)(struct intel_vgpu *vgpu, char *buf, + size_t count, loff_t *ppos, bool iswrite); + void (*release)(struct intel_vgpu *vgpu, + struct vfio_region *region); +}; + struct vfio_region { u32 type; u32 subtype; size_t size; u32 flags; + const struct intel_vgpu_regops *ops; + void *data; }; struct kvmgt_pgfn { @@ -316,6 +328,87 @@ static void kvmgt_protect_table_del(struct kvmgt_guest_info *info, } } +static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf, + size_t count, loff_t *ppos, bool iswrite) +{ + unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - + VFIO_PCI_NUM_REGIONS; + void *base = vgpu->vdev.region[i].data; + loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; + + if (pos >= vgpu->vdev.region[i].size || iswrite) { + gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n"); + return -EINVAL; + } + count = min(count, (size_t)(vgpu->vdev.region[i].size - pos)); + memcpy(buf, base + pos, count); + + return count; +} + +static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu, + struct vfio_region *region) +{ +} + +static const struct intel_vgpu_regops intel_vgpu_regops_opregion = { + .rw = intel_vgpu_reg_rw_opregion, + .release = intel_vgpu_reg_release_opregion, +}; + +static int intel_vgpu_register_reg(struct intel_vgpu *vgpu, + unsigned int type, unsigned int subtype, + const struct intel_vgpu_regops *ops, + size_t size, u32 flags, void *data) +{ + struct vfio_region *region; + + region = krealloc(vgpu->vdev.region, + (vgpu->vdev.num_regions + 1) * sizeof(*region), + GFP_KERNEL); + if (!region) + return -ENOMEM; + + vgpu->vdev.region = region; + vgpu->vdev.region[vgpu->vdev.num_regions].type = type; + vgpu->vdev.region[vgpu->vdev.num_regions].subtype = subtype; + vgpu->vdev.region[vgpu->vdev.num_regions].ops = ops; + vgpu->vdev.region[vgpu->vdev.num_regions].size = size; + vgpu->vdev.region[vgpu->vdev.num_regions].flags = flags; + vgpu->vdev.region[vgpu->vdev.num_regions].data = data; + vgpu->vdev.num_regions++; + + return 0; +} + +static int kvmgt_set_opregion(void *p_vgpu) +{ + struct intel_vgpu *vgpu = (struct intel_vgpu *)p_vgpu; + void *base; + int ret; + + /* Each vgpu has its own opregion, although VFIO would create another + * one later. This one is used to expose opregion to VFIO. And the + * other one created by VFIO later, is used by guest actually. + */ + base = vgpu_opregion(vgpu)->va; + if (!base) + return -ENOMEM; + + if (memcmp(base, OPREGION_SIGNATURE, 16)) { + memunmap(base); + return -EINVAL; + } + + ret = intel_vgpu_register_reg(vgpu, + PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE, + VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, + &intel_vgpu_regops_opregion, OPREGION_SIZE, + VFIO_REGION_INFO_FLAG_READ, base); + + return ret; +} + static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev) { struct intel_vgpu *vgpu = NULL; @@ -546,7 +639,7 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf, int ret = -EINVAL; - if (index >= VFIO_PCI_NUM_REGIONS) { + if (index >= VFIO_PCI_NUM_REGIONS + vgpu->vdev.num_regions) { gvt_vgpu_err("invalid index: %u\n", index); return -EINVAL; } @@ -574,8 +667,14 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf, case VFIO_PCI_BAR5_REGION_INDEX: case VFIO_PCI_VGA_REGION_INDEX: case VFIO_PCI_ROM_REGION_INDEX: + break; default: - gvt_vgpu_err("unsupported region: %u\n", index); + if (index >= VFIO_PCI_NUM_REGIONS + vgpu->vdev.num_regions) + return -EINVAL; + + index -= VFIO_PCI_NUM_REGIONS; + return vgpu->vdev.region[index].ops->rw(vgpu, buf, count, + ppos, is_write); } return ret == 0 ? count : ret; @@ -838,7 +937,8 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, unsigned int cmd, info.flags = VFIO_DEVICE_FLAGS_PCI; info.flags |= VFIO_DEVICE_FLAGS_RESET; - info.num_regions = VFIO_PCI_NUM_REGIONS; + info.num_regions = VFIO_PCI_NUM_REGIONS + + vgpu->vdev.num_regions; info.num_irqs = VFIO_PCI_NUM_IRQS; return copy_to_user((void __user *)arg, &info, minsz) ? @@ -959,6 +1059,7 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, unsigned int cmd, } if (caps.size) { + info.flags |= VFIO_REGION_INFO_FLAG_CAPS; if (info.argsz < sizeof(info) + caps.size) { info.argsz = sizeof(info) + caps.size; info.cap_offset = 0; @@ -1426,6 +1527,7 @@ struct intel_gvt_mpt kvmgt_mpt = { .read_gpa = kvmgt_read_gpa, .write_gpa = kvmgt_write_gpa, .gfn_to_mfn = kvmgt_gfn_to_pfn, + .set_opregion = kvmgt_set_opregion, }; EXPORT_SYMBOL_GPL(kvmgt_mpt); diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h index c436e20ea59e..c99e7964731c 100644 --- a/drivers/gpu/drm/i915/gvt/mpt.h +++ b/drivers/gpu/drm/i915/gvt/mpt.h @@ -294,4 +294,19 @@ static inline int intel_gvt_hypervisor_set_trap_area( return intel_gvt_host.mpt->set_trap_area(vgpu->handle, start, end, map); } +/** + * intel_gvt_hypervisor_set_opregion - Set opregion for guest + * @vgpu: a vGPU + * + * Returns: + * Zero on success, negative error code if failed. + */ +static inline int intel_gvt_hypervisor_set_opregion(struct intel_vgpu *vgpu) +{ + if (!intel_gvt_host.mpt->set_opregion) + return 0; + + return intel_gvt_host.mpt->set_opregion(vgpu); +} + #endif /* _GVT_MPT_H_ */ diff --git a/drivers/gpu/drm/i915/gvt/opregion.c b/drivers/gpu/drm/i915/gvt/opregion.c index 36172f33bd51..8420d1fc3ddb 100644 --- a/drivers/gpu/drm/i915/gvt/opregion.c +++ b/drivers/gpu/drm/i915/gvt/opregion.c @@ -297,19 +297,41 @@ static int map_vgpu_opregion(struct intel_vgpu *vgpu, bool map) */ int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa) { - int i, ret; - /** - * Wins guest on Xengt will write this register twice: xen hvmloader and - * windows graphic driver. - */ - if (vgpu_opregion(vgpu)->mapped) - map_vgpu_opregion(vgpu, false); + int i, ret = 0; + unsigned long pfn; + + gvt_dbg_core("emulate opregion from kernel\n"); + + switch (intel_gvt_host.hypervisor_type) { + case INTEL_GVT_HYPERVISOR_KVM: + pfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gpa >> PAGE_SHIFT); + vgpu_opregion(vgpu)->va_gopregion = memremap(pfn << PAGE_SHIFT, + INTEL_GVT_OPREGION_SIZE, + MEMREMAP_WB); + if (!vgpu_opregion(vgpu)->va_gopregion) { + gvt_vgpu_err("failed to map guest opregion\n"); + ret = -EFAULT; + } + vgpu_opregion(vgpu)->mapped = true; + break; + case INTEL_GVT_HYPERVISOR_XEN: + /** + * Wins guest on Xengt will write this register twice: xen + * hvmloader and windows graphic driver. + */ + if (vgpu_opregion(vgpu)->mapped) + map_vgpu_opregion(vgpu, false); - for (i = 0; i < INTEL_GVT_OPREGION_PAGES; i++) - vgpu_opregion(vgpu)->gfn[i] = (gpa >> PAGE_SHIFT) + i; + for (i = 0; i < INTEL_GVT_OPREGION_PAGES; i++) + vgpu_opregion(vgpu)->gfn[i] = (gpa >> PAGE_SHIFT) + i; - ret = map_vgpu_opregion(vgpu, true); + ret = map_vgpu_opregion(vgpu, true); + break; + default: + ret = -EINVAL; + gvt_vgpu_err("not supported hypervisor\n"); + } return ret; } @@ -326,13 +348,20 @@ void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu) if (!vgpu_opregion(vgpu)->va) return; - if (vgpu_opregion(vgpu)->mapped) - map_vgpu_opregion(vgpu, false); - + if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_XEN) { + if (vgpu_opregion(vgpu)->mapped) + map_vgpu_opregion(vgpu, false); + } else if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_KVM) { + if (vgpu_opregion(vgpu)->mapped) { + memunmap(vgpu_opregion(vgpu)->va_gopregion); + vgpu_opregion(vgpu)->va_gopregion = NULL; + } + } free_pages((unsigned long)vgpu_opregion(vgpu)->va, - get_order(INTEL_GVT_OPREGION_SIZE)); + get_order(INTEL_GVT_OPREGION_SIZE)); vgpu_opregion(vgpu)->va = NULL; + } @@ -454,8 +483,21 @@ int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci) u32 *scic, *parm; u32 func, subfunc; - scic = vgpu_opregion(vgpu)->va + INTEL_GVT_OPREGION_SCIC; - parm = vgpu_opregion(vgpu)->va + INTEL_GVT_OPREGION_PARM; + switch (intel_gvt_host.hypervisor_type) { + case INTEL_GVT_HYPERVISOR_XEN: + scic = vgpu_opregion(vgpu)->va + INTEL_GVT_OPREGION_SCIC; + parm = vgpu_opregion(vgpu)->va + INTEL_GVT_OPREGION_PARM; + break; + case INTEL_GVT_HYPERVISOR_KVM: + scic = vgpu_opregion(vgpu)->va_gopregion + + INTEL_GVT_OPREGION_SCIC; + parm = vgpu_opregion(vgpu)->va_gopregion + + INTEL_GVT_OPREGION_PARM; + break; + default: + gvt_vgpu_err("not supported hypervisor\n"); + return -EINVAL; + } if (!(swsci & SWSCI_SCI_SELECT)) { gvt_vgpu_err("requesting SMI service\n"); diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index 2896aafc9520..dcdd72260cc9 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -390,6 +390,10 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt, if (ret) goto out_clean_sched_policy; + ret = intel_gvt_hypervisor_set_opregion(vgpu); + if (ret) + goto out_clean_sched_policy; + mutex_unlock(&gvt->lock); return vgpu; -- GitLab From 9f31d1063b434c2d54317461d78285b08538c01a Mon Sep 17 00:00:00 2001 From: Tina Zhang Date: Thu, 23 Nov 2017 16:26:32 +0800 Subject: [PATCH 0496/2547] drm/i915/gvt: Add framebuffer decoder support This patch is to introduce the framebuffer decoder which can decode guest OS's framebuffer information, including primary, cursor and sprite plane. v16: - rebase to 4.14.0-rc6. v14: - refine pixel format table. (Zhenyu) v9: - move drm format change to a separate patch. (Xiaoguang) v8: - fix a bug in decoding primary plane. (Tina) v7: - refine framebuffer decoder code. (Zhenyu) Signed-off-by: Tina Zhang Cc: Zhenyu Wang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/Makefile | 3 +- drivers/gpu/drm/i915/gvt/display.c | 2 +- drivers/gpu/drm/i915/gvt/display.h | 2 + drivers/gpu/drm/i915/gvt/fb_decoder.c | 507 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/gvt/fb_decoder.h | 169 +++++++++ drivers/gpu/drm/i915/gvt/gvt.h | 1 + 6 files changed, 682 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile index 7100240a4a81..54d70df96494 100644 --- a/drivers/gpu/drm/i915/gvt/Makefile +++ b/drivers/gpu/drm/i915/gvt/Makefile @@ -1,7 +1,8 @@ GVT_DIR := gvt GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \ interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \ - execlist.o scheduler.o sched_policy.o render.o cmd_parser.o debugfs.o + execlist.o scheduler.o sched_policy.o render.o cmd_parser.o debugfs.o \ + fb_decoder.o ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE)) diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 3c318439a659..fb7fdbacfe64 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -67,7 +67,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) return 1; } -static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) +int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; diff --git a/drivers/gpu/drm/i915/gvt/display.h b/drivers/gpu/drm/i915/gvt/display.h index d73de22102e2..b46b86892d58 100644 --- a/drivers/gpu/drm/i915/gvt/display.h +++ b/drivers/gpu/drm/i915/gvt/display.h @@ -179,4 +179,6 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution); void intel_vgpu_reset_display(struct intel_vgpu *vgpu); void intel_vgpu_clean_display(struct intel_vgpu *vgpu); +int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe); + #endif diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c new file mode 100644 index 000000000000..6c99c64d8e14 --- /dev/null +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -0,0 +1,507 @@ +/* + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Kevin Tian + * + * Contributors: + * Bing Niu + * Xu Han + * Ping Gao + * Xiaoguang Chen + * Yang Liu + * Tina Zhang + * + */ + +#include +#include "i915_drv.h" +#include "gvt.h" + +#define PRIMARY_FORMAT_NUM 16 +struct pixel_format { + int drm_format; /* Pixel format in DRM definition */ + int bpp; /* Bits per pixel, 0 indicates invalid */ + char *desc; /* The description */ +}; + +static struct pixel_format bdw_pixel_formats[] = { + {DRM_FORMAT_C8, 8, "8-bit Indexed"}, + {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"}, + {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"}, + {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"}, + + {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"}, + {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"}, + + /* non-supported format has bpp default to 0 */ + {0, 0, NULL}, +}; + +static struct pixel_format skl_pixel_formats[] = { + {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"}, + {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"}, + {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"}, + {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"}, + + {DRM_FORMAT_C8, 8, "8-bit Indexed"}, + {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"}, + {DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"}, + {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"}, + + {DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"}, + {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"}, + {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"}, + {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"}, + + /* non-supported format has bpp default to 0 */ + {0, 0, NULL}, +}; + +static int bdw_format_to_drm(int format) +{ + int bdw_pixel_formats_index = 6; + + switch (format) { + case DISPPLANE_8BPP: + bdw_pixel_formats_index = 0; + break; + case DISPPLANE_BGRX565: + bdw_pixel_formats_index = 1; + break; + case DISPPLANE_BGRX888: + bdw_pixel_formats_index = 2; + break; + case DISPPLANE_RGBX101010: + bdw_pixel_formats_index = 3; + break; + case DISPPLANE_BGRX101010: + bdw_pixel_formats_index = 4; + break; + case DISPPLANE_RGBX888: + bdw_pixel_formats_index = 5; + break; + + default: + break; + } + + return bdw_pixel_formats_index; +} + +static int skl_format_to_drm(int format, bool rgb_order, bool alpha, + int yuv_order) +{ + int skl_pixel_formats_index = 12; + + switch (format) { + case PLANE_CTL_FORMAT_INDEXED: + skl_pixel_formats_index = 4; + break; + case PLANE_CTL_FORMAT_RGB_565: + skl_pixel_formats_index = 5; + break; + case PLANE_CTL_FORMAT_XRGB_8888: + if (rgb_order) + skl_pixel_formats_index = alpha ? 6 : 7; + else + skl_pixel_formats_index = alpha ? 8 : 9; + break; + case PLANE_CTL_FORMAT_XRGB_2101010: + skl_pixel_formats_index = rgb_order ? 10 : 11; + break; + case PLANE_CTL_FORMAT_YUV422: + skl_pixel_formats_index = yuv_order >> 16; + if (skl_pixel_formats_index > 3) + return -EINVAL; + break; + + default: + break; + } + + return skl_pixel_formats_index; +} + +static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, + u32 tiled, int stride_mask, int bpp) +{ + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + + u32 stride_reg = vgpu_vreg(vgpu, DSPSTRIDE(pipe)) & stride_mask; + u32 stride = stride_reg; + + if (IS_SKYLAKE(dev_priv)) { + switch (tiled) { + case PLANE_CTL_TILED_LINEAR: + stride = stride_reg * 64; + break; + case PLANE_CTL_TILED_X: + stride = stride_reg * 512; + break; + case PLANE_CTL_TILED_Y: + stride = stride_reg * 128; + break; + case PLANE_CTL_TILED_YF: + if (bpp == 8) + stride = stride_reg * 64; + else if (bpp == 16 || bpp == 32 || bpp == 64) + stride = stride_reg * 128; + else + gvt_dbg_core("skl: unsupported bpp:%d\n", bpp); + break; + default: + gvt_dbg_core("skl: unsupported tile format:%x\n", + tiled); + } + } + + return stride; +} + +static int get_active_pipe(struct intel_vgpu *vgpu) +{ + int i; + + for (i = 0; i < I915_MAX_PIPES; i++) + if (pipe_is_enabled(vgpu, i)) + break; + + return i; +} + +/** + * intel_vgpu_decode_primary_plane - Decode primary plane + * @vgpu: input vgpu + * @plane: primary plane to save decoded info + * This function is called for decoding plane + * + * Returns: + * 0 on success, non-zero if failed. + */ +int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, + struct intel_vgpu_primary_plane_format *plane) +{ + u32 val, fmt; + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + int pipe; + + pipe = get_active_pipe(vgpu); + if (pipe >= I915_MAX_PIPES) + return -ENODEV; + + val = vgpu_vreg(vgpu, DSPCNTR(pipe)); + plane->enabled = !!(val & DISPLAY_PLANE_ENABLE); + if (!plane->enabled) + return -ENODEV; + + if (IS_SKYLAKE(dev_priv)) { + plane->tiled = (val & PLANE_CTL_TILED_MASK) >> + _PLANE_CTL_TILED_SHIFT; + fmt = skl_format_to_drm( + val & PLANE_CTL_FORMAT_MASK, + val & PLANE_CTL_ORDER_RGBX, + val & PLANE_CTL_ALPHA_MASK, + val & PLANE_CTL_YUV422_ORDER_MASK); + plane->bpp = skl_pixel_formats[fmt].bpp; + plane->drm_format = skl_pixel_formats[fmt].drm_format; + } else { + plane->tiled = !!(val & DISPPLANE_TILED); + fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK); + plane->bpp = bdw_pixel_formats[fmt].bpp; + plane->drm_format = bdw_pixel_formats[fmt].drm_format; + } + + if (!plane->bpp) { + gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); + return -EINVAL; + } + + plane->hw_format = fmt; + + plane->base = vgpu_vreg(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; + if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) { + gvt_vgpu_err("invalid gma address: %lx\n", + (unsigned long)plane->base); + return -EINVAL; + } + + plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); + if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { + gvt_vgpu_err("invalid gma address: %lx\n", + (unsigned long)plane->base); + return -EINVAL; + } + + plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10), + (IS_SKYLAKE(dev_priv)) ? (_PRI_PLANE_STRIDE_MASK >> 6) : + _PRI_PLANE_STRIDE_MASK, plane->bpp); + + plane->width = (vgpu_vreg(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> + _PIPE_H_SRCSZ_SHIFT; + plane->width += 1; + plane->height = (vgpu_vreg(vgpu, PIPESRC(pipe)) & + _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT; + plane->height += 1; /* raw height is one minus the real value */ + + val = vgpu_vreg(vgpu, DSPTILEOFF(pipe)); + plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >> + _PRI_PLANE_X_OFF_SHIFT; + plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >> + _PRI_PLANE_Y_OFF_SHIFT; + + return 0; +} + +#define CURSOR_FORMAT_NUM (1 << 6) +struct cursor_mode_format { + int drm_format; /* Pixel format in DRM definition */ + u8 bpp; /* Bits per pixel; 0 indicates invalid */ + u32 width; /* In pixel */ + u32 height; /* In lines */ + char *desc; /* The description */ +}; + +static struct cursor_mode_format cursor_pixel_formats[] = { + {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"}, + {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"}, + {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"}, + {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"}, + + /* non-supported format has bpp default to 0 */ + {0, 0, 0, 0, NULL}, +}; + +static int cursor_mode_to_drm(int mode) +{ + int cursor_pixel_formats_index = 4; + + switch (mode) { + case CURSOR_MODE_128_ARGB_AX: + cursor_pixel_formats_index = 0; + break; + case CURSOR_MODE_256_ARGB_AX: + cursor_pixel_formats_index = 1; + break; + case CURSOR_MODE_64_ARGB_AX: + cursor_pixel_formats_index = 2; + break; + case CURSOR_MODE_64_32B_AX: + cursor_pixel_formats_index = 3; + break; + + default: + break; + } + + return cursor_pixel_formats_index; +} + +/** + * intel_vgpu_decode_cursor_plane - Decode sprite plane + * @vgpu: input vgpu + * @plane: cursor plane to save decoded info + * This function is called for decoding plane + * + * Returns: + * 0 on success, non-zero if failed. + */ +int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, + struct intel_vgpu_cursor_plane_format *plane) +{ + u32 val, mode, index; + u32 alpha_plane, alpha_force; + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + int pipe; + + pipe = get_active_pipe(vgpu); + if (pipe >= I915_MAX_PIPES) + return -ENODEV; + + val = vgpu_vreg(vgpu, CURCNTR(pipe)); + mode = val & CURSOR_MODE; + plane->enabled = (mode != CURSOR_MODE_DISABLE); + if (!plane->enabled) + return -ENODEV; + + index = cursor_mode_to_drm(mode); + + if (!cursor_pixel_formats[index].bpp) { + gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode); + return -EINVAL; + } + plane->mode = mode; + plane->bpp = cursor_pixel_formats[index].bpp; + plane->drm_format = cursor_pixel_formats[index].drm_format; + plane->width = cursor_pixel_formats[index].width; + plane->height = cursor_pixel_formats[index].height; + + alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >> + _CURSOR_ALPHA_PLANE_SHIFT; + alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >> + _CURSOR_ALPHA_FORCE_SHIFT; + if (alpha_plane || alpha_force) + gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n", + alpha_plane, alpha_force); + + plane->base = vgpu_vreg(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; + if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) { + gvt_vgpu_err("invalid gma address: %lx\n", + (unsigned long)plane->base); + return -EINVAL; + } + + plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); + if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { + gvt_vgpu_err("invalid gma address: %lx\n", + (unsigned long)plane->base); + return -EINVAL; + } + + val = vgpu_vreg(vgpu, CURPOS(pipe)); + plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT; + plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT; + plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT; + plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT; + + return 0; +} + +#define SPRITE_FORMAT_NUM (1 << 3) + +static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = { + [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"}, + [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"}, + [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"}, + [0x4] = {DRM_FORMAT_AYUV, 32, + "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"}, +}; + +/** + * intel_vgpu_decode_sprite_plane - Decode sprite plane + * @vgpu: input vgpu + * @plane: sprite plane to save decoded info + * This function is called for decoding plane + * + * Returns: + * 0 on success, non-zero if failed. + */ +int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, + struct intel_vgpu_sprite_plane_format *plane) +{ + u32 val, fmt; + u32 color_order, yuv_order; + int drm_format; + int pipe; + + pipe = get_active_pipe(vgpu); + if (pipe >= I915_MAX_PIPES) + return -ENODEV; + + val = vgpu_vreg(vgpu, SPRCTL(pipe)); + plane->enabled = !!(val & SPRITE_ENABLE); + if (!plane->enabled) + return -ENODEV; + + plane->tiled = !!(val & SPRITE_TILED); + color_order = !!(val & SPRITE_RGB_ORDER_RGBX); + yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >> + _SPRITE_YUV_ORDER_SHIFT; + + fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT; + if (!sprite_pixel_formats[fmt].bpp) { + gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); + return -EINVAL; + } + plane->hw_format = fmt; + plane->bpp = sprite_pixel_formats[fmt].bpp; + drm_format = sprite_pixel_formats[fmt].drm_format; + + /* Order of RGB values in an RGBxxx buffer may be ordered RGB or + * BGR depending on the state of the color_order field + */ + if (!color_order) { + if (drm_format == DRM_FORMAT_XRGB2101010) + drm_format = DRM_FORMAT_XBGR2101010; + else if (drm_format == DRM_FORMAT_XRGB8888) + drm_format = DRM_FORMAT_XBGR8888; + } + + if (drm_format == DRM_FORMAT_YUV422) { + switch (yuv_order) { + case 0: + drm_format = DRM_FORMAT_YUYV; + break; + case 1: + drm_format = DRM_FORMAT_UYVY; + break; + case 2: + drm_format = DRM_FORMAT_YVYU; + break; + case 3: + drm_format = DRM_FORMAT_VYUY; + break; + default: + /* yuv_order has only 2 bits */ + break; + } + } + + plane->drm_format = drm_format; + + plane->base = vgpu_vreg(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; + if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) { + gvt_vgpu_err("invalid gma address: %lx\n", + (unsigned long)plane->base); + return -EINVAL; + } + + plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); + if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { + gvt_vgpu_err("invalid gma address: %lx\n", + (unsigned long)plane->base); + return -EINVAL; + } + + plane->stride = vgpu_vreg(vgpu, SPRSTRIDE(pipe)) & + _SPRITE_STRIDE_MASK; + + val = vgpu_vreg(vgpu, SPRSIZE(pipe)); + plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >> + _SPRITE_SIZE_HEIGHT_SHIFT; + plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >> + _SPRITE_SIZE_WIDTH_SHIFT; + plane->height += 1; /* raw height is one minus the real value */ + plane->width += 1; /* raw width is one minus the real value */ + + val = vgpu_vreg(vgpu, SPRPOS(pipe)); + plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT; + plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT; + + val = vgpu_vreg(vgpu, SPROFFSET(pipe)); + plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >> + _SPRITE_OFFSET_START_X_SHIFT; + plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >> + _SPRITE_OFFSET_START_Y_SHIFT; + + return 0; +} diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.h b/drivers/gpu/drm/i915/gvt/fb_decoder.h new file mode 100644 index 000000000000..cb055f3c81a2 --- /dev/null +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.h @@ -0,0 +1,169 @@ +/* + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Kevin Tian + * + * Contributors: + * Bing Niu + * Xu Han + * Ping Gao + * Xiaoguang Chen + * Yang Liu + * Tina Zhang + * + */ + +#ifndef _GVT_FB_DECODER_H_ +#define _GVT_FB_DECODER_H_ + +#define _PLANE_CTL_FORMAT_SHIFT 24 +#define _PLANE_CTL_TILED_SHIFT 10 +#define _PIPE_V_SRCSZ_SHIFT 0 +#define _PIPE_V_SRCSZ_MASK (0xfff << _PIPE_V_SRCSZ_SHIFT) +#define _PIPE_H_SRCSZ_SHIFT 16 +#define _PIPE_H_SRCSZ_MASK (0x1fff << _PIPE_H_SRCSZ_SHIFT) + +#define _PRI_PLANE_FMT_SHIFT 26 +#define _PRI_PLANE_STRIDE_MASK (0x3ff << 6) +#define _PRI_PLANE_X_OFF_SHIFT 0 +#define _PRI_PLANE_X_OFF_MASK (0x1fff << _PRI_PLANE_X_OFF_SHIFT) +#define _PRI_PLANE_Y_OFF_SHIFT 16 +#define _PRI_PLANE_Y_OFF_MASK (0xfff << _PRI_PLANE_Y_OFF_SHIFT) + +#define _CURSOR_MODE 0x3f +#define _CURSOR_ALPHA_FORCE_SHIFT 8 +#define _CURSOR_ALPHA_FORCE_MASK (0x3 << _CURSOR_ALPHA_FORCE_SHIFT) +#define _CURSOR_ALPHA_PLANE_SHIFT 10 +#define _CURSOR_ALPHA_PLANE_MASK (0x3 << _CURSOR_ALPHA_PLANE_SHIFT) +#define _CURSOR_POS_X_SHIFT 0 +#define _CURSOR_POS_X_MASK (0x1fff << _CURSOR_POS_X_SHIFT) +#define _CURSOR_SIGN_X_SHIFT 15 +#define _CURSOR_SIGN_X_MASK (1 << _CURSOR_SIGN_X_SHIFT) +#define _CURSOR_POS_Y_SHIFT 16 +#define _CURSOR_POS_Y_MASK (0xfff << _CURSOR_POS_Y_SHIFT) +#define _CURSOR_SIGN_Y_SHIFT 31 +#define _CURSOR_SIGN_Y_MASK (1 << _CURSOR_SIGN_Y_SHIFT) + +#define _SPRITE_FMT_SHIFT 25 +#define _SPRITE_COLOR_ORDER_SHIFT 20 +#define _SPRITE_YUV_ORDER_SHIFT 16 +#define _SPRITE_STRIDE_SHIFT 6 +#define _SPRITE_STRIDE_MASK (0x1ff << _SPRITE_STRIDE_SHIFT) +#define _SPRITE_SIZE_WIDTH_SHIFT 0 +#define _SPRITE_SIZE_HEIGHT_SHIFT 16 +#define _SPRITE_SIZE_WIDTH_MASK (0x1fff << _SPRITE_SIZE_WIDTH_SHIFT) +#define _SPRITE_SIZE_HEIGHT_MASK (0xfff << _SPRITE_SIZE_HEIGHT_SHIFT) +#define _SPRITE_POS_X_SHIFT 0 +#define _SPRITE_POS_Y_SHIFT 16 +#define _SPRITE_POS_X_MASK (0x1fff << _SPRITE_POS_X_SHIFT) +#define _SPRITE_POS_Y_MASK (0xfff << _SPRITE_POS_Y_SHIFT) +#define _SPRITE_OFFSET_START_X_SHIFT 0 +#define _SPRITE_OFFSET_START_Y_SHIFT 16 +#define _SPRITE_OFFSET_START_X_MASK (0x1fff << _SPRITE_OFFSET_START_X_SHIFT) +#define _SPRITE_OFFSET_START_Y_MASK (0xfff << _SPRITE_OFFSET_START_Y_SHIFT) + +enum GVT_FB_EVENT { + FB_MODE_SET_START = 1, + FB_MODE_SET_END, + FB_DISPLAY_FLIP, +}; + +enum DDI_PORT { + DDI_PORT_NONE = 0, + DDI_PORT_B = 1, + DDI_PORT_C = 2, + DDI_PORT_D = 3, + DDI_PORT_E = 4 +}; + +struct intel_gvt; + +/* color space conversion and gamma correction are not included */ +struct intel_vgpu_primary_plane_format { + u8 enabled; /* plane is enabled */ + u8 tiled; /* X-tiled */ + u8 bpp; /* bits per pixel */ + u32 hw_format; /* format field in the PRI_CTL register */ + u32 drm_format; /* format in DRM definition */ + u32 base; /* framebuffer base in graphics memory */ + u64 base_gpa; + u32 x_offset; /* in pixels */ + u32 y_offset; /* in lines */ + u32 width; /* in pixels */ + u32 height; /* in lines */ + u32 stride; /* in bytes */ +}; + +struct intel_vgpu_sprite_plane_format { + u8 enabled; /* plane is enabled */ + u8 tiled; /* X-tiled */ + u8 bpp; /* bits per pixel */ + u32 hw_format; /* format field in the SPR_CTL register */ + u32 drm_format; /* format in DRM definition */ + u32 base; /* sprite base in graphics memory */ + u64 base_gpa; + u32 x_pos; /* in pixels */ + u32 y_pos; /* in lines */ + u32 x_offset; /* in pixels */ + u32 y_offset; /* in lines */ + u32 width; /* in pixels */ + u32 height; /* in lines */ + u32 stride; /* in bytes */ +}; + +struct intel_vgpu_cursor_plane_format { + u8 enabled; + u8 mode; /* cursor mode select */ + u8 bpp; /* bits per pixel */ + u32 drm_format; /* format in DRM definition */ + u32 base; /* cursor base in graphics memory */ + u64 base_gpa; + u32 x_pos; /* in pixels */ + u32 y_pos; /* in lines */ + u8 x_sign; /* X Position Sign */ + u8 y_sign; /* Y Position Sign */ + u32 width; /* in pixels */ + u32 height; /* in lines */ + u32 x_hot; /* in pixels */ + u32 y_hot; /* in pixels */ +}; + +struct intel_vgpu_pipe_format { + struct intel_vgpu_primary_plane_format primary; + struct intel_vgpu_sprite_plane_format sprite; + struct intel_vgpu_cursor_plane_format cursor; + enum DDI_PORT ddi_port; /* the DDI port that pipe is connected to */ +}; + +struct intel_vgpu_fb_format { + struct intel_vgpu_pipe_format pipes[I915_MAX_PIPES]; +}; + +int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, + struct intel_vgpu_primary_plane_format *plane); +int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, + struct intel_vgpu_cursor_plane_format *plane); +int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, + struct intel_vgpu_sprite_plane_format *plane); + +#endif diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index f3999f251cd5..357d458cded0 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -46,6 +46,7 @@ #include "sched_policy.h" #include "render.h" #include "cmd_parser.h" +#include "fb_decoder.h" #define GVT_MAX_VGPU 8 -- GitLab From e20eaa2382e7888a4e06ccb015c476a6fb1fda0c Mon Sep 17 00:00:00 2001 From: Tina Zhang Date: Thu, 23 Nov 2017 16:26:35 +0800 Subject: [PATCH 0497/2547] vfio: ABI for mdev display dma-buf operation Add VFIO_DEVICE_QUERY_GFX_PLANE ioctl command to let user query and get a plane and its information. So far, two types of buffers are supported: buffers based on dma-buf and buffers based on region. This ioctl can be invoked with: 1) Either DMABUF or REGION flag. Vendor driver returns a plane_info successfully only when the specific kind of buffer is supported. 2) Flag PROBE. And at the same time either DMABUF or REGION must be set, so that vendor driver returns success only when the specific kind of buffer is supported. Add VFIO_DEVICE_GET_GFX_DMABUF ioctl command to let user get a specific dma-buf fd of an exposed MDEV buffer provided by dmabuf_id which was returned in VFIO_DEVICE_QUERY_GFX_PLANE ioctl command. The life cycle of an exposed MDEV buffer is handled by userspace and tracked by kernel space. The returned dmabuf_id in struct vfio_device_ query_gfx_plane can be a new id of a new exposed buffer or an old id of a re-exported buffer. Host user can check the value of dmabuf_id to see if it needs to create new resources according to the new exposed buffer or just re-use the existing resource related to the old buffer. v18: - update comments for VFIO_DEVICE_GET_GFX_DMABUF. (Alex) v17: - modify VFIO_DEVICE_GET_GFX_DMABUF interface. (Alex) v16: - add x_hot and y_hot fields. (Gerd) - add comments for VFIO_DEVICE_GET_GFX_DMABUF. (Alex) - rebase to 4.14.0-rc6. v15: - add a ioctl to get a dmabuf for a given dmabuf id. (Gerd) v14: - add PROBE, DMABUF and REGION flags. (Alex) v12: - add drm_format_mod back. (Gerd and Zhenyu) - add region_index. (Gerd) v11: - rename plane_type to drm_plane_type. (Gerd) - move fields of vfio_device_query_gfx_plane to vfio_device_gfx_plane_info. (Gerd) - remove drm_format_mod, start fields. (Daniel) - remove plane_id. v10: - refine the ABI API VFIO_DEVICE_QUERY_GFX_PLANE. (Alex) (Gerd) v3: - add a field gvt_plane_info in the drm_i915_gem_obj structure to save the decoded plane information to avoid look up while need the plane info. (Gerd) Signed-off-by: Tina Zhang Reviewed-by: Gerd Hoffmann Reviewed-by: Kirti Wankhede Acked-by: Alex Williamson Cc: Daniel Vetter Signed-off-by: Zhenyu Wang --- include/uapi/linux/vfio.h | 62 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index ae461050661a..5c1cca2ba04d 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -502,6 +502,68 @@ struct vfio_pci_hot_reset { #define VFIO_DEVICE_PCI_HOT_RESET _IO(VFIO_TYPE, VFIO_BASE + 13) +/** + * VFIO_DEVICE_QUERY_GFX_PLANE - _IOW(VFIO_TYPE, VFIO_BASE + 14, + * struct vfio_device_query_gfx_plane) + * + * Set the drm_plane_type and flags, then retrieve the gfx plane info. + * + * flags supported: + * - VFIO_GFX_PLANE_TYPE_PROBE and VFIO_GFX_PLANE_TYPE_DMABUF are set + * to ask if the mdev supports dma-buf. 0 on support, -EINVAL on no + * support for dma-buf. + * - VFIO_GFX_PLANE_TYPE_PROBE and VFIO_GFX_PLANE_TYPE_REGION are set + * to ask if the mdev supports region. 0 on support, -EINVAL on no + * support for region. + * - VFIO_GFX_PLANE_TYPE_DMABUF or VFIO_GFX_PLANE_TYPE_REGION is set + * with each call to query the plane info. + * - Others are invalid and return -EINVAL. + * + * Note: + * 1. Plane could be disabled by guest. In that case, success will be + * returned with zero-initialized drm_format, size, width and height + * fields. + * 2. x_hot/y_hot is set to 0xFFFFFFFF if no hotspot information available + * + * Return: 0 on success, -errno on other failure. + */ +struct vfio_device_gfx_plane_info { + __u32 argsz; + __u32 flags; +#define VFIO_GFX_PLANE_TYPE_PROBE (1 << 0) +#define VFIO_GFX_PLANE_TYPE_DMABUF (1 << 1) +#define VFIO_GFX_PLANE_TYPE_REGION (1 << 2) + /* in */ + __u32 drm_plane_type; /* type of plane: DRM_PLANE_TYPE_* */ + /* out */ + __u32 drm_format; /* drm format of plane */ + __u64 drm_format_mod; /* tiled mode */ + __u32 width; /* width of plane */ + __u32 height; /* height of plane */ + __u32 stride; /* stride of plane */ + __u32 size; /* size of plane in bytes, align on page*/ + __u32 x_pos; /* horizontal position of cursor plane */ + __u32 y_pos; /* vertical position of cursor plane*/ + __u32 x_hot; /* horizontal position of cursor hotspot */ + __u32 y_hot; /* vertical position of cursor hotspot */ + union { + __u32 region_index; /* region index */ + __u32 dmabuf_id; /* dma-buf id */ + }; +}; + +#define VFIO_DEVICE_QUERY_GFX_PLANE _IO(VFIO_TYPE, VFIO_BASE + 14) + +/** + * VFIO_DEVICE_GET_GFX_DMABUF - _IOW(VFIO_TYPE, VFIO_BASE + 15, __u32) + * + * Return a new dma-buf file descriptor for an exposed guest framebuffer + * described by the provided dmabuf_id. The dmabuf_id is returned from VFIO_ + * DEVICE_QUERY_GFX_PLANE as a token of the exposed guest framebuffer. + */ + +#define VFIO_DEVICE_GET_GFX_DMABUF _IO(VFIO_TYPE, VFIO_BASE + 15) + /* -------- API for Type1 VFIO IOMMU -------- */ /** -- GitLab From e546e281d33d1fc275651aa06f0659045db67e68 Mon Sep 17 00:00:00 2001 From: Tina Zhang Date: Thu, 23 Nov 2017 16:26:36 +0800 Subject: [PATCH 0498/2547] drm/i915/gvt: Dmabuf support for GVT-g This patch introduces a guest's framebuffer sharing mechanism based on dma-buf subsystem. With this sharing mechanism, guest's framebuffer can be shared between guest VM and host. v17: - modify VFIO_DEVICE_GET_GFX_DMABUF interface. (Alex) v16: - add x_hot and y_hot. (Gerd) - add flag validation for VFIO_DEVICE_GET_GFX_DMABUF. (Alex) - rebase 4.14.0-rc6. v15: - add VFIO_DEVICE_GET_GFX_DMABUF ABI. (Gerd) - add intel_vgpu_dmabuf_cleanup() to clean up the vGPU's dmabuf. (Gerd) v14: - add PROBE, DMABUF and REGION flags. (Alex) v12: - refine the lifecycle of dmabuf. v9: - remove dma-buf management. (Alex) - track the dma-buf create and release in kernel mode. (Gerd) (Daniel) v8: - refine the dma-buf ioctl definition.(Alex) - add a lock to protect the dmabuf list. (Alex) v7: - release dma-buf related allocations in dma-buf's associated release function. (Alex) - refine ioctl interface for querying plane info or create dma-buf. (Alex) v6: - align the dma-buf life cycle with the vfio device. (Alex) - add the dma-buf related operations in a separate patch. (Gerd) - i915 related changes. (Chris) v5: - fix bug while checking whether the gem obj is gvt's dma-buf when user change caching mode or domains. Add a helper function to do it. (Xiaoguang) - add definition for the query plane and create dma-buf. (Xiaoguang) v4: - fix bug while checking whether the gem obj is gvt's dma-buf when set caching mode or doamins. (Xiaoguang) v3: - declare a new flag I915_GEM_OBJECT_IS_GVT_DMABUF in drm_i915_gem_object to represent the gem obj for gvt's dma-buf. The tiling mode, caching mode and domains can not be changed for this kind of gem object. (Alex) - change dma-buf related information to be more generic. So other vendor can use the same interface. (Alex) v2: - create a management fd for dma-buf operations. (Alex) - alloc gem object's backing storage in gem obj's get_pages() callback. (Chris) Signed-off-by: Tina Zhang Cc: Alex Williamson Cc: Chris Wilson Cc: Daniel Vetter Cc: Gerd Hoffmann Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/Makefile | 2 +- drivers/gpu/drm/i915/gvt/dmabuf.c | 523 +++++++++++++++++++++++++ drivers/gpu/drm/i915/gvt/dmabuf.h | 67 ++++ drivers/gpu/drm/i915/gvt/gvt.c | 2 + drivers/gpu/drm/i915/gvt/gvt.h | 11 + drivers/gpu/drm/i915/gvt/hypercall.h | 2 + drivers/gpu/drm/i915/gvt/kvmgt.c | 53 +++ drivers/gpu/drm/i915/gvt/mpt.h | 30 ++ drivers/gpu/drm/i915/gvt/vgpu.c | 5 +- drivers/gpu/drm/i915/i915_gem_object.h | 2 + 10 files changed, 695 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile index 54d70df96494..cae06c1dcdcd 100644 --- a/drivers/gpu/drm/i915/gvt/Makefile +++ b/drivers/gpu/drm/i915/gvt/Makefile @@ -2,7 +2,7 @@ GVT_DIR := gvt GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \ interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \ execlist.o scheduler.o sched_policy.o render.o cmd_parser.o debugfs.o \ - fb_decoder.o + fb_decoder.o dmabuf.o ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE)) diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c new file mode 100644 index 000000000000..190710c8d3e5 --- /dev/null +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c @@ -0,0 +1,523 @@ +/* + * Copyright 2017 Intel Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Zhiyuan Lv + * + * Contributors: + * Xiaoguang Chen + * Tina Zhang + */ + +#include +#include +#include + +#include "i915_drv.h" +#include "gvt.h" + +#define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12)) + +static int vgpu_gem_get_pages( + struct drm_i915_gem_object *obj) +{ + struct drm_i915_private *dev_priv = to_i915(obj->base.dev); + struct sg_table *st; + struct scatterlist *sg; + int i, ret; + gen8_pte_t __iomem *gtt_entries; + struct intel_vgpu_fb_info *fb_info; + + fb_info = (struct intel_vgpu_fb_info *)obj->gvt_info; + if (WARN_ON(!fb_info)) + return -ENODEV; + + st = kmalloc(sizeof(*st), GFP_KERNEL); + if (unlikely(!st)) + return -ENOMEM; + + ret = sg_alloc_table(st, fb_info->size, GFP_KERNEL); + if (ret) { + kfree(st); + return ret; + } + gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + + (fb_info->start >> PAGE_SHIFT); + for_each_sg(st->sgl, sg, fb_info->size, i) { + sg->offset = 0; + sg->length = PAGE_SIZE; + sg_dma_address(sg) = + GEN8_DECODE_PTE(readq(>t_entries[i])); + sg_dma_len(sg) = PAGE_SIZE; + } + + __i915_gem_object_set_pages(obj, st, PAGE_SIZE); + + return 0; +} + +static void vgpu_gem_put_pages(struct drm_i915_gem_object *obj, + struct sg_table *pages) +{ + sg_free_table(pages); + kfree(pages); +} + +static void dmabuf_gem_object_free(struct kref *kref) +{ + struct intel_vgpu_dmabuf_obj *obj = + container_of(kref, struct intel_vgpu_dmabuf_obj, kref); + struct intel_vgpu *vgpu = obj->vgpu; + struct list_head *pos; + + struct intel_vgpu_dmabuf_obj *dmabuf_obj; + + list_for_each(pos, &vgpu->dmabuf_obj_list_head) { + dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj, + list); + if (dmabuf_obj == obj) { + idr_remove(&vgpu->object_idr, dmabuf_obj->dmabuf_id); + kfree(dmabuf_obj->info); + kfree(dmabuf_obj); + list_del(pos); + break; + } + } +} + + +static inline void dmabuf_obj_get(struct intel_vgpu_dmabuf_obj *obj) +{ + kref_get(&obj->kref); +} + +static inline void dmabuf_obj_put(struct intel_vgpu_dmabuf_obj *obj) +{ + kref_put(&obj->kref, dmabuf_gem_object_free); +} + +static void vgpu_gem_release(struct drm_i915_gem_object *gem_obj) +{ + + struct intel_vgpu_fb_info *fb_info = gem_obj->gvt_info; + struct intel_vgpu_dmabuf_obj *obj = fb_info->obj; + struct intel_vgpu *vgpu = obj->vgpu; + + mutex_lock(&vgpu->dmabuf_lock); + gem_obj->base.dma_buf = NULL; + dmabuf_obj_put(obj); + intel_gvt_hypervisor_put_vfio_device(vgpu); + mutex_unlock(&vgpu->dmabuf_lock); +} + +static const struct drm_i915_gem_object_ops intel_vgpu_gem_ops = { + .flags = I915_GEM_OBJECT_IS_PROXY, + .get_pages = vgpu_gem_get_pages, + .put_pages = vgpu_gem_put_pages, + .release = vgpu_gem_release, +}; + +static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, + struct intel_vgpu_fb_info *info) +{ + struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_gem_object *obj; + + obj = i915_gem_object_alloc(dev_priv); + if (obj == NULL) + return NULL; + + drm_gem_private_object_init(dev, &obj->base, + info->size << PAGE_SHIFT); + i915_gem_object_init(obj, &intel_vgpu_gem_ops); + + obj->base.read_domains = I915_GEM_DOMAIN_GTT; + obj->base.write_domain = 0; + if (IS_SKYLAKE(dev_priv)) { + unsigned int tiling_mode = 0; + unsigned int stride = 0; + + switch (info->drm_format_mod << 10) { + case PLANE_CTL_TILED_LINEAR: + tiling_mode = I915_TILING_NONE; + break; + case PLANE_CTL_TILED_X: + tiling_mode = I915_TILING_X; + stride = info->stride; + break; + case PLANE_CTL_TILED_Y: + tiling_mode = I915_TILING_Y; + stride = info->stride; + break; + default: + gvt_dbg_core("not supported tiling mode\n"); + } + obj->tiling_and_stride = tiling_mode | stride; + } else { + obj->tiling_and_stride = info->drm_format_mod ? + I915_TILING_X : 0; + } + + return obj; +} + +static int vgpu_get_plane_info(struct drm_device *dev, + struct intel_vgpu *vgpu, + struct intel_vgpu_fb_info *info, + int plane_id) +{ + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_vgpu_primary_plane_format p; + struct intel_vgpu_cursor_plane_format c; + int ret; + + if (plane_id == DRM_PLANE_TYPE_PRIMARY) { + ret = intel_vgpu_decode_primary_plane(vgpu, &p); + if (ret) + return ret; + info->start = p.base; + info->start_gpa = p.base_gpa; + info->width = p.width; + info->height = p.height; + info->stride = p.stride; + info->drm_format = p.drm_format; + info->drm_format_mod = p.tiled; + info->size = (((p.stride * p.height * p.bpp) / 8) + + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + } else if (plane_id == DRM_PLANE_TYPE_CURSOR) { + ret = intel_vgpu_decode_cursor_plane(vgpu, &c); + if (ret) + return ret; + info->start = c.base; + info->start_gpa = c.base_gpa; + info->width = c.width; + info->height = c.height; + info->stride = c.width * (c.bpp / 8); + info->drm_format = c.drm_format; + info->drm_format_mod = 0; + info->x_pos = c.x_pos; + info->y_pos = c.y_pos; + + /* The invalid cursor hotspot value is delivered to host + * until we find a way to get the cursor hotspot info of + * guest OS. + */ + info->x_hot = UINT_MAX; + info->y_hot = UINT_MAX; + info->size = (((info->stride * c.height * c.bpp) / 8) + + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + } else { + gvt_vgpu_err("invalid plane id:%d\n", plane_id); + return -EINVAL; + } + + if (info->size == 0) { + gvt_vgpu_err("fb size is zero\n"); + return -EINVAL; + } + + if (info->start & (PAGE_SIZE - 1)) { + gvt_vgpu_err("Not aligned fb address:0x%llx\n", info->start); + return -EFAULT; + } + if (((info->start >> PAGE_SHIFT) + info->size) > + ggtt_total_entries(&dev_priv->ggtt)) { + gvt_vgpu_err("Invalid GTT offset or size\n"); + return -EFAULT; + } + + if (!intel_gvt_ggtt_validate_range(vgpu, info->start, info->size)) { + gvt_vgpu_err("invalid gma addr\n"); + return -EFAULT; + } + + return 0; +} + +static struct intel_vgpu_dmabuf_obj * +pick_dmabuf_by_info(struct intel_vgpu *vgpu, + struct intel_vgpu_fb_info *latest_info) +{ + struct list_head *pos; + struct intel_vgpu_fb_info *fb_info; + struct intel_vgpu_dmabuf_obj *dmabuf_obj = NULL; + struct intel_vgpu_dmabuf_obj *ret = NULL; + + list_for_each(pos, &vgpu->dmabuf_obj_list_head) { + dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj, + list); + if ((dmabuf_obj == NULL) || + (dmabuf_obj->info == NULL)) + continue; + + fb_info = (struct intel_vgpu_fb_info *)dmabuf_obj->info; + if ((fb_info->start == latest_info->start) && + (fb_info->start_gpa == latest_info->start_gpa) && + (fb_info->size == latest_info->size) && + (fb_info->drm_format_mod == latest_info->drm_format_mod) && + (fb_info->drm_format == latest_info->drm_format) && + (fb_info->width == latest_info->width) && + (fb_info->height == latest_info->height)) { + ret = dmabuf_obj; + break; + } + } + + return ret; +} + +static struct intel_vgpu_dmabuf_obj * +pick_dmabuf_by_num(struct intel_vgpu *vgpu, u32 id) +{ + struct list_head *pos; + struct intel_vgpu_dmabuf_obj *dmabuf_obj = NULL; + struct intel_vgpu_dmabuf_obj *ret = NULL; + + list_for_each(pos, &vgpu->dmabuf_obj_list_head) { + dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj, + list); + if (!dmabuf_obj) + continue; + + if (dmabuf_obj->dmabuf_id == id) { + ret = dmabuf_obj; + break; + } + } + + return ret; +} + +static void update_fb_info(struct vfio_device_gfx_plane_info *gvt_dmabuf, + struct intel_vgpu_fb_info *fb_info) +{ + gvt_dmabuf->drm_format = fb_info->drm_format; + gvt_dmabuf->width = fb_info->width; + gvt_dmabuf->height = fb_info->height; + gvt_dmabuf->stride = fb_info->stride; + gvt_dmabuf->size = fb_info->size; + gvt_dmabuf->x_pos = fb_info->x_pos; + gvt_dmabuf->y_pos = fb_info->y_pos; + gvt_dmabuf->x_hot = fb_info->x_hot; + gvt_dmabuf->y_hot = fb_info->y_hot; +} + +int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args) +{ + struct drm_device *dev = &vgpu->gvt->dev_priv->drm; + struct vfio_device_gfx_plane_info *gfx_plane_info = args; + struct intel_vgpu_dmabuf_obj *dmabuf_obj; + struct intel_vgpu_fb_info fb_info; + int ret = 0; + + if (gfx_plane_info->flags == (VFIO_GFX_PLANE_TYPE_DMABUF | + VFIO_GFX_PLANE_TYPE_PROBE)) + return ret; + else if ((gfx_plane_info->flags & ~VFIO_GFX_PLANE_TYPE_DMABUF) || + (!gfx_plane_info->flags)) + return -EINVAL; + + ret = vgpu_get_plane_info(dev, vgpu, &fb_info, + gfx_plane_info->drm_plane_type); + if (ret != 0) + goto out; + + mutex_lock(&vgpu->dmabuf_lock); + /* If exists, pick up the exposed dmabuf_obj */ + dmabuf_obj = pick_dmabuf_by_info(vgpu, &fb_info); + if (dmabuf_obj) { + update_fb_info(gfx_plane_info, &fb_info); + gfx_plane_info->dmabuf_id = dmabuf_obj->dmabuf_id; + + /* This buffer may be released between query_plane ioctl and + * get_dmabuf ioctl. Add the refcount to make sure it won't + * be released between the two ioctls. + */ + if (!dmabuf_obj->initref) { + dmabuf_obj->initref = true; + dmabuf_obj_get(dmabuf_obj); + } + ret = 0; + gvt_dbg_dpy("vgpu%d: re-use dmabuf_obj ref %d, id %d\n", + vgpu->id, kref_read(&dmabuf_obj->kref), + gfx_plane_info->dmabuf_id); + mutex_unlock(&vgpu->dmabuf_lock); + goto out; + } + + mutex_unlock(&vgpu->dmabuf_lock); + + /* Need to allocate a new one*/ + dmabuf_obj = kmalloc(sizeof(struct intel_vgpu_dmabuf_obj), GFP_KERNEL); + if (unlikely(!dmabuf_obj)) { + gvt_vgpu_err("alloc dmabuf_obj failed\n"); + ret = -ENOMEM; + goto out; + } + + dmabuf_obj->info = kmalloc(sizeof(struct intel_vgpu_fb_info), + GFP_KERNEL); + if (unlikely(!dmabuf_obj->info)) { + gvt_vgpu_err("allocate intel vgpu fb info failed\n"); + ret = -ENOMEM; + goto out_free_dmabuf; + } + memcpy(dmabuf_obj->info, &fb_info, sizeof(struct intel_vgpu_fb_info)); + + ((struct intel_vgpu_fb_info *)dmabuf_obj->info)->obj = dmabuf_obj; + + dmabuf_obj->vgpu = vgpu; + + ret = idr_alloc(&vgpu->object_idr, dmabuf_obj, 1, 0, GFP_NOWAIT); + if (ret < 0) + goto out_free_info; + gfx_plane_info->dmabuf_id = ret; + dmabuf_obj->dmabuf_id = ret; + + dmabuf_obj->initref = true; + + kref_init(&dmabuf_obj->kref); + + mutex_lock(&vgpu->dmabuf_lock); + if (intel_gvt_hypervisor_get_vfio_device(vgpu)) { + gvt_vgpu_err("get vfio device failed\n"); + mutex_unlock(&vgpu->dmabuf_lock); + goto out_free_info; + } + mutex_unlock(&vgpu->dmabuf_lock); + + update_fb_info(gfx_plane_info, &fb_info); + + INIT_LIST_HEAD(&dmabuf_obj->list); + mutex_lock(&vgpu->dmabuf_lock); + list_add_tail(&dmabuf_obj->list, &vgpu->dmabuf_obj_list_head); + mutex_unlock(&vgpu->dmabuf_lock); + + gvt_dbg_dpy("vgpu%d: %s new dmabuf_obj ref %d, id %d\n", vgpu->id, + __func__, kref_read(&dmabuf_obj->kref), ret); + + return 0; + +out_free_info: + kfree(dmabuf_obj->info); +out_free_dmabuf: + kfree(dmabuf_obj); +out: + /* ENODEV means plane isn't ready, which might be a normal case. */ + return (ret == -ENODEV) ? 0 : ret; +} + +/* To associate an exposed dmabuf with the dmabuf_obj */ +int intel_vgpu_get_dmabuf(struct intel_vgpu *vgpu, unsigned int dmabuf_id) +{ + struct drm_device *dev = &vgpu->gvt->dev_priv->drm; + struct intel_vgpu_dmabuf_obj *dmabuf_obj; + struct drm_i915_gem_object *obj; + struct dma_buf *dmabuf; + int dmabuf_fd; + int ret = 0; + + mutex_lock(&vgpu->dmabuf_lock); + + dmabuf_obj = pick_dmabuf_by_num(vgpu, dmabuf_id); + if (dmabuf_obj == NULL) { + gvt_vgpu_err("invalid dmabuf id:%d\n", dmabuf_id); + ret = -EINVAL; + goto out; + } + + obj = vgpu_create_gem(dev, dmabuf_obj->info); + if (obj == NULL) { + gvt_vgpu_err("create gvt gem obj failed:%d\n", vgpu->id); + ret = -ENOMEM; + goto out; + } + + obj->gvt_info = dmabuf_obj->info; + + dmabuf = i915_gem_prime_export(dev, &obj->base, DRM_CLOEXEC | DRM_RDWR); + if (IS_ERR(dmabuf)) { + gvt_vgpu_err("export dma-buf failed\n"); + ret = PTR_ERR(dmabuf); + goto out_free_gem; + } + obj->base.dma_buf = dmabuf; + + i915_gem_object_put(obj); + + ret = dma_buf_fd(dmabuf, DRM_CLOEXEC | DRM_RDWR); + if (ret < 0) { + gvt_vgpu_err("create dma-buf fd failed ret:%d\n", ret); + goto out_free_dmabuf; + } + dmabuf_fd = ret; + + if (intel_gvt_hypervisor_get_vfio_device(vgpu)) { + gvt_vgpu_err("get vfio device failed\n"); + put_unused_fd(ret); + goto out_free_dmabuf; + } + + dmabuf_obj_get(dmabuf_obj); + + if (dmabuf_obj->initref) { + dmabuf_obj->initref = false; + dmabuf_obj_put(dmabuf_obj); + } + + mutex_unlock(&vgpu->dmabuf_lock); + + gvt_dbg_dpy("vgpu%d: dmabuf:%d, dmabuf ref %d, fd:%d\n" + " file count: %ld, GEM ref: %d\n", + vgpu->id, dmabuf_obj->dmabuf_id, + kref_read(&dmabuf_obj->kref), + dmabuf_fd, + file_count(dmabuf->file), + kref_read(&obj->base.refcount)); + + return dmabuf_fd; + +out_free_dmabuf: + dma_buf_put(dmabuf); +out_free_gem: + i915_gem_object_put(obj); +out: + mutex_unlock(&vgpu->dmabuf_lock); + return ret; +} + +void intel_vgpu_dmabuf_cleanup(struct intel_vgpu *vgpu) +{ + struct list_head *pos, *n; + struct intel_vgpu_dmabuf_obj *dmabuf_obj; + + mutex_lock(&vgpu->dmabuf_lock); + list_for_each_safe(pos, n, &vgpu->dmabuf_obj_list_head) { + dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj, + list); + if (dmabuf_obj->initref) { + dmabuf_obj->initref = false; + dmabuf_obj_put(dmabuf_obj); + } + } + mutex_unlock(&vgpu->dmabuf_lock); +} diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.h b/drivers/gpu/drm/i915/gvt/dmabuf.h new file mode 100644 index 000000000000..5f8f03fb1d1b --- /dev/null +++ b/drivers/gpu/drm/i915/gvt/dmabuf.h @@ -0,0 +1,67 @@ +/* + * Copyright(c) 2017 Intel Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Zhiyuan Lv + * + * Contributors: + * Xiaoguang Chen + * Tina Zhang + */ + +#ifndef _GVT_DMABUF_H_ +#define _GVT_DMABUF_H_ +#include + +struct intel_vgpu_fb_info { + __u64 start; + __u64 start_gpa; + __u64 drm_format_mod; + __u32 drm_format; /* drm format of plane */ + __u32 width; /* width of plane */ + __u32 height; /* height of plane */ + __u32 stride; /* stride of plane */ + __u32 size; /* size of plane in bytes, align on page */ + __u32 x_pos; /* horizontal position of cursor plane */ + __u32 y_pos; /* vertical position of cursor plane */ + __u32 x_hot; /* horizontal position of cursor hotspot */ + __u32 y_hot; /* vertical position of cursor hotspot */ + struct intel_vgpu_dmabuf_obj *obj; +}; + +/** + * struct intel_vgpu_dmabuf_obj- Intel vGPU device buffer object + */ +struct intel_vgpu_dmabuf_obj { + struct intel_vgpu *vgpu; + struct intel_vgpu_fb_info *info; + __u32 dmabuf_id; + struct kref kref; + bool initref; + struct list_head list; +}; + +int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args); +int intel_vgpu_get_dmabuf(struct intel_vgpu *vgpu, unsigned int dmabuf_id); +void intel_vgpu_dmabuf_cleanup(struct intel_vgpu *vgpu); + +#endif diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c index 3a74a408a966..9a5dce3aa10a 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.c +++ b/drivers/gpu/drm/i915/gvt/gvt.c @@ -181,6 +181,8 @@ static const struct intel_gvt_ops intel_gvt_ops = { .vgpu_deactivate = intel_gvt_deactivate_vgpu, .gvt_find_vgpu_type = intel_gvt_find_vgpu_type, .get_gvt_attrs = intel_get_gvt_attrs, + .vgpu_query_plane = intel_vgpu_query_plane, + .vgpu_get_dmabuf = intel_vgpu_get_dmabuf, }; /** diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 357d458cded0..77df9bad5dea 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -47,6 +47,7 @@ #include "render.h" #include "cmd_parser.h" #include "fb_decoder.h" +#include "dmabuf.h" #define GVT_MAX_VGPU 8 @@ -209,8 +210,16 @@ struct intel_vgpu { struct kvm *kvm; struct work_struct release_work; atomic_t released; + struct vfio_device *vfio_device; } vdev; #endif + + struct list_head dmabuf_obj_list_head; + struct mutex dmabuf_lock; + struct idr object_idr; + + struct completion vblank_done; + }; /* validating GM healthy status*/ @@ -536,6 +545,8 @@ struct intel_gvt_ops { const char *name); bool (*get_gvt_attrs)(struct attribute ***type_attrs, struct attribute_group ***intel_vgpu_type_groups); + int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *); + int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int); }; diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h b/drivers/gpu/drm/i915/gvt/hypercall.h index 32c345c3fa27..a1bd82feb827 100644 --- a/drivers/gpu/drm/i915/gvt/hypercall.h +++ b/drivers/gpu/drm/i915/gvt/hypercall.h @@ -56,6 +56,8 @@ struct intel_gvt_mpt { int (*set_trap_area)(unsigned long handle, u64 start, u64 end, bool map); int (*set_opregion)(void *vgpu); + int (*get_vfio_device)(void *vgpu); + void (*put_vfio_device)(void *vgpu); }; extern struct intel_gvt_mpt xengt_mpt; diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index e0cda45ac6c2..b8a85e08091a 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -377,10 +377,23 @@ static int intel_vgpu_register_reg(struct intel_vgpu *vgpu, vgpu->vdev.region[vgpu->vdev.num_regions].flags = flags; vgpu->vdev.region[vgpu->vdev.num_regions].data = data; vgpu->vdev.num_regions++; + return 0; +} + +static int kvmgt_get_vfio_device(void *p_vgpu) +{ + struct intel_vgpu *vgpu = (struct intel_vgpu *)p_vgpu; + vgpu->vdev.vfio_device = vfio_device_get_from_dev( + mdev_dev(vgpu->vdev.mdev)); + if (!vgpu->vdev.vfio_device) { + gvt_vgpu_err("failed to get vfio device\n"); + return -ENODEV; + } return 0; } + static int kvmgt_set_opregion(void *p_vgpu) { struct intel_vgpu *vgpu = (struct intel_vgpu *)p_vgpu; @@ -409,6 +422,14 @@ static int kvmgt_set_opregion(void *p_vgpu) return ret; } +static void kvmgt_put_vfio_device(void *vgpu) +{ + if (WARN_ON(!((struct intel_vgpu *)vgpu)->vdev.vfio_device)) + return; + + vfio_device_put(((struct intel_vgpu *)vgpu)->vdev.vfio_device); +} + static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev) { struct intel_vgpu *vgpu = NULL; @@ -1146,6 +1167,33 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, unsigned int cmd, } else if (cmd == VFIO_DEVICE_RESET) { intel_gvt_ops->vgpu_reset(vgpu); return 0; + } else if (cmd == VFIO_DEVICE_QUERY_GFX_PLANE) { + struct vfio_device_gfx_plane_info dmabuf; + int ret = 0; + + minsz = offsetofend(struct vfio_device_gfx_plane_info, + dmabuf_id); + if (copy_from_user(&dmabuf, (void __user *)arg, minsz)) + return -EFAULT; + if (dmabuf.argsz < minsz) + return -EINVAL; + + ret = intel_gvt_ops->vgpu_query_plane(vgpu, &dmabuf); + if (ret != 0) + return ret; + + return copy_to_user((void __user *)arg, &dmabuf, minsz) ? + -EFAULT : 0; + } else if (cmd == VFIO_DEVICE_GET_GFX_DMABUF) { + __u32 dmabuf_id; + __s32 dmabuf_fd; + + if (get_user(dmabuf_id, (__u32 __user *)arg)) + return -EFAULT; + + dmabuf_fd = intel_gvt_ops->vgpu_get_dmabuf(vgpu, dmabuf_id); + return dmabuf_fd; + } return 0; @@ -1387,6 +1435,9 @@ static int kvmgt_guest_init(struct mdev_device *mdev) kvmgt_protect_table_init(info); gvt_cache_init(vgpu); + mutex_init(&vgpu->dmabuf_lock); + init_completion(&vgpu->vblank_done); + info->track_node.track_write = kvmgt_page_track_write; info->track_node.track_flush_slot = kvmgt_page_track_flush_slot; kvm_page_track_register_notifier(kvm, &info->track_node); @@ -1528,6 +1579,8 @@ struct intel_gvt_mpt kvmgt_mpt = { .write_gpa = kvmgt_write_gpa, .gfn_to_mfn = kvmgt_gfn_to_pfn, .set_opregion = kvmgt_set_opregion, + .get_vfio_device = kvmgt_get_vfio_device, + .put_vfio_device = kvmgt_put_vfio_device, }; EXPORT_SYMBOL_GPL(kvmgt_mpt); diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h index c99e7964731c..ca8005a6d5fa 100644 --- a/drivers/gpu/drm/i915/gvt/mpt.h +++ b/drivers/gpu/drm/i915/gvt/mpt.h @@ -309,4 +309,34 @@ static inline int intel_gvt_hypervisor_set_opregion(struct intel_vgpu *vgpu) return intel_gvt_host.mpt->set_opregion(vgpu); } +/** + * intel_gvt_hypervisor_get_vfio_device - increase vfio device ref count + * @vgpu: a vGPU + * + * Returns: + * Zero on success, negative error code if failed. + */ +static inline int intel_gvt_hypervisor_get_vfio_device(struct intel_vgpu *vgpu) +{ + if (!intel_gvt_host.mpt->get_vfio_device) + return 0; + + return intel_gvt_host.mpt->get_vfio_device(vgpu); +} + +/** + * intel_gvt_hypervisor_put_vfio_device - decrease vfio device ref count + * @vgpu: a vGPU + * + * Returns: + * Zero on success, negative error code if failed. + */ +static inline void intel_gvt_hypervisor_put_vfio_device(struct intel_vgpu *vgpu) +{ + if (!intel_gvt_host.mpt->put_vfio_device) + return; + + intel_gvt_host.mpt->put_vfio_device(vgpu); +} + #endif /* _GVT_MPT_H_ */ diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index dcdd72260cc9..39926176fbeb 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -236,6 +236,7 @@ void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu) } intel_vgpu_stop_schedule(vgpu); + intel_vgpu_dmabuf_cleanup(vgpu); mutex_unlock(&gvt->lock); } @@ -265,6 +266,7 @@ void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu) intel_gvt_hypervisor_detach_vgpu(vgpu); intel_vgpu_free_resource(vgpu); intel_vgpu_clean_mmio(vgpu); + intel_vgpu_dmabuf_cleanup(vgpu); vfree(vgpu); intel_gvt_update_vgpu_types(gvt); @@ -349,7 +351,8 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt, vgpu->handle = param->handle; vgpu->gvt = gvt; vgpu->sched_ctl.weight = param->weight; - + INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head); + idr_init(&vgpu->object_idr); intel_vgpu_init_cfg_space(vgpu, param->primary); ret = intel_vgpu_init_mmio(vgpu); diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h index 19fb28c177d8..05e89e1c0a08 100644 --- a/drivers/gpu/drm/i915/i915_gem_object.h +++ b/drivers/gpu/drm/i915/i915_gem_object.h @@ -261,6 +261,8 @@ struct drm_i915_gem_object { } userptr; unsigned long scratch; + + void *gvt_info; }; /** for phys allocated objects */ -- GitLab From dfb6ae4e14bd6542ee6caa8f661f269c94e19a9f Mon Sep 17 00:00:00 2001 From: Tina Zhang Date: Thu, 23 Nov 2017 16:26:37 +0800 Subject: [PATCH 0499/2547] drm/i915/gvt: Handle orphan dmabuf_objs dmabuf_obj's destruction relys on GEM release operation, which is managed in i915 driver. And there is a time window between vgpu's destruction and its dmabuf_objs' destruction. This patch is to free the orphan dmabuf_objs correctly after the vgpu passes away. Signed-off-by: Tina Zhang Cc: Zhenyu Wang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/dmabuf.c | 56 +++++++++++++++++++------------ 1 file changed, 35 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c index 190710c8d3e5..50215b26b6c8 100644 --- a/drivers/gpu/drm/i915/gvt/dmabuf.c +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c @@ -88,19 +88,26 @@ static void dmabuf_gem_object_free(struct kref *kref) container_of(kref, struct intel_vgpu_dmabuf_obj, kref); struct intel_vgpu *vgpu = obj->vgpu; struct list_head *pos; - struct intel_vgpu_dmabuf_obj *dmabuf_obj; - list_for_each(pos, &vgpu->dmabuf_obj_list_head) { - dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj, - list); - if (dmabuf_obj == obj) { - idr_remove(&vgpu->object_idr, dmabuf_obj->dmabuf_id); - kfree(dmabuf_obj->info); - kfree(dmabuf_obj); - list_del(pos); - break; + if (vgpu) { + list_for_each(pos, &vgpu->dmabuf_obj_list_head) { + dmabuf_obj = container_of(pos, + struct intel_vgpu_dmabuf_obj, list); + if (dmabuf_obj == obj) { + intel_gvt_hypervisor_put_vfio_device(vgpu); + idr_remove(&vgpu->object_idr, + dmabuf_obj->dmabuf_id); + kfree(dmabuf_obj->info); + kfree(dmabuf_obj); + list_del(pos); + break; + } } + } else { + /* Free the orphan dmabuf_objs here */ + kfree(obj->info); + kfree(obj); } } @@ -122,11 +129,16 @@ static void vgpu_gem_release(struct drm_i915_gem_object *gem_obj) struct intel_vgpu_dmabuf_obj *obj = fb_info->obj; struct intel_vgpu *vgpu = obj->vgpu; - mutex_lock(&vgpu->dmabuf_lock); - gem_obj->base.dma_buf = NULL; - dmabuf_obj_put(obj); - intel_gvt_hypervisor_put_vfio_device(vgpu); - mutex_unlock(&vgpu->dmabuf_lock); + if (vgpu) { + mutex_lock(&vgpu->dmabuf_lock); + gem_obj->base.dma_buf = NULL; + dmabuf_obj_put(obj); + mutex_unlock(&vgpu->dmabuf_lock); + } else { + /* vgpu is NULL, as it has been removed already */ + gem_obj->base.dma_buf = NULL; + dmabuf_obj_put(obj); + } } static const struct drm_i915_gem_object_ops intel_vgpu_gem_ops = { @@ -471,12 +483,6 @@ int intel_vgpu_get_dmabuf(struct intel_vgpu *vgpu, unsigned int dmabuf_id) } dmabuf_fd = ret; - if (intel_gvt_hypervisor_get_vfio_device(vgpu)) { - gvt_vgpu_err("get vfio device failed\n"); - put_unused_fd(ret); - goto out_free_dmabuf; - } - dmabuf_obj_get(dmabuf_obj); if (dmabuf_obj->initref) { @@ -518,6 +524,14 @@ void intel_vgpu_dmabuf_cleanup(struct intel_vgpu *vgpu) dmabuf_obj->initref = false; dmabuf_obj_put(dmabuf_obj); } + + idr_remove(&vgpu->object_idr, dmabuf_obj->dmabuf_id); + + if (dmabuf_obj->vgpu) + intel_gvt_hypervisor_put_vfio_device(vgpu); + + dmabuf_obj->vgpu = NULL; + } mutex_unlock(&vgpu->dmabuf_lock); } -- GitLab From 4a136d590bd4c579bb3df154363a3e5b51cb36ce Mon Sep 17 00:00:00 2001 From: Tina Zhang Date: Tue, 28 Nov 2017 13:50:42 +0800 Subject: [PATCH 0500/2547] drm/i915/gvt: Introduce KBL to dma-buf on Gvt-g This patch introduces KBL platform to dma-buf on Gvt-g. Signed-off-by: Tina Zhang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +- drivers/gpu/drm/i915/gvt/fb_decoder.c | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c index 50215b26b6c8..5f39e90f961c 100644 --- a/drivers/gpu/drm/i915/gvt/dmabuf.c +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c @@ -164,7 +164,7 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, obj->base.read_domains = I915_GEM_DOMAIN_GTT; obj->base.write_domain = 0; - if (IS_SKYLAKE(dev_priv)) { + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { unsigned int tiling_mode = 0; unsigned int stride = 0; diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 6c99c64d8e14..72f42176f35c 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -150,7 +150,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, u32 stride_reg = vgpu_vreg(vgpu, DSPSTRIDE(pipe)) & stride_mask; u32 stride = stride_reg; - if (IS_SKYLAKE(dev_priv)) { + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { switch (tiled) { case PLANE_CTL_TILED_LINEAR: stride = stride_reg * 64; @@ -214,7 +214,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, if (!plane->enabled) return -ENODEV; - if (IS_SKYLAKE(dev_priv)) { + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { plane->tiled = (val & PLANE_CTL_TILED_MASK) >> _PLANE_CTL_TILED_SHIFT; fmt = skl_format_to_drm( @@ -253,8 +253,9 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, } plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10), - (IS_SKYLAKE(dev_priv)) ? (_PRI_PLANE_STRIDE_MASK >> 6) : - _PRI_PLANE_STRIDE_MASK, plane->bpp); + (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) ? + (_PRI_PLANE_STRIDE_MASK >> 6) : + _PRI_PLANE_STRIDE_MASK, plane->bpp); plane->width = (vgpu_vreg(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> _PIPE_H_SRCSZ_SHIFT; -- GitLab From 82a3b6701ab1e2cdfb64cf163fc6d1a4576329ff Mon Sep 17 00:00:00 2001 From: Tina Zhang Date: Wed, 29 Nov 2017 14:57:37 +0800 Subject: [PATCH 0501/2547] drm/i915/gvt: Free dmabuf_obj list in intel_vgpu_dmabuf_cleanup The per vGPU dmabuf_obj list should be released in intel_vgpu_dmabuf_ cleanup, which is invoked either in the process of closing a VM or in the process of removing a vGPU. Fixes: e3a0d7976c53 ("drm/i915/gvt: Handle orphan dmabuf_objs") Signed-off-by: Tina Zhang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/dmabuf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c index 5f39e90f961c..9c40a67ecdd6 100644 --- a/drivers/gpu/drm/i915/gvt/dmabuf.c +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c @@ -90,7 +90,7 @@ static void dmabuf_gem_object_free(struct kref *kref) struct list_head *pos; struct intel_vgpu_dmabuf_obj *dmabuf_obj; - if (vgpu) { + if (vgpu && vgpu->active && !list_empty(&vgpu->dmabuf_obj_list_head)) { list_for_each(pos, &vgpu->dmabuf_obj_list_head) { dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj, list); @@ -530,6 +530,7 @@ void intel_vgpu_dmabuf_cleanup(struct intel_vgpu *vgpu) if (dmabuf_obj->vgpu) intel_gvt_hypervisor_put_vfio_device(vgpu); + list_del(pos); dmabuf_obj->vgpu = NULL; } -- GitLab From 59a716c6477c2a095adf274e8f76b9889af7bc7b Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Wed, 29 Nov 2017 15:40:06 +0800 Subject: [PATCH 0502/2547] drm/i915/gvt: Convert macro queue_workload to a function Convert the macro to a function which should always be preferred. Signed-off-by: Changbin Du Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/execlist.c | 2 +- drivers/gpu/drm/i915/gvt/scheduler.c | 11 +++++++++++ drivers/gpu/drm/i915/gvt/scheduler.h | 7 +------ 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index fa4929584744..769c1c24ae75 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c @@ -458,7 +458,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, gvt_dbg_el("workload %p emulate schedule_in %d\n", workload, emulate_schedule_in); - queue_workload(workload); + intel_vgpu_queue_workload(workload); return 0; } diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 13ccc00f0d40..abf71be092f8 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -1328,3 +1328,14 @@ intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id, return workload; } + +/** + * intel_vgpu_queue_workload - Qeue a vGPU workload + * @workload: the workload to queue in + */ +void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload) +{ + list_add_tail(&workload->list, + workload_q_head(workload->vgpu, workload->ring_id)); + wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]); +} diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h index e4a9f9acd4a9..3de77dfa7c59 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.h +++ b/drivers/gpu/drm/i915/gvt/scheduler.h @@ -125,12 +125,7 @@ struct intel_vgpu_shadow_bb { #define workload_q_head(vgpu, ring_id) \ (&(vgpu->submission.workload_q_head[ring_id])) -#define queue_workload(workload) do { \ - list_add_tail(&workload->list, \ - workload_q_head(workload->vgpu, workload->ring_id)); \ - wake_up(&workload->vgpu->gvt-> \ - scheduler.waitq[workload->ring_id]); \ -} while (0) +void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload); int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt); -- GitLab From c130456cefd4cf9531f12f3e9b23805d34706ac0 Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Wed, 29 Nov 2017 15:40:07 +0800 Subject: [PATCH 0503/2547] drm/i915/gvt: Kick scheduler when new workload queued The current schedule policy rely on a 1ms timer to execute workload. This can introduce maximum 1ms unnecessary latency. This is especially bad for small media workloads. And I don't think we need this timer for QoS, but the change is not simply remove the code. So I made a new API intel_gvt_kick_schedule() for future change. Signed-off-by: Changbin Du Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/sched_policy.c | 5 +++++ drivers/gpu/drm/i915/gvt/sched_policy.h | 2 ++ drivers/gpu/drm/i915/gvt/scheduler.c | 1 + 3 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/sched_policy.c b/drivers/gpu/drm/i915/gvt/sched_policy.c index 03532dfc0cd5..eea1a2f92099 100644 --- a/drivers/gpu/drm/i915/gvt/sched_policy.c +++ b/drivers/gpu/drm/i915/gvt/sched_policy.c @@ -372,6 +372,11 @@ void intel_vgpu_start_schedule(struct intel_vgpu *vgpu) vgpu->gvt->scheduler.sched_ops->start_schedule(vgpu); } +void intel_gvt_kick_schedule(struct intel_gvt *gvt) +{ + intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED); +} + void intel_vgpu_stop_schedule(struct intel_vgpu *vgpu) { struct intel_gvt_workload_scheduler *scheduler = diff --git a/drivers/gpu/drm/i915/gvt/sched_policy.h b/drivers/gpu/drm/i915/gvt/sched_policy.h index ba00a5f7455f..7b59e3e88b8b 100644 --- a/drivers/gpu/drm/i915/gvt/sched_policy.h +++ b/drivers/gpu/drm/i915/gvt/sched_policy.h @@ -57,4 +57,6 @@ void intel_vgpu_start_schedule(struct intel_vgpu *vgpu); void intel_vgpu_stop_schedule(struct intel_vgpu *vgpu); +void intel_gvt_kick_schedule(struct intel_gvt *gvt); + #endif diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index abf71be092f8..76d2812f2f03 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -1337,5 +1337,6 @@ void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload) { list_add_tail(&workload->list, workload_q_head(workload->vgpu, workload->ring_id)); + intel_gvt_kick_schedule(workload->vgpu->gvt); wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]); } -- GitLab From da5f99eaccc10e30bf82eb02b1be74703b878720 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Fri, 1 Dec 2017 14:59:53 +0800 Subject: [PATCH 0504/2547] drm/i915/gvt: Don't mark vgpu context as inactive when preempted We shouldn't mark inactive for vGPU context if preempted, which would still be re-scheduled later. So keep active state. Fixes: d6c0511300dc ("drm/i915/execlists: Distinguish the incomplete context notifies") Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/scheduler.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 76d2812f2f03..9100aebcb105 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -188,10 +188,12 @@ static int shadow_context_status_change(struct notifier_block *nb, atomic_set(&workload->shadow_ctx_active, 1); break; case INTEL_CONTEXT_SCHEDULE_OUT: - case INTEL_CONTEXT_SCHEDULE_PREEMPTED: save_ring_hw_state(workload->vgpu, ring_id); atomic_set(&workload->shadow_ctx_active, 0); break; + case INTEL_CONTEXT_SCHEDULE_PREEMPTED: + save_ring_hw_state(workload->vgpu, ring_id); + break; default: WARN_ON(1); return NOTIFY_OK; -- GitLab From 1603660b3342269c95fcafee1945790342a8c28e Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Mon, 4 Dec 2017 10:42:58 +0800 Subject: [PATCH 0505/2547] drm/i915/gvt: set max priority for gvt context This is to workaround guest driver hang regression after preemption enable that gvt hasn't enabled handling of that for guest workload. So in effect this disables preemption for gvt context now. Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/scheduler.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 9100aebcb105..ab9a500ba3e9 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -1038,6 +1038,9 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu) if (IS_ERR(s->shadow_ctx)) return PTR_ERR(s->shadow_ctx); + if (HAS_LOGICAL_RING_PREEMPTION(vgpu->gvt->dev_priv)) + s->shadow_ctx->priority = INT_MAX; + bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES); s->workloads = kmem_cache_create("gvt-g_vgpu_workload", -- GitLab From 81faa5566864e97a5578c4e08c07edf04239abcc Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Sun, 3 Dec 2017 19:28:33 -0800 Subject: [PATCH 0506/2547] firmware: arm_scpi: Revert updates made during v4.15 merge window Revert "Merge tag 'scpi-updates-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/drivers" Paraphrased from email from Kevin Hilman: Revert ARM SCPI changes since v4.14. Untested changes caused regressions in SCPI and CPUfreq/DVFS failures on most Amlogic SoCs. Changes reverted for v4.15 so they can be better reviewed and tested. These ARM SCPI changes caused SCPI regressions resulting in CPUfreq failures on most Amlogic SoCs (found by kernelci.org.) Unfortunately, this was not caught in linux-next due to other bugs/panics on these platforms masking this problem so we've only found it since we've fixed the other issues. Since we're already in the -rc cycle, I'd prefer to revert to a known working state (that of v4.14) rather than finding/reverting a subset, which would just lead to another untested state. These changes can then have some time to be better reviewed and tested and resubmitted for v4.16. Kevin Hilman has tested this revert on the affected Amlogic SoCs and verified that we're back to the previous (working) condition. This reverts commit 6710acf2596a29f7351e8165d981645f403e0025, reversing changes made to 4b367f2e8854da34d14bd154ff4432fb49f69b36. Reported-by: Kevin Hilman Signed-off-by: Olof Johansson --- drivers/firmware/arm_scpi.c | 216 +++++++++++++++++++++--------------- 1 file changed, 129 insertions(+), 87 deletions(-) diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c index dfb373c8ba2a..7da9f1b83ebe 100644 --- a/drivers/firmware/arm_scpi.c +++ b/drivers/firmware/arm_scpi.c @@ -28,7 +28,6 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include -#include #include #include #include @@ -73,13 +72,21 @@ #define MAX_DVFS_DOMAINS 8 #define MAX_DVFS_OPPS 16 - -#define PROTO_REV_MAJOR_MASK GENMASK(31, 16) -#define PROTO_REV_MINOR_MASK GENMASK(15, 0) - -#define FW_REV_MAJOR_MASK GENMASK(31, 24) -#define FW_REV_MINOR_MASK GENMASK(23, 16) -#define FW_REV_PATCH_MASK GENMASK(15, 0) +#define DVFS_LATENCY(hdr) (le32_to_cpu(hdr) >> 16) +#define DVFS_OPP_COUNT(hdr) ((le32_to_cpu(hdr) >> 8) & 0xff) + +#define PROTOCOL_REV_MINOR_BITS 16 +#define PROTOCOL_REV_MINOR_MASK ((1U << PROTOCOL_REV_MINOR_BITS) - 1) +#define PROTOCOL_REV_MAJOR(x) ((x) >> PROTOCOL_REV_MINOR_BITS) +#define PROTOCOL_REV_MINOR(x) ((x) & PROTOCOL_REV_MINOR_MASK) + +#define FW_REV_MAJOR_BITS 24 +#define FW_REV_MINOR_BITS 16 +#define FW_REV_PATCH_MASK ((1U << FW_REV_MINOR_BITS) - 1) +#define FW_REV_MINOR_MASK ((1U << FW_REV_MAJOR_BITS) - 1) +#define FW_REV_MAJOR(x) ((x) >> FW_REV_MAJOR_BITS) +#define FW_REV_MINOR(x) (((x) & FW_REV_MINOR_MASK) >> FW_REV_MINOR_BITS) +#define FW_REV_PATCH(x) ((x) & FW_REV_PATCH_MASK) #define MAX_RX_TIMEOUT (msecs_to_jiffies(30)) @@ -304,6 +311,10 @@ struct clk_get_info { u8 name[20]; } __packed; +struct clk_get_value { + __le32 rate; +} __packed; + struct clk_set_value { __le16 id; __le16 reserved; @@ -317,9 +328,7 @@ struct legacy_clk_set_value { } __packed; struct dvfs_info { - u8 domain; - u8 opp_count; - __le16 latency; + __le32 header; struct { __le32 freq; __le32 m_volt; @@ -342,6 +351,11 @@ struct _scpi_sensor_info { char name[20]; }; +struct sensor_value { + __le32 lo_val; + __le32 hi_val; +} __packed; + struct dev_pstate_set { __le16 dev_id; u8 pstate; @@ -405,20 +419,19 @@ static void scpi_process_cmd(struct scpi_chan *ch, u32 cmd) unsigned int len; if (scpi_info->is_legacy) { - struct legacy_scpi_shared_mem __iomem *mem = - ch->rx_payload; + struct legacy_scpi_shared_mem *mem = ch->rx_payload; /* RX Length is not replied by the legacy Firmware */ len = match->rx_len; - match->status = ioread32(&mem->status); + match->status = le32_to_cpu(mem->status); memcpy_fromio(match->rx_buf, mem->payload, len); } else { - struct scpi_shared_mem __iomem *mem = ch->rx_payload; + struct scpi_shared_mem *mem = ch->rx_payload; len = min(match->rx_len, CMD_SIZE(cmd)); - match->status = ioread32(&mem->status); + match->status = le32_to_cpu(mem->status); memcpy_fromio(match->rx_buf, mem->payload, len); } @@ -432,11 +445,11 @@ static void scpi_process_cmd(struct scpi_chan *ch, u32 cmd) static void scpi_handle_remote_msg(struct mbox_client *c, void *msg) { struct scpi_chan *ch = container_of(c, struct scpi_chan, cl); - struct scpi_shared_mem __iomem *mem = ch->rx_payload; + struct scpi_shared_mem *mem = ch->rx_payload; u32 cmd = 0; if (!scpi_info->is_legacy) - cmd = ioread32(&mem->command); + cmd = le32_to_cpu(mem->command); scpi_process_cmd(ch, cmd); } @@ -446,7 +459,7 @@ static void scpi_tx_prepare(struct mbox_client *c, void *msg) unsigned long flags; struct scpi_xfer *t = msg; struct scpi_chan *ch = container_of(c, struct scpi_chan, cl); - struct scpi_shared_mem __iomem *mem = ch->tx_payload; + struct scpi_shared_mem *mem = (struct scpi_shared_mem *)ch->tx_payload; if (t->tx_buf) { if (scpi_info->is_legacy) @@ -465,7 +478,7 @@ static void scpi_tx_prepare(struct mbox_client *c, void *msg) } if (!scpi_info->is_legacy) - iowrite32(t->cmd, &mem->command); + mem->command = cpu_to_le32(t->cmd); } static struct scpi_xfer *get_scpi_xfer(struct scpi_chan *ch) @@ -570,13 +583,13 @@ scpi_clk_get_range(u16 clk_id, unsigned long *min, unsigned long *max) static unsigned long scpi_clk_get_val(u16 clk_id) { int ret; - __le32 rate; + struct clk_get_value clk; __le16 le_clk_id = cpu_to_le16(clk_id); ret = scpi_send_message(CMD_GET_CLOCK_VALUE, &le_clk_id, - sizeof(le_clk_id), &rate, sizeof(rate)); + sizeof(le_clk_id), &clk, sizeof(clk)); - return ret ? ret : le32_to_cpu(rate); + return ret ? ret : le32_to_cpu(clk.rate); } static int scpi_clk_set_val(u16 clk_id, unsigned long rate) @@ -631,35 +644,35 @@ static int opp_cmp_func(const void *opp1, const void *opp2) } static struct scpi_dvfs_info *scpi_dvfs_get_info(u8 domain) -{ - if (domain >= MAX_DVFS_DOMAINS) - return ERR_PTR(-EINVAL); - - return scpi_info->dvfs[domain] ?: ERR_PTR(-EINVAL); -} - -static int scpi_dvfs_populate_info(struct device *dev, u8 domain) { struct scpi_dvfs_info *info; struct scpi_opp *opp; struct dvfs_info buf; int ret, i; + if (domain >= MAX_DVFS_DOMAINS) + return ERR_PTR(-EINVAL); + + if (scpi_info->dvfs[domain]) /* data already populated */ + return scpi_info->dvfs[domain]; + ret = scpi_send_message(CMD_GET_DVFS_INFO, &domain, sizeof(domain), &buf, sizeof(buf)); if (ret) - return ret; + return ERR_PTR(ret); - info = devm_kmalloc(dev, sizeof(*info), GFP_KERNEL); + info = kmalloc(sizeof(*info), GFP_KERNEL); if (!info) - return -ENOMEM; + return ERR_PTR(-ENOMEM); - info->count = buf.opp_count; - info->latency = le16_to_cpu(buf.latency) * 1000; /* uS to nS */ + info->count = DVFS_OPP_COUNT(buf.header); + info->latency = DVFS_LATENCY(buf.header) * 1000; /* uS to nS */ - info->opps = devm_kcalloc(dev, info->count, sizeof(*opp), GFP_KERNEL); - if (!info->opps) - return -ENOMEM; + info->opps = kcalloc(info->count, sizeof(*opp), GFP_KERNEL); + if (!info->opps) { + kfree(info); + return ERR_PTR(-ENOMEM); + } for (i = 0, opp = info->opps; i < info->count; i++, opp++) { opp->freq = le32_to_cpu(buf.opps[i].freq); @@ -669,15 +682,7 @@ static int scpi_dvfs_populate_info(struct device *dev, u8 domain) sort(info->opps, info->count, sizeof(*opp), opp_cmp_func, NULL); scpi_info->dvfs[domain] = info; - return 0; -} - -static void scpi_dvfs_populate(struct device *dev) -{ - int domain; - - for (domain = 0; domain < MAX_DVFS_DOMAINS; domain++) - scpi_dvfs_populate_info(dev, domain); + return info; } static int scpi_dev_domain_id(struct device *dev) @@ -708,6 +713,9 @@ static int scpi_dvfs_get_transition_latency(struct device *dev) if (IS_ERR(info)) return PTR_ERR(info); + if (!info->latency) + return 0; + return info->latency; } @@ -768,19 +776,20 @@ static int scpi_sensor_get_info(u16 sensor_id, struct scpi_sensor_info *info) static int scpi_sensor_get_value(u16 sensor, u64 *val) { __le16 id = cpu_to_le16(sensor); - __le64 value; + struct sensor_value buf; int ret; ret = scpi_send_message(CMD_SENSOR_VALUE, &id, sizeof(id), - &value, sizeof(value)); + &buf, sizeof(buf)); if (ret) return ret; if (scpi_info->is_legacy) - /* only 32-bits supported, upper 32 bits can be junk */ - *val = le32_to_cpup((__le32 *)&value); + /* only 32-bits supported, hi_val can be junk */ + *val = le32_to_cpu(buf.lo_val); else - *val = le64_to_cpu(value); + *val = (u64)le32_to_cpu(buf.hi_val) << 32 | + le32_to_cpu(buf.lo_val); return 0; } @@ -853,19 +862,23 @@ static int scpi_init_versions(struct scpi_drvinfo *info) static ssize_t protocol_version_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%lu.%lu\n", - FIELD_GET(PROTO_REV_MAJOR_MASK, scpi_info->protocol_version), - FIELD_GET(PROTO_REV_MINOR_MASK, scpi_info->protocol_version)); + struct scpi_drvinfo *scpi_info = dev_get_drvdata(dev); + + return sprintf(buf, "%d.%d\n", + PROTOCOL_REV_MAJOR(scpi_info->protocol_version), + PROTOCOL_REV_MINOR(scpi_info->protocol_version)); } static DEVICE_ATTR_RO(protocol_version); static ssize_t firmware_version_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%lu.%lu.%lu\n", - FIELD_GET(FW_REV_MAJOR_MASK, scpi_info->firmware_version), - FIELD_GET(FW_REV_MINOR_MASK, scpi_info->firmware_version), - FIELD_GET(FW_REV_PATCH_MASK, scpi_info->firmware_version)); + struct scpi_drvinfo *scpi_info = dev_get_drvdata(dev); + + return sprintf(buf, "%d.%d.%d\n", + FW_REV_MAJOR(scpi_info->firmware_version), + FW_REV_MINOR(scpi_info->firmware_version), + FW_REV_PATCH(scpi_info->firmware_version)); } static DEVICE_ATTR_RO(firmware_version); @@ -876,13 +889,39 @@ static struct attribute *versions_attrs[] = { }; ATTRIBUTE_GROUPS(versions); -static void scpi_free_channels(void *data) +static void +scpi_free_channels(struct device *dev, struct scpi_chan *pchan, int count) { - struct scpi_drvinfo *info = data; int i; - for (i = 0; i < info->num_chans; i++) - mbox_free_channel(info->channels[i].chan); + for (i = 0; i < count && pchan->chan; i++, pchan++) { + mbox_free_channel(pchan->chan); + devm_kfree(dev, pchan->xfers); + devm_iounmap(dev, pchan->rx_payload); + } +} + +static int scpi_remove(struct platform_device *pdev) +{ + int i; + struct device *dev = &pdev->dev; + struct scpi_drvinfo *info = platform_get_drvdata(pdev); + + scpi_info = NULL; /* stop exporting SCPI ops through get_scpi_ops */ + + of_platform_depopulate(dev); + sysfs_remove_groups(&dev->kobj, versions_groups); + scpi_free_channels(dev, info->channels, info->num_chans); + platform_set_drvdata(pdev, NULL); + + for (i = 0; i < MAX_DVFS_DOMAINS && info->dvfs[i]; i++) { + kfree(info->dvfs[i]->opps); + kfree(info->dvfs[i]); + } + devm_kfree(dev, info->channels); + devm_kfree(dev, info); + + return 0; } #define MAX_SCPI_XFERS 10 @@ -913,6 +952,7 @@ static int scpi_probe(struct platform_device *pdev) { int count, idx, ret; struct resource res; + struct scpi_chan *scpi_chan; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; @@ -929,19 +969,13 @@ static int scpi_probe(struct platform_device *pdev) return -ENODEV; } - scpi_info->channels = devm_kcalloc(dev, count, sizeof(struct scpi_chan), - GFP_KERNEL); - if (!scpi_info->channels) + scpi_chan = devm_kcalloc(dev, count, sizeof(*scpi_chan), GFP_KERNEL); + if (!scpi_chan) return -ENOMEM; - ret = devm_add_action(dev, scpi_free_channels, scpi_info); - if (ret) - return ret; - - for (; scpi_info->num_chans < count; scpi_info->num_chans++) { + for (idx = 0; idx < count; idx++) { resource_size_t size; - int idx = scpi_info->num_chans; - struct scpi_chan *pchan = scpi_info->channels + idx; + struct scpi_chan *pchan = scpi_chan + idx; struct mbox_client *cl = &pchan->cl; struct device_node *shmem = of_parse_phandle(np, "shmem", idx); @@ -949,14 +983,15 @@ static int scpi_probe(struct platform_device *pdev) of_node_put(shmem); if (ret) { dev_err(dev, "failed to get SCPI payload mem resource\n"); - return ret; + goto err; } size = resource_size(&res); pchan->rx_payload = devm_ioremap(dev, res.start, size); if (!pchan->rx_payload) { dev_err(dev, "failed to ioremap SCPI payload\n"); - return -EADDRNOTAVAIL; + ret = -EADDRNOTAVAIL; + goto err; } pchan->tx_payload = pchan->rx_payload + (size >> 1); @@ -982,11 +1017,17 @@ static int scpi_probe(struct platform_device *pdev) dev_err(dev, "failed to get channel%d err %d\n", idx, ret); } +err: + scpi_free_channels(dev, scpi_chan, idx); + scpi_info = NULL; return ret; } + scpi_info->channels = scpi_chan; + scpi_info->num_chans = count; scpi_info->commands = scpi_std_commands; - scpi_info->scpi_ops = &scpi_ops; + + platform_set_drvdata(pdev, scpi_info); if (scpi_info->is_legacy) { /* Replace with legacy variants */ @@ -1002,23 +1043,23 @@ static int scpi_probe(struct platform_device *pdev) ret = scpi_init_versions(scpi_info); if (ret) { dev_err(dev, "incorrect or no SCP firmware found\n"); + scpi_remove(pdev); return ret; } - scpi_dvfs_populate(dev); - - _dev_info(dev, "SCP Protocol %lu.%lu Firmware %lu.%lu.%lu version\n", - FIELD_GET(PROTO_REV_MAJOR_MASK, scpi_info->protocol_version), - FIELD_GET(PROTO_REV_MINOR_MASK, scpi_info->protocol_version), - FIELD_GET(FW_REV_MAJOR_MASK, scpi_info->firmware_version), - FIELD_GET(FW_REV_MINOR_MASK, scpi_info->firmware_version), - FIELD_GET(FW_REV_PATCH_MASK, scpi_info->firmware_version)); + _dev_info(dev, "SCP Protocol %d.%d Firmware %d.%d.%d version\n", + PROTOCOL_REV_MAJOR(scpi_info->protocol_version), + PROTOCOL_REV_MINOR(scpi_info->protocol_version), + FW_REV_MAJOR(scpi_info->firmware_version), + FW_REV_MINOR(scpi_info->firmware_version), + FW_REV_PATCH(scpi_info->firmware_version)); + scpi_info->scpi_ops = &scpi_ops; - ret = devm_device_add_groups(dev, versions_groups); + ret = sysfs_create_groups(&dev->kobj, versions_groups); if (ret) dev_err(dev, "unable to create sysfs version group\n"); - return devm_of_platform_populate(dev); + return of_platform_populate(dev->of_node, NULL, NULL, dev); } static const struct of_device_id scpi_of_match[] = { @@ -1035,6 +1076,7 @@ static struct platform_driver scpi_driver = { .of_match_table = scpi_of_match, }, .probe = scpi_probe, + .remove = scpi_remove, }; module_platform_driver(scpi_driver); -- GitLab From c894aa97577e47d3066b27b32499ecf899bfa8b0 Mon Sep 17 00:00:00 2001 From: Eryu Guan Date: Sun, 3 Dec 2017 22:52:51 -0500 Subject: [PATCH 0507/2547] ext4: fix fdatasync(2) after fallocate(2) operation Currently, fallocate(2) with KEEP_SIZE followed by a fdatasync(2) then crash, we'll see wrong allocated block number (stat -c %b), the blocks allocated beyond EOF are all lost. fstests generic/468 exposes this bug. Commit 67a7d5f561f4 ("ext4: fix fdatasync(2) after extent manipulation operations") fixed all the other extent manipulation operation paths such as hole punch, zero range, collapse range etc., but forgot the fallocate case. So similarly, fix it by recording the correct journal tid in ext4 inode in fallocate(2) path, so that ext4_sync_file() will wait for the right tid to be committed on fdatasync(2). This addresses the test failure in xfstests test generic/468. Signed-off-by: Eryu Guan Signed-off-by: Theodore Ts'o Cc: stable@vger.kernel.org --- fs/ext4/extents.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/ext4/extents.c b/fs/ext4/extents.c index 07bca11749d4..c941251ac0c0 100644 --- a/fs/ext4/extents.c +++ b/fs/ext4/extents.c @@ -4722,6 +4722,7 @@ static int ext4_alloc_file_blocks(struct file *file, ext4_lblk_t offset, EXT4_INODE_EOFBLOCKS); } ext4_mark_inode_dirty(handle, inode); + ext4_update_inode_fsync_trans(handle, inode, 1); ret2 = ext4_journal_stop(handle); if (ret2) break; -- GitLab From 5aa04b3eb6fca63d2e9827be656dcadc26d54e11 Mon Sep 17 00:00:00 2001 From: Ravi Bangoria Date: Thu, 30 Nov 2017 14:03:22 +0530 Subject: [PATCH 0508/2547] powerpc/perf: Fix oops when grouping different pmu events When user tries to group imc (In-Memory Collections) event with normal event, (sometime) kernel crashes with following log: Faulting instruction address: 0x00000000 [link register ] c00000000010ce88 power_check_constraints+0x128/0x980 ... c00000000010e238 power_pmu_event_init+0x268/0x6f0 c0000000002dc60c perf_try_init_event+0xdc/0x1a0 c0000000002dce88 perf_event_alloc+0x7b8/0xac0 c0000000002e92e0 SyS_perf_event_open+0x530/0xda0 c00000000000b004 system_call+0x38/0xe0 'event_base' field of 'struct hw_perf_event' is used as flags for normal hw events and used as memory address for imc events. While grouping these two types of events, collect_events() tries to interpret imc 'event_base' as a flag, which causes a corruption resulting in a crash. Consider only those events which belongs to 'perf_hw_context' in collect_events(). Signed-off-by: Ravi Bangoria Reviewed-By: Madhavan Srinivasan Signed-off-by: Michael Ellerman --- arch/powerpc/perf/core-book3s.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 9e3da168d54c..153812966365 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -1415,7 +1415,7 @@ static int collect_events(struct perf_event *group, int max_count, int n = 0; struct perf_event *event; - if (!is_software_event(group)) { + if (group->pmu->task_ctx_nr == perf_hw_context) { if (n >= max_count) return -1; ctrs[n] = group; @@ -1423,7 +1423,7 @@ static int collect_events(struct perf_event *group, int max_count, events[n++] = group->hw.config; } list_for_each_entry(event, &group->sibling_list, group_entry) { - if (!is_software_event(event) && + if (event->pmu->task_ctx_nr == perf_hw_context && event->state != PERF_EVENT_STATE_OFF) { if (n >= max_count) return -1; -- GitLab From 006c23327f8de8575508c458131b304188d426f7 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 3 Dec 2017 15:36:20 -0800 Subject: [PATCH 0509/2547] documentation/gpu/i915: fix docs build error after file rename Fix documentation build errors after intel_guc_loader.c was renamed to intel_guc_fw.c. Error: Cannot open file ../drivers/gpu/drm/i915/intel_guc_loader.c WARNING: kernel-doc '../scripts/kernel-doc -rst -enable-lineno -function GuC-specific firmware loader ../drivers/gpu/drm/i915/intel_guc_loader.c' failed with return code 1 Error: Cannot open file ../drivers/gpu/drm/i915/intel_guc_loader.c Error: Cannot open file ../drivers/gpu/drm/i915/intel_guc_loader.c WARNING: kernel-doc '../scripts/kernel-doc -rst -enable-lineno -internal ../drivers/gpu/drm/i915/intel_guc_loader.c' failed with return code 2 Fixes: e8668bbcb0f9 ("drm/i915/guc: Rename intel_guc_loader.c to intel_guc_fw.c") Signed-off-by: Randy Dunlap Cc: Michal Wajdeczko Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/1b214f53-47f5-bef3-f58e-8136de5678ed@infradead.org --- Documentation/gpu/i915.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 21577eabaf78..84021142a8f3 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -341,10 +341,10 @@ GuC GuC-specific firmware loader ---------------------------- -.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c +.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c :doc: GuC-specific firmware loader -.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c +.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c :internal: GuC-based command submission -- GitLab From 251552a2b0d454badc8f486e6d79100970c744b0 Mon Sep 17 00:00:00 2001 From: Jaejoong Kim Date: Mon, 4 Dec 2017 15:31:48 +0900 Subject: [PATCH 0510/2547] ALSA: usb-audio: Fix out-of-bound error The snd_usb_copy_string_desc() retrieves the usb string corresponding to the index number through the usb_string(). The problem is that the usb_string() returns the length of the string (>= 0) when successful, but it can also return a negative value about the error case or status of usb_control_msg(). If iClockSource is '0' as shown below, usb_string() will returns -EINVAL. This will result in '0' being inserted into buf[-22], and the following KASAN out-of-bound error message will be output. AudioControl Interface Descriptor: bLength 8 bDescriptorType 36 bDescriptorSubtype 10 (CLOCK_SOURCE) bClockID 1 bmAttributes 0x07 Internal programmable Clock (synced to SOF) bmControls 0x07 Clock Frequency Control (read/write) Clock Validity Control (read-only) bAssocTerminal 0 iClockSource 0 To fix it, check usb_string()'return value and bail out. ================================================================== BUG: KASAN: stack-out-of-bounds in parse_audio_unit+0x1327/0x1960 [snd_usb_audio] Write of size 1 at addr ffff88007e66735a by task systemd-udevd/18376 CPU: 0 PID: 18376 Comm: systemd-udevd Not tainted 4.13.0+ #3 Hardware name: LG Electronics 15N540-RFLGL/White Tip Mountain, BIOS 15N5 Call Trace: dump_stack+0x63/0x8d print_address_description+0x70/0x290 ? parse_audio_unit+0x1327/0x1960 [snd_usb_audio] kasan_report+0x265/0x350 __asan_store1+0x4a/0x50 parse_audio_unit+0x1327/0x1960 [snd_usb_audio] ? save_stack+0xb5/0xd0 ? save_stack_trace+0x1b/0x20 ? save_stack+0x46/0xd0 ? kasan_kmalloc+0xad/0xe0 ? kmem_cache_alloc_trace+0xff/0x230 ? snd_usb_create_mixer+0xb0/0x4b0 [snd_usb_audio] ? usb_audio_probe+0x4de/0xf40 [snd_usb_audio] ? usb_probe_interface+0x1f5/0x440 ? driver_probe_device+0x3ed/0x660 ? build_feature_ctl+0xb10/0xb10 [snd_usb_audio] ? save_stack_trace+0x1b/0x20 ? init_object+0x69/0xa0 ? snd_usb_find_csint_desc+0xa8/0xf0 [snd_usb_audio] snd_usb_mixer_controls+0x1dc/0x370 [snd_usb_audio] ? build_audio_procunit+0x890/0x890 [snd_usb_audio] ? snd_usb_create_mixer+0xb0/0x4b0 [snd_usb_audio] ? kmem_cache_alloc_trace+0xff/0x230 ? usb_ifnum_to_if+0xbd/0xf0 snd_usb_create_mixer+0x25b/0x4b0 [snd_usb_audio] ? snd_usb_create_stream+0x255/0x2c0 [snd_usb_audio] usb_audio_probe+0x4de/0xf40 [snd_usb_audio] ? snd_usb_autosuspend.part.7+0x30/0x30 [snd_usb_audio] ? __pm_runtime_idle+0x90/0x90 ? kernfs_activate+0xa6/0xc0 ? usb_match_one_id_intf+0xdc/0x130 ? __pm_runtime_set_status+0x2d4/0x450 usb_probe_interface+0x1f5/0x440 Cc: Signed-off-by: Jaejoong Kim Signed-off-by: Takashi Iwai --- sound/usb/mixer.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c index 0537c6322990..8e18f7ec51f4 100644 --- a/sound/usb/mixer.c +++ b/sound/usb/mixer.c @@ -204,6 +204,10 @@ static int snd_usb_copy_string_desc(struct mixer_build *state, int index, char *buf, int maxlen) { int len = usb_string(state->chip->dev, index, buf, maxlen - 1); + + if (len < 0) + return 0; + buf[len] = 0; return len; } -- GitLab From 89b89d121ffcf8d9546633b98ded9d18b8f75891 Mon Sep 17 00:00:00 2001 From: Jaejoong Kim Date: Mon, 4 Dec 2017 15:31:49 +0900 Subject: [PATCH 0511/2547] ALSA: usb-audio: Add check return value for usb_string() snd_usb_copy_string_desc() returns zero if usb_string() fails. In case of failure, we need to check the snd_usb_copy_string_desc()'s return value and add an exception case Signed-off-by: Jaejoong Kim Cc: Signed-off-by: Takashi Iwai --- sound/usb/mixer.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c index 8e18f7ec51f4..afc208e1c756 100644 --- a/sound/usb/mixer.c +++ b/sound/usb/mixer.c @@ -2178,13 +2178,14 @@ static int parse_audio_selector_unit(struct mixer_build *state, int unitid, if (len) ; else if (nameid) - snd_usb_copy_string_desc(state, nameid, kctl->id.name, + len = snd_usb_copy_string_desc(state, nameid, kctl->id.name, sizeof(kctl->id.name)); - else { + else len = get_term_name(state, &state->oterm, kctl->id.name, sizeof(kctl->id.name), 0); - if (!len) - strlcpy(kctl->id.name, "USB", sizeof(kctl->id.name)); + + if (!len) { + strlcpy(kctl->id.name, "USB", sizeof(kctl->id.name)); if (desc->bDescriptorSubtype == UAC2_CLOCK_SELECTOR) append_ctl_name(kctl, " Clock Source"); -- GitLab From 4b380c42f7d00a395feede754f0bc2292eebe6e5 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Sun, 3 Dec 2017 12:12:45 -0800 Subject: [PATCH 0512/2547] netfilter: nfnetlink_cthelper: Add missing permission checks The capability check in nfnetlink_rcv() verifies that the caller has CAP_NET_ADMIN in the namespace that "owns" the netlink socket. However, nfnl_cthelper_list is shared by all net namespaces on the system. An unprivileged user can create user and net namespaces in which he holds CAP_NET_ADMIN to bypass the netlink_net_capable() check: $ nfct helper list nfct v1.4.4: netlink error: Operation not permitted $ vpnns -- nfct helper list { .name = ftp, .queuenum = 0, .l3protonum = 2, .l4protonum = 6, .priv_data_len = 24, .status = enabled, }; Add capable() checks in nfnetlink_cthelper, as this is cleaner than trying to generalize the solution. Signed-off-by: Kevin Cernekee Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nfnetlink_cthelper.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/net/netfilter/nfnetlink_cthelper.c b/net/netfilter/nfnetlink_cthelper.c index 41628b393673..d33ce6d5ebce 100644 --- a/net/netfilter/nfnetlink_cthelper.c +++ b/net/netfilter/nfnetlink_cthelper.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -407,6 +408,9 @@ static int nfnl_cthelper_new(struct net *net, struct sock *nfnl, struct nfnl_cthelper *nlcth; int ret = 0; + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + if (!tb[NFCTH_NAME] || !tb[NFCTH_TUPLE]) return -EINVAL; @@ -611,6 +615,9 @@ static int nfnl_cthelper_get(struct net *net, struct sock *nfnl, struct nfnl_cthelper *nlcth; bool tuple_set = false; + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + if (nlh->nlmsg_flags & NLM_F_DUMP) { struct netlink_dump_control c = { .dump = nfnl_cthelper_dump_table, @@ -678,6 +685,9 @@ static int nfnl_cthelper_del(struct net *net, struct sock *nfnl, struct nfnl_cthelper *nlcth, *n; int j = 0, ret; + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + if (tb[NFCTH_NAME]) helper_name = nla_data(tb[NFCTH_NAME]); -- GitLab From 6ab405114b0b229151ef06f4e31c7834dd09d0c0 Mon Sep 17 00:00:00 2001 From: Jann Horn Date: Fri, 1 Dec 2017 01:46:07 +0100 Subject: [PATCH 0513/2547] netfilter: xt_bpf: add overflow checks Check whether inputs from userspace are too long (explicit length field too big or string not null-terminated) to avoid out-of-bounds reads. As far as I can tell, this can at worst lead to very limited kernel heap memory disclosure or oopses. This bug can be triggered by an unprivileged user even if the xt_bpf module is not loaded: iptables is available in network namespaces, and the xt_bpf module can be autoloaded. Triggering the bug with a classic BPF filter with fake length 0x1000 causes the following KASAN report: ================================================================== BUG: KASAN: slab-out-of-bounds in bpf_prog_create+0x84/0xf0 Read of size 32768 at addr ffff8801eff2c494 by task test/4627 CPU: 0 PID: 4627 Comm: test Not tainted 4.15.0-rc1+ #1 [...] Call Trace: dump_stack+0x5c/0x85 print_address_description+0x6a/0x260 kasan_report+0x254/0x370 ? bpf_prog_create+0x84/0xf0 memcpy+0x1f/0x50 bpf_prog_create+0x84/0xf0 bpf_mt_check+0x90/0xd6 [xt_bpf] [...] Allocated by task 4627: kasan_kmalloc+0xa0/0xd0 __kmalloc_node+0x47/0x60 xt_alloc_table_info+0x41/0x70 [x_tables] [...] The buggy address belongs to the object at ffff8801eff2c3c0 which belongs to the cache kmalloc-2048 of size 2048 The buggy address is located 212 bytes inside of 2048-byte region [ffff8801eff2c3c0, ffff8801eff2cbc0) [...] ================================================================== Fixes: e6f30c731718 ("netfilter: x_tables: add xt_bpf match") Signed-off-by: Jann Horn Signed-off-by: Pablo Neira Ayuso --- net/netfilter/xt_bpf.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/net/netfilter/xt_bpf.c b/net/netfilter/xt_bpf.c index 041da0d9c06f..1f7fbd3c7e5a 100644 --- a/net/netfilter/xt_bpf.c +++ b/net/netfilter/xt_bpf.c @@ -27,6 +27,9 @@ static int __bpf_mt_check_bytecode(struct sock_filter *insns, __u16 len, { struct sock_fprog_kern program; + if (len > XT_BPF_MAX_NUM_INSTR) + return -EINVAL; + program.len = len; program.filter = insns; @@ -55,6 +58,9 @@ static int __bpf_mt_check_path(const char *path, struct bpf_prog **ret) mm_segment_t oldfs = get_fs(); int retval, fd; + if (strnlen(path, XT_BPF_PATH_MAX) == XT_BPF_PATH_MAX) + return -EINVAL; + set_fs(KERNEL_DS); fd = bpf_obj_get_user(path, 0); set_fs(oldfs); -- GitLab From 912d7985f3cef1b901a4fd9fede549b919fe7ac3 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 9 Nov 2017 16:35:35 -0600 Subject: [PATCH 0514/2547] ARM: dts: rockchip: fix rk3288 iep-IOMMU interrupts property cells The interrupts property in the iep-IOMMU node for the rk3288 dts file has a spurious extra cell causing a dtc warning: Warning (interrupts_property): interrupts size is (16), expected multiple of 12 in /iommu@ff900800 Remove the extra cell. Signed-off-by: Rob Herring Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index cd24894ee5c6..6102e4e7f35c 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -956,7 +956,7 @@ iep_mmu: iommu@ff900800 { compatible = "rockchip,iommu"; reg = <0x0 0xff900800 0x0 0x40>; - interrupts = ; + interrupts = ; interrupt-names = "iep_mmu"; #iommu-cells = <0>; status = "disabled"; -- GitLab From 5ba7dcfe77037b67016263ea597a8b431692ecab Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Sun, 3 Dec 2017 11:26:45 +0100 Subject: [PATCH 0515/2547] batman-adv: Fix lock for ogm cnt access in batadv_iv_ogm_calc_tq The originator node object orig_neigh_node is used to when accessing the bcast_own(_sum) and real_packet_count information. The access to them has to be protected with the spinlock in orig_neigh_node. But the function uses the lock in orig_node instead. This is incorrect because they could be two different originator node objects. Fixes: 0ede9f41b217 ("batman-adv: protect bit operations to count OGMs with spinlock") Signed-off-by: Sven Eckelmann Signed-off-by: Simon Wunderlich --- net/batman-adv/bat_iv_ogm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/batman-adv/bat_iv_ogm.c b/net/batman-adv/bat_iv_ogm.c index 1b659ab652fb..bbe8414b6ee7 100644 --- a/net/batman-adv/bat_iv_ogm.c +++ b/net/batman-adv/bat_iv_ogm.c @@ -1214,7 +1214,7 @@ static bool batadv_iv_ogm_calc_tq(struct batadv_orig_node *orig_node, orig_node->last_seen = jiffies; /* find packet count of corresponding one hop neighbor */ - spin_lock_bh(&orig_node->bat_iv.ogm_cnt_lock); + spin_lock_bh(&orig_neigh_node->bat_iv.ogm_cnt_lock); if_num = if_incoming->if_num; orig_eq_count = orig_neigh_node->bat_iv.bcast_own_sum[if_num]; neigh_ifinfo = batadv_neigh_ifinfo_new(neigh_node, if_outgoing); @@ -1224,7 +1224,7 @@ static bool batadv_iv_ogm_calc_tq(struct batadv_orig_node *orig_node, } else { neigh_rq_count = 0; } - spin_unlock_bh(&orig_node->bat_iv.ogm_cnt_lock); + spin_unlock_bh(&orig_neigh_node->bat_iv.ogm_cnt_lock); /* pay attention to not get a value bigger than 100 % */ if (orig_eq_count > neigh_rq_count) -- GitLab From faf4a3ff36137aaa8de1a8da99a92f6e712903f1 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 13 Oct 2017 16:22:19 +0100 Subject: [PATCH 0516/2547] dt-bindings: display: rcar-du: Document R8A774[35] DU Add device tree bindings for r8a7743 and r8a7745 DUs. r8a7743 DU is similar to the one from r8a7791, r8a7745 DU is similar to the one from r8a7794. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Laurent Pinchart [Don't reference R8A779[0123456] and R8A774[35] explicitly] [Number all DPAD, HDMI and LVDS ports] Signed-off-by: Laurent Pinchart --- .../bindings/display/renesas,du.txt | 30 +++++++++++-------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt index 4bbd1e9bf3be..cd48aba3bc8c 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.txt +++ b/Documentation/devicetree/bindings/display/renesas,du.txt @@ -3,6 +3,8 @@ Required Properties: - compatible: must be one of the following. + - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU + - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU @@ -27,10 +29,10 @@ Required Properties: - clock-names: Name of the clocks. This property is model-dependent. - R8A7779 uses a single functional clock. The clock doesn't need to be named. - - R8A779[0123456] use one functional clock per channel and one clock per - LVDS encoder (if available). The functional clocks must be named "du.x" - with "x" being the channel numerical index. The LVDS clocks must be - named "lvds.x" with "x" being the LVDS encoder numerical index. + - All other DU instances use one functional clock per channel and one + clock per LVDS encoder (if available). The functional clocks must be + named "du.x" with "x" being the channel numerical index. The LVDS clocks + must be named "lvds.x" with "x" being the LVDS encoder numerical index. - In addition to the functional and encoder clocks, all DU versions also support externally supplied pixel clocks. Those clocks are optional. When supplied they must be named "dclkin.x" with "x" being the input @@ -49,16 +51,18 @@ bindings specified in Documentation/devicetree/bindings/graph.txt. The following table lists for each supported model the port number corresponding to each DU output. - Port 0 Port1 Port2 Port3 + Port0 Port1 Port2 Port3 ----------------------------------------------------------------------------- - R8A7779 (H1) DPAD 0 DPAD 1 - - - R8A7790 (H2) DPAD LVDS 0 LVDS 1 - - R8A7791 (M2-W) DPAD LVDS 0 - - - R8A7792 (V2H) DPAD 0 DPAD 1 - - - R8A7793 (M2-N) DPAD LVDS 0 - - - R8A7794 (E2) DPAD 0 DPAD 1 - - - R8A7795 (H3) DPAD HDMI 0 HDMI 1 LVDS - R8A7796 (M3-W) DPAD HDMI LVDS - + R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - - + R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - - + R8A7779 (R-Car H1) DPAD 0 DPAD 1 - - + R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 - + R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - - + R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - - + R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - - + R8A7794 (R-Car E2) DPAD 0 DPAD 1 - - + R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0 + R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 - Example: R8A7795 (R-Car H3) ES2.0 DU -- GitLab From 36a46da90212ddeeb78c2f902caaca264d8496a9 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 13 Oct 2017 16:22:20 +0100 Subject: [PATCH 0517/2547] drm: rcar-du: Add R8A7743 support Add support for the R8A7743 DU (which is very similar to the R8A7791 DU); it has 1 DPAD (RGB) output and 1 LVDS output. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index d2f29e6b1112..3db5e8df4ce6 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -34,6 +34,27 @@ * Device Information */ +static const struct rcar_du_device_info rzg1_du_r8a7743_info = { + .gen = 2, + .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK + | RCAR_DU_FEATURE_EXT_CTRL_REGS, + .num_crtcs = 2, + .routes = { + /* + * R8A7743 has one RGB output and one LVDS output + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(1) | BIT(0), + .port = 0, + }, + [RCAR_DU_OUTPUT_LVDS0] = { + .possible_crtcs = BIT(0), + .port = 1, + }, + }, + .num_lvds = 1, +}; + static const struct rcar_du_device_info rcar_du_r8a7779_info = { .gen = 2, .features = 0, @@ -207,6 +228,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = { }; static const struct of_device_id rcar_du_of_table[] = { + { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info }, { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info }, { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info }, { .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info }, -- GitLab From cdd90700157293dc7cb67d932b4f2fc44bd2a623 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 13 Oct 2017 16:22:22 +0100 Subject: [PATCH 0518/2547] drm: rcar-du: Add R8A7745 support Add support for the R8A7745 DU (which is very similar to the R8A7794 DU); it has 2 RGB outputs. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 3db5e8df4ce6..faa5b328986a 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -55,6 +55,27 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = { .num_lvds = 1, }; +static const struct rcar_du_device_info rzg1_du_r8a7745_info = { + .gen = 2, + .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK + | RCAR_DU_FEATURE_EXT_CTRL_REGS, + .num_crtcs = 2, + .routes = { + /* + * R8A7745 has two RGB outputs + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(0), + .port = 0, + }, + [RCAR_DU_OUTPUT_DPAD1] = { + .possible_crtcs = BIT(1), + .port = 1, + }, + }, + .num_lvds = 0, +}; + static const struct rcar_du_device_info rcar_du_r8a7779_info = { .gen = 2, .features = 0, @@ -229,6 +250,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = { static const struct of_device_id rcar_du_of_table[] = { { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info }, + { .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info }, { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info }, { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info }, { .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info }, -- GitLab From e2f930aaa3519865bbdfa1a37d4974a717c1fa09 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 15 Aug 2017 15:36:19 +0300 Subject: [PATCH 0519/2547] drm: rcar-du: Don't set connector DPMS property Since commit 4a97a3da420b ("drm: Don't update property values for atomic drivers") atomic drivers must not update property values as properties are read from the state instead. To catch remaining users, the drm_object_property_set_value() function now throws a warning when called by atomic drivers on non-immutable properties, and we hit that warning when creating connectors. The easy fix is to just remove the drm_object_property_set_value() as it is used here to set the initial value of the connector's DPMS property to OFF. The DPMS property applies on top of the connector's state crtc pointer (initialized to NULL) that is the main connector on/off control, and should thus default to ON. Fixes: 4a97a3da420b ("drm: Don't update property values for atomic drivers") Signed-off-by: Laurent Pinchart Reviewed-by: Daniel Vetter --- drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c index b373ad48ef5f..e96f2df0c305 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c @@ -79,10 +79,6 @@ int rcar_du_lvds_connector_init(struct rcar_du_device *rcdu, drm_connector_helper_add(connector, &connector_helper_funcs); - connector->dpms = DRM_MODE_DPMS_OFF; - drm_object_property_set_value(&connector->base, - rcdu->ddev->mode_config.dpms_property, DRM_MODE_DPMS_OFF); - ret = drm_mode_connector_attach_encoder(connector, encoder); if (ret < 0) return ret; -- GitLab From 7912dee7775e4c7590c227b4163bdb635bc50dd6 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Fri, 15 Sep 2017 17:42:06 +0100 Subject: [PATCH 0520/2547] drm: rcar-du: Implement system suspend/resume support To support system suspend operations we must ensure the hardware is stopped, and resumed explicitly from the suspend and resume handlers. Implement suspend and resume functions using the DRM atomic helper functions. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 18 +++++++++++++++--- drivers/gpu/drm/rcar-du/rcar_du_drv.h | 1 + 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index faa5b328986a..6e02c762a557 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -309,9 +310,19 @@ static struct drm_driver rcar_du_driver = { static int rcar_du_pm_suspend(struct device *dev) { struct rcar_du_device *rcdu = dev_get_drvdata(dev); + struct drm_atomic_state *state; drm_kms_helper_poll_disable(rcdu->ddev); - /* TODO Suspend the CRTC */ + drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, true); + + state = drm_atomic_helper_suspend(rcdu->ddev); + if (IS_ERR(state)) { + drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, false); + drm_kms_helper_poll_enable(rcdu->ddev); + return PTR_ERR(state); + } + + rcdu->suspend_state = state; return 0; } @@ -320,9 +331,10 @@ static int rcar_du_pm_resume(struct device *dev) { struct rcar_du_device *rcdu = dev_get_drvdata(dev); - /* TODO Resume the CRTC */ - + drm_atomic_helper_resume(rcdu->ddev, rcdu->suspend_state); + drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, false); drm_kms_helper_poll_enable(rcdu->ddev); + return 0; } #endif diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h index f8cd79488ece..f400fde65a0c 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h @@ -81,6 +81,7 @@ struct rcar_du_device { struct drm_device *ddev; struct drm_fbdev_cma *fbdev; + struct drm_atomic_state *suspend_state; struct rcar_du_crtc crtcs[RCAR_DU_MAX_CRTCS]; unsigned int num_crtcs; -- GitLab From cf05f74ef40ed608e554f635799e831995213215 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Fri, 15 Sep 2017 17:42:07 +0100 Subject: [PATCH 0521/2547] drm: rcar-du: Remove unused CRTC suspend/resume functions An early implementation of suspend-resume helpers are available in the CRTC module, however they are unused and no longer needed. With suspend and resume handled by the core DRM atomic helpers, we can remove the unused functions. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 35 -------------------------- 1 file changed, 35 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 301ea1a8018e..b492063a6e1f 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -557,41 +557,6 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc) rcar_du_group_start_stop(rcrtc->group, false); } -void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc) -{ - if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) - rcar_du_vsp_disable(rcrtc); - - rcar_du_crtc_stop(rcrtc); - rcar_du_crtc_put(rcrtc); -} - -void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc) -{ - unsigned int i; - - if (!rcrtc->crtc.state->active) - return; - - rcar_du_crtc_get(rcrtc); - rcar_du_crtc_setup(rcrtc); - - /* Commit the planes state. */ - if (!rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) { - for (i = 0; i < rcrtc->group->num_planes; ++i) { - struct rcar_du_plane *plane = &rcrtc->group->planes[i]; - - if (plane->plane.state->crtc != &rcrtc->crtc) - continue; - - rcar_du_plane_setup(plane); - } - } - - rcar_du_crtc_update_planes(rcrtc); - rcar_du_crtc_start(rcrtc); -} - /* ----------------------------------------------------------------------------- * CRTC Functions */ -- GitLab From dd286a531461748ff1b1b3f1d7255389a131ed27 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 15 Aug 2017 14:20:11 +0300 Subject: [PATCH 0522/2547] v4l: vsp1: Start and stop DRM pipeline independently of planes The KMS API supports enabling a CRTC without any plane. To enable that use case, we need to start the pipeline when configuring the LIF, instead of when enabling the first plane. Signed-off-by: Laurent Pinchart Tested-by: Kieran Bingham Reviewed-by: Kieran Bingham Acked-by: Mauro Carvalho Chehab --- drivers/media/platform/vsp1/vsp1_drm.c | 37 +++++++++++++++++++------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c index 4dfbeac8f42c..7ce69f23f50a 100644 --- a/drivers/media/platform/vsp1/vsp1_drm.c +++ b/drivers/media/platform/vsp1/vsp1_drm.c @@ -84,8 +84,12 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index, struct vsp1_drm_pipeline *drm_pipe; struct vsp1_pipeline *pipe; struct vsp1_bru *bru; + struct vsp1_entity *entity; + struct vsp1_entity *next; + struct vsp1_dl_list *dl; struct v4l2_subdev_format format; const char *bru_name; + unsigned long flags; unsigned int i; int ret; @@ -250,6 +254,29 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index, vsp1_write(vsp1, VI6_DISP_IRQ_STA, 0); vsp1_write(vsp1, VI6_DISP_IRQ_ENB, 0); + /* Configure all entities in the pipeline. */ + dl = vsp1_dl_list_get(pipe->output->dlm); + + list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) { + vsp1_entity_route_setup(entity, pipe, dl); + + if (entity->ops->configure) { + entity->ops->configure(entity, pipe, dl, + VSP1_ENTITY_PARAMS_INIT); + entity->ops->configure(entity, pipe, dl, + VSP1_ENTITY_PARAMS_RUNTIME); + entity->ops->configure(entity, pipe, dl, + VSP1_ENTITY_PARAMS_PARTITION); + } + } + + vsp1_dl_list_commit(dl); + + /* Start the pipeline. */ + spin_lock_irqsave(&pipe->irqlock, flags); + vsp1_pipeline_run(pipe); + spin_unlock_irqrestore(&pipe->irqlock, flags); + dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__); return 0; @@ -488,7 +515,6 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index) struct vsp1_entity *next; struct vsp1_dl_list *dl; const char *bru_name; - unsigned long flags; unsigned int i; int ret; @@ -570,15 +596,6 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index) } vsp1_dl_list_commit(dl); - - /* Start or stop the pipeline if needed. */ - if (!drm_pipe->enabled && pipe->num_inputs) { - spin_lock_irqsave(&pipe->irqlock, flags); - vsp1_pipeline_run(pipe); - spin_unlock_irqrestore(&pipe->irqlock, flags); - } else if (drm_pipe->enabled && !pipe->num_inputs) { - vsp1_pipeline_stop(pipe); - } } EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush); -- GitLab From 9c893a61b79d38b8997cc417a6b359222cf92414 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 15 Aug 2017 18:45:21 +0300 Subject: [PATCH 0523/2547] drm: rcar-du: Share plane atomic check code between Gen2 and Gen3 The plane atomic check implementation is identical on Gen2 (DU planes) and Gen3 (VSP planes), but two separate functions exist as they operate on different data structures. Refactor the code to share the implementation. Signed-off-by: Laurent Pinchart Tested-by: Kieran Bingham Reviewed-by: Kieran Bingham --- drivers/gpu/drm/rcar-du/rcar_du_plane.c | 27 ++++++++++++++++--------- drivers/gpu/drm/rcar-du/rcar_du_plane.h | 4 ++++ drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 22 +------------------- 3 files changed, 22 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c index 61833cc1c699..4f076c364f25 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c @@ -565,27 +565,26 @@ void __rcar_du_plane_setup(struct rcar_du_group *rgrp, } } -static int rcar_du_plane_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state) +int __rcar_du_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state, + const struct rcar_du_format_info **format) { - struct rcar_du_plane_state *rstate = to_rcar_plane_state(state); - struct rcar_du_plane *rplane = to_rcar_plane(plane); - struct rcar_du_device *rcdu = rplane->group->dev; + struct drm_device *dev = plane->dev; if (!state->fb || !state->crtc) { - rstate->format = NULL; + *format = NULL; return 0; } if (state->src_w >> 16 != state->crtc_w || state->src_h >> 16 != state->crtc_h) { - dev_dbg(rcdu->dev, "%s: scaling not supported\n", __func__); + dev_dbg(dev->dev, "%s: scaling not supported\n", __func__); return -EINVAL; } - rstate->format = rcar_du_format_info(state->fb->format->format); - if (rstate->format == NULL) { - dev_dbg(rcdu->dev, "%s: unsupported format %08x\n", __func__, + *format = rcar_du_format_info(state->fb->format->format); + if (*format == NULL) { + dev_dbg(dev->dev, "%s: unsupported format %08x\n", __func__, state->fb->format->format); return -EINVAL; } @@ -593,6 +592,14 @@ static int rcar_du_plane_atomic_check(struct drm_plane *plane, return 0; } +static int rcar_du_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct rcar_du_plane_state *rstate = to_rcar_plane_state(state); + + return __rcar_du_plane_atomic_check(plane, state, &rstate->format); +} + static void rcar_du_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/rcar-du/rcar_du_plane.h index f62e09f195de..890321b4665d 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.h @@ -73,6 +73,10 @@ to_rcar_plane_state(struct drm_plane_state *state) int rcar_du_atomic_check_planes(struct drm_device *dev, struct drm_atomic_state *state); +int __rcar_du_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state, + const struct rcar_du_format_info **format); + int rcar_du_planes_init(struct rcar_du_group *rgrp); void __rcar_du_plane_setup(struct rcar_du_group *rgrp, diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c index 2c96147bc444..dd66dcb8da23 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c @@ -268,28 +268,8 @@ static int rcar_du_vsp_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { struct rcar_du_vsp_plane_state *rstate = to_rcar_vsp_plane_state(state); - struct rcar_du_vsp_plane *rplane = to_rcar_vsp_plane(plane); - struct rcar_du_device *rcdu = rplane->vsp->dev; - - if (!state->fb || !state->crtc) { - rstate->format = NULL; - return 0; - } - if (state->src_w >> 16 != state->crtc_w || - state->src_h >> 16 != state->crtc_h) { - dev_dbg(rcdu->dev, "%s: scaling not supported\n", __func__); - return -EINVAL; - } - - rstate->format = rcar_du_format_info(state->fb->format->format); - if (rstate->format == NULL) { - dev_dbg(rcdu->dev, "%s: unsupported format %08x\n", __func__, - state->fb->format->format); - return -EINVAL; - } - - return 0; + return __rcar_du_plane_atomic_check(plane, state, &rstate->format); } static void rcar_du_vsp_plane_atomic_update(struct drm_plane *plane, -- GitLab From 5a93bae2c382c588f437ce0395e8032ae287dc36 Mon Sep 17 00:00:00 2001 From: Chunyu Hu Date: Thu, 19 Oct 2017 14:32:33 +0800 Subject: [PATCH 0524/2547] tracing: Fix code comments in trace.c Naming in code comments for tracing_snapshot, tracing_snapshot_alloc and trace_pid_filter_add_remove_task don't match the real function names. And latency_trace has been removed from tracing directory. Fix them. Link: http://lkml.kernel.org/r/1508394753-20887-1-git-send-email-chuhu@redhat.com Fixes: cab5037 ("tracing/ftrace: Enable snapshot function trigger") Fixes: 886b5b7 ("tracing: remove /debug/tracing/latency_trace") Signed-off-by: Chunyu Hu [ Replaced /sys/kernel/debug/tracing with /sys/kerne/tracing ] Signed-off-by: Steven Rostedt (VMware) --- kernel/trace/trace.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index 73e67b68c53b..5815ec16edd4 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -362,7 +362,7 @@ trace_ignore_this_task(struct trace_pid_list *filtered_pids, struct task_struct } /** - * trace_pid_filter_add_remove - Add or remove a task from a pid_list + * trace_pid_filter_add_remove_task - Add or remove a task from a pid_list * @pid_list: The list to modify * @self: The current task for fork or NULL for exit * @task: The task to add or remove @@ -925,7 +925,7 @@ static void tracing_snapshot_instance(struct trace_array *tr) } /** - * trace_snapshot - take a snapshot of the current buffer. + * tracing_snapshot - take a snapshot of the current buffer. * * This causes a swap between the snapshot buffer and the current live * tracing buffer. You can use this to take snapshots of the live @@ -1004,9 +1004,9 @@ int tracing_alloc_snapshot(void) EXPORT_SYMBOL_GPL(tracing_alloc_snapshot); /** - * trace_snapshot_alloc - allocate and take a snapshot of the current buffer. + * tracing_snapshot_alloc - allocate and take a snapshot of the current buffer. * - * This is similar to trace_snapshot(), but it will allocate the + * This is similar to tracing_snapshot(), but it will allocate the * snapshot buffer if it isn't already allocated. Use this only * where it is safe to sleep, as the allocation may sleep. * @@ -1303,7 +1303,7 @@ unsigned long __read_mostly tracing_thresh; /* * Copy the new maximum trace into the separate maximum-trace * structure. (this way the maximum trace is permanently saved, - * for later retrieval via /sys/kernel/debug/tracing/latency_trace) + * for later retrieval via /sys/kernel/tracing/tracing_max_latency) */ static void __update_max_tr(struct trace_array *tr, struct task_struct *tsk, int cpu) -- GitLab From 250d0c7754aa37c6443f07f1f5f591e2806295d8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 19 Oct 2017 10:32:13 +0200 Subject: [PATCH 0525/2547] tracing: always define trace_{irq,preempt}_{enable_disable} We get a build error in the irqsoff tracer in some configurations: kernel/trace/trace_irqsoff.c: In function 'trace_preempt_on': kernel/trace/trace_irqsoff.c:855:2: error: implicit declaration of function 'trace_preempt_enable_rcuidle'; did you mean 'trace_irq_enable_rcuidle'? [-Werror=implicit-function-declaration] trace_preempt_enable_rcuidle(a0, a1); The problem is that trace_preempt_enable_rcuidle() has different definition based on multiple Kconfig symbols, but not all combinations have a valid definition. This changes the conditions so that we always get exactly one definition of each of the four tracing macros. I have not tried to verify that these definitions are sensible, but now we can build all randconfig combinations again. Link: http://lkml.kernel.org/r/20171019083230.2450779-1-arnd@arndb.de Fixes: d59158162e03 ("tracing: Add support for preempt and irq enable/disable events") Acked-by: Joel Fernandes Signed-off-by: Arnd Bergmann Signed-off-by: Steven Rostedt (VMware) --- include/trace/events/preemptirq.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/include/trace/events/preemptirq.h b/include/trace/events/preemptirq.h index f5024c560d8f..9c4eb33c5a1d 100644 --- a/include/trace/events/preemptirq.h +++ b/include/trace/events/preemptirq.h @@ -56,15 +56,18 @@ DEFINE_EVENT(preemptirq_template, preempt_enable, #include -#else /* !CONFIG_PREEMPTIRQ_EVENTS */ +#endif /* !CONFIG_PREEMPTIRQ_EVENTS */ +#if !defined(CONFIG_PREEMPTIRQ_EVENTS) || defined(CONFIG_PROVE_LOCKING) #define trace_irq_enable(...) #define trace_irq_disable(...) -#define trace_preempt_enable(...) -#define trace_preempt_disable(...) #define trace_irq_enable_rcuidle(...) #define trace_irq_disable_rcuidle(...) +#endif + +#if !defined(CONFIG_PREEMPTIRQ_EVENTS) || !defined(CONFIG_DEBUG_PREEMPT) +#define trace_preempt_enable(...) +#define trace_preempt_disable(...) #define trace_preempt_enable_rcuidle(...) #define trace_preempt_disable_rcuidle(...) - #endif -- GitLab From 90e406f96f630c07d631a021fd4af10aac913e77 Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Thu, 30 Nov 2017 11:39:43 +0800 Subject: [PATCH 0526/2547] tracing: Allocate mask_str buffer dynamically The default NR_CPUS can be very large, but actual possible nr_cpu_ids usually is very small. For my x86 distribution, the NR_CPUS is 8192 and nr_cpu_ids is 4. About 2 pages are wasted. Most machines don't have so many CPUs, so define a array with NR_CPUS just wastes memory. So let's allocate the buffer dynamically when need. With this change, the mutext tracing_cpumask_update_lock also can be removed now, which was used to protect mask_str. Link: http://lkml.kernel.org/r/1512013183-19107-1-git-send-email-changbin.du@intel.com Fixes: 36dfe9252bd4c ("ftrace: make use of tracing_cpumask") Cc: stable@vger.kernel.org Signed-off-by: Changbin Du Signed-off-by: Steven Rostedt (VMware) --- kernel/trace/trace.c | 29 +++++++++-------------------- 1 file changed, 9 insertions(+), 20 deletions(-) diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index 5815ec16edd4..9f3f043ba3b7 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -4178,37 +4178,30 @@ static const struct file_operations show_traces_fops = { .llseek = seq_lseek, }; -/* - * The tracer itself will not take this lock, but still we want - * to provide a consistent cpumask to user-space: - */ -static DEFINE_MUTEX(tracing_cpumask_update_lock); - -/* - * Temporary storage for the character representation of the - * CPU bitmask (and one more byte for the newline): - */ -static char mask_str[NR_CPUS + 1]; - static ssize_t tracing_cpumask_read(struct file *filp, char __user *ubuf, size_t count, loff_t *ppos) { struct trace_array *tr = file_inode(filp)->i_private; + char *mask_str; int len; - mutex_lock(&tracing_cpumask_update_lock); + len = snprintf(NULL, 0, "%*pb\n", + cpumask_pr_args(tr->tracing_cpumask)) + 1; + mask_str = kmalloc(len, GFP_KERNEL); + if (!mask_str) + return -ENOMEM; - len = snprintf(mask_str, count, "%*pb\n", + len = snprintf(mask_str, len, "%*pb\n", cpumask_pr_args(tr->tracing_cpumask)); if (len >= count) { count = -EINVAL; goto out_err; } - count = simple_read_from_buffer(ubuf, count, ppos, mask_str, NR_CPUS+1); + count = simple_read_from_buffer(ubuf, count, ppos, mask_str, len); out_err: - mutex_unlock(&tracing_cpumask_update_lock); + kfree(mask_str); return count; } @@ -4228,8 +4221,6 @@ tracing_cpumask_write(struct file *filp, const char __user *ubuf, if (err) goto err_unlock; - mutex_lock(&tracing_cpumask_update_lock); - local_irq_disable(); arch_spin_lock(&tr->max_lock); for_each_tracing_cpu(cpu) { @@ -4252,8 +4243,6 @@ tracing_cpumask_write(struct file *filp, const char __user *ubuf, local_irq_enable(); cpumask_copy(tr->tracing_cpumask, tracing_cpumask_new); - - mutex_unlock(&tracing_cpumask_update_lock); free_cpumask_var(tracing_cpumask_new); return count; -- GitLab From 2dde6b0034dbc050957cdb6539ce28eca57e8cdf Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 3 Nov 2017 11:39:57 +0100 Subject: [PATCH 0527/2547] tracing: make PREEMPTIRQ_EVENTS depend on TRACING When CONFIG_TRACING is disabled, the new preemptirq events tracer produces a build failure: In file included from kernel/trace/trace_irqsoff.c:17:0: kernel/trace/trace.h: In function 'trace_test_and_set_recursion': kernel/trace/trace.h:542:28: error: 'struct task_struct' has no member named 'trace_recursion' Adding an explicit dependency avoids the broken configuration. Link: http://lkml.kernel.org/r/20171103104031.270375-1-arnd@arndb.de Fixes: d59158162e03 ("tracing: Add support for preempt and irq enable/disable events") Signed-off-by: Arnd Bergmann Signed-off-by: Steven Rostedt (VMware) --- kernel/trace/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/trace/Kconfig b/kernel/trace/Kconfig index af7dad126c13..904c952ac383 100644 --- a/kernel/trace/Kconfig +++ b/kernel/trace/Kconfig @@ -164,6 +164,7 @@ config PREEMPTIRQ_EVENTS bool "Enable trace events for preempt and irq disable/enable" select TRACE_IRQFLAGS depends on DEBUG_PREEMPT || !PROVE_LOCKING + depends on TRACING default n help Enable tracing of disable and enable events for preemption and irqs. -- GitLab From c4bfd39d7fa5203d4b387c283d360e9a108e85b3 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 17 May 2017 17:14:15 -0700 Subject: [PATCH 0528/2547] ring-buffer: Remove unused function __rb_data_page_index() This fixes the following warning when building with clang: kernel/trace/ring_buffer.c:1842:1: error: unused function '__rb_data_page_index' [-Werror,-Wunused-function] Link: http://lkml.kernel.org/r/20170518001415.5223-1-mka@chromium.org Reviewed-by: Douglas Anderson Signed-off-by: Matthias Kaehlcke Signed-off-by: Steven Rostedt (VMware) --- kernel/trace/ring_buffer.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index 91874a95060d..c87766c1c204 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -1799,12 +1799,6 @@ void ring_buffer_change_overwrite(struct ring_buffer *buffer, int val) } EXPORT_SYMBOL_GPL(ring_buffer_change_overwrite); -static __always_inline void * -__rb_data_page_index(struct buffer_data_page *bpage, unsigned index) -{ - return bpage->data + index; -} - static __always_inline void *__rb_page_index(struct buffer_page *bpage, unsigned index) { return bpage->page->data + index; -- GitLab From a773d419275bf54854ca6cfda8f2594ed2790faa Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Fri, 2 Jun 2017 13:20:25 +0300 Subject: [PATCH 0529/2547] tracing: Pass export pointer as argument to ->write() By passing an export descriptor to the write function, users don't need to keep a global static pointer and can rely on container_of() to fetch their own structure. Link: http://lkml.kernel.org/r/20170602102025.5140-1-felipe.balbi@linux.intel.com Acked-by: Steven Rostedt (VMware) Reviewed-by: Chunyan Zhang Signed-off-by: Felipe Balbi Signed-off-by: Steven Rostedt (VMware) --- drivers/hwtracing/stm/ftrace.c | 6 ++++-- include/linux/trace.h | 2 +- kernel/trace/trace.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/stm/ftrace.c b/drivers/hwtracing/stm/ftrace.c index bd126a7c6da2..7da75644c750 100644 --- a/drivers/hwtracing/stm/ftrace.c +++ b/drivers/hwtracing/stm/ftrace.c @@ -42,9 +42,11 @@ static struct stm_ftrace { * @len: length of the data packet */ static void notrace -stm_ftrace_write(const void *buf, unsigned int len) +stm_ftrace_write(struct trace_export *export, const void *buf, unsigned int len) { - stm_source_write(&stm_ftrace.data, STM_FTRACE_CHAN, buf, len); + struct stm_ftrace *stm = container_of(export, struct stm_ftrace, ftrace); + + stm_source_write(&stm->data, STM_FTRACE_CHAN, buf, len); } static int stm_ftrace_link(struct stm_source_data *data) diff --git a/include/linux/trace.h b/include/linux/trace.h index d24991c1fef3..b95ffb2188ab 100644 --- a/include/linux/trace.h +++ b/include/linux/trace.h @@ -18,7 +18,7 @@ */ struct trace_export { struct trace_export __rcu *next; - void (*write)(const void *, unsigned int); + void (*write)(struct trace_export *, const void *, unsigned int); }; int register_ftrace_export(struct trace_export *export); diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index 9f3f043ba3b7..59518b8126d0 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -2415,7 +2415,7 @@ trace_process_export(struct trace_export *export, entry = ring_buffer_event_data(event); size = ring_buffer_event_length(event); - export->write(entry, size); + export->write(export, entry, size); } static DEFINE_MUTEX(ftrace_export_lock); -- GitLab From 65323ee1ab528c9c169f671944ac51896f507428 Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Mon, 4 Dec 2017 11:19:41 +0100 Subject: [PATCH 0530/2547] m68k/defconfig: fix stmark2 broken local compilation Signed-off-by: Angelo Dureghello Signed-off-by: Greg Ungerer --- arch/m68k/configs/stmark2_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/m68k/configs/stmark2_defconfig b/arch/m68k/configs/stmark2_defconfig index 55e55dbc2fb6..3d07b1de7eb0 100644 --- a/arch/m68k/configs/stmark2_defconfig +++ b/arch/m68k/configs/stmark2_defconfig @@ -5,7 +5,6 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="../uClinux-dist/romfs" # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set # CONFIG_RD_XZ is not set -- GitLab From fc396e066318c0a02208c1d3f0b62950a7714999 Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Sun, 3 Dec 2017 23:54:41 +0100 Subject: [PATCH 0531/2547] KVM: arm/arm64: Fix broken GICH_ELRSR big endian conversion We are incorrectly rearranging 32-bit words inside a 64-bit typed value for big endian systems, which would result in never marking a virtual interrupt as inactive on big endian systems (assuming 32 or fewer LRs on the hardware). Fix this by not doing any word order manipulation for the typed values. Cc: Acked-by: Christoffer Dall Signed-off-by: Christoffer Dall --- virt/kvm/arm/hyp/vgic-v2-sr.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/virt/kvm/arm/hyp/vgic-v2-sr.c b/virt/kvm/arm/hyp/vgic-v2-sr.c index a3f18d362366..d7fd46fe9efb 100644 --- a/virt/kvm/arm/hyp/vgic-v2-sr.c +++ b/virt/kvm/arm/hyp/vgic-v2-sr.c @@ -34,11 +34,7 @@ static void __hyp_text save_elrsr(struct kvm_vcpu *vcpu, void __iomem *base) else elrsr1 = 0; -#ifdef CONFIG_CPU_BIG_ENDIAN - cpu_if->vgic_elrsr = ((u64)elrsr0 << 32) | elrsr1; -#else cpu_if->vgic_elrsr = ((u64)elrsr1 << 32) | elrsr0; -#endif } static void __hyp_text save_lrs(struct kvm_vcpu *vcpu, void __iomem *base) -- GitLab From 31eb7431805493e10f4731f366cf4d4e3e952035 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Fri, 1 Dec 2017 14:58:34 +0100 Subject: [PATCH 0532/2547] PM / runtime: Fix handling of suppliers with disabled runtime PM Prevent rpm_get_suppliers() from returning an error code if runtime PM is disabled for one or more of the supplier devices it wants to runtime-resume, so as to make runtime PM work for devices with links to suppliers that don't use runtime PM (such links may be created during device enumeration even before it is known whether or not runtime PM will be enabled for the devices in question, for example). Fixes: 21d5c57b3726 (PM / runtime: Use device links) Reported-by: Adrian Hunter Signed-off-by: Rafael J. Wysocki Reviewed-by: Lukas Wunner Tested-by: Adrian Hunter --- drivers/base/power/runtime.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c index 027d159ac381..6e89b51ea3d9 100644 --- a/drivers/base/power/runtime.c +++ b/drivers/base/power/runtime.c @@ -276,7 +276,8 @@ static int rpm_get_suppliers(struct device *dev) continue; retval = pm_runtime_get_sync(link->supplier); - if (retval < 0) { + /* Ignore suppliers with disabled runtime PM. */ + if (retval < 0 && retval != -EACCES) { pm_runtime_put_noidle(link->supplier); return retval; } -- GitLab From afc567a4977b2d798e05153dd131a3c8d4758c0c Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Sat, 25 Nov 2017 00:27:26 -0500 Subject: [PATCH 0533/2547] dm table: fix regression from improper dm_dev_internal.count refcount_t conversion Multiple refcounts are needed if the device was already added. The micro-optimization of setting the refcount to 1 on first added (rather than fall thru to a common refcount_inc) lost sight of the fact that the refcount_inc is also needed for the case when the device already exists and the mode need not be upgraded. Fixes: 2a0b4682e0 ("dm: convert dm_dev_internal.count from atomic_t to refcount_t") Reported-by: Zdenek Kabelac Signed-off-by: Mike Snitzer --- drivers/md/dm-table.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/md/dm-table.c b/drivers/md/dm-table.c index 88130b5d95f9..aaffd0c0ee9a 100644 --- a/drivers/md/dm-table.c +++ b/drivers/md/dm-table.c @@ -453,14 +453,15 @@ int dm_get_device(struct dm_target *ti, const char *path, fmode_t mode, refcount_set(&dd->count, 1); list_add(&dd->list, &t->devices); + goto out; } else if (dd->dm_dev->mode != (mode | dd->dm_dev->mode)) { r = upgrade_mode(dd, mode, t->md); if (r) return r; - refcount_inc(&dd->count); } - + refcount_inc(&dd->count); +out: *result = dd->dm_dev; return 0; } -- GitLab From 7e6358d244e4706fe612a77b9c36519a33600ac0 Mon Sep 17 00:00:00 2001 From: "monty_pavel@sina.com" Date: Sat, 25 Nov 2017 01:43:50 +0800 Subject: [PATCH 0534/2547] dm: fix various targets to dm_register_target after module __init resources created A NULL pointer is seen if two concurrent "vgchange -ay -K " processes race to load the dm-thin-pool module: PID: 25992 TASK: ffff883cd7d23500 CPU: 4 COMMAND: "vgchange" #0 [ffff883cd743d600] machine_kexec at ffffffff81038fa9 0000001 [ffff883cd743d660] crash_kexec at ffffffff810c5992 0000002 [ffff883cd743d730] oops_end at ffffffff81515c90 0000003 [ffff883cd743d760] no_context at ffffffff81049f1b 0000004 [ffff883cd743d7b0] __bad_area_nosemaphore at ffffffff8104a1a5 0000005 [ffff883cd743d800] bad_area at ffffffff8104a2ce 0000006 [ffff883cd743d830] __do_page_fault at ffffffff8104aa6f 0000007 [ffff883cd743d950] do_page_fault at ffffffff81517bae 0000008 [ffff883cd743d980] page_fault at ffffffff81514f95 [exception RIP: kmem_cache_alloc+108] RIP: ffffffff8116ef3c RSP: ffff883cd743da38 RFLAGS: 00010046 RAX: 0000000000000004 RBX: ffffffff81121b90 RCX: ffff881bf1e78cc0 RDX: 0000000000000000 RSI: 00000000000000d0 RDI: 0000000000000000 RBP: ffff883cd743da68 R8: ffff881bf1a4eb00 R9: 0000000080042000 R10: 0000000000002000 R11: 0000000000000000 R12: 00000000000000d0 R13: 0000000000000000 R14: 00000000000000d0 R15: 0000000000000246 ORIG_RAX: ffffffffffffffff CS: 0010 SS: 0018 0000009 [ffff883cd743da70] mempool_alloc_slab at ffffffff81121ba5 0000010 [ffff883cd743da80] mempool_create_node at ffffffff81122083 0000011 [ffff883cd743dad0] mempool_create at ffffffff811220f4 0000012 [ffff883cd743dae0] pool_ctr at ffffffffa08de049 [dm_thin_pool] 0000013 [ffff883cd743dbd0] dm_table_add_target at ffffffffa0005f2f [dm_mod] 0000014 [ffff883cd743dc30] table_load at ffffffffa0008ba9 [dm_mod] 0000015 [ffff883cd743dc90] ctl_ioctl at ffffffffa0009dc4 [dm_mod] The race results in a NULL pointer because: Process A (vgchange -ay -K): a. send DM_LIST_VERSIONS_CMD ioctl; b. pool_target not registered; c. modprobe dm_thin_pool and wait until end. Process B (vgchange -ay -K): a. send DM_LIST_VERSIONS_CMD ioctl; b. pool_target registered; c. table_load->dm_table_add_target->pool_ctr; d. _new_mapping_cache is NULL and panic. Note: 1. process A and process B are two concurrent processes. 2. pool_target can be detected by process B but _new_mapping_cache initialization has not ended. To fix dm-thin-pool, and other targets (cache, multipath, and snapshot) with the same problem, simply dm_register_target() after all resources created during module init (as labelled with __init) are finished. Cc: stable@vger.kernel.org Signed-off-by: monty Signed-off-by: Mike Snitzer --- drivers/md/dm-cache-target.c | 12 ++++----- drivers/md/dm-mpath.c | 18 +++++++------- drivers/md/dm-snap.c | 48 ++++++++++++++++++------------------ drivers/md/dm-thin.c | 22 ++++++++--------- 4 files changed, 49 insertions(+), 51 deletions(-) diff --git a/drivers/md/dm-cache-target.c b/drivers/md/dm-cache-target.c index cf23a14f9c6a..47407e43b96a 100644 --- a/drivers/md/dm-cache-target.c +++ b/drivers/md/dm-cache-target.c @@ -3472,18 +3472,18 @@ static int __init dm_cache_init(void) { int r; - r = dm_register_target(&cache_target); - if (r) { - DMERR("cache target registration failed: %d", r); - return r; - } - migration_cache = KMEM_CACHE(dm_cache_migration, 0); if (!migration_cache) { dm_unregister_target(&cache_target); return -ENOMEM; } + r = dm_register_target(&cache_target); + if (r) { + DMERR("cache target registration failed: %d", r); + return r; + } + return 0; } diff --git a/drivers/md/dm-mpath.c b/drivers/md/dm-mpath.c index c8faa2b85842..35a2a2fa477f 100644 --- a/drivers/md/dm-mpath.c +++ b/drivers/md/dm-mpath.c @@ -1957,13 +1957,6 @@ static int __init dm_multipath_init(void) { int r; - r = dm_register_target(&multipath_target); - if (r < 0) { - DMERR("request-based register failed %d", r); - r = -EINVAL; - goto bad_register_target; - } - kmultipathd = alloc_workqueue("kmpathd", WQ_MEM_RECLAIM, 0); if (!kmultipathd) { DMERR("failed to create workqueue kmpathd"); @@ -1985,13 +1978,20 @@ static int __init dm_multipath_init(void) goto bad_alloc_kmpath_handlerd; } + r = dm_register_target(&multipath_target); + if (r < 0) { + DMERR("request-based register failed %d", r); + r = -EINVAL; + goto bad_register_target; + } + return 0; +bad_register_target: + destroy_workqueue(kmpath_handlerd); bad_alloc_kmpath_handlerd: destroy_workqueue(kmultipathd); bad_alloc_kmultipathd: - dm_unregister_target(&multipath_target); -bad_register_target: return r; } diff --git a/drivers/md/dm-snap.c b/drivers/md/dm-snap.c index 1113b42e1eda..a0613bd8ed00 100644 --- a/drivers/md/dm-snap.c +++ b/drivers/md/dm-snap.c @@ -2411,24 +2411,6 @@ static int __init dm_snapshot_init(void) return r; } - r = dm_register_target(&snapshot_target); - if (r < 0) { - DMERR("snapshot target register failed %d", r); - goto bad_register_snapshot_target; - } - - r = dm_register_target(&origin_target); - if (r < 0) { - DMERR("Origin target register failed %d", r); - goto bad_register_origin_target; - } - - r = dm_register_target(&merge_target); - if (r < 0) { - DMERR("Merge target register failed %d", r); - goto bad_register_merge_target; - } - r = init_origin_hash(); if (r) { DMERR("init_origin_hash failed."); @@ -2449,19 +2431,37 @@ static int __init dm_snapshot_init(void) goto bad_pending_cache; } + r = dm_register_target(&snapshot_target); + if (r < 0) { + DMERR("snapshot target register failed %d", r); + goto bad_register_snapshot_target; + } + + r = dm_register_target(&origin_target); + if (r < 0) { + DMERR("Origin target register failed %d", r); + goto bad_register_origin_target; + } + + r = dm_register_target(&merge_target); + if (r < 0) { + DMERR("Merge target register failed %d", r); + goto bad_register_merge_target; + } + return 0; -bad_pending_cache: - kmem_cache_destroy(exception_cache); -bad_exception_cache: - exit_origin_hash(); -bad_origin_hash: - dm_unregister_target(&merge_target); bad_register_merge_target: dm_unregister_target(&origin_target); bad_register_origin_target: dm_unregister_target(&snapshot_target); bad_register_snapshot_target: + kmem_cache_destroy(pending_cache); +bad_pending_cache: + kmem_cache_destroy(exception_cache); +bad_exception_cache: + exit_origin_hash(); +bad_origin_hash: dm_exception_store_exit(); return r; diff --git a/drivers/md/dm-thin.c b/drivers/md/dm-thin.c index 89e5dff9b4cf..f91d771fff4b 100644 --- a/drivers/md/dm-thin.c +++ b/drivers/md/dm-thin.c @@ -4355,30 +4355,28 @@ static struct target_type thin_target = { static int __init dm_thin_init(void) { - int r; + int r = -ENOMEM; pool_table_init(); + _new_mapping_cache = KMEM_CACHE(dm_thin_new_mapping, 0); + if (!_new_mapping_cache) + return r; + r = dm_register_target(&thin_target); if (r) - return r; + goto bad_new_mapping_cache; r = dm_register_target(&pool_target); if (r) - goto bad_pool_target; - - r = -ENOMEM; - - _new_mapping_cache = KMEM_CACHE(dm_thin_new_mapping, 0); - if (!_new_mapping_cache) - goto bad_new_mapping_cache; + goto bad_thin_target; return 0; -bad_new_mapping_cache: - dm_unregister_target(&pool_target); -bad_pool_target: +bad_thin_target: dm_unregister_target(&thin_target); +bad_new_mapping_cache: + kmem_cache_destroy(_new_mapping_cache); return r; } -- GitLab From 401712e035c699d569dbd37024f4b21dc76cc870 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 15 Aug 2017 18:52:04 +0300 Subject: [PATCH 0535/2547] drm: rcar-du: Clip planes to screen boundaries Unlike the KMS API, the hardware doesn't support planes exceeding the screen boundaries or planes being located fully off-screen. We need to clip plane coordinates to support the use case. Fortunately the DRM core offers a drm_atomic_helper_check_plane_state() helper that validates the scaling factor and clips the plane coordinates. Use it to implement the plane atomic check and use the clipped source and destination rectangles from the plane state instead of the unclipped source and CRTC coordinates to configure the device. Signed-off-by: Laurent Pinchart Reviewed-by: Kieran Bingham --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 3 +- drivers/gpu/drm/rcar-du/rcar_du_plane.c | 50 ++++++++++++++++++------- drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 42 +++++++++++---------- 3 files changed, 62 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index b492063a6e1f..5685d5af6998 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -319,7 +319,8 @@ static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc) struct rcar_du_plane *plane = &rcrtc->group->planes[i]; unsigned int j; - if (plane->plane.state->crtc != &rcrtc->crtc) + if (plane->plane.state->crtc != &rcrtc->crtc || + !plane->plane.state->visible) continue; /* Insert the plane in the sorted planes array. */ diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c index 4f076c364f25..4a3d16cf3ed6 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c @@ -332,8 +332,8 @@ static void rcar_du_plane_write(struct rcar_du_group *rgrp, static void rcar_du_plane_setup_scanout(struct rcar_du_group *rgrp, const struct rcar_du_plane_state *state) { - unsigned int src_x = state->state.src_x >> 16; - unsigned int src_y = state->state.src_y >> 16; + unsigned int src_x = state->state.src.x1 >> 16; + unsigned int src_y = state->state.src.y1 >> 16; unsigned int index = state->hwindex; unsigned int pitch; bool interlaced; @@ -357,7 +357,7 @@ static void rcar_du_plane_setup_scanout(struct rcar_du_group *rgrp, dma[i] = gem->paddr + fb->offsets[i]; } } else { - pitch = state->state.src_w >> 16; + pitch = drm_rect_width(&state->state.src) >> 16; dma[0] = 0; dma[1] = 0; } @@ -521,6 +521,7 @@ static void rcar_du_plane_setup_format(struct rcar_du_group *rgrp, const struct rcar_du_plane_state *state) { struct rcar_du_device *rcdu = rgrp->dev; + const struct drm_rect *dst = &state->state.dst; if (rcdu->info->gen < 3) rcar_du_plane_setup_format_gen2(rgrp, index, state); @@ -528,10 +529,10 @@ static void rcar_du_plane_setup_format(struct rcar_du_group *rgrp, rcar_du_plane_setup_format_gen3(rgrp, index, state); /* Destination position and size */ - rcar_du_plane_write(rgrp, index, PnDSXR, state->state.crtc_w); - rcar_du_plane_write(rgrp, index, PnDSYR, state->state.crtc_h); - rcar_du_plane_write(rgrp, index, PnDPXR, state->state.crtc_x); - rcar_du_plane_write(rgrp, index, PnDPYR, state->state.crtc_y); + rcar_du_plane_write(rgrp, index, PnDSXR, drm_rect_width(dst)); + rcar_du_plane_write(rgrp, index, PnDSYR, drm_rect_height(dst)); + rcar_du_plane_write(rgrp, index, PnDPXR, dst->x1); + rcar_du_plane_write(rgrp, index, PnDPYR, dst->y1); if (rcdu->info->gen < 3) { /* Wrap-around and blinking, disabled */ @@ -570,16 +571,39 @@ int __rcar_du_plane_atomic_check(struct drm_plane *plane, const struct rcar_du_format_info **format) { struct drm_device *dev = plane->dev; + struct drm_crtc_state *crtc_state; + struct drm_rect clip; + int ret; - if (!state->fb || !state->crtc) { + if (!state->crtc) { + /* + * The visible field is not reset by the DRM core but only + * updated by drm_plane_helper_check_state(), set it manually. + */ + state->visible = false; *format = NULL; return 0; } - if (state->src_w >> 16 != state->crtc_w || - state->src_h >> 16 != state->crtc_h) { - dev_dbg(dev->dev, "%s: scaling not supported\n", __func__); - return -EINVAL; + crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + + clip.x1 = 0; + clip.y1 = 0; + clip.x2 = crtc_state->mode.hdisplay; + clip.y2 = crtc_state->mode.vdisplay; + + ret = drm_atomic_helper_check_plane_state(state, crtc_state, &clip, + DRM_PLANE_HELPER_NO_SCALING, + DRM_PLANE_HELPER_NO_SCALING, + true, true); + if (ret < 0) + return ret; + + if (!state->visible) { + *format = NULL; + return 0; } *format = rcar_du_format_info(state->fb->format->format); @@ -607,7 +631,7 @@ static void rcar_du_plane_atomic_update(struct drm_plane *plane, struct rcar_du_plane_state *old_rstate; struct rcar_du_plane_state *new_rstate; - if (!plane->state->crtc) + if (!plane->state->visible) return; rcar_du_plane_setup(rplane); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c index dd66dcb8da23..2c260c33840b 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c @@ -55,14 +55,14 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc) struct rcar_du_plane_state state = { .state = { .crtc = &crtc->crtc, - .crtc_x = 0, - .crtc_y = 0, - .crtc_w = mode->hdisplay, - .crtc_h = mode->vdisplay, - .src_x = 0, - .src_y = 0, - .src_w = mode->hdisplay << 16, - .src_h = mode->vdisplay << 16, + .dst.x1 = 0, + .dst.y1 = 0, + .dst.x2 = mode->hdisplay, + .dst.y2 = mode->vdisplay, + .src.x1 = 0, + .src.y1 = 0, + .src.x2 = mode->hdisplay << 16, + .src.y2 = mode->vdisplay << 16, .zpos = 0, }, .format = rcar_du_format_info(DRM_FORMAT_ARGB8888), @@ -178,15 +178,15 @@ static void rcar_du_vsp_plane_setup(struct rcar_du_vsp_plane *plane) }; unsigned int i; - cfg.src.left = state->state.src_x >> 16; - cfg.src.top = state->state.src_y >> 16; - cfg.src.width = state->state.src_w >> 16; - cfg.src.height = state->state.src_h >> 16; + cfg.src.left = state->state.src.x1 >> 16; + cfg.src.top = state->state.src.y1 >> 16; + cfg.src.width = drm_rect_width(&state->state.src) >> 16; + cfg.src.height = drm_rect_height(&state->state.src) >> 16; - cfg.dst.left = state->state.crtc_x; - cfg.dst.top = state->state.crtc_y; - cfg.dst.width = state->state.crtc_w; - cfg.dst.height = state->state.crtc_h; + cfg.dst.left = state->state.dst.x1; + cfg.dst.top = state->state.dst.y1; + cfg.dst.width = drm_rect_width(&state->state.dst); + cfg.dst.height = drm_rect_height(&state->state.dst); for (i = 0; i < state->format->planes; ++i) cfg.mem[i] = sg_dma_address(state->sg_tables[i].sgl) @@ -212,7 +212,11 @@ static int rcar_du_vsp_plane_prepare_fb(struct drm_plane *plane, unsigned int i; int ret; - if (!state->fb) + /* + * There's no need to prepare (and unprepare) the framebuffer when the + * plane is not visible, as it will not be displayed. + */ + if (!state->visible) return 0; for (i = 0; i < rstate->format->planes; ++i) { @@ -253,7 +257,7 @@ static void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane, struct rcar_du_vsp *vsp = to_rcar_vsp_plane(plane)->vsp; unsigned int i; - if (!state->fb) + if (!state->visible) return; for (i = 0; i < rstate->format->planes; ++i) { @@ -278,7 +282,7 @@ static void rcar_du_vsp_plane_atomic_update(struct drm_plane *plane, struct rcar_du_vsp_plane *rplane = to_rcar_vsp_plane(plane); struct rcar_du_crtc *crtc = to_rcar_crtc(old_state->crtc); - if (plane->state->crtc) + if (plane->state->visible) rcar_du_vsp_plane_setup(rplane); else vsp1_du_atomic_update(rplane->vsp->vsp, crtc->vsp_pipe, -- GitLab From 8a84bf45143b6b3552a806ab73181d7c7b6020ff Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Mon, 3 Jul 2017 08:31:05 +0100 Subject: [PATCH 0536/2547] bus: arm-ccn: constify attribute_group structures. attribute_groups are not supposed to change at runtime. All functions working with attribute_groups provided by work with const attribute_group. So mark the non-const structs as const. File size before: text data bss dec hex filename 9074 5592 416 15082 3aea drivers/bus/arm-ccn.o File size After adding 'const': text data bss dec hex filename 9327 5336 416 15079 3ae7 drivers/bus/arm-ccn.o Signed-off-by: Arvind Yadav Signed-off-by: Pawel Moll --- drivers/bus/arm-ccn.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/bus/arm-ccn.c b/drivers/bus/arm-ccn.c index 3063f5312397..7625bf762acb 100644 --- a/drivers/bus/arm-ccn.c +++ b/drivers/bus/arm-ccn.c @@ -262,7 +262,7 @@ static struct attribute *arm_ccn_pmu_format_attrs[] = { NULL }; -static struct attribute_group arm_ccn_pmu_format_attr_group = { +static const struct attribute_group arm_ccn_pmu_format_attr_group = { .name = "format", .attrs = arm_ccn_pmu_format_attrs, }; @@ -451,7 +451,7 @@ static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = { static struct attribute *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1]; -static struct attribute_group arm_ccn_pmu_events_attr_group = { +static const struct attribute_group arm_ccn_pmu_events_attr_group = { .name = "events", .is_visible = arm_ccn_pmu_events_is_visible, .attrs = arm_ccn_pmu_events_attrs, @@ -548,7 +548,7 @@ static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = { NULL }; -static struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = { +static const struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = { .name = "cmp_mask", .attrs = arm_ccn_pmu_cmp_mask_attrs, }; @@ -569,7 +569,7 @@ static struct attribute *arm_ccn_pmu_cpumask_attrs[] = { NULL, }; -static struct attribute_group arm_ccn_pmu_cpumask_attr_group = { +static const struct attribute_group arm_ccn_pmu_cpumask_attr_group = { .attrs = arm_ccn_pmu_cpumask_attrs, }; -- GitLab From e2874a3c8c0c3b251d288a6149a80b9fd1c2f019 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Nov 2017 21:15:50 -0500 Subject: [PATCH 0537/2547] drm/amdgpu: add license to Makefiles MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Was missing license text. Acked-by: Harry Wentland Acked-by: Felix Kuehling Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/acp/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/amdgpu/Makefile | 22 +++++++++++++++++- drivers/gpu/drm/amd/amdkfd/Makefile | 22 +++++++++++++++++- drivers/gpu/drm/amd/display/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/basics/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/bios/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/calcs/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/dce100/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/dce110/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/dce112/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/dce120/Makefile | 23 ++++++++++++++++++- drivers/gpu/drm/amd/display/dc/dce80/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/dml/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/gpio/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/i2caux/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/irq/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/virtual/Makefile | 21 +++++++++++++++++ .../drm/amd/display/modules/freesync/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/lib/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/powerplay/Makefile | 22 +++++++++++++++++- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 22 +++++++++++++++++- drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 22 +++++++++++++++++- 26 files changed, 547 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/acp/Makefile b/drivers/gpu/drm/amd/acp/Makefile index 8a08e81ee90d..d4176a3fb706 100644 --- a/drivers/gpu/drm/amd/acp/Makefile +++ b/drivers/gpu/drm/amd/acp/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the ACP, which is a sub-component # of AMDSOC/AMDGPU drm driver. # It provides the HW control for ACP related functionalities. diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 78d609123420..90202cf4cd1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# # # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 7bb0bc0ca3d6..342c2d937b17 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# # # Makefile for Heterogenous System Architecture support for AMD GPU devices # diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile index 8ba37dd9cf7f..c27c81cdeed3 100644 --- a/drivers/gpu/drm/amd/display/Makefile +++ b/drivers/gpu/drm/amd/display/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the DAL (Display Abstract Layer), which is a sub-component # of the AMDGPU drm driver. # It provides the HW control for display related functionalities. diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile index 4699e47aa76b..2b72009844f8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'dm' sub-component of DAL. # It provides the control and status of dm blocks. diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 4f83e3011743..aed538a4d1ba 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for Display Core (dc) component. # diff --git a/drivers/gpu/drm/amd/display/dc/basics/Makefile b/drivers/gpu/drm/amd/display/dc/basics/Makefile index 43c5ccdeeb72..6af8c8a9ad80 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/Makefile +++ b/drivers/gpu/drm/amd/display/dc/basics/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'utils' sub-component of DAL. # It provides the general basic services required by other DAL # subcomponents. diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile index 6ec815dce9cc..239e86bbec5a 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'bios' sub-component of DAL. # It provides the parsing and executing controls for atom bios image. diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile index 41ef35995b02..7959e382ed28 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'calcs' sub-component of DAL. # It calculates Bandwidth and Watermarks values for HW programming # diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile b/drivers/gpu/drm/amd/display/dc/dce/Makefile index 8abec0bed379..11401fd8e535 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for common 'dce' logic # HW object file under this folder follow similar pattern for HW programming # - register offset and/or shift + mask stored in the dec_hw struct diff --git a/drivers/gpu/drm/amd/display/dc/dce100/Makefile b/drivers/gpu/drm/amd/display/dc/dce100/Makefile index ea40870624b3..a822d4e2a169 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce100/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/dc/dce110/Makefile b/drivers/gpu/drm/amd/display/dc/dce110/Makefile index 98d956e2f218..d564c0eb8b04 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce110/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/dc/dce112/Makefile b/drivers/gpu/drm/amd/display/dc/dce112/Makefile index 265ac4310d85..8e090446d511 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce112/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile index 1779b963525c..37db1f8d45ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce120/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. @@ -8,4 +29,4 @@ dce120_hw_sequencer.o AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120)) -AMD_DISPLAY_FILES += $(AMD_DAL_DCE120) \ No newline at end of file +AMD_DISPLAY_FILES += $(AMD_DAL_DCE120) diff --git a/drivers/gpu/drm/amd/display/dc/dce80/Makefile b/drivers/gpu/drm/amd/display/dc/dce80/Makefile index c1105895e5fa..bc388aa4b2f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce80/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile index ebeb88283a14..f565a6042970 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for DCN. DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \ diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 87bab8e8139f..3488af2b5786 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'utils' sub-component of DAL. # It provides the general basic services required by other DAL # subcomponents. diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile index 70d01a9e9676..562ee189d780 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'gpio' sub-component of DAL. # It provides the control and status of HW GPIO pins. diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile index 55603400acd9..352885cb4d07 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile +++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'i2c' sub-component of DAL. # It provides the control and status of HW i2c engine of the adapter. diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index c7e93f7223bd..498515aad4a5 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'audio' sub-component of DAL. # It provides the control and status of HW adapter resources, # that are global for the ASIC and sharable between pipes. diff --git a/drivers/gpu/drm/amd/display/dc/virtual/Makefile b/drivers/gpu/drm/amd/display/dc/virtual/Makefile index fc0b7318d9cc..07326d244d50 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/Makefile +++ b/drivers/gpu/drm/amd/display/dc/virtual/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the virtual sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/modules/freesync/Makefile b/drivers/gpu/drm/amd/display/modules/freesync/Makefile index db8e0ff6d7a9..fb9a499780e8 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/Makefile +++ b/drivers/gpu/drm/amd/display/modules/freesync/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'freesync' sub-module of DAL. # diff --git a/drivers/gpu/drm/amd/lib/Makefile b/drivers/gpu/drm/amd/lib/Makefile index 87cd7009e80f..690243001e1a 100644 --- a/drivers/gpu/drm/amd/lib/Makefile +++ b/drivers/gpu/drm/amd/lib/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for AMD library routines, which are used by AMD driver # components. # diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile index 8c55c6e254d9..231785a9e24c 100644 --- a/drivers/gpu/drm/amd/powerplay/Makefile +++ b/drivers/gpu/drm/amd/powerplay/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# subdir-ccflags-y += \ -I$(FULL_AMD_PATH)/powerplay/inc/ \ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile index 824fb6fe54ae..a212c27f2e17 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# # # Makefile for the 'hw manager' sub-component of powerplay. # It provides the hardware management services for the driver. diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile index 30d3089d7dba..98e701e4f553 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# # # Makefile for the 'smu manager' sub-component of powerplay. # It provides the smu management services for the driver. -- GitLab From bf93b448b80bf71c2003659b06487879153b8b9b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Nov 2017 21:29:47 -0500 Subject: [PATCH 0538/2547] drm/amdgpu: add license to files where it was missing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These files were missing it before. Acked-by: Harry Wentland Acked-by: Felix Kuehling Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 24 ++++++++++++++++++- .../gpu/drm/amd/display/dc/core/dc_debug.c | 22 +++++++++++++++++ .../gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dc_helper.c | 22 +++++++++++++++++ .../amd/display/dc/dce100/dce100_resource.c | 2 +- .../amd/display/dc/dce100/dce100_resource.h | 23 ++++++++++++++++++ .../amd/display/dc/dce110/dce110_resource.c | 2 +- .../dc/dce110/dce110_timing_generator_v.c | 23 ++++++++++++++++++ .../drm/amd/display/dc/inc/hw/link_encoder.h | 22 +++++++++++++++++ .../amd/display/dc/inc/hw/stream_encoder.h | 22 +++++++++++++++++ .../drm/amd/powerplay/hwmgr/pp_overdriver.c | 24 ++++++++++++++++++- drivers/gpu/drm/amd/powerplay/inc/smu72.h | 24 ++++++++++++++++++- .../drm/amd/powerplay/inc/smu72_discrete.h | 24 ++++++++++++++++++- .../gpu/drm/amd/scheduler/gpu_sched_trace.h | 24 ++++++++++++++++++- 15 files changed, 254 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 6c570d4e4516..f8edf5483f11 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -1,4 +1,6 @@ /* + * Copyright 2017 Advanced Micro Devices, Inc. + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index f337c316ec2c..06525f2c36c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #if !defined(_AMDGPU_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) #define _AMDGPU_TRACE_H_ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 6acee5426e4b..43c7a7fddb83 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * dc_debug.c * diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index b7422d3b71ef..928895809867 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1,5 +1,5 @@ /* -* Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 0d84b2a1ccfd..90e81f7ba919 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * dc_helper.c * diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 90911258bdb3..3ea43e2a9450 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -1,5 +1,5 @@ /* -* Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h index de8fdf438f9b..2f366d66635d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h @@ -1,3 +1,26 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ /* * dce100_resource.h * diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 61adb8174ce0..42df17f9aa8d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1,5 +1,5 @@ /* -* Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c index 07d9303d5477..59b4cd329715 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c @@ -1,3 +1,26 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #include "dm_services.h" /* include DCE11 register header files */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 3d33bcda7059..498b7f05c5ca 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * link_encoder.h * diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 3050afe8e8a9..b5db1692393c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * stream_encoder.h * diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c index 67fae834bc67..8de384bf9a8f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c @@ -1,4 +1,26 @@ -// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #include "pp_overdriver.h" #include diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72.h b/drivers/gpu/drm/amd/powerplay/inc/smu72.h index 08cd70c75d8b..9ad1cefff79f 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu72.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu72.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #ifndef SMU72_H #define SMU72_H diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h index b2edbc0c3c4d..2aefbb85f620 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #ifndef SMU72_DISCRETE_H #define SMU72_DISCRETE_H diff --git a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h index 283a0dc25e84..07129e6c31a9 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #if !defined(_GPU_SCHED_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) #define _GPU_SCHED_TRACE_H_ -- GitLab From 24771179c5c138f0ea3ef88b7972979f62f2d5db Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sun, 27 Aug 2017 11:06:50 +0100 Subject: [PATCH 0539/2547] bus: arm-ccn: Check memory allocation failure Check memory allocation failures and return -ENOMEM in such cases This avoids a potential NULL pointer dereference. Signed-off-by: Christophe JAILLET Acked-by: Scott Branden Cc: stable@vger.kernel.org # 3.17+ Signed-off-by: Pawel Moll --- drivers/bus/arm-ccn.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/bus/arm-ccn.c b/drivers/bus/arm-ccn.c index 7625bf762acb..a7951662f85b 100644 --- a/drivers/bus/arm-ccn.c +++ b/drivers/bus/arm-ccn.c @@ -1271,6 +1271,10 @@ static int arm_ccn_pmu_init(struct arm_ccn *ccn) int len = snprintf(NULL, 0, "ccn_%d", ccn->dt.id); name = devm_kzalloc(ccn->dev, len + 1, GFP_KERNEL); + if (!name) { + err = -ENOMEM; + goto error_choose_name; + } snprintf(name, len + 1, "ccn_%d", ccn->dt.id); } @@ -1319,6 +1323,7 @@ static int arm_ccn_pmu_init(struct arm_ccn *ccn) error_pmu_register: error_set_affinity: +error_choose_name: ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); for (i = 0; i < ccn->num_xps; i++) writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); -- GitLab From 0f9afd36bac9543bc087b77016311c3394bd77c2 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sun, 27 Aug 2017 11:07:06 +0100 Subject: [PATCH 0540/2547] bus: arm-ccn: Simplify code Use 'devm_kasprintf()' to simplify the code. Signed-off-by: Christophe JAILLET Acked-by: Scott Branden Signed-off-by: Pawel Moll --- drivers/bus/arm-ccn.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/bus/arm-ccn.c b/drivers/bus/arm-ccn.c index a7951662f85b..bbc1a2ef9639 100644 --- a/drivers/bus/arm-ccn.c +++ b/drivers/bus/arm-ccn.c @@ -1268,14 +1268,12 @@ static int arm_ccn_pmu_init(struct arm_ccn *ccn) if (ccn->dt.id == 0) { name = "ccn"; } else { - int len = snprintf(NULL, 0, "ccn_%d", ccn->dt.id); - - name = devm_kzalloc(ccn->dev, len + 1, GFP_KERNEL); + name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d", + ccn->dt.id); if (!name) { err = -ENOMEM; goto error_choose_name; } - snprintf(name, len + 1, "ccn_%d", ccn->dt.id); } /* Perf driver registration */ -- GitLab From b18c2b9487d8e797fc0a757e57ac3645348c5fba Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 3 Oct 2017 18:14:12 +0100 Subject: [PATCH 0541/2547] bus: arm-ccn: Fix use of smp_processor_id() in preemptible context Booting a DEBUG_PREEMPT enabled kernel on a CCN-based system results in the following splat: [...] arm-ccn e8000000.ccn: No access to interrupts, using timer. BUG: using smp_processor_id() in preemptible [00000000] code: swapper/0/1 caller is debug_smp_processor_id+0x1c/0x28 CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.13.0 #6111 Hardware name: AMD Seattle/Seattle, BIOS 17:08:23 Jun 26 2017 Call trace: [] dump_backtrace+0x0/0x278 [] show_stack+0x24/0x30 [] dump_stack+0x8c/0xb0 [] check_preemption_disabled+0xfc/0x100 [] debug_smp_processor_id+0x1c/0x28 [] arm_ccn_probe+0x358/0x4f0 [...] as we use smp_processor_id() in the wrong context. Turn this into a get_cpu()/put_cpu() that extends over the CPU hotplug registration, making sure that we don't race against a CPU down operation. Signed-off-by: Marc Zyngier Acked-by: Mark Rutland Cc: stable@vger.kernel.org # 4.2+ Signed-off-by: Pawel Moll --- drivers/bus/arm-ccn.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/bus/arm-ccn.c b/drivers/bus/arm-ccn.c index bbc1a2ef9639..508a1a389b7e 100644 --- a/drivers/bus/arm-ccn.c +++ b/drivers/bus/arm-ccn.c @@ -1300,7 +1300,7 @@ static int arm_ccn_pmu_init(struct arm_ccn *ccn) } /* Pick one CPU which we will use to collect data from CCN... */ - cpumask_set_cpu(smp_processor_id(), &ccn->dt.cpu); + cpumask_set_cpu(get_cpu(), &ccn->dt.cpu); /* Also make sure that the overflow interrupt is handled by this CPU */ if (ccn->irq) { @@ -1317,10 +1317,12 @@ static int arm_ccn_pmu_init(struct arm_ccn *ccn) cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE, &ccn->dt.node); + put_cpu(); return 0; error_pmu_register: error_set_affinity: + put_cpu(); error_choose_name: ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); for (i = 0; i < ccn->num_xps; i++) -- GitLab From 4608af8aa53e7f3922ddee695d023b7bcd5cb35b Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 3 Oct 2017 18:14:13 +0100 Subject: [PATCH 0542/2547] bus: arm-cci: Fix use of smp_processor_id() in preemptible context The ARM CCI driver seem to be using smp_processor_id() in a preemptible context, which is likely to make a DEBUG_PREMPT kernel scream at boot time. Turn this into a get_cpu()/put_cpu() that extends over the CPU hotplug registration, making sure that we don't race against a CPU down operation. Signed-off-by: Marc Zyngier Acked-by: Mark Rutland Cc: stable@vger.kernel.org # 4.2+ Signed-off-by: Pawel Moll --- drivers/bus/arm-cci.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 3c29d36702a8..5426c04fe24b 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -1755,14 +1755,17 @@ static int cci_pmu_probe(struct platform_device *pdev) raw_spin_lock_init(&cci_pmu->hw_events.pmu_lock); mutex_init(&cci_pmu->reserve_mutex); atomic_set(&cci_pmu->active_events, 0); - cpumask_set_cpu(smp_processor_id(), &cci_pmu->cpus); + cpumask_set_cpu(get_cpu(), &cci_pmu->cpus); ret = cci_pmu_init(cci_pmu, pdev); - if (ret) + if (ret) { + put_cpu(); return ret; + } cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCI_ONLINE, &cci_pmu->node); + put_cpu(); pr_info("ARM %s PMU driver probed", cci_pmu->model->name); return 0; } -- GitLab From b69f63ebf553504739cc8534cbed31bd530c6f0b Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 11 Oct 2017 22:33:24 +0100 Subject: [PATCH 0543/2547] bus: arm-ccn: fix module unloading Error: Removing state 147 which has instances left. Unregistering the driver before calling cpuhp_remove_multi_state() removes any remaining hotplug cpu instances so __cpuhp_remove_state_cpuslocked() doesn't emit this warning: [ 268.748362] Error: Removing state 147 which has instances left. [ 268.748373] ------------[ cut here ]------------ [ 268.748386] WARNING: CPU: 2 PID: 5476 at kernel/cpu.c:1734 __cpuhp_remove_state_cpuslocked+0x454/0x4f0 [ 268.748389] Modules linked in: arm_ccn(-) [last unloaded: arm_ccn] [ 268.748403] CPU: 2 PID: 5476 Comm: rmmod Tainted: G W 4.14.0-rc4+ #3 [ 268.748406] Hardware name: AMD Seattle/Seattle, BIOS 10:18:39 Dec 8 2016 [ 268.748410] task: ffff8001a18ca000 task.stack: ffff80019c120000 [ 268.748416] PC is at __cpuhp_remove_state_cpuslocked+0x454/0x4f0 [ 268.748421] LR is at __cpuhp_remove_state_cpuslocked+0x448/0x4f0 [ 268.748425] pc : [] lr : [] pstate: 60000145 [ 268.748427] sp : ffff80019c127d30 [ 268.748430] x29: ffff80019c127d30 x28: ffff8001a18ca000 [ 268.748437] x27: ffff20000c2cb000 x26: 1fffe4000042d490 [ 268.748443] x25: ffff20000216a480 x24: 0000000000000000 [ 268.748449] x23: ffff20000b08e000 x22: 0000000000000001 [ 268.748455] x21: 0000000000000093 x20: 00000000000016f8 [ 268.748460] x19: ffff20000c2cbb80 x18: 0000ffffb5fe7c58 [ 268.748466] x17: 00000000004402d0 x16: 1fffe40001864f01 [ 268.748472] x15: ffff20000c4bf8b0 x14: 0000000000000000 [ 268.748477] x13: 0000000000007032 x12: ffff20000829ae48 [ 268.748483] x11: ffff20000c4bf000 x10: 0000000000000004 [ 268.748488] x9 : 0000000000006fbc x8 : ffff20000c318a40 [ 268.748494] x7 : 0000000000000000 x6 : ffff040001864f02 [ 268.748500] x5 : 0000000000000000 x4 : 0000000000000000 [ 268.748505] x3 : 0000000000000007 x2 : dfff200000000000 [ 268.748510] x1 : 000000000000ad3d x0 : 00000000000001f0 [ 268.748516] Call trace: [ 268.748521] Exception stack(0xffff80019c127bf0 to 0xffff80019c127d30) [ 268.748526] 7be0: 00000000000001f0 000000000000ad3d [ 268.748531] 7c00: dfff200000000000 0000000000000007 0000000000000000 0000000000000000 [ 268.748535] 7c20: ffff040001864f02 0000000000000000 ffff20000c318a40 0000000000006fbc [ 268.748539] 7c40: 0000000000000004 ffff20000c4bf000 ffff20000829ae48 0000000000007032 [ 268.748544] 7c60: 0000000000000000 ffff20000c4bf8b0 1fffe40001864f01 00000000004402d0 [ 268.748548] 7c80: 0000ffffb5fe7c58 ffff20000c2cbb80 00000000000016f8 0000000000000093 [ 268.748553] 7ca0: 0000000000000001 ffff20000b08e000 0000000000000000 ffff20000216a480 [ 268.748557] 7cc0: 1fffe4000042d490 ffff20000c2cb000 ffff8001a18ca000 ffff80019c127d30 [ 268.748562] 7ce0: ffff2000081729e0 ffff80019c127d30 ffff2000081729ec 0000000060000145 [ 268.748566] 7d00: 00000000000001f0 0000000000000000 0001000000000000 0000000000000000 [ 268.748569] 7d20: ffff80019c127d30 ffff2000081729ec [ 268.748575] [] __cpuhp_remove_state_cpuslocked+0x454/0x4f0 [ 268.748580] [] __cpuhp_remove_state+0x54/0x80 [ 268.748597] [] arm_ccn_exit+0x2c/0x70 [arm_ccn] [ 268.748604] [] SyS_delete_module+0x5a4/0x708 [ 268.748607] Exception stack(0xffff80019c127ec0 to 0xffff80019c128000) [ 268.748612] 7ec0: 0000000019bb7258 0000000000000800 ba64d0fb3d26a800 00000000000000da [ 268.748616] 7ee0: 0000ffffb6144e28 0000ffffcd95b409 fefefefefefefeff 7f7f7f7f7f7f7f7f [ 268.748621] 7f00: 000000000000006a 1999999999999999 0000ffffb6179000 0000000000bbcc6d [ 268.748625] 7f20: 0000ffffb6176b98 0000ffffcd95c2d0 0000ffffb5fe7b58 0000ffffb6163000 [ 268.748630] 7f40: 0000ffffb60ad3e0 00000000004402d0 0000ffffb5fe7c58 0000000019bb71f0 [ 268.748634] 7f60: 0000ffffcd95c740 0000000000000000 0000000019bb71f0 0000000000416700 [ 268.748639] 7f80: 0000000000000000 00000000004402e8 0000000019bb6010 0000ffffcd95c748 [ 268.748643] 7fa0: 0000000000000000 0000ffffcd95c460 00000000004113a8 0000ffffcd95c460 [ 268.748648] 7fc0: 0000ffffb60ad3e8 0000000080000000 0000000019bb7258 000000000000006a [ 268.748652] 7fe0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 [ 268.748657] [] __sys_trace_return+0x0/0x4 [ 268.748661] ---[ end trace a996d358dcaa7f9c ]--- Fixes: 8df038725ad5 ("bus/arm-ccn: Use cpu-hp's multi instance support instead custom list") Signed-off-by: Kim Phillips Acked-by: Sebastian Andrzej Siewior Cc: stable@vger.kernel.org # 4.8+ Signed-off-by: Pawel Moll --- drivers/bus/arm-ccn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/arm-ccn.c b/drivers/bus/arm-ccn.c index 508a1a389b7e..b52332e52ca5 100644 --- a/drivers/bus/arm-ccn.c +++ b/drivers/bus/arm-ccn.c @@ -1586,8 +1586,8 @@ static int __init arm_ccn_init(void) static void __exit arm_ccn_exit(void) { - cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE); platform_driver_unregister(&arm_ccn_driver); + cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE); } module_init(arm_ccn_init); -- GitLab From 3fa8c49f27c15df259b7b8f94eb126ae491893fd Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 4 Dec 2017 18:36:10 +0100 Subject: [PATCH 0544/2547] arm64: dts: rockchip: fix trailing 0 in rk3328 tsadc interrupts Probably due to some copy-paste mistake, the tsadc of rk3328 ended up with a 0 as 4th element that shouldn't be there, as interrupts on the rk3328 only have multiples of 3, making dtc complain. So remove it. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 41d61840fb99..2426da631938 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -514,7 +514,7 @@ tsadc: tsadc@ff250000 { compatible = "rockchip,rk3328-tsadc"; reg = <0x0 0xff250000 0x0 0x100>; - interrupts = ; + interrupts = ; assigned-clocks = <&cru SCLK_TSADC>; assigned-clock-rates = <50000>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; -- GitLab From adf6895754e2503d994a765535fd1813f8834674 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Thu, 30 Nov 2017 19:42:52 -0800 Subject: [PATCH 0545/2547] acpi, nfit: fix health event notification Integration testing with a BIOS that generates injected health event notifications fails to communicate those events to userspace. The nfit driver neglects to link the ACPI DIMM device with the necessary driver data so acpi_nvdimm_notify() fails this lookup: nfit_mem = dev_get_drvdata(dev); if (nfit_mem && nfit_mem->flags_attr) sysfs_notify_dirent(nfit_mem->flags_attr); Add the necessary linkage when installing the notification handler and clean it up when the nfit driver instance is torn down. Cc: Cc: Toshi Kani Cc: Vishal Verma Fixes: ba9c8dd3c222 ("acpi, nfit: add dimm device notification support") Reported-by: Daniel Osawa Tested-by: Daniel Osawa Signed-off-by: Dan Williams --- drivers/acpi/nfit/core.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/nfit/core.c b/drivers/acpi/nfit/core.c index ff2580e7611d..abeb4df4f22e 100644 --- a/drivers/acpi/nfit/core.c +++ b/drivers/acpi/nfit/core.c @@ -1670,6 +1670,11 @@ static int acpi_nfit_add_dimm(struct acpi_nfit_desc *acpi_desc, dev_name(&adev_dimm->dev)); return -ENXIO; } + /* + * Record nfit_mem for the notification path to track back to + * the nfit sysfs attributes for this dimm device object. + */ + dev_set_drvdata(&adev_dimm->dev, nfit_mem); /* * Until standardization materializes we need to consider 4 @@ -1752,9 +1757,11 @@ static void shutdown_dimm_notify(void *data) sysfs_put(nfit_mem->flags_attr); nfit_mem->flags_attr = NULL; } - if (adev_dimm) + if (adev_dimm) { acpi_remove_notify_handler(adev_dimm->handle, ACPI_DEVICE_NOTIFY, acpi_nvdimm_notify); + dev_set_drvdata(&adev_dimm->dev, NULL); + } } mutex_unlock(&acpi_desc->init_mutex); } -- GitLab From 53ff2641a817099e1c6d1aef409ba004c3a9f1ea Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 13 Nov 2017 23:34:55 +0000 Subject: [PATCH 0546/2547] drm/i915/cnl: only divide up base frequency with crystal source We apply this logic to Gen9 as well. We didn't notice this issue as most part we've encountered so far only use the crystal as source for their timestamp registers. Fixes: dab9178333 ("drm/i915: expose command stream timestamp frequency to userspace") Reviewed-by: Paulo Zanoni Signed-off-by: Lionel Landwerlin Signed-off-by: Paulo Zanoni Link: https://patchwork.freedesktop.org/patch/msgid/20171113233455.12085-5-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/intel_device_info.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 02f8bf101ccd..405d70124a46 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -403,15 +403,15 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) freq = f24_mhz; break; } - } - /* Now figure out how the command stream's timestamp register - * increments from this frequency (it might increment only - * every few clock cycle). - */ - freq >>= 3 - ((rpm_config_reg & - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); + /* Now figure out how the command stream's timestamp + * register increments from this frequency (it might + * increment only every few clock cycle). + */ + freq >>= 3 - ((rpm_config_reg & + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); + } return freq; } -- GitLab From 8ee5ad1d4c0ba93f96d0db31e98102e61ff7d12b Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Mon, 4 Dec 2017 10:52:40 -0500 Subject: [PATCH 0547/2547] arch/tile: mark as orphaned The chip family of TILEPro and TILE-Gx was developed by Tilera, which was eventually acquired by Mellanox. The tile architecture was added to the kernel in 2010 and first appeared in 2.6.36. Now at Mellanox we are developing new chips based on the ARM64 architecture; our last TILE-Gx chip (the Gx72) was released in 2013, and our customers using tile architecture products are not, as far as we know, looking to upgrade to newer kernel releases. In the absence of someone in the community stepping up to take over maintainership, this commit marks the architecture as orphaned. Cc: Chris Metcalf Signed-off-by: Chris Metcalf Signed-off-by: Linus Torvalds --- MAINTAINERS | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index d4fdcb12616c..603d49e877a9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13647,10 +13647,8 @@ F: drivers/net/wireless/ti/ F: include/linux/wl12xx.h TILE ARCHITECTURE -M: Chris Metcalf W: http://www.mellanox.com/repository/solutions/tile-scm/ -T: git git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile.git -S: Supported +S: Orphan F: arch/tile/ F: drivers/char/tile-srom.c F: drivers/edac/tile_edac.c -- GitLab From bc53e3aa88e8240823c1c440e6bab3c3a5ba5f59 Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Mon, 27 Nov 2017 17:31:01 +0100 Subject: [PATCH 0548/2547] ARM: dts: at91: disable the nxp,se97b SMBUS timeout on the TSE-850 The I2C adapter driver is sometimes slow, causing the SCL line to be stuck low for more than the stipulated SMBUS timeout of 25-35 ms. This causes the client device to give up which in turn causes silent corruption of data. So, disable the SMBUS timeout in the client device. Signed-off-by: Peter Rosin Acked-by: Guenter Roeck Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-tse850-3.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts index 5f29010cdbd8..9b82cc8843e1 100644 --- a/arch/arm/boot/dts/at91-tse850-3.dts +++ b/arch/arm/boot/dts/at91-tse850-3.dts @@ -221,6 +221,7 @@ jc42@18 { compatible = "nxp,se97b", "jedec,jc-42.4-temp"; reg = <0x18>; + smbus-timeout-disable; }; dpot: mcp4651-104@28 { -- GitLab From bb5c43428252f27b875c764451321a83a531d6e5 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 28 Nov 2017 15:40:33 +0100 Subject: [PATCH 0549/2547] genirq/matrix: Fix the precedence fix for real The previous commit which made the operator precedence in irq_matrix_available() explicit made the implicit brokenness explicitely wrong. It was wrong in the original commit already. The overworked maintainer did not notice it either when merging the patch. Replace the confusing '?' construct by a simple and obvious if (). Fixes: 75f1133873d6 ("genirq/matrix: Make - vs ?: Precedence explicit") Reported-by: Rasmus Villemoes Signed-off-by: Thomas Gleixner Cc: Kees Cook --- kernel/irq/matrix.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/kernel/irq/matrix.c b/kernel/irq/matrix.c index 7df2480005f8..0ba0dd8863a7 100644 --- a/kernel/irq/matrix.c +++ b/kernel/irq/matrix.c @@ -384,7 +384,9 @@ unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown) { struct cpumap *cm = this_cpu_ptr(m->maps); - return (m->global_available - cpudown) ? cm->available : 0; + if (!cpudown) + return m->global_available; + return m->global_available - cm->available; } /** -- GitLab From 4ce413d1840b25b101be3c0559161db8891f3360 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 1 Dec 2017 15:29:39 +0000 Subject: [PATCH 0550/2547] irqdesc: Use bool return type instead of int The irq_balancing_disabled and irq_is_percpu{,_devid} functions are clearly intended to return bool like the functions in kernel/irq/settings.h, but actually return an int containing a masked value of desc->status_use_accessors. This can lead to subtle breakage if, for example, the return value is subsequently truncated when assigned to a narrower type. As Linus points out: | In particular, what can (and _has_ happened) is that people end up | using these functions that return true or false, and they assign the | result to something like a bitfield (or a char) or whatever. | | And the code looks *obviously* correct, when you have things like | | dev->percpu = irq_is_percpu_devid(dev->irq); | | and that "percpu" thing is just one status bit among many. It may even | *work*, because maybe that "percpu" flag ends up not being all that | important, or it just happens to never be set on the particular | hardware that people end up testing. | | But while it looks obviously correct, and might even work, it's really | fundamentally broken. Because that "true or false" function didn't | actually return 0/1, it returned 0 or 0x20000. | | And 0x20000 may not fit in a bitmask or a "char" or whatever. Fix the problem by consistently using bool as the return type for these functions. Reported-by: Linus Torvalds Signed-off-by: Will Deacon Signed-off-by: Thomas Gleixner Cc: marc.zyngier@arm.com Link: https://lkml.kernel.org/r/1512142179-24616-1-git-send-email-will.deacon@arm.com --- include/linux/irqdesc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/irqdesc.h b/include/linux/irqdesc.h index dd418955962b..39fb3700f7a9 100644 --- a/include/linux/irqdesc.h +++ b/include/linux/irqdesc.h @@ -230,7 +230,7 @@ irq_set_chip_handler_name_locked(struct irq_data *data, struct irq_chip *chip, data->chip = chip; } -static inline int irq_balancing_disabled(unsigned int irq) +static inline bool irq_balancing_disabled(unsigned int irq) { struct irq_desc *desc; @@ -238,7 +238,7 @@ static inline int irq_balancing_disabled(unsigned int irq) return desc->status_use_accessors & IRQ_NO_BALANCING_MASK; } -static inline int irq_is_percpu(unsigned int irq) +static inline bool irq_is_percpu(unsigned int irq) { struct irq_desc *desc; @@ -246,7 +246,7 @@ static inline int irq_is_percpu(unsigned int irq) return desc->status_use_accessors & IRQ_PER_CPU; } -static inline int irq_is_percpu_devid(unsigned int irq) +static inline bool irq_is_percpu_devid(unsigned int irq) { struct irq_desc *desc; -- GitLab From ce179cbdedf2f54306177e591664be7b18cf386a Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Mon, 4 Dec 2017 17:01:20 +0800 Subject: [PATCH 0551/2547] ahci: qoriq: refine port register configuration These PP2C and PP3C registers control the configuration of the PHY control OOB timing for the COMINIT/COMWAKE parameters respectively for sata port. Overwrite default values with calculated ones to get better OOB timing. Signed-off-by: Tang Yuantian Signed-off-by: Tejun Heo --- drivers/ata/ahci_qoriq.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c index b6b0bf76dfc7..2685f28160f7 100644 --- a/drivers/ata/ahci_qoriq.c +++ b/drivers/ata/ahci_qoriq.c @@ -35,6 +35,8 @@ /* port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe +#define AHCI_PORT_PHY2_CFG 0x28184d1f +#define AHCI_PORT_PHY3_CFG 0x0e081509 #define AHCI_PORT_TRANS_CFG 0x08000029 #define AHCI_PORT_AXICC_CFG 0x3fffffff @@ -183,6 +185,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv) writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, qpriv->ecc_addr); writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); + writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); + writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); if (qpriv->is_dmacoherent) writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); @@ -190,6 +194,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv) case AHCI_LS2080A: writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); + writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); + writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); if (qpriv->is_dmacoherent) writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); @@ -201,6 +207,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv) writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, qpriv->ecc_addr); writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); + writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); + writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); if (qpriv->is_dmacoherent) writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); @@ -212,6 +220,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv) writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A, qpriv->ecc_addr); writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); + writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); + writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); if (qpriv->is_dmacoherent) writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); @@ -219,6 +229,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv) case AHCI_LS2088A: writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); + writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); + writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); if (qpriv->is_dmacoherent) writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); -- GitLab From 2467c0451ce5574738e223b93e3253c9a7015be1 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 1 Dec 2017 11:47:22 +0100 Subject: [PATCH 0552/2547] ahci: mtk: Change driver name to ahci-mtk The driver name "ahci" is already used by the ahci platform driver. This leads to the following error: Error: Driver 'ahci' is already registered, aborting... Change the name to ahci-mtk to fix this. Signed-off-by: Matthias Brugger Signed-off-by: Tejun Heo --- drivers/ata/ahci_mtk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c index 489452a64303..0ae6971c2a4c 100644 --- a/drivers/ata/ahci_mtk.c +++ b/drivers/ata/ahci_mtk.c @@ -25,7 +25,7 @@ #include #include "ahci.h" -#define DRV_NAME "ahci" +#define DRV_NAME "ahci-mtk" #define SYS_CFG 0x14 #define SYS_CFG_SATA_MSK GENMASK(31, 30) -- GitLab From d1f6dc1a9a106a73510181cfad9b4a7a0b140990 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 19 Oct 2017 14:29:46 -0400 Subject: [PATCH 0553/2547] drm/amdgpu: Avoid accessing job->entity after the job is scheduled. Bug: amdgpu_job_free_cb was accessing s_job->s_entity when the allocated amdgpu_ctx (and the entity inside it) were already deallocated from amdgpu_cs_parser_fini. Fix: Save job's priority on it's creation instead of accessing it from s_entity later on. Signed-off-by: Andrey Grodzovsky Reviewed-by: Andres Rodriguez Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 ++- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 1 + drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 32 ++++++++----------- 4 files changed, 18 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 57abf7abd7a9..b4b3ecf9f96d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1194,8 +1194,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, job->uf_sequence = seq; amdgpu_job_free_resources(job); - amdgpu_ring_priority_get(job->ring, - amd_sched_get_job_priority(&job->base)); + amdgpu_ring_priority_get(job->ring, job->base.s_priority); trace_amdgpu_cs_ioctl(job); amd_sched_entity_push_job(&job->base); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 0cfc68db575b..a58e3c5dd84b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -104,7 +104,7 @@ static void amdgpu_job_free_cb(struct amd_sched_job *s_job) { struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base); - amdgpu_ring_priority_put(job->ring, amd_sched_get_job_priority(s_job)); + amdgpu_ring_priority_put(job->ring, s_job->s_priority); dma_fence_put(job->fence); amdgpu_sync_free(&job->sync); amdgpu_sync_free(&job->dep_sync); @@ -141,8 +141,7 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, job->fence_ctx = entity->fence_context; *f = dma_fence_get(&job->base.s_fence->finished); amdgpu_job_free_resources(job); - amdgpu_ring_priority_get(job->ring, - amd_sched_get_job_priority(&job->base)); + amdgpu_ring_priority_get(job->ring, job->base.s_priority); amd_sched_entity_push_job(&job->base); return 0; diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 92ec663fdada..9061c88e3e0c 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -529,6 +529,7 @@ int amd_sched_job_init(struct amd_sched_job *job, { job->sched = sched; job->s_entity = entity; + job->s_priority = entity->rq - sched->sched_rq; job->s_fence = amd_sched_fence_create(entity, owner); if (!job->s_fence) return -ENOMEM; diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h index 52c8e5447624..3f75b45ed958 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h @@ -30,6 +30,19 @@ struct amd_gpu_scheduler; struct amd_sched_rq; +enum amd_sched_priority { + AMD_SCHED_PRIORITY_MIN, + AMD_SCHED_PRIORITY_LOW = AMD_SCHED_PRIORITY_MIN, + AMD_SCHED_PRIORITY_NORMAL, + AMD_SCHED_PRIORITY_HIGH_SW, + AMD_SCHED_PRIORITY_HIGH_HW, + AMD_SCHED_PRIORITY_KERNEL, + AMD_SCHED_PRIORITY_MAX, + AMD_SCHED_PRIORITY_INVALID = -1, + AMD_SCHED_PRIORITY_UNSET = -2 +}; + + /** * A scheduler entity is a wrapper around a job queue or a group * of other entities. Entities take turns emitting jobs from their @@ -83,6 +96,7 @@ struct amd_sched_job { struct delayed_work work_tdr; uint64_t id; atomic_t karma; + enum amd_sched_priority s_priority; }; extern const struct dma_fence_ops amd_sched_fence_ops_scheduled; @@ -114,18 +128,6 @@ struct amd_sched_backend_ops { void (*free_job)(struct amd_sched_job *sched_job); }; -enum amd_sched_priority { - AMD_SCHED_PRIORITY_MIN, - AMD_SCHED_PRIORITY_LOW = AMD_SCHED_PRIORITY_MIN, - AMD_SCHED_PRIORITY_NORMAL, - AMD_SCHED_PRIORITY_HIGH_SW, - AMD_SCHED_PRIORITY_HIGH_HW, - AMD_SCHED_PRIORITY_KERNEL, - AMD_SCHED_PRIORITY_MAX, - AMD_SCHED_PRIORITY_INVALID = -1, - AMD_SCHED_PRIORITY_UNSET = -2 -}; - /** * One scheduler is implemented for each hardware ring */ @@ -176,10 +178,4 @@ bool amd_sched_dependency_optimized(struct dma_fence* fence, struct amd_sched_entity *entity); void amd_sched_job_kickout(struct amd_sched_job *s_job); -static inline enum amd_sched_priority -amd_sched_get_job_priority(struct amd_sched_job *job) -{ - return (job->s_entity->rq - job->sched->sched_rq); -} - #endif -- GitLab From 2f9d4084cac96a0281522b548ca0526c1e241b75 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Mon, 16 Oct 2017 14:38:10 +0800 Subject: [PATCH 0554/2547] drm/amdgpu:cleanup force_completion cleanups, now only operate on the given ring Signed-off-by: Monk Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 29 ++++++---------------- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +-- 3 files changed, 11 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 3573ecdb06ee..620e3002001d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2872,7 +2872,7 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) amd_sched_hw_job_reset(&ring->sched); /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ - amdgpu_fence_driver_force_completion_ring(ring); + amdgpu_fence_driver_force_completion(ring); } /* request to take full control of GPU before re-initialization */ @@ -2991,9 +2991,9 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) continue; kthread_park(ring->sched.thread); amd_sched_hw_job_reset(&ring->sched); + /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ + amdgpu_fence_driver_force_completion(ring); } - /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ - amdgpu_fence_driver_force_completion(adev); need_full_reset = amdgpu_need_full_reset(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 2fa95aef74d5..219c15f79a5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -499,7 +499,7 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev) r = amdgpu_fence_wait_empty(ring); if (r) { /* no need to trigger GPU reset as we are unloading */ - amdgpu_fence_driver_force_completion(adev); + amdgpu_fence_driver_force_completion(ring); } amdgpu_irq_put(adev, ring->fence_drv.irq_src, ring->fence_drv.irq_type); @@ -534,7 +534,7 @@ void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) r = amdgpu_fence_wait_empty(ring); if (r) { /* delay GPU reset to resume */ - amdgpu_fence_driver_force_completion(adev); + amdgpu_fence_driver_force_completion(ring); } /* disable the interrupt */ @@ -571,30 +571,15 @@ void amdgpu_fence_driver_resume(struct amdgpu_device *adev) } /** - * amdgpu_fence_driver_force_completion - force all fence waiter to complete + * amdgpu_fence_driver_force_completion - force signal latest fence of ring * - * @adev: amdgpu device pointer + * @ring: fence of the ring to signal * - * In case of GPU reset failure make sure no process keep waiting on fence - * that will never complete. */ -void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) +void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) { - int i; - - for (i = 0; i < AMDGPU_MAX_RINGS; i++) { - struct amdgpu_ring *ring = adev->rings[i]; - if (!ring || !ring->fence_drv.initialized) - continue; - - amdgpu_fence_write(ring, ring->fence_drv.sync_seq); - } -} - -void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring) -{ - if (ring) - amdgpu_fence_write(ring, ring->fence_drv.sync_seq); + amdgpu_fence_write(ring, ring->fence_drv.sync_seq); + amdgpu_fence_process(ring); } /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index b18c2b96691f..a6b89e3932a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -79,8 +79,7 @@ struct amdgpu_fence_driver { int amdgpu_fence_driver_init(struct amdgpu_device *adev); void amdgpu_fence_driver_fini(struct amdgpu_device *adev); -void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); -void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring); +void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, unsigned num_hw_submission); -- GitLab From 95aa9b1d9738faa80c66df41d59358d5ff4c288a Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 17 Oct 2017 13:40:54 +0800 Subject: [PATCH 0555/2547] drm/amdgpu:add hang_limit for sched(v2) since gpu_scheduler source domain cannot access amdgpu variable so need create the hang_limit membewr for sched, and it can refer it for the upcoming GPU RESET patches v2: make hang_limit a parameter of sched_init() Signed-off-by: Monk Liu Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 6 +++++- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 3 ++- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 219c15f79a5d..72e8eacc2c03 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -446,7 +446,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, timeout = MAX_SCHEDULE_TIMEOUT; } r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, - num_hw_submission, + num_hw_submission, amdgpu_job_hang_limit, timeout, ring->name); if (r) { DRM_ERROR("Failed to create scheduler on ring %s.\n", diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 9061c88e3e0c..5a1ece2774b5 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -676,13 +676,17 @@ static int amd_sched_main(void *param) */ int amd_sched_init(struct amd_gpu_scheduler *sched, const struct amd_sched_backend_ops *ops, - unsigned hw_submission, long timeout, const char *name) + unsigned hw_submission, + unsigned hang_limit, + long timeout, + const char *name) { int i; sched->ops = ops; sched->hw_submission_limit = hw_submission; sched->name = name; sched->timeout = timeout; + sched->hang_limit = hang_limit; for (i = AMD_SCHED_PRIORITY_MIN; i < AMD_SCHED_PRIORITY_MAX; i++) amd_sched_rq_init(&sched->sched_rq[i]); diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h index 3f75b45ed958..3ea75a2f35d4 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h @@ -144,11 +144,12 @@ struct amd_gpu_scheduler { struct task_struct *thread; struct list_head ring_mirror_list; spinlock_t job_list_lock; + int hang_limit; }; int amd_sched_init(struct amd_gpu_scheduler *sched, const struct amd_sched_backend_ops *ops, - uint32_t hw_submission, long timeout, const char *name); + uint32_t hw_submission, unsigned hang_limit, long timeout, const char *name); void amd_sched_fini(struct amd_gpu_scheduler *sched); int amd_sched_entity_init(struct amd_gpu_scheduler *sched, -- GitLab From b3eebe3d899fdcc77297f1513983a5250f0bed80 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Mon, 23 Oct 2017 12:23:29 +0800 Subject: [PATCH 0556/2547] drm/amd/scheduler:introduce guilty pointer member this member will be used later, it will points to the real var inside of context and CS_SUBMIT & gpu schdduler can decide if skip a job depends on context->guilty or *entity->guilty Signed-off-by: Monk Liu Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 3 ++- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 3 ++- 10 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index c184468e2b2b..bb5a46a000ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -90,7 +90,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, continue; r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r) goto failed; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index ad5bf86ee8a3..bdefc7b9fcff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -110,7 +110,7 @@ static int amdgpu_ttm_global_init(struct amdgpu_device *adev) ring = adev->mman.buffer_funcs_ring; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; r = amd_sched_entity_init(&ring->sched, &adev->mman.entity, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r) { DRM_ERROR("Failed setting up TTM BO move run queue.\n"); goto error_entity; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index e8bd50cf9785..6604771356cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -232,7 +232,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) ring = &adev->uvd.ring; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r != 0) { DRM_ERROR("Failed setting up UVD run queue.\n"); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 2918de2f39ec..873c99518954 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -176,7 +176,7 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) ring = &adev->vce.ring[0]; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->vce.entity, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r != 0) { DRM_ERROR("Failed setting up VCE run queue.\n"); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 041e0121590c..96df21cca85d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -106,7 +106,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) ring = &adev->vcn.ring_dec; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_dec, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r != 0) { DRM_ERROR("Failed setting up VCN dec run queue.\n"); return r; @@ -115,7 +115,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) ring = &adev->vcn.ring_enc[0]; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_enc, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r != 0) { DRM_ERROR("Failed setting up VCN enc run queue.\n"); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index c8c26f21993c..1e727da2bb64 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2637,7 +2637,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, ring = adev->vm_manager.vm_pte_rings[ring_instance]; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; r = amd_sched_entity_init(&ring->sched, &vm->entity, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 920910ac8663..246dfd74f5c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -416,7 +416,7 @@ static int uvd_v6_0_sw_init(void *handle) ring = &adev->uvd.ring_enc[0]; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r) { DRM_ERROR("Failed setting up UVD ENC run queue.\n"); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 6634545060fd..762ff3901a7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -418,7 +418,7 @@ static int uvd_v7_0_sw_init(void *handle) ring = &adev->uvd.ring_enc[0]; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r) { DRM_ERROR("Failed setting up UVD ENC run queue.\n"); return r; diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 5a1ece2774b5..764606ce3541 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -121,7 +121,7 @@ amd_sched_rq_select_entity(struct amd_sched_rq *rq) int amd_sched_entity_init(struct amd_gpu_scheduler *sched, struct amd_sched_entity *entity, struct amd_sched_rq *rq, - uint32_t jobs) + uint32_t jobs, atomic_t *guilty) { int r; @@ -132,6 +132,7 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched, INIT_LIST_HEAD(&entity->list); entity->rq = rq; entity->sched = sched; + entity->guilty = guilty; spin_lock_init(&entity->rq_lock); spin_lock_init(&entity->queue_lock); diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h index 3ea75a2f35d4..a05994c60b34 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h @@ -63,6 +63,7 @@ struct amd_sched_entity { struct dma_fence *dependency; struct dma_fence_cb cb; + atomic_t *guilty; /* points to ctx's guilty */ }; /** @@ -155,7 +156,7 @@ void amd_sched_fini(struct amd_gpu_scheduler *sched); int amd_sched_entity_init(struct amd_gpu_scheduler *sched, struct amd_sched_entity *entity, struct amd_sched_rq *rq, - uint32_t jobs); + uint32_t jobs, atomic_t* guilty); void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, struct amd_sched_entity *entity); void amd_sched_entity_push_job(struct amd_sched_job *sched_job); -- GitLab From 1102900de082a7ef6991de0ad2ff88047ae859b3 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Mon, 23 Oct 2017 12:25:24 +0800 Subject: [PATCH 0557/2547] drm/amdgpu:pass ctx->guilty address to entity init this way the real interested guilty is connected to entity->guilty pointer, and we can use entity->pointer later in gpu recovery procedure Signed-off-by: Monk Liu Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 0b14b5373783..64a0d384171b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -743,6 +743,7 @@ struct amdgpu_ctx { enum amd_sched_priority init_priority; enum amd_sched_priority override_priority; struct mutex lock; + atomic_t guilty; }; struct amdgpu_ctx_mgr { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index bb5a46a000ee..1bf4cdc597aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -90,7 +90,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, continue; r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity, - rq, amdgpu_sched_jobs, NULL); + rq, amdgpu_sched_jobs, &ctx->guilty); if (r) goto failed; } -- GitLab From 7716ea564f6538236c34749cdf3a6351c2844c1a Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 17 Oct 2017 12:08:02 +0800 Subject: [PATCH 0558/2547] drm/amdgpu:skip job for guilty ctx in parser_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index b4b3ecf9f96d..16947bad5b49 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -90,6 +90,12 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) goto free_chunk; } + /* skip guilty context job */ + if (atomic_read(&p->ctx->guilty) == 1) { + ret = -ECANCELED; + goto free_chunk; + } + mutex_lock(&p->ctx->lock); /* get chunks */ -- GitLab From a8a51a70416baab813606c6014c5f0746958dfb2 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Mon, 16 Oct 2017 19:46:43 +0800 Subject: [PATCH 0559/2547] drm/amdgpu:cleanup job reset routine(v2) merge the setting guilty on context into this function to avoid implement extra routine. v2: go through entity list and compare the fence_ctx before operate on the entity, otherwise the entity may be just a wild pointer Signed-off-by: Monk Liu Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 31 ++++++++++++++++++- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 2 +- 3 files changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 620e3002001d..d5d450e380bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2869,7 +2869,7 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) amd_sched_job_kickout(&job->base); /* only do job_reset on the hang ring if @job not NULL */ - amd_sched_hw_job_reset(&ring->sched); + amd_sched_hw_job_reset(&ring->sched, NULL); /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ amdgpu_fence_driver_force_completion(ring); @@ -2990,7 +2990,7 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) if (!ring || !ring->sched.thread) continue; kthread_park(ring->sched.thread); - amd_sched_hw_job_reset(&ring->sched); + amd_sched_hw_job_reset(&ring->sched, NULL); /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ amdgpu_fence_driver_force_completion(ring); } diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 764606ce3541..1474866d9048 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -443,9 +443,18 @@ static void amd_sched_job_timedout(struct work_struct *work) job->sched->ops->timedout_job(job); } -void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched) +static void amd_sched_set_guilty(struct amd_sched_job *s_job) +{ + if (atomic_inc_return(&s_job->karma) > s_job->sched->hang_limit) + if (s_job->s_entity->guilty) + atomic_set(s_job->s_entity->guilty, 1); +} + +void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_job *bad) { struct amd_sched_job *s_job; + struct amd_sched_entity *entity, *tmp; + int i;; spin_lock(&sched->job_list_lock); list_for_each_entry_reverse(s_job, &sched->ring_mirror_list, node) { @@ -458,6 +467,26 @@ void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched) } } spin_unlock(&sched->job_list_lock); + + if (bad) { + bool found = false; + + for (i = AMD_SCHED_PRIORITY_MIN; i < AMD_SCHED_PRIORITY_MAX; i++ ) { + struct amd_sched_rq *rq = &sched->sched_rq[i]; + + spin_lock(&rq->lock); + list_for_each_entry_safe(entity, tmp, &rq->entities, list) { + if (bad->s_fence->scheduled.context == entity->fence_context) { + found = true; + amd_sched_set_guilty(bad); + break; + } + } + spin_unlock(&rq->lock); + if (found) + break; + } + } } void amd_sched_job_kickout(struct amd_sched_job *s_job) diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h index a05994c60b34..be75172587da 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h @@ -174,7 +174,7 @@ int amd_sched_job_init(struct amd_sched_job *job, struct amd_gpu_scheduler *sched, struct amd_sched_entity *entity, void *owner); -void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched); +void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_job *job); void amd_sched_job_recovery(struct amd_gpu_scheduler *sched); bool amd_sched_dependency_optimized(struct dma_fence* fence, struct amd_sched_entity *entity); -- GitLab From 27105db6c63a571b91d01e749d026105a1e63bcf Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 12 Oct 2017 16:41:39 -0400 Subject: [PATCH 0560/2547] drm/amdgpu: Add SPSC queue to scheduler. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is intended to sabstitute the bounded fifo we are currently using. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/scheduler/spsc_queue.h | 121 +++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 drivers/gpu/drm/amd/scheduler/spsc_queue.h diff --git a/drivers/gpu/drm/amd/scheduler/spsc_queue.h b/drivers/gpu/drm/amd/scheduler/spsc_queue.h new file mode 100644 index 000000000000..5902f35ce759 --- /dev/null +++ b/drivers/gpu/drm/amd/scheduler/spsc_queue.h @@ -0,0 +1,121 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef AMD_SCHEDULER_SPSC_QUEUE_H_ +#define AMD_SCHEDULER_SPSC_QUEUE_H_ + +#include + +/** SPSC lockless queue */ + +struct spsc_node { + + /* Stores spsc_node* */ + struct spsc_node *next; +}; + +struct spsc_queue { + + struct spsc_node *head; + + /* atomic pointer to struct spsc_node* */ + atomic_long_t tail; + + atomic_t job_count; +}; + +static inline void spsc_queue_init(struct spsc_queue *queue) +{ + queue->head = NULL; + atomic_long_set(&queue->tail, (long)&queue->head); + atomic_set(&queue->job_count, 0); +} + +static inline struct spsc_node *spsc_queue_peek(struct spsc_queue *queue) +{ + return queue->head; +} + +static inline int spsc_queue_count(struct spsc_queue *queue) +{ + return atomic_read(&queue->job_count); +} + +static inline bool spsc_queue_push(struct spsc_queue *queue, struct spsc_node *node) +{ + struct spsc_node **tail; + + node->next = NULL; + + preempt_disable(); + + tail = (struct spsc_node **)atomic_long_xchg(&queue->tail, (long)&node->next); + WRITE_ONCE(*tail, node); + atomic_inc(&queue->job_count); + + /* + * In case of first element verify new node will be visible to the consumer + * thread when we ping the kernel thread that there is new work to do. + */ + smp_wmb(); + + preempt_enable(); + + return tail == &queue->head; +} + + +static inline struct spsc_node *spsc_queue_pop(struct spsc_queue *queue) +{ + struct spsc_node *next, *node; + + /* Verify reading from memory and not the cache */ + smp_rmb(); + + node = READ_ONCE(queue->head); + + if (!node) + return NULL; + + next = READ_ONCE(node->next); + WRITE_ONCE(queue->head, next); + + if (unlikely(!next)) { + /* slowpath for the last element in the queue */ + + if (atomic_long_cmpxchg(&queue->tail, + (long)&node->next, (long) &queue->head) != (long)&node->next) { + /* Updating tail failed wait for new next to appear */ + do { + smp_rmb(); + } while (unlikely(!(queue->head = READ_ONCE(node->next)))); + } + } + + atomic_dec(&queue->job_count); + return node; +} + + + +#endif /* AMD_SCHEDULER_SPSC_QUEUE_H_ */ -- GitLab From 83f4b1180155f2d65472ce943a1f051215030560 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 12 Oct 2017 16:46:26 -0400 Subject: [PATCH 0561/2547] drm/amdgpu: Fix deadlock during GPU reset. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bug: Kfifo is limited at size, during GPU reset it would fill up to limit and the pushing thread (producer) would wait for the scheduler worker to consume the items in the fifo while holding reservation lock on a BO. The gpu reset thread on the other hand blocks the scheduler during reset. Before it unblocks the sceduler it might want to recover VRAM and so will try to reserve the same BO the producer thread is already holding creating a deadlock. Fix: Switch from kfifo to SPSC queue which is unlimited in size. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- .../gpu/drm/amd/scheduler/gpu_sched_trace.h | 4 +- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 68 +++++++------------ drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 4 +- 3 files changed, 29 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h index 283a0dc25e84..705380eb693c 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h @@ -29,8 +29,8 @@ TRACE_EVENT(amd_sched_job, __entry->id = sched_job->id; __entry->fence = &sched_job->s_fence->finished; __entry->name = sched_job->sched->name; - __entry->job_count = kfifo_len( - &sched_job->s_entity->job_queue) / sizeof(sched_job); + __entry->job_count = spsc_queue_count( + &sched_job->s_entity->job_queue); __entry->hw_job_count = atomic_read( &sched_job->sched->hw_rq_count); ), diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 1474866d9048..1a2267ce62a8 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -28,9 +28,14 @@ #include #include "gpu_scheduler.h" +#include "spsc_queue.h" + #define CREATE_TRACE_POINTS #include "gpu_sched_trace.h" +#define to_amd_sched_job(sched_job) \ + container_of((sched_job), struct amd_sched_job, queue_node) + static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity); static void amd_sched_wakeup(struct amd_gpu_scheduler *sched); static void amd_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb); @@ -123,8 +128,6 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched, struct amd_sched_rq *rq, uint32_t jobs, atomic_t *guilty) { - int r; - if (!(sched && entity && rq)) return -EINVAL; @@ -136,9 +139,7 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched, spin_lock_init(&entity->rq_lock); spin_lock_init(&entity->queue_lock); - r = kfifo_alloc(&entity->job_queue, jobs * sizeof(void *), GFP_KERNEL); - if (r) - return r; + spsc_queue_init(&entity->job_queue); atomic_set(&entity->fence_seq, 0); entity->fence_context = dma_fence_context_alloc(2); @@ -171,7 +172,7 @@ static bool amd_sched_entity_is_initialized(struct amd_gpu_scheduler *sched, static bool amd_sched_entity_is_idle(struct amd_sched_entity *entity) { rmb(); - if (kfifo_is_empty(&entity->job_queue)) + if (spsc_queue_peek(&entity->job_queue) == NULL) return true; return false; @@ -186,7 +187,7 @@ static bool amd_sched_entity_is_idle(struct amd_sched_entity *entity) */ static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity) { - if (kfifo_is_empty(&entity->job_queue)) + if (spsc_queue_peek(&entity->job_queue) == NULL) return false; if (READ_ONCE(entity->dependency)) @@ -228,7 +229,7 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, */ kthread_park(sched->thread); kthread_unpark(sched->thread); - while (kfifo_out(&entity->job_queue, &job, sizeof(job))) { + while ((job = to_amd_sched_job(spsc_queue_pop(&entity->job_queue)))) { struct amd_sched_fence *s_fence = job->s_fence; amd_sched_fence_scheduled(s_fence); dma_fence_set_error(&s_fence->finished, -ESRCH); @@ -236,9 +237,7 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, dma_fence_put(&s_fence->finished); sched->ops->free_job(job); } - } - kfifo_free(&entity->job_queue); } static void amd_sched_entity_wakeup(struct dma_fence *f, struct dma_fence_cb *cb) @@ -333,40 +332,41 @@ static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity) } static struct amd_sched_job * -amd_sched_entity_peek_job(struct amd_sched_entity *entity) +amd_sched_entity_pop_job(struct amd_sched_entity *entity) { struct amd_gpu_scheduler *sched = entity->sched; - struct amd_sched_job *sched_job; + struct amd_sched_job *sched_job = to_amd_sched_job( + spsc_queue_peek(&entity->job_queue)); - if (!kfifo_out_peek(&entity->job_queue, &sched_job, sizeof(sched_job))) + if (!sched_job) return NULL; while ((entity->dependency = sched->ops->dependency(sched_job))) if (amd_sched_entity_add_dependency_cb(entity)) return NULL; + sched_job->s_entity = NULL; + spsc_queue_pop(&entity->job_queue); return sched_job; } /** - * Helper to submit a job to the job queue + * Submit a job to the job queue * * @sched_job The pointer to job required to submit * - * Returns true if we could submit the job. + * Returns 0 for success, negative error code otherwise. */ -static bool amd_sched_entity_in(struct amd_sched_job *sched_job) +void amd_sched_entity_push_job(struct amd_sched_job *sched_job) { struct amd_gpu_scheduler *sched = sched_job->sched; struct amd_sched_entity *entity = sched_job->s_entity; - bool added, first = false; + bool first = false; - spin_lock(&entity->queue_lock); - added = kfifo_in(&entity->job_queue, &sched_job, - sizeof(sched_job)) == sizeof(sched_job); + trace_amd_sched_job(sched_job); - if (added && kfifo_len(&entity->job_queue) == sizeof(sched_job)) - first = true; + spin_lock(&entity->queue_lock); + first = spsc_queue_push(&entity->job_queue, &sched_job->queue_node); spin_unlock(&entity->queue_lock); @@ -378,7 +378,6 @@ static bool amd_sched_entity_in(struct amd_sched_job *sched_job) spin_unlock(&entity->rq_lock); amd_sched_wakeup(sched); } - return added; } /* job_finish is called after hw fence signaled @@ -535,22 +534,6 @@ void amd_sched_job_recovery(struct amd_gpu_scheduler *sched) spin_unlock(&sched->job_list_lock); } -/** - * Submit a job to the job queue - * - * @sched_job The pointer to job required to submit - * - * Returns 0 for success, negative error code otherwise. - */ -void amd_sched_entity_push_job(struct amd_sched_job *sched_job) -{ - struct amd_sched_entity *entity = sched_job->s_entity; - - trace_amd_sched_job(sched_job); - wait_event(entity->sched->job_scheduled, - amd_sched_entity_in(sched_job)); -} - /* init a sched_job with basic field */ int amd_sched_job_init(struct amd_sched_job *job, struct amd_gpu_scheduler *sched, @@ -641,7 +624,7 @@ static int amd_sched_main(void *param) { struct sched_param sparam = {.sched_priority = 1}; struct amd_gpu_scheduler *sched = (struct amd_gpu_scheduler *)param; - int r, count; + int r; sched_setscheduler(current, SCHED_FIFO, &sparam); @@ -659,7 +642,7 @@ static int amd_sched_main(void *param) if (!entity) continue; - sched_job = amd_sched_entity_peek_job(entity); + sched_job = amd_sched_entity_pop_job(entity); if (!sched_job) continue; @@ -686,9 +669,6 @@ static int amd_sched_main(void *param) amd_sched_process_job(NULL, &s_fence->cb); } - count = kfifo_out(&entity->job_queue, &sched_job, - sizeof(sched_job)); - WARN_ON(count != sizeof(sched_job)); wake_up(&sched->job_scheduled); } return 0; diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h index be75172587da..f9e3a83cddc6 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h @@ -26,6 +26,7 @@ #include #include +#include "spsc_queue.h" struct amd_gpu_scheduler; struct amd_sched_rq; @@ -56,7 +57,7 @@ struct amd_sched_entity { struct amd_gpu_scheduler *sched; spinlock_t queue_lock; - struct kfifo job_queue; + struct spsc_queue job_queue; atomic_t fence_seq; uint64_t fence_context; @@ -88,6 +89,7 @@ struct amd_sched_fence { }; struct amd_sched_job { + struct spsc_node queue_node; struct amd_gpu_scheduler *sched; struct amd_sched_entity *s_entity; struct amd_sched_fence *s_fence; -- GitLab From a4176cb484ac457a08b44c93da06fce09c6e281c Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 24 Oct 2017 13:30:16 -0400 Subject: [PATCH 0562/2547] drm/amdgpu: Remove job->s_entity to avoid keeping reference to stale pointer. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 7 ++++--- .../gpu/drm/amd/scheduler/gpu_sched_trace.h | 9 ++++----- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 19 +++++++++---------- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 7 ++++--- 5 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 16947bad5b49..bf1aad00bb8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1203,7 +1203,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, amdgpu_ring_priority_get(job->ring, job->base.s_priority); trace_amdgpu_cs_ioctl(job); - amd_sched_entity_push_job(&job->base); + amd_sched_entity_push_job(&job->base, entity); ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence); amdgpu_mn_unlock(p->mn); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index a58e3c5dd84b..f60662e03761 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -142,12 +142,13 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, *f = dma_fence_get(&job->base.s_fence->finished); amdgpu_job_free_resources(job); amdgpu_ring_priority_get(job->ring, job->base.s_priority); - amd_sched_entity_push_job(&job->base); + amd_sched_entity_push_job(&job->base, entity); return 0; } -static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job) +static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job, + struct amd_sched_entity *s_entity) { struct amdgpu_job *job = to_amdgpu_job(sched_job); struct amdgpu_vm *vm = job->vm; @@ -155,7 +156,7 @@ static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job) struct dma_fence *fence = amdgpu_sync_get_fence(&job->dep_sync); int r; - if (amd_sched_dependency_optimized(fence, sched_job->s_entity)) { + if (amd_sched_dependency_optimized(fence, s_entity)) { r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence); if (r) DRM_ERROR("Error adding fence to sync (%d)\n", r); diff --git a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h index 705380eb693c..eebe323c7159 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h @@ -13,8 +13,8 @@ #define TRACE_INCLUDE_FILE gpu_sched_trace TRACE_EVENT(amd_sched_job, - TP_PROTO(struct amd_sched_job *sched_job), - TP_ARGS(sched_job), + TP_PROTO(struct amd_sched_job *sched_job, struct amd_sched_entity *entity), + TP_ARGS(sched_job, entity), TP_STRUCT__entry( __field(struct amd_sched_entity *, entity) __field(struct dma_fence *, fence) @@ -25,12 +25,11 @@ TRACE_EVENT(amd_sched_job, ), TP_fast_assign( - __entry->entity = sched_job->s_entity; + __entry->entity = entity; __entry->id = sched_job->id; __entry->fence = &sched_job->s_fence->finished; __entry->name = sched_job->sched->name; - __entry->job_count = spsc_queue_count( - &sched_job->s_entity->job_queue); + __entry->job_count = spsc_queue_count(&entity->job_queue); __entry->hw_job_count = atomic_read( &sched_job->sched->hw_rq_count); ), diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 1a2267ce62a8..f116de798204 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -341,11 +341,10 @@ amd_sched_entity_pop_job(struct amd_sched_entity *entity) if (!sched_job) return NULL; - while ((entity->dependency = sched->ops->dependency(sched_job))) + while ((entity->dependency = sched->ops->dependency(sched_job, entity))) if (amd_sched_entity_add_dependency_cb(entity)) return NULL; - sched_job->s_entity = NULL; spsc_queue_pop(&entity->job_queue); return sched_job; } @@ -357,13 +356,13 @@ amd_sched_entity_pop_job(struct amd_sched_entity *entity) * * Returns 0 for success, negative error code otherwise. */ -void amd_sched_entity_push_job(struct amd_sched_job *sched_job) +void amd_sched_entity_push_job(struct amd_sched_job *sched_job, + struct amd_sched_entity *entity) { struct amd_gpu_scheduler *sched = sched_job->sched; - struct amd_sched_entity *entity = sched_job->s_entity; bool first = false; - trace_amd_sched_job(sched_job); + trace_amd_sched_job(sched_job, entity); spin_lock(&entity->queue_lock); first = spsc_queue_push(&entity->job_queue, &sched_job->queue_node); @@ -442,11 +441,12 @@ static void amd_sched_job_timedout(struct work_struct *work) job->sched->ops->timedout_job(job); } -static void amd_sched_set_guilty(struct amd_sched_job *s_job) +static void amd_sched_set_guilty(struct amd_sched_job *s_job, + struct amd_sched_entity *s_entity) { if (atomic_inc_return(&s_job->karma) > s_job->sched->hang_limit) - if (s_job->s_entity->guilty) - atomic_set(s_job->s_entity->guilty, 1); + if (s_entity->guilty) + atomic_set(s_entity->guilty, 1); } void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_job *bad) @@ -477,7 +477,7 @@ void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_jo list_for_each_entry_safe(entity, tmp, &rq->entities, list) { if (bad->s_fence->scheduled.context == entity->fence_context) { found = true; - amd_sched_set_guilty(bad); + amd_sched_set_guilty(bad, entity); break; } } @@ -541,7 +541,6 @@ int amd_sched_job_init(struct amd_sched_job *job, void *owner) { job->sched = sched; - job->s_entity = entity; job->s_priority = entity->rq - sched->sched_rq; job->s_fence = amd_sched_fence_create(entity, owner); if (!job->s_fence) diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h index f9e3a83cddc6..b590fcc2786a 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h @@ -91,7 +91,6 @@ struct amd_sched_fence { struct amd_sched_job { struct spsc_node queue_node; struct amd_gpu_scheduler *sched; - struct amd_sched_entity *s_entity; struct amd_sched_fence *s_fence; struct dma_fence_cb finish_cb; struct work_struct finish_work; @@ -125,7 +124,8 @@ static inline bool amd_sched_invalidate_job(struct amd_sched_job *s_job, int thr * these functions should be implemented in driver side */ struct amd_sched_backend_ops { - struct dma_fence *(*dependency)(struct amd_sched_job *sched_job); + struct dma_fence *(*dependency)(struct amd_sched_job *sched_job, + struct amd_sched_entity *s_entity); struct dma_fence *(*run_job)(struct amd_sched_job *sched_job); void (*timedout_job)(struct amd_sched_job *sched_job); void (*free_job)(struct amd_sched_job *sched_job); @@ -161,7 +161,8 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched, uint32_t jobs, atomic_t* guilty); void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, struct amd_sched_entity *entity); -void amd_sched_entity_push_job(struct amd_sched_job *sched_job); +void amd_sched_entity_push_job(struct amd_sched_job *sched_job, + struct amd_sched_entity *entity); void amd_sched_entity_set_rq(struct amd_sched_entity *entity, struct amd_sched_rq *rq); -- GitLab From 668ca1b44de16a8182419cc1a5913d33cc6263bd Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 17 Oct 2017 14:39:23 +0800 Subject: [PATCH 0563/2547] drm/amdgpu:don't change ctx->reset_couner upon query MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit reset_counter marks the reset counter number once the context is created, shouldn't be changed due to query. To keep U/K interface on the ctx_query and keep ctx's reset_counter logic compatible with GPU RESET feature, now use another var named "reset_counter_query" to replace the original checked & updated in amdgpu_ctx_query. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 64a0d384171b..34268aac6b9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -735,6 +735,7 @@ struct amdgpu_ctx { struct amdgpu_device *adev; struct amdgpu_queue_mgr queue_mgr; unsigned reset_counter; + unsigned reset_counter_query; uint32_t vram_lost_counter; spinlock_t ring_lock; struct dma_fence **fences; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index 1bf4cdc597aa..c539fb6a597e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -75,6 +75,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, } ctx->reset_counter = atomic_read(&adev->gpu_reset_counter); + ctx->reset_counter_query = ctx->reset_counter; ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter); ctx->init_priority = priority; ctx->override_priority = AMD_SCHED_PRIORITY_UNSET; @@ -216,11 +217,11 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev, /* determine if a GPU reset has occured since the last call */ reset_counter = atomic_read(&adev->gpu_reset_counter); /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ - if (ctx->reset_counter == reset_counter) + if (ctx->reset_counter_query == reset_counter) out->state.reset_status = AMDGPU_CTX_NO_RESET; else out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; - ctx->reset_counter = reset_counter; + ctx->reset_counter_query = reset_counter; mutex_unlock(&mgr->lock); return 0; -- GitLab From bc1b1bf6e347af908c9a994803e18e2e22cf84b3 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 17 Oct 2017 14:58:01 +0800 Subject: [PATCH 0564/2547] drm/amdgpu:implement ctx query2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this query will give flag bits to indicate what happend on the given context Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 37 +++++++++++++++++++++++++ include/uapi/drm/amdgpu_drm.h | 8 ++++++ 2 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index c539fb6a597e..d71dc164b469 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -227,6 +227,40 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev, return 0; } +static int amdgpu_ctx_query2(struct amdgpu_device *adev, + struct amdgpu_fpriv *fpriv, uint32_t id, + union drm_amdgpu_ctx_out *out) +{ + struct amdgpu_ctx *ctx; + struct amdgpu_ctx_mgr *mgr; + + if (!fpriv) + return -EINVAL; + + mgr = &fpriv->ctx_mgr; + mutex_lock(&mgr->lock); + ctx = idr_find(&mgr->ctx_handles, id); + if (!ctx) { + mutex_unlock(&mgr->lock); + return -EINVAL; + } + + out->state.flags = 0x0; + out->state.hangs = 0x0; + + if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter)) + out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET; + + if (ctx->vram_lost_counter != atomic_read(&adev->vram_lost_counter)) + out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST; + + if (atomic_read(&ctx->guilty)) + out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; + + mutex_unlock(&mgr->lock); + return 0; +} + int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { @@ -258,6 +292,9 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, case AMDGPU_CTX_OP_QUERY_STATE: r = amdgpu_ctx_query(adev, fpriv, id, &args->out); break; + case AMDGPU_CTX_OP_QUERY_STATE2: + r = amdgpu_ctx_query2(adev, fpriv, id, &args->out); + break; default: return -EINVAL; } diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 919248fb4028..0e23ce3f3113 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -160,6 +160,7 @@ union drm_amdgpu_bo_list { #define AMDGPU_CTX_OP_ALLOC_CTX 1 #define AMDGPU_CTX_OP_FREE_CTX 2 #define AMDGPU_CTX_OP_QUERY_STATE 3 +#define AMDGPU_CTX_OP_QUERY_STATE2 4 /* GPU reset status */ #define AMDGPU_CTX_NO_RESET 0 @@ -170,6 +171,13 @@ union drm_amdgpu_bo_list { /* unknown cause */ #define AMDGPU_CTX_UNKNOWN_RESET 3 +/* indicate gpu reset occured after ctx created */ +#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) +/* indicate vram lost occured after ctx created */ +#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) +/* indicate some job from this context once cause gpu hang */ +#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) + /* Context priority level */ #define AMDGPU_CTX_PRIORITY_UNSET -2048 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 -- GitLab From 9953b72f9c9cb7733334753788faab33ccc4dc0a Mon Sep 17 00:00:00 2001 From: pding Date: Thu, 26 Oct 2017 09:30:38 +0800 Subject: [PATCH 0565/2547] drm/amdgpu: change redundant init logs to debug level When this VF stays in exclusive mode for long, other VFs will be impacted. The redundant messages causes exclusive mode timeout when they're redirected. That is a normal use case for cloud service to redirect guest log to virtual serial port. Reviewed-by: Alex Deucher Signed-off-by: pding Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +--- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +++--- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 2 +- 24 files changed, 47 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 5432af39a674..c70cda04dbfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -85,7 +85,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions(); break; default: - dev_info(adev->dev, "kfd not supported on this ASIC\n"); + dev_dbg(adev->dev, "kfd not supported on this ASIC\n"); return; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index f450b69323fa..39f4d0df1ada 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -690,12 +690,12 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); /* set a reasonable default for DP */ if (adev->clock.default_dispclk < 53900) { - DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", - adev->clock.default_dispclk / 100); + DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n", + adev->clock.default_dispclk / 100); adev->clock.default_dispclk = 60000; } else if (adev->clock.default_dispclk <= 60000) { - DRM_INFO("Changing default dispclk from %dMhz to 625Mhz\n", - adev->clock.default_dispclk / 100); + DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n", + adev->clock.default_dispclk / 100); adev->clock.default_dispclk = 62500; } adev->clock.dp_extclk = diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index d5d450e380bd..212138476130 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1029,7 +1029,7 @@ static int amdgpu_atombios_init(struct amdgpu_device *adev) atom_card_info->ioreg_read = cail_ioreg_read; atom_card_info->ioreg_write = cail_ioreg_write; } else { - DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); + DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); atom_card_info->ioreg_read = cail_reg_read; atom_card_info->ioreg_write = cail_reg_write; } @@ -2267,8 +2267,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, dev_err(adev->dev, "gpu post error!\n"); goto failed; } - } else { - DRM_INFO("GPU post is not needed\n"); } if (adev->is_atom_fw) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index c2f414ffb2cc..6b11a75839e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -306,7 +306,6 @@ MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled) module_param_named(cik_support, amdgpu_cik_support, int, 0444); #endif - static const struct pci_device_id pciidlist[] = { #ifdef CONFIG_DRM_AMDGPU_SI {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 72e8eacc2c03..eda89dfdef5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -391,9 +391,9 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, ring->fence_drv.irq_type = irq_type; ring->fence_drv.initialized = true; - dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, " - "cpu addr 0x%p\n", ring->idx, - ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); + dev_dbg(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, " + "cpu addr 0x%p\n", ring->idx, + ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 47c5ce9807db..32590e4f9f7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -232,7 +232,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev) int ret = pci_enable_msi(adev->pdev); if (!ret) { adev->irq.msi_enabled = true; - dev_info(adev->dev, "amdgpu: using MSI.\n"); + dev_dbg(adev->dev, "amdgpu: using MSI.\n"); } } @@ -262,7 +262,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev) return r; } - DRM_INFO("amdgpu: irq initialized.\n"); + DRM_DEBUG("amdgpu: irq initialized.\n"); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index ea25164e7f4b..c48fc450d99b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -779,8 +779,8 @@ int amdgpu_bo_init(struct amdgpu_device *adev) adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, adev->mc.aper_size); DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", - adev->mc.mc_vram_size >> 20, - (unsigned long long)adev->mc.aper_size >> 20); + adev->mc.mc_vram_size >> 20, + (unsigned long long)adev->mc.aper_size >> 20); DRM_INFO("RAM width %dbits %s\n", adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]); return amdgpu_ttm_init(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 6604771356cd..be607b2be4e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -1218,7 +1218,7 @@ int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) } else if (r < 0) { DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); } else { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 873c99518954..92477e67087c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -954,7 +954,7 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring) } if (i < timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed\n", @@ -999,7 +999,7 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout) } else if (r < 0) { DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); } else { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } error: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 96df21cca85d..dabaca4da7f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -261,7 +261,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", @@ -467,7 +467,7 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) } else if (r < 0) { DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); } else { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } @@ -500,7 +500,7 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed\n", @@ -643,7 +643,7 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) } else if (r < 0) { DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); } else { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } error: diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 60cecd117705..ed26dcbc4f79 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -657,7 +657,7 @@ static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", ring->idx, tmp); @@ -724,7 +724,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = le32_to_cpu(adev->wb.wb[index]); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index dbbe986f90f2..9430d4809b53 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -1798,7 +1798,7 @@ static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) DRM_UDELAY(1); } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", ring->idx, scratch, tmp); @@ -1951,7 +1951,7 @@ static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 419ba0ce7ee5..015f37bef358 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2085,7 +2085,7 @@ static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) DRM_UDELAY(1); } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", ring->idx, scratch, tmp); @@ -2365,7 +2365,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 9ecdf621a74a..9f93e05bf97e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -804,7 +804,7 @@ static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring) DRM_UDELAY(1); } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", @@ -856,7 +856,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index da43813d67a4..a5811e80e21b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -327,7 +327,7 @@ static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) DRM_UDELAY(1); } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", @@ -379,7 +379,7 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 67f375bfe452..92f8c44a73b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -633,7 +633,7 @@ static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", ring->idx, tmp); @@ -704,7 +704,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = le32_to_cpu(adev->wb.wb[index]); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 6d06f8eb659f..52e6bf2e9e59 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -893,7 +893,7 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", ring->idx, tmp); @@ -964,7 +964,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = le32_to_cpu(adev->wb.wb[index]); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 46009db3d195..fe78c00b9ffa 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -919,7 +919,7 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", ring->idx, tmp); @@ -990,7 +990,7 @@ static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = le32_to_cpu(adev->wb.wb[index]); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 3fa2fbf8c9a1..ee469a906cd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -252,7 +252,7 @@ static int si_dma_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", ring->idx, tmp); @@ -317,7 +317,7 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = le32_to_cpu(adev->wb.wb[index]); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 8ab0f78794a5..15771a53038e 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -521,7 +521,7 @@ static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index bb6d46e168a3..3b29aaba783a 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -536,7 +536,7 @@ static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 246dfd74f5c9..0c01825a8b9e 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -184,7 +184,7 @@ static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed\n", @@ -360,7 +360,7 @@ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) } else if (r < 0) { DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); } else { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } error: @@ -1008,7 +1008,7 @@ static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 762ff3901a7a..7b77339feb1a 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -184,7 +184,7 @@ static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed\n", @@ -359,7 +359,7 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) } else if (r < 0) { DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); } else { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } error: @@ -1192,7 +1192,7 @@ static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index c7e34128cbde..726425809eed 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -122,7 +122,7 @@ static int pp_sw_init(void *handle) ret = hwmgr->smumgr_funcs->smu_init(hwmgr); - pr_info("amdgpu: powerplay sw initialized\n"); + pr_debug("amdgpu: powerplay sw initialized\n"); } return ret; } -- GitLab From 1366b2d01654d2028cba64109ad1bffb8afbef73 Mon Sep 17 00:00:00 2001 From: pding Date: Mon, 23 Oct 2017 16:31:04 +0800 Subject: [PATCH 0566/2547] drm/amdgpu: avoid soft lockup when waiting for RLC serdes (v2) Normally all waiting get timeout if there's one. Release the lock and return immediately when timeout happens. v2: - set the se_sh to broadcase before return Acked-by: Alex Deucher Signed-off-by: pding Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 9f93e05bf97e..46ee74393454 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3851,6 +3851,14 @@ static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev) break; udelay(1); } + if (k == adev->usec_timeout) { + gfx_v8_0_select_se_sh(adev, 0xffffffff, + 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + DRM_INFO("Timeout wait for RLC serdes %u,%u\n", + i, j); + return; + } } } gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index a5811e80e21b..46a0d3ef773f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1645,6 +1645,14 @@ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) break; udelay(1); } + if (k == adev->usec_timeout) { + gfx_v9_0_select_se_sh(adev, 0xffffffff, + 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + DRM_INFO("Timeout wait for RLC serdes %u,%u\n", + i, j); + return; + } } } gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); -- GitLab From a16f8f11c599cdec16e77020d56d230fedabe922 Mon Sep 17 00:00:00 2001 From: pding Date: Tue, 24 Oct 2017 10:01:13 +0800 Subject: [PATCH 0567/2547] drm/amdgpu/virt: add function to check MMIO (v2) MMIO space can be blocked on virtualised device. Add this function to check if MMIO is blocked or not. Todo: need a reliable method such like communation with hypervisor. v2: - add comments inline Signed-off-by: pding Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 6738df836a70..0f227cf7a67c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -24,6 +24,14 @@ #include "amdgpu.h" #define MAX_KIQ_REG_WAIT 100000000 /* in usecs */ +bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) +{ + /* By now all MMIO pages except mailbox are blocked */ + /* if blocking is enabled in hypervisor. Choose the */ + /* SCRATCH_REG0 to test. */ + return RREG32_NO_KIQ(0xc040) == 0xffffffff; +} + int amdgpu_allocate_static_csa(struct amdgpu_device *adev) { int r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index b89d37fc406f..81efb9d291c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -276,6 +276,7 @@ static inline bool is_virtual_machine(void) } struct amdgpu_vm; +bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); int amdgpu_allocate_static_csa(struct amdgpu_device *adev); int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amdgpu_bo_va **bo_va); -- GitLab From b636176efdf0e365a69613f03f6ecbf6fd0408cb Mon Sep 17 00:00:00 2001 From: pding Date: Tue, 24 Oct 2017 09:51:04 +0800 Subject: [PATCH 0568/2547] drm/amdgpu/virt: add wait_reset virt ops Driver can use this interface to check if there's a function level reset done in hypervisor. It's helpful when IRQ handler for reset is not ready, or special handling is required. Acked-by: Alex Deucher Reviewed-by: Monk Liu Signed-off-by: pding Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 16 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 0f227cf7a67c..b7510bf6bc0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -235,6 +235,22 @@ int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) return 0; } +/** + * amdgpu_virt_wait_reset() - wait for reset gpu completed + * @amdgpu: amdgpu device. + * Wait for GPU reset completed. + * Return: Zero if reset success, otherwise will return error. + */ +int amdgpu_virt_wait_reset(struct amdgpu_device *adev) +{ + struct amdgpu_virt *virt = &adev->virt; + + if (!virt->ops || !virt->ops->wait_reset) + return -EINVAL; + + return virt->ops->wait_reset(adev); +} + /** * amdgpu_virt_alloc_mm_table() - alloc memory for mm table * @amdgpu: amdgpu device. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 81efb9d291c4..d149aca71a44 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -55,6 +55,7 @@ struct amdgpu_virt_ops { int (*req_full_gpu)(struct amdgpu_device *adev, bool init); int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); int (*reset_gpu)(struct amdgpu_device *adev); + int (*wait_reset)(struct amdgpu_device *adev); void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3); }; @@ -286,6 +287,7 @@ void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); +int amdgpu_virt_wait_reset(struct amdgpu_device *adev); int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job); int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); -- GitLab From 7413d2faef2d07c6ed558147c59b3f237afb1429 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Thu, 26 Oct 2017 17:29:34 +0800 Subject: [PATCH 0569/2547] drm/amd/powerplay: describe the PCIE link speed in right GT/s Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 6 +++--- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 +++--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index 68b505c768ad..5a60c161b0fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -6625,9 +6625,9 @@ static int ci_dpm_print_clock_levels(void *handle, for (i = 0; i < pcie_table->count; i++) size += sprintf(buf + size, "%d: %s %s\n", i, - (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" : - (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" : - (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "", + (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x1" : + (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" : + (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "", (i == now) ? "*" : ""); break; default: diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index e33ec7fc5d09..8edb0c4c3876 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -4339,9 +4339,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, for (i = 0; i < pcie_table->count; i++) size += sprintf(buf + size, "%d: %s %s\n", i, - (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" : - (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" : - (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "", + (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" : + (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" : + (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "", (i == now) ? "*" : ""); break; default: diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index f8d838c2c8ee..9d4955e33b25 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -4654,9 +4654,9 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, for (i = 0; i < pcie_table->count; i++) size += sprintf(buf + size, "%d: %s %s\n", i, - (pcie_table->pcie_gen[i] == 0) ? "2.5GB, x1" : - (pcie_table->pcie_gen[i] == 1) ? "5.0GB, x16" : - (pcie_table->pcie_gen[i] == 2) ? "8.0GB, x16" : "", + (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" : + (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" : + (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "", (i == now) ? "*" : ""); break; default: -- GitLab From b59142384ed6e2652004d2089bfd8f238bf7f0b9 Mon Sep 17 00:00:00 2001 From: pding Date: Tue, 24 Oct 2017 09:53:16 +0800 Subject: [PATCH 0570/2547] drm/amdgpu/virt: implement wait_reset callbacks for vi/ai Reviewed-by: Monk Liu Signed-off-by: pding Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 1 + drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index b4906d2f30d3..f91aab38637c 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -353,5 +353,6 @@ const struct amdgpu_virt_ops xgpu_ai_virt_ops = { .req_full_gpu = xgpu_ai_request_full_gpu_access, .rel_full_gpu = xgpu_ai_release_full_gpu_access, .reset_gpu = xgpu_ai_request_reset, + .wait_reset = NULL, .trans_msg = xgpu_ai_mailbox_trans_msg, }; diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index c25a831f94ec..27b03c773b1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -458,6 +458,11 @@ static int xgpu_vi_request_reset(struct amdgpu_device *adev) return xgpu_vi_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS); } +static int xgpu_vi_wait_reset_cmpl(struct amdgpu_device *adev) +{ + return xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL); +} + static int xgpu_vi_request_full_gpu_access(struct amdgpu_device *adev, bool init) { @@ -613,5 +618,6 @@ const struct amdgpu_virt_ops xgpu_vi_virt_ops = { .req_full_gpu = xgpu_vi_request_full_gpu_access, .rel_full_gpu = xgpu_vi_release_full_gpu_access, .reset_gpu = xgpu_vi_request_reset, + .wait_reset = xgpu_vi_wait_reset_cmpl, .trans_msg = NULL, /* Does not need to trans VF errors to host. */ }; -- GitLab From 8840a3878d40c9318b08932376fa31e763780dfe Mon Sep 17 00:00:00 2001 From: pding Date: Mon, 23 Oct 2017 17:22:09 +0800 Subject: [PATCH 0571/2547] drm/amdgpu: retry init if it fails due to exclusive mode timeout (v3) The exclusive mode has real-time limitation in reality, such like being done in 300ms. It's easy observed if running many VF/VMs in single host with heavy CPU workload. If we find the init fails due to exclusive mode timeout, try it again. v2: - rewrite the condition for readable value. v3: - fix typo, add comments for sleep Acked-by: Alex Deucher Signed-off-by: pding Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 15 +++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 212138476130..e521850e9409 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2303,6 +2303,15 @@ int amdgpu_device_init(struct amdgpu_device *adev, r = amdgpu_init(adev); if (r) { + /* failed in exclusive mode due to timeout */ + if (amdgpu_sriov_vf(adev) && + !amdgpu_sriov_runtime(adev) && + amdgpu_virt_mmio_blocked(adev) && + !amdgpu_virt_wait_reset(adev)) { + dev_err(adev->dev, "VF exclusive mode timeout\n"); + r = -EAGAIN; + goto failed; + } dev_err(adev->dev, "amdgpu_init failed\n"); amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); amdgpu_fini(adev); @@ -2390,6 +2399,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_vf_error_trans_all(adev); if (runtime) vga_switcheroo_fini_domain_pm_ops(adev->dev); + return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 720139e182a3..f313eee60c4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -86,7 +86,7 @@ void amdgpu_driver_unload_kms(struct drm_device *dev) int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) { struct amdgpu_device *adev; - int r, acpi_status; + int r, acpi_status, retry = 0; #ifdef CONFIG_DRM_AMDGPU_SI if (!amdgpu_si_support) { @@ -122,6 +122,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) } } #endif +retry_init: adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); if (adev == NULL) { @@ -144,7 +145,17 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) * VRAM allocation */ r = amdgpu_device_init(adev, dev, dev->pdev, flags); - if (r) { + if (r == -EAGAIN && ++retry <= 3) { + adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; + adev->virt.ops = NULL; + amdgpu_device_fini(adev); + kfree(adev); + dev->dev_private = NULL; + /* Don't request EX mode too frequently which is attacking */ + msleep(5000); + dev_err(&dev->pdev->dev, "retry init %d\n", retry); + goto retry_init; + } else if (r) { dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); goto out; } -- GitLab From 5e91fb57eb6ac027dcdaec6ced32658ca2dcd3f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 20 Oct 2017 13:11:00 +0200 Subject: [PATCH 0572/2547] drm/amdgpu: use the actual placement for pin accounting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows us to specify multiple possible placements again. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index c48fc450d99b..8a103303da3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -697,6 +697,8 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, } *gpu_addr = amdgpu_bo_gpu_offset(bo); } + + domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); if (domain == AMDGPU_GEM_DOMAIN_VRAM) { adev->vram_pin_size += amdgpu_bo_size(bo); if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) -- GitLab From ead282a4f55ae6476cf2d193d9b501a59810f689 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 20 Oct 2017 13:12:12 +0200 Subject: [PATCH 0573/2547] drm/amdgpu: always bind pinned BOs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We always need to bind pinned BOs, not just when the caller requested the address. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 8a103303da3e..6f876deaafc6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -688,15 +688,15 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, goto error; } + r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); + if (unlikely(r)) { + dev_err(adev->dev, "%p bind failed\n", bo); + goto error; + } + bo->pin_count = 1; - if (gpu_addr != NULL) { - r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); - if (unlikely(r)) { - dev_err(adev->dev, "%p bind failed\n", bo); - goto error; - } + if (gpu_addr != NULL) *gpu_addr = amdgpu_bo_gpu_offset(bo); - } domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); if (domain == AMDGPU_GEM_DOMAIN_VRAM) { -- GitLab From f5318959b51274a5feea129ce472fe66cecc5241 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 23 Oct 2017 17:29:36 +0200 Subject: [PATCH 0574/2547] drm/amdgpu: fix pin domain compatibility check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need to test if any domain fits, not all of them. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 6f876deaafc6..6d4b22fdc1b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -647,7 +647,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, if (bo->pin_count) { uint32_t mem_type = bo->tbo.mem.mem_type; - if (domain != amdgpu_mem_type_to_domain(mem_type)) + if (!(domain & amdgpu_mem_type_to_domain(mem_type))) return -EINVAL; bo->pin_count++; -- GitLab From 2a018f28a8996114515c29d8db4d8ec392306e43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 25 Oct 2017 21:37:35 +0200 Subject: [PATCH 0575/2547] drm/amdgpu: don't wait interruptible while binding GART space MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Display can't seem to handle this correctly. Signed-off-by: Christian König Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index bdefc7b9fcff..470b911200ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -912,7 +912,7 @@ int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem) placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp, true, false); + r = ttm_bo_mem_space(bo, &placement, &tmp, false, false); if (unlikely(r)) return r; -- GitLab From 4ff23be3d50a142ed0787fa6f276afc02ac2577d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 16 Oct 2017 17:24:21 +0200 Subject: [PATCH 0576/2547] drm/amdgpu: remove extra parameter from amdgpu_ttm_bind() v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We always use the BO mem now. v2: minor rebase Signed-off-by: Christian König Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index bf1aad00bb8d..43df84c13f21 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -684,7 +684,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, if (!r && p->uf_entry.robj) { struct amdgpu_bo *uf = p->uf_entry.robj; - r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem); + r = amdgpu_ttm_bind(&uf->tbo); p->job->uf_addr += amdgpu_bo_gpu_offset(uf); } @@ -1601,5 +1601,5 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, return r; } - return amdgpu_ttm_bind(&(*bo)->tbo, &(*bo)->tbo.mem); + return amdgpu_ttm_bind(&(*bo)->tbo); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 6d4b22fdc1b4..589aa5099881 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -688,7 +688,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, goto error; } - r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); + r = amdgpu_ttm_bind(&bo->tbo); if (unlikely(r)) { dev_err(adev->dev, "%p bind failed\n", bo); goto error; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 470b911200ae..6a724f9f1b86 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -889,7 +889,7 @@ bool amdgpu_ttm_is_bound(struct ttm_tt *ttm) return gtt && !list_empty(>t->list); } -int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem) +int amdgpu_ttm_bind(struct ttm_buffer_object *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct ttm_tt *ttm = bo->ttm; @@ -1628,7 +1628,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, } if (bo->tbo.mem.mem_type == TTM_PL_TT) { - r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); + r = amdgpu_ttm_bind(&bo->tbo); if (r) return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index abd4084982a3..0108a59559cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -91,7 +91,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); bool amdgpu_ttm_is_bound(struct ttm_tt *ttm); -int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem); +int amdgpu_ttm_bind(struct ttm_buffer_object *bo); int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); -- GitLab From 2c2b67b479af34fbdb202bb827a564db1d88fc57 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Thu, 28 Sep 2017 15:20:51 +0800 Subject: [PATCH 0577/2547] drm/amdgpu: move DC and PP shared data structures to dm_pp_interface.h Move the display/power interfaces to one place. Reviewed-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/dm_pp_interface.h | 144 ++++++++++++++++++ .../gpu/drm/amd/powerplay/inc/amd_powerplay.h | 143 ----------------- 2 files changed, 144 insertions(+), 143 deletions(-) diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/drm/amd/include/dm_pp_interface.h index 7343aed4d019..721473199921 100644 --- a/drivers/gpu/drm/amd/include/dm_pp_interface.h +++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h @@ -25,6 +25,145 @@ #define PP_MAX_CLOCK_LEVELS 8 +enum amd_pp_display_config_type{ + AMD_PP_DisplayConfigType_None = 0, + AMD_PP_DisplayConfigType_DP54 , + AMD_PP_DisplayConfigType_DP432 , + AMD_PP_DisplayConfigType_DP324 , + AMD_PP_DisplayConfigType_DP27, + AMD_PP_DisplayConfigType_DP243, + AMD_PP_DisplayConfigType_DP216, + AMD_PP_DisplayConfigType_DP162, + AMD_PP_DisplayConfigType_HDMI6G , + AMD_PP_DisplayConfigType_HDMI297 , + AMD_PP_DisplayConfigType_HDMI162, + AMD_PP_DisplayConfigType_LVDS, + AMD_PP_DisplayConfigType_DVI, + AMD_PP_DisplayConfigType_WIRELESS, + AMD_PP_DisplayConfigType_VGA +}; + +struct single_display_configuration +{ + uint32_t controller_index; + uint32_t controller_id; + uint32_t signal_type; + uint32_t display_state; + /* phy id for the primary internal transmitter */ + uint8_t primary_transmitter_phyi_d; + /* bitmap with the active lanes */ + uint8_t primary_transmitter_active_lanemap; + /* phy id for the secondary internal transmitter (for dual-link dvi) */ + uint8_t secondary_transmitter_phy_id; + /* bitmap with the active lanes */ + uint8_t secondary_transmitter_active_lanemap; + /* misc phy settings for SMU. */ + uint32_t config_flags; + uint32_t display_type; + uint32_t view_resolution_cx; + uint32_t view_resolution_cy; + enum amd_pp_display_config_type displayconfigtype; + uint32_t vertical_refresh; /* for active display */ +}; + +#define MAX_NUM_DISPLAY 32 + +struct amd_pp_display_configuration { + bool nb_pstate_switch_disable;/* controls NB PState switch */ + bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ + bool cpu_pstate_disable; + uint32_t cpu_pstate_separation_time; + + uint32_t num_display; /* total number of display*/ + uint32_t num_path_including_non_display; + uint32_t crossfire_display_index; + uint32_t min_mem_set_clock; + uint32_t min_core_set_clock; + /* unit 10KHz x bit*/ + uint32_t min_bus_bandwidth; + /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/ + uint32_t min_core_set_clock_in_sr; + + struct single_display_configuration displays[MAX_NUM_DISPLAY]; + + uint32_t vrefresh; /* for active display*/ + + uint32_t min_vblank_time; /* for active display*/ + bool multi_monitor_in_sync; + /* Controller Index of primary display - used in MCLK SMC switching hang + * SW Workaround*/ + uint32_t crtc_index; + /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ + uint32_t line_time_in_us; + bool invalid_vblank_time; + + uint32_t display_clk; + /* + * for given display configuration if multimonitormnsync == false then + * Memory clock DPMS with this latency or below is allowed, DPMS with + * higher latency not allowed. + */ + uint32_t dce_tolerable_mclk_in_active_latency; + uint32_t min_dcef_set_clk; + uint32_t min_dcef_deep_sleep_set_clk; +}; + +struct amd_pp_simple_clock_info { + uint32_t engine_max_clock; + uint32_t memory_max_clock; + uint32_t level; +}; + +enum PP_DAL_POWERLEVEL { + PP_DAL_POWERLEVEL_INVALID = 0, + PP_DAL_POWERLEVEL_ULTRALOW, + PP_DAL_POWERLEVEL_LOW, + PP_DAL_POWERLEVEL_NOMINAL, + PP_DAL_POWERLEVEL_PERFORMANCE, + + PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW, + PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW, + PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL, + PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE, + PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1, + PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1, + PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1, + PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1, +}; + +struct amd_pp_clock_info { + uint32_t min_engine_clock; + uint32_t max_engine_clock; + uint32_t min_memory_clock; + uint32_t max_memory_clock; + uint32_t min_bus_bandwidth; + uint32_t max_bus_bandwidth; + uint32_t max_engine_clock_in_sr; + uint32_t min_engine_clock_in_sr; + enum PP_DAL_POWERLEVEL max_clocks_state; +}; + +enum amd_pp_clock_type { + amd_pp_disp_clock = 1, + amd_pp_sys_clock, + amd_pp_mem_clock, + amd_pp_dcef_clock, + amd_pp_soc_clock, + amd_pp_pixel_clock, + amd_pp_phy_clock, + amd_pp_dcf_clock, + amd_pp_dpp_clock, + amd_pp_f_clock = amd_pp_dcef_clock, +}; + +#define MAX_NUM_CLOCKS 16 + +struct amd_pp_clocks { + uint32_t count; + uint32_t clock[MAX_NUM_CLOCKS]; + uint32_t latency[MAX_NUM_CLOCKS]; +}; + struct pp_clock_with_latency { uint32_t clocks_in_khz; uint32_t latency_in_us; @@ -45,6 +184,11 @@ struct pp_clock_levels_with_voltage { struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS]; }; +struct pp_display_clock_request { + enum amd_pp_clock_type clock_type; + uint32_t clock_freq_in_khz; +}; + #define PP_MAX_WM_SETS 4 enum pp_wm_set_id { diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index 95932cc88460..da2e6ee5b7fe 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -64,144 +64,6 @@ struct amd_pp_init { uint32_t feature_mask; }; -enum amd_pp_display_config_type{ - AMD_PP_DisplayConfigType_None = 0, - AMD_PP_DisplayConfigType_DP54 , - AMD_PP_DisplayConfigType_DP432 , - AMD_PP_DisplayConfigType_DP324 , - AMD_PP_DisplayConfigType_DP27, - AMD_PP_DisplayConfigType_DP243, - AMD_PP_DisplayConfigType_DP216, - AMD_PP_DisplayConfigType_DP162, - AMD_PP_DisplayConfigType_HDMI6G , - AMD_PP_DisplayConfigType_HDMI297 , - AMD_PP_DisplayConfigType_HDMI162, - AMD_PP_DisplayConfigType_LVDS, - AMD_PP_DisplayConfigType_DVI, - AMD_PP_DisplayConfigType_WIRELESS, - AMD_PP_DisplayConfigType_VGA -}; - -struct single_display_configuration -{ - uint32_t controller_index; - uint32_t controller_id; - uint32_t signal_type; - uint32_t display_state; - /* phy id for the primary internal transmitter */ - uint8_t primary_transmitter_phyi_d; - /* bitmap with the active lanes */ - uint8_t primary_transmitter_active_lanemap; - /* phy id for the secondary internal transmitter (for dual-link dvi) */ - uint8_t secondary_transmitter_phy_id; - /* bitmap with the active lanes */ - uint8_t secondary_transmitter_active_lanemap; - /* misc phy settings for SMU. */ - uint32_t config_flags; - uint32_t display_type; - uint32_t view_resolution_cx; - uint32_t view_resolution_cy; - enum amd_pp_display_config_type displayconfigtype; - uint32_t vertical_refresh; /* for active display */ -}; - -#define MAX_NUM_DISPLAY 32 - -struct amd_pp_display_configuration { - bool nb_pstate_switch_disable;/* controls NB PState switch */ - bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ - bool cpu_pstate_disable; - uint32_t cpu_pstate_separation_time; - - uint32_t num_display; /* total number of display*/ - uint32_t num_path_including_non_display; - uint32_t crossfire_display_index; - uint32_t min_mem_set_clock; - uint32_t min_core_set_clock; - /* unit 10KHz x bit*/ - uint32_t min_bus_bandwidth; - /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/ - uint32_t min_core_set_clock_in_sr; - - struct single_display_configuration displays[MAX_NUM_DISPLAY]; - - uint32_t vrefresh; /* for active display*/ - - uint32_t min_vblank_time; /* for active display*/ - bool multi_monitor_in_sync; - /* Controller Index of primary display - used in MCLK SMC switching hang - * SW Workaround*/ - uint32_t crtc_index; - /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ - uint32_t line_time_in_us; - bool invalid_vblank_time; - - uint32_t display_clk; - /* - * for given display configuration if multimonitormnsync == false then - * Memory clock DPMS with this latency or below is allowed, DPMS with - * higher latency not allowed. - */ - uint32_t dce_tolerable_mclk_in_active_latency; - uint32_t min_dcef_set_clk; - uint32_t min_dcef_deep_sleep_set_clk; -}; - -struct amd_pp_simple_clock_info { - uint32_t engine_max_clock; - uint32_t memory_max_clock; - uint32_t level; -}; - -enum PP_DAL_POWERLEVEL { - PP_DAL_POWERLEVEL_INVALID = 0, - PP_DAL_POWERLEVEL_ULTRALOW, - PP_DAL_POWERLEVEL_LOW, - PP_DAL_POWERLEVEL_NOMINAL, - PP_DAL_POWERLEVEL_PERFORMANCE, - - PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW, - PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW, - PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL, - PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE, - PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1, - PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1, - PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1, - PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1, -}; - -struct amd_pp_clock_info { - uint32_t min_engine_clock; - uint32_t max_engine_clock; - uint32_t min_memory_clock; - uint32_t max_memory_clock; - uint32_t min_bus_bandwidth; - uint32_t max_bus_bandwidth; - uint32_t max_engine_clock_in_sr; - uint32_t min_engine_clock_in_sr; - enum PP_DAL_POWERLEVEL max_clocks_state; -}; - -enum amd_pp_clock_type { - amd_pp_disp_clock = 1, - amd_pp_sys_clock, - amd_pp_mem_clock, - amd_pp_dcef_clock, - amd_pp_soc_clock, - amd_pp_pixel_clock, - amd_pp_phy_clock, - amd_pp_dcf_clock, - amd_pp_dpp_clock, - amd_pp_f_clock = amd_pp_dcef_clock, -}; - -#define MAX_NUM_CLOCKS 16 - -struct amd_pp_clocks { - uint32_t count; - uint32_t clock[MAX_NUM_CLOCKS]; - uint32_t latency[MAX_NUM_CLOCKS]; -}; enum { @@ -223,11 +85,6 @@ struct pp_gpu_power { uint32_t average_gpu_power; }; -struct pp_display_clock_request { - enum amd_pp_clock_type clock_type; - uint32_t clock_freq_in_khz; -}; - #define PP_GROUP_MASK 0xF0000000 #define PP_GROUP_SHIFT 28 -- GitLab From f685d714321daf660d9a9ecf9d4925c297223260 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Wed, 25 Oct 2017 23:55:23 -0400 Subject: [PATCH 0578/2547] drm/amd/powerplay: move functions to amd_pm_funcs table those functions are exported to DC Reviewed-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- .../display/amdgpu_dm/amdgpu_dm_services.c | 29 ++-- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 137 ++++++++++-------- .../gpu/drm/amd/powerplay/inc/amd_powerplay.h | 32 ---- 3 files changed, 90 insertions(+), 108 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index 5df8fd5b537c..82269caedc07 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -131,11 +131,12 @@ bool dm_pp_apply_display_requirements( adev->pm.pm_display_cfg.min_bus_bandwidth = 0; /* TODO: complete implementation of - * amd_powerplay_display_configuration_change(). + * pp_display_configuration_change(). * Follow example of: * PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */ - amd_powerplay_display_configuration_change( + if (adev->powerplay.pp_funcs->display_configuration_change) + adev->powerplay.pp_funcs->display_configuration_change( adev->powerplay.pp_handle, &adev->pm.pm_display_cfg); @@ -264,22 +265,26 @@ bool dm_pp_get_clock_levels_by_type( struct amd_pp_simple_clock_info validation_clks = { 0 }; uint32_t i; - if (amd_powerplay_get_clock_by_type(pp_handle, + if (adev->powerplay.pp_funcs->get_clock_by_type) { + if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle, dc_to_pp_clock_type(clk_type), &pp_clks)) { /* Error in pplib. Provide default values. */ - get_default_clock_levels(clk_type, dc_clks); - return true; + get_default_clock_levels(clk_type, dc_clks); + return true; + } } pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); - if (amd_powerplay_get_display_mode_validation_clocks(pp_handle, - &validation_clks)) { - /* Error in pplib. Provide default values. */ - DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n"); - validation_clks.engine_max_clock = 72000; - validation_clks.memory_max_clock = 80000; - validation_clks.level = 0; + if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) { + if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks( + pp_handle, &validation_clks)) { + /* Error in pplib. Provide default values. */ + DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n"); + validation_clks.engine_max_clock = 72000; + validation_clks.memory_max_clock = 80000; + validation_clks.level = 0; + } } DRM_INFO("DM_PPLIB: Validation clocks:\n"); diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 726425809eed..3d3aa7d17bd9 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -788,6 +788,26 @@ static int pp_dpm_get_pp_table(void *handle, char **table) return size; } +static int amd_powerplay_reset(void *handle) +{ + struct pp_instance *instance = (struct pp_instance *)handle; + int ret; + + ret = pp_check(instance); + if (ret) + return ret; + + ret = pp_hw_fini(instance); + if (ret) + return ret; + + ret = hwmgr_hw_init(instance); + if (ret) + return ret; + + return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL); +} + static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) { struct pp_hwmgr *hwmgr; @@ -1146,64 +1166,9 @@ static int pp_dpm_switch_power_profile(void *handle, return 0; } -const struct amd_pm_funcs pp_dpm_funcs = { - .get_temperature = pp_dpm_get_temperature, - .load_firmware = pp_dpm_load_fw, - .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, - .force_performance_level = pp_dpm_force_performance_level, - .get_performance_level = pp_dpm_get_performance_level, - .get_current_power_state = pp_dpm_get_current_power_state, - .get_sclk = pp_dpm_get_sclk, - .get_mclk = pp_dpm_get_mclk, - .powergate_vce = pp_dpm_powergate_vce, - .powergate_uvd = pp_dpm_powergate_uvd, - .dispatch_tasks = pp_dpm_dispatch_tasks, - .set_fan_control_mode = pp_dpm_set_fan_control_mode, - .get_fan_control_mode = pp_dpm_get_fan_control_mode, - .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, - .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, - .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm, - .get_pp_num_states = pp_dpm_get_pp_num_states, - .get_pp_table = pp_dpm_get_pp_table, - .set_pp_table = pp_dpm_set_pp_table, - .force_clock_level = pp_dpm_force_clock_level, - .print_clock_levels = pp_dpm_print_clock_levels, - .get_sclk_od = pp_dpm_get_sclk_od, - .set_sclk_od = pp_dpm_set_sclk_od, - .get_mclk_od = pp_dpm_get_mclk_od, - .set_mclk_od = pp_dpm_set_mclk_od, - .read_sensor = pp_dpm_read_sensor, - .get_vce_clock_state = pp_dpm_get_vce_clock_state, - .reset_power_profile_state = pp_dpm_reset_power_profile_state, - .get_power_profile_state = pp_dpm_get_power_profile_state, - .set_power_profile_state = pp_dpm_set_power_profile_state, - .switch_power_profile = pp_dpm_switch_power_profile, - .set_clockgating_by_smu = pp_set_clockgating_by_smu, -}; - -int amd_powerplay_reset(void *handle) -{ - struct pp_instance *instance = (struct pp_instance *)handle; - int ret; - - ret = pp_check(instance); - if (ret) - return ret; - - ret = pp_hw_fini(instance); - if (ret) - return ret; - - ret = hwmgr_hw_init(instance); - if (ret) - return ret; - - return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL); -} - /* export this function to DAL */ -int amd_powerplay_display_configuration_change(void *handle, +static int pp_display_configuration_change(void *handle, const struct amd_pp_display_configuration *display_config) { struct pp_hwmgr *hwmgr; @@ -1222,7 +1187,7 @@ int amd_powerplay_display_configuration_change(void *handle, return 0; } -int amd_powerplay_get_display_power_level(void *handle, +static int pp_get_display_power_level(void *handle, struct amd_pp_simple_clock_info *output) { struct pp_hwmgr *hwmgr; @@ -1245,7 +1210,7 @@ int amd_powerplay_get_display_power_level(void *handle, return ret; } -int amd_powerplay_get_current_clocks(void *handle, +static int pp_get_current_clocks(void *handle, struct amd_pp_clock_info *clocks) { struct amd_pp_simple_clock_info simple_clocks; @@ -1299,7 +1264,7 @@ int amd_powerplay_get_current_clocks(void *handle, return 0; } -int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) +static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; @@ -1321,7 +1286,7 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s return ret; } -int amd_powerplay_get_clock_by_type_with_latency(void *handle, +static int pp_get_clock_by_type_with_latency(void *handle, enum amd_pp_clock_type type, struct pp_clock_levels_with_latency *clocks) { @@ -1343,7 +1308,7 @@ int amd_powerplay_get_clock_by_type_with_latency(void *handle, return ret; } -int amd_powerplay_get_clock_by_type_with_voltage(void *handle, +static int pp_get_clock_by_type_with_voltage(void *handle, enum amd_pp_clock_type type, struct pp_clock_levels_with_voltage *clocks) { @@ -1368,7 +1333,7 @@ int amd_powerplay_get_clock_by_type_with_voltage(void *handle, return ret; } -int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle, +static int pp_set_watermarks_for_clocks_ranges(void *handle, struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) { struct pp_hwmgr *hwmgr; @@ -1392,7 +1357,7 @@ int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle, return ret; } -int amd_powerplay_display_clock_voltage_request(void *handle, +static int pp_display_clock_voltage_request(void *handle, struct pp_display_clock_request *clock) { struct pp_hwmgr *hwmgr; @@ -1415,7 +1380,7 @@ int amd_powerplay_display_clock_voltage_request(void *handle, return ret; } -int amd_powerplay_get_display_mode_validation_clocks(void *handle, +static int pp_get_display_mode_validation_clocks(void *handle, struct amd_pp_simple_clock_info *clocks) { struct pp_hwmgr *hwmgr; @@ -1441,3 +1406,47 @@ int amd_powerplay_get_display_mode_validation_clocks(void *handle, return ret; } +const struct amd_pm_funcs pp_dpm_funcs = { + .get_temperature = pp_dpm_get_temperature, + .load_firmware = pp_dpm_load_fw, + .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, + .force_performance_level = pp_dpm_force_performance_level, + .get_performance_level = pp_dpm_get_performance_level, + .get_current_power_state = pp_dpm_get_current_power_state, + .powergate_vce = pp_dpm_powergate_vce, + .powergate_uvd = pp_dpm_powergate_uvd, + .dispatch_tasks = pp_dpm_dispatch_tasks, + .set_fan_control_mode = pp_dpm_set_fan_control_mode, + .get_fan_control_mode = pp_dpm_get_fan_control_mode, + .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, + .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, + .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm, + .get_pp_num_states = pp_dpm_get_pp_num_states, + .get_pp_table = pp_dpm_get_pp_table, + .set_pp_table = pp_dpm_set_pp_table, + .force_clock_level = pp_dpm_force_clock_level, + .print_clock_levels = pp_dpm_print_clock_levels, + .get_sclk_od = pp_dpm_get_sclk_od, + .set_sclk_od = pp_dpm_set_sclk_od, + .get_mclk_od = pp_dpm_get_mclk_od, + .set_mclk_od = pp_dpm_set_mclk_od, + .read_sensor = pp_dpm_read_sensor, + .get_vce_clock_state = pp_dpm_get_vce_clock_state, + .reset_power_profile_state = pp_dpm_reset_power_profile_state, + .get_power_profile_state = pp_dpm_get_power_profile_state, + .set_power_profile_state = pp_dpm_set_power_profile_state, + .switch_power_profile = pp_dpm_switch_power_profile, + .set_clockgating_by_smu = pp_set_clockgating_by_smu, +/* export to DC */ + .get_sclk = pp_dpm_get_sclk, + .get_mclk = pp_dpm_get_mclk, + .display_configuration_change = pp_display_configuration_change, + .get_display_power_level = pp_get_display_power_level, + .get_current_clocks = pp_get_current_clocks, + .get_clock_by_type = pp_get_clock_by_type, + .get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency, + .get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage, + .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges, + .display_clock_voltage_request = pp_display_clock_voltage_request, + .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks, +}; diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index da2e6ee5b7fe..006954e6531a 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -129,37 +129,5 @@ struct amd_powerplay { const struct amd_pm_funcs *pp_funcs; }; -int amd_powerplay_reset(void *handle); - -int amd_powerplay_display_configuration_change(void *handle, - const struct amd_pp_display_configuration *input); - -int amd_powerplay_get_display_power_level(void *handle, - struct amd_pp_simple_clock_info *output); - -int amd_powerplay_get_current_clocks(void *handle, - struct amd_pp_clock_info *output); - -int amd_powerplay_get_clock_by_type(void *handle, - enum amd_pp_clock_type type, - struct amd_pp_clocks *clocks); - -int amd_powerplay_get_clock_by_type_with_latency(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_latency *clocks); - -int amd_powerplay_get_clock_by_type_with_voltage(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_voltage *clocks); - -int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle, - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); - -int amd_powerplay_display_clock_voltage_request(void *handle, - struct pp_display_clock_request *clock); - -int amd_powerplay_get_display_mode_validation_clocks(void *handle, - struct amd_pp_simple_clock_info *output); - #endif /* _AMD_POWERPLAY_H_ */ -- GitLab From 11dc9364bddd1676f754ebf1397cf8c0057dfa7a Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Fri, 29 Sep 2017 16:07:14 +0800 Subject: [PATCH 0579/2547] drm/amdgpu: move struct amd_powerplay to amdgpu.h Clean up the interface. Acked-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +++++++ drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 7 ------- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 34268aac6b9a..cfc0f78c2445 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1423,6 +1423,13 @@ typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); +struct amd_powerplay { + struct cgs_device *cgs_device; + void *pp_handle; + const struct amd_ip_funcs *ip_funcs; + const struct amd_pm_funcs *pp_funcs; +}; + #define AMDGPU_RESET_MAGIC_NUM 64 struct amdgpu_device { struct device *dev; diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index 006954e6531a..47478e09f0b9 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -122,12 +122,5 @@ struct pp_gpu_power { support << PP_STATE_SUPPORT_SHIFT |\ state << PP_STATE_SHIFT) -struct amd_powerplay { - struct cgs_device *cgs_device; - void *pp_handle; - const struct amd_ip_funcs *ip_funcs; - const struct amd_pm_funcs *pp_funcs; -}; - #endif /* _AMD_POWERPLAY_H_ */ -- GitLab From c79563a31620edbea4349498962b1d3b0dbdb201 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Fri, 29 Sep 2017 15:58:19 +0800 Subject: [PATCH 0580/2547] drm/amdgpu: add header kgd_pp_interface.h move powerplay and amdgpu shared structures and definitions to kgd_pp_interface.h. This is the interface between the base driver and powerplay. Acked-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 1 - drivers/gpu/drm/amd/include/amd_shared.h | 172 ----------- .../gpu/drm/amd/include/kgd_pp_interface.h | 289 ++++++++++++++++++ .../gpu/drm/amd/powerplay/inc/amd_powerplay.h | 93 +----- 5 files changed, 293 insertions(+), 267 deletions(-) create mode 100644 drivers/gpu/drm/amd/include/kgd_pp_interface.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index cfc0f78c2445..88fa19b1a802 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -47,6 +47,8 @@ #include #include +#include "dm_pp_interface.h" +#include "kgd_pp_interface.h" #include "amd_shared.h" #include "amdgpu_mode.h" @@ -59,7 +61,6 @@ #include "amdgpu_sync.h" #include "amdgpu_ring.h" #include "amdgpu_vm.h" -#include "amd_powerplay.h" #include "amdgpu_dpm.h" #include "amdgpu_acp.h" #include "amdgpu_uvd.h" @@ -67,11 +68,11 @@ #include "amdgpu_vcn.h" #include "amdgpu_mn.h" #include "amdgpu_dm.h" - #include "gpu_scheduler.h" #include "amdgpu_virt.h" #include "amdgpu_gart.h" + /* * Modules parameters. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 6c570d4e4516..6f56ff606e43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -30,7 +30,6 @@ #include #include -#include "amd_powerplay.h" static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index b72f8a43d86b..9fa3aaef3f33 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -25,7 +25,6 @@ #include -struct seq_file; #define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ @@ -61,71 +60,12 @@ enum amd_clockgating_state { AMD_CG_STATE_UNGATE, }; -enum amd_dpm_forced_level { - AMD_DPM_FORCED_LEVEL_AUTO = 0x1, - AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, - AMD_DPM_FORCED_LEVEL_LOW = 0x4, - AMD_DPM_FORCED_LEVEL_HIGH = 0x8, - AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, - AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, - AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, -}; enum amd_powergating_state { AMD_PG_STATE_GATE = 0, AMD_PG_STATE_UNGATE, }; -struct amd_vce_state { - /* vce clocks */ - u32 evclk; - u32 ecclk; - /* gpu clocks */ - u32 sclk; - u32 mclk; - u8 clk_idx; - u8 pstate; -}; - - -#define AMD_MAX_VCE_LEVELS 6 - -enum amd_vce_level { - AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ - AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ - AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ - AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ - AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ - AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ -}; - -enum amd_pp_profile_type { - AMD_PP_GFX_PROFILE, - AMD_PP_COMPUTE_PROFILE, -}; - -struct amd_pp_profile { - enum amd_pp_profile_type type; - uint32_t min_sclk; - uint32_t min_mclk; - uint16_t activity_threshold; - uint8_t up_hyst; - uint8_t down_hyst; -}; - -enum amd_fan_ctrl_mode { - AMD_FAN_CTRL_NONE = 0, - AMD_FAN_CTRL_MANUAL = 1, - AMD_FAN_CTRL_AUTO = 2, -}; - -enum pp_clock_type { - PP_SCLK, - PP_MCLK, - PP_PCIE, -}; /* CG flags */ #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) @@ -169,27 +109,6 @@ enum pp_clock_type { #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) #define AMD_PG_SUPPORT_MMHUB (1 << 13) -enum amd_pm_state_type { - /* not used for dpm */ - POWER_STATE_TYPE_DEFAULT, - POWER_STATE_TYPE_POWERSAVE, - /* user selectable states */ - POWER_STATE_TYPE_BATTERY, - POWER_STATE_TYPE_BALANCED, - POWER_STATE_TYPE_PERFORMANCE, - /* internal states */ - POWER_STATE_TYPE_INTERNAL_UVD, - POWER_STATE_TYPE_INTERNAL_UVD_SD, - POWER_STATE_TYPE_INTERNAL_UVD_HD, - POWER_STATE_TYPE_INTERNAL_UVD_HD2, - POWER_STATE_TYPE_INTERNAL_UVD_MVC, - POWER_STATE_TYPE_INTERNAL_BOOT, - POWER_STATE_TYPE_INTERNAL_THERMAL, - POWER_STATE_TYPE_INTERNAL_ACPI, - POWER_STATE_TYPE_INTERNAL_ULV, - POWER_STATE_TYPE_INTERNAL_3DPERF, -}; - struct amd_ip_funcs { /* Name of IP block */ char *name; @@ -233,95 +152,4 @@ struct amd_ip_funcs { }; -enum amd_pp_task; -enum amd_pp_clock_type; -struct pp_states_info; -struct amd_pp_simple_clock_info; -struct amd_pp_display_configuration; -struct amd_pp_clock_info; -struct pp_display_clock_request; -struct pp_wm_sets_with_clock_ranges_soc15; -struct pp_clock_levels_with_voltage; -struct pp_clock_levels_with_latency; -struct amd_pp_clocks; - -struct amd_pm_funcs { -/* export for dpm on ci and si */ - int (*pre_set_power_state)(void *handle); - int (*set_power_state)(void *handle); - void (*post_set_power_state)(void *handle); - void (*display_configuration_changed)(void *handle); - void (*print_power_state)(void *handle, void *ps); - bool (*vblank_too_short)(void *handle); - void (*enable_bapm)(void *handle, bool enable); - int (*check_state_equal)(void *handle, - void *cps, - void *rps, - bool *equal); -/* export for sysfs */ - int (*get_temperature)(void *handle); - void (*set_fan_control_mode)(void *handle, u32 mode); - u32 (*get_fan_control_mode)(void *handle); - int (*set_fan_speed_percent)(void *handle, u32 speed); - int (*get_fan_speed_percent)(void *handle, u32 *speed); - int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); - int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); - int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); - int (*get_sclk_od)(void *handle); - int (*set_sclk_od)(void *handle, uint32_t value); - int (*get_mclk_od)(void *handle); - int (*set_mclk_od)(void *handle, uint32_t value); - int (*read_sensor)(void *handle, int idx, void *value, int *size); - enum amd_dpm_forced_level (*get_performance_level)(void *handle); - enum amd_pm_state_type (*get_current_power_state)(void *handle); - int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); - int (*get_pp_num_states)(void *handle, struct pp_states_info *data); - int (*get_pp_table)(void *handle, char **table); - int (*set_pp_table)(void *handle, const char *buf, size_t size); - void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); - - int (*reset_power_profile_state)(void *handle, - struct amd_pp_profile *request); - int (*get_power_profile_state)(void *handle, - struct amd_pp_profile *query); - int (*set_power_profile_state)(void *handle, - struct amd_pp_profile *request); - int (*switch_power_profile)(void *handle, - enum amd_pp_profile_type type); -/* export to amdgpu */ - void (*powergate_uvd)(void *handle, bool gate); - void (*powergate_vce)(void *handle, bool gate); - struct amd_vce_state* (*get_vce_clock_state)(void *handle, u32 idx); - int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, - void *input, void *output); - int (*load_firmware)(void *handle); - int (*wait_for_fw_loading_complete)(void *handle); - int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); -/* export to DC */ - u32 (*get_sclk)(void *handle, bool low); - u32 (*get_mclk)(void *handle, bool low); - int (*display_configuration_change)(void *handle, - const struct amd_pp_display_configuration *input); - int (*get_display_power_level)(void *handle, - struct amd_pp_simple_clock_info *output); - int (*get_current_clocks)(void *handle, - struct amd_pp_clock_info *clocks); - int (*get_clock_by_type)(void *handle, - enum amd_pp_clock_type type, - struct amd_pp_clocks *clocks); - int (*get_clock_by_type_with_latency)(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_latency *clocks); - int (*get_clock_by_type_with_voltage)(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_voltage *clocks); - int (*set_watermarks_for_clocks_ranges)(void *handle, - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); - int (*display_clock_voltage_request)(void *handle, - struct pp_display_clock_request *clock); - int (*get_display_mode_validation_clocks)(void *handle, - struct amd_pp_simple_clock_info *clocks); -}; - - #endif /* __AMD_SHARED_H__ */ diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h new file mode 100644 index 000000000000..f104668d8a7f --- /dev/null +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -0,0 +1,289 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __KGD_PP_INTERFACE_H__ +#define __KGD_PP_INTERFACE_H__ + +extern const struct amd_ip_funcs pp_ip_funcs; +extern const struct amd_pm_funcs pp_dpm_funcs; + +struct amd_vce_state { + /* vce clocks */ + u32 evclk; + u32 ecclk; + /* gpu clocks */ + u32 sclk; + u32 mclk; + u8 clk_idx; + u8 pstate; +}; + + +enum amd_dpm_forced_level { + AMD_DPM_FORCED_LEVEL_AUTO = 0x1, + AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, + AMD_DPM_FORCED_LEVEL_LOW = 0x4, + AMD_DPM_FORCED_LEVEL_HIGH = 0x8, + AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, + AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, + AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, +}; + +enum amd_pm_state_type { + /* not used for dpm */ + POWER_STATE_TYPE_DEFAULT, + POWER_STATE_TYPE_POWERSAVE, + /* user selectable states */ + POWER_STATE_TYPE_BATTERY, + POWER_STATE_TYPE_BALANCED, + POWER_STATE_TYPE_PERFORMANCE, + /* internal states */ + POWER_STATE_TYPE_INTERNAL_UVD, + POWER_STATE_TYPE_INTERNAL_UVD_SD, + POWER_STATE_TYPE_INTERNAL_UVD_HD, + POWER_STATE_TYPE_INTERNAL_UVD_HD2, + POWER_STATE_TYPE_INTERNAL_UVD_MVC, + POWER_STATE_TYPE_INTERNAL_BOOT, + POWER_STATE_TYPE_INTERNAL_THERMAL, + POWER_STATE_TYPE_INTERNAL_ACPI, + POWER_STATE_TYPE_INTERNAL_ULV, + POWER_STATE_TYPE_INTERNAL_3DPERF, +}; + +#define AMD_MAX_VCE_LEVELS 6 + +enum amd_vce_level { + AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ + AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ + AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ + AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ + AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ + AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ +}; + +enum amd_pp_profile_type { + AMD_PP_GFX_PROFILE, + AMD_PP_COMPUTE_PROFILE, +}; + +struct amd_pp_profile { + enum amd_pp_profile_type type; + uint32_t min_sclk; + uint32_t min_mclk; + uint16_t activity_threshold; + uint8_t up_hyst; + uint8_t down_hyst; +}; + +enum amd_fan_ctrl_mode { + AMD_FAN_CTRL_NONE = 0, + AMD_FAN_CTRL_MANUAL = 1, + AMD_FAN_CTRL_AUTO = 2, +}; + +enum pp_clock_type { + PP_SCLK, + PP_MCLK, + PP_PCIE, +}; + +enum amd_pp_sensors { + AMDGPU_PP_SENSOR_GFX_SCLK = 0, + AMDGPU_PP_SENSOR_VDDNB, + AMDGPU_PP_SENSOR_VDDGFX, + AMDGPU_PP_SENSOR_UVD_VCLK, + AMDGPU_PP_SENSOR_UVD_DCLK, + AMDGPU_PP_SENSOR_VCE_ECCLK, + AMDGPU_PP_SENSOR_GPU_LOAD, + AMDGPU_PP_SENSOR_GFX_MCLK, + AMDGPU_PP_SENSOR_GPU_TEMP, + AMDGPU_PP_SENSOR_VCE_POWER, + AMDGPU_PP_SENSOR_UVD_POWER, + AMDGPU_PP_SENSOR_GPU_POWER, +}; + +enum amd_pp_task { + AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, + AMD_PP_TASK_ENABLE_USER_STATE, + AMD_PP_TASK_READJUST_POWER_STATE, + AMD_PP_TASK_COMPLETE_INIT, + AMD_PP_TASK_MAX +}; + +struct amd_pp_init { + struct cgs_device *device; + uint32_t chip_family; + uint32_t chip_id; + bool pm_en; + uint32_t feature_mask; +}; + + + +enum { + PP_GROUP_UNKNOWN = 0, + PP_GROUP_GFX = 1, + PP_GROUP_SYS, + PP_GROUP_MAX +}; + +struct pp_states_info { + uint32_t nums; + uint32_t states[16]; +}; + +struct pp_gpu_power { + uint32_t vddc_power; + uint32_t vddci_power; + uint32_t max_gpu_power; + uint32_t average_gpu_power; +}; + +#define PP_GROUP_MASK 0xF0000000 +#define PP_GROUP_SHIFT 28 + +#define PP_BLOCK_MASK 0x0FFFFF00 +#define PP_BLOCK_SHIFT 8 + +#define PP_BLOCK_GFX_CG 0x01 +#define PP_BLOCK_GFX_MG 0x02 +#define PP_BLOCK_GFX_3D 0x04 +#define PP_BLOCK_GFX_RLC 0x08 +#define PP_BLOCK_GFX_CP 0x10 +#define PP_BLOCK_SYS_BIF 0x01 +#define PP_BLOCK_SYS_MC 0x02 +#define PP_BLOCK_SYS_ROM 0x04 +#define PP_BLOCK_SYS_DRM 0x08 +#define PP_BLOCK_SYS_HDP 0x10 +#define PP_BLOCK_SYS_SDMA 0x20 + +#define PP_STATE_MASK 0x0000000F +#define PP_STATE_SHIFT 0 +#define PP_STATE_SUPPORT_MASK 0x000000F0 +#define PP_STATE_SUPPORT_SHIFT 0 + +#define PP_STATE_CG 0x01 +#define PP_STATE_LS 0x02 +#define PP_STATE_DS 0x04 +#define PP_STATE_SD 0x08 +#define PP_STATE_SUPPORT_CG 0x10 +#define PP_STATE_SUPPORT_LS 0x20 +#define PP_STATE_SUPPORT_DS 0x40 +#define PP_STATE_SUPPORT_SD 0x80 + +#define PP_CG_MSG_ID(group, block, support, state) \ + ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ + (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) + +struct seq_file; +enum amd_pp_clock_type; +struct amd_pp_simple_clock_info; +struct amd_pp_display_configuration; +struct amd_pp_clock_info; +struct pp_display_clock_request; +struct pp_wm_sets_with_clock_ranges_soc15; +struct pp_clock_levels_with_voltage; +struct pp_clock_levels_with_latency; +struct amd_pp_clocks; + +struct amd_pm_funcs { +/* export for dpm on ci and si */ + int (*pre_set_power_state)(void *handle); + int (*set_power_state)(void *handle); + void (*post_set_power_state)(void *handle); + void (*display_configuration_changed)(void *handle); + void (*print_power_state)(void *handle, void *ps); + bool (*vblank_too_short)(void *handle); + void (*enable_bapm)(void *handle, bool enable); + int (*check_state_equal)(void *handle, + void *cps, + void *rps, + bool *equal); +/* export for sysfs */ + int (*get_temperature)(void *handle); + void (*set_fan_control_mode)(void *handle, u32 mode); + u32 (*get_fan_control_mode)(void *handle); + int (*set_fan_speed_percent)(void *handle, u32 speed); + int (*get_fan_speed_percent)(void *handle, u32 *speed); + int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); + int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); + int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); + int (*get_sclk_od)(void *handle); + int (*set_sclk_od)(void *handle, uint32_t value); + int (*get_mclk_od)(void *handle); + int (*set_mclk_od)(void *handle, uint32_t value); + int (*read_sensor)(void *handle, int idx, void *value, int *size); + enum amd_dpm_forced_level (*get_performance_level)(void *handle); + enum amd_pm_state_type (*get_current_power_state)(void *handle); + int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); + int (*get_pp_num_states)(void *handle, struct pp_states_info *data); + int (*get_pp_table)(void *handle, char **table); + int (*set_pp_table)(void *handle, const char *buf, size_t size); + void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); + + int (*reset_power_profile_state)(void *handle, + struct amd_pp_profile *request); + int (*get_power_profile_state)(void *handle, + struct amd_pp_profile *query); + int (*set_power_profile_state)(void *handle, + struct amd_pp_profile *request); + int (*switch_power_profile)(void *handle, + enum amd_pp_profile_type type); +/* export to amdgpu */ + void (*powergate_uvd)(void *handle, bool gate); + void (*powergate_vce)(void *handle, bool gate); + struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); + int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, + void *input, void *output); + int (*load_firmware)(void *handle); + int (*wait_for_fw_loading_complete)(void *handle); + int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); +/* export to DC */ + u32 (*get_sclk)(void *handle, bool low); + u32 (*get_mclk)(void *handle, bool low); + int (*display_configuration_change)(void *handle, + const struct amd_pp_display_configuration *input); + int (*get_display_power_level)(void *handle, + struct amd_pp_simple_clock_info *output); + int (*get_current_clocks)(void *handle, + struct amd_pp_clock_info *clocks); + int (*get_clock_by_type)(void *handle, + enum amd_pp_clock_type type, + struct amd_pp_clocks *clocks); + int (*get_clock_by_type_with_latency)(void *handle, + enum amd_pp_clock_type type, + struct pp_clock_levels_with_latency *clocks); + int (*get_clock_by_type_with_voltage)(void *handle, + enum amd_pp_clock_type type, + struct pp_clock_levels_with_voltage *clocks); + int (*set_watermarks_for_clocks_ranges)(void *handle, + struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); + int (*display_clock_voltage_request)(void *handle, + struct pp_display_clock_request *clock); + int (*get_display_mode_validation_clocks)(void *handle, + struct amd_pp_simple_clock_info *clocks); +}; + +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index 47478e09f0b9..152e70db4a81 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -29,98 +29,7 @@ #include "amd_shared.h" #include "cgs_common.h" #include "dm_pp_interface.h" - -extern const struct amd_ip_funcs pp_ip_funcs; -extern const struct amd_pm_funcs pp_dpm_funcs; - -enum amd_pp_sensors { - AMDGPU_PP_SENSOR_GFX_SCLK = 0, - AMDGPU_PP_SENSOR_VDDNB, - AMDGPU_PP_SENSOR_VDDGFX, - AMDGPU_PP_SENSOR_UVD_VCLK, - AMDGPU_PP_SENSOR_UVD_DCLK, - AMDGPU_PP_SENSOR_VCE_ECCLK, - AMDGPU_PP_SENSOR_GPU_LOAD, - AMDGPU_PP_SENSOR_GFX_MCLK, - AMDGPU_PP_SENSOR_GPU_TEMP, - AMDGPU_PP_SENSOR_VCE_POWER, - AMDGPU_PP_SENSOR_UVD_POWER, - AMDGPU_PP_SENSOR_GPU_POWER, -}; - -enum amd_pp_task { - AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, - AMD_PP_TASK_ENABLE_USER_STATE, - AMD_PP_TASK_READJUST_POWER_STATE, - AMD_PP_TASK_COMPLETE_INIT, - AMD_PP_TASK_MAX -}; - -struct amd_pp_init { - struct cgs_device *device; - uint32_t chip_family; - uint32_t chip_id; - bool pm_en; - uint32_t feature_mask; -}; - - - -enum { - PP_GROUP_UNKNOWN = 0, - PP_GROUP_GFX = 1, - PP_GROUP_SYS, - PP_GROUP_MAX -}; - -struct pp_states_info { - uint32_t nums; - uint32_t states[16]; -}; - -struct pp_gpu_power { - uint32_t vddc_power; - uint32_t vddci_power; - uint32_t max_gpu_power; - uint32_t average_gpu_power; -}; - -#define PP_GROUP_MASK 0xF0000000 -#define PP_GROUP_SHIFT 28 - -#define PP_BLOCK_MASK 0x0FFFFF00 -#define PP_BLOCK_SHIFT 8 - -#define PP_BLOCK_GFX_CG 0x01 -#define PP_BLOCK_GFX_MG 0x02 -#define PP_BLOCK_GFX_3D 0x04 -#define PP_BLOCK_GFX_RLC 0x08 -#define PP_BLOCK_GFX_CP 0x10 -#define PP_BLOCK_SYS_BIF 0x01 -#define PP_BLOCK_SYS_MC 0x02 -#define PP_BLOCK_SYS_ROM 0x04 -#define PP_BLOCK_SYS_DRM 0x08 -#define PP_BLOCK_SYS_HDP 0x10 -#define PP_BLOCK_SYS_SDMA 0x20 - -#define PP_STATE_MASK 0x0000000F -#define PP_STATE_SHIFT 0 -#define PP_STATE_SUPPORT_MASK 0x000000F0 -#define PP_STATE_SUPPORT_SHIFT 0 - -#define PP_STATE_CG 0x01 -#define PP_STATE_LS 0x02 -#define PP_STATE_DS 0x04 -#define PP_STATE_SD 0x08 -#define PP_STATE_SUPPORT_CG 0x10 -#define PP_STATE_SUPPORT_LS 0x20 -#define PP_STATE_SUPPORT_DS 0x40 -#define PP_STATE_SUPPORT_SD 0x80 - -#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\ - block << PP_BLOCK_SHIFT |\ - support << PP_STATE_SUPPORT_SHIFT |\ - state << PP_STATE_SHIFT) +#include "kgd_pp_interface.h" #endif /* _AMD_POWERPLAY_H_ */ -- GitLab From d668942bb8527a7872fdcd94a9ed2d5e4c9b72a6 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Fri, 15 Sep 2017 18:34:42 +0800 Subject: [PATCH 0581/2547] drm/amdgpu: add new pp function point notify_smu_memory_info Used to set up smu power logging. Reviewed-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 6 ++++++ drivers/gpu/drm/amd/include/kgd_pp_interface.h | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h index 56caaeee6fea..a8437a3296a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h @@ -360,6 +360,12 @@ enum amdgpu_pcie_gen { ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\ (adev)->powerplay.pp_handle, msg_id)) +#define amdgpu_dpm_notify_smu_memory_info(adev, virtual_addr_low, \ + virtual_addr_hi, mc_addr_low, mc_addr_hi, size) \ + ((adev)->powerplay.pp_funcs->notify_smu_memory_info)( \ + (adev)->powerplay.pp_handle, virtual_addr_low, \ + virtual_addr_hi, mc_addr_low, mc_addr_hi, size) + struct amdgpu_dpm { struct amdgpu_ps *ps; /* number of valid power states */ diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index f104668d8a7f..eab504ecca25 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -260,6 +260,11 @@ struct amd_pm_funcs { int (*load_firmware)(void *handle); int (*wait_for_fw_loading_complete)(void *handle); int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); + int (*notify_smu_memory_info)(void *handle, uint32_t virtual_addr_low, + uint32_t virtual_addr_hi, + uint32_t mc_addr_low, + uint32_t mc_addr_hi, + uint32_t size); /* export to DC */ u32 (*get_sclk)(void *handle, bool low); u32 (*get_mclk)(void *handle, bool low); -- GitLab From 4c7c8bbb1fb505fde6a2dfd872aa622a2c8a28dd Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Mon, 9 Oct 2017 12:22:21 +0800 Subject: [PATCH 0582/2547] drm/amd/pp: implement notify_smu_memory_info on Powerplay Used to set up smu power logging. Reviewed-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 3d3aa7d17bd9..a698a278ef8d 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -1166,6 +1166,41 @@ static int pp_dpm_switch_power_profile(void *handle, return 0; } +static int pp_dpm_notify_smu_memory_info(void *handle, + uint32_t virtual_addr_low, + uint32_t virtual_addr_hi, + uint32_t mc_addr_low, + uint32_t mc_addr_hi, + uint32_t size) +{ + struct pp_hwmgr *hwmgr; + struct pp_instance *pp_handle = (struct pp_instance *)handle; + int ret = 0; + + ret = pp_check(pp_handle); + + if (ret) + return ret; + + hwmgr = pp_handle->hwmgr; + + if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) { + pr_info("%s was not implemented.\n", __func__); + return -EINVAL; + } + + mutex_lock(&pp_handle->pp_lock); + + ret = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, virtual_addr_low, + virtual_addr_hi, mc_addr_low, mc_addr_hi, + size); + + mutex_unlock(&pp_handle->pp_lock); + + return ret; +} + + /* export this function to DAL */ static int pp_display_configuration_change(void *handle, @@ -1437,6 +1472,7 @@ const struct amd_pm_funcs pp_dpm_funcs = { .set_power_profile_state = pp_dpm_set_power_profile_state, .switch_power_profile = pp_dpm_switch_power_profile, .set_clockgating_by_smu = pp_set_clockgating_by_smu, + .notify_smu_memory_info = pp_dpm_notify_smu_memory_info, /* export to DC */ .get_sclk = pp_dpm_get_sclk, .get_mclk = pp_dpm_get_mclk, -- GitLab From 95a3ff787a49c57e9ebe2abf7ad8362007b7dff6 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Mon, 9 Oct 2017 11:30:42 +0800 Subject: [PATCH 0583/2547] drm/amd/pp: delete an outdated comment in amd_powerplay.c Reviewed-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index a698a278ef8d..9d3bdada79d5 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -1200,9 +1200,6 @@ static int pp_dpm_notify_smu_memory_info(void *handle, return ret; } - -/* export this function to DAL */ - static int pp_display_configuration_change(void *handle, const struct amd_pp_display_configuration *display_config) { -- GitLab From 433f1aa786378e4822f17f7782d8dba321a2740b Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Fri, 20 Oct 2017 14:52:43 +0800 Subject: [PATCH 0584/2547] drm/amdgpu: delete duplicated code. the variable ref_clock was assigned same value twice in same function. Reviewed-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index f2b72c7c6857..85d2149b9dbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -948,7 +948,6 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, (amdgpu_crtc->v_border * 2); mode_info->vblank_time_us = vblank_lines * line_time_us; mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); - mode_info->ref_clock = adev->clock.spll.reference_freq; mode_info = NULL; } } @@ -958,7 +957,6 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, if (mode_info != NULL) { mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time; mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh; - mode_info->ref_clock = adev->clock.spll.reference_freq; } } return 0; -- GitLab From 553aae12e3ad4d4d9cb9accb129a8c818bce506b Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Mon, 16 Oct 2017 10:43:59 -0400 Subject: [PATCH 0585/2547] drm/amd/display: Add APU cap in dc_caps Some features should only be enabled on APUs or should not be enabled on APUs. Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 1 + drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 ++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + 5 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 7240db2e6f09..e8894ad3adf4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -558,6 +558,7 @@ static bool construct(struct dc *dc, dc_version = resource_parse_asic_id(init_params->asic_id); dc->ctx->dce_version = dc_version; + #if defined(CONFIG_DRM_AMD_DC_FBC) dc->ctx->fbc_gpu_addr = init_params->fbc_gpu_addr; #endif diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9d8f4a55c74e..9ca838b3c4d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -60,6 +60,7 @@ struct dc_caps { unsigned int max_video_width; bool dcc_const_color; bool dynamic_audio; + bool is_apu; }; struct dc_dcc_surface_param { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 61adb8174ce0..5228ee78f7e6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1156,6 +1156,7 @@ static bool construct( dc->caps.max_downscale_ratio = 150; dc->caps.i2c_speed_in_khz = 100; dc->caps.max_cursor_size = 128; + dc->caps.is_apu = true; /************************************************* * Create resources * diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 9c18efd3446f..8f2bd56f3461 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -957,6 +957,7 @@ static bool dce81_construct( dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; dc->caps.max_cursor_size = 128; + dc->caps.is_apu = true; /************************************************* * Create resources * @@ -1121,6 +1122,7 @@ static bool dce83_construct( dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; dc->caps.max_cursor_size = 128; + dc->caps.is_apu = true; /************************************************* * Create resources * diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 9fc8f827f2a1..f59b2ab6c134 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1235,6 +1235,7 @@ static bool construct( dc->caps.max_cursor_size = 256; dc->caps.max_slave_planes = 1; + dc->caps.is_apu = true; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; -- GitLab From 3dc780ec3473200ef870eae9b19169445d76be4c Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 17 Oct 2017 14:48:11 -0400 Subject: [PATCH 0586/2547] drm/amd/display: Move lock to front end program. Moved lock and unlock to apply_ctx_to_surface, since all the front end programming is within apply_ctx_to_surface. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 52 +------------------ .../display/dc/dce110/dce110_hw_sequencer.c | 16 ++++++ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 13 ++++- 3 files changed, 29 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e8894ad3adf4..9925d0e01c04 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -839,7 +839,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; - int i, j, k, l; + int i, k, l; struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; disable_dangling_plane(dc, context); @@ -893,15 +893,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c dc_enable_stereo(dc, context, dc_streams, context->stream_count); - for (i = 0; i < context->stream_count; i++) { - for (j = 0; j < MAX_PIPES; j++) { - pipe = &context->res_ctx.pipe_ctx[j]; - - if (!pipe->top_pipe && pipe->stream == context->streams[i]) - dc->hwss.pipe_control_lock(dc, pipe, false); - } - } - dc_release_state(dc->current_state); dc->current_state = context; @@ -1313,27 +1304,6 @@ static void commit_planes_for_stream(struct dc *dc, return; } - /* Lock pipes for provided surfaces, or all active if full update*/ - for (i = 0; i < surface_count; i++) { - struct dc_plane_state *plane_state = srf_updates[i].surface; - - for (j = 0; j < dc->res_pool->pipe_count; j++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - - if (update_type != UPDATE_TYPE_FULL && pipe_ctx->plane_state != plane_state) - continue; - if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) - continue; - - dc->hwss.pipe_control_lock( - dc, - pipe_ctx, - true); - } - if (update_type == UPDATE_TYPE_FULL) - break; - } - /* Full fe update*/ for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -1390,26 +1360,6 @@ static void commit_planes_for_stream(struct dc *dc, } } } - - /* Unlock pipes */ - for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - - for (j = 0; j < surface_count; j++) { - if (update_type != UPDATE_TYPE_FULL && - srf_updates[j].surface != pipe_ctx->plane_state) - continue; - if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) - continue; - - dc->hwss.pipe_control_lock( - dc, - pipe_ctx, - false); - - break; - } - } } void dc_commit_updates_for_stream(struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 07ff8d2faf3f..61e11a1161bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2873,8 +2873,14 @@ static void dce110_apply_ctx_for_surface( be_idx = -1; for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (stream == context->res_ctx.pipe_ctx[i].stream) { be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst; + if (!pipe_ctx->top_pipe && + (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) + dc->hwss.pipe_control_lock(dc, pipe_ctx, true); break; } } @@ -2898,6 +2904,16 @@ static void dce110_apply_ctx_for_surface( program_surface_visibility(dc, pipe_ctx); } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + if ((stream == pipe_ctx->stream) && + (!pipe_ctx->top_pipe) && + (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) + dc->hwss.pipe_control_lock(dc, pipe_ctx, false); + } } static void dce110_power_down_fe(struct dc *dc, int fe_idx) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 961ad5c3b454..ac731c46419d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2550,6 +2550,11 @@ static void dcn10_apply_ctx_for_surface( if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) continue; + if (pipe_ctx->stream_res.tg && + pipe_ctx->stream_res.tg->inst == be_idx && + !pipe_ctx->top_pipe) + pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); + /* * Powergate reused pipes that are not powergated * fairly hacky right now, using opp_id as indicator @@ -2605,13 +2610,19 @@ static void dcn10_apply_ctx_for_surface( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream != stream) continue; /* looking for top pipe to program */ - if (!pipe_ctx->top_pipe) + if (!pipe_ctx->top_pipe) { program_all_pipe_in_tree(dc, pipe_ctx, context); + if (pipe_ctx->stream_res.tg && + pipe_ctx->stream_res.tg->inst == be_idx && + (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) + pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); + } } dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, -- GitLab From 4c7d45fae841a7f3e2d129185acf66f1c7ae37e5 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 17 Oct 2017 14:54:58 -0400 Subject: [PATCH 0587/2547] drm/amd/display: Check cursor address before program. Program cursor attributes during set mode is only needed in case of pipe slipt, bottom pipe should be programmed same as top pipe. Need to program if address is 0. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index ac731c46419d..b477a6508db4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2436,7 +2436,8 @@ static void program_all_pipe_in_tree( /* TODO: this is a hack w/a for switching from mpo to pipe split */ dc_stream_set_cursor_position(pipe_ctx->stream, &position); - dc_stream_set_cursor_attributes(pipe_ctx->stream, + if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) + dc_stream_set_cursor_attributes(pipe_ctx->stream, &pipe_ctx->stream->cursor_attributes); if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { -- GitLab From d182fddbc731a60810fc3b59694c6054a3b180a6 Mon Sep 17 00:00:00 2001 From: Mikita Lipski Date: Tue, 17 Oct 2017 10:53:43 -0400 Subject: [PATCH 0588/2547] drm/amd/display: Adding DCN1 registers Registers added to definition list that are required for multi display synchronization Signed-off-by: Mikita Lipski Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../display/dc/dcn10/dcn10_timing_generator.h | 33 +++++++++++++++++-- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h index 7d4818d7aa31..395820606013 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h @@ -72,7 +72,10 @@ SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ SRI(OPPBUF_CONTROL, OPPBUF, inst),\ SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, inst),\ - SRI(CONTROL, VTG, inst) + SRI(CONTROL, VTG, inst),\ + SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ + SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\ + SRI(OTG_GSL_CONTROL, OTG, inst) #define TG_COMMON_REG_LIST_DCN1_0(inst) \ TG_COMMON_REG_LIST_DCN(inst),\ @@ -82,6 +85,9 @@ struct dcn_tg_registers { + uint32_t OTG_VERT_SYNC_CONTROL; + uint32_t OTG_MASTER_UPDATE_MODE; + uint32_t OTG_GSL_CONTROL; uint32_t OTG_VSTARTUP_PARAM; uint32_t OTG_VUPDATE_PARAM; uint32_t OTG_VREADY_PARAM; @@ -208,7 +214,18 @@ struct dcn_tg_registers { SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\ SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ - SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh) + SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ + SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh) + #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ @@ -317,7 +334,17 @@ struct dcn_tg_registers { type OPPBUF_3D_VACT_SPACE1_SIZE;\ type VTG0_ENABLE;\ type VTG0_FP2;\ - type VTG0_VCOUNT_INIT; + type VTG0_VCOUNT_INIT;\ + type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\ + type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\ + type OTG_AUTO_FORCE_VSYNC_MODE;\ + type MASTER_UPDATE_INTERLACED_MODE;\ + type OTG_GSL0_EN;\ + type OTG_GSL1_EN;\ + type OTG_GSL2_EN;\ + type OTG_GSL_MASTER_EN;\ + type OTG_GSL_FORCE_DELAY;\ + type OTG_GSL_CHECK_ALL_FIELDS; struct dcn_tg_shift { TG_REG_FIELD_LIST(uint8_t) -- GitLab From 8474a22b544e80c5aca2600c3d23ad1ca25f57c3 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 28 Sep 2017 15:39:41 -0400 Subject: [PATCH 0589/2547] drm/amd/display: Cleanup some fail labels in dcn10_resource Signed-off-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 37 +++++++------------ 1 file changed, 13 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index f59b2ab6c134..6ca01937a0a4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1275,7 +1275,7 @@ static bool construct( if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); - goto clock_source_create_fail; + goto fail; } } @@ -1284,7 +1284,7 @@ static bool construct( if (pool->base.display_clock == NULL) { dm_error("DC: failed to create display clock!\n"); BREAK_TO_DEBUGGER(); - goto disp_clk_create_fail; + goto fail; } } @@ -1295,7 +1295,7 @@ static bool construct( if (pool->base.dmcu == NULL) { dm_error("DC: failed to create dmcu!\n"); BREAK_TO_DEBUGGER(); - goto res_create_fail; + goto fail; } pool->base.abm = dce_abm_create(ctx, @@ -1305,7 +1305,7 @@ static bool construct( if (pool->base.abm == NULL) { dm_error("DC: failed to create abm!\n"); BREAK_TO_DEBUGGER(); - goto res_create_fail; + goto fail; } dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1); @@ -1345,13 +1345,11 @@ static bool construct( } { - #if defined(CONFIG_DRM_AMD_DC_DCN1_0) struct irq_service_init_data init_data; init_data.ctx = dc->ctx; pool->base.irqs = dal_irq_service_dcn10_create(&init_data); if (!pool->base.irqs) - goto irqs_create_fail; - #endif + goto fail; } /* index to valid pipe resource */ @@ -1369,7 +1367,7 @@ static bool construct( BREAK_TO_DEBUGGER(); dm_error( "DC: failed to create memory input!\n"); - goto mi_create_fail; + goto fail; } pool->base.ipps[j] = dcn10_ipp_create(ctx, i); @@ -1377,7 +1375,7 @@ static bool construct( BREAK_TO_DEBUGGER(); dm_error( "DC: failed to create input pixel processor!\n"); - goto ipp_create_fail; + goto fail; } pool->base.dpps[j] = dcn10_dpp_create(ctx, i); @@ -1385,7 +1383,7 @@ static bool construct( BREAK_TO_DEBUGGER(); dm_error( "DC: failed to create dpp!\n"); - goto dpp_create_fail; + goto fail; } pool->base.opps[j] = dcn10_opp_create(ctx, i); @@ -1393,7 +1391,7 @@ static bool construct( BREAK_TO_DEBUGGER(); dm_error( "DC: failed to create output pixel processor!\n"); - goto opp_create_fail; + goto fail; } pool->base.timing_generators[j] = dcn10_timing_generator_create( @@ -1401,7 +1399,7 @@ static bool construct( if (pool->base.timing_generators[j] == NULL) { BREAK_TO_DEBUGGER(); dm_error("DC: failed to create tg!\n"); - goto otg_create_fail; + goto fail; } /* check next valid pipe */ j++; @@ -1420,13 +1418,13 @@ static bool construct( if (pool->base.mpc == NULL) { BREAK_TO_DEBUGGER(); dm_error("DC: failed to create mpc!\n"); - goto mpc_create_fail; + goto fail; } if (!resource_construct(num_virtual_links, dc, &pool->base, (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? &res_create_funcs : &res_create_maximus_funcs))) - goto res_create_fail; + goto fail; dcn10_hw_sequencer_construct(dc); dc->caps.max_planes = pool->base.pipe_count; @@ -1435,16 +1433,7 @@ static bool construct( return true; -disp_clk_create_fail: -mpc_create_fail: -otg_create_fail: -opp_create_fail: -dpp_create_fail: -ipp_create_fail: -mi_create_fail: -irqs_create_fail: -res_create_fail: -clock_source_create_fail: +fail: destruct(pool); -- GitLab From e643b1d53dee10a802dfdf6b7cfb91100113e678 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 8 Sep 2017 10:41:46 -0400 Subject: [PATCH 0590/2547] drm/amd/display: Clean some unneeded defines from ddc_service_types.h Remove defines we no longer need Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- .../amd/display/include/ddc_service_types.h | 33 ------------------- 1 file changed, 33 deletions(-) diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h index 0ff2a899b8f7..019e7a095ea1 100644 --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h @@ -27,12 +27,8 @@ #define DP_BRANCH_DEVICE_ID_1 0x0010FA #define DP_BRANCH_DEVICE_ID_2 0x0022B9 -#define DP_SINK_DEVICE_ID_1 0x4CE000 #define DP_BRANCH_DEVICE_ID_3 0x00001A #define DP_BRANCH_DEVICE_ID_4 0x0080e1 -#define DP_BRANCH_DEVICE_ID_5 0x006037 -#define DP_SINK_DEVICE_ID_2 0x001CF8 - enum ddc_result { DDC_RESULT_UNKNOWN = 0, @@ -115,40 +111,11 @@ struct av_sync_data { uint8_t aud_del_ins3;/* DPCD 0002Dh */ }; -/*DP to VGA converter*/ -static const uint8_t DP_VGA_CONVERTER_ID_1[] = "mVGAa"; -/*DP to Dual link DVI converter*/ -static const uint8_t DP_DVI_CONVERTER_ID_1[] = "m2DVIa"; /*Travis*/ static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; /*Nutmeg*/ static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; -/*DP to VGA converter*/ -static const uint8_t DP_VGA_CONVERTER_ID_4[] = "DpVga"; /*DP to Dual link DVI converter*/ static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa"; -/*DP to Dual link DVI converter 2*/ -static const uint8_t DP_DVI_CONVERTER_ID_42[] = "v2DVIa"; - -static const uint8_t DP_SINK_DEV_STRING_ID2_REV0[] = "\0\0\0\0\0\0"; - -/* Identifies second generation PSR TCON from Parade: Device ID string: - * yy-xx-**-**-**-** - */ -/* xx - Hw ID high byte */ -static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_HIGH_BYTE = - 0x06; - -/* yy - HW ID low byte, the same silicon has several package/feature flavors */ -static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE1 = - 0x61; -static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE2 = - 0x62; -static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE3 = - 0x63; -static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE4 = - 0x72; -static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE5 = - 0x73; #endif /* __DAL_DDC_SERVICE_TYPES_H__ */ -- GitLab From c42c275ce3d184100a00b40bd40af0790f20702b Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Thu, 12 Oct 2017 14:46:38 -0400 Subject: [PATCH 0591/2547] drm/amd/display: cleaning up hubp for dcn removing duplicate functions, renaming struct mi_regs, etc. Signed-off-by: Yue Hin Lau Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 16 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 345 +++++++++--------- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 24 +- 3 files changed, 193 insertions(+), 192 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c index b13dee64e0ce..a19fac70b056 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -29,14 +29,14 @@ #include "dcn10_hubp.h" #define REG(reg)\ - hubp1->mi_regs->reg + hubp1->hubp_regs->reg #define CTX \ hubp1->base.ctx #undef FN #define FN(reg_name, field_name) \ - hubp1->mi_shift->field_name, hubp1->mi_mask->field_name + hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name void hubp1_set_blank(struct hubp *hubp, bool blank) { @@ -943,15 +943,15 @@ void dcn10_hubp_construct( struct dcn10_hubp *hubp1, struct dc_context *ctx, uint32_t inst, - const struct dcn_mi_registers *mi_regs, - const struct dcn_mi_shift *mi_shift, - const struct dcn_mi_mask *mi_mask) + const struct dcn_mi_registers *hubp_regs, + const struct dcn_mi_shift *hubp_shift, + const struct dcn_mi_mask *hubp_mask) { hubp1->base.funcs = &dcn10_hubp_funcs; hubp1->base.ctx = ctx; - hubp1->mi_regs = mi_regs; - hubp1->mi_shift = mi_shift; - hubp1->mi_mask = mi_mask; + hubp1->hubp_regs = hubp_regs; + hubp1->hubp_shift = hubp_shift; + hubp1->hubp_mask = hubp_mask; hubp1->base.inst = inst; hubp1->base.opp_id = 0xf; hubp1->base.mpcc_id = 0xf; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h index 66db453c801b..a7834dd50716 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h @@ -30,7 +30,7 @@ #define TO_DCN10_HUBP(hubp)\ container_of(hubp, struct dcn10_hubp, base) -#define MI_REG_LIST_DCN(id)\ +#define HUBP_REG_LIST_DCN(id)\ SRI(DCHUBP_CNTL, HUBP, id),\ SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ @@ -98,8 +98,8 @@ SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id) -#define MI_REG_LIST_DCN10(id)\ - MI_REG_LIST_DCN(id),\ +#define HUBP_REG_LIST_DCN10(id)\ + HUBP_REG_LIST_DCN(id),\ SRI(PREFETCH_SETTINS, HUBPREQ, id),\ SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\ SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\ @@ -235,169 +235,170 @@ struct dcn_mi_registers { uint32_t CURSOR_DST_OFFSET; }; -#define MI_SF(reg_name, field_name, post_fix)\ +#define HUBP_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix -#define MI_MASK_SH_LIST_DCN(mask_sh)\ - MI_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ - MI_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ - MI_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\ - MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ - MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\ - MI_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\ - MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\ - MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\ - MI_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ - MI_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ - MI_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ - MI_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ - MI_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\ - MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ - MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ - MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ - MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ - MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ - MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ - MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ - MI_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ - MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ - MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\ - MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\ - MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\ - MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\ - MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\ - MI_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\ - MI_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\ - MI_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\ - MI_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\ - MI_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\ - MI_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\ - MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\ - MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\ - MI_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\ - MI_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\ - MI_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\ - MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\ - MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\ - MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\ - MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\ - MI_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\ - MI_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\ - MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\ - MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\ - MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\ - MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\ - MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ - MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ - MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ - MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh) - -#define MI_MASK_SH_LIST_DCN10(mask_sh)\ - MI_MASK_SH_LIST_DCN(mask_sh),\ - MI_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\ - MI_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\ - MI_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ - MI_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\ - MI_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ - MI_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ - MI_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ - MI_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ - MI_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ - MI_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ - MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ - MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ - MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ - MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ - MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ - MI_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ - MI_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ - MI_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ - MI_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ - MI_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) - -#define DCN_MI_REG_FIELD_LIST(type) \ +#define HUBP_MASK_SH_LIST_DCN(mask_sh)\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\ + HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\ + HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\ + HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\ + HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\ + HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\ + HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\ + HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\ + HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\ + HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\ + HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\ + HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh) + +#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\ + HUBP_MASK_SH_LIST_DCN(mask_sh),\ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ + HUBP_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\ + HUBP_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ + HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) + + +#define DCN_HUBP_REG_FIELD_LIST(type) \ type HUBP_BLANK_EN;\ type HUBP_TTU_DISABLE;\ type HUBP_NO_OUTSTANDING_REQ;\ @@ -577,18 +578,18 @@ struct dcn_mi_registers { type OUTPUT_FP struct dcn_mi_shift { - DCN_MI_REG_FIELD_LIST(uint8_t); + DCN_HUBP_REG_FIELD_LIST(uint8_t); }; struct dcn_mi_mask { - DCN_MI_REG_FIELD_LIST(uint32_t); + DCN_HUBP_REG_FIELD_LIST(uint32_t); }; struct dcn10_hubp { struct hubp base; - const struct dcn_mi_registers *mi_regs; - const struct dcn_mi_shift *mi_shift; - const struct dcn_mi_mask *mi_mask; + const struct dcn_mi_registers *hubp_regs; + const struct dcn_mi_shift *hubp_shift; + const struct dcn_mi_mask *hubp_mask; }; void hubp1_program_surface_config( @@ -656,9 +657,9 @@ void dcn10_hubp_construct( struct dcn10_hubp *hubp1, struct dc_context *ctx, uint32_t inst, - const struct dcn_mi_registers *mi_regs, - const struct dcn_mi_shift *mi_shift, - const struct dcn_mi_mask *mi_mask); + const struct dcn_mi_registers *hubp_regs, + const struct dcn_mi_shift *hubp_shift, + const struct dcn_mi_mask *hubp_mask); struct dcn_hubp_state { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 6ca01937a0a4..4c3be7c0f9b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -367,25 +367,25 @@ static const struct bios_registers bios_regs = { NBIO_SR(BIOS_SCRATCH_6) }; -#define mi_regs(id)\ +#define hubp_regs(id)\ [id] = {\ - MI_REG_LIST_DCN10(id)\ + HUBP_REG_LIST_DCN10(id)\ } -static const struct dcn_mi_registers mi_regs[] = { - mi_regs(0), - mi_regs(1), - mi_regs(2), - mi_regs(3), +static const struct dcn_mi_registers hubp_regs[] = { + hubp_regs(0), + hubp_regs(1), + hubp_regs(2), + hubp_regs(3), }; -static const struct dcn_mi_shift mi_shift = { - MI_MASK_SH_LIST_DCN10(__SHIFT) +static const struct dcn_mi_shift hubp_shift = { + HUBP_MASK_SH_LIST_DCN10(__SHIFT) }; -static const struct dcn_mi_mask mi_mask = { - MI_MASK_SH_LIST_DCN10(_MASK) +static const struct dcn_mi_mask hubp_mask = { + HUBP_MASK_SH_LIST_DCN10(_MASK) }; #define clk_src_regs(index, pllid)\ @@ -768,7 +768,7 @@ static struct hubp *dcn10_hubp_create( return NULL; dcn10_hubp_construct(hubp1, ctx, inst, - &mi_regs[inst], &mi_shift, &mi_mask); + &hubp_regs[inst], &hubp_shift, &hubp_mask); return &hubp1->base; } -- GitLab From 59c185ac4e54a569cb5e0b7142eae33814ecb7b7 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 12 Oct 2017 10:23:22 -0400 Subject: [PATCH 0592/2547] drm/amd/display: Explicit casting for grph object ids C++ compilers don't like the implicit conversion Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/include/grph_object_id.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/include/grph_object_id.h b/drivers/gpu/drm/amd/display/include/grph_object_id.h index 5eb2b4dc7b9c..03a7a9ca95ea 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_id.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_id.h @@ -248,7 +248,7 @@ static inline enum controller_id dal_graphics_object_id_get_controller_id( struct graphics_object_id id) { if (id.type == OBJECT_TYPE_CONTROLLER) - return id.id; + return (enum controller_id) id.id; return CONTROLLER_ID_UNDEFINED; } @@ -256,7 +256,7 @@ static inline enum clock_source_id dal_graphics_object_id_get_clock_source_id( struct graphics_object_id id) { if (id.type == OBJECT_TYPE_CLOCK_SOURCE) - return id.id; + return (enum clock_source_id) id.id; return CLOCK_SOURCE_ID_UNDEFINED; } @@ -264,7 +264,7 @@ static inline enum encoder_id dal_graphics_object_id_get_encoder_id( struct graphics_object_id id) { if (id.type == OBJECT_TYPE_ENCODER) - return id.id; + return (enum encoder_id) id.id; return ENCODER_ID_UNKNOWN; } @@ -272,7 +272,7 @@ static inline enum connector_id dal_graphics_object_id_get_connector_id( struct graphics_object_id id) { if (id.type == OBJECT_TYPE_CONNECTOR) - return id.id; + return (enum connector_id) id.id; return CONNECTOR_ID_UNKNOWN; } @@ -280,7 +280,7 @@ static inline enum audio_id dal_graphics_object_id_get_audio_id( struct graphics_object_id id) { if (id.type == OBJECT_TYPE_AUDIO) - return id.id; + return (enum audio_id) id.id; return AUDIO_ID_UNKNOWN; } @@ -288,7 +288,7 @@ static inline enum engine_id dal_graphics_object_id_get_engine_id( struct graphics_object_id id) { if (id.type == OBJECT_TYPE_ENGINE) - return id.id; + return (enum engine_id) id.id; return ENGINE_ID_UNKNOWN; } #endif -- GitLab From 7d2638a61ad16aa7145cd3b68ae5757ab988ccab Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Wed, 18 Oct 2017 11:59:13 -0400 Subject: [PATCH 0593/2547] drm/amd/display: Set cursor position as per address. In case of pipe split, cursor position should also be programmed as per cursor address. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index b477a6508db4..40178d8251b8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2414,7 +2414,6 @@ static void program_all_pipe_in_tree( } if (pipe_ctx->plane_state != NULL) { - struct dc_cursor_position position = { 0 }; struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; @@ -2434,11 +2433,13 @@ static void program_all_pipe_in_tree( update_dchubp_dpp(dc, pipe_ctx, context); /* TODO: this is a hack w/a for switching from mpo to pipe split */ - dc_stream_set_cursor_position(pipe_ctx->stream, &position); + if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { + struct dc_cursor_position position = { 0 }; - if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) + dc_stream_set_cursor_position(pipe_ctx->stream, &position); dc_stream_set_cursor_attributes(pipe_ctx->stream, &pipe_ctx->stream->cursor_attributes); + } if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { dc->hwss.set_input_transfer_func( -- GitLab From 4952d4c584ba769919866c27b442c4239ef20a12 Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Wed, 18 Oct 2017 16:14:40 -0400 Subject: [PATCH 0594/2547] drm/amd/display: DMCU FW loading from PSP Update the programming sequence to allow DMCU firmware to be loaded by PSP. This code detects whether the firmware is loaded and does a check to verify the expected interface version and checks for correct response from micro controller. Added registry key method to allow force loading of firmware from kernel mode driver for test purposes. This is old method of firmware loading without PSP. Moved some init sequences into dc/dmcu. Changed loading sequence to initialize IRAM after firmware completely loaded. Firmware will now disable features that use IRAM until initialized. Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 176 +++++++++++++++++- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 12 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 + drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h | 16 ++ 4 files changed, 202 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index fd77df573b61..508c1aa4a775 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -49,9 +49,18 @@ #define PSR_EXIT 0x21 #define PSR_SET 0x23 #define PSR_SET_WAITLOOP 0x31 +#define MCP_INIT_DMCU 0x88 +#define MCP_INIT_IRAM 0x89 +#define MCP_DMCU_VERSION 0x90 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L unsigned int cached_wait_loop_number = 0; +static bool dce_dmcu_init(struct dmcu *dmcu) +{ + // Do nothing + return true; +} + bool dce_dmcu_load_iram(struct dmcu *dmcu, unsigned int start_offset, const char *src, @@ -84,7 +93,7 @@ static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); - uint32_t psrStateOffset = 0xf0; + uint32_t psr_state_offset = 0xf0; /* Enable write access to IRAM */ REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); @@ -92,7 +101,7 @@ static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ - REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset); + REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ *psr_state = REG_READ(DMCU_IRAM_RD_DATA); @@ -286,7 +295,128 @@ static void dce_get_psr_wait_loop(unsigned int *psr_wait_loop_number) } #if defined(CONFIG_DRM_AMD_DC_DCN1_0) -bool dcn10_dmcu_load_iram(struct dmcu *dmcu, +static void dcn10_get_dmcu_state(struct dmcu *dmcu) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + uint32_t dmcu_state_offset = 0xf6; + + /* Enable write access to IRAM */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 1, + IRAM_RD_ADDR_AUTO_INC, 1); + + REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); + + /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ + REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_state_offset); + + /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ + dmcu->dmcu_state = REG_READ(DMCU_IRAM_RD_DATA); + + /* Disable write access to IRAM to allow dynamic sleep state */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 0, + IRAM_RD_ADDR_AUTO_INC, 0); +} + +static void dcn10_get_dmcu_version(struct dmcu *dmcu) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + uint32_t dmcu_version_offset = 0xf1; + + /* Clear scratch */ + REG_WRITE(DC_DMCU_SCRATCH, 0); + + /* Enable write access to IRAM */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 1, + IRAM_RD_ADDR_AUTO_INC, 1); + + REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); + + /* Write address to IRAM_RD_ADDR and read from DATA register */ + REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); + dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); + dmcu->dmcu_version.year = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | + REG_READ(DMCU_IRAM_RD_DATA)); + dmcu->dmcu_version.month = REG_READ(DMCU_IRAM_RD_DATA); + dmcu->dmcu_version.day = REG_READ(DMCU_IRAM_RD_DATA); + + /* Disable write access to IRAM to allow dynamic sleep state */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 0, + IRAM_RD_ADDR_AUTO_INC, 0); + + /* Send MCP command message to DMCU to get version reply from FW. + * We expect this version should match the one in IRAM, otherwise + * something is wrong with DMCU and we should fail and disable UC. + */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); + + /* Set command to get DMCU version from microcontroller */ + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, + MCP_DMCU_VERSION); + + /* Notify microcontroller of new command */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); + + /* Ensure command has been executed before continuing */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); + + /* Somehow version does not match, so fail and return version 0 */ + if (dmcu->dmcu_version.interface_version != REG_READ(DC_DMCU_SCRATCH)) + dmcu->dmcu_version.interface_version = 0; +} + +static bool dcn10_dmcu_init(struct dmcu *dmcu) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + + /* DMCU FW should populate the scratch register if running */ + if (REG_READ(DC_DMCU_SCRATCH) == 0) + return false; + + /* Check state is uninitialized */ + dcn10_get_dmcu_state(dmcu); + + /* If microcontroller is already initialized, do nothing */ + if (dmcu->dmcu_state == DMCU_RUNNING) + return true; + + /* Retrieve and cache the DMCU firmware version. */ + dcn10_get_dmcu_version(dmcu); + + /* Check interface version to confirm firmware is loaded and running */ + if (dmcu->dmcu_version.interface_version == 0) + return false; + + /* Wait until microcontroller is ready to process interrupt */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); + + /* Set initialized ramping boundary value */ + REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); + + /* Set command to initialize microcontroller */ + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, + MCP_INIT_DMCU); + + /* Notify microcontroller of new command */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); + + /* Ensure command has been executed before continuing */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); + + // Check state is initialized + dcn10_get_dmcu_state(dmcu); + + // If microcontroller is not in running state, fail + if (dmcu->dmcu_state != DMCU_RUNNING) + return false; + + return true; +} + +static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, unsigned int start_offset, const char *src, unsigned int bytes) @@ -294,7 +424,9 @@ bool dcn10_dmcu_load_iram(struct dmcu *dmcu, struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); unsigned int count = 0; - REG_UPDATE(DMCU_CTRL, DMCU_ENABLE, 1); + /* If microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != DMCU_RUNNING) + return false; /* Enable write access to IRAM */ REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, @@ -313,6 +445,19 @@ bool dcn10_dmcu_load_iram(struct dmcu *dmcu, IRAM_HOST_ACCESS_EN, 0, IRAM_WR_ADDR_AUTO_INC, 0); + /* Wait until microcontroller is ready to process interrupt */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); + + /* Set command to signal IRAM is loaded and to initialize IRAM */ + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, + MCP_INIT_IRAM); + + /* Notify microcontroller of new command */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); + + /* Ensure command has been executed before continuing */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); + return true; } @@ -320,7 +465,11 @@ static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); - uint32_t psrStateOffset = 0xf0; + uint32_t psr_state_offset = 0xf0; + + /* If microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != DMCU_RUNNING) + return; /* Enable write access to IRAM */ REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); @@ -328,7 +477,7 @@ static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ - REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset); + REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ *psr_state = REG_READ(DMCU_IRAM_RD_DATA); @@ -348,6 +497,10 @@ static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) unsigned int retryCount; uint32_t psr_state = 0; + /* If microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != DMCU_RUNNING) + return; + /* waitDMCUReadyForCmd */ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, dmcu_wait_reg_ready_interval, @@ -399,6 +552,10 @@ static void dcn10_dmcu_setup_psr(struct dmcu *dmcu, union dce_dmcu_psr_config_data_reg2 masterCmdData2; union dce_dmcu_psr_config_data_reg3 masterCmdData3; + /* If microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != DMCU_RUNNING) + return; + link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, psr_context->psrExitLinkTrainingRequired); @@ -505,6 +662,11 @@ static void dcn10_psr_wait_loop( { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; + + /* If microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != DMCU_RUNNING) + return; + if (wait_loop_number != 0) { /* waitDMCUReadyForCmd */ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); @@ -531,6 +693,7 @@ static void dcn10_get_psr_wait_loop(unsigned int *psr_wait_loop_number) #endif static const struct dmcu_funcs dce_funcs = { + .dmcu_init = dce_dmcu_init, .load_iram = dce_dmcu_load_iram, .set_psr_enable = dce_dmcu_set_psr_enable, .setup_psr = dce_dmcu_setup_psr, @@ -541,6 +704,7 @@ static const struct dmcu_funcs dce_funcs = { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) static const struct dmcu_funcs dcn10_funcs = { + .dmcu_init = dcn10_dmcu_init, .load_iram = dcn10_dmcu_load_iram, .set_psr_enable = dcn10_dmcu_set_psr_enable, .setup_psr = dcn10_dmcu_setup_psr, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h index b85f53c2f6f8..4c25e2dd28f8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h @@ -31,6 +31,7 @@ #define DMCU_COMMON_REG_LIST_DCE_BASE() \ SR(DMCU_CTRL), \ + SR(DMCU_STATUS), \ SR(DMCU_RAM_ACCESS_CTRL), \ SR(DMCU_IRAM_WR_CTRL), \ SR(DMCU_IRAM_WR_DATA), \ @@ -42,7 +43,8 @@ SR(DMCU_IRAM_RD_CTRL), \ SR(DMCU_IRAM_RD_DATA), \ SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ - SR(SMU_INTERRUPT_CONTROL) + SR(SMU_INTERRUPT_CONTROL), \ + SR(DC_DMCU_SCRATCH) #define DMCU_DCE110_COMMON_REG_LIST() \ DMCU_COMMON_REG_LIST_DCE_BASE(), \ @@ -58,10 +60,14 @@ #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ DMCU_SF(DMCU_CTRL, \ DMCU_ENABLE, mask_sh), \ + DMCU_SF(DMCU_STATUS, \ + UC_IN_STOP_MODE, mask_sh), \ DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ IRAM_HOST_ACCESS_EN, mask_sh), \ DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ IRAM_WR_ADDR_AUTO_INC, mask_sh), \ + DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ + IRAM_RD_ADDR_AUTO_INC, mask_sh), \ DMCU_SF(MASTER_COMM_CMD_REG, \ MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ @@ -89,7 +95,9 @@ type DMCU_IRAM_MEM_PWR_STATE; \ type IRAM_HOST_ACCESS_EN; \ type IRAM_WR_ADDR_AUTO_INC; \ + type IRAM_RD_ADDR_AUTO_INC; \ type DMCU_ENABLE; \ + type UC_IN_STOP_MODE; \ type MASTER_COMM_CMD_REG_BYTE0; \ type MASTER_COMM_INTERRUPT; \ type DPHY_RX_FAST_TRAINING_CAPABLE; \ @@ -112,6 +120,7 @@ struct dce_dmcu_mask { struct dce_dmcu_registers { uint32_t DMCU_CTRL; + uint32_t DMCU_STATUS; uint32_t DMCU_RAM_ACCESS_CTRL; uint32_t DCI_MEM_PWR_STATUS; uint32_t DMU_MEM_PWR_CNTL; @@ -127,6 +136,7 @@ struct dce_dmcu_registers { uint32_t DMCU_IRAM_RD_DATA; uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK; uint32_t SMU_INTERRUPT_CONTROL; + uint32_t DC_DMCU_SCRATCH; }; struct dce_dmcu { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 40178d8251b8..cd9e5484738d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -31,6 +31,7 @@ #include "dce110/dce110_hw_sequencer.h" #include "dce/dce_hwseq.h" #include "abm.h" +#include "dmcu.h" #include "dcn10/dcn10_timing_generator.h" #include "dcn10/dcn10_dpp.h" #include "dcn10/dcn10_mpc.h" @@ -863,6 +864,7 @@ static void dcn10_init_hw(struct dc *dc) { int i; struct abm *abm = dc->res_pool->abm; + struct dmcu *dmcu = dc->res_pool->dmcu; struct dce_hwseq *hws = dc->hwseq; if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { @@ -925,6 +927,9 @@ static void dcn10_init_hw(struct dc *dc) abm->funcs->abm_init(abm); } + if (dmcu != NULL) + dmcu->funcs->dmcu_init(dmcu); + /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ REG_WRITE(DIO_MEM_PWR_CTRL, 0); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h index 0574c29cc4a8..67996c662c0b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h @@ -27,12 +27,28 @@ #include "dm_services_types.h" +enum dmcu_state { + DMCU_NOT_INITIALIZED = 0, + DMCU_RUNNING = 1 +}; + +struct dmcu_version { + unsigned int day; + unsigned int month; + unsigned int year; + unsigned int interface_version; +}; + struct dmcu { struct dc_context *ctx; const struct dmcu_funcs *funcs; + + enum dmcu_state dmcu_state; + struct dmcu_version dmcu_version; }; struct dmcu_funcs { + bool (*dmcu_init)(struct dmcu *dmcu); bool (*load_iram)(struct dmcu *dmcu, unsigned int start_offset, const char *src, -- GitLab From 0858a8f2047007fdb6a50339d72226fa1e242fa2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 4 Dec 2017 15:49:59 -0500 Subject: [PATCH 0595/2547] drm/amd/display: add mod_freesync_user_enable to dm_connector_state We don't currently expose variable refresh rate, but add the state to the connector state to make it easier to maintain the support for it from a hw support perspective while we figure out the uapi for drm. Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c324c3b76fac..b2359bc4900d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1686,6 +1686,7 @@ struct dm_connector_state { uint8_t underscan_vborder; uint8_t underscan_hborder; bool underscan_enable; + struct mod_freesync_user_enable user_enable; }; #define to_dm_connector_state(x)\ -- GitLab From bfe1708c80d5d7cf08b7907b1850d2d3bf688db2 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Mon, 16 Oct 2017 15:51:00 -0400 Subject: [PATCH 0596/2547] drm/amd/display: Atomic freesync ASSERT fix Changes to atomic set property for freesync. Now In set property, just set the freesync variables and return 0. Based on the variables call mod_freesync_set_user_enable() inside commit_tail Signed-off-by: Bhawanpreet Lakha Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b2359bc4900d..e99ba554f5b9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4154,6 +4154,33 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) mod_freesync_add_stream(adev->dm.freesync_module, new_stream, &aconnector->caps); } + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + struct amdgpu_dm_connector *aconnector = NULL; + struct dm_connector_state *conn_state = NULL; + struct dm_crtc_state *acrtc_state = NULL; + + acrtc_state = to_dm_crtc_state(acrtc->base.state); + + + aconnector = + amdgpu_dm_find_first_crtc_matching_connector( + state, + crtc, + false); + if (aconnector) { + conn_state = to_dm_connector_state(aconnector->base.state); + + if (new_stream) { + mod_freesync_set_user_enable(adev->dm.freesync_module, + &acrtc_state->stream, + 1, + &conn_state->user_enable); + } + } + } } if (dm_state->context) -- GitLab From f01a2cf0a613c52acf941c764f344aefb8949591 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Tue, 17 Oct 2017 12:42:58 -0400 Subject: [PATCH 0597/2547] drm/amd/display: Cleanup code that enables freesync This is a follow-up patch to: Bhawanpreet Lakha Atomic freesync ASSERT fix Changes: - Combine to use one iterator - Use new DRM iterators. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Bhawanpreet Lakha Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 55 +++++++------------ 1 file changed, 19 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e99ba554f5b9..816aa426ddd3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4038,7 +4038,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; - struct dc_stream_state *new_stream = NULL; unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; @@ -4133,52 +4132,36 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) * are removed from freesync module */ if (adev->dm.freesync_module) { - for (i = 0; i < new_crtcs_count; i++) { + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { struct amdgpu_dm_connector *aconnector = NULL; + struct dm_connector_state *dm_new_con_state = NULL; + struct amdgpu_crtc *acrtc = NULL; - new_crtc_state = drm_atomic_get_new_crtc_state(state, - &new_crtcs[i]->base); dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + acrtc = to_amdgpu_crtc(crtc); - new_stream = dm_new_crtc_state->stream; - aconnector = amdgpu_dm_find_first_crtc_matching_connector( - state, - &new_crtcs[i]->base); + aconnector = + amdgpu_dm_find_first_crtc_matching_connector( + state, crtc); if (!aconnector) { DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d " "skipping freesync init\n", - new_crtcs[i]->crtc_id); + acrtc->crtc_id); continue; } mod_freesync_add_stream(adev->dm.freesync_module, - new_stream, &aconnector->caps); - } - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - struct amdgpu_dm_connector *aconnector = NULL; - struct dm_connector_state *conn_state = NULL; - struct dm_crtc_state *acrtc_state = NULL; - - acrtc_state = to_dm_crtc_state(acrtc->base.state); - - - aconnector = - amdgpu_dm_find_first_crtc_matching_connector( - state, - crtc, - false); - if (aconnector) { - conn_state = to_dm_connector_state(aconnector->base.state); - - if (new_stream) { - mod_freesync_set_user_enable(adev->dm.freesync_module, - &acrtc_state->stream, - 1, - &conn_state->user_enable); - } + dm_new_crtc_state->stream, + &aconnector->caps); + new_con_state = drm_atomic_get_new_connector_state( + state, &aconnector->base); + dm_new_con_state = to_dm_connector_state(new_con_state); + + if (dm_new_crtc_state->stream) { + mod_freesync_set_user_enable(adev->dm.freesync_module, + &dm_new_crtc_state->stream, + 1, + &dm_new_con_state->user_enable); } } } -- GitLab From 1c77d4eea7c7c441214c6f30416c7ee16f921fb0 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Wed, 18 Oct 2017 14:22:23 -0400 Subject: [PATCH 0598/2547] drm/amd/display: Only add stream to freesync when modeset required This is a follow-up patch to: Leo (Sunpeng) Li Cleanup code that enables freesync We should only add a stream to freesync if a modeset was requested, so we don't fill the core freesync map with pointless streams. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 ++++++++++++++----- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 816aa426ddd3..f4bebdc60351 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4132,12 +4132,28 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) * are removed from freesync module */ if (adev->dm.freesync_module) { - for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { struct amdgpu_dm_connector *aconnector = NULL; struct dm_connector_state *dm_new_con_state = NULL; struct amdgpu_crtc *acrtc = NULL; + bool modeset_needed; dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); + modeset_needed = modeset_required( + new_crtc_state, + dm_new_crtc_state->stream, + dm_old_crtc_state->stream); + /* We add stream to freesync if: + * 1. Said stream is not null, and + * 2. A modeset is requested. This means that the + * stream was removed previously, and needs to be + * replaced. + */ + if (dm_new_crtc_state->stream == NULL || + !modeset_needed) + continue; + acrtc = to_amdgpu_crtc(crtc); aconnector = @@ -4157,12 +4173,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) state, &aconnector->base); dm_new_con_state = to_dm_connector_state(new_con_state); - if (dm_new_crtc_state->stream) { - mod_freesync_set_user_enable(adev->dm.freesync_module, - &dm_new_crtc_state->stream, - 1, - &dm_new_con_state->user_enable); - } + mod_freesync_set_user_enable(adev->dm.freesync_module, + &dm_new_crtc_state->stream, + 1, + &dm_new_con_state->user_enable); } } -- GitLab From 3a393cf96ab38c72565fda106a825302828b7e05 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 23 Oct 2017 16:45:49 +0200 Subject: [PATCH 0599/2547] drm/amdgpu: fix indentation in amdgpu_display.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit That was somehow completely of. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index 3cc0ef0c055e..11ae4ab23768 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -25,9 +25,8 @@ struct drm_framebuffer * amdgpu_user_framebuffer_create(struct drm_device *dev, - struct drm_file *file_priv, - const struct drm_mode_fb_cmd2 *mode_cmd); - + struct drm_file *file_priv, + const struct drm_mode_fb_cmd2 *mode_cmd); void amdgpu_output_poll_changed(struct drm_device *dev); #endif -- GitLab From 48f05f2955e4a3183b219d6dfdb1c28e17d03da7 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Wed, 25 Oct 2017 16:21:08 +0800 Subject: [PATCH 0600/2547] amd/scheduler:imple job skip feature(v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit jobs are skipped under two cases 1)when the entity behind this job marked guilty, the job poped from this entity's queue will be dropped in sched_main loop. 2)in job_recovery(), skip the scheduling job if its karma detected above limit, and also skipped as well for other jobs sharing the same fence context. this approach is becuase job_recovery() cannot access job->entity due to entity may already dead. v2: some logic fix v3: when entity detected guilty, don't drop the job in the poping stage, instead set its fence error as -ECANCELED in run_job(), skip the scheduling either:1) fence->error < 0 or 2) there was a VRAM LOST occurred on this job. this way we can unify the job skipping logic. with this feature we can introduce new gpu recover feature. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 13 ++++--- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 39 +++++++++++-------- 2 files changed, 31 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index f60662e03761..0a90c768dbc1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -180,7 +180,7 @@ static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job, static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job) { - struct dma_fence *fence = NULL; + struct dma_fence *fence = NULL, *finished; struct amdgpu_device *adev; struct amdgpu_job *job; int r; @@ -190,15 +190,18 @@ static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job) return NULL; } job = to_amdgpu_job(sched_job); + finished = &job->base.s_fence->finished; adev = job->adev; BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL)); trace_amdgpu_sched_run_job(job); - /* skip ib schedule when vram is lost */ - if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter)) { - dma_fence_set_error(&job->base.s_fence->finished, -ECANCELED); - DRM_ERROR("Skip scheduling IBs!\n"); + + if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter)) + dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */ + + if (finished->error < 0) { + DRM_INFO("Skip scheduling IBs!\n"); } else { r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job, &fence); diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index f116de798204..941b5920b97b 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -345,6 +345,10 @@ amd_sched_entity_pop_job(struct amd_sched_entity *entity) if (amd_sched_entity_add_dependency_cb(entity)) return NULL; + /* skip jobs from entity that marked guilty */ + if (entity->guilty && atomic_read(entity->guilty)) + dma_fence_set_error(&sched_job->s_fence->finished, -ECANCELED); + spsc_queue_pop(&entity->job_queue); return sched_job; } @@ -441,14 +445,6 @@ static void amd_sched_job_timedout(struct work_struct *work) job->sched->ops->timedout_job(job); } -static void amd_sched_set_guilty(struct amd_sched_job *s_job, - struct amd_sched_entity *s_entity) -{ - if (atomic_inc_return(&s_job->karma) > s_job->sched->hang_limit) - if (s_entity->guilty) - atomic_set(s_entity->guilty, 1); -} - void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_job *bad) { struct amd_sched_job *s_job; @@ -468,21 +464,24 @@ void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_jo spin_unlock(&sched->job_list_lock); if (bad) { - bool found = false; - - for (i = AMD_SCHED_PRIORITY_MIN; i < AMD_SCHED_PRIORITY_MAX; i++ ) { + /* don't increase @bad's karma if it's from KERNEL RQ, + * becuase sometimes GPU hang would cause kernel jobs (like VM updating jobs) + * corrupt but keep in mind that kernel jobs always considered good. + */ + for (i = AMD_SCHED_PRIORITY_MIN; i < AMD_SCHED_PRIORITY_KERNEL; i++ ) { struct amd_sched_rq *rq = &sched->sched_rq[i]; spin_lock(&rq->lock); list_for_each_entry_safe(entity, tmp, &rq->entities, list) { if (bad->s_fence->scheduled.context == entity->fence_context) { - found = true; - amd_sched_set_guilty(bad, entity); + if (atomic_inc_return(&bad->karma) > bad->sched->hang_limit) + if (entity->guilty) + atomic_set(entity->guilty, 1); break; } } spin_unlock(&rq->lock); - if (found) + if (&entity->list != &rq->entities) break; } } @@ -500,6 +499,7 @@ void amd_sched_job_kickout(struct amd_sched_job *s_job) void amd_sched_job_recovery(struct amd_gpu_scheduler *sched) { struct amd_sched_job *s_job, *tmp; + bool found_guilty = false; int r; spin_lock(&sched->job_list_lock); @@ -511,6 +511,15 @@ void amd_sched_job_recovery(struct amd_gpu_scheduler *sched) list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) { struct amd_sched_fence *s_fence = s_job->s_fence; struct dma_fence *fence; + uint64_t guilty_context; + + if (!found_guilty && atomic_read(&s_job->karma) > sched->hang_limit) { + found_guilty = true; + guilty_context = s_job->s_fence->scheduled.context; + } + + if (found_guilty && s_job->s_fence->scheduled.context == guilty_context) + dma_fence_set_error(&s_fence->finished, -ECANCELED); spin_unlock(&sched->job_list_lock); fence = sched->ops->run_job(s_job); @@ -526,7 +535,6 @@ void amd_sched_job_recovery(struct amd_gpu_scheduler *sched) r); dma_fence_put(fence); } else { - DRM_ERROR("Failed to run job!\n"); amd_sched_process_job(NULL, &s_fence->cb); } spin_lock(&sched->job_list_lock); @@ -664,7 +672,6 @@ static int amd_sched_main(void *param) r); dma_fence_put(fence); } else { - DRM_ERROR("Failed to run job!\n"); amd_sched_process_job(NULL, &s_fence->cb); } -- GitLab From 5740682e66cef57626a328d237698cad329c0449 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Wed, 25 Oct 2017 16:37:02 +0800 Subject: [PATCH 0601/2547] drm/amdgpu:implement new GPU recover(v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1,new imple names amdgpu_gpu_recover which gives more hint on what it does compared with gpu_reset 2,gpu_recover unify bare-metal and SR-IOV, only the asic reset part is implemented differently 3,gpu_recover will increase hang job karma and mark its entity/context as guilty if exceeds limit V2: 4,in scheduler main routine the job from guilty context will be immedialy fake signaled after it poped from queue and its fence be set with "-ECANCELED" error 5,in scheduler recovery routine all jobs from the guilty entity would be dropped 6,in run_job() routine the real IB submission would be skipped if @skip parameter equales true or there was VRAM lost occured. V3: 7,replace deprecated gpu reset, use new gpu recover Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 322 ++++++++++----------- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 - drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 2 +- drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +- 8 files changed, 166 insertions(+), 184 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 88fa19b1a802..5714b7e8cb09 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -178,6 +178,10 @@ extern int amdgpu_cik_support; #define CIK_CURSOR_WIDTH 128 #define CIK_CURSOR_HEIGHT 128 +/* GPU RESET flags */ +#define AMDGPU_RESET_INFO_VRAM_LOST (1 << 0) +#define AMDGPU_RESET_INFO_FULLRESET (1 << 1) + struct amdgpu_device; struct amdgpu_ib; struct amdgpu_cs_parser; @@ -1833,7 +1837,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) /* Common functions */ -int amdgpu_gpu_reset(struct amdgpu_device *adev); +int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job); bool amdgpu_need_backup(struct amdgpu_device *adev); void amdgpu_pci_config_reset(struct amdgpu_device *adev); bool amdgpu_need_post(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e521850e9409..e287eeda2dab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2827,163 +2827,172 @@ static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, return r; } -/** - * amdgpu_sriov_gpu_reset - reset the asic +/* + * amdgpu_reset - reset ASIC/GPU for bare-metal or passthrough * * @adev: amdgpu device pointer - * @job: which job trigger hang + * @reset_flags: output param tells caller the reset result * - * Attempt the reset the GPU if it has hung (all asics). - * for SRIOV case. - * Returns 0 for success or an error on failure. - */ -int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) + * attempt to do soft-reset or full-reset and reinitialize Asic + * return 0 means successed otherwise failed +*/ +static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags) { - int i, j, r = 0; - int resched; - struct amdgpu_bo *bo, *tmp; - struct amdgpu_ring *ring; - struct dma_fence *fence = NULL, *next = NULL; + bool need_full_reset, vram_lost = 0; + int r; - mutex_lock(&adev->virt.lock_reset); - atomic_inc(&adev->gpu_reset_counter); - adev->in_sriov_reset = true; + need_full_reset = amdgpu_need_full_reset(adev); - /* block TTM */ - resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); + if (!need_full_reset) { + amdgpu_pre_soft_reset(adev); + r = amdgpu_soft_reset(adev); + amdgpu_post_soft_reset(adev); + if (r || amdgpu_check_soft_reset(adev)) { + DRM_INFO("soft reset failed, will fallback to full reset!\n"); + need_full_reset = true; + } - /* we start from the ring trigger GPU hang */ - j = job ? job->ring->idx : 0; + } - /* block scheduler */ - for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { - ring = adev->rings[i % AMDGPU_MAX_RINGS]; - if (!ring || !ring->sched.thread) - continue; + if (need_full_reset) { + r = amdgpu_suspend(adev); - kthread_park(ring->sched.thread); +retry: + amdgpu_atombios_scratch_regs_save(adev); + r = amdgpu_asic_reset(adev); + amdgpu_atombios_scratch_regs_restore(adev); + /* post card */ + amdgpu_atom_asic_init(adev->mode_info.atom_context); - if (job && j != i) - continue; + if (!r) { + dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); + r = amdgpu_resume_phase1(adev); + if (r) + goto out; - /* here give the last chance to check if job removed from mirror-list - * since we already pay some time on kthread_park */ - if (job && list_empty(&job->base.node)) { - kthread_unpark(ring->sched.thread); - goto give_up_reset; + vram_lost = amdgpu_check_vram_lost(adev); + if (vram_lost) { + DRM_ERROR("VRAM is lost!\n"); + atomic_inc(&adev->vram_lost_counter); + } + + r = amdgpu_ttm_recover_gart(adev); + if (r) + goto out; + + r = amdgpu_resume_phase2(adev); + if (r) + goto out; + + if (vram_lost) + amdgpu_fill_reset_magic(adev); } + } - if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit)) - amd_sched_job_kickout(&job->base); +out: + if (!r) { + amdgpu_irq_gpu_reset_resume_helper(adev); + r = amdgpu_ib_ring_tests(adev); + if (r) { + dev_err(adev->dev, "ib ring test failed (%d).\n", r); + r = amdgpu_suspend(adev); + need_full_reset = true; + goto retry; + } + } - /* only do job_reset on the hang ring if @job not NULL */ - amd_sched_hw_job_reset(&ring->sched, NULL); + if (reset_flags) { + if (vram_lost) + (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST; - /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ - amdgpu_fence_driver_force_completion(ring); + if (need_full_reset) + (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET; } - /* request to take full control of GPU before re-initialization */ - if (job) - amdgpu_virt_reset_gpu(adev); - else - amdgpu_virt_request_full_gpu(adev, true); + return r; +} + +/* + * amdgpu_reset_sriov - reset ASIC for SR-IOV vf + * + * @adev: amdgpu device pointer + * @reset_flags: output param tells caller the reset result + * + * do VF FLR and reinitialize Asic + * return 0 means successed otherwise failed +*/ +static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, bool from_hypervisor) +{ + int r; + if (from_hypervisor) + r = amdgpu_virt_request_full_gpu(adev, true); + else + r = amdgpu_virt_reset_gpu(adev); + if (r) + return r; /* Resume IP prior to SMC */ - amdgpu_sriov_reinit_early(adev); + r = amdgpu_sriov_reinit_early(adev); + if (r) + goto error; /* we need recover gart prior to run SMC/CP/SDMA resume */ amdgpu_ttm_recover_gart(adev); /* now we are okay to resume SMC/CP/SDMA */ - amdgpu_sriov_reinit_late(adev); + r = amdgpu_sriov_reinit_late(adev); + if (r) + goto error; amdgpu_irq_gpu_reset_resume_helper(adev); - - if (amdgpu_ib_ring_tests(adev)) + r = amdgpu_ib_ring_tests(adev); + if (r) dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); +error: /* release full control of GPU after ib test */ amdgpu_virt_release_full_gpu(adev, true); - DRM_INFO("recover vram bo from shadow\n"); - - ring = adev->mman.buffer_funcs_ring; - mutex_lock(&adev->shadow_list_lock); - list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { - next = NULL; - amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); - if (fence) { - r = dma_fence_wait(fence, false); - if (r) { - WARN(r, "recovery from shadow isn't completed\n"); - break; - } - } - - dma_fence_put(fence); - fence = next; - } - mutex_unlock(&adev->shadow_list_lock); - - if (fence) { - r = dma_fence_wait(fence, false); - if (r) - WARN(r, "recovery from shadow isn't completed\n"); - } - dma_fence_put(fence); - - for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { - ring = adev->rings[i % AMDGPU_MAX_RINGS]; - if (!ring || !ring->sched.thread) - continue; - - if (job && j != i) { - kthread_unpark(ring->sched.thread); - continue; - } - - amd_sched_job_recovery(&ring->sched); - kthread_unpark(ring->sched.thread); - } + if (reset_flags) { + /* will get vram_lost from GIM in future, now all + * reset request considered VRAM LOST + */ + (*reset_flags) |= ~AMDGPU_RESET_INFO_VRAM_LOST; + atomic_inc(&adev->vram_lost_counter); - drm_helper_resume_force_mode(adev->ddev); -give_up_reset: - ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); - if (r) { - /* bad news, how to tell it to userspace ? */ - dev_info(adev->dev, "GPU reset failed\n"); - } else { - dev_info(adev->dev, "GPU reset successed!\n"); + /* VF FLR or hotlink reset is always full-reset */ + (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET; } - adev->in_sriov_reset = false; - mutex_unlock(&adev->virt.lock_reset); return r; } /** - * amdgpu_gpu_reset - reset the asic + * amdgpu_gpu_recover - reset the asic and recover scheduler * * @adev: amdgpu device pointer + * @job: which job trigger hang * - * Attempt the reset the GPU if it has hung (all asics). + * Attempt to reset the GPU if it has hung (all asics). * Returns 0 for success or an error on failure. */ -int amdgpu_gpu_reset(struct amdgpu_device *adev) +int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job) { struct drm_atomic_state *state = NULL; - int i, r; - int resched; - bool need_full_reset, vram_lost = false; + uint64_t reset_flags = 0; + int i, r, resched; if (!amdgpu_check_soft_reset(adev)) { DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); return 0; } + dev_info(adev->dev, "GPU reset begin!\n"); + + mutex_lock(&adev->virt.lock_reset); atomic_inc(&adev->gpu_reset_counter); + adev->in_sriov_reset = 1; /* block TTM */ resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); @@ -2997,69 +3006,26 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) if (!ring || !ring->sched.thread) continue; + + /* only focus on the ring hit timeout if &job not NULL */ + if (job && job->ring->idx != i) + continue; + kthread_park(ring->sched.thread); - amd_sched_hw_job_reset(&ring->sched, NULL); + amd_sched_hw_job_reset(&ring->sched, &job->base); + /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ amdgpu_fence_driver_force_completion(ring); } - need_full_reset = amdgpu_need_full_reset(adev); - - if (!need_full_reset) { - amdgpu_pre_soft_reset(adev); - r = amdgpu_soft_reset(adev); - amdgpu_post_soft_reset(adev); - if (r || amdgpu_check_soft_reset(adev)) { - DRM_INFO("soft reset failed, will fallback to full reset!\n"); - need_full_reset = true; - } - } - - if (need_full_reset) { - r = amdgpu_suspend(adev); - -retry: - amdgpu_atombios_scratch_regs_save(adev); - r = amdgpu_asic_reset(adev); - amdgpu_atombios_scratch_regs_restore(adev); - /* post card */ - amdgpu_atom_asic_init(adev->mode_info.atom_context); + if (amdgpu_sriov_vf(adev)) + r = amdgpu_reset_sriov(adev, &reset_flags, job ? false : true); + else + r = amdgpu_reset(adev, &reset_flags); - if (!r) { - dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); - r = amdgpu_resume_phase1(adev); - if (r) - goto out; - vram_lost = amdgpu_check_vram_lost(adev); - if (vram_lost) { - DRM_ERROR("VRAM is lost!\n"); - atomic_inc(&adev->vram_lost_counter); - } - r = amdgpu_ttm_recover_gart(adev); - if (r) - goto out; - r = amdgpu_resume_phase2(adev); - if (r) - goto out; - if (vram_lost) - amdgpu_fill_reset_magic(adev); - } - } -out: if (!r) { - amdgpu_irq_gpu_reset_resume_helper(adev); - r = amdgpu_ib_ring_tests(adev); - if (r) { - dev_err(adev->dev, "ib ring test failed (%d).\n", r); - r = amdgpu_suspend(adev); - need_full_reset = true; - goto retry; - } - /** - * recovery vm page tables, since we cannot depend on VRAM is - * consistent after gpu full reset. - */ - if (need_full_reset && amdgpu_need_backup(adev)) { + if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) || + (reset_flags & AMDGPU_RESET_INFO_VRAM_LOST)) { struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; struct amdgpu_bo *bo, *tmp; struct dma_fence *fence = NULL, *next = NULL; @@ -3088,40 +3054,56 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) } dma_fence_put(fence); } + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; if (!ring || !ring->sched.thread) continue; + /* only focus on the ring hit timeout if &job not NULL */ + if (job && job->ring->idx != i) + continue; + amd_sched_job_recovery(&ring->sched); kthread_unpark(ring->sched.thread); } } else { - dev_err(adev->dev, "asic resume failed (%d).\n", r); for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { - if (adev->rings[i] && adev->rings[i]->sched.thread) { - kthread_unpark(adev->rings[i]->sched.thread); - } + struct amdgpu_ring *ring = adev->rings[i]; + + if (!ring || !ring->sched.thread) + continue; + + /* only focus on the ring hit timeout if &job not NULL */ + if (job && job->ring->idx != i) + continue; + + kthread_unpark(adev->rings[i]->sched.thread); } } if (amdgpu_device_has_dc_support(adev)) { - r = drm_atomic_helper_resume(adev->ddev, state); + if (drm_atomic_helper_resume(adev->ddev, state)) + dev_info(adev->dev, "drm resume failed:%d\n", r); amdgpu_dm_display_resume(adev); - } else + } else { drm_helper_resume_force_mode(adev->ddev); + } ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); + if (r) { /* bad news, how to tell it to userspace ? */ - dev_info(adev->dev, "GPU reset failed\n"); - } - else { - dev_info(adev->dev, "GPU reset successed!\n"); + dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter)); + amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); + } else { + dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter)); } amdgpu_vf_error_trans_all(adev); + adev->in_sriov_reset = 0; + mutex_unlock(&adev->virt.lock_reset); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index eda89dfdef5b..604ac03a42e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -694,25 +694,25 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) } /** - * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset + * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover * * Manually trigger a gpu reset at the next fence wait. */ -static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data) +static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_device *dev = node->minor->dev; struct amdgpu_device *adev = dev->dev_private; - seq_printf(m, "gpu reset\n"); - amdgpu_gpu_reset(adev); + seq_printf(m, "gpu recover\n"); + amdgpu_gpu_recover(adev, NULL); return 0; } static const struct drm_info_list amdgpu_debugfs_fence_list[] = { {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, - {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL} + {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL} }; static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 32590e4f9f7a..c340774082ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -88,7 +88,7 @@ static void amdgpu_irq_reset_work_func(struct work_struct *work) reset_work); if (!amdgpu_sriov_vf(adev)) - amdgpu_gpu_reset(adev); + amdgpu_gpu_recover(adev, NULL); } /* Disable *all* interrupts */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 0a90c768dbc1..18770a880393 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -37,10 +37,7 @@ static void amdgpu_job_timedout(struct amd_sched_job *s_job) atomic_read(&job->ring->fence_drv.last_seq), job->ring->fence_drv.sync_seq); - if (amdgpu_sriov_vf(job->adev)) - amdgpu_sriov_gpu_reset(job->adev, job); - else - amdgpu_gpu_reset(job->adev); + amdgpu_gpu_recover(job->adev, job); } int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index d149aca71a44..20bdb8fb0b8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -288,7 +288,6 @@ int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); int amdgpu_virt_wait_reset(struct amdgpu_device *adev); -int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job); int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size, diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index f91aab38637c..c32d0b0868e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -254,7 +254,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) } /* Trigger recovery due to world switch failure */ - amdgpu_sriov_gpu_reset(adev, NULL); + amdgpu_gpu_recover(adev, NULL); } static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index 27b03c773b1b..818ec0fe2f51 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -519,7 +519,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work) } /* Trigger recovery due to world switch failure */ - amdgpu_sriov_gpu_reset(adev, NULL); + amdgpu_gpu_recover(adev, NULL); } static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev, -- GitLab From 13a752e3a246493bfaba0cf0e0f376672ebb734c Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 17 Oct 2017 15:11:12 +0800 Subject: [PATCH 0602/2547] drm/amdgpu:cleanup in_sriov_reset and lock_reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit since now gpu reset is unified with gpu_recover for both bare-metal and SR-IOV: 1)rename in_sriov_reset to in_gpu_reset 2)move lock_reset from adev->virt to adev Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 +++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 - drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +++--- 8 files changed, 15 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 5714b7e8cb09..f25d246395a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1643,7 +1643,8 @@ struct amdgpu_device { /* record last mm index being written through WREG32*/ unsigned long last_mm_index; - bool in_sriov_reset; + bool in_gpu_reset; + struct mutex lock_reset; }; static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e287eeda2dab..9d4e0b88b101 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2163,6 +2163,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->mn_lock); mutex_init(&adev->virt.vf_errors.lock); hash_init(adev->mn_hash); + mutex_init(&adev->lock_reset); amdgpu_check_arguments(adev); @@ -2990,9 +2991,9 @@ int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job) dev_info(adev->dev, "GPU reset begin!\n"); - mutex_lock(&adev->virt.lock_reset); + mutex_lock(&adev->lock_reset); atomic_inc(&adev->gpu_reset_counter); - adev->in_sriov_reset = 1; + adev->in_gpu_reset = 1; /* block TTM */ resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); @@ -3102,8 +3103,8 @@ int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job) } amdgpu_vf_error_trans_all(adev); - adev->in_sriov_reset = 0; - mutex_unlock(&adev->virt.lock_reset); + adev->in_gpu_reset = 0; + mutex_unlock(&adev->lock_reset); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 447d446b5015..76f531b8e97b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -264,7 +264,7 @@ static int psp_hw_start(struct psp_context *psp) struct amdgpu_device *adev = psp->adev; int ret; - if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) { + if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { ret = psp_bootloader_load_sysdrv(psp); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index 65649026b836..edc37cc80644 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -370,7 +370,7 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) return 0; } - if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) { + if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index b7510bf6bc0f..733c64cbd1c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -115,8 +115,6 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) adev->enable_virtual_display = true; adev->cg_flags = 0; adev->pg_flags = 0; - - mutex_init(&adev->virt.lock_reset); } uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 20bdb8fb0b8c..e3f78f5edc00 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -239,7 +239,6 @@ struct amdgpu_virt { uint64_t csa_vmid0_addr; bool chained_ib_support; uint32_t reg_val_offs; - struct mutex lock_reset; struct amdgpu_irq_src ack_irq; struct amdgpu_irq_src rcv_irq; struct work_struct flr_work; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 46ee74393454..2ddf126614da 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4824,7 +4824,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring) gfx_v8_0_kiq_setting(ring); - if (adev->in_sriov_reset) { /* for GPU_RESET case */ + if (adev->in_gpu_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); @@ -4861,7 +4861,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) struct vi_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.compute_ring[0]; - if (!adev->in_sriov_reset && !adev->gfx.in_suspend) { + if (!adev->in_gpu_reset && !adev->gfx.in_suspend) { memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; @@ -4873,7 +4873,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); - } else if (adev->in_sriov_reset) { /* for GPU_RESET case */ + } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 46a0d3ef773f..19a619f759f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2757,7 +2757,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) gfx_v9_0_kiq_setting(ring); - if (adev->in_sriov_reset) { /* for GPU_RESET case */ + if (adev->in_gpu_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); @@ -2795,7 +2795,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) struct v9_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.compute_ring[0]; - if (!adev->in_sriov_reset && !adev->gfx.in_suspend) { + if (!adev->in_gpu_reset && !adev->gfx.in_suspend) { memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; @@ -2807,7 +2807,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); - } else if (adev->in_sriov_reset) { /* for GPU_RESET case */ + } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); -- GitLab From 503846e0836a62f6efd536a4c495917c1a50b345 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 17 Oct 2017 17:51:41 +0800 Subject: [PATCH 0603/2547] drm/amdgpu:cleanup ucode_init_bo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1,no sriov check since gpu recover is unified 2,need CPU_ACCESS_REQUIRED flag for VRAM if SRIOV because otherwise after following PIN the first allocated VRAM bo is wasted due to some TTM mgr reason. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index edc37cc80644..ab9b2d4461a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -370,10 +370,10 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) return 0; } - if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { + if (!adev->in_gpu_reset) { err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS|AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, NULL, NULL, 0, bo); if (err) { dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); -- GitLab From 77a3c96b1bcb5f69367df79f964367dd7f086dcc Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 19 Sep 2017 15:40:56 +0800 Subject: [PATCH 0604/2547] drm/amdgpu/sriov:fix memory leak in psp_load_fw MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit for SR-IOV when doing gpu reset this routine shouldn't do resource allocating otherwise memory leak Signed-off-by: Monk Liu Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 76f531b8e97b..2157d4509e84 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -334,23 +334,26 @@ static int psp_load_fw(struct amdgpu_device *adev) int ret; struct psp_context *psp = &adev->psp; + if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0) + goto skip_memalloc; + psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); if (!psp->cmd) return -ENOMEM; ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, - AMDGPU_GEM_DOMAIN_GTT, - &psp->fw_pri_bo, - &psp->fw_pri_mc_addr, - &psp->fw_pri_buf); + AMDGPU_GEM_DOMAIN_GTT, + &psp->fw_pri_bo, + &psp->fw_pri_mc_addr, + &psp->fw_pri_buf); if (ret) goto failed; ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_VRAM, - &psp->fence_buf_bo, - &psp->fence_buf_mc_addr, - &psp->fence_buf); + AMDGPU_GEM_DOMAIN_VRAM, + &psp->fence_buf_bo, + &psp->fence_buf_mc_addr, + &psp->fence_buf); if (ret) goto failed_mem2; @@ -375,6 +378,7 @@ static int psp_load_fw(struct amdgpu_device *adev) if (ret) goto failed_mem; +skip_memalloc: ret = psp_hw_start(psp); if (ret) goto failed_mem; -- GitLab From 34a4d2bf06b3ab92024b8e26d6049411369d1f1a Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 24 Oct 2017 15:10:11 +0800 Subject: [PATCH 0605/2547] drm/amdgpu:fix random missing of FLR NOTIFY MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Monk Liu Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index c32d0b0868e8..d31259e5bb45 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -282,9 +282,17 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev, /* see what event we get */ r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION); - /* only handle FLR_NOTIFY now */ - if (!r) - schedule_work(&adev->virt.flr_work); + /* sometimes the interrupt is delayed to inject to VM, so under such case + * the IDH_FLR_NOTIFICATION is overwritten by VF FLR from GIM side, thus + * above recieve message could be failed, we should schedule the flr_work + * anyway + */ + if (r) { + DRM_ERROR("FLR_NOTIFICATION is missed\n"); + xgpu_ai_mailbox_send_ack(adev); + } + + schedule_work(&adev->virt.flr_work); } return 0; -- GitLab From 3da917b6c6843ad0162e9768c40a83b6c4448646 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 27 Oct 2017 14:17:09 +0200 Subject: [PATCH 0606/2547] drm/amdgpu: nuke amdgpu_ttm_is_bound() v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename amdgpu_gtt_mgr_is_allocated() to amdgpu_gtt_mgr_has_gart_addr() and use that instead. v2: rename the function as well. Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 24 ++++++++------------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +-- 5 files changed, 15 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 00e0ce10862f..f7669dc6909b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -79,13 +79,13 @@ static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man) } /** - * amdgpu_gtt_mgr_is_allocated - Check if mem has address space + * amdgpu_gtt_mgr_has_gart_addr - Check if mem has address space * * @mem: the mem object to check * * Check if a mem object has already address space allocated. */ -bool amdgpu_gtt_mgr_is_allocated(struct ttm_mem_reg *mem) +bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem) { struct drm_mm_node *node = mem->mm_node; @@ -114,7 +114,7 @@ static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, unsigned long fpfn, lpfn; int r; - if (amdgpu_gtt_mgr_is_allocated(mem)) + if (amdgpu_gtt_mgr_has_gart_addr(mem)) return 0; if (place) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 589aa5099881..ff6f842655d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -982,7 +982,7 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) { WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT && - !amdgpu_ttm_is_bound(bo->tbo.ttm)); + !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem)); WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) && !bo->pin_count); WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 428aae048f4b..33615e2ea2e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -187,7 +187,7 @@ static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo) { switch (bo->tbo.mem.mem_type) { - case TTM_PL_TT: return amdgpu_ttm_is_bound(bo->tbo.ttm); + case TTM_PL_TT: return amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem); case TTM_PL_VRAM: return true; default: return false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 6a724f9f1b86..3d02c2dd06e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -282,8 +282,7 @@ static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo, { uint64_t addr = 0; - if (mem->mem_type != TTM_PL_TT || - amdgpu_gtt_mgr_is_allocated(mem)) { + if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) { addr = mm_node->start << PAGE_SHIFT; addr += bo->bdev->man[mem->mem_type].gpu_offset; } @@ -369,7 +368,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, * dst to window 1 */ if (src->mem->mem_type == TTM_PL_TT && - !amdgpu_gtt_mgr_is_allocated(src->mem)) { + !amdgpu_gtt_mgr_has_gart_addr(src->mem)) { r = amdgpu_map_buffer(src->bo, src->mem, PFN_UP(cur_size + src_page_offset), src_node_start, 0, ring, @@ -383,7 +382,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, } if (dst->mem->mem_type == TTM_PL_TT && - !amdgpu_gtt_mgr_is_allocated(dst->mem)) { + !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) { r = amdgpu_map_buffer(dst->bo, dst->mem, PFN_UP(cur_size + dst_page_offset), dst_node_start, 1, ring, @@ -861,8 +860,10 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, bo_mem->mem_type == AMDGPU_PL_OA) return -EINVAL; - if (!amdgpu_gtt_mgr_is_allocated(bo_mem)) + if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { + gtt->offset = AMDGPU_BO_INVALID_OFFSET; return 0; + } spin_lock(>t->adev->gtt_list_lock); flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); @@ -882,23 +883,16 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, return r; } -bool amdgpu_ttm_is_bound(struct ttm_tt *ttm) -{ - struct amdgpu_ttm_tt *gtt = (void *)ttm; - - return gtt && !list_empty(>t->list); -} - int amdgpu_ttm_bind(struct ttm_buffer_object *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); - struct ttm_tt *ttm = bo->ttm; struct ttm_mem_reg tmp; struct ttm_placement placement; struct ttm_place placements; int r; - if (!ttm || amdgpu_ttm_is_bound(ttm)) + if (bo->mem.mem_type != TTM_PL_TT || + amdgpu_gtt_mgr_has_gart_addr(&bo->mem)) return 0; tmp = bo->mem; @@ -959,7 +953,7 @@ static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) if (gtt->userptr) amdgpu_ttm_tt_unpin_userptr(ttm); - if (!amdgpu_ttm_is_bound(ttm)) + if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) return 0; /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 0108a59559cd..016d2af05d34 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -67,7 +67,7 @@ struct amdgpu_copy_mem { extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func; extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func; -bool amdgpu_gtt_mgr_is_allocated(struct ttm_mem_reg *mem); +bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem); uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man); uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man); @@ -90,7 +90,6 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, struct dma_fence **fence); int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); -bool amdgpu_ttm_is_bound(struct ttm_tt *ttm); int amdgpu_ttm_bind(struct ttm_buffer_object *bo); int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); -- GitLab From c1c7ce8f5687bb01b2eb0db3c19cb375267bb16d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 16 Oct 2017 16:50:32 +0200 Subject: [PATCH 0607/2547] drm/amdgpu: move GART recovery into GTT manager v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The GTT manager handles the GART address space anyway, so it is completely pointless to keep the same information around twice. v2: rebased Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 -- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 53 +++++++++++++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 51 ++++++-------------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +- 5 files changed, 59 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index f25d246395a1..d11967a5c392 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1630,9 +1630,6 @@ struct amdgpu_device { /* link all shadow bo */ struct list_head shadow_list; struct mutex shadow_list_lock; - /* link all gtt */ - spinlock_t gtt_list_lock; - struct list_head gtt_list; /* keep an lru list of rings by HW IP */ struct list_head ring_lru_list; spinlock_t ring_lru_list_lock; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 9d4e0b88b101..7af0d5d8cb1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2180,9 +2180,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, INIT_LIST_HEAD(&adev->shadow_list); mutex_init(&adev->shadow_list_lock); - INIT_LIST_HEAD(&adev->gtt_list); - spin_lock_init(&adev->gtt_list_lock); - INIT_LIST_HEAD(&adev->ring_lru_list); spin_lock_init(&adev->ring_lru_list_lock); @@ -2877,7 +2874,8 @@ static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags) atomic_inc(&adev->vram_lost_counter); } - r = amdgpu_ttm_recover_gart(adev); + r = amdgpu_gtt_mgr_recover( + &adev->mman.bdev.man[TTM_PL_TT]); if (r) goto out; @@ -2939,7 +2937,7 @@ static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, goto error; /* we need recover gart prior to run SMC/CP/SDMA resume */ - amdgpu_ttm_recover_gart(adev); + amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]); /* now we are okay to resume SMC/CP/SDMA */ r = amdgpu_sriov_reinit_late(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index f7669dc6909b..e14ab34d8262 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -31,6 +31,11 @@ struct amdgpu_gtt_mgr { atomic64_t available; }; +struct amdgpu_gtt_node { + struct drm_mm_node node; + struct ttm_buffer_object *tbo; +}; + /** * amdgpu_gtt_mgr_init - init GTT manager and DRM MM * @@ -87,9 +92,9 @@ static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man) */ bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem) { - struct drm_mm_node *node = mem->mm_node; + struct amdgpu_gtt_node *node = mem->mm_node; - return (node->start != AMDGPU_BO_INVALID_OFFSET); + return (node->node.start != AMDGPU_BO_INVALID_OFFSET); } /** @@ -109,7 +114,7 @@ static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, { struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev); struct amdgpu_gtt_mgr *mgr = man->priv; - struct drm_mm_node *node = mem->mm_node; + struct amdgpu_gtt_node *node = mem->mm_node; enum drm_mm_insert_mode mode; unsigned long fpfn, lpfn; int r; @@ -132,13 +137,13 @@ static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, mode = DRM_MM_INSERT_HIGH; spin_lock(&mgr->lock); - r = drm_mm_insert_node_in_range(&mgr->mm, node, - mem->num_pages, mem->page_alignment, 0, - fpfn, lpfn, mode); + r = drm_mm_insert_node_in_range(&mgr->mm, &node->node, mem->num_pages, + mem->page_alignment, 0, fpfn, lpfn, + mode); spin_unlock(&mgr->lock); if (!r) - mem->start = node->start; + mem->start = node->node.start; return r; } @@ -159,7 +164,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { struct amdgpu_gtt_mgr *mgr = man->priv; - struct drm_mm_node *node; + struct amdgpu_gtt_node *node; int r; spin_lock(&mgr->lock); @@ -177,8 +182,9 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, goto err_out; } - node->start = AMDGPU_BO_INVALID_OFFSET; - node->size = mem->num_pages; + node->node.start = AMDGPU_BO_INVALID_OFFSET; + node->node.size = mem->num_pages; + node->tbo = tbo; mem->mm_node = node; if (place->fpfn || place->lpfn || place->flags & TTM_PL_FLAG_TOPDOWN) { @@ -190,7 +196,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, goto err_out; } } else { - mem->start = node->start; + mem->start = node->node.start; } return 0; @@ -214,14 +220,14 @@ static void amdgpu_gtt_mgr_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { struct amdgpu_gtt_mgr *mgr = man->priv; - struct drm_mm_node *node = mem->mm_node; + struct amdgpu_gtt_node *node = mem->mm_node; if (!node) return; spin_lock(&mgr->lock); - if (node->start != AMDGPU_BO_INVALID_OFFSET) - drm_mm_remove_node(node); + if (node->node.start != AMDGPU_BO_INVALID_OFFSET) + drm_mm_remove_node(&node->node); spin_unlock(&mgr->lock); atomic64_add(mem->num_pages, &mgr->available); @@ -244,6 +250,25 @@ uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man) return (result > 0 ? result : 0) * PAGE_SIZE; } +int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man) +{ + struct amdgpu_gtt_mgr *mgr = man->priv; + struct amdgpu_gtt_node *node; + struct drm_mm_node *mm_node; + int r = 0; + + spin_lock(&mgr->lock); + drm_mm_for_each_node(mm_node, &mgr->mm) { + node = container_of(mm_node, struct amdgpu_gtt_node, node); + r = amdgpu_ttm_recover_gart(node->tbo); + if (r) + break; + } + spin_unlock(&mgr->lock); + + return r; +} + /** * amdgpu_gtt_mgr_debug - dump VRAM table * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 3d02c2dd06e5..34dbe7afb600 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -689,7 +689,6 @@ struct amdgpu_ttm_tt { struct list_head guptasks; atomic_t mmu_invalidations; uint32_t last_set_pages; - struct list_head list; }; int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages) @@ -865,21 +864,14 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, return 0; } - spin_lock(>t->adev->gtt_list_lock); flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, ttm->pages, gtt->ttm.dma_address, flags); - if (r) { + if (r) DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", ttm->num_pages, gtt->offset); - goto error_gart_bind; - } - - list_add_tail(>t->list, >t->adev->gtt_list); -error_gart_bind: - spin_unlock(>t->adev->gtt_list_lock); return r; } @@ -920,29 +912,23 @@ int amdgpu_ttm_bind(struct ttm_buffer_object *bo) return r; } -int amdgpu_ttm_recover_gart(struct amdgpu_device *adev) +int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) { - struct amdgpu_ttm_tt *gtt, *tmp; - struct ttm_mem_reg bo_mem; + struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); + struct amdgpu_ttm_tt *gtt = (void *)tbo->ttm; uint64_t flags; int r; - bo_mem.mem_type = TTM_PL_TT; - spin_lock(&adev->gtt_list_lock); - list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) { - flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >t->ttm.ttm, &bo_mem); - r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages, - gtt->ttm.ttm.pages, gtt->ttm.dma_address, - flags); - if (r) { - spin_unlock(&adev->gtt_list_lock); - DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", - gtt->ttm.ttm.num_pages, gtt->offset); - return r; - } - } - spin_unlock(&adev->gtt_list_lock); - return 0; + if (!gtt) + return 0; + + flags = amdgpu_ttm_tt_pte_flags(adev, >t->ttm.ttm, &tbo->mem); + r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages, + gtt->ttm.ttm.pages, gtt->ttm.dma_address, flags); + if (r) + DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", + gtt->ttm.ttm.num_pages, gtt->offset); + return r; } static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) @@ -957,16 +943,10 @@ static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) return 0; /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ - spin_lock(>t->adev->gtt_list_lock); r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages); - if (r) { + if (r) DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n", gtt->ttm.ttm.num_pages, gtt->offset); - goto error_unbind; - } - list_del_init(>t->list); -error_unbind: - spin_unlock(>t->adev->gtt_list_lock); return r; } @@ -1003,7 +983,6 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev, kfree(gtt); return NULL; } - INIT_LIST_HEAD(>t->list); return >t->ttm.ttm; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 016d2af05d34..d2985def4168 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -69,6 +69,7 @@ extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func; bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem); uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man); +int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man); uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man); uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man); @@ -91,7 +92,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); int amdgpu_ttm_bind(struct ttm_buffer_object *bo); -int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); +int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); -- GitLab From 8b8f27f972a842a9b8562040c768400fce57ae64 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Wed, 18 Oct 2017 14:31:08 -0400 Subject: [PATCH 0608/2547] drm/amd/display: Fix styling of freesync code in commit_tail For better readability. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Bhawanpreet Lakha Acked-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f4bebdc60351..d7dc6c248630 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4132,7 +4132,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) * are removed from freesync module */ if (adev->dm.freesync_module) { - for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { struct amdgpu_dm_connector *aconnector = NULL; struct dm_connector_state *dm_new_con_state = NULL; struct amdgpu_crtc *acrtc = NULL; @@ -4160,9 +4161,11 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) amdgpu_dm_find_first_crtc_matching_connector( state, crtc); if (!aconnector) { - DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d " - "skipping freesync init\n", - acrtc->crtc_id); + DRM_DEBUG_DRIVER("Atomic commit: Failed to " + "find connector for acrtc " + "id:%d skipping freesync " + "init\n", + acrtc->crtc_id); continue; } -- GitLab From e1fc2dca1295c4ff2de67afe2d9fac07abb0369a Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Wed, 18 Oct 2017 15:32:41 -0400 Subject: [PATCH 0609/2547] drm/amd/display: Complete TODO item: use new DRM iterator Abandon new_crtcs array and use for_each_new iterator to acquire new crtcs. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 36 ++++++++----------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d7dc6c248630..9c5a5f58bfe1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4034,10 +4034,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) struct amdgpu_display_manager *dm = &adev->dm; struct dm_atomic_state *dm_state; uint32_t i, j; - uint32_t new_crtcs_count = 0; struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; - struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; @@ -4096,25 +4094,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) continue; } - if (dm_old_crtc_state->stream) remove_stream(adev, acrtc, dm_old_crtc_state->stream); - - /* - * this loop saves set mode crtcs - * we needed to enable vblanks once all - * resources acquired in dc after dc_commit_streams - */ - - /*TODO move all this into dm_crtc_state, get rid of - * new_crtcs array and use old and new atomic states - * instead - */ - new_crtcs[new_crtcs_count] = acrtc; - new_crtcs_count++; - - new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); acrtc->enabled = true; acrtc->hw_mode = new_crtc_state->mode; crtc->hwmode = new_crtc_state->mode; @@ -4242,18 +4224,28 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) dm_error("%s: Failed to update stream scaling!\n", __func__); } - for (i = 0; i < new_crtcs_count; i++) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { /* * loop to enable interrupts on newly arrived crtc */ - struct amdgpu_crtc *acrtc = new_crtcs[i]; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + bool modeset_needed; - new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); + modeset_needed = modeset_required( + new_crtc_state, + dm_new_crtc_state->stream, + dm_old_crtc_state->stream); + + if (dm_new_crtc_state->stream == NULL || !modeset_needed) + continue; if (adev->dm.freesync_module) mod_freesync_notify_mode_change( - adev->dm.freesync_module, &dm_new_crtc_state->stream, 1); + adev->dm.freesync_module, + &dm_new_crtc_state->stream, 1); manage_dm_interrupts(adev, acrtc, true); } -- GitLab From 62d591a8e00cc349e6a9efb87efac9548f178624 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Wed, 18 Oct 2017 11:59:42 -0400 Subject: [PATCH 0610/2547] drm/amd/display: create new files for hubbub functions moving hubbub functions to new file Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 3 +- .../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 494 ++++++++++++++++++ .../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 67 +++ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 490 +---------------- .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 1 + 5 files changed, 579 insertions(+), 476 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile index ebeb88283a14..a6ca1f97f748 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile @@ -4,7 +4,8 @@ DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \ dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \ dcn10_hubp.o dcn10_mpc.o \ - dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o + dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \ + dcn10_hubbub.o AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10)) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c new file mode 100644 index 000000000000..e6670f6a1b97 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c @@ -0,0 +1,494 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "dcn10_hubp.h" +#include "dcn10_hubbub.h" +#include "dcn10_hw_sequencer.h" +#include "dce110/dce110_hw_sequencer.h" +#include "dce/dce_hwseq.h" +#include "reg_helper.h" + +#define CTX \ + hws->ctx +#define REG(reg)\ + hws->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + hws->shifts->field_name, hws->masks->field_name + +void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws, + struct dcn_hubbub_wm *wm) +{ + struct dcn_hubbub_wm_set *s; + + s = &wm->sets[0]; + s->wm_set = 0; + s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); + s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); + s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); + s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); + s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); + + s = &wm->sets[1]; + s->wm_set = 1; + s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); + s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); + s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); + s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); + s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); + + s = &wm->sets[2]; + s->wm_set = 2; + s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); + s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C); + s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); + s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); + s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); + + s = &wm->sets[3]; + s->wm_set = 3; + s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); + s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D); + s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); + s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); + s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); +} + +void verify_allow_pstate_change_high( + struct dce_hwseq *hws) +{ + /* pstate latency is ~20us so if we wait over 40us and pstate allow + * still not asserted, we are probably stuck and going to hang + * + * TODO: Figure out why it takes ~100us on linux + * pstate takes around ~100us on linux. Unknown currently as to + * why it takes that long on linux + */ + static unsigned int pstate_wait_timeout_us = 200; + static unsigned int pstate_wait_expected_timeout_us = 40; + static unsigned int max_sampled_pstate_wait_us; /* data collection */ + static bool forced_pstate_allow; /* help with revert wa */ + static bool should_log_hw_state; /* prevent hw state log by default */ + + unsigned int debug_index = 0x7; + unsigned int debug_data; + unsigned int i; + + if (forced_pstate_allow) { + /* we hacked to force pstate allow to prevent hang last time + * we verify_allow_pstate_change_high. so disable force + * here so we can check status + */ + REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0, + DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 0); + forced_pstate_allow = false; + } + + /* description "3-0: Pipe0 cursor0 QOS + * 7-4: Pipe1 cursor0 QOS + * 11-8: Pipe2 cursor0 QOS + * 15-12: Pipe3 cursor0 QOS + * 16: Pipe0 Plane0 Allow Pstate Change + * 17: Pipe1 Plane0 Allow Pstate Change + * 18: Pipe2 Plane0 Allow Pstate Change + * 19: Pipe3 Plane0 Allow Pstate Change + * 20: Pipe0 Plane1 Allow Pstate Change + * 21: Pipe1 Plane1 Allow Pstate Change + * 22: Pipe2 Plane1 Allow Pstate Change + * 23: Pipe3 Plane1 Allow Pstate Change + * 24: Pipe0 cursor0 Allow Pstate Change + * 25: Pipe1 cursor0 Allow Pstate Change + * 26: Pipe2 cursor0 Allow Pstate Change + * 27: Pipe3 cursor0 Allow Pstate Change + * 28: WB0 Allow Pstate Change + * 29: WB1 Allow Pstate Change + * 30: Arbiter's allow_pstate_change + * 31: SOC pstate change request + */ + + REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index); + + for (i = 0; i < pstate_wait_timeout_us; i++) { + debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA); + + if (debug_data & (1 << 30)) { + + if (i > pstate_wait_expected_timeout_us) + dm_logger_write(hws->ctx->logger, LOG_WARNING, + "pstate took longer than expected ~%dus\n", + i); + + return; + } + if (max_sampled_pstate_wait_us < i) + max_sampled_pstate_wait_us = i; + + udelay(1); + } + + /* force pstate allow to prevent system hang + * and break to debugger to investigate + */ + REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 1, + DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1); + forced_pstate_allow = true; + + if (should_log_hw_state) { + dcn10_log_hw_state(hws->ctx->dc); + } + + dm_logger_write(hws->ctx->logger, LOG_WARNING, + "pstate TEST_DEBUG_DATA: 0x%X\n", + debug_data); + BREAK_TO_DEBUGGER(); +} + +static uint32_t convert_and_clamp( + uint32_t wm_ns, + uint32_t refclk_mhz, + uint32_t clamp_value) +{ + uint32_t ret_val = 0; + ret_val = wm_ns * refclk_mhz; + ret_val /= 1000; + + if (ret_val > clamp_value) + ret_val = clamp_value; + + return ret_val; +} + + +void program_watermarks( + struct dce_hwseq *hws, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz) +{ + uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0; + /* + * Need to clamp to max of the register values (i.e. no wrap) + * for dcn1, all wm registers are 21-bit wide + */ + uint32_t prog_wm_value; + + REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0); + + /* Repeat for water mark set A, B, C and D. */ + /* clock state A */ + prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); + + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "URGENCY_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.urgent_ns, prog_wm_value); + + prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "PTE_META_URGENCY_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.pte_meta_urgent_ns, prog_wm_value); + + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) { + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_EXIT_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); + } + + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); + + + /* clock state B */ + prog_wm_value = convert_and_clamp( + watermarks->b.urgent_ns, refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "URGENCY_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.urgent_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->b.pte_meta_urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "PTE_META_URGENCY_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.pte_meta_urgent_ns, prog_wm_value); + + + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) { + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_ENTER_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_EXIT_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); + } + + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); + + /* clock state C */ + prog_wm_value = convert_and_clamp( + watermarks->c.urgent_ns, refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "URGENCY_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.urgent_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->c.pte_meta_urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "PTE_META_URGENCY_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.pte_meta_urgent_ns, prog_wm_value); + + + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) { + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_ENTER_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_EXIT_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); + } + + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); + + /* clock state D */ + prog_wm_value = convert_and_clamp( + watermarks->d.urgent_ns, refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "URGENCY_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.urgent_ns, prog_wm_value); + + prog_wm_value = convert_and_clamp( + watermarks->d.pte_meta_urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "PTE_META_URGENCY_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.pte_meta_urgent_ns, prog_wm_value); + + + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) { + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_ENTER_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_EXIT_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); + } + + + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); + + REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); + + REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL, + DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); + REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, + DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68); + + REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0, + DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en); + +#if 0 + REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); +#endif +} + +void dcn10_update_dchub( + struct dce_hwseq *hws, + struct dchub_init_data *dh_data) +{ + /* TODO: port code from dal2 */ + switch (dh_data->fb_mode) { + case FRAME_BUFFER_MODE_ZFB_ONLY: + /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ + REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP, + SDPIF_FB_TOP, 0); + + REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE, + SDPIF_FB_BASE, 0x0FFFF); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, + SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, + SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, + SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1) >> 22); + break; + case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: + /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, + SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, + SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, + SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1) >> 22); + break; + case FRAME_BUFFER_MODE_LOCAL_ONLY: + /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, + SDPIF_AGP_BASE, 0); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, + SDPIF_AGP_BOT, 0X03FFFF); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, + SDPIF_AGP_TOP, 0); + break; + default: + break; + } + + dh_data->dchub_initialzied = true; + dh_data->dchub_info_valid = false; +} + +void toggle_watermark_change_req(struct dce_hwseq *hws) +{ + uint32_t watermark_change_req; + + REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req); + + if (watermark_change_req) + watermark_change_req = 0; + else + watermark_change_req = 1; + + REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); +} + + diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h new file mode 100644 index 000000000000..fe3f787dc158 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h @@ -0,0 +1,67 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HUBBUB_DCN10_H__ +#define __DC_HUBBUB_DCN10_H__ + +#include "core_types.h" + +struct dc; + +struct dcn_hubbub_wm_set { + uint32_t wm_set; + uint32_t data_urgent; + uint32_t pte_meta_urgent; + uint32_t sr_enter; + uint32_t sr_exit; + uint32_t dram_clk_chanage; +}; + +struct dcn_hubbub_wm { + struct dcn_hubbub_wm_set sets[4]; +}; + +void dcn10_update_dchub( + struct dce_hwseq *hws, + struct dchub_init_data *dh_data); + +void dcn10_log_hw_state( + struct dc *dc); + +void verify_allow_pstate_change_high( + struct dce_hwseq *hws); + +void program_watermarks( + struct dce_hwseq *hws, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz); + +void toggle_watermark_change_req( + struct dce_hwseq *hws); + +void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws, + struct dcn_hubbub_wm *wm); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index cd9e5484738d..8d554e63dc7a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -42,6 +42,7 @@ #include "reg_helper.h" #include "custom_float.h" #include "dcn10_hubp.h" +#include "dcn10_hubbub.h" #define CTX \ hws->ctx @@ -52,18 +53,8 @@ #define FN(reg_name, field_name) \ hws->shifts->field_name, hws->masks->field_name -static void log_mpc_crc(struct dc *dc) -{ - struct dc_context *dc_ctx = dc->ctx; - struct dce_hwseq *hws = dc->hwseq; - - if (REG(MPC_CRC_RESULT_GB)) - DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n", - REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR)); - if (REG(DPP_TOP0_DPP_CRC_VAL_B_A)) - DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n", - REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G)); -} +#define DTN_INFO_MICRO_SEC(ref_cycle) \ + print_microsec(dc_ctx, ref_cycle) void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle) { @@ -76,61 +67,21 @@ void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle) us_x10 % frac); } -#define DTN_INFO_MICRO_SEC(ref_cycle) \ - print_microsec(dc_ctx, ref_cycle) - -struct dcn_hubbub_wm_set { - uint32_t wm_set; - uint32_t data_urgent; - uint32_t pte_meta_urgent; - uint32_t sr_enter; - uint32_t sr_exit; - uint32_t dram_clk_chanage; -}; -struct dcn_hubbub_wm { - struct dcn_hubbub_wm_set sets[4]; -}; - -static void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws, - struct dcn_hubbub_wm *wm) +static void log_mpc_crc(struct dc *dc) { - struct dcn_hubbub_wm_set *s; - - s = &wm->sets[0]; - s->wm_set = 0; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); - - s = &wm->sets[1]; - s->wm_set = 1; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); - - s = &wm->sets[2]; - s->wm_set = 2; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C); - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); - - s = &wm->sets[3]; - s->wm_set = 3; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D); - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); + struct dc_context *dc_ctx = dc->ctx; + struct dce_hwseq *hws = dc->hwseq; + + if (REG(MPC_CRC_RESULT_GB)) + DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n", + REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR)); + if (REG(DPP_TOP0_DPP_CRC_VAL_B_A)) + DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n", + REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G)); } -static void dcn10_log_hubbub_state(struct dc *dc) +void dcn10_log_hubbub_state(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct dcn_hubbub_wm wm; @@ -157,7 +108,7 @@ static void dcn10_log_hubbub_state(struct dc *dc) DTN_INFO("\n"); } -static void dcn10_log_hw_state(struct dc *dc) +void dcn10_log_hw_state(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; @@ -241,97 +192,6 @@ static void dcn10_log_hw_state(struct dc *dc) DTN_INFO_END(); } -static void verify_allow_pstate_change_high( - struct dce_hwseq *hws) -{ - /* pstate latency is ~20us so if we wait over 40us and pstate allow - * still not asserted, we are probably stuck and going to hang - * - * TODO: Figure out why it takes ~100us on linux - * pstate takes around ~100us on linux. Unknown currently as to - * why it takes that long on linux - */ - static unsigned int pstate_wait_timeout_us = 200; - static unsigned int pstate_wait_expected_timeout_us = 40; - static unsigned int max_sampled_pstate_wait_us; /* data collection */ - static bool forced_pstate_allow; /* help with revert wa */ - static bool should_log_hw_state; /* prevent hw state log by default */ - - unsigned int debug_index = 0x7; - unsigned int debug_data; - unsigned int i; - - if (forced_pstate_allow) { - /* we hacked to force pstate allow to prevent hang last time - * we verify_allow_pstate_change_high. so disable force - * here so we can check status - */ - REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 0); - forced_pstate_allow = false; - } - - /* description "3-0: Pipe0 cursor0 QOS - * 7-4: Pipe1 cursor0 QOS - * 11-8: Pipe2 cursor0 QOS - * 15-12: Pipe3 cursor0 QOS - * 16: Pipe0 Plane0 Allow Pstate Change - * 17: Pipe1 Plane0 Allow Pstate Change - * 18: Pipe2 Plane0 Allow Pstate Change - * 19: Pipe3 Plane0 Allow Pstate Change - * 20: Pipe0 Plane1 Allow Pstate Change - * 21: Pipe1 Plane1 Allow Pstate Change - * 22: Pipe2 Plane1 Allow Pstate Change - * 23: Pipe3 Plane1 Allow Pstate Change - * 24: Pipe0 cursor0 Allow Pstate Change - * 25: Pipe1 cursor0 Allow Pstate Change - * 26: Pipe2 cursor0 Allow Pstate Change - * 27: Pipe3 cursor0 Allow Pstate Change - * 28: WB0 Allow Pstate Change - * 29: WB1 Allow Pstate Change - * 30: Arbiter's allow_pstate_change - * 31: SOC pstate change request - */ - - REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index); - - for (i = 0; i < pstate_wait_timeout_us; i++) { - debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA); - - if (debug_data & (1 << 30)) { - - if (i > pstate_wait_expected_timeout_us) - dm_logger_write(hws->ctx->logger, LOG_WARNING, - "pstate took longer than expected ~%dus\n", - i); - - return; - } - if (max_sampled_pstate_wait_us < i) - max_sampled_pstate_wait_us = i; - - udelay(1); - } - - /* force pstate allow to prevent system hang - * and break to debugger to investigate - */ - REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 1, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1); - forced_pstate_allow = true; - - if (should_log_hw_state) { - dcn10_log_hw_state(hws->ctx->dc); - } - - dm_logger_write(hws->ctx->logger, LOG_WARNING, - "pstate TEST_DEBUG_DATA: 0x%X\n", - debug_data); - BREAK_TO_DEBUGGER(); -} - static void enable_dppclk( struct dce_hwseq *hws, uint8_t plane_id, @@ -433,312 +293,6 @@ static void dpp_pg_control( } } -static uint32_t convert_and_clamp( - uint32_t wm_ns, - uint32_t refclk_mhz, - uint32_t clamp_value) -{ - uint32_t ret_val = 0; - ret_val = wm_ns * refclk_mhz; - ret_val /= 1000; - - if (ret_val > clamp_value) - ret_val = clamp_value; - - return ret_val; -} - -static void program_watermarks( - struct dce_hwseq *hws, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz) -{ - uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0; - /* - * Need to clamp to max of the register values (i.e. no wrap) - * for dcn1, all wm registers are 21-bit wide - */ - uint32_t prog_wm_value; - - REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0); - - /* Repeat for water mark set A, B, C and D. */ - /* clock state A */ - prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); - - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "URGENCY_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.urgent_ns, prog_wm_value); - - prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "PTE_META_URGENCY_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.pte_meta_urgent_ns, prog_wm_value); - - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) { - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_EXIT_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); - } - - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); - - - /* clock state B */ - prog_wm_value = convert_and_clamp( - watermarks->b.urgent_ns, refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "URGENCY_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.urgent_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->b.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "PTE_META_URGENCY_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.pte_meta_urgent_ns, prog_wm_value); - - - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) { - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_ENTER_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_EXIT_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); - } - - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); - - /* clock state C */ - prog_wm_value = convert_and_clamp( - watermarks->c.urgent_ns, refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "URGENCY_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.urgent_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->c.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "PTE_META_URGENCY_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.pte_meta_urgent_ns, prog_wm_value); - - - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) { - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_ENTER_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_EXIT_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); - } - - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); - - /* clock state D */ - prog_wm_value = convert_and_clamp( - watermarks->d.urgent_ns, refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "URGENCY_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.urgent_ns, prog_wm_value); - - prog_wm_value = convert_and_clamp( - watermarks->d.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "PTE_META_URGENCY_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.pte_meta_urgent_ns, prog_wm_value); - - - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) { - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_ENTER_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_EXIT_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); - } - - - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); - - REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); - - REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL, - DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); - REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, - DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68); - - REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0, - DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en); - -#if 0 - REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); -#endif -} - - -static void dcn10_update_dchub( - struct dce_hwseq *hws, - struct dchub_init_data *dh_data) -{ - /* TODO: port code from dal2 */ - switch (dh_data->fb_mode) { - case FRAME_BUFFER_MODE_ZFB_ONLY: - /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ - REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP, - SDPIF_FB_TOP, 0); - - REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE, - SDPIF_FB_BASE, 0x0FFFF); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 22); - break; - case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 22); - break; - case FRAME_BUFFER_MODE_LOCAL_ONLY: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, 0); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, 0X03FFFF); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, 0); - break; - default: - break; - } - - dh_data->dchub_initialzied = true; - dh_data->dchub_info_valid = false; -} - static void hubp_pg_control( struct dce_hwseq *hws, unsigned int hubp_inst, @@ -1337,21 +891,7 @@ static bool patch_address_for_sbs_tb_stereo( return false; } -static void toggle_watermark_change_req(struct dce_hwseq *hws) -{ - uint32_t watermark_change_req; - - REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req); - if (watermark_change_req) - watermark_change_req = 0; - else - watermark_change_req = 1; - - REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); -} static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index ca53dc1cc19b..b9d326082717 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -35,4 +35,5 @@ extern void fill_display_configs( const struct dc_state *context, struct dm_pp_display_configuration *pp_display_cfg); + #endif /* __DC_HWSS_DCN10_H__ */ -- GitLab From 00893681a0ff41cacecabc3dafe0987593a3d5c5 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Thu, 19 Oct 2017 14:43:36 -0400 Subject: [PATCH 0611/2547] drm/amd/display: Reject PPLib clock values if they are invalid We should be sticking with the default clock values if the values obtained from PPLib are bogus. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 68 ++++++++++++------- 1 file changed, 45 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 3dce35e66b09..6d64a069648e 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -1231,40 +1231,62 @@ unsigned int dcn_find_dcfclk_suits_all( return dcf_clk; } +static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) +{ + int i; + + if (clks->num_levels == 0) + return false; + + for (i = 0; i < clks->num_levels; i++) + /* Ensure that the result is sane */ + if (clks->data[i].clocks_in_khz == 0) + return false; + + return true; +} + void dcn_bw_update_from_pplib(struct dc *dc) { struct dc_context *ctx = dc->ctx; - struct dm_pp_clock_levels_with_voltage clks = {0}; + struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0}; + bool res; kernel_fpu_begin(); /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */ - - if (dm_pp_get_clock_levels_by_type_with_voltage( - ctx, DM_PP_CLOCK_TYPE_FCLK, &clks) && - clks.num_levels != 0) { - ASSERT(clks.num_levels >= 3); - dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (clks.data[0].clocks_in_khz / 1000.0) / 1000.0; - if (clks.num_levels > 2) { - dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels * - (clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; - } else { - dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels * - (clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; - } + res = dm_pp_get_clock_levels_by_type_with_voltage( + ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks); + + if (res) + res = verify_clock_values(&fclks); + + if (res) { + ASSERT(fclks.num_levels >= 3); + dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0; + dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels * + (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0) + * ddr4_dram_factor_single_Channel / 1000.0; dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels * - (clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; + (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0) + * ddr4_dram_factor_single_Channel / 1000.0; dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels * - (clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; + (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0) + * ddr4_dram_factor_single_Channel / 1000.0; } else BREAK_TO_DEBUGGER(); - if (dm_pp_get_clock_levels_by_type_with_voltage( - ctx, DM_PP_CLOCK_TYPE_DCFCLK, &clks) && - clks.num_levels >= 3) { - dc->dcn_soc->dcfclkv_min0p65 = clks.data[0].clocks_in_khz / 1000.0; - dc->dcn_soc->dcfclkv_mid0p72 = clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0; - dc->dcn_soc->dcfclkv_nom0p8 = clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0; - dc->dcn_soc->dcfclkv_max0p9 = clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0; + + res = dm_pp_get_clock_levels_by_type_with_voltage( + ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks); + + if (res) + res = verify_clock_values(&dcfclks); + + if (res && dcfclks.num_levels >= 3) { + dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0; + dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0; + dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0; + dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0; } else BREAK_TO_DEBUGGER(); -- GitLab From 7a5086a71e8228a91ed5e8c7ae73e64799b12b66 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Fri, 20 Oct 2017 14:12:35 -0400 Subject: [PATCH 0612/2547] drm/amd/display: Power down front end in init_hw. front end is initialized during init_hw, but not power gated. There are some left over valuse and will cause some diags test failed. Power gated all front end pipes will make sure every test has same starting point. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 172 +++++++++--------- 1 file changed, 87 insertions(+), 85 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 8d554e63dc7a..3891e9118485 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -414,91 +414,6 @@ static void bios_golden_init(struct dc *dc) } } -static void dcn10_init_hw(struct dc *dc) -{ - int i; - struct abm *abm = dc->res_pool->abm; - struct dmcu *dmcu = dc->res_pool->dmcu; - struct dce_hwseq *hws = dc->hwseq; - - if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { - REG_WRITE(REFCLK_CNTL, 0); - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); - REG_WRITE(DIO_MEM_PWR_CTRL, 0); - - if (!dc->debug.disable_clock_gate) { - /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); - - REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); - } - - enable_power_gating_plane(dc->hwseq, true); - return; - } - /* end of FPGA. Below if real ASIC */ - - bios_golden_init(dc); - - disable_vga(dc->hwseq); - - for (i = 0; i < dc->link_count; i++) { - /* Power up AND update implementation according to the - * required signal (which may be different from the - * default signal on connector). - */ - struct dc_link *link = dc->links[i]; - - link->link_enc->funcs->hw_init(link->link_enc); - } - - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct dpp *dpp = dc->res_pool->dpps[i]; - struct timing_generator *tg = dc->res_pool->timing_generators[i]; - - dpp->funcs->dpp_reset(dpp); - dc->res_pool->mpc->funcs->remove( - dc->res_pool->mpc, &(dc->res_pool->opps[i]->mpc_tree), - dc->res_pool->opps[i]->inst, i); - - /* Blank controller using driver code instead of - * command table. - */ - tg->funcs->set_blank(tg, true); - hwss_wait_for_blank_complete(tg); - } - - for (i = 0; i < dc->res_pool->audio_count; i++) { - struct audio *audio = dc->res_pool->audios[i]; - - audio->funcs->hw_init(audio); - } - - if (abm != NULL) { - abm->funcs->init_backlight(abm); - abm->funcs->abm_init(abm); - } - - if (dmcu != NULL) - dmcu->funcs->dmcu_init(dmcu); - - /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); - - if (!dc->debug.disable_clock_gate) { - /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); - - REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); - } - - enable_power_gating_plane(dc->hwseq, true); -} - static enum dc_status dcn10_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, struct dc_state *context, @@ -784,6 +699,93 @@ static void dcn10_power_down_fe(struct dc *dc, int fe_idx) verify_allow_pstate_change_high(dc->hwseq); } +static void dcn10_init_hw(struct dc *dc) +{ + int i; + struct abm *abm = dc->res_pool->abm; + struct dmcu *dmcu = dc->res_pool->dmcu; + struct dce_hwseq *hws = dc->hwseq; + + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + REG_WRITE(REFCLK_CNTL, 0); + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); + REG_WRITE(DIO_MEM_PWR_CTRL, 0); + + if (!dc->debug.disable_clock_gate) { + /* enable all DCN clock gating */ + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + + REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); + } + + enable_power_gating_plane(dc->hwseq, true); + return; + } + /* end of FPGA. Below if real ASIC */ + + bios_golden_init(dc); + + disable_vga(dc->hwseq); + + for (i = 0; i < dc->link_count; i++) { + /* Power up AND update implementation according to the + * required signal (which may be different from the + * default signal on connector). + */ + struct dc_link *link = dc->links[i]; + + link->link_enc->funcs->hw_init(link->link_enc); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct dpp *dpp = dc->res_pool->dpps[i]; + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + + dpp->funcs->dpp_reset(dpp); + dc->res_pool->mpc->funcs->remove( + dc->res_pool->mpc, &(dc->res_pool->opps[i]->mpc_tree), + dc->res_pool->opps[i]->inst, i); + + /* Blank controller using driver code instead of + * command table. + */ + tg->funcs->set_blank(tg, true); + hwss_wait_for_blank_complete(tg); + + dcn10_power_down_fe(dc, i); + } + + for (i = 0; i < dc->res_pool->audio_count; i++) { + struct audio *audio = dc->res_pool->audios[i]; + + audio->funcs->hw_init(audio); + } + + if (abm != NULL) { + abm->funcs->init_backlight(abm); + abm->funcs->abm_init(abm); + } + + if (dmcu != NULL) + dmcu->funcs->dmcu_init(dmcu); + + /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ + REG_WRITE(DIO_MEM_PWR_CTRL, 0); + + if (!dc->debug.disable_clock_gate) { + /* enable all DCN clock gating */ + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + + REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); + } + + enable_power_gating_plane(dc->hwseq, true); +} + static void reset_hw_ctx_wrap( struct dc *dc, struct dc_state *context) -- GitLab From 74707de3365a0ab1244e0253842e5b10d32c4a01 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 17 Oct 2017 14:24:28 -0400 Subject: [PATCH 0613/2547] drm/amd/display: Not reset front end when program back end. Since front end is programmed before back end programming, no need to reset front end in back end programming. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 76 ------------------- 2 files changed, 2 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 9925d0e01c04..c874dfd099d3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -850,6 +850,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c if (!dcb->funcs->is_accelerated_mode(dcb)) dc->hwss.enable_accelerated_mode(dc); + + for (i = 0; i < context->stream_count; i++) { const struct dc_sink *sink = context->streams[i]->sink; @@ -928,7 +930,6 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context) return (result == DC_OK); } - bool dc_post_update_surfaces_to_stream(struct dc *dc) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 3891e9118485..f7434ae4aec2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -617,32 +617,6 @@ static void plane_atomic_disable(struct dc *dc, verify_allow_pstate_change_high(dc->hwseq); } -/* - * kill power to plane hw - * note: cannot power down until plane is disable - */ -static void plane_atomic_power_down(struct dc *dc, int fe_idx) -{ - struct dce_hwseq *hws = dc->hwseq; - struct dpp *dpp = dc->res_pool->dpps[fe_idx]; - - if (REG(DC_IP_REQUEST_CNTL)) { - REG_SET(DC_IP_REQUEST_CNTL, 0, - IP_REQUEST_EN, 1); - dpp_pg_control(hws, fe_idx, false); - hubp_pg_control(hws, fe_idx, false); - dpp->funcs->dpp_reset(dpp); - REG_SET(DC_IP_REQUEST_CNTL, 0, - IP_REQUEST_EN, 0); - dm_logger_write(dc->ctx->logger, LOG_DEBUG, - "Power gated front end %d\n", fe_idx); - - if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - } -} - - static void reset_front_end( struct dc *dc, int fe_idx) @@ -792,56 +766,6 @@ static void reset_hw_ctx_wrap( { int i; - /* Reset Front End*/ - /* Lock*/ - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; - - if (cur_pipe_ctx->stream) - tg->funcs->lock(tg); - } - /* Disconnect*/ - for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { - struct pipe_ctx *pipe_ctx_old = - &dc->current_state->res_ctx.pipe_ctx[i]; - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - - if (!pipe_ctx->stream || - !pipe_ctx->plane_state || - pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { - - plane_atomic_disconnect(dc, i); - } - } - /* Unlock*/ - for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { - struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; - - if (cur_pipe_ctx->stream) - tg->funcs->unlock(tg); - } - - /* Disable and Powerdown*/ - for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { - struct pipe_ctx *pipe_ctx_old = - &dc->current_state->res_ctx.pipe_ctx[i]; - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - - /*if (!pipe_ctx_old->stream) - continue;*/ - - if (pipe_ctx->stream && pipe_ctx->plane_state - && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) - continue; - - plane_atomic_disable(dc, i); - - if (!pipe_ctx->stream || !pipe_ctx->plane_state) - plane_atomic_power_down(dc, i); - } - /* Reset Back End*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = -- GitLab From d75aee4bbfc4924417c3428c13490cde11a65a18 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Fri, 20 Oct 2017 14:27:47 -0400 Subject: [PATCH 0614/2547] drm/amd/display: dal 3.1.08 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9ca838b3c4d7..32d71ef20c67 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.07" +#define DC_VER "3.1.08" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From 1dbac201be8c48806aaad074475e2e6ba07f35b2 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Sat, 21 Oct 2017 15:52:40 -0400 Subject: [PATCH 0615/2547] drm/amd/display: Added disconnect dchub. Add disable ttu interface to dcn10, when remove mpc, disable ttu as well. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 9 +++++++++ .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 ++++ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 2 ++ 3 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c index a19fac70b056..584e82cc5df3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -56,6 +56,14 @@ void hubp1_set_blank(struct hubp *hubp, bool blank) } } +static void hubp1_disconnect(struct hubp *hubp) +{ + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); + + REG_UPDATE(DCHUBP_CNTL, + HUBP_TTU_DISABLE, 1); +} + static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); @@ -933,6 +941,7 @@ static struct hubp_funcs dcn10_hubp_funcs = { .set_hubp_blank_en = hubp1_set_hubp_blank_en, .set_cursor_attributes = hubp1_cursor_set_attributes, .set_cursor_position = hubp1_cursor_set_position, + .hubp_disconnect = hubp1_disconnect, }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index f7434ae4aec2..b3e587f273e8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2019,6 +2019,7 @@ static void dcn10_apply_ctx_for_surface( struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + struct hubp *hubp = dc->res_pool->hubps[i]; if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) continue; @@ -2067,6 +2068,9 @@ static void dcn10_apply_ctx_for_surface( "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", old_pipe_ctx->mpcc->inst);*/ + if (hubp->funcs->hubp_disconnect) + hubp->funcs->hubp_disconnect(hubp); + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 0d186be24cf4..3286585bd6cd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -100,6 +100,8 @@ struct hubp_funcs { const struct dc_cursor_position *pos, const struct dc_cursor_mi_param *param); + void (*hubp_disconnect)(struct hubp *hubp); + }; #endif -- GitLab From bcb40a670fbc28f4191e72afcff4c552274d815f Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Sat, 21 Oct 2017 18:32:15 -0400 Subject: [PATCH 0616/2547] drm/amd/display: dal 3.1.09 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 32d71ef20c67..45874fa888fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.08" +#define DC_VER "3.1.09" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From c9ef081df08d0ad5bae7f6fb9d7d63422b109b62 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Mon, 23 Oct 2017 16:01:36 -0400 Subject: [PATCH 0617/2547] drm/amd/display: create new structure for hubbub instantiating new structure hubbub in resource.c Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 88 ++++++---- .../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 162 +++++++++++++++++- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 45 +++-- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 38 ++++ .../gpu/drm/amd/display/dc/inc/core_types.h | 1 + 5 files changed, 269 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c index e6670f6a1b97..f60e90cff1bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c @@ -26,21 +26,18 @@ #include "dm_services.h" #include "dcn10_hubp.h" #include "dcn10_hubbub.h" -#include "dcn10_hw_sequencer.h" -#include "dce110/dce110_hw_sequencer.h" -#include "dce/dce_hwseq.h" #include "reg_helper.h" #define CTX \ - hws->ctx + hubbub->ctx #define REG(reg)\ - hws->regs->reg + hubbub->regs->reg #undef FN #define FN(reg_name, field_name) \ - hws->shifts->field_name, hws->masks->field_name + hubbub->shifts->field_name, hubbub->masks->field_name -void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws, +void hubbub1_wm_read_state(struct hubbub *hubbub, struct dcn_hubbub_wm *wm) { struct dcn_hubbub_wm_set *s; @@ -79,7 +76,7 @@ void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws, } void verify_allow_pstate_change_high( - struct dce_hwseq *hws) + struct hubbub *hubbub) { /* pstate latency is ~20us so if we wait over 40us and pstate allow * still not asserted, we are probably stuck and going to hang @@ -139,7 +136,7 @@ void verify_allow_pstate_change_high( if (debug_data & (1 << 30)) { if (i > pstate_wait_expected_timeout_us) - dm_logger_write(hws->ctx->logger, LOG_WARNING, + dm_logger_write(hubbub->ctx->logger, LOG_WARNING, "pstate took longer than expected ~%dus\n", i); @@ -160,10 +157,10 @@ void verify_allow_pstate_change_high( forced_pstate_allow = true; if (should_log_hw_state) { - dcn10_log_hw_state(hws->ctx->dc); + dcn10_log_hw_state(hubbub->ctx->dc); } - dm_logger_write(hws->ctx->logger, LOG_WARNING, + dm_logger_write(hubbub->ctx->logger, LOG_WARNING, "pstate TEST_DEBUG_DATA: 0x%X\n", debug_data); BREAK_TO_DEBUGGER(); @@ -186,11 +183,11 @@ static uint32_t convert_and_clamp( void program_watermarks( - struct dce_hwseq *hws, + struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz) { - uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0; + uint32_t force_en = hubbub->ctx->dc->debug.disable_stutter ? 1 : 0; /* * Need to clamp to max of the register values (i.e. no wrap) * for dcn1, all wm registers are 21-bit wide @@ -206,7 +203,7 @@ void program_watermarks( refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "URGENCY_WATERMARK_A calculated =%d\n" "HW register value = 0x%x\n", watermarks->a.urgent_ns, prog_wm_value); @@ -214,7 +211,7 @@ void program_watermarks( prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "PTE_META_URGENCY_WATERMARK_A calculated =%d\n" "HW register value = 0x%x\n", watermarks->a.pte_meta_urgent_ns, prog_wm_value); @@ -224,7 +221,7 @@ void program_watermarks( watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" "HW register value = 0x%x\n", watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); @@ -234,7 +231,7 @@ void program_watermarks( watermarks->a.cstate_pstate.cstate_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_EXIT_WATERMARK_A calculated =%d\n" "HW register value = 0x%x\n", watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); @@ -244,7 +241,7 @@ void program_watermarks( watermarks->a.cstate_pstate.pstate_change_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" "HW register value = 0x%x\n\n", watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); @@ -254,7 +251,7 @@ void program_watermarks( prog_wm_value = convert_and_clamp( watermarks->b.urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "URGENCY_WATERMARK_B calculated =%d\n" "HW register value = 0x%x\n", watermarks->b.urgent_ns, prog_wm_value); @@ -264,7 +261,7 @@ void program_watermarks( watermarks->b.pte_meta_urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "PTE_META_URGENCY_WATERMARK_B calculated =%d\n" "HW register value = 0x%x\n", watermarks->b.pte_meta_urgent_ns, prog_wm_value); @@ -275,7 +272,7 @@ void program_watermarks( watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_ENTER_WATERMARK_B calculated =%d\n" "HW register value = 0x%x\n", watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); @@ -285,7 +282,7 @@ void program_watermarks( watermarks->b.cstate_pstate.cstate_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_EXIT_WATERMARK_B calculated =%d\n" "HW register value = 0x%x\n", watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); @@ -295,7 +292,7 @@ void program_watermarks( watermarks->b.cstate_pstate.pstate_change_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n" "HW register value = 0x%x\n", watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); @@ -304,7 +301,7 @@ void program_watermarks( prog_wm_value = convert_and_clamp( watermarks->c.urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "URGENCY_WATERMARK_C calculated =%d\n" "HW register value = 0x%x\n", watermarks->c.urgent_ns, prog_wm_value); @@ -314,7 +311,7 @@ void program_watermarks( watermarks->c.pte_meta_urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "PTE_META_URGENCY_WATERMARK_C calculated =%d\n" "HW register value = 0x%x\n", watermarks->c.pte_meta_urgent_ns, prog_wm_value); @@ -325,7 +322,7 @@ void program_watermarks( watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_ENTER_WATERMARK_C calculated =%d\n" "HW register value = 0x%x\n", watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); @@ -335,7 +332,7 @@ void program_watermarks( watermarks->c.cstate_pstate.cstate_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_EXIT_WATERMARK_C calculated =%d\n" "HW register value = 0x%x\n", watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); @@ -345,7 +342,7 @@ void program_watermarks( watermarks->c.cstate_pstate.pstate_change_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n" "HW register value = 0x%x\n", watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); @@ -354,7 +351,7 @@ void program_watermarks( prog_wm_value = convert_and_clamp( watermarks->d.urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "URGENCY_WATERMARK_D calculated =%d\n" "HW register value = 0x%x\n", watermarks->d.urgent_ns, prog_wm_value); @@ -363,7 +360,7 @@ void program_watermarks( watermarks->d.pte_meta_urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "PTE_META_URGENCY_WATERMARK_D calculated =%d\n" "HW register value = 0x%x\n", watermarks->d.pte_meta_urgent_ns, prog_wm_value); @@ -374,7 +371,7 @@ void program_watermarks( watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_ENTER_WATERMARK_D calculated =%d\n" "HW register value = 0x%x\n", watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); @@ -384,7 +381,7 @@ void program_watermarks( watermarks->d.cstate_pstate.cstate_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_EXIT_WATERMARK_D calculated =%d\n" "HW register value = 0x%x\n", watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); @@ -395,7 +392,7 @@ void program_watermarks( watermarks->d.cstate_pstate.pstate_change_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" "HW register value = 0x%x\n\n", watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); @@ -419,8 +416,8 @@ void program_watermarks( #endif } -void dcn10_update_dchub( - struct dce_hwseq *hws, +void hubbub1_update_dchub( + struct hubbub *hubbub, struct dchub_init_data *dh_data) { /* TODO: port code from dal2 */ @@ -475,7 +472,7 @@ void dcn10_update_dchub( dh_data->dchub_info_valid = false; } -void toggle_watermark_change_req(struct dce_hwseq *hws) +void toggle_watermark_change_req(struct hubbub *hubbub) { uint32_t watermark_change_req; @@ -491,4 +488,23 @@ void toggle_watermark_change_req(struct dce_hwseq *hws) DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); } +static const struct hubbub_funcs hubbub1_funcs = { + .update_dchub = hubbub1_update_dchub +}; + +void hubbub1_construct(struct hubbub *hubbub, + struct dc_context *ctx, + const struct dcn_hubbub_registers *hubbub_regs, + const struct dcn_hubbub_shift *hubbub_shift, + const struct dcn_hubbub_mask *hubbub_mask) +{ + hubbub->ctx = ctx; + + hubbub->funcs = &hubbub1_funcs; + + hubbub->regs = hubbub_regs; + hubbub->shifts = hubbub_shift; + hubbub->masks = hubbub_mask; + +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h index fe3f787dc158..e9abb881bd3f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h @@ -28,6 +28,136 @@ #include "core_types.h" +#define HUBHUB_REG_LIST_DCN()\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ + SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ + SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ + SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ + SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\ + SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\ + SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ + SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ + SR(DCHUBBUB_ARB_SAT_LEVEL),\ + SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ + SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DCHUBBUB_TEST_DEBUG_INDEX), \ + SR(DCHUBBUB_TEST_DEBUG_DATA) + +#define HUBBUB_SR_WATERMARK_REG_LIST()\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D) + +#define HUBBUB_REG_LIST_DCN10(id)\ + HUBHUB_REG_LIST_DCN(), \ + HUBBUB_SR_WATERMARK_REG_LIST(), \ + SR(DCHUBBUB_SDPIF_FB_TOP),\ + SR(DCHUBBUB_SDPIF_FB_BASE),\ + SR(DCHUBBUB_SDPIF_FB_OFFSET),\ + SR(DCHUBBUB_SDPIF_AGP_BASE),\ + SR(DCHUBBUB_SDPIF_AGP_BOT),\ + SR(DCHUBBUB_SDPIF_AGP_TOP) + +struct dcn_hubbub_registers { + uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A; + uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A; + uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A; + uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B; + uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B; + uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B; + uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C; + uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C; + uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C; + uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D; + uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D; + uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D; + uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL; + uint32_t DCHUBBUB_ARB_SAT_LEVEL; + uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND; + uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; + uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL; + uint32_t DCHUBBUB_TEST_DEBUG_INDEX; + uint32_t DCHUBBUB_TEST_DEBUG_DATA; + uint32_t DCHUBBUB_SDPIF_FB_TOP; + uint32_t DCHUBBUB_SDPIF_FB_BASE; + uint32_t DCHUBBUB_SDPIF_FB_OFFSET; + uint32_t DCHUBBUB_SDPIF_AGP_BASE; + uint32_t DCHUBBUB_SDPIF_AGP_BOT; + uint32_t DCHUBBUB_SDPIF_AGP_TOP; + uint32_t DCHUBBUB_CRC_CTRL; +}; + +/* set field name */ +#define HUBBUB_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + + +#define HUBBUB_MASK_SH_LIST_DCN(mask_sh)\ + HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh) + +#define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\ + HUBBUB_MASK_SH_LIST_DCN(mask_sh), \ + HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh) + +#define DCN_HUBBUB_REG_FIELD_LIST(type) \ + type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ + type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\ + type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\ + type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\ + type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\ + type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\ + type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\ + type DCHUBBUB_ARB_SAT_LEVEL;\ + type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\ + type DCHUBBUB_GLOBAL_TIMER_REFDIV;\ + type SDPIF_FB_TOP;\ + type SDPIF_FB_BASE;\ + type SDPIF_FB_OFFSET;\ + type SDPIF_AGP_BASE;\ + type SDPIF_AGP_BOT;\ + type SDPIF_AGP_TOP + + +struct dcn_hubbub_shift { + DCN_HUBBUB_REG_FIELD_LIST(uint8_t); +}; + +struct dcn_hubbub_mask { + DCN_HUBBUB_REG_FIELD_LIST(uint32_t); +}; + struct dc; struct dcn_hubbub_wm_set { @@ -43,25 +173,45 @@ struct dcn_hubbub_wm { struct dcn_hubbub_wm_set sets[4]; }; -void dcn10_update_dchub( - struct dce_hwseq *hws, +struct hubbub_funcs { + void (*update_dchub)( + struct hubbub *hubbub, + struct dchub_init_data *dh_data); +}; + +struct hubbub { + const struct hubbub_funcs *funcs; + struct dc_context *ctx; + const struct dcn_hubbub_registers *regs; + const struct dcn_hubbub_shift *shifts; + const struct dcn_hubbub_mask *masks; +}; + +void hubbub1_update_dchub( + struct hubbub *hubbub, struct dchub_init_data *dh_data); void dcn10_log_hw_state( struct dc *dc); void verify_allow_pstate_change_high( - struct dce_hwseq *hws); + struct hubbub *hubbub); void program_watermarks( - struct dce_hwseq *hws, + struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz); void toggle_watermark_change_req( - struct dce_hwseq *hws); + struct hubbub *hubbub); -void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws, +void hubbub1_wm_read_state(struct hubbub *hubbub, struct dcn_hubbub_wm *wm); +void hubbub1_construct(struct hubbub *hubbub, + struct dc_context *ctx, + const struct dcn_hubbub_registers *hubbub_regs, + const struct dcn_hubbub_shift *hubbub_shift, + const struct dcn_hubbub_mask *hubbub_mask); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index b3e587f273e8..163b40dad3f3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -87,7 +87,7 @@ void dcn10_log_hubbub_state(struct dc *dc) struct dcn_hubbub_wm wm; int i; - dcn10_hubbub_wm_read_state(dc->hwseq, &wm); + hubbub1_wm_read_state(dc->res_pool->hubbub, &wm); DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t " "sr_enter \t sr_exit \t dram_clk_change \n"); @@ -571,10 +571,10 @@ static void plane_atomic_disconnect(struct dc *dc, return; if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); hubp->funcs->dcc_control(hubp, false, false); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree), dc->res_pool->opps[opp_id]->inst, fe_idx); @@ -602,7 +602,7 @@ static void plane_atomic_disable(struct dc *dc, hubp->funcs->set_blank(hubp, true); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); REG_UPDATE(HUBP_CLK_CNTL[fe_idx], HUBP_CLOCK_ENABLE, 0); @@ -614,7 +614,7 @@ static void plane_atomic_disable(struct dc *dc, OPP_PIPE_CLOCK_EN, 0); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); } static void reset_front_end( @@ -638,7 +638,7 @@ static void reset_front_end( tg->funcs->unlock(tg); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(hws); + verify_allow_pstate_change_high(dc->res_pool->hubbub); if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], @@ -670,7 +670,7 @@ static void dcn10_power_down_fe(struct dc *dc, int fe_idx) "Power gated front end %d\n", fe_idx); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); } static void dcn10_init_hw(struct dc *dc) @@ -1243,7 +1243,7 @@ static void dcn10_pipe_control_lock( return; if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); if (lock) pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); @@ -1251,7 +1251,7 @@ static void dcn10_pipe_control_lock( pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); } static bool wait_for_reset_trigger_to_occur( @@ -1451,7 +1451,7 @@ static void dcn10_power_on_fe( struct dce_hwseq *hws = dc->hwseq; if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); } power_on_plane(dc->hwseq, @@ -1503,7 +1503,7 @@ static void dcn10_power_on_fe( } if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); } } @@ -1864,11 +1864,11 @@ static void program_all_pipe_in_tree( * this OTG. this is done only one time. */ /* watermark is for all pipes */ - program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz); + program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, ref_clk_mhz); if (dc->debug.sanity_checks) { /* pstate stuck check after watermark update */ - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); } pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); @@ -1899,7 +1899,7 @@ static void program_all_pipe_in_tree( * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have * both driver and fw accessing same register */ - toggle_watermark_change_req(dc->hwseq); + toggle_watermark_change_req(dc->res_pool->hubbub); update_dchubp_dpp(dc, pipe_ctx, context); @@ -1922,7 +1922,7 @@ static void program_all_pipe_in_tree( if (dc->debug.sanity_checks) { /* pstate stuck check after each pipe is programmed */ - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); } if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) @@ -1989,7 +1989,7 @@ static void dcn10_apply_ctx_for_surface( int i, be_idx; if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); be_idx = -1; for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -2072,7 +2072,7 @@ static void dcn10_apply_ctx_for_surface( hubp->funcs->hubp_disconnect(hubp); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); old_pipe_ctx->top_pipe = NULL; old_pipe_ctx->bottom_pipe = NULL; @@ -2150,7 +2150,7 @@ static void dcn10_apply_ctx_for_surface( ); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); } static void dcn10_set_bandwidth( @@ -2164,7 +2164,7 @@ static void dcn10_set_bandwidth( struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu; if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); } if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) @@ -2220,7 +2220,7 @@ static void dcn10_set_bandwidth( dcn10_pplib_apply_display_requirements(dc, context); if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); } /* need to fix this function. not doing the right thing here */ @@ -2345,7 +2345,7 @@ static void dcn10_wait_for_mpcc_disconnect( int i; if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); } if (!pipe_ctx->stream_res.opp) @@ -2363,7 +2363,7 @@ static void dcn10_wait_for_mpcc_disconnect( } if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); + verify_allow_pstate_change_high(dc->res_pool->hubbub); } } @@ -2407,7 +2407,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .apply_ctx_for_surface = dcn10_apply_ctx_for_surface, .set_plane_config = set_plane_config, .update_plane_addr = dcn10_update_plane_addr, - .update_dchub = dcn10_update_dchub, .update_pending_status = dcn10_update_pending_status, .set_input_transfer_func = dcn10_set_input_transfer_func, .set_output_transfer_func = dcn10_set_output_transfer_func, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 4c3be7c0f9b5..256632cce520 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -48,6 +48,7 @@ #include "dce110/dce110_resource.h" #include "dce112/dce112_resource.h" #include "dcn10_hubp.h" +#include "dcn10_hubbub.h" #include "vega10/soc15ip.h" @@ -388,6 +389,19 @@ static const struct dcn_mi_mask hubp_mask = { HUBP_MASK_SH_LIST_DCN10(_MASK) }; + +static const struct dcn_hubbub_registers hubbub_reg = { + HUBBUB_REG_LIST_DCN10(0) +}; + +static const struct dcn_hubbub_shift hubbub_shift = { + HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) +}; + +static const struct dcn_hubbub_mask hubbub_mask = { + HUBBUB_MASK_SH_LIST_DCN10(_MASK) +}; + #define clk_src_regs(index, pllid)\ [index] = {\ CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ @@ -519,6 +533,22 @@ static struct mpc *dcn10_mpc_create(struct dc_context *ctx) return &mpc10->base; } +static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) +{ + struct hubbub *hubbub = kzalloc(sizeof(struct hubbub), + GFP_KERNEL); + + if (!hubbub) + return NULL; + + hubbub1_construct(hubbub, ctx, + &hubbub_reg, + &hubbub_shift, + &hubbub_mask); + + return hubbub; +} + static struct timing_generator *dcn10_timing_generator_create( struct dc_context *ctx, uint32_t instance) @@ -1401,6 +1431,7 @@ static bool construct( dm_error("DC: failed to create tg!\n"); goto fail; } + /* check next valid pipe */ j++; } @@ -1421,6 +1452,13 @@ static bool construct( goto fail; } + pool->base.hubbub = dcn10_hubbub_create(ctx); + if (pool->base.mpc == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mpc!\n"); + goto fail; + } + if (!resource_construct(num_virtual_links, dc, &pool->base, (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? &res_create_funcs : &res_create_maximus_funcs))) diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index b69f321e2ab6..d680b565af6f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -139,6 +139,7 @@ struct resource_pool { struct timing_generator *timing_generators[MAX_PIPES]; struct stream_encoder *stream_enc[MAX_PIPES * 2]; + struct hubbub *hubbub; struct mpc *mpc; struct pp_smu_funcs_rv *pp_smu; struct pp_smu_display_requirement_rv pp_smu_req; -- GitLab From de4a2967737114d426411a79781d9d81d0ff38d2 Mon Sep 17 00:00:00 2001 From: SivapiriyanKumarasamy Date: Thu, 19 Oct 2017 13:41:30 -0400 Subject: [PATCH 0618/2547] drm/amd/display: Apply VQ adjustments in MPO case Signed-off-by: SivapiriyanKumarasamy Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +- drivers/gpu/drm/amd/display/dc/dc.h | 7 ++ drivers/gpu/drm/amd/display/dc/dc_types.h | 5 -- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 31 ++++++-- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 47 +++++++++--- .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 44 ++++++++--- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 75 ++++++++++++++++++- drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 10 ++- .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 14 ++++ drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 6 +- .../gpu/drm/amd/display/dc/inc/hw/transform.h | 6 +- 11 files changed, 211 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index c874dfd099d3..bc596df85ca9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1137,6 +1137,7 @@ static enum surface_update_type get_plane_info_update_type( temp_plane_info.plane_size = u->surface->plane_size; temp_plane_info.rotation = u->surface->rotation; temp_plane_info.stereo_format = u->surface->stereo_format; + temp_plane_info.input_csc_enabled = u->surface->input_csc_color_matrix.enable_adjustment; if (surface_index == 0) temp_plane_info.visible = u->plane_info->visible; @@ -1217,7 +1218,8 @@ static enum surface_update_type det_surface_update( overall_type = type; if (u->in_transfer_func || - u->hdr_static_metadata) { + u->hdr_static_metadata || + u->input_csc_color_matrix) { if (overall_type < UPDATE_TYPE_MED) overall_type = UPDATE_TYPE_MED; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 45874fa888fc..9833b9de650f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -431,6 +431,9 @@ struct dc_plane_state { struct dc_gamma *gamma_correction; struct dc_transfer_func *in_transfer_func; + struct dc_bias_and_scale *bias_and_scale; + struct csc_transform input_csc_color_matrix; + struct fixed31_32 coeff_reduction_factor; // sourceContentAttribute cache bool is_source_input_valid; @@ -468,6 +471,7 @@ struct dc_plane_info { bool horizontal_mirror; bool visible; bool per_pixel_alpha; + bool input_csc_enabled; }; struct dc_scaling_info { @@ -491,6 +495,9 @@ struct dc_surface_update { struct dc_gamma *gamma; struct dc_transfer_func *in_transfer_func; struct dc_hdr_static_metadata *hdr_static_metadata; + + struct csc_transform *input_csc_color_matrix; + struct fixed31_32 *coeff_reduction_factor; }; /* diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index a8698e399111..9291a60126ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -638,11 +638,6 @@ struct colorspace_transform { bool enable_remap; }; -struct csc_transform { - uint16_t matrix[12]; - bool enable_adjustment; -}; - enum i2c_mot_mode { I2C_MOT_UNDEF, I2C_MOT_TRUE, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 74e7c82bdc76..c5f4d5caf976 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -264,8 +264,10 @@ static void dpp1_set_degamma_format_float( void dpp1_cnv_setup ( struct dpp *dpp_base, - enum surface_pixel_format input_format, - enum expansion_mode mode) + enum surface_pixel_format format, + enum expansion_mode mode, + struct csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space) { uint32_t pixel_format; uint32_t alpha_en; @@ -275,8 +277,10 @@ void dpp1_cnv_setup ( bool is_float; struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); bool force_disable_cursor = false; + struct out_csc_color_matrix tbl_entry; + int i = 0; - dpp1_setup_format_flags(input_format, &fmt); + dpp1_setup_format_flags(format, &fmt); alpha_en = 1; pixel_format = 0; color_space = COLOR_SPACE_SRGB; @@ -306,7 +310,7 @@ void dpp1_cnv_setup ( dpp1_set_degamma_format_float(dpp_base, is_float); - switch (input_format) { + switch (format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: pixel_format = 1; break; @@ -362,7 +366,23 @@ void dpp1_cnv_setup ( CNVC_SURFACE_PIXEL_FORMAT, pixel_format); REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); - dpp1_program_input_csc(dpp_base, color_space, select); + // if input adjustments exist, program icsc with those values + + if (input_csc_color_matrix.enable_adjustment + == true) { + for (i = 0; i < 12; i++) + tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; + + tbl_entry.color_space = input_color_space; + + if (color_space >= COLOR_SPACE_YCBCR601) + select = INPUT_CSC_SELECT_ICSC; + else + select = INPUT_CSC_SELECT_BYPASS; + + dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry); + } else + dpp1_program_input_csc(dpp_base, color_space, select, NULL); if (force_disable_cursor) { REG_UPDATE(CURSOR_CONTROL, @@ -435,6 +455,7 @@ static const struct dpp_funcs dcn10_dpp_funcs = { .opp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings, .opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl, .opp_set_regamma_mode = dpp1_cm_set_regamma_mode, + .ipp_program_bias_and_scale = dpp1_program_bias_and_scale, .ipp_set_degamma = dpp1_set_degamma, .ipp_program_input_lut = dpp1_program_input_lut, .ipp_program_degamma_pwl = dpp1_set_degamma_pwl, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index a9782b1aba47..3a6ebd14eea2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -73,9 +73,6 @@ SRI(RECOUT_START, DSCL, id), \ SRI(RECOUT_SIZE, DSCL, id), \ SRI(OBUF_CONTROL, DSCL, id), \ - SRI(CM_ICSC_CONTROL, CM, id), \ - SRI(CM_ICSC_C11_C12, CM, id), \ - SRI(CM_ICSC_C33_C34, CM, id), \ SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \ SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \ SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \ @@ -127,6 +124,12 @@ SRI(CM_OCSC_CONTROL, CM, id), \ SRI(CM_OCSC_C11_C12, CM, id), \ SRI(CM_OCSC_C33_C34, CM, id), \ + SRI(CM_ICSC_CONTROL, CM, id), \ + SRI(CM_ICSC_C11_C12, CM, id), \ + SRI(CM_ICSC_C33_C34, CM, id), \ + SRI(CM_BNS_VALUES_R, CM, id), \ + SRI(CM_BNS_VALUES_G, CM, id), \ + SRI(CM_BNS_VALUES_B, CM, id), \ SRI(CM_MEM_PWR_CTRL, CM, id), \ SRI(CM_RGAM_LUT_DATA, CM, id), \ SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\ @@ -236,11 +239,6 @@ TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \ - TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ - TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ - TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ - TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ - TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \ TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \ @@ -329,6 +327,17 @@ TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \ TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \ + TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ + TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ + TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ + TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ + TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ + TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \ + TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \ + TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \ + TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \ + TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \ + TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \ TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \ TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \ TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \ @@ -913,6 +922,12 @@ type CM_ICSC_C12; \ type CM_ICSC_C33; \ type CM_ICSC_C34; \ + type CM_BNS_BIAS_R; \ + type CM_BNS_BIAS_G; \ + type CM_BNS_BIAS_B; \ + type CM_BNS_SCALE_R; \ + type CM_BNS_SCALE_G; \ + type CM_BNS_SCALE_B; \ type CM_DGAM_RAMB_EXP_REGION_START_B; \ type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ type CM_DGAM_RAMB_EXP_REGION_START_G; \ @@ -1206,6 +1221,9 @@ struct dcn_dpp_registers { uint32_t CM_ICSC_CONTROL; uint32_t CM_ICSC_C11_C12; uint32_t CM_ICSC_C33_C34; + uint32_t CM_BNS_VALUES_R; + uint32_t CM_BNS_VALUES_G; + uint32_t CM_BNS_VALUES_B; uint32_t CM_DGAM_RAMB_START_CNTL_B; uint32_t CM_DGAM_RAMB_START_CNTL_G; uint32_t CM_DGAM_RAMB_START_CNTL_R; @@ -1310,7 +1328,12 @@ void dpp1_power_on_degamma_lut( void dpp1_program_input_csc( struct dpp *dpp_base, enum dc_color_space color_space, - enum dcn10_input_csc_select select); + enum dcn10_input_csc_select select, + const struct out_csc_color_matrix *tbl_entry); + +void dpp1_program_bias_and_scale( + struct dpp *dpp_base, + struct dc_bias_and_scale *params); void dpp1_program_input_lut( struct dpp *dpp_base, @@ -1372,8 +1395,10 @@ void dpp1_dscl_set_scaler_manual_scale( void dpp1_cnv_setup ( struct dpp *dpp_base, - enum surface_pixel_format input_format, - enum expansion_mode mode); + enum surface_pixel_format format, + enum expansion_mode mode, + struct csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space); void dpp1_full_bypass(struct dpp *dpp_base); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index 40627c244bf5..9cb44c90e746 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -473,7 +473,8 @@ void dpp1_cm_program_regamma_lutb_settings( void dpp1_program_input_csc( struct dpp *dpp_base, enum dc_color_space color_space, - enum dcn10_input_csc_select select) + enum dcn10_input_csc_select select, + const struct out_csc_color_matrix *tbl_entry) { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); int i; @@ -487,15 +488,19 @@ void dpp1_program_input_csc( return; } - for (i = 0; i < arr_size; i++) - if (dcn10_input_csc_matrix[i].color_space == color_space) { - regval = dcn10_input_csc_matrix[i].regval; - break; + if (tbl_entry == NULL) { + for (i = 0; i < arr_size; i++) + if (dcn10_input_csc_matrix[i].color_space == color_space) { + regval = dcn10_input_csc_matrix[i].regval; + break; + } + + if (regval == NULL) { + BREAK_TO_DEBUGGER(); + return; } - - if (regval == NULL) { - BREAK_TO_DEBUGGER(); - return; + } else { + regval = tbl_entry->regval; } if (select == INPUT_CSC_SELECT_COMA) @@ -530,6 +535,27 @@ void dpp1_program_input_csc( } } +//keep here for now, decide multi dce support later +void dpp1_program_bias_and_scale( + struct dpp *dpp_base, + struct dc_bias_and_scale *params) +{ + struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); + + REG_SET_2(CM_BNS_VALUES_R, 0, + CM_BNS_SCALE_R, params->scale_red, + CM_BNS_BIAS_R, params->bias_red); + + REG_SET_2(CM_BNS_VALUES_G, 0, + CM_BNS_SCALE_G, params->scale_green, + CM_BNS_BIAS_G, params->bias_green); + + REG_SET_2(CM_BNS_VALUES_B, 0, + CM_BNS_SCALE_B, params->scale_blue, + CM_BNS_BIAS_B, params->bias_blue); + +} + /*program de gamma RAM B*/ void dpp1_program_degamma_lutb_settings( struct dpp *dpp_base, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 163b40dad3f3..cf594fb44328 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1570,6 +1570,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry); } } + static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { if (pipe_ctx->plane_state->visible) @@ -1657,6 +1658,69 @@ static void dcn10_get_surface_visual_confirm_color( } } +static uint16_t fixed_point_to_int_frac( + struct fixed31_32 arg, + uint8_t integer_bits, + uint8_t fractional_bits) +{ + int32_t numerator; + int32_t divisor = 1 << fractional_bits; + + uint16_t result; + + uint16_t d = (uint16_t)dal_fixed31_32_floor( + dal_fixed31_32_abs( + arg)); + + if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor)) + numerator = (uint16_t)dal_fixed31_32_floor( + dal_fixed31_32_mul_int( + arg, + divisor)); + else { + numerator = dal_fixed31_32_floor( + dal_fixed31_32_sub( + dal_fixed31_32_from_int( + 1LL << integer_bits), + dal_fixed31_32_recip( + dal_fixed31_32_from_int( + divisor)))); + } + + if (numerator >= 0) + result = (uint16_t)numerator; + else + result = (uint16_t)( + (1 << (integer_bits + fractional_bits + 1)) + numerator); + + if ((result != 0) && dal_fixed31_32_lt( + arg, dal_fixed31_32_zero)) + result |= 1 << (integer_bits + fractional_bits); + + return result; +} + +void build_prescale_params(struct dc_bias_and_scale *bias_and_scale, + const struct dc_plane_state *plane_state) +{ + if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN + && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID + && plane_state->input_csc_color_matrix.enable_adjustment + && plane_state->coeff_reduction_factor.value != 0) { + bias_and_scale->scale_blue = fixed_point_to_int_frac( + dal_fixed31_32_mul(plane_state->coeff_reduction_factor, + dal_fixed31_32_from_fraction(256, 255)), + 2, + 13); + bias_and_scale->scale_red = bias_and_scale->scale_blue; + bias_and_scale->scale_green = bias_and_scale->scale_blue; + } else { + bias_and_scale->scale_blue = 0x2000; + bias_and_scale->scale_red = 0x2000; + bias_and_scale->scale_green = 0x2000; + } +} + static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1, struct vm_system_aperture_param *apt, struct dce_hwseq *hws) @@ -1757,6 +1821,7 @@ static void update_dchubp_dpp( struct mpcc_cfg mpcc_cfg = {0}; struct pipe_ctx *top_pipe; bool per_pixel_alpha = plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; + struct dc_bias_and_scale bns_params = {0}; /* TODO: proper fix once fpga works */ /* depends on DML calculation, DPP clock value may change dynamically */ @@ -1793,9 +1858,16 @@ static void update_dchubp_dpp( hws ); + // program the input csc dpp->funcs->ipp_setup(dpp, plane_state->format, - EXPANSION_MODE_ZERO); + EXPANSION_MODE_ZERO, + plane_state->input_csc_color_matrix, + COLOR_SPACE_YCBCR601_LIMITED); + + //set scale and bias registers + build_prescale_params(&bns_params, plane_state); + dpp->funcs->ipp_program_bias_and_scale(dpp, &bns_params); mpcc_cfg.dpp_id = hubp->inst; mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst; @@ -1835,6 +1907,7 @@ static void update_dchubp_dpp( pipe_ctx->stream->output_color_space, pipe_ctx->stream->csc_color_matrix.matrix); + hubp->funcs->hubp_program_surface_config( hubp, plane_state->format, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index 83a68460edcd..6eca95931ee1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -98,6 +98,10 @@ struct dpp_funcs { struct dpp *dpp_base, enum opp_regamma mode); + void (*ipp_program_bias_and_scale)( + struct dpp *dpp, + struct dc_bias_and_scale *params); + void (*ipp_set_degamma)( struct dpp *dpp_base, enum ipp_degamma_mode mode); @@ -111,8 +115,10 @@ struct dpp_funcs { void (*ipp_setup)( struct dpp *dpp_base, - enum surface_pixel_format input_format, - enum expansion_mode mode); + enum surface_pixel_format format, + enum expansion_mode mode, + struct csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space); void (*ipp_full_bypass)(struct dpp *dpp_base); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 9602f261b614..fa3d100de264 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -138,4 +138,18 @@ enum opp_regamma { OPP_REGAMMA_USER }; +struct csc_transform { + uint16_t matrix[12]; + bool enable_adjustment; +}; + +struct dc_bias_and_scale { + uint16_t scale_red; + uint16_t bias_red; + uint16_t scale_green; + uint16_t bias_green; + uint16_t scale_blue; + uint16_t bias_blue; +}; + #endif /* __DAL_HW_SHARED_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h index f11aa484f46e..2109eac20a3d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -85,8 +85,10 @@ struct ipp_funcs { /* setup ipp to expand/convert input to pixel processor internal format */ void (*ipp_setup)( struct input_pixel_processor *ipp, - enum surface_pixel_format input_format, - enum expansion_mode mode); + enum surface_pixel_format format, + enum expansion_mode mode, + struct csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space); /* DCE function to setup IPP. TODO: see if we can consolidate to setup */ void (*ipp_program_prescale)( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index ea88997e1bbd..6f6c02b89f90 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -250,8 +250,10 @@ struct transform_funcs { void (*ipp_setup)( struct transform *xfm_base, - enum surface_pixel_format input_format, - enum expansion_mode mode); + enum surface_pixel_format format, + enum expansion_mode mode, + struct csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space); void (*ipp_full_bypass)(struct transform *xfm_base); -- GitLab From 56ef6ed9faf35b9057630dd12aeca134f98214ec Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Mon, 23 Oct 2017 17:02:02 -0400 Subject: [PATCH 0619/2547] drm/amd/display: Move hdr_metadata from plane to stream Need to move HDR Metadata from Surface to Stream since there is only one infoframe possible per stream. Also cleaning up some duplicate definitions. Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 19 +++++++-- .../gpu/drm/amd/display/dc/core/dc_debug.c | 4 ++ .../gpu/drm/amd/display/dc/core/dc_resource.c | 41 ++++++++----------- drivers/gpu/drm/amd/display/dc/dc.h | 35 ++++------------ drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 9 ++++ .../amd/display/dc/dce/dce_stream_encoder.c | 11 ++++- .../display/dc/dce110/dce110_hw_sequencer.c | 3 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +- 8 files changed, 65 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index bc596df85ca9..55317c029d44 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1007,6 +1007,7 @@ bool dc_commit_planes_to_stream( flip_addr[i].address = plane_states[i]->address; flip_addr[i].flip_immediate = plane_states[i]->flip_immediate; plane_info[i].color_space = plane_states[i]->color_space; + plane_info[i].input_tf = plane_states[i]->input_tf; plane_info[i].format = plane_states[i]->format; plane_info[i].plane_size = plane_states[i]->plane_size; plane_info[i].rotation = plane_states[i]->rotation; @@ -1132,12 +1133,12 @@ static enum surface_update_type get_plane_info_update_type( /* Full update parameters */ temp_plane_info.color_space = u->surface->color_space; + temp_plane_info.input_tf = u->surface->input_tf; temp_plane_info.dcc = u->surface->dcc; temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror; temp_plane_info.plane_size = u->surface->plane_size; temp_plane_info.rotation = u->surface->rotation; temp_plane_info.stereo_format = u->surface->stereo_format; - temp_plane_info.input_csc_enabled = u->surface->input_csc_color_matrix.enable_adjustment; if (surface_index == 0) temp_plane_info.visible = u->plane_info->visible; @@ -1218,7 +1219,6 @@ static enum surface_update_type det_surface_update( overall_type = type; if (u->in_transfer_func || - u->hdr_static_metadata || u->input_csc_color_matrix) { if (overall_type < UPDATE_TYPE_MED) overall_type = UPDATE_TYPE_MED; @@ -1350,14 +1350,25 @@ static void commit_planes_for_stream(struct dc *dc, pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state)) dc->hwss.set_input_transfer_func( pipe_ctx, pipe_ctx->plane_state); + } + } + + if (update_type > UPDATE_TYPE_FAST) { + for (j = 0; j < dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; + + if (!pipe_ctx->stream) + continue; if (stream_update != NULL && - stream_update->out_transfer_func != NULL) { + stream_update->out_transfer_func != NULL) { dc->hwss.set_output_transfer_func( pipe_ctx, pipe_ctx->stream); } - if (srf_updates[i].hdr_static_metadata) { + if (stream_update != NULL && + stream_update->hdr_static_metadata) { resource_build_info_frame(pipe_ctx); dc->hwss.update_info_frame(pipe_ctx); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 6acee5426e4b..2e509382935f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -137,6 +137,7 @@ void pre_surface_trace( "plane_state->tiling_info.gfx8.pipe_config = %d;\n" "plane_state->tiling_info.gfx8.array_mode = %d;\n" "plane_state->color_space = %d;\n" + "plane_state->input_tf = %d;\n" "plane_state->dcc.enable = %d;\n" "plane_state->format = %d;\n" "plane_state->rotation = %d;\n" @@ -144,6 +145,7 @@ void pre_surface_trace( plane_state->tiling_info.gfx8.pipe_config, plane_state->tiling_info.gfx8.array_mode, plane_state->color_space, + plane_state->input_tf, plane_state->dcc.enable, plane_state->format, plane_state->rotation, @@ -184,6 +186,7 @@ void update_surface_trace( if (update->plane_info) { SURFACE_TRACE( "plane_info->color_space = %d;\n" + "plane_info->input_tf = %d;\n" "plane_info->format = %d;\n" "plane_info->plane_size.grph.surface_pitch = %d;\n" "plane_info->plane_size.grph.surface_size.height = %d;\n" @@ -192,6 +195,7 @@ void update_surface_trace( "plane_info->plane_size.grph.surface_size.y = %d;\n" "plane_info->rotation = %d;\n", update->plane_info->color_space, + update->plane_info->input_tf, update->plane_info->format, update->plane_info->plane_size.grph.surface_pitch, update->plane_info->plane_size.grph.surface_size.height, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index b7422d3b71ef..15e518aba916 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2319,20 +2319,13 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, - struct dc_plane_state *plane_state, struct dc_stream_state *stream) { uint16_t i = 0; enum signal_type signal = stream->signal; - struct dc_hdr_static_metadata hdr_metadata; uint32_t data; - if (!plane_state) - return; - - hdr_metadata = plane_state->hdr_static_ctx; - - if (!hdr_metadata.hdr_supported) + if (!stream->hdr_static_metadata.hdr_supported) return; if (dc_is_hdmi_signal(signal)) { @@ -2352,55 +2345,55 @@ static void set_hdr_static_info_packet( i = 2; } - data = hdr_metadata.is_hdr; + data = stream->hdr_static_metadata.is_hdr; info_packet->sb[i++] = data ? 0x02 : 0x00; info_packet->sb[i++] = 0x00; - data = hdr_metadata.chromaticity_green_x / 2; + data = stream->hdr_static_metadata.chromaticity_green_x / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_green_y / 2; + data = stream->hdr_static_metadata.chromaticity_green_y / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_blue_x / 2; + data = stream->hdr_static_metadata.chromaticity_blue_x / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_blue_y / 2; + data = stream->hdr_static_metadata.chromaticity_blue_y / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_red_x / 2; + data = stream->hdr_static_metadata.chromaticity_red_x / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_red_y / 2; + data = stream->hdr_static_metadata.chromaticity_red_y / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_white_point_x / 2; + data = stream->hdr_static_metadata.chromaticity_white_point_x / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_white_point_y / 2; + data = stream->hdr_static_metadata.chromaticity_white_point_y / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.max_luminance; + data = stream->hdr_static_metadata.max_luminance; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.min_luminance; + data = stream->hdr_static_metadata.min_luminance; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.maximum_content_light_level; + data = stream->hdr_static_metadata.maximum_content_light_level; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.maximum_frame_average_light_level; + data = stream->hdr_static_metadata.maximum_frame_average_light_level; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; @@ -2551,16 +2544,14 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) set_spd_info_packet(&info->spd, pipe_ctx->stream); - set_hdr_static_info_packet(&info->hdrsmd, - pipe_ctx->plane_state, pipe_ctx->stream); + set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); } else if (dc_is_dp_signal(signal)) { set_vsc_info_packet(&info->vsc, pipe_ctx->stream); set_spd_info_packet(&info->spd, pipe_ctx->stream); - set_hdr_static_info_packet(&info->hdrsmd, - pipe_ctx->plane_state, pipe_ctx->stream); + set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); } patch_gamut_packet_checksum(&info->gamut); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9833b9de650f..e39371797eeb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -334,24 +334,6 @@ enum color_transfer_func { transfer_func_gamma_26 }; -enum color_color_space { - color_space_unsupported, - color_space_srgb, - color_space_bt601, - color_space_bt709, - color_space_xv_ycc_bt601, - color_space_xv_ycc_bt709, - color_space_xr_rgb, - color_space_bt2020, - color_space_adobe, - color_space_dci_p3, - color_space_sc_rgb_ms_ref, - color_space_display_native, - color_space_app_ctrl, - color_space_dolby_vision, - color_space_custom_coordinates -}; - struct dc_hdr_static_metadata { /* display chromaticities and white point in units of 0.00001 */ unsigned int chromaticity_green_x; @@ -427,7 +409,6 @@ struct dc_plane_state { union dc_tiling_info tiling_info; struct dc_plane_dcc_param dcc; - struct dc_hdr_static_metadata hdr_static_ctx; struct dc_gamma *gamma_correction; struct dc_transfer_func *in_transfer_func; @@ -435,13 +416,12 @@ struct dc_plane_state { struct csc_transform input_csc_color_matrix; struct fixed31_32 coeff_reduction_factor; - // sourceContentAttribute cache - bool is_source_input_valid; - struct dc_hdr_static_metadata source_input_mastering_info; - enum color_color_space source_input_color_space; - enum color_transfer_func source_input_tf; + // TODO: No longer used, remove + struct dc_hdr_static_metadata hdr_static_ctx; enum dc_color_space color_space; + enum color_transfer_func input_tf; + enum surface_pixel_format format; enum dc_rotation_angle rotation; enum plane_stereo_format stereo_format; @@ -467,7 +447,8 @@ struct dc_plane_info { enum surface_pixel_format format; enum dc_rotation_angle rotation; enum plane_stereo_format stereo_format; - enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/ + enum dc_color_space color_space; + enum color_transfer_func input_tf; bool horizontal_mirror; bool visible; bool per_pixel_alpha; @@ -488,13 +469,13 @@ struct dc_surface_update { struct dc_flip_addrs *flip_addr; struct dc_plane_info *plane_info; struct dc_scaling_info *scaling_info; + /* following updates require alloc/sleep/spin that is not isr safe, * null means no updates */ /* gamma TO BE REMOVED */ struct dc_gamma *gamma; struct dc_transfer_func *in_transfer_func; - struct dc_hdr_static_metadata *hdr_static_metadata; struct csc_transform *input_csc_color_matrix; struct fixed31_32 *coeff_reduction_factor; @@ -591,6 +572,7 @@ struct dc_stream_state { struct freesync_context freesync_ctx; + struct dc_hdr_static_metadata hdr_static_metadata; struct dc_transfer_func *out_transfer_func; struct colorspace_transform gamut_remap_matrix; struct csc_transform csc_color_matrix; @@ -631,6 +613,7 @@ struct dc_stream_update { struct rect src; struct rect dst; struct dc_transfer_func *out_transfer_func; + struct dc_hdr_static_metadata *hdr_static_metadata; }; bool dc_is_stream_unchanged( diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 1a9f57fb0838..ea58d106fb55 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -492,15 +492,24 @@ struct dc_cursor_attributes { enum dc_color_space { COLOR_SPACE_UNKNOWN, COLOR_SPACE_SRGB, + COLOR_SPACE_XR_RGB, COLOR_SPACE_SRGB_LIMITED, + COLOR_SPACE_MSREF_SCRGB, COLOR_SPACE_YCBCR601, COLOR_SPACE_YCBCR709, + COLOR_SPACE_XV_YCC_709, + COLOR_SPACE_XV_YCC_601, COLOR_SPACE_YCBCR601_LIMITED, COLOR_SPACE_YCBCR709_LIMITED, COLOR_SPACE_2020_RGB_FULLRANGE, COLOR_SPACE_2020_RGB_LIMITEDRANGE, COLOR_SPACE_2020_YCBCR, COLOR_SPACE_ADOBERGB, + COLOR_SPACE_DCIP3, + COLOR_SPACE_DISPLAYNATIVE, + COLOR_SPACE_DOLBYVISION, + COLOR_SPACE_APPCTRL, + COLOR_SPACE_CUSTOMPOINTS, }; enum dc_dither_option { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index e42b6eb1c1f0..4748975fd47e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -437,10 +437,19 @@ static void dce110_stream_encoder_dp_set_stream_attribute( case COLOR_SPACE_2020_RGB_FULLRANGE: case COLOR_SPACE_2020_RGB_LIMITEDRANGE: case COLOR_SPACE_2020_YCBCR: + case COLOR_SPACE_XR_RGB: + case COLOR_SPACE_MSREF_SCRGB: case COLOR_SPACE_ADOBERGB: - case COLOR_SPACE_UNKNOWN: + case COLOR_SPACE_DCIP3: + case COLOR_SPACE_XV_YCC_709: + case COLOR_SPACE_XV_YCC_601: case COLOR_SPACE_YCBCR601_LIMITED: case COLOR_SPACE_YCBCR709_LIMITED: + case COLOR_SPACE_DISPLAYNATIVE: + case COLOR_SPACE_DOLBYVISION: + case COLOR_SPACE_APPCTRL: + case COLOR_SPACE_CUSTOMPOINTS: + case COLOR_SPACE_UNKNOWN: /* do nothing */ break; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 61e11a1161bb..58d019cacaa2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2279,8 +2279,7 @@ static void set_plane_config( dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); set_default_colors(pipe_ctx); - if (pipe_ctx->stream->csc_color_matrix.enable_adjustment - == true) { + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { tbl_entry.color_space = pipe_ctx->stream->output_color_space; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index cf594fb44328..adabd2ad5594 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1556,8 +1556,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, int i; struct out_csc_color_matrix tbl_entry; - if (pipe_ctx->stream->csc_color_matrix.enable_adjustment - == true) { + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { enum dc_color_space color_space = pipe_ctx->stream->output_color_space; -- GitLab From 75dbba34ae6df7bb63f0d836093a7e2d602da07d Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Tue, 24 Oct 2017 11:40:50 -0400 Subject: [PATCH 0620/2547] drm/amd/display: fix bug from last commit for hubbub fix memory leak Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 256632cce520..dd834fdf7ce7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -730,6 +730,12 @@ static void destruct(struct dcn10_resource_pool *pool) kfree(TO_DCN10_MPC(pool->base.mpc)); pool->base.mpc = NULL; } + + if (pool->base.hubbub != NULL) { + kfree(pool->base.hubbub); + pool->base.hubbub = NULL; + } + for (i = 0; i < pool->base.pipe_count; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); @@ -1453,7 +1459,7 @@ static bool construct( } pool->base.hubbub = dcn10_hubbub_create(ctx); - if (pool->base.mpc == NULL) { + if (pool->base.hubbub == NULL) { BREAK_TO_DEBUGGER(); dm_error("DC: failed to create mpc!\n"); goto fail; -- GitLab From 603b83bae4e4df95679045e765964515d3271f6e Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Tue, 24 Oct 2017 18:19:06 -0400 Subject: [PATCH 0621/2547] drm/amd/display: correct DP is always in full range or bt609 Signed-off-by: Charlene Liu Reviewed-by: Krunoslav Kovac Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dce/dce_stream_encoder.c | 25 +++++++++++++------ 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index 4748975fd47e..83bae207371d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -300,6 +300,8 @@ static void dce110_stream_encoder_dp_set_stream_attribute( uint32_t h_back_porch; uint8_t synchronous_clock = 0; /* asynchronous mode */ uint8_t colorimetry_bpc; + uint8_t dynamic_range_rgb = 0; /*full range*/ + uint8_t dynamic_range_ycbcr = 1; /*bt709*/ #endif struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); @@ -380,11 +382,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( } /* set dynamic range and YCbCr range */ - if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) - REG_UPDATE_2( - DP_PIXEL_FORMAT, - DP_DYN_RANGE, 0, - DP_YCBCR_RANGE, 0); + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) switch (crtc_timing->display_color_depth) { @@ -413,29 +411,37 @@ static void dce110_stream_encoder_dp_set_stream_attribute( case COLOR_SPACE_SRGB: misc0 = misc0 | 0x0; misc1 = misc1 & ~0x80; /* bit7 = 0*/ + dynamic_range_rgb = 0; /*full range*/ break; case COLOR_SPACE_SRGB_LIMITED: misc0 = misc0 | 0x8; /* bit3=1 */ misc1 = misc1 & ~0x80; /* bit7 = 0*/ + dynamic_range_rgb = 1; /*limited range*/ break; case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YCBCR601_LIMITED: misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ misc1 = misc1 & ~0x80; /* bit7 = 0*/ + dynamic_range_ycbcr = 0; /*bt601*/ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ break; case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YCBCR709_LIMITED: misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ misc1 = misc1 & ~0x80; /* bit7 = 0*/ + dynamic_range_ycbcr = 1; /*bt709*/ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ break; - case COLOR_SPACE_2020_RGB_FULLRANGE: case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + dynamic_range_rgb = 1; /*limited range*/ + break; + case COLOR_SPACE_2020_RGB_FULLRANGE: case COLOR_SPACE_2020_YCBCR: case COLOR_SPACE_XR_RGB: case COLOR_SPACE_MSREF_SCRGB: @@ -443,8 +449,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute( case COLOR_SPACE_DCIP3: case COLOR_SPACE_XV_YCC_709: case COLOR_SPACE_XV_YCC_601: - case COLOR_SPACE_YCBCR601_LIMITED: - case COLOR_SPACE_YCBCR709_LIMITED: case COLOR_SPACE_DISPLAYNATIVE: case COLOR_SPACE_DOLBYVISION: case COLOR_SPACE_APPCTRL: @@ -453,6 +457,11 @@ static void dce110_stream_encoder_dp_set_stream_attribute( /* do nothing */ break; } + if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) + REG_UPDATE_2( + DP_PIXEL_FORMAT, + DP_DYN_RANGE, dynamic_range_rgb, + DP_YCBCR_RANGE, dynamic_range_ycbcr); #if defined(CONFIG_DRM_AMD_DC_DCN1_0) if (REG(DP_MSA_COLORIMETRY)) -- GitLab From 2d7d273d22aa22cb95077de9d3e366c8084c3b20 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Wed, 25 Oct 2017 00:15:05 -0400 Subject: [PATCH 0622/2547] drm/amd/display: dal 3.1.10 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e39371797eeb..4019e7417c88 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.09" +#define DC_VER "3.1.10" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From b3734397a0b093eae7bce93b7e25a73051ce6972 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 19 Oct 2017 14:28:23 -0400 Subject: [PATCH 0623/2547] drm/amd/display: Move conn_state to header We'll need it in amdgpu_dm_mst_types.c as well. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ------------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 12 ++++++++++++ 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9c5a5f58bfe1..72a08776a6a6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1679,19 +1679,6 @@ static int dm_early_init(void *handle) return 0; } -struct dm_connector_state { - struct drm_connector_state base; - - enum amdgpu_rmx_type scaling; - uint8_t underscan_vborder; - uint8_t underscan_hborder; - bool underscan_enable; - struct mod_freesync_user_enable user_enable; -}; - -#define to_dm_connector_state(x)\ - container_of((x), struct dm_connector_state, base) - static bool modeset_required(struct drm_crtc_state *crtc_state, struct dc_stream_state *new_stream, struct dc_stream_state *old_stream) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 117521c6a6ed..8a1e4f5dbd64 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -220,6 +220,18 @@ struct dm_atomic_state { #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) +struct dm_connector_state { + struct drm_connector_state base; + + enum amdgpu_rmx_type scaling; + uint8_t underscan_vborder; + uint8_t underscan_hborder; + bool underscan_enable; + struct mod_freesync_user_enable user_enable; +}; + +#define to_dm_connector_state(x)\ + container_of((x), struct dm_connector_state, base) void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); struct drm_connector_state * -- GitLab From d794b9f8272203ea1cbea0472fe55b1b28826060 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Tue, 24 Oct 2017 11:03:21 +0200 Subject: [PATCH 0624/2547] amdgpu/dce: Use actual number of CRTCs and HPDs in set_irq_funcs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hardcoding the maximum numbers could result in spurious error messages from the IRQ state callbacks, e.g. on Polaris 11/12: [drm:dce_v11_0_set_pageflip_irq_state [amdgpu]] *ERROR* invalid pageflip crtc 5 [drm:amdgpu_irq_disable_all [amdgpu]] *ERROR* error disabling interrupt (-22) Signed-off-by: Michel Dänzer Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 12 ++++++++---- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 12 ++++++++---- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 12 ++++++++---- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 12 ++++++++---- 4 files changed, 32 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 4e519dc42916..f3dd6b7bfd4d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2773,7 +2773,6 @@ static int dce_v10_0_early_init(void *handle) adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; dce_v10_0_set_display_funcs(adev); - dce_v10_0_set_irq_funcs(adev); adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev); @@ -2788,6 +2787,8 @@ static int dce_v10_0_early_init(void *handle) return -EINVAL; } + dce_v10_0_set_irq_funcs(adev); + return 0; } @@ -3635,13 +3636,16 @@ static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = { static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) { - adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + if (adev->mode_info.num_crtc > 0) + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; + else + adev->crtc_irq.num_types = 0; adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; - adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.num_types = adev->mode_info.num_crtc; adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; - adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.num_types = adev->mode_info.num_hpd; adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 11edc75edaa9..be25706e5f07 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2876,7 +2876,6 @@ static int dce_v11_0_early_init(void *handle) adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; dce_v11_0_set_display_funcs(adev); - dce_v11_0_set_irq_funcs(adev); adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev); @@ -2903,6 +2902,8 @@ static int dce_v11_0_early_init(void *handle) return -EINVAL; } + dce_v11_0_set_irq_funcs(adev); + return 0; } @@ -3759,13 +3760,16 @@ static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) { - adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + if (adev->mode_info.num_crtc > 0) + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; + else + adev->crtc_irq.num_types = 0; adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; - adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.num_types = adev->mode_info.num_crtc; adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; - adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.num_types = adev->mode_info.num_hpd; adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index a51e35f824a1..bd2c4f727df6 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2639,7 +2639,6 @@ static int dce_v6_0_early_init(void *handle) adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; dce_v6_0_set_display_funcs(adev); - dce_v6_0_set_irq_funcs(adev); adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); @@ -2658,6 +2657,8 @@ static int dce_v6_0_early_init(void *handle) return -EINVAL; } + dce_v6_0_set_irq_funcs(adev); + return 0; } @@ -3441,13 +3442,16 @@ static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = { static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev) { - adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + if (adev->mode_info.num_crtc > 0) + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; + else + adev->crtc_irq.num_types = 0; adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; - adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.num_types = adev->mode_info.num_crtc; adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; - adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.num_types = adev->mode_info.num_hpd; adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 9cf14b8b2db9..c008dc030687 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2664,7 +2664,6 @@ static int dce_v8_0_early_init(void *handle) adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; dce_v8_0_set_display_funcs(adev); - dce_v8_0_set_irq_funcs(adev); adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev); @@ -2688,6 +2687,8 @@ static int dce_v8_0_early_init(void *handle) return -EINVAL; } + dce_v8_0_set_irq_funcs(adev); + return 0; } @@ -3525,13 +3526,16 @@ static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = { static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev) { - adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + if (adev->mode_info.num_crtc > 0) + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; + else + adev->crtc_irq.num_types = 0; adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs; - adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.num_types = adev->mode_info.num_crtc; adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs; - adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.num_types = adev->mode_info.num_hpd; adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs; } -- GitLab From c8dd571564c0acd2677b094ce44bafbe595b576f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Tue, 24 Oct 2017 11:13:34 +0200 Subject: [PATCH 0625/2547] drm/amd/display: Use real number of CRTCs and HPDs in set_irq_funcs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Corresponding to the previous non-DC change. Signed-off-by: Michel Dänzer Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 9 ++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 72a08776a6a6..f46cef9bde68 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1590,7 +1590,6 @@ static int dm_early_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; adev->ddev->driver->driver_features |= DRIVER_ATOMIC; - amdgpu_dm_set_irq_funcs(adev); switch (adev->asic_type) { case CHIP_BONAIRE: @@ -1664,6 +1663,8 @@ static int dm_early_init(void *handle) return -EINVAL; } + amdgpu_dm_set_irq_funcs(adev); + if (adev->mode_info.funcs == NULL) adev->mode_info.funcs = &dm_display_funcs; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index ca5d0d1581dc..1874b6cee6af 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -683,13 +683,16 @@ static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = { void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev) { - adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + if (adev->mode_info.num_crtc > 0) + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; + else + adev->crtc_irq.num_types = 0; adev->crtc_irq.funcs = &dm_crtc_irq_funcs; - adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.num_types = adev->mode_info.num_crtc; adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs; - adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.num_types = adev->mode_info.num_hpd; adev->hpd_irq.funcs = &dm_hpd_irq_funcs; } -- GitLab From 8fb0450c9446b38adc5d4b13433ca1702ec09d2e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Tue, 24 Oct 2017 11:15:52 +0200 Subject: [PATCH 0626/2547] amdgpu: Remove AMDGPU_{HPD,CRTC_IRQ,PAGEFLIP_IRQ}_LAST MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not used anymore. Signed-off-by: Michel Dänzer Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index ffde1e9666e8..126b8b068b7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -89,7 +89,6 @@ enum amdgpu_hpd_id { AMDGPU_HPD_4, AMDGPU_HPD_5, AMDGPU_HPD_6, - AMDGPU_HPD_LAST, AMDGPU_HPD_NONE = 0xff, }; @@ -106,7 +105,6 @@ enum amdgpu_crtc_irq { AMDGPU_CRTC_IRQ_VLINE4, AMDGPU_CRTC_IRQ_VLINE5, AMDGPU_CRTC_IRQ_VLINE6, - AMDGPU_CRTC_IRQ_LAST, AMDGPU_CRTC_IRQ_NONE = 0xff }; @@ -117,7 +115,6 @@ enum amdgpu_pageflip_irq { AMDGPU_PAGEFLIP_IRQ_D4, AMDGPU_PAGEFLIP_IRQ_D5, AMDGPU_PAGEFLIP_IRQ_D6, - AMDGPU_PAGEFLIP_IRQ_LAST, AMDGPU_PAGEFLIP_IRQ_NONE = 0xff }; -- GitLab From 9817d5f52d974748f2c3c29095a698b1a88b3cd8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Thu, 26 Oct 2017 16:56:35 +0200 Subject: [PATCH 0627/2547] drm/amd/display: Remove fb_location parameter from get_fb_info MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's dead code. Signed-off-by: Michel Dänzer Reviewed-by: Christian König Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 ++++++------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f46cef9bde68..550e3bd923b2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1762,8 +1762,7 @@ static bool fill_rects_from_plane_state(const struct drm_plane_state *state, return true; } static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, - uint64_t *tiling_flags, - uint64_t *fb_location) + uint64_t *tiling_flags) { struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); int r = amdgpu_bo_reserve(rbo, false); @@ -1775,9 +1774,6 @@ static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, return r; } - if (fb_location) - *fb_location = amdgpu_bo_gpu_offset(rbo); - if (tiling_flags) amdgpu_bo_get_tiling_flags(rbo, tiling_flags); @@ -1788,8 +1784,7 @@ static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, struct dc_plane_state *plane_state, - const struct amdgpu_framebuffer *amdgpu_fb, - bool addReq) + const struct amdgpu_framebuffer *amdgpu_fb) { uint64_t tiling_flags; uint64_t fb_location = 0; @@ -1801,8 +1796,7 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, ret = get_fb_info( amdgpu_fb, - &tiling_flags, - addReq == true ? &fb_location:NULL); + &tiling_flags); if (ret) return ret; @@ -1972,8 +1966,7 @@ static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state, static int fill_plane_attributes(struct amdgpu_device *adev, struct dc_plane_state *dc_plane_state, struct drm_plane_state *plane_state, - struct drm_crtc_state *crtc_state, - bool addrReq) + struct drm_crtc_state *crtc_state) { const struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(plane_state->fb); @@ -1987,8 +1980,7 @@ static int fill_plane_attributes(struct amdgpu_device *adev, ret = fill_plane_attributes_from_fb( crtc->dev->dev_private, dc_plane_state, - amdgpu_fb, - addrReq); + amdgpu_fb); if (ret) return ret; @@ -4660,8 +4652,7 @@ static int dm_update_planes_state(struct dc *dc, new_plane_crtc->dev->dev_private, dm_new_plane_state->dc_state, new_plane_state, - new_crtc_state, - false); + new_crtc_state); if (ret) return ret; -- GitLab From f47110330c98e4d09dc45286942765f4181a0fb1 Mon Sep 17 00:00:00 2001 From: pding Date: Mon, 30 Oct 2017 13:51:54 +0800 Subject: [PATCH 0628/2547] drm/amdgpu: return error when sriov access requests get timeout Reported-by: Sun Gary Signed-off-by: pding Reviewed-by: Xiangliang Yu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index 818ec0fe2f51..2b435c02ef44 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -446,8 +446,10 @@ static int xgpu_vi_send_access_requests(struct amdgpu_device *adev, request == IDH_REQ_GPU_FINI_ACCESS || request == IDH_REQ_GPU_RESET_ACCESS) { r = xgpu_vi_poll_msg(adev, IDH_READY_TO_ACCESS_GPU); - if (r) - pr_err("Doesn't get ack from pf, continue\n"); + if (r) { + pr_err("Doesn't get ack from pf, give up\n"); + return r; + } } return 0; -- GitLab From 5ffa61c1bdc35895f60ef7b553b43266d3fda469 Mon Sep 17 00:00:00 2001 From: pding Date: Mon, 30 Oct 2017 14:07:24 +0800 Subject: [PATCH 0629/2547] drm/amdgpu: retry init if exclusive mode request is failed This is caused of that hypervisor fails to handle request, one known issue is MMIO unblocking timeout. In theory we can retry init here. Signed-off-by: pding Reviewed-by: Xiangliang Yu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7af0d5d8cb1d..69e724c96442 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1625,7 +1625,7 @@ static int amdgpu_early_init(struct amdgpu_device *adev) if (amdgpu_sriov_vf(adev)) { r = amdgpu_virt_request_full_gpu(adev, true); if (r) - return r; + return -EAGAIN; } for (i = 0; i < adev->num_ip_blocks; i++) { -- GitLab From 3c7388936a76affe656d7ba682a33740a99b4a19 Mon Sep 17 00:00:00 2001 From: Horace Chen Date: Wed, 1 Nov 2017 19:32:11 +0800 Subject: [PATCH 0630/2547] drm/amdgpu: refine SR-IOV firmware VRAM reservation to protect data The previous solution will create a zero buffer on the system domain and then move the zeroes to the VRAM. This will break the original data on the VRAM. Refine the code to create bo on VRAM domain directly and then remove and re-create mem node to the exact position before bo_pin. This can avoid breaking the data and will not cause eviction. Signed-off-by: Horace Chen Reviewed-by: monk liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 +++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 69e724c96442..83dbd02004b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -680,8 +680,12 @@ void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev) int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) { int r = 0; + int i; u64 gpu_addr; u64 vram_size = adev->mc.visible_vram_size; + u64 offset = adev->fw_vram_usage.start_offset; + u64 size = adev->fw_vram_usage.size; + struct amdgpu_bo *bo; adev->fw_vram_usage.va = NULL; adev->fw_vram_usage.reserved_bo = NULL; @@ -690,7 +694,7 @@ int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) adev->fw_vram_usage.size <= vram_size) { r = amdgpu_bo_create(adev, adev->fw_vram_usage.size, - PAGE_SIZE, true, 0, + PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0, &adev->fw_vram_usage.reserved_bo); @@ -700,6 +704,23 @@ int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false); if (r) goto error_reserve; + + /* remove the original mem node and create a new one at the + * request position + */ + bo = adev->fw_vram_usage.reserved_bo; + offset = ALIGN(offset, PAGE_SIZE); + for (i = 0; i < bo->placement.num_placement; ++i) { + bo->placements[i].fpfn = offset >> PAGE_SHIFT; + bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; + } + + ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem); + r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem, + false, false); + if (r) + goto error_pin; + r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo, AMDGPU_GEM_DOMAIN_VRAM, adev->fw_vram_usage.start_offset, -- GitLab From d6895ad39f3b396be199f5b6fdfb8cde4be7bbf7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Tue, 28 Feb 2017 10:36:43 +0100 Subject: [PATCH 0631/2547] drm/amdgpu: resize VRAM BAR for CPU access v6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Try to resize BAR0 to let CPU access all of VRAM. v2: rebased, style cleanups, disable mem decode before resize, handle gmc_v9 as well, round size up to power of two. v3: handle gmc_v6 as well, release and reassign all BARs in the driver. v4: rename new function to amdgpu_device_resize_fb_bar, reenable mem decoding only if all resources are assigned. v5: reorder resource release, return -ENODEV instead of BUG_ON(). v6: squash in rebase fix Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 12 ++++-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 13 ++++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 13 ++++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 14 ++++-- 6 files changed, 90 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index d11967a5c392..a7066f55fe2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1847,6 +1847,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); +int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 83dbd02004b0..84c8bbec27ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -410,6 +410,9 @@ static int amdgpu_doorbell_init(struct amdgpu_device *adev) return 0; } + if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) + return -EINVAL; + /* doorbell bar mapping */ adev->doorbell.base = pci_resource_start(adev->pdev, 2); adev->doorbell.size = pci_resource_len(adev->pdev, 2); @@ -749,6 +752,53 @@ int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) return r; } +/** + * amdgpu_device_resize_fb_bar - try to resize FB BAR + * + * @adev: amdgpu_device pointer + * + * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not + * to fail, but if any of the BARs is not accessible after the size we abort + * driver loading by returning -ENODEV. + */ +int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) +{ + u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size); + u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; + u16 cmd; + int r; + + /* Disable memory decoding while we change the BAR addresses and size */ + pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); + pci_write_config_word(adev->pdev, PCI_COMMAND, + cmd & ~PCI_COMMAND_MEMORY); + + /* Free the VRAM and doorbell BAR, we most likely need to move both. */ + amdgpu_doorbell_fini(adev); + if (adev->asic_type >= CHIP_BONAIRE) + pci_release_resource(adev->pdev, 2); + + pci_release_resource(adev->pdev, 0); + + r = pci_resize_resource(adev->pdev, 0, rbar_size); + if (r == -ENOSPC) + DRM_INFO("Not enough PCI address space for a large BAR."); + else if (r && r != -ENOTSUPP) + DRM_ERROR("Problem resizing BAR0 (%d).", r); + + pci_assign_unassigned_bus_resources(adev->pdev->bus); + + /* When the doorbell or fb BAR isn't available we have no chance of + * using the device. + */ + r = amdgpu_doorbell_init(adev); + if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) + return -ENODEV; + + pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); + + return 0; +} /* * GPU helpers function. diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index f4603a7c8ef3..d2a43db22cff 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -283,6 +283,7 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) u32 tmp; int chansize, numchan; + int r; tmp = RREG32(mmMC_ARB_RAMCFG); if (tmp & (1 << 11)) { @@ -324,12 +325,17 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) break; } adev->mc.vram_width = numchan * chansize; - /* Could aper size report 0 ? */ - adev->mc.aper_base = pci_resource_start(adev->pdev, 0); - adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* size in MB on si */ adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + + if (!(adev->flags & AMD_IS_APU)) { + r = amdgpu_device_resize_fb_bar(adev); + if (r) + return r; + } + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); adev->mc.visible_vram_size = adev->mc.aper_size; /* set the gart size */ diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index b0528ca9207b..583d87792820 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -322,6 +322,8 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev) */ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) { + int r; + adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev); if (!adev->mc.vram_width) { u32 tmp; @@ -367,13 +369,18 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) } adev->mc.vram_width = numchan * chansize; } - /* Could aper size report 0 ? */ - adev->mc.aper_base = pci_resource_start(adev->pdev, 0); - adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* size in MB on si */ adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + if (!(adev->flags & AMD_IS_APU)) { + r = amdgpu_device_resize_fb_bar(adev); + if (r) + return r; + } + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); + #ifdef CONFIG_X86_64 if (adev->flags & AMD_IS_APU) { adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index f368cfe2f585..9ca5fea93ebc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -498,6 +498,8 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev) */ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) { + int r; + adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev); if (!adev->mc.vram_width) { u32 tmp; @@ -543,13 +545,18 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) } adev->mc.vram_width = numchan * chansize; } - /* Could aper size report 0 ? */ - adev->mc.aper_base = pci_resource_start(adev->pdev, 0); - adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* size in MB on si */ adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + if (!(adev->flags & AMD_IS_APU)) { + r = amdgpu_device_resize_fb_bar(adev); + if (r) + return r; + } + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); + #ifdef CONFIG_X86_64 if (adev->flags & AMD_IS_APU) { adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index c8f1aebeac7a..f11dfd47b517 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -449,6 +449,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) { u32 tmp; int chansize, numchan; + int r; adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); if (!adev->mc.vram_width) { @@ -491,17 +492,22 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) adev->mc.vram_width = numchan * chansize; } - /* Could aper size report 0 ? */ - adev->mc.aper_base = pci_resource_start(adev->pdev, 0); - adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* size in MB on si */ adev->mc.mc_vram_size = ((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) : nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL; adev->mc.real_vram_size = adev->mc.mc_vram_size; - adev->mc.visible_vram_size = adev->mc.aper_size; + + if (!(adev->flags & AMD_IS_APU)) { + r = amdgpu_device_resize_fb_bar(adev); + if (r) + return r; + } + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* In case the PCI BAR is larger than the actual amount of vram */ + adev->mc.visible_vram_size = adev->mc.aper_size; if (adev->mc.visible_vram_size > adev->mc.real_vram_size) adev->mc.visible_vram_size = adev->mc.real_vram_size; -- GitLab From b2b7e457ba752029c5c9978b0af941313ff706af Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Thu, 2 Nov 2017 17:53:37 +0800 Subject: [PATCH 0632/2547] drm/amdgpu: switch to use new SOC15 reg read/write macros for soc15 ih MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Hawking Zhang Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 46 +++++++++++++------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 697325737ba8..9d8bf3b1b52e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -46,11 +46,11 @@ static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); */ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) { - u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); + u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); adev->irq.ih.enabled = true; } @@ -63,14 +63,14 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) */ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) { - u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); + u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); /* set rptr, wptr to 0 */ - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); adev->irq.ih.enabled = false; adev->irq.ih.rptr = 0; } @@ -102,15 +102,15 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) else nbio_v6_1_ih_control(adev); - ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); + ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ if (adev->irq.ih.use_bus_addr) { - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.rb_dma_addr >> 8); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1); } else { - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.gpu_addr >> 8); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), (adev->irq.ih.gpu_addr >> 40) & 0xff); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4); } rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); @@ -126,21 +126,21 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) if (adev->irq.msi_enabled) ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); /* set the writeback address whether it's enabled or not */ if (adev->irq.ih.use_bus_addr) wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); else wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO), lower_32_bits(wptr_off)); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI), upper_32_bits(wptr_off) & 0xFF); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); /* set rptr, wptr to 0 */ - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); - ih_doorbell_rtpr = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR)); + ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR); if (adev->irq.ih.use_doorbell) { ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, OFFSET, adev->irq.ih.doorbell_index); @@ -150,20 +150,20 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, ENABLE, 0); } - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR), ih_doorbell_rtpr); + WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); if (adev->flags & AMD_IS_APU) nbio_v7_0_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); else nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); - tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL)); + tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, CLIENT18_IS_STORM_CLIENT, 1); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL), tmp); + WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); - tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL)); + tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL), tmp); + WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); pci_set_master(adev->pdev); @@ -367,7 +367,7 @@ static void vega10_ih_set_rptr(struct amdgpu_device *adev) adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); } else { - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), adev->irq.ih.rptr); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr); } } -- GitLab From c5835bbb1195996c6c5bf2bf2cdbae08c936fc93 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 27 Oct 2017 15:43:14 +0200 Subject: [PATCH 0633/2547] drm/amdgpu: rename amdgpu_ttm_bind to amdgpu_ttm_alloc_gart MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We actually don't bind here, but rather allocate GART space if necessary. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 43df84c13f21..bc3a7500fbbd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -684,7 +684,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, if (!r && p->uf_entry.robj) { struct amdgpu_bo *uf = p->uf_entry.robj; - r = amdgpu_ttm_bind(&uf->tbo); + r = amdgpu_ttm_alloc_gart(&uf->tbo); p->job->uf_addr += amdgpu_bo_gpu_offset(uf); } @@ -1601,5 +1601,5 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, return r; } - return amdgpu_ttm_bind(&(*bo)->tbo); + return amdgpu_ttm_alloc_gart(&(*bo)->tbo); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index ff6f842655d1..a937c49590a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -688,7 +688,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, goto error; } - r = amdgpu_ttm_bind(&bo->tbo); + r = amdgpu_ttm_alloc_gart(&bo->tbo); if (unlikely(r)) { dev_err(adev->dev, "%p bind failed\n", bo); goto error; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 34dbe7afb600..793f41dd4ee4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -875,7 +875,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, return r; } -int amdgpu_ttm_bind(struct ttm_buffer_object *bo) +int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct ttm_mem_reg tmp; @@ -1601,7 +1601,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, } if (bo->tbo.mem.mem_type == TTM_PL_TT) { - r = amdgpu_ttm_bind(&bo->tbo); + r = amdgpu_ttm_alloc_gart(&bo->tbo); if (r) return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index d2985def4168..4f9433e61406 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -91,7 +91,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, struct dma_fence **fence); int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); -int amdgpu_ttm_bind(struct ttm_buffer_object *bo); +int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); -- GitLab From 40575732b6a2ad6430ad8056dabe4cdc01224534 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 26 Oct 2017 17:54:12 +0200 Subject: [PATCH 0634/2547] drm/amdgpu: don't use ttm_bo_move_ttm in amdgpu_ttm_bind v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Just allocate the GART space and fill it. This prevents forcing the BO to be idle. v2: don't unbind/bind at all, just fill the allocated GART space Signed-off-by: Christian König Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 793f41dd4ee4..44983d16bf61 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -878,9 +878,11 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); + struct amdgpu_ttm_tt *gtt = (void*)bo->ttm; struct ttm_mem_reg tmp; struct ttm_placement placement; struct ttm_place placements; + uint64_t flags; int r; if (bo->mem.mem_type != TTM_PL_TT || @@ -902,14 +904,21 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) if (unlikely(r)) return r; - r = ttm_bo_move_ttm(bo, true, false, &tmp); - if (unlikely(r)) + flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); + gtt->offset = (u64)tmp.start << PAGE_SHIFT; + r = amdgpu_gart_bind(adev, gtt->offset, bo->ttm->num_pages, + bo->ttm->pages, gtt->ttm.dma_address, flags); + if (unlikely(r)) { ttm_bo_mem_put(bo, &tmp); - else - bo->offset = (bo->mem.start << PAGE_SHIFT) + - bo->bdev->man[bo->mem.mem_type].gpu_offset; + return r; + } - return r; + ttm_bo_mem_put(bo, &bo->mem); + bo->mem = tmp; + bo->offset = (bo->mem.start << PAGE_SHIFT) + + bo->bdev->man[bo->mem.mem_type].gpu_offset; + + return 0; } int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) -- GitLab From 1884734a03904d23137a075c9b64cd9871af1914 Mon Sep 17 00:00:00 2001 From: pding Date: Mon, 6 Nov 2017 10:21:26 +0800 Subject: [PATCH 0635/2547] drm/amdkfd: initialise kfd inside amdgpu_device_init Also finalize kfd inside amdgpu_device_fini. kfd device_init needs SRIOV exclusive accessing. Try to gather exclusive accessing to reduce time consuming. Signed-off-by: pding Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 5 ----- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 84c8bbec27ce..6636fa25aaf5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1693,6 +1693,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev) if (r) return r; + amdgpu_amdkfd_device_probe(adev); + if (amdgpu_sriov_vf(adev)) { r = amdgpu_virt_request_full_gpu(adev, true); if (r) @@ -1787,6 +1789,7 @@ static int amdgpu_init(struct amdgpu_device *adev) adev->ip_blocks[i].status.hw = true; } + amdgpu_amdkfd_device_init(adev); return 0; } @@ -1854,6 +1857,7 @@ static int amdgpu_fini(struct amdgpu_device *adev) { int i, r; + amdgpu_amdkfd_device_fini(adev); /* need to disable SMC first */ for (i = 0; i < adev->num_ip_blocks; i++) { if (!adev->ip_blocks[i].status.hw) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index f313eee60c4a..252d41d5ff56 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -63,8 +63,6 @@ void amdgpu_driver_unload_kms(struct drm_device *dev) pm_runtime_forbid(dev->dev); } - amdgpu_amdkfd_device_fini(adev); - amdgpu_acpi_fini(adev); amdgpu_device_fini(adev); @@ -170,9 +168,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) "Error during ACPI methods call\n"); } - amdgpu_amdkfd_device_probe(adev); - amdgpu_amdkfd_device_init(adev); - if (amdgpu_device_is_px(dev)) { pm_runtime_use_autosuspend(dev->dev); pm_runtime_set_autosuspend_delay(dev->dev, 5000); -- GitLab From c6332b97fa77bafba2e4c68050090c08c21bff35 Mon Sep 17 00:00:00 2001 From: pding Date: Mon, 6 Nov 2017 11:21:55 +0800 Subject: [PATCH 0636/2547] drm/amdgpu: release exclusive mode after hw_init Signed-off-by: pding Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6636fa25aaf5..ddb50c48cb06 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1790,6 +1790,10 @@ static int amdgpu_init(struct amdgpu_device *adev) } amdgpu_amdkfd_device_init(adev); + + if (amdgpu_sriov_vf(adev)) + amdgpu_virt_release_full_gpu(adev, true); + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 252d41d5ff56..9ed1bee0fd64 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -177,9 +177,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) pm_runtime_put_autosuspend(dev->dev); } - if (amdgpu_sriov_vf(adev)) - amdgpu_virt_release_full_gpu(adev, true); - out: if (r) { /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ -- GitLab From 0c03b912d7f84636766bc26d38df5b21f1c00e94 Mon Sep 17 00:00:00 2001 From: pding Date: Tue, 7 Nov 2017 11:02:00 +0800 Subject: [PATCH 0637/2547] drm/amdgpu: bypass FB resizing for SRIOV VF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It introduces 900ms latency in exclusive mode which causes failure of driver loading. Host can resize the BAR before guest staring, so the resizing is not necessary here. Signed-off-by: Pixel Ding Reviewed-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ddb50c48cb06..05087eda0b71 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -768,6 +768,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) u16 cmd; int r; + /* Bypass for VF */ + if (amdgpu_sriov_vf(adev)) + return 0; + /* Disable memory decoding while we change the BAR addresses and size */ pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); pci_write_config_word(adev->pdev, PCI_COMMAND, -- GitLab From 75bc6099bc619bd58e09d5203081ec9dc5535ec1 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Mon, 30 Oct 2017 20:11:54 +0800 Subject: [PATCH 0638/2547] drm/amdgpu:read VRAMLOST from gim Signed-off-by: Monk Liu Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 +++ 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 05087eda0b71..57267ac265f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3037,11 +3037,10 @@ static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, amdgpu_virt_release_full_gpu(adev, true); if (reset_flags) { - /* will get vram_lost from GIM in future, now all - * reset request considered VRAM LOST - */ - (*reset_flags) |= ~AMDGPU_RESET_INFO_VRAM_LOST; - atomic_inc(&adev->vram_lost_counter); + if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { + (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST; + atomic_inc(&adev->vram_lost_counter); + } /* VF FLR or hotlink reset is always full-reset */ (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 733c64cbd1c8..663bf35cdce9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -334,6 +334,7 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) pf2vf_ver = adev->virt.fw_reserve.p_pf2vf->version; AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size); AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum); + AMDGPU_FW_VRAM_PF2VF_READ(adev, feature_flags, &adev->virt.gim_feature); /* pf2vf message must be in 4K */ if (pf2vf_size > 0 && pf2vf_size < 4096) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index e3f78f5edc00..f77d116c7a1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -81,6 +81,8 @@ enum AMDGIM_FEATURE_FLAG { AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, /* GIM supports feature of loading uCodes */ AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, + /* VRAM LOST by GIM */ + AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, }; struct amdgim_pf2vf_info_header { @@ -246,6 +248,7 @@ struct amdgpu_virt { const struct amdgpu_virt_ops *ops; struct amdgpu_vf_error_buffer vf_errors; struct amdgpu_virt_fw_reserve fw_reserve; + uint32_t gim_feature; }; #define AMDGPU_CSA_SIZE (8 * 1024) -- GitLab From cfb83b1d9c38c29c3c89e8d242b8e7f0148d6c09 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Wed, 8 Nov 2017 14:35:04 +0800 Subject: [PATCH 0639/2547] drm/amdgpu:fix gpu recover missing skipping(v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit if app close CTX right after IB submit, gpu recover will fail to find out the entity behind this guilty job thus lead to no job skipping for this guilty job. to fix this corner case just move the increasement of job->karma out of the entity iteration. v2: only do karma increasment if bad->s_priority != KERNEL because we always consider KERNEL job be correct and always want to recover an unfinished kernel job (sometimes kernel job is interrupted by VF FLR or other GPU hang event) Signed-off-by: Monk Liu Reviewed-by: Christian König Reviewed-By: Xiangliang Yu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 941b5920b97b..53ea7e12d219 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -463,7 +463,8 @@ void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_jo } spin_unlock(&sched->job_list_lock); - if (bad) { + if (bad && bad->s_priority != AMD_SCHED_PRIORITY_KERNEL) { + atomic_inc(&bad->karma); /* don't increase @bad's karma if it's from KERNEL RQ, * becuase sometimes GPU hang would cause kernel jobs (like VM updating jobs) * corrupt but keep in mind that kernel jobs always considered good. @@ -474,7 +475,7 @@ void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_jo spin_lock(&rq->lock); list_for_each_entry_safe(entity, tmp, &rq->entities, list) { if (bad->s_fence->scheduled.context == entity->fence_context) { - if (atomic_inc_return(&bad->karma) > bad->sched->hang_limit) + if (atomic_read(&bad->karma) > bad->sched->hang_limit) if (entity->guilty) atomic_set(entity->guilty, 1); break; -- GitLab From baef9a196f00b30400443fd56455b8ed9a6a4173 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 8 Nov 2017 09:58:59 -0500 Subject: [PATCH 0640/2547] amdgpu/dm: Remove fb_location form fill_plane_attributes We no longer set the framebuffer address here so this is now dead code. Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 550e3bd923b2..3bc314872304 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1787,8 +1787,6 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, const struct amdgpu_framebuffer *amdgpu_fb) { uint64_t tiling_flags; - uint64_t fb_location = 0; - uint64_t chroma_addr = 0; unsigned int awidth; const struct drm_framebuffer *fb = &amdgpu_fb->base; int ret = 0; @@ -1834,8 +1832,6 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS; - plane_state->address.grph.addr.low_part = lower_32_bits(fb_location); - plane_state->address.grph.addr.high_part = upper_32_bits(fb_location); plane_state->plane_size.grph.surface_size.x = 0; plane_state->plane_size.grph.surface_size.y = 0; plane_state->plane_size.grph.surface_size.width = fb->width; @@ -1848,15 +1844,6 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, } else { awidth = ALIGN(fb->width, 64); plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; - plane_state->address.video_progressive.luma_addr.low_part - = lower_32_bits(fb_location); - plane_state->address.video_progressive.luma_addr.high_part - = upper_32_bits(fb_location); - chroma_addr = fb_location + (u64)(awidth * fb->height); - plane_state->address.video_progressive.chroma_addr.low_part - = lower_32_bits(chroma_addr); - plane_state->address.video_progressive.chroma_addr.high_part - = upper_32_bits(chroma_addr); plane_state->plane_size.video.luma_size.x = 0; plane_state->plane_size.video.luma_size.y = 0; plane_state->plane_size.video.luma_size.width = awidth; -- GitLab From 2dc0b46b5ea30f169b0b272253ea846a5a281731 Mon Sep 17 00:00:00 2001 From: David Milburn Date: Tue, 14 Nov 2017 16:17:25 -0600 Subject: [PATCH 0641/2547] libata: sata_down_spd_limit should return if driver has not recorded sstatus speed During hotplug, it is possible for 6Gbps link speed to be limited all the way down to 1.5 Gbps which may lead to a slower link speed when drive is re-connected. This behavior has been seen on a Intel Lewisburg SATA controller (8086:a1d2) with HGST HUH728080ALE600 drive where SATA link speed was limited to 1.5 Gbps and when re-connected the link came up 3.0 Gbps. This patch was retested on above configuration and showed the hotplugged link to come back online at max speed (6Gbps). I did not see the downgrade when testing on Intel C600/X79, but retested patched linux-4.14-rc5 kernel and didn't see any side effects from this change. Also, successfully retested hotplug on port multiplier 3Gbps link. tj: Minor comment updates. Signed-off-by: David Milburn Signed-off-by: Tejun Heo --- drivers/ata/libata-core.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 2a882929de4a..8193b38a1cae 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -3082,13 +3082,19 @@ int sata_down_spd_limit(struct ata_link *link, u32 spd_limit) bit = fls(mask) - 1; mask &= ~(1 << bit); - /* Mask off all speeds higher than or equal to the current - * one. Force 1.5Gbps if current SPD is not available. + /* + * Mask off all speeds higher than or equal to the current one. At + * this point, if current SPD is not available and we previously + * recorded the link speed from SStatus, the driver has already + * masked off the highest bit so mask should already be 1 or 0. + * Otherwise, we should not force 1.5Gbps on a link where we have + * not previously recorded speed from SStatus. Just return in this + * case. */ if (spd > 1) mask &= (1 << (spd - 1)) - 1; else - mask &= 1; + return -EINVAL; /* were we already at the bottom? */ if (!mask) -- GitLab From 11db855c3d06e82f432cb1bafd73296586d5ceec Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Mon, 4 Dec 2017 14:41:11 -0800 Subject: [PATCH 0642/2547] Revert "cpuset: Make cpuset hotplug synchronous" This reverts commit 1599a185f0e6113be185b9fb809c621c73865829. This and the previous commit led to another circular locking scenario and the scenario which is fixed by this commit no longer exists after e8b3f8db7aad ("workqueue/hotplug: simplify workqueue_offline_cpu()") which removes work item flushing from hotplug path. Revert it for now. Signed-off-by: Tejun Heo --- include/linux/cpuset.h | 6 ++++++ kernel/cgroup/cpuset.c | 41 +++++++++++++++++++++-------------------- kernel/power/process.c | 2 ++ kernel/sched/core.c | 1 + 4 files changed, 30 insertions(+), 20 deletions(-) diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h index 2ab910f85154..1b8e41597ef5 100644 --- a/include/linux/cpuset.h +++ b/include/linux/cpuset.h @@ -52,7 +52,9 @@ static inline void cpuset_dec(void) extern int cpuset_init(void); extern void cpuset_init_smp(void); +extern void cpuset_force_rebuild(void); extern void cpuset_update_active_cpus(void); +extern void cpuset_wait_for_hotplug(void); extern void cpuset_cpus_allowed(struct task_struct *p, struct cpumask *mask); extern void cpuset_cpus_allowed_fallback(struct task_struct *p); extern nodemask_t cpuset_mems_allowed(struct task_struct *p); @@ -165,11 +167,15 @@ static inline bool cpusets_enabled(void) { return false; } static inline int cpuset_init(void) { return 0; } static inline void cpuset_init_smp(void) {} +static inline void cpuset_force_rebuild(void) { } + static inline void cpuset_update_active_cpus(void) { partition_sched_domains(1, NULL, NULL); } +static inline void cpuset_wait_for_hotplug(void) { } + static inline void cpuset_cpus_allowed(struct task_struct *p, struct cpumask *mask) { diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c index 227bc25d951d..cab5fd1ee767 100644 --- a/kernel/cgroup/cpuset.c +++ b/kernel/cgroup/cpuset.c @@ -2277,8 +2277,15 @@ static void cpuset_hotplug_update_tasks(struct cpuset *cs) mutex_unlock(&cpuset_mutex); } +static bool force_rebuild; + +void cpuset_force_rebuild(void) +{ + force_rebuild = true; +} + /** - * cpuset_hotplug - handle CPU/memory hotunplug for a cpuset + * cpuset_hotplug_workfn - handle CPU/memory hotunplug for a cpuset * * This function is called after either CPU or memory configuration has * changed and updates cpuset accordingly. The top_cpuset is always @@ -2293,7 +2300,7 @@ static void cpuset_hotplug_update_tasks(struct cpuset *cs) * Note that CPU offlining during suspend is ignored. We don't modify * cpusets across suspend/resume cycles at all. */ -static void cpuset_hotplug(bool use_cpu_hp_lock) +static void cpuset_hotplug_workfn(struct work_struct *work) { static cpumask_t new_cpus; static nodemask_t new_mems; @@ -2351,31 +2358,25 @@ static void cpuset_hotplug(bool use_cpu_hp_lock) } /* rebuild sched domains if cpus_allowed has changed */ - if (cpus_updated) { - if (use_cpu_hp_lock) - rebuild_sched_domains(); - else { - /* Acquiring cpu_hotplug_lock is not required. - * When cpuset_hotplug() is called in hotplug path, - * cpu_hotplug_lock is held by the hotplug context - * which is waiting for cpuhp_thread_fun to indicate - * completion of callback. - */ - mutex_lock(&cpuset_mutex); - rebuild_sched_domains_cpuslocked(); - mutex_unlock(&cpuset_mutex); - } + if (cpus_updated || force_rebuild) { + force_rebuild = false; + rebuild_sched_domains(); } } -static void cpuset_hotplug_workfn(struct work_struct *work) +void cpuset_update_active_cpus(void) { - cpuset_hotplug(true); + /* + * We're inside cpu hotplug critical region which usually nests + * inside cgroup synchronization. Bounce actual hotplug processing + * to a work item to avoid reverse locking order. + */ + schedule_work(&cpuset_hotplug_work); } -void cpuset_update_active_cpus(void) +void cpuset_wait_for_hotplug(void) { - cpuset_hotplug(false); + flush_work(&cpuset_hotplug_work); } /* diff --git a/kernel/power/process.c b/kernel/power/process.c index c326d7235c5f..7381d49a44db 100644 --- a/kernel/power/process.c +++ b/kernel/power/process.c @@ -204,6 +204,8 @@ void thaw_processes(void) __usermodehelper_set_disable_depth(UMH_FREEZING); thaw_workqueues(); + cpuset_wait_for_hotplug(); + read_lock(&tasklist_lock); for_each_process_thread(g, p) { /* No other threads should have PF_SUSPEND_TASK set */ diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 88b3450b29ab..75554f366fd3 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5624,6 +5624,7 @@ static void cpuset_cpu_active(void) * restore the original sched domains by considering the * cpuset configurations. */ + cpuset_force_rebuild(); } cpuset_update_active_cpus(); } -- GitLab From e8b3f8db7aad99fcc5234fc5b89984ff6620de3d Mon Sep 17 00:00:00 2001 From: Lai Jiangshan Date: Fri, 1 Dec 2017 22:20:36 +0800 Subject: [PATCH 0643/2547] workqueue/hotplug: simplify workqueue_offline_cpu() Since the recent cpu/hotplug refactoring, workqueue_offline_cpu() is guaranteed to run on the local cpu which is going offline. This also fixes the following deadlock by removing work item scheduling and flushing from CPU hotplug path. http://lkml.kernel.org/r/1504764252-29091-1-git-send-email-prsood@codeaurora.org tj: Description update. Signed-off-by: Lai Jiangshan Signed-off-by: Tejun Heo --- kernel/workqueue.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/kernel/workqueue.c b/kernel/workqueue.c index 6a5658cb46da..48a4d00f55dc 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -1635,7 +1635,7 @@ static void worker_enter_idle(struct worker *worker) mod_timer(&pool->idle_timer, jiffies + IDLE_WORKER_TIMEOUT); /* - * Sanity check nr_running. Because wq_unbind_fn() releases + * Sanity check nr_running. Because unbind_workers() releases * pool->lock between setting %WORKER_UNBOUND and zapping * nr_running, the warning may trigger spuriously. Check iff * unbind is not in progress. @@ -4511,9 +4511,8 @@ void show_workqueue_state(void) * cpu comes back online. */ -static void wq_unbind_fn(struct work_struct *work) +static void unbind_workers(int cpu) { - int cpu = smp_processor_id(); struct worker_pool *pool; struct worker *worker; @@ -4710,12 +4709,13 @@ int workqueue_online_cpu(unsigned int cpu) int workqueue_offline_cpu(unsigned int cpu) { - struct work_struct unbind_work; struct workqueue_struct *wq; /* unbinding per-cpu workers should happen on the local CPU */ - INIT_WORK_ONSTACK(&unbind_work, wq_unbind_fn); - queue_work_on(cpu, system_highpri_wq, &unbind_work); + if (WARN_ON(cpu != smp_processor_id())) + return -1; + + unbind_workers(cpu); /* update NUMA affinity of unbound workqueues */ mutex_lock(&wq_pool_mutex); @@ -4723,9 +4723,6 @@ int workqueue_offline_cpu(unsigned int cpu) wq_update_unbound_numa(wq, cpu, false); mutex_unlock(&wq_pool_mutex); - /* wait for per-cpu unbinding to finish */ - flush_work(&unbind_work); - destroy_work_on_stack(&unbind_work); return 0; } -- GitLab From 62408c1ef00784e8bcfc4848ade76480fb8aed21 Mon Sep 17 00:00:00 2001 From: Lai Jiangshan Date: Fri, 1 Dec 2017 22:23:07 +0800 Subject: [PATCH 0644/2547] workqueue/hotplug: remove the workaround in rebind_workers() Since the cpu/hotplug refactoring, DOWN_FAILED is never called without preceding DOWN_PREPARE making the workaround unnecessary. Remove it. Signed-off-by: Lai Jiangshan Signed-off-by: Tejun Heo --- kernel/workqueue.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/kernel/workqueue.c b/kernel/workqueue.c index 48a4d00f55dc..45ce93f3dd1f 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -4589,16 +4589,6 @@ static void rebind_workers(struct worker_pool *pool) spin_lock_irq(&pool->lock); - /* - * XXX: CPU hotplug notifiers are weird and can call DOWN_FAILED - * w/o preceding DOWN_PREPARE. Work around it. CPU hotplug is - * being reworked and this can go away in time. - */ - if (!(pool->flags & POOL_DISASSOCIATED)) { - spin_unlock_irq(&pool->lock); - return; - } - pool->flags &= ~POOL_DISASSOCIATED; for_each_pool_worker(worker, pool) { -- GitLab From bdfbbda90aeb75ce0951413fd7f495d4d377bd5e Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Mon, 4 Dec 2017 14:55:59 -0800 Subject: [PATCH 0645/2547] Revert "cgroup/cpuset: remove circular dependency deadlock" This reverts commit aa24163b2ee5c92120e32e99b5a93143a0f4258e. This and the following commit led to another circular locking scenario and the scenario which is fixed by this commit no longer exists after e8b3f8db7aad ("workqueue/hotplug: simplify workqueue_offline_cpu()") which removes work item flushing from hotplug path. Revert it for now. Signed-off-by: Tejun Heo --- kernel/cgroup/cpuset.c | 53 ++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 30 deletions(-) diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c index cab5fd1ee767..f7efa7b4d825 100644 --- a/kernel/cgroup/cpuset.c +++ b/kernel/cgroup/cpuset.c @@ -812,18 +812,6 @@ static int generate_sched_domains(cpumask_var_t **domains, return ndoms; } -static void cpuset_sched_change_begin(void) -{ - cpus_read_lock(); - mutex_lock(&cpuset_mutex); -} - -static void cpuset_sched_change_end(void) -{ - mutex_unlock(&cpuset_mutex); - cpus_read_unlock(); -} - /* * Rebuild scheduler domains. * @@ -833,14 +821,16 @@ static void cpuset_sched_change_end(void) * 'cpus' is removed, then call this routine to rebuild the * scheduler's dynamic sched domains. * + * Call with cpuset_mutex held. Takes get_online_cpus(). */ -static void rebuild_sched_domains_cpuslocked(void) +static void rebuild_sched_domains_locked(void) { struct sched_domain_attr *attr; cpumask_var_t *doms; int ndoms; lockdep_assert_held(&cpuset_mutex); + get_online_cpus(); /* * We have raced with CPU hotplug. Don't do anything to avoid @@ -848,25 +838,27 @@ static void rebuild_sched_domains_cpuslocked(void) * Anyways, hotplug work item will rebuild sched domains. */ if (!cpumask_equal(top_cpuset.effective_cpus, cpu_active_mask)) - return; + goto out; /* Generate domain masks and attrs */ ndoms = generate_sched_domains(&doms, &attr); /* Have scheduler rebuild the domains */ partition_sched_domains(ndoms, doms, attr); +out: + put_online_cpus(); } #else /* !CONFIG_SMP */ -static void rebuild_sched_domains_cpuslocked(void) +static void rebuild_sched_domains_locked(void) { } #endif /* CONFIG_SMP */ void rebuild_sched_domains(void) { - cpuset_sched_change_begin(); - rebuild_sched_domains_cpuslocked(); - cpuset_sched_change_end(); + mutex_lock(&cpuset_mutex); + rebuild_sched_domains_locked(); + mutex_unlock(&cpuset_mutex); } /** @@ -952,7 +944,7 @@ static void update_cpumasks_hier(struct cpuset *cs, struct cpumask *new_cpus) rcu_read_unlock(); if (need_rebuild_sched_domains) - rebuild_sched_domains_cpuslocked(); + rebuild_sched_domains_locked(); } /** @@ -1284,7 +1276,7 @@ static int update_relax_domain_level(struct cpuset *cs, s64 val) cs->relax_domain_level = val; if (!cpumask_empty(cs->cpus_allowed) && is_sched_load_balance(cs)) - rebuild_sched_domains_cpuslocked(); + rebuild_sched_domains_locked(); } return 0; @@ -1317,6 +1309,7 @@ static void update_tasks_flags(struct cpuset *cs) * * Call with cpuset_mutex held. */ + static int update_flag(cpuset_flagbits_t bit, struct cpuset *cs, int turning_on) { @@ -1349,7 +1342,7 @@ static int update_flag(cpuset_flagbits_t bit, struct cpuset *cs, spin_unlock_irq(&callback_lock); if (!cpumask_empty(trialcs->cpus_allowed) && balance_flag_changed) - rebuild_sched_domains_cpuslocked(); + rebuild_sched_domains_locked(); if (spread_flag_changed) update_tasks_flags(cs); @@ -1617,7 +1610,7 @@ static int cpuset_write_u64(struct cgroup_subsys_state *css, struct cftype *cft, cpuset_filetype_t type = cft->private; int retval = 0; - cpuset_sched_change_begin(); + mutex_lock(&cpuset_mutex); if (!is_cpuset_online(cs)) { retval = -ENODEV; goto out_unlock; @@ -1653,7 +1646,7 @@ static int cpuset_write_u64(struct cgroup_subsys_state *css, struct cftype *cft, break; } out_unlock: - cpuset_sched_change_end(); + mutex_unlock(&cpuset_mutex); return retval; } @@ -1664,7 +1657,7 @@ static int cpuset_write_s64(struct cgroup_subsys_state *css, struct cftype *cft, cpuset_filetype_t type = cft->private; int retval = -ENODEV; - cpuset_sched_change_begin(); + mutex_lock(&cpuset_mutex); if (!is_cpuset_online(cs)) goto out_unlock; @@ -1677,7 +1670,7 @@ static int cpuset_write_s64(struct cgroup_subsys_state *css, struct cftype *cft, break; } out_unlock: - cpuset_sched_change_end(); + mutex_unlock(&cpuset_mutex); return retval; } @@ -1716,7 +1709,7 @@ static ssize_t cpuset_write_resmask(struct kernfs_open_file *of, kernfs_break_active_protection(of->kn); flush_work(&cpuset_hotplug_work); - cpuset_sched_change_begin(); + mutex_lock(&cpuset_mutex); if (!is_cpuset_online(cs)) goto out_unlock; @@ -1740,7 +1733,7 @@ static ssize_t cpuset_write_resmask(struct kernfs_open_file *of, free_trial_cpuset(trialcs); out_unlock: - cpuset_sched_change_end(); + mutex_unlock(&cpuset_mutex); kernfs_unbreak_active_protection(of->kn); css_put(&cs->css); flush_workqueue(cpuset_migrate_mm_wq); @@ -2041,14 +2034,14 @@ static int cpuset_css_online(struct cgroup_subsys_state *css) /* * If the cpuset being removed has its flag 'sched_load_balance' * enabled, then simulate turning sched_load_balance off, which - * will call rebuild_sched_domains_cpuslocked(). + * will call rebuild_sched_domains_locked(). */ static void cpuset_css_offline(struct cgroup_subsys_state *css) { struct cpuset *cs = css_cs(css); - cpuset_sched_change_begin(); + mutex_lock(&cpuset_mutex); if (is_sched_load_balance(cs)) update_flag(CS_SCHED_LOAD_BALANCE, cs, 0); @@ -2056,7 +2049,7 @@ static void cpuset_css_offline(struct cgroup_subsys_state *css) cpuset_dec(); clear_bit(CS_ONLINE, &cs->flags); - cpuset_sched_change_end(); + mutex_unlock(&cpuset_mutex); } static void cpuset_css_free(struct cgroup_subsys_state *css) -- GitLab From ba69ead9e9e9bb3cec5faf03526c36764ac8942a Mon Sep 17 00:00:00 2001 From: Martin Wilck Date: Mon, 27 Nov 2017 23:47:34 +0100 Subject: [PATCH 0646/2547] scsi: scsi_devinfo: handle non-terminated strings devinfo->vendor and devinfo->model aren't necessarily zero-terminated. Fixes: b8018b973c7c "scsi_devinfo: fixup string compare" Signed-off-by: Martin Wilck Reviewed-by: Bart Van Assche Signed-off-by: Martin K. Petersen --- drivers/scsi/scsi_devinfo.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/scsi_devinfo.c b/drivers/scsi/scsi_devinfo.c index 78d4aa8df675..b256d4cbd3ad 100644 --- a/drivers/scsi/scsi_devinfo.c +++ b/drivers/scsi/scsi_devinfo.c @@ -458,7 +458,8 @@ static struct scsi_dev_info_list *scsi_dev_info_list_find(const char *vendor, /* * vendor strings must be an exact match */ - if (vmax != strlen(devinfo->vendor) || + if (vmax != strnlen(devinfo->vendor, + sizeof(devinfo->vendor)) || memcmp(devinfo->vendor, vskip, vmax)) continue; @@ -466,7 +467,7 @@ static struct scsi_dev_info_list *scsi_dev_info_list_find(const char *vendor, * @model specifies the full string, and * must be larger or equal to devinfo->model */ - mlen = strlen(devinfo->model); + mlen = strnlen(devinfo->model, sizeof(devinfo->model)); if (mmax < mlen || memcmp(devinfo->model, mskip, mlen)) continue; return devinfo; -- GitLab From 81df022b688d43d2a3667518b2f755d384397910 Mon Sep 17 00:00:00 2001 From: Martin Wilck Date: Mon, 27 Nov 2017 23:47:35 +0100 Subject: [PATCH 0647/2547] scsi: scsi_devinfo: cleanly zero-pad devinfo strings Cleanly fill memory for "vendor" and "model" with 0-bytes for the "compatible" case rather than adding only a single 0 byte. This simplifies the devinfo code a a bit, and avoids mistakes in other places of the code (not in current upstream, but we had one such mistake in the SUSE kernel). [mkp: applied by hand and added braces] Signed-off-by: Martin Wilck Reviewed-by: Bart Van Assche Signed-off-by: Martin K. Petersen --- drivers/scsi/scsi_devinfo.c | 22 +++++++--------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/drivers/scsi/scsi_devinfo.c b/drivers/scsi/scsi_devinfo.c index b256d4cbd3ad..449ef5adbb2b 100644 --- a/drivers/scsi/scsi_devinfo.c +++ b/drivers/scsi/scsi_devinfo.c @@ -34,7 +34,6 @@ struct scsi_dev_info_list_table { }; -static const char spaces[] = " "; /* 16 of them */ static blist_flags_t scsi_default_dev_flags; static LIST_HEAD(scsi_dev_info_list); static char scsi_dev_flags[256]; @@ -298,20 +297,13 @@ static void scsi_strcpy_devinfo(char *name, char *to, size_t to_length, size_t from_length; from_length = strlen(from); - strncpy(to, from, min(to_length, from_length)); - if (from_length < to_length) { - if (compatible) { - /* - * NUL terminate the string if it is short. - */ - to[from_length] = '\0'; - } else { - /* - * space pad the string if it is short. - */ - strncpy(&to[from_length], spaces, - to_length - from_length); - } + /* This zero-pads the destination */ + strncpy(to, from, to_length); + if (from_length < to_length && !compatible) { + /* + * space pad the string if it is short. + */ + memset(&to[from_length], ' ', to_length - from_length); } if (from_length > to_length) printk(KERN_WARNING "%s: %s string '%s' is too long\n", -- GitLab From f745e9cc7e40c4570ab5e8d5ef32bfaa6e8ced46 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Mon, 4 Dec 2017 16:48:18 +0000 Subject: [PATCH 0648/2547] drm/i915/gvt: Add missing breaks in switch statement The switch statement is missing breaks for the cases of GVT_FAILSAFE_INSUFFICIENT_RESOURCE and GVT_FAILSAFE_GUEST_ERR. Add them in. Detected by CoverityScan, CID#1462416 ("Missing break in switch") Fixes: e011c6ce2b4f ("drm/i915/gvt: Add VM healthy check for workload_thread") Fixes: a33fc7a0482a ("drm/i915/gvt: enter failsafe mode when guest requires more resources") Signed-off-by: Colin Ian King Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/handlers.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 880448d4adc7..54f5eac8bcc3 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -174,8 +174,10 @@ void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) break; case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: pr_err("Graphics resource is not enough for the guest\n"); + break; case GVT_FAILSAFE_GUEST_ERR: pr_err("GVT Internal error for the guest\n"); + break; default: break; } -- GitLab From 8e60b7f195d2536b2f090ae97f74ed19a504d60c Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Mon, 4 Dec 2017 17:21:06 +0000 Subject: [PATCH 0649/2547] drm/i915/gvt: fix off-by-one comparison of ring_id The ring_id maximum boundary is being compared using the > operator instead of >=, leading to an off-by-one error and an out of bounds write into array vgpu->hws_pga[]. Fix this by simply using the correct comparison operator. Also re-work another comparison that uses the comparison > I915_NUM_ENGINES - 1 to use the >= idiom using to keep this consistent in this code. Detected by CoverityScan, CID#1462404 ("Out-of-bounds write") Fixes: a2ae95af9646 ("drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP") Signed-off-by: Colin Ian King Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/handlers.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 54f5eac8bcc3..6f95bc04f0f0 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1398,7 +1398,7 @@ static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, * update the VM CSB status correctly. Here listed registers can * support BDW, SKL or other platforms with same HWSP registers. */ - if (unlikely(ring_id < 0 || ring_id > I915_NUM_ENGINES)) { + if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) { gvt_vgpu_err("VM(%d) access unknown hardware status page register:0x%x\n", vgpu->id, offset); return -EINVAL; @@ -1507,7 +1507,7 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, u32 data = *(u32 *)p_data; int ret = 0; - if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1)) + if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) return -EINVAL; execlist = &vgpu->submission.execlist[ring_id]; -- GitLab From edfb8d8fcb94a75b2e61c63549d4a5f6474ad3d2 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Tue, 28 Nov 2017 16:11:29 +0200 Subject: [PATCH 0650/2547] s390/virtio: add BSD license to virtio-ccw The original intent of the virtio header relicensing from 2008 was to make sure anyone can implement compatible devices/drivers. The virtio-ccw was omitted by mistake. We have an ack from the only contributor as well as the maintainer from IBM, so it's not too late to fix that. Make it dual-licensed with GPLv2, as the whole kernel is GPL2. Acked-by: Christian Borntraeger Acked-by: Cornelia Huck Signed-off-by: Michael S. Tsirkin Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky --- arch/s390/include/uapi/asm/virtio-ccw.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/s390/include/uapi/asm/virtio-ccw.h b/arch/s390/include/uapi/asm/virtio-ccw.h index 3a77833c74dc..2b605f7e8483 100644 --- a/arch/s390/include/uapi/asm/virtio-ccw.h +++ b/arch/s390/include/uapi/asm/virtio-ccw.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ /* * Definitions for virtio-ccw devices. * -- GitLab From 0b926ac304a9b315f0ce8ce2ae5373b5a0478b68 Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Mon, 23 Oct 2017 09:40:16 +0200 Subject: [PATCH 0651/2547] s390/qdio: consider ERROR buffers for inbound-full condition In the unlikely case that an ERROR buffer (presented by the HW) consumed the last available slot on the input queue, increment the corresponding statistics counter. Signed-off-by: Julian Wiedmann Reviewed-by: Benjamin Block Signed-off-by: Martin Schwidefsky --- drivers/s390/cio/qdio_main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index 59b4a3370cd5..d681e6b56add 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -536,7 +536,8 @@ static int get_inbound_buffer_frontier(struct qdio_q *q) case SLSB_P_INPUT_ERROR: process_buffer_error(q, count); q->first_to_check = add_buf(q->first_to_check, count); - atomic_sub(count, &q->nr_buf_used); + if (atomic_sub_return(count, &q->nr_buf_used) == 0) + qperf_inc(q, inbound_queue_full); if (q->irq_ptr->perf_stat_enabled) account_sbals_error(q, count); break; -- GitLab From b23481fbfc567fea256a69b307ced283c56aba99 Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Mon, 23 Oct 2017 09:38:18 +0200 Subject: [PATCH 0652/2547] s390/qdio: restrict target-full handling to IQDIO The 'no target buffer empty' error code only applies to HiperSockets. If this code is reported on a different queue type, be sure to make the same amount of noise as for any other error code. Signed-off-by: Julian Wiedmann Reviewed-by: Benjamin Block Signed-off-by: Martin Schwidefsky --- drivers/s390/cio/qdio_main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index d681e6b56add..95b0efe28afb 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -431,8 +431,8 @@ static void process_buffer_error(struct qdio_q *q, int count) q->qdio_error = QDIO_ERROR_SLSB_STATE; /* special handling for no target buffer empty */ - if ((!q->is_input_q && - (q->sbal[q->first_to_check]->element[15].sflags) == 0x10)) { + if (queue_type(q) == QDIO_IQDIO_QFMT && !q->is_input_q && + q->sbal[q->first_to_check]->element[15].sflags == 0x10) { qperf_inc(q, target_full); DBF_DEV_EVENT(DBF_INFO, q->irq_ptr, "OUTFULL FTC:%02x", q->first_to_check); -- GitLab From bd7a9b3757895c3a2fd64b3f12e438d9190c83d9 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 27 Nov 2017 12:46:57 +0100 Subject: [PATCH 0653/2547] s390/dasd: remove 'struct timespec' usage getnstimeofday() and timespec are deprecated since they can overflow on 32-bit architectures. This simply changes to the explicitly typed timespec64 version that doesn't have that problem. It would be nice to also convert to monotonic timestamps and call ktime_get_ts64() rather than ktime_get_real_ts64(), but that would be a user-visible change. Signed-off-by: Arnd Bergmann Signed-off-by: Stefan Haberland Signed-off-by: Martin Schwidefsky --- drivers/s390/block/dasd.c | 10 +++++----- drivers/s390/block/dasd_int.h | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/s390/block/dasd.c b/drivers/s390/block/dasd.c index 66e008f7adb6..d4e8dff673cc 100644 --- a/drivers/s390/block/dasd.c +++ b/drivers/s390/block/dasd.c @@ -759,7 +759,7 @@ static void dasd_profile_end_add_data(struct dasd_profile_info *data, /* in case of an overflow, reset the whole profile */ if (data->dasd_io_reqs == UINT_MAX) { memset(data, 0, sizeof(*data)); - getnstimeofday(&data->starttod); + ktime_get_real_ts64(&data->starttod); } data->dasd_io_reqs++; data->dasd_io_sects += sectors; @@ -894,7 +894,7 @@ void dasd_profile_reset(struct dasd_profile *profile) return; } memset(data, 0, sizeof(*data)); - getnstimeofday(&data->starttod); + ktime_get_real_ts64(&data->starttod); spin_unlock_bh(&profile->lock); } @@ -911,7 +911,7 @@ int dasd_profile_on(struct dasd_profile *profile) kfree(data); return 0; } - getnstimeofday(&data->starttod); + ktime_get_real_ts64(&data->starttod); profile->data = data; spin_unlock_bh(&profile->lock); return 0; @@ -995,8 +995,8 @@ static void dasd_stats_array(struct seq_file *m, unsigned int *array) static void dasd_stats_seq_print(struct seq_file *m, struct dasd_profile_info *data) { - seq_printf(m, "start_time %ld.%09ld\n", - data->starttod.tv_sec, data->starttod.tv_nsec); + seq_printf(m, "start_time %lld.%09ld\n", + (s64)data->starttod.tv_sec, data->starttod.tv_nsec); seq_printf(m, "total_requests %u\n", data->dasd_io_reqs); seq_printf(m, "total_sectors %u\n", data->dasd_io_sects); seq_printf(m, "total_pav %u\n", data->dasd_io_alias); diff --git a/drivers/s390/block/dasd_int.h b/drivers/s390/block/dasd_int.h index b095a23bcc0c..96709b1a7bf8 100644 --- a/drivers/s390/block/dasd_int.h +++ b/drivers/s390/block/dasd_int.h @@ -441,7 +441,7 @@ struct dasd_profile_info { unsigned int dasd_io_nr_req[32]; /* hist. of # of requests in chanq */ /* new data */ - struct timespec starttod; /* time of start or last reset */ + struct timespec64 starttod; /* time of start or last reset */ unsigned int dasd_io_alias; /* requests using an alias */ unsigned int dasd_io_tpm; /* requests using transport mode */ unsigned int dasd_read_reqs; /* total number of read requests */ -- GitLab From fbbd7f1a51965b50dd12924841da0d478f3da71b Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Mon, 20 Nov 2017 12:38:44 +0100 Subject: [PATCH 0654/2547] s390: always save and restore all registers on context switch The switch_to() macro has an optimization to avoid saving and restoring register contents that aren't needed for kernel threads. There is however the possibility that a kernel thread execve's a user space program. In such a case the execve'd process can partially see the contents of the previous process, which shouldn't be allowed. To avoid this, simply always save and restore register contents on context switch. Cc: # v2.6.37+ Fixes: fdb6d070effba ("switch_to: dont restore/save access & fpu regs for kernel threads") Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky --- arch/s390/include/asm/switch_to.h | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/arch/s390/include/asm/switch_to.h b/arch/s390/include/asm/switch_to.h index ec7b476c1ac5..c61b2cc1a8a8 100644 --- a/arch/s390/include/asm/switch_to.h +++ b/arch/s390/include/asm/switch_to.h @@ -30,21 +30,20 @@ static inline void restore_access_regs(unsigned int *acrs) asm volatile("lam 0,15,%0" : : "Q" (*(acrstype *)acrs)); } -#define switch_to(prev,next,last) do { \ - if (prev->mm) { \ - save_fpu_regs(); \ - save_access_regs(&prev->thread.acrs[0]); \ - save_ri_cb(prev->thread.ri_cb); \ - save_gs_cb(prev->thread.gs_cb); \ - } \ +#define switch_to(prev, next, last) do { \ + /* save_fpu_regs() sets the CIF_FPU flag, which enforces \ + * a restore of the floating point / vector registers as \ + * soon as the next task returns to user space \ + */ \ + save_fpu_regs(); \ + save_access_regs(&prev->thread.acrs[0]); \ + save_ri_cb(prev->thread.ri_cb); \ + save_gs_cb(prev->thread.gs_cb); \ update_cr_regs(next); \ - if (next->mm) { \ - set_cpu_flag(CIF_FPU); \ - restore_access_regs(&next->thread.acrs[0]); \ - restore_ri_cb(next->thread.ri_cb, prev->thread.ri_cb); \ - restore_gs_cb(next->thread.gs_cb); \ - } \ - prev = __switch_to(prev,next); \ + restore_access_regs(&next->thread.acrs[0]); \ + restore_ri_cb(next->thread.ri_cb, prev->thread.ri_cb); \ + restore_gs_cb(next->thread.gs_cb); \ + prev = __switch_to(prev, next); \ } while (0) #endif /* __ASM_SWITCH_TO_H */ -- GitLab From da340f921d3454f1521671c7a5a43ad3331fbe50 Mon Sep 17 00:00:00 2001 From: Stefan Haberland Date: Thu, 26 Oct 2017 14:37:35 +0200 Subject: [PATCH 0655/2547] s390/dasd: prevent prefix I/O error Prevent that a prefix flag is set based on invalid configuration data. The validity.verify_base flag should only be set for alias devices. Usually the unit address type is either one of base, PAV alias or HyperPAV alias. But in cases where the unit address type is not set or any other value the validity.verify_base flag might be set as well. This would lead to follow on errors. Explicitly check for alias devices and set the validity flag only for them. Signed-off-by: Stefan Haberland Reviewed-by: Jan Hoeppner Signed-off-by: Martin Schwidefsky --- drivers/s390/block/dasd_eckd.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/s390/block/dasd_eckd.c b/drivers/s390/block/dasd_eckd.c index 1a41ef496338..a2edf2a7ace9 100644 --- a/drivers/s390/block/dasd_eckd.c +++ b/drivers/s390/block/dasd_eckd.c @@ -531,10 +531,12 @@ static int prefix_LRE(struct ccw1 *ccw, struct PFX_eckd_data *pfxdata, pfxdata->validity.define_extent = 1; /* private uid is kept up to date, conf_data may be outdated */ - if (startpriv->uid.type != UA_BASE_DEVICE) { + if (startpriv->uid.type == UA_BASE_PAV_ALIAS) pfxdata->validity.verify_base = 1; - if (startpriv->uid.type == UA_HYPER_PAV_ALIAS) - pfxdata->validity.hyper_pav = 1; + + if (startpriv->uid.type == UA_HYPER_PAV_ALIAS) { + pfxdata->validity.verify_base = 1; + pfxdata->validity.hyper_pav = 1; } rc = define_extent(NULL, dedata, trk, totrk, cmd, basedev, blksize); @@ -3415,10 +3417,12 @@ static int prepare_itcw(struct itcw *itcw, pfxdata.validity.define_extent = 1; /* private uid is kept up to date, conf_data may be outdated */ - if (startpriv->uid.type != UA_BASE_DEVICE) { + if (startpriv->uid.type == UA_BASE_PAV_ALIAS) + pfxdata.validity.verify_base = 1; + + if (startpriv->uid.type == UA_HYPER_PAV_ALIAS) { pfxdata.validity.verify_base = 1; - if (startpriv->uid.type == UA_HYPER_PAV_ALIAS) - pfxdata.validity.hyper_pav = 1; + pfxdata.validity.hyper_pav = 1; } switch (cmd) { -- GitLab From 9fa1db4c7511543c951128758f358cd7aad99628 Mon Sep 17 00:00:00 2001 From: Martin Schwidefsky Date: Mon, 4 Dec 2017 10:39:38 +0100 Subject: [PATCH 0656/2547] s390: add a few more SPDX identifiers Add the correct SPDX license to a few more files under arch/s390 and drivers/s390 which have been missed to far. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. Signed-off-by: Martin Schwidefsky --- arch/s390/Kbuild | 1 + arch/s390/appldata/Makefile | 1 + arch/s390/boot/compressed/vmlinux.scr | 1 + arch/s390/crypto/sha1_s390.c | 1 + arch/s390/hypfs/Makefile | 1 + arch/s390/include/asm/Kbuild | 1 + arch/s390/include/asm/alternative.h | 1 + arch/s390/include/asm/ap.h | 1 + arch/s390/include/asm/bugs.h | 1 + arch/s390/include/asm/segment.h | 1 + arch/s390/include/asm/vga.h | 1 + arch/s390/include/uapi/asm/Kbuild | 1 + arch/s390/include/uapi/asm/perf_regs.h | 1 + arch/s390/include/uapi/asm/sthyi.h | 1 + arch/s390/include/uapi/asm/vmcp.h | 1 + arch/s390/kernel/alternative.c | 1 + arch/s390/kernel/perf_regs.c | 1 + arch/s390/kernel/vdso64/note.S | 1 + arch/s390/net/Makefile | 1 + arch/s390/numa/Makefile | 1 + arch/s390/pci/Makefile | 1 + arch/s390/tools/gen_opcode_table.c | 1 + drivers/s390/Makefile | 1 + drivers/s390/block/Kconfig | 1 + drivers/s390/char/Kconfig | 1 + drivers/s390/char/defkeymap.map | 1 + drivers/s390/cio/blacklist.h | 1 + drivers/s390/net/Kconfig | 1 + drivers/s390/scsi/Makefile | 1 + 29 files changed, 29 insertions(+) diff --git a/arch/s390/Kbuild b/arch/s390/Kbuild index eae2c64cf69d..9fdff3fe1a42 100644 --- a/arch/s390/Kbuild +++ b/arch/s390/Kbuild @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 obj-y += kernel/ obj-y += mm/ obj-$(CONFIG_KVM) += kvm/ diff --git a/arch/s390/appldata/Makefile b/arch/s390/appldata/Makefile index 99f1cf071304..b06def4a4f2f 100644 --- a/arch/s390/appldata/Makefile +++ b/arch/s390/appldata/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # # Makefile for the Linux - z/VM Monitor Stream. # diff --git a/arch/s390/boot/compressed/vmlinux.scr b/arch/s390/boot/compressed/vmlinux.scr index f02382ae5c48..42a242597f34 100644 --- a/arch/s390/boot/compressed/vmlinux.scr +++ b/arch/s390/boot/compressed/vmlinux.scr @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ SECTIONS { .rodata.compressed : { diff --git a/arch/s390/crypto/sha1_s390.c b/arch/s390/crypto/sha1_s390.c index c7de53d8da75..71048bd4d64c 100644 --- a/arch/s390/crypto/sha1_s390.c +++ b/arch/s390/crypto/sha1_s390.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Cryptographic API. * diff --git a/arch/s390/hypfs/Makefile b/arch/s390/hypfs/Makefile index 2ee25ba252d6..06f601509ce9 100644 --- a/arch/s390/hypfs/Makefile +++ b/arch/s390/hypfs/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # # Makefile for the linux hypfs filesystem routines. # diff --git a/arch/s390/include/asm/Kbuild b/arch/s390/include/asm/Kbuild index 41c211a4d8b1..048450869328 100644 --- a/arch/s390/include/asm/Kbuild +++ b/arch/s390/include/asm/Kbuild @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 generic-y += asm-offsets.h generic-y += cacheflush.h generic-y += clkdev.h diff --git a/arch/s390/include/asm/alternative.h b/arch/s390/include/asm/alternative.h index a72002056b54..c2cf7bcdef9b 100644 --- a/arch/s390/include/asm/alternative.h +++ b/arch/s390/include/asm/alternative.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_S390_ALTERNATIVE_H #define _ASM_S390_ALTERNATIVE_H diff --git a/arch/s390/include/asm/ap.h b/arch/s390/include/asm/ap.h index c02f4aba88a6..9ff489598d5d 100644 --- a/arch/s390/include/asm/ap.h +++ b/arch/s390/include/asm/ap.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Adjunct processor (AP) interfaces * diff --git a/arch/s390/include/asm/bugs.h b/arch/s390/include/asm/bugs.h index 0f5bd894f4dc..aa42a179be33 100644 --- a/arch/s390/include/asm/bugs.h +++ b/arch/s390/include/asm/bugs.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * S390 version * Copyright IBM Corp. 1999 diff --git a/arch/s390/include/asm/segment.h b/arch/s390/include/asm/segment.h index 8bfce3475b1c..97a0582b8d0f 100644 --- a/arch/s390/include/asm/segment.h +++ b/arch/s390/include/asm/segment.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_SEGMENT_H #define _ASM_SEGMENT_H diff --git a/arch/s390/include/asm/vga.h b/arch/s390/include/asm/vga.h index d375526c261f..605dc46bac5e 100644 --- a/arch/s390/include/asm/vga.h +++ b/arch/s390/include/asm/vga.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_S390_VGA_H #define _ASM_S390_VGA_H diff --git a/arch/s390/include/uapi/asm/Kbuild b/arch/s390/include/uapi/asm/Kbuild index 098f28778a13..92b7c9b3e641 100644 --- a/arch/s390/include/uapi/asm/Kbuild +++ b/arch/s390/include/uapi/asm/Kbuild @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm diff --git a/arch/s390/include/uapi/asm/perf_regs.h b/arch/s390/include/uapi/asm/perf_regs.h index 7c8564f98205..d17dd9e5d516 100644 --- a/arch/s390/include/uapi/asm/perf_regs.h +++ b/arch/s390/include/uapi/asm/perf_regs.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_S390_PERF_REGS_H #define _ASM_S390_PERF_REGS_H diff --git a/arch/s390/include/uapi/asm/sthyi.h b/arch/s390/include/uapi/asm/sthyi.h index ec113db4eb7e..b1b022316983 100644 --- a/arch/s390/include/uapi/asm/sthyi.h +++ b/arch/s390/include/uapi/asm/sthyi.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _UAPI_ASM_STHYI_H #define _UAPI_ASM_STHYI_H diff --git a/arch/s390/include/uapi/asm/vmcp.h b/arch/s390/include/uapi/asm/vmcp.h index 4caf71714a55..aeaaa030030e 100644 --- a/arch/s390/include/uapi/asm/vmcp.h +++ b/arch/s390/include/uapi/asm/vmcp.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Copyright IBM Corp. 2004, 2005 * Interface implementation for communication with the z/VM control program diff --git a/arch/s390/kernel/alternative.c b/arch/s390/kernel/alternative.c index 315986a06cf5..574e77622c04 100644 --- a/arch/s390/kernel/alternative.c +++ b/arch/s390/kernel/alternative.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include #include #include diff --git a/arch/s390/kernel/perf_regs.c b/arch/s390/kernel/perf_regs.c index f8603ebed669..54e2d634b849 100644 --- a/arch/s390/kernel/perf_regs.c +++ b/arch/s390/kernel/perf_regs.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include #include #include diff --git a/arch/s390/kernel/vdso64/note.S b/arch/s390/kernel/vdso64/note.S index 79a071e4357e..db19d0680a0a 100644 --- a/arch/s390/kernel/vdso64/note.S +++ b/arch/s390/kernel/vdso64/note.S @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * This supplies .note.* sections to go into the PT_NOTE inside the vDSO text. * Here we can supply some information useful to userland. diff --git a/arch/s390/net/Makefile b/arch/s390/net/Makefile index 90568c33ddb0..e0d5f245e42b 100644 --- a/arch/s390/net/Makefile +++ b/arch/s390/net/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # # Arch-specific network modules # diff --git a/arch/s390/numa/Makefile b/arch/s390/numa/Makefile index f94ecaffa71b..66c2dff74895 100644 --- a/arch/s390/numa/Makefile +++ b/arch/s390/numa/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 obj-y += numa.o obj-y += toptree.o obj-$(CONFIG_NUMA_EMU) += mode_emu.o diff --git a/arch/s390/pci/Makefile b/arch/s390/pci/Makefile index 805d8b29193a..22d0871291ee 100644 --- a/arch/s390/pci/Makefile +++ b/arch/s390/pci/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # # Makefile for the s390 PCI subsystem. # diff --git a/arch/s390/tools/gen_opcode_table.c b/arch/s390/tools/gen_opcode_table.c index 01d4c5a4bfe9..357d42681cef 100644 --- a/arch/s390/tools/gen_opcode_table.c +++ b/arch/s390/tools/gen_opcode_table.c @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Generate opcode table initializers for the in-kernel disassembler. * diff --git a/drivers/s390/Makefile b/drivers/s390/Makefile index e5225ad9c5b1..2fdab400c1fe 100644 --- a/drivers/s390/Makefile +++ b/drivers/s390/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # # Makefile for the S/390 specific device drivers # diff --git a/drivers/s390/block/Kconfig b/drivers/s390/block/Kconfig index 31f014b57bfc..bc27d716aa6b 100644 --- a/drivers/s390/block/Kconfig +++ b/drivers/s390/block/Kconfig @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 comment "S/390 block device drivers" depends on S390 && BLOCK diff --git a/drivers/s390/char/Kconfig b/drivers/s390/char/Kconfig index 97c4c9fdd53d..ab0b243a947d 100644 --- a/drivers/s390/char/Kconfig +++ b/drivers/s390/char/Kconfig @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 comment "S/390 character device drivers" depends on S390 diff --git a/drivers/s390/char/defkeymap.map b/drivers/s390/char/defkeymap.map index 353b3f268824..f4c095612a02 100644 --- a/drivers/s390/char/defkeymap.map +++ b/drivers/s390/char/defkeymap.map @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # Default keymap for 3270 (ebcdic codepage 037). keymaps 0-1,4-5 diff --git a/drivers/s390/cio/blacklist.h b/drivers/s390/cio/blacklist.h index 95e25c1df922..140e3e4ee2fd 100644 --- a/drivers/s390/cio/blacklist.h +++ b/drivers/s390/cio/blacklist.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef S390_BLACKLIST_H #define S390_BLACKLIST_H diff --git a/drivers/s390/net/Kconfig b/drivers/s390/net/Kconfig index b2837b1c70b7..a782a207ad31 100644 --- a/drivers/s390/net/Kconfig +++ b/drivers/s390/net/Kconfig @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 menu "S/390 network device drivers" depends on NETDEVICES && S390 diff --git a/drivers/s390/scsi/Makefile b/drivers/s390/scsi/Makefile index 9259039e886d..9dda431ec8f3 100644 --- a/drivers/s390/scsi/Makefile +++ b/drivers/s390/scsi/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # # Makefile for the S/390 specific device drivers # -- GitLab From 987b154983f0e70b02edf6fc75fcc2f6e6d670b9 Mon Sep 17 00:00:00 2001 From: Martin Schwidefsky Date: Mon, 4 Dec 2017 10:57:02 +0100 Subject: [PATCH 0657/2547] s390: Remove redudant license text More files under arch/s390 have been tagged with the SPDX identifier, a few of those files have a GPL license text. Remove the GPL text as it is no longer needed. Signed-off-by: Martin Schwidefsky --- arch/s390/crypto/sha1_s390.c | 6 ------ arch/s390/include/asm/ap.h | 4 ---- 2 files changed, 10 deletions(-) diff --git a/arch/s390/crypto/sha1_s390.c b/arch/s390/crypto/sha1_s390.c index 71048bd4d64c..a00c17f761c1 100644 --- a/arch/s390/crypto/sha1_s390.c +++ b/arch/s390/crypto/sha1_s390.c @@ -17,12 +17,6 @@ * Copyright (c) Alan Smithee. * Copyright (c) Andrew McDonald * Copyright (c) Jean-Francois Dive - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * */ #include #include diff --git a/arch/s390/include/asm/ap.h b/arch/s390/include/asm/ap.h index 9ff489598d5d..cfce6835b109 100644 --- a/arch/s390/include/asm/ap.h +++ b/arch/s390/include/asm/ap.h @@ -4,10 +4,6 @@ * * Copyright IBM Corp. 2017 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): Tony Krowiak * Martin Schwidefsky * Harald Freudenberger -- GitLab From 8d306f53b63099fec2d56300149e400d181ba4f5 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Mon, 4 Dec 2017 09:42:45 +0100 Subject: [PATCH 0658/2547] s390/mm: fix off-by-one bug in 5-level page table handling Martin Cermak reported that setting a uprobe doesn't work. Reason for this is that the common uprobes code tries to get an unmapped area at the last possible page within an address space. This broke with commit 1aea9b3f9210 ("s390/mm: implement 5 level pages tables") which introduced an off-by-one bug which prevents to map anything at the last possible page within an address space. The check with the off-by-one bug however can be removed since with commit 8ab867cb0806 ("s390/mm: fix BUG_ON in crst_table_upgrade") the necessary check is done at both call sites. Reported-by: Martin Cermak Bisected-by: Thomas Richter Fixes: 1aea9b3f9210 ("s390/mm: implement 5 level pages tables") Cc: # v4.13+ Reviewed-by: Hendrik Brueckner Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky --- arch/s390/mm/pgalloc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/s390/mm/pgalloc.c b/arch/s390/mm/pgalloc.c index 434a9564917b..cb364153c43c 100644 --- a/arch/s390/mm/pgalloc.c +++ b/arch/s390/mm/pgalloc.c @@ -83,8 +83,6 @@ int crst_table_upgrade(struct mm_struct *mm, unsigned long end) /* upgrade should only happen from 3 to 4, 3 to 5, or 4 to 5 levels */ VM_BUG_ON(mm->context.asce_limit < _REGION2_SIZE); - if (end >= TASK_SIZE_MAX) - return -ENOMEM; rc = 0; notify = 0; while (mm->context.asce_limit < end) { -- GitLab From e2bf801ecd4e62222a46d1ba9e57e710171d29c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Stefan=20Br=C3=BCns?= Date: Mon, 27 Nov 2017 20:05:34 +0100 Subject: [PATCH 0659/2547] sunxi-rsb: Include OF based modalias in device uevent MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include the OF-based modalias in the uevent sent when registering devices on the sunxi RSB bus, so that user space has a chance to autoload the kernel module for the device. Fixes a regression caused by commit 3f241bfa60bd ("arm64: allwinner: a64: pine64: Use dcdc1 regulator for mmc0"). When the axp20x-rsb module for the AXP803 PMIC is built as a module, it is not loaded and the system ends up with an disfunctional MMC controller. Fixes: d787dcdb9c8f ("bus: sunxi-rsb: Add driver for Allwinner Reduced Serial Bus") Cc: stable # 4.4.x 7a3b7cd332db of: device: Export of_device_{get_modalias, uvent_modalias} to modules Acked-by: Chen-Yu Tsai Signed-off-by: Stefan Brüns Signed-off-by: Maxime Ripard --- drivers/bus/sunxi-rsb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c index 328ca93781cf..1b76d9585902 100644 --- a/drivers/bus/sunxi-rsb.c +++ b/drivers/bus/sunxi-rsb.c @@ -178,6 +178,7 @@ static struct bus_type sunxi_rsb_bus = { .match = sunxi_rsb_device_match, .probe = sunxi_rsb_device_probe, .remove = sunxi_rsb_device_remove, + .uevent = of_device_uevent_modalias, }; static void sunxi_rsb_dev_release(struct device *dev) -- GitLab From e17e237cd69f9f6ecaa0e875f889ad401a625148 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 4 Dec 2017 16:44:01 +0800 Subject: [PATCH 0660/2547] ARM: dts: sunxi: Convert to CCU index macros for HDMI controller When the HDMI controller device node was added, the needed PLL clock macros were not exported. A separate patch addresses that, but it is merged through a different tree. Now that both patches are in mainline proper, we can convert the raw numbers to proper macros. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 4 ++-- arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++-- arch/arm/boot/dts/sun6i-a31.dtsi | 4 ++-- arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index b91300d49a31..5840f5c75c3b 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -502,8 +502,8 @@ reg = <0x01c16000 0x1000>; interrupts = <58>; clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, - <&ccu 9>, - <&ccu 18>; + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; clock-names = "ahb", "mod", "pll-0", "pll-1"; dmas = <&dma SUN4I_DMA_NORMAL 16>, <&dma SUN4I_DMA_NORMAL 16>, diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 6ae4d95e230e..316cb8b2945b 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -82,8 +82,8 @@ reg = <0x01c16000 0x1000>; interrupts = <58>; clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, - <&ccu 9>, - <&ccu 16>; + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; clock-names = "ahb", "mod", "pll-0", "pll-1"; dmas = <&dma SUN4I_DMA_NORMAL 16>, <&dma SUN4I_DMA_NORMAL 16>, diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 8bfa12b548e0..72d3fe44ecaf 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -429,8 +429,8 @@ interrupts = ; clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu 7>, - <&ccu 13>; + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; resets = <&ccu RST_AHB1_HDMI>; reset-names = "ahb"; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 68dfa82544fc..59655e42e4b0 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -581,8 +581,8 @@ reg = <0x01c16000 0x1000>; interrupts = ; clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, - <&ccu 9>, - <&ccu 18>; + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; clock-names = "ahb", "mod", "pll-0", "pll-1"; dmas = <&dma SUN4I_DMA_NORMAL 16>, <&dma SUN4I_DMA_NORMAL 16>, -- GitLab From 7d556bfc49adddf2beb0d16c91945c3b8b783282 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 4 Dec 2017 10:23:07 +0530 Subject: [PATCH 0661/2547] arm64: allwinner: a64-sopine: Fix to use dcdc1 regulator instead of vcc3v3 Since current tree support AXP803 regulators, replace fixed regulator vcc3v3 with AXP803 dcdc1 regulator where ever it need to replace. Tested mmc0 on sopine baseboard. Signed-off-by: Jagan Teki Signed-off-by: Maxime Ripard --- .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi | 11 +---------- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index a053a6ac5267..abe179de35d7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -96,7 +96,7 @@ &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; vqmmc-supply = <®_vcc1v8>; bus-width = <8>; non-removable; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi index a5da18a6f286..43418bd881d8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi @@ -45,19 +45,10 @@ #include "sun50i-a64.dtsi" -/ { - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; non-removable; disable-wp; bus-width = <4>; -- GitLab From f88e9301948173dd35afad4a6939092c7f269aed Mon Sep 17 00:00:00 2001 From: Sergey Matyukevich Date: Fri, 3 Nov 2017 22:58:54 +0300 Subject: [PATCH 0662/2547] arm64: dts: orange-pi-zero-plus2: fix sdcard detect The sdcard detect pin on orange-pi-zero-plus2 is pulled up. Fix cd-gpio description to enable sdcard detect. Signed-off-by: Sergey Matyukevich Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts index b6b7a561df8c..a42fd79a62a3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts @@ -71,7 +71,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; status = "okay"; }; -- GitLab From f429e7e494afaded76e62c6f98211a635aa03098 Mon Sep 17 00:00:00 2001 From: Kailang Yang Date: Tue, 5 Dec 2017 15:38:24 +0800 Subject: [PATCH 0663/2547] ALSA: hda/realtek - New codec support for ALC257 Add new support for ALC257 codec. [ It's supposed to be almost equivalent with other ALC25x variants, just adding another type and id -- tiwai ] Signed-off-by: Kailang Yang Cc: Signed-off-by: Takashi Iwai --- sound/pci/hda/patch_realtek.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 921a10eff43a..4b21f71d685c 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -330,6 +330,7 @@ static void alc_fill_eapd_coef(struct hda_codec *codec) case 0x10ec0236: case 0x10ec0255: case 0x10ec0256: + case 0x10ec0257: case 0x10ec0282: case 0x10ec0283: case 0x10ec0286: @@ -2772,6 +2773,7 @@ enum { ALC269_TYPE_ALC298, ALC269_TYPE_ALC255, ALC269_TYPE_ALC256, + ALC269_TYPE_ALC257, ALC269_TYPE_ALC215, ALC269_TYPE_ALC225, ALC269_TYPE_ALC294, @@ -2805,6 +2807,7 @@ static int alc269_parse_auto_config(struct hda_codec *codec) case ALC269_TYPE_ALC298: case ALC269_TYPE_ALC255: case ALC269_TYPE_ALC256: + case ALC269_TYPE_ALC257: case ALC269_TYPE_ALC215: case ALC269_TYPE_ALC225: case ALC269_TYPE_ALC294: @@ -6867,6 +6870,10 @@ static int patch_alc269(struct hda_codec *codec) spec->gen.mixer_nid = 0; /* ALC256 does not have any loopback mixer path */ alc_update_coef_idx(codec, 0x36, 1 << 13, 1 << 5); /* Switch pcbeep path to Line in path*/ break; + case 0x10ec0257: + spec->codec_variant = ALC269_TYPE_ALC257; + spec->gen.mixer_nid = 0; + break; case 0x10ec0215: case 0x10ec0285: case 0x10ec0289: @@ -7914,6 +7921,7 @@ static const struct hda_device_id snd_hda_id_realtek[] = { HDA_CODEC_ENTRY(0x10ec0236, "ALC236", patch_alc269), HDA_CODEC_ENTRY(0x10ec0255, "ALC255", patch_alc269), HDA_CODEC_ENTRY(0x10ec0256, "ALC256", patch_alc269), + HDA_CODEC_ENTRY(0x10ec0257, "ALC257", patch_alc269), HDA_CODEC_ENTRY(0x10ec0260, "ALC260", patch_alc260), HDA_CODEC_ENTRY(0x10ec0262, "ALC262", patch_alc262), HDA_CODEC_ENTRY(0x10ec0267, "ALC267", patch_alc268), -- GitLab From ab9dbf771ff9b6b7e814e759213ed01d7f0de320 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Mon, 4 Dec 2017 16:27:25 +1100 Subject: [PATCH 0664/2547] Revert "powerpc: Do not call ppc_md.panic in fadump panic notifier" This reverts commit a3b2cb30f252b21a6f962e0dd107c8b897ca65e4. That commit tried to fix problems with panic on powerpc in certain circumstances, where some output from the generic panic code was being dropped. Unfortunately, it breaks things worse in other circumstances. In particular when running a PAPR guest, it will now attempt to reboot instead of informing the hypervisor (KVM or PowerVM) that the guest has crashed. The crash notification is important to some virtualization management layers. Revert it for now until we can come up with a better solution. Fixes: a3b2cb30f252 ("powerpc: Do not call ppc_md.panic in fadump panic notifier") Cc: stable@vger.kernel.org # v4.14+ Signed-off-by: David Gibson [mpe: Tweak change log a bit] Signed-off-by: Michael Ellerman --- arch/powerpc/include/asm/machdep.h | 1 + arch/powerpc/include/asm/setup.h | 1 + arch/powerpc/kernel/fadump.c | 22 --------------------- arch/powerpc/kernel/setup-common.c | 27 ++++++++++++++++++++++++++ arch/powerpc/platforms/ps3/setup.c | 15 ++++++++++++++ arch/powerpc/platforms/pseries/setup.c | 1 + 6 files changed, 45 insertions(+), 22 deletions(-) diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h index 73b92017b6d7..cd2fc1cc1cc7 100644 --- a/arch/powerpc/include/asm/machdep.h +++ b/arch/powerpc/include/asm/machdep.h @@ -76,6 +76,7 @@ struct machdep_calls { void __noreturn (*restart)(char *cmd); void __noreturn (*halt)(void); + void (*panic)(char *str); void (*cpu_die)(void); long (*time_init)(void); /* Optional, may be NULL */ diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h index 257d23dbf55d..cf00ec26303a 100644 --- a/arch/powerpc/include/asm/setup.h +++ b/arch/powerpc/include/asm/setup.h @@ -24,6 +24,7 @@ extern void reloc_got2(unsigned long); void check_for_initrd(void); void initmem_init(void); +void setup_panic(void); #define ARCH_PANIC_TIMEOUT 180 #ifdef CONFIG_PPC_PSERIES diff --git a/arch/powerpc/kernel/fadump.c b/arch/powerpc/kernel/fadump.c index 04ea5c04fd24..3c2c2688918f 100644 --- a/arch/powerpc/kernel/fadump.c +++ b/arch/powerpc/kernel/fadump.c @@ -1462,25 +1462,6 @@ static void fadump_init_files(void) return; } -static int fadump_panic_event(struct notifier_block *this, - unsigned long event, void *ptr) -{ - /* - * If firmware-assisted dump has been registered then trigger - * firmware-assisted dump and let firmware handle everything - * else. If this returns, then fadump was not registered, so - * go through the rest of the panic path. - */ - crash_fadump(NULL, ptr); - - return NOTIFY_DONE; -} - -static struct notifier_block fadump_panic_block = { - .notifier_call = fadump_panic_event, - .priority = INT_MIN /* may not return; must be done last */ -}; - /* * Prepare for firmware-assisted dump. */ @@ -1513,9 +1494,6 @@ int __init setup_fadump(void) init_fadump_mem_struct(&fdm, fw_dump.reserve_dump_area_start); fadump_init_files(); - atomic_notifier_chain_register(&panic_notifier_list, - &fadump_panic_block); - return 1; } subsys_initcall(setup_fadump); diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c index 2075322cd225..9d213542a48b 100644 --- a/arch/powerpc/kernel/setup-common.c +++ b/arch/powerpc/kernel/setup-common.c @@ -704,6 +704,30 @@ int check_legacy_ioport(unsigned long base_port) } EXPORT_SYMBOL(check_legacy_ioport); +static int ppc_panic_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + /* + * If firmware-assisted dump has been registered then trigger + * firmware-assisted dump and let firmware handle everything else. + */ + crash_fadump(NULL, ptr); + ppc_md.panic(ptr); /* May not return */ + return NOTIFY_DONE; +} + +static struct notifier_block ppc_panic_block = { + .notifier_call = ppc_panic_event, + .priority = INT_MIN /* may not return; must be done last */ +}; + +void __init setup_panic(void) +{ + if (!ppc_md.panic) + return; + atomic_notifier_chain_register(&panic_notifier_list, &ppc_panic_block); +} + #ifdef CONFIG_CHECK_CACHE_COHERENCY /* * For platforms that have configurable cache-coherency. This function @@ -848,6 +872,9 @@ void __init setup_arch(char **cmdline_p) /* Probe the machine type, establish ppc_md. */ probe_machine(); + /* Setup panic notifier if requested by the platform. */ + setup_panic(); + /* * Configure ppc_md.power_save (ppc32 only, 64-bit machines do * it from their respective probe() function. diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c index 9dabea6e1443..6244bc849469 100644 --- a/arch/powerpc/platforms/ps3/setup.c +++ b/arch/powerpc/platforms/ps3/setup.c @@ -104,6 +104,20 @@ static void __noreturn ps3_halt(void) ps3_sys_manager_halt(); /* never returns */ } +static void ps3_panic(char *str) +{ + DBG("%s:%d %s\n", __func__, __LINE__, str); + + smp_send_stop(); + printk("\n"); + printk(" System does not reboot automatically.\n"); + printk(" Please press POWER button.\n"); + printk("\n"); + + while(1) + lv1_pause(1); +} + #if defined(CONFIG_FB_PS3) || defined(CONFIG_FB_PS3_MODULE) || \ defined(CONFIG_PS3_FLASH) || defined(CONFIG_PS3_FLASH_MODULE) static void __init prealloc(struct ps3_prealloc *p) @@ -255,6 +269,7 @@ define_machine(ps3) { .probe = ps3_probe, .setup_arch = ps3_setup_arch, .init_IRQ = ps3_init_IRQ, + .panic = ps3_panic, .get_boot_time = ps3_get_boot_time, .set_dabr = ps3_set_dabr, .calibrate_decr = ps3_calibrate_decr, diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c index 5f1beb8367ac..a8531e012658 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c @@ -726,6 +726,7 @@ define_machine(pseries) { .pcibios_fixup = pSeries_final_fixup, .restart = rtas_restart, .halt = rtas_halt, + .panic = rtas_os_term, .get_boot_time = rtas_get_boot_time, .get_rtc_time = rtas_get_rtc_time, .set_rtc_time = rtas_set_rtc_time, -- GitLab From 39ccc9852e2b46964c9c44eba52db57413ba6d27 Mon Sep 17 00:00:00 2001 From: Anusha Srivatsa Date: Thu, 9 Nov 2017 17:18:32 -0800 Subject: [PATCH 0665/2547] drm/i915/skl: DMC firmware for skylake v1.27 There is a new version of dmc available for skylake. Following additions from ver1.27 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa Reviewed-by: Imre Deak Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/1510276712-29590-2-git-send-email-anusha.srivatsa@intel.com --- drivers/gpu/drm/i915/intel_csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 07e4f7bc4412..7fe4aac0facc 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -44,9 +44,9 @@ MODULE_FIRMWARE(I915_CSR_KBL); #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin" +#define I915_CSR_SKL "i915/skl_dmc_ver1_27.bin" MODULE_FIRMWARE(I915_CSR_SKL); -#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26) +#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27) #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin" MODULE_FIRMWARE(I915_CSR_BXT); -- GitLab From c895f6f703ad7dd2f99e751d9884b0aa5d0eea25 Mon Sep 17 00:00:00 2001 From: Hendrik Brueckner Date: Mon, 4 Dec 2017 10:56:44 +0100 Subject: [PATCH 0666/2547] bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program type Commit 0515e5999a466dfe ("bpf: introduce BPF_PROG_TYPE_PERF_EVENT program type") introduced the bpf_perf_event_data structure which exports the pt_regs structure. This is OK for multiple architectures but fail for s390 and arm64 which do not export pt_regs. Programs using them, for example, the bpf selftest fail to compile on these architectures. For s390, exporting the pt_regs is not an option because s390 wants to allow changes to it. For arm64, there is a user_pt_regs structure that covers parts of the pt_regs structure for use by user space. To solve the broken uapi for s390 and arm64, introduce an abstract type for pt_regs and add an asm/bpf_perf_event.h file that concretes the type. An asm-generic header file covers the architectures that export pt_regs today. The arch-specific enablement for s390 and arm64 follows in separate commits. Reported-by: Thomas Richter Fixes: 0515e5999a466dfe ("bpf: introduce BPF_PROG_TYPE_PERF_EVENT program type") Signed-off-by: Hendrik Brueckner Reviewed-and-tested-by: Thomas Richter Acked-by: Alexei Starovoitov Cc: Arnaldo Carvalho de Melo Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim Cc: Arnd Bergmann Cc: Daniel Borkmann Signed-off-by: Daniel Borkmann --- arch/alpha/include/uapi/asm/Kbuild | 2 ++ arch/arc/include/uapi/asm/Kbuild | 1 + arch/arm/include/uapi/asm/Kbuild | 1 + arch/blackfin/include/uapi/asm/Kbuild | 1 + arch/c6x/include/uapi/asm/Kbuild | 1 + arch/cris/include/uapi/asm/Kbuild | 1 + arch/frv/include/uapi/asm/Kbuild | 2 ++ arch/h8300/include/uapi/asm/Kbuild | 1 + arch/hexagon/include/uapi/asm/Kbuild | 1 + arch/ia64/include/uapi/asm/Kbuild | 1 + arch/m32r/include/uapi/asm/Kbuild | 1 + arch/m68k/include/uapi/asm/Kbuild | 1 + arch/metag/include/uapi/asm/Kbuild | 1 + arch/microblaze/include/uapi/asm/Kbuild | 1 + arch/mips/include/uapi/asm/Kbuild | 1 + arch/mn10300/include/uapi/asm/Kbuild | 1 + arch/nios2/include/uapi/asm/Kbuild | 1 + arch/openrisc/include/uapi/asm/Kbuild | 1 + arch/parisc/include/uapi/asm/Kbuild | 1 + arch/powerpc/include/uapi/asm/Kbuild | 1 + arch/riscv/include/uapi/asm/Kbuild | 1 + arch/score/include/uapi/asm/Kbuild | 1 + arch/sh/include/uapi/asm/Kbuild | 1 + arch/sparc/include/uapi/asm/Kbuild | 1 + arch/tile/include/uapi/asm/Kbuild | 1 + arch/unicore32/include/uapi/asm/Kbuild | 1 + arch/x86/include/uapi/asm/Kbuild | 1 + arch/xtensa/include/uapi/asm/Kbuild | 1 + include/linux/perf_event.h | 6 +++++- include/uapi/asm-generic/bpf_perf_event.h | 9 +++++++++ include/uapi/linux/bpf_perf_event.h | 5 ++--- kernel/events/core.c | 2 +- 32 files changed, 47 insertions(+), 5 deletions(-) create mode 100644 include/uapi/asm-generic/bpf_perf_event.h diff --git a/arch/alpha/include/uapi/asm/Kbuild b/arch/alpha/include/uapi/asm/Kbuild index b15bf6bc0e94..14a2e9af97e9 100644 --- a/arch/alpha/include/uapi/asm/Kbuild +++ b/arch/alpha/include/uapi/asm/Kbuild @@ -1,2 +1,4 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm + +generic-y += bpf_perf_event.h diff --git a/arch/arc/include/uapi/asm/Kbuild b/arch/arc/include/uapi/asm/Kbuild index fa6d0ff4ff89..170b5db64afe 100644 --- a/arch/arc/include/uapi/asm/Kbuild +++ b/arch/arc/include/uapi/asm/Kbuild @@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += auxvec.h generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild index 4d53de308ee0..4d1cc1847edf 100644 --- a/arch/arm/include/uapi/asm/Kbuild +++ b/arch/arm/include/uapi/asm/Kbuild @@ -7,6 +7,7 @@ generated-y += unistd-oabi.h generated-y += unistd-eabi.h generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += ioctl.h generic-y += ipcbuf.h diff --git a/arch/blackfin/include/uapi/asm/Kbuild b/arch/blackfin/include/uapi/asm/Kbuild index aa624b4ab655..2240b38c2915 100644 --- a/arch/blackfin/include/uapi/asm/Kbuild +++ b/arch/blackfin/include/uapi/asm/Kbuild @@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += auxvec.h generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += ioctl.h generic-y += ipcbuf.h diff --git a/arch/c6x/include/uapi/asm/Kbuild b/arch/c6x/include/uapi/asm/Kbuild index 67ee896a76a7..26644e15d854 100644 --- a/arch/c6x/include/uapi/asm/Kbuild +++ b/arch/c6x/include/uapi/asm/Kbuild @@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += auxvec.h generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/cris/include/uapi/asm/Kbuild b/arch/cris/include/uapi/asm/Kbuild index 3687b54bb18e..3470c6e9c7b9 100644 --- a/arch/cris/include/uapi/asm/Kbuild +++ b/arch/cris/include/uapi/asm/Kbuild @@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += auxvec.h generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/frv/include/uapi/asm/Kbuild b/arch/frv/include/uapi/asm/Kbuild index b15bf6bc0e94..14a2e9af97e9 100644 --- a/arch/frv/include/uapi/asm/Kbuild +++ b/arch/frv/include/uapi/asm/Kbuild @@ -1,2 +1,4 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm + +generic-y += bpf_perf_event.h diff --git a/arch/h8300/include/uapi/asm/Kbuild b/arch/h8300/include/uapi/asm/Kbuild index 187aed820e71..2f65f78792cb 100644 --- a/arch/h8300/include/uapi/asm/Kbuild +++ b/arch/h8300/include/uapi/asm/Kbuild @@ -2,6 +2,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += auxvec.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/hexagon/include/uapi/asm/Kbuild b/arch/hexagon/include/uapi/asm/Kbuild index cb5df3aad3a8..41a176dbb53e 100644 --- a/arch/hexagon/include/uapi/asm/Kbuild +++ b/arch/hexagon/include/uapi/asm/Kbuild @@ -2,6 +2,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += auxvec.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/ia64/include/uapi/asm/Kbuild b/arch/ia64/include/uapi/asm/Kbuild index 13a97aa2285f..f5c6967a93bb 100644 --- a/arch/ia64/include/uapi/asm/Kbuild +++ b/arch/ia64/include/uapi/asm/Kbuild @@ -1,4 +1,5 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm +generic-y += bpf_perf_event.h generic-y += kvm_para.h diff --git a/arch/m32r/include/uapi/asm/Kbuild b/arch/m32r/include/uapi/asm/Kbuild index 1c44d3b3eba0..451bf6071c6e 100644 --- a/arch/m32r/include/uapi/asm/Kbuild +++ b/arch/m32r/include/uapi/asm/Kbuild @@ -1,5 +1,6 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm +generic-y += bpf_perf_event.h generic-y += kvm_para.h generic-y += siginfo.h diff --git a/arch/m68k/include/uapi/asm/Kbuild b/arch/m68k/include/uapi/asm/Kbuild index 3717b64a620d..c2e26a44c482 100644 --- a/arch/m68k/include/uapi/asm/Kbuild +++ b/arch/m68k/include/uapi/asm/Kbuild @@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += auxvec.h generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += ioctl.h generic-y += ipcbuf.h diff --git a/arch/metag/include/uapi/asm/Kbuild b/arch/metag/include/uapi/asm/Kbuild index 6ac763d9a3e3..f9eaf07d29f8 100644 --- a/arch/metag/include/uapi/asm/Kbuild +++ b/arch/metag/include/uapi/asm/Kbuild @@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += auxvec.h generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/microblaze/include/uapi/asm/Kbuild b/arch/microblaze/include/uapi/asm/Kbuild index 06609ca36115..2c6a6bffea32 100644 --- a/arch/microblaze/include/uapi/asm/Kbuild +++ b/arch/microblaze/include/uapi/asm/Kbuild @@ -2,6 +2,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/mips/include/uapi/asm/Kbuild b/arch/mips/include/uapi/asm/Kbuild index a0266feba9e6..7a4becd8963a 100644 --- a/arch/mips/include/uapi/asm/Kbuild +++ b/arch/mips/include/uapi/asm/Kbuild @@ -1,4 +1,5 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm +generic-y += bpf_perf_event.h generic-y += ipcbuf.h diff --git a/arch/mn10300/include/uapi/asm/Kbuild b/arch/mn10300/include/uapi/asm/Kbuild index c94ee54210bc..81271d3af47c 100644 --- a/arch/mn10300/include/uapi/asm/Kbuild +++ b/arch/mn10300/include/uapi/asm/Kbuild @@ -1,4 +1,5 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm +generic-y += bpf_perf_event.h generic-y += siginfo.h diff --git a/arch/nios2/include/uapi/asm/Kbuild b/arch/nios2/include/uapi/asm/Kbuild index ffca24da7647..13a3d77b4d7b 100644 --- a/arch/nios2/include/uapi/asm/Kbuild +++ b/arch/nios2/include/uapi/asm/Kbuild @@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += auxvec.h generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/openrisc/include/uapi/asm/Kbuild b/arch/openrisc/include/uapi/asm/Kbuild index 62286dbeb904..130c16ccba0a 100644 --- a/arch/openrisc/include/uapi/asm/Kbuild +++ b/arch/openrisc/include/uapi/asm/Kbuild @@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += auxvec.h generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/parisc/include/uapi/asm/Kbuild b/arch/parisc/include/uapi/asm/Kbuild index 196d2a4efb31..286ef5a5904b 100644 --- a/arch/parisc/include/uapi/asm/Kbuild +++ b/arch/parisc/include/uapi/asm/Kbuild @@ -2,6 +2,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += auxvec.h +generic-y += bpf_perf_event.h generic-y += kvm_para.h generic-y += param.h generic-y += poll.h diff --git a/arch/powerpc/include/uapi/asm/Kbuild b/arch/powerpc/include/uapi/asm/Kbuild index 0d960ef78a9a..1a6ed5919ffd 100644 --- a/arch/powerpc/include/uapi/asm/Kbuild +++ b/arch/powerpc/include/uapi/asm/Kbuild @@ -1,6 +1,7 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm +generic-y += bpf_perf_event.h generic-y += param.h generic-y += poll.h generic-y += resource.h diff --git a/arch/riscv/include/uapi/asm/Kbuild b/arch/riscv/include/uapi/asm/Kbuild index 5ded96b06352..7e91f4850475 100644 --- a/arch/riscv/include/uapi/asm/Kbuild +++ b/arch/riscv/include/uapi/asm/Kbuild @@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += setup.h generic-y += unistd.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/score/include/uapi/asm/Kbuild b/arch/score/include/uapi/asm/Kbuild index c94ee54210bc..81271d3af47c 100644 --- a/arch/score/include/uapi/asm/Kbuild +++ b/arch/score/include/uapi/asm/Kbuild @@ -1,4 +1,5 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm +generic-y += bpf_perf_event.h generic-y += siginfo.h diff --git a/arch/sh/include/uapi/asm/Kbuild b/arch/sh/include/uapi/asm/Kbuild index e28531333efa..ba4d39cb321d 100644 --- a/arch/sh/include/uapi/asm/Kbuild +++ b/arch/sh/include/uapi/asm/Kbuild @@ -2,6 +2,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/sparc/include/uapi/asm/Kbuild b/arch/sparc/include/uapi/asm/Kbuild index 2178c78c7c1a..4680ba246b55 100644 --- a/arch/sparc/include/uapi/asm/Kbuild +++ b/arch/sparc/include/uapi/asm/Kbuild @@ -1,4 +1,5 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm +generic-y += bpf_perf_event.h generic-y += types.h diff --git a/arch/tile/include/uapi/asm/Kbuild b/arch/tile/include/uapi/asm/Kbuild index 5711de0a1b5e..cc439612bcd5 100644 --- a/arch/tile/include/uapi/asm/Kbuild +++ b/arch/tile/include/uapi/asm/Kbuild @@ -1,6 +1,7 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/unicore32/include/uapi/asm/Kbuild b/arch/unicore32/include/uapi/asm/Kbuild index 759a71411169..8611ef980554 100644 --- a/arch/unicore32/include/uapi/asm/Kbuild +++ b/arch/unicore32/include/uapi/asm/Kbuild @@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += auxvec.h generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/arch/x86/include/uapi/asm/Kbuild b/arch/x86/include/uapi/asm/Kbuild index da1489cb64dc..1e901e421f2d 100644 --- a/arch/x86/include/uapi/asm/Kbuild +++ b/arch/x86/include/uapi/asm/Kbuild @@ -1,6 +1,7 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm +generic-y += bpf_perf_event.h generated-y += unistd_32.h generated-y += unistd_64.h generated-y += unistd_x32.h diff --git a/arch/xtensa/include/uapi/asm/Kbuild b/arch/xtensa/include/uapi/asm/Kbuild index a5bcdfb890f1..837d4dd76785 100644 --- a/arch/xtensa/include/uapi/asm/Kbuild +++ b/arch/xtensa/include/uapi/asm/Kbuild @@ -2,6 +2,7 @@ include include/uapi/asm-generic/Kbuild.asm generic-y += bitsperlong.h +generic-y += bpf_perf_event.h generic-y += errno.h generic-y += fcntl.h generic-y += ioctl.h diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 2c9c87d8a0c1..7546822a1d74 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -15,6 +15,7 @@ #define _LINUX_PERF_EVENT_H #include +#include /* * Kernel-internal data types and definitions: @@ -787,7 +788,7 @@ struct perf_output_handle { }; struct bpf_perf_event_data_kern { - struct pt_regs *regs; + bpf_user_pt_regs_t *regs; struct perf_sample_data *data; struct perf_event *event; }; @@ -1177,6 +1178,9 @@ extern void perf_bp_event(struct perf_event *event, void *data); (user_mode(regs) ? PERF_RECORD_MISC_USER : PERF_RECORD_MISC_KERNEL) # define perf_instruction_pointer(regs) instruction_pointer(regs) #endif +#ifndef perf_arch_bpf_user_pt_regs +# define perf_arch_bpf_user_pt_regs(regs) regs +#endif static inline bool has_branch_stack(struct perf_event *event) { diff --git a/include/uapi/asm-generic/bpf_perf_event.h b/include/uapi/asm-generic/bpf_perf_event.h new file mode 100644 index 000000000000..53815d2cd047 --- /dev/null +++ b/include/uapi/asm-generic/bpf_perf_event.h @@ -0,0 +1,9 @@ +#ifndef _UAPI__ASM_GENERIC_BPF_PERF_EVENT_H__ +#define _UAPI__ASM_GENERIC_BPF_PERF_EVENT_H__ + +#include + +/* Export kernel pt_regs structure */ +typedef struct pt_regs bpf_user_pt_regs_t; + +#endif /* _UAPI__ASM_GENERIC_BPF_PERF_EVENT_H__ */ diff --git a/include/uapi/linux/bpf_perf_event.h b/include/uapi/linux/bpf_perf_event.h index af549d4ecf1b..8f95303f9d80 100644 --- a/include/uapi/linux/bpf_perf_event.h +++ b/include/uapi/linux/bpf_perf_event.h @@ -8,11 +8,10 @@ #ifndef _UAPI__LINUX_BPF_PERF_EVENT_H__ #define _UAPI__LINUX_BPF_PERF_EVENT_H__ -#include -#include +#include struct bpf_perf_event_data { - struct pt_regs regs; + bpf_user_pt_regs_t regs; __u64 sample_period; }; diff --git a/kernel/events/core.c b/kernel/events/core.c index 16beab4767e1..ba957b9812b3 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -7987,11 +7987,11 @@ static void bpf_overflow_handler(struct perf_event *event, { struct bpf_perf_event_data_kern ctx = { .data = data, - .regs = regs, .event = event, }; int ret = 0; + ctx.regs = perf_arch_bpf_user_pt_regs(regs); preempt_disable(); if (unlikely(__this_cpu_inc_return(bpf_prog_active) != 1)) goto out; -- GitLab From 466698e654e8931945301ea999feb6bd4bfaf849 Mon Sep 17 00:00:00 2001 From: Hendrik Brueckner Date: Mon, 4 Dec 2017 10:56:45 +0100 Subject: [PATCH 0667/2547] s390/bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program type To mitigate and correct the broken uapi for the BPF_PROG_TYPE_PERF_EVENT program type, introduce a user_pt_regs structure (similar to arm64) that exports parts from the beginnig of the pt_regs structure. The export must start with the beginning of the pt_regs structure because to correctly calculate BPF prologues for perf (regs_query_register_offset()). For BPF_PROG_TYPE_PERF_EVENT program types, the BPF program is then passed a user_pt_regs structure. Note: Depending on future changes to the s390 pt_regs structure, consider the user_pt_regs structure to be stable for a particular kernel version only. (Of course, s390 tries to ensure keep it stable as much as possible.) Signed-off-by: Hendrik Brueckner Reviewed-and-tested-by: Thomas Richter Acked-by: Alexei Starovoitov Cc: Martin Schwidefsky Cc: Heiko Carstens Cc: Arnaldo Carvalho de Melo Cc: Daniel Borkmann Signed-off-by: Daniel Borkmann --- arch/s390/include/asm/perf_event.h | 1 + arch/s390/include/asm/ptrace.h | 11 ++++++++--- arch/s390/include/uapi/asm/bpf_perf_event.h | 9 +++++++++ arch/s390/include/uapi/asm/ptrace.h | 11 +++++++++++ 4 files changed, 29 insertions(+), 3 deletions(-) create mode 100644 arch/s390/include/uapi/asm/bpf_perf_event.h diff --git a/arch/s390/include/asm/perf_event.h b/arch/s390/include/asm/perf_event.h index d6c9d1e0dc2d..b9c0e361748b 100644 --- a/arch/s390/include/asm/perf_event.h +++ b/arch/s390/include/asm/perf_event.h @@ -40,6 +40,7 @@ struct pt_regs; extern unsigned long perf_instruction_pointer(struct pt_regs *regs); extern unsigned long perf_misc_flags(struct pt_regs *regs); #define perf_misc_flags(regs) perf_misc_flags(regs) +#define perf_arch_bpf_user_pt_regs(regs) ®s->user_regs /* Perf pt_regs extension for sample-data-entry indicators */ struct perf_sf_sde_regs { diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h index a3788dafc0e1..6f70d81c40f2 100644 --- a/arch/s390/include/asm/ptrace.h +++ b/arch/s390/include/asm/ptrace.h @@ -74,9 +74,14 @@ enum { */ struct pt_regs { - unsigned long args[1]; - psw_t psw; - unsigned long gprs[NUM_GPRS]; + union { + user_pt_regs user_regs; + struct { + unsigned long args[1]; + psw_t psw; + unsigned long gprs[NUM_GPRS]; + }; + }; unsigned long orig_gpr2; unsigned int int_code; unsigned int int_parm; diff --git a/arch/s390/include/uapi/asm/bpf_perf_event.h b/arch/s390/include/uapi/asm/bpf_perf_event.h new file mode 100644 index 000000000000..cefe7c7cd4f6 --- /dev/null +++ b/arch/s390/include/uapi/asm/bpf_perf_event.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _UAPI__ASM_BPF_PERF_EVENT_H__ +#define _UAPI__ASM_BPF_PERF_EVENT_H__ + +#include + +typedef user_pt_regs bpf_user_pt_regs_t; + +#endif /* _UAPI__ASM_BPF_PERF_EVENT_H__ */ diff --git a/arch/s390/include/uapi/asm/ptrace.h b/arch/s390/include/uapi/asm/ptrace.h index 0d23c8ff2900..70f7cb2e5e50 100644 --- a/arch/s390/include/uapi/asm/ptrace.h +++ b/arch/s390/include/uapi/asm/ptrace.h @@ -290,6 +290,17 @@ typedef struct unsigned long orig_gpr2; } s390_regs; +/* + * The user_pt_regs structure exports the beginning of + * the in-kernel pt_regs structure to user space. + */ +typedef struct +{ + unsigned long args[1]; + psw_t psw; + unsigned long gprs[NUM_GPRS]; +} user_pt_regs; + /* * Now for the user space program event recording (trace) definitions. * The following structures are used only for the ptrace interface, don't -- GitLab From a39cada70268aadff7153e4f782bcd90a5c69d07 Mon Sep 17 00:00:00 2001 From: Hendrik Brueckner Date: Mon, 4 Dec 2017 10:56:46 +0100 Subject: [PATCH 0668/2547] arm64/bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program type Correct the broken uapi for the BPF_PROG_TYPE_PERF_EVENT program type by exporting the user_pt_regs structure instead of the pt_regs structure that is in-kernel only. Signed-off-by: Hendrik Brueckner Reviewed-by: Thomas Richter Acked-by: Alexei Starovoitov Cc: Will Deacon Cc: Mark Rutland Cc: Arnaldo Carvalho de Melo Signed-off-by: Daniel Borkmann --- arch/arm64/include/asm/perf_event.h | 2 ++ arch/arm64/include/uapi/asm/bpf_perf_event.h | 9 +++++++++ 2 files changed, 11 insertions(+) create mode 100644 arch/arm64/include/uapi/asm/bpf_perf_event.h diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h index 8d5cbec17d80..f9ccc36d3dc3 100644 --- a/arch/arm64/include/asm/perf_event.h +++ b/arch/arm64/include/asm/perf_event.h @@ -18,6 +18,7 @@ #define __ASM_PERF_EVENT_H #include +#include #define ARMV8_PMU_MAX_COUNTERS 32 #define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1) @@ -79,6 +80,7 @@ struct pt_regs; extern unsigned long perf_instruction_pointer(struct pt_regs *regs); extern unsigned long perf_misc_flags(struct pt_regs *regs); #define perf_misc_flags(regs) perf_misc_flags(regs) +#define perf_arch_bpf_user_pt_regs(regs) ®s->user_regs #endif #define perf_arch_fetch_caller_regs(regs, __ip) { \ diff --git a/arch/arm64/include/uapi/asm/bpf_perf_event.h b/arch/arm64/include/uapi/asm/bpf_perf_event.h new file mode 100644 index 000000000000..b551b741653d --- /dev/null +++ b/arch/arm64/include/uapi/asm/bpf_perf_event.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _UAPI__ASM_BPF_PERF_EVENT_H__ +#define _UAPI__ASM_BPF_PERF_EVENT_H__ + +#include + +typedef struct user_pt_regs bpf_user_pt_regs_t; + +#endif /* _UAPI__ASM_BPF_PERF_EVENT_H__ */ -- GitLab From 62e1dfa3e1e32fbc351548e7fae2d97c46d25a33 Mon Sep 17 00:00:00 2001 From: Hendrik Brueckner Date: Mon, 4 Dec 2017 10:56:47 +0100 Subject: [PATCH 0669/2547] s390/uapi: correct whitespace & coding style in asm/ptrace.h Correct whitespace and coding style issues in the s390 asm/ptrace.h uapi header file. This is preparatory work to copy it to the tools/ directory for inclusion by selftests and perf. Signed-off-by: Hendrik Brueckner Signed-off-by: Daniel Borkmann --- arch/s390/include/uapi/asm/ptrace.h | 118 ++++++++++++---------------- 1 file changed, 52 insertions(+), 66 deletions(-) diff --git a/arch/s390/include/uapi/asm/ptrace.h b/arch/s390/include/uapi/asm/ptrace.h index 70f7cb2e5e50..543dd70e12c8 100644 --- a/arch/s390/include/uapi/asm/ptrace.h +++ b/arch/s390/include/uapi/asm/ptrace.h @@ -162,7 +162,7 @@ #define GPR_SIZE 8 #define CR_SIZE 8 -#define STACK_FRAME_OVERHEAD 160 /* size of minimum stack frame */ +#define STACK_FRAME_OVERHEAD 160 /* size of minimum stack frame */ #endif /* __s390x__ */ @@ -179,17 +179,16 @@ #define ACR_SIZE 4 -#define PTRACE_OLDSETOPTIONS 21 +#define PTRACE_OLDSETOPTIONS 21 #ifndef __ASSEMBLY__ #include #include -typedef union -{ - float f; - double d; - __u64 ui; +typedef union { + float f; + double d; + __u64 ui; struct { __u32 hi; @@ -197,23 +196,21 @@ typedef union } fp; } freg_t; -typedef struct -{ - __u32 fpc; +typedef struct { + __u32 fpc; __u32 pad; - freg_t fprs[NUM_FPRS]; + freg_t fprs[NUM_FPRS]; } s390_fp_regs; -#define FPC_EXCEPTION_MASK 0xF8000000 -#define FPC_FLAGS_MASK 0x00F80000 -#define FPC_DXC_MASK 0x0000FF00 -#define FPC_RM_MASK 0x00000003 +#define FPC_EXCEPTION_MASK 0xF8000000 +#define FPC_FLAGS_MASK 0x00F80000 +#define FPC_DXC_MASK 0x0000FF00 +#define FPC_RM_MASK 0x00000003 /* this typedef defines how a Program Status Word looks like */ -typedef struct -{ - unsigned long mask; - unsigned long addr; +typedef struct { + unsigned long mask; + unsigned long addr; } __attribute__ ((aligned(8))) psw_t; #ifndef __s390x__ @@ -282,8 +279,7 @@ typedef struct /* * The s390_regs structure is used to define the elf_gregset_t. */ -typedef struct -{ +typedef struct { psw_t psw; unsigned long gprs[NUM_GPRS]; unsigned int acrs[NUM_ACRS]; @@ -294,8 +290,7 @@ typedef struct * The user_pt_regs structure exports the beginning of * the in-kernel pt_regs structure to user space. */ -typedef struct -{ +typedef struct { unsigned long args[1]; psw_t psw; unsigned long gprs[NUM_GPRS]; @@ -307,19 +302,17 @@ typedef struct * touch or even look at it if you don't want to modify the user-space * ptrace interface. In particular stay away from it for in-kernel PER. */ -typedef struct -{ +typedef struct { unsigned long cr[NUM_CR_WORDS]; } per_cr_words; #define PER_EM_MASK 0xE8000000UL -typedef struct -{ +typedef struct { #ifdef __s390x__ - unsigned : 32; + unsigned : 32; #endif /* __s390x__ */ - unsigned em_branching : 1; + unsigned em_branching : 1; unsigned em_instruction_fetch : 1; /* * Switching on storage alteration automatically fixes @@ -328,44 +321,41 @@ typedef struct unsigned em_storage_alteration : 1; unsigned em_gpr_alt_unused : 1; unsigned em_store_real_address : 1; - unsigned : 3; + unsigned : 3; unsigned branch_addr_ctl : 1; - unsigned : 1; + unsigned : 1; unsigned storage_alt_space_ctl : 1; - unsigned : 21; + unsigned : 21; unsigned long starting_addr; unsigned long ending_addr; } per_cr_bits; -typedef struct -{ +typedef struct { unsigned short perc_atmid; unsigned long address; unsigned char access_id; } per_lowcore_words; -typedef struct -{ - unsigned perc_branching : 1; +typedef struct { + unsigned perc_branching : 1; unsigned perc_instruction_fetch : 1; unsigned perc_storage_alteration : 1; - unsigned perc_gpr_alt_unused : 1; + unsigned perc_gpr_alt_unused : 1; unsigned perc_store_real_address : 1; - unsigned : 3; - unsigned atmid_psw_bit_31 : 1; - unsigned atmid_validity_bit : 1; - unsigned atmid_psw_bit_32 : 1; - unsigned atmid_psw_bit_5 : 1; - unsigned atmid_psw_bit_16 : 1; - unsigned atmid_psw_bit_17 : 1; - unsigned si : 2; + unsigned : 3; + unsigned atmid_psw_bit_31 : 1; + unsigned atmid_validity_bit : 1; + unsigned atmid_psw_bit_32 : 1; + unsigned atmid_psw_bit_5 : 1; + unsigned atmid_psw_bit_16 : 1; + unsigned atmid_psw_bit_17 : 1; + unsigned si : 2; unsigned long address; - unsigned : 4; - unsigned access_id : 4; + unsigned : 4; + unsigned access_id : 4; } per_lowcore_bits; -typedef struct -{ +typedef struct { union { per_cr_words words; per_cr_bits bits; @@ -375,9 +365,9 @@ typedef struct * the kernel always sets them to zero. To enable single * stepping use ptrace(PTRACE_SINGLESTEP) instead. */ - unsigned single_step : 1; + unsigned single_step : 1; unsigned instruction_fetch : 1; - unsigned : 30; + unsigned : 30; /* * These addresses are copied into cr10 & cr11 if single * stepping is switched off @@ -387,11 +377,10 @@ typedef struct union { per_lowcore_words words; per_lowcore_bits bits; - } lowcore; + } lowcore; } per_struct; -typedef struct -{ +typedef struct { unsigned int len; unsigned long kernel_addr; unsigned long process_addr; @@ -401,12 +390,12 @@ typedef struct * S/390 specific non posix ptrace requests. I chose unusual values so * they are unlikely to clash with future ptrace definitions. */ -#define PTRACE_PEEKUSR_AREA 0x5000 -#define PTRACE_POKEUSR_AREA 0x5001 +#define PTRACE_PEEKUSR_AREA 0x5000 +#define PTRACE_POKEUSR_AREA 0x5001 #define PTRACE_PEEKTEXT_AREA 0x5002 #define PTRACE_PEEKDATA_AREA 0x5003 #define PTRACE_POKETEXT_AREA 0x5004 -#define PTRACE_POKEDATA_AREA 0x5005 +#define PTRACE_POKEDATA_AREA 0x5005 #define PTRACE_GET_LAST_BREAK 0x5006 #define PTRACE_PEEK_SYSTEM_CALL 0x5007 #define PTRACE_POKE_SYSTEM_CALL 0x5008 @@ -424,21 +413,19 @@ typedef struct * PT_PROT definition is loosely based on hppa bsd definition in * gdb/hppab-nat.c */ -#define PTRACE_PROT 21 +#define PTRACE_PROT 21 -typedef enum -{ +typedef enum { ptprot_set_access_watchpoint, ptprot_set_write_watchpoint, ptprot_disable_watchpoint } ptprot_flags; -typedef struct -{ +typedef struct { unsigned long lowaddr; unsigned long hiaddr; ptprot_flags prot; -} ptprot_area; +} ptprot_area; /* Sequence of bytes for breakpoint illegal instruction. */ #define S390_BREAKPOINT {0x0,0x1} @@ -450,8 +437,7 @@ typedef struct * The user_regs_struct defines the way the user registers are * store on the stack for signal handling. */ -struct user_regs_struct -{ +struct user_regs_struct { psw_t psw; unsigned long gprs[NUM_GPRS]; unsigned int acrs[NUM_ACRS]; -- GitLab From 618e165b2a8e10765dd2a4f9866d118a474f0faf Mon Sep 17 00:00:00 2001 From: Hendrik Brueckner Date: Mon, 4 Dec 2017 10:56:48 +0100 Subject: [PATCH 0670/2547] selftests/bpf: sync kernel headers and introduce arch support in Makefile Synchronize the uapi kernel header files which solves the broken uapi export of pt_regs. Because of arch-specific uapi headers, extended the include path in the Makefile. With this change, the test_verifier program compiles and runs successfully on s390. Signed-off-by: Hendrik Brueckner Reviewed-and-tested-by: Thomas Richter Acked-by: Alexei Starovoitov Cc: Daniel Borkmann Cc: Shuah Khan Signed-off-by: Daniel Borkmann --- .../arm64/include/uapi/asm/bpf_perf_event.h | 9 + .../s390/include/uapi/asm/bpf_perf_event.h | 9 + tools/arch/s390/include/uapi/asm/ptrace.h | 457 ++++++++++++++++++ .../include/uapi/asm-generic/bpf_perf_event.h | 9 + tools/include/uapi/linux/bpf_perf_event.h | 6 +- tools/testing/selftests/bpf/Makefile | 14 +- 6 files changed, 500 insertions(+), 4 deletions(-) create mode 100644 tools/arch/arm64/include/uapi/asm/bpf_perf_event.h create mode 100644 tools/arch/s390/include/uapi/asm/bpf_perf_event.h create mode 100644 tools/arch/s390/include/uapi/asm/ptrace.h create mode 100644 tools/include/uapi/asm-generic/bpf_perf_event.h diff --git a/tools/arch/arm64/include/uapi/asm/bpf_perf_event.h b/tools/arch/arm64/include/uapi/asm/bpf_perf_event.h new file mode 100644 index 000000000000..b551b741653d --- /dev/null +++ b/tools/arch/arm64/include/uapi/asm/bpf_perf_event.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _UAPI__ASM_BPF_PERF_EVENT_H__ +#define _UAPI__ASM_BPF_PERF_EVENT_H__ + +#include + +typedef struct user_pt_regs bpf_user_pt_regs_t; + +#endif /* _UAPI__ASM_BPF_PERF_EVENT_H__ */ diff --git a/tools/arch/s390/include/uapi/asm/bpf_perf_event.h b/tools/arch/s390/include/uapi/asm/bpf_perf_event.h new file mode 100644 index 000000000000..cefe7c7cd4f6 --- /dev/null +++ b/tools/arch/s390/include/uapi/asm/bpf_perf_event.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _UAPI__ASM_BPF_PERF_EVENT_H__ +#define _UAPI__ASM_BPF_PERF_EVENT_H__ + +#include + +typedef user_pt_regs bpf_user_pt_regs_t; + +#endif /* _UAPI__ASM_BPF_PERF_EVENT_H__ */ diff --git a/tools/arch/s390/include/uapi/asm/ptrace.h b/tools/arch/s390/include/uapi/asm/ptrace.h new file mode 100644 index 000000000000..543dd70e12c8 --- /dev/null +++ b/tools/arch/s390/include/uapi/asm/ptrace.h @@ -0,0 +1,457 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * S390 version + * Copyright IBM Corp. 1999, 2000 + * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) + */ + +#ifndef _UAPI_S390_PTRACE_H +#define _UAPI_S390_PTRACE_H + +/* + * Offsets in the user_regs_struct. They are used for the ptrace + * system call and in entry.S + */ +#ifndef __s390x__ + +#define PT_PSWMASK 0x00 +#define PT_PSWADDR 0x04 +#define PT_GPR0 0x08 +#define PT_GPR1 0x0C +#define PT_GPR2 0x10 +#define PT_GPR3 0x14 +#define PT_GPR4 0x18 +#define PT_GPR5 0x1C +#define PT_GPR6 0x20 +#define PT_GPR7 0x24 +#define PT_GPR8 0x28 +#define PT_GPR9 0x2C +#define PT_GPR10 0x30 +#define PT_GPR11 0x34 +#define PT_GPR12 0x38 +#define PT_GPR13 0x3C +#define PT_GPR14 0x40 +#define PT_GPR15 0x44 +#define PT_ACR0 0x48 +#define PT_ACR1 0x4C +#define PT_ACR2 0x50 +#define PT_ACR3 0x54 +#define PT_ACR4 0x58 +#define PT_ACR5 0x5C +#define PT_ACR6 0x60 +#define PT_ACR7 0x64 +#define PT_ACR8 0x68 +#define PT_ACR9 0x6C +#define PT_ACR10 0x70 +#define PT_ACR11 0x74 +#define PT_ACR12 0x78 +#define PT_ACR13 0x7C +#define PT_ACR14 0x80 +#define PT_ACR15 0x84 +#define PT_ORIGGPR2 0x88 +#define PT_FPC 0x90 +/* + * A nasty fact of life that the ptrace api + * only supports passing of longs. + */ +#define PT_FPR0_HI 0x98 +#define PT_FPR0_LO 0x9C +#define PT_FPR1_HI 0xA0 +#define PT_FPR1_LO 0xA4 +#define PT_FPR2_HI 0xA8 +#define PT_FPR2_LO 0xAC +#define PT_FPR3_HI 0xB0 +#define PT_FPR3_LO 0xB4 +#define PT_FPR4_HI 0xB8 +#define PT_FPR4_LO 0xBC +#define PT_FPR5_HI 0xC0 +#define PT_FPR5_LO 0xC4 +#define PT_FPR6_HI 0xC8 +#define PT_FPR6_LO 0xCC +#define PT_FPR7_HI 0xD0 +#define PT_FPR7_LO 0xD4 +#define PT_FPR8_HI 0xD8 +#define PT_FPR8_LO 0XDC +#define PT_FPR9_HI 0xE0 +#define PT_FPR9_LO 0xE4 +#define PT_FPR10_HI 0xE8 +#define PT_FPR10_LO 0xEC +#define PT_FPR11_HI 0xF0 +#define PT_FPR11_LO 0xF4 +#define PT_FPR12_HI 0xF8 +#define PT_FPR12_LO 0xFC +#define PT_FPR13_HI 0x100 +#define PT_FPR13_LO 0x104 +#define PT_FPR14_HI 0x108 +#define PT_FPR14_LO 0x10C +#define PT_FPR15_HI 0x110 +#define PT_FPR15_LO 0x114 +#define PT_CR_9 0x118 +#define PT_CR_10 0x11C +#define PT_CR_11 0x120 +#define PT_IEEE_IP 0x13C +#define PT_LASTOFF PT_IEEE_IP +#define PT_ENDREGS 0x140-1 + +#define GPR_SIZE 4 +#define CR_SIZE 4 + +#define STACK_FRAME_OVERHEAD 96 /* size of minimum stack frame */ + +#else /* __s390x__ */ + +#define PT_PSWMASK 0x00 +#define PT_PSWADDR 0x08 +#define PT_GPR0 0x10 +#define PT_GPR1 0x18 +#define PT_GPR2 0x20 +#define PT_GPR3 0x28 +#define PT_GPR4 0x30 +#define PT_GPR5 0x38 +#define PT_GPR6 0x40 +#define PT_GPR7 0x48 +#define PT_GPR8 0x50 +#define PT_GPR9 0x58 +#define PT_GPR10 0x60 +#define PT_GPR11 0x68 +#define PT_GPR12 0x70 +#define PT_GPR13 0x78 +#define PT_GPR14 0x80 +#define PT_GPR15 0x88 +#define PT_ACR0 0x90 +#define PT_ACR1 0x94 +#define PT_ACR2 0x98 +#define PT_ACR3 0x9C +#define PT_ACR4 0xA0 +#define PT_ACR5 0xA4 +#define PT_ACR6 0xA8 +#define PT_ACR7 0xAC +#define PT_ACR8 0xB0 +#define PT_ACR9 0xB4 +#define PT_ACR10 0xB8 +#define PT_ACR11 0xBC +#define PT_ACR12 0xC0 +#define PT_ACR13 0xC4 +#define PT_ACR14 0xC8 +#define PT_ACR15 0xCC +#define PT_ORIGGPR2 0xD0 +#define PT_FPC 0xD8 +#define PT_FPR0 0xE0 +#define PT_FPR1 0xE8 +#define PT_FPR2 0xF0 +#define PT_FPR3 0xF8 +#define PT_FPR4 0x100 +#define PT_FPR5 0x108 +#define PT_FPR6 0x110 +#define PT_FPR7 0x118 +#define PT_FPR8 0x120 +#define PT_FPR9 0x128 +#define PT_FPR10 0x130 +#define PT_FPR11 0x138 +#define PT_FPR12 0x140 +#define PT_FPR13 0x148 +#define PT_FPR14 0x150 +#define PT_FPR15 0x158 +#define PT_CR_9 0x160 +#define PT_CR_10 0x168 +#define PT_CR_11 0x170 +#define PT_IEEE_IP 0x1A8 +#define PT_LASTOFF PT_IEEE_IP +#define PT_ENDREGS 0x1B0-1 + +#define GPR_SIZE 8 +#define CR_SIZE 8 + +#define STACK_FRAME_OVERHEAD 160 /* size of minimum stack frame */ + +#endif /* __s390x__ */ + +#define NUM_GPRS 16 +#define NUM_FPRS 16 +#define NUM_CRS 16 +#define NUM_ACRS 16 + +#define NUM_CR_WORDS 3 + +#define FPR_SIZE 8 +#define FPC_SIZE 4 +#define FPC_PAD_SIZE 4 /* gcc insists on aligning the fpregs */ +#define ACR_SIZE 4 + + +#define PTRACE_OLDSETOPTIONS 21 + +#ifndef __ASSEMBLY__ +#include +#include + +typedef union { + float f; + double d; + __u64 ui; + struct + { + __u32 hi; + __u32 lo; + } fp; +} freg_t; + +typedef struct { + __u32 fpc; + __u32 pad; + freg_t fprs[NUM_FPRS]; +} s390_fp_regs; + +#define FPC_EXCEPTION_MASK 0xF8000000 +#define FPC_FLAGS_MASK 0x00F80000 +#define FPC_DXC_MASK 0x0000FF00 +#define FPC_RM_MASK 0x00000003 + +/* this typedef defines how a Program Status Word looks like */ +typedef struct { + unsigned long mask; + unsigned long addr; +} __attribute__ ((aligned(8))) psw_t; + +#ifndef __s390x__ + +#define PSW_MASK_PER 0x40000000UL +#define PSW_MASK_DAT 0x04000000UL +#define PSW_MASK_IO 0x02000000UL +#define PSW_MASK_EXT 0x01000000UL +#define PSW_MASK_KEY 0x00F00000UL +#define PSW_MASK_BASE 0x00080000UL /* always one */ +#define PSW_MASK_MCHECK 0x00040000UL +#define PSW_MASK_WAIT 0x00020000UL +#define PSW_MASK_PSTATE 0x00010000UL +#define PSW_MASK_ASC 0x0000C000UL +#define PSW_MASK_CC 0x00003000UL +#define PSW_MASK_PM 0x00000F00UL +#define PSW_MASK_RI 0x00000000UL +#define PSW_MASK_EA 0x00000000UL +#define PSW_MASK_BA 0x00000000UL + +#define PSW_MASK_USER 0x0000FF00UL + +#define PSW_ADDR_AMODE 0x80000000UL +#define PSW_ADDR_INSN 0x7FFFFFFFUL + +#define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 20) + +#define PSW_ASC_PRIMARY 0x00000000UL +#define PSW_ASC_ACCREG 0x00004000UL +#define PSW_ASC_SECONDARY 0x00008000UL +#define PSW_ASC_HOME 0x0000C000UL + +#else /* __s390x__ */ + +#define PSW_MASK_PER 0x4000000000000000UL +#define PSW_MASK_DAT 0x0400000000000000UL +#define PSW_MASK_IO 0x0200000000000000UL +#define PSW_MASK_EXT 0x0100000000000000UL +#define PSW_MASK_BASE 0x0000000000000000UL +#define PSW_MASK_KEY 0x00F0000000000000UL +#define PSW_MASK_MCHECK 0x0004000000000000UL +#define PSW_MASK_WAIT 0x0002000000000000UL +#define PSW_MASK_PSTATE 0x0001000000000000UL +#define PSW_MASK_ASC 0x0000C00000000000UL +#define PSW_MASK_CC 0x0000300000000000UL +#define PSW_MASK_PM 0x00000F0000000000UL +#define PSW_MASK_RI 0x0000008000000000UL +#define PSW_MASK_EA 0x0000000100000000UL +#define PSW_MASK_BA 0x0000000080000000UL + +#define PSW_MASK_USER 0x0000FF0180000000UL + +#define PSW_ADDR_AMODE 0x0000000000000000UL +#define PSW_ADDR_INSN 0xFFFFFFFFFFFFFFFFUL + +#define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 52) + +#define PSW_ASC_PRIMARY 0x0000000000000000UL +#define PSW_ASC_ACCREG 0x0000400000000000UL +#define PSW_ASC_SECONDARY 0x0000800000000000UL +#define PSW_ASC_HOME 0x0000C00000000000UL + +#endif /* __s390x__ */ + + +/* + * The s390_regs structure is used to define the elf_gregset_t. + */ +typedef struct { + psw_t psw; + unsigned long gprs[NUM_GPRS]; + unsigned int acrs[NUM_ACRS]; + unsigned long orig_gpr2; +} s390_regs; + +/* + * The user_pt_regs structure exports the beginning of + * the in-kernel pt_regs structure to user space. + */ +typedef struct { + unsigned long args[1]; + psw_t psw; + unsigned long gprs[NUM_GPRS]; +} user_pt_regs; + +/* + * Now for the user space program event recording (trace) definitions. + * The following structures are used only for the ptrace interface, don't + * touch or even look at it if you don't want to modify the user-space + * ptrace interface. In particular stay away from it for in-kernel PER. + */ +typedef struct { + unsigned long cr[NUM_CR_WORDS]; +} per_cr_words; + +#define PER_EM_MASK 0xE8000000UL + +typedef struct { +#ifdef __s390x__ + unsigned : 32; +#endif /* __s390x__ */ + unsigned em_branching : 1; + unsigned em_instruction_fetch : 1; + /* + * Switching on storage alteration automatically fixes + * the storage alteration event bit in the users std. + */ + unsigned em_storage_alteration : 1; + unsigned em_gpr_alt_unused : 1; + unsigned em_store_real_address : 1; + unsigned : 3; + unsigned branch_addr_ctl : 1; + unsigned : 1; + unsigned storage_alt_space_ctl : 1; + unsigned : 21; + unsigned long starting_addr; + unsigned long ending_addr; +} per_cr_bits; + +typedef struct { + unsigned short perc_atmid; + unsigned long address; + unsigned char access_id; +} per_lowcore_words; + +typedef struct { + unsigned perc_branching : 1; + unsigned perc_instruction_fetch : 1; + unsigned perc_storage_alteration : 1; + unsigned perc_gpr_alt_unused : 1; + unsigned perc_store_real_address : 1; + unsigned : 3; + unsigned atmid_psw_bit_31 : 1; + unsigned atmid_validity_bit : 1; + unsigned atmid_psw_bit_32 : 1; + unsigned atmid_psw_bit_5 : 1; + unsigned atmid_psw_bit_16 : 1; + unsigned atmid_psw_bit_17 : 1; + unsigned si : 2; + unsigned long address; + unsigned : 4; + unsigned access_id : 4; +} per_lowcore_bits; + +typedef struct { + union { + per_cr_words words; + per_cr_bits bits; + } control_regs; + /* + * The single_step and instruction_fetch bits are obsolete, + * the kernel always sets them to zero. To enable single + * stepping use ptrace(PTRACE_SINGLESTEP) instead. + */ + unsigned single_step : 1; + unsigned instruction_fetch : 1; + unsigned : 30; + /* + * These addresses are copied into cr10 & cr11 if single + * stepping is switched off + */ + unsigned long starting_addr; + unsigned long ending_addr; + union { + per_lowcore_words words; + per_lowcore_bits bits; + } lowcore; +} per_struct; + +typedef struct { + unsigned int len; + unsigned long kernel_addr; + unsigned long process_addr; +} ptrace_area; + +/* + * S/390 specific non posix ptrace requests. I chose unusual values so + * they are unlikely to clash with future ptrace definitions. + */ +#define PTRACE_PEEKUSR_AREA 0x5000 +#define PTRACE_POKEUSR_AREA 0x5001 +#define PTRACE_PEEKTEXT_AREA 0x5002 +#define PTRACE_PEEKDATA_AREA 0x5003 +#define PTRACE_POKETEXT_AREA 0x5004 +#define PTRACE_POKEDATA_AREA 0x5005 +#define PTRACE_GET_LAST_BREAK 0x5006 +#define PTRACE_PEEK_SYSTEM_CALL 0x5007 +#define PTRACE_POKE_SYSTEM_CALL 0x5008 +#define PTRACE_ENABLE_TE 0x5009 +#define PTRACE_DISABLE_TE 0x5010 +#define PTRACE_TE_ABORT_RAND 0x5011 + +/* + * The numbers chosen here are somewhat arbitrary but absolutely MUST + * not overlap with any of the number assigned in . + */ +#define PTRACE_SINGLEBLOCK 12 /* resume execution until next branch */ + +/* + * PT_PROT definition is loosely based on hppa bsd definition in + * gdb/hppab-nat.c + */ +#define PTRACE_PROT 21 + +typedef enum { + ptprot_set_access_watchpoint, + ptprot_set_write_watchpoint, + ptprot_disable_watchpoint +} ptprot_flags; + +typedef struct { + unsigned long lowaddr; + unsigned long hiaddr; + ptprot_flags prot; +} ptprot_area; + +/* Sequence of bytes for breakpoint illegal instruction. */ +#define S390_BREAKPOINT {0x0,0x1} +#define S390_BREAKPOINT_U16 ((__u16)0x0001) +#define S390_SYSCALL_OPCODE ((__u16)0x0a00) +#define S390_SYSCALL_SIZE 2 + +/* + * The user_regs_struct defines the way the user registers are + * store on the stack for signal handling. + */ +struct user_regs_struct { + psw_t psw; + unsigned long gprs[NUM_GPRS]; + unsigned int acrs[NUM_ACRS]; + unsigned long orig_gpr2; + s390_fp_regs fp_regs; + /* + * These per registers are in here so that gdb can modify them + * itself as there is no "official" ptrace interface for hardware + * watchpoints. This is the way intel does it. + */ + per_struct per_info; + unsigned long ieee_instruction_pointer; /* obsolete, always 0 */ +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* _UAPI_S390_PTRACE_H */ diff --git a/tools/include/uapi/asm-generic/bpf_perf_event.h b/tools/include/uapi/asm-generic/bpf_perf_event.h new file mode 100644 index 000000000000..53815d2cd047 --- /dev/null +++ b/tools/include/uapi/asm-generic/bpf_perf_event.h @@ -0,0 +1,9 @@ +#ifndef _UAPI__ASM_GENERIC_BPF_PERF_EVENT_H__ +#define _UAPI__ASM_GENERIC_BPF_PERF_EVENT_H__ + +#include + +/* Export kernel pt_regs structure */ +typedef struct pt_regs bpf_user_pt_regs_t; + +#endif /* _UAPI__ASM_GENERIC_BPF_PERF_EVENT_H__ */ diff --git a/tools/include/uapi/linux/bpf_perf_event.h b/tools/include/uapi/linux/bpf_perf_event.h index 067427259820..8f95303f9d80 100644 --- a/tools/include/uapi/linux/bpf_perf_event.h +++ b/tools/include/uapi/linux/bpf_perf_event.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* Copyright (c) 2016 Facebook * * This program is free software; you can redistribute it and/or @@ -7,11 +8,10 @@ #ifndef _UAPI__LINUX_BPF_PERF_EVENT_H__ #define _UAPI__LINUX_BPF_PERF_EVENT_H__ -#include -#include +#include struct bpf_perf_event_data { - struct pt_regs regs; + bpf_user_pt_regs_t regs; __u64 sample_period; }; diff --git a/tools/testing/selftests/bpf/Makefile b/tools/testing/selftests/bpf/Makefile index 333a48655ee0..21a2d76b67dc 100644 --- a/tools/testing/selftests/bpf/Makefile +++ b/tools/testing/selftests/bpf/Makefile @@ -1,7 +1,19 @@ # SPDX-License-Identifier: GPL-2.0 + +ifeq ($(srctree),) +srctree := $(patsubst %/,%,$(dir $(CURDIR))) +srctree := $(patsubst %/,%,$(dir $(srctree))) +srctree := $(patsubst %/,%,$(dir $(srctree))) +srctree := $(patsubst %/,%,$(dir $(srctree))) +endif +include $(srctree)/tools/scripts/Makefile.arch + +$(call detected_var,SRCARCH) + LIBDIR := ../../../lib BPFDIR := $(LIBDIR)/bpf APIDIR := ../../../include/uapi +ASMDIR:= ../../../arch/$(ARCH)/include/uapi GENDIR := ../../../../include/generated GENHDR := $(GENDIR)/autoconf.h @@ -9,7 +21,7 @@ ifneq ($(wildcard $(GENHDR)),) GENFLAGS := -DHAVE_GENHDR endif -CFLAGS += -Wall -O2 -I$(APIDIR) -I$(LIBDIR) -I$(GENDIR) $(GENFLAGS) -I../../../include +CFLAGS += -Wall -O2 -I$(APIDIR) -I$(ASMDIR) -I$(LIBDIR) -I$(GENDIR) $(GENFLAGS) -I../../../include LDLIBS += -lcap -lelf TEST_GEN_PROGS = test_verifier test_tag test_maps test_lru_map test_lpm_map test_progs \ -- GitLab From a81c42136604fb660b366d1ff6d9e0969f166413 Mon Sep 17 00:00:00 2001 From: Hendrik Brueckner Date: Mon, 4 Dec 2017 10:56:49 +0100 Subject: [PATCH 0671/2547] perf s390: add regs_query_register_offset() The regs_query_register_offset() helper function converts register name like "%r0" to an offset of a register in user_pt_regs It is required by the BPF prologue generator. The user_pt_regs structure was recently added to "asm/ptrace.h". Hence, update tools/perf/check-headers.sh to keep the header file in sync with kernel changes. Suggested-by: Thomas Richter Signed-off-by: Hendrik Brueckner Reviewed-and-tested-by: Thomas Richter Acked-by: Alexei Starovoitov Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Heiko Carstens Signed-off-by: Daniel Borkmann --- tools/perf/arch/s390/Makefile | 1 + tools/perf/arch/s390/util/dwarf-regs.c | 32 +++++++++++++++++++++++--- tools/perf/check-headers.sh | 1 + 3 files changed, 31 insertions(+), 3 deletions(-) diff --git a/tools/perf/arch/s390/Makefile b/tools/perf/arch/s390/Makefile index 21322e0385b8..09ba923debe8 100644 --- a/tools/perf/arch/s390/Makefile +++ b/tools/perf/arch/s390/Makefile @@ -2,3 +2,4 @@ ifndef NO_DWARF PERF_HAVE_DWARF_REGS := 1 endif HAVE_KVM_STAT_SUPPORT := 1 +PERF_HAVE_ARCH_REGS_QUERY_REGISTER_OFFSET := 1 diff --git a/tools/perf/arch/s390/util/dwarf-regs.c b/tools/perf/arch/s390/util/dwarf-regs.c index f47576ce13ea..a8ace5cc6301 100644 --- a/tools/perf/arch/s390/util/dwarf-regs.c +++ b/tools/perf/arch/s390/util/dwarf-regs.c @@ -2,17 +2,43 @@ /* * Mapping of DWARF debug register numbers into register names. * - * Copyright IBM Corp. 2010 - * Author(s): Heiko Carstens , + * Copyright IBM Corp. 2010, 2017 + * Author(s): Heiko Carstens , + * Hendrik Brueckner * */ +#include #include -#include +#include #include +#include +#include +#include #include "dwarf-regs-table.h" const char *get_arch_regstr(unsigned int n) { return (n >= ARRAY_SIZE(s390_dwarf_regs)) ? NULL : s390_dwarf_regs[n]; } + +/* + * Convert the register name into an offset to struct pt_regs (kernel). + * This is required by the BPF prologue generator. The BPF + * program is called in the BPF overflow handler in the perf + * core. + */ +int regs_query_register_offset(const char *name) +{ + unsigned long gpr; + + if (!name || strncmp(name, "%r", 2)) + return -EINVAL; + + errno = 0; + gpr = strtoul(name + 2, NULL, 10); + if (errno || gpr >= 16) + return -EINVAL; + + return offsetof(user_pt_regs, gprs) + 8 * gpr; +} diff --git a/tools/perf/check-headers.sh b/tools/perf/check-headers.sh index 77406d25e521..6db9d809fe97 100755 --- a/tools/perf/check-headers.sh +++ b/tools/perf/check-headers.sh @@ -30,6 +30,7 @@ arch/x86/include/uapi/asm/vmx.h arch/powerpc/include/uapi/asm/kvm.h arch/s390/include/uapi/asm/kvm.h arch/s390/include/uapi/asm/kvm_perf.h +arch/s390/include/uapi/asm/ptrace.h arch/s390/include/uapi/asm/sie.h arch/arm/include/uapi/asm/kvm.h arch/arm64/include/uapi/asm/kvm.h -- GitLab From 567deca8e72df3ceb6c07c63f8541a4928f64d3b Mon Sep 17 00:00:00 2001 From: Ihab Zhaika Date: Thu, 16 Nov 2017 09:29:19 +0200 Subject: [PATCH 0672/2547] iwlwifi: add new cards for 9260 and 22000 series add 1 PCI ID for 9260 series and 1 for 22000 series. Cc: stable@vger.kernel.org Signed-off-by: Ihab Zhaika Signed-off-by: Luca Coelho --- drivers/net/wireless/intel/iwlwifi/pcie/drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c index f21fe59faccf..ccd7c33c4c28 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c @@ -553,6 +553,7 @@ static const struct pci_device_id iwl_hw_card_ids[] = { {IWL_PCI_DEVICE(0x271B, 0x0014, iwl9160_2ac_cfg)}, {IWL_PCI_DEVICE(0x271B, 0x0210, iwl9160_2ac_cfg)}, {IWL_PCI_DEVICE(0x271B, 0x0214, iwl9260_2ac_cfg)}, + {IWL_PCI_DEVICE(0x271C, 0x0214, iwl9260_2ac_cfg)}, {IWL_PCI_DEVICE(0x2720, 0x0034, iwl9560_2ac_cfg)}, {IWL_PCI_DEVICE(0x2720, 0x0038, iwl9560_2ac_cfg)}, {IWL_PCI_DEVICE(0x2720, 0x003C, iwl9560_2ac_cfg)}, @@ -664,6 +665,7 @@ static const struct pci_device_id iwl_hw_card_ids[] = { {IWL_PCI_DEVICE(0x2720, 0x0310, iwla000_2ac_cfg_hr_cdb)}, {IWL_PCI_DEVICE(0x40C0, 0x0000, iwla000_2ax_cfg_hr)}, {IWL_PCI_DEVICE(0x40C0, 0x0A10, iwla000_2ax_cfg_hr)}, + {IWL_PCI_DEVICE(0xA0F0, 0x0000, iwla000_2ax_cfg_hr)}, #endif /* CONFIG_IWLMVM */ -- GitLab From 6c2d49fdc5d947c5fe89935bd52e69f10000f4cb Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Mon, 13 Nov 2017 17:26:09 +0100 Subject: [PATCH 0673/2547] iwlwifi: mvm: flush queue before deleting ROC Before deleting a time event (remain-on-channel instance), flush the queue so that frames cannot get stuck on it. We already flush the AUX STA queues, but a separate station is used for the P2P Device queue. Cc: stable@vger.kernel.org Signed-off-by: Johannes Berg Signed-off-by: Luca Coelho --- drivers/net/wireless/intel/iwlwifi/mvm/mvm.h | 2 ++ .../wireless/intel/iwlwifi/mvm/time-event.c | 24 +++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h index 6a9a25beab3f..55ab5349dd40 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h +++ b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h @@ -1061,6 +1061,7 @@ struct iwl_mvm { * @IWL_MVM_STATUS_ROC_AUX_RUNNING: AUX remain-on-channel is running * @IWL_MVM_STATUS_D3_RECONFIG: D3 reconfiguration is being done * @IWL_MVM_STATUS_FIRMWARE_RUNNING: firmware is running + * @IWL_MVM_STATUS_NEED_FLUSH_P2P: need to flush P2P bcast STA */ enum iwl_mvm_status { IWL_MVM_STATUS_HW_RFKILL, @@ -1072,6 +1073,7 @@ enum iwl_mvm_status { IWL_MVM_STATUS_ROC_AUX_RUNNING, IWL_MVM_STATUS_D3_RECONFIG, IWL_MVM_STATUS_FIRMWARE_RUNNING, + IWL_MVM_STATUS_NEED_FLUSH_P2P, }; /* Keep track of completed init configuration */ diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c b/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c index 4d0314912e94..e25cda9fbf6c 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c @@ -132,6 +132,24 @@ void iwl_mvm_roc_done_wk(struct work_struct *wk) * executed, and a new time event means a new command. */ iwl_mvm_flush_sta(mvm, &mvm->aux_sta, true, CMD_ASYNC); + + /* Do the same for the P2P device queue (STA) */ + if (test_and_clear_bit(IWL_MVM_STATUS_NEED_FLUSH_P2P, &mvm->status)) { + struct iwl_mvm_vif *mvmvif; + + /* + * NB: access to this pointer would be racy, but the flush bit + * can only be set when we had a P2P-Device VIF, and we have a + * flush of this work in iwl_mvm_prepare_mac_removal() so it's + * not really racy. + */ + + if (!WARN_ON(!mvm->p2p_device_vif)) { + mvmvif = iwl_mvm_vif_from_mac80211(mvm->p2p_device_vif); + iwl_mvm_flush_sta(mvm, &mvmvif->bcast_sta, true, + CMD_ASYNC); + } + } } static void iwl_mvm_roc_finished(struct iwl_mvm *mvm) @@ -855,10 +873,12 @@ void iwl_mvm_stop_roc(struct iwl_mvm *mvm) mvmvif = iwl_mvm_vif_from_mac80211(te_data->vif); - if (te_data->vif->type == NL80211_IFTYPE_P2P_DEVICE) + if (te_data->vif->type == NL80211_IFTYPE_P2P_DEVICE) { iwl_mvm_remove_time_event(mvm, mvmvif, te_data); - else + set_bit(IWL_MVM_STATUS_NEED_FLUSH_P2P, &mvm->status); + } else { iwl_mvm_remove_aux_roc_te(mvm, mvmvif, te_data); + } iwl_mvm_roc_finished(mvm); } -- GitLab From 9d0fc5a50a0548f8e5d61243e5e5f26d5c405aef Mon Sep 17 00:00:00 2001 From: David Spinadel Date: Mon, 21 Nov 2016 17:01:25 +0200 Subject: [PATCH 0674/2547] iwlwifi: mvm: enable RX offloading with TKIP and WEP Set the flag that indicates that ICV was stripped on if this option was enabled in the HW. Cc: stable@vger.kernel.org # 4.13+ [this is needed for the 9000-series HW to work properly] Signed-off-by: David Spinadel Signed-off-by: Luca Coelho --- drivers/net/wireless/intel/iwlwifi/iwl-trans.h | 4 +++- drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c | 12 +++++++++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-trans.h b/drivers/net/wireless/intel/iwlwifi/iwl-trans.h index ca0b5536a8a6..921cab9e2d73 100644 --- a/drivers/net/wireless/intel/iwlwifi/iwl-trans.h +++ b/drivers/net/wireless/intel/iwlwifi/iwl-trans.h @@ -117,6 +117,7 @@ #define FH_RSCSR_FRAME_INVALID 0x55550000 #define FH_RSCSR_FRAME_ALIGN 0x40 #define FH_RSCSR_RPA_EN BIT(25) +#define FH_RSCSR_RADA_EN BIT(26) #define FH_RSCSR_RXQ_POS 16 #define FH_RSCSR_RXQ_MASK 0x3F0000 @@ -128,7 +129,8 @@ struct iwl_rx_packet { * 31: flag flush RB request * 30: flag ignore TC (terminal counter) request * 29: flag fast IRQ request - * 28-26: Reserved + * 28-27: Reserved + * 26: RADA enabled * 25: Offload enabled * 24: RPF enabled * 23: RSS enabled diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c b/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c index 20fe23fbf040..bf8409d8a132 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c @@ -234,8 +234,8 @@ static void iwl_mvm_get_signal_strength(struct iwl_mvm *mvm, static int iwl_mvm_rx_crypto(struct iwl_mvm *mvm, struct ieee80211_hdr *hdr, struct ieee80211_rx_status *stats, - struct iwl_rx_mpdu_desc *desc, int queue, - u8 *crypt_len) + struct iwl_rx_mpdu_desc *desc, u32 pkt_flags, + int queue, u8 *crypt_len) { u16 status = le16_to_cpu(desc->status); @@ -272,6 +272,10 @@ static int iwl_mvm_rx_crypto(struct iwl_mvm *mvm, struct ieee80211_hdr *hdr, if ((status & IWL_RX_MPDU_STATUS_SEC_MASK) == IWL_RX_MPDU_STATUS_SEC_WEP) *crypt_len = IEEE80211_WEP_IV_LEN; + + if (pkt_flags & FH_RSCSR_RADA_EN) + stats->flag |= RX_FLAG_ICV_STRIPPED; + return 0; case IWL_RX_MPDU_STATUS_SEC_EXT_ENC: if (!(status & IWL_RX_MPDU_STATUS_MIC_OK)) @@ -850,7 +854,9 @@ void iwl_mvm_rx_mpdu_mq(struct iwl_mvm *mvm, struct napi_struct *napi, rx_status = IEEE80211_SKB_RXCB(skb); - if (iwl_mvm_rx_crypto(mvm, hdr, rx_status, desc, queue, &crypt_len)) { + if (iwl_mvm_rx_crypto(mvm, hdr, rx_status, desc, + le32_to_cpu(pkt->len_n_flags), queue, + &crypt_len)) { kfree_skb(skb); return; } -- GitLab From bf19037074e770aad74b3b90f37b8b98db3f3748 Mon Sep 17 00:00:00 2001 From: Sara Sharon Date: Mon, 8 Feb 2016 23:30:47 +0200 Subject: [PATCH 0675/2547] iwlwifi: mvm: mark MIC stripped MPDUs When RADA is active, the hardware decrypts the packets and strips off the MIC as it is useless after decryption. Indicate that to mac80211. Cc: stable@vger.kernel.org # 4.13+ [this is needed for the 9000-series HW to work properly] Signed-off-by: Sara Sharon Signed-off-by: Luca Coelho --- drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c b/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c index bf8409d8a132..3b8d44361380 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c @@ -255,6 +255,8 @@ static int iwl_mvm_rx_crypto(struct iwl_mvm *mvm, struct ieee80211_hdr *hdr, return -1; stats->flag |= RX_FLAG_DECRYPTED; + if (pkt_flags & FH_RSCSR_RADA_EN) + stats->flag |= RX_FLAG_MIC_STRIPPED; *crypt_len = IEEE80211_CCMP_HDR_LEN; return 0; case IWL_RX_MPDU_STATUS_SEC_TKIP: -- GitLab From ca0168e8a77cf833f8c9ac1d26a3a4012bab4f72 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Tue, 5 Dec 2017 09:32:25 -0500 Subject: [PATCH 0676/2547] alloc_super(): do ->s_umount initialization earlier ... so that failure exits could count on it having been done. Signed-off-by: Al Viro --- fs/super.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/fs/super.c b/fs/super.c index d4e33e8f1e6f..7ff1349609e4 100644 --- a/fs/super.c +++ b/fs/super.c @@ -191,6 +191,24 @@ static struct super_block *alloc_super(struct file_system_type *type, int flags, INIT_LIST_HEAD(&s->s_mounts); s->s_user_ns = get_user_ns(user_ns); + init_rwsem(&s->s_umount); + lockdep_set_class(&s->s_umount, &type->s_umount_key); + /* + * sget() can have s_umount recursion. + * + * When it cannot find a suitable sb, it allocates a new + * one (this one), and tries again to find a suitable old + * one. + * + * In case that succeeds, it will acquire the s_umount + * lock of the old one. Since these are clearly distrinct + * locks, and this object isn't exposed yet, there's no + * risk of deadlocks. + * + * Annotate this by putting this lock in a different + * subclass. + */ + down_write_nested(&s->s_umount, SINGLE_DEPTH_NESTING); if (security_sb_alloc(s)) goto fail; @@ -218,25 +236,6 @@ static struct super_block *alloc_super(struct file_system_type *type, int flags, goto fail; if (list_lru_init_memcg(&s->s_inode_lru)) goto fail; - - init_rwsem(&s->s_umount); - lockdep_set_class(&s->s_umount, &type->s_umount_key); - /* - * sget() can have s_umount recursion. - * - * When it cannot find a suitable sb, it allocates a new - * one (this one), and tries again to find a suitable old - * one. - * - * In case that succeeds, it will acquire the s_umount - * lock of the old one. Since these are clearly distrinct - * locks, and this object isn't exposed yet, there's no - * risk of deadlocks. - * - * Annotate this by putting this lock in a different - * subclass. - */ - down_write_nested(&s->s_umount, SINGLE_DEPTH_NESTING); s->s_count = 1; atomic_set(&s->s_active, 1); mutex_init(&s->s_vfs_rename_mutex); -- GitLab From 66bc5df31110652a31c91f14b4e23f7c51e5328e Mon Sep 17 00:00:00 2001 From: Martijn Coenen Date: Tue, 5 Dec 2017 12:40:17 +0100 Subject: [PATCH 0677/2547] MAINTAINERS: update Android driver maintainers. Add Todd Kjos and myself, remove Riley (who no longer works at Google). Signed-off-by: Martijn Coenen Signed-off-by: Greg Kroah-Hartman --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index aa71ab52fd76..da8264fc09d4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -859,7 +859,8 @@ F: kernel/configs/android* ANDROID DRIVERS M: Greg Kroah-Hartman M: Arve Hjønnevåg -M: Riley Andrews +M: Todd Kjos +M: Martijn Coenen T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git L: devel@driverdev.osuosl.org S: Supported -- GitLab From dda4b8f73231e70df32f3a218b7ceb6704ec860c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 30 Nov 2017 10:29:51 +0000 Subject: [PATCH 0678/2547] drm/i915: Skip switch-to-kernel-context on suspend when wedged If the HW is already wedged, attempting to submit a request will generate an -EIO. If we tried this during suspend, we would abort whereas all we want to do is to go sleep and throw away the corrupt state. Fixes: 5ab57c702069 ("drm/i915: Flush logical context image out to memory upon suspend") Testcase: igt/gem_eio/suspend Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171130102951.14965-1-chris@chris-wilson.co.uk (cherry picked from commit ecf73eb2d27d43b2153bb80671768a06d35521f1) Signed-off-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 3a140eedfc83..46bdea2de268 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4712,17 +4712,19 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv) * state. Fortunately, the kernel_context is disposable and we do * not rely on its state. */ - ret = i915_gem_switch_to_kernel_context(dev_priv); - if (ret) - goto err_unlock; + if (!i915_terminally_wedged(&dev_priv->gpu_error)) { + ret = i915_gem_switch_to_kernel_context(dev_priv); + if (ret) + goto err_unlock; - ret = i915_gem_wait_for_idle(dev_priv, - I915_WAIT_INTERRUPTIBLE | - I915_WAIT_LOCKED); - if (ret && ret != -EIO) - goto err_unlock; + ret = i915_gem_wait_for_idle(dev_priv, + I915_WAIT_INTERRUPTIBLE | + I915_WAIT_LOCKED); + if (ret && ret != -EIO) + goto err_unlock; - assert_kernel_context_is_current(dev_priv); + assert_kernel_context_is_current(dev_priv); + } i915_gem_contexts_lost(dev_priv); mutex_unlock(&dev->struct_mutex); -- GitLab From a87e55f89f0b0dc541d89248a8445635936a3858 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 29 Nov 2017 17:37:30 +0200 Subject: [PATCH 0679/2547] drm/i915: Fix vblank timestamp/frame counter jumps on gen2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Previously I was under the impression that the scanline counter reads 0 when the pipe is off. Turns out that's not correct, and instead the scanline counter simply stops when the pipe stops, and it retains it's last value until the pipe starts up again, at which point the scanline counter jumps to vblank start. These jumps can cause the timestamp to jump backwards by one frame. Since we use the timestamps to guesstimage also the frame counter value on gen2, that would cause the frame counter to also jump backwards, which leads to a massice difference from the previous value. The end result is that flips/vblank events don't appear to complete as they're stuck waiting for the frame counter to catch up to that massive difference. Fix the problem properly by actually making sure the scanline counter has started to move before we assume that it's safe to enable vblank processing. v2: Less pointless duplication in the code (Chris) Cc: stable@vger.kernel.org Cc: Daniel Vetter Cc: Chris Wilson Reviewed-by: Chris Wilson Fixes: b7792d8b54cc ("drm/i915: Wait for pipe to start before sampling vblank timestamps on gen2") Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171129153732.3612-1-ville.syrjala@linux.intel.com (cherry picked from commit 8fedd64dabc86d0f31a0d1e152be3aa23c323553) Signed-off-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_display.c | 51 +++++++++++++++++++--------- 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 878acc432a4b..e8ccf89cb17b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1000,7 +1000,8 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, return crtc->config->cpu_transcoder; } -static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) +static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, + enum pipe pipe) { i915_reg_t reg = PIPEDSL(pipe); u32 line1, line2; @@ -1015,7 +1016,28 @@ static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) msleep(5); line2 = I915_READ(reg) & line_mask; - return line1 == line2; + return line1 != line2; +} + +static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + + /* Wait for the display line to settle/start moving */ + if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) + DRM_ERROR("pipe %c scanline %s wait timed out\n", + pipe_name(pipe), onoff(state)); +} + +static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) +{ + wait_for_pipe_scanline_moving(crtc, false); +} + +static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) +{ + wait_for_pipe_scanline_moving(crtc, true); } /* @@ -1038,7 +1060,6 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; - enum pipe pipe = crtc->pipe; if (INTEL_GEN(dev_priv) >= 4) { i915_reg_t reg = PIPECONF(cpu_transcoder); @@ -1049,9 +1070,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) 100)) WARN(1, "pipe_off wait timed out\n"); } else { - /* Wait for the display line to settle */ - if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) - WARN(1, "pipe_off wait timed out\n"); + intel_wait_for_pipe_scanline_stopped(crtc); } } @@ -1936,15 +1955,14 @@ static void intel_enable_pipe(struct intel_crtc *crtc) POSTING_READ(reg); /* - * Until the pipe starts DSL will read as 0, which would cause - * an apparent vblank timestamp jump, which messes up also the - * frame count when it's derived from the timestamps. So let's - * wait for the pipe to start properly before we call - * drm_crtc_vblank_on() + * Until the pipe starts PIPEDSL reads will return a stale value, + * which causes an apparent vblank timestamp jump when PIPEDSL + * resets to its proper value. That also messes up the frame count + * when it's derived from the timestamps. So let's wait for the + * pipe to start properly before we call drm_crtc_vblank_on() */ - if (dev->max_vblank_count == 0 && - wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) - DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); + if (dev->max_vblank_count == 0) + intel_wait_for_pipe_scanline_moving(crtc); } /** @@ -14643,6 +14661,8 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); + DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n", pipe_name(pipe)); @@ -14652,8 +14672,7 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) I915_WRITE(PIPECONF(pipe), 0); POSTING_READ(PIPECONF(pipe)); - if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) - DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe)); + intel_wait_for_pipe_scanline_stopped(crtc); I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); POSTING_READ(DPLL(pipe)); -- GitLab From 46442beed972d439210580739bc006713375c5b4 Mon Sep 17 00:00:00 2001 From: James Ausmus Date: Thu, 30 Nov 2017 18:17:00 -0800 Subject: [PATCH 0680/2547] drm/i915/cnl: Mask previous DDI - PLL mapping Without masking out the old value, we can end up pointing the DDI to a disabled PLL, which makes the system fall over. Mask out the previous value before setting the PLL to DDI mapping. This can be observed by running igt/testdisplay with both an eDP and HDMI/DP output active. v2: Add the Bugzilla link Fixes: 555e38d273172 ("drm/i915/cnl: DDI - PLL mapping") Testcase: igt/testdisplay Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103997 Cc: Rodrigo Vivi Cc: Matt Atwood Signed-off-by: James Ausmus Reviewed-by: Rodrigo Vivi Tested-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20171201021700.13504-1-james.ausmus@intel.com (cherry picked from commit 23a7068ec581fcc6fb61039448632d25987b1fae) Signed-off-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_ddi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 933c18fd4258..e0843bb99169 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2131,6 +2131,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, if (IS_CANNONLAKE(dev_priv)) { /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ val = I915_READ(DPCLKA_CFGCR0); + val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port); I915_WRITE(DPCLKA_CFGCR0, val); -- GitLab From be17f1ce8572d6e15559897421fb7041360bb64a Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 30 Nov 2017 15:49:10 +0100 Subject: [PATCH 0681/2547] mmc: core: properly init drv_type When the latest version of parsing the new eMMC bindings was moved from core.c to mmc.c, it was overlooked that drv_type could be used uninitialized. Fix it! Fixes: 6186d06c519e21 ("mmc: parse new binding for eMMC fixed driver type") Reported-by: Colin Ian King Reported-by: Dan Carpenter Signed-off-by: Wolfram Sang Signed-off-by: Ulf Hansson --- drivers/mmc/core/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index d209fb466979..208a762b87ef 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -1290,7 +1290,7 @@ int mmc_hs400_to_hs200(struct mmc_card *card) static void mmc_select_driver_type(struct mmc_card *card) { - int card_drv_type, drive_strength, drv_type; + int card_drv_type, drive_strength, drv_type = 0; int fixed_drv_type = card->host->fixed_drv_type; card_drv_type = card->ext_csd.raw_driver_strength | -- GitLab From b7ad7ef742a99c148631d38a98da72e7db8f6fd0 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 5 Dec 2017 08:23:20 -0800 Subject: [PATCH 0682/2547] remove task and stack pointer printout from oops dump Geert Uytterhoeven reported a NFS oops, and pointed out that some of the numbers were hashed and useless. We could just turn them from '%p' into '%px', but those numbers are really just legacy, and useless even when not hashed. So just remove them entirely. Reported-by: Geert Uytterhoeven Signed-off-by: Linus Torvalds --- kernel/printk/printk.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c index 5d81206a572d..b9006617710f 100644 --- a/kernel/printk/printk.c +++ b/kernel/printk/printk.c @@ -3141,9 +3141,6 @@ void dump_stack_print_info(const char *log_lvl) void show_regs_print_info(const char *log_lvl) { dump_stack_print_info(log_lvl); - - printk("%stask: %p task.stack: %p\n", - log_lvl, current, task_stack_page(current)); } #endif -- GitLab From e599ea1410c3a2f55716f9c309587235cca32025 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 1 Dec 2017 15:28:44 -0800 Subject: [PATCH 0683/2547] Revert "tcp: must block bh in __inet_twsk_hashdance()" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We had to disable BH _before_ calling __inet_twsk_hashdance() in commit cfac7f836a71 ("tcp/dccp: block bh before arming time_wait timer"). This means we can revert 614bdd4d6e61 ("tcp: must block bh in __inet_twsk_hashdance()"). Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller --- net/ipv4/inet_timewait_sock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/net/ipv4/inet_timewait_sock.c b/net/ipv4/inet_timewait_sock.c index c690cd0d9b3f..b563e0c46bac 100644 --- a/net/ipv4/inet_timewait_sock.c +++ b/net/ipv4/inet_timewait_sock.c @@ -93,7 +93,7 @@ static void inet_twsk_add_bind_node(struct inet_timewait_sock *tw, } /* - * Enter the time wait state. + * Enter the time wait state. This is called with locally disabled BH. * Essentially we whip up a timewait bucket, copy the relevant info into it * from the SK, and mess with hash chains and list linkage. */ @@ -111,7 +111,7 @@ void __inet_twsk_hashdance(struct inet_timewait_sock *tw, struct sock *sk, */ bhead = &hashinfo->bhash[inet_bhashfn(twsk_net(tw), inet->inet_num, hashinfo->bhash_size)]; - spin_lock_bh(&bhead->lock); + spin_lock(&bhead->lock); tw->tw_tb = icsk->icsk_bind_hash; WARN_ON(!icsk->icsk_bind_hash); inet_twsk_add_bind_node(tw, &tw->tw_tb->owners); @@ -137,7 +137,7 @@ void __inet_twsk_hashdance(struct inet_timewait_sock *tw, struct sock *sk, if (__sk_nulls_del_node_init_rcu(sk)) sock_prot_inuse_add(sock_net(sk), sk->sk_prot, -1); - spin_unlock_bh(lock); + spin_unlock(lock); } EXPORT_SYMBOL_GPL(__inet_twsk_hashdance); -- GitLab From d364b038bc962f494cffb8f6cb6cddbe41bcb5b6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 4 Dec 2017 08:27:17 -0800 Subject: [PATCH 0684/2547] ARM: dts: Fix elm interrupt compiler warning Looks like the interrupt property is missing the controller and level information causing: Warning (interrupts_property): interrupts size is (4), expected multiple of 12 in /ocp/elm@48078000 Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 1dc5a76b3c71..22b377d35201 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -398,7 +398,7 @@ elm: elm@48078000 { compatible = "ti,am3352-elm"; reg = <0x48078000 0x2000>; - interrupts = <4>; + interrupts = ; ti,hwmods = "elm"; status = "disabled"; }; -- GitLab From c22fe696157dc94a25cc5396b43b29b6d6f4a189 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 4 Dec 2017 08:27:18 -0800 Subject: [PATCH 0685/2547] ARM: dts: Fix dm814x missing phy-cells property We have phy-cells for usb_phy0, but it's missing for usb_phy1 and we get: Warning (phys_property): Missing property '#phy-cells' in node /ocp/l4ls@48000000/control@140000/usb-phy@1b00 or bad phandle (referred from /ocp/usb@47400000/usb@47401800:phys[0]) Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 9708157f5daf..46f3ee744526 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -385,6 +385,7 @@ reg = <0x1b00 0x100>; reg-names = "phy"; ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; }; }; -- GitLab From 42d779ffc186f6dd26271fc60a7417cb51aca93e Mon Sep 17 00:00:00 2001 From: Pieter Jansen van Vuuren Date: Fri, 1 Dec 2017 21:37:23 -0800 Subject: [PATCH 0686/2547] nfp: fix port stats for mac representors Previously we swapped the tx_packets, tx_bytes and tx_dropped counters with rx_packets, rx_bytes and rx_dropped counters, respectively. This behaviour is correct and expected for VF representors but it should not be swapped for physical port mac representors. Fixes: eadfa4c3be99 ("nfp: add stats and xmit helpers for representors") Signed-off-by: Pieter Jansen van Vuuren Reviewed-by: Simon Horman Reviewed-by: Jakub Kicinski Signed-off-by: David S. Miller --- drivers/net/ethernet/netronome/nfp/nfp_net_repr.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/netronome/nfp/nfp_net_repr.c b/drivers/net/ethernet/netronome/nfp/nfp_net_repr.c index 924a05e05da0..78b36c67c232 100644 --- a/drivers/net/ethernet/netronome/nfp/nfp_net_repr.c +++ b/drivers/net/ethernet/netronome/nfp/nfp_net_repr.c @@ -84,16 +84,13 @@ nfp_repr_phy_port_get_stats64(struct nfp_port *port, { u8 __iomem *mem = port->eth_stats; - /* TX and RX stats are flipped as we are returning the stats as seen - * at the switch port corresponding to the phys port. - */ - stats->tx_packets = readq(mem + NFP_MAC_STATS_RX_FRAMES_RECEIVED_OK); - stats->tx_bytes = readq(mem + NFP_MAC_STATS_RX_IN_OCTETS); - stats->tx_dropped = readq(mem + NFP_MAC_STATS_RX_IN_ERRORS); + stats->tx_packets = readq(mem + NFP_MAC_STATS_TX_FRAMES_TRANSMITTED_OK); + stats->tx_bytes = readq(mem + NFP_MAC_STATS_TX_OUT_OCTETS); + stats->tx_dropped = readq(mem + NFP_MAC_STATS_TX_OUT_ERRORS); - stats->rx_packets = readq(mem + NFP_MAC_STATS_TX_FRAMES_TRANSMITTED_OK); - stats->rx_bytes = readq(mem + NFP_MAC_STATS_TX_OUT_OCTETS); - stats->rx_dropped = readq(mem + NFP_MAC_STATS_TX_OUT_ERRORS); + stats->rx_packets = readq(mem + NFP_MAC_STATS_RX_FRAMES_RECEIVED_OK); + stats->rx_bytes = readq(mem + NFP_MAC_STATS_RX_IN_OCTETS); + stats->rx_dropped = readq(mem + NFP_MAC_STATS_RX_IN_ERRORS); } static void -- GitLab From 029b6d1405504984b9d2661110ff1a17467d3426 Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Sat, 2 Dec 2017 08:41:55 +0100 Subject: [PATCH 0687/2547] Revert "net: core: maybe return -EEXIST in __dev_alloc_name" This reverts commit d6f295e9def0; some userspace (in the case we noticed it's wpa_supplicant), is relying on the current error code to determine that a fixed name interface already exists. Reported-by: Jouni Malinen Signed-off-by: Johannes Berg Signed-off-by: David S. Miller --- net/core/dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/core/dev.c b/net/core/dev.c index 07ed21d64f92..f47e96b62308 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -1106,7 +1106,7 @@ static int __dev_alloc_name(struct net *net, const char *name, char *buf) * when the name is long and there isn't enough space left * for the digits, or if all bits are used. */ - return p ? -ENFILE : -EEXIST; + return -ENFILE; } static int dev_alloc_name_ns(struct net *net, -- GitLab From 58117672943734715bbe7565ac9f062effa524f0 Mon Sep 17 00:00:00 2001 From: Zumeng Chen Date: Mon, 4 Dec 2017 11:22:02 +0800 Subject: [PATCH 0688/2547] gianfar: fix a flooded alignment reports because of padding issue. According to LS1021A RM, the value of PAL can be set so that the start of the IP header in the receive data buffer is aligned to a 32-bit boundary. Normally, setting PAL = 2 provides minimal padding to ensure such alignment of the IP header. However every incoming packet's 8-byte time stamp will be inserted into the packet data buffer as padding alignment bytes when hardware time stamping is enabled. So we set the padding 8+2 here to avoid the flooded alignment faults: root@128:~# cat /proc/cpu/alignment User: 0 System: 17539 (inet_gro_receive+0x114/0x2c0) Skipped: 0 Half: 0 Word: 0 DWord: 0 Multi: 17539 User faults: 2 (fixup) Also shown when exception report enablement CPU: 0 PID: 161 Comm: irq/66-eth1_g0_ Not tainted 4.1.21-rt13-WR8.0.0.0_preempt-rt #16 Hardware name: Freescale LS1021A [<8001b420>] (unwind_backtrace) from [<8001476c>] (show_stack+0x20/0x24) [<8001476c>] (show_stack) from [<807cfb48>] (dump_stack+0x94/0xac) [<807cfb48>] (dump_stack) from [<80025d70>] (do_alignment+0x720/0x958) [<80025d70>] (do_alignment) from [<80009224>] (do_DataAbort+0x40/0xbc) [<80009224>] (do_DataAbort) from [<80015398>] (__dabt_svc+0x38/0x60) Exception stack(0x86ad1cc0 to 0x86ad1d08) 1cc0: f9b3e080 86b3d072 2d78d287 00000000 866816c0 86b3d05e 86e785d0 00000000 1ce0: 00000011 0000000e 80840ab0 86ad1d3c 86ad1d08 86ad1d08 806d7fc0 806d806c 1d00: 40070013 ffffffff [<80015398>] (__dabt_svc) from [<806d806c>] (inet_gro_receive+0x114/0x2c0) [<806d806c>] (inet_gro_receive) from [<80660eec>] (dev_gro_receive+0x21c/0x3c0) [<80660eec>] (dev_gro_receive) from [<8066133c>] (napi_gro_receive+0x44/0x17c) [<8066133c>] (napi_gro_receive) from [<804f0538>] (gfar_clean_rx_ring+0x39c/0x7d4) [<804f0538>] (gfar_clean_rx_ring) from [<804f0bf4>] (gfar_poll_rx_sq+0x58/0xe0) [<804f0bf4>] (gfar_poll_rx_sq) from [<80660b10>] (net_rx_action+0x27c/0x43c) [<80660b10>] (net_rx_action) from [<80033638>] (do_current_softirqs+0x1e0/0x3dc) [<80033638>] (do_current_softirqs) from [<800338c4>] (__local_bh_enable+0x90/0xa8) [<800338c4>] (__local_bh_enable) from [<8008025c>] (irq_forced_thread_fn+0x70/0x84) [<8008025c>] (irq_forced_thread_fn) from [<800805e8>] (irq_thread+0x16c/0x244) [<800805e8>] (irq_thread) from [<8004e490>] (kthread+0xe8/0x104) [<8004e490>] (kthread) from [<8000fda8>] (ret_from_fork+0x14/0x2c) Signed-off-by: Zumeng Chen Signed-off-by: David S. Miller --- drivers/net/ethernet/freescale/gianfar.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c index 5be52d89b182..81a73af0df31 100644 --- a/drivers/net/ethernet/freescale/gianfar.c +++ b/drivers/net/ethernet/freescale/gianfar.c @@ -1378,9 +1378,11 @@ static int gfar_probe(struct platform_device *ofdev) gfar_init_addr_hash_table(priv); - /* Insert receive time stamps into padding alignment bytes */ + /* Insert receive time stamps into padding alignment bytes, and + * plus 2 bytes padding to ensure the cpu alignment. + */ if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) - priv->padding = 8; + priv->padding = 8 + DEFAULT_PADDING; if (dev->features & NETIF_F_IP_CSUM || priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) -- GitLab From 1ee0d3d778f146b982b100ae7add0c4da9626e9a Mon Sep 17 00:00:00 2001 From: Roger He Date: Tue, 21 Nov 2017 09:58:26 +0800 Subject: [PATCH 0689/2547] drm/ttm: use NUM_PAGES_TO_ALLOC always MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 8d7172e8381d..dca4d8322437 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -510,8 +510,7 @@ static int ttm_alloc_new_pages(struct list_head *pages, gfp_t gfp_flags, int r = 0; unsigned i, j, cpages; unsigned npages = 1 << order; - unsigned max_cpages = min(count, - (unsigned)(PAGE_SIZE/sizeof(struct page *))); + unsigned max_cpages = min(count, (unsigned)NUM_PAGES_TO_ALLOC); /* allocate array for page caching change */ caching_array = kmalloc(max_cpages*sizeof(struct page *), GFP_KERNEL); -- GitLab From 6d5e4e3213f4700338627f1f2fba6d3552b1158a Mon Sep 17 00:00:00 2001 From: Roger He Date: Tue, 21 Nov 2017 09:37:52 +0800 Subject: [PATCH 0690/2547] drm/ttm: add page order in page pool MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit to indicate page order for each element in the pool Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 38 ++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index dca4d8322437..bf25ba25bfc6 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -81,6 +81,7 @@ struct ttm_page_pool { char *name; unsigned long nfrees; unsigned long nrefills; + unsigned int order; }; /** @@ -412,6 +413,7 @@ ttm_pool_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) struct ttm_page_pool *pool; int shrink_pages = sc->nr_to_scan; unsigned long freed = 0; + unsigned int nr_free_pool; if (!mutex_trylock(&lock)) return SHRINK_STOP; @@ -421,10 +423,15 @@ ttm_pool_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) unsigned nr_free = shrink_pages; if (shrink_pages == 0) break; + pool = &_manager->pools[(i + pool_offset)%NUM_POOLS]; /* OK to use static buffer since global mutex is held. */ - shrink_pages = ttm_page_pool_free(pool, nr_free, true); - freed += nr_free - shrink_pages; + nr_free_pool = (nr_free >> pool->order); + if (nr_free_pool == 0) + continue; + + shrink_pages = ttm_page_pool_free(pool, nr_free_pool, true); + freed += ((nr_free_pool - shrink_pages) << pool->order); } mutex_unlock(&lock); return freed; @@ -436,9 +443,12 @@ ttm_pool_shrink_count(struct shrinker *shrink, struct shrink_control *sc) { unsigned i; unsigned long count = 0; + struct ttm_page_pool *pool; - for (i = 0; i < NUM_POOLS; ++i) - count += _manager->pools[i].npages; + for (i = 0; i < NUM_POOLS; ++i) { + pool = &_manager->pools[i]; + count += (pool->npages << pool->order); + } return count; } @@ -936,7 +946,7 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, } static void ttm_page_pool_init_locked(struct ttm_page_pool *pool, gfp_t flags, - char *name) + char *name, unsigned int order) { spin_lock_init(&pool->lock); pool->fill_lock = false; @@ -944,11 +954,17 @@ static void ttm_page_pool_init_locked(struct ttm_page_pool *pool, gfp_t flags, pool->npages = pool->nfrees = 0; pool->gfp_flags = flags; pool->name = name; + pool->order = order; } int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages) { int ret; +#ifdef CONFIG_TRANSPARENT_HUGEPAGE + unsigned order = HPAGE_PMD_ORDER; +#else + unsigned order = 0; +#endif WARN_ON(_manager); @@ -956,23 +972,23 @@ int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages) _manager = kzalloc(sizeof(*_manager), GFP_KERNEL); - ttm_page_pool_init_locked(&_manager->wc_pool, GFP_HIGHUSER, "wc"); + ttm_page_pool_init_locked(&_manager->wc_pool, GFP_HIGHUSER, "wc", 0); - ttm_page_pool_init_locked(&_manager->uc_pool, GFP_HIGHUSER, "uc"); + ttm_page_pool_init_locked(&_manager->uc_pool, GFP_HIGHUSER, "uc", 0); ttm_page_pool_init_locked(&_manager->wc_pool_dma32, - GFP_USER | GFP_DMA32, "wc dma"); + GFP_USER | GFP_DMA32, "wc dma", 0); ttm_page_pool_init_locked(&_manager->uc_pool_dma32, - GFP_USER | GFP_DMA32, "uc dma"); + GFP_USER | GFP_DMA32, "uc dma", 0); ttm_page_pool_init_locked(&_manager->wc_pool_huge, GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP), - "wc huge"); + "wc huge", order); ttm_page_pool_init_locked(&_manager->uc_pool_huge, GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP) - , "uc huge"); + , "uc huge", order); _manager->options.max_size = max_pages; _manager->options.small = SMALL_ALLOCATION; -- GitLab From 54ddc5f2d709e9eae5c55a665b37fe2581681c90 Mon Sep 17 00:00:00 2001 From: Roger He Date: Wed, 22 Nov 2017 15:09:33 +0800 Subject: [PATCH 0691/2547] drm/ttm: add set_pages_wb for handling page order more than zero MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index bf25ba25bfc6..359a641d3211 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -223,6 +223,17 @@ static struct kobj_type ttm_pool_kobj_type = { static struct ttm_pool_manager *_manager; #ifndef CONFIG_X86 +static int set_pages_wb(struct page *page, int numpages) +{ +#if IS_ENABLED(CONFIG_AGP) + int i; + + for (i = 0; i < numpages; i++) + unmap_page_from_agp(page++); +#endif + return 0; +} + static int set_pages_array_wb(struct page **pages, int addrinarray) { #if IS_ENABLED(CONFIG_AGP) -- GitLab From bae5c5b50b20b522002d6f9f6e9dbe1ae95152aa Mon Sep 17 00:00:00 2001 From: Roger He Date: Tue, 21 Nov 2017 14:24:48 +0800 Subject: [PATCH 0692/2547] drm/ttm: add page order support in ttm_pages_put MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 359a641d3211..337c228b44ad 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -296,13 +296,23 @@ static struct ttm_page_pool *ttm_get_pool(int flags, bool huge, } /* set memory back to wb and free the pages. */ -static void ttm_pages_put(struct page *pages[], unsigned npages) +static void ttm_pages_put(struct page *pages[], unsigned npages, + unsigned int order) { - unsigned i; - if (set_pages_array_wb(pages, npages)) - pr_err("Failed to set %d pages to wb!\n", npages); - for (i = 0; i < npages; ++i) - __free_page(pages[i]); + unsigned int i, pages_nr = (1 << order); + + if (order == 0) { + if (set_pages_array_wb(pages, npages)) + pr_err("Failed to set %d pages to wb!\n", npages); + } + + for (i = 0; i < npages; ++i) { + if (order > 0) { + if (set_pages_wb(pages[i], pages_nr)) + pr_err("Failed to set %d pages to wb!\n", pages_nr); + } + __free_pages(pages[i], order); + } } static void ttm_pool_update_free_locked(struct ttm_page_pool *pool, @@ -365,7 +375,7 @@ static int ttm_page_pool_free(struct ttm_page_pool *pool, unsigned nr_free, */ spin_unlock_irqrestore(&pool->lock, irq_flags); - ttm_pages_put(pages_to_free, freed_pages); + ttm_pages_put(pages_to_free, freed_pages, pool->order); if (likely(nr_free != FREE_ALL_PAGES)) nr_free -= freed_pages; @@ -400,7 +410,7 @@ static int ttm_page_pool_free(struct ttm_page_pool *pool, unsigned nr_free, spin_unlock_irqrestore(&pool->lock, irq_flags); if (freed_pages) - ttm_pages_put(pages_to_free, freed_pages); + ttm_pages_put(pages_to_free, freed_pages, pool->order); out: if (pages_to_free != static_buf) kfree(pages_to_free); -- GitLab From 2bf257d662509553ae226239e7dc1c3d00636ca6 Mon Sep 17 00:00:00 2001 From: Roger He Date: Tue, 21 Nov 2017 16:47:16 +0800 Subject: [PATCH 0693/2547] drm/ttm: roundup the shrink request to prevent skip huge pool MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit e.g. shrink reqeust is less than 512, the logic will skip huge pool Reviewed-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 337c228b44ad..116897a20514 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -442,17 +442,19 @@ ttm_pool_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) /* select start pool in round robin fashion */ for (i = 0; i < NUM_POOLS; ++i) { unsigned nr_free = shrink_pages; + unsigned page_nr; + if (shrink_pages == 0) break; pool = &_manager->pools[(i + pool_offset)%NUM_POOLS]; + page_nr = (1 << pool->order); /* OK to use static buffer since global mutex is held. */ - nr_free_pool = (nr_free >> pool->order); - if (nr_free_pool == 0) - continue; - + nr_free_pool = roundup(nr_free, page_nr) >> pool->order; shrink_pages = ttm_page_pool_free(pool, nr_free_pool, true); - freed += ((nr_free_pool - shrink_pages) << pool->order); + freed += (nr_free_pool - shrink_pages) << pool->order; + if (freed >= sc->nr_to_scan) + break; } mutex_unlock(&lock); return freed; -- GitLab From 5ff7ec02f2f306d619c661ff8fd5392d3653d407 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 4 Dec 2017 11:17:54 +0100 Subject: [PATCH 0694/2547] drm/ttm: swap consecutive allocated cached pages v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When we detect consecutive allocation of pages swap them to avoid accidentally freeing them as huge page. v2: use swap v3: check if it's really the first allocated page Signed-off-by: Christian König Reviewed-by: Roger He Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 116897a20514..b6f7ce286fb1 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -877,7 +877,7 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, #endif struct list_head plist; struct page *p = NULL; - unsigned count; + unsigned count, first; int r; /* No pool for cached pages */ @@ -918,6 +918,7 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, } #endif + first = i; while (npages) { p = alloc_page(gfp_flags); if (!p) { @@ -925,6 +926,10 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, return -ENOMEM; } + /* Swap the pages if we detect consecutive order */ + if (i > first && pages[i - 1] == p - 1) + swap(p, pages[i - 1]); + pages[i++] = p; --npages; } -- GitLab From 5c472203421ab4f928aa1ae9e1dbcfdd80324148 Mon Sep 17 00:00:00 2001 From: Nogah Frankel Date: Mon, 4 Dec 2017 13:31:10 +0200 Subject: [PATCH 0695/2547] net_sched: red: Avoid devision by zero Do not allow delta value to be zero since it is used as a divisor. Fixes: 8af2a218de38 ("sch_red: Adaptative RED AQM") Signed-off-by: Nogah Frankel Signed-off-by: David S. Miller --- include/net/red.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/net/red.h b/include/net/red.h index 9a9347710701..5918f78d36a0 100644 --- a/include/net/red.h +++ b/include/net/red.h @@ -179,7 +179,7 @@ static inline void red_set_parms(struct red_parms *p, p->qth_max = qth_max << Wlog; p->Wlog = Wlog; p->Plog = Plog; - if (delta < 0) + if (delta <= 0) delta = 1; p->qth_delta = delta; if (!max_P) { -- GitLab From 8afa10cbe281b10371fee5a87ab266e48d71a7f9 Mon Sep 17 00:00:00 2001 From: Nogah Frankel Date: Mon, 4 Dec 2017 13:31:11 +0200 Subject: [PATCH 0696/2547] net_sched: red: Avoid illegal values Check the qmin & qmax values doesn't overflow for the given Wlog value. Check that qmin <= qmax. Fixes: a783474591f2 ("[PKT_SCHED]: Generic RED layer") Signed-off-by: Nogah Frankel Signed-off-by: David S. Miller --- include/net/red.h | 11 +++++++++++ net/sched/sch_choke.c | 3 +++ net/sched/sch_gred.c | 3 +++ net/sched/sch_red.c | 2 ++ net/sched/sch_sfq.c | 3 +++ 5 files changed, 22 insertions(+) diff --git a/include/net/red.h b/include/net/red.h index 5918f78d36a0..9665582c4687 100644 --- a/include/net/red.h +++ b/include/net/red.h @@ -168,6 +168,17 @@ static inline void red_set_vars(struct red_vars *v) v->qcount = -1; } +static inline bool red_check_params(u32 qth_min, u32 qth_max, u8 Wlog) +{ + if (fls(qth_min) + Wlog > 32) + return false; + if (fls(qth_max) + Wlog > 32) + return false; + if (qth_max < qth_min) + return false; + return true; +} + static inline void red_set_parms(struct red_parms *p, u32 qth_min, u32 qth_max, u8 Wlog, u8 Plog, u8 Scell_log, u8 *stab, u32 max_P) diff --git a/net/sched/sch_choke.c b/net/sched/sch_choke.c index b30a2c70bd48..531250fceb9e 100644 --- a/net/sched/sch_choke.c +++ b/net/sched/sch_choke.c @@ -369,6 +369,9 @@ static int choke_change(struct Qdisc *sch, struct nlattr *opt) ctl = nla_data(tb[TCA_CHOKE_PARMS]); + if (!red_check_params(ctl->qth_min, ctl->qth_max, ctl->Wlog)) + return -EINVAL; + if (ctl->limit > CHOKE_MAX_QUEUE) return -EINVAL; diff --git a/net/sched/sch_gred.c b/net/sched/sch_gred.c index 17c7130454bd..bc30f9186ac6 100644 --- a/net/sched/sch_gred.c +++ b/net/sched/sch_gred.c @@ -356,6 +356,9 @@ static inline int gred_change_vq(struct Qdisc *sch, int dp, struct gred_sched *table = qdisc_priv(sch); struct gred_sched_data *q = table->tab[dp]; + if (!red_check_params(ctl->qth_min, ctl->qth_max, ctl->Wlog)) + return -EINVAL; + if (!q) { table->tab[dp] = q = *prealloc; *prealloc = NULL; diff --git a/net/sched/sch_red.c b/net/sched/sch_red.c index 7f8ea9e297c3..9d874e60e032 100644 --- a/net/sched/sch_red.c +++ b/net/sched/sch_red.c @@ -212,6 +212,8 @@ static int red_change(struct Qdisc *sch, struct nlattr *opt) max_P = tb[TCA_RED_MAX_P] ? nla_get_u32(tb[TCA_RED_MAX_P]) : 0; ctl = nla_data(tb[TCA_RED_PARMS]); + if (!red_check_params(ctl->qth_min, ctl->qth_max, ctl->Wlog)) + return -EINVAL; if (ctl->limit > 0) { child = fifo_create_dflt(sch, &bfifo_qdisc_ops, ctl->limit); diff --git a/net/sched/sch_sfq.c b/net/sched/sch_sfq.c index 09c1203c1711..930e5bd26d3d 100644 --- a/net/sched/sch_sfq.c +++ b/net/sched/sch_sfq.c @@ -639,6 +639,9 @@ static int sfq_change(struct Qdisc *sch, struct nlattr *opt) if (ctl->divisor && (!is_power_of_2(ctl->divisor) || ctl->divisor > 65536)) return -EINVAL; + if (ctl_v1 && !red_check_params(ctl_v1->qth_min, ctl_v1->qth_max, + ctl_v1->Wlog)) + return -EINVAL; if (ctl_v1 && ctl_v1->qth_min) { p = kmalloc(sizeof(*p), GFP_KERNEL); if (!p) -- GitLab From 22c1aed4093a605b120d6e566620364843a318ed Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 4 Dec 2017 14:33:26 +0100 Subject: [PATCH 0697/2547] net: sh_eth: use correct "struct device" when calling DMA mapping functions There are two types of "struct device": the one representing the physical device on its physical bus (platform, SPI, PCI, etc.), and the one representing the logical device in its device class (net, etc.). The DMA mapping API expects to receive as argument a "struct device" representing the physical device, as the "struct device" contains information about the bus that the DMA API needs. However, the sh_eth driver mistakenly uses the "struct device" representing the logical device (embedded in "struct net_device") rather than the "struct device" representing the physical device on its bus. This commit fixes that by adjusting all calls to the DMA mapping API. Signed-off-by: Thomas Petazzoni Acked-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: David S. Miller --- drivers/net/ethernet/renesas/sh_eth.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c index 7e060aa9fbed..91e918e654fe 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c @@ -1149,7 +1149,8 @@ static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) entry, le32_to_cpu(txdesc->status)); /* Free the original skb. */ if (mdp->tx_skbuff[entry]) { - dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr), + dma_unmap_single(&mdp->pdev->dev, + le32_to_cpu(txdesc->addr), le32_to_cpu(txdesc->len) >> 16, DMA_TO_DEVICE); dev_kfree_skb_irq(mdp->tx_skbuff[entry]); @@ -1179,7 +1180,7 @@ static void sh_eth_ring_free(struct net_device *ndev) if (mdp->rx_skbuff[i]) { struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; - dma_unmap_single(&ndev->dev, + dma_unmap_single(&mdp->pdev->dev, le32_to_cpu(rxdesc->addr), ALIGN(mdp->rx_buf_sz, 32), DMA_FROM_DEVICE); @@ -1245,9 +1246,9 @@ static void sh_eth_ring_format(struct net_device *ndev) /* The size of the buffer is a multiple of 32 bytes. */ buf_len = ALIGN(mdp->rx_buf_sz, 32); - dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len, + dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, DMA_FROM_DEVICE); - if (dma_mapping_error(&ndev->dev, dma_addr)) { + if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { kfree_skb(skb); break; } @@ -1527,7 +1528,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) mdp->rx_skbuff[entry] = NULL; if (mdp->cd->rpadir) skb_reserve(skb, NET_IP_ALIGN); - dma_unmap_single(&ndev->dev, dma_addr, + dma_unmap_single(&mdp->pdev->dev, dma_addr, ALIGN(mdp->rx_buf_sz, 32), DMA_FROM_DEVICE); skb_put(skb, pkt_len); @@ -1555,9 +1556,9 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) if (skb == NULL) break; /* Better luck next round. */ sh_eth_set_receive_align(skb); - dma_addr = dma_map_single(&ndev->dev, skb->data, + dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, DMA_FROM_DEVICE); - if (dma_mapping_error(&ndev->dev, dma_addr)) { + if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { kfree_skb(skb); break; } @@ -2441,9 +2442,9 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) /* soft swap. */ if (!mdp->cd->hw_swap) sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); - dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len, + dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); - if (dma_mapping_error(&ndev->dev, dma_addr)) { + if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { kfree_skb(skb); return NETDEV_TX_OK; } -- GitLab From 573500dbf0f2756947517c1d4f942767dbf16dcc Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 4 Dec 2017 14:33:27 +0100 Subject: [PATCH 0698/2547] net: sh_eth: don't use NULL as "struct device" for the DMA mapping API Using NULL as argument for the DMA mapping API is bogus, as the DMA mapping API may use information from the "struct device" to perform the DMA mapping operation. Therefore, pass the appropriate "struct device". Signed-off-by: Thomas Petazzoni Acked-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: David S. Miller --- drivers/net/ethernet/renesas/sh_eth.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c index 91e918e654fe..db72d13cebb9 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c @@ -1187,7 +1187,7 @@ static void sh_eth_ring_free(struct net_device *ndev) } } ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; - dma_free_coherent(NULL, ringsize, mdp->rx_ring, + dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring, mdp->rx_desc_dma); mdp->rx_ring = NULL; } @@ -1204,7 +1204,7 @@ static void sh_eth_ring_free(struct net_device *ndev) sh_eth_tx_free(ndev, false); ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; - dma_free_coherent(NULL, ringsize, mdp->tx_ring, + dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring, mdp->tx_desc_dma); mdp->tx_ring = NULL; } @@ -1324,8 +1324,8 @@ static int sh_eth_ring_init(struct net_device *ndev) /* Allocate all Rx descriptors. */ rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; - mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, - GFP_KERNEL); + mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize, + &mdp->rx_desc_dma, GFP_KERNEL); if (!mdp->rx_ring) goto ring_free; @@ -1333,8 +1333,8 @@ static int sh_eth_ring_init(struct net_device *ndev) /* Allocate all Tx descriptors. */ tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; - mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, - GFP_KERNEL); + mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize, + &mdp->tx_desc_dma, GFP_KERNEL); if (!mdp->tx_ring) goto ring_free; return 0; -- GitLab From c2f31b79d510ec1a27138bdcf2d0ece1080be85e Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Tue, 5 Dec 2017 09:10:17 -0800 Subject: [PATCH 0699/2547] cgroup: add warning about RT not being supported on cgroup2 We haven't yet figured out what to do with RT threads on cgroup2. Document the limitation. v2: Included the warning about system management software behavior as suggested by Michael. Signed-off-by: Tejun Heo Reported-by: "Michael Kerrisk (man-pages)" --- Documentation/cgroup-v2.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/cgroup-v2.txt b/Documentation/cgroup-v2.txt index 779211fbb69f..2cddab7efb20 100644 --- a/Documentation/cgroup-v2.txt +++ b/Documentation/cgroup-v2.txt @@ -898,6 +898,13 @@ controller implements weight and absolute bandwidth limit models for normal scheduling policy and absolute bandwidth allocation model for realtime scheduling policy. +WARNING: cgroup2 doesn't yet support control of realtime processes and +the cpu controller can only be enabled when all RT processes are in +the root cgroup. Be aware that system management software may already +have placed RT processes into nonroot cgroups during the system boot +process, and these processes may need to be moved to the root cgroup +before the cpu controller can be enabled. + CPU Interface Files ~~~~~~~~~~~~~~~~~~~ -- GitLab From 672ecbe1c977616aa720c9397589665b33e72610 Mon Sep 17 00:00:00 2001 From: Cong Wang Date: Mon, 4 Dec 2017 10:31:43 -0800 Subject: [PATCH 0700/2547] tipc: fix a null pointer deref on error path In tipc_topsrv_kern_subscr() when s->tipc_conn_new() fails we call tipc_close_conn() to clean up, but in this case calling conn_put() is just enough. This fixes the folllowing crash: kasan: GPF could be caused by NULL-ptr deref or user memory access general protection fault: 0000 [#1] SMP KASAN Dumping ftrace buffer: (ftrace buffer empty) Modules linked in: CPU: 0 PID: 3085 Comm: syzkaller064164 Not tainted 4.15.0-rc1+ #137 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 task: 00000000c24413a5 task.stack: 000000005e8160b5 RIP: 0010:__lock_acquire+0xd55/0x47f0 kernel/locking/lockdep.c:3378 RSP: 0018:ffff8801cb5474a8 EFLAGS: 00010002 RAX: dffffc0000000000 RBX: 0000000000000000 RCX: 0000000000000000 RDX: 0000000000000004 RSI: 0000000000000000 RDI: ffffffff85ecb400 RBP: ffff8801cb547830 R08: 0000000000000001 R09: 0000000000000000 R10: 0000000000000000 R11: ffffffff87489d60 R12: ffff8801cd2980c0 R13: 0000000000000000 R14: 0000000000000001 R15: 0000000000000020 FS: 00000000014ee880(0000) GS:ffff8801db400000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007ffee2426e40 CR3: 00000001cb85a000 CR4: 00000000001406f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: lock_acquire+0x1d5/0x580 kernel/locking/lockdep.c:4004 __raw_spin_lock_bh include/linux/spinlock_api_smp.h:135 [inline] _raw_spin_lock_bh+0x31/0x40 kernel/locking/spinlock.c:175 spin_lock_bh include/linux/spinlock.h:320 [inline] tipc_subscrb_subscrp_delete+0x8f/0x470 net/tipc/subscr.c:201 tipc_subscrb_delete net/tipc/subscr.c:238 [inline] tipc_subscrb_release_cb+0x17/0x30 net/tipc/subscr.c:316 tipc_close_conn+0x171/0x270 net/tipc/server.c:204 tipc_topsrv_kern_subscr+0x724/0x810 net/tipc/server.c:514 tipc_group_create+0x702/0x9c0 net/tipc/group.c:184 tipc_sk_join net/tipc/socket.c:2747 [inline] tipc_setsockopt+0x249/0xc10 net/tipc/socket.c:2861 SYSC_setsockopt net/socket.c:1851 [inline] SyS_setsockopt+0x189/0x360 net/socket.c:1830 entry_SYSCALL_64_fastpath+0x1f/0x96 Fixes: 14c04493cb77 ("tipc: add ability to order and receive topology events in driver") Reported-by: syzbot Cc: Jon Maloy Cc: Ying Xue Signed-off-by: Cong Wang Signed-off-by: David S. Miller --- net/tipc/server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/tipc/server.c b/net/tipc/server.c index acaef80fb88c..2710101ba4c1 100644 --- a/net/tipc/server.c +++ b/net/tipc/server.c @@ -511,7 +511,7 @@ bool tipc_topsrv_kern_subscr(struct net *net, u32 port, u32 type, s = con->server; scbr = s->tipc_conn_new(*conid); if (!scbr) { - tipc_close_conn(con); + conn_put(con); return false; } -- GitLab From a7d5f107b4978e08eeab599ee7449af34d034053 Mon Sep 17 00:00:00 2001 From: Jon Maloy Date: Mon, 4 Dec 2017 22:00:20 +0100 Subject: [PATCH 0701/2547] tipc: fix memory leak in tipc_accept_from_sock() When the function tipc_accept_from_sock() fails to create an instance of struct tipc_subscriber it omits to free the already created instance of struct tipc_conn instance before it returns. We fix that with this commit. Reported-by: David S. Miller Signed-off-by: Jon Maloy Signed-off-by: David S. Miller --- net/tipc/server.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/tipc/server.c b/net/tipc/server.c index 2710101ba4c1..d60c30342327 100644 --- a/net/tipc/server.c +++ b/net/tipc/server.c @@ -314,6 +314,7 @@ static int tipc_accept_from_sock(struct tipc_conn *con) newcon->usr_data = s->tipc_conn_new(newcon->conid); if (!newcon->usr_data) { sock_release(newsock); + conn_put(newcon); return -ENOMEM; } -- GitLab From c9d3fe9da094a9a7a3d3cd365b334b822e05f5e8 Mon Sep 17 00:00:00 2001 From: Stefan Hajnoczi Date: Tue, 5 Dec 2017 11:31:14 +0000 Subject: [PATCH 0702/2547] VSOCK: fix outdated sk_state value in hvs_release() Since commit 3b4477d2dcf2709d0be89e2a8dced3d0f4a017f2 ("VSOCK: use TCP state constants for sk_state") VSOCK has used TCP_* constants for sk_state. Commit b4562ca7925a3bedada87a3dd072dd5bad043288 ("hv_sock: add locking in the open/close/release code paths") reintroduced the SS_DISCONNECTING constant. This patch replaces the old SS_DISCONNECTING with the new TCP_CLOSING constant. CC: Dexuan Cui CC: Cathy Avery Signed-off-by: Stefan Hajnoczi Reviewed-by: Jorgen Hansen Signed-off-by: David S. Miller --- net/vmw_vsock/hyperv_transport.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/vmw_vsock/hyperv_transport.c b/net/vmw_vsock/hyperv_transport.c index 5583df708b8c..a827547aa102 100644 --- a/net/vmw_vsock/hyperv_transport.c +++ b/net/vmw_vsock/hyperv_transport.c @@ -487,7 +487,7 @@ static void hvs_release(struct vsock_sock *vsk) lock_sock(sk); - sk->sk_state = SS_DISCONNECTING; + sk->sk_state = TCP_CLOSING; vsock_remove_sock(vsk); release_sock(sk); -- GitLab From f775b13eedee2f7f3c6fdd4e90fb79090ce5d339 Mon Sep 17 00:00:00 2001 From: Rik van Riel Date: Tue, 14 Nov 2017 16:54:23 -0500 Subject: [PATCH 0703/2547] x86,kvm: move qemu/guest FPU switching out to vcpu_run MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, every time a VCPU is scheduled out, the host kernel will first save the guest FPU/xstate context, then load the qemu userspace FPU context, only to then immediately save the qemu userspace FPU context back to memory. When scheduling in a VCPU, the same extraneous FPU loads and saves are done. This could be avoided by moving from a model where the guest FPU is loaded and stored with preemption disabled, to a model where the qemu userspace FPU is swapped out for the guest FPU context for the duration of the KVM_RUN ioctl. This is done under the VCPU mutex, which is also taken when other tasks inspect the VCPU FPU context, so the code should already be safe for this change. That should come as no surprise, given that s390 already has this optimization. This can fix a bug where KVM calls get_user_pages while owning the FPU, and the file system ends up requesting the FPU again: [258270.527947] __warn+0xcb/0xf0 [258270.527948] warn_slowpath_null+0x1d/0x20 [258270.527951] kernel_fpu_disable+0x3f/0x50 [258270.527953] __kernel_fpu_begin+0x49/0x100 [258270.527955] kernel_fpu_begin+0xe/0x10 [258270.527958] crc32c_pcl_intel_update+0x84/0xb0 [258270.527961] crypto_shash_update+0x3f/0x110 [258270.527968] crc32c+0x63/0x8a [libcrc32c] [258270.527975] dm_bm_checksum+0x1b/0x20 [dm_persistent_data] [258270.527978] node_prepare_for_write+0x44/0x70 [dm_persistent_data] [258270.527985] dm_block_manager_write_callback+0x41/0x50 [dm_persistent_data] [258270.527988] submit_io+0x170/0x1b0 [dm_bufio] [258270.527992] __write_dirty_buffer+0x89/0x90 [dm_bufio] [258270.527994] __make_buffer_clean+0x4f/0x80 [dm_bufio] [258270.527996] __try_evict_buffer+0x42/0x60 [dm_bufio] [258270.527998] dm_bufio_shrink_scan+0xc0/0x130 [dm_bufio] [258270.528002] shrink_slab.part.40+0x1f5/0x420 [258270.528004] shrink_node+0x22c/0x320 [258270.528006] do_try_to_free_pages+0xf5/0x330 [258270.528008] try_to_free_pages+0xe9/0x190 [258270.528009] __alloc_pages_slowpath+0x40f/0xba0 [258270.528011] __alloc_pages_nodemask+0x209/0x260 [258270.528014] alloc_pages_vma+0x1f1/0x250 [258270.528017] do_huge_pmd_anonymous_page+0x123/0x660 [258270.528021] handle_mm_fault+0xfd3/0x1330 [258270.528025] __get_user_pages+0x113/0x640 [258270.528027] get_user_pages+0x4f/0x60 [258270.528063] __gfn_to_pfn_memslot+0x120/0x3f0 [kvm] [258270.528108] try_async_pf+0x66/0x230 [kvm] [258270.528135] tdp_page_fault+0x130/0x280 [kvm] [258270.528149] kvm_mmu_page_fault+0x60/0x120 [kvm] [258270.528158] handle_ept_violation+0x91/0x170 [kvm_intel] [258270.528162] vmx_handle_exit+0x1ca/0x1400 [kvm_intel] No performance changes were detected in quick ping-pong tests on my 4 socket system, which is expected since an FPU+xstate load is on the order of 0.1us, while ping-ponging between CPUs is on the order of 20us, and somewhat noisy. Cc: stable@vger.kernel.org Signed-off-by: Rik van Riel Suggested-by: Christian Borntraeger Signed-off-by: Paolo Bonzini [Fixed a bug where reset_vcpu called put_fpu without preceding load_fpu, which happened inside from KVM_CREATE_VCPU ioctl. - Radim] Signed-off-by: Radim Krčmář --- arch/x86/include/asm/kvm_host.h | 13 +++++++++++ arch/x86/kvm/x86.c | 39 ++++++++++++++------------------- include/linux/kvm_host.h | 2 +- 3 files changed, 31 insertions(+), 23 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 977de5fb968b..62527e053ee4 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -536,7 +536,20 @@ struct kvm_vcpu_arch { struct kvm_mmu_memory_cache mmu_page_cache; struct kvm_mmu_memory_cache mmu_page_header_cache; + /* + * QEMU userspace and the guest each have their own FPU state. + * In vcpu_run, we switch between the user and guest FPU contexts. + * While running a VCPU, the VCPU thread will have the guest FPU + * context. + * + * Note that while the PKRU state lives inside the fpu registers, + * it is switched out separately at VMENTER and VMEXIT time. The + * "guest_fpu" state here contains the guest FPU context, with the + * host PRKU bits. + */ + struct fpu user_fpu; struct fpu guest_fpu; + u64 xcr0; u64 guest_supported_xcr0; u32 guest_xstate_size; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index eee8e7faf1af..c8da1680a7d6 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -2937,7 +2937,6 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) srcu_read_unlock(&vcpu->kvm->srcu, idx); pagefault_enable(); kvm_x86_ops->vcpu_put(vcpu); - kvm_put_guest_fpu(vcpu); vcpu->arch.last_host_tsc = rdtsc(); } @@ -5254,13 +5253,10 @@ static void emulator_halt(struct x86_emulate_ctxt *ctxt) static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) { - preempt_disable(); - kvm_load_guest_fpu(emul_to_vcpu(ctxt)); } static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) { - preempt_enable(); } static int emulator_intercept(struct x86_emulate_ctxt *ctxt, @@ -6952,7 +6948,6 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) preempt_disable(); kvm_x86_ops->prepare_guest_switch(vcpu); - kvm_load_guest_fpu(vcpu); /* * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt @@ -7297,12 +7292,14 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) } } + kvm_load_guest_fpu(vcpu); + if (unlikely(vcpu->arch.complete_userspace_io)) { int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; vcpu->arch.complete_userspace_io = NULL; r = cui(vcpu); if (r <= 0) - goto out; + goto out_fpu; } else WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); @@ -7311,6 +7308,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) else r = vcpu_run(vcpu); +out_fpu: + kvm_put_guest_fpu(vcpu); out: post_kvm_run_save(vcpu); kvm_sigset_deactivate(vcpu); @@ -7704,32 +7703,25 @@ static void fx_init(struct kvm_vcpu *vcpu) vcpu->arch.cr0 |= X86_CR0_ET; } +/* Swap (qemu) user FPU context for the guest FPU context. */ void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) { - if (vcpu->guest_fpu_loaded) - return; - - /* - * Restore all possible states in the guest, - * and assume host would use all available bits. - * Guest xcr0 would be loaded later. - */ - vcpu->guest_fpu_loaded = 1; - __kernel_fpu_begin(); + preempt_disable(); + copy_fpregs_to_fpstate(&vcpu->arch.user_fpu); /* PKRU is separately restored in kvm_x86_ops->run. */ __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state, ~XFEATURE_MASK_PKRU); + preempt_enable(); trace_kvm_fpu(1); } +/* When vcpu_run ends, restore user space FPU context. */ void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) { - if (!vcpu->guest_fpu_loaded) - return; - - vcpu->guest_fpu_loaded = 0; + preempt_disable(); copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); - __kernel_fpu_end(); + copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state); + preempt_enable(); ++vcpu->stat.fpu_reload; trace_kvm_fpu(0); } @@ -7846,7 +7838,8 @@ void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) * To avoid have the INIT path from kvm_apic_has_events() that be * called with loaded FPU and does not let userspace fix the state. */ - kvm_put_guest_fpu(vcpu); + if (init_event) + kvm_put_guest_fpu(vcpu); mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, XFEATURE_MASK_BNDREGS); if (mpx_state_buffer) @@ -7855,6 +7848,8 @@ void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) XFEATURE_MASK_BNDCSR); if (mpx_state_buffer) memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); + if (init_event) + kvm_load_guest_fpu(vcpu); } if (!init_event) { diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 893d6d606cd0..6bdd4b9f6611 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -232,7 +232,7 @@ struct kvm_vcpu { struct mutex mutex; struct kvm_run *run; - int guest_fpu_loaded, guest_xcr0_loaded; + int guest_xcr0_loaded; struct swait_queue_head wq; struct pid __rcu *pid; int sigset_active; -- GitLab From 6ab0b9feb82a7ac09956e6761fec73cd47789df5 Mon Sep 17 00:00:00 2001 From: Rik van Riel Date: Tue, 14 Nov 2017 16:54:24 -0500 Subject: [PATCH 0704/2547] x86,kvm: remove KVM emulator get_fpu / put_fpu Now that get_fpu and put_fpu do nothing, because the scheduler will automatically load and restore the guest FPU context for us while we are in this code (deep inside the vcpu_run main loop), we can get rid of the get_fpu and put_fpu hooks. Signed-off-by: Rik van Riel Suggested-by: David Hildenbrand Signed-off-by: Paolo Bonzini --- arch/x86/include/asm/kvm_emulate.h | 2 -- arch/x86/kvm/emulate.c | 24 ------------------------ arch/x86/kvm/x86.c | 10 ---------- 3 files changed, 36 deletions(-) diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h index 034caa1a084e..b24b1c8b3979 100644 --- a/arch/x86/include/asm/kvm_emulate.h +++ b/arch/x86/include/asm/kvm_emulate.h @@ -214,8 +214,6 @@ struct x86_emulate_ops { void (*halt)(struct x86_emulate_ctxt *ctxt); void (*wbinvd)(struct x86_emulate_ctxt *ctxt); int (*fix_hypercall)(struct x86_emulate_ctxt *ctxt); - void (*get_fpu)(struct x86_emulate_ctxt *ctxt); /* disables preempt */ - void (*put_fpu)(struct x86_emulate_ctxt *ctxt); /* reenables preempt */ int (*intercept)(struct x86_emulate_ctxt *ctxt, struct x86_instruction_info *info, enum x86_intercept_stage stage); diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index e7d04d0c8008..abe74f779f9d 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -1046,7 +1046,6 @@ static void fetch_register_operand(struct operand *op) static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) { - ctxt->ops->get_fpu(ctxt); switch (reg) { case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break; case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break; @@ -1068,13 +1067,11 @@ static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) #endif default: BUG(); } - ctxt->ops->put_fpu(ctxt); } static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) { - ctxt->ops->get_fpu(ctxt); switch (reg) { case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break; case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break; @@ -1096,12 +1093,10 @@ static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, #endif default: BUG(); } - ctxt->ops->put_fpu(ctxt); } static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) { - ctxt->ops->get_fpu(ctxt); switch (reg) { case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; @@ -1113,12 +1108,10 @@ static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; default: BUG(); } - ctxt->ops->put_fpu(ctxt); } static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) { - ctxt->ops->get_fpu(ctxt); switch (reg) { case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; @@ -1130,7 +1123,6 @@ static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; default: BUG(); } - ctxt->ops->put_fpu(ctxt); } static int em_fninit(struct x86_emulate_ctxt *ctxt) @@ -1138,9 +1130,7 @@ static int em_fninit(struct x86_emulate_ctxt *ctxt) if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) return emulate_nm(ctxt); - ctxt->ops->get_fpu(ctxt); asm volatile("fninit"); - ctxt->ops->put_fpu(ctxt); return X86EMUL_CONTINUE; } @@ -1151,9 +1141,7 @@ static int em_fnstcw(struct x86_emulate_ctxt *ctxt) if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) return emulate_nm(ctxt); - ctxt->ops->get_fpu(ctxt); asm volatile("fnstcw %0": "+m"(fcw)); - ctxt->ops->put_fpu(ctxt); ctxt->dst.val = fcw; @@ -1167,9 +1155,7 @@ static int em_fnstsw(struct x86_emulate_ctxt *ctxt) if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) return emulate_nm(ctxt); - ctxt->ops->get_fpu(ctxt); asm volatile("fnstsw %0": "+m"(fsw)); - ctxt->ops->put_fpu(ctxt); ctxt->dst.val = fsw; @@ -4001,12 +3987,8 @@ static int em_fxsave(struct x86_emulate_ctxt *ctxt) if (rc != X86EMUL_CONTINUE) return rc; - ctxt->ops->get_fpu(ctxt); - rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state)); - ctxt->ops->put_fpu(ctxt); - if (rc != X86EMUL_CONTINUE) return rc; @@ -4049,8 +4031,6 @@ static int em_fxrstor(struct x86_emulate_ctxt *ctxt) if (rc != X86EMUL_CONTINUE) return rc; - ctxt->ops->get_fpu(ctxt); - if (size < __fxstate_size(16)) { rc = fxregs_fixup(&fx_state, size); if (rc != X86EMUL_CONTINUE) @@ -4066,8 +4046,6 @@ static int em_fxrstor(struct x86_emulate_ctxt *ctxt) rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state)); out: - ctxt->ops->put_fpu(ctxt); - return rc; } @@ -5317,9 +5295,7 @@ static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) { int rc; - ctxt->ops->get_fpu(ctxt); rc = asm_safe("fwait"); - ctxt->ops->put_fpu(ctxt); if (unlikely(rc != X86EMUL_CONTINUE)) return emulate_exception(ctxt, MF_VECTOR, 0, false); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c8da1680a7d6..6ca747abfa2f 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -5251,14 +5251,6 @@ static void emulator_halt(struct x86_emulate_ctxt *ctxt) emul_to_vcpu(ctxt)->arch.halt_request = 1; } -static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) -{ -} - -static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) -{ -} - static int emulator_intercept(struct x86_emulate_ctxt *ctxt, struct x86_instruction_info *info, enum x86_intercept_stage stage) @@ -5336,8 +5328,6 @@ static const struct x86_emulate_ops emulate_ops = { .halt = emulator_halt, .wbinvd = emulator_wbinvd, .fix_hypercall = emulator_fix_hypercall, - .get_fpu = emulator_get_fpu, - .put_fpu = emulator_put_fpu, .intercept = emulator_intercept, .get_cpuid = emulator_get_cpuid, .set_nmi_mask = emulator_set_nmi_mask, -- GitLab From d59d51f088014f25c2562de59b9abff4f42a7468 Mon Sep 17 00:00:00 2001 From: Andrew Honig Date: Fri, 1 Dec 2017 10:21:09 -0800 Subject: [PATCH 0705/2547] KVM: VMX: remove I/O port 0x80 bypass on Intel hosts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes CVE-2017-1000407. KVM allows guests to directly access I/O port 0x80 on Intel hosts. If the guest floods this port with writes it generates exceptions and instability in the host kernel, leading to a crash. With this change guest writes to port 0x80 on Intel will behave the same as they currently behave on AMD systems. Prevent the flooding by removing the code that sets port 0x80 as a passthrough port. This is essentially the same as upstream patch 99f85a28a78e96d28907fe036e1671a218fee597, except that patch was for AMD chipsets and this patch is for Intel. Signed-off-by: Andrew Honig Signed-off-by: Jim Mattson Fixes: fdef3ad1b386 ("KVM: VMX: Enable io bitmaps to avoid IO port 0x80 VMEXITs") Cc: Signed-off-by: Radim Krčmář --- arch/x86/kvm/vmx.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 4704aaf6d19e..2fd9a8cec29a 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -6755,12 +6755,7 @@ static __init int hardware_setup(void) memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); - /* - * Allow direct access to the PC debug port (it is often used for I/O - * delays, but the vmexits simply slow things down). - */ memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); - clear_bit(0x80, vmx_io_bitmap_a); memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); -- GitLab From 2895db67b01cb875457c9c3f30a14723b6b5dfd5 Mon Sep 17 00:00:00 2001 From: Jim Mattson Date: Fri, 1 Dec 2017 09:57:56 -0800 Subject: [PATCH 0706/2547] KVM: VMX: fix page leak in hardware_setup() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit vmx_io_bitmap_b should not be allocated twice. Fixes: 23611332938d ("KVM: VMX: refactor setup of global page-sized bitmaps") Signed-off-by: Jim Mattson Reviewed-by: Krish Sadhukhan Reviewed-by: David Hildenbrand Signed-off-by: Radim Krčmář --- arch/x86/kvm/vmx.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 2fd9a8cec29a..8eba631c4dbd 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -6751,7 +6751,6 @@ static __init int hardware_setup(void) goto out; } - vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); -- GitLab From 5888fc9eac3c2ff96e76aeeb865fdb46ab2d711e Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 4 Dec 2017 13:25:13 +0000 Subject: [PATCH 0707/2547] drm/i915: Flush pending GTT writes before unbinding From the shrinker paths, we want to relinquish the GPU and GGTT access to the object, releasing the backing storage back to the system for swapout. As a part of that process we would unpin the pages, marking them for access by the CPU (for the swapout/swapin). However, if that process was interrupted after unbind the vma, we missed a flush of the inflight GGTT writes before we made that GTT space available again for reuse, with the prospect that we would redirect them to another page. The bug dates back to the introduction of multiple GGTT vma, but the code itself dates to commit 02bef8f98d26 ("drm/i915: Unbind closed vma for i915_gem_object_unbind()"). Fixes: 02bef8f98d26 ("drm/i915: Unbind closed vma for i915_gem_object_unbind()") Fixes: c5ad54cf7dd8 ("drm/i915: Use partial view in mmap fault handler") Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: stable@vger.kernel.org Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171204132513.7303-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e083f242b8dc..80b78fb5daac 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -330,17 +330,10 @@ int i915_gem_object_unbind(struct drm_i915_gem_object *obj) * must wait for all rendering to complete to the object (as unbinding * must anyway), and retire the requests. */ - ret = i915_gem_object_wait(obj, - I915_WAIT_INTERRUPTIBLE | - I915_WAIT_LOCKED | - I915_WAIT_ALL, - MAX_SCHEDULE_TIMEOUT, - NULL); + ret = i915_gem_object_set_to_cpu_domain(obj, false); if (ret) return ret; - i915_gem_retire_requests(to_i915(obj->base.dev)); - while ((vma = list_first_entry_or_null(&obj->vma_list, struct i915_vma, obj_link))) { -- GitLab From 107783d00a067cd3e2ebf4564b1b8c03915186e9 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 5 Dec 2017 17:27:57 +0000 Subject: [PATCH 0708/2547] drm/i915: Taint (TAINT_WARN) the kernel if the GPU reset fails MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit History tells us that if we cannot reset the GPU now, we never will. This then impacts everything that is run subsequently. On failing the reset, we mark the driver as wedged, trying to prevent further execution on the GPU, forcing userspace to fallback to using the CPU to update its framebuffers and let the user know what happened. We also want to go one step further and add a taint to the kernel so that any subsequent faults can be traced back to this failure. This is useful for CI, where if the GPU/driver fails we want to reboot and restart testing rather than continue on into oblivion. For everyone else, the warning taint is a testament to the system unreliability. TAINT_WARN is used anytime a WARN() is emitted, which is suitable for our purposes here as well; the driver/system may behave unexpectedly after the failure. v2: Also taint if the recovery fails (again history shows us that is typically fatal). v3: Use TAINT_WARN References: https://bugs.freedesktop.org/show_bug.cgi?id=103514 Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Daniel Vetter Cc: Michał Winiarski Reviewed-by: Joonas Lahtinen Acked-by: Tomi Sarvela Link: https://patchwork.freedesktop.org/patch/msgid/20171205172757.32609-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_drv.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 962d7c7c799c..b2e210b77457 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1897,9 +1897,9 @@ void i915_reset(struct drm_i915_private *i915, unsigned int flags) disable_irq(i915->drm.irq); ret = i915_gem_reset_prepare(i915); if (ret) { - DRM_ERROR("GPU recovery failed\n"); + dev_err(i915->drm.dev, "GPU recovery failed\n"); intel_gpu_reset(i915, ALL_ENGINES); - goto error; + goto taint; } if (!intel_has_gpu_reset(i915)) { @@ -1916,7 +1916,7 @@ void i915_reset(struct drm_i915_private *i915, unsigned int flags) } if (ret) { dev_err(i915->drm.dev, "Failed to reset chip\n"); - goto error; + goto taint; } i915_gem_reset(i915); @@ -1959,6 +1959,20 @@ void i915_reset(struct drm_i915_private *i915, unsigned int flags) wake_up_bit(&error->flags, I915_RESET_HANDOFF); return; +taint: + /* + * History tells us that if we cannot reset the GPU now, we + * never will. This then impacts everything that is run + * subsequently. On failing the reset, we mark the driver + * as wedged, preventing further execution on the GPU. + * We also want to go one step further and add a taint to the + * kernel so that any subsequent faults can be traced back to + * this failure. This is important for CI, where if the + * GPU/driver fails we would like to reboot and restart testing + * rather than continue on into oblivion. For everyone else, + * the system should still plod along, but they have been warned! + */ + add_taint(TAINT_WARN, LOCKDEP_STILL_OK); error: i915_gem_set_wedged(i915); i915_gem_retire_requests(i915); -- GitLab From e0403cb9442c6d452459f4be70f59b20482268e3 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Tue, 5 Dec 2017 11:01:17 -0800 Subject: [PATCH 0709/2547] drm/i915: follow single notation for workaround number MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v2: Allow to have or omit space before platform Cc: Ville Syrjälä Signed-off-by: Lucas De Marchi Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20171205190118.7088-1-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 9d5e72728475..691600ce48c4 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1380,7 +1380,7 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state) } } - /* Display Wa #1139 */ + /* Display WA #1139 */ if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && crtc_state->base.adjusted_mode.htotal > 5460) return false; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 67f326230a7e..07ee5ad5a13f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -58,7 +58,7 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) if (HAS_LLC(dev_priv)) { /* * WaCompressedResourceDisplayNewHashMode:skl,kbl - * Display WA#0390: skl,kbl + * Display WA #0390: skl,kbl * * Must match Sampler, Pixel Back End, and Media. See * WaCompressedResourceSamplerPbeMediaNewHashMode. @@ -8417,7 +8417,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) if (!HAS_PCH_CNP(dev_priv)) return; - /* Wa #1181 */ + /* Display WA #1181 */ I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) | CNP_PWM_CGE_GATING_DISABLE); } -- GitLab From 2abf3c0da99648861e900a2b264b633b9cbca6fa Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Tue, 5 Dec 2017 11:01:18 -0800 Subject: [PATCH 0710/2547] drm/i915: add platform tag to WA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v2: add more missing platform tags v3: change tag to cnp rather than using gen9,gen10 Cc: Ville Syrjälä Signed-off-by: Lucas De Marchi Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20171205190118.7088-2-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 691600ce48c4..c42a6c672b73 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1380,7 +1380,7 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state) } } - /* Display WA #1139 */ + /* Display WA #1139: glk */ if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && crtc_state->base.adjusted_mode.htotal > 5460) return false; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 07ee5ad5a13f..5836181d6f8a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8417,7 +8417,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) if (!HAS_PCH_CNP(dev_priv)) return; - /* Display WA #1181 */ + /* Display WA #1181: cnp */ I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) | CNP_PWM_CGE_GATING_DISABLE); } -- GitLab From 1ecbd7170d6579a1ee389a37bf1f0437ea01a388 Mon Sep 17 00:00:00 2001 From: George Cherian Date: Mon, 4 Dec 2017 14:06:54 +0000 Subject: [PATCH 0711/2547] ACPI / CPPC: Fix KASAN global out of bounds warning Default value of pcc_subspace_idx is -1. Make sure to check pcc_subspace_idx before using the same as array index. This will avoid following KASAN warnings too. [ 15.113449] ================================================================== [ 15.116983] BUG: KASAN: global-out-of-bounds in cppc_get_perf_caps+0xf3/0x3b0 [ 15.116983] Read of size 8 at addr ffffffffb9a5c0d8 by task swapper/0/1 [ 15.116983] CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.15.0-rc2+ #2 [ 15.116983] Hardware name: Dell Inc. OptiPlex 7040/0Y7WYT, BIOS 1.2.8 01/26/2016 [ 15.116983] Call Trace: [ 15.116983] dump_stack+0x7c/0xbb [ 15.116983] print_address_description+0x1df/0x290 [ 15.116983] kasan_report+0x28a/0x370 [ 15.116983] ? cppc_get_perf_caps+0xf3/0x3b0 [ 15.116983] cppc_get_perf_caps+0xf3/0x3b0 [ 15.116983] ? cpc_read+0x210/0x210 [ 15.116983] ? __rdmsr_on_cpu+0x90/0x90 [ 15.116983] ? rdmsrl_on_cpu+0xa9/0xe0 [ 15.116983] ? rdmsr_on_cpu+0x100/0x100 [ 15.116983] ? wrmsrl_on_cpu+0x9c/0xd0 [ 15.116983] ? wrmsrl_on_cpu+0x9c/0xd0 [ 15.116983] ? wrmsr_on_cpu+0xe0/0xe0 [ 15.116983] __intel_pstate_cpu_init.part.16+0x3a2/0x530 [ 15.116983] ? intel_pstate_init_cpu+0x197/0x390 [ 15.116983] ? show_no_turbo+0xe0/0xe0 [ 15.116983] ? __lockdep_init_map+0xa0/0x290 [ 15.116983] intel_pstate_cpu_init+0x30/0x60 [ 15.116983] cpufreq_online+0x155/0xac0 [ 15.116983] cpufreq_add_dev+0x9b/0xb0 [ 15.116983] subsys_interface_register+0x1ae/0x290 [ 15.116983] ? bus_unregister_notifier+0x40/0x40 [ 15.116983] ? mark_held_locks+0x83/0xb0 [ 15.116983] ? _raw_write_unlock_irqrestore+0x32/0x60 [ 15.116983] ? intel_pstate_setup+0xc/0x104 [ 15.116983] ? intel_pstate_setup+0xc/0x104 [ 15.116983] ? cpufreq_register_driver+0x1ce/0x2b0 [ 15.116983] cpufreq_register_driver+0x1ce/0x2b0 [ 15.116983] ? intel_pstate_setup+0x104/0x104 [ 15.116983] intel_pstate_register_driver+0x3a/0xa0 [ 15.116983] intel_pstate_init+0x3c4/0x434 [ 15.116983] ? intel_pstate_setup+0x104/0x104 [ 15.116983] ? intel_pstate_setup+0x104/0x104 [ 15.116983] do_one_initcall+0x9c/0x206 [ 15.116983] ? parameq+0xa0/0xa0 [ 15.116983] ? initcall_blacklisted+0x150/0x150 [ 15.116983] ? lock_downgrade+0x2c0/0x2c0 [ 15.116983] kernel_init_freeable+0x327/0x3f0 [ 15.116983] ? start_kernel+0x612/0x612 [ 15.116983] ? _raw_spin_unlock_irq+0x29/0x40 [ 15.116983] ? finish_task_switch+0xdd/0x320 [ 15.116983] ? finish_task_switch+0x8e/0x320 [ 15.116983] ? rest_init+0xd0/0xd0 [ 15.116983] kernel_init+0xf/0x11a [ 15.116983] ? rest_init+0xd0/0xd0 [ 15.116983] ret_from_fork+0x24/0x30 [ 15.116983] The buggy address belongs to the variable: [ 15.116983] __key.36299+0x38/0x40 [ 15.116983] Memory state around the buggy address: [ 15.116983] ffffffffb9a5bf80: fa fa fa fa 00 fa fa fa fa fa fa fa 00 fa fa fa [ 15.116983] ffffffffb9a5c000: fa fa fa fa 00 fa fa fa fa fa fa fa 00 fa fa fa [ 15.116983] >ffffffffb9a5c080: fa fa fa fa 00 fa fa fa fa fa fa fa 00 00 00 00 [ 15.116983] ^ [ 15.116983] ffffffffb9a5c100: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 15.116983] ffffffffb9a5c180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 15.116983] ================================================================== Fixes: 85b1407bf6d2 (ACPI / CPPC: Make CPPC ACPI driver aware of PCC subspace IDs) Reported-by: Changbin Du Signed-off-by: George Cherian Signed-off-by: Rafael J. Wysocki --- drivers/acpi/cppc_acpi.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 21c28433c590..30e84cc600ae 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -949,7 +949,7 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) } *val = 0; - if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) + if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) vaddr = reg_res->sys_mem_vaddr; @@ -988,7 +988,7 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); struct cpc_reg *reg = ®_res->cpc_entry.reg; - if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) + if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) vaddr = reg_res->sys_mem_vaddr; @@ -1035,14 +1035,15 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) *lowest_non_linear_reg, *nominal_reg; u64 high, low, nom, min_nonlinear; int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); - struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; + struct cppc_pcc_data *pcc_ss_data; int ret = 0, regs_in_pcc = 0; - if (!cpc_desc) { + if (!cpc_desc || pcc_ss_id < 0) { pr_debug("No CPC descriptor for CPU:%d\n", cpunum); return -ENODEV; } + pcc_ss_data = pcc_data[pcc_ss_id]; highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF]; lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF]; lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF]; @@ -1095,15 +1096,16 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) struct cpc_register_resource *delivered_reg, *reference_reg, *ref_perf_reg, *ctr_wrap_reg; int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); - struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; + struct cppc_pcc_data *pcc_ss_data; u64 delivered, reference, ref_perf, ctr_wrap_time; int ret = 0, regs_in_pcc = 0; - if (!cpc_desc) { + if (!cpc_desc || pcc_ss_id < 0) { pr_debug("No CPC descriptor for CPU:%d\n", cpunum); return -ENODEV; } + pcc_ss_data = pcc_data[pcc_ss_id]; delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR]; reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR]; ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF]; @@ -1172,11 +1174,12 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; int ret = 0; - if (!cpc_desc) { + if (!cpc_desc || pcc_ss_id < 0) { pr_debug("No CPC descriptor for CPU:%d\n", cpu); return -ENODEV; } + pcc_ss_data = pcc_data[pcc_ss_id]; desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; /* @@ -1301,7 +1304,7 @@ unsigned int cppc_get_transition_latency(int cpu_num) struct cpc_desc *cpc_desc; struct cpc_register_resource *desired_reg; int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num); - struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; + struct cppc_pcc_data *pcc_ss_data; cpc_desc = per_cpu(cpc_desc_ptr, cpu_num); if (!cpc_desc) @@ -1311,6 +1314,10 @@ unsigned int cppc_get_transition_latency(int cpu_num) if (!CPC_IN_PCC(desired_reg)) return CPUFREQ_ETERNAL; + if (pcc_ss_id < 0) + return CPUFREQ_ETERNAL; + + pcc_ss_data = pcc_data[pcc_ss_id]; if (pcc_ss_data->pcc_mpar) latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar); -- GitLab From 362bca57f5d78220f8b5907b875961af9436e229 Mon Sep 17 00:00:00 2001 From: Robb Glasser Date: Tue, 5 Dec 2017 09:16:55 -0800 Subject: [PATCH 0712/2547] ALSA: pcm: prevent UAF in snd_pcm_info When the device descriptor is closed, the `substream->runtime` pointer is freed. But another thread may be in the ioctl handler, case SNDRV_CTL_IOCTL_PCM_INFO. This case calls snd_pcm_info_user() which calls snd_pcm_info() which accesses the now freed `substream->runtime`. Note: this fixes CVE-2017-0861 Signed-off-by: Robb Glasser Signed-off-by: Nick Desaulniers Cc: Signed-off-by: Takashi Iwai --- sound/core/pcm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/core/pcm.c b/sound/core/pcm.c index 9070f277f8db..09ee8c6b9f75 100644 --- a/sound/core/pcm.c +++ b/sound/core/pcm.c @@ -153,7 +153,9 @@ static int snd_pcm_control_ioctl(struct snd_card *card, err = -ENXIO; goto _error; } + mutex_lock(&pcm->open_mutex); err = snd_pcm_info_user(substream, info); + mutex_unlock(&pcm->open_mutex); _error: mutex_unlock(®ister_mutex); return err; -- GitLab From c20a548792f15f8d8e38cd74356301c6db0d241f Mon Sep 17 00:00:00 2001 From: Subash Abhinov Kasiviswanathan Date: Tue, 5 Dec 2017 13:41:17 -0700 Subject: [PATCH 0713/2547] net: qualcomm: rmnet: Fix leak on transmit failure If a skb in transmit path does not have sufficient headroom to add the map header, the skb is not sent out and is never freed. Fixes: ceed73a2cf4a ("drivers: net: ethernet: qualcomm: rmnet: Initial implementation") Signed-off-by: Subash Abhinov Kasiviswanathan Signed-off-by: David S. Miller --- drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c index 29842ccc91a9..08e4afc0ab39 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c @@ -126,12 +126,12 @@ static int rmnet_map_egress_handler(struct sk_buff *skb, if (skb_headroom(skb) < required_headroom) { if (pskb_expand_head(skb, required_headroom, 0, GFP_KERNEL)) - return RMNET_MAP_CONSUMED; + goto fail; } map_header = rmnet_map_add_map_header(skb, additional_header_len, 0); if (!map_header) - return RMNET_MAP_CONSUMED; + goto fail; if (port->egress_data_format & RMNET_EGRESS_FORMAT_MUXING) { if (mux_id == 0xff) @@ -143,6 +143,10 @@ static int rmnet_map_egress_handler(struct sk_buff *skb, skb->protocol = htons(ETH_P_MAP); return RMNET_MAP_SUCCESS; + +fail: + kfree_skb(skb); + return RMNET_MAP_CONSUMED; } static void -- GitLab From 6296928fa3b9f656d7760fbf346c0cf834788a78 Mon Sep 17 00:00:00 2001 From: Subash Abhinov Kasiviswanathan Date: Tue, 5 Dec 2017 13:41:18 -0700 Subject: [PATCH 0714/2547] net: qualcomm: rmnet: Fix leak in device creation failure If the rmnet device creation fails in the newlink either while registering with the physical device or after subsequent operations, the rmnet endpoint information is never freed. Fixes: ceed73a2cf4a ("drivers: net: ethernet: qualcomm: rmnet: Initial implementation") Signed-off-by: Subash Abhinov Kasiviswanathan Signed-off-by: David S. Miller --- drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c index 71bee1af71ef..df21e900f874 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c @@ -195,6 +195,7 @@ static int rmnet_newlink(struct net *src_net, struct net_device *dev, err1: rmnet_unregister_real_device(real_dev, port); err0: + kfree(ep); return err; } -- GitLab From d7efc6c11b277d9d80b99b1334a78bfe7d7edf10 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 5 Dec 2017 12:45:56 -0800 Subject: [PATCH 0715/2547] net: remove hlist_nulls_add_tail_rcu() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Alexander Potapenko reported use of uninitialized memory [1] This happens when inserting a request socket into TCP ehash, in __sk_nulls_add_node_rcu(), since sk_reuseport is not initialized. Bug was added by commit d894ba18d4e4 ("soreuseport: fix ordering for mixed v4/v6 sockets") Note that d296ba60d8e2 ("soreuseport: Resolve merge conflict for v4/v6 ordering fix") missed the opportunity to get rid of hlist_nulls_add_tail_rcu() : Both UDP sockets and TCP/DCCP listeners no longer use __sk_nulls_add_node_rcu() for their hash insertion. Since all other sockets have unique 4-tuple, the reuseport status has no special meaning, so we can always use hlist_nulls_add_head_rcu() for them and save few cycles/instructions. [1] ================================================================== BUG: KMSAN: use of uninitialized memory in inet_ehash_insert+0xd40/0x1050 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.13.0+ #3288 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Bochs 01/01/2011 Call Trace:    __dump_stack lib/dump_stack.c:16  dump_stack+0x185/0x1d0 lib/dump_stack.c:52  kmsan_report+0x13f/0x1c0 mm/kmsan/kmsan.c:1016  __msan_warning_32+0x69/0xb0 mm/kmsan/kmsan_instr.c:766  __sk_nulls_add_node_rcu ./include/net/sock.h:684  inet_ehash_insert+0xd40/0x1050 net/ipv4/inet_hashtables.c:413  reqsk_queue_hash_req net/ipv4/inet_connection_sock.c:754  inet_csk_reqsk_queue_hash_add+0x1cc/0x300 net/ipv4/inet_connection_sock.c:765  tcp_conn_request+0x31e7/0x36f0 net/ipv4/tcp_input.c:6414  tcp_v4_conn_request+0x16d/0x220 net/ipv4/tcp_ipv4.c:1314  tcp_rcv_state_process+0x42a/0x7210 net/ipv4/tcp_input.c:5917  tcp_v4_do_rcv+0xa6a/0xcd0 net/ipv4/tcp_ipv4.c:1483  tcp_v4_rcv+0x3de0/0x4ab0 net/ipv4/tcp_ipv4.c:1763  ip_local_deliver_finish+0x6bb/0xcb0 net/ipv4/ip_input.c:216  NF_HOOK ./include/linux/netfilter.h:248  ip_local_deliver+0x3fa/0x480 net/ipv4/ip_input.c:257  dst_input ./include/net/dst.h:477  ip_rcv_finish+0x6fb/0x1540 net/ipv4/ip_input.c:397  NF_HOOK ./include/linux/netfilter.h:248  ip_rcv+0x10f6/0x15c0 net/ipv4/ip_input.c:488  __netif_receive_skb_core+0x36f6/0x3f60 net/core/dev.c:4298  __netif_receive_skb net/core/dev.c:4336  netif_receive_skb_internal+0x63c/0x19c0 net/core/dev.c:4497  napi_skb_finish net/core/dev.c:4858  napi_gro_receive+0x629/0xa50 net/core/dev.c:4889  e1000_receive_skb drivers/net/ethernet/intel/e1000/e1000_main.c:4018  e1000_clean_rx_irq+0x1492/0x1d30 drivers/net/ethernet/intel/e1000/e1000_main.c:4474  e1000_clean+0x43aa/0x5970 drivers/net/ethernet/intel/e1000/e1000_main.c:3819  napi_poll net/core/dev.c:5500  net_rx_action+0x73c/0x1820 net/core/dev.c:5566  __do_softirq+0x4b4/0x8dd kernel/softirq.c:284  invoke_softirq kernel/softirq.c:364  irq_exit+0x203/0x240 kernel/softirq.c:405  exiting_irq+0xe/0x10 ./arch/x86/include/asm/apic.h:638  do_IRQ+0x15e/0x1a0 arch/x86/kernel/irq.c:263  common_interrupt+0x86/0x86 Fixes: d894ba18d4e4 ("soreuseport: fix ordering for mixed v4/v6 sockets") Fixes: d296ba60d8e2 ("soreuseport: Resolve merge conflict for v4/v6 ordering fix") Signed-off-by: Eric Dumazet Reported-by: Alexander Potapenko Acked-by: Craig Gallek Signed-off-by: David S. Miller --- include/linux/rculist_nulls.h | 38 ----------------------------------- include/net/sock.h | 6 +----- 2 files changed, 1 insertion(+), 43 deletions(-) diff --git a/include/linux/rculist_nulls.h b/include/linux/rculist_nulls.h index a328e8181e49..e4b257ff881b 100644 --- a/include/linux/rculist_nulls.h +++ b/include/linux/rculist_nulls.h @@ -100,44 +100,6 @@ static inline void hlist_nulls_add_head_rcu(struct hlist_nulls_node *n, first->pprev = &n->next; } -/** - * hlist_nulls_add_tail_rcu - * @n: the element to add to the hash list. - * @h: the list to add to. - * - * Description: - * Adds the specified element to the end of the specified hlist_nulls, - * while permitting racing traversals. NOTE: tail insertion requires - * list traversal. - * - * The caller must take whatever precautions are necessary - * (such as holding appropriate locks) to avoid racing - * with another list-mutation primitive, such as hlist_nulls_add_head_rcu() - * or hlist_nulls_del_rcu(), running on this same list. - * However, it is perfectly legal to run concurrently with - * the _rcu list-traversal primitives, such as - * hlist_nulls_for_each_entry_rcu(), used to prevent memory-consistency - * problems on Alpha CPUs. Regardless of the type of CPU, the - * list-traversal primitive must be guarded by rcu_read_lock(). - */ -static inline void hlist_nulls_add_tail_rcu(struct hlist_nulls_node *n, - struct hlist_nulls_head *h) -{ - struct hlist_nulls_node *i, *last = NULL; - - for (i = hlist_nulls_first_rcu(h); !is_a_nulls(i); - i = hlist_nulls_next_rcu(i)) - last = i; - - if (last) { - n->next = last->next; - n->pprev = &last->next; - rcu_assign_pointer(hlist_nulls_next_rcu(last), n); - } else { - hlist_nulls_add_head_rcu(n, h); - } -} - /** * hlist_nulls_for_each_entry_rcu - iterate over rcu list of given type * @tpos: the type * to use as a loop cursor. diff --git a/include/net/sock.h b/include/net/sock.h index 79e1a2c7912c..9155da422692 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -685,11 +685,7 @@ static inline void sk_add_node_rcu(struct sock *sk, struct hlist_head *list) static inline void __sk_nulls_add_node_rcu(struct sock *sk, struct hlist_nulls_head *list) { - if (IS_ENABLED(CONFIG_IPV6) && sk->sk_reuseport && - sk->sk_family == AF_INET6) - hlist_nulls_add_tail_rcu(&sk->sk_nulls_node, list); - else - hlist_nulls_add_head_rcu(&sk->sk_nulls_node, list); + hlist_nulls_add_head_rcu(&sk->sk_nulls_node, list); } static inline void sk_nulls_add_node_rcu(struct sock *sk, struct hlist_nulls_head *list) -- GitLab From 69c64866ce072dea1d1e59a0d61e0f66c0dffb76 Mon Sep 17 00:00:00 2001 From: Mohamed Ghannam Date: Tue, 5 Dec 2017 20:58:35 +0000 Subject: [PATCH 0716/2547] dccp: CVE-2017-8824: use-after-free in DCCP code Whenever the sock object is in DCCP_CLOSED state, dccp_disconnect() must free dccps_hc_tx_ccid and dccps_hc_rx_ccid and set to NULL. Signed-off-by: Mohamed Ghannam Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller --- net/dccp/proto.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/net/dccp/proto.c b/net/dccp/proto.c index b68168fcc06a..9d43c1f40274 100644 --- a/net/dccp/proto.c +++ b/net/dccp/proto.c @@ -259,6 +259,7 @@ int dccp_disconnect(struct sock *sk, int flags) { struct inet_connection_sock *icsk = inet_csk(sk); struct inet_sock *inet = inet_sk(sk); + struct dccp_sock *dp = dccp_sk(sk); int err = 0; const int old_state = sk->sk_state; @@ -278,6 +279,10 @@ int dccp_disconnect(struct sock *sk, int flags) sk->sk_err = ECONNRESET; dccp_clear_xmit_timers(sk); + ccid_hc_rx_delete(dp->dccps_hc_rx_ccid, sk); + ccid_hc_tx_delete(dp->dccps_hc_tx_ccid, sk); + dp->dccps_hc_rx_ccid = NULL; + dp->dccps_hc_tx_ccid = NULL; __skb_queue_purge(&sk->sk_receive_queue); __skb_queue_purge(&sk->sk_write_queue); -- GitLab From 588fb54b0cc5be5fd2e12bb04810534ffc3d49cc Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 30 Nov 2017 13:14:51 +0100 Subject: [PATCH 0717/2547] clk: Manage proper runtime PM state in clk_change_rate() clk_change_rate() propagates rate change down to all its children. Such operation requires managing proper runtime PM state of each child, what was missing. Add needed calls to clk_pm_runtime*() to ensure that set_rate() clock callback is called on runtime active clock. This fixes following issue found on Exynos5433 TM2 board with devfreq enabled: Synchronous External Abort: synchronous external abort (0x96000210) at 0xffffff80093f5600 Internal error: : 96000210 [#1] PREEMPT SMP Modules linked in: CPU: 0 PID: 5 Comm: kworker/u16:0 Not tainted 4.15.0-rc1-next-20171129+ #4 Hardware name: Samsung TM2 board (DT) Workqueue: devfreq_wq devfreq_monitor task: ffffffc0ca96b600 task.stack: ffffff80093a8000 pstate: a0000085 (NzCv daIf -PAN -UAO) pc : clk_divider_set_rate+0x54/0x118 lr : clk_divider_set_rate+0x44/0x118 ... Process kworker/u16:0 (pid: 5, stack limit = 0xffffff80093a8000) Call trace: clk_divider_set_rate+0x54/0x118 clk_change_rate+0xfc/0x4e0 clk_change_rate+0x1f0/0x4e0 clk_change_rate+0x1f0/0x4e0 clk_change_rate+0x1f0/0x4e0 clk_core_set_rate_nolock+0x138/0x148 clk_set_rate+0x28/0x50 exynos_bus_passive_target+0x6c/0x11c update_devfreq_passive+0x58/0xb4 devfreq_passive_notifier_call+0x50/0x5c notifier_call_chain+0x4c/0x88 __srcu_notifier_call_chain+0x54/0x80 srcu_notifier_call_chain+0x14/0x1c update_devfreq+0x100/0x1b4 devfreq_monitor+0x2c/0x88 process_one_work+0x148/0x3d8 worker_thread+0x13c/0x3f8 kthread+0x100/0x12c ret_from_fork+0x10/0x18 Reported-by: Chanwoo Choi Fixes: 9a34b45397e5 ("clk: Add support for runtime PM") Signed-off-by: Marek Szyprowski Reviewed-by: Ulf Hansson Tested-by: Chanwoo Choi Reviewed-by: Chanwoo Choi Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 647d056df88c..8a1860a36c77 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1564,6 +1564,9 @@ static void clk_change_rate(struct clk_core *core) best_parent_rate = core->parent->rate; } + if (clk_pm_runtime_get(core)) + return; + if (core->flags & CLK_SET_RATE_UNGATE) { unsigned long flags; @@ -1634,6 +1637,8 @@ static void clk_change_rate(struct clk_core *core) /* handle the new child who might not be in core->children yet */ if (core->new_child) clk_change_rate(core->new_child); + + clk_pm_runtime_put(core); } static int clk_core_set_rate_nolock(struct clk_core *core, -- GitLab From 975b820b6836b6b6c42fb84cd2e772e2b41bca67 Mon Sep 17 00:00:00 2001 From: Cai Li Date: Tue, 21 Nov 2017 17:24:38 +0800 Subject: [PATCH 0718/2547] clk: fix a panic error caused by accessing NULL pointer In some cases the clock parent would be set NULL when doing re-parent, it will cause a NULL pointer accessing if clk_set trace event is enabled. This patch sets the parent as "none" if the input parameter is NULL. Fixes: dfc202ead312 (clk: Add tracepoints for hardware operations) Signed-off-by: Cai Li Signed-off-by: Chunyan Zhang Signed-off-by: Stephen Boyd --- include/trace/events/clk.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/trace/events/clk.h b/include/trace/events/clk.h index 758607226bfd..2cd449328aee 100644 --- a/include/trace/events/clk.h +++ b/include/trace/events/clk.h @@ -134,12 +134,12 @@ DECLARE_EVENT_CLASS(clk_parent, TP_STRUCT__entry( __string( name, core->name ) - __string( pname, parent->name ) + __string( pname, parent ? parent->name : "none" ) ), TP_fast_assign( __assign_str(name, core->name); - __assign_str(pname, parent->name); + __assign_str(pname, parent ? parent->name : "none"); ), TP_printk("%s %s", __get_str(name), __get_str(pname)) -- GitLab From a5739435b5a3b8c449f8844ecd71a3b1e89f0a33 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Tue, 5 Dec 2017 23:27:57 +0000 Subject: [PATCH 0719/2547] fix kcm_clone() 1) it's fput() or sock_release(), not both 2) don't do fd_install() until the last failure exit. 3) not a bug per se, but... don't attach socket to struct file until it's set up. Take reserving descriptor into the caller, move fd_install() to the caller, sanitize failure exits and calling conventions. Cc: stable@vger.kernel.org # v4.6+ Acked-by: Tom Herbert Signed-off-by: Al Viro Signed-off-by: David S. Miller --- net/kcm/kcmsock.c | 71 ++++++++++++++++++----------------------------- 1 file changed, 27 insertions(+), 44 deletions(-) diff --git a/net/kcm/kcmsock.c b/net/kcm/kcmsock.c index 0b750a22c4b9..c5fa634e63ca 100644 --- a/net/kcm/kcmsock.c +++ b/net/kcm/kcmsock.c @@ -1625,60 +1625,35 @@ static struct proto kcm_proto = { }; /* Clone a kcm socket. */ -static int kcm_clone(struct socket *osock, struct kcm_clone *info, - struct socket **newsockp) +static struct file *kcm_clone(struct socket *osock) { struct socket *newsock; struct sock *newsk; - struct file *newfile; - int err, newfd; + struct file *file; - err = -ENFILE; newsock = sock_alloc(); if (!newsock) - goto out; + return ERR_PTR(-ENFILE); newsock->type = osock->type; newsock->ops = osock->ops; __module_get(newsock->ops->owner); - newfd = get_unused_fd_flags(0); - if (unlikely(newfd < 0)) { - err = newfd; - goto out_fd_fail; - } - - newfile = sock_alloc_file(newsock, 0, osock->sk->sk_prot_creator->name); - if (IS_ERR(newfile)) { - err = PTR_ERR(newfile); - goto out_sock_alloc_fail; - } - newsk = sk_alloc(sock_net(osock->sk), PF_KCM, GFP_KERNEL, &kcm_proto, true); if (!newsk) { - err = -ENOMEM; - goto out_sk_alloc_fail; + sock_release(newsock); + return ERR_PTR(-ENOMEM); } - sock_init_data(newsock, newsk); init_kcm_sock(kcm_sk(newsk), kcm_sk(osock->sk)->mux); - fd_install(newfd, newfile); - *newsockp = newsock; - info->fd = newfd; - - return 0; + file = sock_alloc_file(newsock, 0, osock->sk->sk_prot_creator->name); + if (IS_ERR(file)) + sock_release(newsock); -out_sk_alloc_fail: - fput(newfile); -out_sock_alloc_fail: - put_unused_fd(newfd); -out_fd_fail: - sock_release(newsock); -out: - return err; + return file; } static int kcm_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg) @@ -1708,17 +1683,25 @@ static int kcm_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg) } case SIOCKCMCLONE: { struct kcm_clone info; - struct socket *newsock = NULL; - - err = kcm_clone(sock, &info, &newsock); - if (!err) { - if (copy_to_user((void __user *)arg, &info, - sizeof(info))) { - err = -EFAULT; - sys_close(info.fd); - } - } + struct file *file; + + info.fd = get_unused_fd_flags(0); + if (unlikely(info.fd < 0)) + return info.fd; + file = kcm_clone(sock); + if (IS_ERR(file)) { + put_unused_fd(info.fd); + return PTR_ERR(file); + } + if (copy_to_user((void __user *)arg, &info, + sizeof(info))) { + put_unused_fd(info.fd); + fput(file); + return -EFAULT; + } + fd_install(info.fd, file); + err = 0; break; } default: -- GitLab From 016a266bdfeda268afb2228b6217fd4771334635 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Tue, 5 Dec 2017 23:28:38 +0000 Subject: [PATCH 0720/2547] socketpair(): allocate descriptors first simplifies failure exits considerably... Reviewed-by: Eric Dumazet Signed-off-by: Al Viro Signed-off-by: David S. Miller --- net/socket.c | 89 ++++++++++++++++++++++------------------------------ 1 file changed, 38 insertions(+), 51 deletions(-) diff --git a/net/socket.c b/net/socket.c index 42d8e9c9ccd5..2df83c0bfde9 100644 --- a/net/socket.c +++ b/net/socket.c @@ -1365,88 +1365,75 @@ SYSCALL_DEFINE4(socketpair, int, family, int, type, int, protocol, if (SOCK_NONBLOCK != O_NONBLOCK && (flags & SOCK_NONBLOCK)) flags = (flags & ~SOCK_NONBLOCK) | O_NONBLOCK; + /* + * reserve descriptors and make sure we won't fail + * to return them to userland. + */ + fd1 = get_unused_fd_flags(flags); + if (unlikely(fd1 < 0)) + return fd1; + + fd2 = get_unused_fd_flags(flags); + if (unlikely(fd2 < 0)) { + put_unused_fd(fd1); + return fd2; + } + + err = put_user(fd1, &usockvec[0]); + if (err) + goto out; + + err = put_user(fd2, &usockvec[1]); + if (err) + goto out; + /* * Obtain the first socket and check if the underlying protocol * supports the socketpair call. */ err = sock_create(family, type, protocol, &sock1); - if (err < 0) + if (unlikely(err < 0)) goto out; err = sock_create(family, type, protocol, &sock2); - if (err < 0) - goto out_release_1; - - err = sock1->ops->socketpair(sock1, sock2); - if (err < 0) - goto out_release_both; - - fd1 = get_unused_fd_flags(flags); - if (unlikely(fd1 < 0)) { - err = fd1; - goto out_release_both; + if (unlikely(err < 0)) { + sock_release(sock1); + goto out; } - fd2 = get_unused_fd_flags(flags); - if (unlikely(fd2 < 0)) { - err = fd2; - goto out_put_unused_1; + err = sock1->ops->socketpair(sock1, sock2); + if (unlikely(err < 0)) { + sock_release(sock2); + sock_release(sock1); + goto out; } newfile1 = sock_alloc_file(sock1, flags, NULL); if (IS_ERR(newfile1)) { err = PTR_ERR(newfile1); - goto out_put_unused_both; + sock_release(sock1); + sock_release(sock2); + goto out; } newfile2 = sock_alloc_file(sock2, flags, NULL); if (IS_ERR(newfile2)) { err = PTR_ERR(newfile2); - goto out_fput_1; + sock_release(sock2); + fput(newfile1); + goto out; } - err = put_user(fd1, &usockvec[0]); - if (err) - goto out_fput_both; - - err = put_user(fd2, &usockvec[1]); - if (err) - goto out_fput_both; - audit_fd_pair(fd1, fd2); fd_install(fd1, newfile1); fd_install(fd2, newfile2); - /* fd1 and fd2 may be already another descriptors. - * Not kernel problem. - */ - return 0; -out_fput_both: - fput(newfile2); - fput(newfile1); - put_unused_fd(fd2); - put_unused_fd(fd1); - goto out; - -out_fput_1: - fput(newfile1); - put_unused_fd(fd2); - put_unused_fd(fd1); - sock_release(sock2); - goto out; - -out_put_unused_both: +out: put_unused_fd(fd2); -out_put_unused_1: put_unused_fd(fd1); -out_release_both: - sock_release(sock2); -out_release_1: - sock_release(sock1); -out: return err; } -- GitLab From 8e1611e2357927b22892ecc062d65c99d0d89066 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Tue, 5 Dec 2017 23:29:09 +0000 Subject: [PATCH 0721/2547] make sock_alloc_file() do sock_release() on failures This changes calling conventions (and simplifies the hell out the callers). New rules: once struct socket had been passed to sock_alloc_file(), it's been consumed either by struct file or by sock_release() done by sock_alloc_file(). Either way the caller should not do sock_release() after that point. Reviewed-by: Eric Dumazet Signed-off-by: Al Viro Signed-off-by: David S. Miller --- drivers/staging/lustre/lnet/lnet/lib-socket.c | 8 ++---- net/9p/trans_fd.c | 1 - net/kcm/kcmsock.c | 7 +----- net/sctp/socket.c | 1 - net/socket.c | 25 ++++++------------- 5 files changed, 11 insertions(+), 31 deletions(-) diff --git a/drivers/staging/lustre/lnet/lnet/lib-socket.c b/drivers/staging/lustre/lnet/lnet/lib-socket.c index 539a26444f31..7d49d4865298 100644 --- a/drivers/staging/lustre/lnet/lnet/lib-socket.c +++ b/drivers/staging/lustre/lnet/lnet/lib-socket.c @@ -71,16 +71,12 @@ lnet_sock_ioctl(int cmd, unsigned long arg) } sock_filp = sock_alloc_file(sock, 0, NULL); - if (IS_ERR(sock_filp)) { - sock_release(sock); - rc = PTR_ERR(sock_filp); - goto out; - } + if (IS_ERR(sock_filp)) + return PTR_ERR(sock_filp); rc = kernel_sock_unlocked_ioctl(sock_filp, cmd, arg); fput(sock_filp); -out: return rc; } diff --git a/net/9p/trans_fd.c b/net/9p/trans_fd.c index 985046ae4231..80f5c79053a4 100644 --- a/net/9p/trans_fd.c +++ b/net/9p/trans_fd.c @@ -839,7 +839,6 @@ static int p9_socket_open(struct p9_client *client, struct socket *csocket) if (IS_ERR(file)) { pr_err("%s (%d): failed to map fd\n", __func__, task_pid_nr(current)); - sock_release(csocket); kfree(p); return PTR_ERR(file); } diff --git a/net/kcm/kcmsock.c b/net/kcm/kcmsock.c index c5fa634e63ca..d4e98f20fc2a 100644 --- a/net/kcm/kcmsock.c +++ b/net/kcm/kcmsock.c @@ -1629,7 +1629,6 @@ static struct file *kcm_clone(struct socket *osock) { struct socket *newsock; struct sock *newsk; - struct file *file; newsock = sock_alloc(); if (!newsock) @@ -1649,11 +1648,7 @@ static struct file *kcm_clone(struct socket *osock) sock_init_data(newsock, newsk); init_kcm_sock(kcm_sk(newsk), kcm_sk(osock->sk)->mux); - file = sock_alloc_file(newsock, 0, osock->sk->sk_prot_creator->name); - if (IS_ERR(file)) - sock_release(newsock); - - return file; + return sock_alloc_file(newsock, 0, osock->sk->sk_prot_creator->name); } static int kcm_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg) diff --git a/net/sctp/socket.c b/net/sctp/socket.c index 014847e25648..eb17a911aa29 100644 --- a/net/sctp/socket.c +++ b/net/sctp/socket.c @@ -5080,7 +5080,6 @@ static int sctp_getsockopt_peeloff_common(struct sock *sk, sctp_peeloff_arg_t *p *newfile = sock_alloc_file(newsock, 0, NULL); if (IS_ERR(*newfile)) { put_unused_fd(retval); - sock_release(newsock); retval = PTR_ERR(*newfile); *newfile = NULL; return retval; diff --git a/net/socket.c b/net/socket.c index 2df83c0bfde9..05f361faec45 100644 --- a/net/socket.c +++ b/net/socket.c @@ -406,8 +406,10 @@ struct file *sock_alloc_file(struct socket *sock, int flags, const char *dname) name.len = strlen(name.name); } path.dentry = d_alloc_pseudo(sock_mnt->mnt_sb, &name); - if (unlikely(!path.dentry)) + if (unlikely(!path.dentry)) { + sock_release(sock); return ERR_PTR(-ENOMEM); + } path.mnt = mntget(sock_mnt); d_instantiate(path.dentry, SOCK_INODE(sock)); @@ -415,9 +417,11 @@ struct file *sock_alloc_file(struct socket *sock, int flags, const char *dname) file = alloc_file(&path, FMODE_READ | FMODE_WRITE, &socket_file_ops); if (IS_ERR(file)) { - /* drop dentry, keep inode */ + /* drop dentry, keep inode for a bit */ ihold(d_inode(path.dentry)); path_put(&path); + /* ... and now kill it properly */ + sock_release(sock); return file; } @@ -1330,19 +1334,9 @@ SYSCALL_DEFINE3(socket, int, family, int, type, int, protocol) retval = sock_create(family, type, protocol, &sock); if (retval < 0) - goto out; - - retval = sock_map_fd(sock, flags & (O_CLOEXEC | O_NONBLOCK)); - if (retval < 0) - goto out_release; - -out: - /* It may be already another descriptor 8) Not kernel problem. */ - return retval; + return retval; -out_release: - sock_release(sock); - return retval; + return sock_map_fd(sock, flags & (O_CLOEXEC | O_NONBLOCK)); } /* @@ -1412,7 +1406,6 @@ SYSCALL_DEFINE4(socketpair, int, family, int, type, int, protocol, newfile1 = sock_alloc_file(sock1, flags, NULL); if (IS_ERR(newfile1)) { err = PTR_ERR(newfile1); - sock_release(sock1); sock_release(sock2); goto out; } @@ -1420,7 +1413,6 @@ SYSCALL_DEFINE4(socketpair, int, family, int, type, int, protocol, newfile2 = sock_alloc_file(sock2, flags, NULL); if (IS_ERR(newfile2)) { err = PTR_ERR(newfile2); - sock_release(sock2); fput(newfile1); goto out; } @@ -1549,7 +1541,6 @@ SYSCALL_DEFINE4(accept4, int, fd, struct sockaddr __user *, upeer_sockaddr, if (IS_ERR(newfile)) { err = PTR_ERR(newfile); put_unused_fd(newfd); - sock_release(newsock); goto out_put; } -- GitLab From 87eba0716011e528f7841026f2cc65683219d0ad Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Tue, 5 Dec 2017 08:11:58 +0100 Subject: [PATCH 0722/2547] arm64: dts: rockchip: remove vdd_log from rk3399-puma vdd_log has no consumer and therefore will not be set to a specific voltage. Still the PWM output pin gets configured and thence the vdd_log output voltage will changed from it's default. Depending on the idle state of the PWM this will slightly over or undervoltage the logic supply of the RK3399 and cause instability with GbE (undervoltage) and PCIe (overvoltage). Since the default value set by a voltage divider is the correct supply voltage and we don't need to change it during runtime we remove the rail from the devicetree completely so the PWM pin will not be configured. Signed-off-by: Klaus Goger Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index 910628d18add..1fc5060d7027 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -155,17 +155,6 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 0>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - status = "okay"; - }; }; &cpu_b0 { -- GitLab From bc631943faba6fc3f755748091ada31798fb7d50 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 6 Dec 2017 01:10:05 +0100 Subject: [PATCH 0723/2547] arm64: dts: rockchip: limit rk3328-rock64 gmac speed to 100MBit for now It looks like either the current kernel or the hardware has reliability issues when the gmac is actually running at 1GBit. In my test-case it is not able to boot on a nfsroot at this speed, as the system will always lose the connection to the nfs-server during boot, before reaching any login prompt and not recover from this. So until this is solved, limit the speed to 100MBit as with this the nfsroot survives stress tests like an apt-get upgrade without problems. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index d4f80786e7c2..3890468678ce 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -132,6 +132,8 @@ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; clock_in_out = "input"; + /* shows instability at 1GBit right now */ + max-speed = <100>; phy-supply = <&vcc_io>; phy-mode = "rgmii"; pinctrl-names = "default"; -- GitLab From b562c171cf011d297059bd0265742eb5fab0ad2f Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Mon, 4 Dec 2017 17:24:54 -0800 Subject: [PATCH 0724/2547] locking/refcounts: Do not force refcount_t usage as GPL-only export The refcount_t protection on x86 was not intended to use the stricter GPL export. This adjusts the linkage again to avoid a regression in the availability of the refcount API. Reported-by: Dave Airlie Fixes: 7a46ec0e2f48 ("locking/refcounts, x86/asm: Implement fast refcount overflow protection") Cc: stable@vger.kernel.org Signed-off-by: Kees Cook Signed-off-by: Linus Torvalds --- arch/x86/mm/extable.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index 3321b446b66c..30bc4812ceb8 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -82,7 +82,7 @@ bool ex_handler_refcount(const struct exception_table_entry *fixup, return true; } -EXPORT_SYMBOL_GPL(ex_handler_refcount); +EXPORT_SYMBOL(ex_handler_refcount); /* * Handler for when we fail to restore a task's FPU state. We should never get -- GitLab From 328b4ed93b69a6f2083d52f31a240a09e5de386a Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 5 Dec 2017 17:59:29 -0800 Subject: [PATCH 0725/2547] x86: don't hash faulting address in oops printout Things like this will probably keep showing up for other architectures and other special cases. I actually thought we already used %lx for this, and that is indeed _historically_ the case, but we moved to %p when merging the 32-bit and 64-bit cases as a convenient way to get the formatting right (ie automatically picking "%08lx" vs "%016lx" based on register size). So just turn this %p into %px. Reported-by: Sergey Senozhatsky Signed-off-by: Linus Torvalds --- arch/x86/mm/fault.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index 78ca9a8ee454..febf6980e653 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -701,7 +701,7 @@ show_fault_oops(struct pt_regs *regs, unsigned long error_code, else printk(KERN_CONT "paging request"); - printk(KERN_CONT " at %p\n", (void *) address); + printk(KERN_CONT " at %px\n", (void *) address); printk(KERN_ALERT "IP: %pS\n", (void *)regs->ip); dump_pagetable(address); -- GitLab From 3073774e638ef18d222465fe92bfc8fccb90d288 Mon Sep 17 00:00:00 2001 From: Serhii Popovych Date: Mon, 4 Dec 2017 09:36:41 -0500 Subject: [PATCH 0726/2547] KVM: PPC: Book3S HV: Drop prepare_done from struct kvm_resize_hpt Currently the kvm_resize_hpt structure has two fields relevant to the state of an ongoing resize: 'prepare_done', which indicates whether the worker thread has completed or not, and 'error' which indicates whether it was successful or not. Since the success/failure isn't known until completion, this is confusingly redundant. This patch consolidates the information into just the 'error' value: -EBUSY indicates the worked is still in progress, other negative values indicate (completed) failure, 0 indicates successful completion. As a bonus this reduces size of struct kvm_resize_hpt by __alignof__(struct kvm_hpt_info) and saves few bytes of code. While there correct comment in struct kvm_resize_hpt which references a non-existent semaphore (leftover from an early draft). Assert with WARN_ON() in case of HPT allocation thread work runs more than once for resize request or resize_hpt_allocate() returns -EBUSY that is treated specially. Change comparison against zero to make checkpatch.pl happy. Cc: stable@vger.kernel.org # v4.10+ Signed-off-by: Serhii Popovych [dwg: Changed BUG_ON()s to WARN_ON()s and altered commit message for clarity] Signed-off-by: David Gibson Signed-off-by: Paul Mackerras --- arch/powerpc/kvm/book3s_64_mmu_hv.c | 44 ++++++++++++++++++----------- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c index 966097232d21..f5f2c6bf5856 100644 --- a/arch/powerpc/kvm/book3s_64_mmu_hv.c +++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c @@ -65,11 +65,17 @@ struct kvm_resize_hpt { u32 order; /* These fields protected by kvm->lock */ + + /* Possible values and their usage: + * <0 an error occurred during allocation, + * -EBUSY allocation is in the progress, + * 0 allocation made successfuly. + */ int error; - bool prepare_done; - /* Private to the work thread, until prepare_done is true, - * then protected by kvm->resize_hpt_sem */ + /* Private to the work thread, until error != -EBUSY, + * then protected by kvm->lock. + */ struct kvm_hpt_info hpt; }; @@ -1433,15 +1439,23 @@ static void resize_hpt_prepare_work(struct work_struct *work) struct kvm *kvm = resize->kvm; int err; + if (WARN_ON(resize->error != -EBUSY)) + return; + resize_hpt_debug(resize, "resize_hpt_prepare_work(): order = %d\n", resize->order); err = resize_hpt_allocate(resize); + /* We have strict assumption about -EBUSY + * when preparing for HPT resize. + */ + if (WARN_ON(err == -EBUSY)) + err = -EINPROGRESS; + mutex_lock(&kvm->lock); resize->error = err; - resize->prepare_done = true; mutex_unlock(&kvm->lock); } @@ -1466,14 +1480,12 @@ long kvm_vm_ioctl_resize_hpt_prepare(struct kvm *kvm, if (resize) { if (resize->order == shift) { - /* Suitable resize in progress */ - if (resize->prepare_done) { - ret = resize->error; - if (ret != 0) - resize_hpt_release(kvm, resize); - } else { + /* Suitable resize in progress? */ + ret = resize->error; + if (ret == -EBUSY) ret = 100; /* estimated time in ms */ - } + else if (ret) + resize_hpt_release(kvm, resize); goto out; } @@ -1493,6 +1505,8 @@ long kvm_vm_ioctl_resize_hpt_prepare(struct kvm *kvm, ret = -ENOMEM; goto out; } + + resize->error = -EBUSY; resize->order = shift; resize->kvm = kvm; INIT_WORK(&resize->work, resize_hpt_prepare_work); @@ -1547,16 +1561,12 @@ long kvm_vm_ioctl_resize_hpt_commit(struct kvm *kvm, if (!resize || (resize->order != shift)) goto out; - ret = -EBUSY; - if (!resize->prepare_done) - goto out; - ret = resize->error; - if (ret != 0) + if (ret) goto out; ret = resize_hpt_rehash(resize); - if (ret != 0) + if (ret) goto out; resize_hpt_pivot(resize); -- GitLab From 4ed11aeefda439c76ddae3ceebcfa4fad111f149 Mon Sep 17 00:00:00 2001 From: Serhii Popovych Date: Mon, 4 Dec 2017 09:36:42 -0500 Subject: [PATCH 0727/2547] KVM: PPC: Book3S HV: Fix use after free in case of multiple resize requests When serving multiple resize requests following could happen: CPU0 CPU1 ---- ---- kvm_vm_ioctl_resize_hpt_prepare(1); -> schedule_work() /* system_rq might be busy: delay */ kvm_vm_ioctl_resize_hpt_prepare(2); mutex_lock(); if (resize) { ... release_hpt_resize(); } ... resize_hpt_prepare_work() -> schedule_work() { mutex_unlock() /* resize->kvm could be wrong */ struct kvm *kvm = resize->kvm; mutex_lock(&kvm->lock); <<<< UAF ... } i.e. a second resize request with different order could be started by kvm_vm_ioctl_resize_hpt_prepare(), causing the previous request to be free()d when there's still an active worker thread which will try to access it. This leads to a use after free in point marked with UAF on the diagram above. To prevent this from happening, instead of unconditionally releasing a pre-existing resize structure from the prepare ioctl(), we check if the existing structure has an in-progress worker. We do that by checking if the resize->error == -EBUSY, which is safe because the resize->error field is protected by the kvm->lock. If there is an active worker, instead of releasing, we mark the structure as stale by unlinking it from kvm_struct. In the worker thread we check for a stale structure (with kvm->lock held), and in that case abort, releasing the stale structure ourself. We make the check both before and the actual allocation. Strictly, only the check afterwards is needed, the check before is an optimization: if the structure happens to become stale before the worker thread is dispatched, rather than during the allocation, it means we can avoid allocating then immediately freeing a potentially substantial amount of memory. This fixes following or similar host kernel crash message: [ 635.277361] Unable to handle kernel paging request for data at address 0x00000000 [ 635.277438] Faulting instruction address: 0xc00000000052f568 [ 635.277446] Oops: Kernel access of bad area, sig: 11 [#1] [ 635.277451] SMP NR_CPUS=2048 NUMA PowerNV [ 635.277470] Modules linked in: xt_CHECKSUM iptable_mangle ipt_MASQUERADE nf_nat_masquerade_ipv4 iptable_nat nf_nat_ipv4 nf_nat nf_conntrack_ipv4 nf_defrag_ipv4 xt_conntrack nf_conntrack ipt_REJECT nf_reject_ipv4 tun bridge stp llc ebtable_filter ebtables ip6table_filter ip6_tables iptable_filter nfsv3 nfs_acl nfs lockd grace fscache kvm_hv kvm rpcrdma sunrpc ib_isert iscsi_target_mod ib_iser libiscsi scsi_transport_iscsi ib_srpt target_core_mod ext4 ib_srp scsi_transport_srp ib_ipoib mbcache jbd2 rdma_ucm ib_ucm ib_uverbs ib_umad rdma_cm ib_cm iw_cm ocrdma(T) ib_core ses enclosure scsi_transport_sas sg shpchp leds_powernv ibmpowernv i2c_opal i2c_core powernv_rng ipmi_powernv ipmi_devintf ipmi_msghandler ip_tables xfs libcrc32c sr_mod sd_mod cdrom lpfc nvme_fc(T) nvme_fabrics nvme_core ipr nvmet_fc(T) tg3 nvmet libata be2net crc_t10dif crct10dif_generic scsi_transport_fc ptp scsi_tgt pps_core crct10dif_common dm_mirror dm_region_hash dm_log dm_mod [ 635.278687] CPU: 40 PID: 749 Comm: kworker/40:1 Tainted: G ------------ T 3.10.0.bz1510771+ #1 [ 635.278782] Workqueue: events resize_hpt_prepare_work [kvm_hv] [ 635.278851] task: c0000007e6840000 ti: c0000007e9180000 task.ti: c0000007e9180000 [ 635.278919] NIP: c00000000052f568 LR: c0000000009ea310 CTR: c0000000009ea4f0 [ 635.278988] REGS: c0000007e91837f0 TRAP: 0300 Tainted: G ------------ T (3.10.0.bz1510771+) [ 635.279077] MSR: 9000000100009033 CR: 24002022 XER: 00000000 [ 635.279248] CFAR: c000000000009368 DAR: 0000000000000000 DSISR: 40000000 SOFTE: 1 GPR00: c0000000009ea310 c0000007e9183a70 c000000001250b00 c0000007e9183b10 GPR04: 0000000000000000 0000000000000000 c0000007e9183650 0000000000000000 GPR08: c0000007ffff7b80 00000000ffffffff 0000000080000028 d00000000d2529a0 GPR12: 0000000000002200 c000000007b56800 c000000000120028 c0000007f135bb40 GPR16: 0000000000000000 c000000005c1e018 c000000005c1e018 0000000000000000 GPR20: 0000000000000001 c0000000011bf778 0000000000000001 fffffffffffffef7 GPR24: 0000000000000000 c000000f1e262e50 0000000000000002 c0000007e9180000 GPR28: c000000f1e262e4c c000000f1e262e50 0000000000000000 c0000007e9183b10 [ 635.280149] NIP [c00000000052f568] __list_add+0x38/0x110 [ 635.280197] LR [c0000000009ea310] __mutex_lock_slowpath+0xe0/0x2c0 [ 635.280253] Call Trace: [ 635.280277] [c0000007e9183af0] [c0000000009ea310] __mutex_lock_slowpath+0xe0/0x2c0 [ 635.280356] [c0000007e9183b70] [c0000000009ea554] mutex_lock+0x64/0x70 [ 635.280426] [c0000007e9183ba0] [d00000000d24da04] resize_hpt_prepare_work+0xe4/0x1c0 [kvm_hv] [ 635.280507] [c0000007e9183c40] [c000000000113c0c] process_one_work+0x1dc/0x680 [ 635.280587] [c0000007e9183ce0] [c000000000114250] worker_thread+0x1a0/0x520 [ 635.280655] [c0000007e9183d80] [c00000000012010c] kthread+0xec/0x100 [ 635.280724] [c0000007e9183e30] [c00000000000a4b8] ret_from_kernel_thread+0x5c/0xa4 [ 635.280814] Instruction dump: [ 635.280880] 7c0802a6 fba1ffe8 fbc1fff0 7cbd2b78 fbe1fff8 7c9e2378 7c7f1b78 f8010010 [ 635.281099] f821ff81 e8a50008 7fa52040 40de00b8 7fbd2840 40de008c 7fbff040 [ 635.281324] ---[ end trace b628b73449719b9d ]--- Cc: stable@vger.kernel.org # v4.10+ Fixes: b5baa6877315 ("KVM: PPC: Book3S HV: KVM-HV HPT resizing implementation") Signed-off-by: Serhii Popovych [dwg: Replaced BUG_ON()s with WARN_ONs() and reworded commit message for clarity] Signed-off-by: David Gibson Signed-off-by: Paul Mackerras --- arch/powerpc/kvm/book3s_64_mmu_hv.c | 50 ++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c index f5f2c6bf5856..8355398f0bb6 100644 --- a/arch/powerpc/kvm/book3s_64_mmu_hv.c +++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c @@ -1419,16 +1419,20 @@ static void resize_hpt_pivot(struct kvm_resize_hpt *resize) static void resize_hpt_release(struct kvm *kvm, struct kvm_resize_hpt *resize) { - BUG_ON(kvm->arch.resize_hpt != resize); + if (WARN_ON(!mutex_is_locked(&kvm->lock))) + return; if (!resize) return; - if (resize->hpt.virt) - kvmppc_free_hpt(&resize->hpt); + if (resize->error != -EBUSY) { + if (resize->hpt.virt) + kvmppc_free_hpt(&resize->hpt); + kfree(resize); + } - kvm->arch.resize_hpt = NULL; - kfree(resize); + if (kvm->arch.resize_hpt == resize) + kvm->arch.resize_hpt = NULL; } static void resize_hpt_prepare_work(struct work_struct *work) @@ -1437,26 +1441,42 @@ static void resize_hpt_prepare_work(struct work_struct *work) struct kvm_resize_hpt, work); struct kvm *kvm = resize->kvm; - int err; + int err = 0; if (WARN_ON(resize->error != -EBUSY)) return; - resize_hpt_debug(resize, "resize_hpt_prepare_work(): order = %d\n", - resize->order); + mutex_lock(&kvm->lock); - err = resize_hpt_allocate(resize); + /* Request is still current? */ + if (kvm->arch.resize_hpt == resize) { + /* We may request large allocations here: + * do not sleep with kvm->lock held for a while. + */ + mutex_unlock(&kvm->lock); - /* We have strict assumption about -EBUSY - * when preparing for HPT resize. - */ - if (WARN_ON(err == -EBUSY)) - err = -EINPROGRESS; + resize_hpt_debug(resize, "resize_hpt_prepare_work(): order = %d\n", + resize->order); - mutex_lock(&kvm->lock); + err = resize_hpt_allocate(resize); + + /* We have strict assumption about -EBUSY + * when preparing for HPT resize. + */ + if (WARN_ON(err == -EBUSY)) + err = -EINPROGRESS; + + mutex_lock(&kvm->lock); + /* It is possible that kvm->arch.resize_hpt != resize + * after we grab kvm->lock again. + */ + } resize->error = err; + if (kvm->arch.resize_hpt != resize) + resize_hpt_release(kvm, resize); + mutex_unlock(&kvm->lock); } -- GitLab From add7e4fc2420e35f200e4aa13764708e62690e2e Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Thu, 2 Nov 2017 13:33:42 +0800 Subject: [PATCH 0728/2547] drm/i915/gvt: Emulate PCI expansion ROM base address register Our vGPU doesn't have a device ROM, we need follow the PCI spec to report this info to drivers. Otherwise, we would see below errors. Inspecting possible rom at 0xfe049000 (vd=8086:1912 bdf=00:10.0) qemu-system-x86_64: vfio-pci: Cannot read device rom at 00000000-0000-0000-0000-000000000001 Device option ROM contents are probably invalid (check dmesg). Skip option ROM probe with rombar=0, or load from file with romfile=No option rom signature (got 4860) I will also send a improvement patch to PCI subsystem related to PCI ROM. But no idea to omit below error, since no pattern to detect vbios shadow without touch its content. 0000:00:10.0: Invalid PCI ROM header signature: expecting 0xaa55, got 0x0000 Signed-off-by: Changbin Du Signed-off-by: Zhenyu Wang (cherry picked from commit c4270d122ccff963a021d1beb893d6192336af96) --- drivers/gpu/drm/i915/gvt/cfg_space.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c index ab19545d59a1..4ce2e6bd0680 100644 --- a/drivers/gpu/drm/i915/gvt/cfg_space.c +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c @@ -208,6 +208,20 @@ static int emulate_pci_command_write(struct intel_vgpu *vgpu, return 0; } +static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu, + unsigned int offset, void *p_data, unsigned int bytes) +{ + u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); + u32 new = *(u32 *)(p_data); + + if ((new & PCI_ROM_ADDRESS_MASK) == PCI_ROM_ADDRESS_MASK) + /* We don't have rom, return size of 0. */ + *pval = 0; + else + vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); + return 0; +} + static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { @@ -300,6 +314,11 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, } switch (rounddown(offset, 4)) { + case PCI_ROM_ADDRESS: + if (WARN_ON(!IS_ALIGNED(offset, 4))) + return -EINVAL; + return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes); + case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5: if (WARN_ON(!IS_ALIGNED(offset, 4))) return -EINVAL; @@ -375,6 +394,8 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, pci_resource_len(gvt->dev_priv->drm.pdev, 0); vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size = pci_resource_len(gvt->dev_priv->drm.pdev, 2); + + memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4); } /** -- GitLab From 365ad5df9caa1a7ebc73b8d70ab94bbf6a74268a Mon Sep 17 00:00:00 2001 From: Zhi Wang Date: Sat, 30 Sep 2017 17:42:20 +0800 Subject: [PATCH 0729/2547] drm/i915/gvt: Export intel_gvt_render_mmio_to_ring_id() Since many emulation logic needs to convert the offset of ring registers into ring id, we export it for other caller which might need it. Signed-off-by: Zhi Wang (cherry picked from commit 62a6a53786fc4b4e7543cc63b704dbb3f7df4c0f) --- drivers/gpu/drm/i915/gvt/handlers.c | 21 +++++++++++++++------ drivers/gpu/drm/i915/gvt/mmio.h | 2 ++ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 44cd5ff5e97d..55cbdb022924 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -137,17 +137,26 @@ static int new_mmio_info(struct intel_gvt *gvt, return 0; } -static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) +/** + * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id + * @gvt: a GVT device + * @offset: register offset + * + * Returns: + * Ring ID on success, negative error code if failed. + */ +int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt, + unsigned int offset) { enum intel_engine_id id; struct intel_engine_cs *engine; - reg &= ~GENMASK(11, 0); + offset &= ~GENMASK(11, 0); for_each_engine(engine, gvt->dev_priv, id) { - if (engine->mmio_base == reg) + if (engine->mmio_base == offset) return id; } - return -1; + return -ENODEV; } #define offset_to_fence_num(offset) \ @@ -1409,7 +1418,7 @@ static int mmio_read_from_hw(struct intel_vgpu *vgpu, static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { - int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); + int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); struct intel_vgpu_execlist *execlist; u32 data = *(u32 *)p_data; int ret = 0; @@ -1436,7 +1445,7 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { u32 data = *(u32 *)p_data; - int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); + int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); bool enable_execlist; write_vreg(vgpu, offset, p_data, bytes); diff --git a/drivers/gpu/drm/i915/gvt/mmio.h b/drivers/gpu/drm/i915/gvt/mmio.h index 32cd64ddad26..dbc04ad2c7a1 100644 --- a/drivers/gpu/drm/i915/gvt/mmio.h +++ b/drivers/gpu/drm/i915/gvt/mmio.h @@ -65,6 +65,8 @@ struct intel_gvt_mmio_info { struct hlist_node node; }; +int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt, + unsigned int reg); unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt); bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device); -- GitLab From 29f9e425973d3c7cdfc32725a4d7c4c2f537d5a9 Mon Sep 17 00:00:00 2001 From: Xiong Zhang Date: Tue, 7 Nov 2017 05:23:02 +0800 Subject: [PATCH 0730/2547] drm/i915/gvt: Limit read hw reg to active vgpu mmio_read_from_hw() let vgpu could read hw reg, if vgpu's workload is running on hw, things is good. Otherwise vgpu will get other vgpu's reg val, it is unsafe. This patch limit such hw access to active vgpu. If vgpu isn't running on hw, the reg read of this vgpu will get the last active val which saved at schedule_out. v2: ring timestamp is walking continuously even if the ring is idle. so read hw directly. (Zhenyu) Signed-off-by: Xiong Zhang Signed-off-by: Zhenyu Wang (cherry picked from commit 295764cd2ff41e2c1bc8af4050de77cec5e7a1c0) --- drivers/gpu/drm/i915/gvt/handlers.c | 26 ++++++++++++++++++++++---- drivers/gpu/drm/i915/gvt/scheduler.c | 15 +++++++++++++++ 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 55cbdb022924..1f840f6b81bb 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1407,11 +1407,29 @@ static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, static int mmio_read_from_hw(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { - struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + struct intel_gvt *gvt = vgpu->gvt; + struct drm_i915_private *dev_priv = gvt->dev_priv; + int ring_id; + u32 ring_base; + + ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset); + /** + * Read HW reg in following case + * a. the offset isn't a ring mmio + * b. the offset's ring is running on hw. + * c. the offset is ring time stamp mmio + */ + if (ring_id >= 0) + ring_base = dev_priv->engine[ring_id]->mmio_base; + + if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] || + offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) || + offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) { + mmio_hw_access_pre(dev_priv); + vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); + mmio_hw_access_post(dev_priv); + } - mmio_hw_access_pre(dev_priv); - vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); - mmio_hw_access_post(dev_priv); return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); } diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 3ac1dc97a7a0..a63787be1e6b 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -131,6 +131,20 @@ static inline bool is_gvt_request(struct drm_i915_gem_request *req) return i915_gem_context_force_single_submission(req->ctx); } +static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id) +{ + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + u32 ring_base = dev_priv->engine[ring_id]->mmio_base; + i915_reg_t reg; + + reg = RING_INSTDONE(ring_base); + vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); + reg = RING_ACTHD(ring_base); + vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); + reg = RING_ACTHD_UDW(ring_base); + vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); +} + static int shadow_context_status_change(struct notifier_block *nb, unsigned long action, void *data) { @@ -176,6 +190,7 @@ static int shadow_context_status_change(struct notifier_block *nb, break; case INTEL_CONTEXT_SCHEDULE_OUT: case INTEL_CONTEXT_SCHEDULE_PREEMPTED: + save_ring_hw_state(workload->vgpu, ring_id); atomic_set(&workload->shadow_ctx_active, 0); break; default: -- GitLab From ac7688c0397442f1c9eef7069737089660322497 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Fri, 1 Dec 2017 14:59:53 +0800 Subject: [PATCH 0731/2547] drm/i915/gvt: Don't mark vgpu context as inactive when preempted We shouldn't mark inactive for vGPU context if preempted, which would still be re-scheduled later. So keep active state. Fixes: d6c0511300dc ("drm/i915/execlists: Distinguish the incomplete context notifies") Signed-off-by: Zhenyu Wang (cherry picked from commit da5f99eaccc10e30bf82eb02b1be74703b878720) --- drivers/gpu/drm/i915/gvt/scheduler.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index a63787be1e6b..ab3d041ee5f9 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -189,10 +189,12 @@ static int shadow_context_status_change(struct notifier_block *nb, atomic_set(&workload->shadow_ctx_active, 1); break; case INTEL_CONTEXT_SCHEDULE_OUT: - case INTEL_CONTEXT_SCHEDULE_PREEMPTED: save_ring_hw_state(workload->vgpu, ring_id); atomic_set(&workload->shadow_ctx_active, 0); break; + case INTEL_CONTEXT_SCHEDULE_PREEMPTED: + save_ring_hw_state(workload->vgpu, ring_id); + break; default: WARN_ON(1); return NOTIFY_OK; -- GitLab From 11474e9091cf2002e948647fd9f63a7f027e488a Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Mon, 4 Dec 2017 10:42:58 +0800 Subject: [PATCH 0732/2547] drm/i915/gvt: set max priority for gvt context This is to workaround guest driver hang regression after preemption enable that gvt hasn't enabled handling of that for guest workload. So in effect this disables preemption for gvt context now. Signed-off-by: Zhenyu Wang (cherry picked from commit 1603660b3342269c95fcafee1945790342a8c28e) --- drivers/gpu/drm/i915/gvt/scheduler.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index ab3d041ee5f9..69f8f0d155b9 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -757,6 +757,9 @@ int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu) if (IS_ERR(vgpu->shadow_ctx)) return PTR_ERR(vgpu->shadow_ctx); + if (INTEL_INFO(vgpu->gvt->dev_priv)->has_logical_ring_preemption) + vgpu->shadow_ctx->priority = INT_MAX; + vgpu->shadow_ctx->engine[RCS].initialised = true; bitmap_zero(vgpu->shadow_ctx_desc_updated, I915_NUM_ENGINES); -- GitLab From 71334963d01ed7ec61a958a5a6585172793f5a24 Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Tue, 5 Dec 2017 11:27:59 +0100 Subject: [PATCH 0733/2547] wireless: replace usage of hexdump with od/sed Since od/sed are in posix, hopefully there's a better chance people will have them, over hexdump. Fixes: 90a53e4432b1 ("cfg80211: implement regdb signature checking") Signed-off-by: Johannes Berg --- net/wireless/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/wireless/Makefile b/net/wireless/Makefile index 278d979c211a..63cbb6432b2d 100644 --- a/net/wireless/Makefile +++ b/net/wireless/Makefile @@ -27,7 +27,7 @@ $(obj)/shipped-certs.c: $(wildcard $(srctree)/$(src)/certs/*.x509) @$(kecho) " GEN $@" @echo '#include "reg.h"' > $@ @echo 'const u8 shipped_regdb_certs[] = {' >> $@ - @for f in $^ ; do hexdump -v -e '1/1 "0x%.2x," "\n"' < $$f >> $@ ; done + @for f in $^ ; do od -An -v -tx1 < $$f | sed -e 's/ /\n/g' | sed -e 's/^[0-9a-f]\+$$/\0/;t;d' | sed -e 's/^/0x/;s/$$/,/' >> $@ ; done @echo '};' >> $@ @echo 'unsigned int shipped_regdb_certs_len = sizeof(shipped_regdb_certs);' >> $@ @@ -36,6 +36,6 @@ $(obj)/extra-certs.c: $(CONFIG_CFG80211_EXTRA_REGDB_KEYDIR:"%"=%) \ @$(kecho) " GEN $@" @echo '#include "reg.h"' > $@ @echo 'const u8 extra_regdb_certs[] = {' >> $@ - @for f in $^ ; do test -f $$f && hexdump -v -e '1/1 "0x%.2x," "\n"' < $$f >> $@ || true ; done + @for f in $^ ; do test -f $$f && od -An -v -tx1 < $$f | sed -e 's/ /\n/g' | sed -e 's/^[0-9a-f]\+$$/\0/;t;d' | sed -e 's/^/0x/;s/$$/,/' >> $@ ; done @echo '};' >> $@ @echo 'unsigned int extra_regdb_certs_len = sizeof(extra_regdb_certs);' >> $@ -- GitLab From 715a12334764657bafb3ab964fb25f4e6115c770 Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Tue, 5 Dec 2017 11:59:33 +0100 Subject: [PATCH 0734/2547] wireless: don't write C files on failures Change the scripting inside the shipped/extra certs C code generation to not write the file when there are any failures. That way, if the build aborts due to failures, we don't get into a situation where a dummy file has been created and the next build succeeds, but not with the desired output. Fixes: 90a53e4432b1 ("cfg80211: implement regdb signature checking") Signed-off-by: Johannes Berg --- net/wireless/Makefile | 48 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/net/wireless/Makefile b/net/wireless/Makefile index 63cbb6432b2d..d7d6cb00c47b 100644 --- a/net/wireless/Makefile +++ b/net/wireless/Makefile @@ -25,17 +25,45 @@ endif $(obj)/shipped-certs.c: $(wildcard $(srctree)/$(src)/certs/*.x509) @$(kecho) " GEN $@" - @echo '#include "reg.h"' > $@ - @echo 'const u8 shipped_regdb_certs[] = {' >> $@ - @for f in $^ ; do od -An -v -tx1 < $$f | sed -e 's/ /\n/g' | sed -e 's/^[0-9a-f]\+$$/\0/;t;d' | sed -e 's/^/0x/;s/$$/,/' >> $@ ; done - @echo '};' >> $@ - @echo 'unsigned int shipped_regdb_certs_len = sizeof(shipped_regdb_certs);' >> $@ + @(set -e; \ + allf=""; \ + for f in $^ ; do \ + # similar to hexdump -v -e '1/1 "0x%.2x," "\n"' \ + thisf=$$(od -An -v -tx1 < $$f | \ + sed -e 's/ /\n/g' | \ + sed -e 's/^[0-9a-f]\+$$/\0/;t;d' | \ + sed -e 's/^/0x/;s/$$/,/'); \ + # file should not be empty - maybe command substitution failed? \ + test ! -z "$$thisf";\ + allf=$$allf$$thisf;\ + done; \ + ( \ + echo '#include "reg.h"'; \ + echo 'const u8 shipped_regdb_certs[] = {'; \ + echo "$$allf"; \ + echo '};'; \ + echo 'unsigned int shipped_regdb_certs_len = sizeof(shipped_regdb_certs);'; \ + ) >> $@) $(obj)/extra-certs.c: $(CONFIG_CFG80211_EXTRA_REGDB_KEYDIR:"%"=%) \ $(wildcard $(CONFIG_CFG80211_EXTRA_REGDB_KEYDIR:"%"=%)/*.x509) @$(kecho) " GEN $@" - @echo '#include "reg.h"' > $@ - @echo 'const u8 extra_regdb_certs[] = {' >> $@ - @for f in $^ ; do test -f $$f && od -An -v -tx1 < $$f | sed -e 's/ /\n/g' | sed -e 's/^[0-9a-f]\+$$/\0/;t;d' | sed -e 's/^/0x/;s/$$/,/' >> $@ ; done - @echo '};' >> $@ - @echo 'unsigned int extra_regdb_certs_len = sizeof(extra_regdb_certs);' >> $@ + @(set -e; \ + allf=""; \ + for f in $^ ; do \ + # similar to hexdump -v -e '1/1 "0x%.2x," "\n"' \ + thisf=$$(od -An -v -tx1 < $$f | \ + sed -e 's/ /\n/g' | \ + sed -e 's/^[0-9a-f]\+$$/\0/;t;d' | \ + sed -e 's/^/0x/;s/$$/,/'); \ + # file should not be empty - maybe command substitution failed? \ + test ! -z "$$thisf";\ + allf=$$allf$$thisf;\ + done; \ + ( \ + echo '#include "reg.h"'; \ + echo 'const u8 extra_regdb_certs[] = {'; \ + echo "$$allf"; \ + echo '};'; \ + echo 'unsigned int extra_regdb_certs_len = sizeof(extra_regdb_certs);'; \ + ) >> $@) -- GitLab From 916a27901de01446bcf57ecca4783f6cff493309 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Tue, 5 Dec 2017 15:42:41 -0800 Subject: [PATCH 0735/2547] netfilter: xt_osf: Add missing permission checks The capability check in nfnetlink_rcv() verifies that the caller has CAP_NET_ADMIN in the namespace that "owns" the netlink socket. However, xt_osf_fingers is shared by all net namespaces on the system. An unprivileged user can create user and net namespaces in which he holds CAP_NET_ADMIN to bypass the netlink_net_capable() check: vpnns -- nfnl_osf -f /tmp/pf.os vpnns -- nfnl_osf -f /tmp/pf.os -d These non-root operations successfully modify the systemwide OS fingerprint list. Add new capable() checks so that they can't. Signed-off-by: Kevin Cernekee Signed-off-by: Pablo Neira Ayuso --- net/netfilter/xt_osf.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/net/netfilter/xt_osf.c b/net/netfilter/xt_osf.c index 36e14b1f061d..a34f314a8c23 100644 --- a/net/netfilter/xt_osf.c +++ b/net/netfilter/xt_osf.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include @@ -70,6 +71,9 @@ static int xt_osf_add_callback(struct net *net, struct sock *ctnl, struct xt_osf_finger *kf = NULL, *sf; int err = 0; + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + if (!osf_attrs[OSF_ATTR_FINGER]) return -EINVAL; @@ -115,6 +119,9 @@ static int xt_osf_remove_callback(struct net *net, struct sock *ctnl, struct xt_osf_finger *sf; int err = -ENOENT; + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + if (!osf_attrs[OSF_ATTR_FINGER]) return -EINVAL; -- GitLab From d809aa238744ae5b7520b73ac5411862ccfdc1bc Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 24 Nov 2017 15:00:33 +0100 Subject: [PATCH 0736/2547] KVM: s390: add SPDX identifiers to the remaining files It's good to have SPDX identifiers in all files to make it easier to audit the kernel tree for correct licenses. Update the arch/s390/kvm/ files with the correct SPDX license identifier based on the license text in the file itself. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This work is based on a script and data from Thomas Gleixner, Philippe Ombredanne, and Kate Stewart. Cc: Christian Borntraeger Cc: Cornelia Huck Cc: Martin Schwidefsky Cc: Heiko Carstens Cc: Thomas Gleixner Cc: Kate Stewart Cc: Philippe Ombredanne Signed-off-by: Greg Kroah-Hartman Message-Id: <20171124140043.10062-3-gregkh@linuxfoundation.org> Acked-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/kvm/Makefile | 1 + arch/s390/kvm/diag.c | 1 + arch/s390/kvm/gaccess.h | 1 + arch/s390/kvm/guestdbg.c | 1 + arch/s390/kvm/intercept.c | 1 + arch/s390/kvm/interrupt.c | 1 + arch/s390/kvm/irq.h | 1 + arch/s390/kvm/kvm-s390.c | 1 + arch/s390/kvm/kvm-s390.h | 1 + arch/s390/kvm/priv.c | 1 + arch/s390/kvm/sigp.c | 1 + arch/s390/kvm/vsie.c | 1 + 12 files changed, 12 insertions(+) diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile index 6048b1c6e580..2c5a8190d5ce 100644 --- a/arch/s390/kvm/Makefile +++ b/arch/s390/kvm/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # Makefile for kernel virtual machines on s390 # # Copyright IBM Corp. 2008 diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c index d93a2c0474bf..481e1fe6095f 100644 --- a/arch/s390/kvm/diag.c +++ b/arch/s390/kvm/diag.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * handling diagnose instructions * diff --git a/arch/s390/kvm/gaccess.h b/arch/s390/kvm/gaccess.h index bec42b852246..443b7fa82d56 100644 --- a/arch/s390/kvm/gaccess.h +++ b/arch/s390/kvm/gaccess.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * access guest memory * diff --git a/arch/s390/kvm/guestdbg.c b/arch/s390/kvm/guestdbg.c index bcbd86621d01..d6a1bead813c 100644 --- a/arch/s390/kvm/guestdbg.c +++ b/arch/s390/kvm/guestdbg.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * kvm guest debug support * diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index 8fe034beb623..fc76a91a7820 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * in-kernel handling for sie intercepts * diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index fa557372d600..f37a34ea1601 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * handling kvm guest interrupts * diff --git a/arch/s390/kvm/irq.h b/arch/s390/kvm/irq.h index d98e4159643d..54a4a59cb4f9 100644 --- a/arch/s390/kvm/irq.h +++ b/arch/s390/kvm/irq.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * s390 irqchip routines * diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 98ad8b9e0360..0d45e32dd868 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * hosting zSeries kernel virtual machines * diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index 10d65dfbc306..9777924c4b5c 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * definition for kvm on s390 * diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index c954ac49eee4..c9d962ac140b 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * handling privileged instructions * diff --git a/arch/s390/kvm/sigp.c b/arch/s390/kvm/sigp.c index 9d592ef4104b..d12ac5d6e8bb 100644 --- a/arch/s390/kvm/sigp.c +++ b/arch/s390/kvm/sigp.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * handling interprocessor communication * diff --git a/arch/s390/kvm/vsie.c b/arch/s390/kvm/vsie.c index a311938b63b3..d2b7886da444 100644 --- a/arch/s390/kvm/vsie.c +++ b/arch/s390/kvm/vsie.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * kvm nested virtualization support for s390x * -- GitLab From 940f89a5a37789b94f332755767c556a64b004e4 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 24 Nov 2017 15:00:39 +0100 Subject: [PATCH 0737/2547] KVM: s390: Remove redundant license text Now that the SPDX tag is in all arch/s390/kvm/ files, that identifies the license in a specific and legally-defined manner. So the extra GPL text wording can be removed as it is no longer needed at all. This is done on a quest to remove the 700+ different ways that files in the kernel describe the GPL license text. And there's unneeded stuff like the address (sometimes incorrect) for the FSF which is never needed. No copyright headers or other non-license-description text was removed. Cc: Christian Borntraeger Cc: Cornelia Huck Cc: Martin Schwidefsky Cc: Heiko Carstens Cc: "Paul E. McKenney" Signed-off-by: Greg Kroah-Hartman Message-Id: <20171124140043.10062-9-gregkh@linuxfoundation.org> Acked-by: Cornelia Huck Acked-by: "Paul E. McKenney" Signed-off-by: Christian Borntraeger --- arch/s390/kvm/Makefile | 4 ---- arch/s390/kvm/diag.c | 4 ---- arch/s390/kvm/gaccess.h | 4 ---- arch/s390/kvm/guestdbg.c | 4 ---- arch/s390/kvm/intercept.c | 4 ---- arch/s390/kvm/interrupt.c | 4 ---- arch/s390/kvm/irq.h | 4 ---- arch/s390/kvm/kvm-s390.c | 4 ---- arch/s390/kvm/kvm-s390.h | 4 ---- arch/s390/kvm/priv.c | 4 ---- arch/s390/kvm/sigp.c | 4 ---- arch/s390/kvm/vsie.c | 4 ---- 12 files changed, 48 deletions(-) diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile index 2c5a8190d5ce..05ee90a5ea08 100644 --- a/arch/s390/kvm/Makefile +++ b/arch/s390/kvm/Makefile @@ -2,10 +2,6 @@ # Makefile for kernel virtual machines on s390 # # Copyright IBM Corp. 2008 -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License (version 2 only) -# as published by the Free Software Foundation. KVM := ../../../virt/kvm common-objs = $(KVM)/kvm_main.o $(KVM)/eventfd.o $(KVM)/async_pf.o $(KVM)/irqchip.o $(KVM)/vfio.o diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c index 481e1fe6095f..89aa114a2cba 100644 --- a/arch/s390/kvm/diag.c +++ b/arch/s390/kvm/diag.c @@ -4,10 +4,6 @@ * * Copyright IBM Corp. 2008, 2011 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): Carsten Otte * Christian Borntraeger */ diff --git a/arch/s390/kvm/gaccess.h b/arch/s390/kvm/gaccess.h index 443b7fa82d56..f4c51756c462 100644 --- a/arch/s390/kvm/gaccess.h +++ b/arch/s390/kvm/gaccess.h @@ -4,10 +4,6 @@ * * Copyright IBM Corp. 2008, 2014 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): Carsten Otte */ diff --git a/arch/s390/kvm/guestdbg.c b/arch/s390/kvm/guestdbg.c index d6a1bead813c..b5f3e82006d0 100644 --- a/arch/s390/kvm/guestdbg.c +++ b/arch/s390/kvm/guestdbg.c @@ -4,10 +4,6 @@ * * Copyright IBM Corp. 2014 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): David Hildenbrand */ #include diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index fc76a91a7820..9c7d70715862 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -4,10 +4,6 @@ * * Copyright IBM Corp. 2008, 2014 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): Carsten Otte * Christian Borntraeger */ diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index f37a34ea1601..024ad8bcc516 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -4,10 +4,6 @@ * * Copyright IBM Corp. 2008, 2015 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): Carsten Otte */ diff --git a/arch/s390/kvm/irq.h b/arch/s390/kvm/irq.h index 54a4a59cb4f9..484608c71dd0 100644 --- a/arch/s390/kvm/irq.h +++ b/arch/s390/kvm/irq.h @@ -4,10 +4,6 @@ * * Copyright IBM Corp. 2014 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): Cornelia Huck */ #ifndef __KVM_IRQ_H diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 0d45e32dd868..34375eed93ee 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -4,10 +4,6 @@ * * Copyright IBM Corp. 2008, 2009 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): Carsten Otte * Christian Borntraeger * Heiko Carstens diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index 9777924c4b5c..5e46ba429bcb 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -4,10 +4,6 @@ * * Copyright IBM Corp. 2008, 2009 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): Carsten Otte * Christian Borntraeger * Christian Ehrhardt diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index c9d962ac140b..28b69ab56b7b 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -4,10 +4,6 @@ * * Copyright IBM Corp. 2008, 2013 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): Carsten Otte * Christian Borntraeger */ diff --git a/arch/s390/kvm/sigp.c b/arch/s390/kvm/sigp.c index d12ac5d6e8bb..c1f5cde2c878 100644 --- a/arch/s390/kvm/sigp.c +++ b/arch/s390/kvm/sigp.c @@ -4,10 +4,6 @@ * * Copyright IBM Corp. 2008, 2013 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): Carsten Otte * Christian Borntraeger * Christian Ehrhardt diff --git a/arch/s390/kvm/vsie.c b/arch/s390/kvm/vsie.c index d2b7886da444..5d6ae0326d9e 100644 --- a/arch/s390/kvm/vsie.c +++ b/arch/s390/kvm/vsie.c @@ -4,10 +4,6 @@ * * Copyright IBM Corp. 2016 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): David Hildenbrand */ #include -- GitLab From bb64da9aba89765fee74b395967b18a7d6c364e9 Mon Sep 17 00:00:00 2001 From: Christian Borntraeger Date: Tue, 21 Nov 2017 16:02:52 +0100 Subject: [PATCH 0738/2547] KVM: s390: mark irq_state.flags as non-usable Old kernels did not check for zero in the irq_state.flags field and old QEMUs did not zero the flag/reserved fields when calling KVM_S390_*_IRQ_STATE. Let's add comments to prevent future uses of these fields. Signed-off-by: Christian Borntraeger Reviewed-by: Thomas Huth Reviewed-by: Cornelia Huck Reviewed-by: David Hildenbrand Signed-off-by: Christian Borntraeger --- Documentation/virtual/kvm/api.txt | 15 ++++++++++++--- arch/s390/kvm/kvm-s390.c | 6 ++++-- include/uapi/linux/kvm.h | 4 ++-- 3 files changed, 18 insertions(+), 7 deletions(-) diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index f670e4b9e7f3..57d3ee9e4bde 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -2901,14 +2901,19 @@ userspace buffer and its length: struct kvm_s390_irq_state { __u64 buf; - __u32 flags; + __u32 flags; /* will stay unused for compatibility reasons */ __u32 len; - __u32 reserved[4]; + __u32 reserved[4]; /* will stay unused for compatibility reasons */ }; Userspace passes in the above struct and for each pending interrupt a struct kvm_s390_irq is copied to the provided buffer. +The structure contains a flags and a reserved field for future extensions. As +the kernel never checked for flags == 0 and QEMU never pre-zeroed flags and +reserved, these fields can not be used in the future without breaking +compatibility. + If -ENOBUFS is returned the buffer provided was too small and userspace may retry with a bigger buffer. @@ -2932,10 +2937,14 @@ containing a struct kvm_s390_irq_state: struct kvm_s390_irq_state { __u64 buf; + __u32 flags; /* will stay unused for compatibility reasons */ __u32 len; - __u32 pad; + __u32 reserved[4]; /* will stay unused for compatibility reasons */ }; +The restrictions for flags and reserved apply as well. +(see KVM_S390_GET_IRQ_STATE) + The userspace memory referenced by buf contains a struct kvm_s390_irq for each interrupt to be injected into the guest. If one of the interrupts could not be injected for some reason the diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 34375eed93ee..efa439f6ffb3 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* - * hosting zSeries kernel virtual machines + * hosting IBM Z kernel virtual machines (s390x) * - * Copyright IBM Corp. 2008, 2009 + * Copyright IBM Corp. 2008, 2017 * * Author(s): Carsten Otte * Christian Borntraeger @@ -3808,6 +3808,7 @@ long kvm_arch_vcpu_ioctl(struct file *filp, r = -EINVAL; break; } + /* do not use irq_state.flags, it will break old QEMUs */ r = kvm_s390_set_irq_state(vcpu, (void __user *) irq_state.buf, irq_state.len); @@ -3823,6 +3824,7 @@ long kvm_arch_vcpu_ioctl(struct file *filp, r = -EINVAL; break; } + /* do not use irq_state.flags, it will break old QEMUs */ r = kvm_s390_get_irq_state(vcpu, (__u8 __user *) irq_state.buf, irq_state.len); diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 282d7613fce8..496e59a2738b 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -630,9 +630,9 @@ struct kvm_s390_irq { struct kvm_s390_irq_state { __u64 buf; - __u32 flags; + __u32 flags; /* will stay unused for compatibility reasons */ __u32 len; - __u32 reserved[4]; + __u32 reserved[4]; /* will stay unused for compatibility reasons */ }; /* for KVM_SET_GUEST_DEBUG */ -- GitLab From ca76ec9ca871e67d8cd0b6caba24aca3d3ac4546 Mon Sep 17 00:00:00 2001 From: Janosch Frank Date: Mon, 4 Dec 2017 12:19:11 +0100 Subject: [PATCH 0739/2547] KVM: s390: Fix skey emulation permission check All skey functions call skey_check_enable at their start, which checks if we are in the PSTATE and injects a privileged operation exception if we are. Unfortunately they continue processing afterwards and perform the operation anyhow as skey_check_enable does not deliver an error if the exception injection was successful. Let's move the PSTATE check into the skey functions and exit them on such an occasion, also we now do not enable skey handling anymore in such a case. Signed-off-by: Janosch Frank Reviewed-by: Christian Borntraeger Fixes: a7e19ab ("KVM: s390: handle missing storage-key facility") Cc: # v4.8+ Reviewed-by: Cornelia Huck Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 28b69ab56b7b..572496c688cc 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -232,8 +232,6 @@ static int try_handle_skey(struct kvm_vcpu *vcpu) VCPU_EVENT(vcpu, 4, "%s", "retrying storage key operation"); return -EAGAIN; } - if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) - return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); return 0; } @@ -244,6 +242,9 @@ static int handle_iske(struct kvm_vcpu *vcpu) int reg1, reg2; int rc; + if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) + return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); + rc = try_handle_skey(vcpu); if (rc) return rc != -EAGAIN ? rc : 0; @@ -273,6 +274,9 @@ static int handle_rrbe(struct kvm_vcpu *vcpu) int reg1, reg2; int rc; + if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) + return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); + rc = try_handle_skey(vcpu); if (rc) return rc != -EAGAIN ? rc : 0; @@ -308,6 +312,9 @@ static int handle_sske(struct kvm_vcpu *vcpu) int reg1, reg2; int rc; + if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) + return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); + rc = try_handle_skey(vcpu); if (rc) return rc != -EAGAIN ? rc : 0; -- GitLab From a703c55004e1c5076d57e43771b3e11117796ea0 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Mon, 4 Dec 2017 21:48:18 +0100 Subject: [PATCH 0740/2547] drm: safely free connectors from connector_iter In commit 613051dac40da1751ab269572766d3348d45a197 Author: Daniel Vetter Date: Wed Dec 14 00:08:06 2016 +0100 drm: locking&new iterators for connector_list we've went to extreme lengths to make sure connector iterations works in any context, without introducing any additional locking context. This worked, except for a small fumble in the implementation: When we actually race with a concurrent connector unplug event, and our temporary connector reference turns out to be the final one, then everything breaks: We call the connector release function from whatever context we happen to be in, which can be an irq/atomic context. And connector freeing grabs all kinds of locks and stuff. Fix this by creating a specially safe put function for connetor_iter, which (in this rare case) punts the cleanup to a worker. Reported-by: Ben Widawsky Cc: Ben Widawsky Fixes: 613051dac40d ("drm: locking&new iterators for connector_list") Cc: Dave Airlie Cc: Chris Wilson Cc: Sean Paul Cc: # v4.11+ Reviewed-by: Dave Airlie Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171204204818.24745-1-daniel.vetter@ffwll.ch --- drivers/gpu/drm/drm_connector.c | 28 ++++++++++++++++++++++++++-- drivers/gpu/drm/drm_mode_config.c | 2 ++ include/drm/drm_connector.h | 8 ++++++++ 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index 25f4b2e9a44f..482014137953 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -152,6 +152,16 @@ static void drm_connector_free(struct kref *kref) connector->funcs->destroy(connector); } +static void drm_connector_free_work_fn(struct work_struct *work) +{ + struct drm_connector *connector = + container_of(work, struct drm_connector, free_work); + struct drm_device *dev = connector->dev; + + drm_mode_object_unregister(dev, &connector->base); + connector->funcs->destroy(connector); +} + /** * drm_connector_init - Init a preallocated connector * @dev: DRM device @@ -181,6 +191,8 @@ int drm_connector_init(struct drm_device *dev, if (ret) return ret; + INIT_WORK(&connector->free_work, drm_connector_free_work_fn); + connector->base.properties = &connector->properties; connector->dev = dev; connector->funcs = funcs; @@ -529,6 +541,18 @@ void drm_connector_list_iter_begin(struct drm_device *dev, } EXPORT_SYMBOL(drm_connector_list_iter_begin); +/* + * Extra-safe connector put function that works in any context. Should only be + * used from the connector_iter functions, where we never really expect to + * actually release the connector when dropping our final reference. + */ +static void +drm_connector_put_safe(struct drm_connector *conn) +{ + if (refcount_dec_and_test(&conn->base.refcount.refcount)) + schedule_work(&conn->free_work); +} + /** * drm_connector_list_iter_next - return next connector * @iter: connectr_list iterator @@ -561,7 +585,7 @@ drm_connector_list_iter_next(struct drm_connector_list_iter *iter) spin_unlock_irqrestore(&config->connector_list_lock, flags); if (old_conn) - drm_connector_put(old_conn); + drm_connector_put_safe(old_conn); return iter->conn; } @@ -580,7 +604,7 @@ void drm_connector_list_iter_end(struct drm_connector_list_iter *iter) { iter->dev = NULL; if (iter->conn) - drm_connector_put(iter->conn); + drm_connector_put_safe(iter->conn); lock_release(&connector_list_iter_dep_map, 0, _RET_IP_); } EXPORT_SYMBOL(drm_connector_list_iter_end); diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c index cda8bfab6d3b..cc78b3d9e5e4 100644 --- a/drivers/gpu/drm/drm_mode_config.c +++ b/drivers/gpu/drm/drm_mode_config.c @@ -431,6 +431,8 @@ void drm_mode_config_cleanup(struct drm_device *dev) drm_connector_put(connector); } drm_connector_list_iter_end(&conn_iter); + /* connector_iter drops references in a work item. */ + flush_scheduled_work(); if (WARN_ON(!list_empty(&dev->mode_config.connector_list))) { drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index df9807a3caae..a4649c56ca2f 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -916,6 +916,14 @@ struct drm_connector { uint8_t num_h_tile, num_v_tile; uint8_t tile_h_loc, tile_v_loc; uint16_t tile_h_size, tile_v_size; + + /** + * @free_work: + * + * Work used only by &drm_connector_iter to be able to clean up a + * connector from any context. + */ + struct work_struct free_work; }; #define obj_to_connector(x) container_of(x, struct drm_connector, base) -- GitLab From 7f6d2ecd3d7acaf205ea7b3e96f9ffc55b92298b Mon Sep 17 00:00:00 2001 From: David Lechner Date: Sun, 3 Dec 2017 19:54:41 -0600 Subject: [PATCH 0741/2547] eeprom: at24: change nvmem stride to 1 Trying to read the MAC address from an eeprom that has an offset that is not a multiple of 4 causes an error currently. Fix it by changing the nvmem stride to 1. Cc: stable@vger.kernel.org Signed-off-by: David Lechner [Bartosz: tweaked the commit message] Signed-off-by: Bartosz Golaszewski --- drivers/misc/eeprom/at24.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c index 20b4f26d30d7..4d63ac8a82e0 100644 --- a/drivers/misc/eeprom/at24.c +++ b/drivers/misc/eeprom/at24.c @@ -876,7 +876,7 @@ static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id) at24->nvmem_config.reg_read = at24_read; at24->nvmem_config.reg_write = at24_write; at24->nvmem_config.priv = at24; - at24->nvmem_config.stride = 4; + at24->nvmem_config.stride = 1; at24->nvmem_config.word_size = 1; at24->nvmem_config.size = chip.byte_len; -- GitLab From e3811a3f74bd1ad773667b78323f396166891f3a Mon Sep 17 00:00:00 2001 From: Rudolf Marek Date: Tue, 28 Nov 2017 22:01:06 +0100 Subject: [PATCH 0742/2547] x86/cpufeatures: Make X86_BUG_FXSAVE_LEAK detectable in CPUID on AMD The latest AMD AMD64 Architecture Programmer's Manual adds a CPUID feature XSaveErPtr (CPUID_Fn80000008_EBX[2]). If this feature is set, the FXSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES / FXRSTOR, XRSTOR, XRSTORS always save/restore error pointers, thus making the X86_BUG_FXSAVE_LEAK workaround obsolete on such CPUs. Signed-off-by: Rudolf Marek Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Tested-by: Borislav Petkov Cc: Andy Lutomirski Link: https://lkml.kernel.org/r/bdcebe90-62c5-1f05-083c-eba7f08b2540@assembler.cz Signed-off-by: Ingo Molnar --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/amd.c | 7 +++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index c0b0e9e8aa66..800104c8a3ed 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -266,6 +266,7 @@ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ +#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index d58184b7cd44..bcb75dc97d44 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -804,8 +804,11 @@ static void init_amd(struct cpuinfo_x86 *c) case 0x17: init_amd_zn(c); break; } - /* Enable workaround for FXSAVE leak */ - if (c->x86 >= 6) + /* + * Enable workaround for FXSAVE leak on CPUs + * without a XSaveErPtr feature + */ + if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); cpu_detect_cache_sizes(c); -- GitLab From f4e9b7af0cd58dd039a0fb2cd67d57cea4889abf Mon Sep 17 00:00:00 2001 From: Tom Lendacky Date: Thu, 30 Nov 2017 16:46:40 -0600 Subject: [PATCH 0743/2547] x86/microcode/AMD: Add support for fam17h microcode loading The size for the Microcode Patch Block (MPB) for an AMD family 17h processor is 3200 bytes. Add a #define for fam17h so that it does not default to 2048 bytes and fail a microcode load/update. Signed-off-by: Tom Lendacky Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Link: https://lkml.kernel.org/r/20171130224640.15391.40247.stgit@tlendack-t1.amdoffice.net Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/microcode/amd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index c6daec4bdba5..330b8462d426 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -470,6 +470,7 @@ static unsigned int verify_patch_size(u8 family, u32 patch_size, #define F14H_MPB_MAX_SIZE 1824 #define F15H_MPB_MAX_SIZE 4096 #define F16H_MPB_MAX_SIZE 3458 +#define F17H_MPB_MAX_SIZE 3200 switch (family) { case 0x14: @@ -481,6 +482,9 @@ static unsigned int verify_patch_size(u8 family, u32 patch_size, case 0x16: max_size = F16H_MPB_MAX_SIZE; break; + case 0x17: + max_size = F17H_MPB_MAX_SIZE; + break; default: max_size = F1XH_MPB_MAX_SIZE; break; -- GitLab From ddec3bdee05b06f1dda20ded003c3e10e4184cab Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Fri, 1 Dec 2017 15:08:12 +0100 Subject: [PATCH 0744/2547] x86/PCI: Make broadcom_postcore_init() check acpi_disabled acpi_os_get_root_pointer() may return a valid address even if acpi_disabled is set, but the host bridge information from the ACPI tables is not going to be used in that case and the Broadcom host bridge initialization should not be skipped then, So make broadcom_postcore_init() check acpi_disabled too to avoid this issue. Fixes: 6361d72b04d1 (x86/PCI: read Broadcom CNB20LE host bridge info before PCI scan) Reported-by: Dave Hansen Signed-off-by: Rafael J. Wysocki Signed-off-by: Thomas Gleixner Cc: Bjorn Helgaas Cc: Linux PCI Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/3186627.pxZj1QbYNg@aspire.rjw.lan Signed-off-by: Ingo Molnar --- arch/x86/pci/broadcom_bus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/pci/broadcom_bus.c b/arch/x86/pci/broadcom_bus.c index bb461cfd01ab..526536c81ddc 100644 --- a/arch/x86/pci/broadcom_bus.c +++ b/arch/x86/pci/broadcom_bus.c @@ -97,7 +97,7 @@ static int __init broadcom_postcore_init(void) * We should get host bridge information from ACPI unless the BIOS * doesn't support it. */ - if (acpi_os_get_root_pointer()) + if (!acpi_disabled && acpi_os_get_root_pointer()) return 0; #endif -- GitLab From 5b06bbcfc2c621da3009da8decb7511500c293ed Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Thu, 30 Nov 2017 07:57:57 -0800 Subject: [PATCH 0745/2547] x86/power: Fix some ordering bugs in __restore_processor_context() __restore_processor_context() had a couple of ordering bugs. It restored GSBASE after calling load_gs_index(), and the latter can call into tracing code. It also tried to restore segment registers before restoring the LDT, which is straight-up wrong. Reorder the code so that we restore GSBASE, then the descriptor tables, then the segments. This fixes two bugs. First, it fixes a regression that broke resume under certain configurations due to irqflag tracing in native_load_gs_index(). Second, it fixes resume when the userspace process that initiated suspect had funny segments. The latter can be reproduced by compiling this: // SPDX-License-Identifier: GPL-2.0 /* * ldt_echo.c - Echo argv[1] while using an LDT segment */ int main(int argc, char **argv) { int ret; size_t len; char *buf; const struct user_desc desc = { .entry_number = 0, .base_addr = 0, .limit = 0xfffff, .seg_32bit = 1, .contents = 0, /* Data, grow-up */ .read_exec_only = 0, .limit_in_pages = 1, .seg_not_present = 0, .useable = 0 }; if (argc != 2) errx(1, "Usage: %s STRING", argv[0]); len = asprintf(&buf, "%s\n", argv[1]); if (len < 0) errx(1, "Out of memory"); ret = syscall(SYS_modify_ldt, 1, &desc, sizeof(desc)); if (ret < -1) errno = -ret; if (ret) err(1, "modify_ldt"); asm volatile ("movw %0, %%es" :: "rm" ((unsigned short)7)); write(1, buf, len); return 0; } and running ldt_echo >/sys/power/mem Without the fix, the latter causes a triple fault on resume. Fixes: ca37e57bbe0c ("x86/entry/64: Add missing irqflags tracing to native_load_gs_index()") Reported-by: Jarkko Nikula Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Tested-by: Jarkko Nikula Cc: Peter Zijlstra Cc: Borislav Petkov Cc: Linus Torvalds Link: https://lkml.kernel.org/r/6b31721ea92f51ea839e79bd97ade4a75b1eeea2.1512057304.git.luto@kernel.org Signed-off-by: Ingo Molnar --- arch/x86/power/cpu.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index 84fcfde53f8f..5191de14f4df 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -226,8 +226,20 @@ static void notrace __restore_processor_state(struct saved_context *ctxt) load_idt((const struct desc_ptr *)&ctxt->idt_limit); #endif +#ifdef CONFIG_X86_64 /* - * segment registers + * We need GSBASE restored before percpu access can work. + * percpu access can happen in exception handlers or in complicated + * helpers like load_gs_index(). + */ + wrmsrl(MSR_GS_BASE, ctxt->gs_base); +#endif + + fix_processor_context(); + + /* + * Restore segment registers. This happens after restoring the GDT + * and LDT, which happen in fix_processor_context(). */ #ifdef CONFIG_X86_32 loadsegment(es, ctxt->es); @@ -248,13 +260,14 @@ static void notrace __restore_processor_state(struct saved_context *ctxt) load_gs_index(ctxt->gs); asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss)); + /* + * Restore FSBASE and user GSBASE after reloading the respective + * segment selectors. + */ wrmsrl(MSR_FS_BASE, ctxt->fs_base); - wrmsrl(MSR_GS_BASE, ctxt->gs_base); wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); #endif - fix_processor_context(); - do_fpu_end(); tsc_verify_tsc_adjust(true); x86_platform.restore_sched_clock_state(); -- GitLab From 371b80447ff33ddac392c189cf884a5a3e18faeb Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Wed, 6 Dec 2017 18:21:14 +1000 Subject: [PATCH 0746/2547] powerpc/64s: Initialize ISAv3 MMU registers before setting partition table kexec can leave MMU registers set when booting into a new kernel, the PIDR (Process Identification Register) in particular. The boot sequence does not zero PIDR, so it only gets set when CPUs first switch to a userspace processes (until then it's running a kernel thread with effective PID = 0). This leaves a window where a process table entry and page tables are set up due to user processes running on other CPUs, that happen to match with a stale PID. The CPU with that PID may cause speculative accesses that address quadrant 0 (aka userspace addresses), which will result in cached translations and PWC (Page Walk Cache) for that process, on a CPU which is not in the mm_cpumask and so they will not be invalidated properly. The most common result is the kernel hanging in infinite page fault loops soon after kexec (usually in schedule_tail, which is usually the first non-speculative quadrant 0 access to a new PID) due to a stale PWC. However being a stale translation error, it could result in anything up to security and data corruption problems. Fix this by zeroing out PIDR at boot and kexec. Fixes: 7e381c0ff618 ("powerpc/mm/radix: Add mmu context handling callback for radix") Cc: stable@vger.kernel.org # v4.7+ Signed-off-by: Nicholas Piggin Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/cpu_setup_power.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index 610955fe8b81..679bbe714e85 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -102,6 +102,7 @@ _GLOBAL(__setup_cpu_power9) li r0,0 mtspr SPRN_PSSCR,r0 mtspr SPRN_LPID,r0 + mtspr SPRN_PID,r0 mfspr r3,SPRN_LPCR LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC) or r3, r3, r4 @@ -126,6 +127,7 @@ _GLOBAL(__restore_cpu_power9) li r0,0 mtspr SPRN_PSSCR,r0 mtspr SPRN_LPID,r0 + mtspr SPRN_PID,r0 mfspr r3,SPRN_LPCR LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC) or r3, r3, r4 -- GitLab From cfe17c9bbe6a673fdafdab179c32b355ed447f66 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 27 Nov 2017 21:15:13 +0900 Subject: [PATCH 0747/2547] kbuild: move cc-option and cc-disable-warning after incl. arch Makefile Geert reported commit ae6b289a3789 ("kbuild: Set KBUILD_CFLAGS before incl. arch Makefile") broke cross-compilation using a cross-compiler that supports less compiler options than the host compiler. For example, cc1: error: unrecognized command line option "-Wno-unused-but-set-variable" This problem happens on architectures that setup CROSS_COMPILE in their arch/*/Makefile. Move the cc-option and cc-disable-warning back to the original position, but keep the Clang target options untouched. Fixes: ae6b289a3789 ("kbuild: Set KBUILD_CFLAGS before incl. arch Makefile") Reported-by: Geert Uytterhoeven Signed-off-by: Masahiro Yamada Tested-by: Geert Uytterhoeven --- Makefile | 43 +++++++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/Makefile b/Makefile index c988e46a53cd..477c4cf01cae 100644 --- a/Makefile +++ b/Makefile @@ -484,26 +484,6 @@ CLANG_GCC_TC := --gcc-toolchain=$(GCC_TOOLCHAIN) endif KBUILD_CFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC) KBUILD_AFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC) -KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,) -KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable) -KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier) -KBUILD_CFLAGS += $(call cc-disable-warning, gnu) -KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member) -# Quiet clang warning: comparison of unsigned expression < 0 is always false -KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare) -# CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the -# source of a reference will be _MergedGlobals and not on of the whitelisted names. -# See modpost pattern 2 -KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,) -KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior) -KBUILD_CFLAGS += $(call cc-option, -no-integrated-as) -KBUILD_AFLAGS += $(call cc-option, -no-integrated-as) -else - -# These warnings generated too much noise in a regular build. -# Use make W=1 to enable them (see scripts/Makefile.extrawarn) -KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable) -KBUILD_CFLAGS += $(call cc-disable-warning, unused-const-variable) endif ifeq ($(config-targets),1) @@ -716,6 +696,29 @@ ifdef CONFIG_CC_STACKPROTECTOR endif KBUILD_CFLAGS += $(stackp-flag) +ifeq ($(cc-name),clang) +KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,) +KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable) +KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier) +KBUILD_CFLAGS += $(call cc-disable-warning, gnu) +KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member) +# Quiet clang warning: comparison of unsigned expression < 0 is always false +KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare) +# CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the +# source of a reference will be _MergedGlobals and not on of the whitelisted names. +# See modpost pattern 2 +KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,) +KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior) +KBUILD_CFLAGS += $(call cc-option, -no-integrated-as) +KBUILD_AFLAGS += $(call cc-option, -no-integrated-as) +else + +# These warnings generated too much noise in a regular build. +# Use make W=1 to enable them (see scripts/Makefile.extrawarn) +KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable) +KBUILD_CFLAGS += $(call cc-disable-warning, unused-const-variable) +endif + ifdef CONFIG_FRAME_POINTER KBUILD_CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls else -- GitLab From 4f7f5551a760eb0124267be65763008169db7087 Mon Sep 17 00:00:00 2001 From: Masamitsu Yamazaki Date: Wed, 15 Nov 2017 07:33:14 +0000 Subject: [PATCH 0748/2547] ipmi: Stop timers before cleaning up the module System may crash after unloading ipmi_si.ko module because a timer may remain and fire after the module cleaned up resources. cleanup_one_si() contains the following processing. /* * Make sure that interrupts, the timer and the thread are * stopped and will not run again. */ if (to_clean->irq_cleanup) to_clean->irq_cleanup(to_clean); wait_for_timer_and_thread(to_clean); /* * Timeouts are stopped, now make sure the interrupts are off * in the BMC. Note that timers and CPU interrupts are off, * so no need for locks. */ while (to_clean->curr_msg || (to_clean->si_state != SI_NORMAL)) { poll(to_clean); schedule_timeout_uninterruptible(1); } si_state changes as following in the while loop calling poll(to_clean). SI_GETTING_MESSAGES => SI_CHECKING_ENABLES => SI_SETTING_ENABLES => SI_GETTING_EVENTS => SI_NORMAL As written in the code comments above, timers are expected to stop before the polling loop and not to run again. But the timer is set again in the following process when si_state becomes SI_SETTING_ENABLES. => poll => smi_event_handler => handle_transaction_done // smi_info->si_state == SI_SETTING_ENABLES => start_getting_events => start_new_msg => smi_mod_timer => mod_timer As a result, before the timer set in start_new_msg() expires, the polling loop may see si_state becoming SI_NORMAL and the module clean-up finishes. For example, hard LOCKUP and panic occurred as following. smi_timeout was called after smi_event_handler, kcs_event and hangs at port_inb() trying to access I/O port after release. [exception RIP: port_inb+19] RIP: ffffffffc0473053 RSP: ffff88069fdc3d80 RFLAGS: 00000006 RAX: ffff8806800f8e00 RBX: ffff880682bd9400 RCX: 0000000000000000 RDX: 0000000000000ca3 RSI: 0000000000000ca3 RDI: ffff8806800f8e40 RBP: ffff88069fdc3d80 R8: ffffffff81d86dfc R9: ffffffff81e36426 R10: 00000000000509f0 R11: 0000000000100000 R12: 0000000000]:000000 R13: 0000000000000000 R14: 0000000000000246 R15: ffff8806800f8e00 ORIG_RAX: ffffffffffffffff CS: 0010 SS: 0000 --- --- To fix the problem I defined a flag, timer_can_start, as member of struct smi_info. The flag is enabled immediately after initializing the timer and disabled immediately before waiting for timer deletion. Fixes: 0cfec916e86d ("ipmi: Start the timer and thread on internal msgs") Signed-off-by: Yamazaki Masamitsu [Adjusted for recent changes in the driver.] Signed-off-by: Corey Minyard --- drivers/char/ipmi/ipmi_si_intf.c | 44 +++++++++++++++++--------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c index 71d33a1807e4..99b0513bb55b 100644 --- a/drivers/char/ipmi/ipmi_si_intf.c +++ b/drivers/char/ipmi/ipmi_si_intf.c @@ -199,6 +199,9 @@ struct smi_info { /* The timer for this si. */ struct timer_list si_timer; + /* This flag is set, if the timer can be set */ + bool timer_can_start; + /* This flag is set, if the timer is running (timer_pending() isn't enough) */ bool timer_running; @@ -355,6 +358,8 @@ static enum si_sm_result start_next_msg(struct smi_info *smi_info) static void smi_mod_timer(struct smi_info *smi_info, unsigned long new_val) { + if (!smi_info->timer_can_start) + return; smi_info->last_timeout_jiffies = jiffies; mod_timer(&smi_info->si_timer, new_val); smi_info->timer_running = true; @@ -374,21 +379,18 @@ static void start_new_msg(struct smi_info *smi_info, unsigned char *msg, smi_info->handlers->start_transaction(smi_info->si_sm, msg, size); } -static void start_check_enables(struct smi_info *smi_info, bool start_timer) +static void start_check_enables(struct smi_info *smi_info) { unsigned char msg[2]; msg[0] = (IPMI_NETFN_APP_REQUEST << 2); msg[1] = IPMI_GET_BMC_GLOBAL_ENABLES_CMD; - if (start_timer) - start_new_msg(smi_info, msg, 2); - else - smi_info->handlers->start_transaction(smi_info->si_sm, msg, 2); + start_new_msg(smi_info, msg, 2); smi_info->si_state = SI_CHECKING_ENABLES; } -static void start_clear_flags(struct smi_info *smi_info, bool start_timer) +static void start_clear_flags(struct smi_info *smi_info) { unsigned char msg[3]; @@ -397,10 +399,7 @@ static void start_clear_flags(struct smi_info *smi_info, bool start_timer) msg[1] = IPMI_CLEAR_MSG_FLAGS_CMD; msg[2] = WDT_PRE_TIMEOUT_INT; - if (start_timer) - start_new_msg(smi_info, msg, 3); - else - smi_info->handlers->start_transaction(smi_info->si_sm, msg, 3); + start_new_msg(smi_info, msg, 3); smi_info->si_state = SI_CLEARING_FLAGS; } @@ -435,11 +434,11 @@ static void start_getting_events(struct smi_info *smi_info) * Note that we cannot just use disable_irq(), since the interrupt may * be shared. */ -static inline bool disable_si_irq(struct smi_info *smi_info, bool start_timer) +static inline bool disable_si_irq(struct smi_info *smi_info) { if ((smi_info->io.irq) && (!smi_info->interrupt_disabled)) { smi_info->interrupt_disabled = true; - start_check_enables(smi_info, start_timer); + start_check_enables(smi_info); return true; } return false; @@ -449,7 +448,7 @@ static inline bool enable_si_irq(struct smi_info *smi_info) { if ((smi_info->io.irq) && (smi_info->interrupt_disabled)) { smi_info->interrupt_disabled = false; - start_check_enables(smi_info, true); + start_check_enables(smi_info); return true; } return false; @@ -467,7 +466,7 @@ static struct ipmi_smi_msg *alloc_msg_handle_irq(struct smi_info *smi_info) msg = ipmi_alloc_smi_msg(); if (!msg) { - if (!disable_si_irq(smi_info, true)) + if (!disable_si_irq(smi_info)) smi_info->si_state = SI_NORMAL; } else if (enable_si_irq(smi_info)) { ipmi_free_smi_msg(msg); @@ -483,7 +482,7 @@ static void handle_flags(struct smi_info *smi_info) /* Watchdog pre-timeout */ smi_inc_stat(smi_info, watchdog_pretimeouts); - start_clear_flags(smi_info, true); + start_clear_flags(smi_info); smi_info->msg_flags &= ~WDT_PRE_TIMEOUT_INT; if (smi_info->intf) ipmi_smi_watchdog_pretimeout(smi_info->intf); @@ -866,7 +865,7 @@ static enum si_sm_result smi_event_handler(struct smi_info *smi_info, * disable and messages disabled. */ if (smi_info->supports_event_msg_buff || smi_info->io.irq) { - start_check_enables(smi_info, true); + start_check_enables(smi_info); } else { smi_info->curr_msg = alloc_msg_handle_irq(smi_info); if (!smi_info->curr_msg) @@ -1167,6 +1166,7 @@ static int smi_start_processing(void *send_info, /* Set up the timer that drives the interface. */ setup_timer(&new_smi->si_timer, smi_timeout, (long)new_smi); + new_smi->timer_can_start = true; smi_mod_timer(new_smi, jiffies + SI_TIMEOUT_JIFFIES); /* Try to claim any interrupts. */ @@ -1936,10 +1936,12 @@ static void check_for_broken_irqs(struct smi_info *smi_info) check_set_rcv_irq(smi_info); } -static inline void wait_for_timer_and_thread(struct smi_info *smi_info) +static inline void stop_timer_and_thread(struct smi_info *smi_info) { if (smi_info->thread != NULL) kthread_stop(smi_info->thread); + + smi_info->timer_can_start = false; if (smi_info->timer_running) del_timer_sync(&smi_info->si_timer); } @@ -2152,7 +2154,7 @@ static int try_smi_init(struct smi_info *new_smi) * Start clearing the flags before we enable interrupts or the * timer to avoid racing with the timer. */ - start_clear_flags(new_smi, false); + start_clear_flags(new_smi); /* * IRQ is defined to be set when non-zero. req_events will @@ -2238,7 +2240,7 @@ static int try_smi_init(struct smi_info *new_smi) dev_set_drvdata(new_smi->io.dev, NULL); out_err_stop_timer: - wait_for_timer_and_thread(new_smi); + stop_timer_and_thread(new_smi); out_err: new_smi->interrupt_disabled = true; @@ -2388,7 +2390,7 @@ static void cleanup_one_si(struct smi_info *to_clean) */ if (to_clean->io.irq_cleanup) to_clean->io.irq_cleanup(&to_clean->io); - wait_for_timer_and_thread(to_clean); + stop_timer_and_thread(to_clean); /* * Timeouts are stopped, now make sure the interrupts are off @@ -2400,7 +2402,7 @@ static void cleanup_one_si(struct smi_info *to_clean) schedule_timeout_uninterruptible(1); } if (to_clean->handlers) - disable_si_irq(to_clean, false); + disable_si_irq(to_clean); while (to_clean->curr_msg || (to_clean->si_state != SI_NORMAL)) { poll(to_clean); schedule_timeout_uninterruptible(1); -- GitLab From d8104182087319fd753d6d8e0afcd95d84c2aa2f Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Wed, 6 Dec 2017 23:23:28 +1100 Subject: [PATCH 0749/2547] powerpc/xmon: Don't print hashed pointers in xmon Since commit ad67b74d2469 ("printk: hash addresses printed with %p") pointers printed with %p are hashed, ie. you don't see the actual pointer value but rather a cryptographic hash of its value. In xmon we want to see the actual pointer values, because xmon is a debugger, so replace %p with %px which prints the actual pointer value. We justify doing this in xmon because 1) xmon is a kernel crash debugger, it's only accessible via the console 2) xmon doesn't print to dmesg, so the pointers it prints are not able to be leaked that way. Signed-off-by: Michael Ellerman --- arch/powerpc/xmon/xmon.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index 1b2d8cb49abb..cab24f549e7c 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -1590,7 +1590,7 @@ static void print_bug_trap(struct pt_regs *regs) printf("kernel BUG at %s:%u!\n", bug->file, bug->line); #else - printf("kernel BUG at %p!\n", (void *)bug->bug_addr); + printf("kernel BUG at %px!\n", (void *)bug->bug_addr); #endif #endif /* CONFIG_BUG */ } @@ -2329,7 +2329,7 @@ static void dump_one_paca(int cpu) p = &paca[cpu]; - printf("paca for cpu 0x%x @ %p:\n", cpu, p); + printf("paca for cpu 0x%x @ %px:\n", cpu, p); printf(" %-*s = %s\n", 20, "possible", cpu_possible(cpu) ? "yes" : "no"); printf(" %-*s = %s\n", 20, "present", cpu_present(cpu) ? "yes" : "no"); @@ -2945,7 +2945,7 @@ static void show_task(struct task_struct *tsk) (tsk->exit_state & EXIT_DEAD) ? 'E' : (tsk->state & TASK_INTERRUPTIBLE) ? 'S' : '?'; - printf("%p %016lx %6d %6d %c %2d %s\n", tsk, + printf("%px %016lx %6d %6d %c %2d %s\n", tsk, tsk->thread.ksp, tsk->pid, tsk->parent->pid, state, task_thread_info(tsk)->cpu, @@ -2988,7 +2988,7 @@ static void show_pte(unsigned long addr) if (setjmp(bus_error_jmp) != 0) { catch_memory_errors = 0; - printf("*** Error dumping pte for task %p\n", tsk); + printf("*** Error dumping pte for task %px\n", tsk); return; } @@ -3074,7 +3074,7 @@ static void show_tasks(void) if (setjmp(bus_error_jmp) != 0) { catch_memory_errors = 0; - printf("*** Error dumping task %p\n", tsk); + printf("*** Error dumping task %px\n", tsk); return; } -- GitLab From e60bb46b5754727c7643cc5bb7b005c49f869930 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 4 Dec 2017 11:26:14 +0100 Subject: [PATCH 0750/2547] drm/ttm: swap consecutive allocated pooled pages v4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When we detect consecutive allocation of pages swap them to avoid accidentally freeing them as huge page. v2: use swap v3: check if it's really the first allocated page v4: don't touch the loop variable Signed-off-by: Christian König Reviewed-by: Roger He Reviewed-by: Michel Dänzer Tested-by: Dieter Nützel Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index b6f7ce286fb1..44343a2bf55c 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -958,8 +958,15 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, r = ttm_page_pool_get_pages(pool, &plist, flags, cstate, npages - count, 0); - list_for_each_entry(p, &plist, lru) - pages[count++] = p; + first = count; + list_for_each_entry(p, &plist, lru) { + struct page *tmp = p; + + /* Swap the pages if we detect consecutive order */ + if (count > first && pages[count - 1] == tmp - 1) + swap(tmp, pages[count - 1]); + pages[count++] = tmp; + } if (r) { /* If there is any pages in the list put them back to -- GitLab From 2fe2d4e386f48e7cd91adea65156beeaa92d8fe7 Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Wed, 6 Dec 2017 13:53:10 +0000 Subject: [PATCH 0751/2547] drm/i915/huc: Move firmware selection to init_early Doing HuC firmware path selection from sanitize_options function is not perfect, while there is no problem with doing so during early init stage as we already have all needed data. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Sagar Arun Kamble Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171206135316.32556-1-michal.wajdeczko@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/intel_huc.c | 60 ++++++++++++++++++++------------ drivers/gpu/drm/i915/intel_huc.h | 2 +- drivers/gpu/drm/i915/intel_uc.c | 4 +-- 4 files changed, 42 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 594fd14e66c5..bd4eea51c9ed 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3234,6 +3234,9 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct) #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) + +/* For now, anything with a GuC has also HuC */ +#define HAS_HUC(dev_priv) (HAS_GUC(dev_priv)) #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c index 98d17254593c..6d0e050ab7d9 100644 --- a/drivers/gpu/drm/i915/intel_huc.c +++ b/drivers/gpu/drm/i915/intel_huc.c @@ -77,42 +77,56 @@ MODULE_FIRMWARE(I915_KBL_HUC_UCODE); #define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \ GLK_HUC_FW_MINOR, GLK_BLD_NUM) -/** - * intel_huc_select_fw() - selects HuC firmware for loading - * @huc: intel_huc struct - */ -void intel_huc_select_fw(struct intel_huc *huc) +static void huc_fw_select(struct intel_uc_fw *huc_fw) { + struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw); struct drm_i915_private *dev_priv = huc_to_i915(huc); - intel_uc_fw_init(&huc->fw, INTEL_UC_FW_TYPE_HUC); + GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC); + + if (!HAS_HUC(dev_priv)) + return; if (i915_modparams.huc_firmware_path) { - huc->fw.path = i915_modparams.huc_firmware_path; - huc->fw.major_ver_wanted = 0; - huc->fw.minor_ver_wanted = 0; + huc_fw->path = i915_modparams.huc_firmware_path; + huc_fw->major_ver_wanted = 0; + huc_fw->minor_ver_wanted = 0; } else if (IS_SKYLAKE(dev_priv)) { - huc->fw.path = I915_SKL_HUC_UCODE; - huc->fw.major_ver_wanted = SKL_HUC_FW_MAJOR; - huc->fw.minor_ver_wanted = SKL_HUC_FW_MINOR; + huc_fw->path = I915_SKL_HUC_UCODE; + huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR; + huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR; } else if (IS_BROXTON(dev_priv)) { - huc->fw.path = I915_BXT_HUC_UCODE; - huc->fw.major_ver_wanted = BXT_HUC_FW_MAJOR; - huc->fw.minor_ver_wanted = BXT_HUC_FW_MINOR; + huc_fw->path = I915_BXT_HUC_UCODE; + huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR; + huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR; } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { - huc->fw.path = I915_KBL_HUC_UCODE; - huc->fw.major_ver_wanted = KBL_HUC_FW_MAJOR; - huc->fw.minor_ver_wanted = KBL_HUC_FW_MINOR; + huc_fw->path = I915_KBL_HUC_UCODE; + huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR; + huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR; } else if (IS_GEMINILAKE(dev_priv)) { - huc->fw.path = I915_GLK_HUC_UCODE; - huc->fw.major_ver_wanted = GLK_HUC_FW_MAJOR; - huc->fw.minor_ver_wanted = GLK_HUC_FW_MINOR; + huc_fw->path = I915_GLK_HUC_UCODE; + huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR; + huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR; } else { - DRM_ERROR("No HuC firmware known for platform with HuC!\n"); - return; + DRM_WARN("%s: No firmware known for this platform!\n", + intel_uc_fw_type_repr(huc_fw->type)); } } +/** + * intel_huc_init_early() - initializes HuC struct + * @huc: intel_huc struct + * + * On platforms with HuC selects firmware for uploading + */ +void intel_huc_init_early(struct intel_huc *huc) +{ + struct intel_uc_fw *huc_fw = &huc->fw; + + intel_uc_fw_init(huc_fw, INTEL_UC_FW_TYPE_HUC); + huc_fw_select(huc_fw); +} + /** * huc_ucode_xfer() - DMA's the firmware * @dev_priv: the drm_i915_private device diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h index aaa38b9e5817..3d757bce9ce3 100644 --- a/drivers/gpu/drm/i915/intel_huc.h +++ b/drivers/gpu/drm/i915/intel_huc.h @@ -34,7 +34,7 @@ struct intel_huc { /* HuC-specific additions */ }; -void intel_huc_select_fw(struct intel_huc *huc); +void intel_huc_init_early(struct intel_huc *huc); void intel_huc_init_hw(struct intel_huc *huc); void intel_huc_auth(struct intel_huc *huc); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 1e2a30a40ede..95b524c9f8f3 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -65,9 +65,6 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv) /* Verify firmware version */ if (i915_modparams.enable_guc_loading) { - if (HAS_HUC_UCODE(dev_priv)) - intel_huc_select_fw(&dev_priv->huc); - if (intel_guc_fw_select(&dev_priv->guc)) i915_modparams.enable_guc_loading = 0; } @@ -84,6 +81,7 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv) void intel_uc_init_early(struct drm_i915_private *dev_priv) { intel_guc_init_early(&dev_priv->guc); + intel_huc_init_early(&dev_priv->huc); } void intel_uc_init_fw(struct drm_i915_private *dev_priv) -- GitLab From 0dd940c8cec444d1864788b654280f96863f6d73 Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Wed, 6 Dec 2017 13:53:11 +0000 Subject: [PATCH 0752/2547] drm/i915/guc: Move firmware selection to init_early Doing GuC firmware path selection from sanitize_options function is not perfect, while there is no problem with doing so during early init stage as we already have all needed data. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Sagar Arun Kamble Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171206135316.32556-2-michal.wajdeczko@intel.com --- drivers/gpu/drm/i915/intel_guc.c | 1 + drivers/gpu/drm/i915/intel_guc_fw.c | 63 ++++++++++++++++------------- drivers/gpu/drm/i915/intel_guc_fw.h | 2 +- drivers/gpu/drm/i915/intel_uc.c | 2 +- drivers/gpu/drm/i915/intel_uc_fw.h | 5 +++ 5 files changed, 44 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index d08e760252d4..df8690738369 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -61,6 +61,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc) void intel_guc_init_early(struct intel_guc *guc) { + intel_guc_fw_init_early(guc); intel_guc_ct_init_early(&guc->ct); mutex_init(&guc->send_mutex); diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index 89862fa8ab42..cbc51c960425 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -56,45 +56,54 @@ MODULE_FIRMWARE(I915_KBL_GUC_UCODE); #define I915_GLK_GUC_UCODE GUC_FW_PATH(glk, GLK_FW_MAJOR, GLK_FW_MINOR) -/** - * intel_guc_fw_select() - selects GuC firmware for uploading - * - * @guc: intel_guc struct - * - * Return: zero when we know firmware, non-zero in other case - */ -int intel_guc_fw_select(struct intel_guc *guc) +static void guc_fw_select(struct intel_uc_fw *guc_fw) { + struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw); struct drm_i915_private *dev_priv = guc_to_i915(guc); - intel_uc_fw_init(&guc->fw, INTEL_UC_FW_TYPE_GUC); + GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC); + + if (!HAS_GUC(dev_priv)) + return; if (i915_modparams.guc_firmware_path) { - guc->fw.path = i915_modparams.guc_firmware_path; - guc->fw.major_ver_wanted = 0; - guc->fw.minor_ver_wanted = 0; + guc_fw->path = i915_modparams.guc_firmware_path; + guc_fw->major_ver_wanted = 0; + guc_fw->minor_ver_wanted = 0; } else if (IS_SKYLAKE(dev_priv)) { - guc->fw.path = I915_SKL_GUC_UCODE; - guc->fw.major_ver_wanted = SKL_FW_MAJOR; - guc->fw.minor_ver_wanted = SKL_FW_MINOR; + guc_fw->path = I915_SKL_GUC_UCODE; + guc_fw->major_ver_wanted = SKL_FW_MAJOR; + guc_fw->minor_ver_wanted = SKL_FW_MINOR; } else if (IS_BROXTON(dev_priv)) { - guc->fw.path = I915_BXT_GUC_UCODE; - guc->fw.major_ver_wanted = BXT_FW_MAJOR; - guc->fw.minor_ver_wanted = BXT_FW_MINOR; + guc_fw->path = I915_BXT_GUC_UCODE; + guc_fw->major_ver_wanted = BXT_FW_MAJOR; + guc_fw->minor_ver_wanted = BXT_FW_MINOR; } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { - guc->fw.path = I915_KBL_GUC_UCODE; - guc->fw.major_ver_wanted = KBL_FW_MAJOR; - guc->fw.minor_ver_wanted = KBL_FW_MINOR; + guc_fw->path = I915_KBL_GUC_UCODE; + guc_fw->major_ver_wanted = KBL_FW_MAJOR; + guc_fw->minor_ver_wanted = KBL_FW_MINOR; } else if (IS_GEMINILAKE(dev_priv)) { - guc->fw.path = I915_GLK_GUC_UCODE; - guc->fw.major_ver_wanted = GLK_FW_MAJOR; - guc->fw.minor_ver_wanted = GLK_FW_MINOR; + guc_fw->path = I915_GLK_GUC_UCODE; + guc_fw->major_ver_wanted = GLK_FW_MAJOR; + guc_fw->minor_ver_wanted = GLK_FW_MINOR; } else { - DRM_ERROR("No GuC firmware known for platform with GuC!\n"); - return -ENOENT; + DRM_WARN("%s: No firmware known for this platform!\n", + intel_uc_fw_type_repr(guc_fw->type)); } +} - return 0; +/** + * intel_guc_fw_init_early() - initializes GuC firmware struct + * @guc: intel_guc struct + * + * On platforms with GuC selects firmware for uploading + */ +void intel_guc_fw_init_early(struct intel_guc *guc) +{ + struct intel_uc_fw *guc_fw = &guc->fw; + + intel_uc_fw_init(guc_fw, INTEL_UC_FW_TYPE_GUC); + guc_fw_select(guc_fw); } static void guc_prepare_xfer(struct intel_guc *guc) diff --git a/drivers/gpu/drm/i915/intel_guc_fw.h b/drivers/gpu/drm/i915/intel_guc_fw.h index 023f5baa9dd6..4ec5d3d9e2b0 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.h +++ b/drivers/gpu/drm/i915/intel_guc_fw.h @@ -27,7 +27,7 @@ struct intel_guc; -int intel_guc_fw_select(struct intel_guc *guc); +void intel_guc_fw_init_early(struct intel_guc *guc); int intel_guc_fw_upload(struct intel_guc *guc); #endif diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 95b524c9f8f3..4b7f2a78b378 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -65,7 +65,7 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv) /* Verify firmware version */ if (i915_modparams.enable_guc_loading) { - if (intel_guc_fw_select(&dev_priv->guc)) + if (!intel_uc_fw_is_selected(&dev_priv->guc.fw)) i915_modparams.enable_guc_loading = 0; } diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h index 5394d9d1e683..d5fd4609c785 100644 --- a/drivers/gpu/drm/i915/intel_uc_fw.h +++ b/drivers/gpu/drm/i915/intel_uc_fw.h @@ -110,6 +110,11 @@ void intel_uc_fw_init(struct intel_uc_fw *uc_fw, enum intel_uc_fw_type type) uc_fw->type = type; } +static inline bool intel_uc_fw_is_selected(struct intel_uc_fw *uc_fw) +{ + return uc_fw->path != NULL; +} + void intel_uc_fw_fetch(struct drm_i915_private *dev_priv, struct intel_uc_fw *uc_fw); int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, -- GitLab From 93ffbe8e9dc744f25cbdb941543030ab8de1d8f5 Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Wed, 6 Dec 2017 13:53:12 +0000 Subject: [PATCH 0753/2547] drm/i915/guc: Introduce USES_GUC_xxx helper macros In the upcoming patch we will change the way how to recognize when GuC is in use. Using helper macros will minimize scope of that changes. While here, update dev_info message. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Sagar Arun Kamble Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171206135316.32556-3-michal.wajdeczko@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 4 ++++ drivers/gpu/drm/i915/i915_gem_context.c | 4 ++-- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- drivers/gpu/drm/i915/i915_irq.c | 2 +- drivers/gpu/drm/i915/intel_guc.c | 2 +- drivers/gpu/drm/i915/intel_guc_log.c | 6 +++--- drivers/gpu/drm/i915/intel_gvt.c | 2 +- drivers/gpu/drm/i915/intel_uc.c | 23 +++++++++++----------- drivers/gpu/drm/i915/selftests/intel_guc.c | 2 +- 9 files changed, 25 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index bd4eea51c9ed..937fa02300e3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3239,6 +3239,10 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv)) #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) +/* Having a GuC is not the same as using a GuC */ +#define USES_GUC(dev_priv) (i915_modparams.enable_guc_loading) +#define USES_GUC_SUBMISSION(dev_priv) (i915_modparams.enable_guc_submission) + #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index ce3139e5ec4c..21ce374d9924 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -316,7 +316,7 @@ __create_hw_context(struct drm_i915_private *dev_priv, * present or not in use we still need a small bias as ring wraparound * at offset 0 sometimes hangs. No idea why. */ - if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) + if (USES_GUC(dev_priv)) ctx->ggtt_offset_bias = GUC_WOPCM_TOP; else ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE; @@ -409,7 +409,7 @@ i915_gem_context_create_gvt(struct drm_device *dev) i915_gem_context_set_closed(ctx); /* not user accessible */ i915_gem_context_clear_bannable(ctx); i915_gem_context_set_force_single_submission(ctx); - if (!i915_modparams.enable_guc_submission) + if (!USES_GUC_SUBMISSION(to_i915(dev))) ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */ GEM_BUG_ON(i915_gem_context_is_kernel(ctx)); diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 41a203e0c160..86fbd67388f3 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3503,7 +3503,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) * currently don't have any bits spare to pass in this upper * restriction! */ - if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) { + if (USES_GUC(dev_priv)) { ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP); ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); } diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 7cac07db89b9..3517c6548e2c 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1400,7 +1400,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift) if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) { notify_ring(engine); - tasklet |= i915_modparams.enable_guc_submission; + tasklet |= USES_GUC_SUBMISSION(engine->i915); } if (tasklet) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index df8690738369..177ee69ca9b1 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -129,7 +129,7 @@ void intel_guc_init_params(struct intel_guc *guc) } /* If GuC submission is enabled, set up additional parameters here */ - if (i915_modparams.enable_guc_submission) { + if (USES_GUC_SUBMISSION(dev_priv)) { u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT; u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool); u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16; diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c index 76d3eb1e4614..1a2c5eed9929 100644 --- a/drivers/gpu/drm/i915/intel_guc_log.c +++ b/drivers/gpu/drm/i915/intel_guc_log.c @@ -505,7 +505,7 @@ static void guc_flush_logs(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); - if (!i915_modparams.enable_guc_submission || + if (!USES_GUC_SUBMISSION(dev_priv) || (i915_modparams.guc_log_level < 0)) return; @@ -646,7 +646,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val) void i915_guc_log_register(struct drm_i915_private *dev_priv) { - if (!i915_modparams.enable_guc_submission || + if (!USES_GUC_SUBMISSION(dev_priv) || (i915_modparams.guc_log_level < 0)) return; @@ -657,7 +657,7 @@ void i915_guc_log_register(struct drm_i915_private *dev_priv) void i915_guc_log_unregister(struct drm_i915_private *dev_priv) { - if (!i915_modparams.enable_guc_submission) + if (!USES_GUC_SUBMISSION(dev_priv)) return; mutex_lock(&dev_priv->drm.struct_mutex); diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c index 126f7c769c69..a2fe7c8d4477 100644 --- a/drivers/gpu/drm/i915/intel_gvt.c +++ b/drivers/gpu/drm/i915/intel_gvt.c @@ -95,7 +95,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv) return 0; } - if (i915_modparams.enable_guc_submission) { + if (USES_GUC_SUBMISSION(dev_priv)) { DRM_ERROR("i915 GVT-g loading failed due to Graphics virtualization is not yet supported with GuC submission\n"); return -EIO; } diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 4b7f2a78b378..ed2dd764fed7 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -152,7 +152,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) struct intel_guc *guc = &dev_priv->guc; int ret, attempts; - if (!i915_modparams.enable_guc_loading) + if (!USES_GUC(dev_priv)) return 0; guc_disable_communication(guc); @@ -161,7 +161,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) /* We need to notify the guc whenever we change the GGTT */ i915_ggtt_enable_guc(dev_priv); - if (i915_modparams.enable_guc_submission) { + if (USES_GUC_SUBMISSION(dev_priv)) { /* * This is stuff we need to have available at fw load time * if we are planning to enable submission later @@ -211,7 +211,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) goto err_log_capture; intel_huc_auth(&dev_priv->huc); - if (i915_modparams.enable_guc_submission) { + if (USES_GUC_SUBMISSION(dev_priv)) { if (i915_modparams.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); @@ -220,11 +220,10 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) goto err_interrupts; } - dev_info(dev_priv->drm.dev, "GuC %s (firmware %s [version %u.%u])\n", - i915_modparams.enable_guc_submission ? "submission enabled" : - "loaded", - guc->fw.path, + dev_info(dev_priv->drm.dev, "GuC firmware version %u.%u\n", guc->fw.major_ver_found, guc->fw.minor_ver_found); + dev_info(dev_priv->drm.dev, "GuC submission %s\n", + enableddisabled(USES_GUC_SUBMISSION(dev_priv))); return 0; @@ -243,7 +242,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) err_log_capture: guc_capture_load_err_log(guc); err_submission: - if (i915_modparams.enable_guc_submission) + if (USES_GUC_SUBMISSION(dev_priv)) intel_guc_submission_fini(guc); err_guc: i915_ggtt_disable_guc(dev_priv); @@ -257,7 +256,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) ret = 0; } - if (i915_modparams.enable_guc_submission) { + if (USES_GUC_SUBMISSION(dev_priv)) { i915_modparams.enable_guc_submission = 0; DRM_NOTE("Falling back from GuC submission to execlist mode\n"); } @@ -273,15 +272,15 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv) guc_free_load_err_log(guc); - if (!i915_modparams.enable_guc_loading) + if (!USES_GUC(dev_priv)) return; - if (i915_modparams.enable_guc_submission) + if (USES_GUC_SUBMISSION(dev_priv)) intel_guc_submission_disable(guc); guc_disable_communication(guc); - if (i915_modparams.enable_guc_submission) { + if (USES_GUC_SUBMISSION(dev_priv)) { gen9_disable_guc_interrupts(dev_priv); intel_guc_submission_fini(guc); } diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c index 7b23597858bb..68d6a69c738f 100644 --- a/drivers/gpu/drm/i915/selftests/intel_guc.c +++ b/drivers/gpu/drm/i915/selftests/intel_guc.c @@ -362,7 +362,7 @@ int intel_guc_live_selftest(struct drm_i915_private *dev_priv) SUBTEST(igt_guc_doorbells), }; - if (!i915_modparams.enable_guc_submission) + if (!USES_GUC_SUBMISSION(dev_priv)) return 0; return i915_subtests(tests, dev_priv); -- GitLab From a655aeb34f7cae135a31a8a643314061ca6737e3 Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Wed, 6 Dec 2017 13:53:13 +0000 Subject: [PATCH 0754/2547] drm/i915/uc: Don't fetch GuC firmware if no plan to use GuC If we don't plan to use GuC then we should not try to fetch GuC and HuC firmwares. We can save memory and avoid possible dmesg noise. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Sagar Arun Kamble Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171206135316.32556-4-michal.wajdeczko@intel.com --- drivers/gpu/drm/i915/intel_uc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index ed2dd764fed7..c3981aa4fb28 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -86,12 +86,18 @@ void intel_uc_init_early(struct drm_i915_private *dev_priv) void intel_uc_init_fw(struct drm_i915_private *dev_priv) { + if (!USES_GUC(dev_priv)) + return; + intel_uc_fw_fetch(dev_priv, &dev_priv->huc.fw); intel_uc_fw_fetch(dev_priv, &dev_priv->guc.fw); } void intel_uc_fini_fw(struct drm_i915_private *dev_priv) { + if (!USES_GUC(dev_priv)) + return; + intel_uc_fw_fini(&dev_priv->guc.fw); intel_uc_fw_fini(&dev_priv->huc.fw); } -- GitLab From 8620eb1dbbf287694ee8e0cd280fadedb1f91012 Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Wed, 6 Dec 2017 13:53:14 +0000 Subject: [PATCH 0755/2547] drm/i915/uc: Don't use -EIO to report missing firmware -EIO has special meaning and is used when we want to allow engine initialization to fail and mark GPU as wedged. However here at this function we should return error code that corresponds to upload status only, as any decision how to handle missing firmware should be done higher level function (silent fallback to non-GuC mode, fail into wedged mode, or abort driver load with fatal error). v2: commit message update (Michal) Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Sagar Arun Kamble Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171206135316.32556-5-michal.wajdeczko@intel.com --- drivers/gpu/drm/i915/intel_uc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c index b376dd3b28cc..784eff9cdfc8 100644 --- a/drivers/gpu/drm/i915/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/intel_uc_fw.c @@ -214,7 +214,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, intel_uc_fw_type_repr(uc_fw->type), uc_fw->path); if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS) - return -EIO; + return -ENOEXEC; uc_fw->load_status = INTEL_UC_FIRMWARE_PENDING; DRM_DEBUG_DRIVER("%s fw load %s\n", -- GitLab From 121981fafe699d9f398a3c717912ef4eae6719b1 Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Wed, 6 Dec 2017 13:53:15 +0000 Subject: [PATCH 0756/2547] drm/i915/guc: Combine enable_guc_loading|submission modparams We currently have two module parameters that control GuC: "enable_guc_loading" and "enable_guc_submission". Whenever we need submission=1, we also need loading=1. We also need loading=1 when we want to want to load and verify the HuC. Lets combine above module parameters into one "enable_guc" modparam. New supported bit values are: 0=disable GuC (no GuC submission, no HuC) 1=enable GuC submission 2=enable HuC load Special value "-1" can be used to let driver decide what option should be enabled for given platform based on hardware/firmware availability or preference. Explicit enabling any of the GuC features makes GuC load a required step, fallback to non-GuC mode will not be supported. v2: Don't use -EIO v3: define modparam bits (Chris) v4: rely on implicit cast (Chris) Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Sagar Arun Kamble Cc: Sujaritha Sundaresan Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171206135316.32556-6-michal.wajdeczko@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 5 +- drivers/gpu/drm/i915/i915_params.c | 11 ++- drivers/gpu/drm/i915/i915_params.h | 7 +- drivers/gpu/drm/i915/intel_uc.c | 109 +++++++++++++++++------------ drivers/gpu/drm/i915/intel_uc.h | 19 +++++ 5 files changed, 96 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 937fa02300e3..02551c781f0a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3240,8 +3240,9 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) /* Having a GuC is not the same as using a GuC */ -#define USES_GUC(dev_priv) (i915_modparams.enable_guc_loading) -#define USES_GUC_SUBMISSION(dev_priv) (i915_modparams.enable_guc_submission) +#define USES_GUC(dev_priv) intel_uc_is_using_guc() +#define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission() +#define USES_HUC(dev_priv) intel_uc_is_using_huc() #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 7bc538687871..8dfea0320c2f 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -147,13 +147,10 @@ i915_param_named_unsafe(edp_vswing, int, 0400, "(0=use value from vbt [default], 1=low power swing(200mV)," "2=default swing(400mV))"); -i915_param_named_unsafe(enable_guc_loading, int, 0400, - "Enable GuC firmware loading " - "(-1=auto, 0=never [default], 1=if available, 2=required)"); - -i915_param_named_unsafe(enable_guc_submission, int, 0400, - "Enable GuC submission " - "(-1=auto, 0=never [default], 1=if available, 2=required)"); +i915_param_named_unsafe(enable_guc, int, 0400, + "Enable GuC load for GuC submission and/or HuC load. " + "Required functionality can be selected using bitmask values. " + "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)"); i915_param_named(guc_log_level, int, 0400, "GuC firmware logging level (-1:disabled (default), 0-3:enabled)"); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c48c88bb95e8..792ce26d7449 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -25,8 +25,12 @@ #ifndef _I915_PARAMS_H_ #define _I915_PARAMS_H_ +#include #include /* for __read_mostly */ +#define ENABLE_GUC_SUBMISSION BIT(0) +#define ENABLE_GUC_LOAD_HUC BIT(1) + #define I915_PARAMS_FOR_EACH(param) \ param(char *, vbt_firmware, NULL) \ param(int, modeset, -1) \ @@ -41,8 +45,7 @@ param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc_loading, 0) \ - param(int, enable_guc_submission, 0) \ + param(int, enable_guc, 0) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index c3981aa4fb28..7dfc7e07982f 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -47,35 +47,65 @@ static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv) return ret; } -void intel_uc_sanitize_options(struct drm_i915_private *dev_priv) +static int __get_platform_enable_guc(struct drm_i915_private *dev_priv) { - if (!HAS_GUC(dev_priv)) { - if (i915_modparams.enable_guc_loading > 0 || - i915_modparams.enable_guc_submission > 0) - DRM_INFO("Ignoring GuC options, no hardware\n"); + struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; + struct intel_uc_fw *huc_fw = &dev_priv->huc.fw; + int enable_guc = 0; - i915_modparams.enable_guc_loading = 0; - i915_modparams.enable_guc_submission = 0; - return; - } + /* Default is to enable GuC/HuC if we know their firmwares */ + if (intel_uc_fw_is_selected(guc_fw)) + enable_guc |= ENABLE_GUC_SUBMISSION; + if (intel_uc_fw_is_selected(huc_fw)) + enable_guc |= ENABLE_GUC_LOAD_HUC; - /* A negative value means "use platform default" */ - if (i915_modparams.enable_guc_loading < 0) - i915_modparams.enable_guc_loading = HAS_GUC_UCODE(dev_priv); + /* Any platform specific fine-tuning can be done here */ - /* Verify firmware version */ - if (i915_modparams.enable_guc_loading) { - if (!intel_uc_fw_is_selected(&dev_priv->guc.fw)) - i915_modparams.enable_guc_loading = 0; - } + return enable_guc; +} - /* Can't enable guc submission without guc loaded */ - if (!i915_modparams.enable_guc_loading) - i915_modparams.enable_guc_submission = 0; +/** + * intel_uc_sanitize_options - sanitize uC related modparam options + * @dev_priv: device private + * + * In case of "enable_guc" option this function will attempt to modify + * it only if it was initially set to "auto(-1)". Default value for this + * modparam varies between platforms and it is hardcoded in driver code. + * Any other modparam value is only monitored against availability of the + * related hardware or firmware definitions. + */ +void intel_uc_sanitize_options(struct drm_i915_private *dev_priv) +{ + struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; + struct intel_uc_fw *huc_fw = &dev_priv->huc.fw; /* A negative value means "use platform default" */ - if (i915_modparams.enable_guc_submission < 0) - i915_modparams.enable_guc_submission = HAS_GUC_SCHED(dev_priv); + if (i915_modparams.enable_guc < 0) + i915_modparams.enable_guc = __get_platform_enable_guc(dev_priv); + + DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n", + i915_modparams.enable_guc, + yesno(intel_uc_is_using_guc_submission()), + yesno(intel_uc_is_using_huc())); + + /* Verify GuC firmware availability */ + if (intel_uc_is_using_guc() && !intel_uc_fw_is_selected(guc_fw)) { + DRM_WARN("Incompatible option detected: enable_guc=%d, %s!\n", + i915_modparams.enable_guc, + !HAS_GUC(dev_priv) ? "no GuC hardware" : + "no GuC firmware"); + } + + /* Verify HuC firmware availability */ + if (intel_uc_is_using_huc() && !intel_uc_fw_is_selected(huc_fw)) { + DRM_WARN("Incompatible option detected: enable_guc=%d, %s!\n", + i915_modparams.enable_guc, + !HAS_HUC(dev_priv) ? "no HuC hardware" : + "no HuC firmware"); + } + + /* Make sure that sanitization was done */ + GEM_BUG_ON(i915_modparams.enable_guc < 0); } void intel_uc_init_early(struct drm_i915_private *dev_priv) @@ -161,6 +191,11 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) if (!USES_GUC(dev_priv)) return 0; + if (!HAS_GUC(dev_priv)) { + ret = -ENODEV; + goto err_out; + } + guc_disable_communication(guc); gen9_reset_guc_interrupts(dev_priv); @@ -235,12 +270,6 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) /* * We've failed to load the firmware :( - * - * Decide whether to disable GuC submission and fall back to - * execlist mode, and whether to hide the error by returning - * zero or to return -EIO, which the caller will treat as a - * nonfatal error (i.e. it doesn't prevent driver load, but - * marks the GPU as wedged until reset). */ err_interrupts: guc_disable_communication(guc); @@ -252,23 +281,15 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) intel_guc_submission_fini(guc); err_guc: i915_ggtt_disable_guc(dev_priv); +err_out: + /* + * Note that there is no fallback as either user explicitly asked for + * the GuC or driver default option was to run with the GuC enabled. + */ + if (GEM_WARN_ON(ret == -EIO)) + ret = -EINVAL; - if (i915_modparams.enable_guc_loading > 1 || - i915_modparams.enable_guc_submission > 1) { - DRM_ERROR("GuC init failed. Firmware loading disabled.\n"); - ret = -EIO; - } else { - DRM_NOTE("GuC init failed. Firmware loading disabled.\n"); - ret = 0; - } - - if (USES_GUC_SUBMISSION(dev_priv)) { - i915_modparams.enable_guc_submission = 0; - DRM_NOTE("Falling back from GuC submission to execlist mode\n"); - } - - i915_modparams.enable_guc_loading = 0; - + dev_err(dev_priv->drm.dev, "GuC initialization failed %d\n", ret); return ret; } diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index e18d3bb02088..7a59e2486e9e 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -26,6 +26,7 @@ #include "intel_guc.h" #include "intel_huc.h" +#include "i915_params.h" void intel_uc_sanitize_options(struct drm_i915_private *dev_priv); void intel_uc_init_early(struct drm_i915_private *dev_priv); @@ -35,4 +36,22 @@ void intel_uc_fini_fw(struct drm_i915_private *dev_priv); int intel_uc_init_hw(struct drm_i915_private *dev_priv); void intel_uc_fini_hw(struct drm_i915_private *dev_priv); +static inline bool intel_uc_is_using_guc(void) +{ + GEM_BUG_ON(i915_modparams.enable_guc < 0); + return i915_modparams.enable_guc > 0; +} + +static inline bool intel_uc_is_using_guc_submission(void) +{ + GEM_BUG_ON(i915_modparams.enable_guc < 0); + return i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION; +} + +static inline bool intel_uc_is_using_huc(void) +{ + GEM_BUG_ON(i915_modparams.enable_guc < 0); + return i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC; +} + #endif -- GitLab From 0dfa1cee613e03cee295b8d1ed8130c84311b584 Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Wed, 6 Dec 2017 13:53:16 +0000 Subject: [PATCH 0757/2547] drm/i915/huc: Load HuC only if requested Our new "enable_guc" modparam allows to control whenever HuC should be loaded. However existing code will try load and authenticate HuC always when we use the GuC. This patch is trying to enforce modparam selection. v2: no need to cast PTR_ERR (Chris) fetch/fini only if required (Michal) fix wrong break (Sagar) v3: add new goto label (Sagar) Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Sagar Arun Kamble Reviewed-by: Sagar Arun Kamble Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171206135316.32556-7-michal.wajdeczko@intel.com --- drivers/gpu/drm/i915/intel_huc.c | 21 +++++++++++---------- drivers/gpu/drm/i915/intel_huc.h | 4 ++-- drivers/gpu/drm/i915/intel_uc.c | 28 +++++++++++++++++++++++----- 3 files changed, 36 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c index 6d0e050ab7d9..974be3defa70 100644 --- a/drivers/gpu/drm/i915/intel_huc.c +++ b/drivers/gpu/drm/i915/intel_huc.c @@ -181,17 +181,17 @@ static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma) * intel_huc_init_hw() - load HuC uCode to device * @huc: intel_huc structure * - * Called from guc_setup() during driver loading and also after a GPU reset. - * Be note that HuC loading must be done before GuC loading. + * Called from intel_uc_init_hw() during driver loading and also after a GPU + * reset. Be note that HuC loading must be done before GuC loading. * * The firmware image should have already been fetched into memory by the - * earlier call to intel_huc_init(), so here we need only check that + * earlier call to intel_uc_init_fw(), so here we need only check that * is succeeded, and then transfer the image to the h/w. * */ -void intel_huc_init_hw(struct intel_huc *huc) +int intel_huc_init_hw(struct intel_huc *huc) { - intel_uc_fw_upload(&huc->fw, huc_ucode_xfer); + return intel_uc_fw_upload(&huc->fw, huc_ucode_xfer); } /** @@ -205,7 +205,7 @@ void intel_huc_init_hw(struct intel_huc *huc) * signature through intel_guc_auth_huc(). It then waits for 50ms for * firmware verification ACK and unpins the object. */ -void intel_huc_auth(struct intel_huc *huc) +int intel_huc_auth(struct intel_huc *huc) { struct drm_i915_private *i915 = huc_to_i915(huc); struct intel_guc *guc = &i915->guc; @@ -213,14 +213,14 @@ void intel_huc_auth(struct intel_huc *huc) int ret; if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) - return; + return -ENOEXEC; vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, PIN_OFFSET_BIAS | GUC_WOPCM_TOP); if (IS_ERR(vma)) { - DRM_ERROR("failed to pin huc fw object %d\n", - (int)PTR_ERR(vma)); - return; + ret = PTR_ERR(vma); + DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret); + return ret; } ret = intel_guc_auth_huc(guc, @@ -243,4 +243,5 @@ void intel_huc_auth(struct intel_huc *huc) out: i915_vma_unpin(vma); + return ret; } diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h index 3d757bce9ce3..40039db59e04 100644 --- a/drivers/gpu/drm/i915/intel_huc.h +++ b/drivers/gpu/drm/i915/intel_huc.h @@ -35,7 +35,7 @@ struct intel_huc { }; void intel_huc_init_early(struct intel_huc *huc); -void intel_huc_init_hw(struct intel_huc *huc); -void intel_huc_auth(struct intel_huc *huc); +int intel_huc_init_hw(struct intel_huc *huc); +int intel_huc_auth(struct intel_huc *huc); #endif diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 7dfc7e07982f..461047c86e0d 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -119,7 +119,9 @@ void intel_uc_init_fw(struct drm_i915_private *dev_priv) if (!USES_GUC(dev_priv)) return; - intel_uc_fw_fetch(dev_priv, &dev_priv->huc.fw); + if (USES_HUC(dev_priv)) + intel_uc_fw_fetch(dev_priv, &dev_priv->huc.fw); + intel_uc_fw_fetch(dev_priv, &dev_priv->guc.fw); } @@ -129,7 +131,9 @@ void intel_uc_fini_fw(struct drm_i915_private *dev_priv) return; intel_uc_fw_fini(&dev_priv->guc.fw); - intel_uc_fw_fini(&dev_priv->huc.fw); + + if (USES_HUC(dev_priv)) + intel_uc_fw_fini(&dev_priv->huc.fw); } /** @@ -186,6 +190,7 @@ static void guc_disable_communication(struct intel_guc *guc) int intel_uc_init_hw(struct drm_i915_private *dev_priv) { struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; int ret, attempts; if (!USES_GUC(dev_priv)) @@ -233,7 +238,12 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) if (ret) goto err_submission; - intel_huc_init_hw(&dev_priv->huc); + if (USES_HUC(dev_priv)) { + ret = intel_huc_init_hw(huc); + if (ret) + goto err_submission; + } + intel_guc_init_params(guc); ret = intel_guc_fw_upload(guc); if (ret == 0 || ret != -EAGAIN) @@ -251,7 +261,12 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) if (ret) goto err_log_capture; - intel_huc_auth(&dev_priv->huc); + if (USES_HUC(dev_priv)) { + ret = intel_huc_auth(huc); + if (ret) + goto err_communication; + } + if (USES_GUC_SUBMISSION(dev_priv)) { if (i915_modparams.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); @@ -265,6 +280,8 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) guc->fw.major_ver_found, guc->fw.minor_ver_found); dev_info(dev_priv->drm.dev, "GuC submission %s\n", enableddisabled(USES_GUC_SUBMISSION(dev_priv))); + dev_info(dev_priv->drm.dev, "HuC %s\n", + enableddisabled(USES_HUC(dev_priv))); return 0; @@ -272,8 +289,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) * We've failed to load the firmware :( */ err_interrupts: - guc_disable_communication(guc); gen9_disable_guc_interrupts(dev_priv); +err_communication: + guc_disable_communication(guc); err_log_capture: guc_capture_load_err_log(guc); err_submission: -- GitLab From 8c71fa88f7778eb093ee22cba13a3813a82113ad Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 5 Dec 2017 17:38:43 +0300 Subject: [PATCH 0758/2547] xen/pvcalls: check for xenbus_read() errors Smatch complains that "len" is uninitialized if xenbus_read() fails so let's add some error handling. Signed-off-by: Dan Carpenter Reviewed-by: Juergen Gross Reviewed-by: Stefano Stabellini Signed-off-by: Boris Ostrovsky --- drivers/xen/pvcalls-front.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/xen/pvcalls-front.c b/drivers/xen/pvcalls-front.c index 40caa92bff33..afa3f1b5d807 100644 --- a/drivers/xen/pvcalls-front.c +++ b/drivers/xen/pvcalls-front.c @@ -1128,6 +1128,8 @@ static int pvcalls_front_probe(struct xenbus_device *dev, } versions = xenbus_read(XBT_NIL, dev->otherend, "versions", &len); + if (IS_ERR(versions)) + return PTR_ERR(versions); if (!len) return -EINVAL; if (strcmp(versions, "1")) { -- GitLab From 1ab134ca3151c55b6fc606857e71d9adb4c355d1 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 5 Dec 2017 17:38:54 +0300 Subject: [PATCH 0759/2547] xen/pvcalls: Fix a check in pvcalls_front_remove() bedata->ref can't be less than zero because it's unsigned. This affects certain error paths in probe. We first set ->ref = -1 and then we set it to a valid value later. Fixes: 219681909913 ("xen/pvcalls: connect to the backend") Signed-off-by: Dan Carpenter Reviewed-by: Juergen Gross Reviewed-by: Stefano Stabellini Signed-off-by: Boris Ostrovsky --- drivers/xen/pvcalls-front.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/xen/pvcalls-front.c b/drivers/xen/pvcalls-front.c index afa3f1b5d807..d1e1d8d2b9d5 100644 --- a/drivers/xen/pvcalls-front.c +++ b/drivers/xen/pvcalls-front.c @@ -1103,7 +1103,7 @@ static int pvcalls_front_remove(struct xenbus_device *dev) kfree(map); } } - if (bedata->ref >= 0) + if (bedata->ref != -1) gnttab_end_foreign_access(bedata->ref, 0, 0); kfree(bedata->ring.sring); kfree(bedata); -- GitLab From aece09024414b54158e03aa45f4a4436e7cb996c Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 5 Dec 2017 17:37:17 +0300 Subject: [PATCH 0760/2547] staging: ccree: Uninitialized return in ssi_ahash_import() The return value isn't initialized on some success paths. Fixes: c5f39d07860c ("staging: ccree: fix leak of import() after init()") Signed-off-by: Dan Carpenter Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ccree/ssi_hash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c index 1799d3f26a9e..2035835b62dc 100644 --- a/drivers/staging/ccree/ssi_hash.c +++ b/drivers/staging/ccree/ssi_hash.c @@ -1769,7 +1769,7 @@ static int ssi_ahash_import(struct ahash_request *req, const void *in) struct device *dev = drvdata_to_dev(ctx->drvdata); struct ahash_req_ctx *state = ahash_request_ctx(req); u32 tmp; - int rc; + int rc = 0; memcpy(&tmp, in, sizeof(u32)); if (tmp != CC_EXPORT_MAGIC) { -- GitLab From 202fc673c626e4ffe6b888c469b248ecc6d50265 Mon Sep 17 00:00:00 2001 From: Marcus Wolf Date: Wed, 8 Nov 2017 19:13:56 +0200 Subject: [PATCH 0761/2547] staging: pi433: Fixes issue with bit shift in rf69_get_modulation Fixes issue with bit shift in rf69_get_modulation Signed-off-by: Marcus Wolf Signed-off-by: Greg Kroah-Hartman --- drivers/staging/pi433/rf69.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/pi433/rf69.c b/drivers/staging/pi433/rf69.c index e69a2153c999..12c9df9cddde 100644 --- a/drivers/staging/pi433/rf69.c +++ b/drivers/staging/pi433/rf69.c @@ -102,7 +102,7 @@ enum modulation rf69_get_modulation(struct spi_device *spi) currentValue = READ_REG(REG_DATAMODUL); - switch (currentValue & MASK_DATAMODUL_MODULATION_TYPE >> 3) { // TODO improvement: change 3 to define + switch (currentValue & MASK_DATAMODUL_MODULATION_TYPE) { case DATAMODUL_MODULATION_TYPE_OOK: return OOK; case DATAMODUL_MODULATION_TYPE_FSK: return FSK; default: return undefined; -- GitLab From b1394e745b9453dcb5b0671c205b770e87dedb87 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= Date: Thu, 30 Nov 2017 19:05:45 +0100 Subject: [PATCH 0762/2547] KVM: x86: fix APIC page invalidation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implementation of the unpinned APIC page didn't update the VMCS address cache when invalidation was done through range mmu notifiers. This became a problem when the page notifier was removed. Re-introduce the arch-specific helper and call it from ...range_start. Reported-by: Fabian Grünbichler Fixes: 38b9917350cb ("kvm: vmx: Implement set_apic_access_page_addr") Fixes: 369ea8242c0f ("mm/rmap: update to new mmu_notifier semantic v2") Cc: Reviewed-by: Paolo Bonzini Reviewed-by: Andrea Arcangeli Tested-by: Wanpeng Li Tested-by: Fabian Grünbichler Signed-off-by: Radim Krčmář --- arch/x86/include/asm/kvm_host.h | 3 +++ arch/x86/kvm/x86.c | 14 ++++++++++++++ virt/kvm/kvm_main.c | 8 ++++++++ 3 files changed, 25 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 62527e053ee4..516798431328 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1448,4 +1448,7 @@ static inline int kvm_cpu_get_apicid(int mps_cpu) #define put_smstate(type, buf, offset, val) \ *(type *)((buf) + (offset) - 0x7e00) = val +void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, + unsigned long start, unsigned long end); + #endif /* _ASM_X86_KVM_HOST_H */ diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 6ca747abfa2f..faf843c9b916 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -6764,6 +6764,20 @@ static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) kvm_x86_ops->tlb_flush(vcpu); } +void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, + unsigned long start, unsigned long end) +{ + unsigned long apic_address; + + /* + * The physical address of apic access page is stored in the VMCS. + * Update it when it becomes invalid. + */ + apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); + if (start <= apic_address && apic_address < end) + kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); +} + void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) { struct page *page = NULL; diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index c422c10cd1dd..210bf820385a 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c @@ -135,6 +135,11 @@ static void kvm_uevent_notify_change(unsigned int type, struct kvm *kvm); static unsigned long long kvm_createvm_count; static unsigned long long kvm_active_vms; +__weak void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, + unsigned long start, unsigned long end) +{ +} + bool kvm_is_reserved_pfn(kvm_pfn_t pfn) { if (pfn_valid(pfn)) @@ -360,6 +365,9 @@ static void kvm_mmu_notifier_invalidate_range_start(struct mmu_notifier *mn, kvm_flush_remote_tlbs(kvm); spin_unlock(&kvm->mmu_lock); + + kvm_arch_mmu_notifier_invalidate_range(kvm, start, end); + srcu_read_unlock(&kvm->srcu, idx); } -- GitLab From c7b92172a61b91936be985cb9bc499a4ebc6489b Mon Sep 17 00:00:00 2001 From: Stefan Potyra Date: Wed, 6 Dec 2017 16:03:24 +0100 Subject: [PATCH 0763/2547] ASoC: rockchip: disable clock on error Disable the clocks in rk_spdif_probe when an error occurs after one of the clocks has been enabled previously. Found by Linux Driver Verification project (linuxtesting.org). Fixes: f874b80e1571 ASoC: rockchip: Add rockchip SPDIF transceiver driver Signed-off-by: Stefan Potyra Signed-off-by: Mark Brown --- sound/soc/rockchip/rockchip_spdif.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c index ee5055d47d13..a89fe9b6463b 100644 --- a/sound/soc/rockchip/rockchip_spdif.c +++ b/sound/soc/rockchip/rockchip_spdif.c @@ -322,26 +322,30 @@ static int rk_spdif_probe(struct platform_device *pdev) spdif->mclk = devm_clk_get(&pdev->dev, "mclk"); if (IS_ERR(spdif->mclk)) { dev_err(&pdev->dev, "Can't retrieve rk_spdif master clock\n"); - return PTR_ERR(spdif->mclk); + ret = PTR_ERR(spdif->mclk); + goto err_disable_hclk; } ret = clk_prepare_enable(spdif->mclk); if (ret) { dev_err(spdif->dev, "clock enable failed %d\n", ret); - return ret; + goto err_disable_clocks; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(regs)) - return PTR_ERR(regs); + if (IS_ERR(regs)) { + ret = PTR_ERR(regs); + goto err_disable_clocks; + } spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs, &rk_spdif_regmap_config); if (IS_ERR(spdif->regmap)) { dev_err(&pdev->dev, "Failed to initialise managed register map\n"); - return PTR_ERR(spdif->regmap); + ret = PTR_ERR(spdif->regmap); + goto err_disable_clocks; } spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR; @@ -373,6 +377,10 @@ static int rk_spdif_probe(struct platform_device *pdev) err_pm_runtime: pm_runtime_disable(&pdev->dev); +err_disable_clocks: + clk_disable_unprepare(spdif->mclk); +err_disable_hclk: + clk_disable_unprepare(spdif->hclk); return ret; } -- GitLab From e02b03303f13b6a571f01b4d84b69440696d2dde Mon Sep 17 00:00:00 2001 From: Guneshwor Singh Date: Wed, 6 Dec 2017 16:34:04 +0530 Subject: [PATCH 0764/2547] ASoC: Intel: Skylake: Do not check dev_type for dmic link type Some BIOS have inconsistent dev_type value for DMIC link type. Since there is only one device type for DMIC link type, remove device type check if link type is NHLT_LINK_DMIC. Signed-off-by: Guneshwor Singh Acked-By: Vinod Koul Signed-off-by: Mark Brown --- sound/soc/intel/skylake/skl-nhlt.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/sound/soc/intel/skylake/skl-nhlt.c b/sound/soc/intel/skylake/skl-nhlt.c index d14c50a60289..3eaac41090ca 100644 --- a/sound/soc/intel/skylake/skl-nhlt.c +++ b/sound/soc/intel/skylake/skl-nhlt.c @@ -119,11 +119,16 @@ static bool skl_check_ep_match(struct device *dev, struct nhlt_endpoint *epnt, if ((epnt->virtual_bus_id == instance_id) && (epnt->linktype == link_type) && - (epnt->direction == dirn) && - (epnt->device_type == dev_type)) - return true; - else - return false; + (epnt->direction == dirn)) { + /* do not check dev_type for DMIC link type */ + if (epnt->linktype == NHLT_LINK_DMIC) + return true; + + if (epnt->device_type == dev_type) + return true; + } + + return false; } struct nhlt_specific_cfg -- GitLab From 1daee8b472e896f477e490ca66e58d1f8f0f4e61 Mon Sep 17 00:00:00 2001 From: Pixel Ding Date: Wed, 8 Nov 2017 11:03:14 +0800 Subject: [PATCH 0765/2547] drm/amdgpu: revise retry init to fully cleanup driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Retry at drm_dev_register instead of amdgpu_device_init. Reviewed-by: Christian König Signed-off-by: Pixel Ding Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 +++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 15 ++------------- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 57267ac265f0..ee2a5f9a32f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2390,6 +2390,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_virt_mmio_blocked(adev) && !amdgpu_virt_wait_reset(adev)) { dev_err(adev->dev, "VF exclusive mode timeout\n"); + /* Don't send request since VF is inactive. */ + adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; + adev->virt.ops = NULL; r = -EAGAIN; goto failed; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6b11a75839e2..eaccd4bd12a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -565,12 +565,13 @@ static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) return 0; } + static int amdgpu_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct drm_device *dev; unsigned long flags = ent->driver_data; - int ret; + int ret, retry = 0; if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { DRM_INFO("This hardware requires experimental hardware support.\n" @@ -603,8 +604,14 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, pci_set_drvdata(pdev, dev); +retry_init: ret = drm_dev_register(dev, ent->driver_data); - if (ret) + if (ret == -EAGAIN && ++retry <= 3) { + DRM_INFO("retry init %d\n", retry); + /* Don't request EX mode too frequently which is attacking */ + msleep(5000); + goto retry_init; + } else if (ret) goto err_pci; return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 9ed1bee0fd64..f55021ae788d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -84,7 +84,7 @@ void amdgpu_driver_unload_kms(struct drm_device *dev) int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) { struct amdgpu_device *adev; - int r, acpi_status, retry = 0; + int r, acpi_status; #ifdef CONFIG_DRM_AMDGPU_SI if (!amdgpu_si_support) { @@ -120,7 +120,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) } } #endif -retry_init: adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); if (adev == NULL) { @@ -143,17 +142,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) * VRAM allocation */ r = amdgpu_device_init(adev, dev, dev->pdev, flags); - if (r == -EAGAIN && ++retry <= 3) { - adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; - adev->virt.ops = NULL; - amdgpu_device_fini(adev); - kfree(adev); - dev->dev_private = NULL; - /* Don't request EX mode too frequently which is attacking */ - msleep(5000); - dev_err(&dev->pdev->dev, "retry init %d\n", retry); - goto retry_init; - } else if (r) { + if (r) { dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); goto out; } -- GitLab From f4323bccd17bca85f9ed10c85ed85bdd6c0b431a Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Tue, 7 Nov 2017 10:40:00 +0800 Subject: [PATCH 0766/2547] drm/amd/scheduler: fix page protection of cb MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We must remove the fence callback. Signed-off-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 53ea7e12d219..9e3748a5b398 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -229,6 +229,13 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, */ kthread_park(sched->thread); kthread_unpark(sched->thread); + if (entity->dependency) { + dma_fence_remove_callback(entity->dependency, + &entity->cb); + dma_fence_put(entity->dependency); + entity->dependency = NULL; + } + while ((job = to_amd_sched_job(spsc_queue_pop(&entity->job_queue)))) { struct amd_sched_fence *s_fence = job->s_fence; amd_sched_fence_scheduled(s_fence); -- GitLab From 45bfd9690a6af05453f7b00ca82ba458d9573c9b Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Tue, 7 Nov 2017 10:27:43 +0800 Subject: [PATCH 0767/2547] drm/amd/scheduler: add WARN_ON for s_fence->parent MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 9e3748a5b398..dcb987e6d94a 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -241,6 +241,7 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, amd_sched_fence_scheduled(s_fence); dma_fence_set_error(&s_fence->finished, -ESRCH); amd_sched_fence_finished(s_fence); + WARN_ON(s_fence->parent); dma_fence_put(&s_fence->finished); sched->ops->free_job(job); } -- GitLab From a376b0cedbb39d1504941821e424ef834325a717 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 8 Nov 2017 12:37:35 +0100 Subject: [PATCH 0768/2547] drm/ttm: move unlocking out of ttm_bo_cleanup_memtype_use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for the next patch and makes the code quite a bit easier to understand. Signed-off-by: Christian König Reviewed-and-Tested-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index c088703777e2..9905cf41cba6 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -390,8 +390,6 @@ static void ttm_bo_cleanup_memtype_use(struct ttm_buffer_object *bo) ttm_tt_destroy(bo->ttm); bo->ttm = NULL; ttm_bo_mem_put(bo, &bo->mem); - - ww_mutex_unlock (&bo->resv->lock); } static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) @@ -457,6 +455,7 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo) reservation_object_unlock(&bo->ttm_resv); ttm_bo_cleanup_memtype_use(bo); + reservation_object_unlock(bo->resv); return; } @@ -559,6 +558,7 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, spin_unlock(&glob->lru_lock); ttm_bo_cleanup_memtype_use(bo); + reservation_object_unlock(bo->resv); return 0; } -- GitLab From 36a0680aac137a9b956fb454d6bf642c9aae0be1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 8 Nov 2017 14:38:34 +0100 Subject: [PATCH 0769/2547] drm/ttm: consistently use reservation_object_unlock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of having a confusing wrapper or call the underlying ww_mutex function directly. Signed-off-by: Christian König Reviewed-and-Tested-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/qxl/qxl_release.c | 2 +- drivers/gpu/drm/ttm/ttm_bo.c | 13 +++++++------ drivers/gpu/drm/ttm/ttm_execbuf_util.c | 8 ++++---- include/drm/ttm/ttm_bo_driver.h | 14 +------------- 4 files changed, 13 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c index a6da6fa6ad58..f27777daae63 100644 --- a/drivers/gpu/drm/qxl/qxl_release.c +++ b/drivers/gpu/drm/qxl/qxl_release.c @@ -468,7 +468,7 @@ void qxl_release_fence_buffer_objects(struct qxl_release *release) reservation_object_add_shared_fence(bo->resv, &release->base); ttm_bo_add_to_lru(bo); - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); } spin_unlock(&glob->lru_lock); ww_acquire_fini(&release->ticket); diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 9905cf41cba6..6f55310a9d09 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -471,7 +471,7 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo) ttm_bo_add_to_lru(bo); } - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); } if (bo->resv != &bo->ttm_resv) reservation_object_unlock(&bo->ttm_resv); @@ -517,7 +517,8 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, if (ret && !no_wait_gpu) { long lret; - ww_mutex_unlock(&bo->resv->lock); + + reservation_object_unlock(bo->resv); spin_unlock(&glob->lru_lock); lret = reservation_object_wait_timeout_rcu(resv, true, @@ -547,7 +548,7 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, } if (ret || unlikely(list_empty(&bo->ddestroy))) { - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); spin_unlock(&glob->lru_lock); return ret; } @@ -749,7 +750,7 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev, if (place && !bdev->driver->eviction_valuable(bo, place)) { - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); ret = -EBUSY; continue; } @@ -1788,7 +1789,7 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) * already swapped buffer. */ - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); kref_put(&bo->list_kref, ttm_bo_release_list); return ret; } @@ -1825,7 +1826,7 @@ int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo) ret = __ttm_bo_reserve(bo, true, false, NULL); if (unlikely(ret != 0)) goto out_unlock; - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); out_unlock: mutex_unlock(&bo->wu_mutex); diff --git a/drivers/gpu/drm/ttm/ttm_execbuf_util.c b/drivers/gpu/drm/ttm/ttm_execbuf_util.c index 5e1bcabffef5..373ced0b2fc2 100644 --- a/drivers/gpu/drm/ttm/ttm_execbuf_util.c +++ b/drivers/gpu/drm/ttm/ttm_execbuf_util.c @@ -38,7 +38,7 @@ static void ttm_eu_backoff_reservation_reverse(struct list_head *list, list_for_each_entry_continue_reverse(entry, list, head) { struct ttm_buffer_object *bo = entry->bo; - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); } } @@ -69,7 +69,7 @@ void ttm_eu_backoff_reservation(struct ww_acquire_ctx *ticket, struct ttm_buffer_object *bo = entry->bo; ttm_bo_add_to_lru(bo); - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); } spin_unlock(&glob->lru_lock); @@ -112,7 +112,7 @@ int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket, ret = __ttm_bo_reserve(bo, intr, (ticket == NULL), ticket); if (!ret && unlikely(atomic_read(&bo->cpu_writers) > 0)) { - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); ret = -EBUSY; @@ -203,7 +203,7 @@ void ttm_eu_fence_buffer_objects(struct ww_acquire_ctx *ticket, else reservation_object_add_excl_fence(bo->resv, fence); ttm_bo_add_to_lru(bo); - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); } spin_unlock(&glob->lru_lock); if (ticket) diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index 5f821a9b3a1f..389359a0006b 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -940,18 +940,6 @@ static inline int ttm_bo_reserve_slowpath(struct ttm_buffer_object *bo, return ret; } -/** - * __ttm_bo_unreserve - * @bo: A pointer to a struct ttm_buffer_object. - * - * Unreserve a previous reservation of @bo where the buffer object is - * already on lru lists. - */ -static inline void __ttm_bo_unreserve(struct ttm_buffer_object *bo) -{ - ww_mutex_unlock(&bo->resv->lock); -} - /** * ttm_bo_unreserve * @@ -966,7 +954,7 @@ static inline void ttm_bo_unreserve(struct ttm_buffer_object *bo) ttm_bo_add_to_lru(bo); spin_unlock(&bo->glob->lru_lock); } - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); } /** -- GitLab From 842cde05840e9203d13383d30cc479f44f4ab599 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 8 Nov 2017 21:02:31 +0100 Subject: [PATCH 0770/2547] drm/ttm: user reservation object wrappers v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Consistently use the reservation object wrappers instead of accessing the ww_mutex directly. Additional to that use the reservation object wrappers directly instead of calling __ttm_bo_reserve with fixed parameters. v2: fix typo Signed-off-by: Christian König Reviewed-and-Tested-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 16 +++++++++------- include/drm/ttm/ttm_bo_driver.h | 6 +++--- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 6f55310a9d09..db0f670911ec 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -446,7 +446,7 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo) } spin_lock(&glob->lru_lock); - ret = __ttm_bo_reserve(bo, false, true, NULL); + ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY; if (!ret) { if (reservation_object_test_signaled_rcu(&bo->ttm_resv, true)) { ttm_bo_del_from_lru(bo); @@ -531,7 +531,7 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, return -EBUSY; spin_lock(&glob->lru_lock); - ret = __ttm_bo_reserve(bo, false, true, NULL); + ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY; /* * We raced, and lost, someone else holds the reservation now, @@ -592,10 +592,10 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) kref_get(&nentry->list_kref); } - ret = __ttm_bo_reserve(entry, false, true, NULL); + ret = reservation_object_trylock(entry->resv) ? 0 : -EBUSY; if (remove_all && ret) { spin_unlock(&glob->lru_lock); - ret = __ttm_bo_reserve(entry, false, false, NULL); + ret = reservation_object_lock(entry->resv, NULL); spin_lock(&glob->lru_lock); } @@ -744,7 +744,7 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev, spin_lock(&glob->lru_lock); for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) { list_for_each_entry(bo, &man->lru[i], lru) { - ret = __ttm_bo_reserve(bo, false, true, NULL); + ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY; if (ret) continue; @@ -1719,7 +1719,7 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) spin_lock(&glob->lru_lock); for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) { list_for_each_entry(bo, &glob->swap_lru[i], swap) { - ret = __ttm_bo_reserve(bo, false, true, NULL); + ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY; if (!ret) break; } @@ -1823,7 +1823,9 @@ int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo) return -ERESTARTSYS; if (!ww_mutex_is_locked(&bo->resv->lock)) goto out_unlock; - ret = __ttm_bo_reserve(bo, true, false, NULL); + ret = reservation_object_lock_interruptible(bo->resv, NULL); + if (ret == -EINTR) + ret = -ERESTARTSYS; if (unlikely(ret != 0)) goto out_unlock; reservation_object_unlock(bo->resv); diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index 389359a0006b..3659cf6150d2 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -836,14 +836,14 @@ static inline int __ttm_bo_reserve(struct ttm_buffer_object *bo, if (WARN_ON(ticket)) return -EBUSY; - success = ww_mutex_trylock(&bo->resv->lock); + success = reservation_object_trylock(bo->resv); return success ? 0 : -EBUSY; } if (interruptible) - ret = ww_mutex_lock_interruptible(&bo->resv->lock, ticket); + ret = reservation_object_lock_interruptible(bo->resv, ticket); else - ret = ww_mutex_lock(&bo->resv->lock, ticket); + ret = reservation_object_lock(bo->resv, ticket); if (ret == -EINTR) return -ERESTARTSYS; return ret; -- GitLab From add526b34a8e183d9df14f1acaaffae31bbf52d0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 8 Nov 2017 21:06:03 +0100 Subject: [PATCH 0771/2547] drm/ttm: remove ttm_bo_unreserve_ticket MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Just another alias for ttm_bo_unreserve. Signed-off-by: Christian König Reviewed-and-Tested-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/nouveau/nouveau_gem.c | 2 +- include/drm/ttm/ttm_bo_driver.h | 13 ------------- 2 files changed, 1 insertion(+), 14 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index efc89aaef66a..e72a7e37eb0a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -354,7 +354,7 @@ validate_fini_no_ticket(struct validate_op *op, struct nouveau_fence *fence, list_del(&nvbo->entry); nvbo->reserved_by = NULL; - ttm_bo_unreserve_ticket(&nvbo->bo, &op->ticket); + ttm_bo_unreserve(&nvbo->bo); drm_gem_object_unreference_unlocked(&nvbo->gem); } } diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index 3659cf6150d2..cba1477aa983 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -957,19 +957,6 @@ static inline void ttm_bo_unreserve(struct ttm_buffer_object *bo) reservation_object_unlock(bo->resv); } -/** - * ttm_bo_unreserve_ticket - * @bo: A pointer to a struct ttm_buffer_object. - * @ticket: ww_acquire_ctx used for reserving - * - * Unreserve a previous reservation of @bo made with @ticket. - */ -static inline void ttm_bo_unreserve_ticket(struct ttm_buffer_object *bo, - struct ww_acquire_ctx *t) -{ - ttm_bo_unreserve(bo); -} - /* * ttm_bo_util.c */ -- GitLab From 75737cb4eb78c7f185e4700b4aa20cf7a3381aca Mon Sep 17 00:00:00 2001 From: "Xiangliang.Yu" Date: Fri, 10 Nov 2017 14:23:38 +0800 Subject: [PATCH 0772/2547] drm/amdgpu/gfx8: Fix compute ring failure after resetting Do ring clear before ring test, otherwise compute ring test will fail after gpu resetting. Still can't find the root cause, just workaround it. Signed-off-by: Xiangliang.Yu Acked-by: Monk Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 2ddf126614da..96a3345e872e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4877,9 +4877,6 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); - /* reset ring buffer */ - ring->wptr = 0; - amdgpu_ring_clear_ring(ring); } else { amdgpu_ring_clear_ring(ring); } @@ -4954,6 +4951,13 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) /* Test KCQs */ for (i = 0; i < adev->gfx.num_compute_rings; i++) { ring = &adev->gfx.compute_ring[i]; + if (adev->in_gpu_reset) { + /* move reset ring buffer to here to workaround + * compute ring test failed + */ + ring->wptr = 0; + amdgpu_ring_clear_ring(ring); + } ring->ready = true; r = amdgpu_ring_test_ring(ring); if (r) -- GitLab From 6f16b4fb60011cbc7d4530e112739ea4416c6ea6 Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Mon, 13 Nov 2017 10:51:57 +0800 Subject: [PATCH 0773/2547] drm/amdgpu: use dep_sync for CS dependency/syncobj MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Otherwise, they could be optimized by scheduled fence. Signed-off-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index bc3a7500fbbd..743875ad4404 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1039,7 +1039,7 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, amdgpu_ctx_put(ctx); return r; } else if (fence) { - r = amdgpu_sync_fence(p->adev, &p->job->sync, + r = amdgpu_sync_fence(p->adev, &p->job->dep_sync, fence); dma_fence_put(fence); amdgpu_ctx_put(ctx); @@ -1059,7 +1059,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p, if (r) return r; - r = amdgpu_sync_fence(p->adev, &p->job->sync, fence); + r = amdgpu_sync_fence(p->adev, &p->job->dep_sync, fence); dma_fence_put(fence); return r; -- GitLab From c47b41a79ab5e8faec9aea6c4a06c4d1e4d1132f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 3 Nov 2017 15:59:25 +0100 Subject: [PATCH 0774/2547] drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not sure what that should originally been good for, but it doesn't seem to make any sense any more. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cik.c | 40 +++++++++++++------------- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 38 ++++++++++++------------ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 18 ++++++------ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 12 ++++---- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 +-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 20 ++++++------- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/si.c | 34 +++++++++++----------- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +-- drivers/gpu/drm/amd/amdgpu/vi.c | 10 +++---- 15 files changed, 113 insertions(+), 113 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index a296f7bbe57c..8ba056a2a5da 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -757,72 +757,72 @@ static void cik_init_golden_registers(struct amdgpu_device *adev) case CHIP_BONAIRE: amdgpu_program_register_sequence(adev, bonaire_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init)); + ARRAY_SIZE(bonaire_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, bonaire_golden_registers, - (const u32)ARRAY_SIZE(bonaire_golden_registers)); + ARRAY_SIZE(bonaire_golden_registers)); amdgpu_program_register_sequence(adev, bonaire_golden_common_registers, - (const u32)ARRAY_SIZE(bonaire_golden_common_registers)); + ARRAY_SIZE(bonaire_golden_common_registers)); amdgpu_program_register_sequence(adev, bonaire_golden_spm_registers, - (const u32)ARRAY_SIZE(bonaire_golden_spm_registers)); + ARRAY_SIZE(bonaire_golden_spm_registers)); break; case CHIP_KABINI: amdgpu_program_register_sequence(adev, kalindi_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); + ARRAY_SIZE(kalindi_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, kalindi_golden_registers, - (const u32)ARRAY_SIZE(kalindi_golden_registers)); + ARRAY_SIZE(kalindi_golden_registers)); amdgpu_program_register_sequence(adev, kalindi_golden_common_registers, - (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); + ARRAY_SIZE(kalindi_golden_common_registers)); amdgpu_program_register_sequence(adev, kalindi_golden_spm_registers, - (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); + ARRAY_SIZE(kalindi_golden_spm_registers)); break; case CHIP_MULLINS: amdgpu_program_register_sequence(adev, kalindi_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); + ARRAY_SIZE(kalindi_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, godavari_golden_registers, - (const u32)ARRAY_SIZE(godavari_golden_registers)); + ARRAY_SIZE(godavari_golden_registers)); amdgpu_program_register_sequence(adev, kalindi_golden_common_registers, - (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); + ARRAY_SIZE(kalindi_golden_common_registers)); amdgpu_program_register_sequence(adev, kalindi_golden_spm_registers, - (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); + ARRAY_SIZE(kalindi_golden_spm_registers)); break; case CHIP_KAVERI: amdgpu_program_register_sequence(adev, spectre_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init)); + ARRAY_SIZE(spectre_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, spectre_golden_registers, - (const u32)ARRAY_SIZE(spectre_golden_registers)); + ARRAY_SIZE(spectre_golden_registers)); amdgpu_program_register_sequence(adev, spectre_golden_common_registers, - (const u32)ARRAY_SIZE(spectre_golden_common_registers)); + ARRAY_SIZE(spectre_golden_common_registers)); amdgpu_program_register_sequence(adev, spectre_golden_spm_registers, - (const u32)ARRAY_SIZE(spectre_golden_spm_registers)); + ARRAY_SIZE(spectre_golden_spm_registers)); break; case CHIP_HAWAII: amdgpu_program_register_sequence(adev, hawaii_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init)); + ARRAY_SIZE(hawaii_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, hawaii_golden_registers, - (const u32)ARRAY_SIZE(hawaii_golden_registers)); + ARRAY_SIZE(hawaii_golden_registers)); amdgpu_program_register_sequence(adev, hawaii_golden_common_registers, - (const u32)ARRAY_SIZE(hawaii_golden_common_registers)); + ARRAY_SIZE(hawaii_golden_common_registers)); amdgpu_program_register_sequence(adev, hawaii_golden_spm_registers, - (const u32)ARRAY_SIZE(hawaii_golden_spm_registers)); + ARRAY_SIZE(hawaii_golden_spm_registers)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index f3dd6b7bfd4d..a397111c2ced 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -147,18 +147,18 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, - (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); + ARRAY_SIZE(golden_settings_fiji_a10)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, - (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + ARRAY_SIZE(golden_settings_tonga_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index be25706e5f07..67e670989e81 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -156,26 +156,26 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, cz_golden_settings_a11, - (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + ARRAY_SIZE(cz_golden_settings_a11)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, - (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + ARRAY_SIZE(stoney_golden_settings_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, polaris11_golden_settings_a11, - (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); + ARRAY_SIZE(polaris11_golden_settings_a11)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, polaris10_golden_settings_a11, - (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); + ARRAY_SIZE(polaris10_golden_settings_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 96a3345e872e..426e51866a15 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -681,53 +681,53 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + ARRAY_SIZE(iceland_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, - (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); + ARRAY_SIZE(golden_settings_iceland_a11)); amdgpu_program_register_sequence(adev, iceland_golden_common_all, - (const u32)ARRAY_SIZE(iceland_golden_common_all)); + ARRAY_SIZE(iceland_golden_common_all)); break; case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, - (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); + ARRAY_SIZE(golden_settings_fiji_a10)); amdgpu_program_register_sequence(adev, fiji_golden_common_all, - (const u32)ARRAY_SIZE(fiji_golden_common_all)); + ARRAY_SIZE(fiji_golden_common_all)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, - (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + ARRAY_SIZE(golden_settings_tonga_a11)); amdgpu_program_register_sequence(adev, tonga_golden_common_all, - (const u32)ARRAY_SIZE(tonga_golden_common_all)); + ARRAY_SIZE(tonga_golden_common_all)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); + ARRAY_SIZE(golden_settings_polaris11_a11)); amdgpu_program_register_sequence(adev, polaris11_golden_common_all, - (const u32)ARRAY_SIZE(polaris11_golden_common_all)); + ARRAY_SIZE(polaris11_golden_common_all)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); + ARRAY_SIZE(golden_settings_polaris10_a11)); amdgpu_program_register_sequence(adev, polaris10_golden_common_all, - (const u32)ARRAY_SIZE(polaris10_golden_common_all)); + ARRAY_SIZE(polaris10_golden_common_all)); WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); if (adev->pdev->revision == 0xc7 && ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || @@ -740,24 +740,24 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, cz_golden_settings_a11, - (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + ARRAY_SIZE(cz_golden_settings_a11)); amdgpu_program_register_sequence(adev, cz_golden_common_all, - (const u32)ARRAY_SIZE(cz_golden_common_all)); + ARRAY_SIZE(cz_golden_common_all)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + ARRAY_SIZE(stoney_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, - (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + ARRAY_SIZE(stoney_golden_settings_a11)); amdgpu_program_register_sequence(adev, stoney_golden_common_all, - (const u32)ARRAY_SIZE(stoney_golden_common_all)); + ARRAY_SIZE(stoney_golden_common_all)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 19a619f759f6..5ba24792f801 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -232,18 +232,18 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_VEGA10: amdgpu_program_register_sequence(adev, golden_settings_gc_9_0, - (const u32)ARRAY_SIZE(golden_settings_gc_9_0)); + ARRAY_SIZE(golden_settings_gc_9_0)); amdgpu_program_register_sequence(adev, golden_settings_gc_9_0_vg10, - (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10)); + ARRAY_SIZE(golden_settings_gc_9_0_vg10)); break; case CHIP_RAVEN: amdgpu_program_register_sequence(adev, golden_settings_gc_9_1, - (const u32)ARRAY_SIZE(golden_settings_gc_9_1)); + ARRAY_SIZE(golden_settings_gc_9_1)); amdgpu_program_register_sequence(adev, golden_settings_gc_9_1_rv1, - (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1)); + ARRAY_SIZE(golden_settings_gc_9_1_rv1)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 583d87792820..6c6a7e14359c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -69,10 +69,10 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + ARRAY_SIZE(iceland_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, - (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); + ARRAY_SIZE(golden_settings_iceland_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 9ca5fea93ebc..edbe0df24d90 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -122,42 +122,42 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, - (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); + ARRAY_SIZE(golden_settings_fiji_a10)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, - (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + ARRAY_SIZE(golden_settings_tonga_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); + ARRAY_SIZE(golden_settings_polaris11_a11)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); + ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + ARRAY_SIZE(stoney_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_stoney_common, - (const u32)ARRAY_SIZE(golden_settings_stoney_common)); + ARRAY_SIZE(golden_settings_stoney_common)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index f11dfd47b517..69c9af7af6f4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -696,15 +696,15 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_VEGA10: amdgpu_program_register_sequence(adev, golden_settings_mmhub_1_0_0, - (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0)); + ARRAY_SIZE(golden_settings_mmhub_1_0_0)); amdgpu_program_register_sequence(adev, golden_settings_athub_1_0_0, - (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0)); + ARRAY_SIZE(golden_settings_athub_1_0_0)); break; case CHIP_RAVEN: amdgpu_program_register_sequence(adev, golden_settings_athub_1_0_0, - (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0)); + ARRAY_SIZE(golden_settings_athub_1_0_0)); break; default: break; @@ -724,7 +724,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) amdgpu_program_register_sequence(adev, golden_settings_vega10_hdp, - (const u32)ARRAY_SIZE(golden_settings_vega10_hdp)); + ARRAY_SIZE(golden_settings_vega10_hdp)); if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index 2b435c02ef44..df52824c0cd4 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -281,29 +281,29 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev) case CHIP_FIJI: amdgpu_program_register_sequence(adev, xgpu_fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, xgpu_fiji_golden_settings_a10, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_fiji_golden_settings_a10)); amdgpu_program_register_sequence(adev, xgpu_fiji_golden_common_all, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_fiji_golden_common_all)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, xgpu_tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, xgpu_tonga_golden_settings_a11, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_tonga_golden_settings_a11)); amdgpu_program_register_sequence(adev, xgpu_tonga_golden_common_all, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_tonga_golden_common_all)); break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 92f8c44a73b6..121e628e7cdb 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -95,10 +95,10 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + ARRAY_SIZE(iceland_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, - (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); + ARRAY_SIZE(golden_settings_iceland_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 52e6bf2e9e59..c8c93f9dac21 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -194,45 +194,45 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, - (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); + ARRAY_SIZE(golden_settings_fiji_a10)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, - (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + ARRAY_SIZE(golden_settings_tonga_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); + ARRAY_SIZE(golden_settings_polaris11_a11)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); + ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, cz_golden_settings_a11, - (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + ARRAY_SIZE(cz_golden_settings_a11)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + ARRAY_SIZE(stoney_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, - (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + ARRAY_SIZE(stoney_golden_settings_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index fe78c00b9ffa..a0a5a8da4c4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -132,18 +132,18 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_VEGA10: amdgpu_program_register_sequence(adev, golden_settings_sdma_4, - (const u32)ARRAY_SIZE(golden_settings_sdma_4)); + ARRAY_SIZE(golden_settings_sdma_4)); amdgpu_program_register_sequence(adev, golden_settings_sdma_vg10, - (const u32)ARRAY_SIZE(golden_settings_sdma_vg10)); + ARRAY_SIZE(golden_settings_sdma_vg10)); break; case CHIP_RAVEN: amdgpu_program_register_sequence(adev, golden_settings_sdma_4_1, - (const u32)ARRAY_SIZE(golden_settings_sdma_4_1)); + ARRAY_SIZE(golden_settings_sdma_4_1)); amdgpu_program_register_sequence(adev, golden_settings_sdma_rv1, - (const u32)ARRAY_SIZE(golden_settings_sdma_rv1)); + ARRAY_SIZE(golden_settings_sdma_rv1)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 8284d5dbfc30..49eef3090f08 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1392,63 +1392,63 @@ static void si_init_golden_registers(struct amdgpu_device *adev) case CHIP_TAHITI: amdgpu_program_register_sequence(adev, tahiti_golden_registers, - (const u32)ARRAY_SIZE(tahiti_golden_registers)); + ARRAY_SIZE(tahiti_golden_registers)); amdgpu_program_register_sequence(adev, tahiti_golden_rlc_registers, - (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers)); + ARRAY_SIZE(tahiti_golden_rlc_registers)); amdgpu_program_register_sequence(adev, tahiti_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init)); + ARRAY_SIZE(tahiti_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, tahiti_golden_registers2, - (const u32)ARRAY_SIZE(tahiti_golden_registers2)); + ARRAY_SIZE(tahiti_golden_registers2)); break; case CHIP_PITCAIRN: amdgpu_program_register_sequence(adev, pitcairn_golden_registers, - (const u32)ARRAY_SIZE(pitcairn_golden_registers)); + ARRAY_SIZE(pitcairn_golden_registers)); amdgpu_program_register_sequence(adev, pitcairn_golden_rlc_registers, - (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers)); + ARRAY_SIZE(pitcairn_golden_rlc_registers)); amdgpu_program_register_sequence(adev, pitcairn_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); + ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); break; case CHIP_VERDE: amdgpu_program_register_sequence(adev, verde_golden_registers, - (const u32)ARRAY_SIZE(verde_golden_registers)); + ARRAY_SIZE(verde_golden_registers)); amdgpu_program_register_sequence(adev, verde_golden_rlc_registers, - (const u32)ARRAY_SIZE(verde_golden_rlc_registers)); + ARRAY_SIZE(verde_golden_rlc_registers)); amdgpu_program_register_sequence(adev, verde_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init)); + ARRAY_SIZE(verde_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, verde_pg_init, - (const u32)ARRAY_SIZE(verde_pg_init)); + ARRAY_SIZE(verde_pg_init)); break; case CHIP_OLAND: amdgpu_program_register_sequence(adev, oland_golden_registers, - (const u32)ARRAY_SIZE(oland_golden_registers)); + ARRAY_SIZE(oland_golden_registers)); amdgpu_program_register_sequence(adev, oland_golden_rlc_registers, - (const u32)ARRAY_SIZE(oland_golden_rlc_registers)); + ARRAY_SIZE(oland_golden_rlc_registers)); amdgpu_program_register_sequence(adev, oland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init)); + ARRAY_SIZE(oland_mgcg_cgcg_init)); break; case CHIP_HAINAN: amdgpu_program_register_sequence(adev, hainan_golden_registers, - (const u32)ARRAY_SIZE(hainan_golden_registers)); + ARRAY_SIZE(hainan_golden_registers)); amdgpu_program_register_sequence(adev, hainan_golden_registers2, - (const u32)ARRAY_SIZE(hainan_golden_registers2)); + ARRAY_SIZE(hainan_golden_registers2)); amdgpu_program_register_sequence(adev, hainan_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init)); + ARRAY_SIZE(hainan_mgcg_cgcg_init)); break; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 4e67fe1e7955..fa27e0354f35 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -265,12 +265,12 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev) case CHIP_VEGA10: amdgpu_program_register_sequence(adev, vega10_golden_init, - (const u32)ARRAY_SIZE(vega10_golden_init)); + ARRAY_SIZE(vega10_golden_init)); break; case CHIP_RAVEN: amdgpu_program_register_sequence(adev, raven_golden_init, - (const u32)ARRAY_SIZE(raven_golden_init)); + ARRAY_SIZE(raven_golden_init)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 3a4c2fa7e36d..bb8ca9489546 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -284,27 +284,27 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + ARRAY_SIZE(iceland_mgcg_cgcg_init)); break; case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + ARRAY_SIZE(stoney_mgcg_cgcg_init)); break; case CHIP_POLARIS11: case CHIP_POLARIS10: -- GitLab From fdd5faaa08f891153ac4fd8cedace6d95bed0968 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Sat, 4 Nov 2017 16:51:44 +0100 Subject: [PATCH 0775/2547] drm/amdgpu: cleanup vm_size handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's pointless to have the same value twice, just always use max_pfn. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 +++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 7 +++---- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 13 +++++-------- 6 files changed, 17 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 1e727da2bb64..122379dfc7d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2576,27 +2576,27 @@ void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, * @adev: amdgpu_device pointer * @vm_size: the default vm size if it's set auto */ -void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, uint32_t fragment_size_default) { /* adjust vm size firstly */ - if (amdgpu_vm_size == -1) - adev->vm_manager.vm_size = vm_size; - else - adev->vm_manager.vm_size = amdgpu_vm_size; + if (amdgpu_vm_size != -1) + vm_size = amdgpu_vm_size; + + adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; /* block size depends on vm size */ if (amdgpu_vm_block_size == -1) adev->vm_manager.block_size = - amdgpu_vm_get_block_size(adev->vm_manager.vm_size); + amdgpu_vm_get_block_size(vm_size); else adev->vm_manager.block_size = amdgpu_vm_block_size; amdgpu_vm_set_fragment_size(adev, fragment_size_default); - DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n", - adev->vm_manager.vm_size, adev->vm_manager.block_size, - adev->vm_manager.fragment_size); + DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n", + vm_size, adev->vm_manager.block_size, + adev->vm_manager.fragment_size); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index bae77353447b..e8f8896d18db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -221,7 +221,6 @@ struct amdgpu_vm_manager { uint64_t max_pfn; uint32_t num_level; - uint64_t vm_size; uint32_t block_size; uint32_t fragment_size; /* vram base address for page table entry */ @@ -313,9 +312,9 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va); void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, - uint32_t fragment_size_default); -void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, - uint32_t fragment_size_default); + uint32_t fragment_size_default); +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, + uint32_t fragment_size_default); int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, struct amdgpu_job *job); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index d2a43db22cff..c8e47c36608e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -838,7 +838,6 @@ static int gmc_v6_0_sw_init(void *handle) return r; amdgpu_vm_adjust_size(adev, 64, 9); - adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; adev->mc.mc_mask = 0xffffffffffULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 6c6a7e14359c..2b7338e22409 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -978,7 +978,6 @@ static int gmc_v7_0_sw_init(void *handle) * Max GPUVM size for cayman and SI is 40 bits. */ amdgpu_vm_adjust_size(adev, 64, 9); - adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; /* Set the internal MC address mask * This is the max address of the GPU's diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index edbe0df24d90..e30a96a8f49b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1075,7 +1075,6 @@ static int gmc_v8_0_sw_init(void *handle) * Max GPUVM size for cayman and SI is 40 bits. */ amdgpu_vm_adjust_size(adev, 64, 9); - adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; /* Set the internal MC address mask * This is the max address of the GPU's diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 69c9af7af6f4..b067b46a418f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -564,7 +564,7 @@ static int gmc_v9_0_sw_init(void *handle) case CHIP_RAVEN: adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { - adev->vm_manager.vm_size = 1U << 18; + adev->vm_manager.max_pfn = 1ULL << 36; adev->vm_manager.block_size = 9; adev->vm_manager.num_level = 3; amdgpu_vm_set_fragment_size(adev, 9); @@ -582,7 +582,7 @@ static int gmc_v9_0_sw_init(void *handle) * vm size is 256TB (48bit), maximum size of Vega10, * block size 512 (9bit) */ - adev->vm_manager.vm_size = 1U << 18; + adev->vm_manager.max_pfn = 1ULL << 36; adev->vm_manager.block_size = 9; adev->vm_manager.num_level = 3; amdgpu_vm_set_fragment_size(adev, 9); @@ -591,10 +591,9 @@ static int gmc_v9_0_sw_init(void *handle) break; } - DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n", - adev->vm_manager.vm_size, - adev->vm_manager.block_size, - adev->vm_manager.fragment_size); + DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n", + adev->vm_manager.max_pfn >> 18, adev->vm_manager.block_size, + adev->vm_manager.fragment_size); /* This interrupt is VMC page fault.*/ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, @@ -605,8 +604,6 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; - /* Set the internal MC address mask * This is the max address of the GPU's * internal address space. -- GitLab From 79c631239a83aeb3e13216f2eda1741650645d64 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 10 Nov 2017 18:35:56 -0500 Subject: [PATCH 0776/2547] drm/amdgpu: Implement BO size validation V2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Validates BO size against each requested domain's total memory. v2: Make GTT size check a MUST to allow fall back to GTT. Rmove redundant NULL check. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index a937c49590a9..5acf20cfb1d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -281,6 +281,44 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, *cpu_addr = NULL; } +/* Validate bo size is bit bigger then the request domain */ +static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, + unsigned long size, u32 domain) +{ + struct ttm_mem_type_manager *man = NULL; + + /* + * If GTT is part of requested domains the check must succeed to + * allow fall back to GTT + */ + if (domain & AMDGPU_GEM_DOMAIN_GTT) { + man = &adev->mman.bdev.man[TTM_PL_TT]; + + if (size < (man->size << PAGE_SHIFT)) + return true; + else + goto fail; + } + + if (domain & AMDGPU_GEM_DOMAIN_VRAM) { + man = &adev->mman.bdev.man[TTM_PL_VRAM]; + + if (size < (man->size << PAGE_SHIFT)) + return true; + else + goto fail; + } + + + /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ + return true; + +fail: + DRM_ERROR("BO size %lu > total memory in domain: %llu\n", size, + man->size << PAGE_SHIFT); + return false; +} + static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size, int byte_align, bool kernel, u32 domain, u64 flags, @@ -299,6 +337,9 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; size = ALIGN(size, PAGE_SIZE); + if (!amdgpu_bo_validate_size(adev, size, domain)) + return -ENOMEM; + if (kernel) { type = ttm_bo_type_kernel; } else if (sg) { -- GitLab From fa2123dbccdc881fae02aaf8b05758db53d62955 Mon Sep 17 00:00:00 2001 From: Mikita Lipski Date: Tue, 17 Oct 2017 15:29:22 -0400 Subject: [PATCH 0777/2547] drm/amd/display: Multi display synchronization logic This feature synchronizes multiple displays with various timings to a display with the highest refresh rate it is enabled if edid caps flag multi_display_sync is set to one There are limitations on refresh rates allowed that can be synchronized. That would prevent from underflow and other potential corruptions. Multi display synchronization is using the same functions as timing_sync in order to minimize redunduncy and decision to disable synchronization is based on trigger parametre set in DM Feature is developed for DCN1 and DCE11 Signed-off-by: Mikita Lipski Reviewed-by: Mikita Lipski Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 54 +++- drivers/gpu/drm/amd/display/dc/core/dc.c | 26 +- drivers/gpu/drm/amd/display/dc/dc.h | 3 + drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 16 ++ .../display/dc/dce110/dce110_hw_sequencer.c | 46 ++- .../dc/dce110/dce110_timing_generator.c | 265 +++++++++++++++--- .../dc/dce110/dce110_timing_generator.h | 6 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 29 +- .../display/dc/dcn10/dcn10_timing_generator.c | 66 ++++- .../amd/display/dc/inc/hw/timing_generator.h | 6 +- .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 + 11 files changed, 456 insertions(+), 66 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3bc314872304..8360d17125ae 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2298,6 +2298,56 @@ static int create_fake_sink(struct amdgpu_dm_connector *aconnector) return 0; } +static void set_multisync_trigger_params( + struct dc_stream_state *stream) +{ + if (stream->triggered_crtc_reset.enabled) { + stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; + stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; + } +} + +static void set_master_stream(struct dc_stream_state *stream_set[], + int stream_count) +{ + int j, highest_rfr = 0, master_stream = 0; + + for (j = 0; j < stream_count; j++) { + if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { + int refresh_rate = 0; + + refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/ + (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); + if (refresh_rate > highest_rfr) { + highest_rfr = refresh_rate; + master_stream = j; + } + } + } + for (j = 0; j < stream_count; j++) { + if (stream_set[j] && j != master_stream) + stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; + } +} + +static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) +{ + int i = 0; + + if (context->stream_count < 2) + return; + for (i = 0; i < context->stream_count ; i++) { + if (!context->streams[i]) + continue; + /* TODO: add a function to read AMD VSDB bits and will set + * crtc_sync_master.multi_sync_enabled flag + * For now its set to false + */ + set_multisync_trigger_params(context->streams[i]); + } + set_master_stream(context->streams, context->stream_count); +} + static struct dc_stream_state * create_stream_for_sink(struct amdgpu_dm_connector *aconnector, const struct drm_display_mode *drm_mode, @@ -4132,8 +4182,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) } } - if (dm_state->context) + if (dm_state->context) { + dm_enable_per_frame_crtc_master_sync(dm_state->context); WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); + } for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 55317c029d44..507b1171d65f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -713,6 +713,28 @@ void dc_destroy(struct dc **dc) *dc = NULL; } +static void enable_timing_multisync( + struct dc *dc, + struct dc_state *ctx) +{ + int i = 0, multisync_count = 0; + int pipe_count = dc->res_pool->pipe_count; + struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL }; + + for (i = 0; i < pipe_count; i++) { + if (!ctx->res_ctx.pipe_ctx[i].stream || + !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled) + continue; + multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i]; + multisync_count++; + } + + if (multisync_count > 1) { + dc->hwss.enable_per_frame_crtc_position_reset( + dc, multisync_count, multisync_pipes); + } +} + static void program_timing_sync( struct dc *dc, struct dc_state *ctx) @@ -891,7 +913,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c } result = dc->hwss.apply_ctx_to_hw(dc, context); - program_timing_sync(dc, context); + if (context->stream_count > 1) + enable_timing_multisync(dc, context); + program_timing_sync(dc, context); dc_enable_stereo(dc, context, dc_streams, context->stream_count); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4019e7417c88..a51a9c748c1a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -607,6 +607,9 @@ struct dc_stream_state { /* from stream struct */ struct kref refcount; + + struct crtc_trigger_info triggered_crtc_reset; + }; struct dc_stream_update { diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index ea58d106fb55..587c0bb3d4ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -673,6 +673,22 @@ enum dc_timing_3d_format { TIMING_3D_FORMAT_MAX, }; +enum trigger_delay { + TRIGGER_DELAY_NEXT_PIXEL = 0, + TRIGGER_DELAY_NEXT_LINE, +}; + +enum crtc_event { + CRTC_EVENT_VSYNC_RISING = 0, + CRTC_EVENT_VSYNC_FALLING +}; + +struct crtc_trigger_info { + bool enabled; + struct dc_stream_state *event_source; + enum crtc_event event; + enum trigger_delay delay; +}; struct dc_crtc_timing { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 58d019cacaa2..868040a4f7ff 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2457,20 +2457,16 @@ static void dce110_enable_timing_synchronization( for (i = 1 /* skip the master */; i < group_size; i++) grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( - grouped_pipes[i]->stream_res.tg, gsl_params.gsl_group); - - + grouped_pipes[i]->stream_res.tg, + gsl_params.gsl_group); for (i = 1 /* skip the master */; i < group_size; i++) { DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); - /* Regardless of success of the wait above, remove the reset or - * the driver will start timing out on Display requests. */ - DC_SYNC_INFO("GSL: disabling trigger-reset.\n"); - grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(grouped_pipes[i]->stream_res.tg); + grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( + grouped_pipes[i]->stream_res.tg); } - /* GSL Vblank synchronization is a one time sync mechanism, assumption * is that the sync'ed displays will not drift out of sync over time*/ DC_SYNC_INFO("GSL: Restoring register states.\n"); @@ -2480,6 +2476,39 @@ static void dce110_enable_timing_synchronization( DC_SYNC_INFO("GSL: Set-up complete.\n"); } +static void dce110_enable_per_frame_crtc_position_reset( + struct dc *dc, + int group_size, + struct pipe_ctx *grouped_pipes[]) +{ + struct dc_context *dc_ctx = dc->ctx; + struct dcp_gsl_params gsl_params = { 0 }; + int i; + + gsl_params.gsl_group = 0; + gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst; + + for (i = 0; i < group_size; i++) + grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( + grouped_pipes[i]->stream_res.tg, &gsl_params); + + DC_SYNC_INFO("GSL: enabling trigger-reset\n"); + + for (i = 1; i < group_size; i++) + grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( + grouped_pipes[i]->stream_res.tg, + gsl_params.gsl_master, + &grouped_pipes[i]->stream->triggered_crtc_reset); + + DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); + for (i = 1; i < group_size; i++) + wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); + + for (i = 0; i < group_size; i++) + grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); + +} + static void init_hw(struct dc *dc) { int i; @@ -2976,6 +3005,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .power_down = dce110_power_down, .enable_accelerated_mode = dce110_enable_accelerated_mode, .enable_timing_synchronization = dce110_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, .update_info_frame = dce110_update_info_frame, .enable_stream = dce110_enable_stream, .disable_stream = dce110_disable_stream, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 4befce6cd87a..25ca72139e5f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -1224,26 +1224,46 @@ void dce110_timing_generator_setup_global_swap_lock( /* This pipe will belong to GSL Group zero. */ set_reg_field_value(value, - 1, - DCP_GSL_CONTROL, - DCP_GSL0_EN); + 1, + DCP_GSL_CONTROL, + DCP_GSL0_EN); set_reg_field_value(value, - gsl_params->gsl_master == tg->inst, - DCP_GSL_CONTROL, - DCP_GSL_MASTER_EN); + gsl_params->gsl_master == tg->inst, + DCP_GSL_CONTROL, + DCP_GSL_MASTER_EN); set_reg_field_value(value, - HFLIP_READY_DELAY, - DCP_GSL_CONTROL, - DCP_GSL_HSYNC_FLIP_FORCE_DELAY); + HFLIP_READY_DELAY, + DCP_GSL_CONTROL, + DCP_GSL_HSYNC_FLIP_FORCE_DELAY); /* Keep signal low (pending high) during 6 lines. * Also defines minimum interval before re-checking signal. */ set_reg_field_value(value, - HFLIP_CHECK_DELAY, - DCP_GSL_CONTROL, - DCP_GSL_HSYNC_FLIP_CHECK_DELAY); + HFLIP_CHECK_DELAY, + DCP_GSL_CONTROL, + DCP_GSL_HSYNC_FLIP_CHECK_DELAY); + + dm_write_reg(tg->ctx, CRTC_REG(mmDCP_GSL_CONTROL), value); + value = 0; + + set_reg_field_value(value, + gsl_params->gsl_master, + DCIO_GSL0_CNTL, + DCIO_GSL0_VSYNC_SEL); + + set_reg_field_value(value, + 0, + DCIO_GSL0_CNTL, + DCIO_GSL0_TIMING_SYNC_SEL); + + set_reg_field_value(value, + 0, + DCIO_GSL0_CNTL, + DCIO_GSL0_GLOBAL_UNLOCK_SEL); + + dm_write_reg(tg->ctx, CRTC_REG(mmDCIO_GSL0_CNTL), value); { @@ -1253,38 +1273,38 @@ void dce110_timing_generator_setup_global_swap_lock( CRTC_REG(mmCRTC_V_TOTAL)); set_reg_field_value(value, - 0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */ - DCP_GSL_CONTROL, - DCP_GSL_SYNC_SOURCE); + 0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */ + DCP_GSL_CONTROL, + DCP_GSL_SYNC_SOURCE); /* Checkpoint relative to end of frame */ check_point = get_reg_field_value(value_crtc_vtotal, - CRTC_V_TOTAL, - CRTC_V_TOTAL); + CRTC_V_TOTAL, + CRTC_V_TOTAL); dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_GSL_WINDOW), 0); } set_reg_field_value(value, - 1, - DCP_GSL_CONTROL, - DCP_GSL_DELAY_SURFACE_UPDATE_PENDING); + 1, + DCP_GSL_CONTROL, + DCP_GSL_DELAY_SURFACE_UPDATE_PENDING); dm_write_reg(tg->ctx, address, value); /********************************************************************/ address = CRTC_REG(mmCRTC_GSL_CONTROL); - value = 0; + value = dm_read_reg(tg->ctx, address); set_reg_field_value(value, - check_point - FLIP_READY_BACK_LOOKUP, - CRTC_GSL_CONTROL, - CRTC_GSL_CHECK_LINE_NUM); + check_point - FLIP_READY_BACK_LOOKUP, + CRTC_GSL_CONTROL, + CRTC_GSL_CHECK_LINE_NUM); set_reg_field_value(value, - VFLIP_READY_DELAY, - CRTC_GSL_CONTROL, - CRTC_GSL_FORCE_DELAY); + VFLIP_READY_DELAY, + CRTC_GSL_CONTROL, + CRTC_GSL_FORCE_DELAY); dm_write_reg(tg->ctx, address, value); } @@ -1555,6 +1575,138 @@ void dce110_timing_generator_enable_reset_trigger( dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); } +void dce110_timing_generator_enable_crtc_reset( + struct timing_generator *tg, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp) +{ + uint32_t value = 0; + uint32_t rising_edge = 0; + uint32_t falling_edge = 0; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + /* Setup trigger edge */ + switch (crtc_tp->event) { + case CRTC_EVENT_VSYNC_RISING: + rising_edge = 1; + break; + + case CRTC_EVENT_VSYNC_FALLING: + falling_edge = 1; + break; + } + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL)); + + set_reg_field_value(value, + source_tg_inst, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_SOURCE_SELECT); + + set_reg_field_value(value, + TRIGGER_POLARITY_SELECT_LOGIC_ZERO, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_POLARITY_SELECT); + + set_reg_field_value(value, + rising_edge, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_RISING_EDGE_DETECT_CNTL); + + set_reg_field_value(value, + falling_edge, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_TRIGB_CNTL, + CRTC_TRIGB_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value); + + /**************************************************************/ + + switch (crtc_tp->delay) { + case TRIGGER_DELAY_NEXT_LINE: + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); + + set_reg_field_value(value, + 0, /* force H count to H_TOTAL and V count to V_TOTAL */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_MODE); + + set_reg_field_value(value, + 0, /* TriggerB - we never use TriggerA */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_TRIG_SEL); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL)); + + set_reg_field_value(value, + 1, + CRTC_VERT_SYNC_CONTROL, + CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR); + + set_reg_field_value(value, + 2, + CRTC_VERT_SYNC_CONTROL, + CRTC_AUTO_FORCE_VSYNC_MODE); + + break; + + case TRIGGER_DELAY_NEXT_PIXEL: + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL)); + + set_reg_field_value(value, + 1, + CRTC_VERT_SYNC_CONTROL, + CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR); + + set_reg_field_value(value, + 0, + CRTC_VERT_SYNC_CONTROL, + CRTC_AUTO_FORCE_VSYNC_MODE); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value); + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); + + set_reg_field_value(value, + 2, /* force H count to H_TOTAL and V count to V_TOTAL */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_MODE); + + set_reg_field_value(value, + 1, /* TriggerB - we never use TriggerA */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_TRIG_SEL); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); + break; + } + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE)); + + set_reg_field_value(value, + 2, + CRTC_MASTER_UPDATE_MODE, + MASTER_UPDATE_MODE); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); +} void dce110_timing_generator_disable_reset_trigger( struct timing_generator *tg) { @@ -1564,34 +1716,48 @@ void dce110_timing_generator_disable_reset_trigger( value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); set_reg_field_value(value, - 0, /* force counter now mode is disabled */ - CRTC_FORCE_COUNT_NOW_CNTL, - CRTC_FORCE_COUNT_NOW_MODE); + 0, /* force counter now mode is disabled */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_MODE); set_reg_field_value(value, - 1, /* clear trigger status */ - CRTC_FORCE_COUNT_NOW_CNTL, - CRTC_FORCE_COUNT_NOW_CLEAR); + 1, /* clear trigger status */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_CLEAR); dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL)); + + set_reg_field_value(value, + 1, + CRTC_VERT_SYNC_CONTROL, + CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR); + + set_reg_field_value(value, + 0, + CRTC_VERT_SYNC_CONTROL, + CRTC_AUTO_FORCE_VSYNC_MODE); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value); + /********************************************************************/ value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL)); set_reg_field_value(value, - TRIGGER_SOURCE_SELECT_LOGIC_ZERO, - CRTC_TRIGB_CNTL, - CRTC_TRIGB_SOURCE_SELECT); + TRIGGER_SOURCE_SELECT_LOGIC_ZERO, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_SOURCE_SELECT); set_reg_field_value(value, - TRIGGER_POLARITY_SELECT_LOGIC_ZERO, - CRTC_TRIGB_CNTL, - CRTC_TRIGB_POLARITY_SELECT); + TRIGGER_POLARITY_SELECT_LOGIC_ZERO, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_POLARITY_SELECT); set_reg_field_value(value, - 1, /* clear trigger status */ - CRTC_TRIGB_CNTL, - CRTC_TRIGB_CLEAR); + 1, /* clear trigger status */ + CRTC_TRIGB_CNTL, + CRTC_TRIGB_CLEAR); dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value); } @@ -1611,10 +1777,16 @@ bool dce110_timing_generator_did_triggered_reset_occur( struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); uint32_t value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); - - return get_reg_field_value(value, - CRTC_FORCE_COUNT_NOW_CNTL, - CRTC_FORCE_COUNT_NOW_OCCURRED) != 0; + uint32_t value1 = dm_read_reg(tg->ctx, + CRTC_REG(mmCRTC_VERT_SYNC_CONTROL)); + bool force = get_reg_field_value(value, + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_OCCURRED) != 0; + bool vert_sync = get_reg_field_value(value1, + CRTC_VERT_SYNC_CONTROL, + CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED) != 0; + + return (force || vert_sync); } /** @@ -1928,6 +2100,7 @@ static const struct timing_generator_funcs dce110_tg_funcs = { .setup_global_swap_lock = dce110_timing_generator_setup_global_swap_lock, .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger, + .enable_crtc_reset = dce110_timing_generator_enable_crtc_reset, .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger, .tear_down_global_swap_lock = dce110_timing_generator_tear_down_global_swap_lock, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index 82737dea6984..232747c7c60b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -174,6 +174,12 @@ void dce110_timing_generator_setup_global_swap_lock( void dce110_timing_generator_tear_down_global_swap_lock( struct timing_generator *tg); +/* Reset crtc position on master VSync */ +void dce110_timing_generator_enable_crtc_reset( + struct timing_generator *tg, + int source, + struct crtc_trigger_info *crtc_tp); + /* Reset slave controllers on master VSync */ void dce110_timing_generator_enable_reset_trigger( struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index adabd2ad5594..762af17485e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1304,14 +1304,15 @@ static void dcn10_enable_timing_synchronization( for (i = 1; i < group_size; i++) grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( - grouped_pipes[i]->stream_res.tg, grouped_pipes[0]->stream_res.tg->inst); - + grouped_pipes[i]->stream_res.tg, + grouped_pipes[0]->stream_res.tg->inst); DC_SYNC_INFO("Waiting for trigger\n"); /* Need to get only check 1 pipe for having reset as all the others are * synchronized. Look at last pipe programmed to reset. */ + wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg); for (i = 1; i < group_size; i++) grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( @@ -1320,6 +1321,29 @@ static void dcn10_enable_timing_synchronization( DC_SYNC_INFO("Sync complete\n"); } +static void dcn10_enable_per_frame_crtc_position_reset( + struct dc *dc, + int group_size, + struct pipe_ctx *grouped_pipes[]) +{ + struct dc_context *dc_ctx = dc->ctx; + int i; + + DC_SYNC_INFO("Setting up\n"); + for (i = 0; i < group_size; i++) + grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( + grouped_pipes[i]->stream_res.tg, + grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst, + &grouped_pipes[i]->stream->triggered_crtc_reset); + + DC_SYNC_INFO("Waiting for trigger\n"); + + for (i = 1; i < group_size; i++) + wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); + + DC_SYNC_INFO("Multi-display sync is complete\n"); +} + static void print_rq_dlg_ttu( struct dc *core_dc, struct pipe_ctx *pipe_ctx) @@ -2485,6 +2509,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .power_down = dce110_power_down, .enable_accelerated_mode = dce110_enable_accelerated_mode, .enable_timing_synchronization = dcn10_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, .update_info_frame = dce110_update_info_frame, .enable_stream = dce110_enable_stream, .disable_stream = dce110_disable_stream, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index fced178c8c79..c178cc0bd426 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -610,12 +610,28 @@ static bool tgn10_did_triggered_reset_occur( struct timing_generator *tg) { struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); - uint32_t occurred; + uint32_t occurred_force, occurred_vsync; REG_GET(OTG_FORCE_COUNT_NOW_CNTL, - OTG_FORCE_COUNT_NOW_OCCURRED, &occurred); + OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); - return occurred != 0; + REG_GET(OTG_VERT_SYNC_CONTROL, + OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); + + return occurred_vsync != 0 || occurred_force != 0; +} + +static void tgn10_disable_reset_trigger(struct timing_generator *tg) +{ + struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + + REG_WRITE(OTG_TRIGA_CNTL, 0); + + REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, + OTG_FORCE_COUNT_NOW_CLEAR, 1); + + REG_SET(OTG_VERT_SYNC_CONTROL, 0, + OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); } static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_tg_inst) @@ -652,14 +668,49 @@ static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_t OTG_FORCE_COUNT_NOW_MODE, 2); } -static void tgn10_disable_reset_trigger(struct timing_generator *tg) +void tgn10_enable_crtc_reset( + struct timing_generator *tg, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp) { struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + uint32_t falling_edge = 0; + uint32_t rising_edge = 0; - REG_WRITE(OTG_TRIGA_CNTL, 0); + switch (crtc_tp->event) { - REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, - OTG_FORCE_COUNT_NOW_CLEAR, 1); + case CRTC_EVENT_VSYNC_RISING: + rising_edge = 1; + break; + + case CRTC_EVENT_VSYNC_FALLING: + falling_edge = 1; + break; + } + + REG_SET_4(OTG_TRIGA_CNTL, 0, + /* vsync signal from selected OTG pipe based + * on OTG_TRIG_SOURCE_PIPE_SELECT setting + */ + OTG_TRIGA_SOURCE_SELECT, 20, + OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, + /* always detect falling edge */ + OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, + OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); + + switch (crtc_tp->delay) { + case TRIGGER_DELAY_NEXT_LINE: + REG_SET(OTG_VERT_SYNC_CONTROL, 0, + OTG_AUTO_FORCE_VSYNC_MODE, 1); + break; + case TRIGGER_DELAY_NEXT_PIXEL: + REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, + /* force H count to H_TOTAL and V count to V_TOTAL in + * progressive mode and V_TOTAL-1 in interlaced mode + */ + OTG_FORCE_COUNT_NOW_MODE, 2); + break; + } } static void tgn10_wait_for_state(struct timing_generator *tg, @@ -1174,6 +1225,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { .set_blank_color = tgn10_program_blank_color, .did_triggered_reset_occur = tgn10_did_triggered_reset_occur, .enable_reset_trigger = tgn10_enable_reset_trigger, + .enable_crtc_reset = tgn10_enable_crtc_reset, .disable_reset_trigger = tgn10_disable_reset_trigger, .lock = tgn10_lock, .unlock = tgn10_unlock, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index c6ab38c5b2be..75f7a01b9175 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -158,7 +158,11 @@ struct timing_generator_funcs { const struct dcp_gsl_params *gsl_params); void (*unlock)(struct timing_generator *tg); void (*lock)(struct timing_generator *tg); - void (*enable_reset_trigger)(struct timing_generator *tg, int source_tg_inst); + void (*enable_reset_trigger)(struct timing_generator *tg, + int source_tg_inst); + void (*enable_crtc_reset)(struct timing_generator *tg, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp); void (*disable_reset_trigger)(struct timing_generator *tg); void (*tear_down_global_swap_lock)(struct timing_generator *tg); void (*enable_advanced_request)(struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 8734689a9245..cebbba345889 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -114,6 +114,11 @@ struct hw_sequencer_funcs { int group_size, struct pipe_ctx *grouped_pipes[]); + void (*enable_per_frame_crtc_position_reset)( + struct dc *dc, + int group_size, + struct pipe_ctx *grouped_pipes[]); + void (*enable_display_pipe_clock_gating)( struct dc_context *ctx, bool clock_gating); -- GitLab From c1fe75c9e42c8c598a7fb810ecc4f7be258e700c Mon Sep 17 00:00:00 2001 From: Piotr Redlewski Date: Fri, 10 Nov 2017 19:28:01 +0100 Subject: [PATCH 0778/2547] drm/amd/amdgpu: fix UVD mc offsets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end. Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end. v2: move firmware size calculation into macro definition v3: align firmware size to the gpu page size Reviewed-by: Christian König Signed-off-by: Piotr Redlewski Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 4 ++++ drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +- 5 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h index 3553b92bf69a..845eea993f75 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h @@ -31,6 +31,10 @@ #define AMDGPU_UVD_SESSION_SIZE (50*1024) #define AMDGPU_UVD_FIRMWARE_OFFSET 256 +#define AMDGPU_UVD_FIRMWARE_SIZE(adev) \ + (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \ + 8) - AMDGPU_UVD_FIRMWARE_OFFSET) + struct amdgpu_uvd { struct amdgpu_bo *vcpu_bo; void *cpu_addr; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 15771a53038e..b13ae34be1c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -563,7 +563,7 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) /* programm the VCPU memory controller bits 0-27 */ addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; - size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; + size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3; WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); WREG32(mmUVD_VCPU_CACHE_SIZE0, size); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 3b29aaba783a..a4b0f1d842b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -258,7 +258,7 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) upper_32_bits(adev->uvd.gpu_addr)); offset = AMDGPU_UVD_FIRMWARE_OFFSET; - size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); + size = AMDGPU_UVD_FIRMWARE_SIZE(adev); WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); WREG32(mmUVD_VCPU_CACHE_SIZE0, size); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 0c01825a8b9e..0e8b887cf03e 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -603,7 +603,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) upper_32_bits(adev->uvd.gpu_addr)); offset = AMDGPU_UVD_FIRMWARE_OFFSET; - size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); + size = AMDGPU_UVD_FIRMWARE_SIZE(adev); WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); WREG32(mmUVD_VCPU_CACHE_SIZE0, size); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 7b77339feb1a..6d4470626d25 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -616,7 +616,7 @@ static int uvd_v7_0_resume(void *handle) */ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev) { - uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); + uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev); uint32_t offset; if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { -- GitLab From 288e46d398aa323ae9cfb735d9e1e93a9f048d64 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Sat, 11 Nov 2017 11:51:10 +0000 Subject: [PATCH 0779/2547] drm/amdgpu/virt: remove redundant variable pf2vf_ver Variable pf2vf_ver is assigned but never read, it is redundant and hence can be removed. Cleans up clang warning: drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:310:3: warning: Value stored to 'pf2vf_ver' is never read Reivewed-by: Horace Chen Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 663bf35cdce9..0769cb935318 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -318,7 +318,6 @@ int amdgpu_virt_fw_reserve_get_checksum(void *obj, void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) { - uint32_t pf2vf_ver = 0; uint32_t pf2vf_size = 0; uint32_t checksum = 0; uint32_t checkval; @@ -331,7 +330,6 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) adev->virt.fw_reserve.p_pf2vf = (struct amdgim_pf2vf_info_header *)( adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET); - pf2vf_ver = adev->virt.fw_reserve.p_pf2vf->version; AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size); AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum); AMDGPU_FW_VRAM_PF2VF_READ(adev, feature_flags, &adev->virt.gim_feature); -- GitLab From afa9104b04fc34ef23c25cb605906e7c0c7be47b Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Tue, 24 Oct 2017 14:13:16 -0400 Subject: [PATCH 0780/2547] drm/amd/display: create new function prototype update_dchub for dcn dcn version of update_dchub now uses hubbub instead of hwseq Signed-off-by: Yue Hin Lau Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 +++++- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 762af17485e0..24c840405c8d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2493,7 +2493,10 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) } } - +void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data) +{ + hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data); +} static const struct hw_sequencer_funcs dcn10_funcs = { .program_gamut_remap = program_gamut_remap, @@ -2503,6 +2506,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .apply_ctx_for_surface = dcn10_apply_ctx_for_surface, .set_plane_config = set_plane_config, .update_plane_addr = dcn10_update_plane_addr, + .update_dchub = dcn10_update_dchub, .update_pending_status = dcn10_update_pending_status, .set_input_transfer_func = dcn10_set_input_transfer_func, .set_output_transfer_func = dcn10_set_output_transfer_func, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index dd834fdf7ce7..340ff1158c10 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1461,7 +1461,7 @@ static bool construct( pool->base.hubbub = dcn10_hubbub_create(ctx); if (pool->base.hubbub == NULL) { BREAK_TO_DEBUGGER(); - dm_error("DC: failed to create mpc!\n"); + dm_error("DC: failed to create hubbub!\n"); goto fail; } -- GitLab From ea00f2979bc5a8c3389db0c88335a077d59eb4b6 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Tue, 24 Oct 2017 15:16:38 -0400 Subject: [PATCH 0781/2547] drm/amd/display: function renaming for hubbub following the naming convention with correct prefix Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 16 ++---- .../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 9 +-- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 55 ++++++++++++------- 3 files changed, 43 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c index f60e90cff1bb..b1c9ba241ba4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c @@ -75,7 +75,7 @@ void hubbub1_wm_read_state(struct hubbub *hubbub, s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); } -void verify_allow_pstate_change_high( +bool hubbub1_verify_allow_pstate_change_high( struct hubbub *hubbub) { /* pstate latency is ~20us so if we wait over 40us and pstate allow @@ -89,7 +89,6 @@ void verify_allow_pstate_change_high( static unsigned int pstate_wait_expected_timeout_us = 40; static unsigned int max_sampled_pstate_wait_us; /* data collection */ static bool forced_pstate_allow; /* help with revert wa */ - static bool should_log_hw_state; /* prevent hw state log by default */ unsigned int debug_index = 0x7; unsigned int debug_data; @@ -140,7 +139,7 @@ void verify_allow_pstate_change_high( "pstate took longer than expected ~%dus\n", i); - return; + return false; } if (max_sampled_pstate_wait_us < i) max_sampled_pstate_wait_us = i; @@ -156,14 +155,11 @@ void verify_allow_pstate_change_high( DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1); forced_pstate_allow = true; - if (should_log_hw_state) { - dcn10_log_hw_state(hubbub->ctx->dc); - } - dm_logger_write(hubbub->ctx->logger, LOG_WARNING, "pstate TEST_DEBUG_DATA: 0x%X\n", debug_data); - BREAK_TO_DEBUGGER(); + + return true; } static uint32_t convert_and_clamp( @@ -182,7 +178,7 @@ static uint32_t convert_and_clamp( } -void program_watermarks( +void hubbub1_program_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz) @@ -472,7 +468,7 @@ void hubbub1_update_dchub( dh_data->dchub_info_valid = false; } -void toggle_watermark_change_req(struct hubbub *hubbub) +void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub) { uint32_t watermark_change_req; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h index e9abb881bd3f..d5c97844312f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h @@ -191,18 +191,15 @@ void hubbub1_update_dchub( struct hubbub *hubbub, struct dchub_init_data *dh_data); -void dcn10_log_hw_state( - struct dc *dc); - -void verify_allow_pstate_change_high( +bool hubbub1_verify_allow_pstate_change_high( struct hubbub *hubbub); -void program_watermarks( +void hubbub1_program_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz); -void toggle_watermark_change_req( +void hubbub1_toggle_watermark_change_req( struct hubbub *hubbub); void hubbub1_wm_read_state(struct hubbub *hubbub, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 24c840405c8d..fe236a9fd147 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -544,6 +544,19 @@ static void reset_back_end_for_pipe( pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); } +void dcn10_verify_allow_pstate_change_high(struct dc *dc) +{ + static bool should_log_hw_state; /* prevent hw state log by default */ + + if (hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) { + if (should_log_hw_state) { + dcn10_log_hw_state(dc); + } + + BREAK_TO_DEBUGGER(); + } +} + /* trigger HW to start disconnect plane from stream on the next vsync */ static void plane_atomic_disconnect(struct dc *dc, int fe_idx) @@ -571,10 +584,10 @@ static void plane_atomic_disconnect(struct dc *dc, return; if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); hubp->funcs->dcc_control(hubp, false, false); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree), dc->res_pool->opps[opp_id]->inst, fe_idx); @@ -602,7 +615,7 @@ static void plane_atomic_disable(struct dc *dc, hubp->funcs->set_blank(hubp, true); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); REG_UPDATE(HUBP_CLK_CNTL[fe_idx], HUBP_CLOCK_ENABLE, 0); @@ -614,7 +627,7 @@ static void plane_atomic_disable(struct dc *dc, OPP_PIPE_CLOCK_EN, 0); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); } static void reset_front_end( @@ -638,7 +651,7 @@ static void reset_front_end( tg->funcs->unlock(tg); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], @@ -670,7 +683,7 @@ static void dcn10_power_down_fe(struct dc *dc, int fe_idx) "Power gated front end %d\n", fe_idx); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); } static void dcn10_init_hw(struct dc *dc) @@ -1243,7 +1256,7 @@ static void dcn10_pipe_control_lock( return; if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); if (lock) pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); @@ -1251,7 +1264,7 @@ static void dcn10_pipe_control_lock( pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); } static bool wait_for_reset_trigger_to_occur( @@ -1475,7 +1488,7 @@ static void dcn10_power_on_fe( struct dce_hwseq *hws = dc->hwseq; if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); } power_on_plane(dc->hwseq, @@ -1527,7 +1540,7 @@ static void dcn10_power_on_fe( } if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); } } @@ -1960,11 +1973,11 @@ static void program_all_pipe_in_tree( * this OTG. this is done only one time. */ /* watermark is for all pipes */ - program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, ref_clk_mhz); + hubbub1_program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, ref_clk_mhz); if (dc->debug.sanity_checks) { /* pstate stuck check after watermark update */ - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); } pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); @@ -1995,7 +2008,7 @@ static void program_all_pipe_in_tree( * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have * both driver and fw accessing same register */ - toggle_watermark_change_req(dc->res_pool->hubbub); + hubbub1_toggle_watermark_change_req(dc->res_pool->hubbub); update_dchubp_dpp(dc, pipe_ctx, context); @@ -2018,7 +2031,7 @@ static void program_all_pipe_in_tree( if (dc->debug.sanity_checks) { /* pstate stuck check after each pipe is programmed */ - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); } if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) @@ -2085,7 +2098,7 @@ static void dcn10_apply_ctx_for_surface( int i, be_idx; if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); be_idx = -1; for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -2168,7 +2181,7 @@ static void dcn10_apply_ctx_for_surface( hubp->funcs->hubp_disconnect(hubp); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); old_pipe_ctx->top_pipe = NULL; old_pipe_ctx->bottom_pipe = NULL; @@ -2246,7 +2259,7 @@ static void dcn10_apply_ctx_for_surface( ); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); } static void dcn10_set_bandwidth( @@ -2260,7 +2273,7 @@ static void dcn10_set_bandwidth( struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu; if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); } if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) @@ -2316,7 +2329,7 @@ static void dcn10_set_bandwidth( dcn10_pplib_apply_display_requirements(dc, context); if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); } /* need to fix this function. not doing the right thing here */ @@ -2441,7 +2454,7 @@ static void dcn10_wait_for_mpcc_disconnect( int i; if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); } if (!pipe_ctx->stream_res.opp) @@ -2459,7 +2472,7 @@ static void dcn10_wait_for_mpcc_disconnect( } if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->res_pool->hubbub); + dcn10_verify_allow_pstate_change_high(dc); } } -- GitLab From c2a5b5008a92efdf816cf3c3b9f37aa8d6f8b54e Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 25 Oct 2017 20:30:46 -0400 Subject: [PATCH 0782/2547] drm/amd/display: Do post_update_surfaces on new state Signed-off-by: Charlene Liu Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 507b1171d65f..01ec1edd1c69 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1469,10 +1469,7 @@ void dc_commit_updates_for_stream(struct dc *dc, stream_update, update_type, context); - - if (update_type >= UPDATE_TYPE_FULL) - dc_post_update_surfaces_to_stream(dc); - + /*update current_State*/ if (dc->current_state != context) { struct dc_state *old = dc->current_state; @@ -1481,6 +1478,9 @@ void dc_commit_updates_for_stream(struct dc *dc, dc_release_state(old); } + /*let's use current_state to update watermark etc*/ + if (update_type >= UPDATE_TYPE_FULL) + dc_post_update_surfaces_to_stream(dc); return; -- GitLab From e70fe3b1f06fb12c5fb181c06bab745d0bad3fa5 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Thu, 26 Oct 2017 11:29:54 -0400 Subject: [PATCH 0783/2547] drm/amd/display: hubbub function flipping true and false no logic change Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c index b1c9ba241ba4..23c4573f7a34 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c @@ -139,7 +139,7 @@ bool hubbub1_verify_allow_pstate_change_high( "pstate took longer than expected ~%dus\n", i); - return false; + return true; } if (max_sampled_pstate_wait_us < i) max_sampled_pstate_wait_us = i; @@ -159,7 +159,7 @@ bool hubbub1_verify_allow_pstate_change_high( "pstate TEST_DEBUG_DATA: 0x%X\n", debug_data); - return true; + return false; } static uint32_t convert_and_clamp( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index fe236a9fd147..90f1f54ade61 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -548,7 +548,7 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc) { static bool should_log_hw_state; /* prevent hw state log by default */ - if (hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) { + if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) { if (should_log_hw_state) { dcn10_log_hw_state(dc); } -- GitLab From f4dd6dca57bc82f00684745c871d8b6f87367896 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Wed, 25 Oct 2017 23:28:38 -0400 Subject: [PATCH 0784/2547] drm/amd/display: dal 3.1.11 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index a51a9c748c1a..79e2ddbc3399 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.10" +#define DC_VER "3.1.11" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From bc71a20db2858739724715e5096a98692320e69f Mon Sep 17 00:00:00 2001 From: Eric Bernstein Date: Thu, 26 Oct 2017 18:13:36 -0400 Subject: [PATCH 0785/2547] drm/amd/display: Call ipp_program_bias_and_scale only if available Also move some register definitions to common DCN regs. Signed-off-by: Eric Bernstein Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 16 ++++++++-------- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 3a6ebd14eea2..880e366568a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -73,6 +73,9 @@ SRI(RECOUT_START, DSCL, id), \ SRI(RECOUT_SIZE, DSCL, id), \ SRI(OBUF_CONTROL, DSCL, id), \ + SRI(CM_ICSC_CONTROL, CM, id), \ + SRI(CM_ICSC_C11_C12, CM, id), \ + SRI(CM_ICSC_C33_C34, CM, id), \ SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \ SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \ SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \ @@ -124,9 +127,6 @@ SRI(CM_OCSC_CONTROL, CM, id), \ SRI(CM_OCSC_C11_C12, CM, id), \ SRI(CM_OCSC_C33_C34, CM, id), \ - SRI(CM_ICSC_CONTROL, CM, id), \ - SRI(CM_ICSC_C11_C12, CM, id), \ - SRI(CM_ICSC_C33_C34, CM, id), \ SRI(CM_BNS_VALUES_R, CM, id), \ SRI(CM_BNS_VALUES_G, CM, id), \ SRI(CM_BNS_VALUES_B, CM, id), \ @@ -239,6 +239,11 @@ TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \ + TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ + TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ + TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ + TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ + TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \ TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \ @@ -327,11 +332,6 @@ TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \ TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \ - TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ - TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ - TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ - TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ - TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \ TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \ TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 90f1f54ade61..75feb4788b6b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1903,7 +1903,8 @@ static void update_dchubp_dpp( //set scale and bias registers build_prescale_params(&bns_params, plane_state); - dpp->funcs->ipp_program_bias_and_scale(dpp, &bns_params); + if (dpp->funcs->ipp_program_bias_and_scale) + dpp->funcs->ipp_program_bias_and_scale(dpp, &bns_params); mpcc_cfg.dpp_id = hubp->inst; mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst; -- GitLab From 8a4cf458a84dfd3ed87ed69c0fdf7b39f20e1c06 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Thu, 26 Oct 2017 16:30:44 -0400 Subject: [PATCH 0786/2547] drm/amd/display: Only update dchub if hubbub is available Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 75feb4788b6b..9b37f65f86f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2509,7 +2509,8 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data) { - hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data); + if (hws->ctx->dc->res_pool->hubbub != NULL) + hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data); } static const struct hw_sequencer_funcs dcn10_funcs = { -- GitLab From 7d8d90d84fe8fd73d09a1efa26c22d4fe902a05e Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Mon, 23 Oct 2017 12:06:54 -0400 Subject: [PATCH 0787/2547] drm/amd/display: get remote dpcd caps for timing validation Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 28 ++++++++++++++++++- 4 files changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index e27ed4a45265..80d9153334dc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1869,7 +1869,7 @@ enum dc_status dc_link_validate_mode_timing( const struct dc_crtc_timing *timing) { uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk; - struct dc_dongle_caps *dongle_caps = &link->link_status.dpcd_caps->dongle_caps; + struct dc_dongle_caps *dongle_caps = &link->dpcd_caps.dongle_caps; /* A hack to avoid failing any modes for EDID override feature on * topology change such as lower quality cable for DP or different dongle diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index e6bf05d76a94..b2dcc462afe2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2127,7 +2127,7 @@ static void get_active_converter_info( union dwnstream_port_caps_byte3_hdmi hdmi_caps = {.raw = det_caps[3] }; - union dwnstream_port_caps_byte1 + union dwnstream_port_caps_byte2 hdmi_color_caps = {.raw = det_caps[2] }; link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk = det_caps[1] * 25000; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 79e2ddbc3399..ee05b8ee3785 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1031,6 +1031,7 @@ struct dc_sink { /* private to dc_sink.c */ struct kref refcount; + }; void dc_sink_retain(struct dc_sink *sink); diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 77e2de69cca3..2726b02e006b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -255,7 +255,7 @@ enum dpcd_downstream_port_detailed_type { DOWN_STREAM_DETAILED_DP_PLUS_PLUS }; -union dwnstream_port_caps_byte1 { +union dwnstream_port_caps_byte2 { struct { uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; uint8_t RESERVED:6; @@ -298,6 +298,32 @@ union dwnstream_port_caps_byte3_hdmi { /*4-byte structure for detailed capabilities of a down-stream port (DP-to-TMDS converter).*/ +union dwnstream_portxcaps { + struct { + union dwnstream_port_caps_byte0 byte0; + unsigned char max_TMDS_clock; //byte1 + union dwnstream_port_caps_byte2 byte2; + + union { + union dwnstream_port_caps_byte3_dvi byteDVI; + union dwnstream_port_caps_byte3_hdmi byteHDMI; + } byte3; + } bytes; + + unsigned char raw[4]; +}; + +union downstream_port { + struct { + unsigned char present:1; + unsigned char type:2; + unsigned char format_conv:1; + unsigned char detailed_caps:1; + unsigned char reserved:3; + } bits; + unsigned char raw; +}; + union sink_status { struct { -- GitLab From 38614212522d07835050c15eb877b6bd68bcebca Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Mon, 23 Oct 2017 15:57:52 -0400 Subject: [PATCH 0788/2547] drm/amd/display: Enalbe blank data double buffer after mpc disconnected. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../display/dc/dcn10/dcn10_timing_generator.c | 19 ++++++++++++++----- .../amd/display/dc/inc/hw/timing_generator.h | 2 ++ 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index c178cc0bd426..5d1edb017b1c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -290,6 +290,16 @@ static void tgn10_program_timing( } +static void tgn10_set_blank_data_double_buffer(struct timing_generator *tg, bool enable) +{ + struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + + uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; + + REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, + OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); +} + /** * unblank_crtc * Call ASIC Control Object to UnBlank CRTC. @@ -306,8 +316,7 @@ static void tgn10_unblank_crtc(struct timing_generator *tg) * this check will be removed. */ if (vertical_interrupt_enable) - REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, - OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 1); + tgn10_set_blank_data_double_buffer(tg, true); REG_UPDATE_2(OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, 0, @@ -334,8 +343,7 @@ static void tgn10_blank_crtc(struct timing_generator *tg) OTG_BLANK_DATA_EN, 1, 1, 100000); - REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, - OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 0); + tgn10_set_blank_data_double_buffer(tg, false); } static void tgn10_set_blank(struct timing_generator *tg, @@ -1234,7 +1242,8 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { .set_static_screen_control = tgn10_set_static_screen_control, .set_test_pattern = tgn10_set_test_pattern, .program_stereo = tgn10_program_stereo, - .is_stereo_left_eye = tgn10_is_stereo_left_eye + .is_stereo_left_eye = tgn10_is_stereo_left_eye, + .set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer }; void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 75f7a01b9175..83f0b1d49e8b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -182,6 +182,8 @@ struct timing_generator_funcs { void (*program_stereo)(struct timing_generator *tg, const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); bool (*is_stereo_left_eye)(struct timing_generator *tg); + + void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable); }; #endif -- GitLab From 073a45e824db22f47940e203dc63ad081e53e9df Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Mon, 30 Oct 2017 13:35:04 -0400 Subject: [PATCH 0789/2547] drm/amd/display: Add tg_init interface. Clear OPTC underflow status when init_hw. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++ .../drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 10 +++++++++- .../drm/amd/display/dc/dcn10/dcn10_timing_generator.h | 2 ++ .../gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 2 ++ 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 9b37f65f86f5..bb4446eecb39 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -742,6 +742,8 @@ static void dcn10_init_hw(struct dc *dc) hwss_wait_for_blank_complete(tg); dcn10_power_down_fe(dc, i); + + tg->funcs->tg_init(tg); } for (i = 0; i < dc->res_pool->audio_count; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index 5d1edb017b1c..819c4edd77a7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -1213,6 +1213,13 @@ void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); } +static void tgn10_tg_init(struct timing_generator *tg) +{ + struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + + tgn10_set_blank_data_double_buffer(tg, true); + REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); +} static const struct timing_generator_funcs dcn10_tg_funcs = { .validate_timing = tgn10_validate_timing, @@ -1243,7 +1250,8 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { .set_test_pattern = tgn10_set_test_pattern, .program_stereo = tgn10_program_stereo, .is_stereo_left_eye = tgn10_is_stereo_left_eye, - .set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer + .set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer, + .tg_init = tgn10_tg_init, }; void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h index 395820606013..bb1cbfdc3554 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h @@ -210,6 +210,7 @@ struct dcn_tg_registers { SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\ SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\ SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ @@ -330,6 +331,7 @@ struct dcn_tg_registers { type OPTC_SRC_SEL;\ type OPTC_SEG0_SRC_SEL;\ type OPTC_UNDERFLOW_OCCURRED_STATUS;\ + type OPTC_UNDERFLOW_CLEAR;\ type OPPBUF_ACTIVE_WIDTH;\ type OPPBUF_3D_VACT_SPACE1_SIZE;\ type VTG0_ENABLE;\ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 83f0b1d49e8b..f77dca87cbbc 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -184,6 +184,8 @@ struct timing_generator_funcs { bool (*is_stereo_left_eye)(struct timing_generator *tg); void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable); + + void (*tg_init)(struct timing_generator *tg); }; #endif -- GitLab From 83c3e57bc4703c5955da9942d7e57bc26465c770 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 30 Oct 2017 15:53:40 -0400 Subject: [PATCH 0790/2547] drm/amd/display: Both timing_sync and multisync need stream_count > 1 Previous code threw a warning about misleading indentation Signed-off-by: Harry Wentland Reviewed-by: Mikita Lipski Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 01ec1edd1c69..f3496881caf4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -913,9 +913,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c } result = dc->hwss.apply_ctx_to_hw(dc, context); - if (context->stream_count > 1) + if (context->stream_count > 1) { enable_timing_multisync(dc, context); program_timing_sync(dc, context); + } dc_enable_stereo(dc, context, dc_streams, context->stream_count); -- GitLab From 069d418f412ec4b33056dc7d84b63c80c2e50abf Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Tue, 26 Sep 2017 19:45:43 -0400 Subject: [PATCH 0791/2547] drm/amd/display: Don't use dc_link in link_encoder dc_link is at a higher level than link_encoder, and we only want higher-level components to be able to access lower-level ones, not the other way around. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- .../drm/amd/display/dc/core/dc_link_hwss.c | 11 ++--- .../drm/amd/display/dc/dce/dce_link_encoder.c | 34 ++++++-------- .../drm/amd/display/dc/dce/dce_link_encoder.h | 5 +- .../display/dc/dce110/dce110_hw_sequencer.c | 46 +++++++++++-------- .../display/dc/dce110/dce110_hw_sequencer.h | 4 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++ .../drm/amd/display/dc/inc/hw/link_encoder.h | 2 +- .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- .../display/dc/virtual/virtual_link_encoder.c | 3 +- 10 files changed, 57 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 80d9153334dc..7b0e43c0685c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1798,7 +1798,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal) else dp_disable_link_phy_mst(link, signal); } else - link->link_enc->funcs->disable_output(link->link_enc, signal, link); + link->link_enc->funcs->disable_output(link->link_enc, signal); } bool dp_active_dongle_validate_timing( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 9a33b471270a..f2902569be2e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -89,7 +89,7 @@ void dp_enable_link_phy( if (dc_is_dp_sst_signal(signal)) { if (signal == SIGNAL_TYPE_EDP) { - link->dc->hwss.edp_power_control(link->link_enc, true); + link->dc->hwss.edp_power_control(link, true); link_enc->funcs->enable_dp_output( link_enc, link_settings, @@ -140,10 +140,10 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) if (signal == SIGNAL_TYPE_EDP) { link->dc->hwss.edp_backlight_control(link, false); edp_receiver_ready_T9(link); - link->link_enc->funcs->disable_output(link->link_enc, signal, link); - link->dc->hwss.edp_power_control(link->link_enc, false); + link->link_enc->funcs->disable_output(link->link_enc, signal); + link->dc->hwss.edp_power_control(link, false); } else - link->link_enc->funcs->disable_output(link->link_enc, signal, link); + link->link_enc->funcs->disable_output(link->link_enc, signal); /* Clear current link setting.*/ memset(&link->cur_link_settings, 0, @@ -286,8 +286,7 @@ void dp_retrain_link_dp_test(struct dc_link *link, link->link_enc->funcs->disable_output( link->link_enc, - SIGNAL_TYPE_DISPLAY_PORT, - link); + SIGNAL_TYPE_DISPLAY_PORT); /* Clear current link setting. */ memset(&link->cur_link_settings, 0, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index fe88852b4774..bad70c6b3aad 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -845,8 +845,6 @@ void dce110_link_encoder_hw_init( ASSERT(result == BP_RESULT_OK); - } else if (enc110->base.connector.id == CONNECTOR_ID_EDP) { - ctx->dc->hwss.edp_power_control(enc, true); } aux_initialize(enc110); @@ -1033,8 +1031,7 @@ void dce110_link_encoder_enable_dp_mst_output( */ void dce110_link_encoder_disable_output( struct link_encoder *enc, - enum signal_type signal, - struct dc_link *link) + enum signal_type signal) { struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); struct dc_context *ctx = enc110->base.ctx; @@ -1045,8 +1042,6 @@ void dce110_link_encoder_disable_output( /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ return; } - if (enc110->base.connector.id == CONNECTOR_ID_EDP) - ctx->dc->hwss.edp_backlight_control(link, false); /* Power-down RX and disable GPU PHY should be paired. * Disabling PHY without powering down RX may cause * symbol lock loss, on which we will get DP Sink interrupt. */ @@ -1078,19 +1073,20 @@ void dce110_link_encoder_disable_output( if (dc_is_dp_signal(signal)) link_encoder_disable(enc110); - if (enc110->base.connector.id == CONNECTOR_ID_EDP) { - /* power down eDP panel */ - /* TODO: Power control cause regression, we should implement - * it properly, for now just comment it. - * - * link_encoder_edp_wait_for_hpd_ready( - link_enc, - link_enc->connector, - false); - - * link_encoder_edp_power_control( - link_enc, false); */ - } + /* + * TODO: Power control cause regression, we should implement + * it properly, for now just comment it. + */ +// if (enc110->base.connector.id == CONNECTOR_ID_EDP) { +// /* power down eDP panel */ +// link_encoder_edp_wait_for_hpd_ready( +// enc, +// enc->connector, +// false); +// +// link_encoder_edp_power_control( +// enc, false); +// } } void dce110_link_encoder_dp_set_lane_settings( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 494067dedd03..8ca9afe47a2b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -228,9 +228,8 @@ void dce110_link_encoder_enable_dp_mst_output( /* disable PHY output */ void dce110_link_encoder_disable_output( - struct link_encoder *link_enc, - enum signal_type signal, - struct dc_link *link); + struct link_encoder *enc, + enum signal_type signal); /* set DP lane settings */ void dce110_link_encoder_dp_set_lane_settings( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 868040a4f7ff..44315aef445b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -814,11 +814,11 @@ static enum bp_result link_transmitter_control( * eDP only. */ void hwss_edp_wait_for_hpd_ready( - struct link_encoder *enc, - bool power_up) + struct dc_link *link, + bool power_up) { - struct dc_context *ctx = enc->ctx; - struct graphics_object_id connector = enc->connector; + struct dc_context *ctx = link->ctx; + struct graphics_object_id connector = link->link_enc->connector; struct gpio *hpd; bool edp_hpd_high = false; uint32_t time_elapsed = 0; @@ -882,16 +882,16 @@ void hwss_edp_wait_for_hpd_ready( } void hwss_edp_power_control( - struct link_encoder *enc, - bool power_up) + struct dc_link *link, + bool power_up) { - struct dc_context *ctx = enc->ctx; + struct dc_context *ctx = link->ctx; struct dce_hwseq *hwseq = ctx->dc->hwseq; struct bp_transmitter_control cntl = { 0 }; enum bp_result bp_result; - if (dal_graphics_object_id_get_connector_id(enc->connector) + if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) != CONNECTOR_ID_EDP) { BREAK_TO_DEBUGGER(); return; @@ -907,11 +907,11 @@ void hwss_edp_power_control( cntl.action = power_up ? TRANSMITTER_CONTROL_POWER_ON : TRANSMITTER_CONTROL_POWER_OFF; - cntl.transmitter = enc->transmitter; - cntl.connector_obj_id = enc->connector; + cntl.transmitter = link->link_enc->transmitter; + cntl.connector_obj_id = link->link_enc->connector; cntl.coherent = false; cntl.lanes_number = LANE_COUNT_FOUR; - cntl.hpd_sel = enc->hpd_source; + cntl.hpd_sel = link->link_enc->hpd_source; bp_result = link_transmitter_control(ctx->dc_bios, &cntl); @@ -925,7 +925,7 @@ void hwss_edp_power_control( __func__, (power_up ? "On":"Off")); } - hwss_edp_wait_for_hpd_ready(enc, true); + hwss_edp_wait_for_hpd_ready(link, true); } /*todo: cloned in stream enc, fix*/ @@ -934,14 +934,14 @@ void hwss_edp_power_control( * eDP only. Control the backlight of the eDP panel */ void hwss_edp_backlight_control( - struct dc_link *link, - bool enable) + struct dc_link *link, + bool enable) { - struct dce_hwseq *hws = link->dc->hwseq; - struct dc_context *ctx = link->dc->ctx; + struct dc_context *ctx = link->ctx; + struct dce_hwseq *hws = ctx->dc->hwseq; struct bp_transmitter_control cntl = { 0 }; - if (dal_graphics_object_id_get_connector_id(link->link_id) + if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) != CONNECTOR_ID_EDP) { BREAK_TO_DEBUGGER(); return; @@ -982,7 +982,7 @@ void hwss_edp_backlight_control( * Enable it in the future if necessary. */ /* dc_service_sleep_in_milliseconds(50); */ - link_transmitter_control(link->dc->ctx->dc_bios, &cntl); + link_transmitter_control(ctx->dc_bios, &cntl); } void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) @@ -1396,12 +1396,14 @@ static void power_down_encoders(struct dc *dc) if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) dp_receiver_power_ctrl(dc->links[i], false); - if (connector_id == CONNECTOR_ID_EDP) + if (connector_id == CONNECTOR_ID_EDP) { signal = SIGNAL_TYPE_EDP; + hwss_edp_backlight_control(dc->links[i], false); + } } dc->links[i]->link_enc->funcs->disable_output( - dc->links[i]->link_enc, signal, dc->links[i]); + dc->links[i]->link_enc, signal); } } @@ -2541,6 +2543,10 @@ static void init_hw(struct dc *dc) * required signal (which may be different from the * default signal on connector). */ struct dc_link *link = dc->links[i]; + + if (link->link_enc->connector.id == CONNECTOR_ID_EDP) + dc->hwss.edp_power_control(link, true); + link->link_enc->funcs->hw_init(link->link_enc); } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index 4d72bb99be93..2dd6ac637572 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -70,8 +70,8 @@ uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context); void dp_receiver_power_ctrl(struct dc_link *link, bool on); void hwss_edp_power_control( - struct link_encoder *enc, - bool power_up); + struct dc_link *link, + bool power_up); void hwss_edp_backlight_control( struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index bb4446eecb39..43d4bfd47ec8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -723,6 +723,9 @@ static void dcn10_init_hw(struct dc *dc) */ struct dc_link *link = dc->links[i]; + if (link->link_enc->connector.id == CONNECTOR_ID_EDP) + dc->hwss.edp_power_control(link, true); + link->link_enc->funcs->hw_init(link->link_enc); } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 3d33bcda7059..8a08f0a97f94 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -111,7 +111,7 @@ struct link_encoder_funcs { const struct dc_link_settings *link_settings, enum clock_source_id clock_source); void (*disable_output)(struct link_encoder *link_enc, - enum signal_type signal, struct dc_link *link); + enum signal_type signal); void (*dp_set_lane_settings)(struct link_encoder *enc, const struct link_training_settings *link_settings); void (*dp_set_phy_pattern)(struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index cebbba345889..f3c5468854bd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -184,7 +184,7 @@ struct hw_sequencer_funcs { void (*ready_shared_resources)(struct dc *dc, struct dc_state *context); void (*optimize_shared_resources)(struct dc *dc); void (*edp_power_control)( - struct link_encoder *enc, + struct dc_link *link, bool enable); void (*edp_backlight_control)( struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index 88c2bde3f039..57a54a7b89e5 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -58,8 +58,7 @@ static void virtual_link_encoder_enable_dp_mst_output( static void virtual_link_encoder_disable_output( struct link_encoder *link_enc, - enum signal_type signal, - struct dc_link *link) {} + enum signal_type signal) {} static void virtual_link_encoder_dp_set_lane_settings( struct link_encoder *enc, -- GitLab From 6334ac93a1e1ff8b99dac98bb7ef790b5786ea3c Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Fri, 27 Oct 2017 17:55:03 -0400 Subject: [PATCH 0792/2547] drm/amd/display: cache pwl params and scl_data to avoid extra programming This saves us about 5000 reg writes per full update. This translates to about 40000 writes over the course of single eDP bootup. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 41 ++++++++----------- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 6 +-- .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 3 ++ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 ++--- drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 8 ++-- 5 files changed, 30 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index c5f4d5caf976..e9cf9d1514eb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -178,32 +178,14 @@ void dpp_reset(struct dpp *dpp_base) dpp->filter_h = NULL; dpp->filter_v = NULL; - /* set boundary mode to 0 */ - REG_SET(DSCL_CONTROL, 0, SCL_BOUNDARY_MODE, 0); + memset(&dpp->scl_data, 0, sizeof(dpp->scl_data)); + memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data)); } static void dpp1_cm_set_regamma_pwl( - struct dpp *dpp_base, const struct pwl_params *params) -{ - struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); - - dpp1_cm_power_on_regamma_lut(dpp_base, true); - dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); - - if (dpp->is_write_to_ram_a_safe) - dpp1_cm_program_regamma_luta_settings(dpp_base, params); - else - dpp1_cm_program_regamma_lutb_settings(dpp_base, params); - - dpp1_cm_program_regamma_lut( - dpp_base, params->rgb_resulted, params->hw_points_num); -} - -static void dpp1_cm_set_regamma_mode( - struct dpp *dpp_base, - enum opp_regamma mode) + struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); uint32_t re_mode = 0; @@ -221,13 +203,27 @@ static void dpp1_cm_set_regamma_mode( re_mode = 2; break; case OPP_REGAMMA_USER: + if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0) + return; + + dpp1_cm_power_on_regamma_lut(dpp_base, true); + dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); + + if (dpp->is_write_to_ram_a_safe) + dpp1_cm_program_regamma_luta_settings(dpp_base, params); + else + dpp1_cm_program_regamma_lutb_settings(dpp_base, params); + + dpp1_cm_program_regamma_lut( + dpp_base, params->rgb_resulted, params->hw_points_num); + dpp->pwl_data = *params; + re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4; dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe; break; default: break; } - REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); REG_UPDATE_2(OBUF_CONTROL, OBUF_BYPASS, obuf_bypass, @@ -454,7 +450,6 @@ static const struct dpp_funcs dcn10_dpp_funcs = { .opp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings, .opp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings, .opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl, - .opp_set_regamma_mode = dpp1_cm_set_regamma_mode, .ipp_program_bias_and_scale = dpp1_program_bias_and_scale, .ipp_set_degamma = dpp1_set_degamma, .ipp_program_input_lut = dpp1_program_input_lut, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 880e366568a3..8b894ebc4e17 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -54,7 +54,6 @@ SRI(LB_MEMORY_CTRL, DSCL, id), \ SRI(DSCL_AUTOCAL, DSCL, id), \ SRI(SCL_BLACK_OFFSET, DSCL, id), \ - SRI(DSCL_CONTROL, DSCL, id), \ SRI(SCL_TAP_CONTROL, DSCL, id), \ SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \ SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \ @@ -194,7 +193,6 @@ TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\ TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\ TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\ - TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\ TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\ TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\ TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\ @@ -440,7 +438,6 @@ type AUTOCAL_PIPE_ID; \ type SCL_BLACK_OFFSET_RGB_Y; \ type SCL_BLACK_OFFSET_CBCR; \ - type SCL_BOUNDARY_MODE; \ type SCL_V_NUM_TAPS; \ type SCL_H_NUM_TAPS; \ type SCL_V_NUM_TAPS_C; \ @@ -1038,7 +1035,6 @@ struct dcn_dpp_registers { uint32_t LB_MEMORY_CTRL; uint32_t DSCL_AUTOCAL; uint32_t SCL_BLACK_OFFSET; - uint32_t DSCL_CONTROL; uint32_t SCL_TAP_CONTROL; uint32_t SCL_COEF_RAM_TAP_SELECT; uint32_t SCL_COEF_RAM_TAP_DATA; @@ -1284,6 +1280,8 @@ struct dcn10_dpp { int lb_memory_size; int lb_bits_per_entry; bool is_write_to_ram_a_safe; + struct scaler_data scl_data; + struct pwl_params pwl_data; }; enum dcn10_input_csc_select { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c index cbad36410b32..242a568294e2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c @@ -648,6 +648,8 @@ void dpp1_dscl_set_scaler_manual_scale( bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN && scl_data->format <= PIXEL_FORMAT_VIDEO_END; + if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) + return; /* Recout */ dpp1_dscl_set_recout(dpp, &scl_data->recout); @@ -699,4 +701,5 @@ void dpp1_dscl_set_scaler_manual_scale( SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1); dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr); + dpp->scl_data = *scl_data; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 43d4bfd47ec8..7bc88f423b3e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1235,13 +1235,12 @@ static bool dcn10_set_output_transfer_func( TF_TYPE_PREDEFINED && stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { - dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_SRGB); + dpp->funcs->opp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB); } else if (dcn10_translate_regamma_to_hw_format( stream->out_transfer_func, &dpp->regamma_params)) { - dpp->funcs->opp_program_regamma_pwl(dpp, &dpp->regamma_params); - dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_USER); + dpp->funcs->opp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER); } else { - dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_BYPASS); + dpp->funcs->opp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS); } return true; @@ -2118,8 +2117,7 @@ static void dcn10_apply_ctx_for_surface( if (num_planes == 0) { for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { - struct pipe_ctx *old_pipe_ctx = - &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) { old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index 6eca95931ee1..71078d184289 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -92,11 +92,9 @@ struct dpp_funcs { const struct pwl_params *params); void (*opp_program_regamma_pwl)( - struct dpp *dpp, const struct pwl_params *params); - - void (*opp_set_regamma_mode)( - struct dpp *dpp_base, - enum opp_regamma mode); + struct dpp *dpp, + const struct pwl_params *params, + enum opp_regamma mode); void (*ipp_program_bias_and_scale)( struct dpp *dpp, -- GitLab From 63340ae9a612063975d661369d07bae499e5e8ba Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Tue, 31 Oct 2017 13:51:40 -0400 Subject: [PATCH 0793/2547] drm/amd/display: dal 3.1.12 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ee05b8ee3785..cb1e39288fa3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.11" +#define DC_VER "3.1.12" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From 6d56c5733282adb608795f1afe763988ba035218 Mon Sep 17 00:00:00 2001 From: Eric Bernstein Date: Tue, 31 Oct 2017 11:52:25 -0400 Subject: [PATCH 0794/2547] drm/amd/display: Add OPP DPG blank function Added a function to blank data using OPP DPG. Clean up code to prepare for pseudocode review with HW. Signed-off-by: Eric Bernstein Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 62 ++++++++++++------- .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 45 ++------------ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 6 ++ 3 files changed, 51 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index a136f70b7a3c..71385a004f52 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -38,6 +38,24 @@ oppn10->base.ctx +enum dpg_mode { + /* RGB colour block mode */ + DPG_MODE_RGB_COLOUR_BLOCK, + /* YCbCr-601 colour block mode */ + DPG_MODE_YCBCR_601_COLOUR_BLOCK, + /* YCbCr-709 colour block mode */ + DPG_MODE_YCBCR_709_COLOUR_BLOCK, + /* Vertical bar mode */ + DPG_MODE_VERTICAL_BAR, + /* Horizontal bar mode */ + DPG_MODE_HORIZONTAL_BAR, + /* Single ramp mode */ + DPG_MODE_RGB_SINGLE_RAMP, + /* Dual ramp mode */ + DPG_MODE_RGB_DUAL_RAMP, + /* RGB XR BIAS mode */ + DPG_MODE_RGB_XR_BIAS +}; /************* FORMATTER ************/ @@ -47,7 +65,7 @@ * 2) enable truncation * 3) HW remove 12bit FMT support for DCE11 power saving reason. */ -static void set_truncation( +static void opp1_set_truncation( struct dcn10_opp *oppn10, const struct bit_depth_reduction_params *params) { @@ -57,7 +75,7 @@ static void set_truncation( FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE); } -static void set_spatial_dither( +static void opp1_set_spatial_dither( struct dcn10_opp *oppn10, const struct bit_depth_reduction_params *params) { @@ -136,14 +154,14 @@ static void set_spatial_dither( FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM); } -static void oppn10_program_bit_depth_reduction( +static void opp1_program_bit_depth_reduction( struct output_pixel_processor *opp, const struct bit_depth_reduction_params *params) { struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - set_truncation(oppn10, params); - set_spatial_dither(oppn10, params); + opp1_set_truncation(oppn10, params); + opp1_set_spatial_dither(oppn10, params); /* TODO * set_temporal_dither(oppn10, params); */ @@ -156,7 +174,7 @@ static void oppn10_program_bit_depth_reduction( * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly * 1: YCbCr 4:2:2 */ -static void set_pixel_encoding( +static void opp1_set_pixel_encoding( struct dcn10_opp *oppn10, const struct clamping_and_pixel_encoding_params *params) { @@ -186,7 +204,7 @@ static void set_pixel_encoding( * 7 for programable * 2) Enable clamp if Limited range requested */ -static void opp_set_clamping( +static void opp1_set_clamping( struct dcn10_opp *oppn10, const struct clamping_and_pixel_encoding_params *params) { @@ -224,7 +242,7 @@ static void opp_set_clamping( } -static void oppn10_set_dyn_expansion( +static void opp1_set_dyn_expansion( struct output_pixel_processor *opp, enum dc_color_space color_sp, enum dc_color_depth color_dpth, @@ -264,17 +282,17 @@ static void oppn10_set_dyn_expansion( } } -static void opp_program_clamping_and_pixel_encoding( +static void opp1_program_clamping_and_pixel_encoding( struct output_pixel_processor *opp, const struct clamping_and_pixel_encoding_params *params) { struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - opp_set_clamping(oppn10, params); - set_pixel_encoding(oppn10, params); + opp1_set_clamping(oppn10, params); + opp1_set_pixel_encoding(oppn10, params); } -static void oppn10_program_fmt( +static void opp1_program_fmt( struct output_pixel_processor *opp, struct bit_depth_reduction_params *fmt_bit_depth, struct clamping_and_pixel_encoding_params *clamping) @@ -286,20 +304,18 @@ static void oppn10_program_fmt( /* dithering is affected by , hence should be * programmed afterwards */ - oppn10_program_bit_depth_reduction( + opp1_program_bit_depth_reduction( opp, fmt_bit_depth); - opp_program_clamping_and_pixel_encoding( + opp1_program_clamping_and_pixel_encoding( opp, clamping); return; } - - -static void oppn10_set_stereo_polarity( +static void opp1_set_stereo_polarity( struct output_pixel_processor *opp, bool enable, bool rightEyePolarity) { @@ -312,18 +328,18 @@ static void oppn10_set_stereo_polarity( /* Constructor, Destructor */ /*****************************************/ -static void dcn10_opp_destroy(struct output_pixel_processor **opp) +static void opp1_destroy(struct output_pixel_processor **opp) { kfree(TO_DCN10_OPP(*opp)); *opp = NULL; } static struct opp_funcs dcn10_opp_funcs = { - .opp_set_dyn_expansion = oppn10_set_dyn_expansion, - .opp_program_fmt = oppn10_program_fmt, - .opp_program_bit_depth_reduction = oppn10_program_bit_depth_reduction, - .opp_set_stereo_polarity = oppn10_set_stereo_polarity, - .opp_destroy = dcn10_opp_destroy + .opp_set_dyn_expansion = opp1_set_dyn_expansion, + .opp_program_fmt = opp1_program_fmt, + .opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction, + .opp_set_stereo_polarity = opp1_set_stereo_polarity, + .opp_destroy = opp1_destroy }; void dcn10_opp_construct(struct dcn10_opp *oppn10, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index 790ce6014832..cdb220ed858e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -78,36 +78,14 @@ type DPG_MODE; \ type DPG_VRES; \ type DPG_HRES; \ + type DPG_ACTIVE_WIDTH; \ + type DPG_ACTIVE_HEIGHT; \ type DPG_COLOUR0_R_CR; \ type DPG_COLOUR1_R_CR; \ type DPG_COLOUR0_B_CB; \ type DPG_COLOUR1_B_CB; \ type DPG_COLOUR0_G_Y; \ type DPG_COLOUR1_G_Y; \ - type CM_OCSC_C11; \ - type CM_OCSC_C12; \ - type CM_OCSC_C13; \ - type CM_OCSC_C14; \ - type CM_OCSC_C21; \ - type CM_OCSC_C22; \ - type CM_OCSC_C23; \ - type CM_OCSC_C24; \ - type CM_OCSC_C31; \ - type CM_OCSC_C32; \ - type CM_OCSC_C33; \ - type CM_OCSC_C34; \ - type CM_COMB_C11; \ - type CM_COMB_C12; \ - type CM_COMB_C13; \ - type CM_COMB_C14; \ - type CM_COMB_C21; \ - type CM_COMB_C22; \ - type CM_COMB_C23; \ - type CM_COMB_C24; \ - type CM_COMB_C31; \ - type CM_COMB_C32; \ - type CM_COMB_C33; \ - type CM_COMB_C34; \ type FMT_TRUNCATE_EN; \ type FMT_TRUNCATE_DEPTH; \ type FMT_TRUNCATE_MODE; \ @@ -129,33 +107,22 @@ type FMT_DYNAMIC_EXP_EN; \ type FMT_DYNAMIC_EXP_MODE; \ type FMT_MAP420MEM_PWR_FORCE; \ - type FMT_STEREOSYNC_OVERRIDE + type FMT_STEREOSYNC_OVERRIDE; struct dcn10_opp_shift { - OPP_DCN10_REG_FIELD_LIST(uint8_t); + OPP_DCN10_REG_FIELD_LIST(uint8_t) }; struct dcn10_opp_mask { - OPP_DCN10_REG_FIELD_LIST(uint32_t); + OPP_DCN10_REG_FIELD_LIST(uint32_t) }; struct dcn10_opp_registers { uint32_t DPG_CONTROL; + uint32_t DPG_DIMENSIONS; uint32_t DPG_COLOUR_B_CB; uint32_t DPG_COLOUR_G_Y; uint32_t DPG_COLOUR_R_CR; - uint32_t CM_OCSC_C11_C12; - uint32_t CM_OCSC_C13_C14; - uint32_t CM_OCSC_C21_C22; - uint32_t CM_OCSC_C23_C24; - uint32_t CM_OCSC_C31_C32; - uint32_t CM_OCSC_C33_C34; - uint32_t CM_COMB_C11_C12; - uint32_t CM_COMB_C13_C14; - uint32_t CM_COMB_C21_C22; - uint32_t CM_COMB_C23_C24; - uint32_t CM_COMB_C31_C32; - uint32_t CM_COMB_C33_C34; uint32_t FMT_BIT_DEPTH_CONTROL; uint32_t FMT_CONTROL; uint32_t FMT_DITHER_RAND_R_SEED; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 75adb8fec551..8141b677fda9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -284,6 +284,12 @@ struct opp_funcs { void (*opp_set_test_pattern)( struct output_pixel_processor *opp, bool enable); + + void (*opp_dpg_blank_enable)( + struct output_pixel_processor *opp, + bool enable, + int width, + int height); }; #endif -- GitLab From ea826d640d8f3cb5b196b41283d41a16c24c013c Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Fri, 27 Oct 2017 15:28:38 -0400 Subject: [PATCH 0795/2547] drm/amd/display: call set csc_default if enable adjustment is false Signed-off-by: Yue Hin Lau Reviewed-by: Eric Bernstein Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 6 ++---- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++ drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 8b894ebc4e17..4355cc21b111 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -1381,7 +1381,7 @@ void dpp1_cm_set_output_csc_adjustment( void dpp1_cm_set_output_csc_default( struct dpp *dpp_base, - const struct default_adjustment *default_adjust); + enum dc_color_space colorspace); void dpp1_cm_set_gamut_remap( struct dpp *dpp, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index 9cb44c90e746..bb430c0ec1b6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -225,14 +225,13 @@ void dpp1_cm_set_gamut_remap( void dpp1_cm_set_output_csc_default( struct dpp *dpp_base, - const struct default_adjustment *default_adjust) + enum dc_color_space colorspace) { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); uint32_t ocsc_mode = 0; - if (default_adjust != NULL) { - switch (default_adjust->out_color_space) { + switch (colorspace) { case COLOR_SPACE_SRGB: case COLOR_SPACE_2020_RGB_FULLRANGE: ocsc_mode = 0; @@ -253,7 +252,6 @@ void dpp1_cm_set_output_csc_default( case COLOR_SPACE_UNKNOWN: default: break; - } } REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7bc88f423b3e..280476c42600 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1608,6 +1608,8 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, tbl_entry.color_space = color_space; //tbl_entry.regval = matrix; pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry); + } else { + pipe_ctx->plane_res.dpp->funcs->opp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace); } } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index 71078d184289..3b1486c3d05c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -64,7 +64,7 @@ struct dpp_funcs { void (*opp_set_csc_default)( struct dpp *dpp, - const struct default_adjustment *default_adjust); + enum dc_color_space colorspace); void (*opp_set_csc_adjustment)( struct dpp *dpp, -- GitLab From 37cf55bad96d7254d1109d577e6301ef92c59fe8 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Tue, 31 Oct 2017 17:55:20 -0400 Subject: [PATCH 0796/2547] drm/amd/display: dal 3.1.13 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index cb1e39288fa3..fbafc8b93a85 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.12" +#define DC_VER "3.1.13" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From 5fa2ec4fad366a6de324c57d51abea6dd4b52a26 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Tue, 31 Oct 2017 15:23:57 -0400 Subject: [PATCH 0797/2547] drm/amd/display: renaming dpp function to follow naming convention Signed-off-by: Yue Hin Lau Reviewed-by: Yuehin Lau Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 28 +++++++++--------- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 29 ++++++++++--------- drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 28 +++++++++--------- 3 files changed, 43 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index e9cf9d1514eb..21eba82aba97 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -442,20 +442,20 @@ static const struct dpp_funcs dcn10_dpp_funcs = { .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, .dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps, .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap, - .opp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment, - .opp_set_csc_default = dpp1_cm_set_output_csc_default, - .opp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut, - .opp_program_regamma_lut = dpp1_cm_program_regamma_lut, - .opp_configure_regamma_lut = dpp1_cm_configure_regamma_lut, - .opp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings, - .opp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings, - .opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl, - .ipp_program_bias_and_scale = dpp1_program_bias_and_scale, - .ipp_set_degamma = dpp1_set_degamma, - .ipp_program_input_lut = dpp1_program_input_lut, - .ipp_program_degamma_pwl = dpp1_set_degamma_pwl, - .ipp_setup = dpp1_cnv_setup, - .ipp_full_bypass = dpp1_full_bypass, + .dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment, + .dpp_set_csc_default = dpp1_cm_set_output_csc_default, + .dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut, + .dpp_program_regamma_lut = dpp1_cm_program_regamma_lut, + .dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut, + .dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings, + .dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings, + .dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl, + .dpp_program_bias_and_scale = dpp1_program_bias_and_scale, + .dpp_set_degamma = dpp1_set_degamma, + .dpp_program_input_lut = dpp1_program_input_lut, + .dpp_program_degamma_pwl = dpp1_set_degamma_pwl, + .dpp_setup = dpp1_cnv_setup, + .dpp_full_bypass = dpp1_full_bypass, .set_cursor_attributes = dpp1_set_cursor_attributes, .set_cursor_position = dpp1_set_cursor_position, }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 280476c42600..680aabda3277 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -869,23 +869,23 @@ static bool dcn10_set_input_transfer_func( tf = plane_state->in_transfer_func; if (plane_state->gamma_correction && dce_use_lut(plane_state)) - dpp_base->funcs->ipp_program_input_lut(dpp_base, + dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction); if (tf == NULL) - dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); else if (tf->type == TF_TYPE_PREDEFINED) { switch (tf->tf) { case TRANSFER_FUNCTION_SRGB: - dpp_base->funcs->ipp_set_degamma(dpp_base, + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB); break; case TRANSFER_FUNCTION_BT709: - dpp_base->funcs->ipp_set_degamma(dpp_base, + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC); break; case TRANSFER_FUNCTION_LINEAR: - dpp_base->funcs->ipp_set_degamma(dpp_base, + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); break; case TRANSFER_FUNCTION_PQ: @@ -896,7 +896,7 @@ static bool dcn10_set_input_transfer_func( break; } } else if (tf->type == TF_TYPE_BYPASS) { - dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); } else { /*TF_TYPE_DISTRIBUTED_POINTS*/ result = false; @@ -1235,12 +1235,12 @@ static bool dcn10_set_output_transfer_func( TF_TYPE_PREDEFINED && stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { - dpp->funcs->opp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB); + dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB); } else if (dcn10_translate_regamma_to_hw_format( stream->out_transfer_func, &dpp->regamma_params)) { - dpp->funcs->opp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER); + dpp->funcs->dpp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER); } else { - dpp->funcs->opp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS); + dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS); } return true; @@ -1607,9 +1607,10 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, tbl_entry.color_space = color_space; //tbl_entry.regval = matrix; - pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry); + + pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry); } else { - pipe_ctx->plane_res.dpp->funcs->opp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace); + pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace); } } @@ -1901,7 +1902,7 @@ static void update_dchubp_dpp( ); // program the input csc - dpp->funcs->ipp_setup(dpp, + dpp->funcs->dpp_setup(dpp, plane_state->format, EXPANSION_MODE_ZERO, plane_state->input_csc_color_matrix, @@ -1909,8 +1910,8 @@ static void update_dchubp_dpp( //set scale and bias registers build_prescale_params(&bns_params, plane_state); - if (dpp->funcs->ipp_program_bias_and_scale) - dpp->funcs->ipp_program_bias_and_scale(dpp, &bns_params); + if (dpp->funcs->dpp_program_bias_and_scale) + dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); mpcc_cfg.dpp_id = hubp->inst; mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index 3b1486c3d05c..ccb4896975c2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -62,63 +62,63 @@ struct dpp_funcs { struct dpp *dpp, const struct dpp_grph_csc_adjustment *adjust); - void (*opp_set_csc_default)( + void (*dpp_set_csc_default)( struct dpp *dpp, enum dc_color_space colorspace); - void (*opp_set_csc_adjustment)( + void (*dpp_set_csc_adjustment)( struct dpp *dpp, const struct out_csc_color_matrix *tbl_entry); - void (*opp_power_on_regamma_lut)( + void (*dpp_power_on_regamma_lut)( struct dpp *dpp, bool power_on); - void (*opp_program_regamma_lut)( + void (*dpp_program_regamma_lut)( struct dpp *dpp, const struct pwl_result_data *rgb, uint32_t num); - void (*opp_configure_regamma_lut)( + void (*dpp_configure_regamma_lut)( struct dpp *dpp, bool is_ram_a); - void (*opp_program_regamma_lutb_settings)( + void (*dpp_program_regamma_lutb_settings)( struct dpp *dpp, const struct pwl_params *params); - void (*opp_program_regamma_luta_settings)( + void (*dpp_program_regamma_luta_settings)( struct dpp *dpp, const struct pwl_params *params); - void (*opp_program_regamma_pwl)( + void (*dpp_program_regamma_pwl)( struct dpp *dpp, const struct pwl_params *params, enum opp_regamma mode); - void (*ipp_program_bias_and_scale)( + void (*dpp_program_bias_and_scale)( struct dpp *dpp, struct dc_bias_and_scale *params); - void (*ipp_set_degamma)( + void (*dpp_set_degamma)( struct dpp *dpp_base, enum ipp_degamma_mode mode); - void (*ipp_program_input_lut)( + void (*dpp_program_input_lut)( struct dpp *dpp_base, const struct dc_gamma *gamma); - void (*ipp_program_degamma_pwl)(struct dpp *dpp_base, + void (*dpp_program_degamma_pwl)(struct dpp *dpp_base, const struct pwl_params *params); - void (*ipp_setup)( + void (*dpp_setup)( struct dpp *dpp_base, enum surface_pixel_format format, enum expansion_mode mode, struct csc_transform input_csc_color_matrix, enum dc_color_space input_color_space); - void (*ipp_full_bypass)(struct dpp *dpp_base); + void (*dpp_full_bypass)(struct dpp *dpp_base); void (*set_cursor_attributes)( struct dpp *dpp_base, -- GitLab From 46f6b85cff2d20a0648c8ef61bfabe12dcf5b640 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Wed, 1 Nov 2017 21:52:21 -0400 Subject: [PATCH 0798/2547] drm/amd/display: dal 3.1.14 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index fbafc8b93a85..86a9c927a312 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.13" +#define DC_VER "3.1.14" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From e6c258cb4e6fbc7500c493df22f52e1046c575b0 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Mon, 30 Oct 2017 17:32:14 -0400 Subject: [PATCH 0799/2547] drm/amd/display: Refactor disable front end pipes. There are different code to disable front end, it is difficult to debug and adding new process. This refactor makes all disable front end call the same functions. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 3 + drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +- .../display/dc/dce110/dce110_hw_sequencer.c | 10 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 262 +++++++++--------- .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- 5 files changed, 154 insertions(+), 138 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 6d64a069648e..88a004cc2690 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -1064,6 +1064,9 @@ bool dcn_validate_bandwidth( hsplit_pipe->stream = NULL; hsplit_pipe->top_pipe = NULL; hsplit_pipe->bottom_pipe = NULL; + /* Clear plane_res and stream_res */ + memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); + memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); resource_build_scaling_params(pipe); } /* for now important to do this after pipe split for building e2e params */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f3496881caf4..39431bd8d77e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -963,9 +963,11 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) post_surface_trace(dc); for (i = 0; i < dc->res_pool->pipe_count; i++) - if (context->res_ctx.pipe_ctx[i].stream == NULL - || context->res_ctx.pipe_ctx[i].plane_state == NULL) - dc->hwss.power_down_front_end(dc, i); + if (context->res_ctx.pipe_ctx[i].stream == NULL || + context->res_ctx.pipe_ctx[i].plane_state == NULL) { + context->res_ctx.pipe_ctx[i].pipe_idx = i; + dc->hwss.power_down_front_end(dc, &context->res_ctx.pipe_ctx[i]); + } /* 3rd param should be true, temp w/a for RV*/ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) @@ -1339,8 +1341,11 @@ static void commit_planes_for_stream(struct dc *dc, if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state) continue; - if (!pipe_ctx->top_pipe && pipe_ctx->stream) { - struct dc_stream_status *stream_status = stream_get_status(context, pipe_ctx->stream); + if (!pipe_ctx->top_pipe && + pipe_ctx->stream && + pipe_ctx->stream == stream) { + struct dc_stream_status *stream_status = + stream_get_status(context, pipe_ctx->stream); dc->hwss.apply_ctx_for_surface( dc, pipe_ctx->stream, stream_status->plane_count, context); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 44315aef445b..73c38c93f5df 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1464,7 +1464,9 @@ static void disable_vga_and_power_gate_all_controllers( enable_display_pipe_clock_gating(ctx, true); - dc->hwss.power_down_front_end(dc, i); + dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; + dc->hwss.power_down_front_end(dc, + &dc->current_state->res_ctx.pipe_ctx[i]); } } @@ -1890,7 +1892,7 @@ static void dce110_reset_hw_ctx_wrap( if (old_clk) old_clk->funcs->cs_power_down(old_clk); - dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); + dc->hwss.power_down_front_end(dc, pipe_ctx_old); pipe_ctx_old->stream = NULL; } @@ -2950,8 +2952,10 @@ static void dce110_apply_ctx_for_surface( } } -static void dce110_power_down_fe(struct dc *dc, int fe_idx) +static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) { + int fe_idx = pipe_ctx->pipe_idx; + /* Do not power down fe when stream is active on dce*/ if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) return; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 680aabda3277..1c536884c080 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -558,13 +558,15 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc) } /* trigger HW to start disconnect plane from stream on the next vsync */ -static void plane_atomic_disconnect(struct dc *dc, - int fe_idx) +static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) { + int fe_idx = pipe_ctx->pipe_idx; struct hubp *hubp = dc->res_pool->hubps[fe_idx]; struct mpc *mpc = dc->res_pool->mpc; int opp_id, z_idx; int mpcc_id = -1; + struct timing_generator *tg = pipe_ctx->stream_res.tg; + struct dce_hwseq *hws = dc->hwseq; /* look at tree rather than mi here to know if we already reset */ for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) { @@ -583,29 +585,56 @@ static void plane_atomic_disconnect(struct dc *dc, if (opp_id == dc->res_pool->pipe_count) return; - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); - hubp->funcs->dcc_control(hubp, false, false); + mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree), + dc->res_pool->opps[opp_id]->inst, fe_idx); + + if (hubp->funcs->hubp_disconnect) + hubp->funcs->hubp_disconnect(hubp); + if (dc->debug.sanity_checks) dcn10_verify_allow_pstate_change_high(dc); - mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree), - dc->res_pool->opps[opp_id]->inst, fe_idx); + if (pipe_ctx->top_pipe) { + pipe_ctx->top_pipe->bottom_pipe = NULL; + pipe_ctx->top_pipe = NULL; + pipe_ctx->stream = NULL; + memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); + memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); + } + + if (pipe_ctx->bottom_pipe) { + pipe_ctx->bottom_pipe->top_pipe = NULL; + pipe_ctx->bottom_pipe = NULL; + } + pipe_ctx->plane_state = NULL; + + /* TODO: Move to tg. */ + REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], + VUPDATE_NO_LOCK_EVENT_CLEAR, 1); } /* disable HW used by plane. * note: cannot disable until disconnect is complete */ -static void plane_atomic_disable(struct dc *dc, - int fe_idx) +static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) { + int fe_idx = pipe_ctx->pipe_idx; struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = dc->res_pool->hubps[fe_idx]; struct mpc *mpc = dc->res_pool->mpc; int opp_id = hubp->opp_id; + struct timing_generator *tg = pipe_ctx->stream_res.tg; + + if (tg == NULL) + return; if (opp_id == 0xf) return; + if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], + VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, + 1, 100000); + mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id); dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false; /*dm_logger_write(dc->ctx->logger, LOG_ERROR, @@ -630,62 +659,52 @@ static void plane_atomic_disable(struct dc *dc, dcn10_verify_allow_pstate_change_high(dc); } -static void reset_front_end( - struct dc *dc, - int fe_idx) +/* kill power to plane hw + * note: cannot power down until plane is disable + */ +static void plane_atomic_power_down(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; - struct timing_generator *tg; - int opp_id = dc->res_pool->hubps[fe_idx]->opp_id; + struct dpp *dpp = dc->res_pool->dpps[fe_idx]; - /*Already reset*/ - if (opp_id == 0xf) - return; + if (REG(DC_IP_REQUEST_CNTL)) { + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 1); + dpp_pg_control(hws, fe_idx, false); + hubp_pg_control(hws, fe_idx, false); + dpp->funcs->dpp_reset(dpp); + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 0); + dm_logger_write(dc->ctx->logger, LOG_DEBUG, + "Power gated front end %d\n", fe_idx); + } +} - tg = dc->res_pool->timing_generators[opp_id]; - tg->funcs->lock(tg); +static void dcn10_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) +{ + int fe_idx = pipe_ctx->pipe_idx; + struct timing_generator *tg = pipe_ctx->stream_res.tg; - plane_atomic_disconnect(dc, fe_idx); + if (tg != NULL) { + tg->funcs->lock(tg); - REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1); - tg->funcs->unlock(tg); + plane_atomic_disconnect(dc, pipe_ctx); - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); + tg->funcs->unlock(tg); - if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) - REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], - VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, - 1, 100000); + if (dc->debug.sanity_checks) + dcn10_verify_allow_pstate_change_high(dc); - plane_atomic_disable(dc, fe_idx); + plane_atomic_disable(dc, pipe_ctx); + } + + plane_atomic_power_down(dc, fe_idx); dm_logger_write(dc->ctx->logger, LOG_DC, "Reset front end %d\n", fe_idx); } -static void dcn10_power_down_fe(struct dc *dc, int fe_idx) -{ - struct dce_hwseq *hws = dc->hwseq; - struct dpp *dpp = dc->res_pool->dpps[fe_idx]; - - reset_front_end(dc, fe_idx); - - REG_SET(DC_IP_REQUEST_CNTL, 0, - IP_REQUEST_EN, 1); - dpp_pg_control(hws, fe_idx, false); - hubp_pg_control(hws, fe_idx, false); - dpp->funcs->dpp_reset(dpp); - REG_SET(DC_IP_REQUEST_CNTL, 0, - IP_REQUEST_EN, 0); - dm_logger_write(dc->ctx->logger, LOG_DEBUG, - "Power gated front end %d\n", fe_idx); - - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); -} - static void dcn10_init_hw(struct dc *dc) { int i; @@ -744,7 +763,7 @@ static void dcn10_init_hw(struct dc *dc) tg->funcs->set_blank(tg, true); hwss_wait_for_blank_complete(tg); - dcn10_power_down_fe(dc, i); + plane_atomic_power_down(dc, i); tg->funcs->tg_init(tg); } @@ -1988,8 +2007,6 @@ static void program_all_pipe_in_tree( dcn10_verify_allow_pstate_change_high(dc); } - pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); - pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset; pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start; pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset; @@ -2097,62 +2114,75 @@ static void ready_shared_resources(struct dc *dc, struct dc_state *context) dcn10_pplib_apply_display_requirements(dc, context); } +static struct pipe_ctx *find_top_pipe_for_stream( + struct dc *dc, + struct dc_state *context, + const struct dc_stream_state *stream) +{ + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = + &dc->current_state->res_ctx.pipe_ctx[i]; + + if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) + continue; + + if (pipe_ctx->stream != stream) + continue; + + if (!pipe_ctx->top_pipe) + return pipe_ctx; + } + return NULL; +} + static void dcn10_apply_ctx_for_surface( struct dc *dc, const struct dc_stream_state *stream, int num_planes, struct dc_state *context) { - int i, be_idx; + int i; + struct timing_generator *tg; + bool removed_pipe[4] = { false }; + + struct pipe_ctx *top_pipe_to_program = + find_top_pipe_for_stream(dc, context, stream); + + if (!top_pipe_to_program) + return; + + tg = top_pipe_to_program->stream_res.tg; if (dc->debug.sanity_checks) dcn10_verify_allow_pstate_change_high(dc); - be_idx = -1; - for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (stream == context->res_ctx.pipe_ctx[i].stream) { - be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst; - break; - } - } - - ASSERT(be_idx != -1); + tg->funcs->lock(tg); if (num_planes == 0) { - for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { - struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) { - old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true); - dcn10_power_down_fe(dc, old_pipe_ctx->pipe_idx); - } - } - return; + /* OTG blank before remove all front end */ + tg->funcs->set_blank(tg, true); } - /* reset unused mpcc */ + /* Disconnect unused mpcc */ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - struct hubp *hubp = dc->res_pool->hubps[i]; - - if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) - continue; - - if (pipe_ctx->stream_res.tg && - pipe_ctx->stream_res.tg->inst == be_idx && - !pipe_ctx->top_pipe) - pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); - /* * Powergate reused pipes that are not powergated * fairly hacky right now, using opp_id as indicator + * TODO: After move dc_post to dc_update, this will + * be removed. */ - if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { - if (pipe_ctx->plane_res.hubp->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) { - dcn10_power_down_fe(dc, pipe_ctx->pipe_idx); + if (old_pipe_ctx->stream_res.tg == tg && + old_pipe_ctx->plane_res.hubp && + old_pipe_ctx->plane_res.hubp->opp_id != 0xf) { + dcn10_power_down_fe(dc, pipe_ctx); /* * power down fe will unlock when calling reset, need * to lock it back here. Messy, need rework. @@ -2161,39 +2191,12 @@ static void dcn10_apply_ctx_for_surface( } } + if (!pipe_ctx->plane_state && + old_pipe_ctx->plane_state && + old_pipe_ctx->stream_res.tg == tg) { - if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state) - || (!pipe_ctx->stream && old_pipe_ctx->stream)) { - if (old_pipe_ctx->stream_res.tg->inst != be_idx) - continue; - - if (!old_pipe_ctx->top_pipe) { - ASSERT(0); - continue; - } - - /* reset mpc */ - dc->res_pool->mpc->funcs->remove( - dc->res_pool->mpc, - &(old_pipe_ctx->stream_res.opp->mpc_tree), - old_pipe_ctx->stream_res.opp->inst, - old_pipe_ctx->pipe_idx); - old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.hubp->mpcc_id] = true; - - /*dm_logger_write(dc->ctx->logger, LOG_ERROR, - "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", - old_pipe_ctx->mpcc->inst);*/ - - if (hubp->funcs->hubp_disconnect) - hubp->funcs->hubp_disconnect(hubp); - - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); - - old_pipe_ctx->top_pipe = NULL; - old_pipe_ctx->bottom_pipe = NULL; - old_pipe_ctx->plane_state = NULL; - old_pipe_ctx->stream = NULL; + plane_atomic_disconnect(dc, old_pipe_ctx); + removed_pipe[i] = true; dm_logger_write(dc->ctx->logger, LOG_DC, "Reset mpcc for pipe %d\n", @@ -2201,23 +2204,24 @@ static void dcn10_apply_ctx_for_surface( } } - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (num_planes > 0) + program_all_pipe_in_tree(dc, top_pipe_to_program, context); + + tg->funcs->unlock(tg); - if (pipe_ctx->stream != stream) - continue; - /* looking for top pipe to program */ - if (!pipe_ctx->top_pipe) { - program_all_pipe_in_tree(dc, pipe_ctx, context); - if (pipe_ctx->stream_res.tg && - pipe_ctx->stream_res.tg->inst == be_idx && - (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) - pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *old_pipe_ctx = + &dc->current_state->res_ctx.pipe_ctx[i]; + + if (removed_pipe[i]) { + plane_atomic_disable(dc, old_pipe_ctx); + if (num_planes == 0) + plane_atomic_power_down(dc, i); } } + dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, "\n============== Watermark parameters ==============\n" "a.urgent_ns: %d \n" diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index f3c5468854bd..19cfca91bb4e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -129,7 +129,7 @@ struct hw_sequencer_funcs { struct dc_bios *dcb, enum pipe_gating_control power_gating); - void (*power_down_front_end)(struct dc *dc, int fe_idx); + void (*power_down_front_end)(struct dc *dc, struct pipe_ctx *pipe_ctx); void (*power_on_front_end)(struct dc *dc, struct pipe_ctx *pipe, -- GitLab From efd5220405df0acd43eb7e16948e92eec87ce2cb Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 31 Oct 2017 14:34:13 -0400 Subject: [PATCH 0800/2547] drm/amd/display: Bunch of indentation cleanups in color stuff Trying to align with kernel coding style and make it a bit more readable. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce/dce_transform.c | 170 +++++++----------- .../display/dc/dce110/dce110_hw_sequencer.c | 10 +- 2 files changed, 68 insertions(+), 112 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index ae32af31eff1..4ff874a43f7a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1260,124 +1260,87 @@ static void program_pwl( REGAMMA_LUT_LIGHT_SLEEP_DIS, 0); } -static void regamma_config_regions_and_segments( - struct dce_transform *xfm_dce, - const struct pwl_params *params) +static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce, + const struct pwl_params *params) { const struct gamma_curve *curve; - { - REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0, - REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x, - REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0); - } - { - REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0, - REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope); - - } - { - REG_SET(REGAMMA_CNTLA_END_CNTL1, 0, - REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x); - } - { - REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, - REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y, - REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope); - } - - curve = params->arr_curve_points; + REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0, + REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x, + REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0); - { - REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - } + REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0, + REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope); - curve += 2; + REG_SET(REGAMMA_CNTLA_END_CNTL1, 0, + REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x); - { - REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, + REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y, + REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope); - } + curve = params->arr_curve_points; + REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - + REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - + REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - + REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - + REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } + REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + curve += 2; + REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - } + REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); } -void dce110_opp_program_regamma_pwl( - struct transform *xfm, - const struct pwl_params *params) +void dce110_opp_program_regamma_pwl(struct transform *xfm, + const struct pwl_params *params) { struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); @@ -1388,9 +1351,8 @@ void dce110_opp_program_regamma_pwl( program_pwl(xfm_dce, params); } -void dce110_opp_power_on_regamma_lut( - struct transform *xfm, - bool power_on) +void dce110_opp_power_on_regamma_lut(struct transform *xfm, + bool power_on) { struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); @@ -1406,29 +1368,25 @@ void dce110_opp_power_on_regamma_lut( } void dce110_opp_set_regamma_mode(struct transform *xfm, - enum opp_regamma mode) + enum opp_regamma mode) { struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); REG_SET(REGAMMA_CONTROL, 0, - GRPH_REGAMMA_MODE, mode); + GRPH_REGAMMA_MODE, mode); } static const struct transform_funcs dce_transform_funcs = { .transform_reset = dce_transform_reset, - .transform_set_scaler = - dce_transform_set_scaler, - .transform_set_gamut_remap = - dce_transform_set_gamut_remap, + .transform_set_scaler = dce_transform_set_scaler, + .transform_set_gamut_remap = dce_transform_set_gamut_remap, .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, .opp_set_csc_default = dce110_opp_set_csc_default, .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl, .opp_set_regamma_mode = dce110_opp_set_regamma_mode, - .transform_set_pixel_storage_depth = - dce_transform_set_pixel_storage_depth, - .transform_get_optimal_number_of_taps = - dce_transform_get_optimal_number_of_taps + .transform_set_pixel_storage_depth = dce_transform_set_pixel_storage_depth, + .transform_get_optimal_number_of_taps = dce_transform_get_optimal_number_of_taps }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 73c38c93f5df..3002978c860e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -650,13 +650,11 @@ static bool dce110_set_output_transfer_func( xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; if (stream->out_transfer_func && - stream->out_transfer_func->type == - TF_TYPE_PREDEFINED && - stream->out_transfer_func->tf == - TRANSFER_FUNCTION_SRGB) { + stream->out_transfer_func->type == TF_TYPE_PREDEFINED && + stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); - } else if (dce110_translate_regamma_to_hw_format( - stream->out_transfer_func, &xfm->regamma_params)) { + } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, + &xfm->regamma_params)) { xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); } else { -- GitLab From a6114e854c55c928b9b8bcf7014eb205bd112c68 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 31 Oct 2017 16:27:59 -0400 Subject: [PATCH 0801/2547] drm/amd/display: Fix some more color indentations Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 ++--- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++- .../display/dc/dce110/dce110_hw_sequencer.c | 35 ++++++--------- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 44 +++++++------------ 4 files changed, 36 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8360d17125ae..80567aa1968e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2142,6 +2142,7 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, const struct drm_connector *connector) { struct dc_crtc_timing *timing_out = &stream->timing; + struct dc_transfer_func *tf = dc_create_transfer_func(); memset(timing_out, 0, sizeof(struct dc_crtc_timing)); @@ -2185,13 +2186,9 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, stream->output_color_space = get_output_color_space(timing_out); - { - struct dc_transfer_func *tf = dc_create_transfer_func(); - - tf->type = TF_TYPE_PREDEFINED; - tf->tf = TRANSFER_FUNCTION_SRGB; - stream->out_transfer_func = tf; - } + tf->type = TF_TYPE_PREDEFINED; + tf->tf = TRANSFER_FUNCTION_SRGB; + stream->out_transfer_func = tf; } static void fill_audio_info(struct audio_info *audio_info, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 39431bd8d77e..f3397ff17345 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1376,10 +1376,9 @@ static void commit_planes_for_stream(struct dc *dc, continue; /* work around to program degamma regs for split pipe after set mode. */ - if (srf_updates[i].in_transfer_func || (pipe_ctx->top_pipe && - pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state)) - dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->plane_state); + if (srf_updates[i].in_transfer_func || + (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state)) + dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 3002978c860e..1ec008404784 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -257,9 +257,9 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, } } -static bool dce110_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *plane_state) +static bool +dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) { struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; const struct dc_transfer_func *tf = NULL; @@ -280,25 +280,19 @@ static bool dce110_set_input_transfer_func( if (tf == NULL) { /* Default case if no input transfer function specified */ - ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_HW_sRGB); + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); } else if (tf->type == TF_TYPE_PREDEFINED) { switch (tf->tf) { case TRANSFER_FUNCTION_SRGB: - ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_HW_sRGB); + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); break; case TRANSFER_FUNCTION_BT709: - ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_HW_xvYCC); + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); break; case TRANSFER_FUNCTION_LINEAR: - ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_BYPASS); + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); break; case TRANSFER_FUNCTION_PQ: - result = false; - break; default: result = false; break; @@ -640,9 +634,9 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func return true; } -static bool dce110_set_output_transfer_func( - struct pipe_ctx *pipe_ctx, - const struct dc_stream_state *stream) +static bool +dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx, + const struct dc_stream_state *stream) { struct transform *xfm = pipe_ctx->plane_res.xfm; @@ -2756,8 +2750,7 @@ static void dce110_program_front_end_for_pipe( struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; - struct pipe_ctx *cur_pipe_ctx = - &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; unsigned int i; memset(&tbl_entry, 0, sizeof(tbl_entry)); @@ -2850,10 +2843,8 @@ static void dce110_program_front_end_for_pipe( /* Moved programming gamma from dc to hwss */ if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { - dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->plane_state); - dc->hwss.set_output_transfer_func( - pipe_ctx, pipe_ctx->stream); + dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); + dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); } dm_logger_write(dc->ctx->logger, LOG_SURFACE, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 1c536884c080..99f478c52421 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -874,8 +874,8 @@ static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_c pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; } -static bool dcn10_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) +static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) { struct dpp *dpp_base = pipe_ctx->plane_res.dpp; const struct dc_transfer_func *tf = NULL; @@ -888,28 +888,22 @@ static bool dcn10_set_input_transfer_func( tf = plane_state->in_transfer_func; if (plane_state->gamma_correction && dce_use_lut(plane_state)) - dpp_base->funcs->dpp_program_input_lut(dpp_base, - plane_state->gamma_correction); + dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction); if (tf == NULL) dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); else if (tf->type == TF_TYPE_PREDEFINED) { switch (tf->tf) { case TRANSFER_FUNCTION_SRGB: - dpp_base->funcs->dpp_set_degamma(dpp_base, - IPP_DEGAMMA_MODE_HW_sRGB); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB); break; case TRANSFER_FUNCTION_BT709: - dpp_base->funcs->dpp_set_degamma(dpp_base, - IPP_DEGAMMA_MODE_HW_xvYCC); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC); break; case TRANSFER_FUNCTION_LINEAR: - dpp_base->funcs->dpp_set_degamma(dpp_base, - IPP_DEGAMMA_MODE_BYPASS); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); break; case TRANSFER_FUNCTION_PQ: - result = false; - break; default: result = false; break; @@ -1238,9 +1232,9 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func return true; } -static bool dcn10_set_output_transfer_func( - struct pipe_ctx *pipe_ctx, - const struct dc_stream_state *stream) +static bool +dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx, + const struct dc_stream_state *stream) { struct dpp *dpp = pipe_ctx->plane_res.dpp; @@ -1250,17 +1244,13 @@ static bool dcn10_set_output_transfer_func( dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; if (stream->out_transfer_func && - stream->out_transfer_func->type == - TF_TYPE_PREDEFINED && - stream->out_transfer_func->tf == - TRANSFER_FUNCTION_SRGB) { + stream->out_transfer_func->type == TF_TYPE_PREDEFINED && + stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB); - } else if (dcn10_translate_regamma_to_hw_format( - stream->out_transfer_func, &dpp->regamma_params)) { - dpp->funcs->dpp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER); - } else { + else if (dcn10_translate_regamma_to_hw_format(stream->out_transfer_func, &dpp->regamma_params)) + dpp->funcs->dpp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER); + else dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS); - } return true; } @@ -2047,10 +2037,8 @@ static void program_all_pipe_in_tree( } if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { - dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->plane_state); - dc->hwss.set_output_transfer_func( - pipe_ctx, pipe_ctx->stream); + dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); + dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); } } -- GitLab From 3e64668d7926854b084f89831ecbe4ae75600db6 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Thu, 2 Nov 2017 10:52:09 -0400 Subject: [PATCH 0802/2547] drm/amd/display: fix regamma programming When new coefficients match cached we would skip setting regamma mode Also, when doing a stream update we would program regamma for all pipes, even thos that are not yet powered on. This resulted in never setting regamma since we would cache before the pipe is powered. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 14 +++----------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 10 +++------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 6 ------ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 - 4 files changed, 6 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f3397ff17345..e59e7028ad57 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1382,27 +1382,19 @@ static void commit_planes_for_stream(struct dc *dc, } } - if (update_type > UPDATE_TYPE_FAST) { + if (stream && stream_update && update_type > UPDATE_TYPE_FAST) for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (!pipe_ctx->stream) + if (pipe_ctx->stream != stream) continue; - if (stream_update != NULL && - stream_update->out_transfer_func != NULL) { - dc->hwss.set_output_transfer_func( - pipe_ctx, pipe_ctx->stream); - } - - if (stream_update != NULL && - stream_update->hdr_static_metadata) { + if (stream_update->hdr_static_metadata) { resource_build_info_frame(pipe_ctx); dc->hwss.update_info_frame(pipe_ctx); } } - } } void dc_commit_updates_for_stream(struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 21eba82aba97..bbf93c94a977 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -188,9 +188,7 @@ static void dpp1_cm_set_regamma_pwl( struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); - uint32_t re_mode = 0; - uint32_t obuf_bypass = 0; /* need for pipe split */ - uint32_t obuf_hupscale = 0; + uint32_t re_mode; switch (mode) { case OPP_REGAMMA_BYPASS: @@ -203,8 +201,9 @@ static void dpp1_cm_set_regamma_pwl( re_mode = 2; break; case OPP_REGAMMA_USER: + re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3; if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0) - return; + break; dpp1_cm_power_on_regamma_lut(dpp_base, true); dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); @@ -225,9 +224,6 @@ static void dpp1_cm_set_regamma_pwl( break; } REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); - REG_UPDATE_2(OBUF_CONTROL, - OBUF_BYPASS, obuf_bypass, - OBUF_H_2X_UPSCALE_EN, obuf_hupscale); } static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 4355cc21b111..ad71fb50f8a5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -71,7 +71,6 @@ SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \ SRI(RECOUT_START, DSCL, id), \ SRI(RECOUT_SIZE, DSCL, id), \ - SRI(OBUF_CONTROL, DSCL, id), \ SRI(CM_ICSC_CONTROL, CM, id), \ SRI(CM_ICSC_C11_C12, CM, id), \ SRI(CM_ICSC_C33_C34, CM, id), \ @@ -236,7 +235,6 @@ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ - TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \ TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ @@ -394,7 +392,6 @@ TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \ - TF_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \ TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \ TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \ TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \ @@ -558,8 +555,6 @@ type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \ type CM_RGAM_LUT_MODE; \ type CM_CMOUT_ROUND_TRUNC_MODE; \ - type OBUF_BYPASS; \ - type OBUF_H_2X_UPSCALE_EN; \ type CM_BLNDGAM_LUT_MODE; \ type CM_BLNDGAM_RAMB_EXP_REGION_START_B; \ type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ @@ -1096,7 +1091,6 @@ struct dcn_dpp_registers { uint32_t CM_RGAM_RAMA_REGION_32_33; uint32_t CM_RGAM_CONTROL; uint32_t CM_CMOUT_CONTROL; - uint32_t OBUF_CONTROL; uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; uint32_t CM_BLNDGAM_CONTROL; uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 99f478c52421..26452b6b38dd 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -820,7 +820,6 @@ static void reset_hw_ctx_wrap( struct clock_source *old_clk = pipe_ctx_old->clock_source; reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); - if (old_clk) old_clk->funcs->cs_power_down(old_clk); } -- GitLab From bbe3f058ecb62bce041a0b03d76f6b9337dc81af Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Thu, 2 Nov 2017 15:07:25 -0400 Subject: [PATCH 0803/2547] drm/amd/display: fix uninitialized variable warning Signed-off-by: Dmytro Laktyushkin Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index bbf93c94a977..d8929b31e5ba 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -188,7 +188,7 @@ static void dpp1_cm_set_regamma_pwl( struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); - uint32_t re_mode; + uint32_t re_mode = 0; switch (mode) { case OPP_REGAMMA_BYPASS: -- GitLab From 33af27bb114ff886c151d1c5a52e40b1cfbc4053 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 31 Oct 2017 18:05:31 -0400 Subject: [PATCH 0804/2547] drm/amd/display: remove unnecessary waits in dcn10 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 9 --------- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 13 +------------ .../amd/display/dc/dcn10/dcn10_timing_generator.c | 13 ++----------- 3 files changed, 3 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 52506155e361..3b0db253ac22 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -140,10 +140,6 @@ BL_REG_LIST() #define HWSEQ_DCN_REG_LIST()\ - SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 0), \ - SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 1), \ - SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 2), \ - SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 3), \ SRII(DCHUBP_CNTL, HUBP, 0), \ SRII(DCHUBP_CNTL, HUBP, 1), \ SRII(DCHUBP_CNTL, HUBP, 2), \ @@ -264,7 +260,6 @@ struct dce_hwseq_registers { uint32_t DCHUB_AGP_BOT; uint32_t DCHUB_AGP_TOP; - uint32_t OTG_GLOBAL_SYNC_STATUS[4]; uint32_t DCHUBP_CNTL[4]; uint32_t HUBP_CLK_CNTL[4]; uint32_t DPP_CONTROL[4]; @@ -438,8 +433,6 @@ struct dce_hwseq_registers { #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ - HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \ - HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \ HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \ HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \ HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ @@ -536,8 +529,6 @@ struct dce_hwseq_registers { type LVTMA_PWRSEQ_TARGET_STATE_R; #define HWSEQ_DCN_REG_FIELD_LIST(type) \ - type VUPDATE_NO_LOCK_EVENT_CLEAR; \ - type VUPDATE_NO_LOCK_EVENT_OCCURRED; \ type HUBP_VTG_SEL; \ type HUBP_CLOCK_ENABLE; \ type DPP_CLOCK_ENABLE; \ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 26452b6b38dd..bd30d49e574a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -565,8 +565,6 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) struct mpc *mpc = dc->res_pool->mpc; int opp_id, z_idx; int mpcc_id = -1; - struct timing_generator *tg = pipe_ctx->stream_res.tg; - struct dce_hwseq *hws = dc->hwseq; /* look at tree rather than mi here to know if we already reset */ for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) { @@ -586,7 +584,7 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) return; mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree), - dc->res_pool->opps[opp_id]->inst, fe_idx); + dc->res_pool->opps[opp_id]->inst, fe_idx); if (hubp->funcs->hubp_disconnect) hubp->funcs->hubp_disconnect(hubp); @@ -607,10 +605,6 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx->bottom_pipe = NULL; } pipe_ctx->plane_state = NULL; - - /* TODO: Move to tg. */ - REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], - VUPDATE_NO_LOCK_EVENT_CLEAR, 1); } /* disable HW used by plane. @@ -630,11 +624,6 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) if (opp_id == 0xf) return; - if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) - REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], - VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, - 1, 100000); - mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id); dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false; /*dm_logger_write(dc->ctx->logger, LOG_ERROR, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index 819c4edd77a7..90e94a3c11a6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -393,19 +393,9 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) OTG_CLOCK_GATE_DIS, 0, OTG_CLOCK_EN, 0); - if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) - REG_WAIT(OTG_CLOCK_CONTROL, - OTG_CLOCK_ON, 0, - 1, 1000); - REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, 0, OPTC_INPUT_CLK_EN, 0); - - if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) - REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, - OPTC_INPUT_CLK_ON, 0, - 1, 1000); } } @@ -568,10 +558,11 @@ static void tgn10_lock(struct timing_generator *tg) REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK, 1); + /* Should be fast, status does not update on maximus */ if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) REG_WAIT(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, 1, - 1, 100); + 1, 10); } static void tgn10_unlock(struct timing_generator *tg) -- GitLab From 42cf181b59b8e3cc75485fa493bd0e812f44a74b Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Thu, 2 Nov 2017 14:55:14 -0400 Subject: [PATCH 0805/2547] drm/amd/display: add warning on long reg_wait Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 0d84b2a1ccfd..c584252669fd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -156,8 +156,13 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, field_value = get_reg_field_value_ex(reg_val, mask, shift); - if (field_value == condition_value) + if (field_value == condition_value) { + if (i * delay_between_poll_us > 1000) + dm_output_to_console("REG_WAIT taking a while: %dms in %s line:%d\n", + delay_between_poll_us * i / 1000, + func_name, line); return reg_val; + } } dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n", -- GitLab From 0af4096db9ec6a7b12475bf8d21ee5464722c7a2 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Thu, 2 Nov 2017 13:24:20 -0400 Subject: [PATCH 0806/2547] drm/amd/display: Modified front end initiail in init_hw Optimized front end initial sequence, reset MPC module properly. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 66 ++++++++++++++----- .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 11 ++++ .../display/dc/dcn10/dcn10_timing_generator.c | 11 ++++ drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 2 + .../amd/display/dc/inc/hw/timing_generator.h | 1 + 5 files changed, 74 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index bd30d49e574a..5d1fb1c297a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -616,10 +616,6 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) struct hubp *hubp = dc->res_pool->hubps[fe_idx]; struct mpc *mpc = dc->res_pool->mpc; int opp_id = hubp->opp_id; - struct timing_generator *tg = pipe_ctx->stream_res.tg; - - if (tg == NULL) - return; if (opp_id == 0xf) return; @@ -700,6 +696,8 @@ static void dcn10_init_hw(struct dc *dc) struct abm *abm = dc->res_pool->abm; struct dmcu *dmcu = dc->res_pool->dmcu; struct dce_hwseq *hws = dc->hwseq; + struct dc_bios *dcb = dc->ctx->dc_bios; + struct dc_state *context = dc->current_state; if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { REG_WRITE(REFCLK_CNTL, 0); @@ -720,9 +718,10 @@ static void dcn10_init_hw(struct dc *dc) } /* end of FPGA. Below if real ASIC */ - bios_golden_init(dc); - - disable_vga(dc->hwseq); + if (!dcb->funcs->is_accelerated_mode(dcb)) { + bios_golden_init(dc); + disable_vga(dc->hwseq); + } for (i = 0; i < dc->link_count; i++) { /* Power up AND update implementation according to the @@ -738,22 +737,55 @@ static void dcn10_init_hw(struct dc *dc) } for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct dpp *dpp = dc->res_pool->dpps[i]; struct timing_generator *tg = dc->res_pool->timing_generators[i]; - dpp->funcs->dpp_reset(dpp); - dc->res_pool->mpc->funcs->remove( - dc->res_pool->mpc, &(dc->res_pool->opps[i]->mpc_tree), - dc->res_pool->opps[i]->inst, i); + if (tg->funcs->is_tg_enabled(tg)) + tg->funcs->lock(tg); + } - /* Blank controller using driver code instead of - * command table. - */ - tg->funcs->set_blank(tg, true); - hwss_wait_for_blank_complete(tg); + /* Blank controller using driver code instead of + * command table. + */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + + if (tg->funcs->is_tg_enabled(tg)) { + tg->funcs->set_blank(tg, true); + hwss_wait_for_blank_complete(tg); + } + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + pipe_ctx->stream_res.tg = tg; + pipe_ctx->pipe_idx = i; + pipe_ctx->plane_res.hubp = dc->res_pool->hubps[i]; + pipe_ctx->plane_res.hubp->mpcc_id = i; + pipe_ctx->plane_res.hubp->opp_id = + dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i); + + plane_atomic_disconnect(dc, pipe_ctx); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + if (tg->funcs->is_tg_enabled(tg)) + tg->funcs->unlock(tg); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + plane_atomic_disable(dc, pipe_ctx); plane_atomic_power_down(dc, i); + pipe_ctx->stream_res.tg = NULL; + pipe_ctx->plane_res.hubp = NULL; + tg->funcs->tg_init(tg); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index 76573e1f5b01..5028619d4fb4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -335,11 +335,22 @@ void mpc10_update_blend_mode( MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha); } +static int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id) +{ + struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); + int opp_id = 0xF; + + REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); + + return opp_id; +} + const struct mpc_funcs dcn10_mpc_funcs = { .add = mpc10_mpcc_add, .remove = mpc10_mpcc_remove, .wait_for_idle = mpc10_assert_idle_mpcc, .update_blend_mode = mpc10_update_blend_mode, + .get_opp_id = mpc10_get_opp_id, }; void dcn10_mpc_construct(struct dcn10_mpc *mpc10, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index 90e94a3c11a6..d248067810c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -1212,6 +1212,16 @@ static void tgn10_tg_init(struct timing_generator *tg) REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); } +static bool tgn10_is_tg_enabled(struct timing_generator *tg) +{ + struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + uint32_t otg_enabled = 0; + + REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); + + return (otg_enabled != 0); + +} static const struct timing_generator_funcs dcn10_tg_funcs = { .validate_timing = tgn10_validate_timing, .program_timing = tgn10_program_timing, @@ -1243,6 +1253,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { .is_stereo_left_eye = tgn10_is_stereo_left_eye, .set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer, .tg_init = tgn10_tg_init, + .is_tg_enabled = tgn10_is_tg_enabled, }; void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index d4188b2c0626..a786d4c3935c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -56,6 +56,8 @@ struct mpc_funcs { void (*update_blend_mode)(struct mpc *mpc, struct mpcc_cfg *cfg); + int (*get_opp_id)(struct mpc *mpc, int mpcc_id); + }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index f77dca87cbbc..860259913d78 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -186,6 +186,7 @@ struct timing_generator_funcs { void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable); void (*tg_init)(struct timing_generator *tg); + bool (*is_tg_enabled)(struct timing_generator *tg); }; #endif -- GitLab From 631aaa0af4be3de8f0184095075650afaa023334 Mon Sep 17 00:00:00 2001 From: Hersen Wu Date: Tue, 31 Oct 2017 15:55:15 -0400 Subject: [PATCH 0807/2547] drm/amd/display: send display_count msg so SMU can enter S0i2 SMU can future lower voltages in long idle case when all display is off. If all display output is turned off via DPMS, send display_count = 0 after all output are turned off. otherwise send display_count msg before turning on display to make sure SMU exit S0i2 state. before is not neccessary as we are out of S0i2 when driver execute code, but send message before anyways for correctness. Signed-off-by: Hersen Wu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ++++++++++-- .../drm/amd/display/dc/dce100/dce100_hw_sequencer.c | 2 ++ .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 +++++ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 ++++ 5 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e59e7028ad57..5745304b5af5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -389,11 +389,19 @@ void set_dpms( if (stream->dpms_off != dpms_off) { stream->dpms_off = dpms_off; - if (dpms_off) + + if (dpms_off) { core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE); - else + + dc->hwss.pplib_apply_display_requirements( + dc, dc->current_state); + } else { + dc->hwss.pplib_apply_display_requirements( + dc, dc->current_state); + core_link_enable_stream(dc->current_state, pipe_ctx); + } } } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index e7a694835e3e..469af0587604 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -148,5 +148,7 @@ void dce100_hw_sequencer_construct(struct dc *dc) dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; dc->hwss.set_bandwidth = dce100_set_bandwidth; + dc->hwss.pplib_apply_display_requirements = + dce100_pplib_apply_display_requirements; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1ec008404784..d22745e6dff0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2595,6 +2595,10 @@ void dce110_fill_display_configs( ASSERT(pipe_ctx != NULL); + /* only notify active stream */ + if (stream->dpms_off) + continue; + num_cfgs++; cfg->signal = pipe_ctx->stream->signal; cfg->pipe_idx = pipe_ctx->pipe_idx; @@ -3024,6 +3028,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, .ready_shared_resources = ready_shared_resources, .optimize_shared_resources = optimize_shared_resources, + .pplib_apply_display_requirements = pplib_apply_display_requirements, .edp_backlight_control = hwss_edp_backlight_control, .edp_power_control = hwss_edp_power_control, }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 5d1fb1c297a3..73e7afb360b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2567,6 +2567,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, .ready_shared_resources = ready_shared_resources, .optimize_shared_resources = optimize_shared_resources, + .pplib_apply_display_requirements = + dcn10_pplib_apply_display_requirements, .edp_backlight_control = hwss_edp_backlight_control, .edp_power_control = hwss_edp_power_control }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 19cfca91bb4e..1d8852683f1f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -183,12 +183,16 @@ struct hw_sequencer_funcs { void (*ready_shared_resources)(struct dc *dc, struct dc_state *context); void (*optimize_shared_resources)(struct dc *dc); + void (*pplib_apply_display_requirements)( + struct dc *dc, + struct dc_state *context); void (*edp_power_control)( struct dc_link *link, bool enable); void (*edp_backlight_control)( struct dc_link *link, bool enable); + }; void color_space_to_black_color( -- GitLab From a03f39a05a85123956ef830cfd5ae44eda703f97 Mon Sep 17 00:00:00 2001 From: SivapiriyanKumarasamy Date: Thu, 2 Nov 2017 15:28:32 -0400 Subject: [PATCH 0808/2547] drm/amd/display: Add transfer function to dc_surface_update Signed-off-by: SivapiriyanKumarasamy Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 86a9c927a312..acb36594acc2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -475,6 +475,8 @@ struct dc_surface_update { */ /* gamma TO BE REMOVED */ struct dc_gamma *gamma; + enum color_transfer_func color_input_tf; + enum color_transfer_func color_output_tf; struct dc_transfer_func *in_transfer_func; struct csc_transform *input_csc_color_matrix; -- GitLab From d39b3acbf6251b3ca20db361d2b12fa9b5f17c71 Mon Sep 17 00:00:00 2001 From: Ken Chalmers Date: Thu, 2 Nov 2017 17:21:35 -0400 Subject: [PATCH 0809/2547] drm/amd/display: fix dcn10_hubbub_wm_read_state The ALLOW_SR registers might not always be available. Signed-off-by: Ken Chalmers Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 26 +++++++++++++------ 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c index 23c4573f7a34..eb8317187f30 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c @@ -42,36 +42,46 @@ void hubbub1_wm_read_state(struct hubbub *hubbub, { struct dcn_hubbub_wm_set *s; + memset(wm, 0, sizeof(struct dcn_hubbub_wm)); + s = &wm->sets[0]; s->wm_set = 0; s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) { + s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); + s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); + } s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); s = &wm->sets[1]; s->wm_set = 1; s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) { + s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); + s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); + } s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); s = &wm->sets[2]; s->wm_set = 2; s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C); - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) { + s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); + s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); + } s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); s = &wm->sets[3]; s->wm_set = 3; s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D); - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) { + s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); + s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); + } s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); } -- GitLab From 8c15e81975a2a6361ac3c6782a6a702fc2dca09a Mon Sep 17 00:00:00 2001 From: Eric Bernstein Date: Thu, 2 Nov 2017 17:39:48 -0400 Subject: [PATCH 0810/2547] drm/amd/display: Remove unused OPP functions from interface Signed-off-by: Eric Bernstein Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 8141b677fda9..cd6b0d4cd457 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -281,15 +281,6 @@ struct opp_funcs { bool enable, bool rightEyePolarity); - void (*opp_set_test_pattern)( - struct output_pixel_processor *opp, - bool enable); - - void (*opp_dpg_blank_enable)( - struct output_pixel_processor *opp, - bool enable, - int width, - int height); }; #endif -- GitLab From c12eefc25757e97335177c26cca934c308c0899e Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Thu, 2 Nov 2017 18:53:26 -0400 Subject: [PATCH 0811/2547] drm/amd/display: dal 3.1.15 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index acb36594acc2..8cdc63f273ca 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.14" +#define DC_VER "3.1.15" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From e58d866e8d6322e9c6f098a538548bd7cf8801c2 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Fri, 3 Nov 2017 16:02:50 -0400 Subject: [PATCH 0812/2547] drm/amd/display: Fixed not set scaler bug. New scaler parameter assign to dpp is after early return, cause next flip scaler not program. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c index 242a568294e2..4b5b70907202 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c @@ -650,6 +650,9 @@ void dpp1_dscl_set_scaler_manual_scale( if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) return; + + dpp->scl_data = *scl_data; + /* Recout */ dpp1_dscl_set_recout(dpp, &scl_data->recout); @@ -701,5 +704,4 @@ void dpp1_dscl_set_scaler_manual_scale( SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1); dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr); - dpp->scl_data = *scl_data; } -- GitLab From 35b71a3f6e5f81fe494e0ed8e82deb640ecfc6ec Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Fri, 3 Nov 2017 16:21:37 -0400 Subject: [PATCH 0813/2547] drm/amd/display: always call set output tf Temporary solution to fix gamma adjustment not working. Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 73e7afb360b1..666c6c0f882a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2058,8 +2058,14 @@ static void program_all_pipe_in_tree( if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); - dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); } + + /* + * TODO: This can be further optimized/cleaned up + * Always call this for now since it does memcmp inside before + * doing heavy calculation and programming + */ + dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); } if (dc->debug.sanity_checks) { -- GitLab From 733a3d2d414647a269a50c28456f834732766785 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Fri, 3 Nov 2017 16:33:14 -0400 Subject: [PATCH 0814/2547] drm/amd/display: dal 3.1.16 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 8cdc63f273ca..74955f458fbb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.15" +#define DC_VER "3.1.16" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From 97110c98a0fa2091190dc3068734ef9f1c12b588 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 31 Oct 2017 14:41:41 -0400 Subject: [PATCH 0815/2547] drm/amd/display: Remove extra arr_points element arr_points[1] and [2] were duplicated. Remove the extra one. If we ever need more points we can add them but the current state of affairs is confusing. Signed-off-by: Harry Wentland Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 2 +- .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 ------- .../gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 7 ------- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 2 +- 5 files changed, 3 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index 4ff874a43f7a..543b4901e987 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1277,7 +1277,7 @@ static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce, REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y, - REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope); + REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[1].custom_float_slope); curve = params->arr_curve_points; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index d22745e6dff0..6b3ab4320b0c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -539,8 +539,6 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func dal_fixed31_32_from_int(segment_start)); arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), dal_fixed31_32_from_int(segment_end)); - arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); y_r = rgb_resulted[0].red; y_g = rgb_resulted[0].green; @@ -563,10 +561,8 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); arr_points[1].y = y3_max; - arr_points[2].y = y3_max; arr_points[1].slope = dal_fixed31_32_zero; - arr_points[2].slope = dal_fixed31_32_zero; if (output_tf->tf == TRANSFER_FUNCTION_PQ) { /* for PQ, we want to have a straight line from last HW X point, @@ -578,9 +574,6 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func arr_points[1].slope = dal_fixed31_32_div( dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), dal_fixed31_32_sub(end_value, arr_points[1].x)); - arr_points[2].slope = dal_fixed31_32_div( - dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), - dal_fixed31_32_sub(end_value, arr_points[1].x)); } regamma_params->hw_points_num = hw_points; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c index e98ed3058ea2..9b65b77e8823 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c @@ -175,7 +175,7 @@ static void regamma_config_regions_and_segments( value = 0; set_reg_field_value( value, - params->arr_points[2].custom_float_slope, + params->arr_points[1].custom_float_slope, GAMMA_CORR_CNTLA_END_CNTL2, GAMMA_CORR_CNTLA_EXP_REGION_END_BASE); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 666c6c0f882a..c4a6ad3f7e25 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1158,8 +1158,6 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func dal_fixed31_32_from_int(segment_start)); arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), dal_fixed31_32_from_int(segment_end)); - arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); y_r = rgb_resulted[0].red; y_g = rgb_resulted[0].green; @@ -1181,10 +1179,8 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); arr_points[1].y = y3_max; - arr_points[2].y = y3_max; arr_points[1].slope = dal_fixed31_32_zero; - arr_points[2].slope = dal_fixed31_32_zero; if (output_tf->tf == TRANSFER_FUNCTION_PQ) { /* for PQ, we want to have a straight line from last HW X point, @@ -1196,9 +1192,6 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func arr_points[1].slope = dal_fixed31_32_div( dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), dal_fixed31_32_sub(end_value, arr_points[1].x)); - arr_points[2].slope = dal_fixed31_32_div( - dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), - dal_fixed31_32_sub(end_value, arr_points[1].x)); } regamma_params->hw_points_num = hw_points; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index fa3d100de264..a650ede413d1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -73,7 +73,7 @@ struct pwl_result_data { struct pwl_params { struct gamma_curve arr_curve_points[34]; - struct curve_points arr_points[3]; + struct curve_points arr_points[2]; struct pwl_result_data rgb_resulted[256 + 3]; uint32_t hw_points_num; }; -- GitLab From b310b081ad744dca288af33ef8331796840a1da2 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 31 Oct 2017 15:16:56 -0400 Subject: [PATCH 0816/2547] drm/amd/display: Bunch more color indentation cleanups Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce/dce_transform.c | 104 +++++++++--------- .../display/dc/dce110/dce110_hw_sequencer.c | 54 ++++----- 2 files changed, 69 insertions(+), 89 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index 543b4901e987..97414abbc69d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1183,81 +1183,75 @@ static void program_pwl( { uint32_t value; int retval; + uint8_t max_tries = 10; + uint8_t counter = 0; + uint32_t i = 0; + const struct pwl_result_data *rgb = params->rgb_resulted; - { - uint8_t max_tries = 10; - uint8_t counter = 0; + /* Power on LUT memory */ + if (REG(DCFE_MEM_PWR_CTRL)) + REG_UPDATE(DCFE_MEM_PWR_CTRL, + DCP_REGAMMA_MEM_PWR_DIS, 1); + else + REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_LIGHT_SLEEP_DIS, 1); - /* Power on LUT memory */ - if (REG(DCFE_MEM_PWR_CTRL)) - REG_UPDATE(DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS, 1); - else - REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS, 1); - - while (counter < max_tries) { - if (REG(DCFE_MEM_PWR_STATUS)) { - value = REG_READ(DCFE_MEM_PWR_STATUS); - REG_GET(DCFE_MEM_PWR_STATUS, - DCP_REGAMMA_MEM_PWR_STATE, - &retval); - - if (retval == 0) - break; - ++counter; - } else { - value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL); - REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_MEM_PWR_STATE, - &retval); - - if (retval == 0) - break; - ++counter; - } + while (counter < max_tries) { + if (REG(DCFE_MEM_PWR_STATUS)) { + value = REG_READ(DCFE_MEM_PWR_STATUS); + REG_GET(DCFE_MEM_PWR_STATUS, + DCP_REGAMMA_MEM_PWR_STATE, + &retval); + + if (retval == 0) + break; + ++counter; + } else { + value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL); + REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_MEM_PWR_STATE, + &retval); + + if (retval == 0) + break; + ++counter; } + } - if (counter == max_tries) { - dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING, + if (counter == max_tries) { + dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING, "%s: regamma lut was not powered on " "in a timely manner," " programming still proceeds\n", __func__); - } } REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK, - REGAMMA_LUT_WRITE_EN_MASK, 7); + REGAMMA_LUT_WRITE_EN_MASK, 7); REG_WRITE(REGAMMA_LUT_INDEX, 0); /* Program REGAMMA_LUT_DATA */ - { - uint32_t i = 0; - const struct pwl_result_data *rgb = params->rgb_resulted; + while (i != params->hw_points_num) { - while (i != params->hw_points_num) { + REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg); - - ++rgb; - ++i; - } + ++rgb; + ++i; } /* we are done with DCP LUT memory; re-enable low power mode */ if (REG(DCFE_MEM_PWR_CTRL)) REG_UPDATE(DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS, 0); + DCP_REGAMMA_MEM_PWR_DIS, 0); else REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS, 0); + REGAMMA_LUT_LIGHT_SLEEP_DIS, 0); } static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce, @@ -1358,12 +1352,12 @@ void dce110_opp_power_on_regamma_lut(struct transform *xfm, if (REG(DCFE_MEM_PWR_CTRL)) REG_UPDATE_2(DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS, power_on, - DCP_LUT_MEM_PWR_DIS, power_on); + DCP_REGAMMA_MEM_PWR_DIS, power_on, + DCP_LUT_MEM_PWR_DIS, power_on); else REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on, - DCP_LUT_LIGHT_SLEEP_DIS, power_on); + REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on, + DCP_LUT_LIGHT_SLEEP_DIS, power_on); } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6b3ab4320b0c..97630fcd230f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -432,8 +432,9 @@ static bool convert_to_custom_float( return true; } -static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func - *output_tf, struct pwl_params *regamma_params) +static bool +dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, + struct pwl_params *regamma_params) { struct curve_points *arr_points; struct pwl_result_data *rgb_resulted; @@ -448,8 +449,7 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func int32_t segment_start, segment_end; uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points; - if (output_tf == NULL || regamma_params == NULL || - output_tf->type == TF_TYPE_BYPASS) + if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) return false; arr_points = regamma_params->arr_points; @@ -528,17 +528,14 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func /* last point */ start_index = (segment_end + 25) * 32; - rgb_resulted[hw_points - 1].red = - output_tf->tf_pts.red[start_index]; - rgb_resulted[hw_points - 1].green = - output_tf->tf_pts.green[start_index]; - rgb_resulted[hw_points - 1].blue = - output_tf->tf_pts.blue[start_index]; + rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; + rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; + rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_start)); + dal_fixed31_32_from_int(segment_start)); arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); + dal_fixed31_32_from_int(segment_end)); y_r = rgb_resulted[0].red; y_g = rgb_resulted[0].green; @@ -547,9 +544,8 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); arr_points[0].y = y1_min; - arr_points[0].slope = dal_fixed31_32_div( - arr_points[0].y, - arr_points[0].x); + arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, + arr_points[0].x); y_r = rgb_resulted[hw_points - 1].red; y_g = rgb_resulted[hw_points - 1].green; @@ -568,12 +564,11 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func /* for PQ, we want to have a straight line from last HW X point, * and the slope to be such that we hit 1.0 at 10000 nits. */ - const struct fixed31_32 end_value = - dal_fixed31_32_from_int(125); + const struct fixed31_32 end_value = dal_fixed31_32_from_int(125); arr_points[1].slope = dal_fixed31_32_div( - dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), - dal_fixed31_32_sub(end_value, arr_points[1].x)); + dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), + dal_fixed31_32_sub(end_value, arr_points[1].x)); } regamma_params->hw_points_num = hw_points; @@ -581,18 +576,15 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func i = 1; for (k = 0; k < 16 && i < 16; k++) { if (seg_distr[k] != -1) { - regamma_params->arr_curve_points[k].segments_num = - seg_distr[k]; + regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; regamma_params->arr_curve_points[i].offset = - regamma_params->arr_curve_points[k]. - offset + (1 << seg_distr[k]); + regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); } i++; } if (seg_distr[k] != -1) - regamma_params->arr_curve_points[k].segments_num = - seg_distr[k]; + regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; rgb = rgb_resulted; rgb_plus_1 = rgb_resulted + 1; @@ -607,15 +599,9 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) rgb_plus_1->blue = rgb->blue; - rgb->delta_red = dal_fixed31_32_sub( - rgb_plus_1->red, - rgb->red); - rgb->delta_green = dal_fixed31_32_sub( - rgb_plus_1->green, - rgb->green); - rgb->delta_blue = dal_fixed31_32_sub( - rgb_plus_1->blue, - rgb->blue); + rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red); + rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green); + rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue); ++rgb_plus_1; ++rgb; -- GitLab From a696dc208fa123d7c710ae757d3f621e9ab8b081 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 31 Oct 2017 15:17:27 -0400 Subject: [PATCH 0817/2547] drm/amd/display: Remove unused register read in program_pwl Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index 97414abbc69d..330dbe9989d4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1181,7 +1181,6 @@ static void program_pwl( struct dce_transform *xfm_dce, const struct pwl_params *params) { - uint32_t value; int retval; uint8_t max_tries = 10; uint8_t counter = 0; @@ -1198,7 +1197,6 @@ static void program_pwl( while (counter < max_tries) { if (REG(DCFE_MEM_PWR_STATUS)) { - value = REG_READ(DCFE_MEM_PWR_STATUS); REG_GET(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, &retval); @@ -1207,7 +1205,6 @@ static void program_pwl( break; ++counter; } else { - value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL); REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, &retval); -- GitLab From bd1be8e894e4963595a35ebeff512dc63d3ee328 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 1 Nov 2017 14:31:58 -0400 Subject: [PATCH 0818/2547] drm/amd/display: A few more color indentation changes Signed-off-by: Harry Wentland Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 33 +++-- .../drm/amd/display/dc/dce/dce_transform.c | 5 +- .../display/dc/dce110/dce110_hw_sequencer.c | 79 ++++-------- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 25 ++-- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 115 ++++++------------ 6 files changed, 96 insertions(+), 165 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c index d618fdd0cc82..d737e911971b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c @@ -135,36 +135,34 @@ static void dce_ipp_cursor_set_attributes( } -static void dce_ipp_program_prescale( - struct input_pixel_processor *ipp, - struct ipp_prescale_params *params) +static void dce_ipp_program_prescale(struct input_pixel_processor *ipp, + struct ipp_prescale_params *params) { struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); /* set to bypass mode first before change */ REG_UPDATE(PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS, - 1); + GRPH_PRESCALE_BYPASS, 1); REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, - GRPH_PRESCALE_SCALE_R, params->scale, - GRPH_PRESCALE_BIAS_R, params->bias); + GRPH_PRESCALE_SCALE_R, params->scale, + GRPH_PRESCALE_BIAS_R, params->bias); REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, - GRPH_PRESCALE_SCALE_G, params->scale, - GRPH_PRESCALE_BIAS_G, params->bias); + GRPH_PRESCALE_SCALE_G, params->scale, + GRPH_PRESCALE_BIAS_G, params->bias); REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, - GRPH_PRESCALE_SCALE_B, params->scale, - GRPH_PRESCALE_BIAS_B, params->bias); + GRPH_PRESCALE_SCALE_B, params->scale, + GRPH_PRESCALE_BIAS_B, params->bias); if (params->mode != IPP_PRESCALE_MODE_BYPASS) { REG_UPDATE(PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS, 0); + GRPH_PRESCALE_BYPASS, 0); /* If prescale is in use, then legacy lut should be bypassed */ REG_UPDATE(INPUT_GAMMA_CONTROL, - GRPH_INPUT_GAMMA_MODE, 1); + GRPH_INPUT_GAMMA_MODE, 1); } } @@ -223,13 +221,12 @@ static void dce_ipp_set_degamma( struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; - ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || - mode == IPP_DEGAMMA_MODE_HW_sRGB); + ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB); REG_SET_3(DEGAMMA_CONTROL, 0, - GRPH_DEGAMMA_MODE, degamma_type, - CURSOR_DEGAMMA_MODE, degamma_type, - CURSOR2_DEGAMMA_MODE, degamma_type); + GRPH_DEGAMMA_MODE, degamma_type, + CURSOR_DEGAMMA_MODE, degamma_type, + CURSOR2_DEGAMMA_MODE, degamma_type); } static const struct ipp_funcs dce_ipp_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index 330dbe9989d4..0f662e6ee9bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1177,9 +1177,8 @@ void dce110_opp_set_csc_default( default_adjust->out_color_space); } -static void program_pwl( - struct dce_transform *xfm_dce, - const struct pwl_params *params) +static void program_pwl(struct dce_transform *xfm_dce, + const struct pwl_params *params) { int retval; uint8_t max_tries = 10; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 97630fcd230f..4f321507ba06 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -307,10 +307,9 @@ dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, return result; } -static bool convert_to_custom_float( - struct pwl_result_data *rgb_resulted, - struct curve_points *arr_points, - uint32_t hw_points_num) +static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, + struct curve_points *arr_points, + uint32_t hw_points_num) { struct custom_float_format fmt; @@ -322,26 +321,20 @@ static bool convert_to_custom_float( fmt.mantissa_bits = 12; fmt.sign = true; - if (!convert_to_custom_float_format( - arr_points[0].x, - &fmt, - &arr_points[0].custom_float_x)) { + if (!convert_to_custom_float_format(arr_points[0].x, &fmt, + &arr_points[0].custom_float_x)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[0].offset, - &fmt, - &arr_points[0].custom_float_offset)) { + if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, + &arr_points[0].custom_float_offset)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[0].slope, - &fmt, - &arr_points[0].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, + &arr_points[0].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } @@ -349,26 +342,20 @@ static bool convert_to_custom_float( fmt.mantissa_bits = 10; fmt.sign = false; - if (!convert_to_custom_float_format( - arr_points[1].x, - &fmt, - &arr_points[1].custom_float_x)) { + if (!convert_to_custom_float_format(arr_points[1].x, &fmt, + &arr_points[1].custom_float_x)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[1].y, - &fmt, - &arr_points[1].custom_float_y)) { + if (!convert_to_custom_float_format(arr_points[1].y, &fmt, + &arr_points[1].custom_float_y)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[2].slope, - &fmt, - &arr_points[2].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[2].slope, &fmt, + &arr_points[2].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } @@ -377,50 +364,38 @@ static bool convert_to_custom_float( fmt.sign = true; while (i != hw_points_num) { - if (!convert_to_custom_float_format( - rgb->red, - &fmt, - &rgb->red_reg)) { + if (!convert_to_custom_float_format(rgb->red, &fmt, + &rgb->red_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->green, - &fmt, - &rgb->green_reg)) { + if (!convert_to_custom_float_format(rgb->green, &fmt, + &rgb->green_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->blue, - &fmt, - &rgb->blue_reg)) { + if (!convert_to_custom_float_format(rgb->blue, &fmt, + &rgb->blue_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_red, - &fmt, - &rgb->delta_red_reg)) { + if (!convert_to_custom_float_format(rgb->delta_red, &fmt, + &rgb->delta_red_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_green, - &fmt, - &rgb->delta_green_reg)) { + if (!convert_to_custom_float_format(rgb->delta_green, &fmt, + &rgb->delta_green_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_blue, - &fmt, - &rgb->delta_blue_reg)) { + if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, + &rgb->delta_blue_reg)) { BREAK_TO_DEBUGGER(); return false; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index d8929b31e5ba..8df3945370cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -213,8 +213,8 @@ static void dpp1_cm_set_regamma_pwl( else dpp1_cm_program_regamma_lutb_settings(dpp_base, params); - dpp1_cm_program_regamma_lut( - dpp_base, params->rgb_resulted, params->hw_points_num); + dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted, + params->hw_points_num); dpp->pwl_data = *params; re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index bb430c0ec1b6..b4892f43cd77 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -365,34 +365,31 @@ void dpp1_cm_set_output_csc_adjustment( dpp1_cm_program_color_matrix(dpp, tbl_entry); } -void dpp1_cm_power_on_regamma_lut( - struct dpp *dpp_base, - bool power_on) +void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, + bool power_on) { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); + REG_SET(CM_MEM_PWR_CTRL, 0, - RGAM_MEM_PWR_FORCE, power_on == true ? 0:1); + RGAM_MEM_PWR_FORCE, power_on == true ? 0:1); } -void dpp1_cm_program_regamma_lut( - struct dpp *dpp_base, - const struct pwl_result_data *rgb, - uint32_t num) +void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, + const struct pwl_result_data *rgb, + uint32_t num) { uint32_t i; struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); + for (i = 0 ; i < num; i++) { REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, - CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, - CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, - CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index c4a6ad3f7e25..cb73d25aca4c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -953,26 +953,20 @@ static bool convert_to_custom_float( fmt.mantissa_bits = 12; fmt.sign = false; - if (!convert_to_custom_float_format( - arr_points[0].x, - &fmt, - &arr_points[0].custom_float_x)) { + if (!convert_to_custom_float_format(arr_points[0].x, &fmt, + &arr_points[0].custom_float_x)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[0].offset, - &fmt, - &arr_points[0].custom_float_offset)) { + if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, + &arr_points[0].custom_float_offset)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[0].slope, - &fmt, - &arr_points[0].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, + &arr_points[0].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } @@ -980,26 +974,20 @@ static bool convert_to_custom_float( fmt.mantissa_bits = 10; fmt.sign = false; - if (!convert_to_custom_float_format( - arr_points[1].x, - &fmt, - &arr_points[1].custom_float_x)) { + if (!convert_to_custom_float_format(arr_points[1].x, &fmt, + &arr_points[1].custom_float_x)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[1].y, - &fmt, - &arr_points[1].custom_float_y)) { + if (!convert_to_custom_float_format(arr_points[1].y, &fmt, + &arr_points[1].custom_float_y)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[1].slope, - &fmt, - &arr_points[1].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, + &arr_points[1].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } @@ -1008,50 +996,38 @@ static bool convert_to_custom_float( fmt.sign = true; while (i != hw_points_num) { - if (!convert_to_custom_float_format( - rgb->red, - &fmt, - &rgb->red_reg)) { + if (!convert_to_custom_float_format(rgb->red, &fmt, + &rgb->red_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->green, - &fmt, - &rgb->green_reg)) { + if (!convert_to_custom_float_format(rgb->green, &fmt, + &rgb->green_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->blue, - &fmt, - &rgb->blue_reg)) { + if (!convert_to_custom_float_format(rgb->blue, &fmt, + &rgb->blue_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_red, - &fmt, - &rgb->delta_red_reg)) { + if (!convert_to_custom_float_format(rgb->delta_red, &fmt, + &rgb->delta_red_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_green, - &fmt, - &rgb->delta_green_reg)) { + if (!convert_to_custom_float_format(rgb->delta_green, &fmt, + &rgb->delta_green_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_blue, - &fmt, - &rgb->delta_blue_reg)) { + if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, + &rgb->delta_blue_reg)) { BREAK_TO_DEBUGGER(); return false; } @@ -1066,8 +1042,9 @@ static bool convert_to_custom_float( #define MAX_LOW_POINT 25 #define NUMBER_SEGMENTS 32 -static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func - *output_tf, struct pwl_params *regamma_params) +static bool +dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, + struct pwl_params *regamma_params) { struct curve_points *arr_points; struct pwl_result_data *rgb_resulted; @@ -1083,8 +1060,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func int32_t i; uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; - if (output_tf == NULL || regamma_params == NULL || - output_tf->type == TF_TYPE_BYPASS) + if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) return false; arr_points = regamma_params->arr_points; @@ -1147,17 +1123,14 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func /* last point */ start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS; - rgb_resulted[hw_points - 1].red = - output_tf->tf_pts.red[start_index]; - rgb_resulted[hw_points - 1].green = - output_tf->tf_pts.green[start_index]; - rgb_resulted[hw_points - 1].blue = - output_tf->tf_pts.blue[start_index]; + rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; + rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; + rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_start)); + dal_fixed31_32_from_int(segment_start)); arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); + dal_fixed31_32_from_int(segment_end)); y_r = rgb_resulted[0].red; y_g = rgb_resulted[0].green; @@ -1166,9 +1139,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); arr_points[0].y = y1_min; - arr_points[0].slope = dal_fixed31_32_div( - arr_points[0].y, - arr_points[0].x); + arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, arr_points[0].x); y_r = rgb_resulted[hw_points - 1].red; y_g = rgb_resulted[hw_points - 1].green; y_b = rgb_resulted[hw_points - 1].blue; @@ -1202,15 +1173,13 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; regamma_params->arr_curve_points[i].offset = - regamma_params->arr_curve_points[k]. - offset + (1 << seg_distr[k]); + regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); } i++; } if (seg_distr[k] != -1) - regamma_params->arr_curve_points[k].segments_num = - seg_distr[k]; + regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; rgb = rgb_resulted; rgb_plus_1 = rgb_resulted + 1; @@ -1225,15 +1194,9 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) rgb_plus_1->blue = rgb->blue; - rgb->delta_red = dal_fixed31_32_sub( - rgb_plus_1->red, - rgb->red); - rgb->delta_green = dal_fixed31_32_sub( - rgb_plus_1->green, - rgb->green); - rgb->delta_blue = dal_fixed31_32_sub( - rgb_plus_1->blue, - rgb->blue); + rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red); + rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green); + rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue); ++rgb_plus_1; ++rgb; -- GitLab From e14ca957797470978cf2a8b18c1a136b6cb7dc8f Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Fri, 3 Nov 2017 17:58:42 -0400 Subject: [PATCH 0819/2547] drm/amd/display: combine output signal and signal output signal used to be a public member to be used by DM to override the stream signal. Now since there is no longer separation between public and private part of stream, they are combined. The overriding was not working properly as well, which is addressed by this change Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 15 ++++++--------- drivers/gpu/drm/amd/display/dc/dc.h | 2 -- 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index e230cc44a0a7..375fb457e223 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -36,16 +36,13 @@ #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000 static void update_stream_signal(struct dc_stream_state *stream) { - if (stream->output_signal == SIGNAL_TYPE_NONE) { - struct dc_sink *dc_sink = stream->sink; - if (dc_sink->sink_signal == SIGNAL_TYPE_NONE) - stream->signal = stream->sink->link->connector_signal; - else - stream->signal = dc_sink->sink_signal; - } else { - stream->signal = stream->output_signal; - } + struct dc_sink *dc_sink = stream->sink; + + if (dc_sink->sink_signal == SIGNAL_TYPE_NONE) + stream->signal = stream->sink->link->connector_signal; + else + stream->signal = dc_sink->sink_signal; if (dc_is_dvi_signal(stream->signal)) { if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST && diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 74955f458fbb..f2647b40f3cb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -579,8 +579,6 @@ struct dc_stream_state { struct colorspace_transform gamut_remap_matrix; struct csc_transform csc_color_matrix; - enum signal_type output_signal; - enum dc_color_space output_color_space; enum dc_dither_option dither_option; -- GitLab From 2a875c41cd520399a72e4bef8779cf13d0c7ed14 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Mon, 6 Nov 2017 11:56:21 -0500 Subject: [PATCH 0820/2547] drm/amd/display: Report pitch_alignment for DCN Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f2647b40f3cb..459a1c55b5cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -58,6 +58,7 @@ struct dc_caps { uint32_t i2c_speed_in_khz; unsigned int max_cursor_size; unsigned int max_video_width; + int pitch_alignment; bool dcc_const_color; bool dynamic_audio; bool is_apu; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 340ff1158c10..531402a50c2c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1269,7 +1269,7 @@ static bool construct( dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 100; dc->caps.max_cursor_size = 256; - + dc->caps.pitch_alignment = 64; /* Alignment is 64 on DCN1 */ dc->caps.max_slave_planes = 1; dc->caps.is_apu = true; -- GitLab From 5fd9f8a10f7cfcb584cdb993610491baa4fc4611 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Mon, 6 Nov 2017 15:53:36 -0500 Subject: [PATCH 0821/2547] drm/amd/display: Loosen plane_info and scaling_info checks Make it so that differing dcc and plane size fields don't necessarily result in a full update, along with upscaling modes. This allows us to save some unnecessary full updates. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 5745304b5af5..4c078c284f90 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1169,9 +1169,7 @@ static enum surface_update_type get_plane_info_update_type( /* Full update parameters */ temp_plane_info.color_space = u->surface->color_space; temp_plane_info.input_tf = u->surface->input_tf; - temp_plane_info.dcc = u->surface->dcc; temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror; - temp_plane_info.plane_size = u->surface->plane_size; temp_plane_info.rotation = u->surface->rotation; temp_plane_info.stereo_format = u->surface->stereo_format; @@ -1214,14 +1212,23 @@ static enum surface_update_type get_scaling_info_update_type( if (!u->scaling_info) return UPDATE_TYPE_FAST; - if (u->scaling_info->src_rect.width != u->surface->src_rect.width - || u->scaling_info->src_rect.height != u->surface->src_rect.height - || u->scaling_info->clip_rect.width != u->surface->clip_rect.width + if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width || u->scaling_info->clip_rect.height != u->surface->clip_rect.height || u->scaling_info->dst_rect.width != u->surface->dst_rect.width || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) return UPDATE_TYPE_FULL; + if (u->scaling_info->src_rect.width != u->surface->src_rect.width + || u->scaling_info->src_rect.height != u->surface->src_rect.height) { + + if (u->scaling_info->src_rect.width > u->surface->src_rect.width + && u->scaling_info->src_rect.height > u->surface->src_rect.height) + return UPDATE_TYPE_FULL; + + /* Upscaling does not require a full update */ + return UPDATE_TYPE_MED; + } + if (u->scaling_info->src_rect.x != u->surface->src_rect.x || u->scaling_info->src_rect.y != u->surface->src_rect.y || u->scaling_info->clip_rect.x != u->surface->clip_rect.x -- GitLab From 950d9265b046de3a296ef670683d826baf528c67 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 31 Oct 2017 17:29:18 -0400 Subject: [PATCH 0822/2547] drm/amd/display: remove dcn10 wait on tg unlock Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index d248067810c8..73ff78f9cae1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -571,11 +571,6 @@ static void tgn10_unlock(struct timing_generator *tg) REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK, 0); - - /* why are we waiting here? */ - REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, - OTG_UPDATE_PENDING, 0, - 1, 100000); } static void tgn10_get_position(struct timing_generator *tg, -- GitLab From 7f914a62c94fb29b96a88d72c9a2688db95275cf Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Mon, 6 Nov 2017 14:40:31 -0500 Subject: [PATCH 0823/2547] drm/amd/display: Apply work around for stutter. Power on one plane after disable all the planes, for a hw bug work around to resolve stutter efficiency issue. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- .../display/dc/dce110/dce110_hw_sequencer.c | 10 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 153 ++++++++---------- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 3 + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 10 +- 6 files changed, 84 insertions(+), 95 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 4c078c284f90..7578b4a9ee5b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -974,7 +974,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) if (context->res_ctx.pipe_ctx[i].stream == NULL || context->res_ctx.pipe_ctx[i].plane_state == NULL) { context->res_ctx.pipe_ctx[i].pipe_idx = i; - dc->hwss.power_down_front_end(dc, &context->res_ctx.pipe_ctx[i]); + dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]); } /* 3rd param should be true, temp w/a for RV*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 4f321507ba06..750bbe9edf5c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1411,7 +1411,7 @@ static void disable_vga_and_power_gate_all_controllers( true); dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; - dc->hwss.power_down_front_end(dc, + dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); } } @@ -1838,7 +1838,7 @@ static void dce110_reset_hw_ctx_wrap( if (old_clk) old_clk->funcs->cs_power_down(old_clk); - dc->hwss.power_down_front_end(dc, pipe_ctx_old); + dc->hwss.disable_plane(dc, pipe_ctx_old); pipe_ctx_old->stream = NULL; } @@ -2063,8 +2063,8 @@ enum dc_status dce110_apply_ctx_to_hw( context, dc); - if (dc->hwss.power_on_front_end) - dc->hwss.power_on_front_end(dc, pipe_ctx, context); + if (dc->hwss.enable_plane) + dc->hwss.enable_plane(dc, pipe_ctx, context); if (DC_OK != status) return status; @@ -2969,7 +2969,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .unblank_stream = dce110_unblank_stream, .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, .enable_display_power_gating = dce110_enable_display_power_gating, - .power_down_front_end = dce110_power_down_fe, + .disable_plane = dce110_power_down_fe, .pipe_control_lock = dce_pipe_control_lock, .set_bandwidth = dce110_set_bandwidth, .set_drr = set_drr, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index cb73d25aca4c..7d1821fb3607 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -363,11 +363,8 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = dc->res_pool->hubps[0]; - int pwr_status = 0; - REG_GET(DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, &pwr_status); - /* Don't need to blank if hubp is power gated*/ - if (pwr_status == 2) + if (!hws->wa_state.DEGVIDCN10_253_applied) return; hubp->funcs->set_blank(hubp, true); @@ -378,16 +375,29 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) hubp_pg_control(hws, 0, false); REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); + + hws->wa_state.DEGVIDCN10_253_applied = false; } static void apply_DEGVIDCN10_253_wa(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = dc->res_pool->hubps[0]; + int i; if (dc->debug.disable_stutter) return; + if (!hws->wa.DEGVIDCN10_253) + return; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (!dc->res_pool->hubps[i]->power_gated) + return; + } + + /* all pipe power gated, apply work around to enable stutter. */ + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); @@ -396,6 +406,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) IP_REQUEST_EN, 0); hubp->funcs->set_hubp_blank_en(hubp, false); + hws->wa_state.DEGVIDCN10_253_applied = true; } static void bios_golden_init(struct dc *dc) @@ -592,61 +603,14 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) if (dc->debug.sanity_checks) dcn10_verify_allow_pstate_change_high(dc); - if (pipe_ctx->top_pipe) { - pipe_ctx->top_pipe->bottom_pipe = NULL; - pipe_ctx->top_pipe = NULL; - pipe_ctx->stream = NULL; - memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); - memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); - } - - if (pipe_ctx->bottom_pipe) { - pipe_ctx->bottom_pipe->top_pipe = NULL; - pipe_ctx->bottom_pipe = NULL; - } + pipe_ctx->stream = NULL; + memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); + memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); + pipe_ctx->top_pipe = NULL; + pipe_ctx->bottom_pipe = NULL; pipe_ctx->plane_state = NULL; } -/* disable HW used by plane. - * note: cannot disable until disconnect is complete */ -static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) -{ - int fe_idx = pipe_ctx->pipe_idx; - struct dce_hwseq *hws = dc->hwseq; - struct hubp *hubp = dc->res_pool->hubps[fe_idx]; - struct mpc *mpc = dc->res_pool->mpc; - int opp_id = hubp->opp_id; - - if (opp_id == 0xf) - return; - - mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id); - dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false; - /*dm_logger_write(dc->ctx->logger, LOG_ERROR, - "[debug_mpo: atomic disable finished on mpcc %d]\n", - fe_idx);*/ - - hubp->funcs->set_blank(hubp, true); - - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); - - REG_UPDATE(HUBP_CLK_CNTL[fe_idx], - HUBP_CLOCK_ENABLE, 0); - REG_UPDATE(DPP_CONTROL[fe_idx], - DPP_CLOCK_ENABLE, 0); - - if (dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0) - REG_UPDATE(OPP_PIPE_CONTROL[opp_id], - OPP_PIPE_CLOCK_EN, 0); - - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); -} - -/* kill power to plane hw - * note: cannot power down until plane is disable - */ static void plane_atomic_power_down(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; @@ -665,29 +629,51 @@ static void plane_atomic_power_down(struct dc *dc, int fe_idx) } } -static void dcn10_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) +/* disable HW used by plane. + * note: cannot disable until disconnect is complete + */ +static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) { int fe_idx = pipe_ctx->pipe_idx; - struct timing_generator *tg = pipe_ctx->stream_res.tg; - - if (tg != NULL) { - tg->funcs->lock(tg); + struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = dc->res_pool->hubps[fe_idx]; + struct mpc *mpc = dc->res_pool->mpc; + int opp_id = hubp->opp_id; + struct output_pixel_processor *opp; - plane_atomic_disconnect(dc, pipe_ctx); + if (opp_id != 0xf) { + mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id); + opp = dc->res_pool->opps[hubp->opp_id]; + opp->mpcc_disconnect_pending[hubp->mpcc_id] = false; + hubp->funcs->set_blank(hubp, true); + } - tg->funcs->unlock(tg); + REG_UPDATE(HUBP_CLK_CNTL[fe_idx], + HUBP_CLOCK_ENABLE, 0); + REG_UPDATE(DPP_CONTROL[fe_idx], + DPP_CLOCK_ENABLE, 0); - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); + if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0) + REG_UPDATE(OPP_PIPE_CONTROL[opp_id], + OPP_PIPE_CLOCK_EN, 0); - plane_atomic_disable(dc, pipe_ctx); - } + hubp->power_gated = true; plane_atomic_power_down(dc, fe_idx); +} + +static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) +{ + if (dc->res_pool->hubps[pipe_ctx->pipe_idx]->power_gated) + return; + + plane_atomic_disable(dc, pipe_ctx); + + apply_DEGVIDCN10_253_wa(dc); dm_logger_write(dc->ctx->logger, LOG_DC, - "Reset front end %d\n", - fe_idx); + "Power down front end %d\n", + pipe_ctx->pipe_idx); } static void dcn10_init_hw(struct dc *dc) @@ -780,8 +766,7 @@ static void dcn10_init_hw(struct dc *dc) struct timing_generator *tg = dc->res_pool->timing_generators[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - plane_atomic_disable(dc, pipe_ctx); - plane_atomic_power_down(dc, i); + dcn10_disable_plane(dc, pipe_ctx); pipe_ctx->stream_res.tg = NULL; pipe_ctx->plane_res.hubp = NULL; @@ -1468,7 +1453,7 @@ static void print_rq_dlg_ttu( ); } -static void dcn10_power_on_fe( +static void dcn10_enable_plane( struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context) @@ -1480,6 +1465,8 @@ static void dcn10_power_on_fe( dcn10_verify_allow_pstate_change_high(dc); } + undo_DEGVIDCN10_253_wa(dc); + power_on_plane(dc->hwseq, pipe_ctx->pipe_idx); @@ -1946,6 +1933,8 @@ static void update_dchubp_dpp( &plane_state->dcc, plane_state->horizontal_mirror); + hubp->power_gated = false; + dc->hwss.update_plane_addr(dc, pipe_ctx); if (is_pipe_tree_visible(pipe_ctx)) @@ -1988,7 +1977,7 @@ static void program_all_pipe_in_tree( struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - dcn10_power_on_fe(dc, pipe_ctx, context); + dcn10_enable_plane(dc, pipe_ctx, context); /* temporary dcn1 wa: * watermark update requires toggle after a/b/c/d sets are programmed @@ -2063,7 +2052,6 @@ static void dcn10_pplib_apply_display_requirements( static void optimize_shared_resources(struct dc *dc) { if (dc->current_state->stream_count == 0) { - apply_DEGVIDCN10_253_wa(dc); /* S0i2 message */ dcn10_pplib_apply_display_requirements(dc, dc->current_state); } @@ -2074,10 +2062,6 @@ static void optimize_shared_resources(struct dc *dc) static void ready_shared_resources(struct dc *dc, struct dc_state *context) { - if (dc->current_state->stream_count == 0 && - !dc->debug.disable_stutter) - undo_DEGVIDCN10_253_wa(dc); - /* S0i2 message */ if (dc->current_state->stream_count == 0 && context->stream_count != 0) @@ -2152,7 +2136,7 @@ static void dcn10_apply_ctx_for_surface( if (old_pipe_ctx->stream_res.tg == tg && old_pipe_ctx->plane_res.hubp && old_pipe_ctx->plane_res.hubp->opp_id != 0xf) { - dcn10_power_down_fe(dc, pipe_ctx); + dcn10_disable_plane(dc, pipe_ctx); /* * power down fe will unlock when calling reset, need * to lock it back here. Messy, need rework. @@ -2184,14 +2168,10 @@ static void dcn10_apply_ctx_for_surface( struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - if (removed_pipe[i]) { - plane_atomic_disable(dc, old_pipe_ctx); - if (num_planes == 0) - plane_atomic_power_down(dc, i); - } + if (removed_pipe[i] && num_planes == 0) + dcn10_disable_plane(dc, old_pipe_ctx); } - dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, "\n============== Watermark parameters ==============\n" "a.urgent_ns: %d \n" @@ -2514,8 +2494,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .disable_stream = dce110_disable_stream, .unblank_stream = dce110_unblank_stream, .enable_display_power_gating = dcn10_dummy_display_power_gating, - .power_down_front_end = dcn10_power_down_fe, - .power_on_front_end = dcn10_power_on_fe, + .disable_plane = dcn10_disable_plane, .pipe_control_lock = dcn10_pipe_control_lock, .set_bandwidth = dcn10_set_bandwidth, .reset_hw_ctx_wrap = reset_hw_ctx_wrap, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 531402a50c2c..209499e5f53b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -677,6 +677,7 @@ static struct dce_hwseq *dcn10_hwseq_create( hws->regs = &hwseq_reg; hws->shifts = &hwseq_shift; hws->masks = &hwseq_mask; + hws->wa.DEGVIDCN10_253 = true; } return hws; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 3286585bd6cd..49b12f602e79 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -34,9 +34,12 @@ struct hubp { struct dc_plane_address request_address; struct dc_plane_address current_address; int inst; + + /* run time states */ int opp_id; int mpcc_id; struct dc_cursor_attributes curs_attr; + bool power_gated; }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 1d8852683f1f..5dc4ecf618ff 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -39,6 +39,11 @@ enum pipe_gating_control { struct dce_hwseq_wa { bool blnd_crtc_trigger; + bool DEGVIDCN10_253; +}; + +struct hwseq_wa_state { + bool DEGVIDCN10_253_applied; }; struct dce_hwseq { @@ -47,6 +52,7 @@ struct dce_hwseq { const struct dce_hwseq_shift *shifts; const struct dce_hwseq_mask *masks; struct dce_hwseq_wa wa; + struct hwseq_wa_state wa_state; }; struct pipe_ctx; @@ -129,9 +135,9 @@ struct hw_sequencer_funcs { struct dc_bios *dcb, enum pipe_gating_control power_gating); - void (*power_down_front_end)(struct dc *dc, struct pipe_ctx *pipe_ctx); + void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); - void (*power_on_front_end)(struct dc *dc, + void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe, struct dc_state *context); -- GitLab From 2194e3ae902a89579141d860d010d78d422cbc4f Mon Sep 17 00:00:00 2001 From: Roman Li Date: Tue, 7 Nov 2017 10:58:40 -0500 Subject: [PATCH 0824/2547] drm/amd/display: Fix unbalanced locking in surface apply also simplifying syntax and removing unused variable in dce110_apply_ctx_for_surface() Signed-off-by: Roman Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 750bbe9edf5c..09051dfe1844 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2849,22 +2849,19 @@ static void dce110_apply_ctx_for_surface( int num_planes, struct dc_state *context) { - int i, be_idx; + int i; if (num_planes == 0) return; - be_idx = -1; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - if (stream == context->res_ctx.pipe_ctx[i].stream) { - be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst; + if (stream == pipe_ctx->stream) { if (!pipe_ctx->top_pipe && (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) dc->hwss.pipe_control_lock(dc, pipe_ctx, true); - break; } } -- GitLab From b8fce2c9d773e178380cfeb659ebe453a8216f4b Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 7 Nov 2017 11:01:34 -0500 Subject: [PATCH 0825/2547] drm/amd/display: Optimize programming front end In case of update type is medium, optimize squence, reduce programing time. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 22 ++++------ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 42 +++++++++---------- 2 files changed, 27 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 7578b4a9ee5b..e0f13d79911d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1353,7 +1353,7 @@ static void commit_planes_for_stream(struct dc *dc, for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state) + if (update_type == UPDATE_TYPE_FAST || !pipe_ctx->plane_state) continue; if (!pipe_ctx->top_pipe && @@ -1374,26 +1374,20 @@ static void commit_planes_for_stream(struct dc *dc, for (i = 0; i < surface_count; i++) { struct dc_plane_state *plane_state = srf_updates[i].surface; - if (update_type == UPDATE_TYPE_MED) - dc->hwss.apply_ctx_for_surface( - dc, stream, surface_count, context); - for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (pipe_ctx->plane_state != plane_state) + if (pipe_ctx->stream != stream) continue; - if (srf_updates[i].flip_addr) - dc->hwss.update_plane_addr(dc, pipe_ctx); - - if (update_type == UPDATE_TYPE_FAST) + if (pipe_ctx->plane_state != plane_state) continue; - /* work around to program degamma regs for split pipe after set mode. */ - if (srf_updates[i].in_transfer_func || - (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state)) - dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); + if (update_type == UPDATE_TYPE_FAST) { + if (srf_updates[i].flip_addr) + dc->hwss.update_plane_addr(dc, pipe_ctx); + continue; + } } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7d1821fb3607..ffce33fb5540 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -555,7 +555,7 @@ static void reset_back_end_for_pipe( pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); } -void dcn10_verify_allow_pstate_change_high(struct dc *dc) +static void dcn10_verify_allow_pstate_change_high(struct dc *dc) { static bool should_log_hw_state; /* prevent hw state log by default */ @@ -1331,7 +1331,7 @@ static void dcn10_enable_per_frame_crtc_position_reset( DC_SYNC_INFO("Multi-display sync is complete\n"); } -static void print_rq_dlg_ttu( +/*static void print_rq_dlg_ttu( struct dc *core_dc, struct pipe_ctx *pipe_ctx) { @@ -1452,13 +1452,13 @@ static void print_rq_dlg_ttu( pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear ); } +*/ static void dcn10_enable_plane( struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context) { - struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dce_hwseq *hws = dc->hwseq; if (dc->debug.sanity_checks) { @@ -1479,6 +1479,7 @@ static void dcn10_enable_plane( OPP_PIPE_CLOCK_EN, 1); /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/ +/* TODO: enable/disable in dm as per update type. if (plane_state) { dm_logger_write(dc->ctx->logger, LOG_DC, "Pipe:%d 0x%x: addr hi:0x%x, " @@ -1514,6 +1515,7 @@ static void dcn10_enable_plane( pipe_ctx->plane_res.scl_data.recout.y); print_rq_dlg_ttu(dc, pipe_ctx); } +*/ if (dc->debug.sanity_checks) { dcn10_verify_allow_pstate_change_high(dc); @@ -1947,16 +1949,8 @@ static void program_all_pipe_in_tree( struct pipe_ctx *pipe_ctx, struct dc_state *context) { - unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000; - if (pipe_ctx->top_pipe == NULL) { - /* lock otg_master_update to process all pipes associated with - * this OTG. this is done only one time. - */ - /* watermark is for all pipes */ - hubbub1_program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, ref_clk_mhz); - if (dc->debug.sanity_checks) { /* pstate stuck check after watermark update */ dcn10_verify_allow_pstate_change_high(dc); @@ -1979,17 +1973,6 @@ static void program_all_pipe_in_tree( dcn10_enable_plane(dc, pipe_ctx, context); - /* temporary dcn1 wa: - * watermark update requires toggle after a/b/c/d sets are programmed - * if hubp is pg then wm value doesn't get properaged to hubp - * need to toggle after ungate to ensure wm gets to hubp. - * - * final solution: we need to get SMU to do the toggle as - * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have - * both driver and fw accessing same register - */ - hubbub1_toggle_watermark_change_req(dc->res_pool->hubbub); - update_dchubp_dpp(dc, pipe_ctx, context); /* TODO: this is a hack w/a for switching from mpo to pipe split */ @@ -2101,6 +2084,7 @@ static void dcn10_apply_ctx_for_surface( int i; struct timing_generator *tg; bool removed_pipe[4] = { false }; + unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000; struct pipe_ctx *top_pipe_to_program = find_top_pipe_for_stream(dc, context, stream); @@ -2163,7 +2147,6 @@ static void dcn10_apply_ctx_for_surface( tg->funcs->unlock(tg); - for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -2172,6 +2155,19 @@ static void dcn10_apply_ctx_for_surface( dcn10_disable_plane(dc, old_pipe_ctx); } + if (dc->debug.sanity_checks) { + /* pstate stuck check after watermark update */ + dcn10_verify_allow_pstate_change_high(dc); + } + /* watermark is for all pipes */ + hubbub1_program_watermarks(dc->res_pool->hubbub, + &context->bw.dcn.watermarks, ref_clk_mhz); + + if (dc->debug.sanity_checks) { + /* pstate stuck check after watermark update */ + dcn10_verify_allow_pstate_change_high(dc); + } + dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, "\n============== Watermark parameters ==============\n" "a.urgent_ns: %d \n" -- GitLab From 4faf6eddfbebba1cdc4653484b7a8c8f28bd3bff Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Tue, 7 Nov 2017 13:21:02 -0500 Subject: [PATCH 0826/2547] drm/amd/display: Remove dangling planes on dc commit state When disabling pipe splitting, we need to make sure we disable both planes used. This should be done for Linux as well. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e0f13d79911d..96267b9b99d5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -880,8 +880,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c if (!dcb->funcs->is_accelerated_mode(dcb)) dc->hwss.enable_accelerated_mode(dc); - - for (i = 0; i < context->stream_count; i++) { const struct dc_sink *sink = context->streams[i]->sink; -- GitLab From b674f1edc9a033f4d3ea61e5f4996186e27bdcb5 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Tue, 7 Nov 2017 13:51:02 -0500 Subject: [PATCH 0827/2547] drm/amd/display: Change frontend/backend programming sequence This is a follow-up to the following change: Yongqiang Sun: Program front end first when set mode. Due to pipe-splitting features, how we handle stream enabling and disabling needs to change. In the case of pipe split disable, two planes need to be combined back into the same stream. This needs to be done before any stream programming happens. The previous patch addresses this, but breaks cross-platform compatibility. It's not guaranteed that a dc commit will be called separately to program planes and streams. Therefore, we handle the combined commit case by doing plane programming both before and after stream programming, to handle pipe split disable and plane enable respectively. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 41 ++++++++++++++++-------- 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 96267b9b99d5..e8ec2b0bd90b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -880,6 +880,33 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c if (!dcb->funcs->is_accelerated_mode(dcb)) dc->hwss.enable_accelerated_mode(dc); + /* Combine planes if required, in case of pipe split disable */ + for (i = 0; i < dc->current_state->stream_count; i++) { + dc->hwss.apply_ctx_for_surface( + dc, dc->current_state->streams[i], + dc->current_state->stream_status[i].plane_count, + dc->current_state); + } + + /* Program hardware */ + dc->hwss.ready_shared_resources(dc, context); + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + pipe = &context->res_ctx.pipe_ctx[i]; + dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe); + } + + result = dc->hwss.apply_ctx_to_hw(dc, context); + + if (result != DC_OK) + goto fail; + + if (context->stream_count > 1) { + enable_timing_multisync(dc, context); + program_timing_sync(dc, context); + } + + /* Program all planes within new context*/ for (i = 0; i < context->stream_count; i++) { const struct dc_sink *sink = context->streams[i]->sink; @@ -911,19 +938,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c context->streams[i]->timing.pix_clk_khz); } - dc->hwss.ready_shared_resources(dc, context); - - for (i = 0; i < dc->res_pool->pipe_count; i++) { - pipe = &context->res_ctx.pipe_ctx[i]; - dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe); - } - result = dc->hwss.apply_ctx_to_hw(dc, context); - - if (context->stream_count > 1) { - enable_timing_multisync(dc, context); - program_timing_sync(dc, context); - } - +fail: dc_enable_stereo(dc, context, dc_streams, context->stream_count); dc_release_state(dc->current_state); -- GitLab From e7f93e906748499951a76e9035ac8f6e85c0a110 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Tue, 7 Nov 2017 15:54:58 -0500 Subject: [PATCH 0828/2547] drm/amd/display: Early return on stream programming failure The fail goto is incorrect. It will incorrectly release the dc_states on stream programming failure. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e8ec2b0bd90b..3808b562a59f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -899,7 +899,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c result = dc->hwss.apply_ctx_to_hw(dc, context); if (result != DC_OK) - goto fail; + return result; if (context->stream_count > 1) { enable_timing_multisync(dc, context); @@ -938,7 +938,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c context->streams[i]->timing.pix_clk_khz); } -fail: dc_enable_stereo(dc, context, dc_streams, context->stream_count); dc_release_state(dc->current_state); -- GitLab From 9f89df7d9bdff3b12ba50183420e1177b259f0e6 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Tue, 7 Nov 2017 14:54:56 -0500 Subject: [PATCH 0829/2547] drm/amd/display: Remove legacy unused workaround We shouldn't be able to get a non-visible plane into DC anymore. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 3808b562a59f..3497d827b877 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1159,9 +1159,7 @@ static unsigned int pixel_format_to_bpp(enum surface_pixel_format format) } } -static enum surface_update_type get_plane_info_update_type( - const struct dc_surface_update *u, - int surface_index) +static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u) { struct dc_plane_info temp_plane_info; memset(&temp_plane_info, 0, sizeof(temp_plane_info)); @@ -1185,11 +1183,6 @@ static enum surface_update_type get_plane_info_update_type( temp_plane_info.rotation = u->surface->rotation; temp_plane_info.stereo_format = u->surface->stereo_format; - if (surface_index == 0) - temp_plane_info.visible = u->plane_info->visible; - else - temp_plane_info.visible = u->surface->visible; - if (memcmp(u->plane_info, &temp_plane_info, sizeof(struct dc_plane_info)) != 0) return UPDATE_TYPE_FULL; @@ -1252,10 +1245,8 @@ static enum surface_update_type get_scaling_info_update_type( return UPDATE_TYPE_FAST; } -static enum surface_update_type det_surface_update( - const struct dc *dc, - const struct dc_surface_update *u, - int surface_index) +static enum surface_update_type det_surface_update(const struct dc *dc, + const struct dc_surface_update *u) { const struct dc_state *context = dc->current_state; enum surface_update_type type = UPDATE_TYPE_FAST; @@ -1264,7 +1255,7 @@ static enum surface_update_type det_surface_update( if (!is_surface_in_context(context, u->surface)) return UPDATE_TYPE_FULL; - type = get_plane_info_update_type(u, surface_index); + type = get_plane_info_update_type(u); if (overall_type < type) overall_type = type; @@ -1299,7 +1290,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( for (i = 0 ; i < surface_count; i++) { enum surface_update_type type = - det_surface_update(dc, &updates[i], i); + det_surface_update(dc, &updates[i]); if (type == UPDATE_TYPE_FULL) return type; -- GitLab From 19ec320e82c63a44d8d61752e139351be18928ba Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Mon, 6 Nov 2017 17:00:07 -0500 Subject: [PATCH 0830/2547] drm/amd/display: Add update flags in to determine surface update type This way, we can know exactly what triggered the update type we're looking at, and we can simplify the logic for determining what exactly needs to be updated in the future. Also allow a dst rect size increase to go through a medium update, since that does not require us to increase clock or bandwidth. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 123 +++++++++++++++-------- drivers/gpu/drm/amd/display/dc/dc.h | 93 +++++++++++------ 2 files changed, 140 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 3497d827b877..34e678f30328 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -54,6 +54,13 @@ /******************************************************************************* * Private functions ******************************************************************************/ + +static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new) +{ + if (new > *original) + *original = new; +} + static void destroy_links(struct dc *dc) { uint32_t i; @@ -1161,77 +1168,88 @@ static unsigned int pixel_format_to_bpp(enum surface_pixel_format format) static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u) { - struct dc_plane_info temp_plane_info; - memset(&temp_plane_info, 0, sizeof(temp_plane_info)); + union surface_update_flags *update_flags = &u->surface->update_flags; if (!u->plane_info) return UPDATE_TYPE_FAST; - temp_plane_info = *u->plane_info; + if (u->plane_info->color_space != u->surface->color_space) + update_flags->bits.color_space_change = 1; - /* Copy all parameters that will cause a full update - * from current surface, the rest of the parameters - * from provided plane configuration. - * Perform memory compare and special validation - * for those that can cause fast/medium updates - */ + if (u->plane_info->input_tf != u->surface->input_tf) + update_flags->bits.input_tf_change = 1; - /* Full update parameters */ - temp_plane_info.color_space = u->surface->color_space; - temp_plane_info.input_tf = u->surface->input_tf; - temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror; - temp_plane_info.rotation = u->surface->rotation; - temp_plane_info.stereo_format = u->surface->stereo_format; + if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) + update_flags->bits.horizontal_mirror_change = 1; - if (memcmp(u->plane_info, &temp_plane_info, - sizeof(struct dc_plane_info)) != 0) - return UPDATE_TYPE_FULL; + if (u->plane_info->rotation != u->surface->rotation) + update_flags->bits.rotation_change = 1; + + if (u->plane_info->stereo_format != u->surface->stereo_format) + update_flags->bits.stereo_format_change = 1; + + if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) + update_flags->bits.per_pixel_alpha_change = 1; if (pixel_format_to_bpp(u->plane_info->format) != - pixel_format_to_bpp(u->surface->format)) { + pixel_format_to_bpp(u->surface->format)) /* different bytes per element will require full bandwidth * and DML calculation */ - return UPDATE_TYPE_FULL; - } + update_flags->bits.bpp_change = 1; if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info, sizeof(union dc_tiling_info)) != 0) { + update_flags->bits.swizzle_change = 1; /* todo: below are HW dependent, we should add a hook to * DCE/N resource and validated there. */ - if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { + if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) /* swizzled mode requires RQ to be setup properly, * thus need to run DML to calculate RQ settings */ - return UPDATE_TYPE_FULL; - } + update_flags->bits.bandwidth_change = 1; } + if (update_flags->bits.rotation_change + || update_flags->bits.stereo_format_change + || update_flags->bits.bpp_change + || update_flags->bits.bandwidth_change) + return UPDATE_TYPE_FULL; + return UPDATE_TYPE_MED; } -static enum surface_update_type get_scaling_info_update_type( +static enum surface_update_type get_scaling_info_update_type( const struct dc_surface_update *u) { + union surface_update_flags *update_flags = &u->surface->update_flags; + if (!u->scaling_info) return UPDATE_TYPE_FAST; if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width || u->scaling_info->clip_rect.height != u->surface->clip_rect.height || u->scaling_info->dst_rect.width != u->surface->dst_rect.width - || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) - return UPDATE_TYPE_FULL; + || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) { + update_flags->bits.scaling_change = 1; + + if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width + || u->scaling_info->dst_rect.height < u->surface->dst_rect.height) + && (u->scaling_info->dst_rect.width < u->surface->src_rect.width + || u->scaling_info->dst_rect.height < u->surface->src_rect.height)) + /* Making dst rect smaller requires a bandwidth change */ + update_flags->bits.bandwidth_change = 1; + } if (u->scaling_info->src_rect.width != u->surface->src_rect.width || u->scaling_info->src_rect.height != u->surface->src_rect.height) { + update_flags->bits.scaling_change = 1; if (u->scaling_info->src_rect.width > u->surface->src_rect.width && u->scaling_info->src_rect.height > u->surface->src_rect.height) - return UPDATE_TYPE_FULL; - - /* Upscaling does not require a full update */ - return UPDATE_TYPE_MED; + /* Making src rect bigger requires a bandwidth change */ + update_flags->bits.clock_change = 1; } if (u->scaling_info->src_rect.x != u->surface->src_rect.x @@ -1240,33 +1258,50 @@ static enum surface_update_type get_scaling_info_update_type( || u->scaling_info->clip_rect.y != u->surface->clip_rect.y || u->scaling_info->dst_rect.x != u->surface->dst_rect.x || u->scaling_info->dst_rect.y != u->surface->dst_rect.y) + update_flags->bits.position_change = 1; + + if (update_flags->bits.clock_change + || update_flags->bits.bandwidth_change) + return UPDATE_TYPE_FULL; + + if (update_flags->bits.scaling_change + || update_flags->bits.position_change) return UPDATE_TYPE_MED; return UPDATE_TYPE_FAST; } static enum surface_update_type det_surface_update(const struct dc *dc, - const struct dc_surface_update *u) + const struct dc_surface_update *u) { const struct dc_state *context = dc->current_state; - enum surface_update_type type = UPDATE_TYPE_FAST; + enum surface_update_type type; enum surface_update_type overall_type = UPDATE_TYPE_FAST; + union surface_update_flags *update_flags = &u->surface->update_flags; + + update_flags->raw = 0; // Reset all flags - if (!is_surface_in_context(context, u->surface)) + if (!is_surface_in_context(context, u->surface)) { + update_flags->bits.new_plane = 1; return UPDATE_TYPE_FULL; + } type = get_plane_info_update_type(u); - if (overall_type < type) - overall_type = type; + elevate_update_type(&overall_type, type); type = get_scaling_info_update_type(u); - if (overall_type < type) - overall_type = type; + elevate_update_type(&overall_type, type); + + if (u->in_transfer_func) + update_flags->bits.in_transfer_func = 1; + + if (u->input_csc_color_matrix) + update_flags->bits.input_csc_change = 1; - if (u->in_transfer_func || - u->input_csc_color_matrix) { - if (overall_type < UPDATE_TYPE_MED) - overall_type = UPDATE_TYPE_MED; + if (update_flags->bits.in_transfer_func + || update_flags->bits.input_csc_change) { + type = UPDATE_TYPE_MED; + elevate_update_type(&overall_type, type); } return overall_type; @@ -1292,11 +1327,11 @@ enum surface_update_type dc_check_update_surfaces_for_stream( enum surface_update_type type = det_surface_update(dc, &updates[i]); + updates[i].surface->update_type = type; if (type == UPDATE_TYPE_FULL) return type; - if (overall_type < type) - overall_type = type; + elevate_update_type(&overall_type, type); } return overall_type; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 459a1c55b5cf..f6d431a942a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -99,6 +99,39 @@ struct dc_static_screen_events { bool overlay_update; }; + +/* Surface update type is used by dc_update_surfaces_and_stream + * The update type is determined at the very beginning of the function based + * on parameters passed in and decides how much programming (or updating) is + * going to be done during the call. + * + * UPDATE_TYPE_FAST is used for really fast updates that do not require much + * logical calculations or hardware register programming. This update MUST be + * ISR safe on windows. Currently fast update will only be used to flip surface + * address. + * + * UPDATE_TYPE_MED is used for slower updates which require significant hw + * re-programming however do not affect bandwidth consumption or clock + * requirements. At present, this is the level at which front end updates + * that do not require us to run bw_calcs happen. These are in/out transfer func + * updates, viewport offset changes, recout size changes and pixel depth changes. + * This update can be done at ISR, but we want to minimize how often this happens. + * + * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our + * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front + * end related. Any time viewport dimensions, recout dimensions, scaling ratios or + * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do + * a full update. This cannot be done at ISR level and should be a rare event. + * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting + * underscan we don't expect to see this call at all. + */ + +enum surface_update_type { + UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ + UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ + UPDATE_TYPE_FULL, /* may need to shuffle resources */ +}; + /* Forward declaration*/ struct dc; struct dc_plane_state; @@ -399,6 +432,32 @@ struct dc_plane_status { bool is_right_eye; }; +union surface_update_flags { + + struct { + /* Medium updates */ + uint32_t color_space_change:1; + uint32_t input_tf_change:1; + uint32_t horizontal_mirror_change:1; + uint32_t per_pixel_alpha_change:1; + uint32_t rotation_change:1; + uint32_t swizzle_change:1; + uint32_t scaling_change:1; + uint32_t position_change:1; + uint32_t in_transfer_func:1; + uint32_t input_csc_change:1; + + /* Full updates */ + uint32_t new_plane:1; + uint32_t bpp_change:1; + uint32_t bandwidth_change:1; + uint32_t clock_change:1; + uint32_t stereo_format_change:1; + } bits; + + uint32_t raw; +}; + struct dc_plane_state { struct dc_plane_address address; struct scaling_taps scaling_quality; @@ -432,6 +491,8 @@ struct dc_plane_state { bool flip_immediate; bool horizontal_mirror; + union surface_update_flags update_flags; + enum surface_update_type update_type; /* private to DC core */ struct dc_plane_status status; struct dc_context *ctx; @@ -516,38 +577,6 @@ struct dc_flip_addrs { bool dc_post_update_surfaces_to_stream( struct dc *dc); -/* Surface update type is used by dc_update_surfaces_and_stream - * The update type is determined at the very beginning of the function based - * on parameters passed in and decides how much programming (or updating) is - * going to be done during the call. - * - * UPDATE_TYPE_FAST is used for really fast updates that do not require much - * logical calculations or hardware register programming. This update MUST be - * ISR safe on windows. Currently fast update will only be used to flip surface - * address. - * - * UPDATE_TYPE_MED is used for slower updates which require significant hw - * re-programming however do not affect bandwidth consumption or clock - * requirements. At present, this is the level at which front end updates - * that do not require us to run bw_calcs happen. These are in/out transfer func - * updates, viewport offset changes, recout size changes and pixel depth changes. - * This update can be done at ISR, but we want to minimize how often this happens. - * - * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our - * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front - * end related. Any time viewport dimensions, recout dimensions, scaling ratios or - * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do - * a full update. This cannot be done at ISR level and should be a rare event. - * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting - * underscan we don't expect to see this call at all. - */ - -enum surface_update_type { - UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ - UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ - UPDATE_TYPE_FULL, /* may need to shuffle resources */ -}; - /******************************************************************************* * Stream Interfaces ******************************************************************************/ -- GitLab From 949785b5d113af61d40999b2841d1a99de6f9075 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Tue, 7 Nov 2017 23:37:49 -0500 Subject: [PATCH 0831/2547] drm/amd/display: fix plane update prior to stream enablement plane update prior to stream enablement is there to recombine pipe in case we need free pipe for new display. need to pass in new state or we will just re-applyingwhat we already have Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 34e678f30328..03d8cea7400a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -887,12 +887,14 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c if (!dcb->funcs->is_accelerated_mode(dcb)) dc->hwss.enable_accelerated_mode(dc); - /* Combine planes if required, in case of pipe split disable */ + /* re-program planes for existing stream, in case we need to + * free up plane resource for later use + */ for (i = 0; i < dc->current_state->stream_count; i++) { dc->hwss.apply_ctx_for_surface( dc, dc->current_state->streams[i], dc->current_state->stream_status[i].plane_count, - dc->current_state); + context); /* use new pipe config in new context */ } /* Program hardware */ -- GitLab From e994340bfa57d96bfbd9e66bf802ea82b4ba56fc Mon Sep 17 00:00:00 2001 From: Arun Pandey Date: Wed, 8 Nov 2017 17:02:55 +0800 Subject: [PATCH 0832/2547] drm/amd/display: Added Opp and Diags Interface for P to I Signed-off-by: Arun Pandey Reviewed-by: Charlene Liu Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 1 + .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 29 +++----------- .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 38 ++++++++++--------- drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 15 ++++++++ 6 files changed, 44 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index ffce33fb5540..0bc1cb889992 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -431,13 +431,13 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; + struct mpc *mpc = dc->res_pool->mpc; enum dc_color_space color_space; struct tg_color black_color = {0}; bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ? false:true; bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY; - /* by upper caller loop, pipe0 is parent pipe and be called first. * back end is set up by for pipe0. Other children pipe share back end * with pipe 0. No program is needed. diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index 5028619d4fb4..b016f4cbd45c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -335,7 +335,7 @@ void mpc10_update_blend_mode( MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha); } -static int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id) +int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id) { struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); int opp_id = 0xF; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h index 683ce4aaa76e..e85e1f342266 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h @@ -134,5 +134,6 @@ void mpc10_assert_idle_mpcc( void mpc10_update_blend_mode( struct mpc *mpc, struct mpcc_cfg *cfg); +int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id); #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index 71385a004f52..341210060cf7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -38,25 +38,6 @@ oppn10->base.ctx -enum dpg_mode { - /* RGB colour block mode */ - DPG_MODE_RGB_COLOUR_BLOCK, - /* YCbCr-601 colour block mode */ - DPG_MODE_YCBCR_601_COLOUR_BLOCK, - /* YCbCr-709 colour block mode */ - DPG_MODE_YCBCR_709_COLOUR_BLOCK, - /* Vertical bar mode */ - DPG_MODE_VERTICAL_BAR, - /* Horizontal bar mode */ - DPG_MODE_HORIZONTAL_BAR, - /* Single ramp mode */ - DPG_MODE_RGB_SINGLE_RAMP, - /* Dual ramp mode */ - DPG_MODE_RGB_DUAL_RAMP, - /* RGB XR BIAS mode */ - DPG_MODE_RGB_XR_BIAS -}; - /************* FORMATTER ************/ /** @@ -154,7 +135,7 @@ static void opp1_set_spatial_dither( FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM); } -static void opp1_program_bit_depth_reduction( +void opp1_program_bit_depth_reduction( struct output_pixel_processor *opp, const struct bit_depth_reduction_params *params) { @@ -242,7 +223,7 @@ static void opp1_set_clamping( } -static void opp1_set_dyn_expansion( +void opp1_set_dyn_expansion( struct output_pixel_processor *opp, enum dc_color_space color_sp, enum dc_color_depth color_dpth, @@ -292,7 +273,7 @@ static void opp1_program_clamping_and_pixel_encoding( opp1_set_pixel_encoding(oppn10, params); } -static void opp1_program_fmt( +void opp1_program_fmt( struct output_pixel_processor *opp, struct bit_depth_reduction_params *fmt_bit_depth, struct clamping_and_pixel_encoding_params *clamping) @@ -315,7 +296,7 @@ static void opp1_program_fmt( return; } -static void opp1_set_stereo_polarity( +void opp1_set_stereo_polarity( struct output_pixel_processor *opp, bool enable, bool rightEyePolarity) { @@ -328,7 +309,7 @@ static void opp1_set_stereo_polarity( /* Constructor, Destructor */ /*****************************************/ -static void opp1_destroy(struct output_pixel_processor **opp) +void opp1_destroy(struct output_pixel_processor **opp) { kfree(TO_DCN10_OPP(*opp)); *opp = NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index cdb220ed858e..4b1e51050d33 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -74,18 +74,6 @@ OPP_MASK_SH_LIST_DCN(mask_sh) #define OPP_DCN10_REG_FIELD_LIST(type) \ - type DPG_EN; \ - type DPG_MODE; \ - type DPG_VRES; \ - type DPG_HRES; \ - type DPG_ACTIVE_WIDTH; \ - type DPG_ACTIVE_HEIGHT; \ - type DPG_COLOUR0_R_CR; \ - type DPG_COLOUR1_R_CR; \ - type DPG_COLOUR0_B_CB; \ - type DPG_COLOUR1_B_CB; \ - type DPG_COLOUR0_G_Y; \ - type DPG_COLOUR1_G_Y; \ type FMT_TRUNCATE_EN; \ type FMT_TRUNCATE_DEPTH; \ type FMT_TRUNCATE_MODE; \ @@ -118,11 +106,6 @@ struct dcn10_opp_mask { }; struct dcn10_opp_registers { - uint32_t DPG_CONTROL; - uint32_t DPG_DIMENSIONS; - uint32_t DPG_COLOUR_B_CB; - uint32_t DPG_COLOUR_G_Y; - uint32_t DPG_COLOUR_R_CR; uint32_t FMT_BIT_DEPTH_CONTROL; uint32_t FMT_CONTROL; uint32_t FMT_DITHER_RAND_R_SEED; @@ -150,4 +133,25 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10, const struct dcn10_opp_shift *opp_shift, const struct dcn10_opp_mask *opp_mask); +void opp1_set_dyn_expansion( + struct output_pixel_processor *opp, + enum dc_color_space color_sp, + enum dc_color_depth color_dpth, + enum signal_type signal); + +void opp1_program_fmt( + struct output_pixel_processor *opp, + struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping); + +void opp1_program_bit_depth_reduction( + struct output_pixel_processor *opp, + const struct bit_depth_reduction_params *params); + +void opp1_set_stereo_polarity( + struct output_pixel_processor *opp, + bool enable, bool rightEyePolarity); + +void opp1_destroy(struct output_pixel_processor **opp); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index cd6b0d4cd457..579d1059a3d4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -281,6 +281,21 @@ struct opp_funcs { bool enable, bool rightEyePolarity); + void (*opp_set_test_pattern)( + struct output_pixel_processor *opp, + bool enable); + + void (*opp_dpg_blank_enable)( + struct output_pixel_processor *opp, + bool enable, + const struct tg_color *color, + int width, + int height); + + void (*opp_convert_pti)( + struct output_pixel_processor *opp, + bool enable, + bool polarity); }; #endif -- GitLab From 746673c79dca3dc4c9720e49cd57b467da7a5ac8 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Wed, 8 Nov 2017 09:21:28 -0500 Subject: [PATCH 0833/2547] drm/amd/display: Rename pitch_alignment to linear_pitch_alignment Also initialize this to 64 for all ASICs. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 1 + drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 - 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 03d8cea7400a..369a5e7af47e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -702,6 +702,7 @@ struct dc *dc_create(const struct dc_init_data *init_params) dc->caps.max_links = dc->link_count; dc->caps.max_audios = dc->res_pool->audio_count; + dc->caps.linear_pitch_alignment = 64; dc->config = init_params->flags; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f6d431a942a1..fb45e1170f42 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -58,7 +58,7 @@ struct dc_caps { uint32_t i2c_speed_in_khz; unsigned int max_cursor_size; unsigned int max_video_width; - int pitch_alignment; + int linear_pitch_alignment; bool dcc_const_color; bool dynamic_audio; bool is_apu; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 209499e5f53b..9ea100223020 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1270,7 +1270,6 @@ static bool construct( dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 100; dc->caps.max_cursor_size = 256; - dc->caps.pitch_alignment = 64; /* Alignment is 64 on DCN1 */ dc->caps.max_slave_planes = 1; dc->caps.is_apu = true; -- GitLab From 27b8931327aa5d0c2cedef16b0d32ac7b25a3cf5 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Wed, 8 Nov 2017 12:15:17 -0500 Subject: [PATCH 0834/2547] drm/amd/display: Add check update surfaces for stream wrapper This allows us to properly clear and set the update flags for all cases. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 24 ++++++++++++++++++++++-- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 369a5e7af47e..63872ce500b8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1310,7 +1310,7 @@ static enum surface_update_type det_surface_update(const struct dc *dc, return overall_type; } -enum surface_update_type dc_check_update_surfaces_for_stream( +static enum surface_update_type check_update_surfaces_for_stream( struct dc *dc, struct dc_surface_update *updates, int surface_count, @@ -1330,7 +1330,6 @@ enum surface_update_type dc_check_update_surfaces_for_stream( enum surface_update_type type = det_surface_update(dc, &updates[i]); - updates[i].surface->update_type = type; if (type == UPDATE_TYPE_FULL) return type; @@ -1340,6 +1339,27 @@ enum surface_update_type dc_check_update_surfaces_for_stream( return overall_type; } +enum surface_update_type dc_check_update_surfaces_for_stream( + struct dc *dc, + struct dc_surface_update *updates, + int surface_count, + struct dc_stream_update *stream_update, + const struct dc_stream_status *stream_status) +{ + int i; + enum surface_update_type type; + + for (i = 0; i < surface_count; i++) + updates[i].surface->update_flags.raw = 0; + + type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status); + if (type == UPDATE_TYPE_FULL) + for (i = 0; i < surface_count; i++) + updates[i].surface->update_flags.bits.full_update = 1; + + return type; +} + static struct dc_stream_status *stream_get_status( struct dc_state *ctx, struct dc_stream_state *stream) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index fb45e1170f42..5fe86fab6995 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -453,6 +453,7 @@ union surface_update_flags { uint32_t bandwidth_change:1; uint32_t clock_change:1; uint32_t stereo_format_change:1; + uint32_t full_update:1; } bits; uint32_t raw; @@ -492,7 +493,6 @@ struct dc_plane_state { bool horizontal_mirror; union surface_update_flags update_flags; - enum surface_update_type update_type; /* private to DC core */ struct dc_plane_status status; struct dc_context *ctx; -- GitLab From 105f6ab86cc26eaa3ee9b4845d90c8b6a0571534 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Wed, 8 Nov 2017 12:00:51 -0500 Subject: [PATCH 0835/2547] drm/amd/display: Fix unused variable warning 'struct mpc *mpc' is not used. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 0bc1cb889992..d0f46e13efca 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -431,7 +431,6 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; - struct mpc *mpc = dc->res_pool->mpc; enum dc_color_space color_space; struct tg_color black_color = {0}; bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ? -- GitLab From a4e6d14ebe80ee53e295540c51dfb1352d7069a8 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Wed, 8 Nov 2017 14:50:06 -0500 Subject: [PATCH 0836/2547] drm/amd/display: Optimize front end programming. for video scaling changes, Reduce reg access count from 1044 to 447, duration time from 4.6ms to 3ms. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 219 +++++++++--------- 1 file changed, 111 insertions(+), 108 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index d0f46e13efca..30f458701f9c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1453,6 +1453,89 @@ static void dcn10_enable_per_frame_crtc_position_reset( } */ +static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1, + struct vm_system_aperture_param *apt, + struct dce_hwseq *hws) +{ + PHYSICAL_ADDRESS_LOC physical_page_number; + uint32_t logical_addr_low; + uint32_t logical_addr_high; + + REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, + PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part); + REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, + PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part); + + REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR, + LOGICAL_ADDR, &logical_addr_low); + + REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, + LOGICAL_ADDR, &logical_addr_high); + + apt->sys_default.quad_part = physical_page_number.quad_part << 12; + apt->sys_low.quad_part = (int64_t)logical_addr_low << 18; + apt->sys_high.quad_part = (int64_t)logical_addr_high << 18; +} + +/* Temporary read settings, future will get values from kmd directly */ +static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1, + struct vm_context0_param *vm0, + struct dce_hwseq *hws) +{ + PHYSICAL_ADDRESS_LOC fb_base; + PHYSICAL_ADDRESS_LOC fb_offset; + uint32_t fb_base_value; + uint32_t fb_offset_value; + + REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value); + REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value); + + REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, + PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part); + REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, + PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part); + + REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part); + REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part); + + REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part); + REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part); + + REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, + PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part); + REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, + PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part); + + /* + * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space. + * Therefore we need to do + * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE + */ + fb_base.quad_part = (uint64_t)fb_base_value << 24; + fb_offset.quad_part = (uint64_t)fb_offset_value << 24; + vm0->pte_base.quad_part += fb_base.quad_part; + vm0->pte_base.quad_part -= fb_offset.quad_part; +} + + +static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp) +{ + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); + struct vm_system_aperture_param apt = { {{ 0 } } }; + struct vm_context0_param vm0 = { { { 0 } } }; + + mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws); + mmhub_read_vm_context0_settings(hubp1, &vm0, hws); + + hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt); + hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0); +} + static void dcn10_enable_plane( struct dc *dc, struct pipe_ctx *pipe_ctx, @@ -1515,6 +1598,8 @@ static void dcn10_enable_plane( print_rq_dlg_ttu(dc, pipe_ctx); } */ + if (dc->config.gpu_vm_support) + dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp); if (dc->debug.sanity_checks) { dcn10_verify_allow_pstate_change_high(dc); @@ -1737,93 +1822,6 @@ void build_prescale_params(struct dc_bias_and_scale *bias_and_scale, } } -static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1, - struct vm_system_aperture_param *apt, - struct dce_hwseq *hws) -{ - PHYSICAL_ADDRESS_LOC physical_page_number; - uint32_t logical_addr_low; - uint32_t logical_addr_high; - - REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, - PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part); - REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, - PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part); - - REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR, - LOGICAL_ADDR, &logical_addr_low); - - REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, - LOGICAL_ADDR, &logical_addr_high); - - apt->sys_default.quad_part = physical_page_number.quad_part << 12; - apt->sys_low.quad_part = (int64_t)logical_addr_low << 18; - apt->sys_high.quad_part = (int64_t)logical_addr_high << 18; -} - -/* Temporary read settings, future will get values from kmd directly */ -static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1, - struct vm_context0_param *vm0, - struct dce_hwseq *hws) -{ - PHYSICAL_ADDRESS_LOC fb_base; - PHYSICAL_ADDRESS_LOC fb_offset; - uint32_t fb_base_value; - uint32_t fb_offset_value; - - REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value); - REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value); - - REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, - PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part); - REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, - PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part); - - REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, - LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part); - REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, - LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part); - - REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, - LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part); - REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, - LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part); - - REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, - PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part); - REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, - PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part); - - /* - * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space. - * Therefore we need to do - * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR - * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE - */ - fb_base.quad_part = (uint64_t)fb_base_value << 24; - fb_offset.quad_part = (uint64_t)fb_offset_value << 24; - vm0->pte_base.quad_part += fb_base.quad_part; - vm0->pte_base.quad_part -= fb_offset.quad_part; -} - -static void dcn10_program_pte_vm(struct hubp *hubp, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - enum dc_rotation_angle rotation, - struct dce_hwseq *hws) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - struct vm_system_aperture_param apt = { {{ 0 } } }; - struct vm_context0_param vm0 = { { { 0 } } }; - - - mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws); - mmhub_read_vm_context0_settings(hubp1, &vm0, hws); - - hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt); - hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0); -} - static void update_dchubp_dpp( struct dc *dc, struct pipe_ctx *pipe_ctx, @@ -1865,15 +1863,6 @@ static void update_dchubp_dpp( size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; - if (dc->config.gpu_vm_support) - dcn10_program_pte_vm( - pipe_ctx->plane_res.hubp, - plane_state->format, - &plane_state->tiling_info, - plane_state->rotation, - hws - ); - // program the input csc dpp->funcs->dpp_setup(dpp, plane_state->format, @@ -1970,18 +1959,11 @@ static void program_all_pipe_in_tree( struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - dcn10_enable_plane(dc, pipe_ctx, context); + if (pipe_ctx->plane_state->update_flags.bits.full_update) + dcn10_enable_plane(dc, pipe_ctx, context); - update_dchubp_dpp(dc, pipe_ctx, context); - - /* TODO: this is a hack w/a for switching from mpo to pipe split */ - if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { - struct dc_cursor_position position = { 0 }; - - dc_stream_set_cursor_position(pipe_ctx->stream, &position); - dc_stream_set_cursor_attributes(pipe_ctx->stream, - &pipe_ctx->stream->cursor_attributes); - } + if (pipe_ctx->plane_state->update_flags.raw != 0) + update_dchubp_dpp(dc, pipe_ctx, context); if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); @@ -2141,9 +2123,30 @@ static void dcn10_apply_ctx_for_surface( } } - if (num_planes > 0) + if (num_planes > 0) { + struct dc_stream_state *stream_for_cursor; + program_all_pipe_in_tree(dc, top_pipe_to_program, context); + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (stream == pipe_ctx->stream) { + stream_for_cursor = pipe_ctx->stream; + break; + } + } + + /* TODO: this is a hack w/a for switching from mpo to pipe split */ + if (stream_for_cursor->cursor_attributes.address.quad_part != 0) { + struct dc_cursor_position position = { 0 }; + + dc_stream_set_cursor_position(stream_for_cursor, &position); + dc_stream_set_cursor_attributes(stream_for_cursor, + &stream_for_cursor->cursor_attributes); + } + } + tg->funcs->unlock(tg); for (i = 0; i < dc->res_pool->pipe_count; i++) { -- GitLab From 7c0c967209591433f31e4992fc58f5e30a16febb Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 8 Nov 2017 14:34:14 -0500 Subject: [PATCH 0837/2547] drm/amd/display: Move dc_stream interface to separate header Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 223 +---------------- drivers/gpu/drm/amd/display/dc/dc_stream.h | 271 +++++++++++++++++++++ 2 files changed, 273 insertions(+), 221 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dc_stream.h diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5fe86fab6995..170cdcb5a027 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -137,6 +137,7 @@ struct dc; struct dc_plane_state; struct dc_state; + struct dc_cap_funcs { bool (*get_dcc_compression_cap)(const struct dc *dc, const struct dc_dcc_surface_param *input, @@ -577,168 +578,7 @@ struct dc_flip_addrs { bool dc_post_update_surfaces_to_stream( struct dc *dc); -/******************************************************************************* - * Stream Interfaces - ******************************************************************************/ - -struct dc_stream_status { - int primary_otg_inst; - int stream_enc_inst; - int plane_count; - struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; - - /* - * link this stream passes through - */ - struct dc_link *link; -}; - -struct dc_stream_state { - struct dc_sink *sink; - struct dc_crtc_timing timing; - - struct rect src; /* composition area */ - struct rect dst; /* stream addressable area */ - - struct audio_info audio_info; - - struct freesync_context freesync_ctx; - - struct dc_hdr_static_metadata hdr_static_metadata; - struct dc_transfer_func *out_transfer_func; - struct colorspace_transform gamut_remap_matrix; - struct csc_transform csc_color_matrix; - - enum dc_color_space output_color_space; - enum dc_dither_option dither_option; - - enum view_3d_format view_format; - - bool ignore_msa_timing_param; - /* TODO: custom INFO packets */ - /* TODO: ABM info (DMCU) */ - /* TODO: PSR info */ - /* TODO: CEA VIC */ - - /* from core_stream struct */ - struct dc_context *ctx; - - /* used by DCP and FMT */ - struct bit_depth_reduction_params bit_depth_params; - struct clamping_and_pixel_encoding_params clamping; - - int phy_pix_clk; - enum signal_type signal; - bool dpms_off; - - struct dc_stream_status status; - - struct dc_cursor_attributes cursor_attributes; - - /* from stream struct */ - struct kref refcount; - - struct crtc_trigger_info triggered_crtc_reset; - -}; - -struct dc_stream_update { - struct rect src; - struct rect dst; - struct dc_transfer_func *out_transfer_func; - struct dc_hdr_static_metadata *hdr_static_metadata; -}; - -bool dc_is_stream_unchanged( - struct dc_stream_state *old_stream, struct dc_stream_state *stream); -bool dc_is_stream_scaling_unchanged( - struct dc_stream_state *old_stream, struct dc_stream_state *stream); - -/* - * Set up surface attributes and associate to a stream - * The surfaces parameter is an absolute set of all surface active for the stream. - * If no surfaces are provided, the stream will be blanked; no memory read. - * Any flip related attribute changes must be done through this interface. - * - * After this call: - * Surfaces attributes are programmed and configured to be composed into stream. - * This does not trigger a flip. No surface address is programmed. - */ - -bool dc_commit_planes_to_stream( - struct dc *dc, - struct dc_plane_state **plane_states, - uint8_t new_plane_count, - struct dc_stream_state *dc_stream, - struct dc_state *state); - -void dc_commit_updates_for_stream(struct dc *dc, - struct dc_surface_update *srf_updates, - int surface_count, - struct dc_stream_state *stream, - struct dc_stream_update *stream_update, - struct dc_plane_state **plane_states, - struct dc_state *state); -/* - * Log the current stream state. - */ -void dc_stream_log( - const struct dc_stream_state *stream, - struct dal_logger *dc_logger, - enum dc_log_type log_type); - -uint8_t dc_get_current_stream_count(struct dc *dc); -struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); - -/* - * Return the current frame counter. - */ -uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); - -/* TODO: Return parsed values rather than direct register read - * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) - * being refactored properly to be dce-specific - */ -bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, - uint32_t *v_blank_start, - uint32_t *v_blank_end, - uint32_t *h_position, - uint32_t *v_position); - -enum dc_status dc_add_stream_to_ctx( - struct dc *dc, - struct dc_state *new_ctx, - struct dc_stream_state *stream); - -enum dc_status dc_remove_stream_from_ctx( - struct dc *dc, - struct dc_state *new_ctx, - struct dc_stream_state *stream); - - -bool dc_add_plane_to_context( - const struct dc *dc, - struct dc_stream_state *stream, - struct dc_plane_state *plane_state, - struct dc_state *context); - -bool dc_remove_plane_from_context( - const struct dc *dc, - struct dc_stream_state *stream, - struct dc_plane_state *plane_state, - struct dc_state *context); - -bool dc_rem_all_planes_for_stream( - const struct dc *dc, - struct dc_stream_state *stream, - struct dc_state *context); - -bool dc_add_all_planes_for_stream( - const struct dc *dc, - struct dc_stream_state *stream, - struct dc_plane_state * const *plane_states, - int plane_count, - struct dc_state *context); +#include "dc_stream.h" /* * Structure to store surface/stream associations for validation @@ -749,22 +589,12 @@ struct dc_validation_set { uint8_t plane_count; }; -enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); - enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); enum dc_status dc_validate_global_state( struct dc *dc, struct dc_state *new_ctx); -/* - * This function takes a stream and checks if it is guaranteed to be supported. - * Guaranteed means that MAX_COFUNC similar streams are supported. - * - * After this call: - * No hardware is programmed for call. Only validation is done. - */ - void dc_resource_state_construct( const struct dc *dc, @@ -791,42 +621,6 @@ void dc_resource_state_destruct(struct dc_state *context); */ bool dc_commit_state(struct dc *dc, struct dc_state *context); -/* - * Set up streams and links associated to drive sinks - * The streams parameter is an absolute set of all active streams. - * - * After this call: - * Phy, Encoder, Timing Generator are programmed and enabled. - * New streams are enabled with blank stream; no memory read. - */ -/* - * Enable stereo when commit_streams is not required, - * for example, frame alternate. - */ -bool dc_enable_stereo( - struct dc *dc, - struct dc_state *context, - struct dc_stream_state *streams[], - uint8_t stream_count); - -/** - * Create a new default stream for the requested sink - */ -struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); - -void dc_stream_retain(struct dc_stream_state *dc_stream); -void dc_stream_release(struct dc_stream_state *dc_stream); - -struct dc_stream_status *dc_stream_get_status( - struct dc_stream_state *dc_stream); - -enum surface_update_type dc_check_update_surfaces_for_stream( - struct dc *dc, - struct dc_surface_update *updates, - int surface_count, - struct dc_stream_update *stream_update, - const struct dc_stream_status *stream_status); - struct dc_state *dc_create_state(void); void dc_retain_state(struct dc_state *context); @@ -1076,18 +870,6 @@ struct dc_sink_init_data { struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); -/******************************************************************************* - * Cursor interfaces - To manages the cursor within a stream - ******************************************************************************/ -/* TODO: Deprecated once we switch to dc_set_cursor_position */ -bool dc_stream_set_cursor_attributes( - struct dc_stream_state *stream, - const struct dc_cursor_attributes *attributes); - -bool dc_stream_set_cursor_position( - struct dc_stream_state *stream, - const struct dc_cursor_position *position); - /* Newer interfaces */ struct dc_cursor { struct dc_plane_address address; @@ -1124,5 +906,4 @@ bool dc_submit_i2c( uint32_t link_index, struct i2c_command *cmd); - #endif /* DC_INTERFACE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h new file mode 100644 index 000000000000..bed2a937de71 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -0,0 +1,271 @@ +/* + * Copyright 2012-14 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef DC_STREAM_H_ +#define DC_STREAM_H_ + +#include "dc_types.h" +#include "grph_object_defs.h" + +/******************************************************************************* + * Stream Interfaces + ******************************************************************************/ + +struct dc_stream_status { + int primary_otg_inst; + int stream_enc_inst; + int plane_count; + struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; + + /* + * link this stream passes through + */ + struct dc_link *link; +}; + +struct dc_stream_state { + struct dc_sink *sink; + struct dc_crtc_timing timing; + + struct rect src; /* composition area */ + struct rect dst; /* stream addressable area */ + + struct audio_info audio_info; + + struct freesync_context freesync_ctx; + + struct dc_hdr_static_metadata hdr_static_metadata; + struct dc_transfer_func *out_transfer_func; + struct colorspace_transform gamut_remap_matrix; + struct csc_transform csc_color_matrix; + + enum dc_color_space output_color_space; + enum dc_dither_option dither_option; + + enum view_3d_format view_format; + + bool ignore_msa_timing_param; + /* TODO: custom INFO packets */ + /* TODO: ABM info (DMCU) */ + /* TODO: PSR info */ + /* TODO: CEA VIC */ + + /* from core_stream struct */ + struct dc_context *ctx; + + /* used by DCP and FMT */ + struct bit_depth_reduction_params bit_depth_params; + struct clamping_and_pixel_encoding_params clamping; + + int phy_pix_clk; + enum signal_type signal; + bool dpms_off; + + struct dc_stream_status status; + + struct dc_cursor_attributes cursor_attributes; + + /* from stream struct */ + struct kref refcount; + + struct crtc_trigger_info triggered_crtc_reset; + +}; + +struct dc_stream_update { + struct rect src; + struct rect dst; + struct dc_transfer_func *out_transfer_func; + struct dc_hdr_static_metadata *hdr_static_metadata; +}; + +bool dc_is_stream_unchanged( + struct dc_stream_state *old_stream, struct dc_stream_state *stream); +bool dc_is_stream_scaling_unchanged( + struct dc_stream_state *old_stream, struct dc_stream_state *stream); + +/* + * Set up surface attributes and associate to a stream + * The surfaces parameter is an absolute set of all surface active for the stream. + * If no surfaces are provided, the stream will be blanked; no memory read. + * Any flip related attribute changes must be done through this interface. + * + * After this call: + * Surfaces attributes are programmed and configured to be composed into stream. + * This does not trigger a flip. No surface address is programmed. + */ + +bool dc_commit_planes_to_stream( + struct dc *dc, + struct dc_plane_state **plane_states, + uint8_t new_plane_count, + struct dc_stream_state *dc_stream, + struct dc_state *state); + +void dc_commit_updates_for_stream(struct dc *dc, + struct dc_surface_update *srf_updates, + int surface_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_plane_state **plane_states, + struct dc_state *state); +/* + * Log the current stream state. + */ +void dc_stream_log( + const struct dc_stream_state *stream, + struct dal_logger *dc_logger, + enum dc_log_type log_type); + +uint8_t dc_get_current_stream_count(struct dc *dc); +struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); + +/* + * Return the current frame counter. + */ +uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); + +/* TODO: Return parsed values rather than direct register read + * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) + * being refactored properly to be dce-specific + */ +bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position); + +enum dc_status dc_add_stream_to_ctx( + struct dc *dc, + struct dc_state *new_ctx, + struct dc_stream_state *stream); + +enum dc_status dc_remove_stream_from_ctx( + struct dc *dc, + struct dc_state *new_ctx, + struct dc_stream_state *stream); + + +bool dc_add_plane_to_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, + struct dc_state *context); + +bool dc_remove_plane_from_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, + struct dc_state *context); + +bool dc_rem_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_state *context); + +bool dc_add_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state * const *plane_states, + int plane_count, + struct dc_state *context); + +enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); + +/* + * This function takes a stream and checks if it is guaranteed to be supported. + * Guaranteed means that MAX_COFUNC similar streams are supported. + * + * After this call: + * No hardware is programmed for call. Only validation is done. + */ + +/* + * Set up streams and links associated to drive sinks + * The streams parameter is an absolute set of all active streams. + * + * After this call: + * Phy, Encoder, Timing Generator are programmed and enabled. + * New streams are enabled with blank stream; no memory read. + */ +/* + * Enable stereo when commit_streams is not required, + * for example, frame alternate. + */ +bool dc_enable_stereo( + struct dc *dc, + struct dc_state *context, + struct dc_stream_state *streams[], + uint8_t stream_count); + + +enum surface_update_type dc_check_update_surfaces_for_stream( + struct dc *dc, + struct dc_surface_update *updates, + int surface_count, + struct dc_stream_update *stream_update, + const struct dc_stream_status *stream_status); + +/** + * Create a new default stream for the requested sink + */ +struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); + +void dc_stream_retain(struct dc_stream_state *dc_stream); +void dc_stream_release(struct dc_stream_state *dc_stream); + +struct dc_stream_status *dc_stream_get_status( + struct dc_stream_state *dc_stream); + +/******************************************************************************* + * Cursor interfaces - To manages the cursor within a stream + ******************************************************************************/ +/* TODO: Deprecated once we switch to dc_set_cursor_position */ +bool dc_stream_set_cursor_attributes( + struct dc_stream_state *stream, + const struct dc_cursor_attributes *attributes); + +bool dc_stream_set_cursor_position( + struct dc_stream_state *stream, + const struct dc_cursor_position *position); + +bool dc_stream_adjust_vmin_vmax(struct dc *dc, + struct dc_stream_state **stream, + int num_streams, + int vmin, + int vmax); + +bool dc_stream_get_crtc_position(struct dc *dc, + struct dc_stream_state **stream, + int num_streams, + unsigned int *v_pos, + unsigned int *nom_v_pos); + +void dc_stream_set_static_screen_events(struct dc *dc, + struct dc_stream_state **stream, + int num_streams, + const struct dc_static_screen_events *events); + +#endif /* DC_STREAM_H_ */ -- GitLab From 2e5fa5ba50b045500fceea1ef1d0fdc13a7e0e1f Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 8 Nov 2017 14:59:48 -0500 Subject: [PATCH 0838/2547] drm/amd/display: Move dc_link interface to separate header Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 175 +------------------ drivers/gpu/drm/amd/display/dc/dc_link.h | 207 +++++++++++++++++++++++ 2 files changed, 208 insertions(+), 174 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dc_link.h diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 170cdcb5a027..5c509707ccd6 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -653,171 +653,7 @@ struct dpcd_caps { bool dpcd_display_control_capable; }; -struct dc_link_status { - struct dpcd_caps *dpcd_caps; -}; - -/* DP MST stream allocation (payload bandwidth number) */ -struct link_mst_stream_allocation { - /* DIG front */ - const struct stream_encoder *stream_enc; - /* associate DRM payload table with DC stream encoder */ - uint8_t vcp_id; - /* number of slots required for the DP stream in transport packet */ - uint8_t slot_count; -}; - -/* DP MST stream allocation table */ -struct link_mst_stream_allocation_table { - /* number of DP video streams */ - int stream_count; - /* array of stream allocations */ - struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; -}; - -/* - * A link contains one or more sinks and their connected status. - * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. - */ -struct dc_link { - struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; - unsigned int sink_count; - struct dc_sink *local_sink; - unsigned int link_index; - enum dc_connection_type type; - enum signal_type connector_signal; - enum dc_irq_source irq_source_hpd; - enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ - /* caps is the same as reported_link_cap. link_traing use - * reported_link_cap. Will clean up. TODO - */ - struct dc_link_settings reported_link_cap; - struct dc_link_settings verified_link_cap; - struct dc_link_settings cur_link_settings; - struct dc_lane_settings cur_lane_setting; - struct dc_link_settings preferred_link_setting; - - uint8_t ddc_hw_inst; - - uint8_t hpd_src; - - uint8_t link_enc_hw_inst; - - bool test_pattern_enabled; - union compliance_test_state compliance_test_state; - - void *priv; - - struct ddc_service *ddc; - - bool aux_mode; - - /* Private to DC core */ - - const struct dc *dc; - - struct dc_context *ctx; - - struct link_encoder *link_enc; - struct graphics_object_id link_id; - union ddi_channel_mapping ddi_channel_mapping; - struct connector_device_tag_info device_tag; - struct dpcd_caps dpcd_caps; - unsigned short chip_caps; - unsigned int dpcd_sink_count; - enum edp_revision edp_revision; - bool psr_enabled; - - /* MST record stream using this link */ - struct link_flags { - bool dp_keep_receiver_powered; - } wa_flags; - struct link_mst_stream_allocation_table mst_stream_alloc_table; - - struct dc_link_status link_status; - -}; - -const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); - -/* - * Return an enumerated dc_link. dc_link order is constant and determined at - * boot time. They cannot be created or destroyed. - * Use dc_get_caps() to get number of links. - */ -static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) -{ - return dc->links[link_index]; -} - -/* Set backlight level of an embedded panel (eDP, LVDS). */ -bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, - uint32_t frame_ramp, const struct dc_stream_state *stream); - -bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait); - -bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); - -bool dc_link_setup_psr(struct dc_link *dc_link, - const struct dc_stream_state *stream, struct psr_config *psr_config, - struct psr_context *psr_context); - -/* Request DC to detect if there is a Panel connected. - * boot - If this call is during initial boot. - * Return false for any type of detection failure or MST detection - * true otherwise. True meaning further action is required (status update - * and OS notification). - */ -enum dc_detect_reason { - DETECT_REASON_BOOT, - DETECT_REASON_HPD, - DETECT_REASON_HPDRX, -}; - -bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason); - -/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). - * Return: - * true - Downstream port status changed. DM should call DC to do the - * detection. - * false - no change in Downstream port status. No further action required - * from DM. */ -bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, - union hpd_irq_data *hpd_irq_dpcd_data); - -struct dc_sink_init_data; - -struct dc_sink *dc_link_add_remote_sink( - struct dc_link *dc_link, - const uint8_t *edid, - int len, - struct dc_sink_init_data *init_data); - -void dc_link_remove_remote_sink( - struct dc_link *link, - struct dc_sink *sink); - -/* Used by diagnostics for virtual link at the moment */ - -void dc_link_dp_set_drive_settings( - struct dc_link *link, - struct link_training_settings *lt_settings); - -enum link_training_result dc_link_dp_perform_link_training( - struct dc_link *link, - const struct dc_link_settings *link_setting, - bool skip_video_pattern); - -void dc_link_dp_enable_hpd(const struct dc_link *link); - -void dc_link_dp_disable_hpd(const struct dc_link *link); - -bool dc_link_dp_set_test_pattern( - struct dc_link *link, - enum dp_test_pattern test_pattern, - const struct link_training_settings *p_link_settings, - const unsigned char *p_custom_pattern, - unsigned int cust_pattern_size); +#include "dc_link.h" /******************************************************************************* * Sink Interfaces - A sink corresponds to a display output device @@ -897,13 +733,4 @@ void dc_set_power_state( enum dc_acpi_cm_power_state power_state); void dc_resume(struct dc *dc); -/* - * DPCD access interfaces - */ - -bool dc_submit_i2c( - struct dc *dc, - uint32_t link_index, - struct i2c_command *cmd); - #endif /* DC_INTERFACE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h new file mode 100644 index 000000000000..f11a734da1db --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h @@ -0,0 +1,207 @@ +/* + * Copyright 2012-14 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef DC_LINK_H_ +#define DC_LINK_H_ + +#include "dc_types.h" +#include "grph_object_defs.h" + +struct dc_link_status { + struct dpcd_caps *dpcd_caps; +}; + +/* DP MST stream allocation (payload bandwidth number) */ +struct link_mst_stream_allocation { + /* DIG front */ + const struct stream_encoder *stream_enc; + /* associate DRM payload table with DC stream encoder */ + uint8_t vcp_id; + /* number of slots required for the DP stream in transport packet */ + uint8_t slot_count; +}; + +/* DP MST stream allocation table */ +struct link_mst_stream_allocation_table { + /* number of DP video streams */ + int stream_count; + /* array of stream allocations */ + struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; +}; + +/* + * A link contains one or more sinks and their connected status. + * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. + */ +struct dc_link { + struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; + unsigned int sink_count; + struct dc_sink *local_sink; + unsigned int link_index; + enum dc_connection_type type; + enum signal_type connector_signal; + enum dc_irq_source irq_source_hpd; + enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ + /* caps is the same as reported_link_cap. link_traing use + * reported_link_cap. Will clean up. TODO + */ + struct dc_link_settings reported_link_cap; + struct dc_link_settings verified_link_cap; + struct dc_link_settings cur_link_settings; + struct dc_lane_settings cur_lane_setting; + struct dc_link_settings preferred_link_setting; + + uint8_t ddc_hw_inst; + + uint8_t hpd_src; + + uint8_t link_enc_hw_inst; + + bool test_pattern_enabled; + union compliance_test_state compliance_test_state; + + void *priv; + + struct ddc_service *ddc; + + bool aux_mode; + + /* Private to DC core */ + + const struct dc *dc; + + struct dc_context *ctx; + + struct link_encoder *link_enc; + struct graphics_object_id link_id; + union ddi_channel_mapping ddi_channel_mapping; + struct connector_device_tag_info device_tag; + struct dpcd_caps dpcd_caps; + unsigned short chip_caps; + unsigned int dpcd_sink_count; + enum edp_revision edp_revision; + bool psr_enabled; + + /* MST record stream using this link */ + struct link_flags { + bool dp_keep_receiver_powered; + } wa_flags; + struct link_mst_stream_allocation_table mst_stream_alloc_table; + + struct dc_link_status link_status; + +}; + +const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); + +/* + * Return an enumerated dc_link. dc_link order is constant and determined at + * boot time. They cannot be created or destroyed. + * Use dc_get_caps() to get number of links. + */ +static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) +{ + return dc->links[link_index]; +} + +/* Set backlight level of an embedded panel (eDP, LVDS). */ +bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, + uint32_t frame_ramp, const struct dc_stream_state *stream); + +bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait); + +bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); + +bool dc_link_setup_psr(struct dc_link *dc_link, + const struct dc_stream_state *stream, struct psr_config *psr_config, + struct psr_context *psr_context); + +/* Request DC to detect if there is a Panel connected. + * boot - If this call is during initial boot. + * Return false for any type of detection failure or MST detection + * true otherwise. True meaning further action is required (status update + * and OS notification). + */ +enum dc_detect_reason { + DETECT_REASON_BOOT, + DETECT_REASON_HPD, + DETECT_REASON_HPDRX, +}; + +bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason); + +/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. */ +bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data); + +struct dc_sink_init_data; + +struct dc_sink *dc_link_add_remote_sink( + struct dc_link *dc_link, + const uint8_t *edid, + int len, + struct dc_sink_init_data *init_data); + +void dc_link_remove_remote_sink( + struct dc_link *link, + struct dc_sink *sink); + +/* Used by diagnostics for virtual link at the moment */ + +void dc_link_dp_set_drive_settings( + struct dc_link *link, + struct link_training_settings *lt_settings); + +enum link_training_result dc_link_dp_perform_link_training( + struct dc_link *link, + const struct dc_link_settings *link_setting, + bool skip_video_pattern); + +void dc_link_dp_enable_hpd(const struct dc_link *link); + +void dc_link_dp_disable_hpd(const struct dc_link *link); + +bool dc_link_dp_set_test_pattern( + struct dc_link *link, + enum dp_test_pattern test_pattern, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size); + +/* + * DPCD access interfaces + */ + +bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd); + +#endif /* DC_LINK_H_ */ -- GitLab From 2a06e0a5a491f306e22eb5a5239a6bd8ce0f1ac6 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 1 Nov 2017 11:43:36 -0400 Subject: [PATCH 0839/2547] drm/amd/display: Remove unnecessary dc_stream vtable There's no need to have this as a vtable. The vtable was initially used for stream_adjust_vmin_vmax but the condition checked here (set_drr) is always true, hence we don't need to assign this dynamically anymore. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 136 +----------------- drivers/gpu/drm/amd/display/dc/dc_stream.h | 18 +++ .../amd/display/modules/freesync/freesync.c | 84 ++++------- 3 files changed, 51 insertions(+), 187 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 63872ce500b8..f9c5ed6310b6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -164,7 +164,7 @@ static bool create_links( return false; } -static bool stream_adjust_vmin_vmax(struct dc *dc, +bool dc_stream_adjust_vmin_vmax(struct dc *dc, struct dc_stream_state **streams, int num_streams, int vmin, int vmax) { @@ -189,7 +189,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, return ret; } -static bool stream_get_crtc_position(struct dc *dc, +bool dc_stream_get_crtc_position(struct dc *dc, struct dc_stream_state **streams, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos) { @@ -214,45 +214,7 @@ static bool stream_get_crtc_position(struct dc *dc, return ret; } -static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) -{ - int i = 0; - bool ret = false; - struct pipe_ctx *pipes; - - for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { - pipes = &dc->current_state->res_ctx.pipe_ctx[i]; - dc->hwss.program_gamut_remap(pipes); - ret = true; - } - } - - return ret; -} - -static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) -{ - int i = 0; - bool ret = false; - struct pipe_ctx *pipes; - - for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_state->res_ctx.pipe_ctx[i].stream - == stream) { - - pipes = &dc->current_state->res_ctx.pipe_ctx[i]; - dc->hwss.program_csc_matrix(pipes, - stream->output_color_space, - stream->csc_color_matrix.matrix); - ret = true; - } - } - - return ret; -} - -static void set_static_screen_events(struct dc *dc, +void dc_stream_set_static_screen_events(struct dc *dc, struct dc_stream_state **streams, int num_streams, const struct dc_static_screen_events *events) @@ -343,100 +305,8 @@ static void set_test_pattern( cust_pattern_size); } -static void set_dither_option(struct dc_stream_state *stream, - enum dc_dither_option option) -{ - struct bit_depth_reduction_params params; - struct dc_link *link = stream->status.link; - struct pipe_ctx *pipes = NULL; - int i; - - for (i = 0; i < MAX_PIPES; i++) { - if (link->dc->current_state->res_ctx.pipe_ctx[i].stream == - stream) { - pipes = &link->dc->current_state->res_ctx.pipe_ctx[i]; - break; - } - } - - memset(¶ms, 0, sizeof(params)); - if (!pipes) - return; - if (option > DITHER_OPTION_MAX) - return; - - stream->dither_option = option; - - resource_build_bit_depth_reduction_params(stream, - ¶ms); - stream->bit_depth_params = params; - pipes->stream_res.opp->funcs-> - opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); -} - -void set_dpms( - struct dc *dc, - struct dc_stream_state *stream, - bool dpms_off) -{ - struct pipe_ctx *pipe_ctx = NULL; - int i; - - for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { - pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - break; - } - } - - if (!pipe_ctx) { - ASSERT(0); - return; - } - - if (stream->dpms_off != dpms_off) { - stream->dpms_off = dpms_off; - - if (dpms_off) { - core_link_disable_stream(pipe_ctx, - KEEP_ACQUIRED_RESOURCE); - - dc->hwss.pplib_apply_display_requirements( - dc, dc->current_state); - } else { - dc->hwss.pplib_apply_display_requirements( - dc, dc->current_state); - - core_link_enable_stream(dc->current_state, pipe_ctx); - } - } -} - static void allocate_dc_stream_funcs(struct dc *dc) { - if (dc->hwss.set_drr != NULL) { - dc->stream_funcs.adjust_vmin_vmax = - stream_adjust_vmin_vmax; - } - - dc->stream_funcs.set_static_screen_events = - set_static_screen_events; - - dc->stream_funcs.get_crtc_position = - stream_get_crtc_position; - - dc->stream_funcs.set_gamut_remap = - set_gamut_remap; - - dc->stream_funcs.program_csc_matrix = - program_csc_matrix; - - dc->stream_funcs.set_dither_option = - set_dither_option; - - dc->stream_funcs.set_dpms = - set_dpms; - dc->link_funcs.set_drive_settings = set_drive_settings; diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index bed2a937de71..9a64cf16c798 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -251,6 +251,24 @@ bool dc_stream_set_cursor_position( struct dc_stream_state *stream, const struct dc_cursor_position *position); +bool dc_stream_adjust_vmin_vmax(struct dc *dc, + struct dc_stream_state **stream, + int num_streams, + int vmin, + int vmax); + +bool dc_stream_get_crtc_position(struct dc *dc, + struct dc_stream_state **stream, + int num_streams, + unsigned int *v_pos, + unsigned int *nom_v_pos); + +void dc_stream_set_static_screen_events(struct dc *dc, + struct dc_stream_state **stream, + int num_streams, + const struct dc_static_screen_events *events); + + bool dc_stream_adjust_vmin_vmax(struct dc *dc, struct dc_stream_state **stream, int num_streams, diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 4d7db4aa28e0..b4723af368a5 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -132,14 +132,6 @@ struct core_freesync { #define MOD_FREESYNC_TO_CORE(mod_freesync)\ container_of(mod_freesync, struct core_freesync, public) -static bool check_dc_support(const struct dc *dc) -{ - if (dc->stream_funcs.adjust_vmin_vmax == NULL) - return false; - - return true; -} - struct mod_freesync *mod_freesync_create(struct dc *dc) { struct core_freesync *core_freesync = @@ -169,9 +161,6 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) core_freesync->dc = dc; - if (!check_dc_support(dc)) - goto fail_construct; - /* Create initial module folder in registry for freesync enable data */ flag.save_per_edid = true; flag.save_per_link = false; @@ -599,10 +588,9 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync, update_stream_freesync_context(core_freesync, streams[stream_idx]); - core_freesync->dc->stream_funcs. - adjust_vmin_vmax(core_freesync->dc, streams, - num_streams, v_total_min, - v_total_max); + dc_stream_adjust_vmin_vmax(core_freesync->dc, streams, + num_streams, v_total_min, + v_total_max); return true; @@ -625,8 +613,7 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync, core_freesync, streams[stream_idx]); - core_freesync->dc->stream_funcs. - adjust_vmin_vmax( + dc_stream_adjust_vmin_vmax( core_freesync->dc, streams, num_streams, v_total_nominal, v_total_nominal); @@ -645,11 +632,9 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync, core_freesync, streams[stream_idx]); - core_freesync->dc->stream_funcs. - adjust_vmin_vmax( - core_freesync->dc, streams, - num_streams, v_total_nominal, - v_total_nominal); + dc_stream_adjust_vmin_vmax(core_freesync->dc, streams, + num_streams, v_total_nominal, + v_total_nominal); /* Reset the cached variables */ reset_freesync_state_variables(state); @@ -665,11 +650,9 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync, * not support freesync because a former stream has * be programmed */ - core_freesync->dc->stream_funcs. - adjust_vmin_vmax( - core_freesync->dc, streams, - num_streams, v_total_nominal, - v_total_nominal); + dc_stream_adjust_vmin_vmax(core_freesync->dc, streams, + num_streams, v_total_nominal, + v_total_nominal); /* Reset the cached variables */ reset_freesync_state_variables(state); } @@ -786,9 +769,8 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, vmin = inserted_frame_v_total; /* Program V_TOTAL */ - core_freesync->dc->stream_funcs.adjust_vmin_vmax( - core_freesync->dc, streams, - num_streams, vmin, vmax); + dc_stream_adjust_vmin_vmax(core_freesync->dc, streams, + num_streams, vmin, vmax); } if (state->btr.frame_counter > 0) @@ -822,17 +804,15 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, update_stream_freesync_context(core_freesync, streams[0]); /* Program static screen ramp values */ - core_freesync->dc->stream_funcs.adjust_vmin_vmax( - core_freesync->dc, streams, - num_streams, v_total, - v_total); + dc_stream_adjust_vmin_vmax(core_freesync->dc, streams, + num_streams, v_total, + v_total); triggers.overlay_update = true; triggers.surface_update = true; - core_freesync->dc->stream_funcs.set_static_screen_events( - core_freesync->dc, streams, num_streams, - &triggers); + dc_stream_set_static_screen_events(core_freesync->dc, streams, + num_streams, &triggers); } } @@ -916,9 +896,8 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, triggers.overlay_update = true; triggers.surface_update = true; - core_freesync->dc->stream_funcs.set_static_screen_events( - core_freesync->dc, streams, num_streams, - &triggers); + dc_stream_set_static_screen_events(core_freesync->dc, streams, + num_streams, &triggers); if (freesync_program_required) /* Program freesync according to current state*/ @@ -1084,10 +1063,9 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, max_refresh); /* Program vtotal min/max */ - core_freesync->dc->stream_funcs.adjust_vmin_vmax( - core_freesync->dc, &streams, 1, - state->freesync_range.vmin, - state->freesync_range.vmax); + dc_stream_adjust_vmin_vmax(core_freesync->dc, &streams, 1, + state->freesync_range.vmin, + state->freesync_range.vmax); } if (min_refresh != 0 && @@ -1163,9 +1141,9 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); index = map_index_from_stream(core_freesync, stream); - if (core_freesync->dc->stream_funcs.get_crtc_position( - core_freesync->dc, &stream, 1, - &position.vertical_count, &position.nominal_vcount)) { + if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1, + &position.vertical_count, + &position.nominal_vcount)) { *nom_v_pos = position.nominal_vcount; *v_pos = position.vertical_count; @@ -1223,9 +1201,9 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, triggers.overlay_update = true; triggers.surface_update = true; - core_freesync->dc->stream_funcs.set_static_screen_events( - core_freesync->dc, streams, num_streams, - &triggers); + dc_stream_set_static_screen_events(core_freesync->dc, + streams, num_streams, + &triggers); } } @@ -1424,10 +1402,8 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, vmax = vmin; - core_freesync->dc->stream_funcs.adjust_vmin_vmax( - core_freesync->dc, &stream, - 1, vmin, - vmax); + dc_stream_adjust_vmin_vmax(core_freesync->dc, &stream, + 1, vmin, vmax); } } -- GitLab From 6c41f30216c2dc60a20d00e32a25fb290a179195 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 8 Nov 2017 14:57:45 +0100 Subject: [PATCH 0840/2547] drm/ttm: make unlocking in ttm_bo_cleanup_refs optional v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for the next patch. v2: actually predicate all unlocks v3: add some cleanups suggested by Michel. Signed-off-by: Christian König Reviewed-and-Tested-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 51 +++++++++++++++++++----------------- 1 file changed, 27 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index db0f670911ec..3aa63c4679f0 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -486,20 +486,21 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo) } /** - * function ttm_bo_cleanup_refs_and_unlock + * function ttm_bo_cleanup_refs * If bo idle, remove from delayed- and lru lists, and unref. * If not idle, do nothing. * * Must be called with lru_lock and reservation held, this function - * will drop both before returning. + * will drop the lru lock and optionally the reservation lock before returning. * * @interruptible Any sleeps should occur interruptibly. * @no_wait_gpu Never wait for gpu. Return -EBUSY instead. + * @unlock_resv Unlock the reservation lock as well. */ -static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, - bool interruptible, - bool no_wait_gpu) +static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, + bool interruptible, bool no_wait_gpu, + bool unlock_resv) { struct ttm_bo_global *glob = bo->glob; struct reservation_object *resv; @@ -518,7 +519,8 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, if (ret && !no_wait_gpu) { long lret; - reservation_object_unlock(bo->resv); + if (unlock_resv) + reservation_object_unlock(bo->resv); spin_unlock(&glob->lru_lock); lret = reservation_object_wait_timeout_rcu(resv, true, @@ -531,24 +533,24 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, return -EBUSY; spin_lock(&glob->lru_lock); - ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY; - - /* - * We raced, and lost, someone else holds the reservation now, - * and is probably busy in ttm_bo_cleanup_memtype_use. - * - * Even if it's not the case, because we finished waiting any - * delayed destruction would succeed, so just return success - * here. - */ - if (ret) { + if (unlock_resv && !reservation_object_trylock(bo->resv)) { + /* + * We raced, and lost, someone else holds the reservation now, + * and is probably busy in ttm_bo_cleanup_memtype_use. + * + * Even if it's not the case, because we finished waiting any + * delayed destruction would succeed, so just return success + * here. + */ spin_unlock(&glob->lru_lock); return 0; } + ret = 0; } if (ret || unlikely(list_empty(&bo->ddestroy))) { - reservation_object_unlock(bo->resv); + if (unlock_resv) + reservation_object_unlock(bo->resv); spin_unlock(&glob->lru_lock); return ret; } @@ -559,7 +561,9 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, spin_unlock(&glob->lru_lock); ttm_bo_cleanup_memtype_use(bo); - reservation_object_unlock(bo->resv); + + if (unlock_resv) + reservation_object_unlock(bo->resv); return 0; } @@ -600,8 +604,8 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) } if (!ret) - ret = ttm_bo_cleanup_refs_and_unlock(entry, false, - !remove_all); + ret = ttm_bo_cleanup_refs(entry, false, !remove_all, + true); else spin_unlock(&glob->lru_lock); @@ -770,8 +774,7 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev, kref_get(&bo->list_kref); if (!list_empty(&bo->ddestroy)) { - ret = ttm_bo_cleanup_refs_and_unlock(bo, interruptible, - no_wait_gpu); + ret = ttm_bo_cleanup_refs(bo, interruptible, no_wait_gpu, true); kref_put(&bo->list_kref, ttm_bo_release_list); return ret; } @@ -1735,7 +1738,7 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) kref_get(&bo->list_kref); if (!list_empty(&bo->ddestroy)) { - ret = ttm_bo_cleanup_refs_and_unlock(bo, false, false); + ret = ttm_bo_cleanup_refs(bo, false, false, true); kref_put(&bo->list_kref, ttm_bo_release_list); return ret; } -- GitLab From 0084e7fc0f6b5e07601715f6bb82c13a25166364 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Wed, 8 Nov 2017 17:58:51 -0500 Subject: [PATCH 0841/2547] drm/amd/display: remove stream_func vtable Signed-off-by: Tony Cheng Reviewed-by: Sun peng Li Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 32 ----------------------------- 1 file changed, 32 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5c509707ccd6..dbb03b3e2c23 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -144,37 +144,6 @@ struct dc_cap_funcs { struct dc_surface_dcc_cap *output); }; -struct dc_stream_state_funcs { - bool (*adjust_vmin_vmax)(struct dc *dc, - struct dc_stream_state **stream, - int num_streams, - int vmin, - int vmax); - bool (*get_crtc_position)(struct dc *dc, - struct dc_stream_state **stream, - int num_streams, - unsigned int *v_pos, - unsigned int *nom_v_pos); - - bool (*set_gamut_remap)(struct dc *dc, - const struct dc_stream_state *stream); - - bool (*program_csc_matrix)(struct dc *dc, - struct dc_stream_state *stream); - - void (*set_static_screen_events)(struct dc *dc, - struct dc_stream_state **stream, - int num_streams, - const struct dc_static_screen_events *events); - - void (*set_dither_option)(struct dc_stream_state *stream, - enum dc_dither_option option); - - void (*set_dpms)(struct dc *dc, - struct dc_stream_state *stream, - bool dpms_off); -}; - struct link_training_settings; struct dc_link_funcs { @@ -268,7 +237,6 @@ struct dce_hwseq; struct dc { struct dc_caps caps; struct dc_cap_funcs cap_funcs; - struct dc_stream_state_funcs stream_funcs; struct dc_link_funcs link_funcs; struct dc_config config; struct dc_debug debug; -- GitLab From db65d4ad91e7dc5b9109b115af70cf294e7686c4 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 8 Nov 2017 16:51:03 -0500 Subject: [PATCH 0842/2547] drm/amd/display: Fix Linux after optimize frontend programming We still require the update_plane_addr call in commit_planes_for_stream. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f9c5ed6310b6..f8cbc4f0b1a3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1314,11 +1314,8 @@ static void commit_planes_for_stream(struct dc *dc, if (pipe_ctx->plane_state != plane_state) continue; - if (update_type == UPDATE_TYPE_FAST) { - if (srf_updates[i].flip_addr) - dc->hwss.update_plane_addr(dc, pipe_ctx); - continue; - } + if (srf_updates[i].flip_addr) + dc->hwss.update_plane_addr(dc, pipe_ctx); } } -- GitLab From 671b00e26c6ca40f90789b0af59fafd44a096be9 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Wed, 8 Nov 2017 15:30:19 -0500 Subject: [PATCH 0843/2547] drm/amd/display: Fix use before initialize warning on stream_for_cursor. Initialize to NULL. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 30f458701f9c..b5d048b364a4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2124,7 +2124,7 @@ static void dcn10_apply_ctx_for_surface( } if (num_planes > 0) { - struct dc_stream_state *stream_for_cursor; + struct dc_stream_state *stream_for_cursor = NULL; program_all_pipe_in_tree(dc, top_pipe_to_program, context); -- GitLab From 93442184c0dd3a7e714eb117038e985e9355a9df Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 13 Nov 2017 15:42:57 -0500 Subject: [PATCH 0844/2547] drm/amdgpu/gfx8: use cached values for raster config in clear state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the cached values rather than hardcoding it. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 33 ++------------------------- 1 file changed, 2 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 426e51866a15..ee77c949bf87 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4313,37 +4313,8 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); - switch (adev->asic_type) { - case CHIP_TONGA: - case CHIP_POLARIS10: - amdgpu_ring_write(ring, 0x16000012); - amdgpu_ring_write(ring, 0x0000002A); - break; - case CHIP_POLARIS11: - case CHIP_POLARIS12: - amdgpu_ring_write(ring, 0x16000012); - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_FIJI: - amdgpu_ring_write(ring, 0x3a00161a); - amdgpu_ring_write(ring, 0x0000002e); - break; - case CHIP_CARRIZO: - amdgpu_ring_write(ring, 0x00000002); - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_TOPAZ: - amdgpu_ring_write(ring, adev->gfx.config.num_rbs == 1 ? - 0x00000000 : 0x00000002); - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_STONEY: - amdgpu_ring_write(ring, 0x00000000); - amdgpu_ring_write(ring, 0x00000000); - break; - default: - BUG(); - } + amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); + amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); -- GitLab From adfb81659cb5c6f781924601462336166fe17174 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 13 Nov 2017 15:45:31 -0500 Subject: [PATCH 0845/2547] drm/amdgpu/gfx7: use cached values for raster config in clear state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the cached values rather than hardcoding it. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 25 ++----------------------- 1 file changed, 2 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 015f37bef358..83d94c23aa78 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2551,29 +2551,8 @@ static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); - switch (adev->asic_type) { - case CHIP_BONAIRE: - amdgpu_ring_write(ring, 0x16000012); - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_KAVERI: - amdgpu_ring_write(ring, 0x00000000); /* XXX */ - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_KABINI: - case CHIP_MULLINS: - amdgpu_ring_write(ring, 0x00000000); /* XXX */ - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_HAWAII: - amdgpu_ring_write(ring, 0x3a00161a); - amdgpu_ring_write(ring, 0x0000002e); - break; - default: - amdgpu_ring_write(ring, 0x00000000); - amdgpu_ring_write(ring, 0x00000000); - break; - } + amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); + amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); -- GitLab From 56f3df448c9458ffd4c2ae62c09afc99f7ab277d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 13 Nov 2017 15:48:37 -0500 Subject: [PATCH 0846/2547] drm/amdgpu/gfx6: use cached values for raster config in clear state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the cached values rather than hardcoding it. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 9430d4809b53..edef17d93527 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -2962,25 +2962,7 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); - - switch (adev->asic_type) { - case CHIP_TAHITI: - case CHIP_PITCAIRN: - buffer[count++] = cpu_to_le32(0x2a00126a); - break; - case CHIP_VERDE: - buffer[count++] = cpu_to_le32(0x0000124a); - break; - case CHIP_OLAND: - buffer[count++] = cpu_to_le32(0x00000082); - break; - case CHIP_HAINAN: - buffer[count++] = cpu_to_le32(0x00000000); - break; - default: - buffer[count++] = cpu_to_le32(0x00000000); - break; - } + buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); -- GitLab From 6ba435812e0d85b016670ba7324d1bb1369d8428 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 8 Nov 2017 15:55:44 +0100 Subject: [PATCH 0847/2547] drm/ttm: optimize ttm_mem_evict_first v5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Deleted BOs with the same reservation object can be reaped even if they can't be reserved. v2: rebase and we still need to remove/add the BO from/to the LRU. v3: fix remove/add one more time, cleanup the logic a bit v4: we should still check if the eviction is valuable v5: add comment suggested by Michel Signed-off-by: Christian König Reviewed-and-Tested-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 54 ++++++++++++++++++++++-------------- 1 file changed, 33 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 3aa63c4679f0..07d9c6e5b6ca 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -734,47 +734,57 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, EXPORT_SYMBOL(ttm_bo_eviction_valuable); static int ttm_mem_evict_first(struct ttm_bo_device *bdev, - uint32_t mem_type, - const struct ttm_place *place, - bool interruptible, - bool no_wait_gpu) + struct reservation_object *resv, + uint32_t mem_type, + const struct ttm_place *place, + bool interruptible, + bool no_wait_gpu) { struct ttm_bo_global *glob = bdev->glob; struct ttm_mem_type_manager *man = &bdev->man[mem_type]; - struct ttm_buffer_object *bo; - int ret = -EBUSY; + struct ttm_buffer_object *bo = NULL; + bool locked = false; unsigned i; + int ret; spin_lock(&glob->lru_lock); for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) { list_for_each_entry(bo, &man->lru[i], lru) { - ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY; - if (ret) - continue; + if (bo->resv == resv) { + if (list_empty(&bo->ddestroy)) + continue; + } else { + locked = reservation_object_trylock(bo->resv); + if (!locked) + continue; + } if (place && !bdev->driver->eviction_valuable(bo, place)) { - reservation_object_unlock(bo->resv); - ret = -EBUSY; + if (locked) + reservation_object_unlock(bo->resv); continue; } - break; } - if (!ret) + /* If the inner loop terminated early, we have our candidate */ + if (&bo->lru != &man->lru[i]) break; + + bo = NULL; } - if (ret) { + if (!bo) { spin_unlock(&glob->lru_lock); - return ret; + return -EBUSY; } kref_get(&bo->list_kref); if (!list_empty(&bo->ddestroy)) { - ret = ttm_bo_cleanup_refs(bo, interruptible, no_wait_gpu, true); + ret = ttm_bo_cleanup_refs(bo, interruptible, no_wait_gpu, + locked); kref_put(&bo->list_kref, ttm_bo_release_list); return ret; } @@ -782,10 +792,11 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev, ttm_bo_del_from_lru(bo); spin_unlock(&glob->lru_lock); - BUG_ON(ret != 0); - ret = ttm_bo_evict(bo, interruptible, no_wait_gpu); - ttm_bo_unreserve(bo); + if (locked) + ttm_bo_unreserve(bo); + else + ttm_bo_add_to_lru(bo); kref_put(&bo->list_kref, ttm_bo_release_list); return ret; @@ -849,7 +860,7 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object *bo, return ret; if (mem->mm_node) break; - ret = ttm_mem_evict_first(bdev, mem_type, place, + ret = ttm_mem_evict_first(bdev, bo->resv, mem_type, place, interruptible, no_wait_gpu); if (unlikely(ret != 0)) return ret; @@ -1352,7 +1363,8 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) { while (!list_empty(&man->lru[i])) { spin_unlock(&glob->lru_lock); - ret = ttm_mem_evict_first(bdev, mem_type, NULL, false, false); + ret = ttm_mem_evict_first(bdev, NULL, mem_type, NULL, + false, false); if (ret) return ret; spin_lock(&glob->lru_lock); -- GitLab From 26f1108525c7f085fd5e555d4b62e7bba42a723b Mon Sep 17 00:00:00 2001 From: David Panariti Date: Fri, 15 Sep 2017 13:25:38 -0400 Subject: [PATCH 0848/2547] drm/amdgpu: New header for fields needed to determine state of ECC. Add header files with ECC related definitions (MASKs, SHIFTs, DEFAULTs and OFFSETS). Signed-off-by: David Panariti Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- .../asic_reg/vega10/UMC/umc_6_0_default.h | 31 +++++++++++ .../asic_reg/vega10/UMC/umc_6_0_offset.h | 52 +++++++++++++++++++ .../asic_reg/vega10/UMC/umc_6_0_sh_mask.h | 36 +++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h new file mode 100644 index 000000000000..128a18f1e362 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _umc_6_0_DEFAULT_HEADER +#define _umc_6_0_DEFAULT_HEADER + +#define mmUMCCH0_0_EccCtrl_DEFAULT 0x00000000 + +#define mmUMCCH0_0_UMC_CONFIG_DEFAULT 0x00000203 + +#define mmUMCCH0_0_UmcLocalCap_DEFAULT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h new file mode 100644 index 000000000000..6985dbba39f5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _umc_6_0_OFFSET_H_ +#define _umc_6_0_OFFSET_H_ + +#define mmUMCCH0_0_EccCtrl 0x0053 +#define mmUMCCH0_0_EccCtrl_BASE_IDX 0 +#define mmUMCCH1_0_EccCtrl 0x0853 +#define mmUMCCH1_0_EccCtrl_BASE_IDX 0 +#define mmUMCCH2_0_EccCtrl 0x1053 +#define mmUMCCH2_0_EccCtrl_BASE_IDX 0 +#define mmUMCCH3_0_EccCtrl 0x1853 +#define mmUMCCH3_0_EccCtrl_BASE_IDX 0 + +#define mmUMCCH0_0_UMC_CONFIG 0x0040 +#define mmUMCCH0_0_UMC_CONFIG_BASE_IDX 0 +#define mmUMCCH1_0_UMC_CONFIG 0x0840 +#define mmUMCCH1_0_UMC_CONFIG_BASE_IDX 0 +#define mmUMCCH2_0_UMC_CONFIG 0x1040 +#define mmUMCCH2_0_UMC_CONFIG_BASE_IDX 0 +#define mmUMCCH3_0_UMC_CONFIG 0x1840 +#define mmUMCCH3_0_UMC_CONFIG_BASE_IDX 0 + +#define mmUMCCH0_0_UmcLocalCap 0x0306 +#define mmUMCCH0_0_UmcLocalCap_BASE_IDX 0 +#define mmUMCCH1_0_UmcLocalCap 0x0b06 +#define mmUMCCH1_0_UmcLocalCap_BASE_IDX 0 +#define mmUMCCH2_0_UmcLocalCap 0x1306 +#define mmUMCCH2_0_UmcLocalCap_BASE_IDX 0 +#define mmUMCCH3_0_UmcLocalCap 0x1b06 +#define mmUMCCH3_0_UmcLocalCap_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h new file mode 100644 index 000000000000..3e857d1613f0 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _umc_6_0_SH_MASK_HEADER +#define _umc_6_0_SH_MASK_HEADER + +#define UMCCH0_0_EccCtrl__RdEccEn_MASK 0x00000400L +#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT 0xa +#define UMCCH0_0_EccCtrl__WrEccEn_MASK 0x00000001L +#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT 0x0 + +#define UMCCH0_0_UMC_CONFIG__DramReady_MASK 0x80000000L +#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT 0x1f + +#define UMCCH0_0_UmcLocalCap__EccDis_MASK 0x00000001L +#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT 0x0 + +#endif -- GitLab From 02bab92328b4d4e0f688be960f0fb5fed1c07ea2 Mon Sep 17 00:00:00 2001 From: David Panariti Date: Fri, 15 Sep 2017 16:30:08 -0400 Subject: [PATCH 0849/2547] drm/amdgpu: Add ability to determine and report if board supports ECC. Make initialization code check the ECC related registers, which are initialized by the VBIOS, to see if ECC is present and initialized and DRM_INFO() the result. Signed-off-by: David Panariti Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 206 ++++++++++++++++++++++++++ 1 file changed, 206 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index b067b46a418f..d9a91098bcb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -36,6 +36,7 @@ #include "vega10/ATHUB/athub_1_0_offset.h" #include "soc15_common.h" +#include "vega10/UMC/umc_6_0_sh_mask.h" #include "nbio_v6_1.h" #include "nbio_v7_0.h" @@ -85,6 +86,121 @@ static const u32 golden_settings_athub_1_0_0[] = SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008 }; +/* Ecc related register addresses, (BASE + reg offset) */ +/* Universal Memory Controller caps (may be fused). */ +/* UMCCH:UmcLocalCap */ +#define UMCLOCALCAPS_ADDR0 (0x00014306 + 0x00000000) +#define UMCLOCALCAPS_ADDR1 (0x00014306 + 0x00000800) +#define UMCLOCALCAPS_ADDR2 (0x00014306 + 0x00001000) +#define UMCLOCALCAPS_ADDR3 (0x00014306 + 0x00001800) +#define UMCLOCALCAPS_ADDR4 (0x00054306 + 0x00000000) +#define UMCLOCALCAPS_ADDR5 (0x00054306 + 0x00000800) +#define UMCLOCALCAPS_ADDR6 (0x00054306 + 0x00001000) +#define UMCLOCALCAPS_ADDR7 (0x00054306 + 0x00001800) +#define UMCLOCALCAPS_ADDR8 (0x00094306 + 0x00000000) +#define UMCLOCALCAPS_ADDR9 (0x00094306 + 0x00000800) +#define UMCLOCALCAPS_ADDR10 (0x00094306 + 0x00001000) +#define UMCLOCALCAPS_ADDR11 (0x00094306 + 0x00001800) +#define UMCLOCALCAPS_ADDR12 (0x000d4306 + 0x00000000) +#define UMCLOCALCAPS_ADDR13 (0x000d4306 + 0x00000800) +#define UMCLOCALCAPS_ADDR14 (0x000d4306 + 0x00001000) +#define UMCLOCALCAPS_ADDR15 (0x000d4306 + 0x00001800) + +/* Universal Memory Controller Channel config. */ +/* UMCCH:UMC_CONFIG */ +#define UMCCH_UMC_CONFIG_ADDR0 (0x00014040 + 0x00000000) +#define UMCCH_UMC_CONFIG_ADDR1 (0x00014040 + 0x00000800) +#define UMCCH_UMC_CONFIG_ADDR2 (0x00014040 + 0x00001000) +#define UMCCH_UMC_CONFIG_ADDR3 (0x00014040 + 0x00001800) +#define UMCCH_UMC_CONFIG_ADDR4 (0x00054040 + 0x00000000) +#define UMCCH_UMC_CONFIG_ADDR5 (0x00054040 + 0x00000800) +#define UMCCH_UMC_CONFIG_ADDR6 (0x00054040 + 0x00001000) +#define UMCCH_UMC_CONFIG_ADDR7 (0x00054040 + 0x00001800) +#define UMCCH_UMC_CONFIG_ADDR8 (0x00094040 + 0x00000000) +#define UMCCH_UMC_CONFIG_ADDR9 (0x00094040 + 0x00000800) +#define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000) +#define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800) +#define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000) +#define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800) +#define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000) +#define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800) + +/* Universal Memory Controller Channel Ecc config. */ +/* UMCCH:EccCtrl */ +#define UMCCH_ECCCTRL_ADDR0 (0x00014053 + 0x00000000) +#define UMCCH_ECCCTRL_ADDR1 (0x00014053 + 0x00000800) +#define UMCCH_ECCCTRL_ADDR2 (0x00014053 + 0x00001000) +#define UMCCH_ECCCTRL_ADDR3 (0x00014053 + 0x00001800) +#define UMCCH_ECCCTRL_ADDR4 (0x00054053 + 0x00000000) +#define UMCCH_ECCCTRL_ADDR5 (0x00054053 + 0x00000800) +#define UMCCH_ECCCTRL_ADDR6 (0x00054053 + 0x00001000) +#define UMCCH_ECCCTRL_ADDR7 (0x00054053 + 0x00001800) +#define UMCCH_ECCCTRL_ADDR8 (0x00094053 + 0x00000000) +#define UMCCH_ECCCTRL_ADDR9 (0x00094053 + 0x00000800) +#define UMCCH_ECCCTRL_ADDR10 (0x00094053 + 0x00001000) +#define UMCCH_ECCCTRL_ADDR11 (0x00094053 + 0x00001800) +#define UMCCH_ECCCTRL_ADDR12 (0x000d4053 + 0x00000000) +#define UMCCH_ECCCTRL_ADDR13 (0x000d4053 + 0x00000800) +#define UMCCH_ECCCTRL_ADDR14 (0x000d4053 + 0x00001000) +#define UMCCH_ECCCTRL_ADDR15 (0x000d4053 + 0x00001800) + +static const uint32_t ecc_umclocalcap_addrs[] = { + UMCLOCALCAPS_ADDR0, + UMCLOCALCAPS_ADDR1, + UMCLOCALCAPS_ADDR2, + UMCLOCALCAPS_ADDR3, + UMCLOCALCAPS_ADDR4, + UMCLOCALCAPS_ADDR5, + UMCLOCALCAPS_ADDR6, + UMCLOCALCAPS_ADDR7, + UMCLOCALCAPS_ADDR8, + UMCLOCALCAPS_ADDR9, + UMCLOCALCAPS_ADDR10, + UMCLOCALCAPS_ADDR11, + UMCLOCALCAPS_ADDR12, + UMCLOCALCAPS_ADDR13, + UMCLOCALCAPS_ADDR14, + UMCLOCALCAPS_ADDR15, +}; + +static const uint32_t ecc_umcch_umc_config_addrs[] = { + UMCCH_UMC_CONFIG_ADDR0, + UMCCH_UMC_CONFIG_ADDR1, + UMCCH_UMC_CONFIG_ADDR2, + UMCCH_UMC_CONFIG_ADDR3, + UMCCH_UMC_CONFIG_ADDR4, + UMCCH_UMC_CONFIG_ADDR5, + UMCCH_UMC_CONFIG_ADDR6, + UMCCH_UMC_CONFIG_ADDR7, + UMCCH_UMC_CONFIG_ADDR8, + UMCCH_UMC_CONFIG_ADDR9, + UMCCH_UMC_CONFIG_ADDR10, + UMCCH_UMC_CONFIG_ADDR11, + UMCCH_UMC_CONFIG_ADDR12, + UMCCH_UMC_CONFIG_ADDR13, + UMCCH_UMC_CONFIG_ADDR14, + UMCCH_UMC_CONFIG_ADDR15, +}; + +static const uint32_t ecc_umcch_eccctrl_addrs[] = { + UMCCH_ECCCTRL_ADDR0, + UMCCH_ECCCTRL_ADDR1, + UMCCH_ECCCTRL_ADDR2, + UMCCH_ECCCTRL_ADDR3, + UMCCH_ECCCTRL_ADDR4, + UMCCH_ECCCTRL_ADDR5, + UMCCH_ECCCTRL_ADDR6, + UMCCH_ECCCTRL_ADDR7, + UMCCH_ECCCTRL_ADDR8, + UMCCH_ECCCTRL_ADDR9, + UMCCH_ECCCTRL_ADDR10, + UMCCH_ECCCTRL_ADDR11, + UMCCH_ECCCTRL_ADDR12, + UMCCH_ECCCTRL_ADDR13, + UMCCH_ECCCTRL_ADDR14, + UMCCH_ECCCTRL_ADDR15, +}; + static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, @@ -389,6 +505,85 @@ static int gmc_v9_0_early_init(void *handle) return 0; } +static int gmc_v9_0_ecc_available(struct amdgpu_device *adev) +{ + uint32_t reg_val; + uint32_t reg_addr; + uint32_t field_val; + size_t i; + uint32_t fv2; + size_t lost_sheep; + + DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n"); + + lost_sheep = 0; + for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) { + reg_addr = ecc_umclocalcap_addrs[i]; + DRM_DEBUG("ecc: " + "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n", + i, reg_addr); + reg_val = RREG32(reg_addr); + field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap, + EccDis); + DRM_DEBUG("ecc: " + "reg_val: 0x%08x, " + "EccDis: 0x%08x, ", + reg_val, field_val); + if (field_val) { + DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n"); + ++lost_sheep; + } + } + + for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) { + reg_addr = ecc_umcch_umc_config_addrs[i]; + DRM_DEBUG("ecc: " + "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x", + i, reg_addr); + reg_val = RREG32(reg_addr); + field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG, + DramReady); + DRM_DEBUG("ecc: " + "reg_val: 0x%08x, " + "DramReady: 0x%08x\n", + reg_val, field_val); + + if (!field_val) { + DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n"); + ++lost_sheep; + } + } + + for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) { + reg_addr = ecc_umcch_eccctrl_addrs[i]; + DRM_DEBUG("ecc: " + "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ", + i, reg_addr); + reg_val = RREG32(reg_addr); + field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl, + WrEccEn); + fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl, + RdEccEn); + DRM_DEBUG("ecc: " + "reg_val: 0x%08x, " + "WrEccEn: 0x%08x, " + "RdEccEn: 0x%08x\n", + reg_val, field_val, fv2); + + if (!field_val) { + DRM_ERROR("ecc: WrEccEn is not set\n"); + ++lost_sheep; + } + if (!fv2) { + DRM_ERROR("ecc: RdEccEn is not set\n"); + ++lost_sheep; + } + } + + DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep); + return lost_sheep == 0; +} + static int gmc_v9_0_late_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -403,6 +598,7 @@ static int gmc_v9_0_late_init(void *handle) */ unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 }; unsigned i; + int r; for(i = 0; i < adev->num_rings; ++i) { struct amdgpu_ring *ring = adev->rings[i]; @@ -418,6 +614,16 @@ static int gmc_v9_0_late_init(void *handle) for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) BUG_ON(vm_inv_eng[i] > 16); + r = gmc_v9_0_ecc_available(adev); + if (r == 1) { + DRM_INFO("ECC is active.\n"); + } else if (r == 0) { + DRM_INFO("ECC is not present.\n"); + } else { + DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r); + return r; + } + return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); } -- GitLab From 424e2c8580286b75c37dc02f26f4fb6168549d32 Mon Sep 17 00:00:00 2001 From: Roger He Date: Fri, 10 Nov 2017 19:05:13 +0800 Subject: [PATCH 0850/2547] drm/amd/amdgpu: not allow gtt size exceed 75%*system memory size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit keep consistency with threshold of swapout Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 44983d16bf61..b12a46fadb16 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1330,9 +1330,14 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) DRM_INFO("amdgpu: %uM of VRAM memory ready\n", (unsigned) (adev->mc.real_vram_size / (1024 * 1024))); - if (amdgpu_gtt_size == -1) - gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), - adev->mc.mc_vram_size); + if (amdgpu_gtt_size == -1) { + struct sysinfo si; + + si_meminfo(&si); + gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), + adev->mc.mc_vram_size), + ((uint64_t)si.totalram * si.mem_unit * 3/4)); + } else gtt_size = (uint64_t)amdgpu_gtt_size << 20; r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT); -- GitLab From 299c776cebb01c121f5deb77f2d02a8340f072e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Wed, 15 Nov 2017 11:37:23 +0100 Subject: [PATCH 0851/2547] amdgpu: Don't use DRM_ERROR when failing to allocate a BO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This can be triggered by userspace, e.g. trying to allocate too large a BO, so it shouldn't log anything by default. Callers need to handle failure anyway. Reviewed-by: Alex Deucher Reviewed-by: Christian König Signed-off-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index e87eedcc0da9..3ad4cf0f22f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -72,7 +72,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, initial_domain |= AMDGPU_GEM_DOMAIN_GTT; goto retry; } - DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", + DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", size, initial_domain, alignment, r); } return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 5acf20cfb1d0..3233d5988f66 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -314,8 +314,8 @@ static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, return true; fail: - DRM_ERROR("BO size %lu > total memory in domain: %llu\n", size, - man->size << PAGE_SHIFT); + DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, + man->size << PAGE_SHIFT); return false; } -- GitLab From 11c6b82afb4cd696e10ab1cfaad3bbfb8dd4f16f Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Mon, 13 Nov 2017 20:41:56 +0800 Subject: [PATCH 0852/2547] drm/amdgpu:cleanup stolen vga memory finish MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index b12a46fadb16..f34adb0cd1ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1401,15 +1401,10 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) if (!adev->mman.initialized) return; + amdgpu_ttm_debugfs_fini(adev); - if (adev->stolen_vga_memory) { - r = amdgpu_bo_reserve(adev->stolen_vga_memory, true); - if (r == 0) { - amdgpu_bo_unpin(adev->stolen_vga_memory); - amdgpu_bo_unreserve(adev->stolen_vga_memory); - } - amdgpu_bo_unref(&adev->stolen_vga_memory); - } + amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); + ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); if (adev->gds.mem.total_size) -- GitLab From c79ee7d8c6cba8775b842063cf5bcdf101dc1e36 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 14 Nov 2017 11:52:35 +0800 Subject: [PATCH 0853/2547] drm/amdgpu:cleanup GMC & gart garbage function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit for gart_ram_alloc/free, they are never used in driver thus ripe them out totally. for gart_vram_pin/unpin, they are not needed becuase we can use bo_creat_kernel/free to replace the original manual way in the gart_vram_alloc/free, thus gart_vram_pin/unpin can also be riped out. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 136 +---------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 4 - drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 - drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 7 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 7 +- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 7 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +- 7 files changed, 13 insertions(+), 156 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index fe818501c520..10eeb307700c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -56,63 +56,6 @@ * Common GART table functions. */ -/** - * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table - * - * @adev: amdgpu_device pointer - * - * Allocate system memory for GART page table - * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the - * gart table to be in system memory. - * Returns 0 for success, -ENOMEM for failure. - */ -int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) -{ - void *ptr; - - ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size, - &adev->gart.table_addr); - if (ptr == NULL) { - return -ENOMEM; - } -#ifdef CONFIG_X86 - if (0) { - set_memory_uc((unsigned long)ptr, - adev->gart.table_size >> PAGE_SHIFT); - } -#endif - adev->gart.ptr = ptr; - memset((void *)adev->gart.ptr, 0, adev->gart.table_size); - return 0; -} - -/** - * amdgpu_gart_table_ram_free - free system ram for gart page table - * - * @adev: amdgpu_device pointer - * - * Free system memory for GART page table - * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the - * gart table to be in system memory. - */ -void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) -{ - if (adev->gart.ptr == NULL) { - return; - } -#ifdef CONFIG_X86 - if (0) { - set_memory_wb((unsigned long)adev->gart.ptr, - adev->gart.table_size >> PAGE_SHIFT); - } -#endif - pci_free_consistent(adev->pdev, adev->gart.table_size, - (void *)adev->gart.ptr, - adev->gart.table_addr); - adev->gart.ptr = NULL; - adev->gart.table_addr = 0; -} - /** * amdgpu_gart_table_vram_alloc - allocate vram for gart page table * @@ -125,75 +68,9 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) */ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) { - int r; - - if (adev->gart.robj == NULL) { - r = amdgpu_bo_create(adev, adev->gart.table_size, - PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, 0, &adev->gart.robj); - if (r) { - return r; - } - } - return 0; -} - -/** - * amdgpu_gart_table_vram_pin - pin gart page table in vram - * - * @adev: amdgpu_device pointer - * - * Pin the GART page table in vram so it will not be moved - * by the memory manager (pcie r4xx, r5xx+). These asics require the - * gart table to be in video memory. - * Returns 0 for success, error for failure. - */ -int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev) -{ - uint64_t gpu_addr; - int r; - - r = amdgpu_bo_reserve(adev->gart.robj, false); - if (unlikely(r != 0)) - return r; - r = amdgpu_bo_pin(adev->gart.robj, - AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr); - if (r) { - amdgpu_bo_unreserve(adev->gart.robj); - return r; - } - r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr); - if (r) - amdgpu_bo_unpin(adev->gart.robj); - amdgpu_bo_unreserve(adev->gart.robj); - adev->gart.table_addr = gpu_addr; - return r; -} - -/** - * amdgpu_gart_table_vram_unpin - unpin gart page table in vram - * - * @adev: amdgpu_device pointer - * - * Unpin the GART page table in vram (pcie r4xx, r5xx+). - * These asics require the gart table to be in video memory. - */ -void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev) -{ - int r; - - if (adev->gart.robj == NULL) { - return; - } - r = amdgpu_bo_reserve(adev->gart.robj, true); - if (likely(r == 0)) { - amdgpu_bo_kunmap(adev->gart.robj); - amdgpu_bo_unpin(adev->gart.robj); - amdgpu_bo_unreserve(adev->gart.robj); - adev->gart.ptr = NULL; - } + return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.robj, + &adev->gart.table_addr, &adev->gart.ptr); } /** @@ -207,10 +84,9 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev) */ void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) { - if (adev->gart.robj == NULL) { - return; - } - amdgpu_bo_unref(&adev->gart.robj); + amdgpu_bo_free_kernel(&adev->gart.robj, + &adev->gart.table_addr, + &adev->gart.ptr); } /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h index afbe803b1a13..f15e319580ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h @@ -56,12 +56,8 @@ struct amdgpu_gart { const struct amdgpu_gart_funcs *gart_funcs; }; -int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); -void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); -int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); -void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); int amdgpu_gart_init(struct amdgpu_device *adev); void amdgpu_gart_fini(struct amdgpu_device *adev); int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index f34adb0cd1ea..d49c768cf3dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1397,8 +1397,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) void amdgpu_ttm_fini(struct amdgpu_device *adev) { - int r; - if (!adev->mman.initialized) return; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index c8e47c36608e..f3e5c9c6a52d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -483,16 +483,14 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) { - int r, i; + int i; u32 field; if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; } - r = amdgpu_gart_table_vram_pin(adev); - if (r) - return r; + /* Setup TLB control */ WREG32(mmMC_VM_MX_L1_TLB_CNTL, (0xA << 7) | @@ -619,7 +617,6 @@ static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) WREG32(mmVM_L2_CNTL3, VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); - amdgpu_gart_table_vram_unpin(adev); } static void gmc_v6_0_gart_fini(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 2b7338e22409..6d153fa8175c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -588,16 +588,14 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) */ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) { - int r, i; + int i; u32 tmp, field; if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; } - r = amdgpu_gart_table_vram_pin(adev); - if (r) - return r; + /* Setup TLB control */ tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); @@ -730,7 +728,6 @@ static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); WREG32(mmVM_L2_CNTL, tmp); WREG32(mmVM_L2_CNTL2, 0); - amdgpu_gart_table_vram_unpin(adev); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index e30a96a8f49b..7ee5f21295d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -787,16 +787,14 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) */ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) { - int r, i; + int i; u32 tmp, field; if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; } - r = amdgpu_gart_table_vram_pin(adev); - if (r) - return r; + /* Setup TLB control */ tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); @@ -946,7 +944,6 @@ static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); WREG32(mmVM_L2_CNTL, tmp); WREG32(mmVM_L2_CNTL2, 0); - amdgpu_gart_table_vram_unpin(adev); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index d9a91098bcb1..4960805bf989 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -869,7 +869,7 @@ static int gmc_v9_0_sw_init(void *handle) } /** - * gmc_v8_0_gart_fini - vm fini callback + * gmc_v9_0_gart_fini - vm fini callback * * @adev: amdgpu_device pointer * @@ -933,9 +933,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; } - r = amdgpu_gart_table_vram_pin(adev); - if (r) - return r; switch (adev->asic_type) { case CHIP_RAVEN: @@ -1013,7 +1010,6 @@ static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) { gfxhub_v1_0_gart_disable(adev); mmhub_v1_0_gart_disable(adev); - amdgpu_gart_table_vram_unpin(adev); } static int gmc_v9_0_hw_fini(void *handle) -- GitLab From f59548c8824c8e361120bf87a12fc3a68f17a1ce Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 14 Nov 2017 11:55:50 +0800 Subject: [PATCH 0854/2547] drm/amdgpu:fix NULL pointer access during drv remove MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit NULL pointer is because original logic will step into set_pde_pte() even after the gart.ptr is freed due to there are twice gart_unbind() on all gart area. also, there are other minor fixes: 1,since gart_init only create dummy page, the corresponding gart_fini shouldn't do more like unbinding all GART, this is unnecessary because in driver fini stage all GART unbinding had already been done during each IP's SW_FINI (GMC's SW_FINI is the last one called), so remove the step for the GART unbinding in gart_fini(). 2,gart_fini() is already invoked during each GMC IP's gart_fini routine,e.g. gmc_vx_0_gart_fini(), so no need to manually call it during ttm_fini(). 3,amdgpu_gem_force_release() should be put ahead of amdgpu_vm_manager_fini() Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 9 +-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- 8 files changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index a7066f55fe2c..ecc2e60e5f0c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1412,6 +1412,7 @@ struct amdgpu_fw_vram_usage { }; int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev); +void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev); /* * CGS diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ee2a5f9a32f0..fc34f745f058 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2506,7 +2506,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev) /* evict vram memory */ amdgpu_bo_evict_vram(adev); amdgpu_ib_pool_fini(adev); - amdgpu_fw_reserve_vram_fini(adev); amdgpu_fence_driver_fini(adev); amdgpu_fbdev_fini(adev); r = amdgpu_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 10eeb307700c..707f85825996 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -253,10 +253,8 @@ int amdgpu_gart_init(struct amdgpu_device *adev) #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS /* Allocate pages table */ adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages); - if (adev->gart.pages == NULL) { - amdgpu_gart_fini(adev); + if (adev->gart.pages == NULL) return -ENOMEM; - } #endif return 0; @@ -271,11 +269,6 @@ int amdgpu_gart_init(struct amdgpu_device *adev) */ void amdgpu_gart_fini(struct amdgpu_device *adev) { - if (adev->gart.ready) { - /* unbind pages */ - amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages); - } - adev->gart.ready = false; #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS vfree(adev->gart.pages); adev->gart.pages = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index d49c768cf3dc..07ecf721ebf9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1402,6 +1402,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) amdgpu_ttm_debugfs_fini(adev); amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); + amdgpu_fw_reserve_vram_fini(adev); ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); @@ -1412,7 +1413,6 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) if (adev->gds.oa.total_size) ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); ttm_bo_device_release(&adev->mman.bdev); - amdgpu_gart_fini(adev); amdgpu_ttm_global_fini(adev); adev->mman.initialized = false; DRM_INFO("amdgpu: ttm finalized\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index f3e5c9c6a52d..9c672ece9f18 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -899,9 +899,9 @@ static int gmc_v6_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_gem_force_release(adev); amdgpu_vm_manager_fini(adev); gmc_v6_0_gart_fini(adev); - amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); release_firmware(adev->mc.fw); adev->mc.fw = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 6d153fa8175c..de7a249f0e24 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1049,9 +1049,9 @@ static int gmc_v7_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_gem_force_release(adev); amdgpu_vm_manager_fini(adev); gmc_v7_0_gart_fini(adev); - amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); release_firmware(adev->mc.fw); adev->mc.fw = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 7ee5f21295d4..67778744da5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1146,9 +1146,9 @@ static int gmc_v8_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_gem_force_release(adev); amdgpu_vm_manager_fini(adev); gmc_v8_0_gart_fini(adev); - amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); release_firmware(adev->mc.fw); adev->mc.fw = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 4960805bf989..798f7fc2d4e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -885,9 +885,9 @@ static int gmc_v9_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_gem_force_release(adev); amdgpu_vm_manager_fini(adev); gmc_v9_0_gart_fini(adev); - amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); return 0; -- GitLab From 9921167d9086d666217fd98be5a28bb43c193a34 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 14 Nov 2017 16:50:31 +0800 Subject: [PATCH 0855/2547] drm/amdgpu:cleanup unused stack var MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index fc34f745f058..29c81c387420 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -684,7 +684,6 @@ int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) { int r = 0; int i; - u64 gpu_addr; u64 vram_size = adev->mc.visible_vram_size; u64 offset = adev->fw_vram_usage.start_offset; u64 size = adev->fw_vram_usage.size; @@ -728,7 +727,7 @@ int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) AMDGPU_GEM_DOMAIN_VRAM, adev->fw_vram_usage.start_offset, (adev->fw_vram_usage.start_offset + - adev->fw_vram_usage.size), &gpu_addr); + adev->fw_vram_usage.size), NULL); if (r) goto error_pin; r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo, -- GitLab From 84e5b5161e7159bcf24dfeed9f985bd86e354ea8 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 14 Nov 2017 16:52:14 +0800 Subject: [PATCH 0856/2547] drm/amdgpu:free CSA in unified place MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit instead of doing it in each GFX ip's sw_fini Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 - 5 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 29c81c387420..fdce06b5b2b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1893,6 +1893,7 @@ static int amdgpu_fini(struct amdgpu_device *adev) if (!adev->ip_blocks[i].status.hw) continue; if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { + amdgpu_free_static_csa(adev); amdgpu_wb_fini(adev); amdgpu_vram_scratch_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 0769cb935318..e7dfb7b44b4b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -47,6 +47,12 @@ int amdgpu_allocate_static_csa(struct amdgpu_device *adev) return 0; } +void amdgpu_free_static_csa(struct amdgpu_device *adev) { + amdgpu_bo_free_kernel(&adev->virt.csa_obj, + &adev->virt.csa_vmid0_addr, + NULL); +} + /* * amdgpu_map_static_csa should be called during amdgpu_vm_init * it maps virtual address "AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index f77d116c7a1c..6a83425aa9ed 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -283,6 +283,7 @@ bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); int amdgpu_allocate_static_csa(struct amdgpu_device *adev); int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amdgpu_bo_va **bo_va); +void amdgpu_free_static_csa(struct amdgpu_device *adev); void amdgpu_virt_init_setting(struct amdgpu_device *adev); uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index ee77c949bf87..d02493cf9175 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -2114,7 +2114,6 @@ static int gfx_v8_0_sw_fini(void *handle) amdgpu_gfx_compute_mqd_sw_fini(adev); amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); amdgpu_gfx_kiq_fini(adev); - amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); gfx_v8_0_mec_fini(adev); gfx_v8_0_rlc_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 5ba24792f801..560d8e76d14c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1464,7 +1464,6 @@ static int gfx_v9_0_sw_fini(void *handle) amdgpu_gfx_compute_mqd_sw_fini(adev); amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); amdgpu_gfx_kiq_fini(adev); - amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); gfx_v9_0_mec_fini(adev); gfx_v9_0_ngg_fini(adev); -- GitLab From a95b0275ffc54131788014f15e7cb7b973201e2e Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 14 Nov 2017 16:53:51 +0800 Subject: [PATCH 0857/2547] drm/amdgpu:cleanup firmware.fw_buf alloc/free MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit use bo_create/free_kernel instead of manually doing it Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 43 +++++------------------ 1 file changed, 9 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index ab9b2d4461a1..474f88fbafce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -359,7 +359,6 @@ static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, int amdgpu_ucode_init_bo(struct amdgpu_device *adev) { - struct amdgpu_bo **bo = &adev->firmware.fw_buf; uint64_t fw_offset = 0; int i, err; struct amdgpu_firmware_info *ucode = NULL; @@ -371,35 +370,15 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) } if (!adev->in_gpu_reset) { - err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, + err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS|AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, - NULL, NULL, 0, bo); + &adev->firmware.fw_buf, + &adev->firmware.fw_buf_mc, + &adev->firmware.fw_buf_ptr); if (err) { - dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); + dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); goto failed; } - - err = amdgpu_bo_reserve(*bo, false); - if (err) { - dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err); - goto failed_reserve; - } - - err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, - &adev->firmware.fw_buf_mc); - if (err) { - dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err); - goto failed_pin; - } - - err = amdgpu_bo_kmap(*bo, &adev->firmware.fw_buf_ptr); - if (err) { - dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err); - goto failed_kmap; - } - - amdgpu_bo_unreserve(*bo); } memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); @@ -436,12 +415,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) } return 0; -failed_kmap: - amdgpu_bo_unpin(*bo); -failed_pin: - amdgpu_bo_unreserve(*bo); -failed_reserve: - amdgpu_bo_unref(bo); failed: if (err) adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; @@ -464,8 +437,10 @@ int amdgpu_ucode_fini_bo(struct amdgpu_device *adev) ucode->kaddr = NULL; } } - amdgpu_bo_unref(&adev->firmware.fw_buf); - adev->firmware.fw_buf = NULL; + + amdgpu_bo_free_kernel(&adev->firmware.fw_buf, + &adev->firmware.fw_buf_mc, + &adev->firmware.fw_buf_ptr); return 0; } -- GitLab From 241361350648adaaa3510410245a66a7c02b2b8e Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 14 Nov 2017 16:56:55 +0800 Subject: [PATCH 0858/2547] drm/amdgpu:show error message if fail on event4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Monk Liu Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index fdce06b5b2b8..636a9138067e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1942,7 +1942,8 @@ static int amdgpu_fini(struct amdgpu_device *adev) } if (amdgpu_sriov_vf(adev)) - amdgpu_virt_release_full_gpu(adev, false); + if (amdgpu_virt_release_full_gpu(adev, false)) + DRM_ERROR("failed to release exclusive mode on fini\n"); return 0; } -- GitLab From 129d65c18ecfb249aceb540c31fdaf79bd5a11ff Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Wed, 15 Nov 2017 17:10:13 +0800 Subject: [PATCH 0859/2547] drm/amdgpu:fix virtual dce bug this fix the issue that access memory after freed after driver unloaded. Signed-off-by: Monk Liu Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c index a8829af120c1..39460eb1e71a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c @@ -437,6 +437,8 @@ static int dce_virtual_sw_fini(void *handle) drm_kms_helper_poll_fini(adev->ddev); drm_mode_config_cleanup(adev->ddev); + /* clear crtcs pointer to avoid dce irq finish routine access freed data */ + memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS); adev->mode_info.mode_config_initialized = false; return 0; } @@ -723,7 +725,7 @@ static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *ad int crtc, enum amdgpu_interrupt_state state) { - if (crtc >= adev->mode_info.num_crtc) { + if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) { DRM_DEBUG("invalid crtc %d\n", crtc); return; } -- GitLab From 1719efc2327dc7485f30f6674c6ba4a793ac3a25 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Thu, 16 Nov 2017 11:11:39 +0800 Subject: [PATCH 0860/2547] drm/amdgpu:cancel timer of virtual DCE(v2) virtual DCE Timer structure is already released after its sw_fini(), so we need to cancel the its Timer in hw_fini() otherwise the Timer canceling is missed. v2: use for loop and num_crtc to replace original code Signed-off-by: Monk Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c index 39460eb1e71a..120dd3b26fc2 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c @@ -44,6 +44,9 @@ static void dce_virtual_set_display_funcs(struct amdgpu_device *adev); static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev); static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev, int index); +static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, + int crtc, + enum amdgpu_interrupt_state state); /** * dce_virtual_vblank_wait - vblank wait asic callback. @@ -491,6 +494,13 @@ static int dce_virtual_hw_init(void *handle) static int dce_virtual_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i = 0; + + for (i = 0; imode_info.num_crtc; i++) + if (adev->mode_info.crtcs[i]) + dce_virtual_set_crtc_vblank_interrupt_state(adev, i, AMDGPU_IRQ_STATE_DISABLE); + return 0; } -- GitLab From 35888630cb65d2a7e28f44b042b671f7d6e91f60 Mon Sep 17 00:00:00 2001 From: Shirish S Date: Tue, 7 Nov 2017 08:56:25 +0530 Subject: [PATCH 0861/2547] drm/amd/display: fix static checker warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes static checker warning of "warn: cast after binop" introduced by 56087b31 drm/amd/display: fix high part address in dm_plane_helper_prepare_fb() Signed-off-by: Shirish S Reviewed-by: Michel Dänzer Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 80567aa1968e..41e829ac2a57 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3001,7 +3001,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, = lower_32_bits(afb->address); plane_state->address.video_progressive.luma_addr.high_part = upper_32_bits(afb->address); - chroma_addr = afb->address + (u64)(awidth * new_state->fb->height); + chroma_addr = afb->address + (u64)awidth * new_state->fb->height; plane_state->address.video_progressive.chroma_addr.low_part = lower_32_bits(chroma_addr); plane_state->address.video_progressive.chroma_addr.high_part -- GitLab From 31b8adab3247eaa6cffbaa59276456b694718cc8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 15 Nov 2017 20:07:38 +0100 Subject: [PATCH 0862/2547] drm/amdgpu: require a root bus window above 4GB for BAR resize MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Don't even try to resize the BAR when there is no window above 4GB. Signed-off-by: Christian König Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 636a9138067e..4e668b70371e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -764,6 +764,9 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) { u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size); u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; + struct pci_bus *root; + struct resource *res; + unsigned i; u16 cmd; int r; @@ -771,6 +774,21 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) if (amdgpu_sriov_vf(adev)) return 0; + /* Check if the root BUS has 64bit memory resources */ + root = adev->pdev->bus; + while (root->parent) + root = root->parent; + + pci_bus_for_each_resource(root, res, i) { + if (res && res->flags & IORESOURCE_MEM_64 && + res->start > 0x100000000ull) + break; + } + + /* Trying to resize is pointless without a root hub window above 4GB */ + if (!res) + return 0; + /* Disable memory decoding while we change the BAR addresses and size */ pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); pci_write_config_word(adev->pdev, PCI_COMMAND, -- GitLab From 090528639321ab09c150603c0da3c38c26aa5ea9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 15 Nov 2017 11:05:17 +0100 Subject: [PATCH 0863/2547] drm/ttm: fix ttm_mem_evict_first once more MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code path isn't hit at the moment, but we need to take the lock to add the BO back to the LRU. Signed-off-by: Christian König Reviewed-and-Tested-by: Michel Dänzer Reviewed-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 07d9c6e5b6ca..7c1eac4f4b4b 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -793,10 +793,13 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev, spin_unlock(&glob->lru_lock); ret = ttm_bo_evict(bo, interruptible, no_wait_gpu); - if (locked) + if (locked) { ttm_bo_unreserve(bo); - else + } else { + spin_lock(&glob->lru_lock); ttm_bo_add_to_lru(bo); + spin_unlock(&glob->lru_lock); + } kref_put(&bo->list_kref, ttm_bo_release_list); return ret; -- GitLab From c0c2c3bffc946f5a44ee695c663cbca96dacc4d0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 15 Nov 2017 13:20:09 +0100 Subject: [PATCH 0864/2547] drm/ttm: completely rework ttm_bo_delayed_delete MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no guarantee that the next entry on the ddelete list stays on the list when we drop the locks. Completely rework this mess by moving processed entries on a temporary list. Signed-off-by: Christian König Reviewed-and-Tested-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 72 ++++++++++++------------------------ 1 file changed, 23 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 7c1eac4f4b4b..e79c927e0075 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -572,60 +572,37 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, * Traverse the delayed list, and call ttm_bo_cleanup_refs on all * encountered buffers. */ - -static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) +static bool ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) { struct ttm_bo_global *glob = bdev->glob; - struct ttm_buffer_object *entry = NULL; - int ret = 0; - - spin_lock(&glob->lru_lock); - if (list_empty(&bdev->ddestroy)) - goto out_unlock; - - entry = list_first_entry(&bdev->ddestroy, - struct ttm_buffer_object, ddestroy); - kref_get(&entry->list_kref); + struct list_head removed; + bool empty; - for (;;) { - struct ttm_buffer_object *nentry = NULL; - - if (entry->ddestroy.next != &bdev->ddestroy) { - nentry = list_first_entry(&entry->ddestroy, - struct ttm_buffer_object, ddestroy); - kref_get(&nentry->list_kref); - } + INIT_LIST_HEAD(&removed); - ret = reservation_object_trylock(entry->resv) ? 0 : -EBUSY; - if (remove_all && ret) { - spin_unlock(&glob->lru_lock); - ret = reservation_object_lock(entry->resv, NULL); - spin_lock(&glob->lru_lock); - } + spin_lock(&glob->lru_lock); + while (!list_empty(&bdev->ddestroy)) { + struct ttm_buffer_object *bo; - if (!ret) - ret = ttm_bo_cleanup_refs(entry, false, !remove_all, - true); - else - spin_unlock(&glob->lru_lock); + bo = list_first_entry(&bdev->ddestroy, struct ttm_buffer_object, + ddestroy); + kref_get(&bo->list_kref); + list_move_tail(&bo->ddestroy, &removed); + spin_unlock(&glob->lru_lock); - kref_put(&entry->list_kref, ttm_bo_release_list); - entry = nentry; + reservation_object_lock(bo->resv, NULL); - if (ret || !entry) - goto out; + spin_lock(&glob->lru_lock); + ttm_bo_cleanup_refs(bo, false, !remove_all, true); + kref_put(&bo->list_kref, ttm_bo_release_list); spin_lock(&glob->lru_lock); - if (list_empty(&entry->ddestroy)) - break; } - -out_unlock: + list_splice_tail(&removed, &bdev->ddestroy); + empty = list_empty(&bdev->ddestroy); spin_unlock(&glob->lru_lock); -out: - if (entry) - kref_put(&entry->list_kref, ttm_bo_release_list); - return ret; + + return empty; } static void ttm_bo_delayed_workqueue(struct work_struct *work) @@ -633,7 +610,7 @@ static void ttm_bo_delayed_workqueue(struct work_struct *work) struct ttm_bo_device *bdev = container_of(work, struct ttm_bo_device, wq.work); - if (ttm_bo_delayed_delete(bdev, false)) { + if (!ttm_bo_delayed_delete(bdev, false)) { schedule_delayed_work(&bdev->wq, ((HZ / 100) < 1) ? 1 : HZ / 100); } @@ -1573,13 +1550,10 @@ int ttm_bo_device_release(struct ttm_bo_device *bdev) cancel_delayed_work_sync(&bdev->wq); - while (ttm_bo_delayed_delete(bdev, true)) - ; - - spin_lock(&glob->lru_lock); - if (list_empty(&bdev->ddestroy)) + if (ttm_bo_delayed_delete(bdev, true)) TTM_DEBUG("Delayed destroy list was clean\n"); + spin_lock(&glob->lru_lock); for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) if (list_empty(&bdev->man[0].lru[0])) TTM_DEBUG("Swap list %d was clean\n", i); -- GitLab From ba87349ed31ee623f3380b5feedaf16a8dfa25bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 16 Feb 2017 14:25:30 +0100 Subject: [PATCH 0865/2547] drm/ttm: cleanup coding style in ttm_bo_api.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extern is the default for function declerations anyway and this solves a bunch of 80char per line issues. Signed-off-by: Christian König Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher --- include/drm/ttm/ttm_bo_api.h | 131 +++++++++++++++-------------------- 1 file changed, 54 insertions(+), 77 deletions(-) diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index fa07be197945..29df3a472bcf 100644 --- a/include/drm/ttm/ttm_bo_api.h +++ b/include/drm/ttm/ttm_bo_api.h @@ -288,8 +288,7 @@ ttm_bo_reference(struct ttm_buffer_object *bo) * Returns -EBUSY if no_wait is true and the buffer is busy. * Returns -ERESTARTSYS if interrupted by a signal. */ -extern int ttm_bo_wait(struct ttm_buffer_object *bo, - bool interruptible, bool no_wait); +int ttm_bo_wait(struct ttm_buffer_object *bo, bool interruptible, bool no_wait); /** * ttm_bo_mem_compat - Check if proposed placement is compatible with a bo @@ -300,9 +299,8 @@ extern int ttm_bo_wait(struct ttm_buffer_object *bo, * * Returns true if the placement is compatible */ -extern bool ttm_bo_mem_compat(struct ttm_placement *placement, - struct ttm_mem_reg *mem, - uint32_t *new_flags); +bool ttm_bo_mem_compat(struct ttm_placement *placement, struct ttm_mem_reg *mem, + uint32_t *new_flags); /** * ttm_bo_validate @@ -320,10 +318,10 @@ extern bool ttm_bo_mem_compat(struct ttm_placement *placement, * -EBUSY if no_wait is true and buffer busy. * -ERESTARTSYS if interrupted by a signal. */ -extern int ttm_bo_validate(struct ttm_buffer_object *bo, - struct ttm_placement *placement, - bool interruptible, - bool no_wait_gpu); +int ttm_bo_validate(struct ttm_buffer_object *bo, + struct ttm_placement *placement, + bool interruptible, + bool no_wait_gpu); /** * ttm_bo_unref @@ -332,7 +330,7 @@ extern int ttm_bo_validate(struct ttm_buffer_object *bo, * * Unreference and clear a pointer to a buffer object. */ -extern void ttm_bo_unref(struct ttm_buffer_object **bo); +void ttm_bo_unref(struct ttm_buffer_object **bo); /** * ttm_bo_add_to_lru @@ -344,7 +342,7 @@ extern void ttm_bo_unref(struct ttm_buffer_object **bo); * This function must be called with struct ttm_bo_global::lru_lock held, and * is typically called immediately prior to unreserving a bo. */ -extern void ttm_bo_add_to_lru(struct ttm_buffer_object *bo); +void ttm_bo_add_to_lru(struct ttm_buffer_object *bo); /** * ttm_bo_del_from_lru @@ -356,7 +354,7 @@ extern void ttm_bo_add_to_lru(struct ttm_buffer_object *bo); * and is usually called just immediately after the bo has been reserved to * avoid recursive reservation from lru lists. */ -extern void ttm_bo_del_from_lru(struct ttm_buffer_object *bo); +void ttm_bo_del_from_lru(struct ttm_buffer_object *bo); /** * ttm_bo_move_to_lru_tail @@ -367,7 +365,7 @@ extern void ttm_bo_del_from_lru(struct ttm_buffer_object *bo); * object. This function must be called with struct ttm_bo_global::lru_lock * held, and is used to make a BO less likely to be considered for eviction. */ -extern void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo); +void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo); /** * ttm_bo_lock_delayed_workqueue @@ -376,15 +374,14 @@ extern void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo); * Returns * True if the workqueue was queued at the time */ -extern int ttm_bo_lock_delayed_workqueue(struct ttm_bo_device *bdev); +int ttm_bo_lock_delayed_workqueue(struct ttm_bo_device *bdev); /** * ttm_bo_unlock_delayed_workqueue * * Allows the delayed workqueue to run. */ -extern void ttm_bo_unlock_delayed_workqueue(struct ttm_bo_device *bdev, - int resched); +void ttm_bo_unlock_delayed_workqueue(struct ttm_bo_device *bdev, int resched); /** * ttm_bo_eviction_valuable @@ -411,8 +408,7 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, * -EBUSY if the buffer is busy and no_wait is true. * -ERESTARTSYS if interrupted by a signal. */ -extern int -ttm_bo_synccpu_write_grab(struct ttm_buffer_object *bo, bool no_wait); +int ttm_bo_synccpu_write_grab(struct ttm_buffer_object *bo, bool no_wait); /** * ttm_bo_synccpu_write_release: @@ -421,7 +417,7 @@ ttm_bo_synccpu_write_grab(struct ttm_buffer_object *bo, bool no_wait); * * Releases a synccpu lock. */ -extern void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo); +void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo); /** * ttm_bo_acc_size @@ -480,18 +476,18 @@ size_t ttm_bo_dma_acc_size(struct ttm_bo_device *bdev, * -ERESTARTSYS: Interrupted by signal while sleeping waiting for resources. */ -extern int ttm_bo_init_reserved(struct ttm_bo_device *bdev, - struct ttm_buffer_object *bo, - unsigned long size, - enum ttm_bo_type type, - struct ttm_placement *placement, - uint32_t page_alignment, - bool interrubtible, - struct file *persistent_swap_storage, - size_t acc_size, - struct sg_table *sg, - struct reservation_object *resv, - void (*destroy) (struct ttm_buffer_object *)); +int ttm_bo_init_reserved(struct ttm_bo_device *bdev, + struct ttm_buffer_object *bo, + unsigned long size, + enum ttm_bo_type type, + struct ttm_placement *placement, + uint32_t page_alignment, + bool interrubtible, + struct file *persistent_swap_storage, + size_t acc_size, + struct sg_table *sg, + struct reservation_object *resv, + void (*destroy) (struct ttm_buffer_object *)); /** * ttm_bo_init @@ -531,19 +527,13 @@ extern int ttm_bo_init_reserved(struct ttm_bo_device *bdev, * -EINVAL: Invalid placement flags. * -ERESTARTSYS: Interrupted by signal while sleeping waiting for resources. */ - -extern int ttm_bo_init(struct ttm_bo_device *bdev, - struct ttm_buffer_object *bo, - unsigned long size, - enum ttm_bo_type type, - struct ttm_placement *placement, - uint32_t page_alignment, - bool interrubtible, - struct file *persistent_swap_storage, - size_t acc_size, - struct sg_table *sg, - struct reservation_object *resv, - void (*destroy) (struct ttm_buffer_object *)); +int ttm_bo_init(struct ttm_bo_device *bdev, struct ttm_buffer_object *bo, + unsigned long size, enum ttm_bo_type type, + struct ttm_placement *placement, + uint32_t page_alignment, bool interrubtible, + struct file *persistent_swap_storage, size_t acc_size, + struct sg_table *sg, struct reservation_object *resv, + void (*destroy) (struct ttm_buffer_object *)); /** * ttm_bo_create @@ -569,15 +559,11 @@ extern int ttm_bo_init(struct ttm_bo_device *bdev, * -EINVAL: Invalid placement flags. * -ERESTARTSYS: Interrupted by signal while waiting for resources. */ - -extern int ttm_bo_create(struct ttm_bo_device *bdev, - unsigned long size, - enum ttm_bo_type type, - struct ttm_placement *placement, - uint32_t page_alignment, - bool interruptible, - struct file *persistent_swap_storage, - struct ttm_buffer_object **p_bo); +int ttm_bo_create(struct ttm_bo_device *bdev, unsigned long size, + enum ttm_bo_type type, struct ttm_placement *placement, + uint32_t page_alignment, bool interruptible, + struct file *persistent_swap_storage, + struct ttm_buffer_object **p_bo); /** * ttm_bo_init_mm @@ -594,9 +580,9 @@ extern int ttm_bo_create(struct ttm_bo_device *bdev, * -ENOMEM: Not enough memory. * May also return driver-specified errors. */ +int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type, + unsigned long p_size); -extern int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type, - unsigned long p_size); /** * ttm_bo_clean_mm * @@ -623,8 +609,7 @@ extern int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type, * -EINVAL: invalid or uninitialized memory type. * -EBUSY: There are still buffers left in this memory type. */ - -extern int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type); +int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type); /** * ttm_bo_evict_mm @@ -644,8 +629,7 @@ extern int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type); * -ERESTARTSYS: The call was interrupted by a signal while waiting to * evict a buffer. */ - -extern int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type); +int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type); /** * ttm_kmap_obj_virtual @@ -658,7 +642,6 @@ extern int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type); * If *is_iomem is 1 on return, the virtual address points to an io memory area, * that should strictly be accessed by the iowriteXX() and similar functions. */ - static inline void *ttm_kmap_obj_virtual(struct ttm_bo_kmap_obj *map, bool *is_iomem) { @@ -682,9 +665,8 @@ static inline void *ttm_kmap_obj_virtual(struct ttm_bo_kmap_obj *map, * -ENOMEM: Out of memory. * -EINVAL: Invalid range. */ - -extern int ttm_bo_kmap(struct ttm_buffer_object *bo, unsigned long start_page, - unsigned long num_pages, struct ttm_bo_kmap_obj *map); +int ttm_bo_kmap(struct ttm_buffer_object *bo, unsigned long start_page, + unsigned long num_pages, struct ttm_bo_kmap_obj *map); /** * ttm_bo_kunmap @@ -693,8 +675,7 @@ extern int ttm_bo_kmap(struct ttm_buffer_object *bo, unsigned long start_page, * * Unmaps a kernel map set up by ttm_bo_kmap. */ - -extern void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map); +void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map); /** * ttm_fbdev_mmap - mmap fbdev memory backed by a ttm buffer object. @@ -706,9 +687,7 @@ extern void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map); * This function is intended to be called by the fbdev mmap method * if the fbdev address space is to be backed by a bo. */ - -extern int ttm_fbdev_mmap(struct vm_area_struct *vma, - struct ttm_buffer_object *bo); +int ttm_fbdev_mmap(struct vm_area_struct *vma, struct ttm_buffer_object *bo); /** * ttm_bo_default_iomem_pfn - get a pfn for a page offset @@ -731,9 +710,8 @@ unsigned long ttm_bo_default_io_mem_pfn(struct ttm_buffer_object *bo, * This function is intended to be called by the device mmap method. * if the device address space is to be backed by the bo manager. */ - -extern int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma, - struct ttm_bo_device *bdev); +int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma, + struct ttm_bo_device *bdev); /** * ttm_bo_io @@ -755,11 +733,10 @@ extern int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma, * the function may return -ERESTARTSYS if * interrupted by a signal. */ +ssize_t ttm_bo_io(struct ttm_bo_device *bdev, struct file *filp, + const char __user *wbuf, char __user *rbuf, + size_t count, loff_t *f_pos, bool write); -extern ssize_t ttm_bo_io(struct ttm_bo_device *bdev, struct file *filp, - const char __user *wbuf, char __user *rbuf, - size_t count, loff_t *f_pos, bool write); - -extern void ttm_bo_swapout_all(struct ttm_bo_device *bdev); -extern int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo); +void ttm_bo_swapout_all(struct ttm_bo_device *bdev); +int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo); #endif -- GitLab From 1144b63a162cef5a57b85108b608f2486b0410c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 12 Apr 2017 15:08:17 +0200 Subject: [PATCH 0866/2547] drm/ttm: cleanup ttm_bo_driver.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extern is the default for function declerations anyway. Signed-off-by: Christian König Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher --- include/drm/ttm/ttm_bo_driver.h | 114 +++++++++++++++----------------- 1 file changed, 54 insertions(+), 60 deletions(-) diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index cba1477aa983..a7c826a1e53f 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -627,12 +627,12 @@ ttm_flag_masked(uint32_t *old, uint32_t new, uint32_t mask) * Returns: * NULL: Out of memory. */ -extern int ttm_tt_init(struct ttm_tt *ttm, struct ttm_bo_device *bdev, - unsigned long size, uint32_t page_flags, - struct page *dummy_read_page); -extern int ttm_dma_tt_init(struct ttm_dma_tt *ttm_dma, struct ttm_bo_device *bdev, - unsigned long size, uint32_t page_flags, - struct page *dummy_read_page); +int ttm_tt_init(struct ttm_tt *ttm, struct ttm_bo_device *bdev, + unsigned long size, uint32_t page_flags, + struct page *dummy_read_page); +int ttm_dma_tt_init(struct ttm_dma_tt *ttm_dma, struct ttm_bo_device *bdev, + unsigned long size, uint32_t page_flags, + struct page *dummy_read_page); /** * ttm_tt_fini @@ -641,8 +641,8 @@ extern int ttm_dma_tt_init(struct ttm_dma_tt *ttm_dma, struct ttm_bo_device *bde * * Free memory of ttm_tt structure */ -extern void ttm_tt_fini(struct ttm_tt *ttm); -extern void ttm_dma_tt_fini(struct ttm_dma_tt *ttm_dma); +void ttm_tt_fini(struct ttm_tt *ttm); +void ttm_dma_tt_fini(struct ttm_dma_tt *ttm_dma); /** * ttm_ttm_bind: @@ -652,7 +652,7 @@ extern void ttm_dma_tt_fini(struct ttm_dma_tt *ttm_dma); * * Bind the pages of @ttm to an aperture location identified by @bo_mem */ -extern int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem); +int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem); /** * ttm_ttm_destroy: @@ -661,7 +661,7 @@ extern int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem); * * Unbind, unpopulate and destroy common struct ttm_tt. */ -extern void ttm_tt_destroy(struct ttm_tt *ttm); +void ttm_tt_destroy(struct ttm_tt *ttm); /** * ttm_ttm_unbind: @@ -670,7 +670,7 @@ extern void ttm_tt_destroy(struct ttm_tt *ttm); * * Unbind a struct ttm_tt. */ -extern void ttm_tt_unbind(struct ttm_tt *ttm); +void ttm_tt_unbind(struct ttm_tt *ttm); /** * ttm_tt_swapin: @@ -679,7 +679,7 @@ extern void ttm_tt_unbind(struct ttm_tt *ttm); * * Swap in a previously swap out ttm_tt. */ -extern int ttm_tt_swapin(struct ttm_tt *ttm); +int ttm_tt_swapin(struct ttm_tt *ttm); /** * ttm_tt_set_placement_caching: @@ -694,9 +694,8 @@ extern int ttm_tt_swapin(struct ttm_tt *ttm); * hit RAM. This function may be very costly as it involves global TLB * and cache flushes and potential page splitting / combining. */ -extern int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement); -extern int ttm_tt_swapout(struct ttm_tt *ttm, - struct file *persistent_swap_storage); +int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement); +int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage); /** * ttm_tt_unpopulate - free pages from a ttm @@ -705,7 +704,7 @@ extern int ttm_tt_swapout(struct ttm_tt *ttm, * * Calls the driver method to free all pages from a ttm */ -extern void ttm_tt_unpopulate(struct ttm_tt *ttm); +void ttm_tt_unpopulate(struct ttm_tt *ttm); /* * ttm_bo.c @@ -720,8 +719,7 @@ extern void ttm_tt_unpopulate(struct ttm_tt *ttm); * Returns true if the memory described by @mem is PCI memory, * false otherwise. */ -extern bool ttm_mem_reg_is_pci(struct ttm_bo_device *bdev, - struct ttm_mem_reg *mem); +bool ttm_mem_reg_is_pci(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem); /** * ttm_bo_mem_space @@ -742,21 +740,20 @@ extern bool ttm_mem_reg_is_pci(struct ttm_bo_device *bdev, * fragmentation or concurrent allocators. * -ERESTARTSYS: An interruptible sleep was interrupted by a signal. */ -extern int ttm_bo_mem_space(struct ttm_buffer_object *bo, - struct ttm_placement *placement, - struct ttm_mem_reg *mem, - bool interruptible, - bool no_wait_gpu); - -extern void ttm_bo_mem_put(struct ttm_buffer_object *bo, +int ttm_bo_mem_space(struct ttm_buffer_object *bo, + struct ttm_placement *placement, + struct ttm_mem_reg *mem, + bool interruptible, + bool no_wait_gpu); + +void ttm_bo_mem_put(struct ttm_buffer_object *bo, struct ttm_mem_reg *mem); +void ttm_bo_mem_put_locked(struct ttm_buffer_object *bo, struct ttm_mem_reg *mem); -extern void ttm_bo_mem_put_locked(struct ttm_buffer_object *bo, - struct ttm_mem_reg *mem); -extern void ttm_bo_global_release(struct drm_global_reference *ref); -extern int ttm_bo_global_init(struct drm_global_reference *ref); +void ttm_bo_global_release(struct drm_global_reference *ref); +int ttm_bo_global_init(struct drm_global_reference *ref); -extern int ttm_bo_device_release(struct ttm_bo_device *bdev); +int ttm_bo_device_release(struct ttm_bo_device *bdev); /** * ttm_bo_device_init @@ -773,18 +770,17 @@ extern int ttm_bo_device_release(struct ttm_bo_device *bdev); * Returns: * !0: Failure. */ -extern int ttm_bo_device_init(struct ttm_bo_device *bdev, - struct ttm_bo_global *glob, - struct ttm_bo_driver *driver, - struct address_space *mapping, - uint64_t file_page_offset, bool need_dma32); +int ttm_bo_device_init(struct ttm_bo_device *bdev, struct ttm_bo_global *glob, + struct ttm_bo_driver *driver, + struct address_space *mapping, + uint64_t file_page_offset, bool need_dma32); /** * ttm_bo_unmap_virtual * * @bo: tear down the virtual mappings for this BO */ -extern void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo); +void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo); /** * ttm_bo_unmap_virtual @@ -793,16 +789,15 @@ extern void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo); * * The caller must take ttm_mem_io_lock before calling this function. */ -extern void ttm_bo_unmap_virtual_locked(struct ttm_buffer_object *bo); +void ttm_bo_unmap_virtual_locked(struct ttm_buffer_object *bo); -extern int ttm_mem_io_reserve_vm(struct ttm_buffer_object *bo); -extern void ttm_mem_io_free_vm(struct ttm_buffer_object *bo); -extern int ttm_mem_io_lock(struct ttm_mem_type_manager *man, - bool interruptible); -extern void ttm_mem_io_unlock(struct ttm_mem_type_manager *man); +int ttm_mem_io_reserve_vm(struct ttm_buffer_object *bo); +void ttm_mem_io_free_vm(struct ttm_buffer_object *bo); +int ttm_mem_io_lock(struct ttm_mem_type_manager *man, bool interruptible); +void ttm_mem_io_unlock(struct ttm_mem_type_manager *man); -extern void ttm_bo_del_sub_from_lru(struct ttm_buffer_object *bo); -extern void ttm_bo_add_to_lru(struct ttm_buffer_object *bo); +void ttm_bo_del_sub_from_lru(struct ttm_buffer_object *bo); +void ttm_bo_add_to_lru(struct ttm_buffer_object *bo); /** * __ttm_bo_reserve: @@ -983,9 +978,9 @@ void ttm_mem_io_free(struct ttm_bo_device *bdev, * !0: Failure. */ -extern int ttm_bo_move_ttm(struct ttm_buffer_object *bo, - bool interruptible, bool no_wait_gpu, - struct ttm_mem_reg *new_mem); +int ttm_bo_move_ttm(struct ttm_buffer_object *bo, + bool interruptible, bool no_wait_gpu, + struct ttm_mem_reg *new_mem); /** * ttm_bo_move_memcpy @@ -1005,9 +1000,9 @@ extern int ttm_bo_move_ttm(struct ttm_buffer_object *bo, * !0: Failure. */ -extern int ttm_bo_move_memcpy(struct ttm_buffer_object *bo, - bool interruptible, bool no_wait_gpu, - struct ttm_mem_reg *new_mem); +int ttm_bo_move_memcpy(struct ttm_buffer_object *bo, + bool interruptible, bool no_wait_gpu, + struct ttm_mem_reg *new_mem); /** * ttm_bo_free_old_node @@ -1016,7 +1011,7 @@ extern int ttm_bo_move_memcpy(struct ttm_buffer_object *bo, * * Utility function to free an old placement after a successful move. */ -extern void ttm_bo_free_old_node(struct ttm_buffer_object *bo); +void ttm_bo_free_old_node(struct ttm_buffer_object *bo); /** * ttm_bo_move_accel_cleanup. @@ -1033,10 +1028,9 @@ extern void ttm_bo_free_old_node(struct ttm_buffer_object *bo); * destroyed when the move is complete. This will help pipeline * buffer moves. */ - -extern int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo, - struct dma_fence *fence, bool evict, - struct ttm_mem_reg *new_mem); +int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo, + struct dma_fence *fence, bool evict, + struct ttm_mem_reg *new_mem); /** * ttm_bo_pipeline_move. @@ -1062,7 +1056,7 @@ int ttm_bo_pipeline_move(struct ttm_buffer_object *bo, * Utility function that returns the pgprot_t that should be used for * setting up a PTE with the caching model indicated by @c_state. */ -extern pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp); +pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp); extern const struct ttm_mem_type_manager_func ttm_bo_manager_func; @@ -1083,10 +1077,10 @@ extern const struct ttm_mem_type_manager_func ttm_bo_manager_func; * for TT memory. This function uses the linux agpgart interface to * bind and unbind memory backing a ttm_tt. */ -extern struct ttm_tt *ttm_agp_tt_create(struct ttm_bo_device *bdev, - struct agp_bridge_data *bridge, - unsigned long size, uint32_t page_flags, - struct page *dummy_read_page); +struct ttm_tt *ttm_agp_tt_create(struct ttm_bo_device *bdev, + struct agp_bridge_data *bridge, + unsigned long size, uint32_t page_flags, + struct page *dummy_read_page); int ttm_agp_tt_populate(struct ttm_tt *ttm); void ttm_agp_tt_unpopulate(struct ttm_tt *ttm); #endif -- GitLab From 01f83e0663a5e731dd59549b5cd13dc1e7a726a6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 27 Apr 2017 17:38:54 +0200 Subject: [PATCH 0867/2547] drm/ttm: remove cur_placement MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not used any more. Signed-off-by: Christian König Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 5 ++--- include/drm/ttm/ttm_bo_api.h | 1 - 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index e79c927e0075..77a0fd22e5ba 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -355,11 +355,10 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, bo->evicted = false; } - if (bo->mem.mm_node) { + if (bo->mem.mm_node) bo->offset = (bo->mem.start << PAGE_SHIFT) + bdev->man[bo->mem.mem_type].gpu_offset; - bo->cur_placement = bo->mem.placement; - } else + else bo->offset = 0; return 0; diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index 29df3a472bcf..833c3ad24091 100644 --- a/include/drm/ttm/ttm_bo_api.h +++ b/include/drm/ttm/ttm_bo_api.h @@ -224,7 +224,6 @@ struct ttm_buffer_object { */ uint64_t offset; /* GPU address space is independent of CPU word size */ - uint32_t cur_placement; struct sg_table *sg; -- GitLab From e778c1319b627e1aabd7aa00757eb50f593fbfa3 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Wed, 15 Nov 2017 15:45:09 +0000 Subject: [PATCH 0868/2547] drm/amd/display: remove unnecessary cast and use kcalloc instead of kzalloc Use kcalloc instead of kzalloc and the cast on the return from kzalloc is unnecessary and can be removed. Reviewed-by: Alex Deucher Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/basics/logger.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c index e04e8ecd4874..2ff5b467603d 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c @@ -70,9 +70,8 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger, { /* malloc buffer and init offsets */ logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE; - logger->log_buffer = (char *)kzalloc(logger->log_buffer_size * sizeof(char), - GFP_KERNEL); - + logger->log_buffer = kcalloc(logger->log_buffer_size, sizeof(char), + GFP_KERNEL); if (!logger->log_buffer) return false; -- GitLab From b3cce465750a46deeeb1ed64c6f7f56ffb1cd6bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 16 Nov 2017 18:29:51 +0100 Subject: [PATCH 0869/2547] drm/amdgpu: always make gart.table_addr 64bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixing warning/compile errors on 32bit kernels. Signed-off-by: Christian König Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h index f15e319580ec..5eb1a6800f72 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h @@ -39,7 +39,7 @@ struct amdgpu_gart_funcs; #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) struct amdgpu_gart { - dma_addr_t table_addr; + u64 table_addr; struct amdgpu_bo *robj; void *ptr; unsigned num_gpu_pages; -- GitLab From 5a16008f5353e0515ab2d317f1239d2c98f116e3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 17 Nov 2017 11:40:58 -0500 Subject: [PATCH 0870/2547] drm/amdgpu/gmc9: make some ECC messages debug only MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To avoid spamming the logs on non-ECC boards. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 798f7fc2d4e9..8529005a5022 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -571,11 +571,11 @@ static int gmc_v9_0_ecc_available(struct amdgpu_device *adev) reg_val, field_val, fv2); if (!field_val) { - DRM_ERROR("ecc: WrEccEn is not set\n"); + DRM_DEBUG("ecc: WrEccEn is not set\n"); ++lost_sheep; } if (!fv2) { - DRM_ERROR("ecc: RdEccEn is not set\n"); + DRM_DEBUG("ecc: RdEccEn is not set\n"); ++lost_sheep; } } -- GitLab From 99676f20dc913672166ab3b22fe29c20a2c27a82 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Fri, 10 Nov 2017 16:38:13 -0600 Subject: [PATCH 0871/2547] drm/amd/display/dc/core/dc_resource: use swap macro in rect_swap_helper Make use of the swap macro instead of _manually_ swapping values and remove unnecessary variable temp. This makes the code easier to read and maintain. This code was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 15e518aba916..9c5e879f18b3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -426,15 +426,8 @@ static enum pixel_format convert_pixel_format_to_dalsurface( static void rect_swap_helper(struct rect *rect) { - uint32_t temp = 0; - - temp = rect->height; - rect->height = rect->width; - rect->width = temp; - - temp = rect->x; - rect->x = rect->y; - rect->y = temp; + swap(rect->height, rect->width); + swap(rect->x, rect->y); } static void calculate_viewport(struct pipe_ctx *pipe_ctx) -- GitLab From 8aa111e34deedded58cd8576755f31659ba676f5 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Fri, 10 Nov 2017 16:31:09 -0600 Subject: [PATCH 0872/2547] drm/amd/display/dc/dce110/dce110_mem_input_v: use swap macro in program_size_and_rotation Make use of the swap macro instead of _manually_ swapping values and remove unnecessary variable swap. This makes the code easier to read and maintain. This code was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva Signed-off-by: Alex Deucher --- .../display/dc/dce110/dce110_mem_input_v.c | 28 ++++++------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index a06c6024deb4..7bab8c6d2a73 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -237,26 +237,14 @@ static void program_size_and_rotation( if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) { - uint32_t swap; - swap = local_size.video.luma_size.x; - local_size.video.luma_size.x = - local_size.video.luma_size.y; - local_size.video.luma_size.y = swap; - - swap = local_size.video.luma_size.width; - local_size.video.luma_size.width = - local_size.video.luma_size.height; - local_size.video.luma_size.height = swap; - - swap = local_size.video.chroma_size.x; - local_size.video.chroma_size.x = - local_size.video.chroma_size.y; - local_size.video.chroma_size.y = swap; - - swap = local_size.video.chroma_size.width; - local_size.video.chroma_size.width = - local_size.video.chroma_size.height; - local_size.video.chroma_size.height = swap; + swap(local_size.video.luma_size.x, + local_size.video.luma_size.y); + swap(local_size.video.luma_size.width, + local_size.video.luma_size.height); + swap(local_size.video.chroma_size.x, + local_size.video.chroma_size.y); + swap(local_size.video.chroma_size.width, + local_size.video.chroma_size.height); } value = 0; -- GitLab From 4f42a2dd3d7ef106e6bd3e2ad61c55333150d896 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Thu, 16 Nov 2017 07:27:27 -0800 Subject: [PATCH 0873/2547] drm: amd: Fix line continuation formats Line continuations with excess spacing causes unexpected output. Miscellanea: o Added missing '\n' to a few of the coalesced pr_ formats Reviewed-by: Harry Wentland Signed-off-by: Joe Perches Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 11 +++----- .../powerplay/hwmgr/process_pptables_v1_0.c | 6 ++--- .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 27 +++++++------------ .../gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 6 ++--- .../drm/amd/powerplay/smumgr/iceland_smumgr.c | 9 +++---- .../drm/amd/powerplay/smumgr/vega10_smumgr.c | 6 ++--- 6 files changed, 22 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index b2dcc462afe2..00528b214a9f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -220,8 +220,7 @@ static void dpcd_set_lt_pattern_and_lane_settings( size_in_bytes); dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING, - "%s:\n %x VS set = %x PE set = %x \ - max VS Reached = %x max PE Reached = %x\n", + "%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", __func__, DP_TRAINING_LANE0_SET, dpcd_lane[0].bits.VOLTAGE_SWING_SET, @@ -558,8 +557,7 @@ static void dpcd_set_lane_settings( */ dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING, - "%s\n %x VS set = %x PE set = %x \ - max VS Reached = %x max PE Reached = %x\n", + "%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", __func__, DP_TRAINING_LANE0_SET, dpcd_lane[0].bits.VOLTAGE_SWING_SET, @@ -872,9 +870,8 @@ static bool perform_clock_recovery_sequence( if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) { ASSERT(0); dm_logger_write(link->ctx->logger, LOG_ERROR, - "%s: Link Training Error, could not \ - get CR after %d tries. \ - Possibly voltage swing issue", __func__, + "%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue", + __func__, LINK_TRAINING_MAX_CR_RETRY); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c index a651ebcf44fd..b49d65c3e984 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c @@ -523,8 +523,7 @@ static int get_pcie_table( if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; else - pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ - Disregarding the excess entries... \n"); + pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n"); pcie_table->count = pcie_count; for (i = 0; i < pcie_count; i++) { @@ -563,8 +562,7 @@ static int get_pcie_table( if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; else - pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ - Disregarding the excess entries... \n"); + pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n"); pcie_table->count = pcie_count; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 9d4955e33b25..07d256d136ad 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -546,8 +546,7 @@ static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, } if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) - pr_info("Voltage value looks like a Leakage ID \ - but it's not patched\n"); + pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); } /** @@ -701,18 +700,14 @@ static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) table_info->vdd_dep_on_mclk; PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table, - "VDD dependency on SCLK table is missing. \ - This table is mandatory", return -EINVAL); + "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL); PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, - "VDD dependency on SCLK table is empty. \ - This table is mandatory", return -EINVAL); + "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL); PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, - "VDD dependency on MCLK table is missing. \ - This table is mandatory", return -EINVAL); + "VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL); PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, - "VDD dependency on MCLK table is empty. \ - This table is mandatory", return -EINVAL); + "VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL); table_info->max_clock_voltage_on_ac.sclk = allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; @@ -3416,8 +3411,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( DPMTABLE_OD_UPDATE_SCLK)) { result = vega10_populate_all_graphic_levels(hwmgr); PP_ASSERT_WITH_CODE(!result, - "Failed to populate SCLK during \ - PopulateNewDPMClocksStates Function!", + "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", return result); } @@ -3426,8 +3420,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( DPMTABLE_OD_UPDATE_MCLK)){ result = vega10_populate_all_memory_levels(hwmgr); PP_ASSERT_WITH_CODE(!result, - "Failed to populate MCLK during \ - PopulateNewDPMClocksStates Function!", + "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", return result); } } else { @@ -3544,8 +3537,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( data->apply_optimized_settings) { result = vega10_populate_all_graphic_levels(hwmgr); PP_ASSERT_WITH_CODE(!result, - "Failed to populate SCLK during \ - PopulateNewDPMClocksStates Function!", + "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", return result); } @@ -3553,8 +3545,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { result = vega10_populate_all_memory_levels(hwmgr); PP_ASSERT_WITH_CODE(!result, - "Failed to populate MCLK during \ - PopulateNewDPMClocksStates Function!", + "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", return result); } } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c index 4d672cd15785..ed4b37e566a3 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c @@ -1732,8 +1732,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, if (0 != result) { smu_data->smc_state_table.GraphicsBootLevel = 0; - pr_err("VBIOS did not find boot engine clock value \ - in dependency table. Using Graphics DPM level 0!"); + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n"); result = 0; } @@ -1743,8 +1742,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, if (0 != result) { smu_data->smc_state_table.MemoryBootLevel = 0; - pr_err("VBIOS did not find boot engine clock value \ - in dependency table. Using Memory DPM level 0!"); + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n"); result = 0; } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c index 34128822b8fb..2ff682d44e8c 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c @@ -911,8 +911,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, &graphic_level->MinVddc); PP_ASSERT_WITH_CODE((0 == result), - "can not find VDDC voltage value for VDDC \ - engine clock dependency table", return result); + "can not find VDDC voltage value for VDDC engine clock dependency table", return result); /* SCLK frequency in units of 10KHz*/ graphic_level->SclkFrequency = engine_clock; @@ -1678,8 +1677,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, if (0 != result) { smu_data->smc_state_table.GraphicsBootLevel = 0; - pr_err("VBIOS did not find boot engine clock value \ - in dependency table. Using Graphics DPM level 0!"); + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n"); result = 0; } @@ -1689,8 +1687,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, if (0 != result) { smu_data->smc_state_table.MemoryBootLevel = 0; - pr_err("VBIOS did not find boot engine clock value \ - in dependency table. Using Memory DPM level 0!"); + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n"); result = 0; } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c index 2f979fb86824..f6f39d01d227 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c @@ -381,10 +381,8 @@ static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr) (rev_id == 0xc1) || (rev_id == 0xc3)))) { if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) { - pr_err("Your firmware(0x%x) doesn't match \ - SMU9_DRIVER_IF_VERSION(0x%x). \ - Please update your firmware!\n", - smc_driver_if_version, SMU9_DRIVER_IF_VERSION); + pr_err("Your firmware(0x%x) doesn't match SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware!\n", + smc_driver_if_version, SMU9_DRIVER_IF_VERSION); return -EINVAL; } } -- GitLab From 3d647c8f930190f728c997c3ac3d987f992420ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 16 Nov 2017 19:36:10 +0100 Subject: [PATCH 0874/2547] drm/amdgpu: remove VRAM size reduction v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove some outdated comments and all code which tries to reduce the VRAM size mapped into the MC. This is superfluous and misleading since we never actually program the size. v2: handle gmc_v6_0.c as well Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 30 +--------------------- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 5 ---- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 6 ----- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 ----- 4 files changed, 1 insertion(+), 46 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 4e668b70371e..a81743d06bb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -578,41 +578,13 @@ void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) * @base: base address at which to put VRAM * * Function will try to place VRAM at base address provided - * as parameter (which is so far either PCI aperture address or - * for IGP TOM base address). - * - * If there is not enough space to fit the unvisible VRAM in the 32bits - * address space then we limit the VRAM size to the aperture. - * - * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, - * this shouldn't be a problem as we are using the PCI aperture as a reference. - * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but - * not IGP. - * - * Note: we use mc_vram_size as on some board we need to program the mc to - * cover the whole aperture even if VRAM size is inferior to aperture size - * Novell bug 204882 + along with lots of ubuntu ones - * - * Note: when limiting vram it's safe to overwritte real_vram_size because - * we are not in case where real_vram_size is inferior to mc_vram_size (ie - * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu - * ones) - * - * Note: IGP TOM addr should be the same as the aperture addr, we don't - * explicitly check for that though. - * - * FIXME: when reducing VRAM size align new size on power of 2. + * as parameter. */ void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) { uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; mc->vram_start = base; - if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { - dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); - mc->real_vram_size = mc->aper_size; - mc->mc_vram_size = mc->aper_size; - } mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; if (limit && limit < mc->real_vram_size) mc->real_vram_size = limit; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 9c672ece9f18..1e7f52f109b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -222,11 +222,6 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - if (mc->mc_vram_size > 0xFFC0000000ULL) { - dev_warn(adev->dev, "limiting VRAM\n"); - mc->real_vram_size = 0xFFC0000000ULL; - mc->mc_vram_size = 0xFFC0000000ULL; - } amdgpu_vram_location(adev, &adev->mc, base); amdgpu_gart_location(adev, mc); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index de7a249f0e24..d521862804ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -240,12 +240,6 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - if (mc->mc_vram_size > 0xFFC0000000ULL) { - /* leave room for at least 1024M GTT */ - dev_warn(adev->dev, "limiting VRAM\n"); - mc->real_vram_size = 0xFFC0000000ULL; - mc->mc_vram_size = 0xFFC0000000ULL; - } amdgpu_vram_location(adev, &adev->mc, base); amdgpu_gart_location(adev, mc); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 67778744da5a..bd3f842cca00 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -405,12 +405,6 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - if (mc->mc_vram_size > 0xFFC0000000ULL) { - /* leave room for at least 1024M GTT */ - dev_warn(adev->dev, "limiting VRAM\n"); - mc->real_vram_size = 0xFFC0000000ULL; - mc->mc_vram_size = 0xFFC0000000ULL; - } amdgpu_vram_location(adev, &adev->mc, base); amdgpu_gart_location(adev, mc); } -- GitLab From b98f1b9e5e71b636036cc6c0e1a3b428acd216cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 16 Nov 2017 20:12:51 +0100 Subject: [PATCH 0875/2547] drm/amdgpu: align GTT start to 4GB v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For VCE to work properly the start of the GTT space must be aligned to a 4GB boundary. v2: add comment why we do this Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a81743d06bb0..a43d096ebb52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -622,7 +622,10 @@ void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) dev_warn(adev->dev, "limiting GTT\n"); mc->gart_size = size_af; } - mc->gart_start = mc->vram_end + 1; + /* VCE doesn't like it when BOs cross a 4GB segment, so align + * the GART base on a 4GB boundary as well. + */ + mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL); } mc->gart_end = mc->gart_start + mc->gart_size - 1; dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", -- GitLab From 235943189db8ce05b888f48a04ded4448eebc408 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 17 Nov 2017 11:09:43 +0100 Subject: [PATCH 0876/2547] drm/amdgpu: fix VCE buffer placement restrictions v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Turned out that VCE still has a placement restriction that BOs can't cross a 4GB boundary. Fix this by adding a command submission parser prepass to correctly place the buffers. v2: add function description Signed-off-by: Christian König Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 101 +++++++++++++++++++++++- 1 file changed, 99 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 92477e67087c..a91abfb32746 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -543,6 +543,54 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, return r; } +/** + * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary + * + * @p: parser context + * @lo: address of lower dword + * @hi: address of higher dword + * @size: minimum size + * @index: bs/fb index + * + * Make sure that no BO cross a 4GB boundary. + */ +static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx, + int lo, int hi, unsigned size, int32_t index) +{ + int64_t offset = ((uint64_t)size) * ((int64_t)index); + struct amdgpu_bo_va_mapping *mapping; + unsigned i, fpfn, lpfn; + struct amdgpu_bo *bo; + uint64_t addr; + int r; + + addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) | + ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32; + if (index >= 0) { + addr += offset; + fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT; + lpfn = 0x100000000ULL >> PAGE_SHIFT; + } else { + fpfn = 0; + lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT; + } + + r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping); + if (r) { + DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n", + addr, lo, hi, size, index); + return r; + } + + for (i = 0; i < bo->placement.num_placement; ++i) { + bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn); + bo->placements[i].lpfn = bo->placements[i].fpfn ? + min(bo->placements[i].fpfn, lpfn) : lpfn; + } + return ttm_bo_validate(&bo->tbo, &bo->placement, false, false); +} + + /** * amdgpu_vce_cs_reloc - command submission relocation * @@ -648,12 +696,13 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx) uint32_t allocated = 0; uint32_t tmp, handle = 0; uint32_t *size = &tmp; - int i, r = 0, idx = 0; + unsigned idx; + int i, r = 0; p->job->vm = NULL; ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); - while (idx < ib->length_dw) { + for (idx = 0; idx < ib->length_dw;) { uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx); uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1); @@ -663,6 +712,54 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx) goto out; } + switch (cmd) { + case 0x00000002: /* task info */ + fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6); + bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7); + break; + + case 0x03000001: /* encode */ + r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10, + idx + 9, 0, 0); + if (r) + goto out; + + r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12, + idx + 11, 0, 0); + if (r) + goto out; + break; + + case 0x05000001: /* context buffer */ + r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, + idx + 2, 0, 0); + if (r) + goto out; + break; + + case 0x05000004: /* video bitstream buffer */ + tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4); + r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2, + tmp, bs_idx); + if (r) + goto out; + break; + + case 0x05000005: /* feedback buffer */ + r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2, + 4096, fb_idx); + if (r) + goto out; + break; + } + + idx += len / 4; + } + + for (idx = 0; idx < ib->length_dw;) { + uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx); + uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1); + switch (cmd) { case 0x00000001: /* session */ handle = amdgpu_get_ib_value(p, ib_idx, idx + 2); -- GitLab From 19fef71cd1f4928b958913bfee38662471f04faf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ernst=20Sj=C3=B6strand?= Date: Sun, 19 Nov 2017 18:52:42 +0100 Subject: [PATCH 0877/2547] drm/amd/powerplay: Minor fixes in processpptables.c (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reported by smatch: init_overdrive_limits() error: uninitialized symbol 'result'. get_clock_voltage_dependency_table() warn: inconsistent indenting v2: set result to 0 (Alex) Reviewed-by: Alex Deucher Signed-off-by: Ernst Sjöstrand Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c index afae32ee2b0d..c3e7e34535e8 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c @@ -394,8 +394,8 @@ static int get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr, dep_table->entries[i].clk = ((unsigned long)table->entries[i].ucClockHigh << 16) | le16_to_cpu(table->entries[i].usClockLow); - dep_table->entries[i].v = - (unsigned long)le16_to_cpu(table->entries[i].usVoltage); + dep_table->entries[i].v = + (unsigned long)le16_to_cpu(table->entries[i].usVoltage); } *ptable = dep_table; @@ -1042,7 +1042,7 @@ static int init_overdrive_limits_V2_1(struct pp_hwmgr *hwmgr, static int init_overdrive_limits(struct pp_hwmgr *hwmgr, const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) { - int result; + int result = 0; uint8_t frev, crev; uint16_t size; -- GitLab From e9c227b253712db75b0623fe1596fec8c8857807 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ernst=20Sj=C3=B6strand?= Date: Sun, 19 Nov 2017 18:52:43 +0100 Subject: [PATCH 0878/2547] drm/amd/powerplay: Fix missing newlines at end of file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Alex Deucher Signed-off-by: Ernst Sjöstrand Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 +- drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h | 2 +- drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index eab504ecca25..ed27626dff14 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -291,4 +291,4 @@ struct amd_pm_funcs { struct amd_pp_simple_clock_info *clocks); }; -#endif \ No newline at end of file +#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h index c6ba0d64cfb7..4112a9398163 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h @@ -43,4 +43,4 @@ struct phm_fuses_default { extern int pp_override_get_default_fuse_value(uint64_t key, struct phm_fuses_default *result); -#endif \ No newline at end of file +#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c index c062844b15f3..560c1c159fcc 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c @@ -542,4 +542,4 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, boot_values->ulDCEFClk = frequency; return 0; -} \ No newline at end of file +} -- GitLab From 7d0331007ab4bea446cf3d173410c3179b12e2ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ernst=20Sj=C3=B6strand?= Date: Sun, 19 Nov 2017 18:52:44 +0100 Subject: [PATCH 0879/2547] drm/amd/amdgpu: Fix missing null check in atombios_i2c.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reported by smatch: amdgpu_atombios_i2c_process_i2c_ch() error: we previously assumed 'buf' could be null Reviewed-by: Alex Deucher Signed-off-by: Ernst Sjöstrand Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/atombios_i2c.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c index b374653bd6cf..f9b2ce9a98f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c @@ -65,8 +65,15 @@ static int amdgpu_atombios_i2c_process_i2c_ch(struct amdgpu_i2c_chan *chan, args.ucRegIndex = buf[0]; if (num) num--; - if (num) - memcpy(&out, &buf[1], num); + if (num) { + if (buf) { + memcpy(&out, &buf[1], num); + } else { + DRM_ERROR("hw i2c: missing buf with num > 1\n"); + r = -EINVAL; + goto done; + } + } args.lpI2CDataOut = cpu_to_le16(out); } else { if (num > ATOM_MAX_HW_I2C_READ) { -- GitLab From 47e8788b4924b0e3348caf4ad08de5a162bfc4cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ernst=20Sj=C3=B6strand?= Date: Sun, 19 Nov 2017 18:52:45 +0100 Subject: [PATCH 0880/2547] drm/amd/powerplay: Fix buffer overflows with mc_reg_address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Smatch warned about the following lines: ci_set_mc_special_registers() error: buffer overflow 'table->mc_reg_address' 16 <= 16 tonga_set_mc_special_registers() error: buffer overflow 'table->mc_reg_address' 16 <= 16 Change the logic to check before access instead of after incrementing. It's fine if j reaches max after we're done. This allows the last entry of the array to be filled without an error message for example. Changed some whitespace to clarify grouping. Reviewed-by: Alex Deucher Signed-off-by: Ernst Sjöstrand Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 10 +++------- drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 10 +++------- 2 files changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index 5a60c161b0fc..f11c0aacf19f 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -4540,9 +4540,9 @@ static int ci_set_mc_special_registers(struct amdgpu_device *adev, ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); } j++; + if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) return -EINVAL; - temp_reg = RREG32(mmMC_PMG_CMD_MRS); table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; @@ -4553,10 +4553,10 @@ static int ci_set_mc_special_registers(struct amdgpu_device *adev, table->mc_reg_table_entry[k].mc_data[j] |= 0x100; } j++; - if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { + if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; for (k = 0; k < table->num_entries; k++) { @@ -4564,8 +4564,6 @@ static int ci_set_mc_special_registers(struct amdgpu_device *adev, (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; } j++; - if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; } break; case mmMC_SEQ_RESERVE_M: @@ -4577,8 +4575,6 @@ static int ci_set_mc_special_registers(struct amdgpu_device *adev, (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); } j++; - if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; break; default: break; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c index 0a8e48bff219..81b8790c0d22 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c @@ -3106,9 +3106,9 @@ static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); } j++; + PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), "Invalid VramInfo table.", return -EINVAL); - temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; @@ -3121,18 +3121,16 @@ static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, table->mc_reg_table_entry[k].mc_data[j] |= 0x100; } j++; - PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); if (!data->is_memory_gddr5) { + PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), + "Invalid VramInfo table.", return -EINVAL); table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; for (k = 0; k < table->num_entries; k++) table->mc_reg_table_entry[k].mc_data[j] = (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; j++; - PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); } break; @@ -3147,8 +3145,6 @@ static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); } j++; - PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); break; default: -- GitLab From 8cdbad98c52380bde20ea5753533640d2cdcc005 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ernst=20Sj=C3=B6strand?= Date: Sun, 19 Nov 2017 18:52:46 +0100 Subject: [PATCH 0881/2547] drm/amd/powerplay: Followup fixes to mc_reg_address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a followup to: drm/amd/powerplay: Fix buffer overflows with mc_reg_address Rework *_set_mc_special_registers for the other architectures to use the same logic as the first patch. This allows the last entry of the array to be filled without an error message for example. This doesn't fix any known problems, perhaps avoided by luck. Reviewed-by: Alex Deucher Signed-off-by: Ernst Sjöstrand Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/si_dpm.c | 10 +++------- drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 12 ++++-------- .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 12 ++++-------- 3 files changed, 11 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c index 51fd0c9a20a5..299cb3161b2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c @@ -5845,9 +5845,9 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev, ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); j++; + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) return -EINVAL; - temp_reg = RREG32(MC_PMG_CMD_MRS); table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; @@ -5859,18 +5859,16 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev, table->mc_reg_table_entry[k].mc_data[j] |= 0x100; } j++; - if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; for (k = 0; k < table->num_entries; k++) table->mc_reg_table_entry[k].mc_data[j] = (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; j++; - if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; } break; case MC_SEQ_RESERVE_M: @@ -5882,8 +5880,6 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev, (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); j++; - if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; break; default: break; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c index ed4b37e566a3..c36f00ef46f3 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c @@ -2600,9 +2600,9 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr, ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); } j++; + PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), "Invalid VramInfo table.", return -EINVAL); - temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; @@ -2615,10 +2615,10 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr, table->mc_reg_table_entry[k].mc_data[j] |= 0x100; } j++; - PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); - if (!data->is_memory_gddr5 && j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) { + if (!data->is_memory_gddr5) { + PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), + "Invalid VramInfo table.", return -EINVAL); table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; for (k = 0; k < table->num_entries; k++) { @@ -2626,8 +2626,6 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr, (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; } j++; - PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); } break; @@ -2642,8 +2640,6 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr, (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); } j++; - PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); break; default: diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c index 2ff682d44e8c..d62078681cae 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c @@ -2549,9 +2549,9 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr, ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); } j++; + PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), "Invalid VramInfo table.", return -EINVAL); - temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; @@ -2565,10 +2565,10 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr, } } j++; - PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); - if (!data->is_memory_gddr5 && j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE) { + if (!data->is_memory_gddr5) { + PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), + "Invalid VramInfo table.", return -EINVAL); table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; for (k = 0; k < table->num_entries; k++) { @@ -2576,8 +2576,6 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr, (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; } j++; - PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); } break; @@ -2592,8 +2590,6 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr, (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); } j++; - PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); break; default: -- GitLab From f991c0ec2b0dd773c7e0f3f31f4b06e763229381 Mon Sep 17 00:00:00 2001 From: Roger He Date: Tue, 21 Nov 2017 09:58:26 +0800 Subject: [PATCH 0882/2547] drm/ttm: use NUM_PAGES_TO_ALLOC always MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 8d7172e8381d..dca4d8322437 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -510,8 +510,7 @@ static int ttm_alloc_new_pages(struct list_head *pages, gfp_t gfp_flags, int r = 0; unsigned i, j, cpages; unsigned npages = 1 << order; - unsigned max_cpages = min(count, - (unsigned)(PAGE_SIZE/sizeof(struct page *))); + unsigned max_cpages = min(count, (unsigned)NUM_PAGES_TO_ALLOC); /* allocate array for page caching change */ caching_array = kmalloc(max_cpages*sizeof(struct page *), GFP_KERNEL); -- GitLab From 750a25037cac56afeb48ab807ce80fa2cd518b8d Mon Sep 17 00:00:00 2001 From: Roger He Date: Tue, 21 Nov 2017 09:37:52 +0800 Subject: [PATCH 0883/2547] drm/ttm: add page order in page pool MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit to indicate page order for each element in the pool Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 38 ++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index dca4d8322437..bf25ba25bfc6 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -81,6 +81,7 @@ struct ttm_page_pool { char *name; unsigned long nfrees; unsigned long nrefills; + unsigned int order; }; /** @@ -412,6 +413,7 @@ ttm_pool_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) struct ttm_page_pool *pool; int shrink_pages = sc->nr_to_scan; unsigned long freed = 0; + unsigned int nr_free_pool; if (!mutex_trylock(&lock)) return SHRINK_STOP; @@ -421,10 +423,15 @@ ttm_pool_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) unsigned nr_free = shrink_pages; if (shrink_pages == 0) break; + pool = &_manager->pools[(i + pool_offset)%NUM_POOLS]; /* OK to use static buffer since global mutex is held. */ - shrink_pages = ttm_page_pool_free(pool, nr_free, true); - freed += nr_free - shrink_pages; + nr_free_pool = (nr_free >> pool->order); + if (nr_free_pool == 0) + continue; + + shrink_pages = ttm_page_pool_free(pool, nr_free_pool, true); + freed += ((nr_free_pool - shrink_pages) << pool->order); } mutex_unlock(&lock); return freed; @@ -436,9 +443,12 @@ ttm_pool_shrink_count(struct shrinker *shrink, struct shrink_control *sc) { unsigned i; unsigned long count = 0; + struct ttm_page_pool *pool; - for (i = 0; i < NUM_POOLS; ++i) - count += _manager->pools[i].npages; + for (i = 0; i < NUM_POOLS; ++i) { + pool = &_manager->pools[i]; + count += (pool->npages << pool->order); + } return count; } @@ -936,7 +946,7 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, } static void ttm_page_pool_init_locked(struct ttm_page_pool *pool, gfp_t flags, - char *name) + char *name, unsigned int order) { spin_lock_init(&pool->lock); pool->fill_lock = false; @@ -944,11 +954,17 @@ static void ttm_page_pool_init_locked(struct ttm_page_pool *pool, gfp_t flags, pool->npages = pool->nfrees = 0; pool->gfp_flags = flags; pool->name = name; + pool->order = order; } int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages) { int ret; +#ifdef CONFIG_TRANSPARENT_HUGEPAGE + unsigned order = HPAGE_PMD_ORDER; +#else + unsigned order = 0; +#endif WARN_ON(_manager); @@ -956,23 +972,23 @@ int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages) _manager = kzalloc(sizeof(*_manager), GFP_KERNEL); - ttm_page_pool_init_locked(&_manager->wc_pool, GFP_HIGHUSER, "wc"); + ttm_page_pool_init_locked(&_manager->wc_pool, GFP_HIGHUSER, "wc", 0); - ttm_page_pool_init_locked(&_manager->uc_pool, GFP_HIGHUSER, "uc"); + ttm_page_pool_init_locked(&_manager->uc_pool, GFP_HIGHUSER, "uc", 0); ttm_page_pool_init_locked(&_manager->wc_pool_dma32, - GFP_USER | GFP_DMA32, "wc dma"); + GFP_USER | GFP_DMA32, "wc dma", 0); ttm_page_pool_init_locked(&_manager->uc_pool_dma32, - GFP_USER | GFP_DMA32, "uc dma"); + GFP_USER | GFP_DMA32, "uc dma", 0); ttm_page_pool_init_locked(&_manager->wc_pool_huge, GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP), - "wc huge"); + "wc huge", order); ttm_page_pool_init_locked(&_manager->uc_pool_huge, GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP) - , "uc huge"); + , "uc huge", order); _manager->options.max_size = max_pages; _manager->options.small = SMALL_ALLOCATION; -- GitLab From 19be5570107108fba772bc2e3a1eb22ec32fb021 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 12 Apr 2017 14:24:39 +0200 Subject: [PATCH 0884/2547] drm/ttm: add operation ctx to ttm_bo_validate v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Give moving a BO into place an operation context to work with. v2: rebased Signed-off-by: Christian König Reviewed-by: Michel Dänzer Reviewed-by: Chunming Zhou Tested-by: Dieter Nützel Tested-by: Michel Dänzer Acked-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 14 ++++++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 12 ++++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 ++- drivers/gpu/drm/ast/ast_ttm.c | 9 ++++++--- drivers/gpu/drm/bochs/bochs_mm.c | 6 ++++-- drivers/gpu/drm/cirrus/cirrus_ttm.c | 6 ++++-- drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c | 6 ++++-- drivers/gpu/drm/mgag200/mgag200_ttm.c | 9 ++++++--- drivers/gpu/drm/nouveau/nouveau_bo.c | 4 ++-- drivers/gpu/drm/qxl/qxl_ioctl.c | 4 ++-- drivers/gpu/drm/qxl/qxl_object.c | 6 ++++-- drivers/gpu/drm/qxl/qxl_release.c | 4 ++-- drivers/gpu/drm/radeon/radeon_gem.c | 3 ++- drivers/gpu/drm/radeon/radeon_mn.c | 3 ++- drivers/gpu/drm/radeon/radeon_object.c | 14 +++++++++----- drivers/gpu/drm/radeon/radeon_vm.c | 3 ++- drivers/gpu/drm/ttm/ttm_bo.c | 16 +++++++++------- drivers/gpu/drm/virtio/virtgpu_ioctl.c | 11 ++++++----- drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c | 3 ++- drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c | 21 +++++++++++++-------- drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 9 ++++----- drivers/gpu/drm/vmwgfx/vmwgfx_resource.c | 6 ++++-- drivers/gpu/drm/vmwgfx/vmwgfx_shader.c | 3 ++- include/drm/ttm/ttm_bo_api.h | 20 ++++++++++++++++---- 27 files changed, 131 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 743875ad4404..faab662ce680 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -343,6 +343,7 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, struct amdgpu_bo *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + struct ttm_operation_ctx ctx = { true, false }; u64 initial_bytes_moved, bytes_moved; uint32_t domain; int r; @@ -374,7 +375,7 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, retry: amdgpu_ttm_placement_from_domain(bo, domain); initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); bytes_moved = atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved; p->bytes_moved += bytes_moved; @@ -396,6 +397,7 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, struct amdgpu_bo *validated) { uint32_t domain = validated->allowed_domains; + struct ttm_operation_ctx ctx = { true, false }; int r; if (!p->evictable) @@ -437,7 +439,7 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, bo->tbo.mem.mem_type == TTM_PL_VRAM && bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT; initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); bytes_moved = atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved; p->bytes_moved += bytes_moved; @@ -476,6 +478,7 @@ static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo) static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, struct list_head *validated) { + struct ttm_operation_ctx ctx = { true, false }; struct amdgpu_bo_list_entry *lobj; int r; @@ -493,8 +496,7 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, lobj->user_pages) { amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, - false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) return r; amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, @@ -1575,6 +1577,7 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, struct amdgpu_bo_va_mapping **map) { struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; + struct ttm_operation_ctx ctx = { false, false }; struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va_mapping *mapping; int r; @@ -1595,8 +1598,7 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) { (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains); - r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, false, - false); + r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx); if (r) return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 3ad4cf0f22f8..c16579287aee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -282,6 +282,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { + struct ttm_operation_ctx ctx = { true, false }; struct amdgpu_device *adev = dev->dev_private; struct drm_amdgpu_gem_userptr *args = data; struct drm_gem_object *gobj; @@ -335,7 +336,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, goto free_pages; amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); amdgpu_bo_unreserve(bo); if (r) goto free_pages; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 3233d5988f66..c2419bc6b3df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -552,6 +552,7 @@ int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev, int amdgpu_bo_validate(struct amdgpu_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; uint32_t domain; int r; @@ -562,7 +563,7 @@ int amdgpu_bo_validate(struct amdgpu_bo *bo) retry: amdgpu_ttm_placement_from_domain(bo, domain); - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { domain = bo->allowed_domains; goto retry; @@ -673,6 +674,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + struct ttm_operation_ctx ctx = { false, false }; int r, i; if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) @@ -723,7 +725,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; } - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (unlikely(r)) { dev_err(adev->dev, "%p pin failed\n", bo); goto error; @@ -760,6 +762,7 @@ int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) int amdgpu_bo_unpin(struct amdgpu_bo *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + struct ttm_operation_ctx ctx = { false, false }; int r, i; if (!bo->pin_count) { @@ -773,7 +776,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo) bo->placements[i].lpfn = 0; bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; } - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (unlikely(r)) { dev_err(adev->dev, "%p validate failed for unpin\n", bo); goto error; @@ -945,6 +948,7 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); + struct ttm_operation_ctx ctx = { false, false }; struct amdgpu_bo *abo; unsigned long offset, size; int r; @@ -978,7 +982,7 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) abo->placement.num_busy_placement = 1; abo->placement.busy_placement = &abo->placements[1]; - r = ttm_bo_validate(bo, &abo->placement, false, false); + r = ttm_bo_validate(bo, &abo->placement, &ctx); if (unlikely(r != 0)) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index be607b2be4e9..2f2a9e17fdb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -408,6 +408,7 @@ static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) */ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) { + struct ttm_operation_ctx tctx = { false, false }; struct amdgpu_bo_va_mapping *mapping; struct amdgpu_bo *bo; uint32_t cmd; @@ -430,7 +431,7 @@ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) } amdgpu_uvd_force_into_uvd_segment(bo); - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); } return r; @@ -949,6 +950,7 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, bool direct, struct dma_fence **fence) { + struct ttm_operation_ctx ctx = { true, false }; struct ttm_validate_buffer tv; struct ww_acquire_ctx ticket; struct list_head head; @@ -975,7 +977,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, amdgpu_uvd_force_into_uvd_segment(bo); } - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) goto err; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index a91abfb32746..ba6d846b08ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -558,6 +558,7 @@ static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx, int lo, int hi, unsigned size, int32_t index) { int64_t offset = ((uint64_t)size) * ((int64_t)index); + struct ttm_operation_ctx ctx = { false, false }; struct amdgpu_bo_va_mapping *mapping; unsigned i, fpfn, lpfn; struct amdgpu_bo *bo; @@ -587,7 +588,7 @@ static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx, bo->placements[i].lpfn = bo->placements[i].fpfn ? min(bo->placements[i].fpfn, lpfn) : lpfn; } - return ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index dabaca4da7f2..df218df332b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -274,6 +274,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, bool direct, struct dma_fence **fence) { + struct ttm_operation_ctx ctx = { true, false }; struct ttm_validate_buffer tv; struct ww_acquire_ctx ticket; struct list_head head; @@ -294,7 +295,7 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *b if (r) return r; - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) goto err; diff --git a/drivers/gpu/drm/ast/ast_ttm.c b/drivers/gpu/drm/ast/ast_ttm.c index 696a15dc2f3f..28da7c2b7ed9 100644 --- a/drivers/gpu/drm/ast/ast_ttm.c +++ b/drivers/gpu/drm/ast/ast_ttm.c @@ -354,6 +354,7 @@ static inline u64 ast_bo_gpu_offset(struct ast_bo *bo) int ast_bo_pin(struct ast_bo *bo, u32 pl_flag, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (bo->pin_count) { @@ -365,7 +366,7 @@ int ast_bo_pin(struct ast_bo *bo, u32 pl_flag, u64 *gpu_addr) ast_ttm_placement(bo, pl_flag); for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; @@ -377,6 +378,7 @@ int ast_bo_pin(struct ast_bo *bo, u32 pl_flag, u64 *gpu_addr) int ast_bo_unpin(struct ast_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i; if (!bo->pin_count) { DRM_ERROR("unpin bad %p\n", bo); @@ -388,11 +390,12 @@ int ast_bo_unpin(struct ast_bo *bo) for (i = 0; i < bo->placement.num_placement ; i++) bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; - return ttm_bo_validate(&bo->bo, &bo->placement, false, false); + return ttm_bo_validate(&bo->bo, &bo->placement, &ctx); } int ast_bo_push_sysram(struct ast_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (!bo->pin_count) { DRM_ERROR("unpin bad %p\n", bo); @@ -409,7 +412,7 @@ int ast_bo_push_sysram(struct ast_bo *bo) for (i = 0; i < bo->placement.num_placement ; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) { DRM_ERROR("pushing to VRAM failed\n"); return ret; diff --git a/drivers/gpu/drm/bochs/bochs_mm.c b/drivers/gpu/drm/bochs/bochs_mm.c index c4cadb638460..8250b5e612d2 100644 --- a/drivers/gpu/drm/bochs/bochs_mm.c +++ b/drivers/gpu/drm/bochs/bochs_mm.c @@ -283,6 +283,7 @@ static inline u64 bochs_bo_gpu_offset(struct bochs_bo *bo) int bochs_bo_pin(struct bochs_bo *bo, u32 pl_flag, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (bo->pin_count) { @@ -295,7 +296,7 @@ int bochs_bo_pin(struct bochs_bo *bo, u32 pl_flag, u64 *gpu_addr) bochs_ttm_placement(bo, pl_flag); for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; @@ -307,6 +308,7 @@ int bochs_bo_pin(struct bochs_bo *bo, u32 pl_flag, u64 *gpu_addr) int bochs_bo_unpin(struct bochs_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (!bo->pin_count) { @@ -320,7 +322,7 @@ int bochs_bo_unpin(struct bochs_bo *bo) for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; diff --git a/drivers/gpu/drm/cirrus/cirrus_ttm.c b/drivers/gpu/drm/cirrus/cirrus_ttm.c index 1ff1838c0d44..2a5b54d3a03a 100644 --- a/drivers/gpu/drm/cirrus/cirrus_ttm.c +++ b/drivers/gpu/drm/cirrus/cirrus_ttm.c @@ -358,6 +358,7 @@ static inline u64 cirrus_bo_gpu_offset(struct cirrus_bo *bo) int cirrus_bo_pin(struct cirrus_bo *bo, u32 pl_flag, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (bo->pin_count) { @@ -369,7 +370,7 @@ int cirrus_bo_pin(struct cirrus_bo *bo, u32 pl_flag, u64 *gpu_addr) cirrus_ttm_placement(bo, pl_flag); for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; @@ -381,6 +382,7 @@ int cirrus_bo_pin(struct cirrus_bo *bo, u32 pl_flag, u64 *gpu_addr) int cirrus_bo_push_sysram(struct cirrus_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (!bo->pin_count) { DRM_ERROR("unpin bad %p\n", bo); @@ -397,7 +399,7 @@ int cirrus_bo_push_sysram(struct cirrus_bo *bo) for (i = 0; i < bo->placement.num_placement ; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) { DRM_ERROR("pushing to VRAM failed\n"); return ret; diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c index 3518167a7dc4..ab4ee5953615 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c @@ -344,6 +344,7 @@ int hibmc_bo_create(struct drm_device *dev, int size, int align, int hibmc_bo_pin(struct hibmc_bo *bo, u32 pl_flag, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (bo->pin_count) { @@ -356,7 +357,7 @@ int hibmc_bo_pin(struct hibmc_bo *bo, u32 pl_flag, u64 *gpu_addr) hibmc_ttm_placement(bo, pl_flag); for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; @@ -368,6 +369,7 @@ int hibmc_bo_pin(struct hibmc_bo *bo, u32 pl_flag, u64 *gpu_addr) int hibmc_bo_unpin(struct hibmc_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (!bo->pin_count) { @@ -380,7 +382,7 @@ int hibmc_bo_unpin(struct hibmc_bo *bo) for (i = 0; i < bo->placement.num_placement ; i++) bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) { DRM_ERROR("validate failed for unpin: %d\n", ret); return ret; diff --git a/drivers/gpu/drm/mgag200/mgag200_ttm.c b/drivers/gpu/drm/mgag200/mgag200_ttm.c index 3e7e1cd31395..f03da63abc7b 100644 --- a/drivers/gpu/drm/mgag200/mgag200_ttm.c +++ b/drivers/gpu/drm/mgag200/mgag200_ttm.c @@ -354,6 +354,7 @@ static inline u64 mgag200_bo_gpu_offset(struct mgag200_bo *bo) int mgag200_bo_pin(struct mgag200_bo *bo, u32 pl_flag, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (bo->pin_count) { @@ -366,7 +367,7 @@ int mgag200_bo_pin(struct mgag200_bo *bo, u32 pl_flag, u64 *gpu_addr) mgag200_ttm_placement(bo, pl_flag); for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; @@ -378,6 +379,7 @@ int mgag200_bo_pin(struct mgag200_bo *bo, u32 pl_flag, u64 *gpu_addr) int mgag200_bo_unpin(struct mgag200_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i; if (!bo->pin_count) { DRM_ERROR("unpin bad %p\n", bo); @@ -389,11 +391,12 @@ int mgag200_bo_unpin(struct mgag200_bo *bo) for (i = 0; i < bo->placement.num_placement ; i++) bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; - return ttm_bo_validate(&bo->bo, &bo->placement, false, false); + return ttm_bo_validate(&bo->bo, &bo->placement, &ctx); } int mgag200_bo_push_sysram(struct mgag200_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (!bo->pin_count) { DRM_ERROR("unpin bad %p\n", bo); @@ -410,7 +413,7 @@ int mgag200_bo_push_sysram(struct mgag200_bo *bo) for (i = 0; i < bo->placement.num_placement ; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) { DRM_ERROR("pushing to VRAM failed\n"); return ret; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 2615912430cc..1cf3da3d7bea 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -548,10 +548,10 @@ int nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, bool no_wait_gpu) { + struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; int ret; - ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, - interruptible, no_wait_gpu); + ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx); if (ret) return ret; diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c index 31effed4a3c8..e8c0b1037230 100644 --- a/drivers/gpu/drm/qxl/qxl_ioctl.c +++ b/drivers/gpu/drm/qxl/qxl_ioctl.c @@ -309,6 +309,7 @@ static int qxl_update_area_ioctl(struct drm_device *dev, void *data, int ret; struct drm_gem_object *gobj = NULL; struct qxl_bo *qobj = NULL; + struct ttm_operation_ctx ctx = { true, false }; if (update_area->left >= update_area->right || update_area->top >= update_area->bottom) @@ -326,8 +327,7 @@ static int qxl_update_area_ioctl(struct drm_device *dev, void *data, if (!qobj->pin_count) { qxl_ttm_placement_from_domain(qobj, qobj->type, false); - ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, - true, false); + ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx); if (unlikely(ret)) goto out; } diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c index 0a67ddf19c3d..f6b80fe47d1f 100644 --- a/drivers/gpu/drm/qxl/qxl_object.c +++ b/drivers/gpu/drm/qxl/qxl_object.c @@ -223,6 +223,7 @@ struct qxl_bo *qxl_bo_ref(struct qxl_bo *bo) static int __qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; struct drm_device *ddev = bo->gem_base.dev; int r; @@ -233,7 +234,7 @@ static int __qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr) return 0; } qxl_ttm_placement_from_domain(bo, domain, true); - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (likely(r == 0)) { bo->pin_count = 1; if (gpu_addr != NULL) @@ -246,6 +247,7 @@ static int __qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr) static int __qxl_bo_unpin(struct qxl_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; struct drm_device *ddev = bo->gem_base.dev; int r, i; @@ -258,7 +260,7 @@ static int __qxl_bo_unpin(struct qxl_bo *bo) return 0; for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (unlikely(r != 0)) dev_err(ddev->dev, "%p validate failed for unpin\n", bo); return r; diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c index f27777daae63..b223c8d0a491 100644 --- a/drivers/gpu/drm/qxl/qxl_release.c +++ b/drivers/gpu/drm/qxl/qxl_release.c @@ -230,12 +230,12 @@ int qxl_release_list_add(struct qxl_release *release, struct qxl_bo *bo) static int qxl_release_validate_bo(struct qxl_bo *bo) { + struct ttm_operation_ctx ctx = { true, false }; int ret; if (!bo->pin_count) { qxl_ttm_placement_from_domain(bo, bo->type, false); - ret = ttm_bo_validate(&bo->tbo, &bo->placement, - true, false); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (ret) return ret; } diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index cf3deb283da5..a9962ffba720 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -285,6 +285,7 @@ int radeon_gem_create_ioctl(struct drm_device *dev, void *data, int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { + struct ttm_operation_ctx ctx = { true, false }; struct radeon_device *rdev = dev->dev_private; struct drm_radeon_gem_userptr *args = data; struct drm_gem_object *gobj; @@ -343,7 +344,7 @@ int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, } radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_GTT); - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); radeon_bo_unreserve(bo); up_read(¤t->mm->mmap_sem); if (r) diff --git a/drivers/gpu/drm/radeon/radeon_mn.c b/drivers/gpu/drm/radeon/radeon_mn.c index 1d62288b7ee3..abd24975c9b1 100644 --- a/drivers/gpu/drm/radeon/radeon_mn.c +++ b/drivers/gpu/drm/radeon/radeon_mn.c @@ -124,6 +124,7 @@ static void radeon_mn_invalidate_range_start(struct mmu_notifier *mn, unsigned long end) { struct radeon_mn *rmn = container_of(mn, struct radeon_mn, mn); + struct ttm_operation_ctx ctx = { false, false }; struct interval_tree_node *it; /* notification is exclusive, but interval is inclusive */ @@ -157,7 +158,7 @@ static void radeon_mn_invalidate_range_start(struct mmu_notifier *mn, DRM_ERROR("(%ld) failed to wait for user bo\n", r); radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_CPU); - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) DRM_ERROR("(%ld) failed to validate user bo\n", r); diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index 093594976126..15404af9d740 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -329,6 +329,7 @@ void radeon_bo_unref(struct radeon_bo **bo) int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int r, i; if (radeon_ttm_tt_has_userptr(bo->tbo.ttm)) @@ -371,7 +372,7 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; } - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (likely(r == 0)) { bo->pin_count = 1; if (gpu_addr != NULL) @@ -393,6 +394,7 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) int radeon_bo_unpin(struct radeon_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int r, i; if (!bo->pin_count) { @@ -406,7 +408,7 @@ int radeon_bo_unpin(struct radeon_bo *bo) bo->placements[i].lpfn = 0; bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; } - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (likely(r == 0)) { if (bo->tbo.mem.mem_type == TTM_PL_VRAM) bo->rdev->vram_pin_size -= radeon_bo_size(bo); @@ -531,6 +533,7 @@ int radeon_bo_list_validate(struct radeon_device *rdev, struct ww_acquire_ctx *ticket, struct list_head *head, int ring) { + struct ttm_operation_ctx ctx = { true, false }; struct radeon_bo_list *lobj; struct list_head duplicates; int r; @@ -572,7 +575,7 @@ int radeon_bo_list_validate(struct radeon_device *rdev, radeon_uvd_force_into_uvd_segment(bo, allowed); initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); bytes_moved += atomic64_read(&rdev->num_bytes_moved) - initial_bytes_moved; @@ -792,6 +795,7 @@ void radeon_bo_move_notify(struct ttm_buffer_object *bo, int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) { + struct ttm_operation_ctx ctx = { false, false }; struct radeon_device *rdev; struct radeon_bo *rbo; unsigned long offset, size, lpfn; @@ -823,10 +827,10 @@ int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) rbo->placements[i].lpfn = lpfn; } - r = ttm_bo_validate(bo, &rbo->placement, false, false); + r = ttm_bo_validate(bo, &rbo->placement, &ctx); if (unlikely(r == -ENOMEM)) { radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); - return ttm_bo_validate(bo, &rbo->placement, false, false); + return ttm_bo_validate(bo, &rbo->placement, &ctx); } else if (unlikely(r != 0)) { return r; } diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c index e5c0e635e371..7f1a9c787bd1 100644 --- a/drivers/gpu/drm/radeon/radeon_vm.c +++ b/drivers/gpu/drm/radeon/radeon_vm.c @@ -387,6 +387,7 @@ static void radeon_vm_set_pages(struct radeon_device *rdev, static int radeon_vm_clear_bo(struct radeon_device *rdev, struct radeon_bo *bo) { + struct ttm_operation_ctx ctx = { true, false }; struct radeon_ib ib; unsigned entries; uint64_t addr; @@ -396,7 +397,7 @@ static int radeon_vm_clear_bo(struct radeon_device *rdev, if (r) return r; - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) goto error_unreserve; diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 77a0fd22e5ba..5347c3f3e2f4 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1091,9 +1091,8 @@ bool ttm_bo_mem_compat(struct ttm_placement *placement, EXPORT_SYMBOL(ttm_bo_mem_compat); int ttm_bo_validate(struct ttm_buffer_object *bo, - struct ttm_placement *placement, - bool interruptible, - bool no_wait_gpu) + struct ttm_placement *placement, + struct ttm_operation_ctx *ctx) { int ret; uint32_t new_flags; @@ -1103,8 +1102,8 @@ int ttm_bo_validate(struct ttm_buffer_object *bo, * Check whether we need to move buffer. */ if (!ttm_bo_mem_compat(placement, &bo->mem, &new_flags)) { - ret = ttm_bo_move_buffer(bo, placement, interruptible, - no_wait_gpu); + ret = ttm_bo_move_buffer(bo, placement, ctx->interruptible, + ctx->no_wait_gpu); if (ret) return ret; } else { @@ -1219,8 +1218,11 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev, WARN_ON(!locked); } - if (likely(!ret)) - ret = ttm_bo_validate(bo, placement, interruptible, false); + if (likely(!ret)) { + struct ttm_operation_ctx ctx = { interruptible, false }; + + ret = ttm_bo_validate(bo, placement, &ctx); + } if (unlikely(ret)) { if (!resv) diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c b/drivers/gpu/drm/virtio/virtgpu_ioctl.c index 461f81aa1bbe..5720a0d4ac0a 100644 --- a/drivers/gpu/drm/virtio/virtgpu_ioctl.c +++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c @@ -56,6 +56,7 @@ static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data, static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket, struct list_head *head) { + struct ttm_operation_ctx ctx = { false, false }; struct ttm_validate_buffer *buf; struct ttm_buffer_object *bo; struct virtio_gpu_object *qobj; @@ -68,7 +69,7 @@ static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket, list_for_each_entry(buf, head, head) { bo = buf->bo; qobj = container_of(bo, struct virtio_gpu_object, tbo); - ret = ttm_bo_validate(bo, &qobj->placement, false, false); + ret = ttm_bo_validate(bo, &qobj->placement, &ctx); if (ret) { ttm_eu_backoff_reservation(ticket, head); return ret; @@ -352,6 +353,7 @@ static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev, struct virtio_gpu_device *vgdev = dev->dev_private; struct virtio_gpu_fpriv *vfpriv = file->driver_priv; struct drm_virtgpu_3d_transfer_from_host *args = data; + struct ttm_operation_ctx ctx = { true, false }; struct drm_gem_object *gobj = NULL; struct virtio_gpu_object *qobj = NULL; struct virtio_gpu_fence *fence; @@ -372,8 +374,7 @@ static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev, if (ret) goto out; - ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, - true, false); + ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx); if (unlikely(ret)) goto out_unres; @@ -399,6 +400,7 @@ static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data, struct virtio_gpu_device *vgdev = dev->dev_private; struct virtio_gpu_fpriv *vfpriv = file->driver_priv; struct drm_virtgpu_3d_transfer_to_host *args = data; + struct ttm_operation_ctx ctx = { true, false }; struct drm_gem_object *gobj = NULL; struct virtio_gpu_object *qobj = NULL; struct virtio_gpu_fence *fence; @@ -416,8 +418,7 @@ static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data, if (ret) goto out; - ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, - true, false); + ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx); if (unlikely(ret)) goto out_unres; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c index d87861bbe971..92df0b08c194 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c @@ -387,6 +387,7 @@ static int vmw_cotable_readback(struct vmw_resource *res) */ static int vmw_cotable_resize(struct vmw_resource *res, size_t new_size) { + struct ttm_operation_ctx ctx = { false, false }; struct vmw_private *dev_priv = res->dev_priv; struct vmw_cotable *vcotbl = vmw_cotable(res); struct vmw_dma_buffer *buf, *old_buf = res->backup; @@ -455,7 +456,7 @@ static int vmw_cotable_resize(struct vmw_resource *res, size_t new_size) } /* Unpin new buffer, and switch backup buffers. */ - ret = ttm_bo_validate(bo, &vmw_mob_placement, false, false); + ret = ttm_bo_validate(bo, &vmw_mob_placement, &ctx); if (unlikely(ret != 0)) { DRM_ERROR("Failed validating new COTable backup buffer.\n"); goto out_wait; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c index 0cd889015dc5..d45d2caffa5a 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c @@ -47,6 +47,7 @@ int vmw_dmabuf_pin_in_placement(struct vmw_private *dev_priv, struct ttm_placement *placement, bool interruptible) { + struct ttm_operation_ctx ctx = {interruptible, false }; struct ttm_buffer_object *bo = &buf->base; int ret; uint32_t new_flags; @@ -65,7 +66,7 @@ int vmw_dmabuf_pin_in_placement(struct vmw_private *dev_priv, ret = ttm_bo_mem_compat(placement, &bo->mem, &new_flags) == true ? 0 : -EINVAL; else - ret = ttm_bo_validate(bo, placement, interruptible, false); + ret = ttm_bo_validate(bo, placement, &ctx); if (!ret) vmw_bo_pin_reserved(buf, true); @@ -95,6 +96,7 @@ int vmw_dmabuf_pin_in_vram_or_gmr(struct vmw_private *dev_priv, struct vmw_dma_buffer *buf, bool interruptible) { + struct ttm_operation_ctx ctx = {interruptible, false }; struct ttm_buffer_object *bo = &buf->base; int ret; uint32_t new_flags; @@ -115,12 +117,11 @@ int vmw_dmabuf_pin_in_vram_or_gmr(struct vmw_private *dev_priv, goto out_unreserve; } - ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, interruptible, - false); + ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, &ctx); if (likely(ret == 0) || ret == -ERESTARTSYS) goto out_unreserve; - ret = ttm_bo_validate(bo, &vmw_vram_placement, interruptible, false); + ret = ttm_bo_validate(bo, &vmw_vram_placement, &ctx); out_unreserve: if (!ret) @@ -170,6 +171,7 @@ int vmw_dmabuf_pin_in_start_of_vram(struct vmw_private *dev_priv, struct vmw_dma_buffer *buf, bool interruptible) { + struct ttm_operation_ctx ctx = {interruptible, false }; struct ttm_buffer_object *bo = &buf->base; struct ttm_placement placement; struct ttm_place place; @@ -200,14 +202,16 @@ int vmw_dmabuf_pin_in_start_of_vram(struct vmw_private *dev_priv, if (bo->mem.mem_type == TTM_PL_VRAM && bo->mem.start < bo->num_pages && bo->mem.start > 0 && - buf->pin_count == 0) - (void) ttm_bo_validate(bo, &vmw_sys_placement, false, false); + buf->pin_count == 0) { + ctx.interruptible = false; + (void) ttm_bo_validate(bo, &vmw_sys_placement, &ctx); + } if (buf->pin_count > 0) ret = ttm_bo_mem_compat(&placement, &bo->mem, &new_flags) == true ? 0 : -EINVAL; else - ret = ttm_bo_validate(bo, &placement, interruptible, false); + ret = ttm_bo_validate(bo, &placement, &ctx); /* For some reason we didn't end up at the start of vram */ WARN_ON(ret == 0 && bo->offset != 0); @@ -286,6 +290,7 @@ void vmw_bo_get_guest_ptr(const struct ttm_buffer_object *bo, */ void vmw_bo_pin_reserved(struct vmw_dma_buffer *vbo, bool pin) { + struct ttm_operation_ctx ctx = { false, true }; struct ttm_place pl; struct ttm_placement placement; struct ttm_buffer_object *bo = &vbo->base; @@ -314,7 +319,7 @@ void vmw_bo_pin_reserved(struct vmw_dma_buffer *vbo, bool pin) placement.num_placement = 1; placement.placement = &pl; - ret = ttm_bo_validate(bo, &placement, false, true); + ret = ttm_bo_validate(bo, &placement, &ctx); BUG_ON(ret != 0 || bo->mem.mem_type != old_mem_type); } diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c index 21c62a34e558..b700667f6f0b 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c @@ -3701,14 +3701,14 @@ int vmw_validate_single_buffer(struct vmw_private *dev_priv, { struct vmw_dma_buffer *vbo = container_of(bo, struct vmw_dma_buffer, base); + struct ttm_operation_ctx ctx = { interruptible, true }; int ret; if (vbo->pin_count > 0) return 0; if (validate_as_mob) - return ttm_bo_validate(bo, &vmw_mob_placement, interruptible, - false); + return ttm_bo_validate(bo, &vmw_mob_placement, &ctx); /** * Put BO in VRAM if there is space, otherwise as a GMR. @@ -3717,8 +3717,7 @@ int vmw_validate_single_buffer(struct vmw_private *dev_priv, * used as a GMR, this will return -ENOMEM. */ - ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, interruptible, - false); + ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, &ctx); if (likely(ret == 0 || ret == -ERESTARTSYS)) return ret; @@ -3727,7 +3726,7 @@ int vmw_validate_single_buffer(struct vmw_private *dev_priv, * previous contents. */ - ret = ttm_bo_validate(bo, &vmw_vram_placement, interruptible, false); + ret = ttm_bo_validate(bo, &vmw_vram_placement, &ctx); return ret; } diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c index a96f90f017d1..200904ff9a22 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c @@ -968,6 +968,7 @@ vmw_resource_check_buffer(struct vmw_resource *res, bool interruptible, struct ttm_validate_buffer *val_buf) { + struct ttm_operation_ctx ctx = { true, false }; struct list_head val_list; bool backup_dirty = false; int ret; @@ -992,7 +993,7 @@ vmw_resource_check_buffer(struct vmw_resource *res, backup_dirty = res->backup_dirty; ret = ttm_bo_validate(&res->backup->base, res->func->backup_placement, - true, false); + &ctx); if (unlikely(ret != 0)) goto out_no_validate; @@ -1446,6 +1447,7 @@ void vmw_resource_evict_all(struct vmw_private *dev_priv) */ int vmw_resource_pin(struct vmw_resource *res, bool interruptible) { + struct ttm_operation_ctx ctx = { interruptible, false }; struct vmw_private *dev_priv = res->dev_priv; int ret; @@ -1466,7 +1468,7 @@ int vmw_resource_pin(struct vmw_resource *res, bool interruptible) ret = ttm_bo_validate (&vbo->base, res->func->backup_placement, - interruptible, false); + &ctx); if (ret) { ttm_bo_unreserve(&vbo->base); goto out_no_validate; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c b/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c index 9b832f136813..004e18b8832c 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c @@ -970,6 +970,7 @@ int vmw_compat_shader_add(struct vmw_private *dev_priv, size_t size, struct list_head *list) { + struct ttm_operation_ctx ctx = { false, true }; struct vmw_dma_buffer *buf; struct ttm_bo_kmap_obj map; bool is_iomem; @@ -1005,7 +1006,7 @@ int vmw_compat_shader_add(struct vmw_private *dev_priv, WARN_ON(is_iomem); ttm_bo_kunmap(&map); - ret = ttm_bo_validate(&buf->base, &vmw_sys_placement, false, true); + ret = ttm_bo_validate(&buf->base, &vmw_sys_placement, &ctx); WARN_ON(ret != 0); ttm_bo_unreserve(&buf->base); diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index 833c3ad24091..097951e999bc 100644 --- a/include/drm/ttm/ttm_bo_api.h +++ b/include/drm/ttm/ttm_bo_api.h @@ -258,6 +258,20 @@ struct ttm_bo_kmap_obj { struct ttm_buffer_object *bo; }; +/** + * struct ttm_operation_ctx + * + * @interruptible: Sleep interruptible if sleeping. + * @no_wait_gpu: Return immediately if the GPU is busy. + * + * Context for TTM operations like changing buffer placement or general memory + * allocation. + */ +struct ttm_operation_ctx { + bool interruptible; + bool no_wait_gpu; +}; + /** * ttm_bo_reference - reference a struct ttm_buffer_object * @@ -306,8 +320,7 @@ bool ttm_bo_mem_compat(struct ttm_placement *placement, struct ttm_mem_reg *mem, * * @bo: The buffer object. * @placement: Proposed placement for the buffer object. - * @interruptible: Sleep interruptible if sleeping. - * @no_wait_gpu: Return immediately if the GPU is busy. + * @ctx: validation parameters. * * Changes placement and caching policy of the buffer object * according proposed placement. @@ -319,8 +332,7 @@ bool ttm_bo_mem_compat(struct ttm_placement *placement, struct ttm_mem_reg *mem, */ int ttm_bo_validate(struct ttm_buffer_object *bo, struct ttm_placement *placement, - bool interruptible, - bool no_wait_gpu); + struct ttm_operation_ctx *ctx); /** * ttm_bo_unref -- GitLab From 6fead44a4c5897c1524005ed3228b86120ff3ada Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 12 Apr 2017 14:41:43 +0200 Subject: [PATCH 0885/2547] drm/ttm: use an operation ctx for ttm_bo_init_reserved MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of specifying if sleeping should be interruptible. Signed-off-by: Christian König Reviewed-by: Michel Dänzer Reviewed-by: Chunming Zhou Tested-by: Dieter Nützel Tested-by: Michel Dänzer Acked-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++- drivers/gpu/drm/ttm/ttm_bo.c | 12 +++++------- include/drm/ttm/ttm_bo_api.h | 5 ++--- 3 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index c2419bc6b3df..15027f751e07 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -327,6 +327,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, uint64_t init_value, struct amdgpu_bo **bo_ptr) { + struct ttm_operation_ctx ctx = { !kernel, false }; struct amdgpu_bo *bo; enum ttm_bo_type type; unsigned long page_align; @@ -408,7 +409,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); /* Kernel allocation are uninterruptible */ r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type, - &bo->placement, page_align, !kernel, NULL, + &bo->placement, page_align, &ctx, NULL, acc_size, sg, resv, &amdgpu_ttm_bo_destroy); if (unlikely(r != 0)) return r; diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 5347c3f3e2f4..1f6957adc19e 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1132,7 +1132,7 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev, enum ttm_bo_type type, struct ttm_placement *placement, uint32_t page_alignment, - bool interruptible, + struct ttm_operation_ctx *ctx, struct file *persistent_swap_storage, size_t acc_size, struct sg_table *sg, @@ -1218,11 +1218,8 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev, WARN_ON(!locked); } - if (likely(!ret)) { - struct ttm_operation_ctx ctx = { interruptible, false }; - - ret = ttm_bo_validate(bo, placement, &ctx); - } + if (likely(!ret)) + ret = ttm_bo_validate(bo, placement, ctx); if (unlikely(ret)) { if (!resv) @@ -1255,10 +1252,11 @@ int ttm_bo_init(struct ttm_bo_device *bdev, struct reservation_object *resv, void (*destroy) (struct ttm_buffer_object *)) { + struct ttm_operation_ctx ctx = { interruptible, false }; int ret; ret = ttm_bo_init_reserved(bdev, bo, size, type, placement, - page_alignment, interruptible, + page_alignment, &ctx, persistent_swap_storage, acc_size, sg, resv, destroy); if (ret) diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index 097951e999bc..d0164d131982 100644 --- a/include/drm/ttm/ttm_bo_api.h +++ b/include/drm/ttm/ttm_bo_api.h @@ -455,8 +455,7 @@ size_t ttm_bo_dma_acc_size(struct ttm_bo_device *bdev, * @type: Requested type of buffer object. * @flags: Initial placement flags. * @page_alignment: Data alignment in pages. - * @interruptible: If needing to sleep to wait for GPU resources, - * sleep interruptible. + * @ctx: TTM operation context for memory allocation. * @persistent_swap_storage: Usually the swap storage is deleted for buffers * pinned in physical memory. If this behaviour is not desired, this member * holds a pointer to a persistent shmem object. Typically, this would @@ -493,7 +492,7 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev, enum ttm_bo_type type, struct ttm_placement *placement, uint32_t page_alignment, - bool interrubtible, + struct ttm_operation_ctx *ctx, struct file *persistent_swap_storage, size_t acc_size, struct sg_table *sg, -- GitLab From c13c55d611865a99871bb86cf1fc0017b8cc605a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 12 Apr 2017 15:33:00 +0200 Subject: [PATCH 0886/2547] drm/ttm: use an operation context for ttm_bo_mem_space v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of specifying interruptible and no_wait_gpu manually. v2: rebase Signed-off-by: Christian König Reviewed-by: Michel Dänzer Reviewed-by: Chunming Zhou Tested-by: Dieter Nützel Tested-by: Michel Dänzer Acked-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 ++++++----- drivers/gpu/drm/nouveau/nouveau_bo.c | 6 ++++-- drivers/gpu/drm/radeon/radeon_ttm.c | 8 ++++---- drivers/gpu/drm/ttm/ttm_bo.c | 22 +++++++++++----------- include/drm/ttm/ttm_bo_driver.h | 3 +-- 6 files changed, 29 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a43d096ebb52..0750b323e03f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -657,6 +657,7 @@ void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev) */ int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) { + struct ttm_operation_ctx ctx = { false, false }; int r = 0; int i; u64 vram_size = adev->mc.visible_vram_size; @@ -693,8 +694,8 @@ int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) } ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem); - r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem, - false, false); + r = ttm_bo_mem_space(&bo->tbo, &bo->placement, + &bo->tbo.mem, &ctx); if (r) goto error_pin; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 07ecf721ebf9..48b24155462c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -471,6 +471,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool no_wait_gpu, struct ttm_mem_reg *new_mem) { + struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; struct amdgpu_device *adev; struct ttm_mem_reg *old_mem = &bo->mem; struct ttm_mem_reg tmp_mem; @@ -488,8 +489,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, placements.fpfn = 0; placements.lpfn = 0; placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp_mem, - interruptible, no_wait_gpu); + r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); if (unlikely(r)) { return r; } @@ -518,6 +518,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool no_wait_gpu, struct ttm_mem_reg *new_mem) { + struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; struct amdgpu_device *adev; struct ttm_mem_reg *old_mem = &bo->mem; struct ttm_mem_reg tmp_mem; @@ -535,8 +536,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, placements.fpfn = 0; placements.lpfn = 0; placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp_mem, - interruptible, no_wait_gpu); + r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); if (unlikely(r)) { return r; } @@ -878,6 +878,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); + struct ttm_operation_ctx ctx = { false, false }; struct amdgpu_ttm_tt *gtt = (void*)bo->ttm; struct ttm_mem_reg tmp; struct ttm_placement placement; @@ -900,7 +901,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp, false, false); + r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); if (unlikely(r)) return r; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 1cf3da3d7bea..dae90cb748a4 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1199,6 +1199,7 @@ static int nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, bool no_wait_gpu, struct ttm_mem_reg *new_reg) { + struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; struct ttm_place placement_memtype = { .fpfn = 0, .lpfn = 0, @@ -1213,7 +1214,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, tmp_reg = *new_reg; tmp_reg.mm_node = NULL; - ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu); + ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); if (ret) return ret; @@ -1235,6 +1236,7 @@ static int nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, bool no_wait_gpu, struct ttm_mem_reg *new_reg) { + struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; struct ttm_place placement_memtype = { .fpfn = 0, .lpfn = 0, @@ -1249,7 +1251,7 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, tmp_reg = *new_reg; tmp_reg.mm_node = NULL; - ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu); + ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); if (ret) return ret; diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 6ada64db00e9..ef7cb83331b3 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -311,6 +311,7 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo, bool no_wait_gpu, struct ttm_mem_reg *new_mem) { + struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; struct radeon_device *rdev; struct ttm_mem_reg *old_mem = &bo->mem; struct ttm_mem_reg tmp_mem; @@ -328,8 +329,7 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo, placements.fpfn = 0; placements.lpfn = 0; placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp_mem, - interruptible, no_wait_gpu); + r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); if (unlikely(r)) { return r; } @@ -358,6 +358,7 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo, bool no_wait_gpu, struct ttm_mem_reg *new_mem) { + struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; struct radeon_device *rdev; struct ttm_mem_reg *old_mem = &bo->mem; struct ttm_mem_reg tmp_mem; @@ -375,8 +376,7 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo, placements.fpfn = 0; placements.lpfn = 0; placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp_mem, - interruptible, no_wait_gpu); + r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); if (unlikely(r)) { return r; } diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 1f6957adc19e..63c1a97b3589 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -656,6 +656,7 @@ EXPORT_SYMBOL(ttm_bo_unlock_delayed_workqueue); static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible, bool no_wait_gpu) { + struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; struct ttm_bo_device *bdev = bo->bdev; struct ttm_mem_reg evict_mem; struct ttm_placement placement; @@ -671,8 +672,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible, placement.num_placement = 0; placement.num_busy_placement = 0; bdev->driver->evict_flags(bo, &placement); - ret = ttm_bo_mem_space(bo, &placement, &evict_mem, interruptible, - no_wait_gpu); + ret = ttm_bo_mem_space(bo, &placement, &evict_mem, &ctx); if (ret) { if (ret != -ERESTARTSYS) { pr_err("Failed to find memory space for buffer 0x%p eviction\n", @@ -682,8 +682,8 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible, goto out; } - ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, interruptible, - no_wait_gpu); + ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, + interruptible, no_wait_gpu); if (unlikely(ret)) { if (ret != -ERESTARTSYS) pr_err("Buffer eviction failed\n"); @@ -903,8 +903,7 @@ static bool ttm_bo_mt_compatible(struct ttm_mem_type_manager *man, int ttm_bo_mem_space(struct ttm_buffer_object *bo, struct ttm_placement *placement, struct ttm_mem_reg *mem, - bool interruptible, - bool no_wait_gpu) + struct ttm_operation_ctx *ctx) { struct ttm_bo_device *bdev = bo->bdev; struct ttm_mem_type_manager *man; @@ -999,7 +998,8 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, } ret = ttm_bo_mem_force_space(bo, mem_type, place, mem, - interruptible, no_wait_gpu); + ctx->interruptible, + ctx->no_wait_gpu); if (ret == 0 && mem->mm_node) { mem->placement = cur_flags; return 0; @@ -1022,6 +1022,7 @@ static int ttm_bo_move_buffer(struct ttm_buffer_object *bo, bool interruptible, bool no_wait_gpu) { + struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; int ret = 0; struct ttm_mem_reg mem; @@ -1035,12 +1036,11 @@ static int ttm_bo_move_buffer(struct ttm_buffer_object *bo, /* * Determine where to move the buffer. */ - ret = ttm_bo_mem_space(bo, placement, &mem, - interruptible, no_wait_gpu); + ret = ttm_bo_mem_space(bo, placement, &mem, &ctx); if (ret) goto out_unlock; - ret = ttm_bo_handle_move_mem(bo, &mem, false, - interruptible, no_wait_gpu); + ret = ttm_bo_handle_move_mem(bo, &mem, false, interruptible, + no_wait_gpu); out_unlock: if (ret && mem.mm_node) ttm_bo_mem_put(bo, &mem); diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index a7c826a1e53f..494322a5f239 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -743,8 +743,7 @@ bool ttm_mem_reg_is_pci(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem); int ttm_bo_mem_space(struct ttm_buffer_object *bo, struct ttm_placement *placement, struct ttm_mem_reg *mem, - bool interruptible, - bool no_wait_gpu); + struct ttm_operation_ctx *ctx); void ttm_bo_mem_put(struct ttm_buffer_object *bo, struct ttm_mem_reg *mem); void ttm_bo_mem_put_locked(struct ttm_buffer_object *bo, -- GitLab From 83876c1bed8c91ed21a00bc929247d7427d9dde8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 12 Apr 2017 16:48:39 +0200 Subject: [PATCH 0887/2547] drm/ttm: use the operation context inside TTM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of passing down the parameters manually to every function. Signed-off-by: Christian König Reviewed-by: Michel Dänzer Reviewed-by: Chunming Zhou Tested-by: Dieter Nützel Tested-by: Michel Dänzer Acked-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 67 ++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 63c1a97b3589..4ed30ffa411f 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -269,9 +269,8 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc) } static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, - struct ttm_mem_reg *mem, - bool evict, bool interruptible, - bool no_wait_gpu) + struct ttm_mem_reg *mem, bool evict, + struct ttm_operation_ctx *ctx) { struct ttm_bo_device *bdev = bo->bdev; bool old_is_pci = ttm_mem_reg_is_pci(bdev, &bo->mem); @@ -325,12 +324,14 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, if (!(old_man->flags & TTM_MEMTYPE_FLAG_FIXED) && !(new_man->flags & TTM_MEMTYPE_FLAG_FIXED)) - ret = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, mem); + ret = ttm_bo_move_ttm(bo, ctx->interruptible, + ctx->no_wait_gpu, mem); else if (bdev->driver->move) - ret = bdev->driver->move(bo, evict, interruptible, - no_wait_gpu, mem); + ret = bdev->driver->move(bo, evict, ctx->interruptible, + ctx->no_wait_gpu, mem); else - ret = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, mem); + ret = ttm_bo_move_memcpy(bo, ctx->interruptible, + ctx->no_wait_gpu, mem); if (ret) { if (bdev->driver->move_notify) { @@ -653,10 +654,9 @@ void ttm_bo_unlock_delayed_workqueue(struct ttm_bo_device *bdev, int resched) } EXPORT_SYMBOL(ttm_bo_unlock_delayed_workqueue); -static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible, - bool no_wait_gpu) +static int ttm_bo_evict(struct ttm_buffer_object *bo, + struct ttm_operation_ctx *ctx) { - struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; struct ttm_bo_device *bdev = bo->bdev; struct ttm_mem_reg evict_mem; struct ttm_placement placement; @@ -672,7 +672,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible, placement.num_placement = 0; placement.num_busy_placement = 0; bdev->driver->evict_flags(bo, &placement); - ret = ttm_bo_mem_space(bo, &placement, &evict_mem, &ctx); + ret = ttm_bo_mem_space(bo, &placement, &evict_mem, ctx); if (ret) { if (ret != -ERESTARTSYS) { pr_err("Failed to find memory space for buffer 0x%p eviction\n", @@ -682,8 +682,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible, goto out; } - ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, - interruptible, no_wait_gpu); + ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, ctx); if (unlikely(ret)) { if (ret != -ERESTARTSYS) pr_err("Buffer eviction failed\n"); @@ -713,8 +712,7 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev, struct reservation_object *resv, uint32_t mem_type, const struct ttm_place *place, - bool interruptible, - bool no_wait_gpu) + struct ttm_operation_ctx *ctx) { struct ttm_bo_global *glob = bdev->glob; struct ttm_mem_type_manager *man = &bdev->man[mem_type]; @@ -759,8 +757,8 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev, kref_get(&bo->list_kref); if (!list_empty(&bo->ddestroy)) { - ret = ttm_bo_cleanup_refs(bo, interruptible, no_wait_gpu, - locked); + ret = ttm_bo_cleanup_refs(bo, ctx->interruptible, + ctx->no_wait_gpu, locked); kref_put(&bo->list_kref, ttm_bo_release_list); return ret; } @@ -768,7 +766,7 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev, ttm_bo_del_from_lru(bo); spin_unlock(&glob->lru_lock); - ret = ttm_bo_evict(bo, interruptible, no_wait_gpu); + ret = ttm_bo_evict(bo, ctx); if (locked) { ttm_bo_unreserve(bo); } else { @@ -826,8 +824,7 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object *bo, uint32_t mem_type, const struct ttm_place *place, struct ttm_mem_reg *mem, - bool interruptible, - bool no_wait_gpu) + struct ttm_operation_ctx *ctx) { struct ttm_bo_device *bdev = bo->bdev; struct ttm_mem_type_manager *man = &bdev->man[mem_type]; @@ -839,8 +836,7 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object *bo, return ret; if (mem->mm_node) break; - ret = ttm_mem_evict_first(bdev, bo->resv, mem_type, place, - interruptible, no_wait_gpu); + ret = ttm_mem_evict_first(bdev, bo->resv, mem_type, place, ctx); if (unlikely(ret != 0)) return ret; } while (1); @@ -997,9 +993,7 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, return 0; } - ret = ttm_bo_mem_force_space(bo, mem_type, place, mem, - ctx->interruptible, - ctx->no_wait_gpu); + ret = ttm_bo_mem_force_space(bo, mem_type, place, mem, ctx); if (ret == 0 && mem->mm_node) { mem->placement = cur_flags; return 0; @@ -1018,11 +1012,9 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, EXPORT_SYMBOL(ttm_bo_mem_space); static int ttm_bo_move_buffer(struct ttm_buffer_object *bo, - struct ttm_placement *placement, - bool interruptible, - bool no_wait_gpu) + struct ttm_placement *placement, + struct ttm_operation_ctx *ctx) { - struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; int ret = 0; struct ttm_mem_reg mem; @@ -1036,11 +1028,10 @@ static int ttm_bo_move_buffer(struct ttm_buffer_object *bo, /* * Determine where to move the buffer. */ - ret = ttm_bo_mem_space(bo, placement, &mem, &ctx); + ret = ttm_bo_mem_space(bo, placement, &mem, ctx); if (ret) goto out_unlock; - ret = ttm_bo_handle_move_mem(bo, &mem, false, interruptible, - no_wait_gpu); + ret = ttm_bo_handle_move_mem(bo, &mem, false, ctx); out_unlock: if (ret && mem.mm_node) ttm_bo_mem_put(bo, &mem); @@ -1102,8 +1093,7 @@ int ttm_bo_validate(struct ttm_buffer_object *bo, * Check whether we need to move buffer. */ if (!ttm_bo_mem_compat(placement, &bo->mem, &new_flags)) { - ret = ttm_bo_move_buffer(bo, placement, ctx->interruptible, - ctx->no_wait_gpu); + ret = ttm_bo_move_buffer(bo, placement, ctx); if (ret) return ret; } else { @@ -1328,6 +1318,7 @@ EXPORT_SYMBOL(ttm_bo_create); static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, unsigned mem_type) { + struct ttm_operation_ctx ctx = { false, false }; struct ttm_mem_type_manager *man = &bdev->man[mem_type]; struct ttm_bo_global *glob = bdev->glob; struct dma_fence *fence; @@ -1342,8 +1333,8 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) { while (!list_empty(&man->lru[i])) { spin_unlock(&glob->lru_lock); - ret = ttm_mem_evict_first(bdev, NULL, mem_type, NULL, - false, false); + ret = ttm_mem_evict_first(bdev, NULL, mem_type, + NULL, &ctx); if (ret) return ret; spin_lock(&glob->lru_lock); @@ -1740,6 +1731,7 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) if (bo->mem.mem_type != TTM_PL_SYSTEM || bo->ttm->caching_state != tt_cached) { + struct ttm_operation_ctx ctx = { false, false }; struct ttm_mem_reg evict_mem; evict_mem = bo->mem; @@ -1747,8 +1739,7 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) evict_mem.placement = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED; evict_mem.mem_type = TTM_PL_SYSTEM; - ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, - false, false); + ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, &ctx); if (unlikely(ret != 0)) goto out; } -- GitLab From 2823f4f019d888472c7032ab7d7bc1c98df3c071 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 26 Apr 2017 16:31:14 +0200 Subject: [PATCH 0888/2547] drm/ttm: add context to driver move callback as well MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of passing the parameters manually. Signed-off-by: Christian König Reviewed-by: Michel Dänzer Reviewed-by: Chunming Zhou Tested-by: Dieter Nützel Tested-by: Michel Dänzer Acked-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 ++++++++++--------- drivers/gpu/drm/nouveau/nouveau_bo.c | 27 +++++++++++++++---------- drivers/gpu/drm/qxl/qxl_ttm.c | 9 ++++----- drivers/gpu/drm/radeon/radeon_ttm.c | 23 +++++++++++---------- drivers/gpu/drm/ttm/ttm_bo.c | 3 +-- drivers/gpu/drm/virtio/virtgpu_ttm.c | 7 +++---- include/drm/ttm/ttm_bo_driver.h | 6 ++---- 7 files changed, 49 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 48b24155462c..0e90f64c2c09 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -553,10 +553,9 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, return r; } -static int amdgpu_bo_move(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, - struct ttm_mem_reg *new_mem) +static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, + struct ttm_mem_reg *new_mem) { struct amdgpu_device *adev; struct amdgpu_bo *abo; @@ -591,19 +590,21 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, if (old_mem->mem_type == TTM_PL_VRAM && new_mem->mem_type == TTM_PL_SYSTEM) { - r = amdgpu_move_vram_ram(bo, evict, interruptible, - no_wait_gpu, new_mem); + r = amdgpu_move_vram_ram(bo, evict, ctx->interruptible, + ctx->no_wait_gpu, new_mem); } else if (old_mem->mem_type == TTM_PL_SYSTEM && new_mem->mem_type == TTM_PL_VRAM) { - r = amdgpu_move_ram_vram(bo, evict, interruptible, - no_wait_gpu, new_mem); + r = amdgpu_move_ram_vram(bo, evict, ctx->interruptible, + ctx->no_wait_gpu, new_mem); } else { - r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); + r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, + new_mem, old_mem); } if (r) { memcpy: - r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem); + r = ttm_bo_move_memcpy(bo, ctx->interruptible, + ctx->no_wait_gpu, new_mem); if (r) { return r; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index dae90cb748a4..949bf6b3feab 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1328,8 +1328,9 @@ nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, } static int -nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, - bool no_wait_gpu, struct ttm_mem_reg *new_reg) +nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, + struct ttm_mem_reg *new_reg) { struct nouveau_drm *drm = nouveau_bdev(bo->bdev); struct nouveau_bo *nvbo = nouveau_bo(bo); @@ -1337,7 +1338,7 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, struct nouveau_drm_tile *new_tile = NULL; int ret = 0; - ret = ttm_bo_wait(bo, intr, no_wait_gpu); + ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (ret) return ret; @@ -1361,22 +1362,26 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, /* Hardware assisted copy. */ if (drm->ttm.move) { if (new_reg->mem_type == TTM_PL_SYSTEM) - ret = nouveau_bo_move_flipd(bo, evict, intr, - no_wait_gpu, new_reg); + ret = nouveau_bo_move_flipd(bo, evict, + ctx->interruptible, + ctx->no_wait_gpu, new_reg); else if (old_reg->mem_type == TTM_PL_SYSTEM) - ret = nouveau_bo_move_flips(bo, evict, intr, - no_wait_gpu, new_reg); + ret = nouveau_bo_move_flips(bo, evict, + ctx->interruptible, + ctx->no_wait_gpu, new_reg); else - ret = nouveau_bo_move_m2mf(bo, evict, intr, - no_wait_gpu, new_reg); + ret = nouveau_bo_move_m2mf(bo, evict, + ctx->interruptible, + ctx->no_wait_gpu, new_reg); if (!ret) goto out; } /* Fallback to software copy. */ - ret = ttm_bo_wait(bo, intr, no_wait_gpu); + ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (ret == 0) - ret = ttm_bo_move_memcpy(bo, intr, no_wait_gpu, new_reg); + ret = ttm_bo_move_memcpy(bo, ctx->interruptible, + ctx->no_wait_gpu, new_reg); out: if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c index 586ecd6e0e45..d866f329e7d8 100644 --- a/drivers/gpu/drm/qxl/qxl_ttm.c +++ b/drivers/gpu/drm/qxl/qxl_ttm.c @@ -341,15 +341,14 @@ static void qxl_move_null(struct ttm_buffer_object *bo, new_mem->mm_node = NULL; } -static int qxl_bo_move(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, +static int qxl_bo_move(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem) { struct ttm_mem_reg *old_mem = &bo->mem; int ret; - ret = ttm_bo_wait(bo, interruptible, no_wait_gpu); + ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (ret) return ret; @@ -358,7 +357,7 @@ static int qxl_bo_move(struct ttm_buffer_object *bo, qxl_move_null(bo, new_mem); return 0; } - return ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, + return ttm_bo_move_memcpy(bo, ctx->interruptible, ctx->no_wait_gpu, new_mem); } diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index ef7cb83331b3..98e30d71d9e0 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -393,17 +393,16 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo, return r; } -static int radeon_bo_move(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, - struct ttm_mem_reg *new_mem) +static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, + struct ttm_mem_reg *new_mem) { struct radeon_device *rdev; struct radeon_bo *rbo; struct ttm_mem_reg *old_mem = &bo->mem; int r; - r = ttm_bo_wait(bo, interruptible, no_wait_gpu); + r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (r) return r; @@ -433,19 +432,21 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, if (old_mem->mem_type == TTM_PL_VRAM && new_mem->mem_type == TTM_PL_SYSTEM) { - r = radeon_move_vram_ram(bo, evict, interruptible, - no_wait_gpu, new_mem); + r = radeon_move_vram_ram(bo, evict, ctx->interruptible, + ctx->no_wait_gpu, new_mem); } else if (old_mem->mem_type == TTM_PL_SYSTEM && new_mem->mem_type == TTM_PL_VRAM) { - r = radeon_move_ram_vram(bo, evict, interruptible, - no_wait_gpu, new_mem); + r = radeon_move_ram_vram(bo, evict, ctx->interruptible, + ctx->no_wait_gpu, new_mem); } else { - r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); + r = radeon_move_blit(bo, evict, ctx->no_wait_gpu, + new_mem, old_mem); } if (r) { memcpy: - r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem); + r = ttm_bo_move_memcpy(bo, ctx->interruptible, + ctx->no_wait_gpu, new_mem); if (r) { return r; } diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 4ed30ffa411f..d3448c38f00d 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -327,8 +327,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, ret = ttm_bo_move_ttm(bo, ctx->interruptible, ctx->no_wait_gpu, mem); else if (bdev->driver->move) - ret = bdev->driver->move(bo, evict, ctx->interruptible, - ctx->no_wait_gpu, mem); + ret = bdev->driver->move(bo, evict, ctx, mem); else ret = ttm_bo_move_memcpy(bo, ctx->interruptible, ctx->no_wait_gpu, mem); diff --git a/drivers/gpu/drm/virtio/virtgpu_ttm.c b/drivers/gpu/drm/virtio/virtgpu_ttm.c index cd389c5eaef5..488c6bd032fc 100644 --- a/drivers/gpu/drm/virtio/virtgpu_ttm.c +++ b/drivers/gpu/drm/virtio/virtgpu_ttm.c @@ -369,14 +369,13 @@ static void virtio_gpu_move_null(struct ttm_buffer_object *bo, new_mem->mm_node = NULL; } -static int virtio_gpu_bo_move(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, +static int virtio_gpu_bo_move(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem) { int ret; - ret = ttm_bo_wait(bo, interruptible, no_wait_gpu); + ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (ret) return ret; diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index 494322a5f239..6996d884c508 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -409,15 +409,13 @@ struct ttm_bo_driver { * @bo: the buffer to move * @evict: whether this motion is evicting the buffer from * the graphics address space - * @interruptible: Use interruptible sleeps if possible when sleeping. - * @no_wait: whether this should give up and return -EBUSY - * if this move would require sleeping + * @ctx: context for this move with parameters * @new_mem: the new memory region receiving the buffer * * Move a buffer between two memory regions. */ int (*move)(struct ttm_buffer_object *bo, bool evict, - bool interruptible, bool no_wait_gpu, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem); /** -- GitLab From 6cd2e71e897f423412c6d5d0d1190341935d36b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 27 Apr 2017 18:19:46 +0200 Subject: [PATCH 0889/2547] drm/ttm: add number of bytes moved to the operation context MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add some statistics how many bytes we have moved. Signed-off-by: Christian König Reviewed-by: Michel Dänzer Reviewed-by: Chunming Zhou Tested-by: Dieter Nützel Tested-by: Michel Dänzer Acked-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 1 + include/drm/ttm/ttm_bo_api.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index d3448c38f00d..97c3da6d5f17 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -361,6 +361,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, else bo->offset = 0; + ctx->bytes_moved += bo->num_pages << PAGE_SHIFT; return 0; out_err: diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index d0164d131982..368eb02b54a9 100644 --- a/include/drm/ttm/ttm_bo_api.h +++ b/include/drm/ttm/ttm_bo_api.h @@ -270,6 +270,7 @@ struct ttm_bo_kmap_obj { struct ttm_operation_ctx { bool interruptible; bool no_wait_gpu; + uint64_t bytes_moved; }; /** -- GitLab From 3f3a7c8259312084291859d3b623db4317365a07 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 24 Nov 2017 11:32:59 +0100 Subject: [PATCH 0890/2547] staging: vboxvideo: adapt to new TTM interface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes interface changes done in the following commits: drm/ttm: add operation ctx to ttm_bo_validate v2 drm/ttm: add context to driver move callback as well I missed this driver because it is in the staging area. Acked-by: Greg Kroah-Hartman Acked-by: Alex Deucher Signed-off-by: Christian König Reviewed-by: Hans de Goede Signed-off-by: Alex Deucher --- drivers/staging/vboxvideo/vbox_ttm.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/staging/vboxvideo/vbox_ttm.c b/drivers/staging/vboxvideo/vbox_ttm.c index 4eb410a2a1a8..231c89e0699c 100644 --- a/drivers/staging/vboxvideo/vbox_ttm.c +++ b/drivers/staging/vboxvideo/vbox_ttm.c @@ -183,13 +183,6 @@ static void vbox_ttm_io_mem_free(struct ttm_bo_device *bdev, { } -static int vbox_bo_move(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, struct ttm_mem_reg *new_mem) -{ - return ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem); -} - static void vbox_ttm_backend_destroy(struct ttm_tt *tt) { ttm_tt_fini(tt); @@ -237,7 +230,6 @@ static struct ttm_bo_driver vbox_bo_driver = { .init_mem_type = vbox_bo_init_mem_type, .eviction_valuable = ttm_bo_eviction_valuable, .evict_flags = vbox_bo_evict_flags, - .move = vbox_bo_move, .verify_access = vbox_bo_verify_access, .io_mem_reserve = &vbox_ttm_io_mem_reserve, .io_mem_free = &vbox_ttm_io_mem_free, @@ -374,6 +366,7 @@ static inline u64 vbox_bo_gpu_offset(struct vbox_bo *bo) int vbox_bo_pin(struct vbox_bo *bo, u32 pl_flag, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (bo->pin_count) { @@ -389,7 +382,7 @@ int vbox_bo_pin(struct vbox_bo *bo, u32 pl_flag, u64 *gpu_addr) for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; @@ -403,6 +396,7 @@ int vbox_bo_pin(struct vbox_bo *bo, u32 pl_flag, u64 *gpu_addr) int vbox_bo_unpin(struct vbox_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (!bo->pin_count) { @@ -416,7 +410,7 @@ int vbox_bo_unpin(struct vbox_bo *bo) for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; @@ -430,6 +424,7 @@ int vbox_bo_unpin(struct vbox_bo *bo) */ int vbox_bo_push_sysram(struct vbox_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (!bo->pin_count) { @@ -448,7 +443,7 @@ int vbox_bo_push_sysram(struct vbox_bo *bo) for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) { DRM_ERROR("pushing to VRAM failed\n"); return ret; -- GitLab From dfb8fa9828dba4a83545c8d854bb6bc003a95d95 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 26 Apr 2017 16:44:41 +0200 Subject: [PATCH 0891/2547] drm/amdgpu: forward operation context to ttm_bo_mem_space MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This way we can finally use some more stats. Signed-off-by: Christian König Reviewed-by: Michel Dänzer Reviewed-by: Chunming Zhou Tested-by: Dieter Nützel Tested-by: Michel Dänzer Acked-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 30 ++++++++++--------------- 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 0e90f64c2c09..3385694a97cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -466,12 +466,10 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, return r; } -static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, +static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem) { - struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; struct amdgpu_device *adev; struct ttm_mem_reg *old_mem = &bo->mem; struct ttm_mem_reg tmp_mem; @@ -489,7 +487,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, placements.fpfn = 0; placements.lpfn = 0; placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); + r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); if (unlikely(r)) { return r; } @@ -503,22 +501,20 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, if (unlikely(r)) { goto out_cleanup; } - r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); + r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, &tmp_mem, old_mem); if (unlikely(r)) { goto out_cleanup; } - r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem); + r = ttm_bo_move_ttm(bo, ctx->interruptible, ctx->no_wait_gpu, new_mem); out_cleanup: ttm_bo_mem_put(bo, &tmp_mem); return r; } -static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, +static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem) { - struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; struct amdgpu_device *adev; struct ttm_mem_reg *old_mem = &bo->mem; struct ttm_mem_reg tmp_mem; @@ -536,15 +532,15 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, placements.fpfn = 0; placements.lpfn = 0; placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); + r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); if (unlikely(r)) { return r; } - r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem); + r = ttm_bo_move_ttm(bo, ctx->interruptible, ctx->no_wait_gpu, &tmp_mem); if (unlikely(r)) { goto out_cleanup; } - r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); + r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, new_mem, old_mem); if (unlikely(r)) { goto out_cleanup; } @@ -590,12 +586,10 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, if (old_mem->mem_type == TTM_PL_VRAM && new_mem->mem_type == TTM_PL_SYSTEM) { - r = amdgpu_move_vram_ram(bo, evict, ctx->interruptible, - ctx->no_wait_gpu, new_mem); + r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem); } else if (old_mem->mem_type == TTM_PL_SYSTEM && new_mem->mem_type == TTM_PL_VRAM) { - r = amdgpu_move_ram_vram(bo, evict, ctx->interruptible, - ctx->no_wait_gpu, new_mem); + r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem); } else { r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem); -- GitLab From 6af046d26f34278eacd6ecddb37170624f6d4251 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 27 Apr 2017 18:20:47 +0200 Subject: [PATCH 0892/2547] drm/amdgpu: use the new TTM bytes moved counter v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of the global statistics use the per context bytes moved counter. v2: rebased Signed-off-by: Christian König Reviewed-by: Michel Dänzer Reviewed-by: Chunming Zhou Tested-by: Dieter Nützel Tested-by: Michel Dänzer Acked-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 +++------ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 +++------- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index faab662ce680..5e89d7a7178f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -344,7 +344,6 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct ttm_operation_ctx ctx = { true, false }; - u64 initial_bytes_moved, bytes_moved; uint32_t domain; int r; @@ -374,15 +373,13 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, retry: amdgpu_ttm_placement_from_domain(bo, domain); - initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); - bytes_moved = atomic64_read(&adev->num_bytes_moved) - - initial_bytes_moved; - p->bytes_moved += bytes_moved; + + p->bytes_moved += ctx.bytes_moved; if (adev->mc.visible_vram_size < adev->mc.real_vram_size && bo->tbo.mem.mem_type == TTM_PL_VRAM && bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT) - p->bytes_moved_vis += bytes_moved; + p->bytes_moved_vis += ctx.bytes_moved; if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { domain = bo->allowed_domains; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 15027f751e07..dc0a8be98043 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -331,7 +331,6 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, struct amdgpu_bo *bo; enum ttm_bo_type type; unsigned long page_align; - u64 initial_bytes_moved, bytes_moved; size_t acc_size; int r; @@ -406,22 +405,19 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, bo->tbo.bdev = &adev->mman.bdev; amdgpu_ttm_placement_from_domain(bo, domain); - initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); - /* Kernel allocation are uninterruptible */ r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type, &bo->placement, page_align, &ctx, NULL, acc_size, sg, resv, &amdgpu_ttm_bo_destroy); if (unlikely(r != 0)) return r; - bytes_moved = atomic64_read(&adev->num_bytes_moved) - - initial_bytes_moved; if (adev->mc.visible_vram_size < adev->mc.real_vram_size && bo->tbo.mem.mem_type == TTM_PL_VRAM && bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT) - amdgpu_cs_report_moved_bytes(adev, bytes_moved, bytes_moved); + amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, + ctx.bytes_moved); else - amdgpu_cs_report_moved_bytes(adev, bytes_moved, 0); + amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); if (kernel) bo->tbo.priority = 1; -- GitLab From bb7939b2030ab55acd203c86160c37db22f5796a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 6 Nov 2017 15:37:01 +0100 Subject: [PATCH 0893/2547] drm/amdgpu: fix VA hole handling on Vega10 v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Similar to the CPU address space the VA on Vega10 has a hole in it. v2: use dev_dbg instead of dev_err v3: add some more comments to explain how the hw works Signed-off-by: Christian König Reviewed-by: Alex Deucher CC: stable@vger.kernel.org Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 11 +++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 13 +++++++++++++ 4 files changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 5e89d7a7178f..93d3cef66503 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -870,8 +870,8 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, struct amdgpu_bo_va_mapping *m; struct amdgpu_bo *aobj = NULL; struct amdgpu_cs_chunk *chunk; + uint64_t offset, va_start; struct amdgpu_ib *ib; - uint64_t offset; uint8_t *kptr; chunk = &p->chunks[i]; @@ -881,14 +881,14 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) continue; - r = amdgpu_cs_find_mapping(p, chunk_ib->va_start, - &aobj, &m); + va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK; + r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m); if (r) { DRM_ERROR("IB va_start is invalid\n"); return r; } - if ((chunk_ib->va_start + chunk_ib->ib_bytes) > + if ((va_start + chunk_ib->ib_bytes) > (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) { DRM_ERROR("IB va_start+ib_bytes is invalid\n"); return -EINVAL; @@ -901,7 +901,7 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, } offset = m->start * AMDGPU_GPU_PAGE_SIZE; - kptr += chunk_ib->va_start - offset; + kptr += va_start - offset; memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); amdgpu_bo_kunmap(aobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index c16579287aee..59c9facf9bd7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -564,6 +564,17 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, return -EINVAL; } + if (args->va_address >= AMDGPU_VA_HOLE_START && + args->va_address < AMDGPU_VA_HOLE_END) { + dev_dbg(&dev->pdev->dev, + "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", + args->va_address, AMDGPU_VA_HOLE_START, + AMDGPU_VA_HOLE_END); + return -EINVAL; + } + + args->va_address &= AMDGPU_VA_HOLE_MASK; + if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n", args->flags); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index f55021ae788d..2614269c4d7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -578,7 +578,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file if (amdgpu_sriov_vf(adev)) dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; - dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; + dev_info.virtual_address_max = + min(adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE, + AMDGPU_VA_HOLE_START); dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index e8f8896d18db..c80d45dd2bd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -96,6 +96,19 @@ struct amdgpu_bo_list_entry; /* hardcode that limit for now */ #define AMDGPU_VA_RESERVED_SIZE (8ULL << 20) +/* VA hole for 48bit addresses on Vega10 */ +#define AMDGPU_VA_HOLE_START 0x0000800000000000ULL +#define AMDGPU_VA_HOLE_END 0xffff800000000000ULL + +/* + * Hardware is programmed as if the hole doesn't exists with start and end + * address values. + * + * This mask is used to remove the upper 16bits of the VA and so come up with + * the linear addr value. + */ +#define AMDGPU_VA_HOLE_MASK 0x0000ffffffffffffULL + /* max vmids dedicated for process */ #define AMDGPU_VM_MAX_RESERVED_VMID 1 -- GitLab From 4b7f0848c4e1e7a92cc3c0243a38a8f183c9b869 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 13 Nov 2017 13:58:17 +0100 Subject: [PATCH 0894/2547] drm/amdgpu: use dev_dbg instead of dev_err in the VA IOCTL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Userspace buggy userspace can spam the logs. Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 59c9facf9bd7..eb75eb44efc6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -558,7 +558,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, int r = 0; if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { - dev_err(&dev->pdev->dev, + dev_dbg(&dev->pdev->dev, "va_address 0x%LX is in reserved area 0x%LX\n", args->va_address, AMDGPU_VA_RESERVED_SIZE); return -EINVAL; @@ -576,7 +576,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, args->va_address &= AMDGPU_VA_HOLE_MASK; if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { - dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n", + dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", args->flags); return -EINVAL; } @@ -588,7 +588,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, case AMDGPU_VA_OP_REPLACE: break; default: - dev_err(&dev->pdev->dev, "unsupported operation %d\n", + dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", args->operation); return -EINVAL; } -- GitLab From 5b565e0e5a9872f8c5a459ce53f8d6a4b19a1a66 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Tue, 7 Nov 2017 12:03:31 +0100 Subject: [PATCH 0895/2547] drm/amdgpu: expose the VA above the hole to userspace MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Let userspace know how much area we have above the 48bit VA hole on Vega10. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 ++++++++++-- include/uapi/drm/amdgpu_drm.h | 4 ++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 2614269c4d7f..3222e1d4636c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -550,6 +550,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file } case AMDGPU_INFO_DEV_INFO: { struct drm_amdgpu_info_device dev_info = {}; + uint64_t vm_size; dev_info.device_id = dev->pdev->device; dev_info.chip_rev = adev->rev_id; @@ -577,10 +578,17 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; if (amdgpu_sriov_vf(adev)) dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; + + vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; dev_info.virtual_address_max = - min(adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE, - AMDGPU_VA_HOLE_START); + min(vm_size, AMDGPU_VA_HOLE_START); + + vm_size -= AMDGPU_VA_RESERVED_SIZE; + if (vm_size > AMDGPU_VA_HOLE_START) { + dev_info.high_va_offset = AMDGPU_VA_HOLE_END; + dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size; + } dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 0e23ce3f3113..4d21191aaed0 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -877,6 +877,10 @@ struct drm_amdgpu_info_device { __u32 _pad1; /* always on cu bitmap */ __u32 cu_ao_bitmap[4][4]; + /** Starting high virtual address for UMDs. */ + __u64 high_va_offset; + /** The maximum high virtual address */ + __u64 high_va_max; }; struct drm_amdgpu_info_hw_ip { -- GitLab From 43fbcde020f100c86fb54cbb2610164466dc8b0e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Wed, 22 Nov 2017 15:55:21 +0100 Subject: [PATCH 0896/2547] drm/amdgpu: Downgrade DRM_ERROR to DRM_DEBUG in amdgpu_queue_mgr_map MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Prevent buggy userspace from spamming dmesg. Reviewed-by: Alex Deucher Reviewed-by: Christian König Signed-off-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c index 93d86619e802..262c1267249e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c @@ -225,7 +225,7 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev, /* Right now all IPs have only one instance - multiple rings. */ if (instance != 0) { - DRM_ERROR("invalid ip instance: %d\n", instance); + DRM_DEBUG("invalid ip instance: %d\n", instance); return -EINVAL; } @@ -255,13 +255,13 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev, ip_num_rings = adev->vcn.num_enc_rings; break; default: - DRM_ERROR("unknown ip type: %d\n", hw_ip); + DRM_DEBUG("unknown ip type: %d\n", hw_ip); return -EINVAL; } if (ring >= ip_num_rings) { - DRM_ERROR("Ring index:%d exceeds maximum:%d for ip:%d\n", - ring, ip_num_rings, hw_ip); + DRM_DEBUG("Ring index:%d exceeds maximum:%d for ip:%d\n", + ring, ip_num_rings, hw_ip); return -EINVAL; } @@ -292,7 +292,7 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev, default: *out_ring = NULL; r = -EINVAL; - DRM_ERROR("unknown HW IP type: %d\n", mapper->hw_ip); + DRM_DEBUG("unknown HW IP type: %d\n", mapper->hw_ip); } out_unlock: -- GitLab From 96b8af6eb4a9fdc49486c4333d80bdbb255c3c5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Wed, 22 Nov 2017 15:55:22 +0100 Subject: [PATCH 0897/2547] drm/amd/display: Fix description of module parameter dc_log MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It was incorrectly referencing the dc parameter, resulting in an empty description of the dc_log parameter. Reviewed-by: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index eaccd4bd12a4..31383e004947 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -216,7 +216,7 @@ module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); module_param_named(dc, amdgpu_dc, int, 0444); -MODULE_PARM_DESC(dc, "Display Core Log Level (0 = minimal (default), 1 = chatty"); +MODULE_PARM_DESC(dc_log, "Display Core Log Level (0 = minimal (default), 1 = chatty"); module_param_named(dc_log, amdgpu_dc_log, int, 0444); MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); -- GitLab From afbeb2638b0a983100a5e6591bd1b76ef45bf20c Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Wed, 1 Nov 2017 16:48:52 -0400 Subject: [PATCH 0898/2547] drm/amd/display: call set_mpc_output_csc from hwsequencer Signed-off-by: Yue Hin Lau Reviewed-by: Eric Bernstein Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 140 ++++++++++-------- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 67 ++++++++- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 16 ++ 3 files changed, 156 insertions(+), 67 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index b4892f43cd77..b5541985e0d8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -117,6 +117,33 @@ static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = { 0x2568, 0x43ee, 0xdbb2} } }; +struct output_csc_matrix { + enum dc_color_space color_space; + uint16_t regval[12]; +}; + +static const struct output_csc_matrix output_csc_matrix[] = { + { COLOR_SPACE_SRGB, + { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, + { COLOR_SPACE_SRGB_LIMITED, + { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} }, + { COLOR_SPACE_YCBCR601, + { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47, + 0xF6B9, 0xE00, 0x1000} }, + { COLOR_SPACE_YCBCR709, + { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA, + 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, + + /* TODO: correct values below */ + { COLOR_SPACE_YCBCR601_LIMITED, + { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, + 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, + { COLOR_SPACE_YCBCR709_LIMITED, + { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, + 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, + { COLOR_SPACE_UNKNOWN, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} } +}; static void program_gamut_remap( @@ -223,68 +250,6 @@ void dpp1_cm_set_gamut_remap( } } -void dpp1_cm_set_output_csc_default( - struct dpp *dpp_base, - enum dc_color_space colorspace) -{ - - struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); - uint32_t ocsc_mode = 0; - - switch (colorspace) { - case COLOR_SPACE_SRGB: - case COLOR_SPACE_2020_RGB_FULLRANGE: - ocsc_mode = 0; - break; - case COLOR_SPACE_SRGB_LIMITED: - case COLOR_SPACE_2020_RGB_LIMITEDRANGE: - ocsc_mode = 1; - break; - case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YCBCR601_LIMITED: - ocsc_mode = 2; - break; - case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YCBCR709_LIMITED: - case COLOR_SPACE_2020_YCBCR: - ocsc_mode = 3; - break; - case COLOR_SPACE_UNKNOWN: - default: - break; - } - - REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); - -} - -static void dpp1_cm_get_reg_field( - struct dcn10_dpp *dpp, - struct xfer_func_reg *reg) -{ - reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; - reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; - reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; - reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; - reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; - reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; - reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; - reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; - - reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; - reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; - reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; - reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; - reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; - reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; - reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; - reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; - reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B; - reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B; - reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; - reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; -} - static void dpp1_cm_program_color_matrix( struct dcn10_dpp *dpp, const struct out_csc_color_matrix *tbl_entry) @@ -326,6 +291,57 @@ static void dpp1_cm_program_color_matrix( } } +void dpp1_cm_set_output_csc_default( + struct dpp *dpp_base, + enum dc_color_space colorspace) +{ + + struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); + struct out_csc_color_matrix tbl_entry; + int i, j; + int arr_size = sizeof(output_csc_matrix) / sizeof(struct output_csc_matrix); + uint32_t ocsc_mode = 4; + + tbl_entry.color_space = colorspace; + + for (i = 0; i < arr_size; i++) + if (output_csc_matrix[i].color_space == colorspace) { + for (j = 0; j < 12; j++) + tbl_entry.regval[j] = output_csc_matrix[i].regval[j]; + break; + } + + REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); + dpp1_cm_program_color_matrix(dpp, &tbl_entry); +} + +static void dpp1_cm_get_reg_field( + struct dcn10_dpp *dpp, + struct xfer_func_reg *reg) +{ + reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; + reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; + reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; + reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; + reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; + reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; + reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; + reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; + + reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; + reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; + reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; + reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; + reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; + reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; + reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; + reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; + reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B; + reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B; + reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; + reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; +} + void dpp1_cm_set_output_csc_adjustment( struct dpp *dpp_base, const struct out_csc_color_matrix *tbl_entry) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index b5d048b364a4..e08ad585b7b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1666,12 +1666,68 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, tbl_entry.color_space = color_space; //tbl_entry.regval = matrix; - pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry); + if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) + pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry); } else { - pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace); + if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL) + pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace); } } +//program ocsc matrix for dcn 2 +static void set_mpc_output_csc(struct dc *dc, + struct pipe_ctx *pipe_ctx, + enum dc_color_space colorspace, + uint16_t *matrix, + int opp_id) +{ + struct mpc *mpc = dc->res_pool->mpc; + int i; + struct out_csc_color_matrix tbl_entry; + enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; + + + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { + //uint16_t matrix[12]; + for (i = 0; i < 12; i++) + tbl_entry.regval[i] = matrix[i]; + tbl_entry.color_space = colorspace; + + if (mpc->funcs->set_output_csc != NULL) + mpc->funcs->set_output_csc(mpc, + opp_id, + &tbl_entry, + ocsc_mode); + } + + else { + if (mpc->funcs->set_ocsc_default != NULL) + mpc->funcs->set_ocsc_default(mpc, + opp_id, + colorspace, + ocsc_mode); + } +} + +static void program_output_csc(struct dc *dc, + struct pipe_ctx *pipe_ctx, + enum dc_color_space colorspace, + uint16_t *matrix, + int opp_id) +{ + if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) + program_csc_matrix(pipe_ctx, + colorspace, + matrix); + else + set_mpc_output_csc(dc, + pipe_ctx, + colorspace, + matrix, + opp_id); + +} + static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { if (pipe_ctx->plane_state->visible) @@ -1909,10 +1965,11 @@ static void update_dchubp_dpp( /*gamut remap*/ program_gamut_remap(pipe_ctx); - program_csc_matrix(pipe_ctx, + program_output_csc(dc, + pipe_ctx, pipe_ctx->stream->output_color_space, - pipe_ctx->stream->csc_color_matrix.matrix); - + pipe_ctx->stream->csc_color_matrix.matrix, + mpcc_cfg.opp_id); hubp->funcs->hubp_program_surface_config( hubp, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index a786d4c3935c..72ea33526a5c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -28,6 +28,12 @@ #include "dc_hw_types.h" #include "opp.h" +enum mpc_output_csc_mode { + MPC_OUTPUT_CSC_DISABLE = 0, + MPC_OUTPUT_CSC_COEF_A, + MPC_OUTPUT_CSC_COEF_B +}; + struct mpcc_cfg { int dpp_id; int opp_id; @@ -58,6 +64,16 @@ struct mpc_funcs { int (*get_opp_id)(struct mpc *mpc, int mpcc_id); + void (*set_output_csc)(struct mpc *mpc, + int opp_id, + const struct out_csc_color_matrix *tbl_entry, + enum mpc_output_csc_mode ocsc_mode); + + void (*set_ocsc_default)(struct mpc *mpc, + int opp_id, + enum dc_color_space color_space, + enum mpc_output_csc_mode ocsc_mode); + }; #endif -- GitLab From 4f804817d5cfb4bd1abf59a29721446af4b4cfd4 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Thu, 9 Nov 2017 13:55:46 -0500 Subject: [PATCH 0899/2547] drm/amd/display: Move update_plane_addr to apply_ctx_for_surface for dce. Move update_plane_addr to apply_ctx_for_surface, address update will just be called once, not twice for updat type is full and medium. This will reduce some reg access and duration time. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f8cbc4f0b1a3..fb33556eeac6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1314,8 +1314,8 @@ static void commit_planes_for_stream(struct dc *dc, if (pipe_ctx->plane_state != plane_state) continue; - if (srf_updates[i].flip_addr) - dc->hwss.update_plane_addr(dc, pipe_ctx); + if (update_type == UPDATE_TYPE_FAST && srf_updates[i].flip_addr) + dc->hwss.update_plane_addr(dc, pipe_ctx); } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 09051dfe1844..e650bdcd9423 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2881,6 +2881,9 @@ static void dce110_apply_ctx_for_surface( context->stream_count); dce110_program_front_end_for_pipe(dc, pipe_ctx); + + dc->hwss.update_plane_addr(dc, pipe_ctx); + program_surface_visibility(dc, pipe_ctx); } -- GitLab From 480bd0cf450bdabeca49f135e6f1c2a58d1bb957 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Wed, 8 Nov 2017 17:24:54 -0500 Subject: [PATCH 0900/2547] drm/amd/display: Update dchub and dpp as per update flags. Check update flags and update dchub and dpp as per flags, reduce reg access from 347 to 200, duration time reduce to 170us. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 191 +++++++++++------- 1 file changed, 117 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e08ad585b7b9..c92eba0f0df8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1878,47 +1878,10 @@ void build_prescale_params(struct dc_bias_and_scale *bias_and_scale, } } -static void update_dchubp_dpp( - struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct dc_state *context) +static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) { - struct dce_hwseq *hws = dc->hwseq; - struct hubp *hubp = pipe_ctx->plane_res.hubp; - struct dpp *dpp = pipe_ctx->plane_res.dpp; - struct dc_plane_state *plane_state = pipe_ctx->plane_state; - union plane_size size = plane_state->plane_size; - struct mpcc_cfg mpcc_cfg = {0}; - struct pipe_ctx *top_pipe; - bool per_pixel_alpha = plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; struct dc_bias_and_scale bns_params = {0}; - /* TODO: proper fix once fpga works */ - /* depends on DML calculation, DPP clock value may change dynamically */ - enable_dppclk( - dc->hwseq, - pipe_ctx->pipe_idx, - pipe_ctx->stream_res.pix_clk_params.requested_pix_clk, - context->bw.dcn.calc_clk.dppclk_div); - dc->current_state->bw.dcn.cur_clk.dppclk_div = - context->bw.dcn.calc_clk.dppclk_div; - context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; - - /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG - * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. - * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG - */ - REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst); - - hubp->funcs->hubp_setup( - hubp, - &pipe_ctx->dlg_regs, - &pipe_ctx->ttu_regs, - &pipe_ctx->rq_regs, - &pipe_ctx->pipe_dlg_param); - - size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; - // program the input csc dpp->funcs->dpp_setup(dpp, plane_state->format, @@ -1930,6 +1893,17 @@ static void update_dchubp_dpp( build_prescale_params(&bns_params, plane_state); if (dpp->funcs->dpp_program_bias_and_scale) dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); +} + +static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) +{ + struct mpcc_cfg mpcc_cfg = {0}; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct pipe_ctx *top_pipe; + bool per_pixel_alpha = + pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; + + /* TODO: proper fix once fpga works */ mpcc_cfg.dpp_id = hubp->inst; mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst; @@ -1952,33 +1926,110 @@ static void update_dchubp_dpp( && per_pixel_alpha; hubp->mpcc_id = dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg); hubp->opp_id = mpcc_cfg.opp_id; +} + +static void update_scaler(struct pipe_ctx *pipe_ctx) +{ + bool per_pixel_alpha = + pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; + + /* TODO: proper fix once fpga works */ pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; /* scaler configuration */ pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); +} - hubp->funcs->mem_program_viewport(hubp, - &pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c); +static void update_dchubp_dpp( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context) +{ + struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct dpp *dpp = pipe_ctx->plane_res.dpp; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; + union plane_size size = plane_state->plane_size; - /*gamut remap*/ - program_gamut_remap(pipe_ctx); + /* depends on DML calculation, DPP clock value may change dynamically */ + if (pipe_ctx->plane_state->update_flags.raw != 0) { + enable_dppclk( + dc->hwseq, + pipe_ctx->pipe_idx, + pipe_ctx->stream_res.pix_clk_params.requested_pix_clk, + context->bw.dcn.calc_clk.dppclk_div); + dc->current_state->bw.dcn.cur_clk.dppclk_div = + context->bw.dcn.calc_clk.dppclk_div; + context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; + } - program_output_csc(dc, - pipe_ctx, - pipe_ctx->stream->output_color_space, - pipe_ctx->stream->csc_color_matrix.matrix, - mpcc_cfg.opp_id); - - hubp->funcs->hubp_program_surface_config( - hubp, - plane_state->format, - &plane_state->tiling_info, - &size, - plane_state->rotation, - &plane_state->dcc, - plane_state->horizontal_mirror); + /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG + * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. + * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG + */ + if (plane_state->update_flags.bits.full_update) { + REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst); + + hubp->funcs->hubp_setup( + hubp, + &pipe_ctx->dlg_regs, + &pipe_ctx->ttu_regs, + &pipe_ctx->rq_regs, + &pipe_ctx->pipe_dlg_param); + } + + size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; + + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.bpp_change) + update_dpp(dpp, plane_state); + + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.per_pixel_alpha_change) + update_mpcc(dc, pipe_ctx); + + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.per_pixel_alpha_change || + plane_state->update_flags.bits.scaling_change || + plane_state->update_flags.bits.position_change) { + update_scaler(pipe_ctx); + } + + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.scaling_change) { + hubp->funcs->mem_program_viewport( + hubp, + &pipe_ctx->plane_res.scl_data.viewport, + &pipe_ctx->plane_res.scl_data.viewport_c); + } + + if (plane_state->update_flags.bits.full_update) { + /*gamut remap*/ + program_gamut_remap(pipe_ctx); + + program_output_csc(dc, + pipe_ctx, + pipe_ctx->stream->output_color_space, + pipe_ctx->stream->csc_color_matrix.matrix, + hubp->opp_id); + } + + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.horizontal_mirror_change || + plane_state->update_flags.bits.rotation_change || + plane_state->update_flags.bits.swizzle_change || + plane_state->update_flags.bits.bpp_change) { + hubp->funcs->hubp_program_surface_config( + hubp, + plane_state->format, + &plane_state->tiling_info, + &size, + plane_state->rotation, + &plane_state->dcc, + plane_state->horizontal_mirror); + } hubp->power_gated = false; @@ -2019,8 +2070,7 @@ static void program_all_pipe_in_tree( if (pipe_ctx->plane_state->update_flags.bits.full_update) dcn10_enable_plane(dc, pipe_ctx, context); - if (pipe_ctx->plane_state->update_flags.raw != 0) - update_dchubp_dpp(dc, pipe_ctx, context); + update_dchubp_dpp(dc, pipe_ctx, context); if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); @@ -2181,26 +2231,18 @@ static void dcn10_apply_ctx_for_surface( } if (num_planes > 0) { - struct dc_stream_state *stream_for_cursor = NULL; - program_all_pipe_in_tree(dc, top_pipe_to_program, context); - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - - if (stream == pipe_ctx->stream) { - stream_for_cursor = pipe_ctx->stream; - break; - } - } - /* TODO: this is a hack w/a for switching from mpo to pipe split */ - if (stream_for_cursor->cursor_attributes.address.quad_part != 0) { + if (stream->cursor_attributes.address.quad_part != 0) { struct dc_cursor_position position = { 0 }; - dc_stream_set_cursor_position(stream_for_cursor, &position); - dc_stream_set_cursor_attributes(stream_for_cursor, - &stream_for_cursor->cursor_attributes); + dc_stream_set_cursor_position( + (struct dc_stream_state *)stream, + &position); + dc_stream_set_cursor_attributes( + (struct dc_stream_state *)stream, + &stream->cursor_attributes); } } @@ -2227,7 +2269,7 @@ static void dcn10_apply_ctx_for_surface( dcn10_verify_allow_pstate_change_high(dc); } - dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, +/* dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, "\n============== Watermark parameters ==============\n" "a.urgent_ns: %d \n" "a.cstate_enter_plus_exit: %d \n" @@ -2273,6 +2315,7 @@ static void dcn10_apply_ctx_for_surface( context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns, context->bw.dcn.watermarks.d.pte_meta_urgent_ns ); +*/ if (dc->debug.sanity_checks) dcn10_verify_allow_pstate_change_high(dc); -- GitLab From 125d10a23347269abf88b05f919d33f4120b82cb Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Thu, 9 Nov 2017 15:56:25 -0500 Subject: [PATCH 0901/2547] drm/amd/display: fix opp header register define Signed-off-by: Yue Hin Lau Reviewed-by: Eric Bernstein Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 25 +++++++++++-------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index 4b1e51050d33..f3c298ec37fb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -46,6 +46,16 @@ #define OPP_REG_LIST_DCN10(id) \ OPP_REG_LIST_DCN(id) +#define OPP_COMMON_REG_VARIABLE_LIST \ + uint32_t FMT_BIT_DEPTH_CONTROL; \ + uint32_t FMT_CONTROL; \ + uint32_t FMT_DITHER_RAND_R_SEED; \ + uint32_t FMT_DITHER_RAND_G_SEED; \ + uint32_t FMT_DITHER_RAND_B_SEED; \ + uint32_t FMT_CLAMP_CNTL; \ + uint32_t FMT_DYNAMIC_EXP_CNTL; \ + uint32_t FMT_MAP420_MEMORY_CONTROL; + #define OPP_MASK_SH_LIST_DCN(mask_sh) \ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \ @@ -97,6 +107,10 @@ type FMT_MAP420MEM_PWR_FORCE; \ type FMT_STEREOSYNC_OVERRIDE; +struct dcn10_opp_registers { + OPP_COMMON_REG_VARIABLE_LIST +}; + struct dcn10_opp_shift { OPP_DCN10_REG_FIELD_LIST(uint8_t) }; @@ -105,17 +119,6 @@ struct dcn10_opp_mask { OPP_DCN10_REG_FIELD_LIST(uint32_t) }; -struct dcn10_opp_registers { - uint32_t FMT_BIT_DEPTH_CONTROL; - uint32_t FMT_CONTROL; - uint32_t FMT_DITHER_RAND_R_SEED; - uint32_t FMT_DITHER_RAND_G_SEED; - uint32_t FMT_DITHER_RAND_B_SEED; - uint32_t FMT_CLAMP_CNTL; - uint32_t FMT_DYNAMIC_EXP_CNTL; - uint32_t FMT_MAP420_MEMORY_CONTROL; -}; - struct dcn10_opp { struct output_pixel_processor base; -- GitLab From a9beb6c741fb8716a19821b7662b81dfd23751d7 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 1 Nov 2017 12:05:35 -0400 Subject: [PATCH 0902/2547] drm/amd/display: Remove unnecessary dc_link vtable None of this needs to be a function table or dynamic in any way. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 89 ------------------------ drivers/gpu/drm/amd/display/dc/dc.h | 20 ------ 2 files changed, 109 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index fb33556eeac6..4b683a9636f3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -239,93 +239,6 @@ void dc_stream_set_static_screen_events(struct dc *dc, dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events); } -static void set_drive_settings(struct dc *dc, - struct link_training_settings *lt_settings, - const struct dc_link *link) -{ - - int i; - - for (i = 0; i < dc->link_count; i++) { - if (dc->links[i] == link) - break; - } - - if (i >= dc->link_count) - ASSERT_CRITICAL(false); - - dc_link_dp_set_drive_settings(dc->links[i], lt_settings); -} - -static void perform_link_training(struct dc *dc, - struct dc_link_settings *link_setting, - bool skip_video_pattern) -{ - int i; - - for (i = 0; i < dc->link_count; i++) - dc_link_dp_perform_link_training( - dc->links[i], - link_setting, - skip_video_pattern); -} - -static void set_preferred_link_settings(struct dc *dc, - struct dc_link_settings *link_setting, - struct dc_link *link) -{ - link->preferred_link_setting = *link_setting; - dp_retrain_link_dp_test(link, link_setting, false); -} - -static void enable_hpd(const struct dc_link *link) -{ - dc_link_dp_enable_hpd(link); -} - -static void disable_hpd(const struct dc_link *link) -{ - dc_link_dp_disable_hpd(link); -} - - -static void set_test_pattern( - struct dc_link *link, - enum dp_test_pattern test_pattern, - const struct link_training_settings *p_link_settings, - const unsigned char *p_custom_pattern, - unsigned int cust_pattern_size) -{ - if (link != NULL) - dc_link_dp_set_test_pattern( - link, - test_pattern, - p_link_settings, - p_custom_pattern, - cust_pattern_size); -} - -static void allocate_dc_stream_funcs(struct dc *dc) -{ - dc->link_funcs.set_drive_settings = - set_drive_settings; - - dc->link_funcs.perform_link_training = - perform_link_training; - - dc->link_funcs.set_preferred_link_settings = - set_preferred_link_settings; - - dc->link_funcs.enable_hpd = - enable_hpd; - - dc->link_funcs.disable_hpd = - disable_hpd; - - dc->link_funcs.set_test_pattern = - set_test_pattern; -} - static void destruct(struct dc *dc) { dc_release_state(dc->current_state); @@ -502,8 +415,6 @@ static bool construct(struct dc *dc, if (!create_links(dc, init_params->num_virtual_links)) goto fail; - allocate_dc_stream_funcs(dc); - return true; fail: diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index dbb03b3e2c23..95d9406b0a6a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -146,25 +146,6 @@ struct dc_cap_funcs { struct link_training_settings; -struct dc_link_funcs { - void (*set_drive_settings)(struct dc *dc, - struct link_training_settings *lt_settings, - const struct dc_link *link); - void (*perform_link_training)(struct dc *dc, - struct dc_link_settings *link_setting, - bool skip_video_pattern); - void (*set_preferred_link_settings)(struct dc *dc, - struct dc_link_settings *link_setting, - struct dc_link *link); - void (*enable_hpd)(const struct dc_link *link); - void (*disable_hpd)(const struct dc_link *link); - void (*set_test_pattern)( - struct dc_link *link, - enum dp_test_pattern test_pattern, - const struct link_training_settings *p_link_settings, - const unsigned char *p_custom_pattern, - unsigned int cust_pattern_size); -}; /* Structure to hold configuration flags set by dm at dc creation. */ struct dc_config { @@ -237,7 +218,6 @@ struct dce_hwseq; struct dc { struct dc_caps caps; struct dc_cap_funcs cap_funcs; - struct dc_link_funcs link_funcs; struct dc_config config; struct dc_debug debug; -- GitLab From dce46c53208f90cf5a401b62b17bbe2bc629c069 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Wed, 8 Nov 2017 16:07:53 -0500 Subject: [PATCH 0903/2547] drm/amd/display: performance profiling instrumentation Signed-off-by: Tony Cheng Reviewed-by: Yongqiang Sun Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 4 ++++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 ++++ drivers/gpu/drm/amd/display/dc/dm_services.h | 7 +++++++ 3 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index 82269caedc07..56e549249134 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -41,6 +41,10 @@ unsigned long long dm_get_timestamp(struct dc_context *ctx) return 0; } +void dm_perf_trace_timestamp(const char *func_name, unsigned int line) +{ +} + bool dm_write_persistent_data(struct dc_context *ctx, const struct dc_sink *sink, const char *module_name, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index c92eba0f0df8..ad0e3b9be055 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1047,6 +1047,8 @@ dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) return false; + PERF_TRACE(); + arr_points = regamma_params->arr_points; rgb_resulted = regamma_params->rgb_resulted; hw_points = 0; @@ -1189,6 +1191,8 @@ dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, convert_to_custom_float(rgb_resulted, arr_points, hw_points); + PERF_TRACE(); + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index d4917037ac42..225b7bfb09a9 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -372,6 +372,13 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id); unsigned long long dm_get_timestamp(struct dc_context *ctx); +/* + * performance tracing + */ +void dm_perf_trace_timestamp(const char *func_name, unsigned int line); +#define PERF_TRACE() dm_perf_trace_timestamp(__func__, __LINE__) + + /* * Debug and verification hooks */ -- GitLab From 675634c5aba341b2fee890fb93b3d3649ac5ce0b Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Fri, 10 Nov 2017 15:40:52 -0500 Subject: [PATCH 0904/2547] drm/amd/display: Only update output transfer function for full type. dcn10_translate_regamma_to_hw_format costs 750us to run, it cannot be called within isr, check update flag before calling, only do it for full update. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 23 +++++++++++++------ 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index ad0e3b9be055..39869d379e3f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1211,9 +1211,17 @@ dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx, stream->out_transfer_func->type == TF_TYPE_PREDEFINED && stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB); - else if (dcn10_translate_regamma_to_hw_format(stream->out_transfer_func, &dpp->regamma_params)) - dpp->funcs->dpp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER); - else + + /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full + * update. + */ + else if (dcn10_translate_regamma_to_hw_format( + stream->out_transfer_func, + &dpp->regamma_params)) { + dpp->funcs->dpp_program_regamma_pwl( + dpp, + &dpp->regamma_params, OPP_REGAMMA_USER); + } else dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS); return true; @@ -2076,16 +2084,17 @@ static void program_all_pipe_in_tree( update_dchubp_dpp(dc, pipe_ctx, context); - if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { + if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); - } - /* + /* dcn10_translate_regamma_to_hw_format takes 750us to finish + * only do gamma programming for full update. * TODO: This can be further optimized/cleaned up * Always call this for now since it does memcmp inside before * doing heavy calculation and programming */ - dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); + if (pipe_ctx->plane_state->update_flags.bits.full_update) + dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); } if (dc->debug.sanity_checks) { -- GitLab From 4a43586bac9ae1d092d23c1cfe937cf05caa4c0d Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Thu, 9 Nov 2017 17:03:00 -0500 Subject: [PATCH 0905/2547] drm/amd/display: update output csc matrix values Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 33 +++++++++---------- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 +-- 2 files changed, 16 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index b5541985e0d8..b601a00fff74 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -123,29 +123,26 @@ struct output_csc_matrix { }; static const struct output_csc_matrix output_csc_matrix[] = { - { COLOR_SPACE_SRGB, + { COLOR_SPACE_SRGB, { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, - { COLOR_SPACE_SRGB_LIMITED, - { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} }, - { COLOR_SPACE_YCBCR601, - { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47, - 0xF6B9, 0xE00, 0x1000} }, - { COLOR_SPACE_YCBCR709, - { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA, - 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, - - /* TODO: correct values below */ - { COLOR_SPACE_YCBCR601_LIMITED, + { COLOR_SPACE_SRGB_LIMITED, + { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 0x201} }, + { COLOR_SPACE_YCBCR601, + { 0xE04, 0xF444, 0xFDB9, 0x1004, 0x831, 0x1016, 0x320, 0x201, 0xFB45, + 0xF6B7, 0xE04, 0x1004} }, + { COLOR_SPACE_YCBCR709, + { 0xE04, 0xF345, 0xFEB7, 0x1004, 0x5D3, 0x1399, 0x1FA, + 0x201, 0xFCCA, 0xF533, 0xE04, 0x1004} }, + + /* TODO: correct values below */ + { COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, - 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, - { COLOR_SPACE_YCBCR709_LIMITED, + 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, + { COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, - 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, - { COLOR_SPACE_UNKNOWN, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} } + 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, }; - static void program_gamut_remap( struct dcn10_dpp *dpp, const uint16_t *regval, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 39869d379e3f..9641b36cbad4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1686,7 +1686,6 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, } } -//program ocsc matrix for dcn 2 static void set_mpc_output_csc(struct dc *dc, struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace, @@ -1710,9 +1709,7 @@ static void set_mpc_output_csc(struct dc *dc, opp_id, &tbl_entry, ocsc_mode); - } - - else { + } else { if (mpc->funcs->set_ocsc_default != NULL) mpc->funcs->set_ocsc_default(mpc, opp_id, -- GitLab From c1f103fc20818ba29022a70cf10077bca78d759c Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Fri, 10 Nov 2017 23:23:24 -0500 Subject: [PATCH 0906/2547] drm/amd/display: dal 3.1.17 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 95d9406b0a6a..8951c11882d9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.16" +#define DC_VER "3.1.17" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From e56dc89b3c6619bb2c4985da13d6f0dfe2711397 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Mon, 13 Nov 2017 14:55:07 -0500 Subject: [PATCH 0907/2547] drm/amd/display: move csc matrix to hw_shared Signed-off-by: Yue Hin Lau Reviewed-by: Eric Bernstein Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 26 ------------------- .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 26 +++++++++++++++++++ 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index b601a00fff74..4c90043e7b8c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -117,32 +117,6 @@ static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = { 0x2568, 0x43ee, 0xdbb2} } }; -struct output_csc_matrix { - enum dc_color_space color_space; - uint16_t regval[12]; -}; - -static const struct output_csc_matrix output_csc_matrix[] = { - { COLOR_SPACE_SRGB, - { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, - { COLOR_SPACE_SRGB_LIMITED, - { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 0x201} }, - { COLOR_SPACE_YCBCR601, - { 0xE04, 0xF444, 0xFDB9, 0x1004, 0x831, 0x1016, 0x320, 0x201, 0xFB45, - 0xF6B7, 0xE04, 0x1004} }, - { COLOR_SPACE_YCBCR709, - { 0xE04, 0xF345, 0xFEB7, 0x1004, 0x5D3, 0x1399, 0x1FA, - 0x201, 0xFCCA, 0xF533, 0xE04, 0x1004} }, - - /* TODO: correct values below */ - { COLOR_SPACE_YCBCR601_LIMITED, - { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, - 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, - { COLOR_SPACE_YCBCR709_LIMITED, - { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, - 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, -}; - static void program_gamut_remap( struct dcn10_dpp *dpp, const uint16_t *regval, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index a650ede413d1..ddc56700109b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -131,6 +131,32 @@ struct out_csc_color_matrix { uint16_t regval[12]; }; +struct output_csc_matrix { + enum dc_color_space color_space; + uint16_t regval[12]; +}; + +static const struct output_csc_matrix output_csc_matrix[] = { + { COLOR_SPACE_SRGB, + { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, + { COLOR_SPACE_SRGB_LIMITED, + { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 0x201} }, + { COLOR_SPACE_YCBCR601, + { 0xE04, 0xF444, 0xFDB9, 0x1004, 0x831, 0x1016, 0x320, 0x201, 0xFB45, + 0xF6B7, 0xE04, 0x1004} }, + { COLOR_SPACE_YCBCR709, + { 0xE04, 0xF345, 0xFEB7, 0x1004, 0x5D3, 0x1399, 0x1FA, + 0x201, 0xFCCA, 0xF533, 0xE04, 0x1004} }, + + /* TODO: correct values below */ + { COLOR_SPACE_YCBCR601_LIMITED, + { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, + 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, + { COLOR_SPACE_YCBCR709_LIMITED, + { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, + 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, +}; + enum opp_regamma { OPP_REGAMMA_BYPASS = 0, OPP_REGAMMA_SRGB, -- GitLab From 26247e77790c00e65e8040416f116519ae7ed1b3 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Mon, 6 Nov 2017 13:50:06 -0500 Subject: [PATCH 0908/2547] drm/amd/display: fix mpo validation failure There was an error in translation of mode support check. "N/A" is a failure condition while "" was a special case. This change will differentiate between the two by using a define. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dml/display_mode_vba.c | 120 ++++++------------ 1 file changed, 36 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c index ea661ee44674..a02c69d10399 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -28,6 +28,8 @@ #include "dml_inline_defs.h" +#define BPP_INVALID 0 +#define BPP_BLENDED_PIPE 0xffffffff static const unsigned int NumberOfStates = DC__VOLTAGE_STATES; static void fetch_socbb_params(struct display_mode_lib *mode_lib); @@ -3928,7 +3930,7 @@ static unsigned int TruncToValidBPP( else if (DecimalBPP >= 12) return 12; else - return 0; + return BPP_INVALID; } else if (Format == dm_444) { if (DecimalBPP >= 36) return 36; @@ -3937,7 +3939,7 @@ static unsigned int TruncToValidBPP( else if (DecimalBPP >= 24) return 24; else - return 0; + return BPP_INVALID; } else { if (DecimalBPP / 1.5 >= 24) return 24; @@ -3946,27 +3948,27 @@ static unsigned int TruncToValidBPP( else if (DecimalBPP / 1.5 >= 16) return 16; else - return 0; + return BPP_INVALID; } } else { if (DSCEnabled) { if (Format == dm_420) { if (DecimalBPP < 6) - return 0; + return BPP_INVALID; else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1 / 16) return 1.5 * DSCInputBitPerComponent - 1 / 16; else return dml_floor(16 * DecimalBPP, 1) / 16; } else if (Format == dm_n422) { if (DecimalBPP < 7) - return 0; + return BPP_INVALID; else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1 / 16) return 2 * DSCInputBitPerComponent - 1 / 16; else return dml_floor(16 * DecimalBPP, 1) / 16; } else { if (DecimalBPP < 8) - return 0; + return BPP_INVALID; else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1 / 16) return 3 * DSCInputBitPerComponent - 1 / 16; else @@ -3980,7 +3982,7 @@ static unsigned int TruncToValidBPP( else if (DecimalBPP >= 12) return 12; else - return 0; + return BPP_INVALID; } else if (Format == dm_s422 || Format == dm_n422) { if (DecimalBPP >= 24) return 24; @@ -3989,7 +3991,7 @@ static unsigned int TruncToValidBPP( else if (DecimalBPP >= 16) return 16; else - return 0; + return BPP_INVALID; } else { if (DecimalBPP >= 36) return 36; @@ -3998,7 +4000,7 @@ static unsigned int TruncToValidBPP( else if (DecimalBPP >= 24) return 24; else - return 0; + return BPP_INVALID; } } } @@ -4922,11 +4924,7 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ mode_lib->vba.ViewportSizeSupport[i] = true; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { if (mode_lib->vba.ODMCombineEnablePerState[i][k] == true) { - if (dml_min( - mode_lib->vba.SwathWidthYSingleDPP[k], - dml_round( - mode_lib->vba.HActive[k] / 2.0 - * mode_lib->vba.HRatio[k])) + if (dml_min(mode_lib->vba.SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k])) > mode_lib->vba.MaximumSwathWidth[k]) { mode_lib->vba.ViewportSizeSupport[i] = false; } @@ -4980,12 +4978,8 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ mode_lib->vba.RequiresDSC[i][k] = 0; mode_lib->vba.RequiresFEC[i][k] = 0; mode_lib->vba.OutputBppPerState[i][k] = - TruncToValidBPP( - dml_min( - 600.0, - mode_lib->vba.PHYCLKPerState[i]) - / mode_lib->vba.PixelClockBackEnd[k] - * 24, + TruncToValidBPP(dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) + / mode_lib->vba.PixelClockBackEnd[k] * 24, false, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], @@ -5000,30 +4994,16 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ } if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { mode_lib->vba.Outbpp = - TruncToValidBPP( - (1.0 - - mode_lib->vba.Downspreading - / 100.0) - * 270.0 - * mode_lib->vba.OutputLinkDPLanes[k] - / mode_lib->vba.PixelClockBackEnd[k] - * 8.0, + TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) * 270.0 + * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, false, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.DSCInputBitPerComponent[k]); mode_lib->vba.OutbppDSC = - TruncToValidBPP( - (1.0 - - mode_lib->vba.Downspreading - / 100.0) - * (1.0 - - mode_lib->vba.EffectiveFECOverhead - / 100.0) - * 270.0 - * mode_lib->vba.OutputLinkDPLanes[k] - / mode_lib->vba.PixelClockBackEnd[k] - * 8.0, + TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) + * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 270.0 + * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, true, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], @@ -5046,32 +5026,18 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ mode_lib->vba.OutputBppPerState[i][k] = mode_lib->vba.Outbpp; } - if (mode_lib->vba.Outbpp == 0) { + if (mode_lib->vba.Outbpp == BPP_INVALID) { mode_lib->vba.Outbpp = - TruncToValidBPP( - (1.0 - - mode_lib->vba.Downspreading - / 100.0) - * 540.0 - * mode_lib->vba.OutputLinkDPLanes[k] - / mode_lib->vba.PixelClockBackEnd[k] - * 8.0, + TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) * 540.0 + * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, false, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.DSCInputBitPerComponent[k]); mode_lib->vba.OutbppDSC = - TruncToValidBPP( - (1.0 - - mode_lib->vba.Downspreading - / 100.0) - * (1.0 - - mode_lib->vba.EffectiveFECOverhead - / 100.0) - * 540.0 - * mode_lib->vba.OutputLinkDPLanes[k] - / mode_lib->vba.PixelClockBackEnd[k] - * 8.0, + TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) + * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 540.0 + * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, true, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], @@ -5094,40 +5060,26 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ mode_lib->vba.OutputBppPerState[i][k] = mode_lib->vba.Outbpp; } - if (mode_lib->vba.Outbpp == 0 + if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 810.0) { mode_lib->vba.Outbpp = - TruncToValidBPP( - (1.0 - - mode_lib->vba.Downspreading - / 100.0) - * 810.0 - * mode_lib->vba.OutputLinkDPLanes[k] - / mode_lib->vba.PixelClockBackEnd[k] - * 8.0, + TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) * 810.0 + * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, false, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.DSCInputBitPerComponent[k]); mode_lib->vba.OutbppDSC = - TruncToValidBPP( - (1.0 - - mode_lib->vba.Downspreading - / 100.0) - * (1.0 - - mode_lib->vba.EffectiveFECOverhead - / 100.0) - * 810.0 - * mode_lib->vba.OutputLinkDPLanes[k] - / mode_lib->vba.PixelClockBackEnd[k] - * 8.0, + TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) + * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 810.0 + * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, true, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.DSCInputBitPerComponent[k]); if (mode_lib->vba.DSCEnabled[k] == true - || mode_lib->vba.Outbpp == 0) { + || mode_lib->vba.Outbpp == BPP_INVALID) { mode_lib->vba.RequiresDSC[i][k] = true; if (mode_lib->vba.Output[k] == dm_dp) { mode_lib->vba.RequiresFEC[i][k] = @@ -5147,14 +5099,14 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ } } } else { - mode_lib->vba.OutputBppPerState[i][k] = 0; + mode_lib->vba.OutputBppPerState[i][k] = BPP_BLENDED_PIPE; } } } for (i = 0; i <= DC__VOLTAGE_STATES; i++) { mode_lib->vba.DIOSupport[i] = true; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - if (mode_lib->vba.OutputBppPerState[i][k] == 0 + if (mode_lib->vba.OutputBppPerState[i][k] == BPP_INVALID || (mode_lib->vba.OutputFormat[k] == dm_420 && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) { @@ -5243,8 +5195,8 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ } else { mode_lib->vba.slices = 1.0; } - if (mode_lib->vba.OutputBppPerState[i][k] == 0 - || mode_lib->vba.OutputBppPerState[i][k] == 0) { + if (mode_lib->vba.OutputBppPerState[i][k] == BPP_BLENDED_PIPE + || mode_lib->vba.OutputBppPerState[i][k] == BPP_INVALID) { mode_lib->vba.bpp = 0.0; } else { mode_lib->vba.bpp = mode_lib->vba.OutputBppPerState[i][k]; -- GitLab From fb7ae8505eb890224112925eed690106e2f3ca24 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Thu, 9 Nov 2017 15:05:52 -0500 Subject: [PATCH 0909/2547] drm/amd/display: fix refclk conversion from khz int to mhz float Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 88a004cc2690..b6b0872f50dd 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -432,7 +432,7 @@ static void dcn_bw_calc_rq_dlg_ttu( input.clks_cfg.dcfclk_mhz = v->dcfclk; input.clks_cfg.dispclk_mhz = v->dispclk; input.clks_cfg.dppclk_mhz = v->dppclk; - input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz/1000; + input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz / 1000.0; input.clks_cfg.socclk_mhz = v->socclk; input.clks_cfg.voltage = v->voltage_level; // dc->dml.logger = pool->base.logger; -- GitLab From 69cff5a4e35077d1e6d2527559eab09621a8ead6 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Thu, 9 Nov 2017 16:02:56 -0500 Subject: [PATCH 0910/2547] drm/amd/display: Rename output_bpc to opp_input_bpc Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 12 ------------ .../drm/amd/display/dc/dml/display_mode_structs.h | 2 +- .../gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 +- 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index b6b0872f50dd..f37fb7c3bf7d 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -439,18 +439,6 @@ static void dcn_bw_calc_rq_dlg_ttu( input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444; input.dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp; //input[in_idx].dout.output_standard; - switch (v->output_deep_color[in_idx]) { - case dcn_bw_encoder_12bpc: - input.dout.output_bpc = dm_out_12; - break; - case dcn_bw_encoder_10bpc: - input.dout.output_bpc = dm_out_10; - break; - case dcn_bw_encoder_8bpc: - default: - input.dout.output_bpc = dm_out_8; - break; - } /*todo: soc->sr_enter_plus_exit_time??*/ dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h index baf182177736..2d9d6298f0d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h @@ -229,7 +229,7 @@ struct _vcs_dpi_display_output_params_st { int output_bpp; int dsc_enable; int wb_enable; - int output_bpc; + int opp_input_bpc; int output_type; int output_format; int output_standard; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c index a02c69d10399..1f337ecfeab0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -589,7 +589,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] = dout->dsc_slices; mode_lib->vba.DSCInputBitPerComponent[mode_lib->vba.NumberOfActivePlanes] = - dout->output_bpc == 0 ? 12 : dout->output_bpc; + dout->opp_input_bpc == 0 ? 12 : dout->opp_input_bpc; mode_lib->vba.WritebackEnable[mode_lib->vba.NumberOfActivePlanes] = dout->wb_enable; mode_lib->vba.WritebackSourceHeight[mode_lib->vba.NumberOfActivePlanes] = dout->wb.wb_src_height; -- GitLab From 000b59ea9f8360a3e82efe1f4adef4d215ba18c8 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Thu, 9 Nov 2017 15:33:43 -0500 Subject: [PATCH 0911/2547] drm/amd/display: Trigger full update on plane change With the optimized DCN10 frontend programming code, things are programmed only when requested. For now, trigger a full update on all plane changes. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 41e829ac2a57..c12331e63816 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4703,6 +4703,11 @@ static int dm_update_planes_state(struct dc *dc, return ret; } + /* Tell DC to do a full surface update every time there + * is a plane change. Inefficient, but works for now. + */ + dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; + *lock_and_validation_needed = true; } } -- GitLab From 27b3f4fc91e1df74aa15f669c9b032d73dee2ef8 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Fri, 10 Nov 2017 16:12:08 -0500 Subject: [PATCH 0912/2547] drm/amd/display: Do not program front-end twice The sequence of front-end > back-end > front-end programming will program the front-end more than once. Add a mode_changed flag, and use it to determine whether the front-end should be programmed before, or after back-end. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +++++++++++++++++++ drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ++++++++--- drivers/gpu/drm/amd/display/dc/dc_stream.h | 3 +++ 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c12331e63816..533f730ff648 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4009,6 +4009,19 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, } } +/** + * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC + * @crtc_state: the DRM CRTC state + * @stream_state: the DC stream state. + * + * Copy the mirrored transient state flags from DRM, to DC. It is used to bring + * a dc_stream_state's flags in sync with a drm_crtc_state's flags. + */ +static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, + struct dc_stream_state *stream_state) +{ + stream_state->mode_changed = crtc_state->mode_changed; +} static int amdgpu_dm_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, @@ -4079,6 +4092,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) new_crtc_state->active_changed, new_crtc_state->connectors_changed); + /* Copy all transient state flags into dc state */ + if (dm_new_crtc_state->stream) { + amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, + dm_new_crtc_state->stream); + } + /* handles headless hotplug case, updating new_state and * aconnector as needed */ @@ -4563,6 +4582,7 @@ static int dm_update_crtcs_state(struct dc *dc, WARN_ON(dm_new_crtc_state->stream); dm_new_crtc_state->stream = new_stream; + dc_stream_retain(new_stream); DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 4b683a9636f3..727f68b39fce 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -672,10 +672,13 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c /* re-program planes for existing stream, in case we need to * free up plane resource for later use */ - for (i = 0; i < dc->current_state->stream_count; i++) { + for (i = 0; i < context->stream_count; i++) { + if (context->streams[i]->mode_changed) + continue; + dc->hwss.apply_ctx_for_surface( - dc, dc->current_state->streams[i], - dc->current_state->stream_status[i].plane_count, + dc, context->streams[i], + context->stream_status[i].plane_count, context); /* use new pipe config in new context */ } @@ -701,6 +704,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c for (i = 0; i < context->stream_count; i++) { const struct dc_sink *sink = context->streams[i]->sink; + if (!context->streams[i]->mode_changed) + continue; + dc->hwss.apply_ctx_for_surface( dc, context->streams[i], context->stream_status[i].plane_count, diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 9a64cf16c798..fed0e5ea9625 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -92,6 +92,9 @@ struct dc_stream_state { struct crtc_trigger_info triggered_crtc_reset; + /* Computed state bits */ + bool mode_changed : 1; + }; struct dc_stream_update { -- GitLab From 7260d1187eb5c81b6c0b0d310bf281bed46a4627 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Mon, 13 Nov 2017 17:09:12 -0500 Subject: [PATCH 0913/2547] drm/amd/display: Set full update flag in dcn_validate_bandwidth Doing bandwidth validation implies that this is a full update. Set the flag inside the function in case whatever is calling dcn_validate_bandwidth doesn't set it. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index f37fb7c3bf7d..a4fbca34bcdf 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -1013,6 +1013,8 @@ bool dcn_validate_bandwidth( if (pipe->plane_state) { struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; + pipe->plane_state->update_flags.bits.full_update = 1; + if (v->dpp_per_plane[input_idx] == 2 || ((pipe->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || -- GitLab From f97da580cf42dd43fa7e5bbb8e434f7761249bfd Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Mon, 13 Nov 2017 18:02:57 -0500 Subject: [PATCH 0914/2547] drm/amd/display: dal 3.1.18 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 8951c11882d9..4a15f9c7068a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.17" +#define DC_VER "3.1.18" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From 8980aa3c9ed63f703fd5e0bff6a53b6ba1356ae1 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Mon, 13 Nov 2017 17:22:17 -0500 Subject: [PATCH 0915/2547] drm/amd/display: Only program watermark for full update. For scaling and position change, it isn't necessary to program watermark and check P-State as well. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 3 ++ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 46 ++++++++----------- 3 files changed, 23 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 727f68b39fce..d1488d5ee028 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1178,9 +1178,7 @@ static void commit_planes_for_stream(struct dc *dc, if (update_type == UPDATE_TYPE_FULL) { dc->hwss.set_bandwidth(dc, context, false); context_clock_trace(dc, context); - } - if (update_type > UPDATE_TYPE_FAST) { for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -1215,7 +1213,7 @@ static void commit_planes_for_stream(struct dc *dc, } } - if (update_type > UPDATE_TYPE_FAST) + if (update_type == UPDATE_TYPE_FULL) context_timing_trace(dc, &context->res_ctx); /* Perform requested Updates */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c index 4b5b70907202..3eb824debf43 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c @@ -651,6 +651,8 @@ void dpp1_dscl_set_scaler_manual_scale( if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) return; + PERF_TRACE(); + dpp->scl_data = *scl_data; /* Recout */ @@ -704,4 +706,5 @@ void dpp1_dscl_set_scaler_manual_scale( SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1); dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr); + PERF_TRACE(); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 9641b36cbad4..522adceaf5d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2056,11 +2056,6 @@ static void program_all_pipe_in_tree( { if (pipe_ctx->top_pipe == NULL) { - if (dc->debug.sanity_checks) { - /* pstate stuck check after watermark update */ - dcn10_verify_allow_pstate_change_high(dc); - } - pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset; pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start; pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset; @@ -2094,11 +2089,6 @@ static void program_all_pipe_in_tree( dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); } - if (dc->debug.sanity_checks) { - /* pstate stuck check after each pipe is programmed */ - dcn10_verify_allow_pstate_change_high(dc); - } - if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context); } @@ -2183,6 +2173,7 @@ static void dcn10_apply_ctx_for_surface( struct timing_generator *tg; bool removed_pipe[4] = { false }; unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000; + bool program_water_mark = false; struct pipe_ctx *top_pipe_to_program = find_top_pipe_for_stream(dc, context, stream); @@ -2192,9 +2183,6 @@ static void dcn10_apply_ctx_for_surface( tg = top_pipe_to_program->stream_res.tg; - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); - tg->funcs->lock(tg); if (num_planes == 0) { @@ -2261,24 +2249,31 @@ static void dcn10_apply_ctx_for_surface( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream == stream && + pipe_ctx->plane_state && + pipe_ctx->plane_state->update_flags.bits.full_update) + program_water_mark = true; if (removed_pipe[i] && num_planes == 0) dcn10_disable_plane(dc, old_pipe_ctx); } - if (dc->debug.sanity_checks) { - /* pstate stuck check after watermark update */ - dcn10_verify_allow_pstate_change_high(dc); - } - /* watermark is for all pipes */ - hubbub1_program_watermarks(dc->res_pool->hubbub, - &context->bw.dcn.watermarks, ref_clk_mhz); + if (program_water_mark) { + if (dc->debug.sanity_checks) { + /* pstate stuck check after watermark update */ + dcn10_verify_allow_pstate_change_high(dc); + } + /* watermark is for all pipes */ + hubbub1_program_watermarks(dc->res_pool->hubbub, + &context->bw.dcn.watermarks, ref_clk_mhz); - if (dc->debug.sanity_checks) { - /* pstate stuck check after watermark update */ - dcn10_verify_allow_pstate_change_high(dc); + if (dc->debug.sanity_checks) { + /* pstate stuck check after watermark update */ + dcn10_verify_allow_pstate_change_high(dc); + } } - /* dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, "\n============== Watermark parameters ==============\n" "a.urgent_ns: %d \n" @@ -2326,9 +2321,6 @@ static void dcn10_apply_ctx_for_surface( context->bw.dcn.watermarks.d.pte_meta_urgent_ns ); */ - - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); } static void dcn10_set_bandwidth( -- GitLab From 404dfe1c564434cddf259b8bc1df34a55d05d934 Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Mon, 13 Nov 2017 10:54:59 -0500 Subject: [PATCH 0916/2547] drm/amd/display: DMCU and ABM maintenance and refactor Remove some globals that should really be per block state. Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 32 ++++++++----------- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 18 ++++++----- drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 10 ++++++ drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h | 4 ++- 4 files changed, 36 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c index 0e0336c5af4e..3fe8e697483f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c @@ -51,16 +51,6 @@ #define MCP_DISABLE_ABM_IMMEDIATELY 255 -struct abm_backlight_registers { - unsigned int BL_PWM_CNTL; - unsigned int BL_PWM_CNTL2; - unsigned int BL_PWM_PERIOD_CNTL; - unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV; -}; - -/* registers setting needs to be save and restored used at InitBacklight */ -static struct abm_backlight_registers stored_backlight_registers = {0}; - static unsigned int get_current_backlight_16_bit(struct dce_abm *abm_dce) { @@ -347,16 +337,16 @@ static bool dce_abm_init_backlight(struct abm *abm) */ REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); if (value == 0 || value == 1) { - if (stored_backlight_registers.BL_PWM_CNTL != 0) { + if (abm->stored_backlight_registers.BL_PWM_CNTL != 0) { REG_WRITE(BL_PWM_CNTL, - stored_backlight_registers.BL_PWM_CNTL); + abm->stored_backlight_registers.BL_PWM_CNTL); REG_WRITE(BL_PWM_CNTL2, - stored_backlight_registers.BL_PWM_CNTL2); + abm->stored_backlight_registers.BL_PWM_CNTL2); REG_WRITE(BL_PWM_PERIOD_CNTL, - stored_backlight_registers.BL_PWM_PERIOD_CNTL); + abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL); REG_UPDATE(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, - stored_backlight_registers. + abm->stored_backlight_registers. LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); } else { /* TODO: Note: This should not really happen since VBIOS @@ -366,15 +356,15 @@ static bool dce_abm_init_backlight(struct abm *abm) REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); } } else { - stored_backlight_registers.BL_PWM_CNTL = + abm->stored_backlight_registers.BL_PWM_CNTL = REG_READ(BL_PWM_CNTL); - stored_backlight_registers.BL_PWM_CNTL2 = + abm->stored_backlight_registers.BL_PWM_CNTL2 = REG_READ(BL_PWM_CNTL2); - stored_backlight_registers.BL_PWM_PERIOD_CNTL = + abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL = REG_READ(BL_PWM_PERIOD_CNTL); REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, - &stored_backlight_registers. + &abm->stored_backlight_registers. LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); } @@ -450,6 +440,10 @@ static void dce_abm_construct( base->ctx = ctx; base->funcs = &dce_funcs; + base->stored_backlight_registers.BL_PWM_CNTL = 0; + base->stored_backlight_registers.BL_PWM_CNTL2 = 0; + base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0; + base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0; abm_dce->regs = regs; abm_dce->abm_shift = abm_shift; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index 508c1aa4a775..a6de99db0444 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -53,7 +53,6 @@ #define MCP_INIT_IRAM 0x89 #define MCP_DMCU_VERSION 0x90 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L -unsigned int cached_wait_loop_number = 0; static bool dce_dmcu_init(struct dmcu *dmcu) { @@ -270,7 +269,7 @@ static void dce_psr_wait_loop( { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; - if (cached_wait_loop_number == wait_loop_number) + if (dmcu->cached_wait_loop_number == wait_loop_number) return; /* waitDMCUReadyForCmd */ @@ -278,7 +277,7 @@ static void dce_psr_wait_loop( masterCmdData1.u32 = 0; masterCmdData1.bits.wait_loop = wait_loop_number; - cached_wait_loop_number = wait_loop_number; + dmcu->cached_wait_loop_number = wait_loop_number; dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); /* setDMCUParam_Cmd */ @@ -288,9 +287,10 @@ static void dce_psr_wait_loop( REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); } -static void dce_get_psr_wait_loop(unsigned int *psr_wait_loop_number) +static void dce_get_psr_wait_loop( + struct dmcu *dmcu, unsigned int *psr_wait_loop_number) { - *psr_wait_loop_number = cached_wait_loop_number; + *psr_wait_loop_number = dmcu->cached_wait_loop_number; return; } @@ -673,7 +673,7 @@ static void dcn10_psr_wait_loop( masterCmdData1.u32 = 0; masterCmdData1.bits.wait_loop = wait_loop_number; - cached_wait_loop_number = wait_loop_number; + dmcu->cached_wait_loop_number = wait_loop_number; dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); /* setDMCUParam_Cmd */ @@ -684,9 +684,10 @@ static void dcn10_psr_wait_loop( } } -static void dcn10_get_psr_wait_loop(unsigned int *psr_wait_loop_number) +static void dcn10_get_psr_wait_loop( + struct dmcu *dmcu, unsigned int *psr_wait_loop_number) { - *psr_wait_loop_number = cached_wait_loop_number; + *psr_wait_loop_number = dmcu->cached_wait_loop_number; return; } @@ -725,6 +726,7 @@ static void dce_dmcu_construct( base->ctx = ctx; base->funcs = &dce_funcs; + base->cached_wait_loop_number = 0; dmcu_dce->regs = regs; dmcu_dce->dmcu_shift = dmcu_shift; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h index c93b9b9a817c..48217ecfabd4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h @@ -27,9 +27,19 @@ #include "dm_services_types.h" +struct abm_backlight_registers { + unsigned int BL_PWM_CNTL; + unsigned int BL_PWM_CNTL2; + unsigned int BL_PWM_PERIOD_CNTL; + unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV; +}; + struct abm { struct dc_context *ctx; const struct abm_funcs *funcs; + + /* registers setting needs to be saved and restored at InitBacklight */ + struct abm_backlight_registers stored_backlight_registers; }; struct abm_funcs { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h index 67996c662c0b..b59712b41b81 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h @@ -45,6 +45,7 @@ struct dmcu { enum dmcu_state dmcu_state; struct dmcu_version dmcu_version; + unsigned int cached_wait_loop_number; }; struct dmcu_funcs { @@ -60,7 +61,8 @@ struct dmcu_funcs { void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state); void (*set_psr_wait_loop)(struct dmcu *dmcu, unsigned int wait_loop_number); - void (*get_psr_wait_loop)(unsigned int *psr_wait_loop_number); + void (*get_psr_wait_loop)(struct dmcu *dmcu, + unsigned int *psr_wait_loop_number); }; #endif -- GitLab From a2c7f9e893acb809a85db473d0c060073f72ca52 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Mon, 13 Nov 2017 18:49:33 -0500 Subject: [PATCH 0917/2547] drm/amd/display: dal 3.1.19 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4a15f9c7068a..33590c02265e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.18" +#define DC_VER "3.1.19" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From 621fd3e39fc0222d7c8d95ddb5a2dff6261a0a86 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Tue, 14 Nov 2017 12:40:20 -0500 Subject: [PATCH 0918/2547] drm/amd/display: Set OPP default values in init_hw On S3 resume, we do not reconstruct OPP, but we do need to reinitialize some of its values to the default ones. Therefore, move those lines out of the OPP constructor and into init_hw. Also reset the hubp power gated flag, since nothing is power gated at init_hw. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 16 ++++++++++++---- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 7 ------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 522adceaf5d0..8e2ddbc2129c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -743,13 +743,21 @@ static void dcn10_init_hw(struct dc *dc) for (i = 0; i < dc->res_pool->pipe_count; i++) { struct timing_generator *tg = dc->res_pool->timing_generators[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct output_pixel_processor *opp = dc->res_pool->opps[i]; + struct mpc_tree_cfg *mpc_tree = &opp->mpc_tree; + struct hubp *hubp = dc->res_pool->hubps[i]; + + mpc_tree->dpp[0] = i; + mpc_tree->mpcc[0] = i; + mpc_tree->num_pipes = 1; pipe_ctx->stream_res.tg = tg; pipe_ctx->pipe_idx = i; - pipe_ctx->plane_res.hubp = dc->res_pool->hubps[i]; - pipe_ctx->plane_res.hubp->mpcc_id = i; - pipe_ctx->plane_res.hubp->opp_id = - dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i); + + pipe_ctx->plane_res.hubp = hubp; + hubp->mpcc_id = i; + hubp->opp_id = dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i); + hubp->power_gated = false; plane_atomic_disconnect(dc, pipe_ctx); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index 341210060cf7..6d6f67b7d30e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -330,17 +330,10 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10, const struct dcn10_opp_shift *opp_shift, const struct dcn10_opp_mask *opp_mask) { - int i; oppn10->base.ctx = ctx; oppn10->base.inst = inst; oppn10->base.funcs = &dcn10_opp_funcs; - oppn10->base.mpc_tree.dpp[0] = inst; - oppn10->base.mpc_tree.mpcc[0] = inst; - oppn10->base.mpc_tree.num_pipes = 1; - for (i = 0; i < MAX_PIPES; i++) - oppn10->base.mpcc_disconnect_pending[i] = false; - oppn10->regs = regs; oppn10->opp_shift = opp_shift; oppn10->opp_mask = opp_mask; -- GitLab From 0293bd519f87e6e081d3430df58b664861b8d415 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Tue, 14 Nov 2017 22:11:05 -0500 Subject: [PATCH 0919/2547] drm/amd/display: dal 3.1.20 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 33590c02265e..c99ed85ba9a2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.19" +#define DC_VER "3.1.20" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From 154683dd39f0591e1c52745cba62156ab946958c Mon Sep 17 00:00:00 2001 From: Roger He Date: Wed, 22 Nov 2017 15:09:33 +0800 Subject: [PATCH 0920/2547] drm/ttm: add set_pages_wb for handling page order more than zero MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index bf25ba25bfc6..359a641d3211 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -223,6 +223,17 @@ static struct kobj_type ttm_pool_kobj_type = { static struct ttm_pool_manager *_manager; #ifndef CONFIG_X86 +static int set_pages_wb(struct page *page, int numpages) +{ +#if IS_ENABLED(CONFIG_AGP) + int i; + + for (i = 0; i < numpages; i++) + unmap_page_from_agp(page++); +#endif + return 0; +} + static int set_pages_array_wb(struct page **pages, int addrinarray) { #if IS_ENABLED(CONFIG_AGP) -- GitLab From 444f8ef3f8f175f0c8bb8a436b1752b1d2d3f5a8 Mon Sep 17 00:00:00 2001 From: Roger He Date: Tue, 21 Nov 2017 14:24:48 +0800 Subject: [PATCH 0921/2547] drm/ttm: add page order support in ttm_pages_put MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 359a641d3211..337c228b44ad 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -296,13 +296,23 @@ static struct ttm_page_pool *ttm_get_pool(int flags, bool huge, } /* set memory back to wb and free the pages. */ -static void ttm_pages_put(struct page *pages[], unsigned npages) +static void ttm_pages_put(struct page *pages[], unsigned npages, + unsigned int order) { - unsigned i; - if (set_pages_array_wb(pages, npages)) - pr_err("Failed to set %d pages to wb!\n", npages); - for (i = 0; i < npages; ++i) - __free_page(pages[i]); + unsigned int i, pages_nr = (1 << order); + + if (order == 0) { + if (set_pages_array_wb(pages, npages)) + pr_err("Failed to set %d pages to wb!\n", npages); + } + + for (i = 0; i < npages; ++i) { + if (order > 0) { + if (set_pages_wb(pages[i], pages_nr)) + pr_err("Failed to set %d pages to wb!\n", pages_nr); + } + __free_pages(pages[i], order); + } } static void ttm_pool_update_free_locked(struct ttm_page_pool *pool, @@ -365,7 +375,7 @@ static int ttm_page_pool_free(struct ttm_page_pool *pool, unsigned nr_free, */ spin_unlock_irqrestore(&pool->lock, irq_flags); - ttm_pages_put(pages_to_free, freed_pages); + ttm_pages_put(pages_to_free, freed_pages, pool->order); if (likely(nr_free != FREE_ALL_PAGES)) nr_free -= freed_pages; @@ -400,7 +410,7 @@ static int ttm_page_pool_free(struct ttm_page_pool *pool, unsigned nr_free, spin_unlock_irqrestore(&pool->lock, irq_flags); if (freed_pages) - ttm_pages_put(pages_to_free, freed_pages); + ttm_pages_put(pages_to_free, freed_pages, pool->order); out: if (pages_to_free != static_buf) kfree(pages_to_free); -- GitLab From 1bfcbad18fc0c2618ae141ff2d8c384cf81bf98e Mon Sep 17 00:00:00 2001 From: Roger He Date: Tue, 21 Nov 2017 16:47:16 +0800 Subject: [PATCH 0922/2547] drm/ttm: roundup the shrink request to prevent skip huge pool MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit e.g. shrink reqeust is less than 512, the logic will skip huge pool Reviewed-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 337c228b44ad..116897a20514 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -442,17 +442,19 @@ ttm_pool_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) /* select start pool in round robin fashion */ for (i = 0; i < NUM_POOLS; ++i) { unsigned nr_free = shrink_pages; + unsigned page_nr; + if (shrink_pages == 0) break; pool = &_manager->pools[(i + pool_offset)%NUM_POOLS]; + page_nr = (1 << pool->order); /* OK to use static buffer since global mutex is held. */ - nr_free_pool = (nr_free >> pool->order); - if (nr_free_pool == 0) - continue; - + nr_free_pool = roundup(nr_free, page_nr) >> pool->order; shrink_pages = ttm_page_pool_free(pool, nr_free_pool, true); - freed += ((nr_free_pool - shrink_pages) << pool->order); + freed += (nr_free_pool - shrink_pages) << pool->order; + if (freed >= sc->nr_to_scan) + break; } mutex_unlock(&lock); return freed; -- GitLab From ce1b1b66cd5ec60927c575858430c099b8b4bceb Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 21 Nov 2017 13:29:14 +0800 Subject: [PATCH 0923/2547] drm/amdgpu:partially revert 1cfd8e237f0318e330190ac21d63c58ae6a1f66c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit found RING0 test fail after S3 resume regression, which is introduced by 1cfd8e237f0318e330190ac21d63c58ae6a1f66c Because after suspend VRAM will be cleared, so driver must unpin the GART table(resident in VRAM) during suspend so it can be evicted to system ram and must correspondingly pin it during resume so the GART table could be restored to VRAM. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 79 ++++++++++++++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 2 + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 7 ++- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 7 ++- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 7 ++- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++ 6 files changed, 94 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 707f85825996..1f51897acc5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -68,9 +68,75 @@ */ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) { - return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.robj, - &adev->gart.table_addr, &adev->gart.ptr); + int r; + + if (adev->gart.robj == NULL) { + r = amdgpu_bo_create(adev, adev->gart.table_size, + PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, + NULL, NULL, 0, &adev->gart.robj); + if (r) { + return r; + } + } + return 0; +} + +/** + * amdgpu_gart_table_vram_pin - pin gart page table in vram + * + * @adev: amdgpu_device pointer + * + * Pin the GART page table in vram so it will not be moved + * by the memory manager (pcie r4xx, r5xx+). These asics require the + * gart table to be in video memory. + * Returns 0 for success, error for failure. + */ +int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev) +{ + uint64_t gpu_addr; + int r; + + r = amdgpu_bo_reserve(adev->gart.robj, false); + if (unlikely(r != 0)) + return r; + r = amdgpu_bo_pin(adev->gart.robj, + AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr); + if (r) { + amdgpu_bo_unreserve(adev->gart.robj); + return r; + } + r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr); + if (r) + amdgpu_bo_unpin(adev->gart.robj); + amdgpu_bo_unreserve(adev->gart.robj); + adev->gart.table_addr = gpu_addr; + return r; +} + +/** + * amdgpu_gart_table_vram_unpin - unpin gart page table in vram + * + * @adev: amdgpu_device pointer + * + * Unpin the GART page table in vram (pcie r4xx, r5xx+). + * These asics require the gart table to be in video memory. + */ +void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev) +{ + int r; + + if (adev->gart.robj == NULL) { + return; + } + r = amdgpu_bo_reserve(adev->gart.robj, true); + if (likely(r == 0)) { + amdgpu_bo_kunmap(adev->gart.robj); + amdgpu_bo_unpin(adev->gart.robj); + amdgpu_bo_unreserve(adev->gart.robj); + adev->gart.ptr = NULL; + } } /** @@ -84,9 +150,10 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) */ void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) { - amdgpu_bo_free_kernel(&adev->gart.robj, - &adev->gart.table_addr, - &adev->gart.ptr); + if (adev->gart.robj == NULL) { + return; + } + amdgpu_bo_unref(&adev->gart.robj); } /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h index 5eb1a6800f72..d4a43302c2be 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h @@ -58,6 +58,8 @@ struct amdgpu_gart { int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); +int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); +void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); int amdgpu_gart_init(struct amdgpu_device *adev); void amdgpu_gart_fini(struct amdgpu_device *adev); int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 1e7f52f109b5..6098c773711f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -478,14 +478,16 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) { - int i; + int r, i; u32 field; if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; } - + r = amdgpu_gart_table_vram_pin(adev); + if (r) + return r; /* Setup TLB control */ WREG32(mmMC_VM_MX_L1_TLB_CNTL, (0xA << 7) | @@ -612,6 +614,7 @@ static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) WREG32(mmVM_L2_CNTL3, VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); + amdgpu_gart_table_vram_unpin(adev); } static void gmc_v6_0_gart_fini(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index d521862804ea..8b460e9d4431 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -582,14 +582,16 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) */ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) { - int i; + int r, i; u32 tmp, field; if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; } - + r = amdgpu_gart_table_vram_pin(adev); + if (r) + return r; /* Setup TLB control */ tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); @@ -722,6 +724,7 @@ static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); WREG32(mmVM_L2_CNTL, tmp); WREG32(mmVM_L2_CNTL2, 0); + amdgpu_gart_table_vram_unpin(adev); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index bd3f842cca00..1fd7f9daab0a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -781,14 +781,16 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) */ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) { - int i; + int r, i; u32 tmp, field; if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; } - + r = amdgpu_gart_table_vram_pin(adev); + if (r) + return r; /* Setup TLB control */ tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); @@ -938,6 +940,7 @@ static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); WREG32(mmVM_L2_CNTL, tmp); WREG32(mmVM_L2_CNTL2, 0); + amdgpu_gart_table_vram_unpin(adev); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 8529005a5022..c30e08d9f30b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -933,6 +933,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; } + r = amdgpu_gart_table_vram_pin(adev); + if (r) + return r; switch (adev->asic_type) { case CHIP_RAVEN: @@ -1010,6 +1013,7 @@ static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) { gfxhub_v1_0_gart_disable(adev); mmhub_v1_0_gart_disable(adev); + amdgpu_gart_table_vram_unpin(adev); } static int gmc_v9_0_hw_fini(void *handle) -- GitLab From 812f77b749a8ae11f58dacf0d3ed65e7ede47458 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Wed, 15 Nov 2017 16:01:30 +0800 Subject: [PATCH 0924/2547] drm/amd/include:cleanup vega10 sdma0/1 header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To remove include/asic_reg/vega10 folder,create IP folders sdma0/1. This patch cleanup asic_reg/vega10/SDMA folders. Signed-off-by: Feifei Xu Reviewed-by: Alex Deucher Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +- .../asic_reg/sdma0/sdma0_4_0_default.h | 286 +++ .../include/asic_reg/sdma0/sdma0_4_0_offset.h | 547 +++++ .../asic_reg/sdma0/sdma0_4_0_sh_mask.h | 1852 +++++++++++++++++ .../asic_reg/sdma1/sdma1_4_0_default.h | 282 +++ .../include/asic_reg/sdma1/sdma1_4_0_offset.h | 539 +++++ .../asic_reg/sdma1/sdma1_4_0_sh_mask.h | 1810 ++++++++++++++++ .../asic_reg/vega10/SDMA0/sdma0_4_0_default.h | 286 --- .../asic_reg/vega10/SDMA0/sdma0_4_0_offset.h | 547 ----- .../asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h | 1852 ----------------- .../asic_reg/vega10/SDMA1/sdma1_4_0_default.h | 282 --- .../asic_reg/vega10/SDMA1/sdma1_4_0_offset.h | 539 ----- .../asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h | 1810 ---------------- 15 files changed, 5323 insertions(+), 5323 deletions(-) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index c7bcfe8e286c..b855964740bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -35,7 +35,7 @@ #include "vega10/MP/mp_9_0_offset.h" #include "vega10/MP/mp_9_0_sh_mask.h" #include "vega10/GC/gc_9_0_offset.h" -#include "vega10/SDMA0/sdma0_4_0_offset.h" +#include "sdma0/sdma0_4_0_offset.h" #include "vega10/NBIO/nbio_6_1_offset.h" MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index a0a5a8da4c4f..4051a14424b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -28,10 +28,10 @@ #include "amdgpu_trace.h" #include "vega10/soc15ip.h" -#include "vega10/SDMA0/sdma0_4_0_offset.h" -#include "vega10/SDMA0/sdma0_4_0_sh_mask.h" -#include "vega10/SDMA1/sdma1_4_0_offset.h" -#include "vega10/SDMA1/sdma1_4_0_sh_mask.h" +#include "sdma0/sdma0_4_0_offset.h" +#include "sdma0/sdma0_4_0_sh_mask.h" +#include "sdma1/sdma1_4_0_offset.h" +#include "sdma1/sdma1_4_0_sh_mask.h" #include "vega10/MMHUB/mmhub_1_0_offset.h" #include "vega10/MMHUB/mmhub_1_0_sh_mask.h" #include "vega10/HDP/hdp_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index fa27e0354f35..82c75536a888 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -38,8 +38,8 @@ #include "vega10/UVD/uvd_7_0_offset.h" #include "vega10/GC/gc_9_0_offset.h" #include "vega10/GC/gc_9_0_sh_mask.h" -#include "vega10/SDMA0/sdma0_4_0_offset.h" -#include "vega10/SDMA1/sdma1_4_0_offset.h" +#include "sdma0/sdma0_4_0_offset.h" +#include "sdma1/sdma1_4_0_offset.h" #include "vega10/HDP/hdp_4_0_offset.h" #include "vega10/HDP/hdp_4_0_sh_mask.h" #include "vega10/MP/mp_9_0_offset.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h new file mode 100644 index 000000000000..4be3cb5c4556 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_0_DEFAULT_HEADER +#define _sdma0_4_0_DEFAULT_HEADER + + +// addressBlock: sdma0_sdma0dec +#define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000 +#define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000 +#define mmSDMA0_VM_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000 +#define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000 +#define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000 +#define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000 +#define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000 +#define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f +#define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff +#define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff +#define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 +#define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000 +#define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882 +#define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 +#define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000 +#define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 +#define mmSDMA0_POWER_CNTL_DEFAULT 0x0003c000 +#define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100 +#define mmSDMA0_CNTL_DEFAULT 0x00000002 +#define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07 +#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012 +#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 +#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000 +#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000 +#define mmSDMA0_PROGRAM_DEFAULT 0x00000000 +#define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557 +#define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff +#define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003 +#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000 +#define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000 +#define mmSDMA0_F32_CNTL_DEFAULT 0x00000001 +#define mmSDMA0_FREEZE_DEFAULT 0x00000000 +#define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA_POWER_GATING_DEFAULT 0x00000000 +#define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000 +#define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000 +#define mmSDMA_PGFSM_READ_DEFAULT 0x00000000 +#define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002 +#define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff +#define mmSDMA0_ID_DEFAULT 0x00000001 +#define mmSDMA0_VERSION_DEFAULT 0x00000400 +#define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000 +#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 +#define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000 +#define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200 +#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019 +#define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe +#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff +#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff +#define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600 +#define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001 +#define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0 +#define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200 +#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 +#define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005 +#define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000 +#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_PHASE2_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f +#define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000 +#define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000 +#define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000 +#define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000 +#define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000 +#define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000 +#define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd +#define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 +#define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 +#define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0 +#define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000 +#define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 +#define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 +#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 +#define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000 +#define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA0_PAGE_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA0_PAGE_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA0_PAGE_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_STATUS_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h new file mode 100644 index 000000000000..99758695f019 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h @@ -0,0 +1,547 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_0_OFFSET_HEADER +#define _sdma0_4_0_OFFSET_HEADER + + + +// addressBlock: sdma0_sdma0dec +// base address: 0x4980 +#define mmSDMA0_UCODE_ADDR 0x0000 +#define mmSDMA0_UCODE_ADDR_BASE_IDX 0 +#define mmSDMA0_UCODE_DATA 0x0001 +#define mmSDMA0_UCODE_DATA_BASE_IDX 0 +#define mmSDMA0_VM_CNTL 0x0004 +#define mmSDMA0_VM_CNTL_BASE_IDX 0 +#define mmSDMA0_VM_CTX_LO 0x0005 +#define mmSDMA0_VM_CTX_LO_BASE_IDX 0 +#define mmSDMA0_VM_CTX_HI 0x0006 +#define mmSDMA0_VM_CTX_HI_BASE_IDX 0 +#define mmSDMA0_ACTIVE_FCN_ID 0x0007 +#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmSDMA0_VM_CTX_CNTL 0x0008 +#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 +#define mmSDMA0_VIRT_RESET_REQ 0x0009 +#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 +#define mmSDMA0_VF_ENABLE 0x000a +#define mmSDMA0_VF_ENABLE_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE0 0x000f +#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE1 0x0010 +#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE2 0x0011 +#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE3 0x0012 +#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 +#define mmSDMA0_MMHUB_CNTL 0x0013 +#define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define mmSDMA0_POWER_CNTL 0x001a +#define mmSDMA0_POWER_CNTL_BASE_IDX 0 +#define mmSDMA0_CLK_CTRL 0x001b +#define mmSDMA0_CLK_CTRL_BASE_IDX 0 +#define mmSDMA0_CNTL 0x001c +#define mmSDMA0_CNTL_BASE_IDX 0 +#define mmSDMA0_CHICKEN_BITS 0x001d +#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 +#define mmSDMA0_GB_ADDR_CONFIG 0x001e +#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 +#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define mmSDMA0_RB_RPTR_FETCH 0x0022 +#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 +#define mmSDMA0_IB_OFFSET_FETCH 0x0023 +#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 +#define mmSDMA0_PROGRAM 0x0024 +#define mmSDMA0_PROGRAM_BASE_IDX 0 +#define mmSDMA0_STATUS_REG 0x0025 +#define mmSDMA0_STATUS_REG_BASE_IDX 0 +#define mmSDMA0_STATUS1_REG 0x0026 +#define mmSDMA0_STATUS1_REG_BASE_IDX 0 +#define mmSDMA0_RD_BURST_CNTL 0x0027 +#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 +#define mmSDMA0_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 +#define mmSDMA0_UCODE_CHECKSUM 0x0029 +#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 +#define mmSDMA0_F32_CNTL 0x002a +#define mmSDMA0_F32_CNTL_BASE_IDX 0 +#define mmSDMA0_FREEZE 0x002b +#define mmSDMA0_FREEZE_BASE_IDX 0 +#define mmSDMA0_PHASE0_QUANTUM 0x002c +#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 +#define mmSDMA0_PHASE1_QUANTUM 0x002d +#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 +#define mmSDMA_POWER_GATING 0x002e +#define mmSDMA_POWER_GATING_BASE_IDX 0 +#define mmSDMA_PGFSM_CONFIG 0x002f +#define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 +#define mmSDMA_PGFSM_WRITE 0x0030 +#define mmSDMA_PGFSM_WRITE_BASE_IDX 0 +#define mmSDMA_PGFSM_READ 0x0031 +#define mmSDMA_PGFSM_READ_BASE_IDX 0 +#define mmSDMA0_EDC_CONFIG 0x0032 +#define mmSDMA0_EDC_CONFIG_BASE_IDX 0 +#define mmSDMA0_BA_THRESHOLD 0x0033 +#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 +#define mmSDMA0_ID 0x0034 +#define mmSDMA0_ID_BASE_IDX 0 +#define mmSDMA0_VERSION 0x0035 +#define mmSDMA0_VERSION_BASE_IDX 0 +#define mmSDMA0_EDC_COUNTER 0x0036 +#define mmSDMA0_EDC_COUNTER_BASE_IDX 0 +#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define mmSDMA0_STATUS2_REG 0x0038 +#define mmSDMA0_STATUS2_REG_BASE_IDX 0 +#define mmSDMA0_ATOMIC_CNTL 0x0039 +#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 +#define mmSDMA0_ATOMIC_PREOP_LO 0x003a +#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 +#define mmSDMA0_ATOMIC_PREOP_HI 0x003b +#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 +#define mmSDMA0_UTCL1_CNTL 0x003c +#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 +#define mmSDMA0_UTCL1_WATERMK 0x003d +#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_STATUS 0x003e +#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_STATUS 0x003f +#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV0 0x0040 +#define mmSDMA0_UTCL1_INV0_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV1 0x0041 +#define mmSDMA0_UTCL1_INV1_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV2 0x0042 +#define mmSDMA0_UTCL1_INV2_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 +#define mmSDMA0_UTCL1_TIMEOUT 0x0047 +#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 +#define mmSDMA0_UTCL1_PAGE 0x0048 +#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 +#define mmSDMA0_POWER_CNTL_IDLE 0x0049 +#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 +#define mmSDMA0_RELAX_ORDERING_LUT 0x004a +#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 +#define mmSDMA0_CHICKEN_BITS_2 0x004b +#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 +#define mmSDMA0_STATUS3_REG 0x004c +#define mmSDMA0_STATUS3_REG_BASE_IDX 0 +#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PHASE2_QUANTUM 0x004f +#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 +#define mmSDMA0_ERROR_LOG 0x0050 +#define mmSDMA0_ERROR_LOG_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG0 0x0051 +#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG1 0x0052 +#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG2 0x0053 +#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG3 0x0054 +#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 +#define mmSDMA0_F32_COUNTER 0x0055 +#define mmSDMA0_F32_COUNTER_BASE_IDX 0 +#define mmSDMA0_UNBREAKABLE 0x0056 +#define mmSDMA0_UNBREAKABLE_BASE_IDX 0 +#define mmSDMA0_PERFMON_CNTL 0x0057 +#define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 +#define mmSDMA0_CRD_CNTL 0x005b +#define mmSDMA0_CRD_CNTL_BASE_IDX 0 +#define mmSDMA0_MMHUB_TRUSTLVL 0x005c +#define mmSDMA0_MMHUB_TRUSTLVL_BASE_IDX 0 +#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define mmSDMA0_ULV_CNTL 0x005e +#define mmSDMA0_ULV_CNTL_BASE_IDX 0 +#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define mmSDMA0_GFX_RB_CNTL 0x0080 +#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_RB_BASE 0x0081 +#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 +#define mmSDMA0_GFX_RB_BASE_HI 0x0082 +#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR 0x0083 +#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR 0x0085 +#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_IB_CNTL 0x008a +#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_IB_RPTR 0x008b +#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_GFX_IB_OFFSET 0x008c +#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_GFX_IB_BASE_LO 0x008d +#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_GFX_IB_BASE_HI 0x008e +#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_GFX_IB_SIZE 0x008f +#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_GFX_SKIP_CNTL 0x0090 +#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL 0x0092 +#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 +#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_STATUS 0x00a8 +#define mmSDMA0_GFX_STATUS_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_GFX_WATERMARK 0x00aa +#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_GFX_PREEMPT 0x00b0 +#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 +#define mmSDMA0_GFX_DUMMY_REG 0x00b1 +#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_CNTL 0x00e0 +#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_BASE 0x00e1 +#define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_BASE_HI 0x00e2 +#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR 0x00e3 +#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4 +#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR 0x00e5 +#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6 +#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7 +#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_CNTL 0x00ea +#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_RPTR 0x00eb +#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_OFFSET 0x00ec +#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_BASE_LO 0x00ed +#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_BASE_HI 0x00ee +#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_SIZE 0x00ef +#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_PAGE_SKIP_CNTL 0x00f0 +#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1 +#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_PAGE_DOORBELL 0x00f2 +#define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 +#define mmSDMA0_PAGE_STATUS 0x0108 +#define mmSDMA0_PAGE_STATUS_BASE_IDX 0 +#define mmSDMA0_PAGE_DOORBELL_LOG 0x0109 +#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_PAGE_WATERMARK 0x010a +#define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 +#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b +#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c +#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d +#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f +#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_PAGE_PREEMPT 0x0110 +#define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 +#define mmSDMA0_PAGE_DUMMY_REG 0x0111 +#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114 +#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115 +#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120 +#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121 +#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122 +#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123 +#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124 +#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125 +#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126 +#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127 +#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128 +#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129 +#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_CNTL 0x0140 +#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_BASE 0x0141 +#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_BASE_HI 0x0142 +#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR 0x0143 +#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_HI 0x0144 +#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR 0x0145 +#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 +#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_CNTL 0x014a +#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_RPTR 0x014b +#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_OFFSET 0x014c +#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_BASE_LO 0x014d +#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_BASE_HI 0x014e +#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_SIZE 0x014f +#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC0_SKIP_CNTL 0x0150 +#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151 +#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL 0x0152 +#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC0_STATUS 0x0168 +#define mmSDMA0_RLC0_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL_LOG 0x0169 +#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC0_WATERMARK 0x016a +#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b +#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c +#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d +#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f +#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC0_PREEMPT 0x0170 +#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC0_DUMMY_REG 0x0171 +#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174 +#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180 +#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181 +#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182 +#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183 +#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184 +#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185 +#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186 +#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187 +#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188 +#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189 +#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_CNTL 0x01a0 +#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_BASE 0x01a1 +#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_BASE_HI 0x01a2 +#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR 0x01a3 +#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4 +#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR 0x01a5 +#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6 +#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_CNTL 0x01aa +#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_RPTR 0x01ab +#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_OFFSET 0x01ac +#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_BASE_LO 0x01ad +#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_BASE_HI 0x01ae +#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_SIZE 0x01af +#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC1_SKIP_CNTL 0x01b0 +#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1 +#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL 0x01b2 +#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC1_STATUS 0x01c8 +#define mmSDMA0_RLC1_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9 +#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC1_WATERMARK 0x01ca +#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb +#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc +#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd +#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf +#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC1_PREEMPT 0x01d0 +#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC1_DUMMY_REG 0x01d1 +#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4 +#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5 +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0 +#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1 +#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2 +#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3 +#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4 +#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5 +#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6 +#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7 +#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8 +#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9 +#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h new file mode 100644 index 000000000000..f846cc8268d8 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h @@ -0,0 +1,1852 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_0_SH_MASK_HEADER +#define _sdma0_4_0_SH_MASK_HEADER + + +// addressBlock: sdma0_sdma0dec +//SDMA0_UCODE_ADDR +#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA0_UCODE_DATA +#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_VM_CNTL +#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA0_VM_CTX_LO +#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_VM_CTX_HI +#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_ACTIVE_FCN_ID +#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA0_VM_CTX_CNTL +#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA0_VIRT_RESET_REQ +#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA0_VF_ENABLE +#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA0_CONTEXT_REG_TYPE0 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA0_CONTEXT_REG_TYPE1 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA0_CONTEXT_REG_TYPE2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA0_CONTEXT_REG_TYPE3 +#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_PUB_REG_TYPE0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE2 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE3 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL +//SDMA0_MMHUB_CNTL +#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA0_CONTEXT_GROUP_BOUNDARY +#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_POWER_CNTL +#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 +#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L +#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L +#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA0_CLK_CTRL +#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA0_CNTL +#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA0_CHICKEN_BITS +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA0_GB_ADDR_CONFIG +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA0_GB_ADDR_CONFIG_READ +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA0_RB_RPTR_FETCH_HI +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA0_RB_RPTR_FETCH +#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA0_IB_OFFSET_FETCH +#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA0_PROGRAM +#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA0_STATUS_REG +#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA0_STATUS1_REG +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA0_RD_BURST_CNTL +#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +//SDMA0_HBM_PAGE_CONFIG +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA0_UCODE_CHECKSUM +#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA0_F32_CNTL +#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L +//SDMA0_FREEZE +#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA0_PHASE0_QUANTUM +#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA0_PHASE1_QUANTUM +#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA_POWER_GATING +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 +#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 +#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L +#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L +#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L +//SDMA_PGFSM_CONFIG +#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL +#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L +#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L +#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L +#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L +#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L +#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L +#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L +//SDMA_PGFSM_WRITE +#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL +//SDMA_PGFSM_READ +#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL +//SDMA0_EDC_CONFIG +#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA0_BA_THRESHOLD +#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA0_ID +#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA0_VERSION +#define SDMA0_VERSION__MINVER__SHIFT 0x0 +#define SDMA0_VERSION__MAJVER__SHIFT 0x8 +#define SDMA0_VERSION__REV__SHIFT 0x10 +#define SDMA0_VERSION__MINVER_MASK 0x0000007FL +#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA0_VERSION__REV_MASK 0x003F0000L +//SDMA0_EDC_COUNTER +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 +#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf +#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L +#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L +#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L +//SDMA0_EDC_COUNTER_CLEAR +#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA0_STATUS2_REG +#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 +#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L +#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL +#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA0_ATOMIC_CNTL +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA0_ATOMIC_PREOP_LO +#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_ATOMIC_PREOP_HI +#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_CNTL +#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA0_UTCL1_WATERMK +#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa +#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 +#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a +#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL +#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L +#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L +#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L +//SDMA0_UTCL1_RD_STATUS +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA0_UTCL1_WR_STATUS +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA0_UTCL1_INV0 +#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA0_UTCL1_INV1 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_INV2 +#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK1 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA0_UTCL1_WR_XNACK0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_WR_XNACK1 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA0_UTCL1_TIMEOUT +#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA0_UTCL1_PAGE +#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA0_POWER_CNTL_IDLE +#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA0_RELAX_ORDERING_LUT +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA0_CHICKEN_BITS_2 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA0_STATUS3_REG +#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +//SDMA0_PHYSICAL_ADDR_LO +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA0_PHYSICAL_ADDR_HI +#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA0_PHASE2_QUANTUM +#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA0_ERROR_LOG +#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA0_PUB_DUMMY_REG0 +#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG1 +#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG2 +#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG3 +#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA0_F32_COUNTER +#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA0_UNBREAKABLE +#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA0_PERFMON_CNTL +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA0_PERFCOUNTER0_RESULT +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER1_RESULT +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA0_CRD_CNTL +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA0_MMHUB_TRUSTLVL +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L +//SDMA0_GPU_IOV_VIOLATION_LOG +#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 +#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL +#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L +//SDMA0_ULV_CNTL +#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA0_EA_DBIT_ADDR_DATA +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_EA_DBIT_ADDR_INDEX +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA0_GFX_RB_CNTL +#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_GFX_RB_BASE +#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_BASE_HI +#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_GFX_RB_RPTR +#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_RPTR_HI +#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR +#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_HI +#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_CNTL +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_GFX_RB_RPTR_ADDR_HI +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_RPTR_ADDR_LO +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_IB_CNTL +#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_GFX_IB_RPTR +#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_GFX_IB_OFFSET +#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_GFX_IB_BASE_LO +#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_GFX_IB_BASE_HI +#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_IB_SIZE +#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_GFX_SKIP_CNTL +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA0_GFX_CONTEXT_STATUS +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_GFX_DOORBELL +#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_GFX_CONTEXT_CNTL +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA0_GFX_STATUS +#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_GFX_DOORBELL_LOG +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_GFX_WATERMARK +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_GFX_DOORBELL_OFFSET +#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_GFX_CSA_ADDR_LO +#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_CSA_ADDR_HI +#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_IB_SUB_REMAIN +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_GFX_PREEMPT +#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_GFX_DUMMY_REG +#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_RB_AQL_CNTL +#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_GFX_MINOR_PTR_UPDATE +#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_GFX_MIDCMD_DATA0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA1 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA2 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA3 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA4 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA5 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA6 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA7 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA8 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_CNTL +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_PAGE_RB_CNTL +#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_PAGE_RB_BASE +#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_BASE_HI +#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_PAGE_RB_RPTR +#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_RPTR_HI +#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR +#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_HI +#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_CNTL +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_PAGE_RB_RPTR_ADDR_HI +#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_RPTR_ADDR_LO +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_IB_CNTL +#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_PAGE_IB_RPTR +#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_PAGE_IB_OFFSET +#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_PAGE_IB_BASE_LO +#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_PAGE_IB_BASE_HI +#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_IB_SIZE +#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_PAGE_SKIP_CNTL +#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA0_PAGE_CONTEXT_STATUS +#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_PAGE_DOORBELL +#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_PAGE_STATUS +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_PAGE_DOORBELL_LOG +#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_PAGE_WATERMARK +#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_PAGE_DOORBELL_OFFSET +#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_PAGE_CSA_ADDR_LO +#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_CSA_ADDR_HI +#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_IB_SUB_REMAIN +#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_PAGE_PREEMPT +#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_PAGE_DUMMY_REG +#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_RB_AQL_CNTL +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_PAGE_MINOR_PTR_UPDATE +#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_PAGE_MIDCMD_DATA0 +#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA1 +#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA2 +#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA3 +#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA4 +#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA5 +#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA6 +#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA7 +#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA8 +#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_CNTL +#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC0_RB_CNTL +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC0_RB_BASE +#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_BASE_HI +#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC0_RB_RPTR +#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_RPTR_HI +#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR +#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_HI +#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_CNTL +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC0_RB_RPTR_ADDR_HI +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_RPTR_ADDR_LO +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_IB_CNTL +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC0_IB_RPTR +#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC0_IB_OFFSET +#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC0_IB_BASE_LO +#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC0_IB_BASE_HI +#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_IB_SIZE +#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC0_SKIP_CNTL +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA0_RLC0_CONTEXT_STATUS +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC0_DOORBELL +#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC0_STATUS +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC0_DOORBELL_LOG +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC0_WATERMARK +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC0_DOORBELL_OFFSET +#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC0_CSA_ADDR_LO +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_CSA_ADDR_HI +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_IB_SUB_REMAIN +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_RLC0_PREEMPT +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC0_DUMMY_REG +#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_RB_AQL_CNTL +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC0_MINOR_PTR_UPDATE +#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC0_MIDCMD_DATA0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA1 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA2 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA3 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA4 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA5 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA6 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA7 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA8 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_CNTL +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC1_RB_CNTL +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC1_RB_BASE +#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_BASE_HI +#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC1_RB_RPTR +#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_RPTR_HI +#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR +#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_HI +#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_CNTL +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC1_RB_RPTR_ADDR_HI +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_RPTR_ADDR_LO +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_IB_CNTL +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC1_IB_RPTR +#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC1_IB_OFFSET +#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC1_IB_BASE_LO +#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC1_IB_BASE_HI +#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_IB_SIZE +#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC1_SKIP_CNTL +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA0_RLC1_CONTEXT_STATUS +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC1_DOORBELL +#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC1_STATUS +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC1_DOORBELL_LOG +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC1_WATERMARK +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC1_DOORBELL_OFFSET +#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC1_CSA_ADDR_LO +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_CSA_ADDR_HI +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_IB_SUB_REMAIN +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_RLC1_PREEMPT +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC1_DUMMY_REG +#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_RB_AQL_CNTL +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC1_MINOR_PTR_UPDATE +#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC1_MIDCMD_DATA0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA1 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA2 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA3 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA4 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA5 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA6 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA7 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA8 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_CNTL +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h new file mode 100644 index 000000000000..934733762ddf --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma1_4_0_DEFAULT_HEADER +#define _sdma1_4_0_DEFAULT_HEADER + + +// addressBlock: sdma1_sdma1dec +#define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000 +#define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000 +#define mmSDMA1_VM_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000 +#define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000 +#define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000 +#define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000 +#define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000 +#define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f +#define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff +#define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff +#define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 +#define mmSDMA1_PUB_REG_TYPE0_DEFAULT 0x3c000000 +#define mmSDMA1_PUB_REG_TYPE1_DEFAULT 0x30003882 +#define mmSDMA1_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 +#define mmSDMA1_PUB_REG_TYPE3_DEFAULT 0x00000000 +#define mmSDMA1_MMHUB_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 +#define mmSDMA1_POWER_CNTL_DEFAULT 0x0003c000 +#define mmSDMA1_CLK_CTRL_DEFAULT 0xff000100 +#define mmSDMA1_CNTL_DEFAULT 0x00000002 +#define mmSDMA1_CHICKEN_BITS_DEFAULT 0x00831f07 +#define mmSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00100012 +#define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 +#define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000 +#define mmSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000 +#define mmSDMA1_PROGRAM_DEFAULT 0x00000000 +#define mmSDMA1_STATUS_REG_DEFAULT 0x46dee557 +#define mmSDMA1_STATUS1_REG_DEFAULT 0x000003ff +#define mmSDMA1_RD_BURST_CNTL_DEFAULT 0x00000003 +#define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000 +#define mmSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000 +#define mmSDMA1_F32_CNTL_DEFAULT 0x00000001 +#define mmSDMA1_FREEZE_DEFAULT 0x00000000 +#define mmSDMA1_PHASE0_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA1_PHASE1_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA1_EDC_CONFIG_DEFAULT 0x00000002 +#define mmSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff +#define mmSDMA1_ID_DEFAULT 0x00000001 +#define mmSDMA1_VERSION_DEFAULT 0x00000400 +#define mmSDMA1_EDC_COUNTER_DEFAULT 0x00000000 +#define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 +#define mmSDMA1_STATUS2_REG_DEFAULT 0x00000001 +#define mmSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200 +#define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_CNTL_DEFAULT 0xd0003019 +#define mmSDMA1_UTCL1_WATERMK_DEFAULT 0xfffbe1fe +#define mmSDMA1_UTCL1_RD_STATUS_DEFAULT 0x201001ff +#define mmSDMA1_UTCL1_WR_STATUS_DEFAULT 0x503001ff +#define mmSDMA1_UTCL1_INV0_DEFAULT 0x00000600 +#define mmSDMA1_UTCL1_INV1_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_INV2_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00010001 +#define mmSDMA1_UTCL1_PAGE_DEFAULT 0x000003e0 +#define mmSDMA1_POWER_CNTL_IDLE_DEFAULT 0x06060200 +#define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 +#define mmSDMA1_CHICKEN_BITS_2_DEFAULT 0x00000005 +#define mmSDMA1_STATUS3_REG_DEFAULT 0x00100000 +#define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_PHASE2_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA1_ERROR_LOG_DEFAULT 0x0000000f +#define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000 +#define mmSDMA1_PUB_DUMMY_REG1_DEFAULT 0x00000000 +#define mmSDMA1_PUB_DUMMY_REG2_DEFAULT 0x00000000 +#define mmSDMA1_PUB_DUMMY_REG3_DEFAULT 0x00000000 +#define mmSDMA1_F32_COUNTER_DEFAULT 0x00000000 +#define mmSDMA1_UNBREAKABLE_DEFAULT 0x00000000 +#define mmSDMA1_PERFMON_CNTL_DEFAULT 0x000ff7fd +#define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 +#define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 +#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 +#define mmSDMA1_CRD_CNTL_DEFAULT 0x000085c0 +#define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT 0x00000000 +#define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 +#define mmSDMA1_ULV_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 +#define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA1_GFX_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_GFX_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA1_GFX_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_GFX_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_GFX_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA1_GFX_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA1_GFX_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 +#define mmSDMA1_GFX_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_GFX_STATUS_DEFAULT 0x00000000 +#define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA1_GFX_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA1_GFX_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA1_GFX_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA1_PAGE_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA1_PAGE_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA1_PAGE_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_STATUS_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA1_RLC0_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA1_RLC0_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA1_RLC0_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_STATUS_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA1_RLC1_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA1_RLC1_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA1_RLC1_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_STATUS_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h new file mode 100644 index 000000000000..f2c151a7935d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h @@ -0,0 +1,539 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma1_4_0_OFFSET_HEADER +#define _sdma1_4_0_OFFSET_HEADER + + + +// addressBlock: sdma1_sdma1dec +// base address: 0x5180 +#define mmSDMA1_UCODE_ADDR 0x0000 +#define mmSDMA1_UCODE_ADDR_BASE_IDX 0 +#define mmSDMA1_UCODE_DATA 0x0001 +#define mmSDMA1_UCODE_DATA_BASE_IDX 0 +#define mmSDMA1_VM_CNTL 0x0004 +#define mmSDMA1_VM_CNTL_BASE_IDX 0 +#define mmSDMA1_VM_CTX_LO 0x0005 +#define mmSDMA1_VM_CTX_LO_BASE_IDX 0 +#define mmSDMA1_VM_CTX_HI 0x0006 +#define mmSDMA1_VM_CTX_HI_BASE_IDX 0 +#define mmSDMA1_ACTIVE_FCN_ID 0x0007 +#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmSDMA1_VM_CTX_CNTL 0x0008 +#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0 +#define mmSDMA1_VIRT_RESET_REQ 0x0009 +#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0 +#define mmSDMA1_VF_ENABLE 0x000a +#define mmSDMA1_VF_ENABLE_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE0 0x000f +#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE1 0x0010 +#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE2 0x0011 +#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE3 0x0012 +#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0 +#define mmSDMA1_MMHUB_CNTL 0x0013 +#define mmSDMA1_MMHUB_CNTL_BASE_IDX 0 +#define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define mmSDMA1_POWER_CNTL 0x001a +#define mmSDMA1_POWER_CNTL_BASE_IDX 0 +#define mmSDMA1_CLK_CTRL 0x001b +#define mmSDMA1_CLK_CTRL_BASE_IDX 0 +#define mmSDMA1_CNTL 0x001c +#define mmSDMA1_CNTL_BASE_IDX 0 +#define mmSDMA1_CHICKEN_BITS 0x001d +#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0 +#define mmSDMA1_GB_ADDR_CONFIG 0x001e +#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 +#define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define mmSDMA1_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define mmSDMA1_RB_RPTR_FETCH 0x0022 +#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0 +#define mmSDMA1_IB_OFFSET_FETCH 0x0023 +#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 +#define mmSDMA1_PROGRAM 0x0024 +#define mmSDMA1_PROGRAM_BASE_IDX 0 +#define mmSDMA1_STATUS_REG 0x0025 +#define mmSDMA1_STATUS_REG_BASE_IDX 0 +#define mmSDMA1_STATUS1_REG 0x0026 +#define mmSDMA1_STATUS1_REG_BASE_IDX 0 +#define mmSDMA1_RD_BURST_CNTL 0x0027 +#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0 +#define mmSDMA1_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 +#define mmSDMA1_UCODE_CHECKSUM 0x0029 +#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0 +#define mmSDMA1_F32_CNTL 0x002a +#define mmSDMA1_F32_CNTL_BASE_IDX 0 +#define mmSDMA1_FREEZE 0x002b +#define mmSDMA1_FREEZE_BASE_IDX 0 +#define mmSDMA1_PHASE0_QUANTUM 0x002c +#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0 +#define mmSDMA1_PHASE1_QUANTUM 0x002d +#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0 +#define mmSDMA1_EDC_CONFIG 0x0032 +#define mmSDMA1_EDC_CONFIG_BASE_IDX 0 +#define mmSDMA1_BA_THRESHOLD 0x0033 +#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0 +#define mmSDMA1_ID 0x0034 +#define mmSDMA1_ID_BASE_IDX 0 +#define mmSDMA1_VERSION 0x0035 +#define mmSDMA1_VERSION_BASE_IDX 0 +#define mmSDMA1_EDC_COUNTER 0x0036 +#define mmSDMA1_EDC_COUNTER_BASE_IDX 0 +#define mmSDMA1_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define mmSDMA1_STATUS2_REG 0x0038 +#define mmSDMA1_STATUS2_REG_BASE_IDX 0 +#define mmSDMA1_ATOMIC_CNTL 0x0039 +#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0 +#define mmSDMA1_ATOMIC_PREOP_LO 0x003a +#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 +#define mmSDMA1_ATOMIC_PREOP_HI 0x003b +#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 +#define mmSDMA1_UTCL1_CNTL 0x003c +#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0 +#define mmSDMA1_UTCL1_WATERMK 0x003d +#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0 +#define mmSDMA1_UTCL1_RD_STATUS 0x003e +#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 +#define mmSDMA1_UTCL1_WR_STATUS 0x003f +#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 +#define mmSDMA1_UTCL1_INV0 0x0040 +#define mmSDMA1_UTCL1_INV0_BASE_IDX 0 +#define mmSDMA1_UTCL1_INV1 0x0041 +#define mmSDMA1_UTCL1_INV1_BASE_IDX 0 +#define mmSDMA1_UTCL1_INV2 0x0042 +#define mmSDMA1_UTCL1_INV2_BASE_IDX 0 +#define mmSDMA1_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 +#define mmSDMA1_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 +#define mmSDMA1_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 +#define mmSDMA1_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 +#define mmSDMA1_UTCL1_TIMEOUT 0x0047 +#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 +#define mmSDMA1_UTCL1_PAGE 0x0048 +#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0 +#define mmSDMA1_POWER_CNTL_IDLE 0x0049 +#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 +#define mmSDMA1_RELAX_ORDERING_LUT 0x004a +#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 +#define mmSDMA1_CHICKEN_BITS_2 0x004b +#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0 +#define mmSDMA1_STATUS3_REG 0x004c +#define mmSDMA1_STATUS3_REG_BASE_IDX 0 +#define mmSDMA1_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PHASE2_QUANTUM 0x004f +#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0 +#define mmSDMA1_ERROR_LOG 0x0050 +#define mmSDMA1_ERROR_LOG_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG0 0x0051 +#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG1 0x0052 +#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG2 0x0053 +#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG3 0x0054 +#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 +#define mmSDMA1_F32_COUNTER 0x0055 +#define mmSDMA1_F32_COUNTER_BASE_IDX 0 +#define mmSDMA1_UNBREAKABLE 0x0056 +#define mmSDMA1_UNBREAKABLE_BASE_IDX 0 +#define mmSDMA1_PERFMON_CNTL 0x0057 +#define mmSDMA1_PERFMON_CNTL_BASE_IDX 0 +#define mmSDMA1_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0 +#define mmSDMA1_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0 +#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 +#define mmSDMA1_CRD_CNTL 0x005b +#define mmSDMA1_CRD_CNTL_BASE_IDX 0 +#define mmSDMA1_MMHUB_TRUSTLVL 0x005c +#define mmSDMA1_MMHUB_TRUSTLVL_BASE_IDX 0 +#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define mmSDMA1_ULV_CNTL 0x005e +#define mmSDMA1_ULV_CNTL_BASE_IDX 0 +#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define mmSDMA1_GFX_RB_CNTL 0x0080 +#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_RB_BASE 0x0081 +#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0 +#define mmSDMA1_GFX_RB_BASE_HI 0x0082 +#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR 0x0083 +#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR 0x0085 +#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_GFX_IB_CNTL 0x008a +#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_IB_RPTR 0x008b +#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_GFX_IB_OFFSET 0x008c +#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_GFX_IB_BASE_LO 0x008d +#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_GFX_IB_BASE_HI 0x008e +#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_GFX_IB_SIZE 0x008f +#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_GFX_SKIP_CNTL 0x0090 +#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_GFX_DOORBELL 0x0092 +#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0 +#define mmSDMA1_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_STATUS 0x00a8 +#define mmSDMA1_GFX_STATUS_BASE_IDX 0 +#define mmSDMA1_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_GFX_WATERMARK 0x00aa +#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0 +#define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_GFX_PREEMPT 0x00b0 +#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0 +#define mmSDMA1_GFX_DUMMY_REG 0x00b1 +#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_CNTL 0x00e0 +#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_BASE 0x00e1 +#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_BASE_HI 0x00e2 +#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR 0x00e3 +#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4 +#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR 0x00e5 +#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6 +#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7 +#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_CNTL 0x00ea +#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_RPTR 0x00eb +#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_OFFSET 0x00ec +#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_BASE_LO 0x00ed +#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_BASE_HI 0x00ee +#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_SIZE 0x00ef +#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_PAGE_SKIP_CNTL 0x00f0 +#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1 +#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_PAGE_DOORBELL 0x00f2 +#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0 +#define mmSDMA1_PAGE_STATUS 0x0108 +#define mmSDMA1_PAGE_STATUS_BASE_IDX 0 +#define mmSDMA1_PAGE_DOORBELL_LOG 0x0109 +#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_PAGE_WATERMARK 0x010a +#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0 +#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b +#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c +#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d +#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f +#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_PAGE_PREEMPT 0x0110 +#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0 +#define mmSDMA1_PAGE_DUMMY_REG 0x0111 +#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114 +#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115 +#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120 +#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121 +#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122 +#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123 +#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124 +#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125 +#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126 +#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127 +#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128 +#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129 +#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_CNTL 0x0140 +#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_BASE 0x0141 +#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_BASE_HI 0x0142 +#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR 0x0143 +#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR_HI 0x0144 +#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR 0x0145 +#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_HI 0x0146 +#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_CNTL 0x014a +#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_RPTR 0x014b +#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_OFFSET 0x014c +#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_BASE_LO 0x014d +#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_BASE_HI 0x014e +#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_SIZE 0x014f +#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC0_SKIP_CNTL 0x0150 +#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151 +#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC0_DOORBELL 0x0152 +#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC0_STATUS 0x0168 +#define mmSDMA1_RLC0_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC0_DOORBELL_LOG 0x0169 +#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC0_WATERMARK 0x016a +#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b +#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c +#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d +#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f +#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC0_PREEMPT 0x0170 +#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC0_DUMMY_REG 0x0171 +#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174 +#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175 +#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180 +#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181 +#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182 +#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183 +#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184 +#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185 +#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186 +#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187 +#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188 +#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189 +#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_CNTL 0x01a0 +#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_BASE 0x01a1 +#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_BASE_HI 0x01a2 +#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR 0x01a3 +#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4 +#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR 0x01a5 +#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6 +#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7 +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_CNTL 0x01aa +#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_RPTR 0x01ab +#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_OFFSET 0x01ac +#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_BASE_LO 0x01ad +#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_BASE_HI 0x01ae +#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_SIZE 0x01af +#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC1_SKIP_CNTL 0x01b0 +#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1 +#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC1_DOORBELL 0x01b2 +#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC1_STATUS 0x01c8 +#define mmSDMA1_RLC1_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9 +#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC1_WATERMARK 0x01ca +#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb +#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc +#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd +#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf +#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC1_PREEMPT 0x01d0 +#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC1_DUMMY_REG 0x01d1 +#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4 +#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5 +#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0 +#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1 +#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2 +#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3 +#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4 +#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5 +#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6 +#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7 +#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8 +#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9 +#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h new file mode 100644 index 000000000000..99849e0dde5e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h @@ -0,0 +1,1810 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma1_4_0_SH_MASK_HEADER +#define _sdma1_4_0_SH_MASK_HEADER + + +// addressBlock: sdma1_sdma1dec +//SDMA1_UCODE_ADDR +#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA1_UCODE_DATA +#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_VM_CNTL +#define SDMA1_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA1_VM_CTX_LO +#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_VM_CTX_HI +#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_ACTIVE_FCN_ID +#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA1_VM_CTX_CNTL +#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA1_VIRT_RESET_REQ +#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA1_VF_ENABLE +#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA1_CONTEXT_REG_TYPE0 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA1_CONTEXT_REG_TYPE1 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA1_CONTEXT_REG_TYPE2 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA1_CONTEXT_REG_TYPE3 +#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA1_PUB_REG_TYPE0 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L +#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L +#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA1_PUB_REG_TYPE1 +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L +#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L +#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA1_PUB_REG_TYPE2 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L +#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL_MASK 0x10000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L +#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA1_PUB_REG_TYPE3 +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL +//SDMA1_MMHUB_CNTL +#define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA1_CONTEXT_GROUP_BOUNDARY +#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA1_POWER_CNTL +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA1_CLK_CTRL +#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA1_CNTL +#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA1_CHICKEN_BITS +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA1_GB_ADDR_CONFIG +#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA1_GB_ADDR_CONFIG_READ +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA1_RB_RPTR_FETCH_HI +#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA1_RB_RPTR_FETCH +#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA1_IB_OFFSET_FETCH +#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA1_PROGRAM +#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA1_STATUS_REG +#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA1_STATUS1_REG +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA1_RD_BURST_CNTL +#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +//SDMA1_HBM_PAGE_CONFIG +#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA1_UCODE_CHECKSUM +#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA1_F32_CNTL +#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L +//SDMA1_FREEZE +#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA1_PHASE0_QUANTUM +#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_PHASE1_QUANTUM +#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_EDC_CONFIG +#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA1_BA_THRESHOLD +#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA1_ID +#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA1_VERSION +#define SDMA1_VERSION__MINVER__SHIFT 0x0 +#define SDMA1_VERSION__MAJVER__SHIFT 0x8 +#define SDMA1_VERSION__REV__SHIFT 0x10 +#define SDMA1_VERSION__MINVER_MASK 0x0000007FL +#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA1_VERSION__REV_MASK 0x003F0000L +//SDMA1_EDC_COUNTER +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 +#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf +#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L +#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L +#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L +//SDMA1_EDC_COUNTER_CLEAR +#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA1_STATUS2_REG +#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 +#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L +#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL +#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA1_ATOMIC_CNTL +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA1_ATOMIC_PREOP_LO +#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_ATOMIC_PREOP_HI +#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_CNTL +#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA1_UTCL1_WATERMK +#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa +#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 +#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a +#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL +#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L +#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L +#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L +//SDMA1_UTCL1_RD_STATUS +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA1_UTCL1_WR_STATUS +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA1_UTCL1_INV0 +#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA1_UTCL1_INV1 +#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_INV2 +#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_RD_XNACK0 +#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_RD_XNACK1 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA1_UTCL1_WR_XNACK0 +#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_WR_XNACK1 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA1_UTCL1_TIMEOUT +#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA1_UTCL1_PAGE +#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA1_POWER_CNTL_IDLE +#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA1_RELAX_ORDERING_LUT +#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA1_CHICKEN_BITS_2 +#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA1_STATUS3_REG +#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +//SDMA1_PHYSICAL_ADDR_LO +#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA1_PHYSICAL_ADDR_HI +#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA1_PHASE2_QUANTUM +#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_ERROR_LOG +#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA1_PUB_DUMMY_REG0 +#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG1 +#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG2 +#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG3 +#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA1_F32_COUNTER +#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA1_UNBREAKABLE +#define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA1_PERFMON_CNTL +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA1_PERFCOUNTER0_RESULT +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA1_PERFCOUNTER1_RESULT +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA1_CRD_CNTL +#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA1_MMHUB_TRUSTLVL +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L +//SDMA1_GPU_IOV_VIOLATION_LOG +#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 +#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 +#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 +#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 +#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL +#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L +#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L +#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L +#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L +//SDMA1_ULV_CNTL +#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA1_EA_DBIT_ADDR_DATA +#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_EA_DBIT_ADDR_INDEX +#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA1_GFX_RB_CNTL +#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_GFX_RB_BASE +#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_BASE_HI +#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_GFX_RB_RPTR +#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_RPTR_HI +#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR +#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_HI +#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_CNTL +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_GFX_RB_RPTR_ADDR_HI +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_RPTR_ADDR_LO +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_IB_CNTL +#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_GFX_IB_RPTR +#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_GFX_IB_OFFSET +#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_GFX_IB_BASE_LO +#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_GFX_IB_BASE_HI +#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_IB_SIZE +#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_GFX_SKIP_CNTL +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA1_GFX_CONTEXT_STATUS +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_GFX_DOORBELL +#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_GFX_CONTEXT_CNTL +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA1_GFX_STATUS +#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_GFX_DOORBELL_LOG +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_GFX_WATERMARK +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_GFX_DOORBELL_OFFSET +#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_GFX_CSA_ADDR_LO +#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_CSA_ADDR_HI +#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_IB_SUB_REMAIN +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_GFX_PREEMPT +#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_GFX_DUMMY_REG +#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_RB_AQL_CNTL +#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_GFX_MINOR_PTR_UPDATE +#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_GFX_MIDCMD_DATA0 +#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA1 +#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA2 +#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA3 +#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA4 +#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA5 +#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA6 +#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA7 +#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA8 +#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_CNTL +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_PAGE_RB_CNTL +#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_PAGE_RB_BASE +#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_BASE_HI +#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_PAGE_RB_RPTR +#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_RPTR_HI +#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR +#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_HI +#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_CNTL +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_PAGE_RB_RPTR_ADDR_HI +#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_RPTR_ADDR_LO +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_IB_CNTL +#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_PAGE_IB_RPTR +#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_PAGE_IB_OFFSET +#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_PAGE_IB_BASE_LO +#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_PAGE_IB_BASE_HI +#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_IB_SIZE +#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_PAGE_SKIP_CNTL +#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA1_PAGE_CONTEXT_STATUS +#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_PAGE_DOORBELL +#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_PAGE_STATUS +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_PAGE_DOORBELL_LOG +#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_PAGE_WATERMARK +#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_PAGE_DOORBELL_OFFSET +#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_PAGE_CSA_ADDR_LO +#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_CSA_ADDR_HI +#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_IB_SUB_REMAIN +#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_PAGE_PREEMPT +#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_PAGE_DUMMY_REG +#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_RB_AQL_CNTL +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_PAGE_MINOR_PTR_UPDATE +#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_PAGE_MIDCMD_DATA0 +#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA1 +#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA2 +#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA3 +#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA4 +#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA5 +#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA6 +#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA7 +#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA8 +#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_CNTL +#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC0_RB_CNTL +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC0_RB_BASE +#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_BASE_HI +#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC0_RB_RPTR +#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_RPTR_HI +#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR +#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_HI +#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_CNTL +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC0_RB_RPTR_ADDR_HI +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_RPTR_ADDR_LO +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_IB_CNTL +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC0_IB_RPTR +#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC0_IB_OFFSET +#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC0_IB_BASE_LO +#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC0_IB_BASE_HI +#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_IB_SIZE +#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC0_SKIP_CNTL +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA1_RLC0_CONTEXT_STATUS +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC0_DOORBELL +#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC0_STATUS +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC0_DOORBELL_LOG +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC0_WATERMARK +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC0_DOORBELL_OFFSET +#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC0_CSA_ADDR_LO +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_CSA_ADDR_HI +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_IB_SUB_REMAIN +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_RLC0_PREEMPT +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC0_DUMMY_REG +#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_RB_AQL_CNTL +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC0_MINOR_PTR_UPDATE +#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC0_MIDCMD_DATA0 +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA1 +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA2 +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA3 +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA4 +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA5 +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA6 +#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA7 +#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA8 +#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_CNTL +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC1_RB_CNTL +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC1_RB_BASE +#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_BASE_HI +#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC1_RB_RPTR +#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_RPTR_HI +#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR +#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_HI +#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_CNTL +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC1_RB_RPTR_ADDR_HI +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_RPTR_ADDR_LO +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_IB_CNTL +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC1_IB_RPTR +#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC1_IB_OFFSET +#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC1_IB_BASE_LO +#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC1_IB_BASE_HI +#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_IB_SIZE +#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC1_SKIP_CNTL +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA1_RLC1_CONTEXT_STATUS +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC1_DOORBELL +#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC1_STATUS +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC1_DOORBELL_LOG +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC1_WATERMARK +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC1_DOORBELL_OFFSET +#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC1_CSA_ADDR_LO +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_CSA_ADDR_HI +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_IB_SUB_REMAIN +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_RLC1_PREEMPT +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC1_DUMMY_REG +#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_RB_AQL_CNTL +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC1_MINOR_PTR_UPDATE +#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC1_MIDCMD_DATA0 +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA1 +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA2 +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA3 +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA4 +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA5 +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA6 +#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA7 +#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA8 +#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_CNTL +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h deleted file mode 100644 index afd15bd6a41a..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma0_4_0_DEFAULT_HEADER -#define _sdma0_4_0_DEFAULT_HEADER - - -// addressBlock: sdma0_sdma0dec -#define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000 -#define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000 -#define mmSDMA0_VM_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000 -#define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000 -#define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000 -#define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f -#define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff -#define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff -#define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 -#define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000 -#define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882 -#define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 -#define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000 -#define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 -#define mmSDMA0_POWER_CNTL_DEFAULT 0x0003c000 -#define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100 -#define mmSDMA0_CNTL_DEFAULT 0x00000002 -#define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07 -#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012 -#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 -#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 -#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000 -#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000 -#define mmSDMA0_PROGRAM_DEFAULT 0x00000000 -#define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557 -#define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff -#define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003 -#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000 -#define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000 -#define mmSDMA0_F32_CNTL_DEFAULT 0x00000001 -#define mmSDMA0_FREEZE_DEFAULT 0x00000000 -#define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002 -#define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002 -#define mmSDMA_POWER_GATING_DEFAULT 0x00000000 -#define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000 -#define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000 -#define mmSDMA_PGFSM_READ_DEFAULT 0x00000000 -#define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002 -#define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff -#define mmSDMA0_ID_DEFAULT 0x00000001 -#define mmSDMA0_VERSION_DEFAULT 0x00000400 -#define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000 -#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 -#define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000 -#define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200 -#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000 -#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019 -#define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe -#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff -#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff -#define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600 -#define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001 -#define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0 -#define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200 -#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 -#define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005 -#define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000 -#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_PHASE2_QUANTUM_DEFAULT 0x00010002 -#define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f -#define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000 -#define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000 -#define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000 -#define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000 -#define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000 -#define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000 -#define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd -#define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 -#define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 -#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 -#define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0 -#define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000 -#define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 -#define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 -#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 -#define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000 -#define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA0_PAGE_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA0_PAGE_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 -#define mmSDMA0_PAGE_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_STATUS_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 -#define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 -#define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h deleted file mode 100644 index b100c4e5f1ca..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h +++ /dev/null @@ -1,547 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma0_4_0_OFFSET_HEADER -#define _sdma0_4_0_OFFSET_HEADER - - - -// addressBlock: sdma0_sdma0dec -// base address: 0x4980 -#define mmSDMA0_UCODE_ADDR 0x0000 -#define mmSDMA0_UCODE_ADDR_BASE_IDX 0 -#define mmSDMA0_UCODE_DATA 0x0001 -#define mmSDMA0_UCODE_DATA_BASE_IDX 0 -#define mmSDMA0_VM_CNTL 0x0004 -#define mmSDMA0_VM_CNTL_BASE_IDX 0 -#define mmSDMA0_VM_CTX_LO 0x0005 -#define mmSDMA0_VM_CTX_LO_BASE_IDX 0 -#define mmSDMA0_VM_CTX_HI 0x0006 -#define mmSDMA0_VM_CTX_HI_BASE_IDX 0 -#define mmSDMA0_ACTIVE_FCN_ID 0x0007 -#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 -#define mmSDMA0_VM_CTX_CNTL 0x0008 -#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 -#define mmSDMA0_VIRT_RESET_REQ 0x0009 -#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 -#define mmSDMA0_VF_ENABLE 0x000a -#define mmSDMA0_VF_ENABLE_BASE_IDX 0 -#define mmSDMA0_CONTEXT_REG_TYPE0 0x000b -#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 -#define mmSDMA0_CONTEXT_REG_TYPE1 0x000c -#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 -#define mmSDMA0_CONTEXT_REG_TYPE2 0x000d -#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 -#define mmSDMA0_CONTEXT_REG_TYPE3 0x000e -#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 -#define mmSDMA0_PUB_REG_TYPE0 0x000f -#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 -#define mmSDMA0_PUB_REG_TYPE1 0x0010 -#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 -#define mmSDMA0_PUB_REG_TYPE2 0x0011 -#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 -#define mmSDMA0_PUB_REG_TYPE3 0x0012 -#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 -#define mmSDMA0_MMHUB_CNTL 0x0013 -#define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 -#define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 -#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 -#define mmSDMA0_POWER_CNTL 0x001a -#define mmSDMA0_POWER_CNTL_BASE_IDX 0 -#define mmSDMA0_CLK_CTRL 0x001b -#define mmSDMA0_CLK_CTRL_BASE_IDX 0 -#define mmSDMA0_CNTL 0x001c -#define mmSDMA0_CNTL_BASE_IDX 0 -#define mmSDMA0_CHICKEN_BITS 0x001d -#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 -#define mmSDMA0_GB_ADDR_CONFIG 0x001e -#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 -#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f -#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 -#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 -#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 -#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 -#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 -#define mmSDMA0_RB_RPTR_FETCH 0x0022 -#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 -#define mmSDMA0_IB_OFFSET_FETCH 0x0023 -#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 -#define mmSDMA0_PROGRAM 0x0024 -#define mmSDMA0_PROGRAM_BASE_IDX 0 -#define mmSDMA0_STATUS_REG 0x0025 -#define mmSDMA0_STATUS_REG_BASE_IDX 0 -#define mmSDMA0_STATUS1_REG 0x0026 -#define mmSDMA0_STATUS1_REG_BASE_IDX 0 -#define mmSDMA0_RD_BURST_CNTL 0x0027 -#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 -#define mmSDMA0_HBM_PAGE_CONFIG 0x0028 -#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 -#define mmSDMA0_UCODE_CHECKSUM 0x0029 -#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 -#define mmSDMA0_F32_CNTL 0x002a -#define mmSDMA0_F32_CNTL_BASE_IDX 0 -#define mmSDMA0_FREEZE 0x002b -#define mmSDMA0_FREEZE_BASE_IDX 0 -#define mmSDMA0_PHASE0_QUANTUM 0x002c -#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 -#define mmSDMA0_PHASE1_QUANTUM 0x002d -#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 -#define mmSDMA_POWER_GATING 0x002e -#define mmSDMA_POWER_GATING_BASE_IDX 0 -#define mmSDMA_PGFSM_CONFIG 0x002f -#define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 -#define mmSDMA_PGFSM_WRITE 0x0030 -#define mmSDMA_PGFSM_WRITE_BASE_IDX 0 -#define mmSDMA_PGFSM_READ 0x0031 -#define mmSDMA_PGFSM_READ_BASE_IDX 0 -#define mmSDMA0_EDC_CONFIG 0x0032 -#define mmSDMA0_EDC_CONFIG_BASE_IDX 0 -#define mmSDMA0_BA_THRESHOLD 0x0033 -#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 -#define mmSDMA0_ID 0x0034 -#define mmSDMA0_ID_BASE_IDX 0 -#define mmSDMA0_VERSION 0x0035 -#define mmSDMA0_VERSION_BASE_IDX 0 -#define mmSDMA0_EDC_COUNTER 0x0036 -#define mmSDMA0_EDC_COUNTER_BASE_IDX 0 -#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 -#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 -#define mmSDMA0_STATUS2_REG 0x0038 -#define mmSDMA0_STATUS2_REG_BASE_IDX 0 -#define mmSDMA0_ATOMIC_CNTL 0x0039 -#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 -#define mmSDMA0_ATOMIC_PREOP_LO 0x003a -#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 -#define mmSDMA0_ATOMIC_PREOP_HI 0x003b -#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 -#define mmSDMA0_UTCL1_CNTL 0x003c -#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 -#define mmSDMA0_UTCL1_WATERMK 0x003d -#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 -#define mmSDMA0_UTCL1_RD_STATUS 0x003e -#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 -#define mmSDMA0_UTCL1_WR_STATUS 0x003f -#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 -#define mmSDMA0_UTCL1_INV0 0x0040 -#define mmSDMA0_UTCL1_INV0_BASE_IDX 0 -#define mmSDMA0_UTCL1_INV1 0x0041 -#define mmSDMA0_UTCL1_INV1_BASE_IDX 0 -#define mmSDMA0_UTCL1_INV2 0x0042 -#define mmSDMA0_UTCL1_INV2_BASE_IDX 0 -#define mmSDMA0_UTCL1_RD_XNACK0 0x0043 -#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 -#define mmSDMA0_UTCL1_RD_XNACK1 0x0044 -#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 -#define mmSDMA0_UTCL1_WR_XNACK0 0x0045 -#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 -#define mmSDMA0_UTCL1_WR_XNACK1 0x0046 -#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 -#define mmSDMA0_UTCL1_TIMEOUT 0x0047 -#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 -#define mmSDMA0_UTCL1_PAGE 0x0048 -#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 -#define mmSDMA0_POWER_CNTL_IDLE 0x0049 -#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 -#define mmSDMA0_RELAX_ORDERING_LUT 0x004a -#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 -#define mmSDMA0_CHICKEN_BITS_2 0x004b -#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 -#define mmSDMA0_STATUS3_REG 0x004c -#define mmSDMA0_STATUS3_REG_BASE_IDX 0 -#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d -#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e -#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_PHASE2_QUANTUM 0x004f -#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 -#define mmSDMA0_ERROR_LOG 0x0050 -#define mmSDMA0_ERROR_LOG_BASE_IDX 0 -#define mmSDMA0_PUB_DUMMY_REG0 0x0051 -#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 -#define mmSDMA0_PUB_DUMMY_REG1 0x0052 -#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 -#define mmSDMA0_PUB_DUMMY_REG2 0x0053 -#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 -#define mmSDMA0_PUB_DUMMY_REG3 0x0054 -#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 -#define mmSDMA0_F32_COUNTER 0x0055 -#define mmSDMA0_F32_COUNTER_BASE_IDX 0 -#define mmSDMA0_UNBREAKABLE 0x0056 -#define mmSDMA0_UNBREAKABLE_BASE_IDX 0 -#define mmSDMA0_PERFMON_CNTL 0x0057 -#define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 -#define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 -#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 -#define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 -#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 -#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a -#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 -#define mmSDMA0_CRD_CNTL 0x005b -#define mmSDMA0_CRD_CNTL_BASE_IDX 0 -#define mmSDMA0_MMHUB_TRUSTLVL 0x005c -#define mmSDMA0_MMHUB_TRUSTLVL_BASE_IDX 0 -#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d -#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 -#define mmSDMA0_ULV_CNTL 0x005e -#define mmSDMA0_ULV_CNTL_BASE_IDX 0 -#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 -#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 -#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 -#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 -#define mmSDMA0_GFX_RB_CNTL 0x0080 -#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_RB_BASE 0x0081 -#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 -#define mmSDMA0_GFX_RB_BASE_HI 0x0082 -#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_RPTR 0x0083 -#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_GFX_RB_RPTR_HI 0x0084 -#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR 0x0085 -#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR_HI 0x0086 -#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 -#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 -#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 -#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_GFX_IB_CNTL 0x008a -#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_IB_RPTR 0x008b -#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_GFX_IB_OFFSET 0x008c -#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_GFX_IB_BASE_LO 0x008d -#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_GFX_IB_BASE_HI 0x008e -#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_GFX_IB_SIZE 0x008f -#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_GFX_SKIP_CNTL 0x0090 -#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 -#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_GFX_DOORBELL 0x0092 -#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 -#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 -#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_STATUS 0x00a8 -#define mmSDMA0_GFX_STATUS_BASE_IDX 0 -#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 -#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_GFX_WATERMARK 0x00aa -#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 -#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab -#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac -#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad -#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af -#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_GFX_PREEMPT 0x00b0 -#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 -#define mmSDMA0_GFX_DUMMY_REG 0x00b1 -#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 -#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 -#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 -#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 -#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 -#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 -#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 -#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 -#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 -#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 -#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 -#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 -#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_CNTL 0x00e0 -#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_BASE 0x00e1 -#define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_BASE_HI 0x00e2 -#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_RPTR 0x00e3 -#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4 -#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR 0x00e5 -#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6 -#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7 -#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_CNTL 0x00ea -#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_RPTR 0x00eb -#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_OFFSET 0x00ec -#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_BASE_LO 0x00ed -#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_BASE_HI 0x00ee -#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_SIZE 0x00ef -#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_PAGE_SKIP_CNTL 0x00f0 -#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1 -#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_PAGE_DOORBELL 0x00f2 -#define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 -#define mmSDMA0_PAGE_STATUS 0x0108 -#define mmSDMA0_PAGE_STATUS_BASE_IDX 0 -#define mmSDMA0_PAGE_DOORBELL_LOG 0x0109 -#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_PAGE_WATERMARK 0x010a -#define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 -#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b -#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c -#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d -#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f -#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_PAGE_PREEMPT 0x0110 -#define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 -#define mmSDMA0_PAGE_DUMMY_REG 0x0111 -#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114 -#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115 -#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120 -#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121 -#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122 -#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123 -#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124 -#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125 -#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126 -#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127 -#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128 -#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129 -#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_CNTL 0x0140 -#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_BASE 0x0141 -#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_BASE_HI 0x0142 -#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_RPTR 0x0143 -#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_RPTR_HI 0x0144 -#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR 0x0145 -#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 -#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147 -#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_CNTL 0x014a -#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_RPTR 0x014b -#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_OFFSET 0x014c -#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_BASE_LO 0x014d -#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_BASE_HI 0x014e -#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_SIZE 0x014f -#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_RLC0_SKIP_CNTL 0x0150 -#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151 -#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC0_DOORBELL 0x0152 -#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 -#define mmSDMA0_RLC0_STATUS 0x0168 -#define mmSDMA0_RLC0_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC0_DOORBELL_LOG 0x0169 -#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_RLC0_WATERMARK 0x016a -#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 -#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b -#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c -#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d -#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f -#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_RLC0_PREEMPT 0x0170 -#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 -#define mmSDMA0_RLC0_DUMMY_REG 0x0171 -#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174 -#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175 -#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180 -#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181 -#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182 -#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183 -#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184 -#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185 -#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186 -#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187 -#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188 -#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189 -#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_CNTL 0x01a0 -#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_BASE 0x01a1 -#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_BASE_HI 0x01a2 -#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_RPTR 0x01a3 -#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4 -#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR 0x01a5 -#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6 -#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7 -#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_CNTL 0x01aa -#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_RPTR 0x01ab -#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_OFFSET 0x01ac -#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_BASE_LO 0x01ad -#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_BASE_HI 0x01ae -#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_SIZE 0x01af -#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_RLC1_SKIP_CNTL 0x01b0 -#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1 -#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC1_DOORBELL 0x01b2 -#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 -#define mmSDMA0_RLC1_STATUS 0x01c8 -#define mmSDMA0_RLC1_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9 -#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_RLC1_WATERMARK 0x01ca -#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 -#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb -#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc -#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd -#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf -#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_RLC1_PREEMPT 0x01d0 -#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 -#define mmSDMA0_RLC1_DUMMY_REG 0x01d1 -#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4 -#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5 -#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0 -#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1 -#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2 -#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3 -#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4 -#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5 -#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6 -#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7 -#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8 -#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9 -#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h deleted file mode 100644 index 412ae457f7e0..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h +++ /dev/null @@ -1,1852 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma0_4_0_SH_MASK_HEADER -#define _sdma0_4_0_SH_MASK_HEADER - - -// addressBlock: sdma0_sdma0dec -//SDMA0_UCODE_ADDR -#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 -#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL -//SDMA0_UCODE_DATA -#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 -#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL -//SDMA0_VM_CNTL -#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 -#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL -//SDMA0_VM_CTX_LO -#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 -#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_VM_CTX_HI -#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 -#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_ACTIVE_FCN_ID -#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 -#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L -#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//SDMA0_VM_CTX_CNTL -#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 -#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 -#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L -#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L -//SDMA0_VIRT_RESET_REQ -#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 -#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f -#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL -#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L -//SDMA0_VF_ENABLE -#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 -#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L -//SDMA0_CONTEXT_REG_TYPE0 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L -//SDMA0_CONTEXT_REG_TYPE1 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 -#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L -#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L -//SDMA0_CONTEXT_REG_TYPE2 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 -#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L -//SDMA0_CONTEXT_REG_TYPE3 -#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 -#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL -//SDMA0_PUB_REG_TYPE0 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 -#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 -#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 -#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 -#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 -#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a -#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b -#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c -#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L -//SDMA0_PUB_REG_TYPE1 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 -#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 -#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 -#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 -#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 -#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa -#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd -#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 -#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 -#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L -#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L -//SDMA0_PUB_REG_TYPE2 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 -#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 -#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa -#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb -#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf -#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 -#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a -#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b -#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c -#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d -#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e -#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L -//SDMA0_PUB_REG_TYPE3 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL -//SDMA0_MMHUB_CNTL -#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 -#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL -//SDMA0_CONTEXT_GROUP_BOUNDARY -#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 -#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL -//SDMA0_POWER_CNTL -#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 -#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 -#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 -#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 -#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 -#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa -#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc -#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L -#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L -#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L -#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L -#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L -#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L -#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L -//SDMA0_CLK_CTRL -#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//SDMA0_CNTL -#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 -#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 -#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 -#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 -#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 -#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 -#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 -#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c -#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d -#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e -#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L -#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L -#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L -#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L -#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L -#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L -#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L -#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L -#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L -#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L -//SDMA0_CHICKEN_BITS -#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 -#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 -#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 -#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 -#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa -#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 -#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 -#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 -#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 -#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 -#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a -#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c -#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e -#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L -#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L -#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L -#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L -#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L -#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L -#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L -#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L -#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L -#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L -#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L -#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L -#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L -//SDMA0_GB_ADDR_CONFIG -#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 -#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc -#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 -#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L -#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L -#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L -//SDMA0_GB_ADDR_CONFIG_READ -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 -#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L -#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L -//SDMA0_RB_RPTR_FETCH_HI -#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL -#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 -#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL -//SDMA0_RB_RPTR_FETCH -#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 -#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL -//SDMA0_IB_OFFSET_FETCH -#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 -#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL -//SDMA0_PROGRAM -#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 -#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL -//SDMA0_STATUS_REG -#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 -#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 -#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 -#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 -#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 -#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 -#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 -#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 -#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 -#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 -#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa -#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb -#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc -#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd -#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe -#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf -#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 -#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 -#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 -#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 -#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 -#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 -#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 -#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 -#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a -#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b -#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c -#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e -#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f -#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L -#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L -#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L -#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L -#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L -#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L -#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L -#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L -#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L -#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L -#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L -#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L -#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L -#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L -#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L -#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L -#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L -#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L -#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L -#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L -#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L -#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L -#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L -#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L -#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L -#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L -#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L -#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L -#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L -//SDMA0_STATUS1_REG -#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 -#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 -#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 -#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 -#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 -#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 -#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 -#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 -#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa -#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd -#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe -#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf -#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 -#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 -#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L -#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L -#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L -#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L -#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L -#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L -#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L -#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L -#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L -#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L -#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L -#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L -#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L -#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L -//SDMA0_RD_BURST_CNTL -#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 -#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L -//SDMA0_HBM_PAGE_CONFIG -#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 -#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L -//SDMA0_UCODE_CHECKSUM -#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 -#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL -//SDMA0_F32_CNTL -#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 -#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 -#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L -#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L -//SDMA0_FREEZE -#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 -#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 -#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 -#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 -#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L -#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L -#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L -#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L -//SDMA0_PHASE0_QUANTUM -#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L -//SDMA0_PHASE1_QUANTUM -#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L -//SDMA_POWER_GATING -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 -#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 -#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 -#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L -#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L -#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L -#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L -//SDMA_PGFSM_CONFIG -#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 -#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 -#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 -#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa -#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb -#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc -#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd -#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b -#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c -#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL -#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L -#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L -#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L -#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L -#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L -#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L -#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L -#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L -//SDMA_PGFSM_WRITE -#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 -#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL -//SDMA_PGFSM_READ -#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 -#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL -//SDMA0_EDC_CONFIG -#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 -#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 -#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L -#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L -//SDMA0_BA_THRESHOLD -#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 -#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 -#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL -#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L -//SDMA0_ID -#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 -#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL -//SDMA0_VERSION -#define SDMA0_VERSION__MINVER__SHIFT 0x0 -#define SDMA0_VERSION__MAJVER__SHIFT 0x8 -#define SDMA0_VERSION__REV__SHIFT 0x10 -#define SDMA0_VERSION__MINVER_MASK 0x0000007FL -#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L -#define SDMA0_VERSION__REV_MASK 0x003F0000L -//SDMA0_EDC_COUNTER -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 -#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 -#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 -#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe -#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf -#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L -#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L -#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L -#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L -#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L -#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L -//SDMA0_EDC_COUNTER_CLEAR -#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 -#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L -//SDMA0_STATUS2_REG -#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 -#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 -#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 -#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L -#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL -#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L -//SDMA0_ATOMIC_CNTL -#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 -#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f -#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL -#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L -//SDMA0_ATOMIC_PREOP_LO -#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 -#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL -//SDMA0_ATOMIC_PREOP_HI -#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 -#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_CNTL -#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 -#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 -#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb -#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe -#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 -#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d -#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L -#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL -#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L -#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L -#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L -#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L -//SDMA0_UTCL1_WATERMK -#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 -#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa -#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 -#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a -#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL -#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L -#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L -#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L -//SDMA0_UTCL1_RD_STATUS -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 -#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 -#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 -#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 -#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 -#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 -#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a -#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d -#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e -#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L -#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L -#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L -#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L -#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L -#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L -//SDMA0_UTCL1_WR_STATUS -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 -#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 -#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 -#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 -#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 -#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 -#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L -#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L -#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L -//SDMA0_UTCL1_INV0 -#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 -#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 -#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 -#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 -#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 -#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 -#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 -#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 -#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 -#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 -#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa -#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb -#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc -#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c -#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L -#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L -#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L -#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L -#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L -#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L -#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L -#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L -#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L -#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L -#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L -#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L -#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L -#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L -//SDMA0_UTCL1_INV1 -#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 -#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_INV2 -#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 -#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_RD_XNACK0 -#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 -#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_RD_XNACK1 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 -#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a -#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L -#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L -//SDMA0_UTCL1_WR_XNACK0 -#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 -#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_WR_XNACK1 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 -#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a -#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L -#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L -//SDMA0_UTCL1_TIMEOUT -#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 -#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 -#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL -#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L -//SDMA0_UTCL1_PAGE -#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 -#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 -#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 -#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 -#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L -#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL -#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L -#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L -//SDMA0_POWER_CNTL_IDLE -#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 -#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 -#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 -#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL -#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L -#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L -//SDMA0_RELAX_ORDERING_LUT -#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 -#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 -#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 -#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 -#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 -#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 -#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa -#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb -#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc -#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd -#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe -#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b -#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c -#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d -#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e -#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f -#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L -#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L -#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L -#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L -#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L -#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L -#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L -#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L -#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L -#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L -#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L -#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L -#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L -#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L -#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L -//SDMA0_CHICKEN_BITS_2 -#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 -#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL -//SDMA0_STATUS3_REG -#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 -#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 -#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 -#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL -#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L -#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L -//SDMA0_PHYSICAL_ADDR_LO -#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 -#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 -#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 -#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc -#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L -#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L -#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L -#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L -//SDMA0_PHYSICAL_ADDR_HI -#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL -//SDMA0_PHASE2_QUANTUM -#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L -//SDMA0_ERROR_LOG -#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 -#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 -#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL -#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L -//SDMA0_PUB_DUMMY_REG0 -#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL -//SDMA0_PUB_DUMMY_REG1 -#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL -//SDMA0_PUB_DUMMY_REG2 -#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL -//SDMA0_PUB_DUMMY_REG3 -#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL -//SDMA0_F32_COUNTER -#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 -#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL -//SDMA0_UNBREAKABLE -#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 -#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L -//SDMA0_PERFMON_CNTL -#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 -#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 -#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 -#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa -#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb -#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc -#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L -#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L -#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL -#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L -#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L -#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L -//SDMA0_PERFCOUNTER0_RESULT -#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 -#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL -//SDMA0_PERFCOUNTER1_RESULT -#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 -#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL -//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L -//SDMA0_CRD_CNTL -#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 -#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd -#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L -#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L -//SDMA0_MMHUB_TRUSTLVL -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L -//SDMA0_GPU_IOV_VIOLATION_LOG -#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 -#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 -#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 -#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 -#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L -#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL -#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L -//SDMA0_ULV_CNTL -#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 -#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d -#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e -#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f -#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL -#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L -#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L -#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L -//SDMA0_EA_DBIT_ADDR_DATA -#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 -#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL -//SDMA0_EA_DBIT_ADDR_INDEX -#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 -#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L -//SDMA0_GFX_RB_CNTL -#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_GFX_RB_BASE -#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_BASE_HI -#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_GFX_RB_RPTR -#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_RPTR_HI -#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR -#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_HI -#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_POLL_CNTL -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_GFX_RB_RPTR_ADDR_HI -#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_RPTR_ADDR_LO -#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_GFX_IB_CNTL -#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_GFX_IB_RPTR -#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_GFX_IB_OFFSET -#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_GFX_IB_BASE_LO -#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_GFX_IB_BASE_HI -#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_IB_SIZE -#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_GFX_SKIP_CNTL -#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_GFX_CONTEXT_STATUS -#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_GFX_DOORBELL -#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_GFX_CONTEXT_CNTL -#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 -#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L -//SDMA0_GFX_STATUS -#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_GFX_DOORBELL_LOG -#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_GFX_WATERMARK -#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_GFX_DOORBELL_OFFSET -#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_GFX_CSA_ADDR_LO -#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_GFX_CSA_ADDR_HI -#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_IB_SUB_REMAIN -#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_GFX_PREEMPT -#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_GFX_DUMMY_REG -#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_GFX_RB_AQL_CNTL -#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_GFX_MINOR_PTR_UPDATE -#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_GFX_MIDCMD_DATA0 -#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA1 -#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA2 -#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA3 -#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA4 -#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA5 -#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA6 -#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA7 -#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA8 -#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_CNTL -#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA0_PAGE_RB_CNTL -#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_PAGE_RB_BASE -#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_BASE_HI -#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_PAGE_RB_RPTR -#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_RPTR_HI -#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_WPTR -#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_WPTR_HI -#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_WPTR_POLL_CNTL -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_PAGE_RB_RPTR_ADDR_HI -#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_RPTR_ADDR_LO -#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_PAGE_IB_CNTL -#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_PAGE_IB_RPTR -#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_PAGE_IB_OFFSET -#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_PAGE_IB_BASE_LO -#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_PAGE_IB_BASE_HI -#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_PAGE_IB_SIZE -#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_PAGE_SKIP_CNTL -#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_PAGE_CONTEXT_STATUS -#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_PAGE_DOORBELL -#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_PAGE_STATUS -#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_PAGE_DOORBELL_LOG -#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_PAGE_WATERMARK -#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_PAGE_DOORBELL_OFFSET -#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_PAGE_CSA_ADDR_LO -#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_PAGE_CSA_ADDR_HI -#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_PAGE_IB_SUB_REMAIN -#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_PAGE_PREEMPT -#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_PAGE_DUMMY_REG -#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI -#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO -#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_PAGE_RB_AQL_CNTL -#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_PAGE_MINOR_PTR_UPDATE -#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_PAGE_MIDCMD_DATA0 -#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA1 -#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA2 -#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA3 -#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA4 -#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA5 -#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA6 -#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA7 -#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA8 -#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_CNTL -#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA0_RLC0_RB_CNTL -#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_RLC0_RB_BASE -#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_BASE_HI -#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_RLC0_RB_RPTR -#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_RPTR_HI -#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR -#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_HI -#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_POLL_CNTL -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_RLC0_RB_RPTR_ADDR_HI -#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_RPTR_ADDR_LO -#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC0_IB_CNTL -#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_RLC0_IB_RPTR -#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC0_IB_OFFSET -#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC0_IB_BASE_LO -#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_RLC0_IB_BASE_HI -#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_IB_SIZE -#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_RLC0_SKIP_CNTL -#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_RLC0_CONTEXT_STATUS -#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_RLC0_DOORBELL -#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_RLC0_STATUS -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_RLC0_DOORBELL_LOG -#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_RLC0_WATERMARK -#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_RLC0_DOORBELL_OFFSET -#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_RLC0_CSA_ADDR_LO -#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC0_CSA_ADDR_HI -#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_IB_SUB_REMAIN -#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_RLC0_PREEMPT -#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_RLC0_DUMMY_REG -#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC0_RB_AQL_CNTL -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_RLC0_MINOR_PTR_UPDATE -#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_RLC0_MIDCMD_DATA0 -#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA1 -#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA2 -#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA3 -#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA4 -#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA5 -#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA6 -#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA7 -#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA8 -#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_CNTL -#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA0_RLC1_RB_CNTL -#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_RLC1_RB_BASE -#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_BASE_HI -#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_RLC1_RB_RPTR -#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_RPTR_HI -#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR -#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_HI -#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_POLL_CNTL -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_RLC1_RB_RPTR_ADDR_HI -#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_RPTR_ADDR_LO -#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC1_IB_CNTL -#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_RLC1_IB_RPTR -#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC1_IB_OFFSET -#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC1_IB_BASE_LO -#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_RLC1_IB_BASE_HI -#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_IB_SIZE -#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_RLC1_SKIP_CNTL -#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_RLC1_CONTEXT_STATUS -#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_RLC1_DOORBELL -#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_RLC1_STATUS -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_RLC1_DOORBELL_LOG -#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_RLC1_WATERMARK -#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_RLC1_DOORBELL_OFFSET -#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_RLC1_CSA_ADDR_LO -#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC1_CSA_ADDR_HI -#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_IB_SUB_REMAIN -#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_RLC1_PREEMPT -#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_RLC1_DUMMY_REG -#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC1_RB_AQL_CNTL -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_RLC1_MINOR_PTR_UPDATE -#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_RLC1_MIDCMD_DATA0 -#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA1 -#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA2 -#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA3 -#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA4 -#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA5 -#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA6 -#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA7 -#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA8 -#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_CNTL -#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h deleted file mode 100644 index 85c5c5e3ce7d..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma1_4_0_DEFAULT_HEADER -#define _sdma1_4_0_DEFAULT_HEADER - - -// addressBlock: sdma1_sdma1dec -#define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000 -#define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000 -#define mmSDMA1_VM_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000 -#define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000 -#define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000 -#define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f -#define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff -#define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff -#define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 -#define mmSDMA1_PUB_REG_TYPE0_DEFAULT 0x3c000000 -#define mmSDMA1_PUB_REG_TYPE1_DEFAULT 0x30003882 -#define mmSDMA1_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 -#define mmSDMA1_PUB_REG_TYPE3_DEFAULT 0x00000000 -#define mmSDMA1_MMHUB_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 -#define mmSDMA1_POWER_CNTL_DEFAULT 0x0003c000 -#define mmSDMA1_CLK_CTRL_DEFAULT 0xff000100 -#define mmSDMA1_CNTL_DEFAULT 0x00000002 -#define mmSDMA1_CHICKEN_BITS_DEFAULT 0x00831f07 -#define mmSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00100012 -#define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 -#define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 -#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000 -#define mmSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000 -#define mmSDMA1_PROGRAM_DEFAULT 0x00000000 -#define mmSDMA1_STATUS_REG_DEFAULT 0x46dee557 -#define mmSDMA1_STATUS1_REG_DEFAULT 0x000003ff -#define mmSDMA1_RD_BURST_CNTL_DEFAULT 0x00000003 -#define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000 -#define mmSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000 -#define mmSDMA1_F32_CNTL_DEFAULT 0x00000001 -#define mmSDMA1_FREEZE_DEFAULT 0x00000000 -#define mmSDMA1_PHASE0_QUANTUM_DEFAULT 0x00010002 -#define mmSDMA1_PHASE1_QUANTUM_DEFAULT 0x00010002 -#define mmSDMA1_EDC_CONFIG_DEFAULT 0x00000002 -#define mmSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff -#define mmSDMA1_ID_DEFAULT 0x00000001 -#define mmSDMA1_VERSION_DEFAULT 0x00000400 -#define mmSDMA1_EDC_COUNTER_DEFAULT 0x00000000 -#define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 -#define mmSDMA1_STATUS2_REG_DEFAULT 0x00000001 -#define mmSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200 -#define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000 -#define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_CNTL_DEFAULT 0xd0003019 -#define mmSDMA1_UTCL1_WATERMK_DEFAULT 0xfffbe1fe -#define mmSDMA1_UTCL1_RD_STATUS_DEFAULT 0x201001ff -#define mmSDMA1_UTCL1_WR_STATUS_DEFAULT 0x503001ff -#define mmSDMA1_UTCL1_INV0_DEFAULT 0x00000600 -#define mmSDMA1_UTCL1_INV1_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_INV2_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00010001 -#define mmSDMA1_UTCL1_PAGE_DEFAULT 0x000003e0 -#define mmSDMA1_POWER_CNTL_IDLE_DEFAULT 0x06060200 -#define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 -#define mmSDMA1_CHICKEN_BITS_2_DEFAULT 0x00000005 -#define mmSDMA1_STATUS3_REG_DEFAULT 0x00100000 -#define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_PHASE2_QUANTUM_DEFAULT 0x00010002 -#define mmSDMA1_ERROR_LOG_DEFAULT 0x0000000f -#define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000 -#define mmSDMA1_PUB_DUMMY_REG1_DEFAULT 0x00000000 -#define mmSDMA1_PUB_DUMMY_REG2_DEFAULT 0x00000000 -#define mmSDMA1_PUB_DUMMY_REG3_DEFAULT 0x00000000 -#define mmSDMA1_F32_COUNTER_DEFAULT 0x00000000 -#define mmSDMA1_UNBREAKABLE_DEFAULT 0x00000000 -#define mmSDMA1_PERFMON_CNTL_DEFAULT 0x000ff7fd -#define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 -#define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 -#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 -#define mmSDMA1_CRD_CNTL_DEFAULT 0x000085c0 -#define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT 0x00000000 -#define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 -#define mmSDMA1_ULV_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 -#define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA1_GFX_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_GFX_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA1_GFX_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_GFX_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_GFX_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA1_GFX_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA1_GFX_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 -#define mmSDMA1_GFX_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_GFX_STATUS_DEFAULT 0x00000000 -#define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA1_GFX_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA1_GFX_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA1_GFX_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA1_PAGE_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA1_PAGE_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 -#define mmSDMA1_PAGE_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_STATUS_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA1_RLC0_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA1_RLC0_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 -#define mmSDMA1_RLC0_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_STATUS_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA1_RLC1_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA1_RLC1_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 -#define mmSDMA1_RLC1_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_STATUS_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h deleted file mode 100644 index 92150d6b65b8..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h +++ /dev/null @@ -1,539 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma1_4_0_OFFSET_HEADER -#define _sdma1_4_0_OFFSET_HEADER - - - -// addressBlock: sdma1_sdma1dec -// base address: 0x5180 -#define mmSDMA1_UCODE_ADDR 0x0000 -#define mmSDMA1_UCODE_ADDR_BASE_IDX 0 -#define mmSDMA1_UCODE_DATA 0x0001 -#define mmSDMA1_UCODE_DATA_BASE_IDX 0 -#define mmSDMA1_VM_CNTL 0x0004 -#define mmSDMA1_VM_CNTL_BASE_IDX 0 -#define mmSDMA1_VM_CTX_LO 0x0005 -#define mmSDMA1_VM_CTX_LO_BASE_IDX 0 -#define mmSDMA1_VM_CTX_HI 0x0006 -#define mmSDMA1_VM_CTX_HI_BASE_IDX 0 -#define mmSDMA1_ACTIVE_FCN_ID 0x0007 -#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0 -#define mmSDMA1_VM_CTX_CNTL 0x0008 -#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0 -#define mmSDMA1_VIRT_RESET_REQ 0x0009 -#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0 -#define mmSDMA1_VF_ENABLE 0x000a -#define mmSDMA1_VF_ENABLE_BASE_IDX 0 -#define mmSDMA1_CONTEXT_REG_TYPE0 0x000b -#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0 -#define mmSDMA1_CONTEXT_REG_TYPE1 0x000c -#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0 -#define mmSDMA1_CONTEXT_REG_TYPE2 0x000d -#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0 -#define mmSDMA1_CONTEXT_REG_TYPE3 0x000e -#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0 -#define mmSDMA1_PUB_REG_TYPE0 0x000f -#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0 -#define mmSDMA1_PUB_REG_TYPE1 0x0010 -#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0 -#define mmSDMA1_PUB_REG_TYPE2 0x0011 -#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0 -#define mmSDMA1_PUB_REG_TYPE3 0x0012 -#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0 -#define mmSDMA1_MMHUB_CNTL 0x0013 -#define mmSDMA1_MMHUB_CNTL_BASE_IDX 0 -#define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019 -#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 -#define mmSDMA1_POWER_CNTL 0x001a -#define mmSDMA1_POWER_CNTL_BASE_IDX 0 -#define mmSDMA1_CLK_CTRL 0x001b -#define mmSDMA1_CLK_CTRL_BASE_IDX 0 -#define mmSDMA1_CNTL 0x001c -#define mmSDMA1_CNTL_BASE_IDX 0 -#define mmSDMA1_CHICKEN_BITS 0x001d -#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0 -#define mmSDMA1_GB_ADDR_CONFIG 0x001e -#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 -#define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f -#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 -#define mmSDMA1_RB_RPTR_FETCH_HI 0x0020 -#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 -#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 -#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 -#define mmSDMA1_RB_RPTR_FETCH 0x0022 -#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0 -#define mmSDMA1_IB_OFFSET_FETCH 0x0023 -#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 -#define mmSDMA1_PROGRAM 0x0024 -#define mmSDMA1_PROGRAM_BASE_IDX 0 -#define mmSDMA1_STATUS_REG 0x0025 -#define mmSDMA1_STATUS_REG_BASE_IDX 0 -#define mmSDMA1_STATUS1_REG 0x0026 -#define mmSDMA1_STATUS1_REG_BASE_IDX 0 -#define mmSDMA1_RD_BURST_CNTL 0x0027 -#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0 -#define mmSDMA1_HBM_PAGE_CONFIG 0x0028 -#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 -#define mmSDMA1_UCODE_CHECKSUM 0x0029 -#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0 -#define mmSDMA1_F32_CNTL 0x002a -#define mmSDMA1_F32_CNTL_BASE_IDX 0 -#define mmSDMA1_FREEZE 0x002b -#define mmSDMA1_FREEZE_BASE_IDX 0 -#define mmSDMA1_PHASE0_QUANTUM 0x002c -#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0 -#define mmSDMA1_PHASE1_QUANTUM 0x002d -#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0 -#define mmSDMA1_EDC_CONFIG 0x0032 -#define mmSDMA1_EDC_CONFIG_BASE_IDX 0 -#define mmSDMA1_BA_THRESHOLD 0x0033 -#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0 -#define mmSDMA1_ID 0x0034 -#define mmSDMA1_ID_BASE_IDX 0 -#define mmSDMA1_VERSION 0x0035 -#define mmSDMA1_VERSION_BASE_IDX 0 -#define mmSDMA1_EDC_COUNTER 0x0036 -#define mmSDMA1_EDC_COUNTER_BASE_IDX 0 -#define mmSDMA1_EDC_COUNTER_CLEAR 0x0037 -#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 -#define mmSDMA1_STATUS2_REG 0x0038 -#define mmSDMA1_STATUS2_REG_BASE_IDX 0 -#define mmSDMA1_ATOMIC_CNTL 0x0039 -#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0 -#define mmSDMA1_ATOMIC_PREOP_LO 0x003a -#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 -#define mmSDMA1_ATOMIC_PREOP_HI 0x003b -#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 -#define mmSDMA1_UTCL1_CNTL 0x003c -#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0 -#define mmSDMA1_UTCL1_WATERMK 0x003d -#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0 -#define mmSDMA1_UTCL1_RD_STATUS 0x003e -#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 -#define mmSDMA1_UTCL1_WR_STATUS 0x003f -#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 -#define mmSDMA1_UTCL1_INV0 0x0040 -#define mmSDMA1_UTCL1_INV0_BASE_IDX 0 -#define mmSDMA1_UTCL1_INV1 0x0041 -#define mmSDMA1_UTCL1_INV1_BASE_IDX 0 -#define mmSDMA1_UTCL1_INV2 0x0042 -#define mmSDMA1_UTCL1_INV2_BASE_IDX 0 -#define mmSDMA1_UTCL1_RD_XNACK0 0x0043 -#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 -#define mmSDMA1_UTCL1_RD_XNACK1 0x0044 -#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 -#define mmSDMA1_UTCL1_WR_XNACK0 0x0045 -#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 -#define mmSDMA1_UTCL1_WR_XNACK1 0x0046 -#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 -#define mmSDMA1_UTCL1_TIMEOUT 0x0047 -#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 -#define mmSDMA1_UTCL1_PAGE 0x0048 -#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0 -#define mmSDMA1_POWER_CNTL_IDLE 0x0049 -#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 -#define mmSDMA1_RELAX_ORDERING_LUT 0x004a -#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 -#define mmSDMA1_CHICKEN_BITS_2 0x004b -#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0 -#define mmSDMA1_STATUS3_REG 0x004c -#define mmSDMA1_STATUS3_REG_BASE_IDX 0 -#define mmSDMA1_PHYSICAL_ADDR_LO 0x004d -#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_PHYSICAL_ADDR_HI 0x004e -#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_PHASE2_QUANTUM 0x004f -#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0 -#define mmSDMA1_ERROR_LOG 0x0050 -#define mmSDMA1_ERROR_LOG_BASE_IDX 0 -#define mmSDMA1_PUB_DUMMY_REG0 0x0051 -#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 -#define mmSDMA1_PUB_DUMMY_REG1 0x0052 -#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 -#define mmSDMA1_PUB_DUMMY_REG2 0x0053 -#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 -#define mmSDMA1_PUB_DUMMY_REG3 0x0054 -#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 -#define mmSDMA1_F32_COUNTER 0x0055 -#define mmSDMA1_F32_COUNTER_BASE_IDX 0 -#define mmSDMA1_UNBREAKABLE 0x0056 -#define mmSDMA1_UNBREAKABLE_BASE_IDX 0 -#define mmSDMA1_PERFMON_CNTL 0x0057 -#define mmSDMA1_PERFMON_CNTL_BASE_IDX 0 -#define mmSDMA1_PERFCOUNTER0_RESULT 0x0058 -#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0 -#define mmSDMA1_PERFCOUNTER1_RESULT 0x0059 -#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0 -#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a -#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 -#define mmSDMA1_CRD_CNTL 0x005b -#define mmSDMA1_CRD_CNTL_BASE_IDX 0 -#define mmSDMA1_MMHUB_TRUSTLVL 0x005c -#define mmSDMA1_MMHUB_TRUSTLVL_BASE_IDX 0 -#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d -#define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 -#define mmSDMA1_ULV_CNTL 0x005e -#define mmSDMA1_ULV_CNTL_BASE_IDX 0 -#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060 -#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 -#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061 -#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 -#define mmSDMA1_GFX_RB_CNTL 0x0080 -#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_RB_BASE 0x0081 -#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0 -#define mmSDMA1_GFX_RB_BASE_HI 0x0082 -#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_RPTR 0x0083 -#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_GFX_RB_RPTR_HI 0x0084 -#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR 0x0085 -#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR_HI 0x0086 -#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087 -#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088 -#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089 -#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_GFX_IB_CNTL 0x008a -#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_IB_RPTR 0x008b -#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_GFX_IB_OFFSET 0x008c -#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_GFX_IB_BASE_LO 0x008d -#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_GFX_IB_BASE_HI 0x008e -#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_GFX_IB_SIZE 0x008f -#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_GFX_SKIP_CNTL 0x0090 -#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_CONTEXT_STATUS 0x0091 -#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_GFX_DOORBELL 0x0092 -#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0 -#define mmSDMA1_GFX_CONTEXT_CNTL 0x0093 -#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_STATUS 0x00a8 -#define mmSDMA1_GFX_STATUS_BASE_IDX 0 -#define mmSDMA1_GFX_DOORBELL_LOG 0x00a9 -#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_GFX_WATERMARK 0x00aa -#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0 -#define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab -#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac -#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad -#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af -#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_GFX_PREEMPT 0x00b0 -#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0 -#define mmSDMA1_GFX_DUMMY_REG 0x00b1 -#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4 -#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5 -#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0 -#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1 -#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2 -#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3 -#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4 -#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5 -#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6 -#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7 -#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8 -#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9 -#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_CNTL 0x00e0 -#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_BASE 0x00e1 -#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_BASE_HI 0x00e2 -#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_RPTR 0x00e3 -#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4 -#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR 0x00e5 -#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6 -#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7 -#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_CNTL 0x00ea -#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_RPTR 0x00eb -#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_OFFSET 0x00ec -#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_BASE_LO 0x00ed -#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_BASE_HI 0x00ee -#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_SIZE 0x00ef -#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_PAGE_SKIP_CNTL 0x00f0 -#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1 -#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_PAGE_DOORBELL 0x00f2 -#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0 -#define mmSDMA1_PAGE_STATUS 0x0108 -#define mmSDMA1_PAGE_STATUS_BASE_IDX 0 -#define mmSDMA1_PAGE_DOORBELL_LOG 0x0109 -#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_PAGE_WATERMARK 0x010a -#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0 -#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b -#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c -#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d -#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f -#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_PAGE_PREEMPT 0x0110 -#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0 -#define mmSDMA1_PAGE_DUMMY_REG 0x0111 -#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114 -#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115 -#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120 -#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121 -#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122 -#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123 -#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124 -#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125 -#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126 -#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127 -#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128 -#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129 -#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_CNTL 0x0140 -#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_BASE 0x0141 -#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_BASE_HI 0x0142 -#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_RPTR 0x0143 -#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_RPTR_HI 0x0144 -#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR 0x0145 -#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR_HI 0x0146 -#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147 -#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_CNTL 0x014a -#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_RPTR 0x014b -#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_OFFSET 0x014c -#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_BASE_LO 0x014d -#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_BASE_HI 0x014e -#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_SIZE 0x014f -#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_RLC0_SKIP_CNTL 0x0150 -#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151 -#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC0_DOORBELL 0x0152 -#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0 -#define mmSDMA1_RLC0_STATUS 0x0168 -#define mmSDMA1_RLC0_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC0_DOORBELL_LOG 0x0169 -#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_RLC0_WATERMARK 0x016a -#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0 -#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b -#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c -#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d -#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f -#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_RLC0_PREEMPT 0x0170 -#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0 -#define mmSDMA1_RLC0_DUMMY_REG 0x0171 -#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174 -#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175 -#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180 -#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181 -#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182 -#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183 -#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184 -#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185 -#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186 -#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187 -#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188 -#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189 -#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_CNTL 0x01a0 -#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_BASE 0x01a1 -#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_BASE_HI 0x01a2 -#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_RPTR 0x01a3 -#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4 -#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR 0x01a5 -#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6 -#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7 -#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_CNTL 0x01aa -#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_RPTR 0x01ab -#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_OFFSET 0x01ac -#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_BASE_LO 0x01ad -#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_BASE_HI 0x01ae -#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_SIZE 0x01af -#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_RLC1_SKIP_CNTL 0x01b0 -#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1 -#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC1_DOORBELL 0x01b2 -#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0 -#define mmSDMA1_RLC1_STATUS 0x01c8 -#define mmSDMA1_RLC1_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9 -#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_RLC1_WATERMARK 0x01ca -#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0 -#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb -#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc -#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd -#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf -#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_RLC1_PREEMPT 0x01d0 -#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0 -#define mmSDMA1_RLC1_DUMMY_REG 0x01d1 -#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4 -#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5 -#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0 -#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1 -#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2 -#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3 -#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4 -#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5 -#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6 -#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7 -#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8 -#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9 -#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h deleted file mode 100644 index 25decdf96d16..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h +++ /dev/null @@ -1,1810 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma1_4_0_SH_MASK_HEADER -#define _sdma1_4_0_SH_MASK_HEADER - - -// addressBlock: sdma1_sdma1dec -//SDMA1_UCODE_ADDR -#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 -#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL -//SDMA1_UCODE_DATA -#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 -#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL -//SDMA1_VM_CNTL -#define SDMA1_VM_CNTL__CMD__SHIFT 0x0 -#define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL -//SDMA1_VM_CTX_LO -#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 -#define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_VM_CTX_HI -#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 -#define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_ACTIVE_FCN_ID -#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 -#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L -#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//SDMA1_VM_CTX_CNTL -#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 -#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 -#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L -#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L -//SDMA1_VIRT_RESET_REQ -#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 -#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f -#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL -#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L -//SDMA1_VF_ENABLE -#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 -#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L -//SDMA1_CONTEXT_REG_TYPE0 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L -//SDMA1_CONTEXT_REG_TYPE1 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd -#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 -#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L -#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L -#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L -//SDMA1_CONTEXT_REG_TYPE2 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 -#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L -#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L -//SDMA1_CONTEXT_REG_TYPE3 -#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 -#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL -//SDMA1_PUB_REG_TYPE0 -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 -#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 -#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 -#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 -#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 -#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 -#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a -#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b -#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c -#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d -#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e -#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L -#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L -#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L -#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L -#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L -//SDMA1_PUB_REG_TYPE1 -#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 -#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 -#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 -#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 -#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 -#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 -#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 -#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 -#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa -#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb -#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc -#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd -#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 -#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 -#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 -#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f -#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L -#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L -#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L -#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L -#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L -#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L -#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L -#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L -#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L -#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L -#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L -//SDMA1_PUB_REG_TYPE2 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 -#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 -#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa -#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb -#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf -#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 -#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a -#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b -#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL__SHIFT 0x1c -#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d -#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e -#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L -#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L -#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L -#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L -#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL_MASK 0x10000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L -#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L -//SDMA1_PUB_REG_TYPE3 -#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 -#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 -#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 -#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L -#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L -#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL -//SDMA1_MMHUB_CNTL -#define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 -#define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL -//SDMA1_CONTEXT_GROUP_BOUNDARY -#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 -#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL -//SDMA1_POWER_CNTL -#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 -#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 -#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa -#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb -#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc -#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L -#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L -#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L -#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L -#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L -//SDMA1_CLK_CTRL -#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//SDMA1_CNTL -#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 -#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 -#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 -#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 -#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 -#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 -#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 -#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 -#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c -#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d -#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e -#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L -#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L -#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L -#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L -#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L -#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L -#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L -#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L -#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L -#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L -//SDMA1_CHICKEN_BITS -#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 -#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 -#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 -#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 -#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa -#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 -#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 -#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 -#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 -#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 -#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a -#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c -#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e -#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L -#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L -#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L -#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L -#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L -#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L -#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L -#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L -#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L -#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L -#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L -#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L -#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L -//SDMA1_GB_ADDR_CONFIG -#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 -#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc -#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 -#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L -#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L -#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L -//SDMA1_GB_ADDR_CONFIG_READ -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 -#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L -#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L -//SDMA1_RB_RPTR_FETCH_HI -#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 -#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL -#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 -#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL -//SDMA1_RB_RPTR_FETCH -#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 -#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL -//SDMA1_IB_OFFSET_FETCH -#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 -#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL -//SDMA1_PROGRAM -#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 -#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL -//SDMA1_STATUS_REG -#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 -#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 -#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 -#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 -#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 -#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 -#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 -#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 -#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 -#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 -#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa -#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb -#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc -#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd -#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe -#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf -#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 -#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 -#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 -#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 -#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 -#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 -#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 -#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 -#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a -#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b -#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c -#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e -#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f -#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L -#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L -#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L -#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L -#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L -#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L -#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L -#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L -#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L -#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L -#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L -#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L -#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L -#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L -#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L -#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L -#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L -#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L -#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L -#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L -#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L -#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L -#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L -#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L -#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L -#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L -#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L -#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L -#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L -//SDMA1_STATUS1_REG -#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 -#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 -#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 -#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 -#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 -#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 -#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 -#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 -#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa -#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd -#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe -#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf -#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 -#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 -#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L -#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L -#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L -#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L -#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L -#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L -#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L -#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L -#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L -#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L -#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L -#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L -#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L -#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L -//SDMA1_RD_BURST_CNTL -#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 -#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L -//SDMA1_HBM_PAGE_CONFIG -#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 -#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L -//SDMA1_UCODE_CHECKSUM -#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 -#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL -//SDMA1_F32_CNTL -#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 -#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 -#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L -#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L -//SDMA1_FREEZE -#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 -#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 -#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 -#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 -#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L -#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L -#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L -#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L -//SDMA1_PHASE0_QUANTUM -#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L -//SDMA1_PHASE1_QUANTUM -#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L -//SDMA1_EDC_CONFIG -#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 -#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 -#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L -#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L -//SDMA1_BA_THRESHOLD -#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 -#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 -#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL -#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L -//SDMA1_ID -#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 -#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL -//SDMA1_VERSION -#define SDMA1_VERSION__MINVER__SHIFT 0x0 -#define SDMA1_VERSION__MAJVER__SHIFT 0x8 -#define SDMA1_VERSION__REV__SHIFT 0x10 -#define SDMA1_VERSION__MINVER_MASK 0x0000007FL -#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L -#define SDMA1_VERSION__REV_MASK 0x003F0000L -//SDMA1_EDC_COUNTER -#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 -#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 -#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 -#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 -#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 -#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 -#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe -#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf -#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 -#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L -#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L -#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L -#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L -#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L -#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L -#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L -#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L -#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L -//SDMA1_EDC_COUNTER_CLEAR -#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 -#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L -//SDMA1_STATUS2_REG -#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 -#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 -#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 -#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L -#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL -#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L -//SDMA1_ATOMIC_CNTL -#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 -#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f -#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL -#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L -//SDMA1_ATOMIC_PREOP_LO -#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 -#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL -//SDMA1_ATOMIC_PREOP_HI -#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 -#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL -//SDMA1_UTCL1_CNTL -#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 -#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 -#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb -#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe -#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 -#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d -#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L -#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL -#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L -#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L -#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L -#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L -//SDMA1_UTCL1_WATERMK -#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 -#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa -#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 -#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a -#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL -#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L -#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L -#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L -//SDMA1_UTCL1_RD_STATUS -#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 -#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 -#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 -#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 -#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 -#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 -#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 -#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 -#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 -#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 -#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa -#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb -#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc -#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd -#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe -#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf -#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 -#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 -#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 -#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 -#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 -#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 -#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 -#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a -#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d -#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e -#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f -#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L -#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L -#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L -#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L -#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L -#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L -//SDMA1_UTCL1_WR_STATUS -#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 -#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 -#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 -#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 -#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 -#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 -#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 -#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 -#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 -#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 -#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa -#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb -#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc -#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd -#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe -#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf -#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 -#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 -#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 -#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 -#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 -#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 -#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 -#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 -#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c -#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d -#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e -#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f -#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L -#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L -#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L -#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L -#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L -#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L -#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L -//SDMA1_UTCL1_INV0 -#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 -#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 -#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 -#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 -#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 -#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 -#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 -#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 -#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 -#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 -#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa -#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb -#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc -#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c -#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L -#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L -#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L -#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L -#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L -#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L -#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L -#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L -#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L -#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L -#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L -#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L -#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L -#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L -//SDMA1_UTCL1_INV1 -#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 -#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA1_UTCL1_INV2 -#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 -#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL -//SDMA1_UTCL1_RD_XNACK0 -#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 -#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA1_UTCL1_RD_XNACK1 -#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 -#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 -#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 -#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a -#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL -#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L -#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L -#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L -//SDMA1_UTCL1_WR_XNACK0 -#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 -#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA1_UTCL1_WR_XNACK1 -#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 -#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 -#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 -#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a -#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL -#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L -#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L -#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L -//SDMA1_UTCL1_TIMEOUT -#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 -#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 -#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL -#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L -//SDMA1_UTCL1_PAGE -#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 -#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 -#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 -#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 -#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L -#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL -#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L -#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L -//SDMA1_POWER_CNTL_IDLE -#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 -#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 -#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 -#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL -#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L -#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L -//SDMA1_RELAX_ORDERING_LUT -#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 -#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 -#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 -#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 -#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 -#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 -#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 -#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 -#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 -#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa -#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb -#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc -#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd -#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe -#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b -#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c -#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d -#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e -#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f -#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L -#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L -#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L -#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L -#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L -#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L -#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L -#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L -#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L -#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L -#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L -#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L -#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L -#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L -#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L -#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L -#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L -#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L -#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L -//SDMA1_CHICKEN_BITS_2 -#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 -#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL -//SDMA1_STATUS3_REG -#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 -#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 -#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 -#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL -#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L -#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L -//SDMA1_PHYSICAL_ADDR_LO -#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 -#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 -#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 -#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc -#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L -#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L -#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L -#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L -//SDMA1_PHYSICAL_ADDR_HI -#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL -//SDMA1_PHASE2_QUANTUM -#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L -//SDMA1_ERROR_LOG -#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 -#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 -#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL -#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L -//SDMA1_PUB_DUMMY_REG0 -#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 -#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL -//SDMA1_PUB_DUMMY_REG1 -#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 -#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL -//SDMA1_PUB_DUMMY_REG2 -#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 -#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL -//SDMA1_PUB_DUMMY_REG3 -#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 -#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL -//SDMA1_F32_COUNTER -#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 -#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL -//SDMA1_UNBREAKABLE -#define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0 -#define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L -//SDMA1_PERFMON_CNTL -#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 -#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 -#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 -#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa -#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb -#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc -#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L -#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L -#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL -#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L -#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L -#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L -//SDMA1_PERFCOUNTER0_RESULT -#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 -#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL -//SDMA1_PERFCOUNTER1_RESULT -#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 -#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL -//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L -//SDMA1_CRD_CNTL -#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 -#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd -#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L -#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L -//SDMA1_MMHUB_TRUSTLVL -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L -//SDMA1_GPU_IOV_VIOLATION_LOG -#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 -#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 -#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 -#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 -#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 -#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 -#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 -#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L -#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL -#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L -#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L -#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L -#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L -//SDMA1_ULV_CNTL -#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 -#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d -#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e -#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f -#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL -#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L -#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L -#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L -//SDMA1_EA_DBIT_ADDR_DATA -#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 -#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL -//SDMA1_EA_DBIT_ADDR_INDEX -#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 -#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L -//SDMA1_GFX_RB_CNTL -#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA1_GFX_RB_BASE -#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_BASE_HI -#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA1_GFX_RB_RPTR -#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_RPTR_HI -#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_WPTR -#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_WPTR_HI -#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_WPTR_POLL_CNTL -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA1_GFX_RB_RPTR_ADDR_HI -#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_RPTR_ADDR_LO -#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_GFX_IB_CNTL -#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA1_GFX_IB_RPTR -#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA1_GFX_IB_OFFSET -#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA1_GFX_IB_BASE_LO -#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA1_GFX_IB_BASE_HI -#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_GFX_IB_SIZE -#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA1_GFX_SKIP_CNTL -#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA1_GFX_CONTEXT_STATUS -#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA1_GFX_DOORBELL -#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA1_GFX_CONTEXT_CNTL -#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 -#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L -//SDMA1_GFX_STATUS -#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA1_GFX_DOORBELL_LOG -#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA1_GFX_WATERMARK -#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA1_GFX_DOORBELL_OFFSET -#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA1_GFX_CSA_ADDR_LO -#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_GFX_CSA_ADDR_HI -#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_GFX_IB_SUB_REMAIN -#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA1_GFX_PREEMPT -#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA1_GFX_DUMMY_REG -#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_GFX_RB_AQL_CNTL -#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA1_GFX_MINOR_PTR_UPDATE -#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA1_GFX_MIDCMD_DATA0 -#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA1 -#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA2 -#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA3 -#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA4 -#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA5 -#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA6 -#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA7 -#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA8 -#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_CNTL -#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA1_PAGE_RB_CNTL -#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA1_PAGE_RB_BASE -#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_BASE_HI -#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA1_PAGE_RB_RPTR -#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_RPTR_HI -#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_WPTR -#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_WPTR_HI -#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_WPTR_POLL_CNTL -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA1_PAGE_RB_RPTR_ADDR_HI -#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_RPTR_ADDR_LO -#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_PAGE_IB_CNTL -#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA1_PAGE_IB_RPTR -#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA1_PAGE_IB_OFFSET -#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA1_PAGE_IB_BASE_LO -#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA1_PAGE_IB_BASE_HI -#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_PAGE_IB_SIZE -#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA1_PAGE_SKIP_CNTL -#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA1_PAGE_CONTEXT_STATUS -#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA1_PAGE_DOORBELL -#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA1_PAGE_STATUS -#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA1_PAGE_DOORBELL_LOG -#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA1_PAGE_WATERMARK -#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA1_PAGE_DOORBELL_OFFSET -#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA1_PAGE_CSA_ADDR_LO -#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_PAGE_CSA_ADDR_HI -#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_PAGE_IB_SUB_REMAIN -#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA1_PAGE_PREEMPT -#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA1_PAGE_DUMMY_REG -#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI -#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO -#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_PAGE_RB_AQL_CNTL -#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA1_PAGE_MINOR_PTR_UPDATE -#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA1_PAGE_MIDCMD_DATA0 -#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA1 -#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA2 -#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA3 -#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA4 -#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA5 -#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA6 -#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA7 -#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA8 -#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_CNTL -#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA1_RLC0_RB_CNTL -#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA1_RLC0_RB_BASE -#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_BASE_HI -#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA1_RLC0_RB_RPTR -#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_RPTR_HI -#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_WPTR -#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_WPTR_HI -#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_WPTR_POLL_CNTL -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA1_RLC0_RB_RPTR_ADDR_HI -#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_RPTR_ADDR_LO -#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_RLC0_IB_CNTL -#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA1_RLC0_IB_RPTR -#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA1_RLC0_IB_OFFSET -#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA1_RLC0_IB_BASE_LO -#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA1_RLC0_IB_BASE_HI -#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC0_IB_SIZE -#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA1_RLC0_SKIP_CNTL -#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA1_RLC0_CONTEXT_STATUS -#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA1_RLC0_DOORBELL -#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA1_RLC0_STATUS -#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA1_RLC0_DOORBELL_LOG -#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA1_RLC0_WATERMARK -#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA1_RLC0_DOORBELL_OFFSET -#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA1_RLC0_CSA_ADDR_LO -#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_RLC0_CSA_ADDR_HI -#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC0_IB_SUB_REMAIN -#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA1_RLC0_PREEMPT -#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA1_RLC0_DUMMY_REG -#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_RLC0_RB_AQL_CNTL -#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA1_RLC0_MINOR_PTR_UPDATE -#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA1_RLC0_MIDCMD_DATA0 -#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA1 -#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA2 -#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA3 -#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA4 -#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA5 -#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA6 -#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA7 -#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA8 -#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_CNTL -#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA1_RLC1_RB_CNTL -#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA1_RLC1_RB_BASE -#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_BASE_HI -#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA1_RLC1_RB_RPTR -#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_RPTR_HI -#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_WPTR -#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_WPTR_HI -#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_WPTR_POLL_CNTL -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA1_RLC1_RB_RPTR_ADDR_HI -#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_RPTR_ADDR_LO -#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_RLC1_IB_CNTL -#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA1_RLC1_IB_RPTR -#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA1_RLC1_IB_OFFSET -#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA1_RLC1_IB_BASE_LO -#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA1_RLC1_IB_BASE_HI -#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC1_IB_SIZE -#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA1_RLC1_SKIP_CNTL -#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA1_RLC1_CONTEXT_STATUS -#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA1_RLC1_DOORBELL -#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA1_RLC1_STATUS -#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA1_RLC1_DOORBELL_LOG -#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA1_RLC1_WATERMARK -#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA1_RLC1_DOORBELL_OFFSET -#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA1_RLC1_CSA_ADDR_LO -#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_RLC1_CSA_ADDR_HI -#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC1_IB_SUB_REMAIN -#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA1_RLC1_PREEMPT -#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA1_RLC1_DUMMY_REG -#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_RLC1_RB_AQL_CNTL -#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA1_RLC1_MINOR_PTR_UPDATE -#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA1_RLC1_MIDCMD_DATA0 -#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA1 -#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA2 -#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA3 -#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA4 -#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA5 -#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA6 -#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA7 -#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA8 -#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_CNTL -#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -#endif -- GitLab From 75199b8c7f94d62c77e0441ed9a7e68e269f656b Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Wed, 15 Nov 2017 18:09:33 +0800 Subject: [PATCH 0925/2547] drm/amd/include:cleanup vega10 hdp header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/vega10/HDP folder, remove hdp_4_0_default.h Signed-off-by: Feifei Xu Reviewed-by: Alex Deucher Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +- .../amd/include/asic_reg/hdp/hdp_4_0_offset.h | 209 ++++++ .../include/asic_reg/hdp/hdp_4_0_sh_mask.h | 601 ++++++++++++++++++ .../asic_reg/vega10/HDP/hdp_4_0_default.h | 117 ---- .../asic_reg/vega10/HDP/hdp_4_0_offset.h | 209 ------ .../asic_reg/vega10/HDP/hdp_4_0_sh_mask.h | 601 ------------------ 11 files changed, 818 insertions(+), 935 deletions(-) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 560d8e76d14c..4fc6a2cf1d83 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -32,7 +32,7 @@ #include "vega10/GC/gc_9_0_offset.h" #include "vega10/GC/gc_9_0_sh_mask.h" #include "vega10/vega10_enum.h" -#include "vega10/HDP/hdp_4_0_offset.h" +#include "hdp/hdp_4_0_offset.h" #include "soc15_common.h" #include "clearstate_gfx9.h" diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index c30e08d9f30b..f5642b27ace0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -26,8 +26,8 @@ #include "amdgpu_atomfirmware.h" #include "vega10/soc15ip.h" -#include "vega10/HDP/hdp_4_0_offset.h" -#include "vega10/HDP/hdp_4_0_sh_mask.h" +#include "hdp/hdp_4_0_offset.h" +#include "hdp/hdp_4_0_sh_mask.h" #include "vega10/GC/gc_9_0_sh_mask.h" #include "vega10/DC/dce_12_0_offset.h" #include "vega10/DC/dce_12_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 4051a14424b9..6d14ea62d5c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -34,7 +34,7 @@ #include "sdma1/sdma1_4_0_sh_mask.h" #include "vega10/MMHUB/mmhub_1_0_offset.h" #include "vega10/MMHUB/mmhub_1_0_sh_mask.h" -#include "vega10/HDP/hdp_4_0_offset.h" +#include "hdp/hdp_4_0_offset.h" #include "raven1/SDMA0/sdma0_4_1_default.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 82c75536a888..11ece450e561 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -40,8 +40,8 @@ #include "vega10/GC/gc_9_0_sh_mask.h" #include "sdma0/sdma0_4_0_offset.h" #include "sdma1/sdma1_4_0_offset.h" -#include "vega10/HDP/hdp_4_0_offset.h" -#include "vega10/HDP/hdp_4_0_sh_mask.h" +#include "hdp/hdp_4_0_offset.h" +#include "hdp/hdp_4_0_sh_mask.h" #include "vega10/MP/mp_9_0_offset.h" #include "vega10/MP/mp_9_0_sh_mask.h" #include "vega10/SMUIO/smuio_9_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 6d4470626d25..2f68f98f61d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -36,7 +36,7 @@ #include "vega10/VCE/vce_4_0_default.h" #include "vega10/VCE/vce_4_0_sh_mask.h" #include "vega10/NBIF/nbif_6_1_offset.h" -#include "vega10/HDP/hdp_4_0_offset.h" +#include "hdp/hdp_4_0_offset.h" #include "vega10/MMHUB/mmhub_1_0_offset.h" #include "vega10/MMHUB/mmhub_1_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 0450ac5ba6b6..061088cca72e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -31,7 +31,7 @@ #include "vega10/soc15ip.h" #include "raven1/VCN/vcn_1_0_offset.h" #include "raven1/VCN/vcn_1_0_sh_mask.h" -#include "vega10/HDP/hdp_4_0_offset.h" +#include "hdp/hdp_4_0_offset.h" #include "raven1/MMHUB/mmhub_9_1_offset.h" #include "raven1/MMHUB/mmhub_9_1_sh_mask.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h new file mode 100644 index 000000000000..94325fc3abd5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _hdp_4_0_OFFSET_HEADER +#define _hdp_4_0_OFFSET_HEADER + + + +// addressBlock: hdp_hdpdec +// base address: 0x3c80 +#define mmHDP_MMHUB_TLVL 0x0000 +#define mmHDP_MMHUB_TLVL_BASE_IDX 0 +#define mmHDP_MMHUB_UNITID 0x0001 +#define mmHDP_MMHUB_UNITID_BASE_IDX 0 +#define mmHDP_NONSURFACE_BASE 0x0040 +#define mmHDP_NONSURFACE_BASE_BASE_IDX 0 +#define mmHDP_NONSURFACE_INFO 0x0041 +#define mmHDP_NONSURFACE_INFO_BASE_IDX 0 +#define mmHDP_NONSURFACE_BASE_HI 0x0042 +#define mmHDP_NONSURFACE_BASE_HI_BASE_IDX 0 +#define mmHDP_NONSURF_FLAGS 0x00c8 +#define mmHDP_NONSURF_FLAGS_BASE_IDX 0 +#define mmHDP_NONSURF_FLAGS_CLR 0x00c9 +#define mmHDP_NONSURF_FLAGS_CLR_BASE_IDX 0 +#define mmHDP_HOST_PATH_CNTL 0x00cc +#define mmHDP_HOST_PATH_CNTL_BASE_IDX 0 +#define mmHDP_SW_SEMAPHORE 0x00cd +#define mmHDP_SW_SEMAPHORE_BASE_IDX 0 +#define mmHDP_DEBUG0 0x00ce +#define mmHDP_DEBUG0_BASE_IDX 0 +#define mmHDP_LAST_SURFACE_HIT 0x00d0 +#define mmHDP_LAST_SURFACE_HIT_BASE_IDX 0 +#define mmHDP_READ_CACHE_INVALIDATE 0x00d1 +#define mmHDP_READ_CACHE_INVALIDATE_BASE_IDX 0 +#define mmHDP_OUTSTANDING_REQ 0x00d2 +#define mmHDP_OUTSTANDING_REQ_BASE_IDX 0 +#define mmHDP_MISC_CNTL 0x00d3 +#define mmHDP_MISC_CNTL_BASE_IDX 0 +#define mmHDP_MEM_POWER_LS 0x00d4 +#define mmHDP_MEM_POWER_LS_BASE_IDX 0 +#define mmHDP_MMHUB_CNTL 0x00d5 +#define mmHDP_MMHUB_CNTL_BASE_IDX 0 +#define mmHDP_EDC_CNT 0x00d6 +#define mmHDP_EDC_CNT_BASE_IDX 0 +#define mmHDP_VERSION 0x00d7 +#define mmHDP_VERSION_BASE_IDX 0 +#define mmHDP_CLK_CNTL 0x00d8 +#define mmHDP_CLK_CNTL_BASE_IDX 0 +#define mmHDP_MEMIO_CNTL 0x00f6 +#define mmHDP_MEMIO_CNTL_BASE_IDX 0 +#define mmHDP_MEMIO_ADDR 0x00f7 +#define mmHDP_MEMIO_ADDR_BASE_IDX 0 +#define mmHDP_MEMIO_STATUS 0x00f8 +#define mmHDP_MEMIO_STATUS_BASE_IDX 0 +#define mmHDP_MEMIO_WR_DATA 0x00f9 +#define mmHDP_MEMIO_WR_DATA_BASE_IDX 0 +#define mmHDP_MEMIO_RD_DATA 0x00fa +#define mmHDP_MEMIO_RD_DATA_BASE_IDX 0 +#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0100 +#define mmHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0 +#define mmHDP_XDP_D2H_FLUSH 0x0101 +#define mmHDP_XDP_D2H_FLUSH_BASE_IDX 0 +#define mmHDP_XDP_D2H_BAR_UPDATE 0x0102 +#define mmHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_3 0x0103 +#define mmHDP_XDP_D2H_RSVD_3_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_4 0x0104 +#define mmHDP_XDP_D2H_RSVD_4_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_5 0x0105 +#define mmHDP_XDP_D2H_RSVD_5_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_6 0x0106 +#define mmHDP_XDP_D2H_RSVD_6_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_7 0x0107 +#define mmHDP_XDP_D2H_RSVD_7_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_8 0x0108 +#define mmHDP_XDP_D2H_RSVD_8_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_9 0x0109 +#define mmHDP_XDP_D2H_RSVD_9_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_10 0x010a +#define mmHDP_XDP_D2H_RSVD_10_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_11 0x010b +#define mmHDP_XDP_D2H_RSVD_11_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_12 0x010c +#define mmHDP_XDP_D2H_RSVD_12_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_13 0x010d +#define mmHDP_XDP_D2H_RSVD_13_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_14 0x010e +#define mmHDP_XDP_D2H_RSVD_14_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_15 0x010f +#define mmHDP_XDP_D2H_RSVD_15_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_16 0x0110 +#define mmHDP_XDP_D2H_RSVD_16_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_17 0x0111 +#define mmHDP_XDP_D2H_RSVD_17_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_18 0x0112 +#define mmHDP_XDP_D2H_RSVD_18_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_19 0x0113 +#define mmHDP_XDP_D2H_RSVD_19_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_20 0x0114 +#define mmHDP_XDP_D2H_RSVD_20_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_21 0x0115 +#define mmHDP_XDP_D2H_RSVD_21_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_22 0x0116 +#define mmHDP_XDP_D2H_RSVD_22_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_23 0x0117 +#define mmHDP_XDP_D2H_RSVD_23_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_24 0x0118 +#define mmHDP_XDP_D2H_RSVD_24_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_25 0x0119 +#define mmHDP_XDP_D2H_RSVD_25_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_26 0x011a +#define mmHDP_XDP_D2H_RSVD_26_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_27 0x011b +#define mmHDP_XDP_D2H_RSVD_27_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_28 0x011c +#define mmHDP_XDP_D2H_RSVD_28_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_29 0x011d +#define mmHDP_XDP_D2H_RSVD_29_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_30 0x011e +#define mmHDP_XDP_D2H_RSVD_30_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_31 0x011f +#define mmHDP_XDP_D2H_RSVD_31_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_32 0x0120 +#define mmHDP_XDP_D2H_RSVD_32_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_33 0x0121 +#define mmHDP_XDP_D2H_RSVD_33_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_34 0x0122 +#define mmHDP_XDP_D2H_RSVD_34_BASE_IDX 0 +#define mmHDP_XDP_DIRECT2HDP_LAST 0x0123 +#define mmHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR_CFG 0x0124 +#define mmHDP_XDP_P2P_BAR_CFG_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_OFFSET 0x0125 +#define mmHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR0 0x0126 +#define mmHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR1 0x0127 +#define mmHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR2 0x0128 +#define mmHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR3 0x0129 +#define mmHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR4 0x012a +#define mmHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR5 0x012b +#define mmHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR6 0x012c +#define mmHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0 +#define mmHDP_XDP_HDP_MBX_MC_CFG 0x012d +#define mmHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0 +#define mmHDP_XDP_HDP_MC_CFG 0x012e +#define mmHDP_XDP_HDP_MC_CFG_BASE_IDX 0 +#define mmHDP_XDP_HST_CFG 0x012f +#define mmHDP_XDP_HST_CFG_BASE_IDX 0 +#define mmHDP_XDP_HDP_IPH_CFG 0x0131 +#define mmHDP_XDP_HDP_IPH_CFG_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR0 0x0134 +#define mmHDP_XDP_P2P_BAR0_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR1 0x0135 +#define mmHDP_XDP_P2P_BAR1_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR2 0x0136 +#define mmHDP_XDP_P2P_BAR2_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR3 0x0137 +#define mmHDP_XDP_P2P_BAR3_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR4 0x0138 +#define mmHDP_XDP_P2P_BAR4_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR5 0x0139 +#define mmHDP_XDP_P2P_BAR5_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR6 0x013a +#define mmHDP_XDP_P2P_BAR6_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR7 0x013b +#define mmHDP_XDP_P2P_BAR7_BASE_IDX 0 +#define mmHDP_XDP_FLUSH_ARMED_STS 0x013c +#define mmHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0 +#define mmHDP_XDP_FLUSH_CNTR0_STS 0x013d +#define mmHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0 +#define mmHDP_XDP_BUSY_STS 0x013e +#define mmHDP_XDP_BUSY_STS_BASE_IDX 0 +#define mmHDP_XDP_STICKY 0x013f +#define mmHDP_XDP_STICKY_BASE_IDX 0 +#define mmHDP_XDP_CHKN 0x0140 +#define mmHDP_XDP_CHKN_BASE_IDX 0 +#define mmHDP_XDP_BARS_ADDR_39_36 0x0144 +#define mmHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0 +#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145 +#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0 +#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG 0x0148 +#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define mmHDP_XDP_MMHUB_ERROR 0x0149 +#define mmHDP_XDP_MMHUB_ERROR_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h new file mode 100644 index 000000000000..25e28691d62d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h @@ -0,0 +1,601 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _hdp_4_0_SH_MASK_HEADER +#define _hdp_4_0_SH_MASK_HEADER + + +// addressBlock: hdp_hdpdec +//HDP_MMHUB_TLVL +#define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0 +#define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4 +#define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8 +#define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc +#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10 +#define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L +#define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L +#define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L +#define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L +#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L +//HDP_MMHUB_UNITID +#define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0 +#define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8 +#define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10 +#define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL +#define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L +#define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L +//HDP_NONSURFACE_BASE +#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0 +#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL +//HDP_NONSURFACE_INFO +#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4 +#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8 +#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L +#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L +//HDP_NONSURFACE_BASE_HI +#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0 +#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL +//HDP_NONSURF_FLAGS +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L +//HDP_NONSURF_FLAGS_CLR +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L +//HDP_HOST_PATH_CNTL +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L +//HDP_SW_SEMAPHORE +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL +//HDP_DEBUG0 +#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 +#define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL +//HDP_LAST_SURFACE_HIT +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L +//HDP_READ_CACHE_INVALIDATE +#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT 0x0 +#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK 0x00000001L +//HDP_OUTSTANDING_REQ +#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 +#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 +#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL +#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L +//HDP_MISC_CNTL +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 +#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2 +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 +#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb +#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 +#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17 +#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 +#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT 0x19 +#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1a +#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1b +#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT 0x1c +#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d +#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L +#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L +#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L +#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L +#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L +#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L +#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK 0x02000000L +#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x04000000L +#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x08000000L +#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK 0x10000000L +#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK 0x20000000L +#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L +//HDP_MEM_POWER_LS +#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 +#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 +#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L +#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001F80L +//HDP_MMHUB_CNTL +#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0 +#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1 +#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2 +#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L +#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L +#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L +//HDP_EDC_CNT +#define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT 0x0 +#define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT 0x2 +#define HDP_EDC_CNT__MEM0_SED_COUNT_MASK 0x00000003L +#define HDP_EDC_CNT__MEM1_SED_COUNT_MASK 0x0000000CL +//HDP_VERSION +#define HDP_VERSION__MINVER__SHIFT 0x0 +#define HDP_VERSION__MAJVER__SHIFT 0x8 +#define HDP_VERSION__REV__SHIFT 0x10 +#define HDP_VERSION__MINVER_MASK 0x000000FFL +#define HDP_VERSION__MAJVER_MASK 0x0000FF00L +#define HDP_VERSION__REV_MASK 0x00FF0000L +//HDP_CLK_CNTL +#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0 +#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT 0x4 +#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c +#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d +#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e +#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f +#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL +#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK 0x00000010L +#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L +#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L +#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L +#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L +//HDP_MEMIO_CNTL +#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 +#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 +#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf +#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 +#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 +#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L +#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L +#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L +#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L +#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L +//HDP_MEMIO_ADDR +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL +//HDP_MEMIO_STATUS +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L +//HDP_MEMIO_WR_DATA +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL +//HDP_MEMIO_RD_DATA +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL +//HDP_XDP_DIRECT2HDP_FIRST +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_FLUSH +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L +//HDP_XDP_D2H_BAR_UPDATE +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L +//HDP_XDP_D2H_RSVD_3 +#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_4 +#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_5 +#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_6 +#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_7 +#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_8 +#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_9 +#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_10 +#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_11 +#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_12 +#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_13 +#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_14 +#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_15 +#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_16 +#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_17 +#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_18 +#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_19 +#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_20 +#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_21 +#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_22 +#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_23 +#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_24 +#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_25 +#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_26 +#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_27 +#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_28 +#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_29 +#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_30 +#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_31 +#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_32 +#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_33 +#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_34 +#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_DIRECT2HDP_LAST +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_P2P_BAR_CFG +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L +//HDP_XDP_P2P_MBX_OFFSET +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL +//HDP_XDP_P2P_MBX_ADDR0 +#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR1 +#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR2 +#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR3 +#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR4 +#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR5 +#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR6 +#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_HDP_MBX_MC_CFG +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L +//HDP_XDP_HDP_MC_CFG +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L +//HDP_XDP_HST_CFG +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 +#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L +#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L +//HDP_XDP_HDP_IPH_CFG +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003FL +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000FC0L +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L +//HDP_XDP_P2P_BAR0 +#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR1 +#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR2 +#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR3 +#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR4 +#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR5 +#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR6 +#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR7 +#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L +//HDP_XDP_FLUSH_ARMED_STS +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL +//HDP_XDP_FLUSH_CNTR0_STS +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL +//HDP_XDP_BUSY_STS +#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 +#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003FFFFL +//HDP_XDP_STICKY +#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 +#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 +#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL +#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L +//HDP_XDP_CHKN +#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 +#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 +#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 +#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 +#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL +#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L +#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L +#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L +//HDP_XDP_BARS_ADDR_39_36 +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L +//HDP_XDP_MC_VM_FB_LOCATION_BASE +#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL +//HDP_XDP_GPU_IOV_VIOLATION_LOG +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L +//HDP_XDP_MMHUB_ERROR +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1 +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2 +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3 +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5 +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6 +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7 +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9 +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11 +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12 +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13 +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15 +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16 +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17 +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h deleted file mode 100644 index 864690cc910a..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _hdp_4_0_DEFAULT_HEADER -#define _hdp_4_0_DEFAULT_HEADER - - -// addressBlock: hdp_hdpdec -#define mmHDP_MMHUB_TLVL_DEFAULT 0x00006666 -#define mmHDP_MMHUB_UNITID_DEFAULT 0x00000000 -#define mmHDP_NONSURFACE_BASE_DEFAULT 0x00000000 -#define mmHDP_NONSURFACE_INFO_DEFAULT 0x00000000 -#define mmHDP_NONSURFACE_BASE_HI_DEFAULT 0x00000000 -#define mmHDP_NONSURF_FLAGS_DEFAULT 0x00000000 -#define mmHDP_NONSURF_FLAGS_CLR_DEFAULT 0x00000000 -#define mmHDP_HOST_PATH_CNTL_DEFAULT 0x00680000 -#define mmHDP_SW_SEMAPHORE_DEFAULT 0x00000000 -#define mmHDP_DEBUG0_DEFAULT 0x00000000 -#define mmHDP_LAST_SURFACE_HIT_DEFAULT 0x00000003 -#define mmHDP_READ_CACHE_INVALIDATE_DEFAULT 0x00000000 -#define mmHDP_OUTSTANDING_REQ_DEFAULT 0x00000000 -#define mmHDP_MISC_CNTL_DEFAULT 0x2d200861 -#define mmHDP_MEM_POWER_LS_DEFAULT 0x00000901 -#define mmHDP_MMHUB_CNTL_DEFAULT 0x00000000 -#define mmHDP_EDC_CNT_DEFAULT 0x00000000 -#define mmHDP_VERSION_DEFAULT 0x00000400 -#define mmHDP_CLK_CNTL_DEFAULT 0x0000000f -#define mmHDP_MEMIO_CNTL_DEFAULT 0x00000000 -#define mmHDP_MEMIO_ADDR_DEFAULT 0x00000000 -#define mmHDP_MEMIO_STATUS_DEFAULT 0x00000000 -#define mmHDP_MEMIO_WR_DATA_DEFAULT 0x00000000 -#define mmHDP_MEMIO_RD_DATA_DEFAULT 0xdeadbeef -#define mmHDP_XDP_DIRECT2HDP_FIRST_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_FLUSH_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_BAR_UPDATE_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_3_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_4_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_5_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_6_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_7_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_8_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_9_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_10_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_11_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_12_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_13_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_14_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_15_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_16_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_17_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_18_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_19_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_20_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_21_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_22_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_23_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_24_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_25_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_26_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_27_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_28_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_29_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_30_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_31_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_32_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_33_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_34_DEFAULT 0x00000000 -#define mmHDP_XDP_DIRECT2HDP_LAST_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR_CFG_DEFAULT 0x0000000f -#define mmHDP_XDP_P2P_MBX_OFFSET_DEFAULT 0x000011bc -#define mmHDP_XDP_P2P_MBX_ADDR0_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_MBX_ADDR1_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_MBX_ADDR2_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_MBX_ADDR3_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_MBX_ADDR4_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_MBX_ADDR5_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_MBX_ADDR6_DEFAULT 0x00000000 -#define mmHDP_XDP_HDP_MBX_MC_CFG_DEFAULT 0x00000000 -#define mmHDP_XDP_HDP_MC_CFG_DEFAULT 0x00020000 -#define mmHDP_XDP_HST_CFG_DEFAULT 0x0000001b -#define mmHDP_XDP_HDP_IPH_CFG_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR0_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR1_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR2_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR3_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR4_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR5_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR6_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR7_DEFAULT 0x00000000 -#define mmHDP_XDP_FLUSH_ARMED_STS_DEFAULT 0x00000000 -#define mmHDP_XDP_FLUSH_CNTR0_STS_DEFAULT 0x00000000 -#define mmHDP_XDP_BUSY_STS_DEFAULT 0x00000000 -#define mmHDP_XDP_STICKY_DEFAULT 0x00000000 -#define mmHDP_XDP_CHKN_DEFAULT 0x48584450 -#define mmHDP_XDP_BARS_ADDR_39_36_DEFAULT 0x00000000 -#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 -#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 -#define mmHDP_XDP_MMHUB_ERROR_DEFAULT 0x00000000 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h deleted file mode 100644 index fbad771a569e..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _hdp_4_0_OFFSET_HEADER -#define _hdp_4_0_OFFSET_HEADER - - - -// addressBlock: hdp_hdpdec -// base address: 0x3c80 -#define mmHDP_MMHUB_TLVL 0x0000 -#define mmHDP_MMHUB_TLVL_BASE_IDX 0 -#define mmHDP_MMHUB_UNITID 0x0001 -#define mmHDP_MMHUB_UNITID_BASE_IDX 0 -#define mmHDP_NONSURFACE_BASE 0x0040 -#define mmHDP_NONSURFACE_BASE_BASE_IDX 0 -#define mmHDP_NONSURFACE_INFO 0x0041 -#define mmHDP_NONSURFACE_INFO_BASE_IDX 0 -#define mmHDP_NONSURFACE_BASE_HI 0x0042 -#define mmHDP_NONSURFACE_BASE_HI_BASE_IDX 0 -#define mmHDP_NONSURF_FLAGS 0x00c8 -#define mmHDP_NONSURF_FLAGS_BASE_IDX 0 -#define mmHDP_NONSURF_FLAGS_CLR 0x00c9 -#define mmHDP_NONSURF_FLAGS_CLR_BASE_IDX 0 -#define mmHDP_HOST_PATH_CNTL 0x00cc -#define mmHDP_HOST_PATH_CNTL_BASE_IDX 0 -#define mmHDP_SW_SEMAPHORE 0x00cd -#define mmHDP_SW_SEMAPHORE_BASE_IDX 0 -#define mmHDP_DEBUG0 0x00ce -#define mmHDP_DEBUG0_BASE_IDX 0 -#define mmHDP_LAST_SURFACE_HIT 0x00d0 -#define mmHDP_LAST_SURFACE_HIT_BASE_IDX 0 -#define mmHDP_READ_CACHE_INVALIDATE 0x00d1 -#define mmHDP_READ_CACHE_INVALIDATE_BASE_IDX 0 -#define mmHDP_OUTSTANDING_REQ 0x00d2 -#define mmHDP_OUTSTANDING_REQ_BASE_IDX 0 -#define mmHDP_MISC_CNTL 0x00d3 -#define mmHDP_MISC_CNTL_BASE_IDX 0 -#define mmHDP_MEM_POWER_LS 0x00d4 -#define mmHDP_MEM_POWER_LS_BASE_IDX 0 -#define mmHDP_MMHUB_CNTL 0x00d5 -#define mmHDP_MMHUB_CNTL_BASE_IDX 0 -#define mmHDP_EDC_CNT 0x00d6 -#define mmHDP_EDC_CNT_BASE_IDX 0 -#define mmHDP_VERSION 0x00d7 -#define mmHDP_VERSION_BASE_IDX 0 -#define mmHDP_CLK_CNTL 0x00d8 -#define mmHDP_CLK_CNTL_BASE_IDX 0 -#define mmHDP_MEMIO_CNTL 0x00f6 -#define mmHDP_MEMIO_CNTL_BASE_IDX 0 -#define mmHDP_MEMIO_ADDR 0x00f7 -#define mmHDP_MEMIO_ADDR_BASE_IDX 0 -#define mmHDP_MEMIO_STATUS 0x00f8 -#define mmHDP_MEMIO_STATUS_BASE_IDX 0 -#define mmHDP_MEMIO_WR_DATA 0x00f9 -#define mmHDP_MEMIO_WR_DATA_BASE_IDX 0 -#define mmHDP_MEMIO_RD_DATA 0x00fa -#define mmHDP_MEMIO_RD_DATA_BASE_IDX 0 -#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0100 -#define mmHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0 -#define mmHDP_XDP_D2H_FLUSH 0x0101 -#define mmHDP_XDP_D2H_FLUSH_BASE_IDX 0 -#define mmHDP_XDP_D2H_BAR_UPDATE 0x0102 -#define mmHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_3 0x0103 -#define mmHDP_XDP_D2H_RSVD_3_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_4 0x0104 -#define mmHDP_XDP_D2H_RSVD_4_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_5 0x0105 -#define mmHDP_XDP_D2H_RSVD_5_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_6 0x0106 -#define mmHDP_XDP_D2H_RSVD_6_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_7 0x0107 -#define mmHDP_XDP_D2H_RSVD_7_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_8 0x0108 -#define mmHDP_XDP_D2H_RSVD_8_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_9 0x0109 -#define mmHDP_XDP_D2H_RSVD_9_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_10 0x010a -#define mmHDP_XDP_D2H_RSVD_10_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_11 0x010b -#define mmHDP_XDP_D2H_RSVD_11_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_12 0x010c -#define mmHDP_XDP_D2H_RSVD_12_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_13 0x010d -#define mmHDP_XDP_D2H_RSVD_13_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_14 0x010e -#define mmHDP_XDP_D2H_RSVD_14_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_15 0x010f -#define mmHDP_XDP_D2H_RSVD_15_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_16 0x0110 -#define mmHDP_XDP_D2H_RSVD_16_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_17 0x0111 -#define mmHDP_XDP_D2H_RSVD_17_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_18 0x0112 -#define mmHDP_XDP_D2H_RSVD_18_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_19 0x0113 -#define mmHDP_XDP_D2H_RSVD_19_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_20 0x0114 -#define mmHDP_XDP_D2H_RSVD_20_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_21 0x0115 -#define mmHDP_XDP_D2H_RSVD_21_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_22 0x0116 -#define mmHDP_XDP_D2H_RSVD_22_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_23 0x0117 -#define mmHDP_XDP_D2H_RSVD_23_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_24 0x0118 -#define mmHDP_XDP_D2H_RSVD_24_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_25 0x0119 -#define mmHDP_XDP_D2H_RSVD_25_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_26 0x011a -#define mmHDP_XDP_D2H_RSVD_26_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_27 0x011b -#define mmHDP_XDP_D2H_RSVD_27_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_28 0x011c -#define mmHDP_XDP_D2H_RSVD_28_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_29 0x011d -#define mmHDP_XDP_D2H_RSVD_29_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_30 0x011e -#define mmHDP_XDP_D2H_RSVD_30_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_31 0x011f -#define mmHDP_XDP_D2H_RSVD_31_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_32 0x0120 -#define mmHDP_XDP_D2H_RSVD_32_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_33 0x0121 -#define mmHDP_XDP_D2H_RSVD_33_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_34 0x0122 -#define mmHDP_XDP_D2H_RSVD_34_BASE_IDX 0 -#define mmHDP_XDP_DIRECT2HDP_LAST 0x0123 -#define mmHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR_CFG 0x0124 -#define mmHDP_XDP_P2P_BAR_CFG_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_OFFSET 0x0125 -#define mmHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR0 0x0126 -#define mmHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR1 0x0127 -#define mmHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR2 0x0128 -#define mmHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR3 0x0129 -#define mmHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR4 0x012a -#define mmHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR5 0x012b -#define mmHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR6 0x012c -#define mmHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0 -#define mmHDP_XDP_HDP_MBX_MC_CFG 0x012d -#define mmHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0 -#define mmHDP_XDP_HDP_MC_CFG 0x012e -#define mmHDP_XDP_HDP_MC_CFG_BASE_IDX 0 -#define mmHDP_XDP_HST_CFG 0x012f -#define mmHDP_XDP_HST_CFG_BASE_IDX 0 -#define mmHDP_XDP_HDP_IPH_CFG 0x0131 -#define mmHDP_XDP_HDP_IPH_CFG_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR0 0x0134 -#define mmHDP_XDP_P2P_BAR0_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR1 0x0135 -#define mmHDP_XDP_P2P_BAR1_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR2 0x0136 -#define mmHDP_XDP_P2P_BAR2_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR3 0x0137 -#define mmHDP_XDP_P2P_BAR3_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR4 0x0138 -#define mmHDP_XDP_P2P_BAR4_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR5 0x0139 -#define mmHDP_XDP_P2P_BAR5_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR6 0x013a -#define mmHDP_XDP_P2P_BAR6_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR7 0x013b -#define mmHDP_XDP_P2P_BAR7_BASE_IDX 0 -#define mmHDP_XDP_FLUSH_ARMED_STS 0x013c -#define mmHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0 -#define mmHDP_XDP_FLUSH_CNTR0_STS 0x013d -#define mmHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0 -#define mmHDP_XDP_BUSY_STS 0x013e -#define mmHDP_XDP_BUSY_STS_BASE_IDX 0 -#define mmHDP_XDP_STICKY 0x013f -#define mmHDP_XDP_STICKY_BASE_IDX 0 -#define mmHDP_XDP_CHKN 0x0140 -#define mmHDP_XDP_CHKN_BASE_IDX 0 -#define mmHDP_XDP_BARS_ADDR_39_36 0x0144 -#define mmHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0 -#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145 -#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0 -#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG 0x0148 -#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 -#define mmHDP_XDP_MMHUB_ERROR 0x0149 -#define mmHDP_XDP_MMHUB_ERROR_BASE_IDX 0 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h deleted file mode 100644 index 586187576d70..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h +++ /dev/null @@ -1,601 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _hdp_4_0_SH_MASK_HEADER -#define _hdp_4_0_SH_MASK_HEADER - - -// addressBlock: hdp_hdpdec -//HDP_MMHUB_TLVL -#define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0 -#define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4 -#define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8 -#define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc -#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10 -#define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L -#define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L -#define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L -#define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L -#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L -//HDP_MMHUB_UNITID -#define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0 -#define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8 -#define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10 -#define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL -#define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L -#define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L -//HDP_NONSURFACE_BASE -#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0 -#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL -//HDP_NONSURFACE_INFO -#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4 -#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8 -#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L -#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L -//HDP_NONSURFACE_BASE_HI -#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0 -#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL -//HDP_NONSURF_FLAGS -#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 -#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 -#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L -#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L -//HDP_NONSURF_FLAGS_CLR -#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 -#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 -#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L -#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L -//HDP_HOST_PATH_CNTL -#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 -#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12 -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16 -#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d -#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e -#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f -#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L -#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L -#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L -#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L -#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L -//HDP_SW_SEMAPHORE -#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 -#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL -//HDP_DEBUG0 -#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 -#define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL -//HDP_LAST_SURFACE_HIT -#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 -#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L -//HDP_READ_CACHE_INVALIDATE -#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT 0x0 -#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK 0x00000001L -//HDP_OUTSTANDING_REQ -#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 -#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 -#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL -#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L -//HDP_MISC_CNTL -#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 -#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2 -#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 -#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 -#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb -#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 -#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17 -#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 -#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT 0x19 -#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1a -#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1b -#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT 0x1c -#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d -#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e -#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L -#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL -#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L -#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L -#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L -#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L -#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L -#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L -#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK 0x02000000L -#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x04000000L -#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x08000000L -#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK 0x10000000L -#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK 0x20000000L -#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L -//HDP_MEM_POWER_LS -#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 -#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 -#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L -#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001F80L -//HDP_MMHUB_CNTL -#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0 -#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1 -#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2 -#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L -#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L -#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L -//HDP_EDC_CNT -#define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT 0x0 -#define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT 0x2 -#define HDP_EDC_CNT__MEM0_SED_COUNT_MASK 0x00000003L -#define HDP_EDC_CNT__MEM1_SED_COUNT_MASK 0x0000000CL -//HDP_VERSION -#define HDP_VERSION__MINVER__SHIFT 0x0 -#define HDP_VERSION__MAJVER__SHIFT 0x8 -#define HDP_VERSION__REV__SHIFT 0x10 -#define HDP_VERSION__MINVER_MASK 0x000000FFL -#define HDP_VERSION__MAJVER_MASK 0x0000FF00L -#define HDP_VERSION__REV_MASK 0x00FF0000L -//HDP_CLK_CNTL -#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0 -#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT 0x4 -#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c -#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d -#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e -#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f -#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL -#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK 0x00000010L -#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L -#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L -#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L -#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L -//HDP_MEMIO_CNTL -#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 -#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 -#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 -#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 -#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 -#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 -#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe -#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf -#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 -#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 -#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L -#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L -#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL -#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L -#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L -#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L -#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L -#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L -#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L -#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L -//HDP_MEMIO_ADDR -#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 -#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL -//HDP_MEMIO_STATUS -#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 -#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 -#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 -#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 -#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L -#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L -#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L -#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L -//HDP_MEMIO_WR_DATA -#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 -#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL -//HDP_MEMIO_RD_DATA -#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 -#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL -//HDP_XDP_DIRECT2HDP_FIRST -#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 -#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_FLUSH -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L -//HDP_XDP_D2H_BAR_UPDATE -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L -//HDP_XDP_D2H_RSVD_3 -#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_4 -#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_5 -#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_6 -#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_7 -#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_8 -#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_9 -#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_10 -#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_11 -#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_12 -#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_13 -#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_14 -#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_15 -#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_16 -#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_17 -#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_18 -#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_19 -#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_20 -#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_21 -#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_22 -#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_23 -#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_24 -#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_25 -#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_26 -#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_27 -#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_28 -#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_29 -#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_30 -#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_31 -#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_32 -#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_33 -#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_34 -#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_DIRECT2HDP_LAST -#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 -#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_P2P_BAR_CFG -#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 -#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 -#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL -#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L -//HDP_XDP_P2P_MBX_OFFSET -#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL -//HDP_XDP_P2P_MBX_ADDR0 -#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_P2P_MBX_ADDR1 -#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_P2P_MBX_ADDR2 -#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_P2P_MBX_ADDR3 -#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_P2P_MBX_ADDR4 -#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_P2P_MBX_ADDR5 -#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_P2P_MBX_ADDR6 -#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_HDP_MBX_MC_CFG -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0 -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4 -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8 -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L -//HDP_XDP_HDP_MC_CFG -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L -//HDP_XDP_HST_CFG -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 -#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3 -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4 -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5 -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L -#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L -//HDP_XDP_HDP_IPH_CFG -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003FL -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000FC0L -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L -//HDP_XDP_P2P_BAR0 -#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR1 -#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR2 -#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR3 -#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR4 -#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR5 -#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR6 -#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR7 -#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L -//HDP_XDP_FLUSH_ARMED_STS -#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 -#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL -//HDP_XDP_FLUSH_CNTR0_STS -#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 -#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL -//HDP_XDP_BUSY_STS -#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 -#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003FFFFL -//HDP_XDP_STICKY -#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 -#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 -#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL -#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L -//HDP_XDP_CHKN -#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 -#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 -#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 -#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 -#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL -#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L -#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L -#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L -//HDP_XDP_BARS_ADDR_39_36 -#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 -#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 -#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 -#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc -#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 -#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 -#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c -#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL -#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L -#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L -#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L -#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L -#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L -#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L -//HDP_XDP_MC_VM_FB_LOCATION_BASE -#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 -#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL -//HDP_XDP_GPU_IOV_VIOLATION_LOG -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L -//HDP_XDP_MMHUB_ERROR -#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1 -#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2 -#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3 -#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5 -#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6 -#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7 -#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9 -#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa -#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb -#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd -#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe -#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf -#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11 -#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12 -#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13 -#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15 -#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16 -#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17 -#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L -#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L -#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L -#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L -#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L -#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L -#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L -#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L -#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L -#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L -#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L -#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L -#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L -#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L -#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L -#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L -#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L -#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L - -#endif -- GitLab From a6651c98c6bb4e0e0523d9cdc7868d8642ac9046 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Wed, 15 Nov 2017 18:39:21 +0800 Subject: [PATCH 0926/2547] drm/amd/include:cleanup vega10 mp header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/vega10/MP folder, remove mp_9_0_default.h Signed-off-by: Feifei Xu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 4 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +- .../amd/include/asic_reg/mp/mp_9_0_offset.h | 375 +++++ .../amd/include/asic_reg/mp/mp_9_0_sh_mask.h | 1463 +++++++++++++++++ .../asic_reg/vega10/MP/mp_9_0_default.h | 342 ---- .../asic_reg/vega10/MP/mp_9_0_offset.h | 375 ----- .../asic_reg/vega10/MP/mp_9_0_sh_mask.h | 1463 ----------------- .../gpu/drm/amd/powerplay/hwmgr/vega10_inc.h | 5 +- 8 files changed, 1844 insertions(+), 2187 deletions(-) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index b855964740bc..53df7446295e 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -32,8 +32,8 @@ #include "psp_v3_1.h" #include "vega10/soc15ip.h" -#include "vega10/MP/mp_9_0_offset.h" -#include "vega10/MP/mp_9_0_sh_mask.h" +#include "mp/mp_9_0_offset.h" +#include "mp/mp_9_0_sh_mask.h" #include "vega10/GC/gc_9_0_offset.h" #include "sdma0/sdma0_4_0_offset.h" #include "vega10/NBIO/nbio_6_1_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 11ece450e561..de66d22d097e 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -42,8 +42,8 @@ #include "sdma1/sdma1_4_0_offset.h" #include "hdp/hdp_4_0_offset.h" #include "hdp/hdp_4_0_sh_mask.h" -#include "vega10/MP/mp_9_0_offset.h" -#include "vega10/MP/mp_9_0_sh_mask.h" +#include "mp/mp_9_0_offset.h" +#include "mp/mp_9_0_sh_mask.h" #include "vega10/SMUIO/smuio_9_0_offset.h" #include "vega10/SMUIO/smuio_9_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h new file mode 100644 index 000000000000..299e5266a8c0 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h @@ -0,0 +1,375 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mp_9_0_OFFSET_HEADER +#define _mp_9_0_OFFSET_HEADER + + + +// addressBlock: mp_SmuMp0_SmnDec +// base address: 0x0 +#define mmMP0_SMN_C2PMSG_32 0x0060 +#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_33 0x0061 +#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_34 0x0062 +#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_35 0x0063 +#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_36 0x0064 +#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_37 0x0065 +#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_38 0x0066 +#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_39 0x0067 +#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_40 0x0068 +#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_41 0x0069 +#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_42 0x006a +#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_43 0x006b +#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_44 0x006c +#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_45 0x006d +#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_46 0x006e +#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_47 0x006f +#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_48 0x0070 +#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_49 0x0071 +#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_50 0x0072 +#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_51 0x0073 +#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_52 0x0074 +#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_53 0x0075 +#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_54 0x0076 +#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_55 0x0077 +#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_56 0x0078 +#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_57 0x0079 +#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_58 0x007a +#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_59 0x007b +#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_60 0x007c +#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_61 0x007d +#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_62 0x007e +#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_63 0x007f +#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_64 0x0080 +#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_65 0x0081 +#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_66 0x0082 +#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_67 0x0083 +#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_68 0x0084 +#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_69 0x0085 +#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_70 0x0086 +#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_71 0x0087 +#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_72 0x0088 +#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_73 0x0089 +#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_74 0x008a +#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_75 0x008b +#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_76 0x008c +#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_77 0x008d +#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_78 0x008e +#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_79 0x008f +#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_80 0x0090 +#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_81 0x0091 +#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_82 0x0092 +#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_83 0x0093 +#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_84 0x0094 +#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_85 0x0095 +#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_86 0x0096 +#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_87 0x0097 +#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_88 0x0098 +#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_89 0x0099 +#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_90 0x009a +#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_91 0x009b +#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_92 0x009c +#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_93 0x009d +#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_94 0x009e +#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_95 0x009f +#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_96 0x00a0 +#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_97 0x00a1 +#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_98 0x00a2 +#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_99 0x00a3 +#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_100 0x00a4 +#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_101 0x00a5 +#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_102 0x00a6 +#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_103 0x00a7 +#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0 +#define mmMP0_SMN_ACTIVE_FCN_ID 0x00c0 +#define mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmMP0_SMN_IH_CREDIT 0x00c1 +#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0 +#define mmMP0_SMN_IH_SW_INT 0x00c2 +#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0 +#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3 +#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 + + +// addressBlock: mp_SmuMp1_SmnDec +// base address: 0x0 +#define mmMP1_SMN_ACP2MP_RESP 0x0240 +#define mmMP1_SMN_ACP2MP_RESP_BASE_IDX 0 +#define mmMP1_SMN_DC2MP_RESP 0x0241 +#define mmMP1_SMN_DC2MP_RESP_BASE_IDX 0 +#define mmMP1_SMN_UVD2MP_RESP 0x0242 +#define mmMP1_SMN_UVD2MP_RESP_BASE_IDX 0 +#define mmMP1_SMN_VCE2MP_RESP 0x0243 +#define mmMP1_SMN_VCE2MP_RESP_BASE_IDX 0 +#define mmMP1_SMN_RLC2MP_RESP 0x0244 +#define mmMP1_SMN_RLC2MP_RESP_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_32 0x0260 +#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_33 0x0261 +#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_34 0x0262 +#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_35 0x0263 +#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_36 0x0264 +#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_37 0x0265 +#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_38 0x0266 +#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_39 0x0267 +#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_40 0x0268 +#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_41 0x0269 +#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_42 0x026a +#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_43 0x026b +#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_44 0x026c +#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_45 0x026d +#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_46 0x026e +#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_47 0x026f +#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_48 0x0270 +#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_49 0x0271 +#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_50 0x0272 +#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_51 0x0273 +#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_52 0x0274 +#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_53 0x0275 +#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_54 0x0276 +#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_55 0x0277 +#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_56 0x0278 +#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_57 0x0279 +#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_58 0x027a +#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_59 0x027b +#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_60 0x027c +#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_61 0x027d +#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_62 0x027e +#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_63 0x027f +#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_64 0x0280 +#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_65 0x0281 +#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_66 0x0282 +#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_67 0x0283 +#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_68 0x0284 +#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_69 0x0285 +#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_70 0x0286 +#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_71 0x0287 +#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_72 0x0288 +#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_73 0x0289 +#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_74 0x028a +#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_75 0x028b +#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_76 0x028c +#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_77 0x028d +#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_78 0x028e +#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_79 0x028f +#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_80 0x0290 +#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_81 0x0291 +#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_82 0x0292 +#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_83 0x0293 +#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_84 0x0294 +#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_85 0x0295 +#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_86 0x0296 +#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_87 0x0297 +#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_88 0x0298 +#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_89 0x0299 +#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_90 0x029a +#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_91 0x029b +#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_92 0x029c +#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_93 0x029d +#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_94 0x029e +#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_95 0x029f +#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_96 0x02a0 +#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_97 0x02a1 +#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_98 0x02a2 +#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_99 0x02a3 +#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_100 0x02a4 +#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_101 0x02a5 +#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_102 0x02a6 +#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_103 0x02a7 +#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0 +#define mmMP1_SMN_ACTIVE_FCN_ID 0x02c0 +#define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmMP1_SMN_IH_CREDIT 0x02c1 +#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0 +#define mmMP1_SMN_IH_SW_INT 0x02c2 +#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0 +#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3 +#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 +#define mmMP1_SMN_FPS_CNT 0x02c4 +#define mmMP1_SMN_FPS_CNT_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH0 0x03c0 +#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH1 0x03c1 +#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH2 0x03c2 +#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH3 0x03c3 +#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH4 0x03c4 +#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH5 0x03c5 +#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH6 0x03c6 +#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH7 0x03c7 +#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH8 0x03c8 +#define mmMP1_SMN_EXT_SCRATCH8_BASE_IDX 0 + + +// addressBlock: mp_SmuMp1Pub_CruDec +// base address: 0x0 +#define mmMP1_SMN_PUB_CTRL 0x02c5 +#define mmMP1_SMN_PUB_CTRL_BASE_IDX 0 + + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h new file mode 100644 index 000000000000..d5a623deca77 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h @@ -0,0 +1,1463 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mp_9_0_SH_MASK_HEADER +#define _mp_9_0_SH_MASK_HEADER + + +// addressBlock: mp_SmuMp0_SmnDec +//MP0_SMN_C2PMSG_32 +#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_33 +#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_34 +#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_35 +#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_36 +#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_37 +#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_38 +#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_39 +#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_40 +#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_41 +#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_42 +#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_43 +#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_44 +#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_45 +#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_46 +#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_47 +#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_48 +#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_49 +#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_50 +#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_51 +#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_52 +#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_53 +#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_54 +#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_55 +#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_56 +#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_57 +#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_58 +#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_59 +#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_60 +#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_61 +#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_62 +#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_63 +#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_64 +#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_65 +#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_66 +#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_67 +#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_68 +#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_69 +#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_70 +#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_71 +#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_72 +#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_73 +#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_74 +#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_75 +#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_76 +#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_77 +#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_78 +#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_79 +#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_80 +#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_81 +#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_82 +#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_83 +#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_84 +#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_85 +#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_86 +#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_87 +#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_88 +#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_89 +#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_90 +#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_91 +#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_92 +#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_93 +#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_94 +#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_95 +#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_96 +#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_97 +#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_98 +#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_99 +#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_100 +#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_101 +#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_102 +#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_103 +#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_ACTIVE_FCN_ID +#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP0_SMN_IH_CREDIT +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP0_SMN_IH_SW_INT +#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1 +#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L +#define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL +//MP0_SMN_IH_SW_INT_CTRL +#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 +#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L +#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L + + +// addressBlock: mp_SmuMp1_SmnDec +//MP1_SMN_ACP2MP_RESP +#define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_DC2MP_RESP +#define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_UVD2MP_RESP +#define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_VCE2MP_RESP +#define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_RLC2MP_RESP +#define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_32 +#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_33 +#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_34 +#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_35 +#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_36 +#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_37 +#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_38 +#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_39 +#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_40 +#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_41 +#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_42 +#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_43 +#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_44 +#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_45 +#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_46 +#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_47 +#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_48 +#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_49 +#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_50 +#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_51 +#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_52 +#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_53 +#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_54 +#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_55 +#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_56 +#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_57 +#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_58 +#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_59 +#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_60 +#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_61 +#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_62 +#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_63 +#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_64 +#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_65 +#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_66 +#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_67 +#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_68 +#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_69 +#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_70 +#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_71 +#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_72 +#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_73 +#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_74 +#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_75 +#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_76 +#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_77 +#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_78 +#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_79 +#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_80 +#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_81 +#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_82 +#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_83 +#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_84 +#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_85 +#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_86 +#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_87 +#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_88 +#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_89 +#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_90 +#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_91 +#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_92 +#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_93 +#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_94 +#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_95 +#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_96 +#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_97 +#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_98 +#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_99 +#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_100 +#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_101 +#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_102 +#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_103 +#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_ACTIVE_FCN_ID +#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP1_SMN_IH_CREDIT +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_SMN_IH_SW_INT +#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1 +#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L +#define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL +//MP1_SMN_IH_SW_INT_CTRL +#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L +#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L +//MP1_SMN_FPS_CNT +#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH0 +#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH1 +#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH2 +#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH3 +#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH4 +#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH5 +#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH6 +#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH7 +#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH8 +#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL + + + + +// addressBlock: mp_SmuMp0Pub_CruDec +//MP0_SOC_INFO +#define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x0 +#define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x2 +#define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L +#define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001CL +//MP0_PUB_SCRATCH0 +#define MP0_PUB_SCRATCH0__DATA__SHIFT 0x0 +#define MP0_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP0_PUB_SCRATCH1 +#define MP0_PUB_SCRATCH1__DATA__SHIFT 0x0 +#define MP0_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP0_PUB_SCRATCH2 +#define MP0_PUB_SCRATCH2__DATA__SHIFT 0x0 +#define MP0_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP0_PUB_SCRATCH3 +#define MP0_PUB_SCRATCH3__DATA__SHIFT 0x0 +#define MP0_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP0_FW_INTF +#define MP0_FW_INTF__SS_SECURE__SHIFT 0x13 +#define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L +//MP0_C2PMSG_0 +#define MP0_C2PMSG_0__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_1 +#define MP0_C2PMSG_1__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_2 +#define MP0_C2PMSG_2__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_3 +#define MP0_C2PMSG_3__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_4 +#define MP0_C2PMSG_4__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_5 +#define MP0_C2PMSG_5__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_6 +#define MP0_C2PMSG_6__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_7 +#define MP0_C2PMSG_7__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_8 +#define MP0_C2PMSG_8__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_9 +#define MP0_C2PMSG_9__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_10 +#define MP0_C2PMSG_10__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_11 +#define MP0_C2PMSG_11__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_12 +#define MP0_C2PMSG_12__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_13 +#define MP0_C2PMSG_13__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_14 +#define MP0_C2PMSG_14__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_15 +#define MP0_C2PMSG_15__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_16 +#define MP0_C2PMSG_16__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_17 +#define MP0_C2PMSG_17__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_18 +#define MP0_C2PMSG_18__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_19 +#define MP0_C2PMSG_19__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_20 +#define MP0_C2PMSG_20__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_21 +#define MP0_C2PMSG_21__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_22 +#define MP0_C2PMSG_22__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_23 +#define MP0_C2PMSG_23__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_24 +#define MP0_C2PMSG_24__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_25 +#define MP0_C2PMSG_25__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_26 +#define MP0_C2PMSG_26__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_27 +#define MP0_C2PMSG_27__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_28 +#define MP0_C2PMSG_28__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_29 +#define MP0_C2PMSG_29__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_30 +#define MP0_C2PMSG_30__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_31 +#define MP0_C2PMSG_31__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2CMSG_0 +#define MP0_P2CMSG_0__CONTENT__SHIFT 0x0 +#define MP0_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2CMSG_1 +#define MP0_P2CMSG_1__CONTENT__SHIFT 0x0 +#define MP0_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2CMSG_2 +#define MP0_P2CMSG_2__CONTENT__SHIFT 0x0 +#define MP0_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2CMSG_3 +#define MP0_P2CMSG_3__CONTENT__SHIFT 0x0 +#define MP0_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2CMSG_INTEN +#define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x0 +#define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000FL +//MP0_P2CMSG_INTSTS +#define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 +#define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 +#define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 +#define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 +#define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L +#define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L +#define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L +#define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L +//MP0_C2PMSG_ATTR_0 +#define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xFFFFFFFFL +//MP0_C2PMSG_ATTR_1 +#define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xFFFFFFFFL +//MP0_C2PMSG_ATTR_2 +#define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xFFFFFFFFL +//MP0_C2PMSG_ATTR_3 +#define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xFFFFFFFFL +//MP0_C2PMSG_ATTR_4 +#define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xFFFFFFFFL +//MP0_C2PMSG_ATTR_5 +#define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xFFFFFFFFL +//MP0_C2PMSG_ATTR_6 +#define MP0_C2PMSG_ATTR_6__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_6__MSG_ATTR_MASK 0x0000FFFFL +//MP0_P2CMSG_ATTR +#define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x0 +#define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000FFL +//MP0_P2SMSG_0 +#define MP0_P2SMSG_0__CONTENT__SHIFT 0x0 +#define MP0_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2SMSG_1 +#define MP0_P2SMSG_1__CONTENT__SHIFT 0x0 +#define MP0_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2SMSG_2 +#define MP0_P2SMSG_2__CONTENT__SHIFT 0x0 +#define MP0_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2SMSG_3 +#define MP0_P2SMSG_3__CONTENT__SHIFT 0x0 +#define MP0_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2SMSG_ATTR +#define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x0 +#define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000FFL +//MP0_S2PMSG_ATTR +#define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x0 +#define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L +//MP0_P2SMSG_INTSTS +#define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 +#define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 +#define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 +#define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 +#define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L +#define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L +#define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L +#define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L +//MP0_S2PMSG_0 +#define MP0_S2PMSG_0__CONTENT__SHIFT 0x0 +#define MP0_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_32 +#define MP0_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_33 +#define MP0_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_34 +#define MP0_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_35 +#define MP0_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_36 +#define MP0_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_37 +#define MP0_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_38 +#define MP0_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_39 +#define MP0_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_40 +#define MP0_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_41 +#define MP0_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_42 +#define MP0_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_43 +#define MP0_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_44 +#define MP0_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_45 +#define MP0_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_46 +#define MP0_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_47 +#define MP0_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_48 +#define MP0_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_49 +#define MP0_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_50 +#define MP0_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_51 +#define MP0_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_52 +#define MP0_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_53 +#define MP0_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_54 +#define MP0_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_55 +#define MP0_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_56 +#define MP0_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_57 +#define MP0_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_58 +#define MP0_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_59 +#define MP0_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_60 +#define MP0_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_61 +#define MP0_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_62 +#define MP0_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_63 +#define MP0_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_64 +#define MP0_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_65 +#define MP0_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_66 +#define MP0_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_67 +#define MP0_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_68 +#define MP0_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_69 +#define MP0_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_70 +#define MP0_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_71 +#define MP0_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_72 +#define MP0_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_73 +#define MP0_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_74 +#define MP0_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_75 +#define MP0_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_76 +#define MP0_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_77 +#define MP0_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_78 +#define MP0_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_79 +#define MP0_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_80 +#define MP0_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_81 +#define MP0_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_82 +#define MP0_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_83 +#define MP0_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_84 +#define MP0_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_85 +#define MP0_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_86 +#define MP0_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_87 +#define MP0_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_88 +#define MP0_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_89 +#define MP0_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_90 +#define MP0_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_91 +#define MP0_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_92 +#define MP0_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_93 +#define MP0_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_94 +#define MP0_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_95 +#define MP0_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_96 +#define MP0_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_97 +#define MP0_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_98 +#define MP0_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_99 +#define MP0_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_100 +#define MP0_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_101 +#define MP0_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_102 +#define MP0_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_103 +#define MP0_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP0_ACTIVE_FCN_ID +#define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP0_IH_CREDIT +#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP0_IH_SW_INT +#define MP0_IH_SW_INT__ID__SHIFT 0x0 +#define MP0_IH_SW_INT__VALID__SHIFT 0x8 +#define MP0_IH_SW_INT__ID_MASK 0x000000FFL +#define MP0_IH_SW_INT__VALID_MASK 0x00000100L +//MP0_IH_SW_INT_CTRL +#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L + + +//CGTT_DRM_CLK_CTRL0 +#define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_DRM_CLK_CTRL0__DIV_ID__SHIFT 0xc +#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0__SHIFT 0x15 +#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG__SHIFT 0x16 +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_DRM_CLK_CTRL0__DIV_ID_MASK 0x00007000L +#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0_MASK 0x00200000L +#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG_MASK 0x00400000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L +//DRM_LIGHT_SLEEP_CTRL +#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0 +#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK 0x00000001L + + +// addressBlock: mp_SmuMp1Pub_CruDec +//MP1_SMN_PUB_CTRL +#define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0 +#define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L +//MP1_FIRMWARE_FLAGS +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL +//MP1_PUB_SCRATCH0 +#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_PUB_SCRATCH1 +#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_PUB_SCRATCH2 +#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_PUB_SCRATCH3 +#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_C2PMSG_0 +#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_1 +#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_2 +#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_3 +#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_4 +#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_5 +#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_6 +#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_7 +#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_8 +#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_9 +#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_10 +#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_11 +#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_12 +#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_13 +#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_14 +#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_15 +#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_16 +#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_17 +#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_18 +#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_19 +#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_20 +#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_21 +#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_22 +#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_23 +#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_24 +#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_25 +#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_26 +#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_27 +#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_28 +#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_29 +#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_30 +#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_31 +#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_0 +#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_1 +#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_2 +#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_3 +#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_INTEN +#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 +#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL +//MP1_P2CMSG_INTSTS +#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 +#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 +#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 +#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 +#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L +#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L +#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L +#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L +//MP1_P2SMSG_0 +#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0 +#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2SMSG_1 +#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0 +#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2SMSG_2 +#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0 +#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2SMSG_3 +#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0 +#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2SMSG_INTSTS +#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 +#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 +#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 +#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 +#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L +#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L +#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L +#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L +//MP1_S2PMSG_0 +#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0 +#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_ACP2MP_RESP +#define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_DC2MP_RESP +#define MP1_DC2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_UVD2MP_RESP +#define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_VCE2MP_RESP +#define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_RLC2MP_RESP +#define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_32 +#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_33 +#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_34 +#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_35 +#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_36 +#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_37 +#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_38 +#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_39 +#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_40 +#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_41 +#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_42 +#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_43 +#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_44 +#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_45 +#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_46 +#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_47 +#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_48 +#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_49 +#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_50 +#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_51 +#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_52 +#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_53 +#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_54 +#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_55 +#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_56 +#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_57 +#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_58 +#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_59 +#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_60 +#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_61 +#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_62 +#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_63 +#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_64 +#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_65 +#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_66 +#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_67 +#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_68 +#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_69 +#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_70 +#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_71 +#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_72 +#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_73 +#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_74 +#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_75 +#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_76 +#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_77 +#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_78 +#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_79 +#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_80 +#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_81 +#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_82 +#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_83 +#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_84 +#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_85 +#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_86 +#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_87 +#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_88 +#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_89 +#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_90 +#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_91 +#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_92 +#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_93 +#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_94 +#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_95 +#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_96 +#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_97 +#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_98 +#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_99 +#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_100 +#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_101 +#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_102 +#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_103 +#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_ACTIVE_FCN_ID +#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP1_IH_CREDIT +#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_IH_SW_INT +#define MP1_IH_SW_INT__ID__SHIFT 0x0 +#define MP1_IH_SW_INT__VALID__SHIFT 0x8 +#define MP1_IH_SW_INT__ID_MASK 0x000000FFL +#define MP1_IH_SW_INT__VALID_MASK 0x00000100L +//MP1_IH_SW_INT_CTRL +#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +//MP1_FPS_CNT +#define MP1_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +//MP1_PUB_CTRL +#define MP1_PUB_CTRL__RESET__SHIFT 0x0 +#define MP1_PUB_CTRL__RESET_MASK 0x00000001L +//MP1_EXT_SCRATCH0 +#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH1 +#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH2 +#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH3 +#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH4 +#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH5 +#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH6 +#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH7 +#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h deleted file mode 100644 index 98ba7d832423..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _mp_9_0_DEFAULT_HEADER -#define _mp_9_0_DEFAULT_HEADER - - -// addressBlock: mp_SmuMp0_SmnDec -#define mmMP0_SMN_C2PMSG_32_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_33_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_34_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_35_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_36_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_37_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_38_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_39_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_40_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_41_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_42_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_43_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_44_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_45_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_46_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_47_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_48_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_49_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_50_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_51_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_52_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_53_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_54_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_55_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_56_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_57_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_58_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_59_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_60_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_61_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_62_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_63_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_64_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_65_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_66_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_67_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_68_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_69_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_70_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_71_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_72_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_73_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_74_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_75_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_76_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_77_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_78_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_79_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_80_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_81_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_82_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_83_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_84_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_85_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_86_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_87_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_88_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_89_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_90_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_91_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_92_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_93_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_94_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_95_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_96_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_97_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_98_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_99_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_100_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_101_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_102_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_103_DEFAULT 0x00000000 -#define mmMP0_SMN_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmMP0_SMN_IH_CREDIT_DEFAULT 0x00000000 -#define mmMP0_SMN_IH_SW_INT_DEFAULT 0x00000000 -#define mmMP0_SMN_IH_SW_INT_CTRL_DEFAULT 0x00000000 - - -// addressBlock: mp_SmuMp1_SmnDec -#define mmMP1_SMN_ACP2MP_RESP_DEFAULT 0x00000000 -#define mmMP1_SMN_DC2MP_RESP_DEFAULT 0x00000000 -#define mmMP1_SMN_UVD2MP_RESP_DEFAULT 0x00000000 -#define mmMP1_SMN_VCE2MP_RESP_DEFAULT 0x00000000 -#define mmMP1_SMN_RLC2MP_RESP_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_32_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_33_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_34_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_35_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_36_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_37_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_38_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_39_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_40_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_41_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_42_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_43_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_44_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_45_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_46_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_47_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_48_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_49_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_50_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_51_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_52_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_53_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_54_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_55_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_56_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_57_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_58_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_59_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_60_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_61_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_62_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_63_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_64_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_65_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_66_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_67_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_68_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_69_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_70_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_71_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_72_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_73_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_74_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_75_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_76_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_77_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_78_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_79_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_80_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_81_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_82_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_83_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_84_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_85_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_86_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_87_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_88_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_89_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_90_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_91_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_92_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_93_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_94_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_95_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_96_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_97_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_98_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_99_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_100_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_101_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_102_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_103_DEFAULT 0x00000000 -#define mmMP1_SMN_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmMP1_SMN_IH_CREDIT_DEFAULT 0x00000000 -#define mmMP1_SMN_IH_SW_INT_DEFAULT 0x00000000 -#define mmMP1_SMN_IH_SW_INT_CTRL_DEFAULT 0x00000000 -#define mmMP1_SMN_FPS_CNT_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH0_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH1_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH2_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH3_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH4_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH5_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH6_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH7_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH8_DEFAULT 0x00000000 - - -// addressBlock: mp_SmuMp1Pub_CruDec -#define mmMP1_SMN_PUB_CTRL_DEFAULT 0x00000001 -#define smnMP1_FIRMWARE_FLAGS_DEFAULT 0x00000000 -#define smnMP1_PUB_SCRATCH0_DEFAULT 0x00000000 -#define smnMP1_PUB_SCRATCH1_DEFAULT 0x00000000 -#define smnMP1_PUB_SCRATCH2_DEFAULT 0x00000000 -#define smnMP1_PUB_SCRATCH3_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_0_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_1_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_2_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_3_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_4_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_5_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_6_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_7_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_8_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_9_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_10_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_11_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_12_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_13_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_14_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_15_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_16_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_17_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_18_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_19_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_20_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_21_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_22_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_23_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_24_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_25_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_26_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_27_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_28_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_29_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_30_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_31_DEFAULT 0x00000000 -#define smnMP1_P2CMSG_0_DEFAULT 0x00000000 -#define smnMP1_P2CMSG_1_DEFAULT 0x00000000 -#define smnMP1_P2CMSG_2_DEFAULT 0x00000000 -#define smnMP1_P2CMSG_3_DEFAULT 0x00000000 -#define smnMP1_P2CMSG_INTEN_DEFAULT 0x00000000 -#define smnMP1_P2CMSG_INTSTS_DEFAULT 0x00000000 -#define smnMP1_P2SMSG_0_DEFAULT 0x00000000 -#define smnMP1_P2SMSG_1_DEFAULT 0x00000000 -#define smnMP1_P2SMSG_2_DEFAULT 0x00000000 -#define smnMP1_P2SMSG_3_DEFAULT 0x00000000 -#define smnMP1_P2SMSG_INTSTS_DEFAULT 0x00000000 -#define smnMP1_S2PMSG_0_DEFAULT 0x00000000 -#define smnMP1_ACP2MP_RESP_DEFAULT 0x00000000 -#define smnMP1_DC2MP_RESP_DEFAULT 0x00000000 -#define smnMP1_UVD2MP_RESP_DEFAULT 0x00000000 -#define smnMP1_VCE2MP_RESP_DEFAULT 0x00000000 -#define smnMP1_RLC2MP_RESP_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_32_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_33_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_34_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_35_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_36_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_37_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_38_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_39_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_40_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_41_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_42_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_43_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_44_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_45_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_46_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_47_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_48_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_49_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_50_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_51_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_52_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_53_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_54_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_55_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_56_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_57_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_58_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_59_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_60_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_61_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_62_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_63_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_64_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_65_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_66_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_67_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_68_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_69_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_70_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_71_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_72_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_73_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_74_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_75_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_76_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_77_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_78_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_79_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_80_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_81_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_82_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_83_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_84_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_85_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_86_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_87_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_88_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_89_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_90_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_91_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_92_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_93_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_94_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_95_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_96_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_97_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_98_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_99_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_100_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_101_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_102_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_103_DEFAULT 0x00000000 -#define smnMP1_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define smnMP1_IH_CREDIT_DEFAULT 0x00000000 -#define smnMP1_IH_SW_INT_DEFAULT 0x00000000 -#define smnMP1_IH_SW_INT_CTRL_DEFAULT 0x00000000 -#define smnMP1_FPS_CNT_DEFAULT 0x00000000 -#define smnMP1_PUB_CTRL_DEFAULT 0x00000001 -#define smnMP1_EXT_SCRATCH0_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH1_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH2_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH3_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH4_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH5_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH6_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH7_DEFAULT 0x00000000 - - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h deleted file mode 100644 index 621e8809c867..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h +++ /dev/null @@ -1,375 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _mp_9_0_OFFSET_HEADER -#define _mp_9_0_OFFSET_HEADER - - - -// addressBlock: mp_SmuMp0_SmnDec -// base address: 0x0 -#define mmMP0_SMN_C2PMSG_32 0x0060 -#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_33 0x0061 -#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_34 0x0062 -#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_35 0x0063 -#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_36 0x0064 -#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_37 0x0065 -#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_38 0x0066 -#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_39 0x0067 -#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_40 0x0068 -#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_41 0x0069 -#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_42 0x006a -#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_43 0x006b -#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_44 0x006c -#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_45 0x006d -#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_46 0x006e -#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_47 0x006f -#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_48 0x0070 -#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_49 0x0071 -#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_50 0x0072 -#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_51 0x0073 -#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_52 0x0074 -#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_53 0x0075 -#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_54 0x0076 -#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_55 0x0077 -#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_56 0x0078 -#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_57 0x0079 -#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_58 0x007a -#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_59 0x007b -#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_60 0x007c -#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_61 0x007d -#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_62 0x007e -#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_63 0x007f -#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_64 0x0080 -#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_65 0x0081 -#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_66 0x0082 -#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_67 0x0083 -#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_68 0x0084 -#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_69 0x0085 -#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_70 0x0086 -#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_71 0x0087 -#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_72 0x0088 -#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_73 0x0089 -#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_74 0x008a -#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_75 0x008b -#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_76 0x008c -#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_77 0x008d -#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_78 0x008e -#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_79 0x008f -#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_80 0x0090 -#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_81 0x0091 -#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_82 0x0092 -#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_83 0x0093 -#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_84 0x0094 -#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_85 0x0095 -#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_86 0x0096 -#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_87 0x0097 -#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_88 0x0098 -#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_89 0x0099 -#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_90 0x009a -#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_91 0x009b -#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_92 0x009c -#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_93 0x009d -#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_94 0x009e -#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_95 0x009f -#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_96 0x00a0 -#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_97 0x00a1 -#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_98 0x00a2 -#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_99 0x00a3 -#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_100 0x00a4 -#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_101 0x00a5 -#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_102 0x00a6 -#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_103 0x00a7 -#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0 -#define mmMP0_SMN_ACTIVE_FCN_ID 0x00c0 -#define mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX 0 -#define mmMP0_SMN_IH_CREDIT 0x00c1 -#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0 -#define mmMP0_SMN_IH_SW_INT 0x00c2 -#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0 -#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3 -#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 - - -// addressBlock: mp_SmuMp1_SmnDec -// base address: 0x0 -#define mmMP1_SMN_ACP2MP_RESP 0x0240 -#define mmMP1_SMN_ACP2MP_RESP_BASE_IDX 0 -#define mmMP1_SMN_DC2MP_RESP 0x0241 -#define mmMP1_SMN_DC2MP_RESP_BASE_IDX 0 -#define mmMP1_SMN_UVD2MP_RESP 0x0242 -#define mmMP1_SMN_UVD2MP_RESP_BASE_IDX 0 -#define mmMP1_SMN_VCE2MP_RESP 0x0243 -#define mmMP1_SMN_VCE2MP_RESP_BASE_IDX 0 -#define mmMP1_SMN_RLC2MP_RESP 0x0244 -#define mmMP1_SMN_RLC2MP_RESP_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_32 0x0260 -#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_33 0x0261 -#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_34 0x0262 -#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_35 0x0263 -#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_36 0x0264 -#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_37 0x0265 -#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_38 0x0266 -#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_39 0x0267 -#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_40 0x0268 -#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_41 0x0269 -#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_42 0x026a -#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_43 0x026b -#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_44 0x026c -#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_45 0x026d -#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_46 0x026e -#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_47 0x026f -#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_48 0x0270 -#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_49 0x0271 -#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_50 0x0272 -#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_51 0x0273 -#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_52 0x0274 -#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_53 0x0275 -#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_54 0x0276 -#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_55 0x0277 -#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_56 0x0278 -#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_57 0x0279 -#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_58 0x027a -#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_59 0x027b -#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_60 0x027c -#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_61 0x027d -#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_62 0x027e -#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_63 0x027f -#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_64 0x0280 -#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_65 0x0281 -#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_66 0x0282 -#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_67 0x0283 -#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_68 0x0284 -#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_69 0x0285 -#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_70 0x0286 -#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_71 0x0287 -#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_72 0x0288 -#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_73 0x0289 -#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_74 0x028a -#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_75 0x028b -#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_76 0x028c -#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_77 0x028d -#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_78 0x028e -#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_79 0x028f -#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_80 0x0290 -#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_81 0x0291 -#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_82 0x0292 -#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_83 0x0293 -#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_84 0x0294 -#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_85 0x0295 -#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_86 0x0296 -#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_87 0x0297 -#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_88 0x0298 -#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_89 0x0299 -#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_90 0x029a -#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_91 0x029b -#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_92 0x029c -#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_93 0x029d -#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_94 0x029e -#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_95 0x029f -#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_96 0x02a0 -#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_97 0x02a1 -#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_98 0x02a2 -#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_99 0x02a3 -#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_100 0x02a4 -#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_101 0x02a5 -#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_102 0x02a6 -#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_103 0x02a7 -#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0 -#define mmMP1_SMN_ACTIVE_FCN_ID 0x02c0 -#define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX 0 -#define mmMP1_SMN_IH_CREDIT 0x02c1 -#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0 -#define mmMP1_SMN_IH_SW_INT 0x02c2 -#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0 -#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3 -#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 -#define mmMP1_SMN_FPS_CNT 0x02c4 -#define mmMP1_SMN_FPS_CNT_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH0 0x03c0 -#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH1 0x03c1 -#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH2 0x03c2 -#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH3 0x03c3 -#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH4 0x03c4 -#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH5 0x03c5 -#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH6 0x03c6 -#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH7 0x03c7 -#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH8 0x03c8 -#define mmMP1_SMN_EXT_SCRATCH8_BASE_IDX 0 - - -// addressBlock: mp_SmuMp1Pub_CruDec -// base address: 0x0 -#define mmMP1_SMN_PUB_CTRL 0x02c5 -#define mmMP1_SMN_PUB_CTRL_BASE_IDX 0 - - - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h deleted file mode 100644 index ae7b51870322..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h +++ /dev/null @@ -1,1463 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _mp_9_0_SH_MASK_HEADER -#define _mp_9_0_SH_MASK_HEADER - - -// addressBlock: mp_SmuMp0_SmnDec -//MP0_SMN_C2PMSG_32 -#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_33 -#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_34 -#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_35 -#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_36 -#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_37 -#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_38 -#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_39 -#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_40 -#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_41 -#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_42 -#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_43 -#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_44 -#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_45 -#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_46 -#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_47 -#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_48 -#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_49 -#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_50 -#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_51 -#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_52 -#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_53 -#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_54 -#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_55 -#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_56 -#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_57 -#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_58 -#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_59 -#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_60 -#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_61 -#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_62 -#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_63 -#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_64 -#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_65 -#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_66 -#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_67 -#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_68 -#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_69 -#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_70 -#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_71 -#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_72 -#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_73 -#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_74 -#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_75 -#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_76 -#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_77 -#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_78 -#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_79 -#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_80 -#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_81 -#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_82 -#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_83 -#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_84 -#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_85 -#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_86 -#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_87 -#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_88 -#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_89 -#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_90 -#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_91 -#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_92 -#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_93 -#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_94 -#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_95 -#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_96 -#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_97 -#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_98 -#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_99 -#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_100 -#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_101 -#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_102 -#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_103 -#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_ACTIVE_FCN_ID -#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//MP0_SMN_IH_CREDIT -#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 -#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L -//MP0_SMN_IH_SW_INT -#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0 -#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1 -#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L -#define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL -//MP0_SMN_IH_SW_INT_CTRL -#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 -#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 -#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L -#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L - - -// addressBlock: mp_SmuMp1_SmnDec -//MP1_SMN_ACP2MP_RESP -#define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_DC2MP_RESP -#define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_UVD2MP_RESP -#define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_VCE2MP_RESP -#define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_RLC2MP_RESP -#define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_32 -#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_33 -#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_34 -#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_35 -#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_36 -#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_37 -#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_38 -#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_39 -#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_40 -#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_41 -#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_42 -#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_43 -#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_44 -#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_45 -#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_46 -#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_47 -#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_48 -#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_49 -#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_50 -#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_51 -#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_52 -#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_53 -#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_54 -#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_55 -#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_56 -#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_57 -#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_58 -#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_59 -#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_60 -#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_61 -#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_62 -#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_63 -#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_64 -#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_65 -#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_66 -#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_67 -#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_68 -#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_69 -#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_70 -#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_71 -#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_72 -#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_73 -#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_74 -#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_75 -#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_76 -#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_77 -#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_78 -#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_79 -#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_80 -#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_81 -#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_82 -#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_83 -#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_84 -#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_85 -#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_86 -#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_87 -#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_88 -#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_89 -#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_90 -#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_91 -#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_92 -#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_93 -#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_94 -#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_95 -#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_96 -#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_97 -#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_98 -#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_99 -#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_100 -#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_101 -#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_102 -#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_103 -#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_ACTIVE_FCN_ID -#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//MP1_SMN_IH_CREDIT -#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 -#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L -//MP1_SMN_IH_SW_INT -#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0 -#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1 -#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L -#define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL -//MP1_SMN_IH_SW_INT_CTRL -#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 -#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 -#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L -#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L -//MP1_SMN_FPS_CNT -#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 -#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH0 -#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH1 -#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH2 -#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH3 -#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH4 -#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH5 -#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH6 -#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH7 -#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH8 -#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL - - - - -// addressBlock: mp_SmuMp0Pub_CruDec -//MP0_SOC_INFO -#define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x0 -#define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x2 -#define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L -#define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001CL -//MP0_PUB_SCRATCH0 -#define MP0_PUB_SCRATCH0__DATA__SHIFT 0x0 -#define MP0_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL -//MP0_PUB_SCRATCH1 -#define MP0_PUB_SCRATCH1__DATA__SHIFT 0x0 -#define MP0_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL -//MP0_PUB_SCRATCH2 -#define MP0_PUB_SCRATCH2__DATA__SHIFT 0x0 -#define MP0_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL -//MP0_PUB_SCRATCH3 -#define MP0_PUB_SCRATCH3__DATA__SHIFT 0x0 -#define MP0_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL -//MP0_FW_INTF -#define MP0_FW_INTF__SS_SECURE__SHIFT 0x13 -#define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L -//MP0_C2PMSG_0 -#define MP0_C2PMSG_0__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_1 -#define MP0_C2PMSG_1__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_2 -#define MP0_C2PMSG_2__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_3 -#define MP0_C2PMSG_3__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_4 -#define MP0_C2PMSG_4__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_5 -#define MP0_C2PMSG_5__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_6 -#define MP0_C2PMSG_6__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_7 -#define MP0_C2PMSG_7__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_8 -#define MP0_C2PMSG_8__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_9 -#define MP0_C2PMSG_9__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_10 -#define MP0_C2PMSG_10__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_11 -#define MP0_C2PMSG_11__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_12 -#define MP0_C2PMSG_12__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_13 -#define MP0_C2PMSG_13__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_14 -#define MP0_C2PMSG_14__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_15 -#define MP0_C2PMSG_15__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_16 -#define MP0_C2PMSG_16__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_17 -#define MP0_C2PMSG_17__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_18 -#define MP0_C2PMSG_18__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_19 -#define MP0_C2PMSG_19__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_20 -#define MP0_C2PMSG_20__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_21 -#define MP0_C2PMSG_21__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_22 -#define MP0_C2PMSG_22__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_23 -#define MP0_C2PMSG_23__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_24 -#define MP0_C2PMSG_24__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_25 -#define MP0_C2PMSG_25__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_26 -#define MP0_C2PMSG_26__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_27 -#define MP0_C2PMSG_27__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_28 -#define MP0_C2PMSG_28__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_29 -#define MP0_C2PMSG_29__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_30 -#define MP0_C2PMSG_30__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_31 -#define MP0_C2PMSG_31__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2CMSG_0 -#define MP0_P2CMSG_0__CONTENT__SHIFT 0x0 -#define MP0_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2CMSG_1 -#define MP0_P2CMSG_1__CONTENT__SHIFT 0x0 -#define MP0_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2CMSG_2 -#define MP0_P2CMSG_2__CONTENT__SHIFT 0x0 -#define MP0_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2CMSG_3 -#define MP0_P2CMSG_3__CONTENT__SHIFT 0x0 -#define MP0_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2CMSG_INTEN -#define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x0 -#define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000FL -//MP0_P2CMSG_INTSTS -#define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 -#define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 -#define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 -#define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 -#define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L -#define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L -#define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L -#define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L -//MP0_C2PMSG_ATTR_0 -#define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xFFFFFFFFL -//MP0_C2PMSG_ATTR_1 -#define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xFFFFFFFFL -//MP0_C2PMSG_ATTR_2 -#define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xFFFFFFFFL -//MP0_C2PMSG_ATTR_3 -#define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xFFFFFFFFL -//MP0_C2PMSG_ATTR_4 -#define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xFFFFFFFFL -//MP0_C2PMSG_ATTR_5 -#define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xFFFFFFFFL -//MP0_C2PMSG_ATTR_6 -#define MP0_C2PMSG_ATTR_6__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_6__MSG_ATTR_MASK 0x0000FFFFL -//MP0_P2CMSG_ATTR -#define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x0 -#define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000FFL -//MP0_P2SMSG_0 -#define MP0_P2SMSG_0__CONTENT__SHIFT 0x0 -#define MP0_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2SMSG_1 -#define MP0_P2SMSG_1__CONTENT__SHIFT 0x0 -#define MP0_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2SMSG_2 -#define MP0_P2SMSG_2__CONTENT__SHIFT 0x0 -#define MP0_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2SMSG_3 -#define MP0_P2SMSG_3__CONTENT__SHIFT 0x0 -#define MP0_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2SMSG_ATTR -#define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x0 -#define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000FFL -//MP0_S2PMSG_ATTR -#define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x0 -#define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L -//MP0_P2SMSG_INTSTS -#define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 -#define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 -#define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 -#define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 -#define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L -#define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L -#define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L -#define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L -//MP0_S2PMSG_0 -#define MP0_S2PMSG_0__CONTENT__SHIFT 0x0 -#define MP0_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_32 -#define MP0_C2PMSG_32__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_33 -#define MP0_C2PMSG_33__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_34 -#define MP0_C2PMSG_34__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_35 -#define MP0_C2PMSG_35__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_36 -#define MP0_C2PMSG_36__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_37 -#define MP0_C2PMSG_37__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_38 -#define MP0_C2PMSG_38__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_39 -#define MP0_C2PMSG_39__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_40 -#define MP0_C2PMSG_40__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_41 -#define MP0_C2PMSG_41__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_42 -#define MP0_C2PMSG_42__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_43 -#define MP0_C2PMSG_43__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_44 -#define MP0_C2PMSG_44__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_45 -#define MP0_C2PMSG_45__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_46 -#define MP0_C2PMSG_46__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_47 -#define MP0_C2PMSG_47__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_48 -#define MP0_C2PMSG_48__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_49 -#define MP0_C2PMSG_49__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_50 -#define MP0_C2PMSG_50__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_51 -#define MP0_C2PMSG_51__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_52 -#define MP0_C2PMSG_52__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_53 -#define MP0_C2PMSG_53__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_54 -#define MP0_C2PMSG_54__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_55 -#define MP0_C2PMSG_55__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_56 -#define MP0_C2PMSG_56__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_57 -#define MP0_C2PMSG_57__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_58 -#define MP0_C2PMSG_58__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_59 -#define MP0_C2PMSG_59__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_60 -#define MP0_C2PMSG_60__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_61 -#define MP0_C2PMSG_61__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_62 -#define MP0_C2PMSG_62__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_63 -#define MP0_C2PMSG_63__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_64 -#define MP0_C2PMSG_64__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_65 -#define MP0_C2PMSG_65__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_66 -#define MP0_C2PMSG_66__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_67 -#define MP0_C2PMSG_67__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_68 -#define MP0_C2PMSG_68__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_69 -#define MP0_C2PMSG_69__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_70 -#define MP0_C2PMSG_70__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_71 -#define MP0_C2PMSG_71__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_72 -#define MP0_C2PMSG_72__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_73 -#define MP0_C2PMSG_73__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_74 -#define MP0_C2PMSG_74__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_75 -#define MP0_C2PMSG_75__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_76 -#define MP0_C2PMSG_76__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_77 -#define MP0_C2PMSG_77__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_78 -#define MP0_C2PMSG_78__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_79 -#define MP0_C2PMSG_79__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_80 -#define MP0_C2PMSG_80__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_81 -#define MP0_C2PMSG_81__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_82 -#define MP0_C2PMSG_82__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_83 -#define MP0_C2PMSG_83__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_84 -#define MP0_C2PMSG_84__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_85 -#define MP0_C2PMSG_85__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_86 -#define MP0_C2PMSG_86__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_87 -#define MP0_C2PMSG_87__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_88 -#define MP0_C2PMSG_88__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_89 -#define MP0_C2PMSG_89__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_90 -#define MP0_C2PMSG_90__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_91 -#define MP0_C2PMSG_91__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_92 -#define MP0_C2PMSG_92__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_93 -#define MP0_C2PMSG_93__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_94 -#define MP0_C2PMSG_94__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_95 -#define MP0_C2PMSG_95__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_96 -#define MP0_C2PMSG_96__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_97 -#define MP0_C2PMSG_97__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_98 -#define MP0_C2PMSG_98__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_99 -#define MP0_C2PMSG_99__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_100 -#define MP0_C2PMSG_100__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_101 -#define MP0_C2PMSG_101__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_102 -#define MP0_C2PMSG_102__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_103 -#define MP0_C2PMSG_103__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL -//MP0_ACTIVE_FCN_ID -#define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//MP0_IH_CREDIT -#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10 -#define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L -//MP0_IH_SW_INT -#define MP0_IH_SW_INT__ID__SHIFT 0x0 -#define MP0_IH_SW_INT__VALID__SHIFT 0x8 -#define MP0_IH_SW_INT__ID_MASK 0x000000FFL -#define MP0_IH_SW_INT__VALID_MASK 0x00000100L -//MP0_IH_SW_INT_CTRL -#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 -#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 -#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L -#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L - - -//CGTT_DRM_CLK_CTRL0 -#define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 -#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_DRM_CLK_CTRL0__DIV_ID__SHIFT 0xc -#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0__SHIFT 0x15 -#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG__SHIFT 0x16 -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL -#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_DRM_CLK_CTRL0__DIV_ID_MASK 0x00007000L -#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0_MASK 0x00200000L -#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG_MASK 0x00400000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L -//DRM_LIGHT_SLEEP_CTRL -#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0 -#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK 0x00000001L - - -// addressBlock: mp_SmuMp1Pub_CruDec -//MP1_SMN_PUB_CTRL -#define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0 -#define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L -//MP1_FIRMWARE_FLAGS -#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 -#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 -#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L -#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL -//MP1_PUB_SCRATCH0 -#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0 -#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL -//MP1_PUB_SCRATCH1 -#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0 -#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL -//MP1_PUB_SCRATCH2 -#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0 -#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL -//MP1_PUB_SCRATCH3 -#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0 -#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL -//MP1_C2PMSG_0 -#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_1 -#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_2 -#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_3 -#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_4 -#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_5 -#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_6 -#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_7 -#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_8 -#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_9 -#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_10 -#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_11 -#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_12 -#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_13 -#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_14 -#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_15 -#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_16 -#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_17 -#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_18 -#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_19 -#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_20 -#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_21 -#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_22 -#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_23 -#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_24 -#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_25 -#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_26 -#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_27 -#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_28 -#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_29 -#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_30 -#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_31 -#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2CMSG_0 -#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 -#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2CMSG_1 -#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 -#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2CMSG_2 -#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 -#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2CMSG_3 -#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 -#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2CMSG_INTEN -#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 -#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL -//MP1_P2CMSG_INTSTS -#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 -#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 -#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 -#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 -#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L -#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L -#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L -#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L -//MP1_P2SMSG_0 -#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0 -#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2SMSG_1 -#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0 -#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2SMSG_2 -#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0 -#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2SMSG_3 -#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0 -#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2SMSG_INTSTS -#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 -#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 -#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 -#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 -#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L -#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L -#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L -#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L -//MP1_S2PMSG_0 -#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0 -#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP1_ACP2MP_RESP -#define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_DC2MP_RESP -#define MP1_DC2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_UVD2MP_RESP -#define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_VCE2MP_RESP -#define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_RLC2MP_RESP -#define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_32 -#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_33 -#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_34 -#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_35 -#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_36 -#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_37 -#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_38 -#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_39 -#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_40 -#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_41 -#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_42 -#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_43 -#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_44 -#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_45 -#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_46 -#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_47 -#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_48 -#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_49 -#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_50 -#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_51 -#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_52 -#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_53 -#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_54 -#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_55 -#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_56 -#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_57 -#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_58 -#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_59 -#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_60 -#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_61 -#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_62 -#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_63 -#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_64 -#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_65 -#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_66 -#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_67 -#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_68 -#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_69 -#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_70 -#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_71 -#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_72 -#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_73 -#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_74 -#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_75 -#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_76 -#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_77 -#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_78 -#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_79 -#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_80 -#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_81 -#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_82 -#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_83 -#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_84 -#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_85 -#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_86 -#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_87 -#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_88 -#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_89 -#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_90 -#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_91 -#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_92 -#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_93 -#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_94 -#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_95 -#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_96 -#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_97 -#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_98 -#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_99 -#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_100 -#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_101 -#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_102 -#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_103 -#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL -//MP1_ACTIVE_FCN_ID -#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//MP1_IH_CREDIT -#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 -#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L -//MP1_IH_SW_INT -#define MP1_IH_SW_INT__ID__SHIFT 0x0 -#define MP1_IH_SW_INT__VALID__SHIFT 0x8 -#define MP1_IH_SW_INT__ID_MASK 0x000000FFL -#define MP1_IH_SW_INT__VALID_MASK 0x00000100L -//MP1_IH_SW_INT_CTRL -#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 -#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 -#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L -#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L -//MP1_FPS_CNT -#define MP1_FPS_CNT__COUNT__SHIFT 0x0 -#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL -//MP1_PUB_CTRL -#define MP1_PUB_CTRL__RESET__SHIFT 0x0 -#define MP1_PUB_CTRL__RESET_MASK 0x00000001L -//MP1_EXT_SCRATCH0 -#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH1 -#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH2 -#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH3 -#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH4 -#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH5 -#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH6 -#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH7 -#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL - - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h index 8c55eaa3c32b..2573f95fd39f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h @@ -28,9 +28,8 @@ #include "asic_reg/vega10/THM/thm_9_0_offset.h" #include "asic_reg/vega10/THM/thm_9_0_sh_mask.h" -#include "asic_reg/vega10/MP/mp_9_0_default.h" -#include "asic_reg/vega10/MP/mp_9_0_offset.h" -#include "asic_reg/vega10/MP/mp_9_0_sh_mask.h" +#include "asic_reg/mp/mp_9_0_offset.h" +#include "asic_reg/mp/mp_9_0_sh_mask.h" #include "asic_reg/vega10/GC/gc_9_0_default.h" #include "asic_reg/vega10/GC/gc_9_0_offset.h" -- GitLab From 6ce682251dd7dc4dab6813b032622f8381208e42 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 16 Nov 2017 17:50:10 +0800 Subject: [PATCH 0927/2547] drm/amd/include:cleanup vega10 athub header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/vega10/ATHUB folder,remove unused files. Signed-off-by: Feifei Xu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 5 +- .../include/asic_reg/athub/athub_1_0_offset.h | 453 ++++ .../asic_reg/athub/athub_1_0_sh_mask.h | 2045 +++++++++++++++++ .../asic_reg/vega10/ATHUB/athub_1_0_default.h | 241 -- .../asic_reg/vega10/ATHUB/athub_1_0_offset.h | 453 ---- .../asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h | 2045 ----------------- 7 files changed, 2501 insertions(+), 2743 deletions(-) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_sh_mask.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index f5642b27ace0..9b6532a1622b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -33,7 +33,7 @@ #include "vega10/DC/dce_12_0_sh_mask.h" #include "vega10/vega10_enum.h" #include "vega10/MMHUB/mmhub_1_0_offset.h" -#include "vega10/ATHUB/athub_1_0_offset.h" +#include "athub/athub_1_0_offset.h" #include "soc15_common.h" #include "vega10/UMC/umc_6_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index cc21c4bdec27..04e9527f5bce 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -27,9 +27,8 @@ #include "vega10/MMHUB/mmhub_1_0_offset.h" #include "vega10/MMHUB/mmhub_1_0_sh_mask.h" #include "vega10/MMHUB/mmhub_1_0_default.h" -#include "vega10/ATHUB/athub_1_0_offset.h" -#include "vega10/ATHUB/athub_1_0_sh_mask.h" -#include "vega10/ATHUB/athub_1_0_default.h" +#include "athub/athub_1_0_offset.h" +#include "athub/athub_1_0_sh_mask.h" #include "vega10/vega10_enum.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h new file mode 100644 index 000000000000..b1e878ecf9bf --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h @@ -0,0 +1,453 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _athub_1_0_OFFSET_HEADER +#define _athub_1_0_OFFSET_HEADER + + + +// addressBlock: athub_atsdec +// base address: 0x3080 +#define mmATC_ATS_CNTL 0x0000 +#define mmATC_ATS_CNTL_BASE_IDX 0 +#define mmATC_ATS_STATUS 0x0003 +#define mmATC_ATS_STATUS_BASE_IDX 0 +#define mmATC_ATS_FAULT_CNTL 0x0004 +#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0 +#define mmATC_ATS_FAULT_STATUS_INFO 0x0005 +#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0 +#define mmATC_ATS_FAULT_STATUS_ADDR 0x0006 +#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0 +#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007 +#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0 +#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008 +#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0 +#define mmATC_ATS_FAULT_STATUS_INFO2 0x0009 +#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0 +#define mmATHUB_MISC_CNTL 0x000a +#define mmATHUB_MISC_CNTL_BASE_IDX 0 +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0 +#define mmATC_VMID0_PASID_MAPPING 0x000c +#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID1_PASID_MAPPING 0x000d +#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID2_PASID_MAPPING 0x000e +#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID3_PASID_MAPPING 0x000f +#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID4_PASID_MAPPING 0x0010 +#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID5_PASID_MAPPING 0x0011 +#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID6_PASID_MAPPING 0x0012 +#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID7_PASID_MAPPING 0x0013 +#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID8_PASID_MAPPING 0x0014 +#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID9_PASID_MAPPING 0x0015 +#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID10_PASID_MAPPING 0x0016 +#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID11_PASID_MAPPING 0x0017 +#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID12_PASID_MAPPING 0x0018 +#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID13_PASID_MAPPING 0x0019 +#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID14_PASID_MAPPING 0x001a +#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID15_PASID_MAPPING 0x001b +#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0 +#define mmATC_ATS_VMID_STATUS 0x001c +#define mmATC_ATS_VMID_STATUS_BASE_IDX 0 +#define mmATC_ATS_GFX_ATCL2_STATUS 0x001d +#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0 +#define mmATC_PERFCOUNTER0_CFG 0x001e +#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmATC_PERFCOUNTER1_CFG 0x001f +#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmATC_PERFCOUNTER2_CFG 0x0020 +#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0 +#define mmATC_PERFCOUNTER3_CFG 0x0021 +#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0 +#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022 +#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define mmATC_PERFCOUNTER_LO 0x0023 +#define mmATC_PERFCOUNTER_LO_BASE_IDX 0 +#define mmATC_PERFCOUNTER_HI 0x0024 +#define mmATC_PERFCOUNTER_HI_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL 0x0025 +#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0 +#define mmATHUB_PCIE_PASID_CNTL 0x0026 +#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0 +#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027 +#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0 +#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028 +#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0 +#define mmATHUB_COMMAND 0x0029 +#define mmATHUB_COMMAND_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a +#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b +#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c +#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d +#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e +#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f +#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030 +#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031 +#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032 +#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033 +#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034 +#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035 +#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036 +#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037 +#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038 +#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039 +#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 +#define mmATHUB_MEM_POWER_LS 0x003a +#define mmATHUB_MEM_POWER_LS_BASE_IDX 0 +#define mmATS_IH_CREDIT 0x003b +#define mmATS_IH_CREDIT_BASE_IDX 0 +#define mmATHUB_IH_CREDIT 0x003c +#define mmATHUB_IH_CREDIT_BASE_IDX 0 +#define mmATC_VMID16_PASID_MAPPING 0x003d +#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID17_PASID_MAPPING 0x003e +#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID18_PASID_MAPPING 0x003f +#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID19_PASID_MAPPING 0x0040 +#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID20_PASID_MAPPING 0x0041 +#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID21_PASID_MAPPING 0x0042 +#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID22_PASID_MAPPING 0x0043 +#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID23_PASID_MAPPING 0x0044 +#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID24_PASID_MAPPING 0x0045 +#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID25_PASID_MAPPING 0x0046 +#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID26_PASID_MAPPING 0x0047 +#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID27_PASID_MAPPING 0x0048 +#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID28_PASID_MAPPING 0x0049 +#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID29_PASID_MAPPING 0x004a +#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID30_PASID_MAPPING 0x004b +#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID31_PASID_MAPPING 0x004c +#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0 +#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x004d +#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0 +#define mmATHUB_SHARED_VIRT_RESET_REQ 0x004e +#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0 +#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x004f +#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmATC_ATS_SDPPORT_CNTL 0x0050 +#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0 +#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0052 +#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0 +#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0053 +#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0 + + +// addressBlock: athub_xpbdec +// base address: 0x31f0 +#define mmXPB_RTR_SRC_APRTR0 0x005c +#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR1 0x005d +#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR2 0x005e +#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR3 0x005f +#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR4 0x0060 +#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR5 0x0061 +#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR6 0x0062 +#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR7 0x0063 +#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR8 0x0064 +#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR9 0x0065 +#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0 +#define mmXPB_XDMA_RTR_SRC_APRTR0 0x0066 +#define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0 +#define mmXPB_XDMA_RTR_SRC_APRTR1 0x0067 +#define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0 +#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0068 +#define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0 +#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0069 +#define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP0 0x006a +#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP1 0x006b +#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP2 0x006c +#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP3 0x006d +#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP4 0x006e +#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP5 0x006f +#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP6 0x0070 +#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP7 0x0071 +#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP8 0x0072 +#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP9 0x0073 +#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0 +#define mmXPB_XDMA_RTR_DEST_MAP0 0x0074 +#define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0 +#define mmXPB_XDMA_RTR_DEST_MAP1 0x0075 +#define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0 +#define mmXPB_XDMA_RTR_DEST_MAP2 0x0076 +#define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0 +#define mmXPB_XDMA_RTR_DEST_MAP3 0x0077 +#define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0 +#define mmXPB_CLG_CFG0 0x0078 +#define mmXPB_CLG_CFG0_BASE_IDX 0 +#define mmXPB_CLG_CFG1 0x0079 +#define mmXPB_CLG_CFG1_BASE_IDX 0 +#define mmXPB_CLG_CFG2 0x007a +#define mmXPB_CLG_CFG2_BASE_IDX 0 +#define mmXPB_CLG_CFG3 0x007b +#define mmXPB_CLG_CFG3_BASE_IDX 0 +#define mmXPB_CLG_CFG4 0x007c +#define mmXPB_CLG_CFG4_BASE_IDX 0 +#define mmXPB_CLG_CFG5 0x007d +#define mmXPB_CLG_CFG5_BASE_IDX 0 +#define mmXPB_CLG_CFG6 0x007e +#define mmXPB_CLG_CFG6_BASE_IDX 0 +#define mmXPB_CLG_CFG7 0x007f +#define mmXPB_CLG_CFG7_BASE_IDX 0 +#define mmXPB_CLG_EXTRA 0x0080 +#define mmXPB_CLG_EXTRA_BASE_IDX 0 +#define mmXPB_CLG_EXTRA_MSK 0x0081 +#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0 +#define mmXPB_LB_ADDR 0x0082 +#define mmXPB_LB_ADDR_BASE_IDX 0 +#define mmXPB_WCB_STS 0x0083 +#define mmXPB_WCB_STS_BASE_IDX 0 +#define mmXPB_HST_CFG 0x0084 +#define mmXPB_HST_CFG_BASE_IDX 0 +#define mmXPB_P2P_BAR_CFG 0x0085 +#define mmXPB_P2P_BAR_CFG_BASE_IDX 0 +#define mmXPB_P2P_BAR0 0x0086 +#define mmXPB_P2P_BAR0_BASE_IDX 0 +#define mmXPB_P2P_BAR1 0x0087 +#define mmXPB_P2P_BAR1_BASE_IDX 0 +#define mmXPB_P2P_BAR2 0x0088 +#define mmXPB_P2P_BAR2_BASE_IDX 0 +#define mmXPB_P2P_BAR3 0x0089 +#define mmXPB_P2P_BAR3_BASE_IDX 0 +#define mmXPB_P2P_BAR4 0x008a +#define mmXPB_P2P_BAR4_BASE_IDX 0 +#define mmXPB_P2P_BAR5 0x008b +#define mmXPB_P2P_BAR5_BASE_IDX 0 +#define mmXPB_P2P_BAR6 0x008c +#define mmXPB_P2P_BAR6_BASE_IDX 0 +#define mmXPB_P2P_BAR7 0x008d +#define mmXPB_P2P_BAR7_BASE_IDX 0 +#define mmXPB_P2P_BAR_SETUP 0x008e +#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0 +#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0090 +#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0 +#define mmXPB_P2P_BAR_DELTA_BELOW 0x0091 +#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR0 0x0092 +#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR1 0x0093 +#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR2 0x0094 +#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR3 0x0095 +#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR4 0x0096 +#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR5 0x0097 +#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR6 0x0098 +#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR7 0x0099 +#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR8 0x009a +#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR9 0x009b +#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0 +#define mmXPB_XDMA_PEER_SYS_BAR0 0x009c +#define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0 +#define mmXPB_XDMA_PEER_SYS_BAR1 0x009d +#define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0 +#define mmXPB_XDMA_PEER_SYS_BAR2 0x009e +#define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0 +#define mmXPB_XDMA_PEER_SYS_BAR3 0x009f +#define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0 +#define mmXPB_CLK_GAT 0x00a0 +#define mmXPB_CLK_GAT_BASE_IDX 0 +#define mmXPB_INTF_CFG 0x00a1 +#define mmXPB_INTF_CFG_BASE_IDX 0 +#define mmXPB_INTF_STS 0x00a2 +#define mmXPB_INTF_STS_BASE_IDX 0 +#define mmXPB_PIPE_STS 0x00a3 +#define mmXPB_PIPE_STS_BASE_IDX 0 +#define mmXPB_SUB_CTRL 0x00a4 +#define mmXPB_SUB_CTRL_BASE_IDX 0 +#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00a5 +#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0 +#define mmXPB_PERF_KNOBS 0x00a6 +#define mmXPB_PERF_KNOBS_BASE_IDX 0 +#define mmXPB_STICKY 0x00a7 +#define mmXPB_STICKY_BASE_IDX 0 +#define mmXPB_STICKY_W1C 0x00a8 +#define mmXPB_STICKY_W1C_BASE_IDX 0 +#define mmXPB_MISC_CFG 0x00a9 +#define mmXPB_MISC_CFG_BASE_IDX 0 +#define mmXPB_INTF_CFG2 0x00aa +#define mmXPB_INTF_CFG2_BASE_IDX 0 +#define mmXPB_CLG_EXTRA_RD 0x00ab +#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0 +#define mmXPB_CLG_EXTRA_MSK_RD 0x00ac +#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0 +#define mmXPB_CLG_GFX_MATCH 0x00ad +#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0 +#define mmXPB_CLG_GFX_MATCH_MSK 0x00ae +#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0 +#define mmXPB_CLG_MM_MATCH 0x00af +#define mmXPB_CLG_MM_MATCH_BASE_IDX 0 +#define mmXPB_CLG_MM_MATCH_MSK 0x00b0 +#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00b1 +#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00b2 +#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00b3 +#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00b4 +#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00b5 +#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00b6 +#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00b7 +#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00b8 +#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0 +#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00b9 +#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0 +#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00ba +#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0 +#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00bb +#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0 +#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00bc +#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0 + + +// addressBlock: athub_rpbdec +// base address: 0x33b0 +#define mmRPB_PASSPW_CONF 0x00cc +#define mmRPB_PASSPW_CONF_BASE_IDX 0 +#define mmRPB_BLOCKLEVEL_CONF 0x00cd +#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0 +#define mmRPB_TAG_CONF 0x00cf +#define mmRPB_TAG_CONF_BASE_IDX 0 +#define mmRPB_EFF_CNTL 0x00d1 +#define mmRPB_EFF_CNTL_BASE_IDX 0 +#define mmRPB_ARB_CNTL 0x00d2 +#define mmRPB_ARB_CNTL_BASE_IDX 0 +#define mmRPB_ARB_CNTL2 0x00d3 +#define mmRPB_ARB_CNTL2_BASE_IDX 0 +#define mmRPB_BIF_CNTL 0x00d4 +#define mmRPB_BIF_CNTL_BASE_IDX 0 +#define mmRPB_WR_SWITCH_CNTL 0x00d5 +#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0 +#define mmRPB_RD_SWITCH_CNTL 0x00d7 +#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0 +#define mmRPB_CID_QUEUE_WR 0x00d8 +#define mmRPB_CID_QUEUE_WR_BASE_IDX 0 +#define mmRPB_CID_QUEUE_RD 0x00d9 +#define mmRPB_CID_QUEUE_RD_BASE_IDX 0 +#define mmRPB_CID_QUEUE_EX 0x00dc +#define mmRPB_CID_QUEUE_EX_BASE_IDX 0 +#define mmRPB_CID_QUEUE_EX_DATA 0x00dd +#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0 +#define mmRPB_SWITCH_CNTL2 0x00de +#define mmRPB_SWITCH_CNTL2_BASE_IDX 0 +#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00df +#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0 +#define mmRPB_VC_SWITCH_RDWR 0x00e0 +#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0 +#define mmRPB_PERFCOUNTER_LO 0x00e1 +#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0 +#define mmRPB_PERFCOUNTER_HI 0x00e2 +#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0 +#define mmRPB_PERFCOUNTER0_CFG 0x00e3 +#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmRPB_PERFCOUNTER1_CFG 0x00e4 +#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmRPB_PERFCOUNTER2_CFG 0x00e5 +#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0 +#define mmRPB_PERFCOUNTER3_CFG 0x00e6 +#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0 +#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00e7 +#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define mmRPB_RD_QUEUE_CNTL 0x00e9 +#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0 +#define mmRPB_RD_QUEUE_CNTL2 0x00ea +#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0 +#define mmRPB_WR_QUEUE_CNTL 0x00eb +#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0 +#define mmRPB_WR_QUEUE_CNTL2 0x00ec +#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0 +#define mmRPB_EA_QUEUE_WR 0x00ed +#define mmRPB_EA_QUEUE_WR_BASE_IDX 0 +#define mmRPB_ATS_CNTL 0x00ee +#define mmRPB_ATS_CNTL_BASE_IDX 0 +#define mmRPB_ATS_CNTL2 0x00ef +#define mmRPB_ATS_CNTL2_BASE_IDX 0 +#define mmRPB_SDPPORT_CNTL 0x00f0 +#define mmRPB_SDPPORT_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_sh_mask.h new file mode 100644 index 000000000000..2968c6e2f7b9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_sh_mask.h @@ -0,0 +1,2045 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _athub_1_0_SH_MASK_HEADER +#define _athub_1_0_SH_MASK_HEADER + + +// addressBlock: athub_atsdec +//ATC_ATS_CNTL +#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 +#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 +#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 +#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 +#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14 +#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15 +#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16 +#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L +#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L +#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L +#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L +#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L +#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L +#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L +//ATC_ATS_STATUS +#define ATC_ATS_STATUS__BUSY__SHIFT 0x0 +#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 +#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3 +#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6 +#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L +#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L +#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L +#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L +#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L +//ATC_ATS_FAULT_CNTL +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L +//ATC_ATS_FAULT_STATUS_INFO +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL +#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L +#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L +//ATC_ATS_FAULT_STATUS_ADDR +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL +//ATC_ATS_DEFAULT_PAGE_LOW +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL +//ATC_TRANS_FAULT_RSPCNTRL +#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa +#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb +#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc +#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd +#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe +#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf +#define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a +#define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b +#define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c +#define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d +#define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e +#define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f +#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L +//ATC_ATS_FAULT_STATUS_INFO2 +#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 +#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9 +#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L +#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL +#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L +//ATHUB_MISC_CNTL +#define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6 +#define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12 +#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13 +#define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14 +#define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15 +#define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b +#define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c +#define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L +#define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L +#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L +#define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L +#define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L +#define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L +#define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L +//ATC_VMID_PASID_MAPPING_UPDATE_STATUS +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L +//ATC_VMID0_PASID_MAPPING +#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID1_PASID_MAPPING +#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID2_PASID_MAPPING +#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID3_PASID_MAPPING +#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID4_PASID_MAPPING +#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID5_PASID_MAPPING +#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID6_PASID_MAPPING +#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID7_PASID_MAPPING +#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID8_PASID_MAPPING +#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID9_PASID_MAPPING +#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID10_PASID_MAPPING +#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID11_PASID_MAPPING +#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID12_PASID_MAPPING +#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID13_PASID_MAPPING +#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID14_PASID_MAPPING +#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID15_PASID_MAPPING +#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_ATS_VMID_STATUS +#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 +#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 +#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 +#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 +#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 +#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 +#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 +#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 +#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 +#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 +#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa +#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb +#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc +#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd +#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe +#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf +#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10 +#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11 +#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12 +#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13 +#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14 +#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15 +#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16 +#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17 +#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18 +#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19 +#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a +#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b +#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c +#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d +#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e +#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f +#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L +#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L +#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L +#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L +#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L +#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L +#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L +#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L +#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L +#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L +#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L +#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L +#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L +#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L +#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L +#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L +#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L +#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L +#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L +#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L +#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L +#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L +#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L +#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L +#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L +#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L +#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L +#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L +#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L +#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L +#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L +#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L +//ATC_ATS_GFX_ATCL2_STATUS +#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 +#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L +//ATC_PERFCOUNTER0_CFG +#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//ATC_PERFCOUNTER1_CFG +#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//ATC_PERFCOUNTER2_CFG +#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//ATC_PERFCOUNTER3_CFG +#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//ATC_PERFCOUNTER_RSLT_CNTL +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//ATC_PERFCOUNTER_LO +#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//ATC_PERFCOUNTER_HI +#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//ATHUB_PCIE_ATS_CNTL +#define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_PASID_CNTL +#define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10 +#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11 +#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12 +#define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L +#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L +#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L +//ATHUB_PCIE_PAGE_REQ_CNTL +#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L +#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L +//ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//ATHUB_COMMAND +#define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L +//ATHUB_PCIE_ATS_CNTL_VF_0 +#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_1 +#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_2 +#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_3 +#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_4 +#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_5 +#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_6 +#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_7 +#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_8 +#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_9 +#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_10 +#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_11 +#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_12 +#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_13 +#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_14 +#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_15 +#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L +//ATHUB_MEM_POWER_LS +#define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//ATS_IH_CREDIT +#define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 +#define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L +//ATHUB_IH_CREDIT +#define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 +#define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L +//ATC_VMID16_PASID_MAPPING +#define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID17_PASID_MAPPING +#define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID18_PASID_MAPPING +#define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID19_PASID_MAPPING +#define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID20_PASID_MAPPING +#define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID21_PASID_MAPPING +#define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID22_PASID_MAPPING +#define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID23_PASID_MAPPING +#define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID24_PASID_MAPPING +#define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID25_PASID_MAPPING +#define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID26_PASID_MAPPING +#define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID27_PASID_MAPPING +#define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID28_PASID_MAPPING +#define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID29_PASID_MAPPING +#define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID30_PASID_MAPPING +#define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID31_PASID_MAPPING +#define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_ATS_MMHUB_ATCL2_STATUS +#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 +#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L +//ATHUB_SHARED_VIRT_RESET_REQ +#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L +//ATHUB_SHARED_ACTIVE_FCN_ID +#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//ATC_ATS_SDPPORT_CNTL +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0 +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1 +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe +#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19 +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L +//ATC_ATS_VMID_SNAPSHOT_GFX_STAT +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L +//ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L + + +// addressBlock: athub_xpbdec +//XPB_RTR_SRC_APRTR0 +#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR1 +#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR2 +#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR3 +#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR4 +#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR5 +#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR6 +#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR7 +#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR8 +#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR9 +#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_XDMA_RTR_SRC_APRTR0 +#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_XDMA_RTR_SRC_APRTR1 +#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_XDMA_RTR_SRC_APRTR2 +#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_XDMA_RTR_SRC_APRTR3 +#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_DEST_MAP0 +#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP1 +#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP2 +#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP3 +#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP4 +#define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP5 +#define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP6 +#define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP7 +#define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP8 +#define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP9 +#define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L +//XPB_XDMA_RTR_DEST_MAP0 +#define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L +#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L +#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L +//XPB_XDMA_RTR_DEST_MAP1 +#define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L +#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L +#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L +//XPB_XDMA_RTR_DEST_MAP2 +#define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L +#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L +#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L +//XPB_XDMA_RTR_DEST_MAP3 +#define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L +#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L +#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L +//XPB_CLG_CFG0 +#define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG1 +#define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG2 +#define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG3 +#define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG4 +#define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG5 +#define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG6 +#define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG7 +#define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_EXTRA +#define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0 +#define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6 +#define XPB_CLG_EXTRA__VLD0__SHIFT 0xb +#define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc +#define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf +#define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15 +#define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a +#define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b +#define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL +#define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L +#define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L +#define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L +#define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L +#define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L +#define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L +#define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L +//XPB_CLG_EXTRA_MSK +#define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 +#define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6 +#define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb +#define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11 +#define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL +#define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L +#define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L +#define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L +//XPB_LB_ADDR +#define XPB_LB_ADDR__CMP0__SHIFT 0x0 +#define XPB_LB_ADDR__MASK0__SHIFT 0xa +#define XPB_LB_ADDR__CMP1__SHIFT 0x14 +#define XPB_LB_ADDR__MASK1__SHIFT 0x1a +#define XPB_LB_ADDR__CMP0_MASK 0x000003FFL +#define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L +#define XPB_LB_ADDR__CMP1_MASK 0x03F00000L +#define XPB_LB_ADDR__MASK1_MASK 0xFC000000L +//XPB_WCB_STS +#define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 +#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 +#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 +#define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL +#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L +#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L +//XPB_HST_CFG +#define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 +#define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L +//XPB_P2P_BAR_CFG +#define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 +#define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 +#define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 +#define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 +#define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 +#define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 +#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa +#define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb +#define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc +#define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL +#define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L +#define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L +#define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L +#define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L +#define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L +#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L +#define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L +#define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L +//XPB_P2P_BAR0 +#define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR0__VALID__SHIFT 0xc +#define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR0__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR0__VALID_MASK 0x00001000L +#define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR1 +#define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR1__VALID__SHIFT 0xc +#define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR1__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR1__VALID_MASK 0x00001000L +#define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR2 +#define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR2__VALID__SHIFT 0xc +#define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR2__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR2__VALID_MASK 0x00001000L +#define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR3 +#define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR3__VALID__SHIFT 0xc +#define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR3__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR3__VALID_MASK 0x00001000L +#define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR4 +#define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR4__VALID__SHIFT 0xc +#define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR4__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR4__VALID_MASK 0x00001000L +#define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR5 +#define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR5__VALID__SHIFT 0xc +#define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR5__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR5__VALID_MASK 0x00001000L +#define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR6 +#define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR6__VALID__SHIFT 0xc +#define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR6__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR6__VALID_MASK 0x00001000L +#define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR7 +#define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR7__VALID__SHIFT 0xc +#define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR7__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR7__VALID_MASK 0x00001000L +#define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR_SETUP +#define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 +#define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc +#define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL +#define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L +#define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR_DELTA_ABOVE +#define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 +#define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 +#define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL +#define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L +//XPB_P2P_BAR_DELTA_BELOW +#define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 +#define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 +#define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL +#define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L +//XPB_PEER_SYS_BAR0 +#define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR1 +#define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR2 +#define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR3 +#define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR4 +#define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR5 +#define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR6 +#define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR7 +#define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR8 +#define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR9 +#define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL +//XPB_XDMA_PEER_SYS_BAR0 +#define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1 +#define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L +#define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL +//XPB_XDMA_PEER_SYS_BAR1 +#define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1 +#define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L +#define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL +//XPB_XDMA_PEER_SYS_BAR2 +#define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1 +#define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L +#define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL +//XPB_XDMA_PEER_SYS_BAR3 +#define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1 +#define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L +#define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL +//XPB_CLK_GAT +#define XPB_CLK_GAT__ONDLY__SHIFT 0x0 +#define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 +#define XPB_CLK_GAT__RDYDLY__SHIFT 0xc +#define XPB_CLK_GAT__ENABLE__SHIFT 0x12 +#define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 +#define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL +#define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L +#define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L +#define XPB_CLK_GAT__ENABLE_MASK 0x00040000L +#define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L +//XPB_INTF_CFG +#define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 +#define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 +#define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 +#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 +#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 +#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 +#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a +#define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b +#define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d +#define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e +#define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f +#define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL +#define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L +#define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L +#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L +#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L +#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L +#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L +#define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L +#define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L +#define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L +#define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L +//XPB_INTF_STS +#define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 +#define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 +#define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf +#define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 +#define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 +#define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 +#define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 +#define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL +#define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L +#define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L +#define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L +#define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L +#define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L +#define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L +//XPB_PIPE_STS +#define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 +#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 +#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 +#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf +#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 +#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 +#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 +#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 +#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 +#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 +#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 +#define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 +#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 +#define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L +#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL +#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L +#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L +#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L +#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L +#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L +#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L +#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L +#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L +#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L +#define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L +#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L +//XPB_SUB_CTRL +#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 +#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 +#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 +#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 +#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 +#define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 +#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 +#define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 +#define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 +#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 +#define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa +#define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb +#define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc +#define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd +#define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe +#define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf +#define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 +#define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 +#define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 +#define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 +#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L +#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L +#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L +#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L +#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L +#define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L +#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L +#define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L +#define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L +#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L +#define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L +#define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L +#define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L +#define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L +#define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L +#define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L +#define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L +#define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L +#define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L +#define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L +//XPB_MAP_INVERT_FLUSH_NUM_LSB +#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 +#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL +//XPB_PERF_KNOBS +#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 +#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 +#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc +#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL +#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L +#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L +//XPB_STICKY +#define XPB_STICKY__BITS__SHIFT 0x0 +#define XPB_STICKY__BITS_MASK 0xFFFFFFFFL +//XPB_STICKY_W1C +#define XPB_STICKY_W1C__BITS__SHIFT 0x0 +#define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL +//XPB_MISC_CFG +#define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 +#define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 +#define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 +#define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 +#define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f +#define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL +#define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L +#define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L +#define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L +#define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L +//XPB_INTF_CFG2 +#define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 +#define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL +//XPB_CLG_EXTRA_RD +#define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 +#define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 +#define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb +#define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc +#define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf +#define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 +#define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a +#define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b +#define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL +#define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L +#define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L +#define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L +#define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L +#define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L +#define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L +#define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L +//XPB_CLG_EXTRA_MSK_RD +#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 +#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 +#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb +#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 +#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL +#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L +#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L +#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L +//XPB_CLG_GFX_MATCH +#define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 +#define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6 +#define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc +#define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12 +#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18 +#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19 +#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a +#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b +#define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL +#define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L +#define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L +#define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L +#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L +#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L +#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L +#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L +//XPB_CLG_GFX_MATCH_MSK +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L +//XPB_CLG_MM_MATCH +#define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 +#define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6 +#define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0xc +#define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x12 +#define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0x18 +#define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0x19 +#define XPB_CLG_MM_MATCH__FARBIRC2_VLD__SHIFT 0x1a +#define XPB_CLG_MM_MATCH__FARBIRC3_VLD__SHIFT 0x1b +#define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL +#define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L +#define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x0003F000L +#define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0x00FC0000L +#define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x01000000L +#define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x02000000L +#define XPB_CLG_MM_MATCH__FARBIRC2_VLD_MASK 0x04000000L +#define XPB_CLG_MM_MATCH__FARBIRC3_VLD_MASK 0x08000000L +//XPB_CLG_MM_MATCH_MSK +#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 +#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 +#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc +#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 +#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL +#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L +#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L +#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L +//XPB_CLG_GFX_UNITID_MAPPING0 +#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING1 +#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING2 +#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING3 +#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING4 +#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING5 +#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING6 +#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING7 +#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_MM_UNITID_MAPPING0 +#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_MM_UNITID_MAPPING1 +#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_MM_UNITID_MAPPING2 +#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_MM_UNITID_MAPPING3 +#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L + + +// addressBlock: athub_rpbdec +//RPB_PASSPW_CONF +#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 +#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 +#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2 +#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3 +#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4 +#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5 +#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6 +#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7 +#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8 +#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9 +#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa +#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb +#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc +#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd +#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe +#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf +#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10 +#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11 +#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L +#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L +#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L +#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L +#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L +#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L +#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L +#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L +#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L +#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L +#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L +#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L +#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L +#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L +#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L +#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L +#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L +#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L +//RPB_BLOCKLEVEL_CONF +#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 +#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2 +#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4 +#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6 +#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8 +#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa +#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc +#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe +#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf +#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 +#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11 +#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L +#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL +#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L +#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L +#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L +#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L +#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L +#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L +#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L +#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L +#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L +//RPB_TAG_CONF +#define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0 +#define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0x8 +#define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x10 +#define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000000FFL +#define RPB_TAG_CONF__RPB_IO_WR_MASK 0x0000FF00L +#define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x00FF0000L +//RPB_EFF_CNTL +#define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 +#define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 +#define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL +#define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L +//RPB_ARB_CNTL +#define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 +#define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 +#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 +#define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 +#define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 +#define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL +#define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L +#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L +#define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L +#define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L +//RPB_ARB_CNTL2 +#define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 +#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 +#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 +#define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL +#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L +#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L +//RPB_BIF_CNTL +#define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 +#define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 +#define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10 +#define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11 +#define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12 +#define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13 +#define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b +#define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c +#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d +#define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e +#define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL +#define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L +#define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L +#define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L +#define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L +#define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L +#define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L +#define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L +#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L +#define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L +//RPB_WR_SWITCH_CNTL +#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 +#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe +#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 +#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c +#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL +#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L +#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L +#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L +#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L +//RPB_RD_SWITCH_CNTL +#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 +#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe +#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 +#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c +#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL +#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L +#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L +#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L +#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L +//RPB_CID_QUEUE_WR +#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0 +#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5 +#define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb +#define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc +#define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf +#define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12 +#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL +#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L +#define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L +#define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L +#define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L +#define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L +//RPB_CID_QUEUE_RD +#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0 +#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5 +#define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb +#define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe +#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL +#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L +#define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L +#define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L +//RPB_CID_QUEUE_EX +#define RPB_CID_QUEUE_EX__START__SHIFT 0x0 +#define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 +#define RPB_CID_QUEUE_EX__START_MASK 0x00000001L +#define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL +//RPB_CID_QUEUE_EX_DATA +#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 +#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 +#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL +#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L +//RPB_SWITCH_CNTL2 +#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0 +#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7 +#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe +#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15 +#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL +#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L +#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L +#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L +//RPB_DEINTRLV_COMBINE_CNTL +#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 +#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 +#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 +#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL +#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L +#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L +//RPB_VC_SWITCH_RDWR +#define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 +#define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 +#define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa +#define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L +#define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL +#define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L +//RPB_PERFCOUNTER_LO +#define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//RPB_PERFCOUNTER_HI +#define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//RPB_PERFCOUNTER0_CFG +#define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//RPB_PERFCOUNTER1_CFG +#define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//RPB_PERFCOUNTER2_CFG +#define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//RPB_PERFCOUNTER3_CFG +#define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//RPB_PERFCOUNTER_RSLT_CNTL +#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//RPB_RD_QUEUE_CNTL +#define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 +#define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 +#define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 +#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 +#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 +#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 +#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa +#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 +#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 +#define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L +#define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L +#define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L +#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L +#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L +#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L +#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L +#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L +#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L +//RPB_RD_QUEUE_CNTL2 +#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 +#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 +#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb +#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 +#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL +#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L +#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L +#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L +//RPB_WR_QUEUE_CNTL +#define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 +#define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 +#define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 +#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 +#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 +#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 +#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa +#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 +#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 +#define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L +#define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L +#define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L +#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L +#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L +#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L +#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L +#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L +#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L +//RPB_WR_QUEUE_CNTL2 +#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 +#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 +#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb +#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 +#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL +#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L +#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L +#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L +//RPB_EA_QUEUE_WR +#define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0 +#define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5 +#define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8 +#define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb +#define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL +#define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L +#define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L +#define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L +//RPB_ATS_CNTL +#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 +#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 +#define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 +#define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 +#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf +#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 +#define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 +#define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19 +#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L +#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L +#define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL +#define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L +#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L +#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L +#define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L +#define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L +//RPB_ATS_CNTL2 +#define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0 +#define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6 +#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc +#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf +#define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12 +#define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL +#define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L +#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L +#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L +#define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L +//RPB_SDPPORT_CNTL +#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 +#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 +#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 +#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa +#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf +#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10 +#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14 +#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b +#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L +#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L +#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L +#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L +#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L +#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L +#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L +#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h deleted file mode 100644 index 1650dc369f7d..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _athub_1_0_DEFAULT_HEADER -#define _athub_1_0_DEFAULT_HEADER - - -// addressBlock: athub_atsdec -#define mmATC_ATS_CNTL_DEFAULT 0x009a0800 -#define mmATC_ATS_STATUS_DEFAULT 0x00000000 -#define mmATC_ATS_FAULT_CNTL_DEFAULT 0x000001ff -#define mmATC_ATS_FAULT_STATUS_INFO_DEFAULT 0x00000000 -#define mmATC_ATS_FAULT_STATUS_ADDR_DEFAULT 0x00000000 -#define mmATC_ATS_DEFAULT_PAGE_LOW_DEFAULT 0x00000000 -#define mmATC_TRANS_FAULT_RSPCNTRL_DEFAULT 0xffffffff -#define mmATC_ATS_FAULT_STATUS_INFO2_DEFAULT 0x00000000 -#define mmATHUB_MISC_CNTL_DEFAULT 0x00040200 -#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_DEFAULT 0x00000000 -#define mmATC_VMID0_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID1_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID2_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID3_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID4_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID5_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID6_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID7_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID8_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID9_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID10_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID11_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID12_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID13_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID14_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID15_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_ATS_VMID_STATUS_DEFAULT 0x00000000 -#define mmATC_ATS_GFX_ATCL2_STATUS_DEFAULT 0x00000000 -#define mmATC_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmATC_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmATC_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmATC_PERFCOUNTER3_CFG_DEFAULT 0x00000000 -#define mmATC_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmATC_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmATC_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_DEFAULT 0x00000000 -#define mmATHUB_PCIE_PASID_CNTL_DEFAULT 0x00000000 -#define mmATHUB_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 -#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 -#define mmATHUB_COMMAND_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 -#define mmATHUB_MEM_POWER_LS_DEFAULT 0x00000208 -#define mmATS_IH_CREDIT_DEFAULT 0x00150002 -#define mmATHUB_IH_CREDIT_DEFAULT 0x00020002 -#define mmATC_VMID16_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID17_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID18_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID19_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID20_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID21_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID22_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID23_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID24_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID25_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID26_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID27_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID28_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID29_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID30_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID31_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_ATS_MMHUB_ATCL2_STATUS_DEFAULT 0x00000000 -#define mmATHUB_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmATHUB_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmATC_ATS_SDPPORT_CNTL_DEFAULT 0x03ffa210 -#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_DEFAULT 0x00000000 -#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_DEFAULT 0x00000000 - - -// addressBlock: athub_xpbdec -#define mmXPB_RTR_SRC_APRTR0_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR1_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR2_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR3_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR4_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR5_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR6_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR7_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR8_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR9_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_SRC_APRTR0_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_SRC_APRTR1_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_SRC_APRTR2_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_SRC_APRTR3_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP0_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP1_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP2_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP3_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP4_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP5_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP6_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP7_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP8_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP9_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_DEST_MAP0_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_DEST_MAP1_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_DEST_MAP2_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_DEST_MAP3_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG0_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG1_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG2_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG3_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG4_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG5_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG6_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG7_DEFAULT 0x00000000 -#define mmXPB_CLG_EXTRA_DEFAULT 0x00000000 -#define mmXPB_CLG_EXTRA_MSK_DEFAULT 0x00000000 -#define mmXPB_LB_ADDR_DEFAULT 0x00000000 -#define mmXPB_WCB_STS_DEFAULT 0x00000000 -#define mmXPB_HST_CFG_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR_CFG_DEFAULT 0x0000000f -#define mmXPB_P2P_BAR0_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR1_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR2_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR3_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR4_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR5_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR6_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR7_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR_SETUP_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR_DELTA_ABOVE_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR_DELTA_BELOW_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR0_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR1_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR2_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR3_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR4_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR5_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR6_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR7_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR8_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR9_DEFAULT 0x00000000 -#define mmXPB_XDMA_PEER_SYS_BAR0_DEFAULT 0x00000000 -#define mmXPB_XDMA_PEER_SYS_BAR1_DEFAULT 0x00000000 -#define mmXPB_XDMA_PEER_SYS_BAR2_DEFAULT 0x00000000 -#define mmXPB_XDMA_PEER_SYS_BAR3_DEFAULT 0x00000000 -#define mmXPB_CLK_GAT_DEFAULT 0x00040400 -#define mmXPB_INTF_CFG_DEFAULT 0x000f1040 -#define mmXPB_INTF_STS_DEFAULT 0x00000000 -#define mmXPB_PIPE_STS_DEFAULT 0x00000000 -#define mmXPB_SUB_CTRL_DEFAULT 0x00000000 -#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_DEFAULT 0x00000000 -#define mmXPB_PERF_KNOBS_DEFAULT 0x00000000 -#define mmXPB_STICKY_DEFAULT 0x00000000 -#define mmXPB_STICKY_W1C_DEFAULT 0x00000000 -#define mmXPB_MISC_CFG_DEFAULT 0x4d585042 -#define mmXPB_INTF_CFG2_DEFAULT 0x00000040 -#define mmXPB_CLG_EXTRA_RD_DEFAULT 0x00000000 -#define mmXPB_CLG_EXTRA_MSK_RD_DEFAULT 0x00000000 -#define mmXPB_CLG_GFX_MATCH_DEFAULT 0x03000000 -#define mmXPB_CLG_GFX_MATCH_MSK_DEFAULT 0x00000000 -#define mmXPB_CLG_MM_MATCH_DEFAULT 0x03000000 -#define mmXPB_CLG_MM_MATCH_MSK_DEFAULT 0x00000000 -#define mmXPB_CLG_GFX_UNITID_MAPPING0_DEFAULT 0x00000000 -#define mmXPB_CLG_GFX_UNITID_MAPPING1_DEFAULT 0x00000040 -#define mmXPB_CLG_GFX_UNITID_MAPPING2_DEFAULT 0x00000080 -#define mmXPB_CLG_GFX_UNITID_MAPPING3_DEFAULT 0x000000c0 -#define mmXPB_CLG_GFX_UNITID_MAPPING4_DEFAULT 0x00000100 -#define mmXPB_CLG_GFX_UNITID_MAPPING5_DEFAULT 0x00000140 -#define mmXPB_CLG_GFX_UNITID_MAPPING6_DEFAULT 0x00000000 -#define mmXPB_CLG_GFX_UNITID_MAPPING7_DEFAULT 0x000001c0 -#define mmXPB_CLG_MM_UNITID_MAPPING0_DEFAULT 0x00000000 -#define mmXPB_CLG_MM_UNITID_MAPPING1_DEFAULT 0x00000040 -#define mmXPB_CLG_MM_UNITID_MAPPING2_DEFAULT 0x00000080 -#define mmXPB_CLG_MM_UNITID_MAPPING3_DEFAULT 0x000000c0 - - -// addressBlock: athub_rpbdec -#define mmRPB_PASSPW_CONF_DEFAULT 0x00000230 -#define mmRPB_BLOCKLEVEL_CONF_DEFAULT 0x000000f0 -#define mmRPB_TAG_CONF_DEFAULT 0x00204020 -#define mmRPB_EFF_CNTL_DEFAULT 0x00001010 -#define mmRPB_ARB_CNTL_DEFAULT 0x00040404 -#define mmRPB_ARB_CNTL2_DEFAULT 0x00040104 -#define mmRPB_BIF_CNTL_DEFAULT 0x01000404 -#define mmRPB_WR_SWITCH_CNTL_DEFAULT 0x02040810 -#define mmRPB_RD_SWITCH_CNTL_DEFAULT 0x02040810 -#define mmRPB_CID_QUEUE_WR_DEFAULT 0x00000000 -#define mmRPB_CID_QUEUE_RD_DEFAULT 0x00000000 -#define mmRPB_CID_QUEUE_EX_DEFAULT 0x00000000 -#define mmRPB_CID_QUEUE_EX_DATA_DEFAULT 0x00000000 -#define mmRPB_SWITCH_CNTL2_DEFAULT 0x02040810 -#define mmRPB_DEINTRLV_COMBINE_CNTL_DEFAULT 0x00000004 -#define mmRPB_VC_SWITCH_RDWR_DEFAULT 0x00004040 -#define mmRPB_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmRPB_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmRPB_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmRPB_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmRPB_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmRPB_PERFCOUNTER3_CFG_DEFAULT 0x00000000 -#define mmRPB_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmRPB_RD_QUEUE_CNTL_DEFAULT 0x00000000 -#define mmRPB_RD_QUEUE_CNTL2_DEFAULT 0x00000000 -#define mmRPB_WR_QUEUE_CNTL_DEFAULT 0x00000000 -#define mmRPB_WR_QUEUE_CNTL2_DEFAULT 0x00000000 -#define mmRPB_EA_QUEUE_WR_DEFAULT 0x00000000 -#define mmRPB_ATS_CNTL_DEFAULT 0x58088422 -#define mmRPB_ATS_CNTL2_DEFAULT 0x00050b13 -#define mmRPB_SDPPORT_CNTL_DEFAULT 0x0fd14814 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h deleted file mode 100644 index 80042e1c8770..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _athub_1_0_OFFSET_HEADER -#define _athub_1_0_OFFSET_HEADER - - - -// addressBlock: athub_atsdec -// base address: 0x3080 -#define mmATC_ATS_CNTL 0x0000 -#define mmATC_ATS_CNTL_BASE_IDX 0 -#define mmATC_ATS_STATUS 0x0003 -#define mmATC_ATS_STATUS_BASE_IDX 0 -#define mmATC_ATS_FAULT_CNTL 0x0004 -#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0 -#define mmATC_ATS_FAULT_STATUS_INFO 0x0005 -#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0 -#define mmATC_ATS_FAULT_STATUS_ADDR 0x0006 -#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0 -#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007 -#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0 -#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008 -#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0 -#define mmATC_ATS_FAULT_STATUS_INFO2 0x0009 -#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0 -#define mmATHUB_MISC_CNTL 0x000a -#define mmATHUB_MISC_CNTL_BASE_IDX 0 -#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b -#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0 -#define mmATC_VMID0_PASID_MAPPING 0x000c -#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID1_PASID_MAPPING 0x000d -#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID2_PASID_MAPPING 0x000e -#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID3_PASID_MAPPING 0x000f -#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID4_PASID_MAPPING 0x0010 -#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID5_PASID_MAPPING 0x0011 -#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID6_PASID_MAPPING 0x0012 -#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID7_PASID_MAPPING 0x0013 -#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID8_PASID_MAPPING 0x0014 -#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID9_PASID_MAPPING 0x0015 -#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID10_PASID_MAPPING 0x0016 -#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID11_PASID_MAPPING 0x0017 -#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID12_PASID_MAPPING 0x0018 -#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID13_PASID_MAPPING 0x0019 -#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID14_PASID_MAPPING 0x001a -#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID15_PASID_MAPPING 0x001b -#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0 -#define mmATC_ATS_VMID_STATUS 0x001c -#define mmATC_ATS_VMID_STATUS_BASE_IDX 0 -#define mmATC_ATS_GFX_ATCL2_STATUS 0x001d -#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0 -#define mmATC_PERFCOUNTER0_CFG 0x001e -#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0 -#define mmATC_PERFCOUNTER1_CFG 0x001f -#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0 -#define mmATC_PERFCOUNTER2_CFG 0x0020 -#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0 -#define mmATC_PERFCOUNTER3_CFG 0x0021 -#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0 -#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022 -#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 -#define mmATC_PERFCOUNTER_LO 0x0023 -#define mmATC_PERFCOUNTER_LO_BASE_IDX 0 -#define mmATC_PERFCOUNTER_HI 0x0024 -#define mmATC_PERFCOUNTER_HI_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL 0x0025 -#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0 -#define mmATHUB_PCIE_PASID_CNTL 0x0026 -#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0 -#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027 -#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0 -#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028 -#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0 -#define mmATHUB_COMMAND 0x0029 -#define mmATHUB_COMMAND_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a -#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b -#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c -#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d -#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e -#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f -#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030 -#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031 -#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032 -#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033 -#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034 -#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035 -#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036 -#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037 -#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038 -#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039 -#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 -#define mmATHUB_MEM_POWER_LS 0x003a -#define mmATHUB_MEM_POWER_LS_BASE_IDX 0 -#define mmATS_IH_CREDIT 0x003b -#define mmATS_IH_CREDIT_BASE_IDX 0 -#define mmATHUB_IH_CREDIT 0x003c -#define mmATHUB_IH_CREDIT_BASE_IDX 0 -#define mmATC_VMID16_PASID_MAPPING 0x003d -#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID17_PASID_MAPPING 0x003e -#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID18_PASID_MAPPING 0x003f -#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID19_PASID_MAPPING 0x0040 -#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID20_PASID_MAPPING 0x0041 -#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID21_PASID_MAPPING 0x0042 -#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID22_PASID_MAPPING 0x0043 -#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID23_PASID_MAPPING 0x0044 -#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID24_PASID_MAPPING 0x0045 -#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID25_PASID_MAPPING 0x0046 -#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID26_PASID_MAPPING 0x0047 -#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID27_PASID_MAPPING 0x0048 -#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID28_PASID_MAPPING 0x0049 -#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID29_PASID_MAPPING 0x004a -#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID30_PASID_MAPPING 0x004b -#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID31_PASID_MAPPING 0x004c -#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0 -#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x004d -#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0 -#define mmATHUB_SHARED_VIRT_RESET_REQ 0x004e -#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0 -#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x004f -#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 -#define mmATC_ATS_SDPPORT_CNTL 0x0050 -#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0 -#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0052 -#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0 -#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0053 -#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0 - - -// addressBlock: athub_xpbdec -// base address: 0x31f0 -#define mmXPB_RTR_SRC_APRTR0 0x005c -#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR1 0x005d -#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR2 0x005e -#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR3 0x005f -#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR4 0x0060 -#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR5 0x0061 -#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR6 0x0062 -#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR7 0x0063 -#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR8 0x0064 -#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR9 0x0065 -#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0 -#define mmXPB_XDMA_RTR_SRC_APRTR0 0x0066 -#define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0 -#define mmXPB_XDMA_RTR_SRC_APRTR1 0x0067 -#define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0 -#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0068 -#define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0 -#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0069 -#define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP0 0x006a -#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP1 0x006b -#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP2 0x006c -#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP3 0x006d -#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP4 0x006e -#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP5 0x006f -#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP6 0x0070 -#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP7 0x0071 -#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP8 0x0072 -#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP9 0x0073 -#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0 -#define mmXPB_XDMA_RTR_DEST_MAP0 0x0074 -#define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0 -#define mmXPB_XDMA_RTR_DEST_MAP1 0x0075 -#define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0 -#define mmXPB_XDMA_RTR_DEST_MAP2 0x0076 -#define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0 -#define mmXPB_XDMA_RTR_DEST_MAP3 0x0077 -#define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0 -#define mmXPB_CLG_CFG0 0x0078 -#define mmXPB_CLG_CFG0_BASE_IDX 0 -#define mmXPB_CLG_CFG1 0x0079 -#define mmXPB_CLG_CFG1_BASE_IDX 0 -#define mmXPB_CLG_CFG2 0x007a -#define mmXPB_CLG_CFG2_BASE_IDX 0 -#define mmXPB_CLG_CFG3 0x007b -#define mmXPB_CLG_CFG3_BASE_IDX 0 -#define mmXPB_CLG_CFG4 0x007c -#define mmXPB_CLG_CFG4_BASE_IDX 0 -#define mmXPB_CLG_CFG5 0x007d -#define mmXPB_CLG_CFG5_BASE_IDX 0 -#define mmXPB_CLG_CFG6 0x007e -#define mmXPB_CLG_CFG6_BASE_IDX 0 -#define mmXPB_CLG_CFG7 0x007f -#define mmXPB_CLG_CFG7_BASE_IDX 0 -#define mmXPB_CLG_EXTRA 0x0080 -#define mmXPB_CLG_EXTRA_BASE_IDX 0 -#define mmXPB_CLG_EXTRA_MSK 0x0081 -#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0 -#define mmXPB_LB_ADDR 0x0082 -#define mmXPB_LB_ADDR_BASE_IDX 0 -#define mmXPB_WCB_STS 0x0083 -#define mmXPB_WCB_STS_BASE_IDX 0 -#define mmXPB_HST_CFG 0x0084 -#define mmXPB_HST_CFG_BASE_IDX 0 -#define mmXPB_P2P_BAR_CFG 0x0085 -#define mmXPB_P2P_BAR_CFG_BASE_IDX 0 -#define mmXPB_P2P_BAR0 0x0086 -#define mmXPB_P2P_BAR0_BASE_IDX 0 -#define mmXPB_P2P_BAR1 0x0087 -#define mmXPB_P2P_BAR1_BASE_IDX 0 -#define mmXPB_P2P_BAR2 0x0088 -#define mmXPB_P2P_BAR2_BASE_IDX 0 -#define mmXPB_P2P_BAR3 0x0089 -#define mmXPB_P2P_BAR3_BASE_IDX 0 -#define mmXPB_P2P_BAR4 0x008a -#define mmXPB_P2P_BAR4_BASE_IDX 0 -#define mmXPB_P2P_BAR5 0x008b -#define mmXPB_P2P_BAR5_BASE_IDX 0 -#define mmXPB_P2P_BAR6 0x008c -#define mmXPB_P2P_BAR6_BASE_IDX 0 -#define mmXPB_P2P_BAR7 0x008d -#define mmXPB_P2P_BAR7_BASE_IDX 0 -#define mmXPB_P2P_BAR_SETUP 0x008e -#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0 -#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0090 -#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0 -#define mmXPB_P2P_BAR_DELTA_BELOW 0x0091 -#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR0 0x0092 -#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR1 0x0093 -#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR2 0x0094 -#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR3 0x0095 -#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR4 0x0096 -#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR5 0x0097 -#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR6 0x0098 -#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR7 0x0099 -#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR8 0x009a -#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR9 0x009b -#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0 -#define mmXPB_XDMA_PEER_SYS_BAR0 0x009c -#define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0 -#define mmXPB_XDMA_PEER_SYS_BAR1 0x009d -#define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0 -#define mmXPB_XDMA_PEER_SYS_BAR2 0x009e -#define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0 -#define mmXPB_XDMA_PEER_SYS_BAR3 0x009f -#define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0 -#define mmXPB_CLK_GAT 0x00a0 -#define mmXPB_CLK_GAT_BASE_IDX 0 -#define mmXPB_INTF_CFG 0x00a1 -#define mmXPB_INTF_CFG_BASE_IDX 0 -#define mmXPB_INTF_STS 0x00a2 -#define mmXPB_INTF_STS_BASE_IDX 0 -#define mmXPB_PIPE_STS 0x00a3 -#define mmXPB_PIPE_STS_BASE_IDX 0 -#define mmXPB_SUB_CTRL 0x00a4 -#define mmXPB_SUB_CTRL_BASE_IDX 0 -#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00a5 -#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0 -#define mmXPB_PERF_KNOBS 0x00a6 -#define mmXPB_PERF_KNOBS_BASE_IDX 0 -#define mmXPB_STICKY 0x00a7 -#define mmXPB_STICKY_BASE_IDX 0 -#define mmXPB_STICKY_W1C 0x00a8 -#define mmXPB_STICKY_W1C_BASE_IDX 0 -#define mmXPB_MISC_CFG 0x00a9 -#define mmXPB_MISC_CFG_BASE_IDX 0 -#define mmXPB_INTF_CFG2 0x00aa -#define mmXPB_INTF_CFG2_BASE_IDX 0 -#define mmXPB_CLG_EXTRA_RD 0x00ab -#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0 -#define mmXPB_CLG_EXTRA_MSK_RD 0x00ac -#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0 -#define mmXPB_CLG_GFX_MATCH 0x00ad -#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0 -#define mmXPB_CLG_GFX_MATCH_MSK 0x00ae -#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0 -#define mmXPB_CLG_MM_MATCH 0x00af -#define mmXPB_CLG_MM_MATCH_BASE_IDX 0 -#define mmXPB_CLG_MM_MATCH_MSK 0x00b0 -#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00b1 -#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00b2 -#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00b3 -#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00b4 -#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00b5 -#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00b6 -#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00b7 -#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00b8 -#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0 -#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00b9 -#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0 -#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00ba -#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0 -#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00bb -#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0 -#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00bc -#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0 - - -// addressBlock: athub_rpbdec -// base address: 0x33b0 -#define mmRPB_PASSPW_CONF 0x00cc -#define mmRPB_PASSPW_CONF_BASE_IDX 0 -#define mmRPB_BLOCKLEVEL_CONF 0x00cd -#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0 -#define mmRPB_TAG_CONF 0x00cf -#define mmRPB_TAG_CONF_BASE_IDX 0 -#define mmRPB_EFF_CNTL 0x00d1 -#define mmRPB_EFF_CNTL_BASE_IDX 0 -#define mmRPB_ARB_CNTL 0x00d2 -#define mmRPB_ARB_CNTL_BASE_IDX 0 -#define mmRPB_ARB_CNTL2 0x00d3 -#define mmRPB_ARB_CNTL2_BASE_IDX 0 -#define mmRPB_BIF_CNTL 0x00d4 -#define mmRPB_BIF_CNTL_BASE_IDX 0 -#define mmRPB_WR_SWITCH_CNTL 0x00d5 -#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0 -#define mmRPB_RD_SWITCH_CNTL 0x00d7 -#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0 -#define mmRPB_CID_QUEUE_WR 0x00d8 -#define mmRPB_CID_QUEUE_WR_BASE_IDX 0 -#define mmRPB_CID_QUEUE_RD 0x00d9 -#define mmRPB_CID_QUEUE_RD_BASE_IDX 0 -#define mmRPB_CID_QUEUE_EX 0x00dc -#define mmRPB_CID_QUEUE_EX_BASE_IDX 0 -#define mmRPB_CID_QUEUE_EX_DATA 0x00dd -#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0 -#define mmRPB_SWITCH_CNTL2 0x00de -#define mmRPB_SWITCH_CNTL2_BASE_IDX 0 -#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00df -#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0 -#define mmRPB_VC_SWITCH_RDWR 0x00e0 -#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0 -#define mmRPB_PERFCOUNTER_LO 0x00e1 -#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0 -#define mmRPB_PERFCOUNTER_HI 0x00e2 -#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0 -#define mmRPB_PERFCOUNTER0_CFG 0x00e3 -#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0 -#define mmRPB_PERFCOUNTER1_CFG 0x00e4 -#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0 -#define mmRPB_PERFCOUNTER2_CFG 0x00e5 -#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0 -#define mmRPB_PERFCOUNTER3_CFG 0x00e6 -#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0 -#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00e7 -#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 -#define mmRPB_RD_QUEUE_CNTL 0x00e9 -#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0 -#define mmRPB_RD_QUEUE_CNTL2 0x00ea -#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0 -#define mmRPB_WR_QUEUE_CNTL 0x00eb -#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0 -#define mmRPB_WR_QUEUE_CNTL2 0x00ec -#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0 -#define mmRPB_EA_QUEUE_WR 0x00ed -#define mmRPB_EA_QUEUE_WR_BASE_IDX 0 -#define mmRPB_ATS_CNTL 0x00ee -#define mmRPB_ATS_CNTL_BASE_IDX 0 -#define mmRPB_ATS_CNTL2 0x00ef -#define mmRPB_ATS_CNTL2_BASE_IDX 0 -#define mmRPB_SDPPORT_CNTL 0x00f0 -#define mmRPB_SDPPORT_CNTL_BASE_IDX 0 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h deleted file mode 100644 index 777b05c89708..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h +++ /dev/null @@ -1,2045 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _athub_1_0_SH_MASK_HEADER -#define _athub_1_0_SH_MASK_HEADER - - -// addressBlock: athub_atsdec -//ATC_ATS_CNTL -#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 -#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 -#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 -#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 -#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14 -#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15 -#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16 -#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L -#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L -#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L -#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L -#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L -#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L -#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L -//ATC_ATS_STATUS -#define ATC_ATS_STATUS__BUSY__SHIFT 0x0 -#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 -#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 -#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3 -#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6 -#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L -#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L -#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L -#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L -#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L -//ATC_ATS_FAULT_CNTL -#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 -#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa -#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 -#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL -#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L -#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L -//ATC_ATS_FAULT_STATUS_INFO -#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 -#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 -#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 -#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 -#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL -#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L -#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L -#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L -//ATC_ATS_FAULT_STATUS_ADDR -#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 -#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL -//ATC_ATS_DEFAULT_PAGE_LOW -#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 -#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL -//ATC_TRANS_FAULT_RSPCNTRL -#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa -#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb -#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc -#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd -#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe -#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf -#define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a -#define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b -#define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c -#define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d -#define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e -#define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f -#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L -//ATC_ATS_FAULT_STATUS_INFO2 -#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 -#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 -#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9 -#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L -#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL -#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L -//ATHUB_MISC_CNTL -#define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6 -#define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12 -#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13 -#define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14 -#define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15 -#define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b -#define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c -#define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L -#define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L -#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L -#define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L -#define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L -#define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L -#define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L -//ATC_VMID_PASID_MAPPING_UPDATE_STATUS -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L -//ATC_VMID0_PASID_MAPPING -#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID1_PASID_MAPPING -#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID2_PASID_MAPPING -#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID3_PASID_MAPPING -#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID4_PASID_MAPPING -#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID5_PASID_MAPPING -#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID6_PASID_MAPPING -#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID7_PASID_MAPPING -#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID8_PASID_MAPPING -#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID9_PASID_MAPPING -#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID10_PASID_MAPPING -#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID11_PASID_MAPPING -#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID12_PASID_MAPPING -#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID13_PASID_MAPPING -#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID14_PASID_MAPPING -#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID15_PASID_MAPPING -#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_ATS_VMID_STATUS -#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 -#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 -#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 -#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 -#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 -#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 -#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 -#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 -#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 -#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 -#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa -#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb -#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc -#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd -#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe -#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf -#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10 -#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11 -#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12 -#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13 -#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14 -#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15 -#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16 -#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17 -#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18 -#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19 -#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a -#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b -#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c -#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d -#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e -#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f -#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L -#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L -#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L -#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L -#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L -#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L -#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L -#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L -#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L -#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L -#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L -#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L -#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L -#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L -#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L -#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L -#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L -#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L -#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L -#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L -#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L -#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L -#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L -#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L -#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L -#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L -#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L -#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L -#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L -#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L -#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L -#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L -//ATC_ATS_GFX_ATCL2_STATUS -#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 -#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L -//ATC_PERFCOUNTER0_CFG -#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//ATC_PERFCOUNTER1_CFG -#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//ATC_PERFCOUNTER2_CFG -#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c -#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d -#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L -//ATC_PERFCOUNTER3_CFG -#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c -#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d -#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L -#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L -//ATC_PERFCOUNTER_RSLT_CNTL -#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L -//ATC_PERFCOUNTER_LO -#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//ATC_PERFCOUNTER_HI -#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L -//ATHUB_PCIE_ATS_CNTL -#define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10 -#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L -#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_PASID_CNTL -#define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10 -#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11 -#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12 -#define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L -#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L -#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L -//ATHUB_PCIE_PAGE_REQ_CNTL -#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 -#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 -#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L -#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L -//ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC -#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 -#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL -//ATHUB_COMMAND -#define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 -#define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L -//ATHUB_PCIE_ATS_CNTL_VF_0 -#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_1 -#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_2 -#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_3 -#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_4 -#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_5 -#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_6 -#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_7 -#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_8 -#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_9 -#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_10 -#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_11 -#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_12 -#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_13 -#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_14 -#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_15 -#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L -//ATHUB_MEM_POWER_LS -#define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 -#define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 -#define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL -#define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L -//ATS_IH_CREDIT -#define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 -#define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L -//ATHUB_IH_CREDIT -#define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 -#define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L -//ATC_VMID16_PASID_MAPPING -#define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID17_PASID_MAPPING -#define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID18_PASID_MAPPING -#define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID19_PASID_MAPPING -#define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID20_PASID_MAPPING -#define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID21_PASID_MAPPING -#define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID22_PASID_MAPPING -#define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID23_PASID_MAPPING -#define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID24_PASID_MAPPING -#define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID25_PASID_MAPPING -#define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID26_PASID_MAPPING -#define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID27_PASID_MAPPING -#define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID28_PASID_MAPPING -#define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID29_PASID_MAPPING -#define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID30_PASID_MAPPING -#define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID31_PASID_MAPPING -#define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_ATS_MMHUB_ATCL2_STATUS -#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 -#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L -//ATHUB_SHARED_VIRT_RESET_REQ -#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 -#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f -#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL -#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L -//ATHUB_SHARED_ACTIVE_FCN_ID -#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//ATC_ATS_SDPPORT_CNTL -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0 -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1 -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe -#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19 -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L -//ATC_ATS_VMID_SNAPSHOT_GFX_STAT -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L -//ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L - - -// addressBlock: athub_xpbdec -//XPB_RTR_SRC_APRTR0 -#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR1 -#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR2 -#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR3 -#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR4 -#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR5 -#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR6 -#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR7 -#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR8 -#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR9 -#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_XDMA_RTR_SRC_APRTR0 -#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 -#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_XDMA_RTR_SRC_APRTR1 -#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 -#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_XDMA_RTR_SRC_APRTR2 -#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 -#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_XDMA_RTR_SRC_APRTR3 -#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 -#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_DEST_MAP0 -#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP1 -#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP2 -#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP3 -#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP4 -#define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP5 -#define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP6 -#define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP7 -#define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP8 -#define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP9 -#define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L -//XPB_XDMA_RTR_DEST_MAP0 -#define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 -#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 -#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 -#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a -#define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L -#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L -#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L -//XPB_XDMA_RTR_DEST_MAP1 -#define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 -#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 -#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 -#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a -#define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L -#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L -#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L -//XPB_XDMA_RTR_DEST_MAP2 -#define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 -#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 -#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 -#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a -#define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L -#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L -#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L -//XPB_XDMA_RTR_DEST_MAP3 -#define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 -#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 -#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 -#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a -#define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L -#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L -#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L -//XPB_CLG_CFG0 -#define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG1 -#define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG2 -#define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG3 -#define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG4 -#define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG5 -#define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG6 -#define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG7 -#define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_EXTRA -#define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0 -#define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6 -#define XPB_CLG_EXTRA__VLD0__SHIFT 0xb -#define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc -#define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf -#define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15 -#define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a -#define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b -#define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL -#define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L -#define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L -#define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L -#define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L -#define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L -#define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L -#define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L -//XPB_CLG_EXTRA_MSK -#define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 -#define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6 -#define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb -#define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11 -#define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL -#define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L -#define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L -#define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L -//XPB_LB_ADDR -#define XPB_LB_ADDR__CMP0__SHIFT 0x0 -#define XPB_LB_ADDR__MASK0__SHIFT 0xa -#define XPB_LB_ADDR__CMP1__SHIFT 0x14 -#define XPB_LB_ADDR__MASK1__SHIFT 0x1a -#define XPB_LB_ADDR__CMP0_MASK 0x000003FFL -#define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L -#define XPB_LB_ADDR__CMP1_MASK 0x03F00000L -#define XPB_LB_ADDR__MASK1_MASK 0xFC000000L -//XPB_WCB_STS -#define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 -#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 -#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 -#define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL -#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L -#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L -//XPB_HST_CFG -#define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 -#define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L -//XPB_P2P_BAR_CFG -#define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 -#define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 -#define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 -#define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 -#define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 -#define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 -#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa -#define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb -#define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc -#define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL -#define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L -#define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L -#define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L -#define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L -#define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L -#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L -#define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L -#define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L -//XPB_P2P_BAR0 -#define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR0__VALID__SHIFT 0xc -#define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR0__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR0__VALID_MASK 0x00001000L -#define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR1 -#define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR1__VALID__SHIFT 0xc -#define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR1__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR1__VALID_MASK 0x00001000L -#define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR2 -#define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR2__VALID__SHIFT 0xc -#define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR2__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR2__VALID_MASK 0x00001000L -#define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR3 -#define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR3__VALID__SHIFT 0xc -#define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR3__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR3__VALID_MASK 0x00001000L -#define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR4 -#define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR4__VALID__SHIFT 0xc -#define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR4__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR4__VALID_MASK 0x00001000L -#define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR5 -#define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR5__VALID__SHIFT 0xc -#define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR5__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR5__VALID_MASK 0x00001000L -#define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR6 -#define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR6__VALID__SHIFT 0xc -#define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR6__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR6__VALID_MASK 0x00001000L -#define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR7 -#define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR7__VALID__SHIFT 0xc -#define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR7__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR7__VALID_MASK 0x00001000L -#define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR_SETUP -#define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 -#define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc -#define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL -#define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L -#define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR_DELTA_ABOVE -#define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 -#define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 -#define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL -#define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L -//XPB_P2P_BAR_DELTA_BELOW -#define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 -#define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 -#define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL -#define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L -//XPB_PEER_SYS_BAR0 -#define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR1 -#define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR2 -#define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR3 -#define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR4 -#define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR5 -#define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR6 -#define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR7 -#define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR8 -#define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR9 -#define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL -//XPB_XDMA_PEER_SYS_BAR0 -#define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 -#define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1 -#define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L -#define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL -//XPB_XDMA_PEER_SYS_BAR1 -#define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 -#define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1 -#define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L -#define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL -//XPB_XDMA_PEER_SYS_BAR2 -#define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 -#define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1 -#define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L -#define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL -//XPB_XDMA_PEER_SYS_BAR3 -#define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 -#define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1 -#define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L -#define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL -//XPB_CLK_GAT -#define XPB_CLK_GAT__ONDLY__SHIFT 0x0 -#define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 -#define XPB_CLK_GAT__RDYDLY__SHIFT 0xc -#define XPB_CLK_GAT__ENABLE__SHIFT 0x12 -#define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 -#define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL -#define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L -#define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L -#define XPB_CLK_GAT__ENABLE_MASK 0x00040000L -#define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L -//XPB_INTF_CFG -#define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 -#define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 -#define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 -#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 -#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 -#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 -#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a -#define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b -#define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d -#define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e -#define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f -#define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL -#define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L -#define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L -#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L -#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L -#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L -#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L -#define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L -#define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L -#define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L -#define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L -//XPB_INTF_STS -#define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 -#define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 -#define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf -#define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 -#define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 -#define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 -#define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 -#define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL -#define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L -#define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L -#define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L -#define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L -#define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L -#define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L -//XPB_PIPE_STS -#define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 -#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 -#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 -#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf -#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 -#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 -#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 -#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 -#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 -#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 -#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 -#define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 -#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 -#define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L -#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL -#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L -#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L -#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L -#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L -#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L -#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L -#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L -#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L -#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L -#define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L -#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L -//XPB_SUB_CTRL -#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 -#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 -#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 -#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 -#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 -#define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 -#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 -#define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 -#define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 -#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 -#define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa -#define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb -#define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc -#define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd -#define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe -#define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf -#define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 -#define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 -#define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 -#define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 -#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L -#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L -#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L -#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L -#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L -#define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L -#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L -#define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L -#define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L -#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L -#define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L -#define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L -#define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L -#define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L -#define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L -#define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L -#define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L -#define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L -#define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L -#define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L -//XPB_MAP_INVERT_FLUSH_NUM_LSB -#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 -#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL -//XPB_PERF_KNOBS -#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 -#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 -#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc -#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL -#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L -#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L -//XPB_STICKY -#define XPB_STICKY__BITS__SHIFT 0x0 -#define XPB_STICKY__BITS_MASK 0xFFFFFFFFL -//XPB_STICKY_W1C -#define XPB_STICKY_W1C__BITS__SHIFT 0x0 -#define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL -//XPB_MISC_CFG -#define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 -#define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 -#define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 -#define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 -#define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f -#define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL -#define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L -#define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L -#define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L -#define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L -//XPB_INTF_CFG2 -#define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 -#define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL -//XPB_CLG_EXTRA_RD -#define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 -#define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 -#define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb -#define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc -#define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf -#define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 -#define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a -#define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b -#define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL -#define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L -#define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L -#define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L -#define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L -#define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L -#define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L -#define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L -//XPB_CLG_EXTRA_MSK_RD -#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 -#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 -#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb -#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 -#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL -#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L -#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L -#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L -//XPB_CLG_GFX_MATCH -#define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 -#define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6 -#define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc -#define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12 -#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18 -#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19 -#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a -#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b -#define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL -#define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L -#define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L -#define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L -#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L -#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L -#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L -#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L -//XPB_CLG_GFX_MATCH_MSK -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L -//XPB_CLG_MM_MATCH -#define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 -#define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6 -#define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0xc -#define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x12 -#define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0x18 -#define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0x19 -#define XPB_CLG_MM_MATCH__FARBIRC2_VLD__SHIFT 0x1a -#define XPB_CLG_MM_MATCH__FARBIRC3_VLD__SHIFT 0x1b -#define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL -#define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L -#define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x0003F000L -#define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0x00FC0000L -#define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x01000000L -#define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x02000000L -#define XPB_CLG_MM_MATCH__FARBIRC2_VLD_MASK 0x04000000L -#define XPB_CLG_MM_MATCH__FARBIRC3_VLD_MASK 0x08000000L -//XPB_CLG_MM_MATCH_MSK -#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 -#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 -#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc -#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 -#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL -#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L -#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L -#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L -//XPB_CLG_GFX_UNITID_MAPPING0 -#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING1 -#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING2 -#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING3 -#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING4 -#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING5 -#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING6 -#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING7 -#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_MM_UNITID_MAPPING0 -#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_MM_UNITID_MAPPING1 -#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_MM_UNITID_MAPPING2 -#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_MM_UNITID_MAPPING3 -#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L - - -// addressBlock: athub_rpbdec -//RPB_PASSPW_CONF -#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 -#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 -#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2 -#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3 -#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4 -#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5 -#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6 -#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7 -#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8 -#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9 -#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa -#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb -#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc -#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd -#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe -#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf -#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10 -#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11 -#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L -#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L -#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L -#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L -#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L -#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L -#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L -#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L -#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L -#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L -#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L -#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L -#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L -#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L -#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L -#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L -#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L -#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L -//RPB_BLOCKLEVEL_CONF -#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 -#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2 -#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4 -#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6 -#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8 -#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa -#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc -#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe -#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf -#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 -#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11 -#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L -#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL -#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L -#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L -#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L -#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L -#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L -#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L -#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L -#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L -#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L -//RPB_TAG_CONF -#define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0 -#define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0x8 -#define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x10 -#define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000000FFL -#define RPB_TAG_CONF__RPB_IO_WR_MASK 0x0000FF00L -#define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x00FF0000L -//RPB_EFF_CNTL -#define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 -#define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 -#define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL -#define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L -//RPB_ARB_CNTL -#define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 -#define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 -#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 -#define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 -#define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 -#define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL -#define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L -#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L -#define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L -#define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L -//RPB_ARB_CNTL2 -#define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 -#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 -#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 -#define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL -#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L -#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L -//RPB_BIF_CNTL -#define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 -#define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 -#define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10 -#define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11 -#define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12 -#define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13 -#define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b -#define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c -#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d -#define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e -#define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL -#define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L -#define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L -#define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L -#define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L -#define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L -#define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L -#define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L -#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L -#define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L -//RPB_WR_SWITCH_CNTL -#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 -#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 -#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe -#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 -#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c -#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL -#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L -#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L -#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L -#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L -//RPB_RD_SWITCH_CNTL -#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 -#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 -#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe -#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 -#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c -#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL -#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L -#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L -#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L -#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L -//RPB_CID_QUEUE_WR -#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0 -#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5 -#define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb -#define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc -#define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf -#define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12 -#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL -#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L -#define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L -#define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L -#define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L -#define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L -//RPB_CID_QUEUE_RD -#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0 -#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5 -#define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb -#define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe -#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL -#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L -#define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L -#define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L -//RPB_CID_QUEUE_EX -#define RPB_CID_QUEUE_EX__START__SHIFT 0x0 -#define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 -#define RPB_CID_QUEUE_EX__START_MASK 0x00000001L -#define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL -//RPB_CID_QUEUE_EX_DATA -#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 -#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 -#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL -#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L -//RPB_SWITCH_CNTL2 -#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0 -#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7 -#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe -#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15 -#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL -#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L -#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L -#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L -//RPB_DEINTRLV_COMBINE_CNTL -#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 -#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 -#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 -#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL -#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L -#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L -//RPB_VC_SWITCH_RDWR -#define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 -#define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 -#define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa -#define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L -#define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL -#define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L -//RPB_PERFCOUNTER_LO -#define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//RPB_PERFCOUNTER_HI -#define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L -//RPB_PERFCOUNTER0_CFG -#define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//RPB_PERFCOUNTER1_CFG -#define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//RPB_PERFCOUNTER2_CFG -#define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 -#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 -#define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 -#define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c -#define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d -#define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL -#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L -#define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L -//RPB_PERFCOUNTER3_CFG -#define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 -#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 -#define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 -#define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c -#define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d -#define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL -#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L -#define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L -#define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L -//RPB_PERFCOUNTER_RSLT_CNTL -#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L -//RPB_RD_QUEUE_CNTL -#define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 -#define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 -#define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 -#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 -#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 -#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 -#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa -#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 -#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 -#define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L -#define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L -#define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L -#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L -#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L -#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L -#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L -#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L -#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L -//RPB_RD_QUEUE_CNTL2 -#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 -#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 -#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb -#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 -#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL -#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L -#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L -#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L -//RPB_WR_QUEUE_CNTL -#define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 -#define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 -#define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 -#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 -#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 -#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 -#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa -#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 -#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 -#define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L -#define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L -#define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L -#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L -#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L -#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L -#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L -#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L -#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L -//RPB_WR_QUEUE_CNTL2 -#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 -#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 -#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb -#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 -#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL -#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L -#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L -#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L -//RPB_EA_QUEUE_WR -#define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0 -#define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5 -#define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8 -#define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb -#define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL -#define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L -#define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L -#define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L -//RPB_ATS_CNTL -#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 -#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 -#define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 -#define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 -#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf -#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 -#define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 -#define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19 -#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L -#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L -#define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL -#define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L -#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L -#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L -#define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L -#define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L -//RPB_ATS_CNTL2 -#define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0 -#define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6 -#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc -#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf -#define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12 -#define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL -#define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L -#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L -#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L -#define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L -//RPB_SDPPORT_CNTL -#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 -#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 -#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 -#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa -#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf -#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10 -#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14 -#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b -#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L -#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L -#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L -#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L -#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L -#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L -#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L -#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L - -#endif -- GitLab From a629bf32df4659b79595115e247dcc65df27727b Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Wed, 22 Nov 2017 14:57:05 +0800 Subject: [PATCH 0928/2547] drm/amd/include:cleanup vega10 thm header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/vega10/THM folder. Signed-off-by: Feifei Xu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- .../include/asic_reg/{vega10/THM => thm}/thm_9_0_default.h | 0 .../include/asic_reg/{vega10/THM => thm}/thm_9_0_offset.h | 0 .../include/asic_reg/{vega10/THM => thm}/thm_9_0_sh_mask.h | 0 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h | 6 +++--- 4 files changed, 3 insertions(+), 3 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/THM => thm}/thm_9_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/THM => thm}/thm_9_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/THM => thm}/thm_9_0_sh_mask.h (100%) diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_default.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h index 2573f95fd39f..e316cd79a321 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h @@ -24,9 +24,9 @@ #ifndef VEGA10_INC_H #define VEGA10_INC_H -#include "asic_reg/vega10/THM/thm_9_0_default.h" -#include "asic_reg/vega10/THM/thm_9_0_offset.h" -#include "asic_reg/vega10/THM/thm_9_0_sh_mask.h" +#include "asic_reg/thm/thm_9_0_default.h" +#include "asic_reg/thm/thm_9_0_offset.h" +#include "asic_reg/thm/thm_9_0_sh_mask.h" #include "asic_reg/mp/mp_9_0_offset.h" #include "asic_reg/mp/mp_9_0_sh_mask.h" -- GitLab From 90c7a9358fcbf5bfec84c1841122107f2cf5e489 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Wed, 22 Nov 2017 15:23:20 +0800 Subject: [PATCH 0929/2547] drm/amd/include: cleanup vega10 umc header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove asic/vega10/UMC folder. Signed-off-by: Feifei Xu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- .../amd/include/asic_reg/{vega10/UMC => umc}/umc_6_0_default.h | 0 .../amd/include/asic_reg/{vega10/UMC => umc}/umc_6_0_offset.h | 0 .../amd/include/asic_reg/{vega10/UMC => umc}/umc_6_0_sh_mask.h | 0 4 files changed, 1 insertion(+), 1 deletion(-) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/UMC => umc}/umc_6_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/UMC => umc}/umc_6_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/UMC => umc}/umc_6_0_sh_mask.h (100%) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 9b6532a1622b..2bf943f7dd8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -36,7 +36,7 @@ #include "athub/athub_1_0_offset.h" #include "soc15_common.h" -#include "vega10/UMC/umc_6_0_sh_mask.h" +#include "umc/umc_6_0_sh_mask.h" #include "nbio_v6_1.h" #include "nbio_v7_0.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h rename to drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h -- GitLab From 135d4b10d3b64a4b2a77118961ed288c1a88def3 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 23 Nov 2017 18:18:14 +0800 Subject: [PATCH 0930/2547] drm/amd/include:cleanup vega10 dce header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/vega10/DC folder.Remove dce_12_0_default.h. Signed-off-by: Feifei Xu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +- .../display/dc/dce120/dce120_hw_sequencer.c | 4 +- .../amd/display/dc/dce120/dce120_resource.c | 4 +- .../dc/dce120/dce120_timing_generator.c | 4 +- .../dc/gpio/dce120/hw_factory_dce120.c | 4 +- .../dc/gpio/dce120/hw_translate_dce120.c | 4 +- .../display/dc/i2caux/dce120/i2caux_dce120.c | 4 +- .../dc/irq/dce120/irq_service_dce120.c | 4 +- .../{vega10/DC => dce}/dce_12_0_offset.h | 0 .../{vega10/DC => dce}/dce_12_0_sh_mask.h | 0 .../asic_reg/vega10/DC/dce_12_0_default.h | 9868 ----------------- 11 files changed, 16 insertions(+), 9884 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/DC => dce}/dce_12_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/DC => dce}/dce_12_0_sh_mask.h (100%) delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 2bf943f7dd8d..2760adaa767b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -29,8 +29,8 @@ #include "hdp/hdp_4_0_offset.h" #include "hdp/hdp_4_0_sh_mask.h" #include "vega10/GC/gc_9_0_sh_mask.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" #include "vega10/vega10_enum.h" #include "vega10/MMHUB/mmhub_1_0_offset.h" #include "athub/athub_1_0_offset.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c index 1a0b54d6034e..8613ecf06514 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c @@ -31,8 +31,8 @@ #include "dce110/dce110_hw_sequencer.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" #include "vega10/soc15ip.h" #include "reg_helper.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 5c48c22d9d98..e59a4e6d6a55 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -54,8 +54,8 @@ #include "dce/dce_abm.h" #include "dce/dce_dmcu.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" #include "vega10/soc15ip.h" #include "vega10/NBIO/nbio_6_1_offset.h" #include "reg_helper.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 2502182d5e82..5ad04d24fd27 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -25,8 +25,8 @@ #include "dm_services.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" #include "vega10/soc15ip.h" #include "dc_types.h" diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c index 4ced9a7d63dd..d8b70d151457 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c @@ -34,8 +34,8 @@ #include "hw_factory_dce120.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" #include "vega10/soc15ip.h" #define block HPD diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c index af3843a69652..0d0bc440835f 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c @@ -33,8 +33,8 @@ #include "include/gpio_types.h" #include "../hw_translate.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" #include "vega10/soc15ip.h" /* begin ********************* diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c index 668981a4c285..0de53257b865 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c @@ -36,8 +36,8 @@ #include "../dce110/aux_engine_dce110.h" #include "../dce110/i2caux_dce110.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" #include "vega10/soc15ip.h" /* begin ********************* diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c index 2ad56b1a4099..8135d7a5f4d6 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c @@ -30,8 +30,8 @@ #include "irq_service_dce120.h" #include "../dce110/irq_service_dce110.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" #include "vega10/soc15ip.h" #include "ivsrcid/ivsrcid_vislands30.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h deleted file mode 100644 index 8a0007ce43dc..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h +++ /dev/null @@ -1,9868 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _dce_12_0_DEFAULT_HEADER -#define _dce_12_0_DEFAULT_HEADER - - -// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR -#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR -#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon0_dispdec -#define mmDC_PERFMON0_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON0_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon13_dispdec -#define mmDC_PERFMON13_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON13_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_displaypllregs_dispdec -#define mmPPLL_VREG_CFG_DEFAULT 0x00000000 -#define mmPPLL_MODE_CNTL_DEFAULT 0x00020100 -#define mmPPLL_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmPPLL_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmPPLL_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmPPLL_FREQ_CTRL3_DEFAULT 0x00190040 -#define mmPPLL_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmPPLL_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmPPLL_CAL_CTRL_DEFAULT 0x64000002 -#define mmPPLL_LOOP_CTRL_DEFAULT 0x00000090 -#define mmPPLL_REFCLK_CNTL_DEFAULT 0x00018004 -#define mmPPLL_CLKOUT_CNTL_DEFAULT 0x00022500 -#define mmPPLL_DFT_CNTL_DEFAULT 0x00000004 -#define mmPPLL_ANALOG_CNTL_DEFAULT 0x00000000 -#define mmPPLL_POSTDIV_DEFAULT 0x00000400 -#define mmPPLL_OBSERVE0_DEFAULT 0x00000000 -#define mmPPLL_OBSERVE1_DEFAULT 0x04b00000 -#define mmPPLL_UPDATE_CNTL_DEFAULT 0x00000000 -#define mmPPLL_OBSERVE0_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dccg_pll0_dispdec -#define mmPLL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon1_dispdec -#define mmDC_PERFMON1_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON1_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mcif_wb0_dispdec -#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 -#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 -#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 -#define mmMCIF_WB0_MCIF_WB_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 -#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 -#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 -#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff -#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff - - -// addressBlock: dce_dc_mcif_wb1_dispdec -#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 -#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 -#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 -#define mmMCIF_WB1_MCIF_WB_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 -#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 -#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 -#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff -#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff - - -// addressBlock: dce_dc_mcif_wb2_dispdec -#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 -#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 -#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 -#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 -#define mmMCIF_WB2_MCIF_WB_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 -#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 -#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 -#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff -#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff - - -// addressBlock: dce_dc_cwb0_dispdec -#define mmCWB0_CWB_CTRL_DEFAULT 0x00000110 -#define mmCWB0_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff -#define mmCWB0_CWB_FENCE_PAR1_DEFAULT 0x000102ff -#define mmCWB0_CWB_CRC_CTRL_DEFAULT 0x00000000 -#define mmCWB0_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmCWB0_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff -#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000 -#define mmCWB0_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_cwb1_dispdec -#define mmCWB1_CWB_CTRL_DEFAULT 0x00000110 -#define mmCWB1_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff -#define mmCWB1_CWB_FENCE_PAR1_DEFAULT 0x000102ff -#define mmCWB1_CWB_CRC_CTRL_DEFAULT 0x00000000 -#define mmCWB1_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmCWB1_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff -#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000 -#define mmCWB1_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon9_dispdec -#define mmDC_PERFMON9_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON9_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dispdec -#define mmVGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000 -#define mmVGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000 -#define mmVGA_RENDER_CONTROL_DEFAULT 0x0000000f -#define mmVGA_SEQUENCER_RESET_CONTROL_DEFAULT 0x00003f3f -#define mmVGA_MODE_CONTROL_DEFAULT 0x00000000 -#define mmVGA_SURFACE_PITCH_SELECT_DEFAULT 0x00000002 -#define mmVGA_MEMORY_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmVGA_DISPBUF1_SURFACE_ADDR_DEFAULT 0x00000000 -#define mmVGA_DISPBUF2_SURFACE_ADDR_DEFAULT 0x00000000 -#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmVGA_HDP_CONTROL_DEFAULT 0x00000000 -#define mmVGA_CACHE_CONTROL_DEFAULT 0x00000000 -#define mmD1VGA_CONTROL_DEFAULT 0x00000000 -#define mmD2VGA_CONTROL_DEFAULT 0x00000000 -#define mmVGA_STATUS_DEFAULT 0x00000000 -#define mmVGA_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmVGA_STATUS_CLEAR_DEFAULT 0x00000000 -#define mmVGA_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmVGA_MAIN_CONTROL_DEFAULT 0x00005018 -#define mmVGA_TEST_CONTROL_DEFAULT 0x00000000 -#define mmVGA_QOS_CTRL_DEFAULT 0x00000000 -#define mmCRTC8_IDX_DEFAULT 0x00000000 -#define mmCRTC8_DATA_DEFAULT 0x00000000 -#define mmGENFC_WT_DEFAULT 0x00000000 -#define mmGENS1_DEFAULT 0x00000000 -#define mmATTRDW_DEFAULT 0x00000000 -#define mmATTRX_DEFAULT 0x00000000 -#define mmATTRDR_DEFAULT 0x00000000 -#define mmGENMO_WT_DEFAULT 0x00000000 -#define mmGENS0_DEFAULT 0x00000000 -#define mmGENENB_DEFAULT 0x00000000 -#define mmSEQ8_IDX_DEFAULT 0x00000000 -#define mmSEQ8_DATA_DEFAULT 0x00000000 -#define mmDAC_MASK_DEFAULT 0x00000000 -#define mmDAC_R_INDEX_DEFAULT 0x00000000 -#define mmDAC_W_INDEX_DEFAULT 0x00000000 -#define mmDAC_DATA_DEFAULT 0x00000000 -#define mmGENFC_RD_DEFAULT 0x00000000 -#define mmGENMO_RD_DEFAULT 0x00000000 -#define mmGRPH8_IDX_DEFAULT 0x00000000 -#define mmGRPH8_DATA_DEFAULT 0x00000000 -#define mmCRTC8_IDX_1_DEFAULT 0x00000000 -#define mmCRTC8_DATA_1_DEFAULT 0x00000000 -#define mmGENFC_WT_1_DEFAULT 0x00000000 -#define mmGENS1_1_DEFAULT 0x00000000 -#define mmD3VGA_CONTROL_DEFAULT 0x00000000 -#define mmD4VGA_CONTROL_DEFAULT 0x00000000 -#define mmD5VGA_CONTROL_DEFAULT 0x00000000 -#define mmD6VGA_CONTROL_DEFAULT 0x00000000 -#define mmVGA_SOURCE_SELECT_DEFAULT 0x00000100 -#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmSYMCLKLPA_CLOCK_ENABLE_DEFAULT 0x00000000 -#define mmSYMCLKLPB_CLOCK_ENABLE_DEFAULT 0x00000100 -#define mmDPREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmREFCLK_CNTL_DEFAULT 0x00000000 -#define mmMIPI_CLK_CNTL_DEFAULT 0x00000000 -#define mmREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDSICLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmDCCG_CBUS_WRCMD_DELAY_DEFAULT 0x00000003 -#define mmDCCG_DS_DTO_INCR_DEFAULT 0x00000000 -#define mmDCCG_DS_DTO_MODULO_DEFAULT 0x00000000 -#define mmDCCG_DS_CNTL_DEFAULT 0x00000000 -#define mmDCCG_DS_HW_CAL_INTERVAL_DEFAULT 0x00989680 -#define mmSYMCLKG_CLOCK_ENABLE_DEFAULT 0x00000600 -#define mmDPREFCLK_CNTL_DEFAULT 0x00000000 -#define mmAOMCLK0_CNTL_DEFAULT 0x00000000 -#define mmAOMCLK1_CNTL_DEFAULT 0x00000000 -#define mmAOMCLK2_CNTL_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO2_PHASE_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO2_MODULO_DEFAULT 0x00000001 -#define mmDCE_VERSION_DEFAULT 0x00000000 -#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_GTC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_GTC_DTO_INCR_DEFAULT 0x00000000 -#define mmDCCG_GTC_DTO_MODULO_DEFAULT 0x00000000 -#define mmDCCG_GTC_CURRENT_DEFAULT 0x00000000 -#define mmDENTIST_DISPCLK_CNTL_DEFAULT 0x64010064 -#define mmMIPI_DTO_CNTL_DEFAULT 0x00000000 -#define mmMIPI_DTO_PHASE_DEFAULT 0x00000000 -#define mmMIPI_DTO_MODULO_DEFAULT 0x00000000 -#define mmDAC_CLK_ENABLE_DEFAULT 0x00000000 -#define mmDVO_CLK_ENABLE_DEFAULT 0x00000000 -#define mmAVSYNC_COUNTER_WRITE_DEFAULT 0x00000000 -#define mmAVSYNC_COUNTER_CONTROL_DEFAULT 0x00000000 -#define mmDMCU_SMU_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmSMU_CONTROL_DEFAULT 0x00000000 -#define mmSMU_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmAVSYNC_COUNTER_READ_DEFAULT 0x00000000 -#define mmMILLISECOND_TIME_BASE_DIV_DEFAULT 0x001186a0 -#define mmDISPCLK_FREQ_CHANGE_CNTL_DEFAULT 0x08010028 -#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x00000001 -#define mmDCCG_PERFMON_CNTL_DEFAULT 0xfffff800 -#define mmDCCG_GATE_DISABLE_CNTL_DEFAULT 0x74ee00fd -#define mmDISPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmSCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmDCCG_CAC_STATUS_DEFAULT 0x00000000 -#define mmPIXCLK1_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPIXCLK2_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPIXCLK0_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmMICROSECOND_TIME_BASE_DIV_DEFAULT 0x00120464 -#define mmDCCG_GATE_DISABLE_CNTL2_DEFAULT 0x037f037f -#define mmSYMCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_DISP_CNTL_REG_DEFAULT 0x00000000 -#define mmCRTC0_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO0_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO0_MODULO_DEFAULT 0x00000000 -#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO1_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO1_MODULO_DEFAULT 0x00000000 -#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO2_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO2_MODULO_DEFAULT 0x00000000 -#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO3_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO3_MODULO_DEFAULT 0x00000000 -#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO4_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO4_MODULO_DEFAULT 0x00000000 -#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO5_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO5_MODULO_DEFAULT 0x00000000 -#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCCG_SOFT_RESET_DEFAULT 0x00000000 -#define mmSYMCLKA_CLOCK_ENABLE_DEFAULT 0x00000000 -#define mmSYMCLKB_CLOCK_ENABLE_DEFAULT 0x00000100 -#define mmSYMCLKC_CLOCK_ENABLE_DEFAULT 0x00000200 -#define mmSYMCLKD_CLOCK_ENABLE_DEFAULT 0x00000300 -#define mmSYMCLKE_CLOCK_ENABLE_DEFAULT 0x00000400 -#define mmSYMCLKF_CLOCK_ENABLE_DEFAULT 0x00000500 -#define mmDVOACLKD_CNTL_DEFAULT 0x00070000 -#define mmDVOACLKC_MVP_CNTL_DEFAULT 0x00030000 -#define mmDVOACLKC_CNTL_DEFAULT 0x00030000 -#define mmDCCG_AUDIO_DTO_SOURCE_DEFAULT 0x00000030 -#define mmDCCG_AUDIO_DTO0_PHASE_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO0_MODULE_DEFAULT 0x00000001 -#define mmDCCG_AUDIO_DTO1_PHASE_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO1_MODULE_DEFAULT 0x00000001 -#define mmDCCG_TEST_CLK_SEL_DEFAULT 0x01ff01ff -#define mmFBC_CNTL_DEFAULT 0x00000500 -#define mmFBC_IDLE_FORCE_CLEAR_MASK_DEFAULT 0x00000000 -#define mmFBC_START_STOP_DELAY_DEFAULT 0x00000000 -#define mmFBC_COMP_CNTL_DEFAULT 0x0000000f -#define mmFBC_COMP_MODE_DEFAULT 0x00000000 -#define mmFBC_IND_LUT0_DEFAULT 0x00000000 -#define mmFBC_IND_LUT1_DEFAULT 0x00000000 -#define mmFBC_IND_LUT2_DEFAULT 0x00000000 -#define mmFBC_IND_LUT3_DEFAULT 0x00000000 -#define mmFBC_IND_LUT4_DEFAULT 0x00000000 -#define mmFBC_IND_LUT5_DEFAULT 0x00000000 -#define mmFBC_IND_LUT6_DEFAULT 0x00000000 -#define mmFBC_IND_LUT7_DEFAULT 0x00000000 -#define mmFBC_IND_LUT8_DEFAULT 0x00000000 -#define mmFBC_IND_LUT9_DEFAULT 0x00000000 -#define mmFBC_IND_LUT10_DEFAULT 0x00000000 -#define mmFBC_IND_LUT11_DEFAULT 0x00000000 -#define mmFBC_IND_LUT12_DEFAULT 0x00000000 -#define mmFBC_IND_LUT13_DEFAULT 0x00000000 -#define mmFBC_IND_LUT14_DEFAULT 0x00000000 -#define mmFBC_IND_LUT15_DEFAULT 0x00000000 -#define mmFBC_CSM_REGION_OFFSET_01_DEFAULT 0x00000000 -#define mmFBC_CSM_REGION_OFFSET_23_DEFAULT 0x00000000 -#define mmFBC_CLIENT_REGION_MASK_DEFAULT 0x00000000 -#define mmFBC_DEBUG_COMP_DEFAULT 0x00000000 -#define mmFBC_MISC_DEFAULT 0x0c306008 -#define mmFBC_STATUS_DEFAULT 0x00000000 -#define mmFBC_ALPHA_CNTL_DEFAULT 0x00000000 -#define mmFBC_ALPHA_RGB_OVERRIDE_DEFAULT 0x00000000 -#define mmPIPE0_PG_CONFIG_DEFAULT 0x00000001 -#define mmPIPE0_PG_ENABLE_DEFAULT 0x00000000 -#define mmPIPE0_PG_STATUS_DEFAULT 0x00000000 -#define mmPIPE1_PG_CONFIG_DEFAULT 0x00000001 -#define mmPIPE1_PG_ENABLE_DEFAULT 0x00000000 -#define mmPIPE1_PG_STATUS_DEFAULT 0x00000000 -#define mmPIPE2_PG_CONFIG_DEFAULT 0x00000001 -#define mmPIPE2_PG_ENABLE_DEFAULT 0x00000000 -#define mmPIPE2_PG_STATUS_DEFAULT 0x00000000 -#define mmPIPE3_PG_CONFIG_DEFAULT 0x00000001 -#define mmPIPE3_PG_ENABLE_DEFAULT 0x00000000 -#define mmPIPE3_PG_STATUS_DEFAULT 0x00000000 -#define mmPIPE4_PG_CONFIG_DEFAULT 0x00000001 -#define mmPIPE4_PG_ENABLE_DEFAULT 0x00000000 -#define mmPIPE4_PG_STATUS_DEFAULT 0x00000000 -#define mmPIPE5_PG_CONFIG_DEFAULT 0x00000001 -#define mmPIPE5_PG_ENABLE_DEFAULT 0x00000000 -#define mmPIPE5_PG_STATUS_DEFAULT 0x00000000 -#define mmDSI_PG_CONFIG_DEFAULT 0x00000001 -#define mmDSI_PG_ENABLE_DEFAULT 0x00000000 -#define mmDSI_PG_STATUS_DEFAULT 0x00000000 -#define mmDCFEV0_PG_CONFIG_DEFAULT 0x00000001 -#define mmDCFEV0_PG_ENABLE_DEFAULT 0x00000000 -#define mmDCFEV0_PG_STATUS_DEFAULT 0x00000000 -#define mmDCPG_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCPG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCPG_INTERRUPT_CONTROL2_DEFAULT 0x00000000 -#define mmDCFEV1_PG_CONFIG_DEFAULT 0x00000001 -#define mmDCFEV1_PG_ENABLE_DEFAULT 0x00000000 -#define mmDCFEV1_PG_STATUS_DEFAULT 0x00000000 -#define mmDC_IP_REQUEST_CNTL_DEFAULT 0x00000000 -#define mmDC_PGCNTL_STATUS_REG_DEFAULT 0x00000000 -#define mmDMIFV_STATUS_DEFAULT 0x00000000 -#define mmDMIF_CONTROL_DEFAULT 0x00000c04 -#define mmDMIF_STATUS_DEFAULT 0x0ff00000 -#define mmDMIF_ARBITRATION_CONTROL_DEFAULT 0x00042710 -#define mmPIPE0_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE1_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE2_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE3_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE4_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE5_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmDMIF_P_VMID_DEFAULT 0x00000000 -#define mmDMIF_ADDR_CALC_DEFAULT 0x00000000 -#define mmDMIF_STATUS2_DEFAULT 0x00000000 -#define mmPIPE0_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmPIPE1_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmPIPE2_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmPIPE3_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmPIPE4_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmPIPE5_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmLOW_POWER_TILING_CONTROL_DEFAULT 0x00001000 -#define mmMCIF_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WRITE_COMBINE_CONTROL_DEFAULT 0x00000080 -#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmCC_DC_PIPE_DIS_DEFAULT 0x00000000 -#define mmSMU_WM_CONTROL_DEFAULT 0x00000000 -#define mmRBBMIF_TIMEOUT_DEFAULT 0x20000a00 -#define mmRBBMIF_STATUS_DEFAULT 0x80000000 -#define mmRBBMIF_TIMEOUT_DIS_DEFAULT 0x00000000 -#define mmDCI_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCI_MEM_PWR_STATUS2_DEFAULT 0x00000000 -#define mmDCI_CLK_CNTL_DEFAULT 0x00000000 -#define mmDCI_CLK_CNTL2_DEFAULT 0x00020020 -#define mmDCI_MEM_PWR_CNTL_DEFAULT 0x00000000 -#define mmDCI_MEM_PWR_CNTL2_DEFAULT 0x00000000 -#define mmDCI_MEM_PWR_CNTL3_DEFAULT 0x00000000 -#define mmPIPE0_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmPIPE1_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmPIPE2_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmPIPE3_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmPIPE4_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmPIPE5_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmRBBMIF_STATUS_FLAG_DEFAULT 0x00000000 -#define mmDCI_SOFT_RESET_DEFAULT 0x00000000 -#define mmDMIF_URG_OVERRIDE_DEFAULT 0x00000000 -#define mmPIPE6_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE7_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE6_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmPIPE7_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmDVMM_REG_RD_STATUS_DEFAULT 0x00000000 -#define mmDVMM_REG_RD_DATA_DEFAULT 0x00000000 -#define mmDVMM_PTE_REQ_DEFAULT 0x000120ff -#define mmDVMM_CNTL_DEFAULT 0x00000000 -#define mmDVMM_FAULT_STATUS_DEFAULT 0x00000000 -#define mmDVMM_FAULT_ADDR_DEFAULT 0x00000000 -#define mmFMON_CTRL_DEFAULT 0x0000f040 -#define mmDVMM_PTE_PGMEM_CONTROL_DEFAULT 0x00000000 -#define mmDVMM_PTE_PGMEM_STATE_DEFAULT 0x00000000 -#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmDCI_MEM_PWR_CNTL4_DEFAULT 0x0000003f -#define mmMCIF_WB_MISC_CTRL_DEFAULT 0x00010001 -#define mmDCI_MEM_PWR_STATUS3_DEFAULT 0x00000000 -#define mmDMIF_CURSOR_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_CURSOR_MEM_CONTROL_DEFAULT 0x00000000 -#define mmDCHUB_FB_LOCATION_DEFAULT 0x00000000 -#define mmDCHUB_FB_OFFSET_DEFAULT 0x00000000 -#define mmDCHUB_AGP_BASE_DEFAULT 0x00000000 -#define mmDCHUB_AGP_BOT_DEFAULT 0x00000000 -#define mmDCHUB_AGP_TOP_DEFAULT 0x00000000 -#define mmDCHUB_DRAM_APER_BASE_DEFAULT 0x00000000 -#define mmDCHUB_DRAM_APER_DEF_DEFAULT 0x00000000 -#define mmDCHUB_DRAM_APER_TOP_DEFAULT 0x00000000 -#define mmDCHUB_CONTROL_STATUS_DEFAULT 0x00c00000 -#define mmWB_ENABLE_DEFAULT 0x00000000 -#define mmWB_EC_CONFIG_DEFAULT 0x55000000 -#define mmCNV_MODE_DEFAULT 0x00000000 -#define mmCNV_WINDOW_START_DEFAULT 0x00000000 -#define mmCNV_WINDOW_SIZE_DEFAULT 0x00100010 -#define mmCNV_UPDATE_DEFAULT 0x00000000 -#define mmCNV_SOURCE_SIZE_DEFAULT 0x00100010 -#define mmCNV_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCNV_CSC_C11_C12_DEFAULT 0x00000000 -#define mmCNV_CSC_C13_C14_DEFAULT 0x00000000 -#define mmCNV_CSC_C21_C22_DEFAULT 0x00000000 -#define mmCNV_CSC_C23_C24_DEFAULT 0x00000000 -#define mmCNV_CSC_C31_C32_DEFAULT 0x00000000 -#define mmCNV_CSC_C33_C34_DEFAULT 0x00000000 -#define mmCNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000 -#define mmCNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000 -#define mmCNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000 -#define mmCNV_CSC_CLAMP_R_DEFAULT 0x00000fff -#define mmCNV_CSC_CLAMP_G_DEFAULT 0x00000fff -#define mmCNV_CSC_CLAMP_B_DEFAULT 0x00000fff -#define mmCNV_TEST_CNTL_DEFAULT 0x00000000 -#define mmCNV_TEST_CRC_RED_DEFAULT 0x0000fff0 -#define mmCNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0 -#define mmCNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0 -#define mmCNV_INPUT_SELECT_DEFAULT 0x00000000 -#define mmWB_SOFT_RESET_DEFAULT 0x00000000 -#define mmWB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100 -#define mmWB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100 -#define mmWBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmWBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmWBSCL_MODE_DEFAULT 0x00000000 -#define mmWBSCL_TAP_CONTROL_DEFAULT 0x00001111 -#define mmWBSCL_DEST_SIZE_DEFAULT 0x00010001 -#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000 -#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 -#define mmWBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000 -#define mmWBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000 -#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 -#define mmWBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000 -#define mmWBSCL_ROUND_OFFSET_DEFAULT 0x00800010 -#define mmWBSCL_CLAMP_DEFAULT 0x01fe01fe -#define mmWBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000 -#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmWBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000 -#define mmWBSCL_TEST_CNTL_DEFAULT 0x00000000 -#define mmWBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00 -#define mmWBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff -#define mmWBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00 -#define mmWBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000 -#define mmWB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000 -#define mmWBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000 -#define mmDMCU_CTRL_DEFAULT 0xffff0101 -#define mmDMCU_STATUS_DEFAULT 0x00000001 -#define mmDMCU_PC_START_ADDR_DEFAULT 0x00000000 -#define mmDMCU_FW_START_ADDR_DEFAULT 0x00000000 -#define mmDMCU_FW_END_ADDR_DEFAULT 0x00000000 -#define mmDMCU_FW_ISR_START_ADDR_DEFAULT 0x00000004 -#define mmDMCU_FW_CS_HI_DEFAULT 0x00000000 -#define mmDMCU_FW_CS_LO_DEFAULT 0x00000000 -#define mmDMCU_RAM_ACCESS_CTRL_DEFAULT 0x00000000 -#define mmDMCU_ERAM_WR_CTRL_DEFAULT 0x000f0000 -#define mmDMCU_ERAM_WR_DATA_DEFAULT 0x00000000 -#define mmDMCU_ERAM_RD_CTRL_DEFAULT 0x000f0000 -#define mmDMCU_ERAM_RD_DATA_DEFAULT 0x00000000 -#define mmDMCU_IRAM_WR_CTRL_DEFAULT 0x00000000 -#define mmDMCU_IRAM_WR_DATA_DEFAULT 0x00000000 -#define mmDMCU_IRAM_RD_CTRL_DEFAULT 0x00000000 -#define mmDMCU_IRAM_RD_DATA_DEFAULT 0x00000000 -#define mmDMCU_EVENT_TRIGGER_DEFAULT 0x00000000 -#define mmDMCU_UC_INTERNAL_INT_STATUS_DEFAULT 0x00000000 -#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_DEFAULT 0x00000000 -#define mmDC_DMCU_SCRATCH_DEFAULT 0x00000000 -#define mmDMCU_INT_CNT_DEFAULT 0x00000000 -#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_DEFAULT 0x00000000 -#define mmDMCU_UC_CLK_GATING_CNTL_DEFAULT 0x00010102 -#define mmMASTER_COMM_DATA_REG1_DEFAULT 0x00000000 -#define mmMASTER_COMM_DATA_REG2_DEFAULT 0x00000000 -#define mmMASTER_COMM_DATA_REG3_DEFAULT 0x00000000 -#define mmMASTER_COMM_CMD_REG_DEFAULT 0x00000000 -#define mmMASTER_COMM_CNTL_REG_DEFAULT 0x00000000 -#define mmSLAVE_COMM_DATA_REG1_DEFAULT 0x00000000 -#define mmSLAVE_COMM_DATA_REG2_DEFAULT 0x00000000 -#define mmSLAVE_COMM_DATA_REG3_DEFAULT 0x00000000 -#define mmSLAVE_COMM_CMD_REG_DEFAULT 0x00000000 -#define mmSLAVE_COMM_CNTL_REG_DEFAULT 0x00000000 -#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000 -#define mmBL1_PWM_USER_LEVEL_DEFAULT 0x00000000 -#define mmBL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000 -#define mmBL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000 -#define mmBL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000 -#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000 -#define mmBL1_PWM_ABM_CNTL_DEFAULT 0x00000000 -#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmBL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_STATUS_1_DEFAULT 0x00000000 -#define mmDMCU_DPRX_INTERRUPT_STATUS1_DEFAULT 0x00000000 -#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000 -#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000 -#define mmDC_ABM1_CNTL_DEFAULT 0x00000000 -#define mmDC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000 -#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400 -#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400 -#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400 -#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400 -#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400 -#define mmDC_ABM1_ACE_THRES_12_DEFAULT 0x00000000 -#define mmDC_ABM1_ACE_THRES_34_DEFAULT 0x00000000 -#define mmDC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS5_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS1_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS2_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS3_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS4_DEFAULT 0x00000000 -#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_OVR_SCAN_BIN_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_1_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_2_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_3_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_4_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_5_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_6_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_7_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_8_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_9_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_10_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_11_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_12_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_13_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_14_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_15_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_16_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_17_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_18_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_19_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_20_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_21_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_22_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_23_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_24_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_DEFAULT 0x00000000 -#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_DEFAULT 0x00000000 -#define mmDC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000 -#define mmAZALIA_CONTROLLER_CLOCK_GATING_DEFAULT 0x00000000 -#define mmAZALIA_AUDIO_DTO_DEFAULT 0x001b0018 -#define mmAZALIA_AUDIO_DTO_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_SOCCLK_CONTROL_DEFAULT 0x00000001 -#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_DEFAULT 0x00000000 -#define mmAZALIA_DATA_DMA_CONTROL_DEFAULT 0x0000000a -#define mmAZALIA_BDL_DMA_CONTROL_DEFAULT 0x0000000a -#define mmAZALIA_RIRB_AND_DP_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_CORB_DMA_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_DEFAULT 0x00000000 -#define mmAZALIA_CYCLIC_BUFFER_SYNC_DEFAULT 0x00000000 -#define mmAZALIA_GLOBAL_CAPABILITIES_DEFAULT 0x00000000 -#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000060 -#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_DEFAULT 0x00080008 -#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000080 -#define mmAZALIA_INPUT_CRC0_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmAZALIA_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x1002aa01 -#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00100700 -#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_DEFAULT 0x0000000d -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000001 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0xc0000009 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000200 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00aa0100 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000 -#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET0_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET1_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET2_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET3_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET4_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET5_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET6_DEFAULT 0x00000000 -#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmDAC_ENABLE_DEFAULT 0x00000004 -#define mmDAC_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmDAC_CRC_EN_DEFAULT 0x00000000 -#define mmDAC_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDAC_CRC_SIG_RGB_MASK_DEFAULT 0x3fffffff -#define mmDAC_CRC_SIG_CONTROL_MASK_DEFAULT 0x0000003f -#define mmDAC_CRC_SIG_RGB_DEFAULT 0x3fffffff -#define mmDAC_CRC_SIG_CONTROL_DEFAULT 0x0000003f -#define mmDAC_SYNC_TRISTATE_CONTROL_DEFAULT 0x00000000 -#define mmDAC_STEREOSYNC_SELECT_DEFAULT 0x00000000 -#define mmDAC_AUTODETECT_CONTROL_DEFAULT 0x00070000 -#define mmDAC_AUTODETECT_CONTROL2_DEFAULT 0x0000000b -#define mmDAC_AUTODETECT_CONTROL3_DEFAULT 0x00000519 -#define mmDAC_AUTODETECT_STATUS_DEFAULT 0x00000000 -#define mmDAC_AUTODETECT_INT_CONTROL_DEFAULT 0x00000000 -#define mmDAC_FORCE_OUTPUT_CNTL_DEFAULT 0x00000000 -#define mmDAC_FORCE_DATA_DEFAULT 0x000001e6 -#define mmDAC_POWERDOWN_DEFAULT 0x01010100 -#define mmDAC_CONTROL_DEFAULT 0x00000000 -#define mmDAC_COMPARATOR_ENABLE_DEFAULT 0x00000000 -#define mmDAC_COMPARATOR_OUTPUT_DEFAULT 0x00000000 -#define mmDAC_PWR_CNTL_DEFAULT 0x00000000 -#define mmDAC_DFT_CONFIG_DEFAULT 0x00000000 -#define mmDAC_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_CONTROL_DEFAULT 0x00000000 -#define mmDC_I2C_ARBITRATION_DEFAULT 0x00000001 -#define mmDC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDC_I2C_SW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC1_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC2_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC3_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC4_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC5_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC6_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC1_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC1_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC2_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC2_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC3_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC3_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC4_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC4_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC5_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC5_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC6_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC6_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION0_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION1_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION2_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION3_DEFAULT 0x00000000 -#define mmDC_I2C_DATA_DEFAULT 0x00000000 -#define mmDC_I2C_DDCVGA_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDCVGA_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDCVGA_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_EDID_DETECT_CTRL_DEFAULT 0x004001f4 -#define mmDC_I2C_READ_REQUEST_INTERRUPT_DEFAULT 0x40000000 -#define mmGENERIC_I2C_CONTROL_DEFAULT 0x00000000 -#define mmGENERIC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmGENERIC_I2C_STATUS_DEFAULT 0x00000000 -#define mmGENERIC_I2C_SPEED_DEFAULT 0x00000002 -#define mmGENERIC_I2C_SETUP_DEFAULT 0x00000000 -#define mmGENERIC_I2C_TRANSACTION_DEFAULT 0x00000000 -#define mmGENERIC_I2C_DATA_DEFAULT 0x00000000 -#define mmGENERIC_I2C_PIN_SELECTION_DEFAULT 0x00000000 -#define mmDCO_SCRATCH0_DEFAULT 0x00000000 -#define mmDCO_SCRATCH1_DEFAULT 0x00000000 -#define mmDCO_SCRATCH2_DEFAULT 0x00000000 -#define mmDCO_SCRATCH3_DEFAULT 0x00000000 -#define mmDCO_SCRATCH4_DEFAULT 0x00000000 -#define mmDCO_SCRATCH5_DEFAULT 0x00000000 -#define mmDCO_SCRATCH6_DEFAULT 0x00000000 -#define mmDCO_SCRATCH7_DEFAULT 0x00000000 -#define mmDCE_VCE_CONTROL_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE2_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE3_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE4_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE5_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE6_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE7_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE8_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE9_DEFAULT 0x00000000 -#define mmDCO_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCO_MEM_PWR_CTRL_DEFAULT 0x6db6d800 -#define mmDCO_MEM_PWR_CTRL2_DEFAULT 0x001b0000 -#define mmDCO_CLK_CNTL_DEFAULT 0x00000000 -#define mmDCO_POWER_MANAGEMENT_CNTL_DEFAULT 0x00000000 -#define mmDIG_SOFT_RESET_2_DEFAULT 0x00000000 -#define mmDCO_STEREOSYNC_SEL_DEFAULT 0x00000000 -#define mmDCO_SOFT_RESET_DEFAULT 0x00000000 -#define mmDIG_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCO_MEM_PWR_STATUS1_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE10_DEFAULT 0x00000000 -#define mmDCO_CLK_CNTL2_DEFAULT 0x00000000 -#define mmDCO_CLK_CNTL3_DEFAULT 0x00000000 -#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_DEFAULT 0x00000000 -#define mmDCO_PSP_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCO_PSP_INTERRUPT_CLEAR_DEFAULT 0x00000000 -#define mmDCO_GENERIC_INTERRUPT_MESSAGE_DEFAULT 0x00000000 -#define mmDCO_GENERIC_INTERRUPT_CLEAR_DEFAULT 0x00000000 -#define mmFMT_MEMORY0_CONTROL_DEFAULT 0x00000030 -#define mmFMT_MEMORY1_CONTROL_DEFAULT 0x00000031 -#define mmFMT_MEMORY2_CONTROL_DEFAULT 0x00000032 -#define mmFMT_MEMORY3_CONTROL_DEFAULT 0x00000033 -#define mmFMT_MEMORY4_CONTROL_DEFAULT 0x00000034 -#define mmFMT_MEMORY5_CONTROL_DEFAULT 0x00000035 -#define mmDISP_INTERRUPT_STATUS_CONTINUE11_DEFAULT 0x00000000 -#define mmDC_GENERICA_DEFAULT 0x00000000 -#define mmDC_GENERICB_DEFAULT 0x00000000 -#define mmDC_PAD_EXTERN_SIG_DEFAULT 0x00000000 -#define mmDC_REF_CLK_CNTL_DEFAULT 0x00000000 -#define mmDC_GPIO_DEBUG_DEFAULT 0x00000101 -#define mmUNIPHYA_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYB_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYC_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYC_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYD_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYD_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYE_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYE_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYF_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYF_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYG_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYG_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmDCIO_WRCMD_DELAY_DEFAULT 0x00033333 -#define mmDC_DVODATA_CONFIG_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_CNTL_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_STATE_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_REF_DIV_DEFAULT 0x00010000 -#define mmLVTMA_PWRSEQ_DELAY1_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_DELAY2_DEFAULT 0x00000000 -#define mmBL_PWM_CNTL_DEFAULT 0x00000000 -#define mmBL_PWM_CNTL2_DEFAULT 0x00000000 -#define mmBL_PWM_PERIOD_CNTL_DEFAULT 0x00000001 -#define mmBL_PWM_GRP1_REG_LOCK_DEFAULT 0x00000000 -#define mmDCIO_GSL_GENLK_PAD_CNTL_DEFAULT 0x00000000 -#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_DEFAULT 0x00000000 -#define mmDCIO_GSL0_CNTL_DEFAULT 0x00000000 -#define mmDCIO_GSL1_CNTL_DEFAULT 0x00000000 -#define mmDCIO_GSL2_CNTL_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_READ_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_READ_CNTL_DEFAULT 0x00000000 -#define mmDCIO_CLOCK_CNTL_DEFAULT 0x00000000 -#define mmDCO_DCFE_EXT_VSYNC_CNTL_DEFAULT 0x00000000 -#define mmDCIO_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCIO_DPHY_SEL_DEFAULT 0x000000e4 -#define mmUNIPHY_IMPCAL_LINKA_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_LINKB_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_PERIOD_DEFAULT 0x00000000 -#define mmAUXP_IMPCAL_DEFAULT 0x0a000000 -#define mmAUXN_IMPCAL_DEFAULT 0x04000000 -#define mmDCIO_IMPCAL_CNTL_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_PSW_AB_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_LINKC_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_LINKD_DEFAULT 0x0f000000 -#define mmDCIO_IMPCAL_CNTL_CD_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_PSW_CD_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_LINKE_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_LINKF_DEFAULT 0x0f000000 -#define mmDCIO_IMPCAL_CNTL_EF_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_PSW_EF_DEFAULT 0x00000000 -#define mmUNIPHYLPA_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYLPB_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmDCIO_DPCS_TX_INTERRUPT_DEFAULT 0x00000000 -#define mmDCIO_DPCS_RX_INTERRUPT_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE0_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE1_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE2_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE3_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE4_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE5_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE6_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE7_DEFAULT 0x00000000 -#define mmDC_GPIO_GENERIC_MASK_DEFAULT 0x04444444 -#define mmDC_GPIO_GENERIC_A_DEFAULT 0x00000000 -#define mmDC_GPIO_GENERIC_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_GENERIC_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_MASK_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC1_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC1_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC1_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC1_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC2_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC2_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC2_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC2_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC3_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC3_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC3_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC3_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC4_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC4_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC4_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC4_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC5_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC5_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC5_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC5_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC6_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC6_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC6_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC6_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDCVGA_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDCVGA_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDCVGA_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDCVGA_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_SYNCA_MASK_DEFAULT 0x00004040 -#define mmDC_GPIO_SYNCA_A_DEFAULT 0x00000000 -#define mmDC_GPIO_SYNCA_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_SYNCA_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_GENLK_MASK_DEFAULT 0x10101a10 -#define mmDC_GPIO_GENLK_A_DEFAULT 0x00000000 -#define mmDC_GPIO_GENLK_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_GENLK_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_HPD_MASK_DEFAULT 0x44440440 -#define mmDC_GPIO_HPD_A_DEFAULT 0x00000000 -#define mmDC_GPIO_HPD_EN_DEFAULT 0x22220202 -#define mmDC_GPIO_HPD_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_PWRSEQ_MASK_DEFAULT 0x66404040 -#define mmDC_GPIO_PWRSEQ_A_DEFAULT 0x00000000 -#define mmDC_GPIO_PWRSEQ_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_PWRSEQ_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_PAD_STRENGTH_1_DEFAULT 0x47ac470f -#define mmDC_GPIO_PAD_STRENGTH_2_DEFAULT 0x00472147 -#define mmPHY_AUX_CNTL_DEFAULT 0x00010001 -#define mmDC_GPIO_I2CPAD_MASK_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_A_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_STRENGTH_DEFAULT 0x0000004c -#define mmDVO_STRENGTH_CONTROL_DEFAULT 0x31116060 -#define mmDVO_VREF_CONTROL_DEFAULT 0x00000000 -#define mmDVO_SKEW_ADJUST_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_MASK_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_A_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_EN_DEFAULT 0x00008000 -#define mmDC_GPIO_I2S_SPDIF_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_STRENGTH_DEFAULT 0x01021202 -#define mmDC_GPIO_TX12_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_AUX_CTRL_0_DEFAULT 0x00000000 -#define mmDC_GPIO_AUX_CTRL_1_DEFAULT 0x00500000 -#define mmDC_GPIO_AUX_CTRL_2_DEFAULT 0x00000000 -#define mmDC_GPIO_RXEN_DEFAULT 0x007fff7f -#define mmBPHYC_DAC_MACRO_CNTL_DEFAULT 0x00202002 -#define mmDAC_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_DEFAULT 0x00700255 -#define mmDAC_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDAC_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDAC_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDISP_DSI_DUAL_CTRL_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDPRX_AUX_REFERENCE_PULSE_DIV_DEFAULT 0x0a640064 -#define mmDPRX_AUX_CONTROL_DEFAULT 0x01012c00 -#define mmDPRX_AUX_HPD_CONTROL1_DEFAULT 0x00001407 -#define mmDPRX_AUX_HPD_CONTROL2_DEFAULT 0x00000000 -#define mmDPRX_AUX_RX_STATUS_DEFAULT 0x00000000 -#define mmDPRX_AUX_RX_ERROR_MASK_DEFAULT 0x00000000 -#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDPRX_AUX_DPHY_TX_CONTROL_DEFAULT 0x00001002 -#define mmDPRX_AUX_DPHY_RX_CONTROL0_DEFAULT 0x203d1210 -#define mmDPRX_AUX_DPHY_RX_CONTROL1_DEFAULT 0x0a00fa00 -#define mmDPRX_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDPRX_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDPRX_AUX_DMCU_HW_INT_STATUS_DEFAULT 0x00003f00 -#define mmDPRX_AUX_DMCU_HW_INT_ACK_DEFAULT 0x00000000 -#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_DEFAULT 0x00000000 -#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_DEFAULT 0x00000001 -#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_DEFAULT 0x00000000 -#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_DEFAULT 0x00000000 -#define mmDPRX_AUX_AUX_BUF_INDEX_DEFAULT 0x00000000 -#define mmDPRX_AUX_AUX_BUF_DATA_DEFAULT 0x00000000 -#define mmDPRX_AUX_EDID_INDEX_DEFAULT 0x00000000 -#define mmDPRX_AUX_EDID_DATA_DEFAULT 0x00000000 -#define mmDPRX_AUX_DPCD_INDEX1_DEFAULT 0x00000000 -#define mmDPRX_AUX_DPCD_DATA1_DEFAULT 0x00000000 -#define mmDPRX_AUX_DPCD_INDEX2_DEFAULT 0x00000000 -#define mmDPRX_AUX_DPCD_DATA2_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG_INDEX1_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG_DATA1_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG_INDEX2_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG_DATA2_DEFAULT 0x00000000 -#define mmDPRX_AUX_KSV_INDEX1_DEFAULT 0x00000000 -#define mmDPRX_AUX_KSV_DATA1_DEFAULT 0x00000000 -#define mmDPRX_AUX_KSV_INDEX2_DEFAULT 0x00000000 -#define mmDPRX_AUX_KSV_DATA2_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_DEFAULT 0x00000032 -#define mmDPRX_AUX_MSG_BUF_CONTROL1_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG_BUF_CONTROL2_DEFAULT 0x00000000 -#define mmDPRX_AUX_SCRATCH1_DEFAULT 0x00000000 -#define mmDPRX_AUX_SCRATCH2_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG1_PENDING_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG2_PENDING_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG3_PENDING_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG4_PENDING_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_DEFAULT 0x00000003 -#define mmDPRX_DPHY_DPCD_MSTM_CTRL_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_DEFAULT 0x20000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_DEFAULT 0x20000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_DEFAULT 0x20000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_DEFAULT 0x20000000 -#define mmDPRX_DPHY_READY_DEFAULT 0x00000000 -#define mmDPRX_DPHY_COMMA_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_DEFAULT 0x00000000 -#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_DEFAULT 0x00000000 -#define mmDPRX_DPHY_SR_ERROR_COUNT_A_DEFAULT 0x00000000 -#define mmDPRX_DPHY_BS_ERROR_COUNT_A_DEFAULT 0x00000000 -#define mmDPRX_DPHY_BS_ERROR_COUNT_B_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LANESETUP0_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LANESETUP1_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LFSRADV_DEFAULT 0x00000039 -#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_DEFAULT 0x00000000 -#define mmDPRX_DPHY_SET_ENABLE_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ECF_LSB_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ECF_MSB_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ENHANCED_FRAME_EN_DEFAULT 0x00000001 -#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_DEFAULT 0x000a6800 -#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_DEFAULT 0xbcbcbcbc -#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_DEFAULT 0x800071c5 -#define mmDPRX_DPHY_BYPASS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_INT_RESET_DEFAULT 0x00000000 -#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_SPARE_DEFAULT 0x00000000 -#define mmDCRX_GATE_DISABLE_CNTL_DEFAULT 0x00001f0f -#define mmDCRX_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCRX_LIGHT_SLEEP_CNTL_DEFAULT 0x00000101 -#define mmDCRX_DISPCLK_GATE_CNTL_DEFAULT 0x00000200 -#define mmDCRX_CLK_CNTL_DEFAULT 0x00000000 -#define mmDCRX_TEST_CLK_CNTL_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED160_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED161_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED162_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED163_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED164_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED165_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED166_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED167_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED168_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED169_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED170_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED171_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED172_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED173_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED174_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED175_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED176_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED177_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED178_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED179_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED180_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED181_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED182_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED183_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED184_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED185_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED186_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED187_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED188_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED189_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED190_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED191_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED192_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED193_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED194_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED195_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED196_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED197_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED198_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED199_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED200_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED201_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED202_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED203_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED204_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED205_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED206_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED207_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED208_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED209_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED210_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED211_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED212_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED213_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED214_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED215_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED216_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED217_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED218_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED219_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED220_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED221_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED222_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED223_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED224_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED225_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED226_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED227_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED228_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED229_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED230_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED231_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED232_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED233_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED234_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED235_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED236_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED237_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED238_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED239_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED240_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED241_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED242_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED243_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED244_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED245_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED246_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED247_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED248_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED249_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED250_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED251_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED252_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED253_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED254_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED255_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED256_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED257_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED258_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED259_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED260_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED261_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED262_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED263_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED264_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED265_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED266_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED267_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED268_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED269_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED270_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED271_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED272_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED273_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED274_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED275_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED276_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED277_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED278_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED279_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED280_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED281_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED282_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED283_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED284_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED285_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED286_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED287_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED288_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED289_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED290_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED291_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED292_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED293_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED294_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED295_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED296_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED297_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED298_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED299_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED300_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED301_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED302_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED303_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED304_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED305_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED306_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED307_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED308_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED309_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED310_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED311_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED312_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED313_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED314_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED315_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED316_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED317_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED318_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED319_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED320_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED321_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED322_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED323_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED324_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED325_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED326_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED327_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED328_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED329_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED330_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED331_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED332_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED333_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED334_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED335_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED336_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED337_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED338_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED339_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED340_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED341_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED342_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED343_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED344_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED345_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED346_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED347_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED348_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED349_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED350_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED351_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED352_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED353_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED354_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED355_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED356_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED357_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED358_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED359_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED360_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED361_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED362_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED363_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED364_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED365_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED366_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED367_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED368_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED369_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED370_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED371_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED372_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED373_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED374_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED375_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED376_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED377_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED378_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED379_DEFAULT 0x00000000 -#define mmI2S0_CNTL_DEFAULT 0x00010000 -#define mmSPDIF0_CNTL_DEFAULT 0x00000000 -#define mmI2S1_CNTL_DEFAULT 0x00010000 -#define mmSPDIF1_CNTL_DEFAULT 0x00000000 -#define mmI2S0_STATUS_DEFAULT 0x00000000 -#define mmI2S1_STATUS_DEFAULT 0x00000000 -#define mmI2S0_CRC_TEST_CNTL_DEFAULT 0x00000100 -#define mmI2S0_CRC_TEST_DATA_01_DEFAULT 0x00000000 -#define mmI2S0_CRC_TEST_DATA_23_DEFAULT 0x00000000 -#define mmI2S1_CRC_TEST_CNTL_DEFAULT 0x00000100 -#define mmI2S1_CRC_TEST_DATA_0_DEFAULT 0x00000000 -#define mmSPDIF0_CRC_TEST_CNTL_DEFAULT 0x00000100 -#define mmSPDIF0_CRC_TEST_DATA_0_DEFAULT 0x00000000 -#define mmSPDIF1_CRC_TEST_CNTL_DEFAULT 0x00000100 -#define mmSPDIF1_CRC_TEST_DATA_DEFAULT 0x00000000 -#define mmCRC_I2S_CONT_REPEAT_NUM_DEFAULT 0x00000000 -#define mmCRC_SPDIF_CONT_REPEAT_NUM_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream0_dispdec -#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM0_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream1_dispdec -#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM1_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream2_dispdec -#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM2_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream3_dispdec -#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM3_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream4_dispdec -#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM4_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream5_dispdec -#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM5_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream6_dispdec -#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM6_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream7_dispdec -#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM7_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint0_dispdec -#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint1_dispdec -#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint2_dispdec -#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint3_dispdec -#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint4_dispdec -#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint5_dispdec -#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint6_dispdec -#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint7_dispdec -#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream8_dispdec -#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM8_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream9_dispdec -#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM9_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream10_dispdec -#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM10_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream11_dispdec -#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM11_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream12_dispdec -#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM12_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream13_dispdec -#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM13_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream14_dispdec -#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM14_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream15_dispdec -#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM15_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint0_dispdec -#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint1_dispdec -#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint2_dispdec -#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint3_dispdec -#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint4_dispdec -#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint5_dispdec -#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint6_dispdec -#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint7_dispdec -#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcp0_dispdec -#define mmDCP0_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmDCP0_GRPH_CONTROL_DEFAULT 0x20002040 -#define mmDCP0_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_PITCH_DEFAULT 0x00000000 -#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 -#define mmDCP0_GRPH_X_START_DEFAULT 0x00000000 -#define mmDCP0_GRPH_Y_START_DEFAULT 0x00000000 -#define mmDCP0_GRPH_X_END_DEFAULT 0x00000000 -#define mmDCP0_GRPH_Y_END_DEFAULT 0x00000000 -#define mmDCP0_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmDCP0_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 -#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 -#define mmDCP0_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_GRPH_DFQ_STATUS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 -#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 -#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff -#define mmDCP0_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 -#define mmDCP0_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 -#define mmDCP0_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 -#define mmDCP0_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 -#define mmDCP0_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_INPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP0_INPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP0_INPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP0_INPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP0_INPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP0_INPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP0_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP0_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP0_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP0_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP0_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP0_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP0_DENORM_CONTROL_DEFAULT 0x00000003 -#define mmDCP0_OUT_ROUND_CONTROL_DEFAULT 0x0000000a -#define mmDCP0_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff -#define mmDCP0_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff -#define mmDCP0_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff -#define mmDCP0_KEY_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_KEY_RANGE_ALPHA_DEFAULT 0x00000000 -#define mmDCP0_KEY_RANGE_RED_DEFAULT 0x00000000 -#define mmDCP0_KEY_RANGE_GREEN_DEFAULT 0x00000000 -#define mmDCP0_KEY_RANGE_BLUE_DEFAULT 0x00000000 -#define mmDCP0_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmDCP0_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmDCP0_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmDCP0_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmDCP0_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmDCP0_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmDCP0_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 -#define mmDCP0_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmDCP0_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmDCP0_CUR_CONTROL_DEFAULT 0x00000810 -#define mmDCP0_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP0_CUR_SIZE_DEFAULT 0x00000000 -#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP0_CUR_POSITION_DEFAULT 0x00000000 -#define mmDCP0_CUR_HOT_SPOT_DEFAULT 0x00000000 -#define mmDCP0_CUR_COLOR1_DEFAULT 0x00000000 -#define mmDCP0_CUR_COLOR2_DEFAULT 0x00000000 -#define mmDCP0_CUR_UPDATE_DEFAULT 0x00000000 -#define mmDCP0_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 -#define mmDCP0_CUR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_RW_MODE_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP0_DC_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff -#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff -#define mmDCP0_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff -#define mmDCP0_DCP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_DCP_CRC_MASK_DEFAULT 0x00000000 -#define mmDCP0_DCP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmDCP0_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmDCP0_DCP_CRC_LAST_DEFAULT 0x00000000 -#define mmDCP0_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmDCP0_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCP0_DCP_GSL_CONTROL_DEFAULT 0x60000020 -#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 -#define mmDCP0_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 -#define mmDCP0_HW_ROTATION_DEFAULT 0x00000000 -#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 -#define mmDCP0_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP0_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP0_ALPHA_CONTROL_DEFAULT 0x00000002 -#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 -#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 -#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_lb0_dispdec -#define mmLB0_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLB0_LB_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLB0_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLB0_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLB0_LB_VLINE_START_END_DEFAULT 0x00000000 -#define mmLB0_LB_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLB0_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmLB0_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLB0_LB_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLB0_LB_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLB0_LB_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLB0_LB_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLB0_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLB0_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLB0_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLB0_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLB0_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLB0_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLB0_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLB0_LB_BUFFER_STATUS_DEFAULT 0x00000002 -#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 -#define mmLB0_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 -#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 -#define mmLB0_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 -#define mmLB0_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dcfe0_dispdec -#define mmDCFE0_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFE0_DCFE_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFE0_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFE0_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFE0_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFE0_DCFE_MISC_DEFAULT 0x00000001 -#define mmDCFE0_DCFE_FLUSH_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon3_dispdec -#define mmDC_PERFMON3_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON3_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmif_pg0_dispdec -#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 -#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_DVMM_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_scl0_dispdec -#define mmSCL0_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCL0_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCL0_SCL_MODE_DEFAULT 0x00000000 -#define mmSCL0_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL0_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL0_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL0_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL0_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCL0_SCL_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCL0_SCL_UPDATE_DEFAULT 0x00000000 -#define mmSCL0_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmSCL0_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCL0_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCL0_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCL0_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCL0_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCL0_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCL0_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blnd0_dispdec -#define mmBLND0_BLND_CONTROL_DEFAULT 0xff0220ff -#define mmBLND0_BLND_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLND0_BLND_CONTROL2_DEFAULT 0x00000010 -#define mmBLND0_BLND_UPDATE_DEFAULT 0x00000000 -#define mmBLND0_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLND0_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLND0_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtc0_dispdec -#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTC0_CRTC_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VBI_END_DEFAULT 0x00000003 -#define mmCRTC0_CRTC_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CONTROL_DEFAULT 0x80400110 -#define mmCRTC0_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTC0_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTC0_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTC0_CRTC_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTC0_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_GSL_CONTROL_DEFAULT 0x00020000 -#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_DRR_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_fmt0_dispdec -#define mmFMT0_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT0_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT0_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT0_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT0_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT0_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT0_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT0_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT0_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT0_FMT_CRC_CNTL_DEFAULT 0x01000040 -#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff -#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff -#define mmFMT0_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 -#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 -#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT0_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcp1_dispdec -#define mmDCP1_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmDCP1_GRPH_CONTROL_DEFAULT 0x20002040 -#define mmDCP1_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_PITCH_DEFAULT 0x00000000 -#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 -#define mmDCP1_GRPH_X_START_DEFAULT 0x00000000 -#define mmDCP1_GRPH_Y_START_DEFAULT 0x00000000 -#define mmDCP1_GRPH_X_END_DEFAULT 0x00000000 -#define mmDCP1_GRPH_Y_END_DEFAULT 0x00000000 -#define mmDCP1_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmDCP1_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 -#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 -#define mmDCP1_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_GRPH_DFQ_STATUS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 -#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 -#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff -#define mmDCP1_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 -#define mmDCP1_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 -#define mmDCP1_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 -#define mmDCP1_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 -#define mmDCP1_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_INPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP1_INPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP1_INPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP1_INPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP1_INPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP1_INPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP1_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP1_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP1_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP1_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP1_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP1_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP1_DENORM_CONTROL_DEFAULT 0x00000003 -#define mmDCP1_OUT_ROUND_CONTROL_DEFAULT 0x0000000a -#define mmDCP1_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff -#define mmDCP1_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff -#define mmDCP1_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff -#define mmDCP1_KEY_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_KEY_RANGE_ALPHA_DEFAULT 0x00000000 -#define mmDCP1_KEY_RANGE_RED_DEFAULT 0x00000000 -#define mmDCP1_KEY_RANGE_GREEN_DEFAULT 0x00000000 -#define mmDCP1_KEY_RANGE_BLUE_DEFAULT 0x00000000 -#define mmDCP1_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmDCP1_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmDCP1_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmDCP1_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmDCP1_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmDCP1_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmDCP1_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 -#define mmDCP1_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmDCP1_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmDCP1_CUR_CONTROL_DEFAULT 0x00000810 -#define mmDCP1_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP1_CUR_SIZE_DEFAULT 0x00000000 -#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP1_CUR_POSITION_DEFAULT 0x00000000 -#define mmDCP1_CUR_HOT_SPOT_DEFAULT 0x00000000 -#define mmDCP1_CUR_COLOR1_DEFAULT 0x00000000 -#define mmDCP1_CUR_COLOR2_DEFAULT 0x00000000 -#define mmDCP1_CUR_UPDATE_DEFAULT 0x00000000 -#define mmDCP1_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 -#define mmDCP1_CUR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_RW_MODE_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP1_DC_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff -#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff -#define mmDCP1_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff -#define mmDCP1_DCP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_DCP_CRC_MASK_DEFAULT 0x00000000 -#define mmDCP1_DCP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmDCP1_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmDCP1_DCP_CRC_LAST_DEFAULT 0x00000000 -#define mmDCP1_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmDCP1_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCP1_DCP_GSL_CONTROL_DEFAULT 0x60000020 -#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 -#define mmDCP1_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 -#define mmDCP1_HW_ROTATION_DEFAULT 0x00000000 -#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 -#define mmDCP1_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP1_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP1_ALPHA_CONTROL_DEFAULT 0x00000002 -#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 -#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 -#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_lb1_dispdec -#define mmLB1_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLB1_LB_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLB1_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLB1_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLB1_LB_VLINE_START_END_DEFAULT 0x00000000 -#define mmLB1_LB_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLB1_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmLB1_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLB1_LB_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLB1_LB_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLB1_LB_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLB1_LB_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLB1_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLB1_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLB1_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLB1_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLB1_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLB1_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLB1_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLB1_LB_BUFFER_STATUS_DEFAULT 0x00000002 -#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 -#define mmLB1_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 -#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 -#define mmLB1_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 -#define mmLB1_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dcfe1_dispdec -#define mmDCFE1_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFE1_DCFE_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFE1_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFE1_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFE1_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFE1_DCFE_MISC_DEFAULT 0x00000001 -#define mmDCFE1_DCFE_FLUSH_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon4_dispdec -#define mmDC_PERFMON4_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON4_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmif_pg1_dispdec -#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 -#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_DVMM_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_scl1_dispdec -#define mmSCL1_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCL1_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCL1_SCL_MODE_DEFAULT 0x00000000 -#define mmSCL1_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL1_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL1_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL1_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL1_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCL1_SCL_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCL1_SCL_UPDATE_DEFAULT 0x00000000 -#define mmSCL1_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmSCL1_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCL1_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCL1_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCL1_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCL1_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCL1_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCL1_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blnd1_dispdec -#define mmBLND1_BLND_CONTROL_DEFAULT 0xff0220ff -#define mmBLND1_BLND_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLND1_BLND_CONTROL2_DEFAULT 0x00000010 -#define mmBLND1_BLND_UPDATE_DEFAULT 0x00000000 -#define mmBLND1_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLND1_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLND1_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtc1_dispdec -#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTC1_CRTC_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VBI_END_DEFAULT 0x00000003 -#define mmCRTC1_CRTC_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CONTROL_DEFAULT 0x80400110 -#define mmCRTC1_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTC1_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTC1_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTC1_CRTC_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTC1_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_GSL_CONTROL_DEFAULT 0x00020000 -#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_DRR_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_fmt1_dispdec -#define mmFMT1_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT1_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT1_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT1_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT1_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT1_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT1_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT1_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT1_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT1_FMT_CRC_CNTL_DEFAULT 0x01000040 -#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff -#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff -#define mmFMT1_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 -#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 -#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT1_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcp2_dispdec -#define mmDCP2_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmDCP2_GRPH_CONTROL_DEFAULT 0x20002040 -#define mmDCP2_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_PITCH_DEFAULT 0x00000000 -#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 -#define mmDCP2_GRPH_X_START_DEFAULT 0x00000000 -#define mmDCP2_GRPH_Y_START_DEFAULT 0x00000000 -#define mmDCP2_GRPH_X_END_DEFAULT 0x00000000 -#define mmDCP2_GRPH_Y_END_DEFAULT 0x00000000 -#define mmDCP2_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmDCP2_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 -#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 -#define mmDCP2_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_GRPH_DFQ_STATUS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 -#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 -#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff -#define mmDCP2_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 -#define mmDCP2_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 -#define mmDCP2_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 -#define mmDCP2_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 -#define mmDCP2_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_INPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP2_INPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP2_INPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP2_INPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP2_INPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP2_INPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP2_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP2_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP2_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP2_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP2_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP2_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP2_DENORM_CONTROL_DEFAULT 0x00000003 -#define mmDCP2_OUT_ROUND_CONTROL_DEFAULT 0x0000000a -#define mmDCP2_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff -#define mmDCP2_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff -#define mmDCP2_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff -#define mmDCP2_KEY_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_KEY_RANGE_ALPHA_DEFAULT 0x00000000 -#define mmDCP2_KEY_RANGE_RED_DEFAULT 0x00000000 -#define mmDCP2_KEY_RANGE_GREEN_DEFAULT 0x00000000 -#define mmDCP2_KEY_RANGE_BLUE_DEFAULT 0x00000000 -#define mmDCP2_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmDCP2_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmDCP2_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmDCP2_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmDCP2_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmDCP2_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmDCP2_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 -#define mmDCP2_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmDCP2_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmDCP2_CUR_CONTROL_DEFAULT 0x00000810 -#define mmDCP2_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP2_CUR_SIZE_DEFAULT 0x00000000 -#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP2_CUR_POSITION_DEFAULT 0x00000000 -#define mmDCP2_CUR_HOT_SPOT_DEFAULT 0x00000000 -#define mmDCP2_CUR_COLOR1_DEFAULT 0x00000000 -#define mmDCP2_CUR_COLOR2_DEFAULT 0x00000000 -#define mmDCP2_CUR_UPDATE_DEFAULT 0x00000000 -#define mmDCP2_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 -#define mmDCP2_CUR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_RW_MODE_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP2_DC_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff -#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff -#define mmDCP2_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff -#define mmDCP2_DCP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_DCP_CRC_MASK_DEFAULT 0x00000000 -#define mmDCP2_DCP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmDCP2_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmDCP2_DCP_CRC_LAST_DEFAULT 0x00000000 -#define mmDCP2_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmDCP2_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCP2_DCP_GSL_CONTROL_DEFAULT 0x60000020 -#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 -#define mmDCP2_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 -#define mmDCP2_HW_ROTATION_DEFAULT 0x00000000 -#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 -#define mmDCP2_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP2_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP2_ALPHA_CONTROL_DEFAULT 0x00000002 -#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 -#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 -#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_lb2_dispdec -#define mmLB2_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLB2_LB_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLB2_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLB2_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLB2_LB_VLINE_START_END_DEFAULT 0x00000000 -#define mmLB2_LB_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLB2_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmLB2_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLB2_LB_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLB2_LB_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLB2_LB_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLB2_LB_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLB2_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLB2_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLB2_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLB2_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLB2_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLB2_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLB2_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLB2_LB_BUFFER_STATUS_DEFAULT 0x00000002 -#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 -#define mmLB2_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 -#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 -#define mmLB2_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 -#define mmLB2_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dcfe2_dispdec -#define mmDCFE2_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFE2_DCFE_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFE2_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFE2_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFE2_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFE2_DCFE_MISC_DEFAULT 0x00000001 -#define mmDCFE2_DCFE_FLUSH_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon5_dispdec -#define mmDC_PERFMON5_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON5_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmif_pg2_dispdec -#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 -#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_DVMM_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_scl2_dispdec -#define mmSCL2_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCL2_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCL2_SCL_MODE_DEFAULT 0x00000000 -#define mmSCL2_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL2_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL2_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL2_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL2_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCL2_SCL_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCL2_SCL_UPDATE_DEFAULT 0x00000000 -#define mmSCL2_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmSCL2_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCL2_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCL2_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCL2_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCL2_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCL2_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCL2_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blnd2_dispdec -#define mmBLND2_BLND_CONTROL_DEFAULT 0xff0220ff -#define mmBLND2_BLND_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLND2_BLND_CONTROL2_DEFAULT 0x00000010 -#define mmBLND2_BLND_UPDATE_DEFAULT 0x00000000 -#define mmBLND2_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLND2_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLND2_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtc2_dispdec -#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTC2_CRTC_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VBI_END_DEFAULT 0x00000003 -#define mmCRTC2_CRTC_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CONTROL_DEFAULT 0x80400110 -#define mmCRTC2_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTC2_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTC2_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTC2_CRTC_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTC2_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_GSL_CONTROL_DEFAULT 0x00020000 -#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_DRR_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_fmt2_dispdec -#define mmFMT2_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT2_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT2_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT2_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT2_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT2_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT2_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT2_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT2_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT2_FMT_CRC_CNTL_DEFAULT 0x01000040 -#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff -#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff -#define mmFMT2_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 -#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 -#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT2_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcp3_dispdec -#define mmDCP3_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmDCP3_GRPH_CONTROL_DEFAULT 0x20002040 -#define mmDCP3_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_PITCH_DEFAULT 0x00000000 -#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 -#define mmDCP3_GRPH_X_START_DEFAULT 0x00000000 -#define mmDCP3_GRPH_Y_START_DEFAULT 0x00000000 -#define mmDCP3_GRPH_X_END_DEFAULT 0x00000000 -#define mmDCP3_GRPH_Y_END_DEFAULT 0x00000000 -#define mmDCP3_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmDCP3_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 -#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 -#define mmDCP3_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_GRPH_DFQ_STATUS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 -#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 -#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff -#define mmDCP3_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 -#define mmDCP3_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 -#define mmDCP3_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 -#define mmDCP3_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 -#define mmDCP3_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_INPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP3_INPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP3_INPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP3_INPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP3_INPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP3_INPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP3_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP3_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP3_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP3_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP3_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP3_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP3_DENORM_CONTROL_DEFAULT 0x00000003 -#define mmDCP3_OUT_ROUND_CONTROL_DEFAULT 0x0000000a -#define mmDCP3_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff -#define mmDCP3_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff -#define mmDCP3_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff -#define mmDCP3_KEY_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_KEY_RANGE_ALPHA_DEFAULT 0x00000000 -#define mmDCP3_KEY_RANGE_RED_DEFAULT 0x00000000 -#define mmDCP3_KEY_RANGE_GREEN_DEFAULT 0x00000000 -#define mmDCP3_KEY_RANGE_BLUE_DEFAULT 0x00000000 -#define mmDCP3_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmDCP3_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmDCP3_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmDCP3_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmDCP3_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmDCP3_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmDCP3_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 -#define mmDCP3_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmDCP3_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmDCP3_CUR_CONTROL_DEFAULT 0x00000810 -#define mmDCP3_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP3_CUR_SIZE_DEFAULT 0x00000000 -#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP3_CUR_POSITION_DEFAULT 0x00000000 -#define mmDCP3_CUR_HOT_SPOT_DEFAULT 0x00000000 -#define mmDCP3_CUR_COLOR1_DEFAULT 0x00000000 -#define mmDCP3_CUR_COLOR2_DEFAULT 0x00000000 -#define mmDCP3_CUR_UPDATE_DEFAULT 0x00000000 -#define mmDCP3_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 -#define mmDCP3_CUR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_RW_MODE_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP3_DC_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff -#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff -#define mmDCP3_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff -#define mmDCP3_DCP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_DCP_CRC_MASK_DEFAULT 0x00000000 -#define mmDCP3_DCP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmDCP3_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmDCP3_DCP_CRC_LAST_DEFAULT 0x00000000 -#define mmDCP3_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmDCP3_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCP3_DCP_GSL_CONTROL_DEFAULT 0x60000020 -#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 -#define mmDCP3_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 -#define mmDCP3_HW_ROTATION_DEFAULT 0x00000000 -#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 -#define mmDCP3_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP3_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP3_ALPHA_CONTROL_DEFAULT 0x00000002 -#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 -#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 -#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_lb3_dispdec -#define mmLB3_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLB3_LB_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLB3_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLB3_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLB3_LB_VLINE_START_END_DEFAULT 0x00000000 -#define mmLB3_LB_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLB3_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmLB3_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLB3_LB_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLB3_LB_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLB3_LB_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLB3_LB_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLB3_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLB3_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLB3_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLB3_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLB3_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLB3_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLB3_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLB3_LB_BUFFER_STATUS_DEFAULT 0x00000002 -#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 -#define mmLB3_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 -#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 -#define mmLB3_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 -#define mmLB3_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dcfe3_dispdec -#define mmDCFE3_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFE3_DCFE_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFE3_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFE3_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFE3_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFE3_DCFE_MISC_DEFAULT 0x00000001 -#define mmDCFE3_DCFE_FLUSH_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon6_dispdec -#define mmDC_PERFMON6_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON6_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmif_pg3_dispdec -#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 -#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_DVMM_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_scl3_dispdec -#define mmSCL3_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCL3_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCL3_SCL_MODE_DEFAULT 0x00000000 -#define mmSCL3_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL3_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL3_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL3_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL3_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCL3_SCL_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCL3_SCL_UPDATE_DEFAULT 0x00000000 -#define mmSCL3_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmSCL3_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCL3_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCL3_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCL3_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCL3_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCL3_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCL3_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blnd3_dispdec -#define mmBLND3_BLND_CONTROL_DEFAULT 0xff0220ff -#define mmBLND3_BLND_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLND3_BLND_CONTROL2_DEFAULT 0x00000010 -#define mmBLND3_BLND_UPDATE_DEFAULT 0x00000000 -#define mmBLND3_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLND3_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLND3_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtc3_dispdec -#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTC3_CRTC_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VBI_END_DEFAULT 0x00000003 -#define mmCRTC3_CRTC_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CONTROL_DEFAULT 0x80400110 -#define mmCRTC3_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTC3_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTC3_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTC3_CRTC_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTC3_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_GSL_CONTROL_DEFAULT 0x00020000 -#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_DRR_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_fmt3_dispdec -#define mmFMT3_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT3_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT3_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT3_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT3_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT3_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT3_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT3_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT3_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT3_FMT_CRC_CNTL_DEFAULT 0x01000040 -#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff -#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff -#define mmFMT3_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 -#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 -#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT3_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcp4_dispdec -#define mmDCP4_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmDCP4_GRPH_CONTROL_DEFAULT 0x20002040 -#define mmDCP4_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_PITCH_DEFAULT 0x00000000 -#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 -#define mmDCP4_GRPH_X_START_DEFAULT 0x00000000 -#define mmDCP4_GRPH_Y_START_DEFAULT 0x00000000 -#define mmDCP4_GRPH_X_END_DEFAULT 0x00000000 -#define mmDCP4_GRPH_Y_END_DEFAULT 0x00000000 -#define mmDCP4_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmDCP4_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 -#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 -#define mmDCP4_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_GRPH_DFQ_STATUS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 -#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 -#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff -#define mmDCP4_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 -#define mmDCP4_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 -#define mmDCP4_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 -#define mmDCP4_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 -#define mmDCP4_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_INPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP4_INPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP4_INPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP4_INPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP4_INPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP4_INPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP4_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP4_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP4_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP4_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP4_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP4_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP4_DENORM_CONTROL_DEFAULT 0x00000003 -#define mmDCP4_OUT_ROUND_CONTROL_DEFAULT 0x0000000a -#define mmDCP4_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff -#define mmDCP4_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff -#define mmDCP4_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff -#define mmDCP4_KEY_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_KEY_RANGE_ALPHA_DEFAULT 0x00000000 -#define mmDCP4_KEY_RANGE_RED_DEFAULT 0x00000000 -#define mmDCP4_KEY_RANGE_GREEN_DEFAULT 0x00000000 -#define mmDCP4_KEY_RANGE_BLUE_DEFAULT 0x00000000 -#define mmDCP4_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmDCP4_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmDCP4_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmDCP4_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmDCP4_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmDCP4_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmDCP4_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 -#define mmDCP4_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmDCP4_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmDCP4_CUR_CONTROL_DEFAULT 0x00000810 -#define mmDCP4_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP4_CUR_SIZE_DEFAULT 0x00000000 -#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP4_CUR_POSITION_DEFAULT 0x00000000 -#define mmDCP4_CUR_HOT_SPOT_DEFAULT 0x00000000 -#define mmDCP4_CUR_COLOR1_DEFAULT 0x00000000 -#define mmDCP4_CUR_COLOR2_DEFAULT 0x00000000 -#define mmDCP4_CUR_UPDATE_DEFAULT 0x00000000 -#define mmDCP4_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 -#define mmDCP4_CUR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_RW_MODE_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP4_DC_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff -#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff -#define mmDCP4_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff -#define mmDCP4_DCP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_DCP_CRC_MASK_DEFAULT 0x00000000 -#define mmDCP4_DCP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmDCP4_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmDCP4_DCP_CRC_LAST_DEFAULT 0x00000000 -#define mmDCP4_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmDCP4_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCP4_DCP_GSL_CONTROL_DEFAULT 0x60000020 -#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 -#define mmDCP4_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 -#define mmDCP4_HW_ROTATION_DEFAULT 0x00000000 -#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 -#define mmDCP4_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP4_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP4_ALPHA_CONTROL_DEFAULT 0x00000002 -#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 -#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 -#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_lb4_dispdec -#define mmLB4_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLB4_LB_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLB4_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLB4_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLB4_LB_VLINE_START_END_DEFAULT 0x00000000 -#define mmLB4_LB_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLB4_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmLB4_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLB4_LB_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLB4_LB_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLB4_LB_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLB4_LB_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLB4_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLB4_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLB4_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLB4_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLB4_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLB4_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLB4_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLB4_LB_BUFFER_STATUS_DEFAULT 0x00000002 -#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 -#define mmLB4_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 -#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 -#define mmLB4_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 -#define mmLB4_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dcfe4_dispdec -#define mmDCFE4_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFE4_DCFE_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFE4_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFE4_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFE4_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFE4_DCFE_MISC_DEFAULT 0x00000001 -#define mmDCFE4_DCFE_FLUSH_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon7_dispdec -#define mmDC_PERFMON7_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON7_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmif_pg4_dispdec -#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 -#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_DVMM_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_scl4_dispdec -#define mmSCL4_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCL4_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCL4_SCL_MODE_DEFAULT 0x00000000 -#define mmSCL4_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL4_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL4_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL4_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL4_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCL4_SCL_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCL4_SCL_UPDATE_DEFAULT 0x00000000 -#define mmSCL4_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmSCL4_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCL4_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCL4_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCL4_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCL4_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCL4_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCL4_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blnd4_dispdec -#define mmBLND4_BLND_CONTROL_DEFAULT 0xff0220ff -#define mmBLND4_BLND_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLND4_BLND_CONTROL2_DEFAULT 0x00000010 -#define mmBLND4_BLND_UPDATE_DEFAULT 0x00000000 -#define mmBLND4_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLND4_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLND4_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtc4_dispdec -#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTC4_CRTC_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VBI_END_DEFAULT 0x00000003 -#define mmCRTC4_CRTC_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CONTROL_DEFAULT 0x80400110 -#define mmCRTC4_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTC4_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTC4_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTC4_CRTC_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTC4_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_GSL_CONTROL_DEFAULT 0x00020000 -#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_DRR_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_fmt4_dispdec -#define mmFMT4_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT4_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT4_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT4_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT4_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT4_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT4_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT4_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT4_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT4_FMT_CRC_CNTL_DEFAULT 0x01000040 -#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff -#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff -#define mmFMT4_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 -#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 -#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT4_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcp5_dispdec -#define mmDCP5_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmDCP5_GRPH_CONTROL_DEFAULT 0x20002040 -#define mmDCP5_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_PITCH_DEFAULT 0x00000000 -#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 -#define mmDCP5_GRPH_X_START_DEFAULT 0x00000000 -#define mmDCP5_GRPH_Y_START_DEFAULT 0x00000000 -#define mmDCP5_GRPH_X_END_DEFAULT 0x00000000 -#define mmDCP5_GRPH_Y_END_DEFAULT 0x00000000 -#define mmDCP5_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmDCP5_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 -#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 -#define mmDCP5_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_GRPH_DFQ_STATUS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 -#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 -#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff -#define mmDCP5_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 -#define mmDCP5_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 -#define mmDCP5_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 -#define mmDCP5_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 -#define mmDCP5_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_INPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP5_INPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP5_INPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP5_INPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP5_INPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP5_INPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP5_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP5_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP5_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP5_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP5_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP5_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP5_DENORM_CONTROL_DEFAULT 0x00000003 -#define mmDCP5_OUT_ROUND_CONTROL_DEFAULT 0x0000000a -#define mmDCP5_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff -#define mmDCP5_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff -#define mmDCP5_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff -#define mmDCP5_KEY_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_KEY_RANGE_ALPHA_DEFAULT 0x00000000 -#define mmDCP5_KEY_RANGE_RED_DEFAULT 0x00000000 -#define mmDCP5_KEY_RANGE_GREEN_DEFAULT 0x00000000 -#define mmDCP5_KEY_RANGE_BLUE_DEFAULT 0x00000000 -#define mmDCP5_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmDCP5_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmDCP5_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmDCP5_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmDCP5_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmDCP5_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmDCP5_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 -#define mmDCP5_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmDCP5_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmDCP5_CUR_CONTROL_DEFAULT 0x00000810 -#define mmDCP5_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP5_CUR_SIZE_DEFAULT 0x00000000 -#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP5_CUR_POSITION_DEFAULT 0x00000000 -#define mmDCP5_CUR_HOT_SPOT_DEFAULT 0x00000000 -#define mmDCP5_CUR_COLOR1_DEFAULT 0x00000000 -#define mmDCP5_CUR_COLOR2_DEFAULT 0x00000000 -#define mmDCP5_CUR_UPDATE_DEFAULT 0x00000000 -#define mmDCP5_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 -#define mmDCP5_CUR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_RW_MODE_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP5_DC_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff -#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff -#define mmDCP5_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff -#define mmDCP5_DCP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_DCP_CRC_MASK_DEFAULT 0x00000000 -#define mmDCP5_DCP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmDCP5_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmDCP5_DCP_CRC_LAST_DEFAULT 0x00000000 -#define mmDCP5_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmDCP5_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCP5_DCP_GSL_CONTROL_DEFAULT 0x60000020 -#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 -#define mmDCP5_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 -#define mmDCP5_HW_ROTATION_DEFAULT 0x00000000 -#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 -#define mmDCP5_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP5_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP5_ALPHA_CONTROL_DEFAULT 0x00000002 -#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 -#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 -#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_lb5_dispdec -#define mmLB5_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLB5_LB_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLB5_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLB5_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLB5_LB_VLINE_START_END_DEFAULT 0x00000000 -#define mmLB5_LB_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLB5_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmLB5_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLB5_LB_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLB5_LB_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLB5_LB_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLB5_LB_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLB5_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLB5_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLB5_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLB5_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLB5_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLB5_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLB5_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLB5_LB_BUFFER_STATUS_DEFAULT 0x00000002 -#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 -#define mmLB5_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 -#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 -#define mmLB5_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 -#define mmLB5_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dcfe5_dispdec -#define mmDCFE5_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFE5_DCFE_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFE5_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFE5_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFE5_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFE5_DCFE_MISC_DEFAULT 0x00000001 -#define mmDCFE5_DCFE_FLUSH_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon8_dispdec -#define mmDC_PERFMON8_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON8_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmif_pg5_dispdec -#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 -#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_DVMM_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_scl5_dispdec -#define mmSCL5_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCL5_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCL5_SCL_MODE_DEFAULT 0x00000000 -#define mmSCL5_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL5_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL5_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL5_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL5_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCL5_SCL_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCL5_SCL_UPDATE_DEFAULT 0x00000000 -#define mmSCL5_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmSCL5_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCL5_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCL5_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCL5_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCL5_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCL5_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCL5_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blnd5_dispdec -#define mmBLND5_BLND_CONTROL_DEFAULT 0xff0220ff -#define mmBLND5_BLND_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLND5_BLND_CONTROL2_DEFAULT 0x00000010 -#define mmBLND5_BLND_UPDATE_DEFAULT 0x00000000 -#define mmBLND5_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLND5_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLND5_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtc5_dispdec -#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTC5_CRTC_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VBI_END_DEFAULT 0x00000003 -#define mmCRTC5_CRTC_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CONTROL_DEFAULT 0x80400110 -#define mmCRTC5_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTC5_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTC5_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTC5_CRTC_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTC5_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_GSL_CONTROL_DEFAULT 0x00020000 -#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_DRR_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_fmt5_dispdec -#define mmFMT5_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT5_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT5_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT5_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT5_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT5_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT5_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT5_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT5_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT5_FMT_CRC_CNTL_DEFAULT 0x01000040 -#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff -#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff -#define mmFMT5_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 -#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 -#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT5_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_unp0_dispdec -#define mmUNP0_UNP_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmUNP0_UNP_GRPH_CONTROL_DEFAULT 0x0a008008 -#define mmUNP0_UNP_GRPH_CONTROL_C_DEFAULT 0x00008000 -#define mmUNP0_UNP_GRPH_CONTROL_EXP_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PITCH_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PITCH_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_X_START_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_X_START_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_Y_START_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_Y_START_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_X_END_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_X_END_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_Y_END_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_Y_END_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x0000ffff -#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmUNP0_UNP_DVMM_PTE_CONTROL_C_DEFAULT 0x00004000 -#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_DEFAULT 0x00002220 -#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00002020 -#define mmUNP0_UNP_FLIP_CONTROL_DEFAULT 0x00000001 -#define mmUNP0_UNP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmUNP0_UNP_CRC_MASK_DEFAULT 0x00000000 -#define mmUNP0_UNP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmUNP0_UNP_CRC_LAST_DEFAULT 0x00000000 -#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000100 -#define mmUNP0_UNP_HW_ROTATION_DEFAULT 0x00000010 - - -// addressBlock: dce_dc_lbv0_dispdec -#define mmLBV0_LBV_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLBV0_LBV_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLBV0_LBV_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLBV0_LBV_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLBV0_LBV_VLINE_START_END_DEFAULT 0x00000000 -#define mmLBV0_LBV_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLBV0_LBV_V_COUNTER_DEFAULT 0x00000000 -#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLBV0_LBV_V_COUNTER_CHROMA_DEFAULT 0x00000000 -#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_DEFAULT 0x00000000 -#define mmLBV0_LBV_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLBV0_LBV_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLBV0_LBV_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLBV0_LBV_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLBV0_LBV_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLBV0_LBV_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLBV0_LBV_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLBV0_LBV_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLBV0_LBV_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLBV0_LBV_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLBV0_LBV_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLBV0_LBV_BUFFER_STATUS_DEFAULT 0x12000002 -#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_sclv0_dispdec -#define mmSCLV0_SCLV_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_MODE_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VERT_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCLV0_SCLV_UPDATE_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VIEWPORT_SIZE_C_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_MODE_CHANGE_MASK_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_DEFAULT 0x01000000 - - -// addressBlock: dce_dc_col_man0_dispdec -#define mmCOL_MAN0_COL_MAN_UPDATE_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C11_C12_A_DEFAULT 0x00002000 -#define mmCOL_MAN0_INPUT_CSC_C13_C14_A_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C21_C22_A_DEFAULT 0x20000000 -#define mmCOL_MAN0_INPUT_CSC_C23_C24_A_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C31_C32_A_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C33_C34_A_DEFAULT 0x00002000 -#define mmCOL_MAN0_INPUT_CSC_C11_C12_B_DEFAULT 0x00002000 -#define mmCOL_MAN0_INPUT_CSC_C13_C14_B_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C21_C22_B_DEFAULT 0x20000000 -#define mmCOL_MAN0_INPUT_CSC_C23_C24_B_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C31_C32_B_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C33_C34_B_DEFAULT 0x00002000 -#define mmCOL_MAN0_PRESCALE_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_PRESCALE_VALUES_R_DEFAULT 0x20000000 -#define mmCOL_MAN0_PRESCALE_VALUES_G_DEFAULT 0x20000000 -#define mmCOL_MAN0_PRESCALE_VALUES_B_DEFAULT 0x20000000 -#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_DEFAULT 0x00002000 -#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_DEFAULT 0x20000000 -#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_DEFAULT 0x00002000 -#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_DEFAULT 0x00002000 -#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_DEFAULT 0x20000000 -#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_DEFAULT 0x00002000 -#define mmCOL_MAN0_DENORM_CLAMP_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_DEFAULT 0x00000fff -#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_DEFAULT 0x00000fff -#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_DEFAULT 0x00000fff -#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmCOL_MAN0_PACK_FIFO_ERROR_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_FIFO_ERROR_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_DEFAULT 0x03800000 -#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_DEFAULT 0xffff0000 -#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_DEFAULT 0xffff0000 -#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_DEFAULT 0xffff0000 -#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 - - -// addressBlock: dce_dc_dcfev0_dispdec -#define mmDCFEV0_DCFEV_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_L_FLUSH_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_C_FLUSH_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_MISC_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dc_perfmon11_dispdec -#define mmDC_PERFMON11_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON11_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmifv_pg0_dispdec -#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303 -#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_DEFAULT 0x00003000 -#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200 -#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200 -#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303 -#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_DEFAULT 0x00003000 -#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200 -#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200 -#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blndv0_dispdec -#define mmBLNDV0_BLNDV_CONTROL_DEFAULT 0xff0220ff -#define mmBLNDV0_BLNDV_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLNDV0_BLNDV_CONTROL2_DEFAULT 0x00000010 -#define mmBLNDV0_BLNDV_UPDATE_DEFAULT 0x00000000 -#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLNDV0_BLNDV_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtcv0_dispdec -#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTCV0_CRTCV_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VBI_END_DEFAULT 0x00000003 -#define mmCRTCV0_CRTCV_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CONTROL_DEFAULT 0x80400110 -#define mmCRTCV0_CRTCV_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTCV0_CRTCV_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_GSL_CONTROL_DEFAULT 0x00020000 - - -// addressBlock: dce_dc_unp1_dispdec -#define mmUNP1_UNP_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmUNP1_UNP_GRPH_CONTROL_DEFAULT 0x0a008008 -#define mmUNP1_UNP_GRPH_CONTROL_C_DEFAULT 0x00008000 -#define mmUNP1_UNP_GRPH_CONTROL_EXP_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PITCH_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PITCH_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_X_START_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_X_START_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_Y_START_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_Y_START_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_X_END_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_X_END_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_Y_END_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_Y_END_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x0000ffff -#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmUNP1_UNP_DVMM_PTE_CONTROL_C_DEFAULT 0x00004000 -#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_DEFAULT 0x00002220 -#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00002020 -#define mmUNP1_UNP_FLIP_CONTROL_DEFAULT 0x00000001 -#define mmUNP1_UNP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmUNP1_UNP_CRC_MASK_DEFAULT 0x00000000 -#define mmUNP1_UNP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmUNP1_UNP_CRC_LAST_DEFAULT 0x00000000 -#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000100 -#define mmUNP1_UNP_HW_ROTATION_DEFAULT 0x00000010 - - -// addressBlock: dce_dc_lbv1_dispdec -#define mmLBV1_LBV_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLBV1_LBV_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLBV1_LBV_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLBV1_LBV_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLBV1_LBV_VLINE_START_END_DEFAULT 0x00000000 -#define mmLBV1_LBV_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLBV1_LBV_V_COUNTER_DEFAULT 0x00000000 -#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLBV1_LBV_V_COUNTER_CHROMA_DEFAULT 0x00000000 -#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_DEFAULT 0x00000000 -#define mmLBV1_LBV_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLBV1_LBV_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLBV1_LBV_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLBV1_LBV_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLBV1_LBV_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLBV1_LBV_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLBV1_LBV_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLBV1_LBV_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLBV1_LBV_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLBV1_LBV_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLBV1_LBV_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLBV1_LBV_BUFFER_STATUS_DEFAULT 0x12000002 -#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_sclv1_dispdec -#define mmSCLV1_SCLV_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_MODE_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VERT_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCLV1_SCLV_UPDATE_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VIEWPORT_SIZE_C_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_MODE_CHANGE_MASK_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_DEFAULT 0x01000000 - - -// addressBlock: dce_dc_col_man1_dispdec -#define mmCOL_MAN1_COL_MAN_UPDATE_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C11_C12_A_DEFAULT 0x00002000 -#define mmCOL_MAN1_INPUT_CSC_C13_C14_A_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C21_C22_A_DEFAULT 0x20000000 -#define mmCOL_MAN1_INPUT_CSC_C23_C24_A_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C31_C32_A_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C33_C34_A_DEFAULT 0x00002000 -#define mmCOL_MAN1_INPUT_CSC_C11_C12_B_DEFAULT 0x00002000 -#define mmCOL_MAN1_INPUT_CSC_C13_C14_B_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C21_C22_B_DEFAULT 0x20000000 -#define mmCOL_MAN1_INPUT_CSC_C23_C24_B_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C31_C32_B_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C33_C34_B_DEFAULT 0x00002000 -#define mmCOL_MAN1_PRESCALE_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_PRESCALE_VALUES_R_DEFAULT 0x20000000 -#define mmCOL_MAN1_PRESCALE_VALUES_G_DEFAULT 0x20000000 -#define mmCOL_MAN1_PRESCALE_VALUES_B_DEFAULT 0x20000000 -#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_DEFAULT 0x00002000 -#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_DEFAULT 0x20000000 -#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_DEFAULT 0x00002000 -#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_DEFAULT 0x00002000 -#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_DEFAULT 0x20000000 -#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_DEFAULT 0x00002000 -#define mmCOL_MAN1_DENORM_CLAMP_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_DEFAULT 0x00000fff -#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_DEFAULT 0x00000fff -#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_DEFAULT 0x00000fff -#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmCOL_MAN1_PACK_FIFO_ERROR_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_FIFO_ERROR_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_DEFAULT 0x03800000 -#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_DEFAULT 0xffff0000 -#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_DEFAULT 0xffff0000 -#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_DEFAULT 0xffff0000 -#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 - - -// addressBlock: dce_dc_dcfev1_dispdec -#define mmDCFEV1_DCFEV_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_L_FLUSH_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_C_FLUSH_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_MISC_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dc_perfmon12_dispdec -#define mmDC_PERFMON12_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON12_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmifv_pg1_dispdec -#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303 -#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_DEFAULT 0x00003000 -#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200 -#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200 -#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303 -#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_DEFAULT 0x00003000 -#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200 -#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200 -#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blndv1_dispdec -#define mmBLNDV1_BLNDV_CONTROL_DEFAULT 0xff0220ff -#define mmBLNDV1_BLNDV_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLNDV1_BLNDV_CONTROL2_DEFAULT 0x00000010 -#define mmBLNDV1_BLNDV_UPDATE_DEFAULT 0x00000000 -#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLNDV1_BLNDV_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtcv1_dispdec -#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTCV1_CRTCV_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VBI_END_DEFAULT 0x00000003 -#define mmCRTCV1_CRTCV_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CONTROL_DEFAULT 0x80400110 -#define mmCRTCV1_CRTCV_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTCV1_CRTCV_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_GSL_CONTROL_DEFAULT 0x00020000 - - -// addressBlock: dce_dc_hpd0_dispdec -#define mmHPD0_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD0_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD0_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hpd1_dispdec -#define mmHPD1_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD1_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD1_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hpd2_dispdec -#define mmHPD2_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD2_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD2_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hpd3_dispdec -#define mmHPD3_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD3_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD3_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hpd4_dispdec -#define mmHPD4_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD4_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD4_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hpd5_dispdec -#define mmHPD5_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD5_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD5_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon2_dispdec -#define mmDC_PERFMON2_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON2_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp_aux0_dispdec -#define mmDP_AUX0_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX0_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp_aux1_dispdec -#define mmDP_AUX1_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX1_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp_aux2_dispdec -#define mmDP_AUX2_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX2_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp_aux3_dispdec -#define mmDP_AUX3_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX3_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp_aux4_dispdec -#define mmDP_AUX4_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX4_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp_aux5_dispdec -#define mmDP_AUX5_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX5_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig0_dispdec -#define mmDIG0_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG0_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG0_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG0_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG0_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG0_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG0_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG0_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG0_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG0_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG0_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG0_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG0_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG0_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG0_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG0_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG0_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG0_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG0_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG0_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG0_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp0_dispdec -#define mmDP0_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP0_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP0_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP0_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP0_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP0_DP_VID_N_DEFAULT 0x00002000 -#define mmDP0_DP_VID_M_DEFAULT 0x00000000 -#define mmDP0_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP0_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP0_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP0_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP0_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP0_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP0_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP0_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP0_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP0_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP0_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig1_dispdec -#define mmDIG1_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG1_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG1_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG1_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG1_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG1_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG1_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG1_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG1_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG1_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG1_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG1_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG1_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG1_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG1_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG1_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG1_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG1_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG1_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG1_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG1_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp1_dispdec -#define mmDP1_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP1_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP1_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP1_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP1_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP1_DP_VID_N_DEFAULT 0x00002000 -#define mmDP1_DP_VID_M_DEFAULT 0x00000000 -#define mmDP1_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP1_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP1_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP1_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP1_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP1_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP1_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP1_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP1_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP1_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP1_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig2_dispdec -#define mmDIG2_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG2_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG2_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG2_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG2_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG2_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG2_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG2_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG2_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG2_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG2_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG2_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG2_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG2_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG2_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG2_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG2_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG2_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG2_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG2_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG2_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp2_dispdec -#define mmDP2_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP2_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP2_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP2_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP2_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP2_DP_VID_N_DEFAULT 0x00002000 -#define mmDP2_DP_VID_M_DEFAULT 0x00000000 -#define mmDP2_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP2_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP2_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP2_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP2_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP2_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP2_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP2_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP2_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP2_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP2_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig3_dispdec -#define mmDIG3_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG3_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG3_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG3_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG3_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG3_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG3_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG3_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG3_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG3_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG3_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG3_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG3_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG3_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG3_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG3_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG3_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG3_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG3_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG3_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG3_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp3_dispdec -#define mmDP3_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP3_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP3_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP3_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP3_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP3_DP_VID_N_DEFAULT 0x00002000 -#define mmDP3_DP_VID_M_DEFAULT 0x00000000 -#define mmDP3_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP3_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP3_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP3_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP3_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP3_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP3_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP3_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP3_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP3_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP3_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig4_dispdec -#define mmDIG4_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG4_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG4_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG4_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG4_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG4_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG4_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG4_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG4_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG4_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG4_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG4_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG4_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG4_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG4_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG4_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG4_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG4_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG4_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG4_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG4_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp4_dispdec -#define mmDP4_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP4_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP4_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP4_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP4_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP4_DP_VID_N_DEFAULT 0x00002000 -#define mmDP4_DP_VID_M_DEFAULT 0x00000000 -#define mmDP4_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP4_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP4_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP4_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP4_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP4_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP4_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP4_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP4_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP4_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP4_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig5_dispdec -#define mmDIG5_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG5_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG5_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG5_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG5_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG5_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG5_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG5_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG5_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG5_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG5_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG5_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG5_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG5_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG5_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG5_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG5_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG5_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG5_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG5_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG5_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp5_dispdec -#define mmDP5_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP5_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP5_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP5_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP5_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP5_DP_VID_N_DEFAULT 0x00002000 -#define mmDP5_DP_VID_M_DEFAULT 0x00000000 -#define mmDP5_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP5_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP5_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP5_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP5_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP5_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP5_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP5_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP5_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP5_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP5_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig6_dispdec -#define mmDIG6_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG6_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG6_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG6_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG6_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG6_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG6_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG6_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG6_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG6_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG6_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG6_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG6_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG6_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG6_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG6_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG6_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG6_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG6_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG6_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG6_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp6_dispdec -#define mmDP6_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP6_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP6_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP6_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP6_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP6_DP_VID_N_DEFAULT 0x00002000 -#define mmDP6_DP_VID_M_DEFAULT 0x00000000 -#define mmDP6_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP6_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP6_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP6_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP6_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP6_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP6_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP6_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP6_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP6_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP6_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy0_dispdec -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs0_dispdec -#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs0_dispdec -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs0_dispdec -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy1_dispdec -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs1_dispdec -#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs1_dispdec -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs1_dispdec -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy2_dispdec -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs2_dispdec -#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs2_dispdec -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs2_dispdec -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy3_dispdec -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs3_dispdec -#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs3_dispdec -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs3_dispdec -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy4_dispdec -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs4_dispdec -#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs4_dispdec -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs4_dispdec -#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS4_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS4_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS4_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS4_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy5_dispdec -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs5_dispdec -#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs5_dispdec -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs5_dispdec -#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS5_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS5_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS5_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS5_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy6_dispdec -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs6_dispdec -#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs6_dispdec -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs6_dispdec -#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS6_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS6_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS6_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS6_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy8_dispdec -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs8_dispdec -#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs8_dispdec -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs8_dispdec -#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS8_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS8_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS8_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS8_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dsi0_dispdec -#define mmDSI0_DISP_DSI_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_STATUS_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_DEFAULT 0x00008000 -#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_DEFAULT 0x31211101 -#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_DEFAULT 0x3e2e1e0e -#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_DEFAULT 0x00001900 -#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_DEFAULT 0x00000066 -#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_DEFAULT 0x00003c2c -#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_DATA_PITCH_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_DEFAULT 0x00000900 -#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RDBK_DATA0_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RDBK_DATA1_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RDBK_DATA2_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RDBK_DATA3_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RDBK_DATATYPE0_DEFAULT 0x22211211 -#define mmDSI0_DISP_DSI_RDBK_DATATYPE1_DEFAULT 0x001c1a02 -#define mmDSI0_DISP_DSI_TRIG_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_EXT_MUX_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_EXT_RESET_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_LANE_CRC_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_LANE_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_DEFAULT 0x00088888 -#define mmDSI0_DISP_DSI_LP_TIMER_CTRL_DEFAULT 0xffffffff -#define mmDSI0_DISP_DSI_HS_TIMER_CTRL_DEFAULT 0x0000ffff -#define mmDSI0_DISP_DSI_TIMEOUT_STATUS_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_EOT_PACKET_DEFAULT 0x010f0f08 -#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_START_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_DEFAULT 0xfd37377f -#define mmDSI0_DISP_DSI_INTERRUPT_CTRL_DEFAULT 0x02222222 -#define mmDSI0_DISP_DSI_CLK_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CLK_STATUS_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CMD_FIFO_DATA_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_DEFAULT 0x00000001 -#define mmDSI0_DISP_DSI_TE_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_LANE_STATUS_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_PERF_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_HSYNC_LENGTH_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RDBK_NUM_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dsi1_dispdec -#define mmDSI1_DISP_DSI_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_STATUS_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_DEFAULT 0x00008000 -#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_DEFAULT 0x31211101 -#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_DEFAULT 0x3e2e1e0e -#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_DEFAULT 0x00001900 -#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_DEFAULT 0x00000066 -#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_DEFAULT 0x00003c2c -#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_DATA_PITCH_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_DEFAULT 0x00000900 -#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RDBK_DATA0_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RDBK_DATA1_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RDBK_DATA2_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RDBK_DATA3_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RDBK_DATATYPE0_DEFAULT 0x22211211 -#define mmDSI1_DISP_DSI_RDBK_DATATYPE1_DEFAULT 0x001c1a02 -#define mmDSI1_DISP_DSI_TRIG_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_EXT_MUX_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_EXT_RESET_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_LANE_CRC_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_LANE_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_DEFAULT 0x00088888 -#define mmDSI1_DISP_DSI_LP_TIMER_CTRL_DEFAULT 0xffffffff -#define mmDSI1_DISP_DSI_HS_TIMER_CTRL_DEFAULT 0x0000ffff -#define mmDSI1_DISP_DSI_TIMEOUT_STATUS_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_EOT_PACKET_DEFAULT 0x010f0f08 -#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_START_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_DEFAULT 0xfd37377f -#define mmDSI1_DISP_DSI_INTERRUPT_CTRL_DEFAULT 0x02222222 -#define mmDSI1_DISP_DSI_CLK_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CLK_STATUS_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CMD_FIFO_DATA_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_DEFAULT 0x00000001 -#define mmDSI1_DISP_DSI_TE_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_LANE_STATUS_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_PERF_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_HSYNC_LENGTH_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RDBK_NUM_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dprx_sd0_dispdec -#define mmDPRX_SD0_DPRX_SD_CONTROL_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA0_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA1_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA2_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA3_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA4_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA5_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA6_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA7_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA8_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_VBID_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSE_SAT_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_V_PARAMETER_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_DEFAULT 0x0000ffff -#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_DEFAULT 0x0000ffff -#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_DEFAULT 0x000003ff -#define mmDPRX_SD0_DPRX_SD_SDP_STEER_DEFAULT 0x00000001 -#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_SDP_DATA_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_SDP_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_DEFAULT 0x00000001 -#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_BS_COUNTER_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dprx_sd1_dispdec -#define mmDPRX_SD1_DPRX_SD_CONTROL_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA0_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA1_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA2_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA3_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA4_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA5_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA6_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA7_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA8_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_VBID_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSE_SAT_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_V_PARAMETER_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_DEFAULT 0x0000ffff -#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_DEFAULT 0x0000ffff -#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_DEFAULT 0x000003ff -#define mmDPRX_SD1_DPRX_SD_SDP_STEER_DEFAULT 0x00000001 -#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_SDP_DATA_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_SDP_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_DEFAULT 0x00000001 -#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_BS_COUNTER_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon10_dispdec -#define mmDC_PERFMON10_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON10_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_zcalregs_dispdec -#define mmCOMP_EN_CTL_DEFAULT 0x00080000 -#define mmCOMP_EN_DFX_DEFAULT 0x00000000 -#define mmZCAL_FUSES_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR - - -// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR - - -// addressBlock: dce_dc_dispdec[948..986] - - -// addressBlock: dce_dc_azdec -#define mmCORB_WRITE_POINTER_DEFAULT 0x00000000 -#define mmCORB_READ_POINTER_DEFAULT 0x00000000 -#define mmCORB_CONTROL_DEFAULT 0x00000000 -#define mmCORB_STATUS_DEFAULT 0x00000000 -#define mmCORB_SIZE_DEFAULT 0x00000002 -#define mmRIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmRIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmRIRB_WRITE_POINTER_DEFAULT 0x00000000 -#define mmRESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000 -#define mmRIRB_CONTROL_DEFAULT 0x00000000 -#define mmRIRB_STATUS_DEFAULT 0x00000000 -#define mmRIRB_SIZE_DEFAULT 0x00000002 -#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000 -#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 -#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 -#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000 -#define mmDMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmDMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmWALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream0_azdec -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream1_azdec -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream2_azdec -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream3_azdec -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream4_azdec -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream5_azdec -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream6_azdec -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream7_azdec -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: azf0stream0_streamind -#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream1_streamind -#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream2_streamind -#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream3_streamind -#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream4_streamind -#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream5_streamind -#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream6_streamind -#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream7_streamind -#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream8_streamind -#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream9_streamind -#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream10_streamind -#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream11_streamind -#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream12_streamind -#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream13_streamind -#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream14_streamind -#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream15_streamind -#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint0_endpointind -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint1_endpointind -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint2_endpointind -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint3_endpointind -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint4_endpointind -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint5_endpointind -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint6_endpointind -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint7_endpointind -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint0_inputendpointind -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint1_inputendpointind -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint2_inputendpointind -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint3_inputendpointind -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint4_inputendpointind -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint5_inputendpointind -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint6_inputendpointind -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint7_inputendpointind -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: f2codecind -#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000003 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2_DEFAULT 0x00000001 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3_DEFAULT 0x000000aa -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x000000b4 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020 -#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000040 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x00000010 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x00000056 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x000000f0 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x000000d6 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000010 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000 - - -// addressBlock: descriptorind -#define ixAUDIO_DESCRIPTOR0_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR13_DEFAULT 0x00000000 - - -// addressBlock: sinkinfoind -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION0_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION1_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION2_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION3_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION4_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION5_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION6_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION7_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION8_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION9_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION10_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION11_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION12_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION13_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION14_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION15_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION16_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION17_DEFAULT 0x00000000 - - -// addressBlock: azinputcrc0resultind -#define ixAZALIA_INPUT_CRC0_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azinputcrc1resultind -#define ixAZALIA_INPUT_CRC1_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azcrc0resultind -#define ixAZALIA_CRC0_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azcrc1resultind -#define ixAZALIA_CRC1_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: vgaseqind -#define ixSEQ00_DEFAULT 0x00000003 -#define ixSEQ01_DEFAULT 0x00000021 -#define ixSEQ02_DEFAULT 0x00000000 -#define ixSEQ03_DEFAULT 0x00000000 -#define ixSEQ04_DEFAULT 0x00000000 - - -// addressBlock: vgacrtind -#define ixCRT00_DEFAULT 0x00000000 -#define ixCRT01_DEFAULT 0x00000000 -#define ixCRT02_DEFAULT 0x00000000 -#define ixCRT03_DEFAULT 0x00000000 -#define ixCRT04_DEFAULT 0x00000000 -#define ixCRT05_DEFAULT 0x00000000 -#define ixCRT06_DEFAULT 0x00000000 -#define ixCRT07_DEFAULT 0x00000000 -#define ixCRT08_DEFAULT 0x00000000 -#define ixCRT09_DEFAULT 0x00000000 -#define ixCRT0A_DEFAULT 0x00000000 -#define ixCRT0B_DEFAULT 0x00000000 -#define ixCRT0C_DEFAULT 0x00000000 -#define ixCRT0D_DEFAULT 0x00000000 -#define ixCRT0E_DEFAULT 0x00000000 -#define ixCRT0F_DEFAULT 0x00000000 -#define ixCRT10_DEFAULT 0x00000000 -#define ixCRT11_DEFAULT 0x00000000 -#define ixCRT12_DEFAULT 0x00000000 -#define ixCRT13_DEFAULT 0x00000000 -#define ixCRT14_DEFAULT 0x00000000 -#define ixCRT15_DEFAULT 0x00000000 -#define ixCRT16_DEFAULT 0x00000000 -#define ixCRT17_DEFAULT 0x00000000 -#define ixCRT18_DEFAULT 0x00000000 -#define ixCRT1E_DEFAULT 0x00000000 -#define ixCRT1F_DEFAULT 0x00000000 -#define ixCRT22_DEFAULT 0x00000000 - - -// addressBlock: vgagrphind -#define ixGRA00_DEFAULT 0x00000000 -#define ixGRA01_DEFAULT 0x00000000 -#define ixGRA02_DEFAULT 0x00000000 -#define ixGRA03_DEFAULT 0x00000000 -#define ixGRA04_DEFAULT 0x00000000 -#define ixGRA05_DEFAULT 0x00000000 -#define ixGRA06_DEFAULT 0x00000000 -#define ixGRA07_DEFAULT 0x00000000 -#define ixGRA08_DEFAULT 0x00000000 - - -// addressBlock: vgaattrind -#define ixATTR00_DEFAULT 0x00000000 -#define ixATTR01_DEFAULT 0x00000000 -#define ixATTR02_DEFAULT 0x00000000 -#define ixATTR03_DEFAULT 0x00000000 -#define ixATTR04_DEFAULT 0x00000000 -#define ixATTR05_DEFAULT 0x00000000 -#define ixATTR06_DEFAULT 0x00000000 -#define ixATTR07_DEFAULT 0x00000000 -#define ixATTR08_DEFAULT 0x00000000 -#define ixATTR09_DEFAULT 0x00000000 -#define ixATTR0A_DEFAULT 0x00000000 -#define ixATTR0B_DEFAULT 0x00000000 -#define ixATTR0C_DEFAULT 0x00000000 -#define ixATTR0D_DEFAULT 0x00000000 -#define ixATTR0E_DEFAULT 0x00000000 -#define ixATTR0F_DEFAULT 0x00000000 -#define ixATTR10_DEFAULT 0x00000000 -#define ixATTR11_DEFAULT 0x00000000 -#define ixATTR12_DEFAULT 0x00000000 -#define ixATTR13_DEFAULT 0x00000000 -#define ixATTR14_DEFAULT 0x00000000 - - -#endif -- GitLab From 5d735f83c2b06ba51f2fae6404da576c6847cb64 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 23 Nov 2017 11:09:07 +0800 Subject: [PATCH 0931/2547] drm/amd/include:cleanup vega10 uvd header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/vega10/UVD folder,remove unused uvd_7_0_default.h. Signed-off-by: Feifei Xu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 +- .../{vega10/UVD => uvd}/uvd_7_0_offset.h | 0 .../{vega10/UVD => uvd}/uvd_7_0_sh_mask.h | 0 .../asic_reg/vega10/UVD/uvd_7_0_default.h | 127 ------------------ 5 files changed, 3 insertions(+), 130 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/UVD => uvd}/uvd_7_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/UVD => uvd}/uvd_7_0_sh_mask.h (100%) delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index de66d22d097e..77c6d1887079 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -35,7 +35,7 @@ #include "amd_pcie.h" #include "vega10/soc15ip.h" -#include "vega10/UVD/uvd_7_0_offset.h" +#include "uvd/uvd_7_0_offset.h" #include "vega10/GC/gc_9_0_offset.h" #include "vega10/GC/gc_9_0_sh_mask.h" #include "sdma0/sdma0_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 2f68f98f61d5..83e26caf1211 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -30,8 +30,8 @@ #include "mmsch_v1_0.h" #include "vega10/soc15ip.h" -#include "vega10/UVD/uvd_7_0_offset.h" -#include "vega10/UVD/uvd_7_0_sh_mask.h" +#include "uvd/uvd_7_0_offset.h" +#include "uvd/uvd_7_0_sh_mask.h" #include "vega10/VCE/vce_4_0_offset.h" #include "vega10/VCE/vce_4_0_default.h" #include "vega10/VCE/vce_4_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h deleted file mode 100644 index 48963caac534..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _uvd_7_0_DEFAULT_HEADER -#define _uvd_7_0_DEFAULT_HEADER - - -// addressBlock: uvd0_uvd_pg_dec -#define mmUVD_POWER_STATUS_DEFAULT 0x00000000 -#define mmUVD_DPG_RBC_RB_CNTL_DEFAULT 0x01000101 -#define mmUVD_DPG_RBC_RB_BASE_LOW_DEFAULT 0x00000000 -#define mmUVD_DPG_RBC_RB_BASE_HIGH_DEFAULT 0x00000000 -#define mmUVD_DPG_RBC_RB_WPTR_CNTL_DEFAULT 0x00000000 -#define mmUVD_DPG_RBC_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_DPG_RBC_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_DPG_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000 - - -// addressBlock: uvd0_uvdnpdec -#define mmUVD_JPEG_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_GPCOM_VCPU_CMD_DEFAULT 0x00000000 -#define mmUVD_GPCOM_VCPU_DATA0_DEFAULT 0x00000000 -#define mmUVD_GPCOM_VCPU_DATA1_DEFAULT 0x00000000 -#define mmUVD_UDEC_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_UDEC_DB_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_UDEC_DBW_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_SUVD_CGC_GATE_DEFAULT 0x00000000 -#define mmUVD_SUVD_CGC_CTRL_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_POWER_STATUS_U_DEFAULT 0x00000000 -#define mmUVD_NO_OP_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH8_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO2_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI2_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE2_DEFAULT 0x00000000 -#define mmUVD_RB_RPTR2_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR2_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE_DEFAULT 0x00000000 -#define mmUVD_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_JRBC_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_DEFAULT 0x00000000 - - -// addressBlock: uvd0_uvddec -#define mmUVD_SEMA_CNTL_DEFAULT 0x00000003 -#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_JRBC_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_RB_RPTR3_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR3_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO3_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI3_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE3_DEFAULT 0x00000000 -#define mmJPEG_CGC_GATE_DEFAULT 0x00300000 -#define mmUVD_CTX_INDEX_DEFAULT 0x00000000 -#define mmUVD_CTX_DATA_DEFAULT 0x00000000 -#define mmUVD_CGC_GATE_DEFAULT 0x000fffff -#define mmUVD_CGC_CTRL_DEFAULT 0x1fff018d -#define mmUVD_GP_SCRATCH4_DEFAULT 0x00000000 -#define mmUVD_LMI_CTRL2_DEFAULT 0x003e0000 -#define mmUVD_MASTINT_EN_DEFAULT 0x00000000 -#define mmJPEG_CGC_CTRL_DEFAULT 0x0000018d -#define mmUVD_LMI_CTRL_DEFAULT 0x00104340 -#define mmUVD_LMI_VM_CTRL_DEFAULT 0x00000000 -#define mmUVD_LMI_SWAP_CNTL_DEFAULT 0x00000000 -#define mmUVD_MP_SWAP_CNTL_DEFAULT 0x00000000 -#define mmUVD_MPC_SET_MUXA0_DEFAULT 0x00002040 -#define mmUVD_MPC_SET_MUXA1_DEFAULT 0x00000000 -#define mmUVD_MPC_SET_MUXB0_DEFAULT 0x00002040 -#define mmUVD_MPC_SET_MUXB1_DEFAULT 0x00000000 -#define mmUVD_MPC_SET_MUX_DEFAULT 0x00000088 -#define mmUVD_MPC_SET_ALU_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_SIZE0_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_SIZE1_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_SIZE2_DEFAULT 0x00000000 -#define mmUVD_VCPU_CNTL_DEFAULT 0x0ff20000 -#define mmUVD_SOFT_RESET_DEFAULT 0x00000008 -#define mmUVD_LMI_RBC_IB_VMID_DEFAULT 0x00000000 -#define mmUVD_RBC_IB_SIZE_DEFAULT 0x00000000 -#define mmUVD_LMI_RBC_RB_VMID_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_WPTR_CNTL_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_CNTL_DEFAULT 0x01000101 -#define mmUVD_RBC_RB_RPTR_ADDR_DEFAULT 0x00000000 -#define mmUVD_STATUS_DEFAULT 0x00000000 -#define mmUVD_SEMA_TIMEOUT_STATUS_DEFAULT 0x00000000 -#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000 -#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_DEFAULT 0x02000000 -#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000 -#define mmUVD_CONTEXT_ID_DEFAULT 0x00000000 -#define mmUVD_CONTEXT_ID2_DEFAULT 0x00000000 - - -#endif -- GitLab From 18297a215ba44a9a28aea87486ec52aecf807e13 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 23 Nov 2017 14:08:34 +0800 Subject: [PATCH 0932/2547] drm/amd/include:cleanup vega10 vce header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/vega10/VCE folder. Signed-off-by: Feifei Xu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +++--- .../include/asic_reg/{vega10/VCE => vce}/vce_4_0_default.h | 0 .../include/asic_reg/{vega10/VCE => vce}/vce_4_0_offset.h | 0 .../include/asic_reg/{vega10/VCE => vce}/vce_4_0_sh_mask.h | 0 5 files changed, 6 insertions(+), 6 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/VCE => vce}/vce_4_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/VCE => vce}/vce_4_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/VCE => vce}/vce_4_0_sh_mask.h (100%) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 83e26caf1211..c122e95efe7d 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -32,9 +32,9 @@ #include "vega10/soc15ip.h" #include "uvd/uvd_7_0_offset.h" #include "uvd/uvd_7_0_sh_mask.h" -#include "vega10/VCE/vce_4_0_offset.h" -#include "vega10/VCE/vce_4_0_default.h" -#include "vega10/VCE/vce_4_0_sh_mask.h" +#include "vce/vce_4_0_offset.h" +#include "vce/vce_4_0_default.h" +#include "vce/vce_4_0_sh_mask.h" #include "vega10/NBIF/nbif_6_1_offset.h" #include "hdp/hdp_4_0_offset.h" #include "vega10/MMHUB/mmhub_1_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 75745544600a..1b28c91506eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -33,9 +33,9 @@ #include "mmsch_v1_0.h" #include "vega10/soc15ip.h" -#include "vega10/VCE/vce_4_0_offset.h" -#include "vega10/VCE/vce_4_0_default.h" -#include "vega10/VCE/vce_4_0_sh_mask.h" +#include "vce/vce_4_0_offset.h" +#include "vce/vce_4_0_default.h" +#include "vce/vce_4_0_sh_mask.h" #include "vega10/MMHUB/mmhub_1_0_offset.h" #include "vega10/MMHUB/mmhub_1_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h rename to drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h -- GitLab From cde5c34f63a6bbd082e3ce993919f23f1ac5fb68 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Fri, 24 Nov 2017 10:29:00 +0800 Subject: [PATCH 0933/2547] drm/amd/include:cleanup vega10 gc header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/vega10/GC folder. Signed-off-by: Feifei Xu Signed-off-by: Feifei Xu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- .../amd/include/asic_reg/{vega10/GC => gc}/gc_9_0_default.h | 0 .../amd/include/asic_reg/{vega10/GC => gc}/gc_9_0_offset.h | 0 .../amd/include/asic_reg/{vega10/GC => gc}/gc_9_0_sh_mask.h | 0 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h | 6 +++--- 10 files changed, 14 insertions(+), 14 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/GC => gc}/gc_9_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/GC => gc}/gc_9_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/GC => gc}/gc_9_0_sh_mask.h (100%) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 4fc6a2cf1d83..35e134df7e07 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -29,8 +29,8 @@ #include "soc15d.h" #include "vega10/soc15ip.h" -#include "vega10/GC/gc_9_0_offset.h" -#include "vega10/GC/gc_9_0_sh_mask.h" +#include "gc/gc_9_0_offset.h" +#include "gc/gc_9_0_sh_mask.h" #include "vega10/vega10_enum.h" #include "hdp/hdp_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index c17996e18086..9c93b20bf4ed 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -24,9 +24,9 @@ #include "gfxhub_v1_0.h" #include "vega10/soc15ip.h" -#include "vega10/GC/gc_9_0_offset.h" -#include "vega10/GC/gc_9_0_sh_mask.h" -#include "vega10/GC/gc_9_0_default.h" +#include "gc/gc_9_0_offset.h" +#include "gc/gc_9_0_sh_mask.h" +#include "gc/gc_9_0_default.h" #include "vega10/vega10_enum.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 2760adaa767b..bee0ea11446e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -28,7 +28,7 @@ #include "vega10/soc15ip.h" #include "hdp/hdp_4_0_offset.h" #include "hdp/hdp_4_0_sh_mask.h" -#include "vega10/GC/gc_9_0_sh_mask.h" +#include "gc/gc_9_0_sh_mask.h" #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" #include "vega10/vega10_enum.h" diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index d31259e5bb45..7405d7bb43b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -25,8 +25,8 @@ #include "vega10/soc15ip.h" #include "vega10/NBIO/nbio_6_1_offset.h" #include "vega10/NBIO/nbio_6_1_sh_mask.h" -#include "vega10/GC/gc_9_0_offset.h" -#include "vega10/GC/gc_9_0_sh_mask.h" +#include "gc/gc_9_0_offset.h" +#include "gc/gc_9_0_sh_mask.h" #include "soc15.h" #include "vega10_ih.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 53df7446295e..ff93070e3bf0 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -34,7 +34,7 @@ #include "vega10/soc15ip.h" #include "mp/mp_9_0_offset.h" #include "mp/mp_9_0_sh_mask.h" -#include "vega10/GC/gc_9_0_offset.h" +#include "gc/gc_9_0_offset.h" #include "sdma0/sdma0_4_0_offset.h" #include "vega10/NBIO/nbio_6_1_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 77c6d1887079..47cef08c9951 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -36,8 +36,8 @@ #include "vega10/soc15ip.h" #include "uvd/uvd_7_0_offset.h" -#include "vega10/GC/gc_9_0_offset.h" -#include "vega10/GC/gc_9_0_sh_mask.h" +#include "gc/gc_9_0_offset.h" +#include "gc/gc_9_0_sh_mask.h" #include "sdma0/sdma0_4_0_offset.h" #include "sdma1/sdma1_4_0_offset.h" #include "hdp/hdp_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h rename to drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h index e316cd79a321..4aec8f2415e8 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h @@ -31,9 +31,9 @@ #include "asic_reg/mp/mp_9_0_offset.h" #include "asic_reg/mp/mp_9_0_sh_mask.h" -#include "asic_reg/vega10/GC/gc_9_0_default.h" -#include "asic_reg/vega10/GC/gc_9_0_offset.h" -#include "asic_reg/vega10/GC/gc_9_0_sh_mask.h" +#include "asic_reg/gc/gc_9_0_default.h" +#include "asic_reg/gc/gc_9_0_offset.h" +#include "asic_reg/gc/gc_9_0_sh_mask.h" #include "asic_reg/vega10/NBIO/nbio_6_1_default.h" #include "asic_reg/vega10/NBIO/nbio_6_1_offset.h" -- GitLab From 65417d9f553b5877a3fa4e32544e6a2bcb539ea9 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 23 Nov 2017 14:30:43 +0800 Subject: [PATCH 0934/2547] drm/amd/include:cleanup vega10 mmhub header files. Cleanup asic_reg/vega10/MMHUB folder. Signed-off-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- .../asic_reg/{vega10/MMHUB => mmhub}/mmhub_1_0_default.h | 0 .../asic_reg/{vega10/MMHUB => mmhub}/mmhub_1_0_offset.h | 0 .../asic_reg/{vega10/MMHUB => mmhub}/mmhub_1_0_sh_mask.h | 0 8 files changed, 10 insertions(+), 10 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/MMHUB => mmhub}/mmhub_1_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/MMHUB => mmhub}/mmhub_1_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/MMHUB => mmhub}/mmhub_1_0_sh_mask.h (100%) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index bee0ea11446e..a201efd41279 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -32,7 +32,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" #include "vega10/vega10_enum.h" -#include "vega10/MMHUB/mmhub_1_0_offset.h" +#include "mmhub/mmhub_1_0_offset.h" #include "athub/athub_1_0_offset.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index 04e9527f5bce..d2268575b098 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -24,9 +24,9 @@ #include "mmhub_v1_0.h" #include "vega10/soc15ip.h" -#include "vega10/MMHUB/mmhub_1_0_offset.h" -#include "vega10/MMHUB/mmhub_1_0_sh_mask.h" -#include "vega10/MMHUB/mmhub_1_0_default.h" +#include "mmhub/mmhub_1_0_offset.h" +#include "mmhub/mmhub_1_0_sh_mask.h" +#include "mmhub/mmhub_1_0_default.h" #include "athub/athub_1_0_offset.h" #include "athub/athub_1_0_sh_mask.h" #include "vega10/vega10_enum.h" diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 6d14ea62d5c1..67b34914679f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -32,8 +32,8 @@ #include "sdma0/sdma0_4_0_sh_mask.h" #include "sdma1/sdma1_4_0_offset.h" #include "sdma1/sdma1_4_0_sh_mask.h" -#include "vega10/MMHUB/mmhub_1_0_offset.h" -#include "vega10/MMHUB/mmhub_1_0_sh_mask.h" +#include "mmhub/mmhub_1_0_offset.h" +#include "mmhub/mmhub_1_0_sh_mask.h" #include "hdp/hdp_4_0_offset.h" #include "raven1/SDMA0/sdma0_4_1_default.h" diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index c122e95efe7d..19beff3505fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -37,8 +37,8 @@ #include "vce/vce_4_0_sh_mask.h" #include "vega10/NBIF/nbif_6_1_offset.h" #include "hdp/hdp_4_0_offset.h" -#include "vega10/MMHUB/mmhub_1_0_offset.h" -#include "vega10/MMHUB/mmhub_1_0_sh_mask.h" +#include "mmhub/mmhub_1_0_offset.h" +#include "mmhub/mmhub_1_0_sh_mask.h" static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev); static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 1b28c91506eb..a6bb51b1322c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -36,8 +36,8 @@ #include "vce/vce_4_0_offset.h" #include "vce/vce_4_0_default.h" #include "vce/vce_4_0_sh_mask.h" -#include "vega10/MMHUB/mmhub_1_0_offset.h" -#include "vega10/MMHUB/mmhub_1_0_sh_mask.h" +#include "mmhub/mmhub_1_0_offset.h" +#include "mmhub/mmhub_1_0_sh_mask.h" #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_default.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h rename to drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h -- GitLab From f0a58aa3f2ca113ff1f435cd186a0d3895a1cafb Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 23 Nov 2017 14:54:48 +0800 Subject: [PATCH 0935/2547] drm/amd/include:cleanup vega10 nbio header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/vega10/NBIO folder. Signed-off-by: Feifei Xu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +- drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 2 +- .../asic_reg/{vega10/NBIO => nbio}/nbio_6_1_default.h | 0 .../asic_reg/{vega10/NBIO => nbio}/nbio_6_1_offset.h | 0 .../asic_reg/{vega10/NBIO => nbio}/nbio_6_1_sh_mask.h | 0 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h | 6 +++--- 8 files changed, 10 insertions(+), 10 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/NBIO => nbio}/nbio_6_1_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/NBIO => nbio}/nbio_6_1_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/NBIO => nbio}/nbio_6_1_sh_mask.h (100%) diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index 7405d7bb43b7..19327b782124 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -23,8 +23,8 @@ #include "amdgpu.h" #include "vega10/soc15ip.h" -#include "vega10/NBIO/nbio_6_1_offset.h" -#include "vega10/NBIO/nbio_6_1_sh_mask.h" +#include "nbio/nbio_6_1_offset.h" +#include "nbio/nbio_6_1_sh_mask.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" #include "soc15.h" diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index 904a1bab9b9f..fd9f71e8a2d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -25,9 +25,9 @@ #include "nbio_v6_1.h" #include "vega10/soc15ip.h" -#include "vega10/NBIO/nbio_6_1_default.h" -#include "vega10/NBIO/nbio_6_1_offset.h" -#include "vega10/NBIO/nbio_6_1_sh_mask.h" +#include "nbio/nbio_6_1_default.h" +#include "nbio/nbio_6_1_offset.h" +#include "nbio/nbio_6_1_sh_mask.h" #include "vega10/vega10_enum.h" #define smnCPM_CONTROL 0x11180460 diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index ff93070e3bf0..7a9832b8ff51 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -36,7 +36,7 @@ #include "mp/mp_9_0_sh_mask.h" #include "gc/gc_9_0_offset.h" #include "sdma0/sdma0_4_0_offset.h" -#include "vega10/NBIO/nbio_6_1_offset.h" +#include "nbio/nbio_6_1_offset.h" MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index e59a4e6d6a55..9d64e669ba52 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -57,7 +57,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" #include "vega10/soc15ip.h" -#include "vega10/NBIO/nbio_6_1_offset.h" +#include "nbio/nbio_6_1_offset.h" #include "reg_helper.h" #include "dce100/dce100_resource.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_default.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h rename to drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h index 4aec8f2415e8..faf7ac044348 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h @@ -35,9 +35,9 @@ #include "asic_reg/gc/gc_9_0_offset.h" #include "asic_reg/gc/gc_9_0_sh_mask.h" -#include "asic_reg/vega10/NBIO/nbio_6_1_default.h" -#include "asic_reg/vega10/NBIO/nbio_6_1_offset.h" -#include "asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h" +#include "asic_reg/nbio/nbio_6_1_default.h" +#include "asic_reg/nbio/nbio_6_1_offset.h" +#include "asic_reg/nbio/nbio_6_1_sh_mask.h" #endif -- GitLab From daad67b51e89f50e50ec157bddc57c2c159e43c1 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 23 Nov 2017 15:02:23 +0800 Subject: [PATCH 0936/2547] drm/amd/include:cleanup vega10 nbif header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/vega10/NBIF folder. Signed-off-by: Feifei Xu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +- .../{vega10/NBIF => nbif}/nbif_6_1_offset.h | 0 .../{vega10/NBIF => nbif}/nbif_6_1_sh_mask.h | 0 .../asic_reg/vega10/NBIF/nbif_6_1_default.h | 1271 ----------------- 4 files changed, 1 insertion(+), 1272 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/NBIF => nbif}/nbif_6_1_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/NBIF => nbif}/nbif_6_1_sh_mask.h (100%) delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 19beff3505fc..c271c6b4b451 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -35,7 +35,7 @@ #include "vce/vce_4_0_offset.h" #include "vce/vce_4_0_default.h" #include "vce/vce_4_0_sh_mask.h" -#include "vega10/NBIF/nbif_6_1_offset.h" +#include "nbif/nbif_6_1_offset.h" #include "hdp/hdp_4_0_offset.h" #include "mmhub/mmhub_1_0_offset.h" #include "mmhub/mmhub_1_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h deleted file mode 100644 index daa7eaef01b8..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h +++ /dev/null @@ -1,1271 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _nbif_6_1_DEFAULT_HEADER -#define _nbif_6_1_DEFAULT_HEADER - - -// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp -// base address: 0x0 -#define cfgVENDOR_ID_DEFAULT 0x00000000 -#define cfgDEVICE_ID_DEFAULT 0x00000000 -#define cfgCOMMAND_DEFAULT 0x00000000 -#define cfgSTATUS_DEFAULT 0x00000000 -#define cfgREVISION_ID_DEFAULT 0x00000000 -#define cfgPROG_INTERFACE_DEFAULT 0x00000000 -#define cfgSUB_CLASS_DEFAULT 0x00000000 -#define cfgBASE_CLASS_DEFAULT 0x00000000 -#define cfgCACHE_LINE_DEFAULT 0x00000000 -#define cfgLATENCY_DEFAULT 0x00000000 -#define cfgHEADER_DEFAULT 0x00000000 -#define cfgBIST_DEFAULT 0x00000000 -#define cfgBASE_ADDR_1_DEFAULT 0x00000000 -#define cfgBASE_ADDR_2_DEFAULT 0x00000000 -#define cfgBASE_ADDR_3_DEFAULT 0x00000000 -#define cfgBASE_ADDR_4_DEFAULT 0x00000000 -#define cfgBASE_ADDR_5_DEFAULT 0x00000000 -#define cfgBASE_ADDR_6_DEFAULT 0x00000000 -#define cfgADAPTER_ID_DEFAULT 0x00000000 -#define cfgROM_BASE_ADDR_DEFAULT 0x00000000 -#define cfgCAP_PTR_DEFAULT 0x00000000 -#define cfgINTERRUPT_LINE_DEFAULT 0x000000ff -#define cfgINTERRUPT_PIN_DEFAULT 0x00000000 -#define cfgMIN_GRANT_DEFAULT 0x00000000 -#define cfgMAX_LATENCY_DEFAULT 0x00000000 -#define cfgVENDOR_CAP_LIST_DEFAULT 0x00000000 -#define cfgADAPTER_ID_W_DEFAULT 0x00000000 -#define cfgPMI_CAP_LIST_DEFAULT 0x00000000 -#define cfgPMI_CAP_DEFAULT 0x00000000 -#define cfgPMI_STATUS_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_CAP_LIST_DEFAULT 0x0000a000 -#define cfgPCIE_CAP_DEFAULT 0x00000002 -#define cfgDEVICE_CAP_DEFAULT 0x10000000 -#define cfgDEVICE_CNTL_DEFAULT 0x00002810 -#define cfgDEVICE_STATUS_DEFAULT 0x00000000 -#define cfgLINK_CAP_DEFAULT 0x00011c03 -#define cfgLINK_CNTL_DEFAULT 0x00000000 -#define cfgLINK_STATUS_DEFAULT 0x00000001 -#define cfgDEVICE_CAP2_DEFAULT 0x00000000 -#define cfgDEVICE_CNTL2_DEFAULT 0x00000000 -#define cfgDEVICE_STATUS2_DEFAULT 0x00000000 -#define cfgLINK_CAP2_DEFAULT 0x0000000e -#define cfgLINK_CNTL2_DEFAULT 0x00000003 -#define cfgLINK_STATUS2_DEFAULT 0x00000000 -#define cfgSLOT_CAP2_DEFAULT 0x00000000 -#define cfgSLOT_CNTL2_DEFAULT 0x00000000 -#define cfgSLOT_STATUS2_DEFAULT 0x00000000 -#define cfgMSI_CAP_LIST_DEFAULT 0x0000c000 -#define cfgMSI_MSG_CNTL_DEFAULT 0x00000080 -#define cfgMSI_MSG_ADDR_LO_DEFAULT 0x00000000 -#define cfgMSI_MSG_ADDR_HI_DEFAULT 0x00000000 -#define cfgMSI_MSG_DATA_DEFAULT 0x00000000 -#define cfgMSI_MSG_DATA_64_DEFAULT 0x00000000 -#define cfgMSI_MASK_DEFAULT 0x00000000 -#define cfgMSI_PENDING_DEFAULT 0x00000000 -#define cfgMSI_MASK_64_DEFAULT 0x00000000 -#define cfgMSI_PENDING_64_DEFAULT 0x00000000 -#define cfgMSIX_CAP_LIST_DEFAULT 0x00000000 -#define cfgMSIX_MSG_CNTL_DEFAULT 0x00000000 -#define cfgMSIX_TABLE_DEFAULT 0x00000000 -#define cfgMSIX_PBA_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 -#define cfgPCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 -#define cfgPCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 -#define cfgPCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 -#define cfgPCIE_PORT_VC_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_PORT_VC_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 -#define cfgPCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe -#define cfgPCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 -#define cfgPCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 -#define cfgPCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 -#define cfgPCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 -#define cfgPCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 -#define cfgPCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_CORR_ERR_MASK_DEFAULT 0x00002000 -#define cfgPCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_HDR_LOG0_DEFAULT 0x00000000 -#define cfgPCIE_HDR_LOG1_DEFAULT 0x00000000 -#define cfgPCIE_HDR_LOG2_DEFAULT 0x00000000 -#define cfgPCIE_HDR_LOG3_DEFAULT 0x00000000 -#define cfgPCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 -#define cfgPCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_ERR_SRC_ID_DEFAULT 0x00000000 -#define cfgPCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 -#define cfgPCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 -#define cfgPCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 -#define cfgPCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 -#define cfgPCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 -#define cfgPCIE_BAR1_CAP_DEFAULT 0x00000000 -#define cfgPCIE_BAR1_CNTL_DEFAULT 0x00000020 -#define cfgPCIE_BAR2_CAP_DEFAULT 0x00000000 -#define cfgPCIE_BAR2_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_BAR3_CAP_DEFAULT 0x00000000 -#define cfgPCIE_BAR3_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_BAR4_CAP_DEFAULT 0x00000000 -#define cfgPCIE_BAR4_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_BAR5_CAP_DEFAULT 0x00000000 -#define cfgPCIE_BAR5_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_BAR6_CAP_DEFAULT 0x00000000 -#define cfgPCIE_BAR6_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 -#define cfgPCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 -#define cfgPCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 -#define cfgPCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 -#define cfgPCIE_DPA_CAP_DEFAULT 0x00000000 -#define cfgPCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 -#define cfgPCIE_DPA_STATUS_DEFAULT 0x00000100 -#define cfgPCIE_DPA_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 -#define cfgPCIE_LINK_CNTL3_DEFAULT 0x00000000 -#define cfgPCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 -#define cfgPCIE_ACS_CAP_DEFAULT 0x00000000 -#define cfgPCIE_ACS_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 -#define cfgPCIE_ATS_CAP_DEFAULT 0x00000000 -#define cfgPCIE_ATS_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 -#define cfgPCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 -#define cfgPCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 -#define cfgPCIE_PASID_CAP_DEFAULT 0x00000000 -#define cfgPCIE_PASID_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 -#define cfgPCIE_TPH_REQR_CAP_DEFAULT 0x00000000 -#define cfgPCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 -#define cfgPCIE_MC_CAP_DEFAULT 0x00000000 -#define cfgPCIE_MC_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_MC_ADDR0_DEFAULT 0x00000000 -#define cfgPCIE_MC_ADDR1_DEFAULT 0x00000000 -#define cfgPCIE_MC_RCV0_DEFAULT 0x00000000 -#define cfgPCIE_MC_RCV1_DEFAULT 0x00000000 -#define cfgPCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 -#define cfgPCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 -#define cfgPCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 -#define cfgPCIE_LTR_CAP_DEFAULT 0x00000000 -#define cfgPCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 -#define cfgPCIE_ARI_CAP_DEFAULT 0x00000000 -#define cfgPCIE_ARI_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_CAP_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_CONTROL_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 - - -// addressBlock: bif_cfg_dev0_swds_bifcfgdecp -// base address: 0x0 -#define mmSUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 -#define mmIO_BASE_LIMIT_DEFAULT 0x00000000 -#define mmSECONDARY_STATUS_DEFAULT 0x00000000 -#define mmMEM_BASE_LIMIT_DEFAULT 0x00000000 -#define mmPREF_BASE_LIMIT_DEFAULT 0x00000000 -#define mmPREF_BASE_UPPER_DEFAULT 0x00000000 -#define mmPREF_LIMIT_UPPER_DEFAULT 0x00000000 -#define mmIO_BASE_LIMIT_HI_DEFAULT 0x00000000 -#define mmIRQ_BRIDGE_CNTL_DEFAULT 0x00000000 -#define mmSLOT_CAP_DEFAULT 0x00000000 -#define mmSLOT_CNTL_DEFAULT 0x00000000 -#define mmSLOT_STATUS_DEFAULT 0x00000000 -#define mmSSID_CAP_LIST_DEFAULT 0x00000000 -#define mmSSID_CAP_DEFAULT 0x00000000 - - -// addressBlock: rcc_shadow_reg_shadowdec -// base address: 0x0 -#define ixSHADOW_COMMAND_DEFAULT 0x00000000 -#define ixSHADOW_BASE_ADDR_1_DEFAULT 0x00000000 -#define ixSHADOW_BASE_ADDR_2_DEFAULT 0x00000000 -#define ixSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 -#define ixSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000 -#define ixSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000 -#define ixSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000 -#define ixSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000 -#define ixSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000 -#define ixSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 -#define ixSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 -#define ixSUC_INDEX_DEFAULT 0x00000000 -#define ixSUC_DATA_DEFAULT 0x00000000 - - -// addressBlock: bif_bx_pf_SUMDEC -// base address: 0x0 -#define ixSUM_INDEX_DEFAULT 0x00000000 -#define ixSUM_DATA_DEFAULT 0x00000000 - - -// addressBlock: gdc_GDCDEC -// base address: 0x1400000 -#define mmA2S_CNTL_CL0_DEFAULT 0x00280540 -#define mmA2S_CNTL_CL1_DEFAULT 0x00282540 -#define mmA2S_CNTL_CL2_DEFAULT 0x002825a0 -#define mmA2S_CNTL_CL3_DEFAULT 0x00282550 -#define mmA2S_CNTL_CL4_DEFAULT 0x00282550 -#define mmA2S_CNTL_SW0_DEFAULT 0x08080005 -#define mmA2S_CNTL_SW1_DEFAULT 0x08080205 -#define mmA2S_CNTL_SW2_DEFAULT 0x08080200 -#define mmNGDC_MGCG_CTRL_DEFAULT 0x00000080 -#define mmA2S_MISC_CNTL_DEFAULT 0x00000003 -#define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f -#define mmNGDC_RESERVED_0_DEFAULT 0x00000000 -#define mmNGDC_RESERVED_1_DEFAULT 0x00000000 -#define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 -#define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 -#define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 -#define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 -#define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 -#define mmS2A_MISC_CNTL_DEFAULT 0x00000000 -#define mmA2S_CNTL2_SEC_CL0_DEFAULT 0x00000006 -#define mmA2S_CNTL2_SEC_CL1_DEFAULT 0x00000006 -#define mmA2S_CNTL2_SEC_CL2_DEFAULT 0x00000006 -#define mmA2S_CNTL2_SEC_CL3_DEFAULT 0x00000006 -#define mmA2S_CNTL2_SEC_CL4_DEFAULT 0x00000006 - - -// addressBlock: nbif_sion_SIONDEC -// base address: 0x1400000 -#define ixSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_Req_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_Req_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_Req_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_Req_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_Req_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_Req_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_Req_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_Req_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CNTL_REG0_DEFAULT 0x00000000 -#define ixSION_CNTL_REG1_DEFAULT 0x00000000 - - -// addressBlock: syshub_mmreg_direct_syshubdirect -// base address: 0x1400000 -#define ixSYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 -#define ixSYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 -#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 -#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 -#define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixDMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 -#define ixSYSHUB_CG_CNTL_DEFAULT 0x00082000 -#define ixSYSHUB_TRANS_IDLE_DEFAULT 0x00000000 -#define ixSYSHUB_HP_TIMER_DEFAULT 0x00000100 -#define ixSYSHUB_SCRATCH_DEFAULT 0x00000040 -#define ixSYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 -#define ixSYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 -#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 -#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 -#define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixDMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 - - -// addressBlock: gdc_ras_gdc_ras_regblk -// base address: 0x1400000 -#define ixGDC_RAS_LEAF0_CTRL_DEFAULT 0x00000000 -#define ixGDC_RAS_LEAF1_CTRL_DEFAULT 0x00000000 -#define ixGDC_RAS_LEAF2_CTRL_DEFAULT 0x00000000 -#define ixGDC_RAS_LEAF3_CTRL_DEFAULT 0x00000000 -#define ixGDC_RAS_LEAF4_CTRL_DEFAULT 0x00000000 -#define ixGDC_RAS_LEAF5_CTRL_DEFAULT 0x00000000 - - -// addressBlock: gdc_rst_GDCRST_DEC -// base address: 0x1400000 -#define ixSHUB_PF_FLR_RST_DEFAULT 0x00000000 -#define ixSHUB_GFX_DRV_MODE1_RST_DEFAULT 0x00000000 -#define ixSHUB_LINK_RESET_DEFAULT 0x00000000 -#define ixSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000 -#define ixSHUB_HARD_RST_CTRL_DEFAULT 0x0000001b -#define ixSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009 -#define ixSHUB_SDP_PORT_RST_DEFAULT 0x00000000 - - -// addressBlock: bif_bx_pf_SYSDEC -// base address: 0x0 -#define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000 -#define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000 -#define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000 -#define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_0_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_1_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_2_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_3_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_4_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_5_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_6_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_7_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_8_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_9_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_10_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_11_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_12_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_13_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_14_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_15_DEFAULT 0x00000000 -#define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000 -#define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000 -#define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 - - -// addressBlock: bif_bx_pf_SYSPFVFDEC -// base address: 0x0 -#define mmMM_INDEX_DEFAULT 0x00000000 -#define mmMM_DATA_DEFAULT 0x00000000 -#define mmMM_INDEX_HI_DEFAULT 0x00000000 -#define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 -#define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000 -#define mmPCIE_INDEX_DEFAULT 0x00000000 -#define mmPCIE_DATA_DEFAULT 0x00000000 -#define mmPCIE_INDEX2_DEFAULT 0x00000000 -#define mmPCIE_DATA2_DEFAULT 0x00000000 - - -// addressBlock: rcc_dwn_BIFDEC1 -// base address: 0x0 -#define mmDN_PCIE_RESERVED_DEFAULT 0x00000000 -#define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000 -#define mmDN_PCIE_CNTL_DEFAULT 0x00000000 -#define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 -#define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000 -#define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080 -#define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000 -#define mmDN_PCIE_STRAP_F0_DEFAULT 0x00000001 -#define mmDN_PCIE_STRAP_MISC_DEFAULT 0x00000000 -#define mmDN_PCIE_STRAP_MISC2_DEFAULT 0x00000000 - - -// addressBlock: rcc_dwnp_BIFDEC1 -// base address: 0x0 -#define mmPCIEP_RESERVED_DEFAULT 0x00000000 -#define mmPCIEP_SCRATCH_DEFAULT 0x00000000 -#define mmPCIE_ERR_CNTL_DEFAULT 0x00000500 -#define mmPCIE_RX_CNTL_DEFAULT 0x00000000 -#define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 -#define mmPCIE_LC_CNTL2_DEFAULT 0x00000000 -#define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000 -#define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 - - -// addressBlock: rcc_ep_BIFDEC1 -// base address: 0x0 -#define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000 -#define mmEP_PCIE_CNTL_DEFAULT 0x00000100 -#define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000 -#define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000 -#define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000 -#define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080 -#define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000 -#define mmEP_PCIE_OBFF_CNTL_DEFAULT 0x00012774 -#define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00003468 -#define mmEP_PCIE_STRAP_MISC_DEFAULT 0x00000000 -#define mmEP_PCIE_STRAP_MISC2_DEFAULT 0x00000000 -#define mmEP_PCIE_STRAP_PI_DEFAULT 0x00000000 -#define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 -#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 -#define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a -#define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000 -#define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000 -#define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000 -#define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 -#define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500 -#define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000 -#define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 - - -// addressBlock: bif_bx_pf_BIFDEC1 -// base address: 0x0 -#define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 -#define mmBUS_CNTL_DEFAULT 0x00000000 -#define mmBIF_SCRATCH0_DEFAULT 0x00000000 -#define mmBIF_SCRATCH1_DEFAULT 0x00000000 -#define mmBX_RESET_EN_DEFAULT 0x00010003 -#define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000 -#define mmBX_RESET_CNTL_DEFAULT 0x00000000 -#define mmINTERRUPT_CNTL_DEFAULT 0x00000010 -#define mmINTERRUPT_CNTL2_DEFAULT 0x00000000 -#define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0 -#define mmCLKREQB_PERF_COUNTER_DEFAULT 0x00000000 -#define mmBIF_CLK_CTRL_DEFAULT 0x00000000 -#define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 -#define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000 -#define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 -#define mmBIF_SLVARB_MODE_DEFAULT 0x00000000 -#define mmBIF_FB_EN_DEFAULT 0x00000000 -#define mmBIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f -#define mmBIF_PERFMON_CNTL_DEFAULT 0x00000000 -#define mmBIF_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 -#define mmBIF_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 -#define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 -#define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 -#define mmBACO_CNTL_DEFAULT 0x00000000 -#define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 -#define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x00000100 -#define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 -#define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000400 -#define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000100 -#define mmMEM_TYPE_CNTL_DEFAULT 0x00000000 -#define mmSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000 -#define mmBIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc -#define mmBIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000 -#define mmBIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc -#define mmBIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000 -#define mmBIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc -#define mmBIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000 -#define mmBIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc -#define mmBIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00 -#define mmBIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc -#define mmBIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00 -#define mmBIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc -#define mmBIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_FB_CMP_DEFAULT 0x00000000 -#define mmBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780 -#define mmBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc -#define mmBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800 -#define mmBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c -#define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c -#define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 -#define mmBIF_RB_CNTL_DEFAULT 0x00000000 -#define mmBIF_RB_BASE_DEFAULT 0x00000000 -#define mmBIF_RB_RPTR_DEFAULT 0x00000000 -#define mmBIF_RB_WPTR_DEFAULT 0x00000000 -#define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmMAILBOX_INDEX_DEFAULT 0x00000000 -#define mmBIF_GPUIOV_RESET_NOTIFICATION_DEFAULT 0x00000000 -#define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 -#define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 -#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 -#define mmBIF_GMI_WRR_WEIGHT_DEFAULT 0x00202020 -#define mmNBIF_STRAP_WRITE_CTRL_DEFAULT 0x00000000 -#define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 -#define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 -#define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 -#define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 - - -// addressBlock: rcc_pf_0_BIFDEC1 -// base address: 0x0 -#define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000 -#define mmRCC_RESET_EN_DEFAULT 0x00008000 -#define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000 -#define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000 -#define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000 -#define mmRCC_BUS_CNTL_DEFAULT 0x00000000 -#define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000 -#define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000 -#define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000 -#define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000 -#define mmRCC_XDMA_LO_DEFAULT 0x00000000 -#define mmRCC_XDMA_HI_DEFAULT 0x00000000 -#define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 -#define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000 -#define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000 -#define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000 -#define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000 -#define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000 -#define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000 -#define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000 -#define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000 -#define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000 -#define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000 -#define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000 -#define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000 -#define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000 -#define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000 -#define mmRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000 -#define mmRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000 -#define mmRCC_DEV0_LINK_CNTL_DEFAULT 0x00000000 -#define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00000000 -#define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000 -#define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000 -#define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000 - - -// addressBlock: rcc_pf_0_BIFDEC2 -// base address: 0x0 -#define mmGFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 -#define mmGFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 -#define mmGFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 -#define mmGFXMSIX_PBA_DEFAULT 0x00000000 - - -// addressBlock: rcc_strap_BIFDEC1 -// base address: 0x0 -#define mmRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0 -#define mmRCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e -#define mmRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009 -#define mmRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 -#define mmRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 -#define mmRCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002 -#define mmRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000 -#define mmRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 -#define mmRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000 -#define mmRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001 -#define mmRCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042 -#define mmRCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022 -#define mmRCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002 -#define mmRCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000 -#define mmRCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001 -#define mmRCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 -#define mmRCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022 -#define mmRCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 - - -// addressBlock: bif_bx_pf_BIFPFVFDEC1 -// base address: 0x0 -#define mmBIF_BME_STATUS_DEFAULT 0x00000000 -#define mmBIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 -#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 -#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 -#define mmDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000000 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 -#define mmGPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 -#define mmGPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 -#define mmBIF_TRANS_PENDING_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 -#define mmMAILBOX_CONTROL_DEFAULT 0x00000000 -#define mmMAILBOX_INT_CNTL_DEFAULT 0x00000000 -#define mmBIF_VMHV_MAILBOX_DEFAULT 0x00000000 - - -// addressBlock: rcc_pf_0_BIFPFVFDEC1 -// base address: 0x0 -#define mmRCC_DOORBELL_APER_EN_DEFAULT 0x00000000 -#define mmRCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 -#define mmRCC_CONFIG_RESERVED_DEFAULT 0x00000000 -#define mmRCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 - - -// addressBlock: syshub_mmreg_ind_syshubdec -// base address: 0x0 -#define mmSYSHUB_INDEX_DEFAULT 0x00000000 -#define mmSYSHUB_DATA_DEFAULT 0x00000000 - - -// addressBlock: rcc_strap_rcc_strap_internal -// base address: 0x10100000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP1_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP7_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP13_DEFAULT 0x00000000 - - -// addressBlock: bif_rst_bif_rst_regblk -// base address: 0x10100000 -#define ixHARD_RST_CTRL_DEFAULT 0xb0000055 -#define ixRSMU_SOFT_RST_CTRL_DEFAULT 0x90000000 -#define ixSELF_SOFT_RST_DEFAULT 0x00000000 -#define ixGFX_DRV_MODE1_RST_CTRL_DEFAULT 0x000000a9 -#define ixBIF_RST_MISC_CTRL_DEFAULT 0x00000644 -#define ixBIF_RST_MISC_CTRL2_DEFAULT 0x00000000 -#define ixBIF_RST_MISC_CTRL3_DEFAULT 0x00004900 -#define ixBIF_RST_GFXVF_FLR_IDLE_DEFAULT 0x00000000 -#define ixDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x0206a9a9 -#define ixDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000 -#define ixBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000 -#define ixBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000 -#define ixBIF_POWER_INTR_STS_DEFAULT 0x00000000 -#define ixBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000 -#define ixBIF_PF0_VF_FLR_INTR_STS_DEFAULT 0x00000000 -#define ixBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000 -#define ixBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000 -#define ixBIF_D3HOTD0_INTR_MASK_DEFAULT 0x000000ff -#define ixBIF_POWER_INTR_MASK_DEFAULT 0x00000000 -#define ixBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000 -#define ixBIF_PF0_VF_FLR_INTR_MASK_DEFAULT 0x00000000 -#define ixBIF_PF_FLR_RST_DEFAULT 0x00000000 -#define ixBIF_PF0_VF_FLR_RST_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000 - - -// addressBlock: bif_misc_bif_misc_regblk -// base address: 0x10100000 -#define ixMISC_SCRATCH_DEFAULT 0x00000000 -#define ixINTR_LINE_POLARITY_DEFAULT 0x00000000 -#define ixINTR_LINE_ENABLE_DEFAULT 0x00000000 -#define ixOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf -#define ixBIFC_MISC_CTRL0_DEFAULT 0x08000004 -#define ixBIFC_MISC_CTRL1_DEFAULT 0x00008004 -#define ixBIFC_BME_ERR_LOG_DEFAULT 0x00000000 -#define ixBIFC_RCCBIH_BME_ERR_LOG_DEFAULT 0x00000000 -#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x00000000 -#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x00000000 -#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x00000000 -#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x00000000 -#define ixNBIF_VWIRE_CTRL_DEFAULT 0x00000000 -#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 -#define ixNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 -#define ixNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000 -#define ixNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000 -#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000 -#define ixNBIF_MGCG_CTRL_DEFAULT 0x00000080 -#define ixNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000 -#define ixSMN_MST_CNTL0_DEFAULT 0x00000001 -#define ixSMN_MST_EP_CNTL1_DEFAULT 0x00000000 -#define ixSMN_MST_EP_CNTL2_DEFAULT 0x00000000 -#define ixNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 -#define ixNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 -#define ixNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000 -#define ixNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000 -#define ixBME_DUMMY_CNTL_0_DEFAULT 0x0000aaaa -#define ixBIFC_THT_CNTL_DEFAULT 0x00000222 -#define ixBIFC_HSTARB_CNTL_DEFAULT 0x00000000 -#define ixBIFC_GSI_CNTL_DEFAULT 0x000017c0 -#define ixBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000 -#define ixBIFC_SDP_CNTL_0_DEFAULT 0x003cf3cf -#define ixBIFC_PERF_CNTL_0_DEFAULT 0x00000000 -#define ixBIFC_PERF_CNTL_1_DEFAULT 0x00000000 -#define ixBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000 -#define ixBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000 -#define ixBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000 -#define ixBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000 -#define ixNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000 -#define ixSMN_MST_EP_CNTL3_DEFAULT 0x00000000 -#define ixSMN_MST_EP_CNTL4_DEFAULT 0x00000000 -#define ixBIF_SELFRING_BUFFER_VID_DEFAULT 0x0000605f -#define ixBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000 - - -// addressBlock: bif_ras_bif_ras_regblk -// base address: 0x10100000 -#define ixBIF_RAS_LEAF0_CTRL_DEFAULT 0x00000000 -#define ixBIF_RAS_LEAF1_CTRL_DEFAULT 0x00000000 -#define ixBIF_RAS_LEAF2_CTRL_DEFAULT 0x00000000 -#define ixBIF_RAS_MISC_CTRL_DEFAULT 0x00000000 -#define ixBIF_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000 -#define ixBIF_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000 - - -// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC -// base address: 0x10134000 -#define ixRCC_PFC_LTR_CNTL_DEFAULT 0x00000000 -#define ixRCC_PFC_PME_RESTORE_DEFAULT 0x00000000 -#define ixRCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 -#define ixRCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 -#define ixRCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 -#define ixRCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 -#define ixRCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 -#define ixRCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 -#define ixRCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 - - -// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC -// base address: 0x10134200 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 - - -// addressBlock: pciemsix_amdgfx_MSIXTDEC -// base address: 0x10170000 -#define ixPCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: pciemsix_amdgfx_MSIXPDEC -// base address: 0x10171000 -#define ixPCIEMSIX_PBA_DEFAULT 0x00000000 - - -// addressBlock: syshub_mmreg_ind_syshubind -// base address: 0x0 -#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 -#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL_DEFAULT 0x00082000 -#define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER_DEFAULT 0x00000100 -#define ixSYSHUBMMREGIND_SYSHUB_SCRATCH_DEFAULT 0x00000040 -#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 -#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 - -#endif -- GitLab From 424d9bb4d51c87b49f72a0c762bb551776ff640e Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 23 Nov 2017 15:09:51 +0800 Subject: [PATCH 0937/2547] drm/amd/include:cleanup vega10 smuio header files. Cleanup asic_reg/vega10/SMUIO folder. Signed-off-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +- .../SMUIO => smuio}/smuio_9_0_offset.h | 0 .../SMUIO => smuio}/smuio_9_0_sh_mask.h | 0 .../asic_reg/vega10/SMUIO/smuio_9_0_default.h | 100 ------------------ 4 files changed, 2 insertions(+), 102 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/SMUIO => smuio}/smuio_9_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/SMUIO => smuio}/smuio_9_0_sh_mask.h (100%) delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 47cef08c9951..85d7e6f1a3c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -44,8 +44,8 @@ #include "hdp/hdp_4_0_sh_mask.h" #include "mp/mp_9_0_offset.h" #include "mp/mp_9_0_sh_mask.h" -#include "vega10/SMUIO/smuio_9_0_offset.h" -#include "vega10/SMUIO/smuio_9_0_sh_mask.h" +#include "smuio/smuio_9_0_offset.h" +#include "smuio/smuio_9_0_sh_mask.h" #include "soc15.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h deleted file mode 100644 index 5c186c2e8739..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _smuio_9_0_DEFAULT_HEADER -#define _smuio_9_0_DEFAULT_HEADER - - -// addressBlock: smuio_smuio_SmuSmuioDec -#define mmROM_CNTL_DEFAULT 0x00000000 -#define mmROM_STATUS_DEFAULT 0x00000000 -#define mmCGTT_ROM_CLK_CTRL0_DEFAULT 0xc0000100 -#define mmROM_INDEX_DEFAULT 0x00000000 -#define mmROM_DATA_DEFAULT 0x00000000 -#define mmROM_START_DEFAULT 0x00000000 -#define mmROM_SW_CNTL_DEFAULT 0x00000000 -#define mmROM_SW_STATUS_DEFAULT 0x00000000 -#define mmROM_SW_COMMAND_DEFAULT 0x00000000 -#define mmROM_SW_DATA_1_DEFAULT 0x00000000 -#define mmROM_SW_DATA_2_DEFAULT 0x00000000 -#define mmROM_SW_DATA_3_DEFAULT 0x00000000 -#define mmROM_SW_DATA_4_DEFAULT 0x00000000 -#define mmROM_SW_DATA_5_DEFAULT 0x00000000 -#define mmROM_SW_DATA_6_DEFAULT 0x00000000 -#define mmROM_SW_DATA_7_DEFAULT 0x00000000 -#define mmROM_SW_DATA_8_DEFAULT 0x00000000 -#define mmROM_SW_DATA_9_DEFAULT 0x00000000 -#define mmROM_SW_DATA_10_DEFAULT 0x00000000 -#define mmROM_SW_DATA_11_DEFAULT 0x00000000 -#define mmROM_SW_DATA_12_DEFAULT 0x00000000 -#define mmROM_SW_DATA_13_DEFAULT 0x00000000 -#define mmROM_SW_DATA_14_DEFAULT 0x00000000 -#define mmROM_SW_DATA_15_DEFAULT 0x00000000 -#define mmROM_SW_DATA_16_DEFAULT 0x00000000 -#define mmROM_SW_DATA_17_DEFAULT 0x00000000 -#define mmROM_SW_DATA_18_DEFAULT 0x00000000 -#define mmROM_SW_DATA_19_DEFAULT 0x00000000 -#define mmROM_SW_DATA_20_DEFAULT 0x00000000 -#define mmROM_SW_DATA_21_DEFAULT 0x00000000 -#define mmROM_SW_DATA_22_DEFAULT 0x00000000 -#define mmROM_SW_DATA_23_DEFAULT 0x00000000 -#define mmROM_SW_DATA_24_DEFAULT 0x00000000 -#define mmROM_SW_DATA_25_DEFAULT 0x00000000 -#define mmROM_SW_DATA_26_DEFAULT 0x00000000 -#define mmROM_SW_DATA_27_DEFAULT 0x00000000 -#define mmROM_SW_DATA_28_DEFAULT 0x00000000 -#define mmROM_SW_DATA_29_DEFAULT 0x00000000 -#define mmROM_SW_DATA_30_DEFAULT 0x00000000 -#define mmROM_SW_DATA_31_DEFAULT 0x00000000 -#define mmROM_SW_DATA_32_DEFAULT 0x00000000 -#define mmROM_SW_DATA_33_DEFAULT 0x00000000 -#define mmROM_SW_DATA_34_DEFAULT 0x00000000 -#define mmROM_SW_DATA_35_DEFAULT 0x00000000 -#define mmROM_SW_DATA_36_DEFAULT 0x00000000 -#define mmROM_SW_DATA_37_DEFAULT 0x00000000 -#define mmROM_SW_DATA_38_DEFAULT 0x00000000 -#define mmROM_SW_DATA_39_DEFAULT 0x00000000 -#define mmROM_SW_DATA_40_DEFAULT 0x00000000 -#define mmROM_SW_DATA_41_DEFAULT 0x00000000 -#define mmROM_SW_DATA_42_DEFAULT 0x00000000 -#define mmROM_SW_DATA_43_DEFAULT 0x00000000 -#define mmROM_SW_DATA_44_DEFAULT 0x00000000 -#define mmROM_SW_DATA_45_DEFAULT 0x00000000 -#define mmROM_SW_DATA_46_DEFAULT 0x00000000 -#define mmROM_SW_DATA_47_DEFAULT 0x00000000 -#define mmROM_SW_DATA_48_DEFAULT 0x00000000 -#define mmROM_SW_DATA_49_DEFAULT 0x00000000 -#define mmROM_SW_DATA_50_DEFAULT 0x00000000 -#define mmROM_SW_DATA_51_DEFAULT 0x00000000 -#define mmROM_SW_DATA_52_DEFAULT 0x00000000 -#define mmROM_SW_DATA_53_DEFAULT 0x00000000 -#define mmROM_SW_DATA_54_DEFAULT 0x00000000 -#define mmROM_SW_DATA_55_DEFAULT 0x00000000 -#define mmROM_SW_DATA_56_DEFAULT 0x00000000 -#define mmROM_SW_DATA_57_DEFAULT 0x00000000 -#define mmROM_SW_DATA_58_DEFAULT 0x00000000 -#define mmROM_SW_DATA_59_DEFAULT 0x00000000 -#define mmROM_SW_DATA_60_DEFAULT 0x00000000 -#define mmROM_SW_DATA_61_DEFAULT 0x00000000 -#define mmROM_SW_DATA_62_DEFAULT 0x00000000 -#define mmROM_SW_DATA_63_DEFAULT 0x00000000 -#define mmROM_SW_DATA_64_DEFAULT 0x00000000 - -#endif -- GitLab From 8af7454e7c6b20cd8d130f08c443d1e76033d0ca Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Fri, 24 Nov 2017 10:46:24 +0800 Subject: [PATCH 0938/2547] drm/amd/include:cleanup vega10 osssys header files. Cleanup asic_reg/vega10/OSSSYS folder. Signed-off-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 +- .../OSSSYS => oss}/osssys_4_0_offset.h | 0 .../OSSSYS => oss}/osssys_4_0_sh_mask.h | 0 .../vega10/OSSSYS/osssys_4_0_default.h | 176 ------------------ 4 files changed, 2 insertions(+), 178 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/OSSSYS => oss}/osssys_4_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/OSSSYS => oss}/osssys_4_0_sh_mask.h (100%) delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 9d8bf3b1b52e..76626786c3fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -27,8 +27,8 @@ #include "vega10/soc15ip.h" -#include "vega10/OSSSYS/osssys_4_0_offset.h" -#include "vega10/OSSSYS/osssys_4_0_sh_mask.h" +#include "oss/osssys_4_0_offset.h" +#include "oss/osssys_4_0_sh_mask.h" #include "soc15_common.h" #include "vega10_ih.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h deleted file mode 100644 index 1fddd0f5aaa2..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _osssys_4_0_DEFAULT_HEADER -#define _osssys_4_0_DEFAULT_HEADER - - -// addressBlock: osssys_osssysdec -#define mmIH_VMID_0_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_1_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_2_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_3_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_4_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_5_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_6_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_7_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_8_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_9_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_10_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_11_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_12_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_13_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_14_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_15_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_0_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_1_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_2_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_3_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_4_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_5_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_6_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_7_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_8_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_9_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_10_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_11_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_12_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_13_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_14_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_15_LUT_MM_DEFAULT 0x00000000 -#define mmIH_COOKIE_0_DEFAULT 0x00000000 -#define mmIH_COOKIE_1_DEFAULT 0x00000000 -#define mmIH_COOKIE_2_DEFAULT 0x00000000 -#define mmIH_COOKIE_3_DEFAULT 0x00000000 -#define mmIH_COOKIE_4_DEFAULT 0x00000000 -#define mmIH_COOKIE_5_DEFAULT 0x00000000 -#define mmIH_COOKIE_6_DEFAULT 0x00000000 -#define mmIH_COOKIE_7_DEFAULT 0x00000000 -#define mmIH_REGISTER_LAST_PART0_DEFAULT 0x00000000 -#define mmSEM_REQ_INPUT_0_DEFAULT 0x00000000 -#define mmSEM_REQ_INPUT_1_DEFAULT 0x00000000 -#define mmSEM_REQ_INPUT_2_DEFAULT 0x00000000 -#define mmSEM_REQ_INPUT_3_DEFAULT 0x00000000 -#define mmSEM_REGISTER_LAST_PART0_DEFAULT 0x00000000 -#define mmIH_RB_CNTL_DEFAULT 0x10610000 -#define mmIH_RB_BASE_DEFAULT 0x00000000 -#define mmIH_RB_BASE_HI_DEFAULT 0x00000000 -#define mmIH_RB_RPTR_DEFAULT 0x00000000 -#define mmIH_RB_WPTR_DEFAULT 0x00000000 -#define mmIH_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmIH_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmIH_DOORBELL_RPTR_DEFAULT 0x00000000 -#define mmIH_RB_CNTL_RING1_DEFAULT 0x10410000 -#define mmIH_RB_BASE_RING1_DEFAULT 0x00000000 -#define mmIH_RB_BASE_HI_RING1_DEFAULT 0x00000000 -#define mmIH_RB_RPTR_RING1_DEFAULT 0x00000000 -#define mmIH_RB_WPTR_RING1_DEFAULT 0x00000000 -#define mmIH_DOORBELL_RPTR_RING1_DEFAULT 0x00000000 -#define mmIH_RB_CNTL_RING2_DEFAULT 0x10410000 -#define mmIH_RB_BASE_RING2_DEFAULT 0x00000000 -#define mmIH_RB_BASE_HI_RING2_DEFAULT 0x00000000 -#define mmIH_RB_RPTR_RING2_DEFAULT 0x00000000 -#define mmIH_RB_WPTR_RING2_DEFAULT 0x00000000 -#define mmIH_DOORBELL_RPTR_RING2_DEFAULT 0x00000000 -#define mmIH_VERSION_DEFAULT 0x00000400 -#define mmIH_CNTL_DEFAULT 0x01000000 -#define mmIH_CNTL2_DEFAULT 0x000000ff -#define mmIH_STATUS_DEFAULT 0x00040847 -#define mmIH_PERFMON_CNTL_DEFAULT 0x00000000 -#define mmIH_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 -#define mmIH_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 -#define mmIH_DSM_MATCH_VALUE_BIT_31_0_DEFAULT 0x00000000 -#define mmIH_DSM_MATCH_VALUE_BIT_63_32_DEFAULT 0x00000000 -#define mmIH_DSM_MATCH_VALUE_BIT_95_64_DEFAULT 0x00000000 -#define mmIH_DSM_MATCH_FIELD_CONTROL_DEFAULT 0x0000007f -#define mmIH_DSM_MATCH_DATA_CONTROL_DEFAULT 0x0fffffff -#define mmIH_DSM_MATCH_FCN_ID_DEFAULT 0x00000000 -#define mmIH_LIMIT_INT_RATE_CNTL_DEFAULT 0x00000000 -#define mmIH_VF_RB_STATUS_DEFAULT 0x00000000 -#define mmIH_VF_RB_STATUS2_DEFAULT 0x00000000 -#define mmIH_VF_RB1_STATUS_DEFAULT 0x00000000 -#define mmIH_VF_RB1_STATUS2_DEFAULT 0x00000000 -#define mmIH_VF_RB2_STATUS_DEFAULT 0x00000000 -#define mmIH_VF_RB2_STATUS2_DEFAULT 0x00000000 -#define mmIH_INT_FLOOD_CNTL_DEFAULT 0x00000000 -#define mmIH_RB0_INT_FLOOD_STATUS_DEFAULT 0x00000000 -#define mmIH_RB1_INT_FLOOD_STATUS_DEFAULT 0x00000000 -#define mmIH_RB2_INT_FLOOD_STATUS_DEFAULT 0x00000000 -#define mmIH_INT_FLOOD_STATUS_DEFAULT 0x00000000 -#define mmIH_STORM_CLIENT_LIST_CNTL_DEFAULT 0x00000000 -#define mmIH_CLK_CTRL_DEFAULT 0x00000000 -#define mmIH_INT_FLAGS_DEFAULT 0x00000000 -#define mmIH_LAST_INT_INFO0_DEFAULT 0x00000000 -#define mmIH_LAST_INT_INFO1_DEFAULT 0x00000000 -#define mmIH_LAST_INT_INFO2_DEFAULT 0x00000000 -#define mmIH_SCRATCH_DEFAULT 0x00000000 -#define mmIH_CLIENT_CREDIT_ERROR_DEFAULT 0x00000000 -#define mmIH_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 -#define mmIH_COOKIE_REC_VIOLATION_LOG_DEFAULT 0x00000000 -#define mmIH_CREDIT_STATUS_DEFAULT 0xfffffffe -#define mmIH_MMHUB_ERROR_DEFAULT 0x00000000 -#define mmIH_REGISTER_LAST_PART2_DEFAULT 0x00000000 -#define mmSEM_CLK_CTRL_DEFAULT 0x00000100 -#define mmSEM_UTC_CREDIT_DEFAULT 0x00000510 -#define mmSEM_UTC_CONFIG_DEFAULT 0x00000020 -#define mmSEM_UTCL2_TRAN_EN_LUT_DEFAULT 0x800000ff -#define mmSEM_MCIF_CONFIG_DEFAULT 0x00001040 -#define mmSEM_PERFMON_CNTL_DEFAULT 0x00000000 -#define mmSEM_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 -#define mmSEM_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 -#define mmSEM_STATUS_DEFAULT 0x80f90003 -#define mmSEM_MAILBOX_CLIENTCONFIG_DEFAULT 0x00fac688 -#define mmSEM_MAILBOX_DEFAULT 0x00000000 -#define mmSEM_MAILBOX_CONTROL_DEFAULT 0x00000000 -#define mmSEM_CHICKEN_BITS_DEFAULT 0x00084ad6 -#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_DEFAULT 0x00000008 -#define mmSEM_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 -#define mmSEM_OUTSTANDING_THRESHOLD_DEFAULT 0x00000010 -#define mmSEM_REGISTER_LAST_PART2_DEFAULT 0x00000000 -#define mmIH_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmIH_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmIH_CLIENT_CFG_DEFAULT 0x0000001f -#define mmIH_CLIENT_CFG_INDEX_DEFAULT 0x00000000 -#define mmIH_CLIENT_CFG_DATA_DEFAULT 0x00000000 -#define mmIH_CID_REMAP_INDEX_DEFAULT 0x00000000 -#define mmIH_CID_REMAP_DATA_DEFAULT 0x00000000 -#define mmIH_CHICKEN_DEFAULT 0x00000000 -#define mmIH_MMHUB_CNTL_DEFAULT 0x00000001 -#define mmIH_REGISTER_LAST_PART1_DEFAULT 0x00000000 -#define mmSEM_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmSEM_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmSEM_RESP_SDMA0_DEFAULT 0x0004950c -#define mmSEM_RESP_SDMA1_DEFAULT 0x0004958c -#define mmSEM_RESP_UVD_DEFAULT 0x0004860c -#define mmSEM_RESP_VCE_0_DEFAULT 0x0004900c -#define mmSEM_RESP_ACP_DEFAULT 0x0004870c -#define mmSEM_RESP_ISP_DEFAULT 0x00000000 -#define mmSEM_RESP_VCE_1_DEFAULT 0x0004908c -#define mmSEM_RESP_VP8_DEFAULT 0x00000000 -#define mmSEM_RESP_GC_DEFAULT 0x0004858c -#define mmSEM_CID_REMAP_INDEX_DEFAULT 0x00000000 -#define mmSEM_CID_REMAP_DATA_DEFAULT 0x00000000 -#define mmSEM_ATOMIC_OP_LUT_DEFAULT 0x040a102f -#define mmSEM_EDC_CONFIG_DEFAULT 0x00000002 -#define mmSEM_CHICKEN_BITS2_DEFAULT 0x00000000 -#define mmSEM_MMHUB_CNTL_DEFAULT 0x00000000 -#define mmSEM_REGISTER_LAST_PART1_DEFAULT 0x00000000 - -#endif -- GitLab From fb960bd28354805a7e2a6dbdf8d8d07a5160d0cd Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Fri, 24 Nov 2017 12:31:36 +0800 Subject: [PATCH 0939/2547] drm/amd/include:cleanup vega10 header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove asic_reg/vega10 folder. Signed-off-by: Feifei Xu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 2 +- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c | 2 +- drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 2 +- .../gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- .../gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c | 2 +- .../gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c | 2 +- drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c | 2 +- .../gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c | 2 +- drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c | 2 +- drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 2 +- .../gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c | 2 +- drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c | 2 +- drivers/gpu/drm/amd/include/{asic_reg/vega10 => }/soc15ip.h | 0 .../gpu/drm/amd/include/{asic_reg/vega10 => }/vega10_enum.h | 0 drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 2 +- 32 files changed, 36 insertions(+), 36 deletions(-) rename drivers/gpu/drm/amd/include/{asic_reg/vega10 => }/soc15ip.h (100%) rename drivers/gpu/drm/amd/include/{asic_reg/vega10 => }/vega10_enum.h (100%) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index df218df332b3..c22c73f458bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -35,7 +35,7 @@ #include "soc15d.h" #include "soc15_common.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "raven1/VCN/vcn_1_0_offset.h" /* 1 second timeout */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 35e134df7e07..6c5289ae67be 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -28,10 +28,10 @@ #include "soc15.h" #include "soc15d.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" -#include "vega10/vega10_enum.h" +#include "vega10_enum.h" #include "hdp/hdp_4_0_offset.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 9c93b20bf4ed..f1effadfbaa6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -23,11 +23,11 @@ #include "amdgpu.h" #include "gfxhub_v1_0.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" #include "gc/gc_9_0_default.h" -#include "vega10/vega10_enum.h" +#include "vega10_enum.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index a201efd41279..30eb625a991c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -25,13 +25,13 @@ #include "gmc_v9_0.h" #include "amdgpu_atomfirmware.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "hdp/hdp_4_0_offset.h" #include "hdp/hdp_4_0_sh_mask.h" #include "gc/gc_9_0_sh_mask.h" #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/vega10_enum.h" +#include "vega10_enum.h" #include "mmhub/mmhub_1_0_offset.h" #include "athub/athub_1_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index d2268575b098..bd160d8700e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -23,13 +23,13 @@ #include "amdgpu.h" #include "mmhub_v1_0.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "mmhub/mmhub_1_0_offset.h" #include "mmhub/mmhub_1_0_sh_mask.h" #include "mmhub/mmhub_1_0_default.h" #include "athub/athub_1_0_offset.h" #include "athub/athub_1_0_sh_mask.h" -#include "vega10/vega10_enum.h" +#include "vega10_enum.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index 19327b782124..ad9054e3903c 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -22,7 +22,7 @@ */ #include "amdgpu.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "nbio/nbio_6_1_offset.h" #include "nbio/nbio_6_1_sh_mask.h" #include "gc/gc_9_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index fd9f71e8a2d2..76db711097c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -24,11 +24,11 @@ #include "amdgpu_atombios.h" #include "nbio_v6_1.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "nbio/nbio_6_1_default.h" #include "nbio/nbio_6_1_offset.h" #include "nbio/nbio_6_1_sh_mask.h" -#include "vega10/vega10_enum.h" +#include "vega10_enum.h" #define smnCPM_CONTROL 0x11180460 #define smnPCIE_CNTL2 0x11180070 diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index f802b973410a..8ddc44b503e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -24,11 +24,11 @@ #include "amdgpu_atombios.h" #include "nbio_v7_0.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "raven1/NBIO/nbio_7_0_default.h" #include "raven1/NBIO/nbio_7_0_offset.h" #include "raven1/NBIO/nbio_7_0_sh_mask.h" -#include "vega10/vega10_enum.h" +#include "vega10_enum.h" #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 4e20d91d5d50..062cd8af6b19 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -30,7 +30,7 @@ #include "soc15_common.h" #include "psp_v10_0.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "raven1/MP/mp_10_0_offset.h" #include "raven1/GC/gc_9_1_offset.h" #include "raven1/SDMA0/sdma0_4_1_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 7a9832b8ff51..e75a23d858ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -31,7 +31,7 @@ #include "soc15_common.h" #include "psp_v3_1.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "mp/mp_9_0_offset.h" #include "mp/mp_9_0_sh_mask.h" #include "gc/gc_9_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 67b34914679f..a487fa7cb30a 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -27,7 +27,7 @@ #include "amdgpu_ucode.h" #include "amdgpu_trace.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "sdma0/sdma0_4_0_offset.h" #include "sdma0/sdma0_4_0_sh_mask.h" #include "sdma1/sdma1_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 85d7e6f1a3c5..f134ca0c093c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -34,7 +34,7 @@ #include "atom.h" #include "amd_pcie.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "uvd/uvd_7_0_offset.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index c271c6b4b451..660fa41dc877 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -29,7 +29,7 @@ #include "soc15_common.h" #include "mmsch_v1_0.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "uvd/uvd_7_0_offset.h" #include "uvd/uvd_7_0_sh_mask.h" #include "vce/vce_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index a6bb51b1322c..d06bafe28c2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -32,7 +32,7 @@ #include "soc15_common.h" #include "mmsch_v1_0.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "vce/vce_4_0_offset.h" #include "vce/vce_4_0_default.h" #include "vce/vce_4_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 061088cca72e..ab92cd71d4c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -28,7 +28,7 @@ #include "soc15d.h" #include "soc15_common.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "raven1/VCN/vcn_1_0_offset.h" #include "raven1/VCN/vcn_1_0_sh_mask.h" #include "hdp/hdp_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 76626786c3fc..ca778cd4e6e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -26,7 +26,7 @@ #include "soc15.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "oss/osssys_4_0_offset.h" #include "oss/osssys_4_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 533f730ff648..1c60b018ad1e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -61,7 +61,7 @@ #include "raven1/DCN/dcn_1_0_offset.h" #include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "soc15_common.h" #endif diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c index 8613ecf06514..75d029742f96 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c @@ -33,7 +33,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "reg_helper.h" #define CTX \ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 9d64e669ba52..57cd67359567 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -56,7 +56,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "nbio/nbio_6_1_offset.h" #include "reg_helper.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 5ad04d24fd27..0aa60e5727e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -27,7 +27,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "dc_types.h" #include "dc_bios_types.h" diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 9ea100223020..63d05f34db9f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -50,7 +50,7 @@ #include "dcn10_hubp.h" #include "dcn10_hubbub.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "raven1/DCN/dcn_1_0_offset.h" #include "raven1/DCN/dcn_1_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c index d8b70d151457..0c2314efb47e 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c @@ -36,7 +36,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #define block HPD #define reg_num 0 diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c index 0d0bc440835f..a225b02cc779 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c @@ -35,7 +35,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c index 409763c70ce5..f937b354fdd5 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c @@ -36,7 +36,7 @@ #include "raven1/DCN/dcn_1_0_offset.h" #include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #define block HPD #define reg_num 0 diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c index 64a6915b846b..75bfe6ae962b 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c @@ -35,7 +35,7 @@ #include "raven1/DCN/dcn_1_0_offset.h" #include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c index 0de53257b865..a401636bf3f8 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c @@ -38,7 +38,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c index 13b807d8aff8..b5237322ef41 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c @@ -38,7 +38,7 @@ #include "raven1/DCN/dcn_1_0_offset.h" #include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c index 8135d7a5f4d6..66d52580e29f 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c @@ -32,7 +32,7 @@ #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "ivsrcid/ivsrcid_vislands30.h" diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c index 74ad24714f6b..8e2dabe08bd0 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c @@ -31,7 +31,7 @@ #include "raven1/DCN/dcn_1_0_offset.h" #include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" #include "irq_service_dcn10.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h b/drivers/gpu/drm/amd/include/soc15ip.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h rename to drivers/gpu/drm/amd/include/soc15ip.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h b/drivers/gpu/drm/amd/include/vega10_enum.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h rename to drivers/gpu/drm/amd/include/vega10_enum.h diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h index a511611ec7e0..b7ab69e4c254 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h @@ -23,7 +23,7 @@ #ifndef PP_SOC15_H #define PP_SOC15_H -#include "vega10/soc15ip.h" +#include "soc15ip.h" inline static uint32_t soc15_get_register_offset( uint32_t hw_id, -- GitLab From 02cf8837d0ef87be7ef22a5817256489a6dd7f51 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Mon, 27 Nov 2017 18:40:15 +0800 Subject: [PATCH 0940/2547] drm/amd/include:cleanup raven1 sdma header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/raven1/SDMA0 folder.Remove unused sdma0_4_1_sh_mask.h. Signed-off-by: Feifei Xu Acked-by: Christian König Reviewed-by: Junwei Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- .../asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h | 1658 ----------------- .../SDMA0 => sdma0}/sdma0_4_1_default.h | 0 .../SDMA0 => sdma0}/sdma0_4_1_offset.h | 0 5 files changed, 2 insertions(+), 1660 deletions(-) delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h rename drivers/gpu/drm/amd/include/asic_reg/{raven1/SDMA0 => sdma0}/sdma0_4_1_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/SDMA0 => sdma0}/sdma0_4_1_offset.h (100%) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 062cd8af6b19..a7ec158f114f 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -33,7 +33,7 @@ #include "soc15ip.h" #include "raven1/MP/mp_10_0_offset.h" #include "raven1/GC/gc_9_1_offset.h" -#include "raven1/SDMA0/sdma0_4_1_offset.h" +#include "sdma0/sdma0_4_1_offset.h" MODULE_FIRMWARE("amdgpu/raven_asd.bin"); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index a487fa7cb30a..4c55f21e37a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -35,7 +35,7 @@ #include "mmhub/mmhub_1_0_offset.h" #include "mmhub/mmhub_1_0_sh_mask.h" #include "hdp/hdp_4_0_offset.h" -#include "raven1/SDMA0/sdma0_4_1_default.h" +#include "sdma0/sdma0_4_1_default.h" #include "soc15_common.h" #include "soc15.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h deleted file mode 100644 index 1445bba8f41f..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h +++ /dev/null @@ -1,1658 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma0_4_1_SH_MASK_HEADER -#define _sdma0_4_1_SH_MASK_HEADER - - -// addressBlock: sdma0_sdma0dec -//SDMA0_UCODE_ADDR -#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 -#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL -//SDMA0_UCODE_DATA -#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 -#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL -//SDMA0_VM_CNTL -#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 -#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL -//SDMA0_VM_CTX_LO -#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 -#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_VM_CTX_HI -#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 -#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_ACTIVE_FCN_ID -#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 -#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L -#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//SDMA0_VM_CTX_CNTL -#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 -#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 -#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L -#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L -//SDMA0_VIRT_RESET_REQ -#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 -#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f -#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL -#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L -//SDMA0_CONTEXT_REG_TYPE0 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L -//SDMA0_CONTEXT_REG_TYPE1 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 -#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L -#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L -//SDMA0_CONTEXT_REG_TYPE2 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 -#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L -//SDMA0_CONTEXT_REG_TYPE3 -#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 -#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL -//SDMA0_PUB_REG_TYPE0 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 -#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 -#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 -#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 -#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 -#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a -#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b -#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c -#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L -//SDMA0_PUB_REG_TYPE1 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 -#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 -#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 -#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 -#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 -#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa -#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd -#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 -#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 -#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L -#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L -//SDMA0_PUB_REG_TYPE2 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 -#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 -#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa -#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb -#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe -#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 -#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a -#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b -#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c -#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d -#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e -#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L -//SDMA0_PUB_REG_TYPE3 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL -//SDMA0_MMHUB_CNTL -#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 -#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL -//SDMA0_CONTEXT_GROUP_BOUNDARY -#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 -#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL -//SDMA0_POWER_CNTL -#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 -#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 -#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 -#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 -#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 -#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 -#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa -#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc -#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a -#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L -#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L -#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L -#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L -#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L -#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L -#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L -#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L -#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L -//SDMA0_CLK_CTRL -#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//SDMA0_CNTL -#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 -#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 -#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 -#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 -#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 -#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 -#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 -#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c -#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d -#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e -#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L -#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L -#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L -#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L -#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L -#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L -#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L -#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L -#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L -#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L -//SDMA0_CHICKEN_BITS -#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 -#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 -#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 -#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 -#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa -#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 -#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 -#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 -#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 -#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 -#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a -#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c -#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e -#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L -#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L -#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L -#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L -#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L -#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L -#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L -#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L -#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L -#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L -#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L -#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L -#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L -//SDMA0_GB_ADDR_CONFIG -#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 -#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc -#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 -#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L -#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L -#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L -//SDMA0_GB_ADDR_CONFIG_READ -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 -#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L -#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L -//SDMA0_RB_RPTR_FETCH_HI -#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL -#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 -#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL -//SDMA0_RB_RPTR_FETCH -#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 -#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL -//SDMA0_IB_OFFSET_FETCH -#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 -#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL -//SDMA0_PROGRAM -#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 -#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL -//SDMA0_STATUS_REG -#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 -#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 -#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 -#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 -#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 -#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 -#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 -#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 -#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 -#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 -#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa -#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb -#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc -#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd -#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe -#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf -#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 -#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 -#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 -#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 -#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 -#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 -#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 -#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 -#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a -#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b -#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c -#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e -#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f -#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L -#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L -#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L -#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L -#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L -#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L -#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L -#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L -#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L -#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L -#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L -#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L -#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L -#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L -#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L -#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L -#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L -#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L -#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L -#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L -#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L -#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L -#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L -#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L -#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L -#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L -#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L -#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L -#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L -//SDMA0_STATUS1_REG -#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 -#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 -#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 -#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 -#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 -#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 -#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 -#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 -#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa -#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd -#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe -#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf -#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 -#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 -#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L -#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L -#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L -#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L -#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L -#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L -#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L -#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L -#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L -#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L -#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L -#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L -#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L -#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L -//SDMA0_RD_BURST_CNTL -#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 -#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L -//SDMA0_HBM_PAGE_CONFIG -#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 -#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L -//SDMA0_UCODE_CHECKSUM -#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 -#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL -//SDMA0_F32_CNTL -#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 -#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 -#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L -#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L -//SDMA0_FREEZE -#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 -#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 -#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 -#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 -#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L -#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L -#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L -#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L -//SDMA0_PHASE0_QUANTUM -#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L -//SDMA0_PHASE1_QUANTUM -#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L -//SDMA_POWER_GATING -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 -#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 -#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 -#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L -#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L -#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L -#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L -//SDMA_PGFSM_CONFIG -#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 -#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 -#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 -#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa -#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb -#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc -#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd -#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b -#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c -#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL -#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L -#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L -#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L -#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L -#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L -#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L -#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L -#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L -//SDMA_PGFSM_WRITE -#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 -#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL -//SDMA_PGFSM_READ -#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 -#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL -//SDMA0_EDC_CONFIG -#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 -#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 -#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L -#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L -//SDMA0_BA_THRESHOLD -#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 -#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 -#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL -#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L -//SDMA0_ID -#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 -#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL -//SDMA0_VERSION -#define SDMA0_VERSION__MINVER__SHIFT 0x0 -#define SDMA0_VERSION__MAJVER__SHIFT 0x8 -#define SDMA0_VERSION__REV__SHIFT 0x10 -#define SDMA0_VERSION__MINVER_MASK 0x0000007FL -#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L -#define SDMA0_VERSION__REV_MASK 0x003F0000L -//SDMA0_EDC_COUNTER -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 -#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 -#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 -#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe -#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf -#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L -#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L -#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L -#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L -#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L -#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L -//SDMA0_EDC_COUNTER_CLEAR -#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 -#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L -//SDMA0_STATUS2_REG -#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 -#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 -#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 -#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L -#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL -#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L -//SDMA0_ATOMIC_CNTL -#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 -#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f -#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL -#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L -//SDMA0_ATOMIC_PREOP_LO -#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 -#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL -//SDMA0_ATOMIC_PREOP_HI -#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 -#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_CNTL -#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 -#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 -#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb -#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe -#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 -#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d -#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L -#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL -#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L -#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L -#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L -#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L -//SDMA0_UTCL1_WATERMK -#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 -#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa -#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 -#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a -#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL -#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L -#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L -#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L -//SDMA0_UTCL1_RD_STATUS -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 -#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 -#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 -#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 -#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 -#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 -#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a -#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d -#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e -#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L -#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L -#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L -#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L -#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L -#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L -//SDMA0_UTCL1_WR_STATUS -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 -#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 -#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 -#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 -#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 -#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 -#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L -#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L -#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L -//SDMA0_UTCL1_INV0 -#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 -#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 -#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 -#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 -#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 -#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 -#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 -#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 -#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 -#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 -#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa -#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb -#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc -#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c -#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L -#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L -#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L -#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L -#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L -#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L -#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L -#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L -#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L -#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L -#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L -#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L -#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L -#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L -//SDMA0_UTCL1_INV1 -#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 -#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_INV2 -#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 -#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_RD_XNACK0 -#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 -#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_RD_XNACK1 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 -#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a -#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L -#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L -//SDMA0_UTCL1_WR_XNACK0 -#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 -#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_WR_XNACK1 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 -#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a -#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L -#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L -//SDMA0_UTCL1_TIMEOUT -#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 -#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 -#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL -#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L -//SDMA0_UTCL1_PAGE -#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 -#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 -#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 -#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 -#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L -#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL -#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L -#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L -//SDMA0_POWER_CNTL_IDLE -#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 -#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 -#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 -#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL -#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L -#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L -//SDMA0_RELAX_ORDERING_LUT -#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 -#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 -#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 -#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 -#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 -#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 -#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa -#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb -#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc -#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd -#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe -#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b -#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c -#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d -#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e -#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f -#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L -#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L -#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L -#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L -#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L -#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L -#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L -#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L -#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L -#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L -#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L -#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L -#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L -#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L -#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L -//SDMA0_CHICKEN_BITS_2 -#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 -#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL -//SDMA0_STATUS3_REG -#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 -#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 -#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 -#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL -#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L -#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L -//SDMA0_PHYSICAL_ADDR_LO -#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 -#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 -#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 -#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc -#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L -#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L -#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L -#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L -//SDMA0_PHYSICAL_ADDR_HI -#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL -//SDMA0_ERROR_LOG -#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 -#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 -#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL -#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L -//SDMA0_PUB_DUMMY_REG0 -#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL -//SDMA0_PUB_DUMMY_REG1 -#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL -//SDMA0_PUB_DUMMY_REG2 -#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL -//SDMA0_PUB_DUMMY_REG3 -#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL -//SDMA0_F32_COUNTER -#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 -#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL -//SDMA0_UNBREAKABLE -#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 -#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L -//SDMA0_PERFMON_CNTL -#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 -#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 -#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 -#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa -#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb -#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc -#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L -#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L -#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL -#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L -#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L -#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L -//SDMA0_PERFCOUNTER0_RESULT -#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 -#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL -//SDMA0_PERFCOUNTER1_RESULT -#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 -#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL -//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L -//SDMA0_CRD_CNTL -#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 -#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd -#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L -#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L -//SDMA0_MMHUB_TRUSTLVL -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L -//SDMA0_GPU_IOV_VIOLATION_LOG -#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 -#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 -#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 -#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 -#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L -#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL -#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L -//SDMA0_ULV_CNTL -#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 -#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d -#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e -#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f -#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL -#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L -#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L -#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L -//SDMA0_EA_DBIT_ADDR_DATA -#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 -#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL -//SDMA0_EA_DBIT_ADDR_INDEX -#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 -#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L -//SDMA0_GFX_RB_CNTL -#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_GFX_RB_BASE -#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_BASE_HI -#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_GFX_RB_RPTR -#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_RPTR_HI -#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR -#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_HI -#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_POLL_CNTL -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_GFX_RB_RPTR_ADDR_HI -#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_RPTR_ADDR_LO -#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_GFX_IB_CNTL -#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_GFX_IB_RPTR -#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_GFX_IB_OFFSET -#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_GFX_IB_BASE_LO -#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_GFX_IB_BASE_HI -#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_IB_SIZE -#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_GFX_SKIP_CNTL -#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_GFX_CONTEXT_STATUS -#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_GFX_DOORBELL -#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_GFX_CONTEXT_CNTL -#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 -#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L -//SDMA0_GFX_STATUS -#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_GFX_DOORBELL_LOG -#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_GFX_WATERMARK -#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_GFX_DOORBELL_OFFSET -#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_GFX_CSA_ADDR_LO -#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_GFX_CSA_ADDR_HI -#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_IB_SUB_REMAIN -#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_GFX_PREEMPT -#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_GFX_DUMMY_REG -#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_GFX_RB_AQL_CNTL -#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_GFX_MINOR_PTR_UPDATE -#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_GFX_MIDCMD_DATA0 -#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA1 -#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA2 -#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA3 -#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA4 -#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA5 -#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA6 -#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA7 -#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA8 -#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_CNTL -#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA0_RLC0_RB_CNTL -#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_RLC0_RB_BASE -#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_BASE_HI -#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_RLC0_RB_RPTR -#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_RPTR_HI -#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR -#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_HI -#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_POLL_CNTL -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_RLC0_RB_RPTR_ADDR_HI -#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_RPTR_ADDR_LO -#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC0_IB_CNTL -#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_RLC0_IB_RPTR -#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC0_IB_OFFSET -#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC0_IB_BASE_LO -#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_RLC0_IB_BASE_HI -#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_IB_SIZE -#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_RLC0_SKIP_CNTL -#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_RLC0_CONTEXT_STATUS -#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_RLC0_DOORBELL -#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_RLC0_STATUS -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_RLC0_DOORBELL_LOG -#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_RLC0_WATERMARK -#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_RLC0_DOORBELL_OFFSET -#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_RLC0_CSA_ADDR_LO -#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC0_CSA_ADDR_HI -#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_IB_SUB_REMAIN -#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_RLC0_PREEMPT -#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_RLC0_DUMMY_REG -#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC0_RB_AQL_CNTL -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_RLC0_MINOR_PTR_UPDATE -#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_RLC0_MIDCMD_DATA0 -#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA1 -#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA2 -#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA3 -#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA4 -#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA5 -#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA6 -#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA7 -#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA8 -#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_CNTL -#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA0_RLC1_RB_CNTL -#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_RLC1_RB_BASE -#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_BASE_HI -#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_RLC1_RB_RPTR -#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_RPTR_HI -#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR -#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_HI -#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_POLL_CNTL -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_RLC1_RB_RPTR_ADDR_HI -#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_RPTR_ADDR_LO -#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC1_IB_CNTL -#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_RLC1_IB_RPTR -#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC1_IB_OFFSET -#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC1_IB_BASE_LO -#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_RLC1_IB_BASE_HI -#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_IB_SIZE -#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_RLC1_SKIP_CNTL -#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_RLC1_CONTEXT_STATUS -#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_RLC1_DOORBELL -#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_RLC1_STATUS -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_RLC1_DOORBELL_LOG -#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_RLC1_WATERMARK -#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_RLC1_DOORBELL_OFFSET -#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_RLC1_CSA_ADDR_LO -#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC1_CSA_ADDR_HI -#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_IB_SUB_REMAIN -#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_RLC1_PREEMPT -#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_RLC1_DUMMY_REG -#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC1_RB_AQL_CNTL -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_RLC1_MINOR_PTR_UPDATE -#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_RLC1_MIDCMD_DATA0 -#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA1 -#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA2 -#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA3 -#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA4 -#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA5 -#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA6 -#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA7 -#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA8 -#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_CNTL -#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_default.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default.h rename to drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h -- GitLab From ad941f7a8bf58b07c6fe5b4731541965cc3d652b Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Mon, 27 Nov 2017 18:59:10 +0800 Subject: [PATCH 0941/2547] drm/amd/include:cleanup raven1 dcn header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/raven1/DCN folder.Remove unused dcn_1_0_default.h. Signed-off-by: Feifei Xu Acked-by: Christian König Reviewed-by: Junwei Zhang Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +- .../display/dc/gpio/dcn10/hw_factory_dcn10.c | 4 +- .../dc/gpio/dcn10/hw_translate_dcn10.c | 4 +- .../display/dc/i2caux/dcn10/i2caux_dcn10.c | 4 +- .../display/dc/irq/dcn10/irq_service_dcn10.c | 4 +- .../{raven1/DCN => dcn}/dcn_1_0_offset.h | 0 .../{raven1/DCN => dcn}/dcn_1_0_sh_mask.h | 0 .../asic_reg/raven1/DCN/dcn_1_0_default.h | 7988 ----------------- 9 files changed, 12 insertions(+), 8000 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/DCN => dcn}/dcn_1_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/DCN => dcn}/dcn_1_0_sh_mask.h (100%) delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1c60b018ad1e..82226a337bde 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -59,8 +59,8 @@ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "ivsrcid/irqsrcs_dcn_1_0.h" -#include "raven1/DCN/dcn_1_0_offset.h" -#include "raven1/DCN/dcn_1_0_sh_mask.h" +#include "dcn/dcn_1_0_offset.h" +#include "dcn/dcn_1_0_sh_mask.h" #include "soc15ip.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 63d05f34db9f..278899d72dc5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -52,8 +52,8 @@ #include "soc15ip.h" -#include "raven1/DCN/dcn_1_0_offset.h" -#include "raven1/DCN/dcn_1_0_sh_mask.h" +#include "dcn/dcn_1_0_offset.h" +#include "dcn/dcn_1_0_sh_mask.h" #include "raven1/NBIO/nbio_7_0_offset.h" diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c index f937b354fdd5..5235f69f0602 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c @@ -34,8 +34,8 @@ #include "hw_factory_dcn10.h" -#include "raven1/DCN/dcn_1_0_offset.h" -#include "raven1/DCN/dcn_1_0_sh_mask.h" +#include "dcn/dcn_1_0_offset.h" +#include "dcn/dcn_1_0_sh_mask.h" #include "soc15ip.h" #define block HPD diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c index 75bfe6ae962b..347864810d01 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c @@ -33,8 +33,8 @@ #include "include/gpio_types.h" #include "../hw_translate.h" -#include "raven1/DCN/dcn_1_0_offset.h" -#include "raven1/DCN/dcn_1_0_sh_mask.h" +#include "dcn/dcn_1_0_offset.h" +#include "dcn/dcn_1_0_sh_mask.h" #include "soc15ip.h" /* begin ********************* diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c index b5237322ef41..bed7cc3e77de 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c @@ -36,8 +36,8 @@ #include "../dce110/i2c_hw_engine_dce110.h" #include "../dce110/i2caux_dce110.h" -#include "raven1/DCN/dcn_1_0_offset.h" -#include "raven1/DCN/dcn_1_0_sh_mask.h" +#include "dcn/dcn_1_0_offset.h" +#include "dcn/dcn_1_0_sh_mask.h" #include "soc15ip.h" /* begin ********************* diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c index 8e2dabe08bd0..7f7db66c48b0 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c @@ -29,8 +29,8 @@ #include "../dce110/irq_service_dce110.h" -#include "raven1/DCN/dcn_1_0_offset.h" -#include "raven1/DCN/dcn_1_0_sh_mask.h" +#include "dcn/dcn_1_0_offset.h" +#include "dcn/dcn_1_0_sh_mask.h" #include "soc15ip.h" #include "irq_service_dcn10.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h deleted file mode 100644 index eac125c9e300..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h +++ /dev/null @@ -1,7988 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _dcn_1_0_DEFAULT_HEADER -#define _dcn_1_0_DEFAULT_HEADER - - -// addressBlock: dce_dc_hda_azcontroller_azdec -#define smnAZCONTROLLER0_GLOBAL_CAPABILITIES_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_MINOR_VERSION_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_MAJOR_VERSION_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_WAKE_ENABLE_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_STATE_CHANGE_STATUS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_GLOBAL_STATUS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_WALL_CLOCK_COUNTER_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_STREAM_SYNCHRONIZATION_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_WRITE_POINTER_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_READ_POINTER_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_CONTROL_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_STATUS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_SIZE_DEFAULT 0x00000002 -#define smnAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_RIRB_WRITE_POINTER_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_RIRB_CONTROL_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_RIRB_STATUS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_RIRB_SIZE_DEFAULT 0x00000002 -#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azendpoint_azdec -#define smnAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define smnAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azinputendpoint_azdec -#define smnAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define smnAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azroot_azdec -#define smnAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define smnAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream0_azdec -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream1_azdec -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream2_azdec -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream3_azdec -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream4_azdec -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream5_azdec -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream6_azdec -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream7_azdec -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] -#define mmVGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000 -#define mmVGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] -#define mmCRTC8_IDX_DEFAULT 0x00000000 -#define mmCRTC8_DATA_DEFAULT 0x00000000 -#define mmGENFC_WT_DEFAULT 0x00000000 -#define mmGENS1_DEFAULT 0x00000000 -#define mmATTRDW_DEFAULT 0x00000000 -#define mmATTRX_DEFAULT 0x00000000 -#define mmATTRDR_DEFAULT 0x00000000 -#define mmGENMO_WT_DEFAULT 0x00000000 -#define mmGENS0_DEFAULT 0x00000000 -#define mmGENENB_DEFAULT 0x00000000 -#define mmSEQ8_IDX_DEFAULT 0x00000000 -#define mmSEQ8_DATA_DEFAULT 0x00000000 -#define mmDAC_MASK_DEFAULT 0x00000000 -#define mmDAC_R_INDEX_DEFAULT 0x00000000 -#define mmDAC_W_INDEX_DEFAULT 0x00000000 -#define mmDAC_DATA_DEFAULT 0x00000000 -#define mmGENFC_RD_DEFAULT 0x00000000 -#define mmGENMO_RD_DEFAULT 0x00000000 -#define mmGRPH8_IDX_DEFAULT 0x00000000 -#define mmGRPH8_DATA_DEFAULT 0x00000000 -#define mmCRTC8_IDX_1_DEFAULT 0x00000000 -#define mmCRTC8_DATA_1_DEFAULT 0x00000000 -#define mmGENFC_WT_1_DEFAULT 0x00000000 -#define mmGENS1_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azcontroller_azdec -#define mmCORB_WRITE_POINTER_DEFAULT 0x00000000 -#define mmCORB_READ_POINTER_DEFAULT 0x00000000 -#define mmCORB_CONTROL_DEFAULT 0x00000000 -#define mmCORB_STATUS_DEFAULT 0x00000000 -#define mmCORB_SIZE_DEFAULT 0x00000002 -#define mmRIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmRIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmRIRB_WRITE_POINTER_DEFAULT 0x00000000 -#define mmRESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000 -#define mmRIRB_CONTROL_DEFAULT 0x00000000 -#define mmRIRB_STATUS_DEFAULT 0x00000000 -#define mmRIRB_SIZE_DEFAULT 0x00000002 -#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 -#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000 -#define mmDMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmDMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmWALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azendpoint_azdec -#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azinputendpoint_azdec -#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azroot_azdec -#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream0_azdec -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream1_azdec -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream2_azdec -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream3_azdec -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream4_azdec -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream5_azdec -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream6_azdec -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream7_azdec -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] - - -// addressBlock: dce_dc_mmhubbub_vga_dispdec -#define mmVGA_RENDER_CONTROL_DEFAULT 0x0000000f -#define mmVGA_SEQUENCER_RESET_CONTROL_DEFAULT 0x00003f3f -#define mmVGA_MODE_CONTROL_DEFAULT 0x00000000 -#define mmVGA_SURFACE_PITCH_SELECT_DEFAULT 0x00000002 -#define mmVGA_MEMORY_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmVGA_DISPBUF1_SURFACE_ADDR_DEFAULT 0x00000000 -#define mmVGA_DISPBUF2_SURFACE_ADDR_DEFAULT 0x00000000 -#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmVGA_HDP_CONTROL_DEFAULT 0x00000000 -#define mmVGA_CACHE_CONTROL_DEFAULT 0x00000000 -#define mmD1VGA_CONTROL_DEFAULT 0x00000000 -#define mmD2VGA_CONTROL_DEFAULT 0x00000000 -#define mmVGA_STATUS_DEFAULT 0x00000000 -#define mmVGA_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmVGA_STATUS_CLEAR_DEFAULT 0x00000000 -#define mmVGA_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmVGA_MAIN_CONTROL_DEFAULT 0x00005018 -#define mmVGA_TEST_CONTROL_DEFAULT 0x00000000 -#define mmVGA_QOS_CTRL_DEFAULT 0x00000000 -#define mmD3VGA_CONTROL_DEFAULT 0x00000000 -#define mmD4VGA_CONTROL_DEFAULT 0x00000000 -#define mmD5VGA_CONTROL_DEFAULT 0x00000000 -#define mmD6VGA_CONTROL_DEFAULT 0x00000000 -#define mmVGA_SOURCE_SELECT_DEFAULT 0x00000100 - - -// addressBlock: dce_dc_dccg_dccg_dispdec -#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO_DBUF_EN_DEFAULT 0x00000000 -#define mmDPREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmREFCLK_CNTL_DEFAULT 0x00000000 -#define mmMIPI_CLK_CNTL_DEFAULT 0x00000000 -#define mmREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDSICLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmDCCG_CBUS_WRCMD_DELAY_DEFAULT 0x00000003 -#define mmDCCG_DS_DTO_INCR_DEFAULT 0x00000000 -#define mmDCCG_DS_DTO_MODULO_DEFAULT 0x00000000 -#define mmDCCG_DS_CNTL_DEFAULT 0x00000000 -#define mmDCCG_DS_HW_CAL_INTERVAL_DEFAULT 0x00989680 -#define mmSYMCLKG_CLOCK_ENABLE_DEFAULT 0x00000600 -#define mmDPREFCLK_CNTL_DEFAULT 0x00000000 -#define mmAOMCLK0_CNTL_DEFAULT 0x00000000 -#define mmAOMCLK1_CNTL_DEFAULT 0x00000000 -#define mmAOMCLK2_CNTL_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO2_PHASE_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO2_MODULO_DEFAULT 0x00000001 -#define mmDCE_VERSION_DEFAULT 0x00000000 -#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_GTC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_GTC_DTO_INCR_DEFAULT 0x00000000 -#define mmDCCG_GTC_DTO_MODULO_DEFAULT 0x00000000 -#define mmDCCG_GTC_CURRENT_DEFAULT 0x00000000 -#define mmMIPI_DTO_CNTL_DEFAULT 0x00000000 -#define mmMIPI_DTO_PHASE_DEFAULT 0x00000000 -#define mmMIPI_DTO_MODULO_DEFAULT 0x00000000 -#define mmDAC_CLK_ENABLE_DEFAULT 0x00000000 -#define mmDVO_CLK_ENABLE_DEFAULT 0x00000000 -#define mmAVSYNC_COUNTER_WRITE_DEFAULT 0x00000000 -#define mmAVSYNC_COUNTER_CONTROL_DEFAULT 0x00000000 -#define mmAVSYNC_COUNTER_READ_DEFAULT 0x00000000 -#define mmMILLISECOND_TIME_BASE_DIV_DEFAULT 0x001186a0 -#define mmDISPCLK_FREQ_CHANGE_CNTL_DEFAULT 0x08010028 -#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x00000001 -#define mmDCCG_PERFMON_CNTL_DEFAULT 0xfffff800 -#define mmDCCG_GATE_DISABLE_CNTL_DEFAULT 0x74ee02dd -#define mmDISPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmSOCCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmDCCG_CAC_STATUS_DEFAULT 0x00000000 -#define mmPIXCLK1_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPIXCLK2_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPIXCLK0_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmMICROSECOND_TIME_BASE_DIV_DEFAULT 0x00120464 -#define mmDCCG_GATE_DISABLE_CNTL2_DEFAULT 0x007f007f -#define mmSYMCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_DISP_CNTL_REG_DEFAULT 0x00000000 -#define mmOTG0_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO0_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO0_MODULO_DEFAULT 0x00000000 -#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmOTG1_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO1_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO1_MODULO_DEFAULT 0x00000000 -#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmOTG2_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO2_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO2_MODULO_DEFAULT 0x00000000 -#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmOTG3_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO3_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO3_MODULO_DEFAULT 0x00000000 -#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmOTG4_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO4_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO4_MODULO_DEFAULT 0x00000000 -#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmOTG5_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO5_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO5_MODULO_DEFAULT 0x00000000 -#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDPPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmSYMCLKA_CLOCK_ENABLE_DEFAULT 0x00000000 -#define mmSYMCLKB_CLOCK_ENABLE_DEFAULT 0x00000100 -#define mmSYMCLKC_CLOCK_ENABLE_DEFAULT 0x00000200 -#define mmSYMCLKD_CLOCK_ENABLE_DEFAULT 0x00000300 -#define mmSYMCLKE_CLOCK_ENABLE_DEFAULT 0x00000400 -#define mmSYMCLKF_CLOCK_ENABLE_DEFAULT 0x00000500 -#define mmDCCG_SOFT_RESET_DEFAULT 0x00000000 -#define mmDVOACLKD_CNTL_DEFAULT 0x00070000 -#define mmDVOACLKC_MVP_CNTL_DEFAULT 0x00030000 -#define mmDVOACLKC_CNTL_DEFAULT 0x00030000 -#define mmDCCG_AUDIO_DTO_SOURCE_DEFAULT 0x00000030 -#define mmDCCG_AUDIO_DTO0_PHASE_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO0_MODULE_DEFAULT 0x00000001 -#define mmDCCG_AUDIO_DTO1_PHASE_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO1_MODULE_DEFAULT 0x00000001 -#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_CNT_CTRL_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_CNT_INT_CTRL_DEFAULT 0x00000000 -#define mmDCCG_TEST_CLK_SEL_DEFAULT 0x01ff01ff - - -// addressBlock: dce_dc_dccg_dccg_dfs_dispdec -#define mmDENTIST_DISPCLK_CNTL_DEFAULT 0x64010064 - - -// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec -#define mmDC_PERFMON0_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON0_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec -#define mmDC_PERFMON1_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON1_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dccg_dccg_pll_dispdec -#define mmPLL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmu_rbbmif_dispdec -#define mmRBBMIF_TIMEOUT_DEFAULT 0x20000a00 -#define mmRBBMIF_STATUS_DEFAULT 0x00000000 -#define mmRBBMIF_INT_STATUS_DEFAULT 0x80000000 -#define mmRBBMIF_TIMEOUT_DIS_DEFAULT 0x00000000 -#define mmRBBMIF_STATUS_FLAG_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmu_dc_pg_dispdec -#define mmDOMAIN0_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN0_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN1_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN1_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN2_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN2_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN3_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN3_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN4_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN4_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN5_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN5_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN6_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN6_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN7_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN7_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN8_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN8_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN9_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN9_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN10_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN10_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN11_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN11_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN12_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN12_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN13_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN13_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN14_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN14_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN15_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN15_PG_STATUS_DEFAULT 0x00000000 -#define mmDCPG_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCPG_INTERRUPT_CONTROL_1_DEFAULT 0x00000000 -#define mmDCPG_INTERRUPT_CONTROL_2_DEFAULT 0x00000000 -#define mmDC_IP_REQUEST_CNTL_DEFAULT 0x00000000 -#define mmDC_PGCNTL_STATUS_REG_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON2_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON2_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmu_dmu_misc_dispdec -#define mmCC_DC_PIPE_DIS_DEFAULT 0x00000000 -#define mmDMU_CLK_CNTL_DEFAULT 0x00000000 -#define mmDMU_MEM_PWR_CNTL_DEFAULT 0x00000000 -#define mmDMCU_SMU_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmSMU_INTERRUPT_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmu_dmcu_dispdec -#define mmDMCU_CTRL_DEFAULT 0xffff0101 -#define mmDMCU_STATUS_DEFAULT 0x00000001 -#define mmDMCU_PC_START_ADDR_DEFAULT 0x00000000 -#define mmDMCU_FW_START_ADDR_DEFAULT 0x00000000 -#define mmDMCU_FW_END_ADDR_DEFAULT 0x00000000 -#define mmDMCU_FW_ISR_START_ADDR_DEFAULT 0x00000004 -#define mmDMCU_FW_CS_HI_DEFAULT 0x00000000 -#define mmDMCU_FW_CS_LO_DEFAULT 0x00000000 -#define mmDMCU_RAM_ACCESS_CTRL_DEFAULT 0x00000000 -#define mmDMCU_ERAM_WR_CTRL_DEFAULT 0x000f0000 -#define mmDMCU_ERAM_WR_DATA_DEFAULT 0x00000000 -#define mmDMCU_ERAM_RD_CTRL_DEFAULT 0x000f0000 -#define mmDMCU_ERAM_RD_DATA_DEFAULT 0x00000000 -#define mmDMCU_IRAM_WR_CTRL_DEFAULT 0x00000000 -#define mmDMCU_IRAM_WR_DATA_DEFAULT 0x00000000 -#define mmDMCU_IRAM_RD_CTRL_DEFAULT 0x00000000 -#define mmDMCU_IRAM_RD_DATA_DEFAULT 0x00000000 -#define mmDMCU_EVENT_TRIGGER_DEFAULT 0x00000000 -#define mmDMCU_UC_INTERNAL_INT_STATUS_DEFAULT 0x00000000 -#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_STATUS_1_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_DEFAULT 0x00000000 -#define mmDC_DMCU_SCRATCH_DEFAULT 0x00000000 -#define mmDMCU_INT_CNT_DEFAULT 0x00000000 -#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_DEFAULT 0x00000000 -#define mmDMCU_UC_CLK_GATING_CNTL_DEFAULT 0x00010102 -#define mmMASTER_COMM_DATA_REG1_DEFAULT 0x00000000 -#define mmMASTER_COMM_DATA_REG2_DEFAULT 0x00000000 -#define mmMASTER_COMM_DATA_REG3_DEFAULT 0x00000000 -#define mmMASTER_COMM_CMD_REG_DEFAULT 0x00000000 -#define mmMASTER_COMM_CNTL_REG_DEFAULT 0x00000000 -#define mmSLAVE_COMM_DATA_REG1_DEFAULT 0x00000000 -#define mmSLAVE_COMM_DATA_REG2_DEFAULT 0x00000000 -#define mmSLAVE_COMM_DATA_REG3_DEFAULT 0x00000000 -#define mmSLAVE_COMM_CMD_REG_DEFAULT 0x00000000 -#define mmSLAVE_COMM_CNTL_REG_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS1_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS2_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS3_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS4_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS5_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_DEFAULT 0x00000000 -#define mmDMCU_DPRX_INTERRUPT_STATUS1_DEFAULT 0x00000000 -#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000 -#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_DEFAULT 0x00000000 -#define mmDMCU_INT_CNT_CONTINUE_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmu_ihc_dispdec -#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_READ_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_READ_CNTL_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE2_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE3_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE4_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE5_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE6_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE7_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE8_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE9_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE10_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE11_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE12_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE13_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE14_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE15_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE16_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE17_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE18_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE19_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE20_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE21_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE22_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_VREADY_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_FLIP_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec -#define mmCNV0_WB_ENABLE_DEFAULT 0x00000000 -#define mmCNV0_WB_EC_CONFIG_DEFAULT 0x55000000 -#define mmCNV0_CNV_MODE_DEFAULT 0x00000000 -#define mmCNV0_CNV_WINDOW_START_DEFAULT 0x00000000 -#define mmCNV0_CNV_WINDOW_SIZE_DEFAULT 0x00100010 -#define mmCNV0_CNV_UPDATE_DEFAULT 0x00000000 -#define mmCNV0_CNV_SOURCE_SIZE_DEFAULT 0x00100010 -#define mmCNV0_CNV_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_C11_C12_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_C13_C14_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_C21_C22_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_C23_C24_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_C31_C32_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_C33_C34_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_CLAMP_R_DEFAULT 0x00000fff -#define mmCNV0_CNV_CSC_CLAMP_G_DEFAULT 0x00000fff -#define mmCNV0_CNV_CSC_CLAMP_B_DEFAULT 0x00000fff -#define mmCNV0_CNV_TEST_CNTL_DEFAULT 0x00000000 -#define mmCNV0_CNV_TEST_CRC_RED_DEFAULT 0x0000fff0 -#define mmCNV0_CNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0 -#define mmCNV0_CNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0 -#define mmCNV0_CNV_INPUT_SELECT_DEFAULT 0x00000001 -#define mmCNV0_WB_SOFT_RESET_DEFAULT 0x00000000 -#define mmCNV0_WB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100 -#define mmCNV0_WB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100 - - -// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec -#define mmWBSCL0_WBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_MODE_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_TAP_CONTROL_DEFAULT 0x00001111 -#define mmWBSCL0_WBSCL_DEST_SIZE_DEFAULT 0x00010001 -#define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000 -#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 -#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000 -#define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000 -#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 -#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000 -#define mmWBSCL0_WBSCL_ROUND_OFFSET_DEFAULT 0x00800010 -#define mmWBSCL0_WBSCL_CLAMP_DEFAULT 0x01fe01fe -#define mmWBSCL0_WBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000 -#define mmWBSCL0_WBSCL_TEST_CNTL_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00 -#define mmWBSCL0_WBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff -#define mmWBSCL0_WBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00 -#define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000 -#define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON3_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON3_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_wb1_dispdec_cnv_dispdec -#define mmCNV1_WB_ENABLE_DEFAULT 0x00000000 -#define mmCNV1_WB_EC_CONFIG_DEFAULT 0x55000000 -#define mmCNV1_CNV_MODE_DEFAULT 0x00000000 -#define mmCNV1_CNV_WINDOW_START_DEFAULT 0x00000000 -#define mmCNV1_CNV_WINDOW_SIZE_DEFAULT 0x00100010 -#define mmCNV1_CNV_UPDATE_DEFAULT 0x00000000 -#define mmCNV1_CNV_SOURCE_SIZE_DEFAULT 0x00100010 -#define mmCNV1_CNV_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_C11_C12_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_C13_C14_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_C21_C22_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_C23_C24_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_C31_C32_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_C33_C34_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_CLAMP_R_DEFAULT 0x00000fff -#define mmCNV1_CNV_CSC_CLAMP_G_DEFAULT 0x00000fff -#define mmCNV1_CNV_CSC_CLAMP_B_DEFAULT 0x00000fff -#define mmCNV1_CNV_TEST_CNTL_DEFAULT 0x00000000 -#define mmCNV1_CNV_TEST_CRC_RED_DEFAULT 0x0000fff0 -#define mmCNV1_CNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0 -#define mmCNV1_CNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0 -#define mmCNV1_CNV_INPUT_SELECT_DEFAULT 0x00000001 -#define mmCNV1_WB_SOFT_RESET_DEFAULT 0x00000000 -#define mmCNV1_WB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100 -#define mmCNV1_WB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100 - - -// addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec -#define mmWBSCL1_WBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_MODE_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_TAP_CONTROL_DEFAULT 0x00001111 -#define mmWBSCL1_WBSCL_DEST_SIZE_DEFAULT 0x00010001 -#define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000 -#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 -#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000 -#define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000 -#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 -#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000 -#define mmWBSCL1_WBSCL_ROUND_OFFSET_DEFAULT 0x00800010 -#define mmWBSCL1_WBSCL_CLAMP_DEFAULT 0x01fe01fe -#define mmWBSCL1_WBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000 -#define mmWBSCL1_WBSCL_TEST_CNTL_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00 -#define mmWBSCL1_WBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff -#define mmWBSCL1_WBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00 -#define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000 -#define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON4_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON4_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec -#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 -#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 -#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 -#define mmMCIF_WB0_MCIF_WB_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 -#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 -#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 -#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff -#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff - - -// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec -#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 -#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 -#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 -#define mmMCIF_WB1_MCIF_WB_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 -#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 -#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 -#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff -#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff - - -// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec -#define mmWBIF0_MISC_CTRL_DEFAULT 0x00010001 -#define mmWBIF0_SMU_WM_CONTROL_DEFAULT 0x00000000 -#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmWBIF1_MISC_CTRL_DEFAULT 0x00010001 -#define mmWBIF1_SMU_WM_CONTROL_DEFAULT 0x00000000 -#define mmWBIF1_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmWBIF1_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmVGA_SRC_SPLIT_CNTL_DEFAULT 0x00000000 -#define mmMMHUBBUB_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmMMHUBBUB_MEM_PWR_CNTL_DEFAULT 0x0000c180 -#define mmMMHUBBUB_CLOCK_CNTL_DEFAULT 0x00000000 -#define mmMMHUBBUB_SOFT_RESET_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mmhubbub_vgaif_dispdec -#define mmMCIF_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WRITE_COMBINE_CONTROL_DEFAULT 0x00000080 -#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON5_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON5_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream0_dispdec -#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM0_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream1_dispdec -#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM1_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream2_dispdec -#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM2_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream3_dispdec -#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM3_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream4_dispdec -#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM4_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream5_dispdec -#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM5_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream6_dispdec -#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM6_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream7_dispdec -#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM7_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_az_misc_dispdec -#define mmAZ_CLOCK_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON6_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON6_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint0_dispdec -#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint1_dispdec -#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint2_dispdec -#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint3_dispdec -#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint4_dispdec -#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint5_dispdec -#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint6_dispdec -#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint7_dispdec -#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0controller_dispdec -#define mmAZALIA_CONTROLLER_CLOCK_GATING_DEFAULT 0x00000000 -#define mmAZALIA_AUDIO_DTO_DEFAULT 0x00300018 -#define mmAZALIA_AUDIO_DTO_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_SOCCLK_CONTROL_DEFAULT 0x00000001 -#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_DEFAULT 0x00000000 -#define mmAZALIA_DATA_DMA_CONTROL_DEFAULT 0x0000000a -#define mmAZALIA_BDL_DMA_CONTROL_DEFAULT 0x0000000a -#define mmAZALIA_RIRB_AND_DP_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_CORB_DMA_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_DEFAULT 0x00000000 -#define mmAZALIA_CYCLIC_BUFFER_SYNC_DEFAULT 0x00000000 -#define mmAZALIA_GLOBAL_CAPABILITIES_DEFAULT 0x00000000 -#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000060 -#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_DEFAULT 0x00080008 -#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000080 -#define mmAZALIA_INPUT_CRC0_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmAZALIA_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0root_dispdec -#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x1002aa01 -#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00100700 -#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_DEFAULT 0x0000000d -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000001 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0xc0000009 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000200 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00aa0100 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000 -#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET0_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET1_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET2_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET3_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET4_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET5_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET6_DEFAULT 0x00000000 -#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream8_dispdec -#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM8_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream9_dispdec -#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM9_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream10_dispdec -#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM10_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream11_dispdec -#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM11_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream12_dispdec -#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM12_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream13_dispdec -#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM13_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream14_dispdec -#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM14_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream15_dispdec -#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM15_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec -#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec -#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec -#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec -#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec -#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec -#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec -#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec -#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec -#define mmDCHUBBUB_SDPIF_CFG0_DEFAULT 0x00cd3001 -#define mmDCHUBBUB_SDPIF_CFG1_DEFAULT 0x0000005c -#define mmDCHUBBUB_FORCE_IO_STATUS_0_DEFAULT 0x00000002 -#define mmDCHUBBUB_FORCE_IO_STATUS_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_FB_BASE_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_FB_TOP_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_FB_OFFSET_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_AGP_BOT_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_AGP_TOP_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_AGP_BASE_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_APER_BASE_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_APER_TOP_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_APER_DEF_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_APER_DEF_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec -#define mmDCHUBBUB_RET_PATH_DCC_CFG_DEFAULT 0x00000001 -#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCHUBBUB_CRC_CTRL_DEFAULT 0x00000000 -#define mmDCHUBBUB_CRC0_VAL_R_G_DEFAULT 0x00000000 -#define mmDCHUBBUB_CRC0_VAL_B_A_DEFAULT 0x00000000 -#define mmDCHUBBUB_CRC1_VAL_R_G_DEFAULT 0x00000000 -#define mmDCHUBBUB_CRC1_VAL_B_A_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dchubbub_hubbub_dispdec -#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_DEFAULT 0x01000100 -#define mmDCHUBBUB_ARB_SAT_LEVEL_DEFAULT 0xffffffff -#define mmDCHUBBUB_ARB_QOS_FORCE_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_DEFAULT 0x00000010 -#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_DEFAULT 0x00000000 -#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_DEFAULT 0x00000000 -#define mmSURFACE_CHECK0_ADDRESS_LSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK0_ADDRESS_MSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK1_ADDRESS_LSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK1_ADDRESS_MSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK2_ADDRESS_LSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK2_ADDRESS_MSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK3_ADDRESS_LSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK3_ADDRESS_MSB_DEFAULT 0x00000000 -#define mmVTG0_CONTROL_DEFAULT 0x00000000 -#define mmVTG1_CONTROL_DEFAULT 0x00000000 -#define mmVTG2_CONTROL_DEFAULT 0x00000000 -#define mmVTG3_CONTROL_DEFAULT 0x00000000 -#define mmVTG4_CONTROL_DEFAULT 0x00000000 -#define mmVTG5_CONTROL_DEFAULT 0x00000000 -#define mmDCHUBBUB_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCHUBBUB_CLOCK_CNTL_DEFAULT 0x00000000 -#define mmDCFCLK_CNTL_DEFAULT 0x80000200 -#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_DEFAULT 0x00000000 -#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_DEFAULT 0x00000000 -#define mmDCHUBBUB_VLINE_SNAPSHOT_DEFAULT 0x00000000 -#define mmDCHUBBUB_SPARE_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON7_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON7_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec -#define mmHUBP0_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008 -#define mmHUBP0_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_TILING_CONFIG_DEFAULT 0x00000080 -#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000 -#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000 -#define mmHUBP0_DCHUBP_CNTL_DEFAULT 0x00001001 -#define mmHUBP0_HUBP_CLK_CNTL_DEFAULT 0x00000000 -#define mmHUBP0_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000 -#define mmHUBP0_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000 -#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000 -#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec -#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040 -#define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000 -#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_EXPANSION_MODE_DEFAULT 0x00000055 -#define mmHUBPREQ0_DCN_TTU_QOS_WM_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010 -#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ0_BLANK_OFFSET_0_DEFAULT 0x00000000 -#define mmHUBPREQ0_BLANK_OFFSET_1_DEFAULT 0x00000000 -#define mmHUBPREQ0_DST_DIMENSIONS_DEFAULT 0x00000000 -#define mmHUBPREQ0_DST_AFTER_SCALER_DEFAULT 0x00000000 -#define mmHUBPREQ0_PREFETCH_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ0_PREFETCH_SETTINS_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_VBLANK_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ0_VBLANK_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ0_VBLANK_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ0_VBLANK_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ0_VBLANK_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_5_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_6_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_7_DEFAULT 0x00000000 -#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000 -#define mmHUBPREQ0_PER_LINE_DELIVERY_DEFAULT 0x00000000 -#define mmHUBPREQ0_CURSOR_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000 -#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec -#define mmHUBPRET0_HUBPRET_CONTROL_DEFAULT 0x00e40000 -#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_READ_LINE0_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_READ_LINE1_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421 - - -// addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec -#define mmCURSOR0_CURSOR_CONTROL_DEFAULT 0x01000000 -#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_SIZE_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_POSITION_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_HOT_SPOT_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_DST_OFFSET_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON8_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON8_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec -#define mmHUBP1_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008 -#define mmHUBP1_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_TILING_CONFIG_DEFAULT 0x00000080 -#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000 -#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000 -#define mmHUBP1_DCHUBP_CNTL_DEFAULT 0x00001001 -#define mmHUBP1_HUBP_CLK_CNTL_DEFAULT 0x00000000 -#define mmHUBP1_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000 -#define mmHUBP1_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000 -#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000 -#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec -#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040 -#define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000 -#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_EXPANSION_MODE_DEFAULT 0x00000055 -#define mmHUBPREQ1_DCN_TTU_QOS_WM_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010 -#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ1_BLANK_OFFSET_0_DEFAULT 0x00000000 -#define mmHUBPREQ1_BLANK_OFFSET_1_DEFAULT 0x00000000 -#define mmHUBPREQ1_DST_DIMENSIONS_DEFAULT 0x00000000 -#define mmHUBPREQ1_DST_AFTER_SCALER_DEFAULT 0x00000000 -#define mmHUBPREQ1_PREFETCH_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ1_PREFETCH_SETTINS_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_VBLANK_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ1_VBLANK_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ1_VBLANK_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ1_VBLANK_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ1_VBLANK_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_5_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_6_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_7_DEFAULT 0x00000000 -#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000 -#define mmHUBPREQ1_PER_LINE_DELIVERY_DEFAULT 0x00000000 -#define mmHUBPREQ1_CURSOR_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000 -#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec -#define mmHUBPRET1_HUBPRET_CONTROL_DEFAULT 0x00e40000 -#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_READ_LINE0_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_READ_LINE1_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421 - - -// addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec -#define mmCURSOR1_CURSOR_CONTROL_DEFAULT 0x01000000 -#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_SIZE_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_POSITION_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_HOT_SPOT_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_DST_OFFSET_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON9_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON9_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec -#define mmHUBP2_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008 -#define mmHUBP2_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_TILING_CONFIG_DEFAULT 0x00000080 -#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000 -#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000 -#define mmHUBP2_DCHUBP_CNTL_DEFAULT 0x00001001 -#define mmHUBP2_HUBP_CLK_CNTL_DEFAULT 0x00000000 -#define mmHUBP2_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000 -#define mmHUBP2_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000 -#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000 -#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec -#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040 -#define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000 -#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_EXPANSION_MODE_DEFAULT 0x00000055 -#define mmHUBPREQ2_DCN_TTU_QOS_WM_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010 -#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ2_BLANK_OFFSET_0_DEFAULT 0x00000000 -#define mmHUBPREQ2_BLANK_OFFSET_1_DEFAULT 0x00000000 -#define mmHUBPREQ2_DST_DIMENSIONS_DEFAULT 0x00000000 -#define mmHUBPREQ2_DST_AFTER_SCALER_DEFAULT 0x00000000 -#define mmHUBPREQ2_PREFETCH_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ2_PREFETCH_SETTINS_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_VBLANK_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ2_VBLANK_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ2_VBLANK_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ2_VBLANK_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ2_VBLANK_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_5_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_6_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_7_DEFAULT 0x00000000 -#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000 -#define mmHUBPREQ2_PER_LINE_DELIVERY_DEFAULT 0x00000000 -#define mmHUBPREQ2_CURSOR_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000 -#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec -#define mmHUBPRET2_HUBPRET_CONTROL_DEFAULT 0x00e40000 -#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_READ_LINE0_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_READ_LINE1_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421 - - -// addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec -#define mmCURSOR2_CURSOR_CONTROL_DEFAULT 0x01000000 -#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_SIZE_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_POSITION_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_HOT_SPOT_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_DST_OFFSET_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON10_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON10_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec -#define mmHUBP3_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008 -#define mmHUBP3_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_TILING_CONFIG_DEFAULT 0x00000080 -#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000 -#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000 -#define mmHUBP3_DCHUBP_CNTL_DEFAULT 0x00001001 -#define mmHUBP3_HUBP_CLK_CNTL_DEFAULT 0x00000000 -#define mmHUBP3_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000 -#define mmHUBP3_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000 -#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000 -#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec -#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040 -#define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000 -#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_EXPANSION_MODE_DEFAULT 0x00000055 -#define mmHUBPREQ3_DCN_TTU_QOS_WM_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010 -#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ3_BLANK_OFFSET_0_DEFAULT 0x00000000 -#define mmHUBPREQ3_BLANK_OFFSET_1_DEFAULT 0x00000000 -#define mmHUBPREQ3_DST_DIMENSIONS_DEFAULT 0x00000000 -#define mmHUBPREQ3_DST_AFTER_SCALER_DEFAULT 0x00000000 -#define mmHUBPREQ3_PREFETCH_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ3_PREFETCH_SETTINS_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_VBLANK_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ3_VBLANK_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ3_VBLANK_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ3_VBLANK_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ3_VBLANK_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_5_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_6_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_7_DEFAULT 0x00000000 -#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000 -#define mmHUBPREQ3_PER_LINE_DELIVERY_DEFAULT 0x00000000 -#define mmHUBPREQ3_CURSOR_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000 -#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec -#define mmHUBPRET3_HUBPRET_CONTROL_DEFAULT 0x00e40000 -#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_READ_LINE0_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_READ_LINE1_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421 - - -// addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec -#define mmCURSOR3_CURSOR_CONTROL_DEFAULT 0x01000000 -#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_SIZE_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_POSITION_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_HOT_SPOT_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_DST_OFFSET_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON11_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON11_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec -#define mmDPP_TOP0_DPP_CONTROL_DEFAULT 0x70000000 -#define mmDPP_TOP0_DPP_SOFT_RESET_DEFAULT 0x00000000 -#define mmDPP_TOP0_DPP_CRC_VAL_R_G_DEFAULT 0x00000000 -#define mmDPP_TOP0_DPP_CRC_VAL_B_A_DEFAULT 0x00000000 -#define mmDPP_TOP0_DPP_CRC_CTRL_DEFAULT 0x00000000 -#define mmDPP_TOP0_HOST_READ_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec -#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 -#define mmCNVC_CFG0_FORMAT_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00 -#define mmCNVC_CFG0_DENORM_CONTROL_DEFAULT 0x00002000 -#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 -#define mmCNVC_CFG0_COLOR_KEYER_RED_DEFAULT 0x00000000 -#define mmCNVC_CFG0_COLOR_KEYER_GREEN_DEFAULT 0x00000000 -#define mmCNVC_CFG0_COLOR_KEYER_BLUE_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec -#define mmCNVC_CUR0_CURSOR0_CONTROL_DEFAULT 0x0003ff00 -#define mmCNVC_CUR0_CURSOR0_COLOR0_DEFAULT 0x00000000 -#define mmCNVC_CUR0_CURSOR0_COLOR1_DEFAULT 0x00000000 -#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00 - - -// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec -#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 -#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmDSCL0_SCL_MODE_DEFAULT 0x00000000 -#define mmDSCL0_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_CONTROL_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_2TAP_CONTROL_DEFAULT 0x01000100 -#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL0_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL0_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL0_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 -#define mmDSCL0_SCL_BLACK_OFFSET_DEFAULT 0x80000000 -#define mmDSCL0_DSCL_UPDATE_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_AUTOCAL_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmDSCL0_OTG_H_BLANK_DEFAULT 0x00000000 -#define mmDSCL0_OTG_V_BLANK_DEFAULT 0x00000000 -#define mmDSCL0_RECOUT_START_DEFAULT 0x00000000 -#define mmDSCL0_RECOUT_SIZE_DEFAULT 0x00000000 -#define mmDSCL0_MPC_SIZE_DEFAULT 0x00000000 -#define mmDSCL0_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmDSCL0_LB_MEMORY_CTRL_DEFAULT 0x00003f00 -#define mmDSCL0_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDSCL0_OBUF_CONTROL_DEFAULT 0xe0000000 -#define mmDSCL0_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec -#define mmCM0_CM_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_COMA_C11_C12_DEFAULT 0x00002000 -#define mmCM0_CM_COMA_C13_C14_DEFAULT 0x00000000 -#define mmCM0_CM_COMA_C21_C22_DEFAULT 0x20000000 -#define mmCM0_CM_COMA_C23_C24_DEFAULT 0x00000000 -#define mmCM0_CM_COMA_C31_C32_DEFAULT 0x00000000 -#define mmCM0_CM_COMA_C33_C34_DEFAULT 0x00002000 -#define mmCM0_CM_COMB_C11_C12_DEFAULT 0x00002000 -#define mmCM0_CM_COMB_C13_C14_DEFAULT 0x00000000 -#define mmCM0_CM_COMB_C21_C22_DEFAULT 0x20000000 -#define mmCM0_CM_COMB_C23_C24_DEFAULT 0x00000000 -#define mmCM0_CM_COMB_C31_C32_DEFAULT 0x00000000 -#define mmCM0_CM_COMB_C33_C34_DEFAULT 0x00002000 -#define mmCM0_CM_IGAM_CONTROL_DEFAULT 0x08000002 -#define mmCM0_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070 -#define mmCM0_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmCM0_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmCM0_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmCM0_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmCM0_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000 -#define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000 -#define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000 -#define mmCM0_CM_ICSC_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_ICSC_C11_C12_DEFAULT 0x00002000 -#define mmCM0_CM_ICSC_C13_C14_DEFAULT 0x00000000 -#define mmCM0_CM_ICSC_C21_C22_DEFAULT 0x20000000 -#define mmCM0_CM_ICSC_C23_C24_DEFAULT 0x00000000 -#define mmCM0_CM_ICSC_C31_C32_DEFAULT 0x00000000 -#define mmCM0_CM_ICSC_C33_C34_DEFAULT 0x00002000 -#define mmCM0_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmCM0_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmCM0_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmCM0_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmCM0_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmCM0_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmCM0_CM_OCSC_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_OCSC_C11_C12_DEFAULT 0x00002000 -#define mmCM0_CM_OCSC_C13_C14_DEFAULT 0x00000000 -#define mmCM0_CM_OCSC_C21_C22_DEFAULT 0x20000000 -#define mmCM0_CM_OCSC_C23_C24_DEFAULT 0x00000000 -#define mmCM0_CM_OCSC_C31_C32_DEFAULT 0x00000000 -#define mmCM0_CM_OCSC_C33_C34_DEFAULT 0x00002000 -#define mmCM0_CM_BNS_VALUES_R_DEFAULT 0x20000000 -#define mmCM0_CM_BNS_VALUES_G_DEFAULT 0x20000000 -#define mmCM0_CM_BNS_VALUES_B_DEFAULT 0x20000000 -#define mmCM0_CM_DGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM0_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000 -#define mmCM0_CM_HDR_MULT_COEF_DEFAULT 0x0001f000 -#define mmCM0_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff -#define mmCM0_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff -#define mmCM0_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff -#define mmCM0_CM_DENORM_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_CMOUT_CONTROL_DEFAULT 0x0000000a -#define mmCM0_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmCM0_CM_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCM0_CM_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON12_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON12_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec -#define mmDPP_TOP1_DPP_CONTROL_DEFAULT 0x70000000 -#define mmDPP_TOP1_DPP_SOFT_RESET_DEFAULT 0x00000000 -#define mmDPP_TOP1_DPP_CRC_VAL_R_G_DEFAULT 0x00000000 -#define mmDPP_TOP1_DPP_CRC_VAL_B_A_DEFAULT 0x00000000 -#define mmDPP_TOP1_DPP_CRC_CTRL_DEFAULT 0x00000000 -#define mmDPP_TOP1_HOST_READ_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec -#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 -#define mmCNVC_CFG1_FORMAT_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00 -#define mmCNVC_CFG1_DENORM_CONTROL_DEFAULT 0x00002000 -#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 -#define mmCNVC_CFG1_COLOR_KEYER_RED_DEFAULT 0x00000000 -#define mmCNVC_CFG1_COLOR_KEYER_GREEN_DEFAULT 0x00000000 -#define mmCNVC_CFG1_COLOR_KEYER_BLUE_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec -#define mmCNVC_CUR1_CURSOR0_CONTROL_DEFAULT 0x0003ff00 -#define mmCNVC_CUR1_CURSOR0_COLOR0_DEFAULT 0x00000000 -#define mmCNVC_CUR1_CURSOR0_COLOR1_DEFAULT 0x00000000 -#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00 - - -// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec -#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 -#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmDSCL1_SCL_MODE_DEFAULT 0x00000000 -#define mmDSCL1_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_CONTROL_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_2TAP_CONTROL_DEFAULT 0x01000100 -#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL1_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL1_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL1_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 -#define mmDSCL1_SCL_BLACK_OFFSET_DEFAULT 0x80000000 -#define mmDSCL1_DSCL_UPDATE_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_AUTOCAL_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmDSCL1_OTG_H_BLANK_DEFAULT 0x00000000 -#define mmDSCL1_OTG_V_BLANK_DEFAULT 0x00000000 -#define mmDSCL1_RECOUT_START_DEFAULT 0x00000000 -#define mmDSCL1_RECOUT_SIZE_DEFAULT 0x00000000 -#define mmDSCL1_MPC_SIZE_DEFAULT 0x00000000 -#define mmDSCL1_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmDSCL1_LB_MEMORY_CTRL_DEFAULT 0x00003f00 -#define mmDSCL1_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDSCL1_OBUF_CONTROL_DEFAULT 0xe0000000 -#define mmDSCL1_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec -#define mmCM1_CM_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_COMA_C11_C12_DEFAULT 0x00002000 -#define mmCM1_CM_COMA_C13_C14_DEFAULT 0x00000000 -#define mmCM1_CM_COMA_C21_C22_DEFAULT 0x20000000 -#define mmCM1_CM_COMA_C23_C24_DEFAULT 0x00000000 -#define mmCM1_CM_COMA_C31_C32_DEFAULT 0x00000000 -#define mmCM1_CM_COMA_C33_C34_DEFAULT 0x00002000 -#define mmCM1_CM_COMB_C11_C12_DEFAULT 0x00002000 -#define mmCM1_CM_COMB_C13_C14_DEFAULT 0x00000000 -#define mmCM1_CM_COMB_C21_C22_DEFAULT 0x20000000 -#define mmCM1_CM_COMB_C23_C24_DEFAULT 0x00000000 -#define mmCM1_CM_COMB_C31_C32_DEFAULT 0x00000000 -#define mmCM1_CM_COMB_C33_C34_DEFAULT 0x00002000 -#define mmCM1_CM_IGAM_CONTROL_DEFAULT 0x08000002 -#define mmCM1_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070 -#define mmCM1_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmCM1_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmCM1_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmCM1_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmCM1_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000 -#define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000 -#define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000 -#define mmCM1_CM_ICSC_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_ICSC_C11_C12_DEFAULT 0x00002000 -#define mmCM1_CM_ICSC_C13_C14_DEFAULT 0x00000000 -#define mmCM1_CM_ICSC_C21_C22_DEFAULT 0x20000000 -#define mmCM1_CM_ICSC_C23_C24_DEFAULT 0x00000000 -#define mmCM1_CM_ICSC_C31_C32_DEFAULT 0x00000000 -#define mmCM1_CM_ICSC_C33_C34_DEFAULT 0x00002000 -#define mmCM1_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmCM1_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmCM1_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmCM1_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmCM1_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmCM1_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmCM1_CM_OCSC_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_OCSC_C11_C12_DEFAULT 0x00002000 -#define mmCM1_CM_OCSC_C13_C14_DEFAULT 0x00000000 -#define mmCM1_CM_OCSC_C21_C22_DEFAULT 0x20000000 -#define mmCM1_CM_OCSC_C23_C24_DEFAULT 0x00000000 -#define mmCM1_CM_OCSC_C31_C32_DEFAULT 0x00000000 -#define mmCM1_CM_OCSC_C33_C34_DEFAULT 0x00002000 -#define mmCM1_CM_BNS_VALUES_R_DEFAULT 0x20000000 -#define mmCM1_CM_BNS_VALUES_G_DEFAULT 0x20000000 -#define mmCM1_CM_BNS_VALUES_B_DEFAULT 0x20000000 -#define mmCM1_CM_DGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM1_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000 -#define mmCM1_CM_HDR_MULT_COEF_DEFAULT 0x0001f000 -#define mmCM1_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff -#define mmCM1_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff -#define mmCM1_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff -#define mmCM1_CM_DENORM_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_CMOUT_CONTROL_DEFAULT 0x0000000a -#define mmCM1_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmCM1_CM_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCM1_CM_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON13_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON13_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec -#define mmDPP_TOP2_DPP_CONTROL_DEFAULT 0x70000000 -#define mmDPP_TOP2_DPP_SOFT_RESET_DEFAULT 0x00000000 -#define mmDPP_TOP2_DPP_CRC_VAL_R_G_DEFAULT 0x00000000 -#define mmDPP_TOP2_DPP_CRC_VAL_B_A_DEFAULT 0x00000000 -#define mmDPP_TOP2_DPP_CRC_CTRL_DEFAULT 0x00000000 -#define mmDPP_TOP2_HOST_READ_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec -#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 -#define mmCNVC_CFG2_FORMAT_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00 -#define mmCNVC_CFG2_DENORM_CONTROL_DEFAULT 0x00002000 -#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 -#define mmCNVC_CFG2_COLOR_KEYER_RED_DEFAULT 0x00000000 -#define mmCNVC_CFG2_COLOR_KEYER_GREEN_DEFAULT 0x00000000 -#define mmCNVC_CFG2_COLOR_KEYER_BLUE_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec -#define mmCNVC_CUR2_CURSOR0_CONTROL_DEFAULT 0x0003ff00 -#define mmCNVC_CUR2_CURSOR0_COLOR0_DEFAULT 0x00000000 -#define mmCNVC_CUR2_CURSOR0_COLOR1_DEFAULT 0x00000000 -#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00 - - -// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec -#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 -#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmDSCL2_SCL_MODE_DEFAULT 0x00000000 -#define mmDSCL2_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_CONTROL_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_2TAP_CONTROL_DEFAULT 0x01000100 -#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL2_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL2_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL2_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 -#define mmDSCL2_SCL_BLACK_OFFSET_DEFAULT 0x80000000 -#define mmDSCL2_DSCL_UPDATE_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_AUTOCAL_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmDSCL2_OTG_H_BLANK_DEFAULT 0x00000000 -#define mmDSCL2_OTG_V_BLANK_DEFAULT 0x00000000 -#define mmDSCL2_RECOUT_START_DEFAULT 0x00000000 -#define mmDSCL2_RECOUT_SIZE_DEFAULT 0x00000000 -#define mmDSCL2_MPC_SIZE_DEFAULT 0x00000000 -#define mmDSCL2_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmDSCL2_LB_MEMORY_CTRL_DEFAULT 0x00003f00 -#define mmDSCL2_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDSCL2_OBUF_CONTROL_DEFAULT 0xe0000000 -#define mmDSCL2_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec -#define mmCM2_CM_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_COMA_C11_C12_DEFAULT 0x00002000 -#define mmCM2_CM_COMA_C13_C14_DEFAULT 0x00000000 -#define mmCM2_CM_COMA_C21_C22_DEFAULT 0x20000000 -#define mmCM2_CM_COMA_C23_C24_DEFAULT 0x00000000 -#define mmCM2_CM_COMA_C31_C32_DEFAULT 0x00000000 -#define mmCM2_CM_COMA_C33_C34_DEFAULT 0x00002000 -#define mmCM2_CM_COMB_C11_C12_DEFAULT 0x00002000 -#define mmCM2_CM_COMB_C13_C14_DEFAULT 0x00000000 -#define mmCM2_CM_COMB_C21_C22_DEFAULT 0x20000000 -#define mmCM2_CM_COMB_C23_C24_DEFAULT 0x00000000 -#define mmCM2_CM_COMB_C31_C32_DEFAULT 0x00000000 -#define mmCM2_CM_COMB_C33_C34_DEFAULT 0x00002000 -#define mmCM2_CM_IGAM_CONTROL_DEFAULT 0x08000002 -#define mmCM2_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070 -#define mmCM2_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmCM2_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmCM2_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmCM2_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmCM2_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000 -#define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000 -#define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000 -#define mmCM2_CM_ICSC_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_ICSC_C11_C12_DEFAULT 0x00002000 -#define mmCM2_CM_ICSC_C13_C14_DEFAULT 0x00000000 -#define mmCM2_CM_ICSC_C21_C22_DEFAULT 0x20000000 -#define mmCM2_CM_ICSC_C23_C24_DEFAULT 0x00000000 -#define mmCM2_CM_ICSC_C31_C32_DEFAULT 0x00000000 -#define mmCM2_CM_ICSC_C33_C34_DEFAULT 0x00002000 -#define mmCM2_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmCM2_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmCM2_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmCM2_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmCM2_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmCM2_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmCM2_CM_OCSC_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_OCSC_C11_C12_DEFAULT 0x00002000 -#define mmCM2_CM_OCSC_C13_C14_DEFAULT 0x00000000 -#define mmCM2_CM_OCSC_C21_C22_DEFAULT 0x20000000 -#define mmCM2_CM_OCSC_C23_C24_DEFAULT 0x00000000 -#define mmCM2_CM_OCSC_C31_C32_DEFAULT 0x00000000 -#define mmCM2_CM_OCSC_C33_C34_DEFAULT 0x00002000 -#define mmCM2_CM_BNS_VALUES_R_DEFAULT 0x20000000 -#define mmCM2_CM_BNS_VALUES_G_DEFAULT 0x20000000 -#define mmCM2_CM_BNS_VALUES_B_DEFAULT 0x20000000 -#define mmCM2_CM_DGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM2_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000 -#define mmCM2_CM_HDR_MULT_COEF_DEFAULT 0x0001f000 -#define mmCM2_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff -#define mmCM2_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff -#define mmCM2_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff -#define mmCM2_CM_DENORM_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_CMOUT_CONTROL_DEFAULT 0x0000000a -#define mmCM2_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmCM2_CM_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCM2_CM_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON14_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON14_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec -#define mmDPP_TOP3_DPP_CONTROL_DEFAULT 0x70000000 -#define mmDPP_TOP3_DPP_SOFT_RESET_DEFAULT 0x00000000 -#define mmDPP_TOP3_DPP_CRC_VAL_R_G_DEFAULT 0x00000000 -#define mmDPP_TOP3_DPP_CRC_VAL_B_A_DEFAULT 0x00000000 -#define mmDPP_TOP3_DPP_CRC_CTRL_DEFAULT 0x00000000 -#define mmDPP_TOP3_HOST_READ_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec -#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 -#define mmCNVC_CFG3_FORMAT_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00 -#define mmCNVC_CFG3_DENORM_CONTROL_DEFAULT 0x00002000 -#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 -#define mmCNVC_CFG3_COLOR_KEYER_RED_DEFAULT 0x00000000 -#define mmCNVC_CFG3_COLOR_KEYER_GREEN_DEFAULT 0x00000000 -#define mmCNVC_CFG3_COLOR_KEYER_BLUE_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec -#define mmCNVC_CUR3_CURSOR0_CONTROL_DEFAULT 0x0003ff00 -#define mmCNVC_CUR3_CURSOR0_COLOR0_DEFAULT 0x00000000 -#define mmCNVC_CUR3_CURSOR0_COLOR1_DEFAULT 0x00000000 -#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00 - - -// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec -#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 -#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmDSCL3_SCL_MODE_DEFAULT 0x00000000 -#define mmDSCL3_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_CONTROL_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_2TAP_CONTROL_DEFAULT 0x01000100 -#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL3_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL3_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL3_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 -#define mmDSCL3_SCL_BLACK_OFFSET_DEFAULT 0x80000000 -#define mmDSCL3_DSCL_UPDATE_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_AUTOCAL_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmDSCL3_OTG_H_BLANK_DEFAULT 0x00000000 -#define mmDSCL3_OTG_V_BLANK_DEFAULT 0x00000000 -#define mmDSCL3_RECOUT_START_DEFAULT 0x00000000 -#define mmDSCL3_RECOUT_SIZE_DEFAULT 0x00000000 -#define mmDSCL3_MPC_SIZE_DEFAULT 0x00000000 -#define mmDSCL3_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmDSCL3_LB_MEMORY_CTRL_DEFAULT 0x00003f00 -#define mmDSCL3_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDSCL3_OBUF_CONTROL_DEFAULT 0xe0000000 -#define mmDSCL3_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec -#define mmCM3_CM_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_COMA_C11_C12_DEFAULT 0x00002000 -#define mmCM3_CM_COMA_C13_C14_DEFAULT 0x00000000 -#define mmCM3_CM_COMA_C21_C22_DEFAULT 0x20000000 -#define mmCM3_CM_COMA_C23_C24_DEFAULT 0x00000000 -#define mmCM3_CM_COMA_C31_C32_DEFAULT 0x00000000 -#define mmCM3_CM_COMA_C33_C34_DEFAULT 0x00002000 -#define mmCM3_CM_COMB_C11_C12_DEFAULT 0x00002000 -#define mmCM3_CM_COMB_C13_C14_DEFAULT 0x00000000 -#define mmCM3_CM_COMB_C21_C22_DEFAULT 0x20000000 -#define mmCM3_CM_COMB_C23_C24_DEFAULT 0x00000000 -#define mmCM3_CM_COMB_C31_C32_DEFAULT 0x00000000 -#define mmCM3_CM_COMB_C33_C34_DEFAULT 0x00002000 -#define mmCM3_CM_IGAM_CONTROL_DEFAULT 0x08000002 -#define mmCM3_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070 -#define mmCM3_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmCM3_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmCM3_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmCM3_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmCM3_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000 -#define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000 -#define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000 -#define mmCM3_CM_ICSC_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_ICSC_C11_C12_DEFAULT 0x00002000 -#define mmCM3_CM_ICSC_C13_C14_DEFAULT 0x00000000 -#define mmCM3_CM_ICSC_C21_C22_DEFAULT 0x20000000 -#define mmCM3_CM_ICSC_C23_C24_DEFAULT 0x00000000 -#define mmCM3_CM_ICSC_C31_C32_DEFAULT 0x00000000 -#define mmCM3_CM_ICSC_C33_C34_DEFAULT 0x00002000 -#define mmCM3_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmCM3_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmCM3_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmCM3_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmCM3_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmCM3_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmCM3_CM_OCSC_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_OCSC_C11_C12_DEFAULT 0x00002000 -#define mmCM3_CM_OCSC_C13_C14_DEFAULT 0x00000000 -#define mmCM3_CM_OCSC_C21_C22_DEFAULT 0x20000000 -#define mmCM3_CM_OCSC_C23_C24_DEFAULT 0x00000000 -#define mmCM3_CM_OCSC_C31_C32_DEFAULT 0x00000000 -#define mmCM3_CM_OCSC_C33_C34_DEFAULT 0x00002000 -#define mmCM3_CM_BNS_VALUES_R_DEFAULT 0x20000000 -#define mmCM3_CM_BNS_VALUES_G_DEFAULT 0x20000000 -#define mmCM3_CM_BNS_VALUES_B_DEFAULT 0x20000000 -#define mmCM3_CM_DGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM3_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000 -#define mmCM3_CM_HDR_MULT_COEF_DEFAULT 0x0001f000 -#define mmCM3_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff -#define mmCM3_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff -#define mmCM3_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff -#define mmCM3_CM_DENORM_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_CMOUT_CONTROL_DEFAULT 0x0000000a -#define mmCM3_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmCM3_CM_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCM3_CM_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON15_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON15_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mpc_mpcc0_dispdec -#define mmMPCC0_MPCC_TOP_SEL_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_BOT_SEL_DEFAULT 0x0000000f -#define mmMPCC0_MPCC_OPP_ID_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_CONTROL_DEFAULT 0xffff0061 -#define mmMPCC0_MPCC_SM_CONTROL_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f -#define mmMPCC0_MPCC_TOP_OFFSET_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_BOT_OFFSET_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_OFFSET_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_BG_R_CR_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_BG_G_Y_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_BG_B_CB_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_STALL_STATUS_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mpc_mpcc1_dispdec -#define mmMPCC1_MPCC_TOP_SEL_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_BOT_SEL_DEFAULT 0x0000000f -#define mmMPCC1_MPCC_OPP_ID_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_CONTROL_DEFAULT 0xffff0061 -#define mmMPCC1_MPCC_SM_CONTROL_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f -#define mmMPCC1_MPCC_TOP_OFFSET_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_BOT_OFFSET_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_OFFSET_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_BG_R_CR_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_BG_G_Y_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_BG_B_CB_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_STALL_STATUS_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mpc_mpcc2_dispdec -#define mmMPCC2_MPCC_TOP_SEL_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_BOT_SEL_DEFAULT 0x0000000f -#define mmMPCC2_MPCC_OPP_ID_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_CONTROL_DEFAULT 0xffff0061 -#define mmMPCC2_MPCC_SM_CONTROL_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f -#define mmMPCC2_MPCC_TOP_OFFSET_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_BOT_OFFSET_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_OFFSET_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_BG_R_CR_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_BG_G_Y_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_BG_B_CB_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_STALL_STATUS_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mpc_mpcc3_dispdec -#define mmMPCC3_MPCC_TOP_SEL_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_BOT_SEL_DEFAULT 0x0000000f -#define mmMPCC3_MPCC_OPP_ID_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_CONTROL_DEFAULT 0xffff0061 -#define mmMPCC3_MPCC_SM_CONTROL_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f -#define mmMPCC3_MPCC_TOP_OFFSET_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_BOT_OFFSET_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_OFFSET_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_BG_R_CR_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_BG_G_Y_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_BG_B_CB_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_STALL_STATUS_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mpc_mpc_cfg_dispdec -#define mmMPC_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmMPC_SOFT_RESET_DEFAULT 0x00000000 -#define mmMPC_CRC_CTRL_DEFAULT 0x00000000 -#define mmMPC_CRC_SEL_CONTROL_DEFAULT 0x00000000 -#define mmMPC_CRC_RESULT_AR_DEFAULT 0x00000000 -#define mmMPC_CRC_RESULT_GB_DEFAULT 0x00000000 -#define mmMPC_CRC_RESULT_C_DEFAULT 0x00000000 -#define mmMPC_PERFMON_EVENT_CTRL_DEFAULT 0x00000000 -#define mmMPC_BYPASS_BG_AR_DEFAULT 0x00000000 -#define mmMPC_BYPASS_BG_GB_DEFAULT 0x00000000 -#define mmMPC_OUT0_MUX_DEFAULT 0x0000000f -#define mmMPC_OUT1_MUX_DEFAULT 0x0000000f -#define mmMPC_OUT2_MUX_DEFAULT 0x0000000f -#define mmMPC_OUT3_MUX_DEFAULT 0x0000000f -#define mmMPC_STALL_GRACE_WINDOW_DEFAULT 0x00000000 -#define mmADR_CFG_VUPDATE_LOCK_SET0_DEFAULT 0x00000000 -#define mmADR_VUPDATE_LOCK_SET0_DEFAULT 0x00000000 -#define mmCUR0_VUPDATE_LOCK_SET0_DEFAULT 0x00000000 -#define mmCUR1_VUPDATE_LOCK_SET0_DEFAULT 0x00000000 -#define mmADR_CFG_VUPDATE_LOCK_SET1_DEFAULT 0x00000000 -#define mmADR_VUPDATE_LOCK_SET1_DEFAULT 0x00000000 -#define mmCUR0_VUPDATE_LOCK_SET1_DEFAULT 0x00000000 -#define mmCUR1_VUPDATE_LOCK_SET1_DEFAULT 0x00000000 -#define mmADR_CFG_VUPDATE_LOCK_SET2_DEFAULT 0x00000000 -#define mmADR_VUPDATE_LOCK_SET2_DEFAULT 0x00000000 -#define mmCUR0_VUPDATE_LOCK_SET2_DEFAULT 0x00000000 -#define mmCUR1_VUPDATE_LOCK_SET2_DEFAULT 0x00000000 -#define mmADR_CFG_VUPDATE_LOCK_SET3_DEFAULT 0x00000000 -#define mmADR_VUPDATE_LOCK_SET3_DEFAULT 0x00000000 -#define mmCUR0_VUPDATE_LOCK_SET3_DEFAULT 0x00000000 -#define mmCUR1_VUPDATE_LOCK_SET3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON16_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON16_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_abm0_dispdec -#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_USER_LEVEL_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_ABM_CNTL_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_CNTL_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400 -#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400 -#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400 -#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400 -#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400 -#define mmABM0_DC_ABM1_ACE_THRES_12_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_ACE_THRES_34_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_1_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_2_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_3_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_4_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_5_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_6_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_7_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_8_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_9_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_10_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_11_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_12_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_13_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_14_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_15_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_16_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_17_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_18_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_19_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_20_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_21_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_22_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_23_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_24_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_abm1_dispdec -#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_USER_LEVEL_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_ABM_CNTL_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_CNTL_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400 -#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400 -#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400 -#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400 -#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400 -#define mmABM1_DC_ABM1_ACE_THRES_12_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_ACE_THRES_34_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_1_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_2_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_3_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_4_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_5_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_6_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_7_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_8_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_9_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_10_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_11_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_12_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_13_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_14_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_15_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_16_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_17_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_18_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_19_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_20_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_21_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_22_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_23_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_24_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_fmt0_dispdec -#define mmFMT0_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT0_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT0_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT0_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT0_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT0_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT0_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT0_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT0_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_oppbuf0_dispdec -#define mmOPPBUF0_OPPBUF_CONTROL_DEFAULT 0x00000000 -#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 -#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe0_dispdec -#define mmOPP_PIPE0_OPP_PIPE_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec -#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff -#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_fmt1_dispdec -#define mmFMT1_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT1_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT1_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT1_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT1_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT1_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT1_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT1_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT1_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_oppbuf1_dispdec -#define mmOPPBUF1_OPPBUF_CONTROL_DEFAULT 0x00000000 -#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 -#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe1_dispdec -#define mmOPP_PIPE1_OPP_PIPE_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec -#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff -#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_fmt2_dispdec -#define mmFMT2_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT2_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT2_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT2_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT2_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT2_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT2_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT2_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT2_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_oppbuf2_dispdec -#define mmOPPBUF2_OPPBUF_CONTROL_DEFAULT 0x00000000 -#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 -#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe2_dispdec -#define mmOPP_PIPE2_OPP_PIPE_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec -#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff -#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_fmt3_dispdec -#define mmFMT3_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT3_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT3_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT3_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT3_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT3_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT3_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT3_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT3_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_oppbuf3_dispdec -#define mmOPPBUF3_OPPBUF_CONTROL_DEFAULT 0x00000000 -#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 -#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe3_dispdec -#define mmOPP_PIPE3_OPP_PIPE_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec -#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff -#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_fmt4_dispdec -#define mmFMT4_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT4_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT4_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT4_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT4_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT4_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT4_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT4_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT4_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_oppbuf4_dispdec -#define mmOPPBUF4_OPPBUF_CONTROL_DEFAULT 0x00000000 -#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 -#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe4_dispdec -#define mmOPP_PIPE4_OPP_PIPE_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec -#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff -#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_fmt5_dispdec -#define mmFMT5_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT5_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT5_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT5_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT5_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT5_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT5_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT5_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT5_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_oppbuf5_dispdec -#define mmOPPBUF5_OPPBUF_CONTROL_DEFAULT 0x00000000 -#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 -#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe5_dispdec -#define mmOPP_PIPE5_OPP_PIPE_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec -#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff -#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_top_dispdec -#define mmOPP_TOP_CLK_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON17_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON17_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_odm0_dispdec -#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define mmODM0_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmODM0_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_odm1_dispdec -#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define mmODM1_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmODM1_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_odm2_dispdec -#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define mmODM2_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmODM2_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_odm3_dispdec -#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define mmODM3_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmODM3_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_odm4_dispdec -#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define mmODM4_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmODM4_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_odm5_dispdec -#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define mmODM5_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmODM5_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_otg0_dispdec -#define mmOTG0_OTG_H_TOTAL_DEFAULT 0x00000000 -#define mmOTG0_OTG_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG0_OTG_H_SYNC_A_DEFAULT 0x00000000 -#define mmOTG0_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_TOTAL_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_TOTAL_MID_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_SYNC_A_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG0_OTG_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmOTG0_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmOTG0_OTG_CONTROL_DEFAULT 0x80000110 -#define mmOTG0_OTG_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmOTG0_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmOTG0_OTG_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_STATUS_POSITION_DEFAULT 0x00000000 -#define mmOTG0_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmOTG0_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmOTG0_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmOTG0_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmOTG0_OTG_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_COUNT_RESET_DEFAULT 0x00000000 -#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_STEREO_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmOTG0_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmOTG0_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmOTG0_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmOTG0_OTG_MASTER_EN_DEFAULT 0x00000000 -#define mmOTG0_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG0_OTG_BLACK_COLOR_DEFAULT 0x00000000 -#define mmOTG0_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC2_DATA_B_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC3_DATA_B_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff -#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmOTG0_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmOTG0_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 -#define mmOTG0_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 -#define mmOTG0_OTG_VREADY_PARAM_DEFAULT 0x00000000 -#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG0_OTG_GSL_CONTROL_DEFAULT 0x00020000 -#define mmOTG0_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 -#define mmOTG0_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 -#define mmOTG0_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 -#define mmOTG0_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 -#define mmOTG0_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 -#define mmOTG0_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 -#define mmOTG0_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 -#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_DRR_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_otg1_dispdec -#define mmOTG1_OTG_H_TOTAL_DEFAULT 0x00000000 -#define mmOTG1_OTG_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG1_OTG_H_SYNC_A_DEFAULT 0x00000000 -#define mmOTG1_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_TOTAL_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_TOTAL_MID_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_SYNC_A_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG1_OTG_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmOTG1_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmOTG1_OTG_CONTROL_DEFAULT 0x80000110 -#define mmOTG1_OTG_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmOTG1_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmOTG1_OTG_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_STATUS_POSITION_DEFAULT 0x00000000 -#define mmOTG1_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmOTG1_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmOTG1_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmOTG1_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmOTG1_OTG_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_COUNT_RESET_DEFAULT 0x00000000 -#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_STEREO_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmOTG1_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmOTG1_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmOTG1_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmOTG1_OTG_MASTER_EN_DEFAULT 0x00000000 -#define mmOTG1_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG1_OTG_BLACK_COLOR_DEFAULT 0x00000000 -#define mmOTG1_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC2_DATA_B_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC3_DATA_B_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff -#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmOTG1_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmOTG1_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 -#define mmOTG1_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 -#define mmOTG1_OTG_VREADY_PARAM_DEFAULT 0x00000000 -#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG1_OTG_GSL_CONTROL_DEFAULT 0x00020000 -#define mmOTG1_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 -#define mmOTG1_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 -#define mmOTG1_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 -#define mmOTG1_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 -#define mmOTG1_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 -#define mmOTG1_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 -#define mmOTG1_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 -#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_DRR_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_otg2_dispdec -#define mmOTG2_OTG_H_TOTAL_DEFAULT 0x00000000 -#define mmOTG2_OTG_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG2_OTG_H_SYNC_A_DEFAULT 0x00000000 -#define mmOTG2_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_TOTAL_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_TOTAL_MID_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_SYNC_A_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG2_OTG_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmOTG2_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmOTG2_OTG_CONTROL_DEFAULT 0x80000110 -#define mmOTG2_OTG_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmOTG2_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmOTG2_OTG_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_STATUS_POSITION_DEFAULT 0x00000000 -#define mmOTG2_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmOTG2_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmOTG2_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmOTG2_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmOTG2_OTG_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_COUNT_RESET_DEFAULT 0x00000000 -#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_STEREO_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmOTG2_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmOTG2_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmOTG2_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmOTG2_OTG_MASTER_EN_DEFAULT 0x00000000 -#define mmOTG2_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG2_OTG_BLACK_COLOR_DEFAULT 0x00000000 -#define mmOTG2_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC2_DATA_B_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC3_DATA_B_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff -#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmOTG2_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmOTG2_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 -#define mmOTG2_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 -#define mmOTG2_OTG_VREADY_PARAM_DEFAULT 0x00000000 -#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG2_OTG_GSL_CONTROL_DEFAULT 0x00020000 -#define mmOTG2_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 -#define mmOTG2_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 -#define mmOTG2_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 -#define mmOTG2_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 -#define mmOTG2_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 -#define mmOTG2_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 -#define mmOTG2_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 -#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_DRR_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_otg3_dispdec -#define mmOTG3_OTG_H_TOTAL_DEFAULT 0x00000000 -#define mmOTG3_OTG_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG3_OTG_H_SYNC_A_DEFAULT 0x00000000 -#define mmOTG3_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_TOTAL_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_TOTAL_MID_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_SYNC_A_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG3_OTG_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmOTG3_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmOTG3_OTG_CONTROL_DEFAULT 0x80000110 -#define mmOTG3_OTG_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmOTG3_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmOTG3_OTG_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_STATUS_POSITION_DEFAULT 0x00000000 -#define mmOTG3_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmOTG3_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmOTG3_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmOTG3_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmOTG3_OTG_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_COUNT_RESET_DEFAULT 0x00000000 -#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_STEREO_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmOTG3_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmOTG3_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmOTG3_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmOTG3_OTG_MASTER_EN_DEFAULT 0x00000000 -#define mmOTG3_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG3_OTG_BLACK_COLOR_DEFAULT 0x00000000 -#define mmOTG3_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC2_DATA_B_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC3_DATA_B_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff -#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmOTG3_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmOTG3_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 -#define mmOTG3_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 -#define mmOTG3_OTG_VREADY_PARAM_DEFAULT 0x00000000 -#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG3_OTG_GSL_CONTROL_DEFAULT 0x00020000 -#define mmOTG3_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 -#define mmOTG3_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 -#define mmOTG3_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 -#define mmOTG3_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 -#define mmOTG3_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 -#define mmOTG3_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 -#define mmOTG3_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 -#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_DRR_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_otg4_dispdec -#define mmOTG4_OTG_H_TOTAL_DEFAULT 0x00000000 -#define mmOTG4_OTG_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG4_OTG_H_SYNC_A_DEFAULT 0x00000000 -#define mmOTG4_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_TOTAL_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_TOTAL_MID_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_SYNC_A_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG4_OTG_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmOTG4_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmOTG4_OTG_CONTROL_DEFAULT 0x80000110 -#define mmOTG4_OTG_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmOTG4_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmOTG4_OTG_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_STATUS_POSITION_DEFAULT 0x00000000 -#define mmOTG4_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmOTG4_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmOTG4_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmOTG4_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmOTG4_OTG_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_COUNT_RESET_DEFAULT 0x00000000 -#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_STEREO_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmOTG4_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmOTG4_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmOTG4_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmOTG4_OTG_MASTER_EN_DEFAULT 0x00000000 -#define mmOTG4_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG4_OTG_BLACK_COLOR_DEFAULT 0x00000000 -#define mmOTG4_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC2_DATA_B_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC3_DATA_B_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff -#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmOTG4_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmOTG4_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 -#define mmOTG4_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 -#define mmOTG4_OTG_VREADY_PARAM_DEFAULT 0x00000000 -#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG4_OTG_GSL_CONTROL_DEFAULT 0x00020000 -#define mmOTG4_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 -#define mmOTG4_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 -#define mmOTG4_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 -#define mmOTG4_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 -#define mmOTG4_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 -#define mmOTG4_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 -#define mmOTG4_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 -#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_DRR_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_otg5_dispdec -#define mmOTG5_OTG_H_TOTAL_DEFAULT 0x00000000 -#define mmOTG5_OTG_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG5_OTG_H_SYNC_A_DEFAULT 0x00000000 -#define mmOTG5_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_TOTAL_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_TOTAL_MID_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_SYNC_A_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG5_OTG_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmOTG5_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmOTG5_OTG_CONTROL_DEFAULT 0x80000110 -#define mmOTG5_OTG_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmOTG5_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmOTG5_OTG_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_STATUS_POSITION_DEFAULT 0x00000000 -#define mmOTG5_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmOTG5_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmOTG5_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmOTG5_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmOTG5_OTG_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_COUNT_RESET_DEFAULT 0x00000000 -#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_STEREO_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmOTG5_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmOTG5_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmOTG5_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmOTG5_OTG_MASTER_EN_DEFAULT 0x00000000 -#define mmOTG5_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG5_OTG_BLACK_COLOR_DEFAULT 0x00000000 -#define mmOTG5_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC2_DATA_B_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC3_DATA_B_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff -#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmOTG5_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmOTG5_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 -#define mmOTG5_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 -#define mmOTG5_OTG_VREADY_PARAM_DEFAULT 0x00000000 -#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG5_OTG_GSL_CONTROL_DEFAULT 0x00020000 -#define mmOTG5_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 -#define mmOTG5_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 -#define mmOTG5_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 -#define mmOTG5_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 -#define mmOTG5_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 -#define mmOTG5_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 -#define mmOTG5_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 -#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_DRR_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_optc_misc_dispdec -#define mmDWB_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmGSL_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmOPTC_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOPTC_MISC_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON18_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON18_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dac_dispdec -#define mmDAC_ENABLE_DEFAULT 0x00000004 -#define mmDAC_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmDAC_CRC_EN_DEFAULT 0x00000000 -#define mmDAC_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDAC_CRC_SIG_RGB_MASK_DEFAULT 0x3fffffff -#define mmDAC_CRC_SIG_CONTROL_MASK_DEFAULT 0x0000003f -#define mmDAC_CRC_SIG_RGB_DEFAULT 0x3fffffff -#define mmDAC_CRC_SIG_CONTROL_DEFAULT 0x0000003f -#define mmDAC_SYNC_TRISTATE_CONTROL_DEFAULT 0x00000000 -#define mmDAC_STEREOSYNC_SELECT_DEFAULT 0x00000000 -#define mmDAC_AUTODETECT_CONTROL_DEFAULT 0x00070000 -#define mmDAC_AUTODETECT_CONTROL2_DEFAULT 0x0000000b -#define mmDAC_AUTODETECT_CONTROL3_DEFAULT 0x00000519 -#define mmDAC_AUTODETECT_STATUS_DEFAULT 0x00000000 -#define mmDAC_AUTODETECT_INT_CONTROL_DEFAULT 0x00000000 -#define mmDAC_FORCE_OUTPUT_CNTL_DEFAULT 0x00000000 -#define mmDAC_FORCE_DATA_DEFAULT 0x000001e6 -#define mmDAC_POWERDOWN_DEFAULT 0x01010100 -#define mmDAC_CONTROL_DEFAULT 0x00000000 -#define mmDAC_COMPARATOR_ENABLE_DEFAULT 0x00000000 -#define mmDAC_COMPARATOR_OUTPUT_DEFAULT 0x00000000 -#define mmDAC_PWR_CNTL_DEFAULT 0x00000000 -#define mmDAC_DFT_CONFIG_DEFAULT 0x00000000 -#define mmDAC_FIFO_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dout_i2c_dispdec -#define mmDC_I2C_CONTROL_DEFAULT 0x00000000 -#define mmDC_I2C_ARBITRATION_DEFAULT 0x00000001 -#define mmDC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDC_I2C_SW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC1_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC2_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC3_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC4_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC5_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC6_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC1_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC1_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC2_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC2_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC3_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC3_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC4_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC4_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC5_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC5_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC6_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC6_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION0_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION1_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION2_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION3_DEFAULT 0x00000000 -#define mmDC_I2C_DATA_DEFAULT 0x00000000 -#define mmDC_I2C_DDCVGA_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDCVGA_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDCVGA_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_EDID_DETECT_CTRL_DEFAULT 0x004001f4 -#define mmDC_I2C_READ_REQUEST_INTERRUPT_DEFAULT 0x40000000 - - -// addressBlock: dce_dc_dio_generic_i2c_dispdec -#define mmGENERIC_I2C_CONTROL_DEFAULT 0x00000000 -#define mmGENERIC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmGENERIC_I2C_STATUS_DEFAULT 0x00000000 -#define mmGENERIC_I2C_SPEED_DEFAULT 0x00000002 -#define mmGENERIC_I2C_SETUP_DEFAULT 0x00000000 -#define mmGENERIC_I2C_TRANSACTION_DEFAULT 0x00000000 -#define mmGENERIC_I2C_DATA_DEFAULT 0x00000000 -#define mmGENERIC_I2C_PIN_SELECTION_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dio_misc_dispdec -#define mmDIO_SCRATCH0_DEFAULT 0x00000000 -#define mmDIO_SCRATCH1_DEFAULT 0x00000000 -#define mmDIO_SCRATCH2_DEFAULT 0x00000000 -#define mmDIO_SCRATCH3_DEFAULT 0x00000000 -#define mmDIO_SCRATCH4_DEFAULT 0x00000000 -#define mmDIO_SCRATCH5_DEFAULT 0x00000000 -#define mmDIO_SCRATCH6_DEFAULT 0x00000000 -#define mmDIO_SCRATCH7_DEFAULT 0x00000000 -#define mmDCE_VCE_CONTROL_DEFAULT 0x00000000 -#define mmDIO_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDIO_MEM_PWR_CTRL_DEFAULT 0x6db6d800 -#define mmDIO_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDIO_CLK_CNTL_DEFAULT 0x00000000 -#define mmDIO_POWER_MANAGEMENT_CNTL_DEFAULT 0x00000000 -#define mmDIO_STEREOSYNC_SEL_DEFAULT 0x00000000 -#define mmDIO_SOFT_RESET_DEFAULT 0x00000000 -#define mmDIG_SOFT_RESET_DEFAULT 0x00000000 -#define mmDIO_MEM_PWR_STATUS1_DEFAULT 0x00000000 -#define mmDIO_CLK_CNTL2_DEFAULT 0x00000000 -#define mmDIO_CLK_CNTL3_DEFAULT 0x00000000 -#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_DEFAULT 0x00000000 -#define mmDIO_PSP_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIO_PSP_INTERRUPT_CLEAR_DEFAULT 0x00000000 -#define mmDIO_GENERIC_INTERRUPT_MESSAGE_DEFAULT 0x00000000 -#define mmDIO_GENERIC_INTERRUPT_CLEAR_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_hpd0_dispdec -#define mmHPD0_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD0_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD0_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_hpd1_dispdec -#define mmHPD1_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD1_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD1_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_hpd2_dispdec -#define mmHPD2_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD2_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD2_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_hpd3_dispdec -#define mmHPD3_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD3_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD3_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_hpd4_dispdec -#define mmHPD4_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD4_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD4_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_hpd5_dispdec -#define mmHPD5_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD5_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD5_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON19_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON19_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux0_dispdec -#define mmDP_AUX0_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX0_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux1_dispdec -#define mmDP_AUX1_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX1_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux2_dispdec -#define mmDP_AUX2_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX2_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux3_dispdec -#define mmDP_AUX3_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX3_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux4_dispdec -#define mmDP_AUX4_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX4_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux5_dispdec -#define mmDP_AUX5_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX5_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux6_dispdec -#define mmDP_AUX6_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX6_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX6_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX6_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX6_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig0_dispdec -#define mmDIG0_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG0_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG0_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG0_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG0_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG0_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG0_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG0_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG0_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG0_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG0_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG0_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG0_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG0_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG0_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG0_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG0_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG0_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG0_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG0_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG0_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp0_dispdec -#define mmDP0_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP0_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP0_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP0_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP0_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP0_DP_VID_N_DEFAULT 0x00002000 -#define mmDP0_DP_VID_M_DEFAULT 0x00000000 -#define mmDP0_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP0_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP0_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP0_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP0_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP0_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP0_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP0_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP0_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP0_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP0_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP0_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP0_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP0_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP0_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig1_dispdec -#define mmDIG1_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG1_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG1_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG1_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG1_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG1_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG1_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG1_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG1_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG1_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG1_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG1_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG1_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG1_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG1_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG1_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG1_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG1_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG1_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG1_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG1_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp1_dispdec -#define mmDP1_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP1_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP1_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP1_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP1_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP1_DP_VID_N_DEFAULT 0x00002000 -#define mmDP1_DP_VID_M_DEFAULT 0x00000000 -#define mmDP1_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP1_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP1_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP1_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP1_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP1_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP1_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP1_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP1_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP1_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP1_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP1_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP1_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP1_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP1_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig2_dispdec -#define mmDIG2_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG2_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG2_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG2_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG2_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG2_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG2_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG2_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG2_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG2_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG2_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG2_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG2_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG2_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG2_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG2_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG2_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG2_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG2_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG2_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG2_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp2_dispdec -#define mmDP2_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP2_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP2_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP2_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP2_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP2_DP_VID_N_DEFAULT 0x00002000 -#define mmDP2_DP_VID_M_DEFAULT 0x00000000 -#define mmDP2_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP2_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP2_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP2_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP2_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP2_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP2_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP2_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP2_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP2_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP2_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP2_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP2_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP2_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP2_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig3_dispdec -#define mmDIG3_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG3_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG3_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG3_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG3_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG3_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG3_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG3_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG3_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG3_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG3_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG3_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG3_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG3_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG3_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG3_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG3_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG3_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG3_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG3_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG3_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp3_dispdec -#define mmDP3_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP3_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP3_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP3_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP3_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP3_DP_VID_N_DEFAULT 0x00002000 -#define mmDP3_DP_VID_M_DEFAULT 0x00000000 -#define mmDP3_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP3_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP3_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP3_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP3_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP3_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP3_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP3_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP3_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP3_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP3_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP3_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP3_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP3_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP3_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig4_dispdec -#define mmDIG4_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG4_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG4_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG4_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG4_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG4_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG4_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG4_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG4_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG4_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG4_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG4_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG4_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG4_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG4_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG4_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG4_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG4_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG4_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG4_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG4_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp4_dispdec -#define mmDP4_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP4_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP4_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP4_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP4_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP4_DP_VID_N_DEFAULT 0x00002000 -#define mmDP4_DP_VID_M_DEFAULT 0x00000000 -#define mmDP4_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP4_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP4_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP4_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP4_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP4_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP4_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP4_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP4_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP4_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP4_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP4_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP4_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP4_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP4_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig5_dispdec -#define mmDIG5_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG5_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG5_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG5_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG5_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG5_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG5_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG5_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG5_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG5_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG5_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG5_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG5_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG5_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG5_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG5_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG5_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG5_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG5_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG5_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG5_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG5_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp5_dispdec -#define mmDP5_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP5_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP5_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP5_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP5_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP5_DP_VID_N_DEFAULT 0x00002000 -#define mmDP5_DP_VID_M_DEFAULT 0x00000000 -#define mmDP5_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP5_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP5_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP5_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP5_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP5_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP5_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP5_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP5_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP5_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP5_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP5_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP5_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP5_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP5_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig6_dispdec -#define mmDIG6_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG6_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG6_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG6_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG6_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG6_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG6_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG6_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG6_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG6_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG6_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG6_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG6_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG6_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG6_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG6_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG6_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG6_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG6_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG6_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG6_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG6_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp6_dispdec -#define mmDP6_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP6_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP6_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP6_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP6_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP6_DP_VID_N_DEFAULT 0x00002000 -#define mmDP6_DP_VID_M_DEFAULT 0x00000000 -#define mmDP6_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP6_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP6_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP6_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP6_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP6_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP6_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP6_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP6_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP6_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP6_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP6_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP6_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP6_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP6_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_dcio_dispdec -#define mmDC_GENERICA_DEFAULT 0x00000000 -#define mmDC_GENERICB_DEFAULT 0x00000000 -#define mmDC_REF_CLK_CNTL_DEFAULT 0x00000000 -#define mmDC_GPIO_DEBUG_DEFAULT 0x00000101 -#define mmUNIPHYA_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYB_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYC_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYC_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYD_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYD_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYE_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYE_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYF_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYF_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYG_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYG_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmDCIO_WRCMD_DELAY_DEFAULT 0x00033333 -#define mmDC_DVODATA_CONFIG_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_CNTL_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_STATE_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_REF_DIV_DEFAULT 0x00010000 -#define mmLVTMA_PWRSEQ_DELAY1_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_DELAY2_DEFAULT 0x00000000 -#define mmBL_PWM_CNTL_DEFAULT 0x00000000 -#define mmBL_PWM_CNTL2_DEFAULT 0x00000000 -#define mmBL_PWM_PERIOD_CNTL_DEFAULT 0x00000001 -#define mmBL_PWM_GRP1_REG_LOCK_DEFAULT 0x00000000 -#define mmDCIO_GSL_GENLK_PAD_CNTL_DEFAULT 0x00000000 -#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_DEFAULT 0x00000000 -#define mmDCIO_CLOCK_CNTL_DEFAULT 0x00000000 -#define mmDIO_OTG_EXT_VSYNC_CNTL_DEFAULT 0x00000000 -#define mmDCIO_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCIO_DPHY_SEL_DEFAULT 0x000000e4 -#define mmUNIPHY_IMPCAL_LINKA_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_LINKB_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_PERIOD_DEFAULT 0x00000000 -#define mmAUXP_IMPCAL_DEFAULT 0x0a000000 -#define mmAUXN_IMPCAL_DEFAULT 0x04000000 -#define mmDCIO_IMPCAL_CNTL_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_PSW_AB_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_LINKC_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_LINKD_DEFAULT 0x0f000000 -#define mmDCIO_IMPCAL_CNTL_CD_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_PSW_CD_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_LINKE_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_LINKF_DEFAULT 0x0f000000 -#define mmDCIO_IMPCAL_CNTL_EF_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_PSW_EF_DEFAULT 0x00000000 -#define mmDCIO_DPCS_TX_INTERRUPT_DEFAULT 0x00000000 -#define mmDCIO_DPCS_RX_INTERRUPT_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE0_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE1_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE2_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE3_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE4_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE5_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE6_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE7_DEFAULT 0x00000000 -#define mmDCIO_USBC_FLIP_EN_SEL_DEFAULT 0x00543210 - - -// addressBlock: dce_dc_dcio_dcio_chip_dispdec -#define mmDC_GPIO_GENERIC_MASK_DEFAULT 0x04444444 -#define mmDC_GPIO_GENERIC_A_DEFAULT 0x00000000 -#define mmDC_GPIO_GENERIC_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_GENERIC_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_MASK_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC1_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC1_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC1_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC1_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC2_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC2_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC2_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC2_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC3_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC3_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC3_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC3_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC4_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC4_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC4_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC4_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC5_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC5_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC5_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC5_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC6_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC6_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC6_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC6_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDCVGA_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDCVGA_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDCVGA_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDCVGA_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_SYNCA_MASK_DEFAULT 0x00004040 -#define mmDC_GPIO_SYNCA_A_DEFAULT 0x00000000 -#define mmDC_GPIO_SYNCA_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_SYNCA_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_GENLK_MASK_DEFAULT 0x10101a10 -#define mmDC_GPIO_GENLK_A_DEFAULT 0x00000000 -#define mmDC_GPIO_GENLK_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_GENLK_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_HPD_MASK_DEFAULT 0x44440440 -#define mmDC_GPIO_HPD_A_DEFAULT 0x00000000 -#define mmDC_GPIO_HPD_EN_DEFAULT 0x22220202 -#define mmDC_GPIO_HPD_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_PWRSEQ_MASK_DEFAULT 0x66404040 -#define mmDC_GPIO_PWRSEQ_A_DEFAULT 0x00000000 -#define mmDC_GPIO_PWRSEQ_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_PWRSEQ_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_PAD_STRENGTH_1_DEFAULT 0x47fc470f -#define mmDC_GPIO_PAD_STRENGTH_2_DEFAULT 0x00472147 -#define mmPHY_AUX_CNTL_DEFAULT 0x00010001 -#define mmDC_GPIO_I2CPAD_MASK_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_A_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_STRENGTH_DEFAULT 0x0000004c -#define mmDVO_STRENGTH_CONTROL_DEFAULT 0x31116060 -#define mmDVO_VREF_CONTROL_DEFAULT 0x00000000 -#define mmDVO_SKEW_ADJUST_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_MASK_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_A_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_EN_DEFAULT 0x00008000 -#define mmDC_GPIO_I2S_SPDIF_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_STRENGTH_DEFAULT 0x01021202 -#define mmDC_GPIO_TX12_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_AUX_CTRL_0_DEFAULT 0x00000000 -#define mmDC_GPIO_AUX_CTRL_1_DEFAULT 0x00500000 -#define mmDC_GPIO_AUX_CTRL_2_DEFAULT 0x00000000 -#define mmDC_GPIO_RXEN_DEFAULT 0x007fff7f -#define mmDC_GPIO_PULLUPEN_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_dcio_dac_dispdec -#define mmDAC_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDAC_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDAC_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDAC_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophycmregs0_dispdec -#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_DEFAULT 0x1c010000 -#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophytxregs0_dispdec -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophypllregs0_dispdec -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL_DEFAULT 0x00010520 - - -// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophycmregs1_dispdec -#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_DEFAULT 0x1c010000 -#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophytxregs1_dispdec -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophypllregs1_dispdec -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL_DEFAULT 0x00010520 - - -// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophycmregs2_dispdec -#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_DEFAULT 0x1c010000 -#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophytxregs2_dispdec -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophypllregs2_dispdec -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL_DEFAULT 0x00010520 - - -// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophycmregs3_dispdec -#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_DEFAULT 0x1c010000 -#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophytxregs3_dispdec -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophypllregs3_dispdec -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL_DEFAULT 0x00010520 - - -// addressBlock: dce_dc_dcio_dcio_zcal_dispdec -#define mmZCAL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_zcal_dc_zcalregs_dispdec -#define mmCOMP_EN_CTL_DEFAULT 0x00080000 -#define mmCOMP_EN_DFX_DEFAULT 0x00000000 -#define mmZCAL_FUSES_DEFAULT 0x00000000 - - -// addressBlock: vga_vgaseqind -#define ixSEQ00_DEFAULT 0x00000003 -#define ixSEQ01_DEFAULT 0x00000021 -#define ixSEQ02_DEFAULT 0x00000000 -#define ixSEQ03_DEFAULT 0x00000000 -#define ixSEQ04_DEFAULT 0x00000000 - - -// addressBlock: vga_vgacrtind -#define ixCRT00_DEFAULT 0x00000000 -#define ixCRT01_DEFAULT 0x00000000 -#define ixCRT02_DEFAULT 0x00000000 -#define ixCRT03_DEFAULT 0x00000000 -#define ixCRT04_DEFAULT 0x00000000 -#define ixCRT05_DEFAULT 0x00000000 -#define ixCRT06_DEFAULT 0x00000000 -#define ixCRT07_DEFAULT 0x00000000 -#define ixCRT08_DEFAULT 0x00000000 -#define ixCRT09_DEFAULT 0x00000000 -#define ixCRT0A_DEFAULT 0x00000000 -#define ixCRT0B_DEFAULT 0x00000000 -#define ixCRT0C_DEFAULT 0x00000000 -#define ixCRT0D_DEFAULT 0x00000000 -#define ixCRT0E_DEFAULT 0x00000000 -#define ixCRT0F_DEFAULT 0x00000000 -#define ixCRT10_DEFAULT 0x00000000 -#define ixCRT11_DEFAULT 0x00000000 -#define ixCRT12_DEFAULT 0x00000000 -#define ixCRT13_DEFAULT 0x00000000 -#define ixCRT14_DEFAULT 0x00000000 -#define ixCRT15_DEFAULT 0x00000000 -#define ixCRT16_DEFAULT 0x00000000 -#define ixCRT17_DEFAULT 0x00000000 -#define ixCRT18_DEFAULT 0x00000000 -#define ixCRT1E_DEFAULT 0x00000000 -#define ixCRT1F_DEFAULT 0x00000000 -#define ixCRT22_DEFAULT 0x00000000 - - -// addressBlock: vga_vgagrphind -#define ixGRA00_DEFAULT 0x00000000 -#define ixGRA01_DEFAULT 0x00000000 -#define ixGRA02_DEFAULT 0x00000000 -#define ixGRA03_DEFAULT 0x00000000 -#define ixGRA04_DEFAULT 0x00000000 -#define ixGRA05_DEFAULT 0x00000000 -#define ixGRA06_DEFAULT 0x00000000 -#define ixGRA07_DEFAULT 0x00000000 -#define ixGRA08_DEFAULT 0x00000000 - - -// addressBlock: vga_vgaattrind -#define ixATTR00_DEFAULT 0x00000000 -#define ixATTR01_DEFAULT 0x00000000 -#define ixATTR02_DEFAULT 0x00000000 -#define ixATTR03_DEFAULT 0x00000000 -#define ixATTR04_DEFAULT 0x00000000 -#define ixATTR05_DEFAULT 0x00000000 -#define ixATTR06_DEFAULT 0x00000000 -#define ixATTR07_DEFAULT 0x00000000 -#define ixATTR08_DEFAULT 0x00000000 -#define ixATTR09_DEFAULT 0x00000000 -#define ixATTR0A_DEFAULT 0x00000000 -#define ixATTR0B_DEFAULT 0x00000000 -#define ixATTR0C_DEFAULT 0x00000000 -#define ixATTR0D_DEFAULT 0x00000000 -#define ixATTR0E_DEFAULT 0x00000000 -#define ixATTR0F_DEFAULT 0x00000000 -#define ixATTR10_DEFAULT 0x00000000 -#define ixATTR11_DEFAULT 0x00000000 -#define ixATTR12_DEFAULT 0x00000000 -#define ixATTR13_DEFAULT 0x00000000 -#define ixATTR14_DEFAULT 0x00000000 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -// addressBlock: azendpoint_f2codecind -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x000000b4 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020 -#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000040 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x00000010 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x00000056 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH_DEFAULT 0x00000000 - - -// addressBlock: azendpoint_descriptorind -#define ixAUDIO_DESCRIPTOR0_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR13_DEFAULT 0x00000000 - - -// addressBlock: azendpoint_sinkinfoind -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION0_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION1_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION2_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION3_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION4_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION5_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION6_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION7_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION8_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION9_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION10_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION11_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION12_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION13_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION14_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION15_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION16_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION17_DEFAULT 0x00000000 - - -// addressBlock: azf0controller_azinputcrc0resultind -#define ixAZALIA_INPUT_CRC0_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azf0controller_azinputcrc1resultind -#define ixAZALIA_INPUT_CRC1_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azf0controller_azcrc0resultind -#define ixAZALIA_CRC0_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azf0controller_azcrc1resultind -#define ixAZALIA_CRC1_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azinputendpoint_f2codecind -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x000000f0 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x000000d6 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000010 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000 - - -// addressBlock: azroot_f2codecind -#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000003 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2_DEFAULT 0x00000001 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3_DEFAULT 0x000000aa -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0x00000000 - - -// addressBlock: azf0stream0_streamind -#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream1_streamind -#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream2_streamind -#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream3_streamind -#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream4_streamind -#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream5_streamind -#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream6_streamind -#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream7_streamind -#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream8_streamind -#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream9_streamind -#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream10_streamind -#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream11_streamind -#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream12_streamind -#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream13_streamind -#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream14_streamind -#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream15_streamind -#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint0_endpointind -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint1_endpointind -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint2_endpointind -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint3_endpointind -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint4_endpointind -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint5_endpointind -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint6_endpointind -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint7_endpointind -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint0_inputendpointind -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint1_inputendpointind -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint2_inputendpointind -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint3_inputendpointind -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint4_inputendpointind -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint5_inputendpointind -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint6_inputendpointind -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint7_inputendpointind -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - -#endif -- GitLab From 5a18155d991e808562dab8cd1f67ab637c0970c9 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Mon, 27 Nov 2017 17:00:12 +0800 Subject: [PATCH 0942/2547] drm/amd/include:cleanup raven1 gc header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/raven1/GC folder. Remove unused files: gc_9_1_default.h gc_9_1_sh_mask.h Signed-off-by: Feifei Xu Acked-by: Christian König Reviewed-by: Junwei Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 2 +- .../{raven1/GC => gc}/gc_9_1_offset.h | 0 .../asic_reg/raven1/GC/gc_9_1_default.h | 4005 -- .../asic_reg/raven1/GC/gc_9_1_sh_mask.h | 31191 ---------------- 4 files changed, 1 insertion(+), 35197 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/GC => gc}/gc_9_1_offset.h (100%) delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index a7ec158f114f..0cf36acbf51a 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -32,7 +32,7 @@ #include "soc15ip.h" #include "raven1/MP/mp_10_0_offset.h" -#include "raven1/GC/gc_9_1_offset.h" +#include "gc/gc_9_1_offset.h" #include "sdma0/sdma0_4_1_offset.h" MODULE_FIRMWARE("amdgpu/raven_asd.bin"); diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h deleted file mode 100644 index 582f1a66e354..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h +++ /dev/null @@ -1,4005 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _gc_9_1_DEFAULT_HEADER -#define _gc_9_1_DEFAULT_HEADER - - -// addressBlock: gc_grbmdec -#define mmGRBM_CNTL_DEFAULT 0x00000018 -#define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020 -#define mmGRBM_STATUS2_DEFAULT 0x00000000 -#define mmGRBM_PWR_CNTL_DEFAULT 0x00000000 -#define mmGRBM_STATUS_DEFAULT 0x00000000 -#define mmGRBM_STATUS_SE0_DEFAULT 0x00000000 -#define mmGRBM_STATUS_SE1_DEFAULT 0x00000000 -#define mmGRBM_SOFT_RESET_DEFAULT 0x00000000 -#define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100 -#define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008 -#define mmGRBM_WAIT_IDLE_CLOCKS_DEFAULT 0x00000030 -#define mmGRBM_STATUS_SE2_DEFAULT 0x00000000 -#define mmGRBM_STATUS_SE3_DEFAULT 0x00000000 -#define mmGRBM_READ_ERROR_DEFAULT 0x00000000 -#define mmGRBM_READ_ERROR2_DEFAULT 0x00000000 -#define mmGRBM_INT_CNTL_DEFAULT 0x00000000 -#define mmGRBM_TRAP_OP_DEFAULT 0x00000000 -#define mmGRBM_TRAP_ADDR_DEFAULT 0x00000000 -#define mmGRBM_TRAP_ADDR_MSK_DEFAULT 0x0003ffff -#define mmGRBM_TRAP_WD_DEFAULT 0x00000000 -#define mmGRBM_TRAP_WD_MSK_DEFAULT 0xffffffff -#define mmGRBM_DSM_BYPASS_DEFAULT 0x00000000 -#define mmGRBM_WRITE_ERROR_DEFAULT 0x00000000 -#define mmGRBM_IOV_ERROR_DEFAULT 0x00000000 -#define mmGRBM_CHIP_REVISION_DEFAULT 0x00000000 -#define mmGRBM_GFX_CNTL_DEFAULT 0x00000000 -#define mmGRBM_RSMU_CFG_DEFAULT 0x00011000 -#define mmGRBM_IH_CREDIT_DEFAULT 0x00010000 -#define mmGRBM_PWR_CNTL2_DEFAULT 0x00010000 -#define mmGRBM_UTCL2_INVAL_RANGE_START_DEFAULT 0x00002891 -#define mmGRBM_UTCL2_INVAL_RANGE_END_DEFAULT 0x000028ea -#define mmGRBM_RSMU_READ_ERROR_DEFAULT 0x00000000 -#define mmGRBM_CHICKEN_BITS_DEFAULT 0x00000000 -#define mmGRBM_NOWHERE_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG0_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG1_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG2_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG3_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG4_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG5_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG6_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG7_DEFAULT 0x00000000 - - -// addressBlock: gc_cpdec -#define mmCP_CPC_STATUS_DEFAULT 0x00000000 -#define mmCP_CPC_BUSY_STAT_DEFAULT 0x00000000 -#define mmCP_CPC_STALLED_STAT1_DEFAULT 0x00000000 -#define mmCP_CPF_STATUS_DEFAULT 0x00000000 -#define mmCP_CPF_BUSY_STAT_DEFAULT 0x00000000 -#define mmCP_CPF_STALLED_STAT1_DEFAULT 0x00000000 -#define mmCP_CPC_GRBM_FREE_COUNT_DEFAULT 0x00000008 -#define mmCP_MEC_CNTL_DEFAULT 0x50000000 -#define mmCP_MEC_ME1_HEADER_DUMP_DEFAULT 0x00000000 -#define mmCP_MEC_ME2_HEADER_DUMP_DEFAULT 0x00000000 -#define mmCP_CPC_SCRATCH_INDEX_DEFAULT 0x00000000 -#define mmCP_CPC_SCRATCH_DATA_DEFAULT 0x00000000 -#define mmCP_CPF_GRBM_FREE_COUNT_DEFAULT 0x00000004 -#define mmCP_CPC_HALT_HYST_COUNT_DEFAULT 0x00000002 -#define mmCP_PRT_LOD_STATS_CNTL0_DEFAULT 0x00000000 -#define mmCP_PRT_LOD_STATS_CNTL1_DEFAULT 0x00000000 -#define mmCP_PRT_LOD_STATS_CNTL2_DEFAULT 0x00000000 -#define mmCP_PRT_LOD_STATS_CNTL3_DEFAULT 0x00000000 -#define mmCP_CE_COMPARE_COUNT_DEFAULT 0x00000000 -#define mmCP_CE_DE_COUNT_DEFAULT 0x00000000 -#define mmCP_DE_CE_COUNT_DEFAULT 0x00000000 -#define mmCP_DE_LAST_INVAL_COUNT_DEFAULT 0x00000000 -#define mmCP_DE_DE_COUNT_DEFAULT 0x00000000 -#define mmCP_STALLED_STAT3_DEFAULT 0x00000000 -#define mmCP_STALLED_STAT1_DEFAULT 0x00000000 -#define mmCP_STALLED_STAT2_DEFAULT 0x00000000 -#define mmCP_BUSY_STAT_DEFAULT 0x00000000 -#define mmCP_STAT_DEFAULT 0x00000000 -#define mmCP_ME_HEADER_DUMP_DEFAULT 0x00000000 -#define mmCP_PFP_HEADER_DUMP_DEFAULT 0x00000000 -#define mmCP_GRBM_FREE_COUNT_DEFAULT 0x00080808 -#define mmCP_CE_HEADER_DUMP_DEFAULT 0x00000000 -#define mmCP_PFP_INSTR_PNTR_DEFAULT 0x00000000 -#define mmCP_ME_INSTR_PNTR_DEFAULT 0x00000000 -#define mmCP_CE_INSTR_PNTR_DEFAULT 0x00000000 -#define mmCP_MEC1_INSTR_PNTR_DEFAULT 0x00000000 -#define mmCP_MEC2_INSTR_PNTR_DEFAULT 0x00000000 -#define mmCP_CSF_STAT_DEFAULT 0x00000000 -#define mmCP_ME_CNTL_DEFAULT 0x15000000 -#define mmCP_CNTX_STAT_DEFAULT 0x00000000 -#define mmCP_ME_PREEMPTION_DEFAULT 0x00000000 -#define mmCP_ROQ_THRESHOLDS_DEFAULT 0x00003010 -#define mmCP_MEQ_STQ_THRESHOLD_DEFAULT 0x00000010 -#define mmCP_RB2_RPTR_DEFAULT 0x00000000 -#define mmCP_RB1_RPTR_DEFAULT 0x00000000 -#define mmCP_RB0_RPTR_DEFAULT 0x00000000 -#define mmCP_RB_RPTR_DEFAULT 0x00000000 -#define mmCP_RB_WPTR_DELAY_DEFAULT 0x00000000 -#define mmCP_RB_WPTR_POLL_CNTL_DEFAULT 0x00400100 -#define mmCP_ROQ1_THRESHOLDS_DEFAULT 0x30101010 -#define mmCP_ROQ2_THRESHOLDS_DEFAULT 0x40403030 -#define mmCP_STQ_THRESHOLDS_DEFAULT 0x00804000 -#define mmCP_QUEUE_THRESHOLDS_DEFAULT 0x00002b16 -#define mmCP_MEQ_THRESHOLDS_DEFAULT 0x00008040 -#define mmCP_ROQ_AVAIL_DEFAULT 0x00000000 -#define mmCP_STQ_AVAIL_DEFAULT 0x00000000 -#define mmCP_ROQ2_AVAIL_DEFAULT 0x00000000 -#define mmCP_MEQ_AVAIL_DEFAULT 0x00000000 -#define mmCP_CMD_INDEX_DEFAULT 0x00000000 -#define mmCP_CMD_DATA_DEFAULT 0x00000000 -#define mmCP_ROQ_RB_STAT_DEFAULT 0x00000000 -#define mmCP_ROQ_IB1_STAT_DEFAULT 0x00000000 -#define mmCP_ROQ_IB2_STAT_DEFAULT 0x00000000 -#define mmCP_STQ_STAT_DEFAULT 0x00000000 -#define mmCP_STQ_WR_STAT_DEFAULT 0x00000000 -#define mmCP_MEQ_STAT_DEFAULT 0x00000000 -#define mmCP_CEQ1_AVAIL_DEFAULT 0x00000000 -#define mmCP_CEQ2_AVAIL_DEFAULT 0x00000000 -#define mmCP_CE_ROQ_RB_STAT_DEFAULT 0x00000000 -#define mmCP_CE_ROQ_IB1_STAT_DEFAULT 0x00000000 -#define mmCP_CE_ROQ_IB2_STAT_DEFAULT 0x00000000 - - -// addressBlock: gc_padec -#define mmVGT_VTX_VECT_EJECT_REG_DEFAULT 0x0000007d -#define mmVGT_DMA_DATA_FIFO_DEPTH_DEFAULT 0x00040180 -#define mmVGT_DMA_REQ_FIFO_DEPTH_DEFAULT 0x00000020 -#define mmVGT_DRAW_INIT_FIFO_DEPTH_DEFAULT 0x00000020 -#define mmVGT_LAST_COPY_STATE_DEFAULT 0x00000000 -#define mmVGT_CACHE_INVALIDATION_DEFAULT 0x09000000 -#define mmVGT_STRMOUT_DELAY_DEFAULT 0x00092410 -#define mmVGT_FIFO_DEPTHS_DEFAULT 0x08000040 -#define mmVGT_GS_VERTEX_REUSE_DEFAULT 0x00000010 -#define mmVGT_MC_LAT_CNTL_DEFAULT 0x000000fe -#define mmIA_CNTL_STATUS_DEFAULT 0x00000000 -#define mmVGT_CNTL_STATUS_DEFAULT 0x00000000 -#define mmWD_CNTL_STATUS_DEFAULT 0x00000000 -#define mmCC_GC_PRIM_CONFIG_DEFAULT 0x0e020000 -#define mmGC_USER_PRIM_CONFIG_DEFAULT 0x00000000 -#define mmWD_QOS_DEFAULT 0x00000000 -#define mmWD_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmWD_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmIA_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmIA_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmVGT_SYS_CONFIG_DEFAULT 0x00000011 -#define mmVGT_VS_MAX_WAVE_ID_DEFAULT 0x0000007f -#define mmVGT_GS_MAX_WAVE_ID_DEFAULT 0x000000ff -#define mmGFX_PIPE_CONTROL_DEFAULT 0x00000000 -#define mmCC_GC_SHADER_ARRAY_CONFIG_DEFAULT 0xf8000000 -#define mmGC_USER_SHADER_ARRAY_CONFIG_DEFAULT 0x00000000 -#define mmVGT_DMA_PRIMITIVE_TYPE_DEFAULT 0x00000000 -#define mmVGT_DMA_CONTROL_DEFAULT 0x000000ff -#define mmVGT_DMA_LS_HS_CONFIG_DEFAULT 0x00000000 -#define mmWD_BUF_RESOURCE_1_DEFAULT 0x00000000 -#define mmWD_BUF_RESOURCE_2_DEFAULT 0x00000000 -#define mmPA_CL_CNTL_STATUS_DEFAULT 0x00000000 -#define mmPA_CL_ENHANCE_DEFAULT 0x00000007 -#define mmPA_SU_CNTL_STATUS_DEFAULT 0x00000000 -#define mmPA_SC_FIFO_DEPTH_CNTL_DEFAULT 0x00000018 -#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000 -#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000 -#define mmPA_SC_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000 -#define mmPA_SC_FORCE_EOV_MAX_CNTS_DEFAULT 0x00ffffff -#define mmPA_SC_BINNER_EVENT_CNTL_0_DEFAULT 0x842a4402 -#define mmPA_SC_BINNER_EVENT_CNTL_1_DEFAULT 0x8a000008 -#define mmPA_SC_BINNER_EVENT_CNTL_2_DEFAULT 0x9118aaa8 -#define mmPA_SC_BINNER_EVENT_CNTL_3_DEFAULT 0x82400025 -#define mmPA_SC_BINNER_TIMEOUT_COUNTER_DEFAULT 0x00000000 -#define mmPA_SC_BINNER_PERF_CNTL_0_DEFAULT 0x00000000 -#define mmPA_SC_BINNER_PERF_CNTL_1_DEFAULT 0x00000000 -#define mmPA_SC_BINNER_PERF_CNTL_2_DEFAULT 0x00000000 -#define mmPA_SC_BINNER_PERF_CNTL_3_DEFAULT 0x00000000 -#define mmPA_SC_FIFO_SIZE_DEFAULT 0x00000000 -#define mmPA_SC_IF_FIFO_SIZE_DEFAULT 0x00000000 -#define mmPA_SC_PKR_WAVE_TABLE_CNTL_DEFAULT 0x00000000 -#define mmPA_UTCL1_CNTL1_DEFAULT 0x00000600 -#define mmPA_UTCL1_CNTL2_DEFAULT 0x00000000 -#define mmPA_SIDEBAND_REQUEST_DELAYS_DEFAULT 0x08000020 -#define mmPA_SC_ENHANCE_DEFAULT 0x00000001 -#define mmPA_SC_ENHANCE_1_DEFAULT 0x00040000 -#define mmPA_SC_DSM_CNTL_DEFAULT 0x00000000 -#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_DEFAULT 0x00000000 - - -// addressBlock: gc_sqdec -#define mmSQ_CONFIG_DEFAULT 0x01180000 -#define mmSQC_CONFIG_DEFAULT 0x010a2000 -#define mmLDS_CONFIG_DEFAULT 0x00000000 -#define mmSQ_RANDOM_WAVE_PRI_DEFAULT 0x0000007f -#define mmSQ_REG_CREDITS_DEFAULT 0x00000820 -#define mmSQ_FIFO_SIZES_DEFAULT 0x00000f01 -#define mmSQ_DSM_CNTL_DEFAULT 0x00000000 -#define mmSQ_DSM_CNTL2_DEFAULT 0x00000000 -#define mmSQ_RUNTIME_CONFIG_DEFAULT 0x00000000 -#define mmSH_MEM_BASES_DEFAULT 0x00000000 -#define mmSH_MEM_CONFIG_DEFAULT 0x00000000 -#define mmCC_GC_SHADER_RATE_CONFIG_DEFAULT 0x00000000 -#define mmGC_USER_SHADER_RATE_CONFIG_DEFAULT 0x00000000 -#define mmSQ_INTERRUPT_AUTO_MASK_DEFAULT 0x00ffffff -#define mmSQ_INTERRUPT_MSG_CTRL_DEFAULT 0x00000000 -#define mmSQ_UTCL1_CNTL1_DEFAULT 0x00000580 -#define mmSQ_UTCL1_CNTL2_DEFAULT 0x00000000 -#define mmSQ_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmSQ_SHADER_TBA_LO_DEFAULT 0x00000000 -#define mmSQ_SHADER_TBA_HI_DEFAULT 0x00000000 -#define mmSQ_SHADER_TMA_LO_DEFAULT 0x00000000 -#define mmSQ_SHADER_TMA_HI_DEFAULT 0x00000000 -#define mmSQC_DSM_CNTL_DEFAULT 0x00000000 -#define mmSQC_DSM_CNTLA_DEFAULT 0x00000000 -#define mmSQC_DSM_CNTLB_DEFAULT 0x00000000 -#define mmSQC_DSM_CNTL2_DEFAULT 0x00000000 -#define mmSQC_DSM_CNTL2A_DEFAULT 0x00000000 -#define mmSQC_DSM_CNTL2B_DEFAULT 0x00000000 -#define mmSQC_EDC_FUE_CNTL_DEFAULT 0x00000000 -#define mmSQC_EDC_CNT2_DEFAULT 0x00000000 -#define mmSQC_EDC_CNT3_DEFAULT 0x00000000 -#define mmSQ_REG_TIMESTAMP_DEFAULT 0x00000000 -#define mmSQ_CMD_TIMESTAMP_DEFAULT 0x00000000 -#define mmSQ_IND_INDEX_DEFAULT 0x00000000 -#define mmSQ_IND_DATA_DEFAULT 0x00000000 -#define mmSQ_CMD_DEFAULT 0x00000000 -#define mmSQ_TIME_HI_DEFAULT 0x00000000 -#define mmSQ_TIME_LO_DEFAULT 0x00000000 -#define mmSQ_DS_0_DEFAULT 0x00000000 -#define mmSQ_DS_1_DEFAULT 0x00000000 -#define mmSQ_EXP_0_DEFAULT 0x00000000 -#define mmSQ_EXP_1_DEFAULT 0x00000000 -#define mmSQ_FLAT_0_DEFAULT 0x00000000 -#define mmSQ_FLAT_1_DEFAULT 0x00000000 -#define mmSQ_GLBL_0_DEFAULT 0x00000000 -#define mmSQ_GLBL_1_DEFAULT 0x00000000 -#define mmSQ_INST_DEFAULT 0x00000000 -#define mmSQ_MIMG_0_DEFAULT 0x00000000 -#define mmSQ_MIMG_1_DEFAULT 0x00000000 -#define mmSQ_MTBUF_0_DEFAULT 0x00000000 -#define mmSQ_MTBUF_1_DEFAULT 0x00000000 -#define mmSQ_MUBUF_0_DEFAULT 0x00000000 -#define mmSQ_MUBUF_1_DEFAULT 0x00000000 -#define mmSQ_SCRATCH_0_DEFAULT 0x00000000 -#define mmSQ_SCRATCH_1_DEFAULT 0x00000000 -#define mmSQ_SMEM_0_DEFAULT 0x00000000 -#define mmSQ_SMEM_1_DEFAULT 0x00000000 -#define mmSQ_SOP1_DEFAULT 0x00000000 -#define mmSQ_SOP2_DEFAULT 0x00000000 -#define mmSQ_SOPC_DEFAULT 0x00000000 -#define mmSQ_SOPK_DEFAULT 0x00000000 -#define mmSQ_SOPP_DEFAULT 0x00000000 -#define mmSQ_VINTRP_DEFAULT 0x00000000 -#define mmSQ_VOP1_DEFAULT 0x00000000 -#define mmSQ_VOP2_DEFAULT 0x00000000 -#define mmSQ_VOP3P_0_DEFAULT 0x00000000 -#define mmSQ_VOP3P_1_DEFAULT 0x00000000 -#define mmSQ_VOP3_0_DEFAULT 0x00000000 -#define mmSQ_VOP3_0_SDST_ENC_DEFAULT 0x00000000 -#define mmSQ_VOP3_1_DEFAULT 0x00000000 -#define mmSQ_VOPC_DEFAULT 0x00000000 -#define mmSQ_VOP_DPP_DEFAULT 0x00000000 -#define mmSQ_VOP_SDWA_DEFAULT 0x00000000 -#define mmSQ_VOP_SDWA_SDST_ENC_DEFAULT 0x00000000 -#define mmSQ_LB_CTR_CTRL_DEFAULT 0x00000000 -#define mmSQ_LB_DATA0_DEFAULT 0x00000000 -#define mmSQ_LB_DATA1_DEFAULT 0x00000000 -#define mmSQ_LB_DATA2_DEFAULT 0x00000000 -#define mmSQ_LB_DATA3_DEFAULT 0x00000000 -#define mmSQ_LB_CTR_SEL_DEFAULT 0x00000000 -#define mmSQ_LB_CTR0_CU_DEFAULT 0xffffffff -#define mmSQ_LB_CTR1_CU_DEFAULT 0xffffffff -#define mmSQ_LB_CTR2_CU_DEFAULT 0xffffffff -#define mmSQ_LB_CTR3_CU_DEFAULT 0xffffffff -#define mmSQC_EDC_CNT_DEFAULT 0x00000000 -#define mmSQ_EDC_SEC_CNT_DEFAULT 0x00000000 -#define mmSQ_EDC_DED_CNT_DEFAULT 0x00000000 -#define mmSQ_EDC_INFO_DEFAULT 0x00000000 -#define mmSQ_EDC_CNT_DEFAULT 0x00000000 -#define mmSQ_EDC_FUE_CNTL_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_CMN_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_EVENT_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_INST_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_ISSUE_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_MISC_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_WAVE_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_WAVE_START_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_DEFAULT 0x00000000 -#define mmSQ_WREXEC_EXEC_HI_DEFAULT 0x00000000 -#define mmSQ_WREXEC_EXEC_LO_DEFAULT 0x00000000 -#define mmSQ_BUF_RSRC_WORD0_DEFAULT 0x00000000 -#define mmSQ_BUF_RSRC_WORD1_DEFAULT 0x00000000 -#define mmSQ_BUF_RSRC_WORD2_DEFAULT 0x00000000 -#define mmSQ_BUF_RSRC_WORD3_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD0_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD1_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD2_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD3_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD4_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD5_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD6_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD7_DEFAULT 0x00000000 -#define mmSQ_IMG_SAMP_WORD0_DEFAULT 0x00000000 -#define mmSQ_IMG_SAMP_WORD1_DEFAULT 0x00000000 -#define mmSQ_IMG_SAMP_WORD2_DEFAULT 0x00000000 -#define mmSQ_IMG_SAMP_WORD3_DEFAULT 0x00000000 -#define mmSQ_FLAT_SCRATCH_WORD0_DEFAULT 0x00000000 -#define mmSQ_FLAT_SCRATCH_WORD1_DEFAULT 0x00000000 -#define mmSQ_M0_GPR_IDX_WORD_DEFAULT 0x00000000 -#define mmSQC_ICACHE_UTCL1_CNTL1_DEFAULT 0x00000480 -#define mmSQC_ICACHE_UTCL1_CNTL2_DEFAULT 0x00000000 -#define mmSQC_DCACHE_UTCL1_CNTL1_DEFAULT 0x00000500 -#define mmSQC_DCACHE_UTCL1_CNTL2_DEFAULT 0x00000000 -#define mmSQC_ICACHE_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmSQC_DCACHE_UTCL1_STATUS_DEFAULT 0x00000000 - - -// addressBlock: gc_shsdec -#define mmSX_DEBUG_1_DEFAULT 0x00000020 -#define mmSPI_PS_MAX_WAVE_ID_DEFAULT 0x020000ff -#define mmSPI_START_PHASE_DEFAULT 0x00000000 -#define mmSPI_GFX_CNTL_DEFAULT 0x00000000 -#define mmSPI_DSM_CNTL_DEFAULT 0x00000000 -#define mmSPI_DSM_CNTL2_DEFAULT 0x00000000 -#define mmSPI_EDC_CNT_DEFAULT 0x00000000 -#define mmSPI_CONFIG_PS_CU_EN_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_CNTL_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_LIMIT_0_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_1_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_2_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_3_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_4_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_5_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_6_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_7_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_8_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_9_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_STATUS_0_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_1_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_2_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_3_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_4_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_5_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_6_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_7_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_8_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_9_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_10_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_11_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_12_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_13_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_14_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_15_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_16_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_17_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_18_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_19_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_20_DEFAULT 0x00000000 -#define mmSPI_LB_CTR_CTRL_DEFAULT 0x00000000 -#define mmSPI_LB_CU_MASK_DEFAULT 0x0000ffff -#define mmSPI_LB_DATA_REG_DEFAULT 0x00000000 -#define mmSPI_PG_ENABLE_STATIC_CU_MASK_DEFAULT 0x0000ffff -#define mmSPI_GDS_CREDITS_DEFAULT 0x00001080 -#define mmSPI_SX_EXPORT_BUFFER_SIZES_DEFAULT 0x08000800 -#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_DEFAULT 0x00200040 -#define mmSPI_CSQ_WF_ACTIVE_STATUS_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_DEFAULT 0x00000000 -#define mmSPI_LB_DATA_WAVES_DEFAULT 0x00000000 -#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_DEFAULT 0x00000000 -#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_DEFAULT 0x00000000 -#define mmSPI_LB_DATA_PERCU_WAVE_CS_DEFAULT 0x00000000 -#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000 -#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000 -#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000 -#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000 -#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000 -#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000 -#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000 -#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000 -#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000 -#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000 - - -// addressBlock: gc_tpdec -#define mmTD_CNTL_DEFAULT 0x00000000 -#define mmTD_STATUS_DEFAULT 0x00000000 -#define mmTD_DSM_CNTL_DEFAULT 0x00000000 -#define mmTD_DSM_CNTL2_DEFAULT 0x00000000 -#define mmTD_SCRATCH_DEFAULT 0x00000000 -#define mmTA_CNTL_DEFAULT 0x8004d850 -#define mmTA_CNTL_AUX_DEFAULT 0x00000000 -#define mmTA_RESERVED_010C_DEFAULT 0x00000000 -#define mmTA_GRAD_ADJ_DEFAULT 0x40000040 -#define mmTA_STATUS_DEFAULT 0x00000000 -#define mmTA_SCRATCH_DEFAULT 0x00000000 - - -// addressBlock: gc_gdsdec -#define mmGDS_CONFIG_DEFAULT 0x00000000 -#define mmGDS_CNTL_STATUS_DEFAULT 0x00000000 -#define mmGDS_ENHANCE2_DEFAULT 0x00000000 -#define mmGDS_PROTECTION_FAULT_DEFAULT 0x00000000 -#define mmGDS_VM_PROTECTION_FAULT_DEFAULT 0x00000000 -#define mmGDS_EDC_CNT_DEFAULT 0x00000000 -#define mmGDS_EDC_GRBM_CNT_DEFAULT 0x00000000 -#define mmGDS_EDC_OA_DED_DEFAULT 0x00000000 -#define mmGDS_DSM_CNTL_DEFAULT 0x00000000 -#define mmGDS_EDC_OA_PHY_CNT_DEFAULT 0x00000000 -#define mmGDS_EDC_OA_PIPE_CNT_DEFAULT 0x00000000 -#define mmGDS_DSM_CNTL2_DEFAULT 0x00000000 -#define mmGDS_WD_GDS_CSB_DEFAULT 0x00000000 - - -// addressBlock: gc_rbdec -#define mmDB_DEBUG_DEFAULT 0x00000000 -#define mmDB_DEBUG2_DEFAULT 0x00000000 -#define mmDB_DEBUG3_DEFAULT 0x00000000 -#define mmDB_DEBUG4_DEFAULT 0x00000000 -#define mmDB_CREDIT_LIMIT_DEFAULT 0x00000000 -#define mmDB_WATERMARKS_DEFAULT 0x01020204 -#define mmDB_SUBTILE_CONTROL_DEFAULT 0x00000000 -#define mmDB_FREE_CACHELINES_DEFAULT 0x00000000 -#define mmDB_FIFO_DEPTH1_DEFAULT 0x00000000 -#define mmDB_FIFO_DEPTH2_DEFAULT 0x00000000 -#define mmDB_EXCEPTION_CONTROL_DEFAULT 0x00000000 -#define mmDB_RING_CONTROL_DEFAULT 0x00000001 -#define mmDB_MEM_ARB_WATERMARKS_DEFAULT 0x04040404 -#define mmDB_RMI_CACHE_POLICY_DEFAULT 0x0f0f0f07 -#define mmDB_DFSM_CONFIG_DEFAULT 0x00007f00 -#define mmDB_DFSM_WATERMARK_DEFAULT 0x00640064 -#define mmDB_DFSM_TILES_IN_FLIGHT_DEFAULT 0x05dc03e8 -#define mmDB_DFSM_PRIMS_IN_FLIGHT_DEFAULT 0x00fa00c8 -#define mmDB_DFSM_WATCHDOG_DEFAULT 0x000f4240 -#define mmDB_DFSM_FLUSH_ENABLE_DEFAULT 0x000003ff -#define mmDB_DFSM_FLUSH_AUX_EVENT_DEFAULT 0x00000000 -#define mmCC_RB_REDUNDANCY_DEFAULT 0x00000000 -#define mmCC_RB_BACKEND_DISABLE_DEFAULT 0x00000000 -#define mmGB_ADDR_CONFIG_DEFAULT 0x26010011 -#define mmGB_BACKEND_MAP_DEFAULT 0x33221100 -#define mmGB_GPU_ID_DEFAULT 0x00000000 -#define mmCC_RB_DAISY_CHAIN_DEFAULT 0x76543210 -#define mmGB_ADDR_CONFIG_READ_DEFAULT 0x26010011 -#define mmGB_TILE_MODE0_DEFAULT 0x00000000 -#define mmGB_TILE_MODE1_DEFAULT 0x00000000 -#define mmGB_TILE_MODE2_DEFAULT 0x00000000 -#define mmGB_TILE_MODE3_DEFAULT 0x00000000 -#define mmGB_TILE_MODE4_DEFAULT 0x00000000 -#define mmGB_TILE_MODE5_DEFAULT 0x00000000 -#define mmGB_TILE_MODE6_DEFAULT 0x00000000 -#define mmGB_TILE_MODE7_DEFAULT 0x00000000 -#define mmGB_TILE_MODE8_DEFAULT 0x00000000 -#define mmGB_TILE_MODE9_DEFAULT 0x00000000 -#define mmGB_TILE_MODE10_DEFAULT 0x00000000 -#define mmGB_TILE_MODE11_DEFAULT 0x00000000 -#define mmGB_TILE_MODE12_DEFAULT 0x00000000 -#define mmGB_TILE_MODE13_DEFAULT 0x00000000 -#define mmGB_TILE_MODE14_DEFAULT 0x00000000 -#define mmGB_TILE_MODE15_DEFAULT 0x00000000 -#define mmGB_TILE_MODE16_DEFAULT 0x00000000 -#define mmGB_TILE_MODE17_DEFAULT 0x00000000 -#define mmGB_TILE_MODE18_DEFAULT 0x00000000 -#define mmGB_TILE_MODE19_DEFAULT 0x00000000 -#define mmGB_TILE_MODE20_DEFAULT 0x00000000 -#define mmGB_TILE_MODE21_DEFAULT 0x00000000 -#define mmGB_TILE_MODE22_DEFAULT 0x00000000 -#define mmGB_TILE_MODE23_DEFAULT 0x00000000 -#define mmGB_TILE_MODE24_DEFAULT 0x00000000 -#define mmGB_TILE_MODE25_DEFAULT 0x00000000 -#define mmGB_TILE_MODE26_DEFAULT 0x00000000 -#define mmGB_TILE_MODE27_DEFAULT 0x00000000 -#define mmGB_TILE_MODE28_DEFAULT 0x00000000 -#define mmGB_TILE_MODE29_DEFAULT 0x00000000 -#define mmGB_TILE_MODE30_DEFAULT 0x00000000 -#define mmGB_TILE_MODE31_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE0_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE1_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE2_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE3_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE4_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE5_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE6_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE7_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE8_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE9_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE10_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE11_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE12_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE13_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE14_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE15_DEFAULT 0x00000000 -#define mmCB_HW_CONTROL_DEFAULT 0x00014107 -#define mmCB_HW_CONTROL_1_DEFAULT 0x10000000 -#define mmCB_HW_CONTROL_2_DEFAULT 0x00000000 -#define mmCB_HW_CONTROL_3_DEFAULT 0x00000000 -#define mmCB_HW_MEM_ARBITER_RD_DEFAULT 0x00029000 -#define mmCB_HW_MEM_ARBITER_WR_DEFAULT 0x00029000 -#define mmCB_DCC_CONFIG_DEFAULT 0x04000000 -#define mmGC_USER_RB_REDUNDANCY_DEFAULT 0x00000000 -#define mmGC_USER_RB_BACKEND_DISABLE_DEFAULT 0x00000000 - - -// addressBlock: gc_ea_gceadec2 -#define mmGCEA_EDC_CNT_DEFAULT 0x00000000 -#define mmGCEA_EDC_CNT2_DEFAULT 0x00000000 -#define mmGCEA_DSM_CNTL_DEFAULT 0x00000000 -#define mmGCEA_DSM_CNTLA_DEFAULT 0x00000000 -#define mmGCEA_DSM_CNTLB_DEFAULT 0x00000000 -#define mmGCEA_DSM_CNTL2_DEFAULT 0x00000000 -#define mmGCEA_DSM_CNTL2A_DEFAULT 0x00000000 -#define mmGCEA_DSM_CNTL2B_DEFAULT 0x00000000 -#define mmGCEA_TCC_XBR_CREDITS_DEFAULT 0x637f637f -#define mmGCEA_TCC_XBR_MAXBURST_DEFAULT 0x00003333 -#define mmGCEA_PROBE_CNTL_DEFAULT 0x00000000 -#define mmGCEA_PROBE_MAP_DEFAULT 0x0000aaaa -#define mmGCEA_ERR_STATUS_DEFAULT 0x00000000 -#define mmGCEA_MISC2_DEFAULT 0x00000000 -#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_DEFAULT 0x00000000 -#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_DEFAULT 0x00000000 -#define mmGCEA_SDP_BACKDOOR_DATACREDITS0_DEFAULT 0x00000000 -#define mmGCEA_SDP_BACKDOOR_DATACREDITS1_DEFAULT 0x00000000 -#define mmGCEA_SDP_BACKDOOR_MISCCREDITS_DEFAULT 0x00000000 -#define mmGCEA_SDP_ENABLE_DEFAULT 0x00000000 - - -// addressBlock: gc_rmi_rmidec -#define mmRMI_GENERAL_CNTL_DEFAULT 0x00000000 -#define mmRMI_GENERAL_CNTL1_DEFAULT 0x00001a03 -#define mmRMI_GENERAL_STATUS_DEFAULT 0x00000000 -#define mmRMI_SUBBLOCK_STATUS0_DEFAULT 0x00000000 -#define mmRMI_SUBBLOCK_STATUS1_DEFAULT 0x00000000 -#define mmRMI_SUBBLOCK_STATUS2_DEFAULT 0x00000000 -#define mmRMI_SUBBLOCK_STATUS3_DEFAULT 0x00000000 -#define mmRMI_XBAR_CONFIG_DEFAULT 0x00000f00 -#define mmRMI_PROBE_POP_LOGIC_CNTL_DEFAULT 0x000300c0 -#define mmRMI_UTC_XNACK_N_MISC_CNTL_DEFAULT 0x00000564 -#define mmRMI_DEMUX_CNTL_DEFAULT 0x02000200 -#define mmRMI_UTCL1_CNTL1_DEFAULT 0x00020000 -#define mmRMI_UTCL1_CNTL2_DEFAULT 0x00010000 -#define mmRMI_UTC_UNIT_CONFIG_DEFAULT 0x00000000 -#define mmRMI_TCIW_FORMATTER0_CNTL_DEFAULT 0x4404001e -#define mmRMI_TCIW_FORMATTER1_CNTL_DEFAULT 0x4404001e -#define mmRMI_SCOREBOARD_CNTL_DEFAULT 0x001ffe00 -#define mmRMI_SCOREBOARD_STATUS0_DEFAULT 0x00000000 -#define mmRMI_SCOREBOARD_STATUS1_DEFAULT 0x00000000 -#define mmRMI_SCOREBOARD_STATUS2_DEFAULT 0x00000000 -#define mmRMI_XBAR_ARBITER_CONFIG_DEFAULT 0x08000800 -#define mmRMI_XBAR_ARBITER_CONFIG_1_DEFAULT 0xffffffff -#define mmRMI_CLOCK_CNTRL_DEFAULT 0x04208822 -#define mmRMI_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmRMI_SPARE_DEFAULT 0x00000001 -#define mmRMI_SPARE_1_DEFAULT 0x00000000 -#define mmRMI_SPARE_2_DEFAULT 0x00000000 - - -// addressBlock: gc_dbgu_gfx_dbgudec -#define mmport_a_addr_DEFAULT 0x00000000 -#define mmport_a_data_lo_DEFAULT 0x00000000 -#define mmport_a_data_hi_DEFAULT 0x00000000 -#define mmport_b_addr_DEFAULT 0x00000000 -#define mmport_b_data_lo_DEFAULT 0x00000000 -#define mmport_b_data_hi_DEFAULT 0x00000000 -#define mmport_c_addr_DEFAULT 0x00000000 -#define mmport_c_data_lo_DEFAULT 0x00000000 -#define mmport_c_data_hi_DEFAULT 0x00000000 -#define mmport_d_addr_DEFAULT 0x00000000 -#define mmport_d_data_lo_DEFAULT 0x00000000 -#define mmport_d_data_hi_DEFAULT 0x00000000 - - -// addressBlock: gc_utcl2_atcl2dec -#define mmATC_L2_CNTL_DEFAULT 0x000001c9 -#define mmATC_L2_CNTL2_DEFAULT 0x00000100 -#define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000 -#define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000 -#define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000 -#define mmATC_L2_CNTL3_DEFAULT 0x000001f8 -#define mmATC_L2_STATUS_DEFAULT 0x00000000 -#define mmATC_L2_STATUS2_DEFAULT 0x00000000 -#define mmATC_L2_MISC_CG_DEFAULT 0x00000200 -#define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 -#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: gc_utcl2_vml2pfdec -#define mmVM_L2_CNTL_DEFAULT 0x00080602 -#define mmVM_L2_CNTL2_DEFAULT 0x00000000 -#define mmVM_L2_CNTL3_DEFAULT 0x80100007 -#define mmVM_L2_STATUS_DEFAULT 0x00000000 -#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc -#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff -#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CNTL4_DEFAULT 0x000000c1 -#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 -#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 -#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 -#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 -#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: gc_utcl2_vml2vcdec -#define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 - - -// addressBlock: gc_utcl2_vmsharedpfdec -#define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000 -#define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 -#define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 -#define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008 -#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 -#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 -#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 -#define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmMC_VM_STEERING_DEFAULT 0x00000001 -#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmMC_MEM_POWER_LS_DEFAULT 0x00000208 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 -#define mmMC_VM_APT_CNTL_DEFAULT 0x00000000 -#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 -#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff -#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 - - -// addressBlock: gc_utcl2_vmsharedvcdec -#define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 -#define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 -#define mmMC_VM_AGP_TOP_DEFAULT 0x00000000 -#define mmMC_VM_AGP_BOT_DEFAULT 0x00000000 -#define mmMC_VM_AGP_BASE_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 - - -// addressBlock: gc_ea_gceadec -#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0xeaaa9580 -#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0xeaaa9580 -#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0xeaaa9580 -#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0xeaaa9580 -#define mmGCEA_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000924 -#define mmGCEA_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000324 -#define mmGCEA_DRAM_RD_LAZY_DEFAULT 0x00000924 -#define mmGCEA_DRAM_WR_LAZY_DEFAULT 0x00000924 -#define mmGCEA_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 -#define mmGCEA_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 -#define mmGCEA_DRAM_PAGE_BURST_DEFAULT 0x20082008 -#define mmGCEA_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmGCEA_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmGCEA_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmGCEA_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmGCEA_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmGCEA_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmGCEA_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmGCEA_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmGCEA_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 -#define mmGCEA_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 -#define mmGCEA_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 -#define mmGCEA_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 -#define mmGCEA_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 -#define mmGCEA_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef -#define mmGCEA_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmGCEA_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmGCEA_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmGCEA_IO_RD_CLI2GRP_MAP0_DEFAULT 0xeaaa9580 -#define mmGCEA_IO_RD_CLI2GRP_MAP1_DEFAULT 0xeaaa9580 -#define mmGCEA_IO_WR_CLI2GRP_MAP0_DEFAULT 0xeaaa9580 -#define mmGCEA_IO_WR_CLI2GRP_MAP1_DEFAULT 0xeaaa9580 -#define mmGCEA_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmGCEA_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmGCEA_IO_GROUP_BURST_DEFAULT 0x1f031f03 -#define mmGCEA_IO_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmGCEA_IO_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmGCEA_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmGCEA_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmGCEA_IO_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmGCEA_IO_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmGCEA_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 -#define mmGCEA_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 -#define mmGCEA_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmGCEA_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmGCEA_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmGCEA_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmGCEA_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmGCEA_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmGCEA_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmGCEA_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmGCEA_SDP_ARB_DRAM_DEFAULT 0x00102040 -#define mmGCEA_SDP_ARB_FINAL_DEFAULT 0x00007fff -#define mmGCEA_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 -#define mmGCEA_SDP_IO_PRIORITY_DEFAULT 0x00000000 -#define mmGCEA_SDP_CREDITS_DEFAULT 0x000100bf -#define mmGCEA_SDP_TAG_RESERVE0_DEFAULT 0x00000000 -#define mmGCEA_SDP_TAG_RESERVE1_DEFAULT 0x00000000 -#define mmGCEA_SDP_VCC_RESERVE0_DEFAULT 0x00000000 -#define mmGCEA_SDP_VCC_RESERVE1_DEFAULT 0x00000000 -#define mmGCEA_SDP_VCD_RESERVE0_DEFAULT 0x00000000 -#define mmGCEA_SDP_VCD_RESERVE1_DEFAULT 0x00000000 -#define mmGCEA_SDP_REQ_CNTL_DEFAULT 0x0000000f -#define mmGCEA_MISC_DEFAULT 0x0de03ff0 -#define mmGCEA_LATENCY_SAMPLING_DEFAULT 0x00000000 -#define mmGCEA_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmGCEA_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmGCEA_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmGCEA_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmGCEA_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - - -// addressBlock: gc_tcdec -#define mmTCP_INVALIDATE_DEFAULT 0x00000000 -#define mmTCP_STATUS_DEFAULT 0x00000000 -#define mmTCP_CNTL_DEFAULT 0x2f9c0000 -#define mmTCP_CHAN_STEER_LO_DEFAULT 0x76543210 -#define mmTCP_CHAN_STEER_HI_DEFAULT 0xfedcba98 -#define mmTCP_ADDR_CONFIG_DEFAULT 0x000000f3 -#define mmTCP_CREDIT_DEFAULT 0x804001c0 -#define mmTCP_BUFFER_ADDR_HASH_CNTL_DEFAULT 0x00000000 -#define mmTCP_EDC_CNT_DEFAULT 0x00000000 -#define mmTC_CFG_L1_LOAD_POLICY0_DEFAULT 0x00000000 -#define mmTC_CFG_L1_LOAD_POLICY1_DEFAULT 0x00000000 -#define mmTC_CFG_L1_STORE_POLICY_DEFAULT 0x00000000 -#define mmTC_CFG_L2_LOAD_POLICY0_DEFAULT 0x00000000 -#define mmTC_CFG_L2_LOAD_POLICY1_DEFAULT 0x00000000 -#define mmTC_CFG_L2_STORE_POLICY0_DEFAULT 0x00000000 -#define mmTC_CFG_L2_STORE_POLICY1_DEFAULT 0x00000000 -#define mmTC_CFG_L2_ATOMIC_POLICY_DEFAULT 0x00000000 -#define mmTC_CFG_L1_VOLATILE_DEFAULT 0x00000000 -#define mmTC_CFG_L2_VOLATILE_DEFAULT 0x00000000 -#define mmTCI_STATUS_DEFAULT 0x00000000 -#define mmTCI_CNTL_1_DEFAULT 0x40080022 -#define mmTCI_CNTL_2_DEFAULT 0x00000041 -#define mmTCC_CTRL_DEFAULT 0xf30fff7f -#define mmTCC_CTRL2_DEFAULT 0x0000000f -#define mmTCC_EDC_CNT_DEFAULT 0x00000000 -#define mmTCC_EDC_CNT2_DEFAULT 0x00000000 -#define mmTCC_REDUNDANCY_DEFAULT 0x00000000 -#define mmTCC_EXE_DISABLE_DEFAULT 0x00000000 -#define mmTCC_DSM_CNTL_DEFAULT 0x00000000 -#define mmTCC_DSM_CNTLA_DEFAULT 0x00000000 -#define mmTCC_DSM_CNTL2_DEFAULT 0x00000000 -#define mmTCC_DSM_CNTL2A_DEFAULT 0x00000000 -#define mmTCC_DSM_CNTL2B_DEFAULT 0x00000000 -#define mmTCC_WBINVL2_DEFAULT 0x00000010 -#define mmTCC_SOFT_RESET_DEFAULT 0x00000000 -#define mmTCA_CTRL_DEFAULT 0x00000088 -#define mmTCA_BURST_MASK_DEFAULT 0xffffffff -#define mmTCA_BURST_CTRL_DEFAULT 0x00000007 -#define mmTCA_DSM_CNTL_DEFAULT 0x00000000 -#define mmTCA_DSM_CNTL2_DEFAULT 0x00000000 -#define mmTCA_EDC_CNT_DEFAULT 0x00000000 - - -// addressBlock: gc_shdec -#define mmSPI_SHADER_PGM_RSRC3_PS_DEFAULT 0x0000ffff -#define mmSPI_SHADER_PGM_LO_PS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_HI_PS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC1_PS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC2_PS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_0_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_1_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_2_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_3_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_4_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_5_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_6_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_7_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_8_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_9_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_10_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_11_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_12_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_13_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_14_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_15_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_16_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_17_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_18_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_19_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_20_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_21_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_22_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_23_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_24_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_25_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_26_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_27_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_28_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_29_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_30_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_31_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC3_VS_DEFAULT 0x0000ffff -#define mmSPI_SHADER_LATE_ALLOC_VS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_LO_VS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_HI_VS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC1_VS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC2_VS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_0_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_1_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_2_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_3_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_4_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_5_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_6_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_7_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_8_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_9_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_10_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_11_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_12_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_13_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_14_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_15_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_16_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_17_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_18_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_19_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_20_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_21_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_22_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_23_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_24_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_25_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_26_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_27_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_28_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_29_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_30_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_31_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC2_GS_VS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC4_GS_DEFAULT 0x00000800 -#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_LO_ES_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_HI_ES_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC3_GS_DEFAULT 0x0000fffe -#define mmSPI_SHADER_PGM_LO_GS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_HI_GS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC1_GS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC2_GS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_0_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_1_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_2_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_3_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_4_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_5_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_6_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_7_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_8_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_9_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_10_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_11_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_12_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_13_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_14_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_15_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_16_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_17_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_18_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_19_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_20_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_21_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_22_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_23_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_24_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_25_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_26_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_27_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_28_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_29_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_30_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_31_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC4_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_LO_LS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_HI_LS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC3_HS_DEFAULT 0xffff0000 -#define mmSPI_SHADER_PGM_LO_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_HI_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC1_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC2_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_0_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_1_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_2_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_3_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_4_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_5_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_6_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_7_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_8_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_9_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_10_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_11_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_12_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_13_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_14_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_15_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_16_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_17_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_18_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_19_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_20_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_21_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_22_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_23_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_24_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_25_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_26_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_27_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_28_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_29_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_30_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_31_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_0_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_1_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_2_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_3_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_4_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_5_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_6_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_7_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_8_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_9_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_10_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_11_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_12_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_13_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_14_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_15_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_16_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_17_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_18_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_19_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_20_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_21_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_22_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_23_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_24_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_25_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_26_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_27_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_28_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_29_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_30_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_31_DEFAULT 0x00000000 -#define mmCOMPUTE_DISPATCH_INITIATOR_DEFAULT 0x00000000 -#define mmCOMPUTE_DIM_X_DEFAULT 0x00000000 -#define mmCOMPUTE_DIM_Y_DEFAULT 0x00000000 -#define mmCOMPUTE_DIM_Z_DEFAULT 0x00000000 -#define mmCOMPUTE_START_X_DEFAULT 0x00000000 -#define mmCOMPUTE_START_Y_DEFAULT 0x00000000 -#define mmCOMPUTE_START_Z_DEFAULT 0x00000000 -#define mmCOMPUTE_NUM_THREAD_X_DEFAULT 0x00000000 -#define mmCOMPUTE_NUM_THREAD_Y_DEFAULT 0x00000000 -#define mmCOMPUTE_NUM_THREAD_Z_DEFAULT 0x00000000 -#define mmCOMPUTE_PIPELINESTAT_ENABLE_DEFAULT 0x00000001 -#define mmCOMPUTE_PERFCOUNT_ENABLE_DEFAULT 0x00000000 -#define mmCOMPUTE_PGM_LO_DEFAULT 0x00000000 -#define mmCOMPUTE_PGM_HI_DEFAULT 0x00000000 -#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_DEFAULT 0x00000000 -#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_DEFAULT 0x00000000 -#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_DEFAULT 0x00000000 -#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_DEFAULT 0x00000000 -#define mmCOMPUTE_PGM_RSRC1_DEFAULT 0x00000000 -#define mmCOMPUTE_PGM_RSRC2_DEFAULT 0x00000000 -#define mmCOMPUTE_VMID_DEFAULT 0x00000000 -#define mmCOMPUTE_RESOURCE_LIMITS_DEFAULT 0x00000000 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_DEFAULT 0xffffffff -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_DEFAULT 0xffffffff -#define mmCOMPUTE_TMPRING_SIZE_DEFAULT 0x00000000 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_DEFAULT 0xffffffff -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_DEFAULT 0xffffffff -#define mmCOMPUTE_RESTART_X_DEFAULT 0x00000000 -#define mmCOMPUTE_RESTART_Y_DEFAULT 0x00000000 -#define mmCOMPUTE_RESTART_Z_DEFAULT 0x00000000 -#define mmCOMPUTE_THREAD_TRACE_ENABLE_DEFAULT 0x00000000 -#define mmCOMPUTE_MISC_RESERVED_DEFAULT 0x00000002 -#define mmCOMPUTE_DISPATCH_ID_DEFAULT 0x00000000 -#define mmCOMPUTE_THREADGROUP_ID_DEFAULT 0x00000000 -#define mmCOMPUTE_RELAUNCH_DEFAULT 0x00000000 -#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_DEFAULT 0x00000000 -#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_0_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_1_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_2_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_3_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_4_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_5_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_6_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_7_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_8_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_9_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_10_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_11_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_12_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_13_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_14_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_15_DEFAULT 0x00000000 -#define mmCOMPUTE_NOWHERE_DEFAULT 0x00000000 - - -// addressBlock: gc_cppdec -#define mmCP_DFY_CNTL_DEFAULT 0x00000000 -#define mmCP_DFY_STAT_DEFAULT 0x00000000 -#define mmCP_DFY_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DFY_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_0_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_1_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_2_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_3_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_4_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_5_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_6_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_7_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_8_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_9_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_10_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_11_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_12_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_13_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_14_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_15_DEFAULT 0x00000000 -#define mmCP_DFY_CMD_DEFAULT 0x00000000 -#define mmCP_EOPQ_WAIT_TIME_DEFAULT 0x0000052c -#define mmCP_CPC_MGCG_SYNC_CNTL_DEFAULT 0x00001020 -#define mmCPC_INT_INFO_DEFAULT 0x00000000 -#define mmCP_VIRT_STATUS_DEFAULT 0x00000000 -#define mmCPC_INT_ADDR_DEFAULT 0x00000000 -#define mmCPC_INT_PASID_DEFAULT 0x00000000 -#define mmCP_GFX_ERROR_DEFAULT 0x00000000 -#define mmCPG_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmCPC_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmCPF_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmCP_AQL_SMM_STATUS_DEFAULT 0x00000000 -#define mmCP_RB0_BASE_DEFAULT 0x00000000 -#define mmCP_RB_BASE_DEFAULT 0x00000000 -#define mmCP_RB0_CNTL_DEFAULT 0x00400000 -#define mmCP_RB_CNTL_DEFAULT 0x00400000 -#define mmCP_RB_RPTR_WR_DEFAULT 0x00000000 -#define mmCP_RB0_RPTR_ADDR_DEFAULT 0x00000000 -#define mmCP_RB_RPTR_ADDR_DEFAULT 0x00000000 -#define mmCP_RB0_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_RB0_BUFSZ_MASK_DEFAULT 0x00000000 -#define mmCP_RB_BUFSZ_MASK_DEFAULT 0x00000000 -#define mmCP_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmGC_PRIV_MODE_DEFAULT 0x00000000 -#define mmCP_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_DEVICE_ID_DEFAULT 0x00000000 -#define mmCP_ME0_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 -#define mmCP_RING_PRIORITY_CNTS_DEFAULT 0x08081020 -#define mmCP_ME0_PIPE0_PRIORITY_DEFAULT 0x00000002 -#define mmCP_RING0_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME0_PIPE1_PRIORITY_DEFAULT 0x00000002 -#define mmCP_RING1_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME0_PIPE2_PRIORITY_DEFAULT 0x00000002 -#define mmCP_RING2_PRIORITY_DEFAULT 0x00000002 -#define mmCP_FATAL_ERROR_DEFAULT 0x00000000 -#define mmCP_RB_VMID_DEFAULT 0x00000000 -#define mmCP_ME0_PIPE0_VMID_DEFAULT 0x00000000 -#define mmCP_ME0_PIPE1_VMID_DEFAULT 0x00000000 -#define mmCP_RB0_WPTR_DEFAULT 0x00000000 -#define mmCP_RB_WPTR_DEFAULT 0x00000000 -#define mmCP_RB0_WPTR_HI_DEFAULT 0x00000000 -#define mmCP_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmCP_RB1_WPTR_DEFAULT 0x00000000 -#define mmCP_RB1_WPTR_HI_DEFAULT 0x00000000 -#define mmCP_RB2_WPTR_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_RANGE_LOWER_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_RANGE_UPPER_DEFAULT 0x00000044 -#define mmCP_MEC_DOORBELL_RANGE_LOWER_DEFAULT 0x00000048 -#define mmCP_MEC_DOORBELL_RANGE_UPPER_DEFAULT 0x0ffffffc -#define mmCPG_UTCL1_ERROR_DEFAULT 0x00000000 -#define mmCPC_UTCL1_ERROR_DEFAULT 0x00000000 -#define mmCP_RB1_BASE_DEFAULT 0x00000000 -#define mmCP_RB1_CNTL_DEFAULT 0x00400000 -#define mmCP_RB1_RPTR_ADDR_DEFAULT 0x00000000 -#define mmCP_RB1_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_RB2_BASE_DEFAULT 0x00000000 -#define mmCP_RB2_CNTL_DEFAULT 0x00400000 -#define mmCP_RB2_RPTR_ADDR_DEFAULT 0x00000000 -#define mmCP_RB2_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_RB0_ACTIVE_DEFAULT 0x00000001 -#define mmCP_RB_ACTIVE_DEFAULT 0x00000001 -#define mmCP_INT_CNTL_RING0_DEFAULT 0x00000000 -#define mmCP_INT_CNTL_RING1_DEFAULT 0x00000000 -#define mmCP_INT_CNTL_RING2_DEFAULT 0x00000000 -#define mmCP_INT_STATUS_RING0_DEFAULT 0x00000000 -#define mmCP_INT_STATUS_RING1_DEFAULT 0x00000000 -#define mmCP_INT_STATUS_RING2_DEFAULT 0x00000000 -#define mmCP_PWR_CNTL_DEFAULT 0x00000000 -#define mmCP_MEM_SLP_CNTL_DEFAULT 0x00020200 -#define mmCP_ECC_FIRSTOCCURRENCE_DEFAULT 0x00000000 -#define mmCP_ECC_FIRSTOCCURRENCE_RING0_DEFAULT 0x00000000 -#define mmCP_ECC_FIRSTOCCURRENCE_RING1_DEFAULT 0x00000000 -#define mmCP_ECC_FIRSTOCCURRENCE_RING2_DEFAULT 0x00000000 -#define mmGB_EDC_MODE_DEFAULT 0x00000000 -#define mmCP_PQ_WPTR_POLL_CNTL_DEFAULT 0x00000001 -#define mmCP_PQ_WPTR_POLL_CNTL1_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE0_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE1_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE2_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE3_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE0_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE1_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE2_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE3_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE0_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE1_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE2_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE3_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE0_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE1_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE2_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE3_INT_STATUS_DEFAULT 0x00000000 -#define mmCC_GC_EDC_CONFIG_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 -#define mmCP_ME1_PIPE0_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME1_PIPE1_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME1_PIPE2_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME1_PIPE3_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME2_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 -#define mmCP_ME2_PIPE0_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME2_PIPE1_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME2_PIPE2_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME2_PIPE3_PRIORITY_DEFAULT 0x00000002 -#define mmCP_CE_PRGRM_CNTR_START_DEFAULT 0x00000000 -#define mmCP_PFP_PRGRM_CNTR_START_DEFAULT 0x00000000 -#define mmCP_ME_PRGRM_CNTR_START_DEFAULT 0x00000000 -#define mmCP_MEC1_PRGRM_CNTR_START_DEFAULT 0x00000000 -#define mmCP_MEC2_PRGRM_CNTR_START_DEFAULT 0x00000000 -#define mmCP_CE_INTR_ROUTINE_START_DEFAULT 0x00000002 -#define mmCP_PFP_INTR_ROUTINE_START_DEFAULT 0x00000002 -#define mmCP_ME_INTR_ROUTINE_START_DEFAULT 0x00000002 -#define mmCP_MEC1_INTR_ROUTINE_START_DEFAULT 0x00000002 -#define mmCP_MEC2_INTR_ROUTINE_START_DEFAULT 0x00000002 -#define mmCP_CONTEXT_CNTL_DEFAULT 0x00750075 -#define mmCP_MAX_CONTEXT_DEFAULT 0x00000007 -#define mmCP_IQ_WAIT_TIME1_DEFAULT 0x40404040 -#define mmCP_IQ_WAIT_TIME2_DEFAULT 0x40404040 -#define mmCP_RB0_BASE_HI_DEFAULT 0x00000000 -#define mmCP_RB1_BASE_HI_DEFAULT 0x00000000 -#define mmCP_VMID_RESET_DEFAULT 0x00000000 -#define mmCPC_INT_CNTL_DEFAULT 0x00000000 -#define mmCPC_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_VMID_PREEMPT_DEFAULT 0x00000000 -#define mmCPC_INT_CNTX_ID_DEFAULT 0x00000000 -#define mmCP_PQ_STATUS_DEFAULT 0x00000000 -#define mmCP_CPC_IC_BASE_LO_DEFAULT 0x00000000 -#define mmCP_CPC_IC_BASE_HI_DEFAULT 0x00000000 -#define mmCP_CPC_IC_BASE_CNTL_DEFAULT 0x00000000 -#define mmCP_CPC_IC_OP_CNTL_DEFAULT 0x00000000 -#define mmCP_MEC1_F32_INT_DIS_DEFAULT 0x00000000 -#define mmCP_MEC2_F32_INT_DIS_DEFAULT 0x00000000 -#define mmCP_VMID_STATUS_DEFAULT 0x00000000 - - -// addressBlock: gc_cppdec2 -#define mmCP_RB_DOORBELL_CONTROL_SCH_0_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_1_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_2_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_3_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_4_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_5_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_6_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_7_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CLEAR_DEFAULT 0x00000000 -#define mmCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 -#define mmCP_GFX_MQD_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_GFX_MQD_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_RB_STATUS_DEFAULT 0x00000000 -#define mmCPG_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmCPC_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmCPF_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmCP_SD_CNTL_DEFAULT 0x0000001f -#define mmCP_SOFT_RESET_CNTL_DEFAULT 0x00000000 -#define mmCP_CPC_GFX_CNTL_DEFAULT 0x00000000 - - -// addressBlock: gc_spipdec -#define mmSPI_ARB_PRIORITY_DEFAULT 0x00000000 -#define mmSPI_ARB_CYCLES_0_DEFAULT 0x00000000 -#define mmSPI_ARB_CYCLES_1_DEFAULT 0x00000000 -#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff -#define mmSPI_WCL_PIPE_PERCENT_HP3D_DEFAULT 0x07c1f07f -#define mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS1_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS2_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS3_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS4_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f -#define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_2_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_3_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_4_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_5_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_6_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_7_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_8_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_9_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_0_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_1_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_2_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_3_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_4_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_5_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_6_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_7_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_8_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_9_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_10_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_11_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_10_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_11_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_12_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_13_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_14_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_15_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_12_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_13_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_14_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_15_DEFAULT 0x00000000 -#define mmSPI_COMPUTE_WF_CTX_SAVE_DEFAULT 0x00000000 -#define mmSPI_ARB_CNTL_0_DEFAULT 0x00000000 - - -// addressBlock: gc_cpphqddec -#define mmCP_HQD_GFX_CONTROL_DEFAULT 0x00000000 -#define mmCP_HQD_GFX_STATUS_DEFAULT 0x00000000 -#define mmCP_HPD_ROQ_OFFSETS_DEFAULT 0x00200604 -#define mmCP_HPD_STATUS0_DEFAULT 0x01000000 -#define mmCP_HPD_UTCL1_CNTL_DEFAULT 0x00000000 -#define mmCP_HPD_UTCL1_ERROR_DEFAULT 0x00000000 -#define mmCP_HPD_UTCL1_ERROR_ADDR_DEFAULT 0x00000000 -#define mmCP_MQD_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_MQD_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_HQD_ACTIVE_DEFAULT 0x00000000 -#define mmCP_HQD_VMID_DEFAULT 0x00000000 -#define mmCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05301 -#define mmCP_HQD_PIPE_PRIORITY_DEFAULT 0x00000000 -#define mmCP_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 -#define mmCP_HQD_QUANTUM_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_BASE_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_BASE_HI_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_RPTR_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_WPTR_POLL_ADDR_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 -#define mmCP_HQD_IB_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_HQD_IB_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_HQD_IB_RPTR_DEFAULT 0x00000000 -#define mmCP_HQD_IB_CONTROL_DEFAULT 0x00300000 -#define mmCP_HQD_IQ_TIMER_DEFAULT 0x00000000 -#define mmCP_HQD_IQ_RPTR_DEFAULT 0x00000000 -#define mmCP_HQD_DEQUEUE_REQUEST_DEFAULT 0x00000000 -#define mmCP_HQD_DMA_OFFLOAD_DEFAULT 0x00000000 -#define mmCP_HQD_OFFLOAD_DEFAULT 0x00000000 -#define mmCP_HQD_SEMA_CMD_DEFAULT 0x00000000 -#define mmCP_HQD_MSG_TYPE_DEFAULT 0x00000000 -#define mmCP_HQD_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_HQD_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_HQD_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_HQD_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_HQD_HQ_SCHEDULER0_DEFAULT 0x00000000 -#define mmCP_HQD_HQ_STATUS0_DEFAULT 0x40000000 -#define mmCP_HQD_HQ_CONTROL0_DEFAULT 0x00000000 -#define mmCP_HQD_HQ_SCHEDULER1_DEFAULT 0x00000000 -#define mmCP_MQD_CONTROL_DEFAULT 0x00000100 -#define mmCP_HQD_HQ_STATUS1_DEFAULT 0x00000000 -#define mmCP_HQD_HQ_CONTROL1_DEFAULT 0x00000000 -#define mmCP_HQD_EOP_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_HQD_EOP_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 -#define mmCP_HQD_EOP_RPTR_DEFAULT 0x40000000 -#define mmCP_HQD_EOP_WPTR_DEFAULT 0x007f8000 -#define mmCP_HQD_EOP_EVENTS_DEFAULT 0x00000000 -#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_HQD_CTX_SAVE_CONTROL_DEFAULT 0x00000000 -#define mmCP_HQD_CNTL_STACK_OFFSET_DEFAULT 0x00000000 -#define mmCP_HQD_CNTL_STACK_SIZE_DEFAULT 0x00000000 -#define mmCP_HQD_WG_STATE_OFFSET_DEFAULT 0x00000000 -#define mmCP_HQD_CTX_SAVE_SIZE_DEFAULT 0x00000000 -#define mmCP_HQD_GDS_RESOURCE_STATE_DEFAULT 0x00000000 -#define mmCP_HQD_ERROR_DEFAULT 0x00000000 -#define mmCP_HQD_EOP_WPTR_MEM_DEFAULT 0x00000000 -#define mmCP_HQD_AQL_CONTROL_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_WPTR_LO_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_WPTR_HI_DEFAULT 0x00000000 - - -// addressBlock: gc_didtdec -#define mmDIDT_IND_INDEX_DEFAULT 0x00000000 -#define mmDIDT_IND_DATA_DEFAULT 0x00000000 - - -// addressBlock: gc_gccacdec -#define mmGC_CAC_CTRL_1_DEFAULT 0x01000000 -#define mmGC_CAC_CTRL_2_DEFAULT 0x00000000 -#define mmGC_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmGC_CAC_AGGR_LOWER_DEFAULT 0x00000000 -#define mmGC_CAC_AGGR_UPPER_DEFAULT 0x00000000 -#define mmGC_CAC_PG_AGGR_LOWER_DEFAULT 0x00000000 -#define mmGC_CAC_PG_AGGR_UPPER_DEFAULT 0x00000000 -#define mmGC_CAC_SOFT_CTRL_DEFAULT 0x00000000 -#define mmGC_DIDT_CTRL0_DEFAULT 0x00000000 -#define mmGC_DIDT_CTRL1_DEFAULT 0xffff0000 -#define mmGC_DIDT_CTRL2_DEFAULT 0x1880000f -#define mmGC_DIDT_WEIGHT_DEFAULT 0x00000000 -#define mmGC_EDC_CTRL_DEFAULT 0x00000000 -#define mmGC_EDC_THRESHOLD_DEFAULT 0x00000000 -#define mmGC_EDC_STATUS_DEFAULT 0x00000000 -#define mmGC_EDC_OVERFLOW_DEFAULT 0x00000000 -#define mmGC_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 -#define mmGC_DIDT_DROOP_CTRL_DEFAULT 0x00000000 -#define mmGC_EDC_DROOP_CTRL_DEFAULT 0x00100000 -#define mmGC_CAC_IND_INDEX_DEFAULT 0x00000000 -#define mmGC_CAC_IND_DATA_DEFAULT 0x00000000 -#define mmSE_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmSE_CAC_IND_INDEX_DEFAULT 0x00000000 -#define mmSE_CAC_IND_DATA_DEFAULT 0x00000000 - - -// addressBlock: gc_tcpdec -#define mmTCP_WATCH0_ADDR_H_DEFAULT 0x00000000 -#define mmTCP_WATCH0_ADDR_L_DEFAULT 0x00000000 -#define mmTCP_WATCH0_CNTL_DEFAULT 0x00000000 -#define mmTCP_WATCH1_ADDR_H_DEFAULT 0x00000000 -#define mmTCP_WATCH1_ADDR_L_DEFAULT 0x00000000 -#define mmTCP_WATCH1_CNTL_DEFAULT 0x00000000 -#define mmTCP_WATCH2_ADDR_H_DEFAULT 0x00000000 -#define mmTCP_WATCH2_ADDR_L_DEFAULT 0x00000000 -#define mmTCP_WATCH2_CNTL_DEFAULT 0x00000000 -#define mmTCP_WATCH3_ADDR_H_DEFAULT 0x00000000 -#define mmTCP_WATCH3_ADDR_L_DEFAULT 0x00000000 -#define mmTCP_WATCH3_CNTL_DEFAULT 0x00000000 -#define mmTCP_GATCL1_CNTL_DEFAULT 0x00000000 -#define mmTCP_ATC_EDC_GATCL1_CNT_DEFAULT 0x00000000 -#define mmTCP_GATCL1_DSM_CNTL_DEFAULT 0x00000000 -#define mmTCP_CNTL2_DEFAULT 0x0000000a -#define mmTCP_UTCL1_CNTL1_DEFAULT 0x00800400 -#define mmTCP_UTCL1_CNTL2_DEFAULT 0x00000000 -#define mmTCP_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER_FILTER_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER_FILTER_EN_DEFAULT 0x00000000 - - -// addressBlock: gc_gdspdec -#define mmGDS_VMID0_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID0_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID1_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID1_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID2_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID2_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID3_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID3_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID4_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID4_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID5_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID5_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID6_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID6_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID7_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID7_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID8_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID8_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID9_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID9_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID10_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID10_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID11_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID11_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID12_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID12_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID13_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID13_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID14_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID14_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID15_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID15_SIZE_DEFAULT 0x00010000 -#define mmGDS_GWS_VMID0_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID1_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID2_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID3_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID4_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID5_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID6_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID7_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID8_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID9_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID10_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID11_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID12_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID13_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID14_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID15_DEFAULT 0x00400000 -#define mmGDS_OA_VMID0_DEFAULT 0x00000000 -#define mmGDS_OA_VMID1_DEFAULT 0x00000000 -#define mmGDS_OA_VMID2_DEFAULT 0x00000000 -#define mmGDS_OA_VMID3_DEFAULT 0x00000000 -#define mmGDS_OA_VMID4_DEFAULT 0x00000000 -#define mmGDS_OA_VMID5_DEFAULT 0x00000000 -#define mmGDS_OA_VMID6_DEFAULT 0x00000000 -#define mmGDS_OA_VMID7_DEFAULT 0x00000000 -#define mmGDS_OA_VMID8_DEFAULT 0x00000000 -#define mmGDS_OA_VMID9_DEFAULT 0x00000000 -#define mmGDS_OA_VMID10_DEFAULT 0x00000000 -#define mmGDS_OA_VMID11_DEFAULT 0x00000000 -#define mmGDS_OA_VMID12_DEFAULT 0x00000000 -#define mmGDS_OA_VMID13_DEFAULT 0x00000000 -#define mmGDS_OA_VMID14_DEFAULT 0x00000000 -#define mmGDS_OA_VMID15_DEFAULT 0x00000000 -#define mmGDS_GWS_RESET0_DEFAULT 0x00000000 -#define mmGDS_GWS_RESET1_DEFAULT 0x00000000 -#define mmGDS_GWS_RESOURCE_RESET_DEFAULT 0x00000000 -#define mmGDS_COMPUTE_MAX_WAVE_ID_DEFAULT 0x0000015f -#define mmGDS_OA_RESET_MASK_DEFAULT 0x00000000 -#define mmGDS_OA_RESET_DEFAULT 0x00000000 -#define mmGDS_ENHANCE_DEFAULT 0x00000000 -#define mmGDS_OA_CGPG_RESTORE_DEFAULT 0x00000000 -#define mmGDS_CS_CTXSW_STATUS_DEFAULT 0x00000000 -#define mmGDS_CS_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_CS_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_CS_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_CS_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_GFX_CTXSW_STATUS_DEFAULT 0x00000000 -#define mmGDS_VS_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_VS_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_VS_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_VS_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS0_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS0_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS0_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS0_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS1_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS1_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS1_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS1_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS2_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS2_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS2_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS2_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS3_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS3_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS3_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS3_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS4_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS4_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS4_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS4_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS5_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS5_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS5_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS5_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS6_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS6_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS6_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS6_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS7_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS7_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS7_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS7_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_GS_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_GS_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_GS_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_GS_CTXSW_CNT3_DEFAULT 0x00000000 - - -// addressBlock: gc_rasdec -#define mmRAS_SIGNATURE_CONTROL_DEFAULT 0x00000000 -#define mmRAS_SIGNATURE_MASK_DEFAULT 0x00000000 -#define mmRAS_SX_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_SX_SIGNATURE1_DEFAULT 0x00000000 -#define mmRAS_SX_SIGNATURE2_DEFAULT 0x00000000 -#define mmRAS_SX_SIGNATURE3_DEFAULT 0x00000000 -#define mmRAS_DB_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_PA_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_VGT_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_SQ_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE1_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE2_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE3_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE4_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE5_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE6_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE7_DEFAULT 0x00000000 -#define mmRAS_IA_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_IA_SIGNATURE1_DEFAULT 0x00000000 -#define mmRAS_SPI_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_SPI_SIGNATURE1_DEFAULT 0x00000000 -#define mmRAS_TA_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_TD_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_CB_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_BCI_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_BCI_SIGNATURE1_DEFAULT 0x00000000 -#define mmRAS_TA_SIGNATURE1_DEFAULT 0x00000000 - - -// addressBlock: gc_gfxdec0 -#define mmDB_RENDER_CONTROL_DEFAULT 0x00000000 -#define mmDB_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmDB_DEPTH_VIEW_DEFAULT 0x00000000 -#define mmDB_RENDER_OVERRIDE_DEFAULT 0x00000000 -#define mmDB_RENDER_OVERRIDE2_DEFAULT 0x00000000 -#define mmDB_HTILE_DATA_BASE_DEFAULT 0x00000000 -#define mmDB_HTILE_DATA_BASE_HI_DEFAULT 0x00000000 -#define mmDB_DEPTH_SIZE_DEFAULT 0x00000000 -#define mmDB_DEPTH_BOUNDS_MIN_DEFAULT 0x00000000 -#define mmDB_DEPTH_BOUNDS_MAX_DEFAULT 0x00000000 -#define mmDB_STENCIL_CLEAR_DEFAULT 0x00000000 -#define mmDB_DEPTH_CLEAR_DEFAULT 0x00000000 -#define mmPA_SC_SCREEN_SCISSOR_TL_DEFAULT 0x00000000 -#define mmPA_SC_SCREEN_SCISSOR_BR_DEFAULT 0x00000000 -#define mmDB_Z_INFO_DEFAULT 0x00000000 -#define mmDB_STENCIL_INFO_DEFAULT 0x00000000 -#define mmDB_Z_READ_BASE_DEFAULT 0x00000000 -#define mmDB_Z_READ_BASE_HI_DEFAULT 0x00000000 -#define mmDB_STENCIL_READ_BASE_DEFAULT 0x00000000 -#define mmDB_STENCIL_READ_BASE_HI_DEFAULT 0x00000000 -#define mmDB_Z_WRITE_BASE_DEFAULT 0x00000000 -#define mmDB_Z_WRITE_BASE_HI_DEFAULT 0x00000000 -#define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000 -#define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000 -#define mmDB_DFSM_CONTROL_DEFAULT 0x00000000 -#define mmDB_RENDER_FILTER_DEFAULT 0x00000000 -#define mmDB_Z_INFO2_DEFAULT 0x00000000 -#define mmDB_STENCIL_INFO2_DEFAULT 0x00000000 -#define mmTA_BC_BASE_ADDR_DEFAULT 0x00000000 -#define mmTA_BC_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_HI_0_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_HI_1_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_HI_2_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_HI_3_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_2_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_3_DEFAULT 0x00000000 -#define mmPA_SC_WINDOW_OFFSET_DEFAULT 0x00000000 -#define mmPA_SC_WINDOW_SCISSOR_TL_DEFAULT 0x00000000 -#define mmPA_SC_WINDOW_SCISSOR_BR_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_RULE_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_0_TL_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_0_BR_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_1_TL_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_1_BR_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_2_TL_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_2_BR_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_3_TL_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_3_BR_DEFAULT 0x00000000 -#define mmPA_SC_EDGERULE_DEFAULT 0x00000000 -#define mmPA_SU_HARDWARE_SCREEN_OFFSET_DEFAULT 0x00000000 -#define mmCB_TARGET_MASK_DEFAULT 0x00000000 -#define mmCB_SHADER_MASK_DEFAULT 0x00000000 -#define mmPA_SC_GENERIC_SCISSOR_TL_DEFAULT 0x00000000 -#define mmPA_SC_GENERIC_SCISSOR_BR_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_0_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_1_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_0_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_0_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_1_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_1_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_2_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_2_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_3_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_3_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_4_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_4_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_5_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_5_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_6_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_6_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_7_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_7_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_8_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_8_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_9_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_9_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_10_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_10_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_11_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_11_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_12_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_12_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_13_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_13_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_14_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_14_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_15_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_15_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_0_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_0_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_1_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_1_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_2_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_2_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_3_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_3_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_4_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_4_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_5_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_5_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_6_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_6_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_7_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_7_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_8_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_8_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_9_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_9_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_10_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_10_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_11_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_11_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_12_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_12_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_13_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_13_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_14_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_14_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_15_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_15_DEFAULT 0x00000000 -#define mmPA_SC_RASTER_CONFIG_DEFAULT 0x00000000 -#define mmPA_SC_RASTER_CONFIG_1_DEFAULT 0x00000000 -#define mmPA_SC_SCREEN_EXTENT_CONTROL_DEFAULT 0x00000000 -#define mmPA_SC_TILE_STEERING_OVERRIDE_DEFAULT 0x00000000 -#define mmCP_PERFMON_CNTX_CNTL_DEFAULT 0x00000000 -#define mmCP_PIPEID_DEFAULT 0x00000000 -#define mmCP_RINGID_DEFAULT 0x00000000 -#define mmCP_VMID_DEFAULT 0x00000000 -#define mmPA_SC_RIGHT_VERT_GRID_DEFAULT 0x00000000 -#define mmPA_SC_LEFT_VERT_GRID_DEFAULT 0x00000000 -#define mmPA_SC_HORIZ_GRID_DEFAULT 0x00000000 -#define mmPA_SC_FOV_WINDOW_LR_DEFAULT 0x00000000 -#define mmPA_SC_FOV_WINDOW_TB_DEFAULT 0x00000000 -#define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000 -#define mmCB_BLEND_RED_DEFAULT 0x00000000 -#define mmCB_BLEND_GREEN_DEFAULT 0x00000000 -#define mmCB_BLEND_BLUE_DEFAULT 0x00000000 -#define mmCB_BLEND_ALPHA_DEFAULT 0x00000000 -#define mmCB_DCC_CONTROL_DEFAULT 0x00000000 -#define mmDB_STENCIL_CONTROL_DEFAULT 0x00000000 -#define mmDB_STENCILREFMASK_DEFAULT 0x00000000 -#define mmDB_STENCILREFMASK_BF_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_1_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_1_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_1_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_1_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_1_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_1_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_2_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_2_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_2_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_2_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_2_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_2_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_3_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_3_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_3_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_3_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_3_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_3_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_4_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_4_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_4_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_4_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_4_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_4_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_5_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_5_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_5_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_5_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_5_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_5_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_6_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_6_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_6_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_6_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_6_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_6_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_7_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_7_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_7_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_7_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_7_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_7_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_8_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_8_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_8_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_8_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_8_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_8_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_9_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_9_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_9_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_9_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_9_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_9_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_10_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_10_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_10_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_10_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_10_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_10_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_11_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_11_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_11_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_11_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_11_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_11_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_12_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_12_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_12_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_12_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_12_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_12_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_13_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_13_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_13_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_13_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_13_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_13_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_14_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_14_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_14_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_14_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_14_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_14_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_15_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_15_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_15_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_15_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_15_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_15_DEFAULT 0x00000000 -#define mmPA_CL_UCP_0_X_DEFAULT 0x00000000 -#define mmPA_CL_UCP_0_Y_DEFAULT 0x00000000 -#define mmPA_CL_UCP_0_Z_DEFAULT 0x00000000 -#define mmPA_CL_UCP_0_W_DEFAULT 0x00000000 -#define mmPA_CL_UCP_1_X_DEFAULT 0x00000000 -#define mmPA_CL_UCP_1_Y_DEFAULT 0x00000000 -#define mmPA_CL_UCP_1_Z_DEFAULT 0x00000000 -#define mmPA_CL_UCP_1_W_DEFAULT 0x00000000 -#define mmPA_CL_UCP_2_X_DEFAULT 0x00000000 -#define mmPA_CL_UCP_2_Y_DEFAULT 0x00000000 -#define mmPA_CL_UCP_2_Z_DEFAULT 0x00000000 -#define mmPA_CL_UCP_2_W_DEFAULT 0x00000000 -#define mmPA_CL_UCP_3_X_DEFAULT 0x00000000 -#define mmPA_CL_UCP_3_Y_DEFAULT 0x00000000 -#define mmPA_CL_UCP_3_Z_DEFAULT 0x00000000 -#define mmPA_CL_UCP_3_W_DEFAULT 0x00000000 -#define mmPA_CL_UCP_4_X_DEFAULT 0x00000000 -#define mmPA_CL_UCP_4_Y_DEFAULT 0x00000000 -#define mmPA_CL_UCP_4_Z_DEFAULT 0x00000000 -#define mmPA_CL_UCP_4_W_DEFAULT 0x00000000 -#define mmPA_CL_UCP_5_X_DEFAULT 0x00000000 -#define mmPA_CL_UCP_5_Y_DEFAULT 0x00000000 -#define mmPA_CL_UCP_5_Z_DEFAULT 0x00000000 -#define mmPA_CL_UCP_5_W_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_0_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_1_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_2_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_3_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_4_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_5_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_6_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_7_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_8_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_9_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_10_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_11_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_12_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_13_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_14_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_15_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_16_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_17_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_18_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_19_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_20_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_21_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_22_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_23_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_24_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_25_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_26_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_27_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_28_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_29_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_30_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_31_DEFAULT 0x00000000 -#define mmSPI_VS_OUT_CONFIG_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_ENA_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_ADDR_DEFAULT 0x00000000 -#define mmSPI_INTERP_CONTROL_0_DEFAULT 0x00000000 -#define mmSPI_PS_IN_CONTROL_DEFAULT 0x00000000 -#define mmSPI_BARYC_CNTL_DEFAULT 0x00000000 -#define mmSPI_TMPRING_SIZE_DEFAULT 0x00000000 -#define mmSPI_SHADER_POS_FORMAT_DEFAULT 0x00000000 -#define mmSPI_SHADER_Z_FORMAT_DEFAULT 0x00000000 -#define mmSPI_SHADER_COL_FORMAT_DEFAULT 0x00000000 -#define mmSX_PS_DOWNCONVERT_DEFAULT 0x00000000 -#define mmSX_BLEND_OPT_EPSILON_DEFAULT 0x00000000 -#define mmSX_BLEND_OPT_CONTROL_DEFAULT 0x00000000 -#define mmSX_MRT0_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT1_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT2_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT3_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT4_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT5_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT6_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT7_BLEND_OPT_DEFAULT 0x00000000 -#define mmCB_BLEND0_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND1_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND2_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND3_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND4_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND5_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND6_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND7_CONTROL_DEFAULT 0x00000000 -#define mmCB_MRT0_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT1_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT2_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT3_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT4_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT5_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT6_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT7_EPITCH_DEFAULT 0x00000000 -#define mmCS_COPY_STATE_DEFAULT 0x00000000 -#define mmGFX_COPY_STATE_DEFAULT 0x00000000 -#define mmPA_CL_POINT_X_RAD_DEFAULT 0x00000000 -#define mmPA_CL_POINT_Y_RAD_DEFAULT 0x00000000 -#define mmPA_CL_POINT_SIZE_DEFAULT 0x00000000 -#define mmPA_CL_POINT_CULL_RAD_DEFAULT 0x00000000 -#define mmVGT_DMA_BASE_HI_DEFAULT 0x00000000 -#define mmVGT_DMA_BASE_DEFAULT 0x00000000 -#define mmVGT_DRAW_INITIATOR_DEFAULT 0x00000000 -#define mmVGT_IMMED_DATA_DEFAULT 0x00000000 -#define mmVGT_EVENT_ADDRESS_REG_DEFAULT 0x00000000 -#define mmDB_DEPTH_CONTROL_DEFAULT 0x00000000 -#define mmDB_EQAA_DEFAULT 0x00000000 -#define mmCB_COLOR_CONTROL_DEFAULT 0x00000000 -#define mmDB_SHADER_CONTROL_DEFAULT 0x00000000 -#define mmPA_CL_CLIP_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_SC_MODE_CNTL_DEFAULT 0x00000000 -#define mmPA_CL_VTE_CNTL_DEFAULT 0x00000000 -#define mmPA_CL_VS_OUT_CNTL_DEFAULT 0x00000000 -#define mmPA_CL_NANINF_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_LINE_STIPPLE_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_LINE_STIPPLE_SCALE_DEFAULT 0x00000000 -#define mmPA_SU_PRIM_FILTER_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_DEFAULT 0x00000000 -#define mmPA_CL_OBJPRIM_ID_CNTL_DEFAULT 0x00000000 -#define mmPA_CL_NGG_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_POINT_SIZE_DEFAULT 0x00000000 -#define mmPA_SU_POINT_MINMAX_DEFAULT 0x00000000 -#define mmPA_SU_LINE_CNTL_DEFAULT 0x00000000 -#define mmPA_SC_LINE_STIPPLE_DEFAULT 0x00000000 -#define mmVGT_OUTPUT_PATH_CNTL_DEFAULT 0x00000000 -#define mmVGT_HOS_CNTL_DEFAULT 0x00000000 -#define mmVGT_HOS_MAX_TESS_LEVEL_DEFAULT 0x00000000 -#define mmVGT_HOS_MIN_TESS_LEVEL_DEFAULT 0x00000000 -#define mmVGT_HOS_REUSE_DEPTH_DEFAULT 0x00000000 -#define mmVGT_GROUP_PRIM_TYPE_DEFAULT 0x00000000 -#define mmVGT_GROUP_FIRST_DECR_DEFAULT 0x00000000 -#define mmVGT_GROUP_DECR_DEFAULT 0x00000000 -#define mmVGT_GROUP_VECT_0_CNTL_DEFAULT 0x00000000 -#define mmVGT_GROUP_VECT_1_CNTL_DEFAULT 0x00000000 -#define mmVGT_GROUP_VECT_0_FMT_CNTL_DEFAULT 0x00000000 -#define mmVGT_GROUP_VECT_1_FMT_CNTL_DEFAULT 0x00000000 -#define mmVGT_GS_MODE_DEFAULT 0x00000000 -#define mmVGT_GS_ONCHIP_CNTL_DEFAULT 0x00000000 -#define mmPA_SC_MODE_CNTL_0_DEFAULT 0x00000000 -#define mmPA_SC_MODE_CNTL_1_DEFAULT 0x06000000 -#define mmVGT_ENHANCE_DEFAULT 0x00000000 -#define mmVGT_GS_PER_ES_DEFAULT 0x00000000 -#define mmVGT_ES_PER_GS_DEFAULT 0x00000000 -#define mmVGT_GS_PER_VS_DEFAULT 0x00000000 -#define mmVGT_GSVS_RING_OFFSET_1_DEFAULT 0x00000000 -#define mmVGT_GSVS_RING_OFFSET_2_DEFAULT 0x00000000 -#define mmVGT_GSVS_RING_OFFSET_3_DEFAULT 0x00000000 -#define mmVGT_GS_OUT_PRIM_TYPE_DEFAULT 0x00000000 -#define mmIA_ENHANCE_DEFAULT 0x00000000 -#define mmVGT_DMA_SIZE_DEFAULT 0x00000000 -#define mmVGT_DMA_MAX_SIZE_DEFAULT 0x00000000 -#define mmVGT_DMA_INDEX_TYPE_DEFAULT 0x00000000 -#define mmWD_ENHANCE_DEFAULT 0x00000000 -#define mmVGT_PRIMITIVEID_EN_DEFAULT 0x00000000 -#define mmVGT_DMA_NUM_INSTANCES_DEFAULT 0x00000000 -#define mmVGT_PRIMITIVEID_RESET_DEFAULT 0x00000000 -#define mmVGT_EVENT_INITIATOR_DEFAULT 0x00000000 -#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT 0x00000000 -#define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000 -#define mmVGT_INDEX_PAYLOAD_CNTL_DEFAULT 0x00000000 -#define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 0x00000000 -#define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 0x00000000 -#define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000 -#define mmVGT_GSVS_RING_ITEMSIZE_DEFAULT 0x00000000 -#define mmVGT_REUSE_OFF_DEFAULT 0x00000000 -#define mmVGT_VTX_CNT_EN_DEFAULT 0x00000000 -#define mmDB_HTILE_SURFACE_DEFAULT 0x00000000 -#define mmDB_SRESULTS_COMPARE_STATE0_DEFAULT 0x00000000 -#define mmDB_SRESULTS_COMPARE_STATE1_DEFAULT 0x00000000 -#define mmDB_PRELOAD_CONTROL_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_SIZE_0_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_VTX_STRIDE_0_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_OFFSET_0_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_SIZE_1_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_VTX_STRIDE_1_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_OFFSET_1_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_SIZE_2_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_VTX_STRIDE_2_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_OFFSET_2_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_SIZE_3_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_VTX_STRIDE_3_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_OFFSET_3_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_DEFAULT 0x00000000 -#define mmVGT_GS_MAX_VERT_OUT_DEFAULT 0x00000000 -#define mmVGT_TESS_DISTRIBUTION_DEFAULT 0x00000000 -#define mmVGT_SHADER_STAGES_EN_DEFAULT 0x00000000 -#define mmVGT_LS_HS_CONFIG_DEFAULT 0x00000000 -#define mmVGT_GS_VERT_ITEMSIZE_DEFAULT 0x00000000 -#define mmVGT_GS_VERT_ITEMSIZE_1_DEFAULT 0x00000000 -#define mmVGT_GS_VERT_ITEMSIZE_2_DEFAULT 0x00000000 -#define mmVGT_GS_VERT_ITEMSIZE_3_DEFAULT 0x00000000 -#define mmVGT_TF_PARAM_DEFAULT 0x00000000 -#define mmDB_ALPHA_TO_MASK_DEFAULT 0x00000000 -#define mmVGT_DISPATCH_DRAW_INDEX_DEFAULT 0x00000000 -#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_POLY_OFFSET_CLAMP_DEFAULT 0x00000000 -#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_DEFAULT 0x00000000 -#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_DEFAULT 0x00000000 -#define mmPA_SU_POLY_OFFSET_BACK_SCALE_DEFAULT 0x00000000 -#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_DEFAULT 0x00000000 -#define mmVGT_GS_INSTANCE_CNT_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_CONFIG_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_CONFIG_DEFAULT 0x00000000 -#define mmVGT_DMA_EVENT_INITIATOR_DEFAULT 0x00000000 -#define mmPA_SC_CENTROID_PRIORITY_0_DEFAULT 0x00000000 -#define mmPA_SC_CENTROID_PRIORITY_1_DEFAULT 0x00000000 -#define mmPA_SC_LINE_CNTL_DEFAULT 0x00000000 -#define mmPA_SC_AA_CONFIG_DEFAULT 0x00000000 -#define mmPA_SU_VTX_CNTL_DEFAULT 0x00000000 -#define mmPA_CL_GB_VERT_CLIP_ADJ_DEFAULT 0x00000000 -#define mmPA_CL_GB_VERT_DISC_ADJ_DEFAULT 0x00000000 -#define mmPA_CL_GB_HORZ_CLIP_ADJ_DEFAULT 0x00000000 -#define mmPA_CL_GB_HORZ_DISC_ADJ_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_DEFAULT 0x00000000 -#define mmPA_SC_AA_MASK_X0Y0_X1Y0_DEFAULT 0x00000000 -#define mmPA_SC_AA_MASK_X0Y1_X1Y1_DEFAULT 0x00000000 -#define mmPA_SC_SHADER_CONTROL_DEFAULT 0x00000000 -#define mmPA_SC_BINNER_CNTL_0_DEFAULT 0x00000000 -#define mmPA_SC_BINNER_CNTL_1_DEFAULT 0x00000000 -#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_DEFAULT 0x00000000 -#define mmPA_SC_NGG_MODE_CNTL_DEFAULT 0x00000000 -#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_DEFAULT 0x00000000 -#define mmVGT_OUT_DEALLOC_CNTL_DEFAULT 0x00000000 -#define mmCB_COLOR0_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR0_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR0_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR0_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR0_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR0_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR0_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR0_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR0_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR0_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR0_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR0_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR0_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR0_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR0_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR1_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR1_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR1_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR1_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR1_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR1_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR1_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR1_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR1_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR1_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR1_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR1_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR1_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR1_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR1_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR2_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR2_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR2_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR2_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR2_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR2_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR2_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR2_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR2_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR2_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR2_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR2_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR2_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR2_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR2_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR3_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR3_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR3_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR3_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR3_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR3_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR3_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR3_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR3_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR3_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR3_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR3_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR3_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR3_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR3_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR4_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR4_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR4_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR4_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR4_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR4_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR4_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR4_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR4_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR4_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR4_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR4_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR4_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR4_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR4_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR5_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR5_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR5_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR5_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR5_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR5_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR5_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR5_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR5_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR5_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR5_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR5_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR5_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR5_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR5_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR6_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR6_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR6_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR6_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR6_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR6_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR6_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR6_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR6_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR6_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR6_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR6_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR6_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR6_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR6_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR7_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR7_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR7_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR7_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR7_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR7_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR7_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR7_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR7_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR7_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR7_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR7_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR7_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR7_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR7_DCC_BASE_EXT_DEFAULT 0x00000000 - - -// addressBlock: gc_gfxudec -#define mmCP_EOP_DONE_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_EOP_DONE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_EOP_DONE_DATA_LO_DEFAULT 0x00000000 -#define mmCP_EOP_DONE_DATA_HI_DEFAULT 0x00000000 -#define mmCP_EOP_LAST_FENCE_LO_DEFAULT 0x00000000 -#define mmCP_EOP_LAST_FENCE_HI_DEFAULT 0x00000000 -#define mmCP_STREAM_OUT_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_STREAM_OUT_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_DEFAULT 0x00000000 -#define mmCP_PIPE_STATS_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_PIPE_STATS_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_VGT_IAVERT_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_IAVERT_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_VGT_IAPRIM_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_IAPRIM_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_VGT_GSPRIM_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_GSPRIM_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_VGT_VSINVOC_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_VSINVOC_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_VGT_GSINVOC_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_GSINVOC_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_VGT_HSINVOC_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_HSINVOC_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_VGT_DSINVOC_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_DSINVOC_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_PA_CINVOC_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_PA_CINVOC_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_PA_CPRIM_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_PA_CPRIM_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_SC_PSINVOC_COUNT0_LO_DEFAULT 0x00000000 -#define mmCP_SC_PSINVOC_COUNT0_HI_DEFAULT 0x00000000 -#define mmCP_SC_PSINVOC_COUNT1_LO_DEFAULT 0x00000000 -#define mmCP_SC_PSINVOC_COUNT1_HI_DEFAULT 0x00000000 -#define mmCP_VGT_CSINVOC_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_CSINVOC_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_PIPE_STATS_CONTROL_DEFAULT 0x00000000 -#define mmCP_STREAM_OUT_CONTROL_DEFAULT 0x00000000 -#define mmCP_STRMOUT_CNTL_DEFAULT 0x00000000 -#define mmSCRATCH_REG0_DEFAULT 0x00000000 -#define mmSCRATCH_REG1_DEFAULT 0x00000000 -#define mmSCRATCH_REG2_DEFAULT 0x00000000 -#define mmSCRATCH_REG3_DEFAULT 0x00000000 -#define mmSCRATCH_REG4_DEFAULT 0x00000000 -#define mmSCRATCH_REG5_DEFAULT 0x00000000 -#define mmSCRATCH_REG6_DEFAULT 0x00000000 -#define mmSCRATCH_REG7_DEFAULT 0x00000000 -#define mmCP_APPEND_DATA_HI_DEFAULT 0x00000000 -#define mmCP_APPEND_LAST_CS_FENCE_HI_DEFAULT 0x00000000 -#define mmCP_APPEND_LAST_PS_FENCE_HI_DEFAULT 0x00000000 -#define mmSCRATCH_UMSK_DEFAULT 0x00000000 -#define mmSCRATCH_ADDR_DEFAULT 0x00000000 -#define mmCP_PFP_ATOMIC_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_PFP_ATOMIC_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_APPEND_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_APPEND_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_APPEND_DATA_LO_DEFAULT 0x00000000 -#define mmCP_APPEND_LAST_CS_FENCE_LO_DEFAULT 0x00000000 -#define mmCP_APPEND_LAST_PS_FENCE_LO_DEFAULT 0x00000000 -#define mmCP_ATOMIC_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_ME_ATOMIC_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_ATOMIC_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_ME_ATOMIC_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_ME_MC_WADDR_LO_DEFAULT 0x00000000 -#define mmCP_ME_MC_WADDR_HI_DEFAULT 0x00000000 -#define mmCP_ME_MC_WDATA_LO_DEFAULT 0x00000000 -#define mmCP_ME_MC_WDATA_HI_DEFAULT 0x00000000 -#define mmCP_ME_MC_RADDR_LO_DEFAULT 0x00000000 -#define mmCP_ME_MC_RADDR_HI_DEFAULT 0x00000000 -#define mmCP_SEM_WAIT_TIMER_DEFAULT 0x00000000 -#define mmCP_SIG_SEM_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_SIG_SEM_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_WAIT_REG_MEM_TIMEOUT_DEFAULT 0x00000000 -#define mmCP_WAIT_SEM_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_WAIT_SEM_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DMA_PFP_CONTROL_DEFAULT 0x00000000 -#define mmCP_DMA_ME_CONTROL_DEFAULT 0x00000000 -#define mmCP_COHER_BASE_HI_DEFAULT 0x00000000 -#define mmCP_COHER_START_DELAY_DEFAULT 0x00000020 -#define mmCP_COHER_CNTL_DEFAULT 0x00000000 -#define mmCP_COHER_SIZE_DEFAULT 0x00000000 -#define mmCP_COHER_BASE_DEFAULT 0x00000000 -#define mmCP_COHER_STATUS_DEFAULT 0x00000000 -#define mmCP_DMA_ME_SRC_ADDR_DEFAULT 0x00000000 -#define mmCP_DMA_ME_SRC_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DMA_ME_DST_ADDR_DEFAULT 0x00000000 -#define mmCP_DMA_ME_DST_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DMA_ME_COMMAND_DEFAULT 0x00000000 -#define mmCP_DMA_PFP_SRC_ADDR_DEFAULT 0x00000000 -#define mmCP_DMA_PFP_SRC_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DMA_PFP_DST_ADDR_DEFAULT 0x00000000 -#define mmCP_DMA_PFP_DST_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DMA_PFP_COMMAND_DEFAULT 0x00000000 -#define mmCP_DMA_CNTL_DEFAULT 0x00080030 -#define mmCP_DMA_READ_TAGS_DEFAULT 0x00000000 -#define mmCP_COHER_SIZE_HI_DEFAULT 0x00000000 -#define mmCP_PFP_IB_CONTROL_DEFAULT 0x00000000 -#define mmCP_PFP_LOAD_CONTROL_DEFAULT 0x00000000 -#define mmCP_SCRATCH_INDEX_DEFAULT 0x00000000 -#define mmCP_SCRATCH_DATA_DEFAULT 0x00000000 -#define mmCP_RB_OFFSET_DEFAULT 0x00000000 -#define mmCP_IB1_OFFSET_DEFAULT 0x00000000 -#define mmCP_IB2_OFFSET_DEFAULT 0x00000000 -#define mmCP_IB1_PREAMBLE_BEGIN_DEFAULT 0x00000000 -#define mmCP_IB1_PREAMBLE_END_DEFAULT 0x00000000 -#define mmCP_IB2_PREAMBLE_BEGIN_DEFAULT 0x00000000 -#define mmCP_IB2_PREAMBLE_END_DEFAULT 0x00000000 -#define mmCP_CE_IB1_OFFSET_DEFAULT 0x00000000 -#define mmCP_CE_IB2_OFFSET_DEFAULT 0x00000000 -#define mmCP_CE_COUNTER_DEFAULT 0x00000000 -#define mmCP_CE_RB_OFFSET_DEFAULT 0x00000000 -#define mmCP_CE_INIT_CMD_BUFSZ_DEFAULT 0x00000000 -#define mmCP_CE_IB1_CMD_BUFSZ_DEFAULT 0x00000000 -#define mmCP_CE_IB2_CMD_BUFSZ_DEFAULT 0x00000000 -#define mmCP_IB1_CMD_BUFSZ_DEFAULT 0x00000000 -#define mmCP_IB2_CMD_BUFSZ_DEFAULT 0x00000000 -#define mmCP_ST_CMD_BUFSZ_DEFAULT 0x00000000 -#define mmCP_CE_INIT_BASE_LO_DEFAULT 0x00000000 -#define mmCP_CE_INIT_BASE_HI_DEFAULT 0x00000000 -#define mmCP_CE_INIT_BUFSZ_DEFAULT 0x00000000 -#define mmCP_CE_IB1_BASE_LO_DEFAULT 0x00000000 -#define mmCP_CE_IB1_BASE_HI_DEFAULT 0x00000000 -#define mmCP_CE_IB1_BUFSZ_DEFAULT 0x00000000 -#define mmCP_CE_IB2_BASE_LO_DEFAULT 0x00000000 -#define mmCP_CE_IB2_BASE_HI_DEFAULT 0x00000000 -#define mmCP_CE_IB2_BUFSZ_DEFAULT 0x00000000 -#define mmCP_IB1_BASE_LO_DEFAULT 0x00000000 -#define mmCP_IB1_BASE_HI_DEFAULT 0x00000000 -#define mmCP_IB1_BUFSZ_DEFAULT 0x00000000 -#define mmCP_IB2_BASE_LO_DEFAULT 0x00000000 -#define mmCP_IB2_BASE_HI_DEFAULT 0x00000000 -#define mmCP_IB2_BUFSZ_DEFAULT 0x00000000 -#define mmCP_ST_BASE_LO_DEFAULT 0x00000000 -#define mmCP_ST_BASE_HI_DEFAULT 0x00000000 -#define mmCP_ST_BUFSZ_DEFAULT 0x00000000 -#define mmCP_EOP_DONE_EVENT_CNTL_DEFAULT 0x00000000 -#define mmCP_EOP_DONE_DATA_CNTL_DEFAULT 0x00000000 -#define mmCP_EOP_DONE_CNTX_ID_DEFAULT 0x00000000 -#define mmCP_PFP_COMPLETION_STATUS_DEFAULT 0x00000000 -#define mmCP_CE_COMPLETION_STATUS_DEFAULT 0x00000000 -#define mmCP_PRED_NOT_VISIBLE_DEFAULT 0x00000000 -#define mmCP_PFP_METADATA_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_PFP_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_CE_METADATA_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_CE_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DRAW_INDX_INDR_ADDR_DEFAULT 0x00000000 -#define mmCP_DRAW_INDX_INDR_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DISPATCH_INDR_ADDR_DEFAULT 0x00000000 -#define mmCP_DISPATCH_INDR_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_INDEX_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_INDEX_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_INDEX_TYPE_DEFAULT 0x00000000 -#define mmCP_GDS_BKUP_ADDR_DEFAULT 0x00000000 -#define mmCP_GDS_BKUP_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_SAMPLE_STATUS_DEFAULT 0x00000000 -#define mmCP_ME_COHER_CNTL_DEFAULT 0x00000000 -#define mmCP_ME_COHER_SIZE_DEFAULT 0x00000000 -#define mmCP_ME_COHER_SIZE_HI_DEFAULT 0x00000000 -#define mmCP_ME_COHER_BASE_DEFAULT 0x00000000 -#define mmCP_ME_COHER_BASE_HI_DEFAULT 0x00000000 -#define mmCP_ME_COHER_STATUS_DEFAULT 0x00000000 -#define mmRLC_GPM_PERF_COUNT_0_DEFAULT 0x00000000 -#define mmRLC_GPM_PERF_COUNT_1_DEFAULT 0x00000000 -#define mmGRBM_GFX_INDEX_DEFAULT 0xe0000000 -#define mmVGT_GSVS_RING_SIZE_DEFAULT 0x00000000 -#define mmVGT_PRIMITIVE_TYPE_DEFAULT 0x00000000 -#define mmVGT_INDEX_TYPE_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_DEFAULT 0x00000000 -#define mmVGT_MAX_VTX_INDX_DEFAULT 0x00000000 -#define mmVGT_MIN_VTX_INDX_DEFAULT 0x00000000 -#define mmVGT_INDX_OFFSET_DEFAULT 0x00000000 -#define mmVGT_MULTI_PRIM_IB_RESET_EN_DEFAULT 0x00000000 -#define mmVGT_NUM_INDICES_DEFAULT 0x00000000 -#define mmVGT_NUM_INSTANCES_DEFAULT 0x00000000 -#define mmVGT_TF_RING_SIZE_DEFAULT 0x00002000 -#define mmVGT_HS_OFFCHIP_PARAM_DEFAULT 0x00000000 -#define mmVGT_TF_MEMORY_BASE_DEFAULT 0x00000000 -#define mmVGT_TF_MEMORY_BASE_HI_DEFAULT 0x00000000 -#define mmWD_POS_BUF_BASE_DEFAULT 0x00000000 -#define mmWD_POS_BUF_BASE_HI_DEFAULT 0x00000000 -#define mmWD_CNTL_SB_BUF_BASE_DEFAULT 0x00000000 -#define mmWD_CNTL_SB_BUF_BASE_HI_DEFAULT 0x00000000 -#define mmWD_INDEX_BUF_BASE_DEFAULT 0x00000000 -#define mmWD_INDEX_BUF_BASE_HI_DEFAULT 0x00000000 -#define mmIA_MULTI_VGT_PARAM_DEFAULT 0x006000ff -#define mmVGT_OBJECT_ID_DEFAULT 0x00000000 -#define mmVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000 -#define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000 -#define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000 -#define mmPA_SC_SCREEN_EXTENT_MIN_0_DEFAULT 0x7fff7fff -#define mmPA_SC_SCREEN_EXTENT_MAX_0_DEFAULT 0x80008000 -#define mmPA_SC_SCREEN_EXTENT_MIN_1_DEFAULT 0x7fff7fff -#define mmPA_SC_SCREEN_EXTENT_MAX_1_DEFAULT 0x80008000 -#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000 -#define mmPA_SC_P3D_TRAP_SCREEN_H_DEFAULT 0x00000000 -#define mmPA_SC_P3D_TRAP_SCREEN_V_DEFAULT 0x00000000 -#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000 -#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000 -#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000 -#define mmPA_SC_HP3D_TRAP_SCREEN_H_DEFAULT 0x00000000 -#define mmPA_SC_HP3D_TRAP_SCREEN_V_DEFAULT 0x00000000 -#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000 -#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000 -#define mmPA_SC_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000 -#define mmPA_SC_TRAP_SCREEN_H_DEFAULT 0x00000000 -#define mmPA_SC_TRAP_SCREEN_V_DEFAULT 0x00000000 -#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000 -#define mmPA_SC_TRAP_SCREEN_COUNT_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_BASE_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_SIZE_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_MASK_DEFAULT 0x0000cf80 -#define mmSQ_THREAD_TRACE_TOKEN_MASK_DEFAULT 0x00ffffff -#define mmSQ_THREAD_TRACE_PERF_MASK_DEFAULT 0xffffffff -#define mmSQ_THREAD_TRACE_CTRL_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_MODE_DEFAULT 0x02049249 -#define mmSQ_THREAD_TRACE_BASE2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_TOKEN_MASK2_DEFAULT 0xffffffff -#define mmSQ_THREAD_TRACE_WPTR_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_STATUS_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_HIWATER_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_CNTR_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_USERDATA_0_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_USERDATA_1_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_USERDATA_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_USERDATA_3_DEFAULT 0x00000000 -#define mmSQC_CACHES_DEFAULT 0x00000000 -#define mmSQC_WRITEBACK_DEFAULT 0x00000000 -#define mmTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000 -#define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmTA_GRAD_ADJ_UCONFIG_DEFAULT 0x40000040 -#define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT1_HI_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT2_LOW_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT2_HI_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT3_LOW_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT3_HI_DEFAULT 0x00000000 -#define mmDB_ZPASS_COUNT_LOW_DEFAULT 0x00000000 -#define mmDB_ZPASS_COUNT_HI_DEFAULT 0x00000000 -#define mmGDS_RD_ADDR_DEFAULT 0x00000000 -#define mmGDS_RD_DATA_DEFAULT 0x00000000 -#define mmGDS_RD_BURST_ADDR_DEFAULT 0x00000000 -#define mmGDS_RD_BURST_COUNT_DEFAULT 0x00000000 -#define mmGDS_RD_BURST_DATA_DEFAULT 0x00000000 -#define mmGDS_WR_ADDR_DEFAULT 0x00000000 -#define mmGDS_WR_DATA_DEFAULT 0x00000000 -#define mmGDS_WR_BURST_ADDR_DEFAULT 0x00000000 -#define mmGDS_WR_BURST_DATA_DEFAULT 0x00000000 -#define mmGDS_WRITE_COMPLETE_DEFAULT 0x00000000 -#define mmGDS_ATOM_CNTL_DEFAULT 0x00000000 -#define mmGDS_ATOM_COMPLETE_DEFAULT 0x00000001 -#define mmGDS_ATOM_BASE_DEFAULT 0x00000000 -#define mmGDS_ATOM_SIZE_DEFAULT 0x00000000 -#define mmGDS_ATOM_OFFSET0_DEFAULT 0x00000000 -#define mmGDS_ATOM_OFFSET1_DEFAULT 0x00000000 -#define mmGDS_ATOM_DST_DEFAULT 0x00000000 -#define mmGDS_ATOM_OP_DEFAULT 0x00000000 -#define mmGDS_ATOM_SRC0_DEFAULT 0x00000000 -#define mmGDS_ATOM_SRC0_U_DEFAULT 0x00000000 -#define mmGDS_ATOM_SRC1_DEFAULT 0x00000000 -#define mmGDS_ATOM_SRC1_U_DEFAULT 0x00000000 -#define mmGDS_ATOM_READ0_DEFAULT 0x00000000 -#define mmGDS_ATOM_READ0_U_DEFAULT 0x00000000 -#define mmGDS_ATOM_READ1_DEFAULT 0x00000000 -#define mmGDS_ATOM_READ1_U_DEFAULT 0x00000000 -#define mmGDS_GWS_RESOURCE_CNTL_DEFAULT 0x00000000 -#define mmGDS_GWS_RESOURCE_DEFAULT 0x00000000 -#define mmGDS_GWS_RESOURCE_CNT_DEFAULT 0x00000000 -#define mmGDS_OA_CNTL_DEFAULT 0x00000000 -#define mmGDS_OA_COUNTER_DEFAULT 0x00000000 -#define mmGDS_OA_ADDRESS_DEFAULT 0x00000000 -#define mmGDS_OA_INCDEC_DEFAULT 0x00000000 -#define mmGDS_OA_RING_SIZE_DEFAULT 0x00000000 -#define mmSPI_CONFIG_CNTL_DEFAULT 0x0062c688 -#define mmSPI_CONFIG_CNTL_1_DEFAULT 0x01000104 -#define mmSPI_CONFIG_CNTL_2_DEFAULT 0x00000011 - - -// addressBlock: gc_perfddec -#define mmCPG_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmCPG_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmCPG_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmCPG_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmCPC_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmCPC_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmCPC_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmCPC_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmCPF_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmCPF_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmCPF_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmCPF_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmCPF_LATENCY_STATS_DATA_DEFAULT 0x00000000 -#define mmCPG_LATENCY_STATS_DATA_DEFAULT 0x00000000 -#define mmCPC_LATENCY_STATS_DATA_DEFAULT 0x00000000 -#define mmGRBM_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmGRBM_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmGRBM_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmGRBM_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmGRBM_SE0_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmGRBM_SE0_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmGRBM_SE1_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmGRBM_SE1_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmGRBM_SE2_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmGRBM_SE2_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmGRBM_SE3_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmGRBM_SE3_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER4_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER4_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER5_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER5_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER6_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER6_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER7_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER7_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER4_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER4_LO_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER5_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER5_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER4_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER4_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER5_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER5_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER6_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER6_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER7_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER7_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER8_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER8_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER9_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER9_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER10_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER10_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER11_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER11_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER12_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER12_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER13_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER13_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER14_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER14_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER15_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER15_HI_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmRLC_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmRLC_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmRLC_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmRLC_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER3_HI_DEFAULT 0x00000000 - - -// addressBlock: gc_utcl2_atcl2pfcntrdec -#define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: gc_utcl2_vml2prdec -#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: gc_perfsdec -#define mmCPG_PERFCOUNTER1_SELECT_DEFAULT 0x11000401 -#define mmCPG_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401 -#define mmCPG_PERFCOUNTER0_SELECT_DEFAULT 0x11000401 -#define mmCPC_PERFCOUNTER1_SELECT_DEFAULT 0x11000401 -#define mmCPC_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401 -#define mmCPF_PERFCOUNTER1_SELECT_DEFAULT 0x11000401 -#define mmCPF_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401 -#define mmCPF_PERFCOUNTER0_SELECT_DEFAULT 0x11000401 -#define mmCP_PERFMON_CNTL_DEFAULT 0x00000000 -#define mmCPC_PERFCOUNTER0_SELECT_DEFAULT 0x11000401 -#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000 -#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000 -#define mmCPF_LATENCY_STATS_SELECT_DEFAULT 0x00000000 -#define mmCPG_LATENCY_STATS_SELECT_DEFAULT 0x00000000 -#define mmCPC_LATENCY_STATS_SELECT_DEFAULT 0x00000000 -#define mmCP_DRAW_OBJECT_DEFAULT 0x00000000 -#define mmCP_DRAW_OBJECT_COUNTER_DEFAULT 0x00000000 -#define mmCP_DRAW_WINDOW_MASK_HI_DEFAULT 0x00000000 -#define mmCP_DRAW_WINDOW_HI_DEFAULT 0x00000000 -#define mmCP_DRAW_WINDOW_LO_DEFAULT 0x00000000 -#define mmCP_DRAW_WINDOW_CNTL_DEFAULT 0x00000007 -#define mmGRBM_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmGRBM_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmGRBM_SE0_PERFCOUNTER_SELECT_DEFAULT 0x00000000 -#define mmGRBM_SE1_PERFCOUNTER_SELECT_DEFAULT 0x00000000 -#define mmGRBM_SE2_PERFCOUNTER_SELECT_DEFAULT 0x00000000 -#define mmGRBM_SE3_PERFCOUNTER_SELECT_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER_SEID_MASK_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER4_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER5_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER6_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER7_SELECT_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER4_SELECT_DEFAULT 0x000000ff -#define mmSPI_PERFCOUNTER5_SELECT_DEFAULT 0x000000ff -#define mmSPI_PERFCOUNTER_BINS_DEFAULT 0xfcb87430 -#define mmSQ_PERFCOUNTER0_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER1_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER2_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER3_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER4_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER5_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER6_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER7_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER8_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER9_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER10_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER11_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER12_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER13_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER14_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER15_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER_CTRL_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER_MASK_DEFAULT 0xffffffff -#define mmSQ_PERFCOUNTER_CTRL2_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff -#define mmTCP_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff -#define mmTCP_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff -#define mmTCP_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff -#define mmTCP_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff -#define mmTCP_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff -#define mmTCC_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff -#define mmTCC_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff -#define mmTCC_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff -#define mmTCC_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff -#define mmTCC_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff -#define mmTCC_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff -#define mmTCA_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff -#define mmTCA_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff -#define mmTCA_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff -#define mmTCA_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff -#define mmTCA_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff -#define mmTCA_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff -#define mmCB_PERFCOUNTER_FILTER_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmRLC_SPM_PERFMON_CNTL_DEFAULT 0x00000000 -#define mmRLC_SPM_PERFMON_RING_BASE_LO_DEFAULT 0x00000000 -#define mmRLC_SPM_PERFMON_RING_BASE_HI_DEFAULT 0x00000000 -#define mmRLC_SPM_PERFMON_RING_SIZE_DEFAULT 0x00000000 -#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_DEFAULT 0x00000000 -#define mmRLC_SPM_SE_MUXSEL_ADDR_DEFAULT 0x00000000 -#define mmRLC_SPM_SE_MUXSEL_DATA_DEFAULT 0x00000000 -#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_DEFAULT 0x00000000 -#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_DEFAULT 0x00000000 -#define mmRLC_SPM_RING_RDPTR_DEFAULT 0x00000000 -#define mmRLC_SPM_SEGMENT_THRESHOLD_DEFAULT 0x00000000 -#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_PERFMON_CLK_CNTL_DEFAULT 0x00000001 -#define mmRLC_PERFMON_CNTL_DEFAULT 0x00000000 -#define mmRLC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmRLC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_PERF_CNT_CNTL_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER2_SELECT1_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmRMI_PERF_COUNTER_CNTL_DEFAULT 0x00080240 - - -// addressBlock: gc_utcl2_atcl2pfcntldec -#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - - -// addressBlock: gc_utcl2_vml2pldec -#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - - -// addressBlock: gc_rlcpdec -#define mmRLC_CNTL_DEFAULT 0x00000001 -#define mmRLC_STAT_DEFAULT 0x00000000 -#define mmRLC_SAFE_MODE_DEFAULT 0x00000000 -#define mmRLC_MEM_SLP_CNTL_DEFAULT 0x00020200 -#define mmSMU_RLC_RESPONSE_DEFAULT 0x00000000 -#define mmRLC_RLCV_SAFE_MODE_DEFAULT 0x00000000 -#define mmRLC_SMU_SAFE_MODE_DEFAULT 0x00000000 -#define mmRLC_RLCV_COMMAND_DEFAULT 0x00000000 -#define mmRLC_REFCLOCK_TIMESTAMP_LSB_DEFAULT 0x00000000 -#define mmRLC_REFCLOCK_TIMESTAMP_MSB_DEFAULT 0x00000000 -#define mmRLC_GPM_TIMER_INT_0_DEFAULT 0x00000000 -#define mmRLC_GPM_TIMER_INT_1_DEFAULT 0x00000000 -#define mmRLC_GPM_TIMER_INT_2_DEFAULT 0x00000000 -#define mmRLC_GPM_TIMER_CTRL_DEFAULT 0x00000000 -#define mmRLC_LB_CNTR_MAX_DEFAULT 0xffffffff -#define mmRLC_GPM_TIMER_STAT_DEFAULT 0x00000000 -#define mmRLC_GPM_TIMER_INT_3_DEFAULT 0x00000000 -#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_DEFAULT 0x00000000 -#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_DEFAULT 0x00000000 -#define mmRLC_INT_STAT_DEFAULT 0x00000000 -#define mmRLC_LB_CNTL_DEFAULT 0x00000010 -#define mmRLC_MGCG_CTRL_DEFAULT 0x00018800 -#define mmRLC_LB_CNTR_INIT_DEFAULT 0x00000000 -#define mmRLC_LOAD_BALANCE_CNTR_DEFAULT 0x00000000 -#define mmRLC_JUMP_TABLE_RESTORE_DEFAULT 0x00000000 -#define mmRLC_PG_DELAY_2_DEFAULT 0x00000004 -#define mmRLC_GPU_CLOCK_COUNT_LSB_DEFAULT 0x00000000 -#define mmRLC_GPU_CLOCK_COUNT_MSB_DEFAULT 0x00000000 -#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_DEFAULT 0x00000000 -#define mmRLC_UCODE_CNTL_DEFAULT 0x00000000 -#define mmRLC_GPM_THREAD_RESET_DEFAULT 0x0000000f -#define mmRLC_GPM_CP_DMA_COMPLETE_T0_DEFAULT 0x00000000 -#define mmRLC_GPM_CP_DMA_COMPLETE_T1_DEFAULT 0x00000000 -#define mmRLC_FIREWALL_VIOLATION_DEFAULT 0x00000000 -#define mmRLC_GPM_STAT_DEFAULT 0x00100016 -#define mmRLC_GPU_CLOCK_32_RES_SEL_DEFAULT 0x00000000 -#define mmRLC_GPU_CLOCK_32_DEFAULT 0x00000000 -#define mmRLC_PG_CNTL_DEFAULT 0x00000000 -#define mmRLC_GPM_THREAD_PRIORITY_DEFAULT 0x08080808 -#define mmRLC_GPM_THREAD_ENABLE_DEFAULT 0x00000001 -#define mmRLC_CGTT_MGCG_OVERRIDE_DEFAULT 0xffffffff -#define mmRLC_CGCG_CGLS_CTRL_DEFAULT 0x0001003c -#define mmRLC_CGCG_RAMP_CTRL_DEFAULT 0x00021711 -#define mmRLC_DYN_PG_STATUS_DEFAULT 0xffffffff -#define mmRLC_DYN_PG_REQUEST_DEFAULT 0xffffffff -#define mmRLC_PG_DELAY_DEFAULT 0x00101010 -#define mmRLC_CU_STATUS_DEFAULT 0x00000000 -#define mmRLC_LB_INIT_CU_MASK_DEFAULT 0xffffffff -#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_DEFAULT 0x00000001 -#define mmRLC_LB_PARAMS_DEFAULT 0x00601008 -#define mmRLC_THREAD1_DELAY_DEFAULT 0x00400401 -#define mmRLC_PG_ALWAYS_ON_CU_MASK_DEFAULT 0x00000003 -#define mmRLC_MAX_PG_CU_DEFAULT 0x0000000b -#define mmRLC_AUTO_PG_CTRL_DEFAULT 0x00000000 -#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_DEFAULT 0x00000000 -#define mmRLC_SERDES_RD_MASTER_INDEX_DEFAULT 0x00000000 -#define mmRLC_SERDES_RD_DATA_0_DEFAULT 0x00000000 -#define mmRLC_SERDES_RD_DATA_1_DEFAULT 0x00000000 -#define mmRLC_SERDES_RD_DATA_2_DEFAULT 0x00000000 -#define mmRLC_SERDES_WR_CU_MASTER_MASK_DEFAULT 0x00000000 -#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_DEFAULT 0x00000000 -#define mmRLC_SERDES_WR_CTRL_DEFAULT 0x00000000 -#define mmRLC_SERDES_WR_DATA_DEFAULT 0x00000000 -#define mmRLC_SERDES_CU_MASTER_BUSY_DEFAULT 0x00000000 -#define mmRLC_SERDES_NONCU_MASTER_BUSY_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_0_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_1_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_2_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_3_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_4_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_5_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_6_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_7_DEFAULT 0x00000000 -#define mmRLC_GPM_SCRATCH_ADDR_DEFAULT 0x00000000 -#define mmRLC_GPM_SCRATCH_DATA_DEFAULT 0x00000000 -#define mmRLC_STATIC_PG_STATUS_DEFAULT 0xffffffff -#define mmRLC_SPM_MC_CNTL_DEFAULT 0x00000000 -#define mmRLC_SPM_INT_CNTL_DEFAULT 0x00000000 -#define mmRLC_SPM_INT_STATUS_DEFAULT 0x00000000 -#define mmRLC_SMU_MESSAGE_DEFAULT 0x00000000 -#define mmRLC_GPM_LOG_SIZE_DEFAULT 0x00000000 -#define mmRLC_PG_DELAY_3_DEFAULT 0x00000000 -#define mmRLC_GPR_REG1_DEFAULT 0x00000000 -#define mmRLC_GPR_REG2_DEFAULT 0x00000000 -#define mmRLC_GPM_LOG_CONT_DEFAULT 0x00000000 -#define mmRLC_GPM_INT_DISABLE_TH0_DEFAULT 0x00000000 -#define mmRLC_GPM_INT_DISABLE_TH1_DEFAULT 0x00000000 -#define mmRLC_GPM_INT_FORCE_TH0_DEFAULT 0x00000000 -#define mmRLC_GPM_INT_FORCE_TH1_DEFAULT 0x00000000 -#define mmRLC_SRM_CNTL_DEFAULT 0x00000002 -#define mmRLC_SRM_ARAM_ADDR_DEFAULT 0x00000000 -#define mmRLC_SRM_ARAM_DATA_DEFAULT 0x00000000 -#define mmRLC_SRM_DRAM_ADDR_DEFAULT 0x00000000 -#define mmRLC_SRM_DRAM_DATA_DEFAULT 0x00000000 -#define mmRLC_SRM_GPM_COMMAND_DEFAULT 0x00000000 -#define mmRLC_SRM_GPM_COMMAND_STATUS_DEFAULT 0x00000000 -#define mmRLC_SRM_RLCV_COMMAND_DEFAULT 0x00000000 -#define mmRLC_SRM_RLCV_COMMAND_STATUS_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_0_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_1_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_2_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_3_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_4_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_5_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_6_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_7_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_0_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_1_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_2_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_3_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_4_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_5_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_6_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_7_DEFAULT 0x00000000 -#define mmRLC_SRM_STAT_DEFAULT 0x00000000 -#define mmRLC_SRM_GPM_ABORT_DEFAULT 0x00000000 -#define mmRLC_CSIB_ADDR_LO_DEFAULT 0x00000000 -#define mmRLC_CSIB_ADDR_HI_DEFAULT 0x00000000 -#define mmRLC_CSIB_LENGTH_DEFAULT 0x00000000 -#define mmRLC_SMU_COMMAND_DEFAULT 0x00000000 -#define mmRLC_CP_SCHEDULERS_DEFAULT 0x58504840 -#define mmRLC_SMU_ARGUMENT_1_DEFAULT 0x00000000 -#define mmRLC_SMU_ARGUMENT_2_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_8_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_9_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_10_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_11_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_12_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_CNTL_0_DEFAULT 0x00000080 -#define mmRLC_GPM_UTCL1_CNTL_1_DEFAULT 0x00000080 -#define mmRLC_GPM_UTCL1_CNTL_2_DEFAULT 0x00000080 -#define mmRLC_SPM_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmRLC_UTCL1_STATUS_2_DEFAULT 0x00000000 -#define mmRLC_LB_THR_CONFIG_2_DEFAULT 0x00000000 -#define mmRLC_LB_THR_CONFIG_3_DEFAULT 0x00000000 -#define mmRLC_LB_THR_CONFIG_4_DEFAULT 0x00000000 -#define mmRLC_SPM_UTCL1_ERROR_1_DEFAULT 0x00000000 -#define mmRLC_SPM_UTCL1_ERROR_2_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_TH0_ERROR_1_DEFAULT 0x00000000 -#define mmRLC_LB_THR_CONFIG_1_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_TH0_ERROR_2_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_TH1_ERROR_1_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_TH1_ERROR_2_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_TH2_ERROR_1_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_TH2_ERROR_2_DEFAULT 0x00000000 -#define mmRLC_CGCG_CGLS_CTRL_3D_DEFAULT 0x0001003c -#define mmRLC_CGCG_RAMP_CTRL_3D_DEFAULT 0x00021711 -#define mmRLC_SEMAPHORE_0_DEFAULT 0x00000000 -#define mmRLC_SEMAPHORE_1_DEFAULT 0x00000000 -#define mmRLC_CP_EOF_INT_DEFAULT 0x00000000 -#define mmRLC_CP_EOF_INT_CNT_DEFAULT 0x00000000 -#define mmRLC_SPARE_INT_DEFAULT 0x00000000 -#define mmRLC_PREWALKER_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmRLC_PREWALKER_UTCL1_TRIG_DEFAULT 0x00000000 -#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_DEFAULT 0x00000000 -#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_DEFAULT 0x00000000 -#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_DEFAULT 0x00000000 -#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_DEFAULT 0x00000000 -#define mmRLC_DSM_TRIG_DEFAULT 0x00000000 -#define mmRLC_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmRLC_R2I_CNTL_0_DEFAULT 0x00000000 -#define mmRLC_R2I_CNTL_1_DEFAULT 0x00000000 -#define mmRLC_R2I_CNTL_2_DEFAULT 0x00000000 -#define mmRLC_R2I_CNTL_3_DEFAULT 0x00000000 -#define mmRLC_UTCL2_CNTL_DEFAULT 0x00000000 -#define mmRLC_LBPW_CU_STAT_DEFAULT 0x00000000 -#define mmRLC_DS_CNTL_DEFAULT 0x00030003 -#define mmRLC_RLCV_SPARE_INT_DEFAULT 0x00000000 - - -// addressBlock: gc_pwrdec -#define mmCGTS_SM_CTRL_REG_DEFAULT 0x00600200 -#define mmCGTS_RD_CTRL_REG_DEFAULT 0x00000000 -#define mmCGTS_RD_REG_DEFAULT 0x00000000 -#define mmCGTS_TCC_DISABLE_DEFAULT 0x00000000 -#define mmCGTS_USER_TCC_DISABLE_DEFAULT 0x00000000 -#define mmCGTS_CU0_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU0_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU0_TA_SQC_CTRL_REG_DEFAULT 0x00040007 -#define mmCGTS_CU0_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU0_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU1_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU1_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU1_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU1_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU1_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU2_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU2_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU2_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU2_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU2_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU3_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU3_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU3_TA_SQC_CTRL_REG_DEFAULT 0x00040007 -#define mmCGTS_CU3_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU3_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU4_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU4_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU4_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU4_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU4_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU5_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU5_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU5_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU5_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU5_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU6_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU6_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU6_TA_SQC_CTRL_REG_DEFAULT 0x00040007 -#define mmCGTS_CU6_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU6_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU7_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU7_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU7_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU7_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU7_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU8_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU8_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU8_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU8_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU8_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU9_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU9_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU9_TA_SQC_CTRL_REG_DEFAULT 0x00040007 -#define mmCGTS_CU9_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU9_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU10_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU10_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU10_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU10_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU10_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU11_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU11_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU11_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU11_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU11_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU12_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU12_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU12_TA_SQC_CTRL_REG_DEFAULT 0x00040007 -#define mmCGTS_CU12_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU12_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU13_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU13_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU13_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU13_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU13_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU14_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU14_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU14_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU14_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU14_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU15_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU15_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU15_TA_SQC_CTRL_REG_DEFAULT 0x00040007 -#define mmCGTS_CU15_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU15_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU0_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU1_TCPI_CTRL_REG_DEFAULT 0x00000001 -#define mmCGTS_CU2_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU3_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU4_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU5_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU6_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU7_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU8_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU9_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU10_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU11_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU12_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU13_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU14_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU15_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTT_SPI_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_PC_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_BCI_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_VGT_CLK_CTRL_DEFAULT 0x00018100 -#define mmCGTT_IA_CLK_CTRL_DEFAULT 0x06000100 -#define mmCGTT_WD_CLK_CTRL_DEFAULT 0x00018100 -#define mmCGTT_PA_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_SC_CLK_CTRL0_DEFAULT 0x00000100 -#define mmCGTT_SC_CLK_CTRL1_DEFAULT 0x00000100 -#define mmCGTT_SQ_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_SQG_CLK_CTRL_DEFAULT 0x00000100 -#define mmSQ_ALU_CLK_CTRL_DEFAULT 0x00000000 -#define mmSQ_TEX_CLK_CTRL_DEFAULT 0x00000000 -#define mmSQ_LDS_CLK_CTRL_DEFAULT 0x00000000 -#define mmSQ_POWER_THROTTLE_DEFAULT 0x3fff3fff -#define mmSQ_POWER_THROTTLE2_DEFAULT 0x18800004 -#define mmCGTT_SX_CLK_CTRL0_DEFAULT 0x00000100 -#define mmCGTT_SX_CLK_CTRL1_DEFAULT 0x00000100 -#define mmCGTT_SX_CLK_CTRL2_DEFAULT 0x00000100 -#define mmCGTT_SX_CLK_CTRL3_DEFAULT 0x00000100 -#define mmCGTT_SX_CLK_CTRL4_DEFAULT 0x00000100 -#define mmTD_CGTT_CTRL_DEFAULT 0x00000100 -#define mmTA_CGTT_CTRL_DEFAULT 0x00000100 -#define mmCGTT_TCPI_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_TCI_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_GDS_CLK_CTRL_DEFAULT 0x00000100 -#define mmDB_CGTT_CLK_CTRL_0_DEFAULT 0x00000100 -#define mmCB_CGTT_SCLK_CTRL_DEFAULT 0x00000100 -#define mmTCC_CGTT_SCLK_CTRL_DEFAULT 0x00000100 -#define mmTCA_CGTT_SCLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_CP_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_CPF_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_CPC_CLK_CTRL_DEFAULT 0x00000100 -#define mmRLC_PWR_CTRL_DEFAULT 0x00000000 -#define mmCGTT_RLC_CLK_CTRL_DEFAULT 0x00000100 -#define mmRLC_GFX_RM_CNTL_DEFAULT 0x00000000 -#define mmRMI_CGTT_SCLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_TCPF_CLK_CTRL_DEFAULT 0x00000100 - - -// addressBlock: gc_ea_pwrdec -#define mmGCEA_CGTT_CLK_CTRL_DEFAULT 0x00000100 - - -// addressBlock: gc_utcl2_vmsharedhvdec -#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 -#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 -#define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 -#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 -#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 -#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: gc_hypdec -#define mmCP_HYP_PFP_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_PFP_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_HYP_PFP_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_PFP_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_HYP_ME_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_ME_RAM_RADDR_DEFAULT 0x00000000 -#define mmCP_ME_RAM_WADDR_DEFAULT 0x00000000 -#define mmCP_HYP_ME_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_ME_RAM_DATA_DEFAULT 0x00000000 -#define mmCP_CE_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_HYP_CE_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_CE_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_HYP_CE_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_HYP_MEC1_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_MEC_ME1_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_HYP_MEC1_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_MEC_ME1_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_HYP_MEC2_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_MEC_ME2_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_HYP_MEC2_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_MEC_ME2_UCODE_DATA_DEFAULT 0x00000000 -#define mmRLC_GPM_UCODE_ADDR_DEFAULT 0x00000000 -#define mmRLC_GPM_UCODE_DATA_DEFAULT 0x00000000 -#define mmGRBM_GFX_INDEX_SR_SELECT_DEFAULT 0x00000000 -#define mmGRBM_GFX_INDEX_SR_DATA_DEFAULT 0xe0000000 -#define mmGRBM_GFX_CNTL_SR_SELECT_DEFAULT 0x00000000 -#define mmGRBM_GFX_CNTL_SR_DATA_DEFAULT 0x00000000 -#define mmGRBM_CAM_INDEX_DEFAULT 0x00000000 -#define mmGRBM_HYP_CAM_INDEX_DEFAULT 0x00000000 -#define mmGRBM_CAM_DATA_DEFAULT 0x00000000 -#define mmGRBM_HYP_CAM_DATA_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_VF_ENABLE_DEFAULT 0x00000000 -#define mmRLC_GFX_RM_CNTL_ADJ_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_CFG_REG6_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_CFG_REG8_DEFAULT 0x00000000 -#define mmRLC_RLCV_TIMER_INT_0_DEFAULT 0x00000000 -#define mmRLC_RLCV_TIMER_CTRL_DEFAULT 0x00000000 -#define mmRLC_RLCV_TIMER_STAT_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_DEFAULT 0x0000ffff -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_VF_MASK_DEFAULT 0x00010001 -#define mmRLC_HYP_SEMAPHORE_2_DEFAULT 0x00000000 -#define mmRLC_HYP_SEMAPHORE_3_DEFAULT 0x00000000 -#define mmRLC_CLK_CNTL_DEFAULT 0x00000003 -#define mmRLC_GPU_IOV_SCH_BLOCK_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_CFG_REG1_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_CFG_REG2_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_VM_BUSY_STATUS_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SCH_0_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SCH_3_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SCH_1_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SCH_2_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_UCODE_ADDR_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_UCODE_DATA_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SCRATCH_ADDR_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SCRATCH_DATA_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_F32_CNTL_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_F32_RESET_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SDMA0_STATUS_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SDMA1_STATUS_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SMU_RESPONSE_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_RLC_RESPONSE_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_INT_DISABLE_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_INT_FORCE_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_DEFAULT 0x00000000 - - -// addressBlock: gccacind -#define ixGC_CAC_CNTL_DEFAULT 0x000001fe -#define ixGC_CAC_OVR_SEL_DEFAULT 0x00000000 -#define ixGC_CAC_OVR_VAL_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_BCI_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CB_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CB_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CP_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CP_1_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_DB_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_DB_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_GDS_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_GDS_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_IA_0_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_LDS_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_LDS_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_PA_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_PC_0_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_SC_0_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_SPI_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SPI_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SPI_2_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SQ_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SQ_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SQ_2_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SQ_3_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SQ_4_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_SX_0_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_SXRB_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TA_0_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_TCC_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TCC_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TCC_2_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_TCP_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TCP_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TCP_2_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_TD_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TD_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TD_2_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_VGT_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_VGT_1_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_WD_0_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_CU_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CU_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CU_2_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CU_3_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CU_4_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CU_5_DEFAULT 0x00010001 -#define ixGC_CAC_ACC_BCI0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CB0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CB1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CB2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CB3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CP0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CP1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CP2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_DB0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_DB1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_DB2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_DB3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_GDS0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_GDS1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_GDS2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_GDS3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_IA0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_LDS0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_LDS1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_LDS2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_LDS3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_PA0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_PA1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_PC0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SC0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SPI0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SPI1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SPI2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SPI3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SPI4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SPI5_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_PG_0_DEFAULT 0x00000001 -#define ixGC_CAC_ACC_PG0_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_PG_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0_DEFAULT 0x00010001 -#define ixGC_CAC_ACC_EA0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_EA1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_EA2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_EA3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ATCL20_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_EA_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_UTCL2_ATCL2_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_EA_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_EA_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_RMI_0_DEFAULT 0x00000001 -#define ixGC_CAC_ACC_RMI0_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_RMI_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1_DEFAULT 0x00010001 -#define ixGC_CAC_ACC_UTCL2_ATCL21_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ATCL22_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ATCL23_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_EA4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_EA5_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_EA_2_DEFAULT 0x00010001 -#define ixGC_CAC_ACC_SQ0_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ0_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ1_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ1_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ2_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ2_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ3_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ3_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ4_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ4_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ5_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ5_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ6_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ6_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ7_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ7_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ8_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ8_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SX0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SXRB0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SXRB1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TA0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCC0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCC1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCC2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCC3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCC4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCP0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCP1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCP2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCP3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCP4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TD0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TD1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TD2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TD3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TD4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TD5_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_VGT0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_VGT1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_VGT2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_WD0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU5_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU6_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU7_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU8_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU9_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU10_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_BCI_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_CB_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_CP_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_DB_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_GDS_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_IA_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_LDS_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_PA_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_PC_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_SC_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_SPI_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_CU_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_SQ_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_SX_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_SXRB_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_TA_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_TCC_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_TCP_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_TD_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_VGT_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_WD_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_BCI1_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_VML2_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_VML2_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_VML2_2_DEFAULT 0x00010001 -#define ixGC_CAC_ACC_UTCL2_ATCL24_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER5_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER6_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER7_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER8_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER9_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_VML20_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_VML21_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_VML22_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_VML23_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_VML24_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_UTCL2_ROUTER_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_UTCL2_VML2_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2_DEFAULT 0x00010001 -#define ixGC_CAC_ACC_UTCL2_WALKER0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_WALKER1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_WALKER2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_WALKER3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_WALKER4_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_UTCL2_WALKER_DEFAULT 0x00000000 - - -// addressBlock: secacind -#define ixSE_CAC_CNTL_DEFAULT 0x000001fe -#define ixSE_CAC_OVR_SEL_DEFAULT 0x00000000 -#define ixSE_CAC_OVR_VAL_DEFAULT 0x00000000 - - -// addressBlock: sqind -#define ixSQ_WAVE_MODE_DEFAULT 0x00000000 -#define ixSQ_WAVE_STATUS_DEFAULT 0x00000000 -#define ixSQ_WAVE_TRAPSTS_DEFAULT 0x00000000 -#define ixSQ_WAVE_HW_ID_DEFAULT 0x00000000 -#define ixSQ_WAVE_GPR_ALLOC_DEFAULT 0x00000000 -#define ixSQ_WAVE_LDS_ALLOC_DEFAULT 0x00000000 -#define ixSQ_WAVE_IB_STS_DEFAULT 0x00000000 -#define ixSQ_WAVE_PC_LO_DEFAULT 0x00000000 -#define ixSQ_WAVE_PC_HI_DEFAULT 0x00000000 -#define ixSQ_WAVE_INST_DW0_DEFAULT 0x00000000 -#define ixSQ_WAVE_INST_DW1_DEFAULT 0x00000000 -#define ixSQ_WAVE_IB_DBG0_DEFAULT 0x00000000 -#define ixSQ_WAVE_IB_DBG1_DEFAULT 0x00000000 -#define ixSQ_WAVE_FLUSH_IB_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP0_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP1_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP2_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP3_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP4_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP5_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP6_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP7_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP8_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP9_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP10_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP11_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP12_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP13_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP14_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP15_DEFAULT 0x00000000 -#define ixSQ_WAVE_M0_DEFAULT 0x00000000 -#define ixSQ_WAVE_EXEC_LO_DEFAULT 0x00000000 -#define ixSQ_WAVE_EXEC_HI_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_AUTO_CTXID_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_AUTO_HI_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_AUTO_LO_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_CMN_CTXID_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_CMN_HI_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_WAVE_CTXID_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_WAVE_HI_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_WAVE_LO_DEFAULT 0x00000000 - - - - - - - - -// addressBlock: didtind -#define ixDIDT_SQ_CTRL0_DEFAULT 0x0000ff00 -#define ixDIDT_SQ_CTRL1_DEFAULT 0x00ff00ff -#define ixDIDT_SQ_CTRL2_DEFAULT 0x18800004 -#define ixDIDT_SQ_STALL_CTRL_DEFAULT 0x00fff000 -#define ixDIDT_SQ_TUNING_CTRL_DEFAULT 0x00010004 -#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff -#define ixDIDT_SQ_CTRL3_DEFAULT 0x00038000 -#define ixDIDT_SQ_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_SQ_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_SQ_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_SQ_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_SQ_WEIGHT0_3_DEFAULT 0x00000000 -#define ixDIDT_SQ_WEIGHT4_7_DEFAULT 0x00000000 -#define ixDIDT_SQ_WEIGHT8_11_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_CTRL_DEFAULT 0x00001c00 -#define ixDIDT_SQ_EDC_THRESHOLD_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_SQ_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_SQ_EDC_STATUS_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_STALL_DELAY_1_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_STALL_DELAY_2_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_STALL_DELAY_3_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_OVERFLOW_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 -#define ixDIDT_DB_CTRL0_DEFAULT 0x0000ff00 -#define ixDIDT_DB_CTRL1_DEFAULT 0x00ff00ff -#define ixDIDT_DB_CTRL2_DEFAULT 0x18800004 -#define ixDIDT_DB_STALL_CTRL_DEFAULT 0x00fff000 -#define ixDIDT_DB_TUNING_CTRL_DEFAULT 0x00010004 -#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff -#define ixDIDT_DB_CTRL3_DEFAULT 0x00038000 -#define ixDIDT_DB_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_DB_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_DB_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_DB_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_DB_WEIGHT0_3_DEFAULT 0x00000000 -#define ixDIDT_DB_WEIGHT4_7_DEFAULT 0x00000000 -#define ixDIDT_DB_WEIGHT8_11_DEFAULT 0x00000000 -#define ixDIDT_DB_EDC_CTRL_DEFAULT 0x00001c00 -#define ixDIDT_DB_EDC_THRESHOLD_DEFAULT 0x00000000 -#define ixDIDT_DB_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_DB_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_DB_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_DB_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_DB_EDC_STATUS_DEFAULT 0x00000000 -#define ixDIDT_DB_EDC_STALL_DELAY_1_DEFAULT 0x00000000 -#define ixDIDT_DB_EDC_OVERFLOW_DEFAULT 0x00000000 -#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 -#define ixDIDT_TD_CTRL0_DEFAULT 0x0000ff00 -#define ixDIDT_TD_CTRL1_DEFAULT 0x00ff00ff -#define ixDIDT_TD_CTRL2_DEFAULT 0x18800004 -#define ixDIDT_TD_STALL_CTRL_DEFAULT 0x00fff000 -#define ixDIDT_TD_TUNING_CTRL_DEFAULT 0x00010004 -#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff -#define ixDIDT_TD_CTRL3_DEFAULT 0x00038000 -#define ixDIDT_TD_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_TD_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_TD_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_TD_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_TD_WEIGHT0_3_DEFAULT 0x00000000 -#define ixDIDT_TD_WEIGHT4_7_DEFAULT 0x00000000 -#define ixDIDT_TD_WEIGHT8_11_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_CTRL_DEFAULT 0x00001c00 -#define ixDIDT_TD_EDC_THRESHOLD_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_TD_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_TD_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_TD_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_TD_EDC_STATUS_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_STALL_DELAY_1_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_STALL_DELAY_2_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_STALL_DELAY_3_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_OVERFLOW_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 -#define ixDIDT_TCP_CTRL0_DEFAULT 0x0000ff00 -#define ixDIDT_TCP_CTRL1_DEFAULT 0x00ff00ff -#define ixDIDT_TCP_CTRL2_DEFAULT 0x18800004 -#define ixDIDT_TCP_STALL_CTRL_DEFAULT 0x00fff000 -#define ixDIDT_TCP_TUNING_CTRL_DEFAULT 0x00010004 -#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff -#define ixDIDT_TCP_CTRL3_DEFAULT 0x00038000 -#define ixDIDT_TCP_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_TCP_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_TCP_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_TCP_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_TCP_WEIGHT0_3_DEFAULT 0x00000000 -#define ixDIDT_TCP_WEIGHT4_7_DEFAULT 0x00000000 -#define ixDIDT_TCP_WEIGHT8_11_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_CTRL_DEFAULT 0x00001c00 -#define ixDIDT_TCP_EDC_THRESHOLD_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_TCP_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_TCP_EDC_STATUS_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_STALL_DELAY_1_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_STALL_DELAY_2_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_STALL_DELAY_3_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_OVERFLOW_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 -#define ixDIDT_DBR_CTRL0_DEFAULT 0x0000ff00 -#define ixDIDT_DBR_CTRL1_DEFAULT 0x00ff00ff -#define ixDIDT_DBR_CTRL2_DEFAULT 0x18800004 -#define ixDIDT_DBR_STALL_CTRL_DEFAULT 0x00fff000 -#define ixDIDT_DBR_TUNING_CTRL_DEFAULT 0x00010004 -#define ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff -#define ixDIDT_DBR_CTRL3_DEFAULT 0x00038000 -#define ixDIDT_DBR_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_DBR_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_DBR_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_DBR_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_DBR_WEIGHT0_3_DEFAULT 0x00000000 -#define ixDIDT_DBR_WEIGHT4_7_DEFAULT 0x00000000 -#define ixDIDT_DBR_WEIGHT8_11_DEFAULT 0x00000000 -#define ixDIDT_DBR_EDC_CTRL_DEFAULT 0x00001c00 -#define ixDIDT_DBR_EDC_THRESHOLD_DEFAULT 0x00000000 -#define ixDIDT_DBR_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_DBR_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_DBR_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_DBR_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_DBR_EDC_STATUS_DEFAULT 0x00000000 -#define ixDIDT_DBR_EDC_STALL_DELAY_1_DEFAULT 0x00000000 -#define ixDIDT_DBR_EDC_OVERFLOW_DEFAULT 0x00000000 -#define ixDIDT_DBR_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 -#define ixDIDT_SQ_STALL_EVENT_COUNTER_DEFAULT 0x00000000 -#define ixDIDT_DB_STALL_EVENT_COUNTER_DEFAULT 0x00000000 -#define ixDIDT_TD_STALL_EVENT_COUNTER_DEFAULT 0x00000000 -#define ixDIDT_TCP_STALL_EVENT_COUNTER_DEFAULT 0x00000000 -#define ixDIDT_DBR_STALL_EVENT_COUNTER_DEFAULT 0x00000000 - - - - - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h deleted file mode 100644 index ab0a25eba483..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h +++ /dev/null @@ -1,31191 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _gc_9_1_SH_MASK_HEADER -#define _gc_9_1_SH_MASK_HEADER - - -// addressBlock: gc_grbmdec -//GRBM_CNTL -#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 -#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f -#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL -#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L -//GRBM_SKEW_CNTL -#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 -#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 -#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL -#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L -//GRBM_STATUS2 -#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 -#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 -#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 -#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 -#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 -#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 -#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 -#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa -#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb -#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc -#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd -#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe -#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf -#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 -#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 -#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 -#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13 -#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 -#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 -#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 -#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a -#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c -#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d -#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e -#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f -#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL -#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L -#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L -#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L -#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L -#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L -#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L -#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L -#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L -#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L -#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L -#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L -#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L -#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L -#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L -#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L -#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L -#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L -#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L -#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L -#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L -#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L -#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L -#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L -#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L -//GRBM_PWR_CNTL -#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 -#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 -#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 -#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 -#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe -#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf -#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L -#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL -#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L -#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L -#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L -#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L -//GRBM_STATUS -#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 -#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5 -#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 -#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 -#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 -#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc -#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd -#define GRBM_STATUS__TA_BUSY__SHIFT 0xe -#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf -#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 -#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 -#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 -#define GRBM_STATUS__IA_BUSY__SHIFT 0x13 -#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 -#define GRBM_STATUS__WD_BUSY__SHIFT 0x15 -#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 -#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 -#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 -#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 -#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a -#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c -#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d -#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e -#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f -#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL -#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L -#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L -#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L -#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L -#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L -#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L -#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L -#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L -#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L -#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L -#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L -#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L -#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L -#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L -#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L -#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L -#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L -#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L -#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L -#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L -#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L -#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L -#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L -//GRBM_STATUS_SE0 -#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 -#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 -#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 -#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 -#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 -#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 -#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 -#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a -#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b -#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d -#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e -#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f -#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L -#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L -//GRBM_STATUS_SE1 -#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 -#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 -#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 -#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 -#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 -#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 -#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 -#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a -#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b -#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d -#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e -#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f -#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L -#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L -//GRBM_SOFT_RESET -#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 -#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 -#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 -#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 -#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 -#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 -#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 -#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15 -#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 -#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L -#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L -#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L -#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L -#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L -//GRBM_CGTT_CLK_CNTL -#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 -#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL -#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -//GRBM_GFX_CLKEN_CNTL -#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 -#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 -#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL -#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L -//GRBM_WAIT_IDLE_CLOCKS -#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 -#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL -//GRBM_STATUS_SE2 -#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 -#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 -#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 -#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 -#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 -#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 -#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 -#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a -#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b -#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d -#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e -#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f -#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L -#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L -//GRBM_STATUS_SE3 -#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 -#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 -#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 -#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 -#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 -#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 -#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 -#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a -#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b -#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d -#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e -#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f -#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L -#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L -//GRBM_READ_ERROR -#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 -#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 -#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 -#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f -#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL -#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L -#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L -#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L -//GRBM_READ_ERROR2 -#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10 -#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11 -#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 -#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f -#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L -#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L -#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L -#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L -//GRBM_INT_CNTL -#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 -#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 -#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L -#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L -//GRBM_TRAP_OP -#define GRBM_TRAP_OP__RW__SHIFT 0x0 -#define GRBM_TRAP_OP__RW_MASK 0x00000001L -//GRBM_TRAP_ADDR -#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 -#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL -//GRBM_TRAP_ADDR_MSK -#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 -#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL -//GRBM_TRAP_WD -#define GRBM_TRAP_WD__DATA__SHIFT 0x0 -#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL -//GRBM_TRAP_WD_MSK -#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 -#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL -//GRBM_DSM_BYPASS -#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 -#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 -#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L -#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L -//GRBM_WRITE_ERROR -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1 -#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 -#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 -#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc -#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd -#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 -#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 -#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L -#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL -#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L -#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L -#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L -#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L -#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L -#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L -//GRBM_IOV_ERROR -#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2 -#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14 -#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a -#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b -#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f -#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL -#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L -#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L -#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L -#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L -//GRBM_CHIP_REVISION -#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 -#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL -//GRBM_GFX_CNTL -#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 -#define GRBM_GFX_CNTL__MEID__SHIFT 0x2 -#define GRBM_GFX_CNTL__VMID__SHIFT 0x4 -#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 -#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L -#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL -#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L -#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L -//GRBM_RSMU_CFG -#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0 -#define GRBM_RSMU_CFG__QOS__SHIFT 0xc -#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10 -#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL -#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L -#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L -//GRBM_IH_CREDIT -#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 -#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L -//GRBM_PWR_CNTL2 -#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 -#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 -#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L -#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L -//GRBM_UTCL2_INVAL_RANGE_START -#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 -#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL -//GRBM_UTCL2_INVAL_RANGE_END -#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 -#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL -//GRBM_RSMU_READ_ERROR -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2 -#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14 -#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15 -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL -#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L -#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L -//GRBM_CHICKEN_BITS -#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0 -#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L -//GRBM_NOWHERE -#define GRBM_NOWHERE__DATA__SHIFT 0x0 -#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG0 -#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 -#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG1 -#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 -#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG2 -#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 -#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG3 -#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 -#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG4 -#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 -#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG5 -#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 -#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG6 -#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 -#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG7 -#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 -#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL - - -// addressBlock: gc_cpdec -//CP_CPC_STATUS -#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 -#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 -#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 -#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 -#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 -#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 -#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 -#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 -#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa -#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb -#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc -#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd -#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe -#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d -#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e -#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f -#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L -#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L -#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L -#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L -#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L -#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L -#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L -#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L -#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L -#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L -#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L -#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L -#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L -#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L -#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L -#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L -//CP_CPC_BUSY_STAT -#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 -#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 -#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 -#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 -#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 -#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 -#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 -#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 -#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 -#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 -#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa -#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb -#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc -#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd -#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 -#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 -#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 -#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 -#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 -#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 -#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 -#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 -#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 -#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 -#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a -#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b -#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c -#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d -#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L -#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L -#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L -#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L -#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L -#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L -#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L -#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L -#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L -#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L -#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L -#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L -#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L -#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L -#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L -#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L -#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L -#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L -#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L -#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L -#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L -#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L -#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L -#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L -//CP_CPC_STALLED_STAT1 -#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 -#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 -#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 -#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd -#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 -#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 -#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 -#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 -#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L -#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L -#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L -#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L -#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L -#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L -#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L -#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L -//CP_CPF_STATUS -#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 -#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 -#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 -#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 -#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 -#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 -#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 -#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 -#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa -#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb -#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc -#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd -#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe -#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf -#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 -#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 -#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a -#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b -#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c -#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e -#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f -#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L -#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L -#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L -#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L -#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L -#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L -#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L -#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L -#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L -#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L -#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L -#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L -#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L -#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L -#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L -#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L -#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L -#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L -#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L -#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L -#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L -//CP_CPF_BUSY_STAT -#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 -#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 -#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 -#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 -#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 -#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 -#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 -#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 -#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 -#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 -#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb -#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc -#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd -#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe -#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf -#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 -#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 -#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 -#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 -#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 -#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 -#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 -#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 -#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 -#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 -#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a -#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b -#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c -#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d -#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e -#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f -#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L -#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L -#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L -#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L -#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L -#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L -#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L -#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L -#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L -#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L -#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L -#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L -#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L -#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L -#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L -#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L -#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L -#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L -#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L -#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L -#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L -#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L -#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L -#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L -#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L -#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L -//CP_CPF_STALLED_STAT1 -#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 -#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 -#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 -#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 -#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 -#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 -#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 -#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa -#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb -#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L -#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L -#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L -#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L -#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L -#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L -#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L -#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L -#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L -//CP_CPC_GRBM_FREE_COUNT -#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 -#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL -//CP_MEC_CNTL -#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 -#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 -#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 -#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 -#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 -#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 -#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 -#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c -#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d -#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e -#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f -#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L -#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L -#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L -#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L -#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L -#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L -#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L -#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L -#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L -#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L -#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L -//CP_MEC_ME1_HEADER_DUMP -#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 -#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL -//CP_MEC_ME2_HEADER_DUMP -#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 -#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL -//CP_CPC_SCRATCH_INDEX -#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 -#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL -//CP_CPC_SCRATCH_DATA -#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 -#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL -//CP_CPF_GRBM_FREE_COUNT -#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 -#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L -//CP_CPC_HALT_HYST_COUNT -#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 -#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL -//CP_PRT_LOD_STATS_CNTL0 -#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0 -#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xFFFFFFFFL -//CP_PRT_LOD_STATS_CNTL1 -#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0 -#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xFFFFFFFFL -//CP_PRT_LOD_STATS_CNTL2 -#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0 -#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003FFL -//CP_PRT_LOD_STATS_CNTL3 -#define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x2 -#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa -#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x12 -#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x13 -#define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x17 -#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x1c -#define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003FCL -#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003FC00L -#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L -#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L -#define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L -#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L -//CP_CE_COMPARE_COUNT -#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 -#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL -//CP_CE_DE_COUNT -#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 -#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL -//CP_DE_CE_COUNT -#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 -#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL -//CP_DE_LAST_INVAL_COUNT -#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 -#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL -//CP_DE_DE_COUNT -#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 -#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL -//CP_STALLED_STAT3 -#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 -#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 -#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 -#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 -#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 -#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 -#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa -#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd -#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe -#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf -#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 -#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 -#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 -#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 -#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 -#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L -#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L -#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L -#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L -#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L -#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L -#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L -#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L -#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L -#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L -#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L -#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L -#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L -#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L -#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L -//CP_STALLED_STAT1 -#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 -#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 -#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb -#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc -#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd -#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe -#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 -#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 -#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a -#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b -#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c -#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d -#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L -#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L -#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L -#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L -#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L -#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L -#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L -#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L -#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L -#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L -#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L -#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L -//CP_STALLED_STAT2 -#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 -#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 -#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 -#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 -#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 -#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 -#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 -#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa -#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb -#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc -#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe -#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf -#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 -#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 -#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 -#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 -#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 -#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a -#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b -#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c -#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f -#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L -#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L -#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L -#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L -#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L -#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L -#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L -#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L -#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L -#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L -#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L -#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L -#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L -#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L -#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L -#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L -#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L -#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L -#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L -#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L -#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L -//CP_BUSY_STAT -#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 -#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 -#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 -#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 -#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 -#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa -#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc -#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd -#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe -#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf -#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 -#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 -#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 -#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 -#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 -#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 -#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L -#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L -#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L -#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L -#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L -#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L -#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L -#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L -#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L -#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L -#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L -#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L -#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L -#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L -#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L -#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L -//CP_STAT -#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 -#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa -#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb -#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc -#define CP_STAT__DC_BUSY__SHIFT 0xd -#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe -#define CP_STAT__PFP_BUSY__SHIFT 0xf -#define CP_STAT__MEQ_BUSY__SHIFT 0x10 -#define CP_STAT__ME_BUSY__SHIFT 0x11 -#define CP_STAT__QUERY_BUSY__SHIFT 0x12 -#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 -#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 -#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 -#define CP_STAT__DMA_BUSY__SHIFT 0x16 -#define CP_STAT__RCIU_BUSY__SHIFT 0x17 -#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 -#define CP_STAT__CE_BUSY__SHIFT 0x1a -#define CP_STAT__TCIU_BUSY__SHIFT 0x1b -#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c -#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d -#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e -#define CP_STAT__CP_BUSY__SHIFT 0x1f -#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L -#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L -#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L -#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L -#define CP_STAT__DC_BUSY_MASK 0x00002000L -#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L -#define CP_STAT__PFP_BUSY_MASK 0x00008000L -#define CP_STAT__MEQ_BUSY_MASK 0x00010000L -#define CP_STAT__ME_BUSY_MASK 0x00020000L -#define CP_STAT__QUERY_BUSY_MASK 0x00040000L -#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L -#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L -#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L -#define CP_STAT__DMA_BUSY_MASK 0x00400000L -#define CP_STAT__RCIU_BUSY_MASK 0x00800000L -#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L -#define CP_STAT__CE_BUSY_MASK 0x04000000L -#define CP_STAT__TCIU_BUSY_MASK 0x08000000L -#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L -#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L -#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L -#define CP_STAT__CP_BUSY_MASK 0x80000000L -//CP_ME_HEADER_DUMP -#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 -#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL -//CP_PFP_HEADER_DUMP -#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 -#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL -//CP_GRBM_FREE_COUNT -#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 -#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 -#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 -#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL -#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L -#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L -//CP_CE_HEADER_DUMP -#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 -#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL -//CP_PFP_INSTR_PNTR -#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 -#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL -//CP_ME_INSTR_PNTR -#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 -#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL -//CP_CE_INSTR_PNTR -#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 -#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL -//CP_MEC1_INSTR_PNTR -#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 -#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL -//CP_MEC2_INSTR_PNTR -#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 -#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL -//CP_CSF_STAT -#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 -#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L -//CP_ME_CNTL -#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 -#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 -#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 -#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 -#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 -#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 -#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 -#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 -#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 -#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 -#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 -#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a -#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b -#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c -#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d -#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L -#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L -#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L -#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L -#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L -#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L -#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L -#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L -#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L -#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L -#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L -#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L -#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L -#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L -#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L -//CP_CNTX_STAT -#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 -#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 -#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 -#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c -#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL -#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L -#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L -#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L -//CP_ME_PREEMPTION -#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 -#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L -//CP_ROQ_THRESHOLDS -#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 -#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 -#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL -#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L -//CP_MEQ_STQ_THRESHOLD -#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 -#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL -//CP_RB2_RPTR -#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 -#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL -//CP_RB1_RPTR -#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 -#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL -//CP_RB0_RPTR -#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 -#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL -//CP_RB_RPTR -#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 -#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL -//CP_RB_WPTR_DELAY -#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 -#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c -#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL -#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L -//CP_RB_WPTR_POLL_CNTL -#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 -#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL -#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//CP_ROQ1_THRESHOLDS -#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 -#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 -#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 -#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 -#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL -#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L -#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L -#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L -//CP_ROQ2_THRESHOLDS -#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 -#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 -#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 -#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 -#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL -#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L -#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L -#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L -//CP_STQ_THRESHOLDS -#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 -#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 -#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 -#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL -#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L -#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L -//CP_QUEUE_THRESHOLDS -#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 -#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 -#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL -#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L -//CP_MEQ_THRESHOLDS -#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 -#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 -#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL -#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L -//CP_ROQ_AVAIL -#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 -#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 -#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL -#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L -//CP_STQ_AVAIL -#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 -#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL -//CP_ROQ2_AVAIL -#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 -#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL -//CP_MEQ_AVAIL -#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 -#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL -//CP_CMD_INDEX -#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 -#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc -#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 -#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL -#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L -#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L -//CP_CMD_DATA -#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 -#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL -//CP_ROQ_RB_STAT -#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 -#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 -#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL -#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L -//CP_ROQ_IB1_STAT -#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 -#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 -#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL -#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L -//CP_ROQ_IB2_STAT -#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 -#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 -#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL -#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L -//CP_STQ_STAT -#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 -#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL -//CP_STQ_WR_STAT -#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 -#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL -//CP_MEQ_STAT -#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 -#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 -#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL -#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L -//CP_CEQ1_AVAIL -#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 -#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 -#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL -#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L -//CP_CEQ2_AVAIL -#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 -#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL -//CP_CE_ROQ_RB_STAT -#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 -#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 -#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL -#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L -//CP_CE_ROQ_IB1_STAT -#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 -#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 -#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL -#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L -//CP_CE_ROQ_IB2_STAT -#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 -#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 -#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL -#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L -#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 -#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 -#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L -#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L - - -// addressBlock: gc_padec -//VGT_VTX_VECT_EJECT_REG -#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 -#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL -//VGT_DMA_DATA_FIFO_DEPTH -#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 -#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9 -#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL -#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L -//VGT_DMA_REQ_FIFO_DEPTH -#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 -#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL -//VGT_DRAW_INIT_FIFO_DEPTH -#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 -#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL -//VGT_LAST_COPY_STATE -#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 -#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 -#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L -#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L -//VGT_CACHE_INVALIDATION -#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 -#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 -#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 -#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 -#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 -#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb -#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc -#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd -#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 -#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15 -#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16 -#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19 -#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c -#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d -#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L -#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L -#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L -#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L -#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L -#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L -#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L -#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L -#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L -#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L -#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L -#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L -#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L -#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L -//VGT_STRMOUT_DELAY -#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 -#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 -#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb -#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe -#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 -#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL -#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L -#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L -#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L -#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L -//VGT_FIFO_DEPTHS -#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 -#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 -#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 -#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 -#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL -#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L -#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L -#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L -//VGT_GS_VERTEX_REUSE -#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 -#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL -//VGT_MC_LAT_CNTL -#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 -#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL -//IA_CNTL_STATUS -#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 -#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 -#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 -#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 -#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 -#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L -#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L -#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L -#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L -#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L -//VGT_CNTL_STATUS -#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 -#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 -#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 -#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 -#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 -#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 -#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 -#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 -#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 -#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 -#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa -#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L -#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L -#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L -#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L -#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L -#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L -#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L -#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L -#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L -#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L -#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L -//WD_CNTL_STATUS -#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 -#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 -#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 -#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 -#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L -#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L -#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L -#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L -//CC_GC_PRIM_CONFIG -#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 -#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 -#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L -#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L -//GC_USER_PRIM_CONFIG -#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 -#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 -#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L -#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L -//WD_QOS -#define WD_QOS__DRAW_STALL__SHIFT 0x0 -#define WD_QOS__DRAW_STALL_MASK 0x00000001L -//WD_UTCL1_CNTL -#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 -#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L -#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -//WD_UTCL1_STATUS -#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 -#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 -#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 -#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L -#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L -#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L -//IA_UTCL1_CNTL -#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 -#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L -#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -//IA_UTCL1_STATUS -#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 -#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 -#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 -#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L -#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L -#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L -//VGT_SYS_CONFIG -#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 -#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 -#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 -#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L -#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL -#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L -//VGT_VS_MAX_WAVE_ID -#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 -#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL -//VGT_GS_MAX_WAVE_ID -#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 -#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL -//GFX_PIPE_CONTROL -#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 -#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd -#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 -#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL -#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L -#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L -//CC_GC_SHADER_ARRAY_CONFIG -#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 -#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L -//GC_USER_SHADER_ARRAY_CONFIG -#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 -#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L -//VGT_DMA_PRIMITIVE_TYPE -#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 -#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL -//VGT_DMA_CONTROL -#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 -#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 -#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13 -#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 -#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15 -#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16 -#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17 -#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL -#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L -#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L -#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L -#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L -#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L -#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L -//VGT_DMA_LS_HS_CONFIG -#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 -#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L -//WD_BUF_RESOURCE_1 -#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0 -#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10 -#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL -#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L -//WD_BUF_RESOURCE_2 -#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0 -#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf -#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10 -#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL -#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L -#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L -//PA_CL_CNTL_STATUS -#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0 -#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1 -#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2 -#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L -#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L -#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L -//PA_CL_ENHANCE -#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 -#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 -#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 -#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 -#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 -#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 -#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 -#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 -#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb -#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc -#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe -#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c -#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d -#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e -#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f -#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L -#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L -#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L -#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L -#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L -#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L -#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L -#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L -#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L -#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L -#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L -#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L -#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L -#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L -#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L -//PA_SU_CNTL_STATUS -#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f -#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L -//PA_SC_FIFO_DEPTH_CNTL -#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 -#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL -//PA_SC_P3D_TRAP_SCREEN_HV_LOCK -#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 -#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L -//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK -#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 -#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L -//PA_SC_TRAP_SCREEN_HV_LOCK -#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 -#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L -//PA_SC_FORCE_EOV_MAX_CNTS -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L -//PA_SC_BINNER_EVENT_CNTL_0 -#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 -#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 -#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa -#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc -#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe -#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 -#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 -#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 -#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 -#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 -#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a -#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c -#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e -#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L -#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L -#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L -#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L -#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L -#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L -#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L -#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L -#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L -#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L -#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L -#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L -#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L -//PA_SC_BINNER_EVENT_CNTL_1 -#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 -#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 -#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 -#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa -#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 -#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 -#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a -#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c -#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e -#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L -#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L -#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L -#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L -#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L -#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L -#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L -#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L -#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L -//PA_SC_BINNER_EVENT_CNTL_2 -#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 -#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 -#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 -#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6 -#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 -#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa -#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc -#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe -#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12 -#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c -#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e -#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L -#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL -#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L -#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L -#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L -#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L -#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L -#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L -#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L -#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L -#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L -//PA_SC_BINNER_EVENT_CNTL_3 -#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 -#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 -#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4 -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 -#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 -#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 -#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a -#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c -#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e -#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L -#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL -#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L -#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L -#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L -#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L -#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L -#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L -//PA_SC_BINNER_TIMEOUT_COUNTER -#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 -#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL -//PA_SC_BINNER_PERF_CNTL_0 -#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 -#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa -#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 -#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 -#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL -#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L -#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L -#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L -//PA_SC_BINNER_PERF_CNTL_1 -#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 -#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 -#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa -#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL -#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L -#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L -//PA_SC_BINNER_PERF_CNTL_2 -#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 -#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb -#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL -#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L -//PA_SC_BINNER_PERF_CNTL_3 -#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 -#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL -//PA_SC_FIFO_SIZE -#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 -#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 -#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf -#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 -#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL -#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L -#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L -#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L -//PA_SC_IF_FIFO_SIZE -#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 -#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 -#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc -#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 -#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL -#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L -#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L -#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L -//PA_SC_PKR_WAVE_TABLE_CNTL -#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 -#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL -//PA_UTCL1_CNTL1 -#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 -#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 -#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 -#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 -#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 -#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 -#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10 -#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 -#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 -#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 -#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 -#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 -#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19 -#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a -#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b -#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L -#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L -#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L -#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L -#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L -#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L -#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L -#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//PA_UTCL1_CNTL2 -#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0 -#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8 -#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 -#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa -#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb -#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc -#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd -#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe -#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf -#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10 -#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 -#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 -#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 -#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 -#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19 -#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a -#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b -#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL -#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L -#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L -#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L -#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L -#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L -#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L -#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L -#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L -#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L -#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L -//PA_SIDEBAND_REQUEST_DELAYS -#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0 -#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10 -#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL -#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L -//PA_SC_ENHANCE -#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 -#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 -#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 -#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 -#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 -#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa -#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb -#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc -#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 -#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 -#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 -#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 -#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a -#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b -#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c -#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d -#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L -#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L -#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L -#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L -#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L -#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L -#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L -#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L -#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L -#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L -#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L -#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L -#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L -#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L -#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L -#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L -//PA_SC_ENHANCE_1 -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 -#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 -#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 -#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5 -#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 -#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 -#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 -#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 -#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa -#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb -#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd -#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe -#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf -#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 -#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11 -#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 -#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 -#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 -#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 -#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 -#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x17 -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L -#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L -#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L -#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L -#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L -#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L -#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L -#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L -#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L -#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L -#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L -#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L -#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L -#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L -#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L -#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L -#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L -#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L -#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L -#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L -#define PA_SC_ENHANCE_1__RSVD_MASK 0xFF800000L -//PA_SC_DSM_CNTL -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L -//PA_SC_TILE_STEERING_CREST_OVERRIDE -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L - - -// addressBlock: gc_sqdec -//SQ_CONFIG -#define SQ_CONFIG__UNUSED__SHIFT 0x0 -#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7 -#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb -#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc -#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd -#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe -#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf -#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 -#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 -#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 -#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 -#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 -#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c -#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d -#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e -#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f -#define SQ_CONFIG__UNUSED_MASK 0x0000007FL -#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L -#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L -#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L -#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L -#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L -#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L -#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L -#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L -#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L -#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L -#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L -#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L -#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L -#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L -#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L -//SQC_CONFIG -#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 -#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 -#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 -#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 -#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 -#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 -#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 -#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa -#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb -#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc -#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe -#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf -#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 -#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18 -#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a -#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L -#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL -#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L -#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L -#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L -#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L -#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L -#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L -#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L -#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L -#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L -#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L -#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L -#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L -#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L -//LDS_CONFIG -#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 -#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L -//SQ_RANDOM_WAVE_PRI -#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 -#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 -#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa -#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL -#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L -#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L -//SQ_REG_CREDITS -#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 -#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 -#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c -#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d -#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e -#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f -#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL -#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L -#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L -#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L -#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L -#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L -//SQ_FIFO_SIZES -#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 -#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 -#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 -#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 -#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL -#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L -#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L -#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L -//SQ_DSM_CNTL -#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 -#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 -#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 -#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a -#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L -#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L -#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L -#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L -//SQ_DSM_CNTL2 -#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 -#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 -#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 -#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb -#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe -#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 -#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a -#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L -#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L -#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L -#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L -#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L -#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L -//SQ_RUNTIME_CONFIG -#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0 -#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L -//SH_MEM_BASES -#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 -#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 -#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL -#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L -//SH_MEM_CONFIG -#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 -#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 -#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc -#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd -#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L -#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L -#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L -#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L -//CC_GC_SHADER_RATE_CONFIG -#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 -#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 -#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 -#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L -#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L -#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L -//GC_USER_SHADER_RATE_CONFIG -#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 -#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 -#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 -#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L -#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L -#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L -//SQ_INTERRUPT_AUTO_MASK -#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 -#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL -//SQ_INTERRUPT_MSG_CTRL -#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 -#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L -//SQ_UTCL1_CNTL1 -#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 -#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 -#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 -#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 -#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 -#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 -#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 -#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 -#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19 -#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a -#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b -#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L -#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L -#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L -#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L -#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//SQ_UTCL1_CNTL2 -#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0 -#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 -#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 -#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa -#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb -#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc -#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd -#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe -#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf -#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10 -#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a -#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c -#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL -#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L -#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L -#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L -#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L -#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L -//SQ_UTCL1_STATUS -#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3 -#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10 -#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L -#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L -//SQ_SHADER_TBA_LO -#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 -#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL -//SQ_SHADER_TBA_HI -#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 -#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL -//SQ_SHADER_TMA_LO -#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 -#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL -//SQ_SHADER_TMA_HI -#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 -#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL -//SQC_DSM_CNTL -#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc -#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf -#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L -//SQC_DSM_CNTLA -#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc -#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf -#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 -#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 -#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 -#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a -#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L -#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L -#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L -#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L -#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L -//SQC_DSM_CNTLB -#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc -#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf -#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 -#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 -#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 -#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a -#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L -#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L -#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L -#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L -#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L -//SQC_DSM_CNTL2 -#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2 -#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5 -#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8 -#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb -#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc -#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe -#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf -#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11 -#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14 -#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a -#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L -#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L -#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L -#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L -#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L -#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L -#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L -//SQC_DSM_CNTL2A -#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 -#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 -#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb -#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe -#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf -#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 -#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 -#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 -#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 -#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 -#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a -#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L -#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L -#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L -#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L -#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L -#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L -#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L -//SQC_DSM_CNTL2B -#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 -#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 -#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb -#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe -#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf -#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 -#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 -#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 -#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 -#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 -#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a -#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L -#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L -#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L -#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L -#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L -#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L -#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L -//SQC_EDC_FUE_CNTL -#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 -#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 -#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL -#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L -//SQC_EDC_CNT2 -#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0 -#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2 -#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4 -#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6 -#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8 -#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa -#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc -#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe -#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10 -#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x12 -#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x14 -#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x16 -#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18 -#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1a -#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1c -#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L -#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL -#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L -#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L -#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L -#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L -#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L -#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L -#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L -#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000C0000L -#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L -#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00C00000L -#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L -#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0C000000L -#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L -//SQC_EDC_CNT3 -#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0 -#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2 -#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4 -#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6 -#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8 -#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa -#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc -#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe -#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10 -#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x12 -#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x14 -#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x16 -#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18 -#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L -#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL -#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L -#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L -#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L -#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L -#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L -#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L -#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L -#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000C0000L -#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L -#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00C00000L -#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L -//SQ_REG_TIMESTAMP -#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 -#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL -//SQ_CMD_TIMESTAMP -#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 -#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL -//SQ_IND_INDEX -#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 -#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 -#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 -#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc -#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd -#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe -#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf -#define SQ_IND_INDEX__INDEX__SHIFT 0x10 -#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL -#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L -#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L -#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L -#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L -#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L -#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L -#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L -//SQ_IND_DATA -#define SQ_IND_DATA__DATA__SHIFT 0x0 -#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL -//SQ_CMD -#define SQ_CMD__CMD__SHIFT 0x0 -#define SQ_CMD__MODE__SHIFT 0x4 -#define SQ_CMD__CHECK_VMID__SHIFT 0x7 -#define SQ_CMD__DATA__SHIFT 0x8 -#define SQ_CMD__WAVE_ID__SHIFT 0x10 -#define SQ_CMD__SIMD_ID__SHIFT 0x14 -#define SQ_CMD__QUEUE_ID__SHIFT 0x18 -#define SQ_CMD__VM_ID__SHIFT 0x1c -#define SQ_CMD__CMD_MASK 0x00000007L -#define SQ_CMD__MODE_MASK 0x00000070L -#define SQ_CMD__CHECK_VMID_MASK 0x00000080L -#define SQ_CMD__DATA_MASK 0x00000F00L -#define SQ_CMD__WAVE_ID_MASK 0x000F0000L -#define SQ_CMD__SIMD_ID_MASK 0x00300000L -#define SQ_CMD__QUEUE_ID_MASK 0x07000000L -#define SQ_CMD__VM_ID_MASK 0xF0000000L -//SQ_TIME_HI -#define SQ_TIME_HI__TIME__SHIFT 0x0 -#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL -//SQ_TIME_LO -#define SQ_TIME_LO__TIME__SHIFT 0x0 -#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL -//SQ_DS_0 -#define SQ_DS_0__OFFSET0__SHIFT 0x0 -#define SQ_DS_0__OFFSET1__SHIFT 0x8 -#define SQ_DS_0__GDS__SHIFT 0x10 -#define SQ_DS_0__OP__SHIFT 0x11 -#define SQ_DS_0__ENCODING__SHIFT 0x1a -#define SQ_DS_0__OFFSET0_MASK 0x000000FFL -#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L -#define SQ_DS_0__GDS_MASK 0x00010000L -#define SQ_DS_0__OP_MASK 0x01FE0000L -#define SQ_DS_0__ENCODING_MASK 0xFC000000L -//SQ_DS_1 -#define SQ_DS_1__ADDR__SHIFT 0x0 -#define SQ_DS_1__DATA0__SHIFT 0x8 -#define SQ_DS_1__DATA1__SHIFT 0x10 -#define SQ_DS_1__VDST__SHIFT 0x18 -#define SQ_DS_1__ADDR_MASK 0x000000FFL -#define SQ_DS_1__DATA0_MASK 0x0000FF00L -#define SQ_DS_1__DATA1_MASK 0x00FF0000L -#define SQ_DS_1__VDST_MASK 0xFF000000L -//SQ_EXP_0 -#define SQ_EXP_0__EN__SHIFT 0x0 -#define SQ_EXP_0__TGT__SHIFT 0x4 -#define SQ_EXP_0__COMPR__SHIFT 0xa -#define SQ_EXP_0__DONE__SHIFT 0xb -#define SQ_EXP_0__VM__SHIFT 0xc -#define SQ_EXP_0__ENCODING__SHIFT 0x1a -#define SQ_EXP_0__EN_MASK 0x0000000FL -#define SQ_EXP_0__TGT_MASK 0x000003F0L -#define SQ_EXP_0__COMPR_MASK 0x00000400L -#define SQ_EXP_0__DONE_MASK 0x00000800L -#define SQ_EXP_0__VM_MASK 0x00001000L -#define SQ_EXP_0__ENCODING_MASK 0xFC000000L -//SQ_EXP_1 -#define SQ_EXP_1__VSRC0__SHIFT 0x0 -#define SQ_EXP_1__VSRC1__SHIFT 0x8 -#define SQ_EXP_1__VSRC2__SHIFT 0x10 -#define SQ_EXP_1__VSRC3__SHIFT 0x18 -#define SQ_EXP_1__VSRC0_MASK 0x000000FFL -#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L -#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L -#define SQ_EXP_1__VSRC3_MASK 0xFF000000L -//SQ_FLAT_0 -#define SQ_FLAT_0__OFFSET__SHIFT 0x0 -#define SQ_FLAT_0__LDS__SHIFT 0xd -#define SQ_FLAT_0__SEG__SHIFT 0xe -#define SQ_FLAT_0__GLC__SHIFT 0x10 -#define SQ_FLAT_0__SLC__SHIFT 0x11 -#define SQ_FLAT_0__OP__SHIFT 0x12 -#define SQ_FLAT_0__ENCODING__SHIFT 0x1a -#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL -#define SQ_FLAT_0__LDS_MASK 0x00002000L -#define SQ_FLAT_0__SEG_MASK 0x0000C000L -#define SQ_FLAT_0__GLC_MASK 0x00010000L -#define SQ_FLAT_0__SLC_MASK 0x00020000L -#define SQ_FLAT_0__OP_MASK 0x01FC0000L -#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L -//SQ_FLAT_1 -#define SQ_FLAT_1__ADDR__SHIFT 0x0 -#define SQ_FLAT_1__DATA__SHIFT 0x8 -#define SQ_FLAT_1__SADDR__SHIFT 0x10 -#define SQ_FLAT_1__NV__SHIFT 0x17 -#define SQ_FLAT_1__VDST__SHIFT 0x18 -#define SQ_FLAT_1__ADDR_MASK 0x000000FFL -#define SQ_FLAT_1__DATA_MASK 0x0000FF00L -#define SQ_FLAT_1__SADDR_MASK 0x007F0000L -#define SQ_FLAT_1__NV_MASK 0x00800000L -#define SQ_FLAT_1__VDST_MASK 0xFF000000L -//SQ_GLBL_0 -#define SQ_GLBL_0__OFFSET__SHIFT 0x0 -#define SQ_GLBL_0__LDS__SHIFT 0xd -#define SQ_GLBL_0__SEG__SHIFT 0xe -#define SQ_GLBL_0__GLC__SHIFT 0x10 -#define SQ_GLBL_0__SLC__SHIFT 0x11 -#define SQ_GLBL_0__OP__SHIFT 0x12 -#define SQ_GLBL_0__ENCODING__SHIFT 0x1a -#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL -#define SQ_GLBL_0__LDS_MASK 0x00002000L -#define SQ_GLBL_0__SEG_MASK 0x0000C000L -#define SQ_GLBL_0__GLC_MASK 0x00010000L -#define SQ_GLBL_0__SLC_MASK 0x00020000L -#define SQ_GLBL_0__OP_MASK 0x01FC0000L -#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L -//SQ_GLBL_1 -#define SQ_GLBL_1__ADDR__SHIFT 0x0 -#define SQ_GLBL_1__DATA__SHIFT 0x8 -#define SQ_GLBL_1__SADDR__SHIFT 0x10 -#define SQ_GLBL_1__NV__SHIFT 0x17 -#define SQ_GLBL_1__VDST__SHIFT 0x18 -#define SQ_GLBL_1__ADDR_MASK 0x000000FFL -#define SQ_GLBL_1__DATA_MASK 0x0000FF00L -#define SQ_GLBL_1__SADDR_MASK 0x007F0000L -#define SQ_GLBL_1__NV_MASK 0x00800000L -#define SQ_GLBL_1__VDST_MASK 0xFF000000L -//SQ_INST -#define SQ_INST__ENCODING__SHIFT 0x0 -#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL -//SQ_MIMG_0 -#define SQ_MIMG_0__OPM__SHIFT 0x0 -#define SQ_MIMG_0__DMASK__SHIFT 0x8 -#define SQ_MIMG_0__UNORM__SHIFT 0xc -#define SQ_MIMG_0__GLC__SHIFT 0xd -#define SQ_MIMG_0__DA__SHIFT 0xe -#define SQ_MIMG_0__A16__SHIFT 0xf -#define SQ_MIMG_0__TFE__SHIFT 0x10 -#define SQ_MIMG_0__LWE__SHIFT 0x11 -#define SQ_MIMG_0__OP__SHIFT 0x12 -#define SQ_MIMG_0__SLC__SHIFT 0x19 -#define SQ_MIMG_0__ENCODING__SHIFT 0x1a -#define SQ_MIMG_0__OPM_MASK 0x00000001L -#define SQ_MIMG_0__DMASK_MASK 0x00000F00L -#define SQ_MIMG_0__UNORM_MASK 0x00001000L -#define SQ_MIMG_0__GLC_MASK 0x00002000L -#define SQ_MIMG_0__DA_MASK 0x00004000L -#define SQ_MIMG_0__A16_MASK 0x00008000L -#define SQ_MIMG_0__TFE_MASK 0x00010000L -#define SQ_MIMG_0__LWE_MASK 0x00020000L -#define SQ_MIMG_0__OP_MASK 0x01FC0000L -#define SQ_MIMG_0__SLC_MASK 0x02000000L -#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L -//SQ_MIMG_1 -#define SQ_MIMG_1__VADDR__SHIFT 0x0 -#define SQ_MIMG_1__VDATA__SHIFT 0x8 -#define SQ_MIMG_1__SRSRC__SHIFT 0x10 -#define SQ_MIMG_1__SSAMP__SHIFT 0x15 -#define SQ_MIMG_1__D16__SHIFT 0x1f -#define SQ_MIMG_1__VADDR_MASK 0x000000FFL -#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L -#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L -#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L -#define SQ_MIMG_1__D16_MASK 0x80000000L -//SQ_MTBUF_0 -#define SQ_MTBUF_0__OFFSET__SHIFT 0x0 -#define SQ_MTBUF_0__OFFEN__SHIFT 0xc -#define SQ_MTBUF_0__IDXEN__SHIFT 0xd -#define SQ_MTBUF_0__GLC__SHIFT 0xe -#define SQ_MTBUF_0__OP__SHIFT 0xf -#define SQ_MTBUF_0__DFMT__SHIFT 0x13 -#define SQ_MTBUF_0__NFMT__SHIFT 0x17 -#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a -#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL -#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L -#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L -#define SQ_MTBUF_0__GLC_MASK 0x00004000L -#define SQ_MTBUF_0__OP_MASK 0x00078000L -#define SQ_MTBUF_0__DFMT_MASK 0x00780000L -#define SQ_MTBUF_0__NFMT_MASK 0x03800000L -#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L -//SQ_MTBUF_1 -#define SQ_MTBUF_1__VADDR__SHIFT 0x0 -#define SQ_MTBUF_1__VDATA__SHIFT 0x8 -#define SQ_MTBUF_1__SRSRC__SHIFT 0x10 -#define SQ_MTBUF_1__SLC__SHIFT 0x16 -#define SQ_MTBUF_1__TFE__SHIFT 0x17 -#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 -#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL -#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L -#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L -#define SQ_MTBUF_1__SLC_MASK 0x00400000L -#define SQ_MTBUF_1__TFE_MASK 0x00800000L -#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L -//SQ_MUBUF_0 -#define SQ_MUBUF_0__OFFSET__SHIFT 0x0 -#define SQ_MUBUF_0__OFFEN__SHIFT 0xc -#define SQ_MUBUF_0__IDXEN__SHIFT 0xd -#define SQ_MUBUF_0__GLC__SHIFT 0xe -#define SQ_MUBUF_0__LDS__SHIFT 0x10 -#define SQ_MUBUF_0__SLC__SHIFT 0x11 -#define SQ_MUBUF_0__OP__SHIFT 0x12 -#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a -#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL -#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L -#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L -#define SQ_MUBUF_0__GLC_MASK 0x00004000L -#define SQ_MUBUF_0__LDS_MASK 0x00010000L -#define SQ_MUBUF_0__SLC_MASK 0x00020000L -#define SQ_MUBUF_0__OP_MASK 0x01FC0000L -#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L -//SQ_MUBUF_1 -#define SQ_MUBUF_1__VADDR__SHIFT 0x0 -#define SQ_MUBUF_1__VDATA__SHIFT 0x8 -#define SQ_MUBUF_1__SRSRC__SHIFT 0x10 -#define SQ_MUBUF_1__TFE__SHIFT 0x17 -#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 -#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL -#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L -#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L -#define SQ_MUBUF_1__TFE_MASK 0x00800000L -#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L -//SQ_SCRATCH_0 -#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0 -#define SQ_SCRATCH_0__LDS__SHIFT 0xd -#define SQ_SCRATCH_0__SEG__SHIFT 0xe -#define SQ_SCRATCH_0__GLC__SHIFT 0x10 -#define SQ_SCRATCH_0__SLC__SHIFT 0x11 -#define SQ_SCRATCH_0__OP__SHIFT 0x12 -#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a -#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL -#define SQ_SCRATCH_0__LDS_MASK 0x00002000L -#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L -#define SQ_SCRATCH_0__GLC_MASK 0x00010000L -#define SQ_SCRATCH_0__SLC_MASK 0x00020000L -#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L -#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L -//SQ_SCRATCH_1 -#define SQ_SCRATCH_1__ADDR__SHIFT 0x0 -#define SQ_SCRATCH_1__DATA__SHIFT 0x8 -#define SQ_SCRATCH_1__SADDR__SHIFT 0x10 -#define SQ_SCRATCH_1__NV__SHIFT 0x17 -#define SQ_SCRATCH_1__VDST__SHIFT 0x18 -#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL -#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L -#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L -#define SQ_SCRATCH_1__NV_MASK 0x00800000L -#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L -//SQ_SMEM_0 -#define SQ_SMEM_0__SBASE__SHIFT 0x0 -#define SQ_SMEM_0__SDATA__SHIFT 0x6 -#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe -#define SQ_SMEM_0__NV__SHIFT 0xf -#define SQ_SMEM_0__GLC__SHIFT 0x10 -#define SQ_SMEM_0__IMM__SHIFT 0x11 -#define SQ_SMEM_0__OP__SHIFT 0x12 -#define SQ_SMEM_0__ENCODING__SHIFT 0x1a -#define SQ_SMEM_0__SBASE_MASK 0x0000003FL -#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L -#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L -#define SQ_SMEM_0__NV_MASK 0x00008000L -#define SQ_SMEM_0__GLC_MASK 0x00010000L -#define SQ_SMEM_0__IMM_MASK 0x00020000L -#define SQ_SMEM_0__OP_MASK 0x03FC0000L -#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L -//SQ_SMEM_1 -#define SQ_SMEM_1__OFFSET__SHIFT 0x0 -#define SQ_SMEM_1__SOFFSET__SHIFT 0x19 -#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL -#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L -//SQ_SOP1 -#define SQ_SOP1__SSRC0__SHIFT 0x0 -#define SQ_SOP1__OP__SHIFT 0x8 -#define SQ_SOP1__SDST__SHIFT 0x10 -#define SQ_SOP1__ENCODING__SHIFT 0x17 -#define SQ_SOP1__SSRC0_MASK 0x000000FFL -#define SQ_SOP1__OP_MASK 0x0000FF00L -#define SQ_SOP1__SDST_MASK 0x007F0000L -#define SQ_SOP1__ENCODING_MASK 0xFF800000L -//SQ_SOP2 -#define SQ_SOP2__SSRC0__SHIFT 0x0 -#define SQ_SOP2__SSRC1__SHIFT 0x8 -#define SQ_SOP2__SDST__SHIFT 0x10 -#define SQ_SOP2__OP__SHIFT 0x17 -#define SQ_SOP2__ENCODING__SHIFT 0x1e -#define SQ_SOP2__SSRC0_MASK 0x000000FFL -#define SQ_SOP2__SSRC1_MASK 0x0000FF00L -#define SQ_SOP2__SDST_MASK 0x007F0000L -#define SQ_SOP2__OP_MASK 0x3F800000L -#define SQ_SOP2__ENCODING_MASK 0xC0000000L -//SQ_SOPC -#define SQ_SOPC__SSRC0__SHIFT 0x0 -#define SQ_SOPC__SSRC1__SHIFT 0x8 -#define SQ_SOPC__OP__SHIFT 0x10 -#define SQ_SOPC__ENCODING__SHIFT 0x17 -#define SQ_SOPC__SSRC0_MASK 0x000000FFL -#define SQ_SOPC__SSRC1_MASK 0x0000FF00L -#define SQ_SOPC__OP_MASK 0x007F0000L -#define SQ_SOPC__ENCODING_MASK 0xFF800000L -//SQ_SOPK -#define SQ_SOPK__SIMM16__SHIFT 0x0 -#define SQ_SOPK__SDST__SHIFT 0x10 -#define SQ_SOPK__OP__SHIFT 0x17 -#define SQ_SOPK__ENCODING__SHIFT 0x1c -#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL -#define SQ_SOPK__SDST_MASK 0x007F0000L -#define SQ_SOPK__OP_MASK 0x0F800000L -#define SQ_SOPK__ENCODING_MASK 0xF0000000L -//SQ_SOPP -#define SQ_SOPP__SIMM16__SHIFT 0x0 -#define SQ_SOPP__OP__SHIFT 0x10 -#define SQ_SOPP__ENCODING__SHIFT 0x17 -#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL -#define SQ_SOPP__OP_MASK 0x007F0000L -#define SQ_SOPP__ENCODING_MASK 0xFF800000L -//SQ_VINTRP -#define SQ_VINTRP__VSRC__SHIFT 0x0 -#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 -#define SQ_VINTRP__ATTR__SHIFT 0xa -#define SQ_VINTRP__OP__SHIFT 0x10 -#define SQ_VINTRP__VDST__SHIFT 0x12 -#define SQ_VINTRP__ENCODING__SHIFT 0x1a -#define SQ_VINTRP__VSRC_MASK 0x000000FFL -#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L -#define SQ_VINTRP__ATTR_MASK 0x0000FC00L -#define SQ_VINTRP__OP_MASK 0x00030000L -#define SQ_VINTRP__VDST_MASK 0x03FC0000L -#define SQ_VINTRP__ENCODING_MASK 0xFC000000L -//SQ_VOP1 -#define SQ_VOP1__SRC0__SHIFT 0x0 -#define SQ_VOP1__OP__SHIFT 0x9 -#define SQ_VOP1__VDST__SHIFT 0x11 -#define SQ_VOP1__ENCODING__SHIFT 0x19 -#define SQ_VOP1__SRC0_MASK 0x000001FFL -#define SQ_VOP1__OP_MASK 0x0001FE00L -#define SQ_VOP1__VDST_MASK 0x01FE0000L -#define SQ_VOP1__ENCODING_MASK 0xFE000000L -//SQ_VOP2 -#define SQ_VOP2__SRC0__SHIFT 0x0 -#define SQ_VOP2__VSRC1__SHIFT 0x9 -#define SQ_VOP2__VDST__SHIFT 0x11 -#define SQ_VOP2__OP__SHIFT 0x19 -#define SQ_VOP2__ENCODING__SHIFT 0x1f -#define SQ_VOP2__SRC0_MASK 0x000001FFL -#define SQ_VOP2__VSRC1_MASK 0x0001FE00L -#define SQ_VOP2__VDST_MASK 0x01FE0000L -#define SQ_VOP2__OP_MASK 0x7E000000L -#define SQ_VOP2__ENCODING_MASK 0x80000000L -//SQ_VOP3P_0 -#define SQ_VOP3P_0__VDST__SHIFT 0x0 -#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8 -#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb -#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe -#define SQ_VOP3P_0__CLAMP__SHIFT 0xf -#define SQ_VOP3P_0__OP__SHIFT 0x10 -#define SQ_VOP3P_0__ENCODING__SHIFT 0x17 -#define SQ_VOP3P_0__VDST_MASK 0x000000FFL -#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L -#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L -#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L -#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L -#define SQ_VOP3P_0__OP_MASK 0x007F0000L -#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L -//SQ_VOP3P_1 -#define SQ_VOP3P_1__SRC0__SHIFT 0x0 -#define SQ_VOP3P_1__SRC1__SHIFT 0x9 -#define SQ_VOP3P_1__SRC2__SHIFT 0x12 -#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b -#define SQ_VOP3P_1__NEG__SHIFT 0x1d -#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL -#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L -#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L -#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L -#define SQ_VOP3P_1__NEG_MASK 0xE0000000L -//SQ_VOP3_0 -#define SQ_VOP3_0__VDST__SHIFT 0x0 -#define SQ_VOP3_0__ABS__SHIFT 0x8 -#define SQ_VOP3_0__OP_SEL__SHIFT 0xb -#define SQ_VOP3_0__CLAMP__SHIFT 0xf -#define SQ_VOP3_0__OP__SHIFT 0x10 -#define SQ_VOP3_0__ENCODING__SHIFT 0x1a -#define SQ_VOP3_0__VDST_MASK 0x000000FFL -#define SQ_VOP3_0__ABS_MASK 0x00000700L -#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L -#define SQ_VOP3_0__CLAMP_MASK 0x00008000L -#define SQ_VOP3_0__OP_MASK 0x03FF0000L -#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L -//SQ_VOP3_0_SDST_ENC -#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 -#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 -#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf -#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 -#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a -#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL -#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L -#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L -#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L -#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L -//SQ_VOP3_1 -#define SQ_VOP3_1__SRC0__SHIFT 0x0 -#define SQ_VOP3_1__SRC1__SHIFT 0x9 -#define SQ_VOP3_1__SRC2__SHIFT 0x12 -#define SQ_VOP3_1__OMOD__SHIFT 0x1b -#define SQ_VOP3_1__NEG__SHIFT 0x1d -#define SQ_VOP3_1__SRC0_MASK 0x000001FFL -#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L -#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L -#define SQ_VOP3_1__OMOD_MASK 0x18000000L -#define SQ_VOP3_1__NEG_MASK 0xE0000000L -//SQ_VOPC -#define SQ_VOPC__SRC0__SHIFT 0x0 -#define SQ_VOPC__VSRC1__SHIFT 0x9 -#define SQ_VOPC__OP__SHIFT 0x11 -#define SQ_VOPC__ENCODING__SHIFT 0x19 -#define SQ_VOPC__SRC0_MASK 0x000001FFL -#define SQ_VOPC__VSRC1_MASK 0x0001FE00L -#define SQ_VOPC__OP_MASK 0x01FE0000L -#define SQ_VOPC__ENCODING_MASK 0xFE000000L -//SQ_VOP_DPP -#define SQ_VOP_DPP__SRC0__SHIFT 0x0 -#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 -#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 -#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 -#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 -#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 -#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 -#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 -#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c -#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL -#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L -#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L -#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L -#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L -#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L -#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L -#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L -#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L -//SQ_VOP_SDWA -#define SQ_VOP_SDWA__SRC0__SHIFT 0x0 -#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 -#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb -#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd -#define SQ_VOP_SDWA__OMOD__SHIFT 0xe -#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 -#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 -#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 -#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 -#define SQ_VOP_SDWA__S0__SHIFT 0x17 -#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 -#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b -#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c -#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d -#define SQ_VOP_SDWA__S1__SHIFT 0x1f -#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL -#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L -#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L -#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L -#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L -#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L -#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L -#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L -#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L -#define SQ_VOP_SDWA__S0_MASK 0x00800000L -#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L -#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L -#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L -#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L -#define SQ_VOP_SDWA__S1_MASK 0x80000000L -//SQ_VOP_SDWA_SDST_ENC -#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0 -#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8 -#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf -#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10 -#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13 -#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14 -#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15 -#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17 -#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18 -#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b -#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c -#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d -#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f -#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL -#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L -#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L -#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L -#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L -#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L -#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L -#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L -#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L -#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L -#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L -#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L -#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L -//SQ_LB_CTR_CTRL -#define SQ_LB_CTR_CTRL__START__SHIFT 0x0 -#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 -#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 -#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L -#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L -#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L -//SQ_LB_DATA0 -#define SQ_LB_DATA0__DATA__SHIFT 0x0 -#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL -//SQ_LB_DATA1 -#define SQ_LB_DATA1__DATA__SHIFT 0x0 -#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL -//SQ_LB_DATA2 -#define SQ_LB_DATA2__DATA__SHIFT 0x0 -#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL -//SQ_LB_DATA3 -#define SQ_LB_DATA3__DATA__SHIFT 0x0 -#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL -//SQ_LB_CTR_SEL -#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0 -#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4 -#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8 -#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc -#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL -#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L -#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L -#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L -//SQ_LB_CTR0_CU -#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0 -#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10 -#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL -#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L -//SQ_LB_CTR1_CU -#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0 -#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10 -#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL -#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L -//SQ_LB_CTR2_CU -#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0 -#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10 -#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL -#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L -//SQ_LB_CTR3_CU -#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0 -#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10 -#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL -#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L -//SQC_EDC_CNT -#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0 -#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2 -#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4 -#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6 -#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8 -#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa -#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc -#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe -#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10 -#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12 -#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14 -#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16 -#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18 -#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a -#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c -#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e -#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L -#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL -#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L -#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L -#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L -#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L -#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L -#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L -#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L -#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L -#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L -#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L -#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L -#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L -#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L -#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L -//SQ_EDC_SEC_CNT -#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 -#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 -#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 -#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL -#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L -#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L -//SQ_EDC_DED_CNT -#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 -#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 -#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 -#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL -#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L -#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L -//SQ_EDC_INFO -#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 -#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 -#define SQ_EDC_INFO__SOURCE__SHIFT 0x6 -#define SQ_EDC_INFO__VM_ID__SHIFT 0x9 -#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL -#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L -#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L -#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L -//SQ_EDC_CNT -#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0 -#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2 -#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4 -#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6 -#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8 -#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa -#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc -#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe -#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10 -#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12 -#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14 -#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16 -#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18 -#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a -#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L -#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL -#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L -#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L -#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L -#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L -#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L -#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L -#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L -#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L -#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L -#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L -#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L -#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L -//SQ_EDC_FUE_CNTL -#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 -#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 -#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL -#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_WORD_CMN -#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL -#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L -//SQ_THREAD_TRACE_WORD_EVENT -#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 -#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL -#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L -#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L -#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L -#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L -//SQ_THREAD_TRACE_WORD_INST -#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 -#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb -#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL -#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L -#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L -#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L -#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L -//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_WORD_ISSUE -#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc -#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe -#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a -#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L -//SQ_THREAD_TRACE_WORD_MISC -#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc -#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd -#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL -#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L -#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L -#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L -//SQ_THREAD_TRACE_WORD_PERF_1_OF_2 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L -//SQ_THREAD_TRACE_WORD_REG_1_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_WORD_REG_2_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL -//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_WORD_WAVE -#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 -#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe -#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL -#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L -#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L -#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L -#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L -#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L -//SQ_THREAD_TRACE_WORD_WAVE_START -#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 -#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe -#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 -#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 -#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d -#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L -#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L -#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L -//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL -//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL -//SQ_THREAD_TRACE_WORD_PERF_2_OF_2 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L -//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL -//SQ_WREXEC_EXEC_HI -#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 -#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a -#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b -#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c -#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f -#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL -#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L -#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L -#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L -#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L -//SQ_WREXEC_EXEC_LO -#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 -#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL -//SQ_BUF_RSRC_WORD0 -#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 -#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL -//SQ_BUF_RSRC_WORD1 -#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 -#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 -#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e -#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f -#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL -#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L -#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L -#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L -//SQ_BUF_RSRC_WORD2 -#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 -#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL -//SQ_BUF_RSRC_WORD3 -#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 -#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 -#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 -#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 -#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc -#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf -#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13 -#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14 -#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 -#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 -#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b -#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e -#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L -#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L -#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L -#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L -#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L -#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L -#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L -#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L -#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L -#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L -#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L -#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L -//SQ_IMG_RSRC_WORD0 -#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL -//SQ_IMG_RSRC_WORD1 -#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 -#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 -#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a -#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e -#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f -#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL -#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L -#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L -#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L -#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L -#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L -//SQ_IMG_RSRC_WORD2 -#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe -#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c -#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL -#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L -#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L -//SQ_IMG_RSRC_WORD3 -#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 -#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 -#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 -#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc -#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 -#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14 -#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c -#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L -#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L -#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L -#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L -#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L -#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L -#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L -#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L -//SQ_IMG_RSRC_WORD4 -#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd -#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d -#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL -#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L -#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L -//SQ_IMG_RSRC_WORD5 -#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd -#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11 -#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19 -#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a -#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b -#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c -#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL -#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L -#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L -#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L -#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L -#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L -#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L -//SQ_IMG_RSRC_WORD6 -#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc -#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 -#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 -#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 -#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 -#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 -#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c -#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL -#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L -#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L -#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L -#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L -#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L -#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L -#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L -//SQ_IMG_RSRC_WORD7 -#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL -//SQ_IMG_SAMP_WORD0 -#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 -#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 -#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 -#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 -#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc -#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf -#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 -#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 -#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 -#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 -#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b -#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c -#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d -#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f -#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L -#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L -#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L -#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L -#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L -#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L -#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L -#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L -#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L -#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L -#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L -#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L -#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L -#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L -//SQ_IMG_SAMP_WORD1 -#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 -#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc -#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 -#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c -#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL -#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L -#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L -#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L -//SQ_IMG_SAMP_WORD2 -#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 -#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe -#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 -#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 -#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 -#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a -#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c -#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d -#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e -#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f -#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL -#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L -#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L -#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L -#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L -#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L -#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L -#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L -#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L -#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L -//SQ_IMG_SAMP_WORD3 -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 -#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL -#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L -//SQ_FLAT_SCRATCH_WORD0 -#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 -#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL -//SQ_FLAT_SCRATCH_WORD1 -#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 -#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL -//SQ_M0_GPR_IDX_WORD -#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 -#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc -#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd -#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe -#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf -#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL -#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L -#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L -#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L -#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L -//SQC_ICACHE_UTCL1_CNTL1 -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 -#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 -#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 -#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 -#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 -#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 -#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 -#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 -#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b -#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L -#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L -#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L -#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//SQC_ICACHE_UTCL1_CNTL2 -#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 -#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 -#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 -#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa -#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb -#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc -#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf -#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 -#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 -#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 -#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 -#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a -#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL -#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L -#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L -#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L -#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L -#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L -#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L -#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -//SQC_DCACHE_UTCL1_CNTL1 -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 -#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 -#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 -#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 -#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 -#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 -#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 -#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 -#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b -#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L -#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L -#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L -#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//SQC_DCACHE_UTCL1_CNTL2 -#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 -#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 -#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 -#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa -#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb -#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc -#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf -#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 -#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 -#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 -#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 -#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a -#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL -#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L -#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L -#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L -#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L -#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L -#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L -#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -//SQC_ICACHE_UTCL1_STATUS -#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -//SQC_DCACHE_UTCL1_STATUS -#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L - - -// addressBlock: gc_shsdec -//SX_DEBUG_1 -#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 -#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa -#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb -#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc -#define SX_DEBUG_1__PC_CFG__SHIFT 0xd -#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe -#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L -#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L -#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L -#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L -#define SX_DEBUG_1__PC_CFG_MASK 0x00002000L -#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L -//SPI_PS_MAX_WAVE_ID -#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 -#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 -#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL -#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L -//SPI_START_PHASE -#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0 -#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2 -#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4 -#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L -#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL -#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L -//SPI_GFX_CNTL -#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 -#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L -//SPI_DSM_CNTL -#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3 -#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L -//SPI_DSM_CNTL2 -#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4 -#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa -#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L -#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L -//SPI_EDC_CNT -#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0 -#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L -//SPI_CONFIG_PS_CU_EN -#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0 -#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1 -#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10 -#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L -#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL -#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L -//SPI_WF_LIFETIME_CNTL -#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 -#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 -#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL -#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L -//SPI_WF_LIFETIME_LIMIT_0 -#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_1 -#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_2 -#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_3 -#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_4 -#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_5 -#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_6 -#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_7 -#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_8 -#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_9 -#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_0 -#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_1 -#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_2 -#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_3 -#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_4 -#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_5 -#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_6 -#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_7 -#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_8 -#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_9 -#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_10 -#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_11 -#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_12 -#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_13 -#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_14 -#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_15 -#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_16 -#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_17 -#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_18 -#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_19 -#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_20 -#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L -//SPI_LB_CTR_CTRL -#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 -#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 -#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 -#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 -#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L -#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L -#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L -#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L -//SPI_LB_CU_MASK -#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 -#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL -//SPI_LB_DATA_REG -#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 -#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL -//SPI_PG_ENABLE_STATIC_CU_MASK -#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 -#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL -//SPI_GDS_CREDITS -#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 -#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 -#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 -#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL -#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L -#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L -//SPI_SX_EXPORT_BUFFER_SIZES -#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 -#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 -#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL -#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L -//SPI_SX_SCOREBOARD_BUFFER_SIZES -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L -//SPI_CSQ_WF_ACTIVE_STATUS -#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL -//SPI_CSQ_WF_ACTIVE_COUNT_0 -#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_1 -#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_2 -#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_3 -#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_4 -#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_5 -#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_6 -#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_7 -#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L -//SPI_LB_DATA_WAVES -#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 -#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 -#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL -#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L -//SPI_LB_DATA_PERCU_WAVE_HSGS -#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0 -#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10 -#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL -#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L -//SPI_LB_DATA_PERCU_WAVE_VSPS -#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0 -#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10 -#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL -#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L -//SPI_LB_DATA_PERCU_WAVE_CS -#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0 -#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL -//SPI_P0_TRAP_SCREEN_PSBA_LO -#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 -#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_P0_TRAP_SCREEN_PSBA_HI -#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 -#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL -//SPI_P0_TRAP_SCREEN_PSMA_LO -#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 -#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_P0_TRAP_SCREEN_PSMA_HI -#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 -#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL -//SPI_P0_TRAP_SCREEN_GPR_MIN -#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 -#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 -#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL -#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L -//SPI_P1_TRAP_SCREEN_PSBA_LO -#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 -#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_P1_TRAP_SCREEN_PSBA_HI -#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 -#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL -//SPI_P1_TRAP_SCREEN_PSMA_LO -#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 -#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_P1_TRAP_SCREEN_PSMA_HI -#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 -#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL -//SPI_P1_TRAP_SCREEN_GPR_MIN -#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 -#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 -#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL -#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L - - -// addressBlock: gc_tpdec -//TD_CNTL -#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 -#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 -#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 -#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 -#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb -#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf -#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 -#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 -#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 -#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 -#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 -#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17 -#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18 -#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L -#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L -#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L -#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L -#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L -#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L -#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L -#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L -#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L -#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L -#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L -#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L -#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L -//TD_STATUS -#define TD_STATUS__BUSY__SHIFT 0x1f -#define TD_STATUS__BUSY_MASK 0x80000000L -//TD_DSM_CNTL -#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L -//TD_DSM_CNTL2 -#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2 -#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5 -#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 -#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a -#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L -#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L -#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L -//TD_SCRATCH -#define TD_SCRATCH__SCRATCH__SHIFT 0x0 -#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL -//TA_CNTL -#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0 -#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9 -#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd -#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 -#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 -#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL -#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L -#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L -#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L -#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L -//TA_CNTL_AUX -#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 -#define TA_CNTL_AUX__RESERVED__SHIFT 0x1 -#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 -#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6 -#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 -#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9 -#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa -#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc -#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd -#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe -#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf -#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 -#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 -#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 -#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13 -#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 -#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 -#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 -#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 -#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 -#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 -#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a -#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b -#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c -#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d -#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e -#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L -#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL -#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L -#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L -#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L -#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L -#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L -#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L -#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L -#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L -#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L -#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L -#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L -#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L -#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L -#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L -#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L -#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L -#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L -#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L -#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L -#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L -#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L -#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L -#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L -#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L -//TA_RESERVED_010C -#define TA_RESERVED_010C__Unused__SHIFT 0x0 -#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL -//TA_GRAD_ADJ -#define TA_GRAD_ADJ__GRAD_ADJ_0__SHIFT 0x0 -#define TA_GRAD_ADJ__GRAD_ADJ_1__SHIFT 0x8 -#define TA_GRAD_ADJ__GRAD_ADJ_2__SHIFT 0x10 -#define TA_GRAD_ADJ__GRAD_ADJ_3__SHIFT 0x18 -#define TA_GRAD_ADJ__GRAD_ADJ_0_MASK 0x000000FFL -#define TA_GRAD_ADJ__GRAD_ADJ_1_MASK 0x0000FF00L -#define TA_GRAD_ADJ__GRAD_ADJ_2_MASK 0x00FF0000L -#define TA_GRAD_ADJ__GRAD_ADJ_3_MASK 0xFF000000L -//TA_STATUS -#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc -#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd -#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe -#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 -#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 -#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 -#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 -#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 -#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 -#define TA_STATUS__IN_BUSY__SHIFT 0x18 -#define TA_STATUS__FG_BUSY__SHIFT 0x19 -#define TA_STATUS__LA_BUSY__SHIFT 0x1a -#define TA_STATUS__FL_BUSY__SHIFT 0x1b -#define TA_STATUS__TA_BUSY__SHIFT 0x1c -#define TA_STATUS__FA_BUSY__SHIFT 0x1d -#define TA_STATUS__AL_BUSY__SHIFT 0x1e -#define TA_STATUS__BUSY__SHIFT 0x1f -#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L -#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L -#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L -#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L -#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L -#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L -#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L -#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L -#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L -#define TA_STATUS__IN_BUSY_MASK 0x01000000L -#define TA_STATUS__FG_BUSY_MASK 0x02000000L -#define TA_STATUS__LA_BUSY_MASK 0x04000000L -#define TA_STATUS__FL_BUSY_MASK 0x08000000L -#define TA_STATUS__TA_BUSY_MASK 0x10000000L -#define TA_STATUS__FA_BUSY_MASK 0x20000000L -#define TA_STATUS__AL_BUSY_MASK 0x40000000L -#define TA_STATUS__BUSY_MASK 0x80000000L -//TA_SCRATCH -#define TA_SCRATCH__SCRATCH__SHIFT 0x0 -#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL - - -// addressBlock: gc_gdsdec -//GDS_CONFIG -#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 -#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 -#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 -#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 -#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L -#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L -#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L -#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L -//GDS_CNTL_STATUS -#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 -#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 -#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 -#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 -#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 -#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 -#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 -#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 -#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 -#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 -#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa -#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb -#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc -#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd -#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe -#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L -#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L -#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L -#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L -#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L -#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L -#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L -#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L -#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L -#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L -#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L -#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L -#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L -#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L -#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L -//GDS_ENHANCE2 -#define GDS_ENHANCE2__MISC__SHIFT 0x0 -#define GDS_ENHANCE2__UNUSED__SHIFT 0x10 -#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL -#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L -//GDS_PROTECTION_FAULT -#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 -#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 -#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 -#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 -#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 -#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa -#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc -#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 -#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L -#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L -#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L -#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L -#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L -#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L -#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L -#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L -//GDS_VM_PROTECTION_FAULT -#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 -#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 -#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 -#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 -#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 -#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5 -#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 -#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 -#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L -#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L -#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L -#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L -#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L -#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L -#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L -#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L -//GDS_EDC_CNT -#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 -#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2 -#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 -#define GDS_EDC_CNT__UNUSED__SHIFT 0x6 -#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L -#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL -#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L -#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L -//GDS_EDC_GRBM_CNT -#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 -#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 -#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 -#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L -#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL -#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L -//GDS_EDC_OA_DED -#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 -#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 -#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 -#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 -#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 -#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 -#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 -#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 -#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 -#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 -#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa -#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb -#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc -#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L -#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L -#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L -#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L -#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L -#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L -#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L -#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L -#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L -#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L -#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L -#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L -#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L -//GDS_DSM_CNTL -#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0 -#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1 -#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3 -#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4 -#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6 -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7 -#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9 -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa -#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc -#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd -#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf -#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L -#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L -#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L -#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L -#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L -#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L -#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L -#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L -//GDS_EDC_OA_PHY_CNT -#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 -#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 -#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 -#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 -#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8 -#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa -#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L -#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL -#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L -#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L -#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L -#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L -//GDS_EDC_OA_PIPE_CNT -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe -#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L -#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L -//GDS_DSM_CNTL2 -#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5 -#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 -#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb -#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe -#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf -#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a -#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L -#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L -#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L -//GDS_WD_GDS_CSB -#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0 -#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd -#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL -#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L - - -// addressBlock: gc_rbdec -//DB_DEBUG -#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 -#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 -#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 -#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 -#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 -#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 -#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 -#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc -#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe -#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf -#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 -#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 -#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 -#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 -#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 -#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 -#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 -#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 -#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c -#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d -#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e -#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f -#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L -#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L -#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L -#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L -#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L -#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L -#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L -#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L -#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L -#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L -#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L -#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L -#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L -#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L -#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L -#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L -#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L -#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L -#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L -#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L -#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L -#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L -//DB_DEBUG2 -#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 -#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 -#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 -#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 -#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 -#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 -#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 -#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 -#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 -#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 -#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe -#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf -#define DB_DEBUG2__RESERVED__SHIFT 0x10 -#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 -#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 -#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 -#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c -#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d -#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e -#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f -#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L -#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L -#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L -#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L -#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L -#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L -#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L -#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L -#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L -#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L -#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L -#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L -#define DB_DEBUG2__RESERVED_MASK 0x00010000L -#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L -#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L -#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L -#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L -#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L -#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L -#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L -//DB_DEBUG3 -#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0 -#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1 -#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 -#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 -#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 -#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 -#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 -#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 -#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 -#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 -#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa -#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb -#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc -#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd -#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe -#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf -#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 -#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 -#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 -#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 -#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 -#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 -#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 -#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 -#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 -#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 -#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a -#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b -#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c -#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d -#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e -#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f -#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L -#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L -#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L -#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L -#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L -#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L -#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L -#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L -#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L -#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L -#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L -#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L -#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L -#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L -#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L -#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L -#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L -#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L -#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L -#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L -#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L -#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L -#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L -#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L -#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L -#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L -#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L -#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L -#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L -#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L -#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L -#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L -//DB_DEBUG4 -#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 -#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 -#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 -#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 -#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4 -#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5 -#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6 -#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7 -#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8 -#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9 -#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa -#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb -#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc -#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd -#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe -#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf -#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10 -#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11 -#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12 -#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13 -#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L -#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L -#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L -#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L -#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L -#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L -#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L -#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L -#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L -#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L -#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L -#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L -#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L -#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L -#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L -#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L -#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L -#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L -#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L -#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xFFF80000L -//DB_CREDIT_LIMIT -#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 -#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 -#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa -#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 -#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL -#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L -#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L -#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L -//DB_WATERMARKS -#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 -#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 -#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb -#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf -#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 -#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e -#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f -#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL -#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L -#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L -#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L -#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L -#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L -#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L -//DB_SUBTILE_CONTROL -#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 -#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 -#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 -#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 -#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 -#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa -#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc -#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe -#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 -#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 -#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L -#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL -#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L -#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L -#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L -#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L -#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L -#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L -#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L -#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L -//DB_FREE_CACHELINES -#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 -#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 -#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe -#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14 -#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18 -#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL -#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L -#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L -#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L -#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L -//DB_FIFO_DEPTH1 -#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0 -#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5 -#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa -#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 -#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 -#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL -#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L -#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L -#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L -#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L -//DB_FIFO_DEPTH2 -#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 -#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 -#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf -#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 -#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL -#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L -#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L -#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L -//DB_EXCEPTION_CONTROL -#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 -#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 -#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 -#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L -#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L -#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L -//DB_RING_CONTROL -#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 -#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L -//DB_MEM_ARB_WATERMARKS -#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 -#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 -#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 -#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 -#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L -#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L -#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L -#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L -//DB_RMI_CACHE_POLICY -#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0 -#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1 -#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2 -#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8 -#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9 -#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa -#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb -#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10 -#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11 -#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12 -#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13 -#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18 -#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19 -#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a -#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b -#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L -#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L -#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L -#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L -#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L -#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L -#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L -#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L -#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L -#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L -#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L -#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L -#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L -#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L -#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L -//DB_DFSM_CONFIG -#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0 -#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1 -#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2 -#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3 -#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8 -#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L -#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L -#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L -#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L -#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L -//DB_DFSM_WATERMARK -#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0 -#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10 -#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL -#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L -//DB_DFSM_TILES_IN_FLIGHT -#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 -#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 -#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL -#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L -//DB_DFSM_PRIMS_IN_FLIGHT -#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 -#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 -#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL -#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L -//DB_DFSM_WATCHDOG -#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0 -#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL -//DB_DFSM_FLUSH_ENABLE -#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0 -#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18 -#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c -#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL -#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L -#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L -//DB_DFSM_FLUSH_AUX_EVENT -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0 -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8 -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10 -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18 -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L -//CC_RB_REDUNDANCY -#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 -#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc -#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 -#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 -#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L -#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L -#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L -#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L -//CC_RB_BACKEND_DISABLE -#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 -#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L -//GB_ADDR_CONFIG -#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 -#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 -#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc -#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 -#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 -#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 -#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 -#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a -#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c -#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e -#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f -#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L -#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L -#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L -#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L -#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L -#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L -#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L -#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L -#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L -#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L -#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L -//GB_BACKEND_MAP -#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 -#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL -//GB_GPU_ID -#define GB_GPU_ID__GPU_ID__SHIFT 0x0 -#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL -//CC_RB_DAISY_CHAIN -#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 -#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 -#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 -#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc -#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 -#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 -#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 -#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c -#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL -#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L -#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L -#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L -#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L -#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L -#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L -#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L -//GB_ADDR_CONFIG_READ -#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 -#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 -#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc -#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 -#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 -#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15 -#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18 -#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a -#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c -#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e -#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f -#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L -#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L -#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L -#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L -#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L -#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L -#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L -#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L -#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L -#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L -#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L -//GB_TILE_MODE0 -#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE1 -#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE2 -#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE3 -#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE4 -#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE5 -#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE6 -#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE7 -#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE8 -#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE9 -#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE10 -#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE11 -#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE12 -#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE13 -#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE14 -#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE15 -#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE16 -#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE17 -#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE18 -#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE19 -#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE20 -#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE21 -#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE22 -#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE23 -#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE24 -#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE25 -#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE26 -#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE27 -#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE28 -#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE29 -#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE30 -#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE31 -#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L -//GB_MACROTILE_MODE0 -#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE1 -#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE2 -#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE3 -#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE4 -#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE5 -#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE6 -#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE7 -#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE8 -#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE9 -#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE10 -#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE11 -#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE12 -#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE13 -#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE14 -#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE15 -#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L -//CB_HW_CONTROL -#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 -#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 -#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc -#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 -#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 -#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 -#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 -#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 -#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b -#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c -#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d -#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e -#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f -#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL -#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L -#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L -#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L -#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L -#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L -#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L -#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L -#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L -#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L -#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L -#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L -#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L -//CB_HW_CONTROL_1 -#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 -#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 -#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb -#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 -#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a -#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL -#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L -#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L -#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L -#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L -//CB_HW_CONTROL_2 -#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 -#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 -#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf -#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 -#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c -#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL -#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L -#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L -#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L -#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L -//CB_HW_CONTROL_3 -#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 -#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 -#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 -#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6 -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 -#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9 -#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa -#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd -#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe -#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf -#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10 -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11 -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12 -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13 -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14 -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15 -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16 -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17 -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18 -#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19 -#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a -#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b -#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c -#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L -#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L -#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L -#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L -#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L -#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L -#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L -#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L -#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L -#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L -#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L -#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L -#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L -#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L -//CB_HW_MEM_ARBITER_RD -#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0 -#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2 -#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6 -#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa -#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc -#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10 -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12 -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14 -#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16 -#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17 -#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a -#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d -#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L -#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL -#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L -#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L -#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L -#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L -//CB_HW_MEM_ARBITER_WR -#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0 -#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2 -#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6 -#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa -#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc -#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10 -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12 -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14 -#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16 -#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17 -#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a -#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d -#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L -#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL -#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L -#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L -#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L -#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L -//CB_DCC_CONFIG -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 -#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8 -#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 -#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18 -#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L -#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L -#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L -#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L -#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L -//GC_USER_RB_REDUNDANCY -#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc -#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 -#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L -#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L -//GC_USER_RB_BACKEND_DISABLE -#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 -#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L - - -// addressBlock: gc_ea_gceadec2 -//GCEA_EDC_CNT -#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 -#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 -#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 -#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 -#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 -#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa -#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc -#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe -#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 -#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 -#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 -#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 -#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 -#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a -#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c -#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L -#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL -#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L -#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L -#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L -#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L -#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L -#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L -#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L -#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L -#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L -#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L -#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L -#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L -#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L -//GCEA_EDC_CNT2 -#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 -#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 -#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 -#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 -#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 -#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa -#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc -#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe -#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L -#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL -#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L -#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L -#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L -#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L -#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L -#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L -//GCEA_DSM_CNTL -#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc -#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf -#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 -#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 -#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L -#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L -#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L -//GCEA_DSM_CNTLA -#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc -#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf -#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L -//GCEA_DSM_CNTLB -//GCEA_DSM_CNTL2 -#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 -#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 -#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb -#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe -#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf -#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 -#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 -#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 -#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 -#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a -#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L -#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L -#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L -#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L -#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L -//GCEA_DSM_CNTL2A -#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 -#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 -#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb -#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe -#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf -#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 -#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 -#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L -#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L -#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L -//GCEA_DSM_CNTL2B -//GCEA_TCC_XBR_CREDITS -#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0 -#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6 -#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8 -#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe -#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10 -#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16 -#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18 -#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e -#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL -#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L -#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L -#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L -#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L -#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L -#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L -#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L -//GCEA_TCC_XBR_MAXBURST -#define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x0 -#define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x4 -#define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x8 -#define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0xc -#define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL -#define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000F0L -#define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L -#define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000F000L -//GCEA_PROBE_CNTL -#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0 -#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5 -#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL -#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L -//GCEA_PROBE_MAP -#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x0 -#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x1 -#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x2 -#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x3 -#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x4 -#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x5 -#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x6 -#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x7 -#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x8 -#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x9 -#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa -#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0xb -#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0xc -#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0xd -#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0xe -#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0xf -#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10 -#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L -#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L -#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L -#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L -#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L -#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L -#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L -#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L -#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L -#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L -#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L -#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L -#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L -#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L -#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L -#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L -#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L -//GCEA_ERR_STATUS -#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 -#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 -#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 -#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 -#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa -#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL -#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L -#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L -#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L -#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L -//GCEA_MISC2 -#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 -#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 -#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 -#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 -#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L -#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L -#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL -#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L -//GCEA_SDP_BACKDOOR_CMDCREDITS0 -#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT 0x0 -#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL -//GCEA_SDP_BACKDOOR_CMDCREDITS1 -#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT 0x0 -#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL -//GCEA_SDP_BACKDOOR_DATACREDITS0 -#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT 0x0 -#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL -//GCEA_SDP_BACKDOOR_DATACREDITS1 -#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT 0x0 -#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL -//GCEA_SDP_BACKDOOR_MISCCREDITS -#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0 -#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8 -#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x10 -#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x17 -#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL -#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L -#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L -#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L -//GCEA_SDP_ENABLE -#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0 -#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L - - -// addressBlock: gc_rmi_rmidec -//RMI_GENERAL_CNTL -#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 -#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 -#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11 -#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 -#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14 -#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 -#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19 -#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a -#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b -#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c -#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d -#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e -#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L -#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL -#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L -#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L -#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L -#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L -#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L -//RMI_GENERAL_CNTL1 -#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 -#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 -#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 -#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 -#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 -#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa -#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb -#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc -#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL -#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L -#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L -#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L -#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L -#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L -#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L -#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L -//RMI_GENERAL_STATUS -#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 -#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 -#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 -#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 -#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 -#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 -#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6 -#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 -#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 -#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 -#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa -#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb -#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc -#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd -#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe -#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf -#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10 -#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11 -#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12 -#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13 -#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14 -#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15 -#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d -#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e -#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f -#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L -#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L -#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L -#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L -#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L -#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L -#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L -#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L -#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L -#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L -#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L -#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L -#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L -#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L -#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L -#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L -#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L -#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L -#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L -#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L -#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L -#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L -#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L -#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L -#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L -//RMI_SUBBLOCK_STATUS0 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 -#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L -#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L -//RMI_SUBBLOCK_STATUS1 -#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 -#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa -#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 -#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL -#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L -#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L -//RMI_SUBBLOCK_STATUS2 -#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 -#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 -#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL -#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L -//RMI_SUBBLOCK_STATUS3 -#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 -#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa -#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL -#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L -//RMI_XBAR_CONFIG -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 -#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 -#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 -#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc -#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd -#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L -#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L -#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L -#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L -#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L -#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L -//RMI_PROBE_POP_LOGIC_CNTL -#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 -#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 -#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 -#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa -#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 -#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL -#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L -#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L -#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L -#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L -//RMI_UTC_XNACK_N_MISC_CNTL -#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 -#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 -#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc -#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd -#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL -#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L -#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L -#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L -//RMI_DEMUX_CNTL -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0 -#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1 -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4 -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 -#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10 -#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11 -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14 -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 -#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L -#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L -#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L -//RMI_UTCL1_CNTL1 -#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 -#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 -#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 -#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 -#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 -#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 -#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 -#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 -#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 -#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 -#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 -#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 -#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 -#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a -#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b -#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L -#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L -#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L -#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L -#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L -#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L -#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L -#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//RMI_UTCL1_CNTL2 -#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 -#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 -#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa -#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb -#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc -#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd -#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe -#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf -#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 -#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 -#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 -#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 -#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 -#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 -#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a -#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL -#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L -#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L -#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L -#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L -#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L -#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L -#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L -#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L -#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -//RMI_UTC_UNIT_CONFIG -//RMI_TCIW_FORMATTER0_CNTL -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0 -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1 -#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 -#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13 -#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b -#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c -#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e -#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL -#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L -#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L -#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L -#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L -#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L -#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L -//RMI_TCIW_FORMATTER1_CNTL -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 -#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 -#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13 -#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b -#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c -#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e -#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL -#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L -#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L -#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L -#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L -#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L -#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L -//RMI_SCOREBOARD_CNTL -#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 -#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 -#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 -#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 -#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4 -#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 -#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 -#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7 -#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8 -#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 -#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L -#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L -#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L -#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L -#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L -#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L -#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L -#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L -#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L -#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L -//RMI_SCOREBOARD_STATUS0 -#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 -#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 -#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L -#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L -//RMI_SCOREBOARD_STATUS1 -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd -#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c -#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d -#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L -#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L -#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L -#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L -//RMI_SCOREBOARD_STATUS2 -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 -#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a -#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L -#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L -#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L -//RMI_XBAR_ARBITER_CONFIG -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L -//RMI_XBAR_ARBITER_CONFIG_1 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L -//RMI_CLOCK_CNTRL -#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 -#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 -#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa -#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf -#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14 -#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19 -#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL -#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L -#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L -#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L -#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L -#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L -//RMI_UTCL1_STATUS -#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -//RMI_SPARE -#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0 -#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1 -#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2 -#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3 -#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4 -#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5 -#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6 -#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 -#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8 -#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10 -#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L -#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L -#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L -#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L -#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L -#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L -#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L -#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L -#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L -#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L -//RMI_SPARE_1 -#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0 -#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 -#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 -#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 -#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 -#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 -#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 -#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 -#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8 -#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 -#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L -#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L -#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L -#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L -#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L -#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L -#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L -#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L -#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L -#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L -//RMI_SPARE_2 -#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0 -#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1 -#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2 -#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3 -#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4 -#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5 -#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6 -#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7 -#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8 -#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc -#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 -#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 -#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L -#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L -#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L -#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L -#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L -#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L -#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L -#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L -#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L -#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L -#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L -#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L - - -// addressBlock: gc_dbgu_gfx_dbgudec -//port_a_addr -#define port_a_addr__Index__SHIFT 0x0 -#define port_a_addr__Reserved__SHIFT 0x8 -#define port_a_addr__ReadEnable__SHIFT 0x1f -#define port_a_addr__Index_MASK 0x000000FFL -#define port_a_addr__Reserved_MASK 0x7FFFFF00L -#define port_a_addr__ReadEnable_MASK 0x80000000L -//port_a_data_lo -#define port_a_data_lo__Data__SHIFT 0x0 -#define port_a_data_lo__Data_MASK 0xFFFFFFFFL -//port_a_data_hi -#define port_a_data_hi__Data__SHIFT 0x0 -#define port_a_data_hi__Data_MASK 0xFFFFFFFFL -//port_b_addr -#define port_b_addr__Index__SHIFT 0x0 -#define port_b_addr__Reserved__SHIFT 0x8 -#define port_b_addr__ReadEnable__SHIFT 0x1f -#define port_b_addr__Index_MASK 0x000000FFL -#define port_b_addr__Reserved_MASK 0x7FFFFF00L -#define port_b_addr__ReadEnable_MASK 0x80000000L -//port_b_data_lo -#define port_b_data_lo__Data__SHIFT 0x0 -#define port_b_data_lo__Data_MASK 0xFFFFFFFFL -//port_b_data_hi -#define port_b_data_hi__Data__SHIFT 0x0 -#define port_b_data_hi__Data_MASK 0xFFFFFFFFL -//port_c_addr -#define port_c_addr__Index__SHIFT 0x0 -#define port_c_addr__Reserved__SHIFT 0x8 -#define port_c_addr__ReadEnable__SHIFT 0x1f -#define port_c_addr__Index_MASK 0x000000FFL -#define port_c_addr__Reserved_MASK 0x7FFFFF00L -#define port_c_addr__ReadEnable_MASK 0x80000000L -//port_c_data_lo -#define port_c_data_lo__Data__SHIFT 0x0 -#define port_c_data_lo__Data_MASK 0xFFFFFFFFL -//port_c_data_hi -#define port_c_data_hi__Data__SHIFT 0x0 -#define port_c_data_hi__Data_MASK 0xFFFFFFFFL -//port_d_addr -#define port_d_addr__Index__SHIFT 0x0 -#define port_d_addr__Reserved__SHIFT 0x8 -#define port_d_addr__ReadEnable__SHIFT 0x1f -#define port_d_addr__Index_MASK 0x000000FFL -#define port_d_addr__Reserved_MASK 0x7FFFFF00L -#define port_d_addr__ReadEnable_MASK 0x80000000L -//port_d_data_lo -#define port_d_data_lo__Data__SHIFT 0x0 -#define port_d_data_lo__Data_MASK 0xFFFFFFFFL -//port_d_data_hi -#define port_d_data_hi__Data__SHIFT 0x0 -#define port_d_data_hi__Data_MASK 0xFFFFFFFFL - - -// addressBlock: gc_utcl2_atcl2dec -//ATC_L2_CNTL -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 -#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 -#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L -#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L -#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L -//ATC_L2_CNTL2 -#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 -#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 -#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 -#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf -#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L -#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L -#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L -#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L -//ATC_L2_CACHE_DATA0 -#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 -#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 -#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 -#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 -#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L -#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L -#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL -#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L -//ATC_L2_CACHE_DATA1 -#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 -#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL -//ATC_L2_CACHE_DATA2 -#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 -#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL -//ATC_L2_CNTL3 -#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 -#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 -#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L -#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L -//ATC_L2_STATUS -#define ATC_L2_STATUS__BUSY__SHIFT 0x0 -#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 -#define ATC_L2_STATUS__BUSY_MASK 0x00000001L -#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL -//ATC_L2_STATUS2 -#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 -#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 -#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL -#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L -//ATC_L2_MISC_CG -#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 -#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 -#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 -#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L -#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L -#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L -//ATC_L2_MEM_POWER_LS -#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 -#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 -#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL -#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L -//ATC_L2_CGTT_CLK_CTRL -#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 -#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 -#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L -#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L - - -// addressBlock: gc_utcl2_vml2pfdec -//VM_L2_CNTL -#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 -#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 -#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 -#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 -#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 -#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 -#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa -#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb -#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc -#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf -#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 -#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 -#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 -#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a -#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L -#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L -#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL -#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L -#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L -#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L -#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L -#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L -#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L -#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L -#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L -#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L -#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L -#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L -//VM_L2_CNTL2 -#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 -#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 -#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 -#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 -#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 -#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a -#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c -#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L -#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L -#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L -#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L -#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L -#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L -#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L -//VM_L2_CNTL3 -#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 -#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 -#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 -#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf -#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 -#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 -#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 -#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c -#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d -#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e -#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f -#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL -#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L -#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L -#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L -#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L -#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L -#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L -#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L -//VM_L2_STATUS -#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 -#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 -#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 -#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 -#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 -#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 -#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 -#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L -#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL -#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L -#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L -#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L -#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L -#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L -//VM_DUMMY_PAGE_FAULT_CNTL -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL -//VM_DUMMY_PAGE_FAULT_ADDR_LO32 -#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 -#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL -//VM_DUMMY_PAGE_FAULT_ADDR_HI32 -#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 -#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL -//VM_L2_PROTECTION_FAULT_CNTL -#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 -#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 -#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 -#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 -#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 -#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 -#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 -#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 -#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 -#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb -#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd -#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f -#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L -#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L -#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L -#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L -#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L -#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L -#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L -#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L -#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L -#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L -#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L -#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L -#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L -//VM_L2_PROTECTION_FAULT_CNTL2 -#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 -#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 -#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL -#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L -#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L -//VM_L2_PROTECTION_FAULT_MM_CNTL3 -#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL -//VM_L2_PROTECTION_FAULT_MM_CNTL4 -#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL -//VM_L2_PROTECTION_FAULT_STATUS -#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 -#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 -#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 -#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 -#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 -#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 -#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 -#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 -#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 -#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L -#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL -#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L -#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L -#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L -#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L -#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L -#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L -#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L -#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L -//VM_L2_PROTECTION_FAULT_ADDR_LO32 -#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL -//VM_L2_PROTECTION_FAULT_ADDR_HI32 -#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL -//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL -//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL -//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL -//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL -//VM_L2_CNTL4 -#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 -#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 -#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 -#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c -#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L -#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L -#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L -#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L -//VM_L2_MM_GROUP_RT_CLASSES -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L -//VM_L2_BANK_SELECT_RESERVED_CID -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa -#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L -#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L -//VM_L2_BANK_SELECT_RESERVED_CID2 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa -#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L -#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L -//VM_L2_CACHE_PARITY_CNTL -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L -//VM_L2_CGTT_CLK_CTRL -#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 -#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 -#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L -#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L - - -// addressBlock: gc_utcl2_vml2vcdec -//VM_CONTEXT0_CNTL -#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT1_CNTL -#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT2_CNTL -#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT3_CNTL -#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT4_CNTL -#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT5_CNTL -#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT6_CNTL -#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT7_CNTL -#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT8_CNTL -#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT9_CNTL -#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT10_CNTL -#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT11_CNTL -#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT12_CNTL -#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT13_CNTL -#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT14_CNTL -#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT15_CNTL -#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXTS_DISABLE -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L -//VM_INVALIDATE_ENG0_SEM -#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG1_SEM -#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG2_SEM -#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG3_SEM -#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG4_SEM -#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG5_SEM -#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG6_SEM -#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG7_SEM -#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG8_SEM -#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG9_SEM -#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG10_SEM -#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG11_SEM -#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG12_SEM -#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG13_SEM -#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG14_SEM -#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG15_SEM -#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG16_SEM -#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG17_SEM -#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG0_REQ -#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG1_REQ -#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG2_REQ -#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG3_REQ -#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG4_REQ -#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG5_REQ -#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG6_REQ -#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG7_REQ -#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG8_REQ -#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG9_REQ -#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG10_REQ -#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG11_REQ -#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG12_REQ -#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG13_REQ -#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG14_REQ -#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG15_REQ -#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG16_REQ -#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG17_REQ -#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG0_ACK -#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG1_ACK -#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG2_ACK -#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG3_ACK -#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG4_ACK -#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG5_ACK -#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG6_ACK -#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG7_ACK -#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG8_ACK -#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG9_ACK -#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG10_ACK -#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG11_ACK -#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG12_ACK -#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG13_ACK -#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG14_ACK -#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG15_ACK -#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG16_ACK -#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG17_ACK -#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL - - -// addressBlock: gc_utcl2_vmsharedpfdec -//MC_VM_NB_MMIOBASE -#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 -#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL -//MC_VM_NB_MMIOLIMIT -#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 -#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL -//MC_VM_NB_PCI_CTRL -#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 -#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L -//MC_VM_NB_PCI_ARB -#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 -#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L -//MC_VM_NB_TOP_OF_DRAM_SLOT1 -#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 -#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L -//MC_VM_NB_LOWER_TOP_OF_DRAM2 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L -//MC_VM_NB_UPPER_TOP_OF_DRAM2 -#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 -#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL -//MC_VM_FB_OFFSET -#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 -#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL -//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL -//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL -//MC_VM_STEERING -#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 -#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L -//MC_SHARED_VIRT_RESET_REQ -#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 -#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f -#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL -#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L -//MC_MEM_POWER_LS -#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 -#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 -#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL -#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L -//MC_VM_CACHEABLE_DRAM_ADDRESS_START -#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 -#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL -//MC_VM_CACHEABLE_DRAM_ADDRESS_END -#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 -#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL -//MC_VM_APT_CNTL -#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 -#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 -#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L -#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L -//MC_VM_LOCAL_HBM_ADDRESS_START -#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 -#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL -//MC_VM_LOCAL_HBM_ADDRESS_END -#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 -#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL -//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL -#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 -#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L - - -// addressBlock: gc_utcl2_vmsharedvcdec -//MC_VM_FB_LOCATION_BASE -#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 -#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL -//MC_VM_FB_LOCATION_TOP -#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 -#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL -//MC_VM_AGP_TOP -#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 -#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL -//MC_VM_AGP_BOT -#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 -#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL -//MC_VM_AGP_BASE -#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 -#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL -//MC_VM_SYSTEM_APERTURE_LOW_ADDR -#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 -#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL -//MC_VM_SYSTEM_APERTURE_HIGH_ADDR -#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 -#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL -//MC_VM_MX_L1_TLB_CNTL -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 -#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 -#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb -#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L -#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L -#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L -#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L - - -// addressBlock: gc_ea_gceadec -//GCEA_DRAM_RD_CLI2GRP_MAP0 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//GCEA_DRAM_RD_CLI2GRP_MAP1 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//GCEA_DRAM_WR_CLI2GRP_MAP0 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//GCEA_DRAM_WR_CLI2GRP_MAP1 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//GCEA_DRAM_RD_GRP2VC_MAP -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L -//GCEA_DRAM_WR_GRP2VC_MAP -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L -//GCEA_DRAM_RD_LAZY -#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 -#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 -#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 -#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 -#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L -#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L -#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L -#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L -//GCEA_DRAM_WR_LAZY -#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 -#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 -#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 -#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 -#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L -#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L -#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L -#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L -//GCEA_DRAM_RD_CAM_CNTL -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L -//GCEA_DRAM_WR_CAM_CNTL -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L -//GCEA_DRAM_PAGE_BURST -#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 -#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 -#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 -#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 -#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL -#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L -#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L -#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L -//GCEA_DRAM_RD_PRI_AGE -#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//GCEA_DRAM_WR_PRI_AGE -#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//GCEA_DRAM_RD_PRI_QUEUING -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//GCEA_DRAM_WR_PRI_QUEUING -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//GCEA_DRAM_RD_PRI_FIXED -#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//GCEA_DRAM_WR_PRI_FIXED -#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//GCEA_DRAM_RD_PRI_URGENCY -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//GCEA_DRAM_WR_PRI_URGENCY -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//GCEA_DRAM_RD_PRI_QUANT_PRI1 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_DRAM_RD_PRI_QUANT_PRI2 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_DRAM_RD_PRI_QUANT_PRI3 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_DRAM_WR_PRI_QUANT_PRI1 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_DRAM_WR_PRI_QUANT_PRI2 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_DRAM_WR_PRI_QUANT_PRI3 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_ADDRNORM_BASE_ADDR0 -#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 -#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 -#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 -#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 -#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc -#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L -#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L -#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L -#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L -#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L -//GCEA_ADDRNORM_LIMIT_ADDR0 -#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 -#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 -#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa -#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc -#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL -#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L -#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L -#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L -//GCEA_ADDRNORM_BASE_ADDR1 -#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 -#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 -#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 -#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 -#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc -#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L -#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L -#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L -#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L -#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L -//GCEA_ADDRNORM_LIMIT_ADDR1 -#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 -#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 -#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa -#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc -#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL -#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L -#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L -#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L -//GCEA_ADDRNORM_OFFSET_ADDR1 -#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 -#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 -#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L -#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L -//GCEA_ADDRNORM_HOLE_CNTL -#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 -#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 -#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L -#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L -//GCEA_ADDRDEC_BANK_CFG -#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 -#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 -#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL -#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L -//GCEA_ADDRDEC_MISC_CFG -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 -#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 -#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 -#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc -#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 -#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 -#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 -#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 -#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L -#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L -#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L -#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L -#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L -#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L -#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L -#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L -#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L -//GCEA_ADDRDECDRAM_ADDR_HASH_BANK0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L -//GCEA_ADDRDECDRAM_ADDR_HASH_BANK1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L -//GCEA_ADDRDECDRAM_ADDR_HASH_BANK2 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L -//GCEA_ADDRDECDRAM_ADDR_HASH_BANK3 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L -//GCEA_ADDRDECDRAM_ADDR_HASH_BANK4 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L -//GCEA_ADDRDECDRAM_ADDR_HASH_PC -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L -//GCEA_ADDRDECDRAM_ADDR_HASH_PC2 -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL -//GCEA_ADDRDECDRAM_ADDR_HASH_CS0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL -//GCEA_ADDRDECDRAM_ADDR_HASH_CS1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL -//GCEA_ADDRDECDRAM_HARVEST_ENABLE -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L -//GCEA_ADDRDEC0_BASE_ADDR_CS0 -#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_CS1 -#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_CS2 -#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_CS3 -#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_SECCS0 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_SECCS1 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_SECCS2 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_SECCS3 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_ADDR_MASK_CS01 -#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_ADDR_MASK_CS23 -#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_ADDR_MASK_SECCS01 -#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_ADDR_MASK_SECCS23 -#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_ADDR_CFG_CS01 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L -//GCEA_ADDRDEC0_ADDR_CFG_CS23 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L -//GCEA_ADDRDEC0_ADDR_SEL_CS01 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L -//GCEA_ADDRDEC0_ADDR_SEL_CS23 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L -//GCEA_ADDRDEC0_COL_SEL_LO_CS01 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L -//GCEA_ADDRDEC0_COL_SEL_LO_CS23 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L -//GCEA_ADDRDEC0_COL_SEL_HI_CS01 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L -//GCEA_ADDRDEC0_COL_SEL_HI_CS23 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L -//GCEA_ADDRDEC0_RM_SEL_CS01 -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC0_RM_SEL_CS23 -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC0_RM_SEL_SECCS01 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC0_RM_SEL_SECCS23 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC1_BASE_ADDR_CS0 -#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_CS1 -#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_CS2 -#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_CS3 -#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_SECCS0 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_SECCS1 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_SECCS2 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_SECCS3 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_ADDR_MASK_CS01 -#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_ADDR_MASK_CS23 -#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_ADDR_MASK_SECCS01 -#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_ADDR_MASK_SECCS23 -#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_ADDR_CFG_CS01 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L -//GCEA_ADDRDEC1_ADDR_CFG_CS23 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L -//GCEA_ADDRDEC1_ADDR_SEL_CS01 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L -//GCEA_ADDRDEC1_ADDR_SEL_CS23 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L -//GCEA_ADDRDEC1_COL_SEL_LO_CS01 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L -//GCEA_ADDRDEC1_COL_SEL_LO_CS23 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L -//GCEA_ADDRDEC1_COL_SEL_HI_CS01 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L -//GCEA_ADDRDEC1_COL_SEL_HI_CS23 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L -//GCEA_ADDRDEC1_RM_SEL_CS01 -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC1_RM_SEL_CS23 -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC1_RM_SEL_SECCS01 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC1_RM_SEL_SECCS23 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_IO_RD_CLI2GRP_MAP0 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//GCEA_IO_RD_CLI2GRP_MAP1 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//GCEA_IO_WR_CLI2GRP_MAP0 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//GCEA_IO_WR_CLI2GRP_MAP1 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//GCEA_IO_RD_COMBINE_FLUSH -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L -//GCEA_IO_WR_COMBINE_FLUSH -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L -//GCEA_IO_GROUP_BURST -#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 -#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 -#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 -#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 -#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL -#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L -#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L -#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L -//GCEA_IO_RD_PRI_AGE -#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//GCEA_IO_WR_PRI_AGE -#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//GCEA_IO_RD_PRI_QUEUING -#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//GCEA_IO_WR_PRI_QUEUING -#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//GCEA_IO_RD_PRI_FIXED -#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//GCEA_IO_WR_PRI_FIXED -#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//GCEA_IO_RD_PRI_URGENCY -#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//GCEA_IO_WR_PRI_URGENCY -#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//GCEA_IO_RD_PRI_URGENCY_MASK -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L -//GCEA_IO_WR_PRI_URGENCY_MASK -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L -//GCEA_IO_RD_PRI_QUANT_PRI1 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_IO_RD_PRI_QUANT_PRI2 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_IO_RD_PRI_QUANT_PRI3 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_IO_WR_PRI_QUANT_PRI1 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_IO_WR_PRI_QUANT_PRI2 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_IO_WR_PRI_QUANT_PRI3 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_SDP_ARB_DRAM -#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 -#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 -#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 -#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 -#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 -#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 -#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 -#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL -#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L -#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L -#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L -#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L -#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L -#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L -//GCEA_SDP_ARB_FINAL -#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 -#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 -#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa -#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf -#define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 -#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 -#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a -#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL -#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L -#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L -#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L -#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L -#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L -//GCEA_SDP_DRAM_PRIORITY -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L -//GCEA_SDP_IO_PRIORITY -#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 -#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 -#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 -#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc -#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 -#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 -#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 -#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c -#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL -#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L -#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L -#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L -#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L -#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L -#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L -#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L -//GCEA_SDP_CREDITS -#define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 -#define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 -#define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 -#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18 -#define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL -#define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L -#define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L -#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L -//GCEA_SDP_TAG_RESERVE0 -#define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 -#define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 -#define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 -#define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 -#define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL -#define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L -#define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L -#define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L -//GCEA_SDP_TAG_RESERVE1 -#define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 -#define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 -#define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 -#define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 -#define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL -#define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L -#define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L -#define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L -//GCEA_SDP_VCC_RESERVE0 -#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 -#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 -#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc -#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 -#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 -#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL -#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L -#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L -#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L -#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L -//GCEA_SDP_VCC_RESERVE1 -#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 -#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 -#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc -#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f -#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL -#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L -#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L -#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L -//GCEA_SDP_VCD_RESERVE0 -#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 -#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 -#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc -#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 -#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 -#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL -#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L -#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L -#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L -#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L -//GCEA_SDP_VCD_RESERVE1 -#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 -#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 -#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc -#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f -#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL -#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L -#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L -#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L -//GCEA_SDP_REQ_CNTL -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 -#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 -#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L -#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L -#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L -//GCEA_MISC -#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 -#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 -#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 -#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 -#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 -#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa -#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb -#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc -#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd -#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe -#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf -#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 -#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 -#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 -#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a -#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b -#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c -#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d -#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e -#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f -#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L -#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L -#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L -#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L -#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L -#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L -#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L -#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L -#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L -#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L -#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L -#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L -#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L -#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L -#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L -#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L -#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L -//GCEA_LATENCY_SAMPLING -#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa -#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb -#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc -#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd -#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe -#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L -//GCEA_PERFCOUNTER_LO -#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//GCEA_PERFCOUNTER_HI -#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L -//GCEA_PERFCOUNTER0_CFG -#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//GCEA_PERFCOUNTER1_CFG -#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//GCEA_PERFCOUNTER_RSLT_CNTL -#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - - -// addressBlock: gc_tcdec -//TCP_INVALIDATE -#define TCP_INVALIDATE__START__SHIFT 0x0 -#define TCP_INVALIDATE__START_MASK 0x00000001L -//TCP_STATUS -#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 -#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 -#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 -#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 -#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 -#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 -#define TCP_STATUS__READ_BUSY__SHIFT 0x6 -#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 -#define TCP_STATUS__VM_BUSY__SHIFT 0x8 -#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L -#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L -#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L -#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L -#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L -#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L -#define TCP_STATUS__READ_BUSY_MASK 0x00000040L -#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L -#define TCP_STATUS__VM_BUSY_MASK 0x00000100L -//TCP_CNTL -#define TCP_CNTL__FORCE_HIT__SHIFT 0x0 -#define TCP_CNTL__FORCE_MISS__SHIFT 0x1 -#define TCP_CNTL__L1_SIZE__SHIFT 0x2 -#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 -#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 -#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf -#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 -#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c -#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d -#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1e -#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L -#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L -#define TCP_CNTL__L1_SIZE_MASK 0x0000000CL -#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L -#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L -#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L -#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L -#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L -#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L -#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x40000000L -//TCP_CHAN_STEER_LO -#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0 -#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4 -#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8 -#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc -#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10 -#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14 -#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18 -#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c -#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000FL -#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000F0L -#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000F00L -#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000F000L -#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000F0000L -#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00F00000L -#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0F000000L -#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xF0000000L -//TCP_CHAN_STEER_HI -#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0 -#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4 -#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8 -#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc -#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10 -#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14 -#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18 -#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c -#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000FL -#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000F0L -#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000F00L -#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000F000L -#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000F0000L -#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00F00000L -#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0F000000L -#define TCP_CHAN_STEER_HI__CHANF_MASK 0xF0000000L -//TCP_ADDR_CONFIG -#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 -#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4 -#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6 -#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9 -#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000FL -#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L -#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001C0L -#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L -//TCP_CREDIT -#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 -#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 -#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d -#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003FFL -#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L -#define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L -//TCP_BUFFER_ADDR_HASH_CNTL -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L -//TCP_EDC_CNT -#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 -#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 -#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 -#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL -#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L -#define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L -//TC_CFG_L1_LOAD_POLICY0 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa -#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc -#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe -#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a -#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c -#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e -#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL -#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L -//TC_CFG_L1_LOAD_POLICY1 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa -#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc -#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe -#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a -#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c -#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e -#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL -#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L -//TC_CFG_L1_STORE_POLICY -#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 -#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 -#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 -#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 -#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 -#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 -#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 -#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 -#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 -#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 -#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa -#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb -#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc -#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd -#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe -#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf -#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 -#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 -#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 -#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 -#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 -#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 -#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 -#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 -#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 -#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 -#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a -#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b -#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c -#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d -#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e -#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f -#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L -#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L -#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L -#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L -#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L -#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L -#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L -#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L -#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L -#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L -#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L -#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L -#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L -#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L -#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L -#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L -#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L -#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L -#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L -#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L -#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L -#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L -#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L -#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L -#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L -//TC_CFG_L2_LOAD_POLICY0 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa -#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc -#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe -#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a -#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c -#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e -#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL -#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L -//TC_CFG_L2_LOAD_POLICY1 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa -#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc -#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe -#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a -#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c -#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e -#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL -#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L -//TC_CFG_L2_STORE_POLICY0 -#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 -#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 -#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 -#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 -#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 -#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa -#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc -#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe -#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 -#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 -#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 -#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 -#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 -#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a -#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c -#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e -#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L -#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL -#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L -#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L -#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L -#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L -#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L -//TC_CFG_L2_STORE_POLICY1 -#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 -#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 -#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 -#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 -#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 -#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa -#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc -#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe -#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 -#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 -#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 -#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 -#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 -#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a -#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c -#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e -#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L -#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL -#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L -#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L -#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L -#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L -#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L -//TC_CFG_L2_ATOMIC_POLICY -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L -//TC_CFG_L1_VOLATILE -#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 -#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL -//TC_CFG_L2_VOLATILE -#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 -#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL -//TCI_STATUS -#define TCI_STATUS__TCI_BUSY__SHIFT 0x0 -#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L -//TCI_CNTL_1 -#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 -#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 -#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 -#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL -#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L -#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L -//TCI_CNTL_2 -#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 -#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 -#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L -#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL -//TCC_CTRL -#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 -#define TCC_CTRL__RATE__SHIFT 0x2 -#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 -#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 -#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc -#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 -#define TCC_CTRL__LINEAR_SET_HASH__SHIFT 0x15 -#define TCC_CTRL__MDC_SIZE__SHIFT 0x18 -#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a -#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c -#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L -#define TCC_CTRL__RATE_MASK 0x0000000CL -#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L -#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L -#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L -#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L -#define TCC_CTRL__LINEAR_SET_HASH_MASK 0x00200000L -#define TCC_CTRL__MDC_SIZE_MASK 0x03000000L -#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0x0C000000L -#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L -//TCC_CTRL2 -#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0 -#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL -//TCC_EDC_CNT -#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0 -#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2 -#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4 -#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6 -#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8 -#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa -#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc -#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe -#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10 -#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12 -#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT__SHIFT 0x14 -#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT__SHIFT 0x16 -#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT__SHIFT 0x18 -#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT__SHIFT 0x1a -#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT__SHIFT 0x1c -#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT__SHIFT 0x1e -#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L -#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL -#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L -#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L -#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L -#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L -#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L -#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L -#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L -#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L -#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT_MASK 0x00300000L -#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT_MASK 0x00C00000L -#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT_MASK 0x03000000L -#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT_MASK 0x0C000000L -#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT_MASK 0x30000000L -#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT_MASK 0xC0000000L -//TCC_EDC_CNT2 -#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT__SHIFT 0x0 -#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT__SHIFT 0x2 -#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x4 -#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x6 -#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT 0x8 -#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK 0x00000003L -#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK 0x0000000CL -#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK 0x00000030L -#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK 0x000000C0L -#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK 0x00000300L -//TCC_REDUNDANCY -#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 -#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 -#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L -#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L -//TCC_EXE_DISABLE -#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1 -#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L -//TCC_DSM_CNTL -#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0 -#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 -#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12 -#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 -#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15 -#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 -#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18 -#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a -#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b -#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d -#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L -#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L -#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L -#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L -#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L -#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L -#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L -#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L -#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L -#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L -//TCC_DSM_CNTLA -#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0 -#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 -#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3 -#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 -#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6 -#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 -#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9 -#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb -#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc -#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe -#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf -#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 -#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12 -#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 -#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x15 -#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 -#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x18 -#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a -#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x1b -#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d -#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L -#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L -#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L -#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L -#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L -#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L -#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L -#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L -#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L -#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L -#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L -#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L -#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L -#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L -#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x00600000L -#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L -#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x03000000L -#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L -#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x18000000L -#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L -//TCC_DSM_CNTL2 -#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11 -#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14 -#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15 -#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17 -#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a -#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L -#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L -#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L -#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L -//TCC_DSM_CNTL2A -#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2 -#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5 -#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8 -#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb -#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc -#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe -#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf -#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11 -#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14 -#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15 -#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17 -#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 -#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a -#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x1b -#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1d -#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L -#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L -#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L -#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L -#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L -#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L -#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L -#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L -#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L -#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x18000000L -#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x20000000L -//TCC_DSM_CNTL2B -#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2 -#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 -#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L -//TCC_WBINVL2 -#define TCC_WBINVL2__DONE__SHIFT 0x4 -#define TCC_WBINVL2__DONE_MASK 0x00000010L -//TCC_SOFT_RESET -#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0 -#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L -//TCA_CTRL -#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 -#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4 -#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5 -#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6 -#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7 -#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL -#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L -#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L -#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L -#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L -//TCA_BURST_MASK -#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0 -#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL -//TCA_BURST_CTRL -#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0 -#define TCA_BURST_CTRL__RB_DISABLE__SHIFT 0x3 -#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4 -#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5 -#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6 -#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7 -#define TCA_BURST_CTRL__IA_DISABLE__SHIFT 0x8 -#define TCA_BURST_CTRL__WD_DISABLE__SHIFT 0x9 -#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa -#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb -#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc -#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd -#define TCA_BURST_CTRL__PA_DISABLE__SHIFT 0xe -#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L -#define TCA_BURST_CTRL__RB_DISABLE_MASK 0x00000008L -#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L -#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L -#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L -#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L -#define TCA_BURST_CTRL__IA_DISABLE_MASK 0x00000100L -#define TCA_BURST_CTRL__WD_DISABLE_MASK 0x00000200L -#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L -#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L -#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L -#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L -#define TCA_BURST_CTRL__PA_DISABLE_MASK 0x00004000L -//TCA_DSM_CNTL -#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0 -#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 -#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3 -#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 -#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L -#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L -#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L -#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L -//TCA_DSM_CNTL2 -#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2 -#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5 -#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a -#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L -#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L -//TCA_EDC_CNT -#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT__SHIFT 0x0 -#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT__SHIFT 0x2 -#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK 0x00000003L -#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK 0x0000000CL - - -// addressBlock: gc_shdec -//SPI_SHADER_PGM_RSRC3_PS -#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 -#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a -#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL -#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L -#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L -#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L -//SPI_SHADER_PGM_LO_PS -#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_HI_PS -#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL -//SPI_SHADER_PGM_RSRC1_PS -#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa -#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc -#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 -#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 -#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 -#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 -#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d -#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL -#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L -#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L -#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L -#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L -#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L -//SPI_SHADER_PGM_RSRC2_PS -#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 -#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 -#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 -#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 -#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a -#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c -#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL -#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L -#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L -#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L -#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L -#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L -#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L -//SPI_SHADER_USER_DATA_PS_0 -#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_1 -#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_2 -#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_3 -#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_4 -#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_5 -#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_6 -#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_7 -#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_8 -#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_9 -#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_10 -#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_11 -#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_12 -#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_13 -#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_14 -#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_15 -#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_16 -#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_17 -#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_18 -#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_19 -#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_20 -#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_21 -#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_22 -#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_23 -#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_24 -#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_25 -#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_26 -#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_27 -#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_28 -#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_29 -#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_30 -#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_31 -#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_RSRC3_VS -#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 -#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a -#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL -#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L -#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L -#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L -//SPI_SHADER_LATE_ALLOC_VS -#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 -#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL -//SPI_SHADER_PGM_LO_VS -#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_HI_VS -#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL -//SPI_SHADER_PGM_RSRC1_VS -#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa -#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc -#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 -#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 -#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 -#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 -#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a -#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f -#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL -#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L -#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L -#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L -#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L -#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L -#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L -//SPI_SHADER_PGM_RSRC2_VS -#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 -#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb -#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc -#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd -#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16 -#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 -#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c -#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL -#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L -#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L -#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L -#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L -#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L -//SPI_SHADER_USER_DATA_VS_0 -#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_1 -#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_2 -#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_3 -#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_4 -#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_5 -#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_6 -#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_7 -#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_8 -#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_9 -#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_10 -#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_11 -#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_12 -#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_13 -#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_14 -#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_15 -#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_16 -#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_17 -#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_18 -#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_19 -#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_20 -#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_21 -#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_22 -#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_23 -#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_24 -#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_25 -#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_26 -#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_27 -#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_28 -#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_29 -#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_30 -#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_31 -#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_RSRC2_GS_VS -#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1 -#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7 -#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12 -#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13 -#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b -#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c -#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL -#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L -#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L -#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L -#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L -#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L -//SPI_SHADER_PGM_RSRC4_GS -#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7 -#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL -#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L -//SPI_SHADER_USER_DATA_ADDR_LO_GS -#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ADDR_HI_GS -#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_LO_ES -#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_HI_ES -#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL -//SPI_SHADER_PGM_RSRC3_GS -#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 -#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a -#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL -#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L -#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L -#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L -//SPI_SHADER_PGM_LO_GS -#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_HI_GS -#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL -//SPI_SHADER_PGM_RSRC1_GS -#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa -#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc -#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 -#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 -#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 -#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 -#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d -#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f -#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL -#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L -#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L -#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L -#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L -#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L -#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L -//SPI_SHADER_PGM_RSRC2_GS -#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 -#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 -#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 -#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 -#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c -#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL -#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L -#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L -#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L -#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L -#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L -//SPI_SHADER_USER_DATA_ES_0 -#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_1 -#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_2 -#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_3 -#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_4 -#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_5 -#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_6 -#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_7 -#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_8 -#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_9 -#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_10 -#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_11 -#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_12 -#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_13 -#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_14 -#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_15 -#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_16 -#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_17 -#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_18 -#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_19 -#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_20 -#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_21 -#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_22 -#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_23 -#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_24 -#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_25 -#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_26 -#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_27 -#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_28 -#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_29 -#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_30 -#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_31 -#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_RSRC4_HS -#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL -//SPI_SHADER_USER_DATA_ADDR_LO_HS -#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ADDR_HI_HS -#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_LO_LS -#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_HI_LS -#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL -//SPI_SHADER_PGM_RSRC3_HS -#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa -#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL -#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L -#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L -#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L -//SPI_SHADER_PGM_LO_HS -#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_HI_HS -#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL -//SPI_SHADER_PGM_RSRC1_HS -#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa -#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc -#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 -#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 -#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 -#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c -#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e -#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL -#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L -#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L -#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L -#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L -#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L -//SPI_SHADER_PGM_RSRC2_HS -#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 -#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7 -#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c -#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL -#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L -#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L -#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L -//SPI_SHADER_USER_DATA_LS_0 -#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_1 -#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_2 -#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_3 -#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_4 -#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_5 -#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_6 -#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_7 -#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_8 -#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_9 -#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_10 -#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_11 -#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_12 -#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_13 -#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_14 -#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_15 -#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_16 -#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_17 -#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_18 -#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_19 -#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_20 -#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_21 -#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_22 -#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_23 -#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_24 -#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_25 -#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_26 -#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_27 -#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_28 -#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_29 -#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_30 -#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_31 -#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_0 -#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_1 -#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_2 -#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_3 -#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_4 -#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_5 -#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_6 -#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_7 -#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_8 -#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_9 -#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_10 -#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_11 -#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_12 -#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_13 -#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_14 -#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_15 -#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_16 -#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_17 -#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_18 -#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_19 -#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_20 -#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_21 -#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_22 -#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_23 -#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_24 -#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_25 -#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_26 -#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_27 -#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_28 -#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_29 -#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_30 -#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_31 -#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL -//COMPUTE_DISPATCH_INITIATOR -#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 -#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 -#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 -#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 -#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 -#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa -#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb -#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc -#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe -#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L -#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L -#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L -#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L -#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L -#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L -#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L -#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L -#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L -//COMPUTE_DIM_X -#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 -#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL -//COMPUTE_DIM_Y -#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 -#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL -//COMPUTE_DIM_Z -#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 -#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL -//COMPUTE_START_X -#define COMPUTE_START_X__START__SHIFT 0x0 -#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL -//COMPUTE_START_Y -#define COMPUTE_START_Y__START__SHIFT 0x0 -#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL -//COMPUTE_START_Z -#define COMPUTE_START_Z__START__SHIFT 0x0 -#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL -//COMPUTE_NUM_THREAD_X -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L -//COMPUTE_NUM_THREAD_Y -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L -//COMPUTE_NUM_THREAD_Z -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L -//COMPUTE_PIPELINESTAT_ENABLE -#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 -#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L -//COMPUTE_PERFCOUNT_ENABLE -#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 -#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L -//COMPUTE_PGM_LO -#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 -#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL -//COMPUTE_PGM_HI -#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 -#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL -//COMPUTE_DISPATCH_PKT_ADDR_LO -#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 -#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL -//COMPUTE_DISPATCH_PKT_ADDR_HI -#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 -#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL -//COMPUTE_DISPATCH_SCRATCH_BASE_LO -#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 -#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL -//COMPUTE_DISPATCH_SCRATCH_BASE_HI -#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 -#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL -//COMPUTE_PGM_RSRC1 -#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 -#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 -#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa -#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc -#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 -#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 -#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 -#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 -#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a -#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL -#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L -#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L -#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L -#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L -#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L -#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L -#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L -#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L -//COMPUTE_PGM_RSRC2 -#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 -#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 -#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 -#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 -#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 -#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 -#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa -#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb -#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd -#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf -#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 -#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f -#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L -#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL -#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L -#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L -#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L -#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L -#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L -#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L -#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L -#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L -#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L -#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L -//COMPUTE_VMID -#define COMPUTE_VMID__DATA__SHIFT 0x0 -#define COMPUTE_VMID__DATA_MASK 0x0000000FL -//COMPUTE_RESOURCE_LIMITS -#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 -#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc -#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 -#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 -#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 -#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 -#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b -#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL -#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L -#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L -#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L -#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L -#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L -#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L -//COMPUTE_STATIC_THREAD_MGMT_SE0 -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L -//COMPUTE_STATIC_THREAD_MGMT_SE1 -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L -//COMPUTE_TMPRING_SIZE -#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 -#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc -#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL -#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L -//COMPUTE_STATIC_THREAD_MGMT_SE2 -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L -//COMPUTE_STATIC_THREAD_MGMT_SE3 -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L -//COMPUTE_RESTART_X -#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 -#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL -//COMPUTE_RESTART_Y -#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 -#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL -//COMPUTE_RESTART_Z -#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 -#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL -//COMPUTE_THREAD_TRACE_ENABLE -#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 -#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L -//COMPUTE_MISC_RESERVED -#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 -#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 -#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 -#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 -#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 -#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L -#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L -#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L -#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L -#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L -//COMPUTE_DISPATCH_ID -#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 -#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL -//COMPUTE_THREADGROUP_ID -#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 -#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL -//COMPUTE_RELAUNCH -#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 -#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e -#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f -#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL -#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L -#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L -//COMPUTE_WAVE_RESTORE_ADDR_LO -#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 -#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL -//COMPUTE_WAVE_RESTORE_ADDR_HI -#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 -#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL -//COMPUTE_USER_DATA_0 -#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_1 -#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_2 -#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_3 -#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_4 -#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_5 -#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_6 -#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_7 -#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_8 -#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_9 -#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_10 -#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_11 -#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_12 -#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_13 -#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_14 -#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_15 -#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL -//COMPUTE_NOWHERE -#define COMPUTE_NOWHERE__DATA__SHIFT 0x0 -#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL - - -// addressBlock: gc_cppdec -//CP_DFY_CNTL -#define CP_DFY_CNTL__POLICY__SHIFT 0x0 -#define CP_DFY_CNTL__MTYPE__SHIFT 0x2 -#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a -#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c -#define CP_DFY_CNTL__MODE__SHIFT 0x1d -#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f -#define CP_DFY_CNTL__POLICY_MASK 0x00000001L -#define CP_DFY_CNTL__MTYPE_MASK 0x0000000CL -#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L -#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L -#define CP_DFY_CNTL__MODE_MASK 0x60000000L -#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L -//CP_DFY_STAT -#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 -#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 -#define CP_DFY_STAT__BUSY__SHIFT 0x1f -#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL -#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L -#define CP_DFY_STAT__BUSY_MASK 0x80000000L -//CP_DFY_ADDR_HI -#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL -//CP_DFY_ADDR_LO -#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 -#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L -//CP_DFY_DATA_0 -#define CP_DFY_DATA_0__DATA__SHIFT 0x0 -#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_1 -#define CP_DFY_DATA_1__DATA__SHIFT 0x0 -#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_2 -#define CP_DFY_DATA_2__DATA__SHIFT 0x0 -#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_3 -#define CP_DFY_DATA_3__DATA__SHIFT 0x0 -#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_4 -#define CP_DFY_DATA_4__DATA__SHIFT 0x0 -#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_5 -#define CP_DFY_DATA_5__DATA__SHIFT 0x0 -#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_6 -#define CP_DFY_DATA_6__DATA__SHIFT 0x0 -#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_7 -#define CP_DFY_DATA_7__DATA__SHIFT 0x0 -#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_8 -#define CP_DFY_DATA_8__DATA__SHIFT 0x0 -#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_9 -#define CP_DFY_DATA_9__DATA__SHIFT 0x0 -#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_10 -#define CP_DFY_DATA_10__DATA__SHIFT 0x0 -#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_11 -#define CP_DFY_DATA_11__DATA__SHIFT 0x0 -#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_12 -#define CP_DFY_DATA_12__DATA__SHIFT 0x0 -#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_13 -#define CP_DFY_DATA_13__DATA__SHIFT 0x0 -#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_14 -#define CP_DFY_DATA_14__DATA__SHIFT 0x0 -#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_15 -#define CP_DFY_DATA_15__DATA__SHIFT 0x0 -#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL -//CP_DFY_CMD -#define CP_DFY_CMD__OFFSET__SHIFT 0x0 -#define CP_DFY_CMD__SIZE__SHIFT 0x10 -#define CP_DFY_CMD__OFFSET_MASK 0x000001FFL -#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L -//CP_EOPQ_WAIT_TIME -#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 -#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa -#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL -#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L -//CP_CPC_MGCG_SYNC_CNTL -#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 -#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 -#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL -#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L -//CPC_INT_INFO -#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 -#define CPC_INT_INFO__TYPE__SHIFT 0x10 -#define CPC_INT_INFO__VMID__SHIFT 0x14 -#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c -#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL -#define CPC_INT_INFO__TYPE_MASK 0x00010000L -#define CPC_INT_INFO__VMID_MASK 0x00F00000L -#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L -//CP_VIRT_STATUS -#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 -#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL -//CPC_INT_ADDR -#define CPC_INT_ADDR__ADDR__SHIFT 0x0 -#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL -//CPC_INT_PASID -#define CPC_INT_PASID__PASID__SHIFT 0x0 -#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL -//CP_GFX_ERROR -#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0 -#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 -#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5 -#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6 -#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7 -#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8 -#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 -#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa -#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb -#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc -#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd -#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe -#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf -#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10 -#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11 -#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 -#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 -#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 -#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 -#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16 -#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 -#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 -#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 -#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a -#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b -#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c -#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d -#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e -#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f -#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL -#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L -#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L -#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L -#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L -#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L -#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L -#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L -#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L -#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L -#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L -#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L -#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L -#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L -#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L -#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L -#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L -#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L -#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L -#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L -#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L -#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L -#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L -#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L -#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L -#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L -#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L -#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L -#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L -//CPG_UTCL1_CNTL -#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 -#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e -#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L -#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L -//CPC_UTCL1_CNTL -#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e -#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L -//CPF_UTCL1_CNTL -#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 -#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e -#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f -#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L -#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L -#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L -//CP_AQL_SMM_STATUS -#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 -#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL -//CP_RB0_BASE -#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 -#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL -//CP_RB_BASE -#define CP_RB_BASE__RB_BASE__SHIFT 0x0 -#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL -//CP_RB0_CNTL -#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 -#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 -#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11 -#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 -#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 -#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 -#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b -#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f -#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL -#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L -#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L -#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L -#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L -#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L -//CP_RB_CNTL -#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 -#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 -#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 -#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 -#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 -#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b -#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f -#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL -#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L -#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L -#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L -#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L -//CP_RB_RPTR_WR -#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 -#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL -//CP_RB0_RPTR_ADDR -#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 -#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL -//CP_RB_RPTR_ADDR -#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 -#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL -//CP_RB0_RPTR_ADDR_HI -#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 -#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL -//CP_RB_RPTR_ADDR_HI -#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 -#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL -//CP_RB0_BUFSZ_MASK -#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 -#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL -//CP_RB_BUFSZ_MASK -#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 -#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL -//CP_RB_WPTR_POLL_ADDR_LO -#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 -#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL -//CP_RB_WPTR_POLL_ADDR_HI -#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 -#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL -//GC_PRIV_MODE -//CP_INT_CNTL -#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb -#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 -#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 -#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 -#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 -#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 -#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L -#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L -#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L -#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_INT_STATUS -#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb -#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe -#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 -#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 -#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 -#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 -#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 -#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 -#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 -#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 -#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 -#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a -#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b -#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d -#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e -#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f -#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L -#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L -#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L -#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L -#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L -#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L -#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L -//CP_DEVICE_ID -#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 -#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL -//CP_ME0_PIPE_PRIORITY_CNTS -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L -//CP_RING_PRIORITY_CNTS -#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 -#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 -#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 -#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 -#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL -#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L -#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L -#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L -//CP_ME0_PIPE0_PRIORITY -#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_RING0_PRIORITY -#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME0_PIPE1_PRIORITY -#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_RING1_PRIORITY -#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME0_PIPE2_PRIORITY -#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_RING2_PRIORITY -#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_FATAL_ERROR -#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 -#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 -#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 -#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 -#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 -#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L -#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L -#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L -#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L -#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L -//CP_RB_VMID -#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 -#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 -#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 -#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL -#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L -#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L -//CP_ME0_PIPE0_VMID -#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 -#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL -//CP_ME0_PIPE1_VMID -#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 -#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL -//CP_RB0_WPTR -#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 -#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL -//CP_RB_WPTR -#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 -#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL -//CP_RB0_WPTR_HI -#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 -#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL -//CP_RB_WPTR_HI -#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 -#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL -//CP_RB1_WPTR -#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 -#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL -//CP_RB1_WPTR_HI -#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0 -#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL -//CP_RB2_WPTR -#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 -#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL -//CP_RB_DOORBELL_CONTROL -#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 -#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L -#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_RANGE_LOWER -#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 -#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL -//CP_RB_DOORBELL_RANGE_UPPER -#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 -#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL -//CP_MEC_DOORBELL_RANGE_LOWER -#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 -#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL -//CP_MEC_DOORBELL_RANGE_UPPER -#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 -#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL -//CPG_UTCL1_ERROR -#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 -#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L -//CPC_UTCL1_ERROR -#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 -#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L -//CP_RB1_BASE -#define CP_RB1_BASE__RB_BASE__SHIFT 0x0 -#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL -//CP_RB1_CNTL -#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 -#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 -#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 -#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 -#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 -#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b -#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f -#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL -#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L -#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L -#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L -#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L -//CP_RB1_RPTR_ADDR -#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 -#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL -//CP_RB1_RPTR_ADDR_HI -#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 -#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL -//CP_RB2_BASE -#define CP_RB2_BASE__RB_BASE__SHIFT 0x0 -#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL -//CP_RB2_CNTL -#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 -#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 -#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 -#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 -#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 -#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b -#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f -#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL -#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L -#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L -#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L -#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L -//CP_RB2_RPTR_ADDR -#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 -#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL -//CP_RB2_RPTR_ADDR_HI -#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 -#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL -//CP_RB0_ACTIVE -#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 -#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L -//CP_RB_ACTIVE -#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 -#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L -//CP_INT_CNTL_RING0 -#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb -#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 -#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 -#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 -#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 -#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 -#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L -#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L -#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L -#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_INT_CNTL_RING1 -#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb -#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 -#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 -#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 -#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 -#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 -#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L -#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L -#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L -#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_INT_CNTL_RING2 -#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb -#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 -#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 -#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 -#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 -#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 -#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L -#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L -#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L -#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_INT_STATUS_RING0 -#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb -#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe -#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 -#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 -#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 -#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 -#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 -#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 -#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 -#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 -#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 -#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a -#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b -#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d -#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e -#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f -#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L -#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L -#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L -#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L -#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L -#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L -#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L -//CP_INT_STATUS_RING1 -#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb -#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe -#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10 -#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 -#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 -#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 -#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 -#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 -#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 -#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 -#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 -#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a -#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b -#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d -#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e -#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f -#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L -#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L -#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L -#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L -#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L -#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L -#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L -//CP_INT_STATUS_RING2 -#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb -#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe -#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10 -#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 -#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 -#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 -#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 -#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 -#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 -#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 -#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 -#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a -#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b -#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d -#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e -#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f -#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L -#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L -#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L -#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L -#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L -#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L -#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L -#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 -#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L -#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 -#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L -#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 -#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L -//CP_PWR_CNTL -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L -//CP_MEM_SLP_CNTL -#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 -#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 -#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 -#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 -#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 -#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 -#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 -#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L -#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L -#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL -#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L -#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L -#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L -#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L -//CP_ECC_FIRSTOCCURRENCE -#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 -#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 -#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 -#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa -#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc -#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 -#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L -#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L -#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L -#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L -#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L -#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L -//CP_ECC_FIRSTOCCURRENCE_RING0 -#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 -#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL -//CP_ECC_FIRSTOCCURRENCE_RING1 -#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 -#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL -//CP_ECC_FIRSTOCCURRENCE_RING2 -#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 -#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL -//GB_EDC_MODE -#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf -#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 -#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 -#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 -#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d -#define GB_EDC_MODE__BYPASS__SHIFT 0x1f -#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L -#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L -#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L -#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L -#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L -#define GB_EDC_MODE__BYPASS_MASK 0x80000000L -//CP_PQ_WPTR_POLL_CNTL -#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 -#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d -#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e -#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f -#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL -#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L -#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L -#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L -//CP_PQ_WPTR_POLL_CNTL1 -#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 -#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL -//CP_ME1_PIPE0_INT_CNTL -#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME1_PIPE1_INT_CNTL -#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME1_PIPE2_INT_CNTL -#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME1_PIPE3_INT_CNTL -#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME2_PIPE0_INT_CNTL -#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME2_PIPE1_INT_CNTL -#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME2_PIPE2_INT_CNTL -#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME2_PIPE3_INT_CNTL -#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME1_PIPE0_INT_STATUS -#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME1_PIPE1_INT_STATUS -#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME1_PIPE2_INT_STATUS -#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME1_PIPE3_INT_STATUS -#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME2_PIPE0_INT_STATUS -#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME2_PIPE1_INT_STATUS -#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME2_PIPE2_INT_STATUS -#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME2_PIPE3_INT_STATUS -#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 -#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L -#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 -#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L -//CC_GC_EDC_CONFIG -#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 -#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L -//CP_ME1_PIPE_PRIORITY_CNTS -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L -//CP_ME1_PIPE0_PRIORITY -#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME1_PIPE1_PRIORITY -#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME1_PIPE2_PRIORITY -#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME1_PIPE3_PRIORITY -#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME2_PIPE_PRIORITY_CNTS -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L -//CP_ME2_PIPE0_PRIORITY -#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME2_PIPE1_PRIORITY -#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME2_PIPE2_PRIORITY -#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME2_PIPE3_PRIORITY -#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_CE_PRGRM_CNTR_START -#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 -#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL -//CP_PFP_PRGRM_CNTR_START -#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 -#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL -//CP_ME_PRGRM_CNTR_START -#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 -#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL -//CP_MEC1_PRGRM_CNTR_START -#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 -#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL -//CP_MEC2_PRGRM_CNTR_START -#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 -#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL -//CP_CE_INTR_ROUTINE_START -#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 -#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL -//CP_PFP_INTR_ROUTINE_START -#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 -#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL -//CP_ME_INTR_ROUTINE_START -#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 -#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL -//CP_MEC1_INTR_ROUTINE_START -#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 -#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL -//CP_MEC2_INTR_ROUTINE_START -#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 -#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL -//CP_CONTEXT_CNTL -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L -//CP_MAX_CONTEXT -#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 -#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L -//CP_IQ_WAIT_TIME1 -#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 -#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 -#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 -#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 -#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL -#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L -#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L -#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L -//CP_IQ_WAIT_TIME2 -#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 -#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 -#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 -#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 -#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL -#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L -#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L -#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L -//CP_RB0_BASE_HI -#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 -#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL -//CP_RB1_BASE_HI -#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 -#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL -//CP_VMID_RESET -#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 -#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL -//CPC_INT_CNTL -#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CPC_INT_STATUS -#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_VMID_PREEMPT -#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 -#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 -#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL -#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L -//CPC_INT_CNTX_ID -#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 -#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL -//CP_PQ_STATUS -#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 -#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 -#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L -#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L -//CP_CPC_IC_BASE_LO -#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc -#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L -//CP_CPC_IC_BASE_HI -#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 -#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL -//CP_CPC_IC_BASE_CNTL -#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 -#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 -#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL -#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L -//CP_CPC_IC_OP_CNTL -#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 -#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 -#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 -#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L -#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L -#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L -//CP_MEC1_F32_INT_DIS -#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 -#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 -#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 -#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 -#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 -#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 -#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 -#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 -#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 -#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 -#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa -#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb -#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc -#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd -#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe -#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf -#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L -#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L -#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L -#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L -#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L -#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L -#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L -#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L -#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L -#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L -#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L -#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L -#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L -#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L -#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L -#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L -//CP_MEC2_F32_INT_DIS -#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 -#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 -#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 -#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 -#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 -#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 -#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 -#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 -#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 -#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 -#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa -#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb -#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc -#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd -#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe -#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf -#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L -#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L -#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L -#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L -#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L -#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L -#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L -#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L -#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L -#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L -#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L -#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L -#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L -#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L -#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L -#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L -//CP_VMID_STATUS -#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 -#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 -#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL -#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L - - -// addressBlock: gc_cppdec2 -//CP_RB_DOORBELL_CONTROL_SCH_0 -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_1 -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_2 -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_3 -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_4 -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_5 -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_6 -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_7 -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CLEAR -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 -#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa -#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb -#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc -#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L -#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L -#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L -#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L -#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L -//CP_GFX_MQD_CONTROL -#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 -#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 -#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 -#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL -#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L -#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L -//CP_GFX_MQD_BASE_ADDR -#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 -#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL -//CP_GFX_MQD_BASE_ADDR_HI -#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 -#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL -//CP_RB_STATUS -#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 -#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 -#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L -#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L -//CPG_UTCL1_STATUS -#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 -#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 -#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 -#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L -#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L -#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L -//CPC_UTCL1_STATUS -#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 -#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 -#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 -#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L -#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L -#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L -//CPF_UTCL1_STATUS -#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 -#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 -#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 -#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L -#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L -#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L -//CP_SD_CNTL -#define CP_SD_CNTL__CPF_EN__SHIFT 0x0 -#define CP_SD_CNTL__CPG_EN__SHIFT 0x1 -#define CP_SD_CNTL__CPC_EN__SHIFT 0x2 -#define CP_SD_CNTL__RLC_EN__SHIFT 0x3 -#define CP_SD_CNTL__SPI_EN__SHIFT 0x4 -#define CP_SD_CNTL__WD_EN__SHIFT 0x5 -#define CP_SD_CNTL__IA_EN__SHIFT 0x6 -#define CP_SD_CNTL__PA_EN__SHIFT 0x7 -#define CP_SD_CNTL__RMI_EN__SHIFT 0x8 -#define CP_SD_CNTL__EA_EN__SHIFT 0x9 -#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L -#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L -#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L -#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L -#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L -#define CP_SD_CNTL__WD_EN_MASK 0x00000020L -#define CP_SD_CNTL__IA_EN_MASK 0x00000040L -#define CP_SD_CNTL__PA_EN_MASK 0x00000080L -#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L -#define CP_SD_CNTL__EA_EN_MASK 0x00000200L -//CP_SOFT_RESET_CNTL -#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 -#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 -#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 -#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 -#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 -#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 -#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 -#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L -#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L -#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L -#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L -#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L -#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L -#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L -//CP_CPC_GFX_CNTL -#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 -#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 -#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 -#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 -#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L -#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L -#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L -#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L - - -// addressBlock: gc_spipdec -//SPI_ARB_PRIORITY -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 -#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc -#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe -#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 -#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L -#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L -#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L -#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L -#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L -//SPI_ARB_CYCLES_0 -#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 -#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 -#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL -#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L -//SPI_ARB_CYCLES_1 -#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 -#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 -#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL -#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L -//SPI_WCL_PIPE_PERCENT_GFX -#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 -#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc -#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 -#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 -#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL -#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L -#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L -#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L -#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L -//SPI_WCL_PIPE_PERCENT_HP3D -#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc -#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 -#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL -#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L -#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L -//SPI_WCL_PIPE_PERCENT_CS0 -#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS1 -#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS2 -#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS3 -#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS4 -#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS5 -#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS6 -#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS7 -#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL -//SPI_COMPUTE_QUEUE_RESET -#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 -#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L -//SPI_RESOURCE_RESERVE_CU_0 -#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_1 -#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_2 -#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_3 -#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_4 -#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_5 -#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_6 -#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_7 -#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_8 -#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_9 -#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_EN_CU_0 -#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_1 -#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_2 -#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_3 -#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_4 -#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_5 -#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_6 -#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_7 -#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_8 -#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_9 -#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_CU_10 -#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_11 -#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_EN_CU_10 -#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_11 -#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_CU_12 -#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_13 -#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_14 -#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_15 -#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_EN_CU_12 -#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_13 -#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_14 -#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_15 -#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_COMPUTE_WF_CTX_SAVE -#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 -#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e -#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f -#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L -#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L -#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L -//SPI_ARB_CNTL_0 -#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 -#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 -#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 -#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL -#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L -#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L - - -// addressBlock: gc_cpphqddec -//CP_HQD_GFX_CONTROL -#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 -#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 -#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf -#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL -#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L -#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L -//CP_HQD_GFX_STATUS -#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 -#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL -//CP_HPD_ROQ_OFFSETS -#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 -#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 -#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 -#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L -#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L -#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L -//CP_HPD_STATUS0 -#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 -#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 -#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 -#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 -#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 -#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 -#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 -#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f -#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL -#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L -#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L -#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L -#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L -#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L -#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L -#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L -//CP_HPD_UTCL1_CNTL -#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 -#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL -//CP_HPD_UTCL1_ERROR -#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 -#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10 -#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14 -#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL -#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L -#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L -//CP_HPD_UTCL1_ERROR_ADDR -#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc -#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L -//CP_MQD_BASE_ADDR -#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 -#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL -//CP_MQD_BASE_ADDR_HI -#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 -#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL -//CP_HQD_ACTIVE -#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 -#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 -#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L -#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L -//CP_HQD_VMID -#define CP_HQD_VMID__VMID__SHIFT 0x0 -#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 -#define CP_HQD_VMID__VQID__SHIFT 0x10 -#define CP_HQD_VMID__VMID_MASK 0x0000000FL -#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L -#define CP_HQD_VMID__VQID_MASK 0x03FF0000L -//CP_HQD_PERSISTENT_STATE -#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 -#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 -#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 -#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 -#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 -#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 -#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 -#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a -#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b -#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c -#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d -#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e -#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f -#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L -#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L -#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L -#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L -#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L -#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L -#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L -#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L -#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L -#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L -#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L -#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L -#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L -//CP_HQD_PIPE_PRIORITY -#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 -#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L -//CP_HQD_QUEUE_PRIORITY -#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 -#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL -//CP_HQD_QUANTUM -#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 -#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 -#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 -#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f -#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L -#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L -#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L -#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L -//CP_HQD_PQ_BASE -#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 -#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL -//CP_HQD_PQ_BASE_HI -#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 -#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL -//CP_HQD_PQ_RPTR -#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 -#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL -//CP_HQD_PQ_RPTR_REPORT_ADDR -#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 -#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL -//CP_HQD_PQ_RPTR_REPORT_ADDR_HI -#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 -#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL -//CP_HQD_PQ_WPTR_POLL_ADDR -#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 -#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L -//CP_HQD_PQ_WPTR_POLL_ADDR_HI -#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 -#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL -//CP_HQD_PQ_DOORBELL_CONTROL -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L -//CP_HQD_PQ_CONTROL -#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 -#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 -#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 -#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 -#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe -#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf -#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10 -#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11 -#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 -#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 -#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 -#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 -#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b -#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c -#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d -#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e -#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f -#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL -#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L -#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L -#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L -#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L -#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L -#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L -#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L -#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L -#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L -#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L -#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L -#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L -#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L -#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L -#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L -#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L -//CP_HQD_IB_BASE_ADDR -#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 -#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL -//CP_HQD_IB_BASE_ADDR_HI -#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 -#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL -//CP_HQD_IB_RPTR -#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 -#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL -//CP_HQD_IB_CONTROL -#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 -#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 -#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 -#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 -#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f -#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL -#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L -#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L -#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L -#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L -//CP_HQD_IQ_TIMER -#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 -#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 -#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb -#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc -#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe -#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 -#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 -#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 -#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 -#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19 -#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c -#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d -#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e -#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f -#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL -#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L -#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L -#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L -#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L -#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L -#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L -#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L -#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L -#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L -#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L -#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L -#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L -#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L -//CP_HQD_IQ_RPTR -#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 -#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL -//CP_HQD_DEQUEUE_REQUEST -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L -//CP_HQD_DMA_OFFLOAD -#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 -#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L -//CP_HQD_OFFLOAD -#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 -#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 -#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 -#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 -#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 -#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 -#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L -#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L -#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L -#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L -#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L -#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L -//CP_HQD_SEMA_CMD -#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 -#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 -#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L -#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L -//CP_HQD_MSG_TYPE -#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 -#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 -#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L -#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L -//CP_HQD_ATOMIC0_PREOP_LO -#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 -#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL -//CP_HQD_ATOMIC0_PREOP_HI -#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 -#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL -//CP_HQD_ATOMIC1_PREOP_LO -#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 -#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL -//CP_HQD_ATOMIC1_PREOP_HI -#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 -#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL -//CP_HQD_HQ_SCHEDULER0 -#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 -#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL -//CP_HQD_HQ_STATUS0 -#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 -#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 -#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 -#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 -#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 -#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 -#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa -#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e -#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f -#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L -#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL -#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L -#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L -#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L -#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L -#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L -#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L -#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L -//CP_HQD_HQ_CONTROL0 -#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 -#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL -//CP_HQD_HQ_SCHEDULER1 -#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 -#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL -//CP_MQD_CONTROL -#define CP_MQD_CONTROL__VMID__SHIFT 0x0 -#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 -#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc -#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd -#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 -#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 -#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL -#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L -#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L -#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L -#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L -#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L -//CP_HQD_HQ_STATUS1 -#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 -#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL -//CP_HQD_HQ_CONTROL1 -#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 -#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL -//CP_HQD_EOP_BASE_ADDR -#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 -#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL -//CP_HQD_EOP_BASE_ADDR_HI -#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 -#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL -//CP_HQD_EOP_CONTROL -#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 -#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 -#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc -#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd -#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe -#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 -#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 -#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 -#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 -#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d -#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f -#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL -#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L -#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L -#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L -#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L -#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L -#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L -#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L -#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L -#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L -#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L -//CP_HQD_EOP_RPTR -#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 -#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c -#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d -#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e -#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f -#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL -#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L -#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L -#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L -#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L -//CP_HQD_EOP_WPTR -#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 -#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf -#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 -#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL -#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L -#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L -//CP_HQD_EOP_EVENTS -#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 -#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 -#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL -#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L -//CP_HQD_CTX_SAVE_BASE_ADDR_LO -#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc -#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L -//CP_HQD_CTX_SAVE_BASE_ADDR_HI -#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_HQD_CTX_SAVE_CONTROL -#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 -#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 -#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L -#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L -//CP_HQD_CNTL_STACK_OFFSET -#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 -#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL -//CP_HQD_CNTL_STACK_SIZE -#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc -#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L -//CP_HQD_WG_STATE_OFFSET -#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 -#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL -//CP_HQD_CTX_SAVE_SIZE -#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc -#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L -//CP_HQD_GDS_RESOURCE_STATE -#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 -#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 -#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 -#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc -#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L -#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L -#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L -#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L -//CP_HQD_ERROR -#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 -#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 -#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 -#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 -#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 -#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa -#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb -#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc -#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd -#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe -#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf -#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 -#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 -#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 -#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 -#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL -#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L -#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L -#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L -#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L -#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L -#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L -#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L -#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L -#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L -#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L -#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L -#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L -#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L -#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L -//CP_HQD_EOP_WPTR_MEM -#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 -#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL -//CP_HQD_AQL_CONTROL -#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 -#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf -#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 -#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f -#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL -#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L -#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L -#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L -//CP_HQD_PQ_WPTR_LO -#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 -#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL -//CP_HQD_PQ_WPTR_HI -#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 -#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL - - -// addressBlock: gc_didtdec -//DIDT_IND_INDEX -#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 -#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL -//DIDT_IND_DATA -#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 -#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL - - -// addressBlock: gc_gccacdec -//GC_CAC_CTRL_1 -#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 -#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18 -#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL -#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L -//GC_CAC_CTRL_2 -#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 -#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1 -#define GC_CAC_CTRL_2__UNUSED_0__SHIFT 0x2 -#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L -#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L -#define GC_CAC_CTRL_2__UNUSED_0_MASK 0xFFFFFFFCL -//GC_CAC_CGTT_CLK_CTRL -#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f -#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -//GC_CAC_AGGR_LOWER -#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0 -#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_AGGR_UPPER -#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0 -#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL -//GC_CAC_PG_AGGR_LOWER -#define GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT 0x0 -#define GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_PG_AGGR_UPPER -#define GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT 0x0 -#define GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32_MASK 0xFFFFFFFFL -//GC_CAC_SOFT_CTRL -#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0 -#define GC_CAC_SOFT_CTRL__UNUSED__SHIFT 0x1 -#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L -#define GC_CAC_SOFT_CTRL__UNUSED_MASK 0xFFFFFFFEL -//GC_DIDT_CTRL0 -#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 -#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1 -#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3 -#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 -#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5 -#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L -#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L -//GC_DIDT_CTRL1 -#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0 -#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10 -#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL -#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L -//GC_DIDT_CTRL2 -#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 -#define GC_DIDT_CTRL2__UNUSED_0__SHIFT 0xe -#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define GC_DIDT_CTRL2__UNUSED_1__SHIFT 0x1a -#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define GC_DIDT_CTRL2__UNUSED_2__SHIFT 0x1f -#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define GC_DIDT_CTRL2__UNUSED_0_MASK 0x0000C000L -#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define GC_DIDT_CTRL2__UNUSED_1_MASK 0x04000000L -#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define GC_DIDT_CTRL2__UNUSED_2_MASK 0x80000000L -//GC_DIDT_WEIGHT -#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0 -#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8 -#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10 -#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18 -#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL -#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L -#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L -#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L -//GC_EDC_CTRL -#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 -#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 -#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 -#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 -#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9 -#define GC_EDC_CTRL__UNUSED_0__SHIFT 0xa -#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L -#define GC_EDC_CTRL__UNUSED_0_MASK 0xFFFFFC00L -//GC_EDC_THRESHOLD -#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 -#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL -//GC_EDC_STATUS -#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0 -#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA__SHIFT 0x3 -#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L -#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA_MASK 0x03FFFFF8L -//GC_EDC_OVERFLOW -#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 -#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 -#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW__SHIFT 0x11 -#define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT 0x12 -#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL -#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW_MASK 0x00020000L -#define GC_EDC_OVERFLOW__PSM_COUNTER_MASK 0xFFFC0000L -//GC_EDC_ROLLING_POWER_DELTA -#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 -#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL -//GC_DIDT_DROOP_CTRL -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT 0x0 -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT 0x1 -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT 0xf -#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT 0x13 -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT 0x1f -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK 0x00000001L -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK 0x00007FFEL -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK 0x00078000L -#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK 0x00080000L -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK 0x80000000L -//GC_EDC_DROOP_CTRL -#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT 0x0 -#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT 0x1 -#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT 0xf -#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT 0x14 -#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT 0x15 -#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK 0x00000001L -#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK 0x00007FFEL -#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK 0x000F8000L -#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK 0x00100000L -#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK 0x00200000L -//GC_CAC_IND_INDEX -#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 -#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL -//GC_CAC_IND_DATA -#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 -#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL -//SE_CAC_CGTT_CLK_CTRL -#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f -#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -//SE_CAC_IND_INDEX -#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 -#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL -//SE_CAC_IND_DATA -#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 -#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL - - -// addressBlock: gc_tcpdec -//TCP_WATCH0_ADDR_H -#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 -#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL -//TCP_WATCH0_ADDR_L -#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 -#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L -//TCP_WATCH0_CNTL -#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 -#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 -#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c -#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d -#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f -#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL -#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L -#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L -#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L -#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L -//TCP_WATCH1_ADDR_H -#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 -#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL -//TCP_WATCH1_ADDR_L -#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 -#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L -//TCP_WATCH1_CNTL -#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 -#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 -#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c -#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d -#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f -#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL -#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L -#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L -#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L -#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L -//TCP_WATCH2_ADDR_H -#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 -#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL -//TCP_WATCH2_ADDR_L -#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 -#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L -//TCP_WATCH2_CNTL -#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 -#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 -#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c -#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d -#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f -#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL -#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L -#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L -#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L -#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L -//TCP_WATCH3_ADDR_H -#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 -#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL -//TCP_WATCH3_ADDR_L -#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 -#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L -//TCP_WATCH3_CNTL -#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 -#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 -#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c -#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d -#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f -#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL -#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L -#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L -#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L -#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L -//TCP_GATCL1_CNTL -#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19 -#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a -#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b -#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L -#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L -#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L -#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//TCP_ATC_EDC_GATCL1_CNT -#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 -#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL -//TCP_GATCL1_DSM_CNTL -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0 -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1 -#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L -#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L -//TCP_CNTL2 -#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 -#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL -//TCP_UTCL1_CNTL1 -#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 -#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 -#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 -#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 -#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 -#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 -#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 -#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 -#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 -#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 -#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a -#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L -#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L -#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L -#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L -#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L -#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L -#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//TCP_UTCL1_CNTL2 -#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0 -#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 -#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa -#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc -#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe -#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf -#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a -#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL -#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L -#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -//TCP_UTCL1_STATUS -#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -//TCP_PERFCOUNTER_FILTER -#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 -#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 -#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 -#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 -#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb -#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf -#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14 -#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16 -#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19 -#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a -#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b -#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c -#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L -#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L -#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL -#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L -#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L -#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L -#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L -#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L -#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L -#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L -#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L -#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L -//TCP_PERFCOUNTER_FILTER_EN -#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 -#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 -#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 -#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 -#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 -#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 -#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 -#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 -#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8 -#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9 -#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa -#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb -#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L -#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L -#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L -#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L -#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L -#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L -#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L -#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L -#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L -#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L -#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L -#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L - - -// addressBlock: gc_gdspdec -//GDS_VMID0_BASE -#define GDS_VMID0_BASE__BASE__SHIFT 0x0 -#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID0_SIZE -#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID1_BASE -#define GDS_VMID1_BASE__BASE__SHIFT 0x0 -#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID1_SIZE -#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID2_BASE -#define GDS_VMID2_BASE__BASE__SHIFT 0x0 -#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID2_SIZE -#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID3_BASE -#define GDS_VMID3_BASE__BASE__SHIFT 0x0 -#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID3_SIZE -#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID4_BASE -#define GDS_VMID4_BASE__BASE__SHIFT 0x0 -#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID4_SIZE -#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID5_BASE -#define GDS_VMID5_BASE__BASE__SHIFT 0x0 -#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID5_SIZE -#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID6_BASE -#define GDS_VMID6_BASE__BASE__SHIFT 0x0 -#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID6_SIZE -#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID7_BASE -#define GDS_VMID7_BASE__BASE__SHIFT 0x0 -#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID7_SIZE -#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID8_BASE -#define GDS_VMID8_BASE__BASE__SHIFT 0x0 -#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID8_SIZE -#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID9_BASE -#define GDS_VMID9_BASE__BASE__SHIFT 0x0 -#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID9_SIZE -#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID10_BASE -#define GDS_VMID10_BASE__BASE__SHIFT 0x0 -#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID10_SIZE -#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID11_BASE -#define GDS_VMID11_BASE__BASE__SHIFT 0x0 -#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID11_SIZE -#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID12_BASE -#define GDS_VMID12_BASE__BASE__SHIFT 0x0 -#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID12_SIZE -#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID13_BASE -#define GDS_VMID13_BASE__BASE__SHIFT 0x0 -#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID13_SIZE -#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID14_BASE -#define GDS_VMID14_BASE__BASE__SHIFT 0x0 -#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID14_SIZE -#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID15_BASE -#define GDS_VMID15_BASE__BASE__SHIFT 0x0 -#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID15_SIZE -#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_GWS_VMID0 -#define GDS_GWS_VMID0__BASE__SHIFT 0x0 -#define GDS_GWS_VMID0__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID1 -#define GDS_GWS_VMID1__BASE__SHIFT 0x0 -#define GDS_GWS_VMID1__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID2 -#define GDS_GWS_VMID2__BASE__SHIFT 0x0 -#define GDS_GWS_VMID2__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID3 -#define GDS_GWS_VMID3__BASE__SHIFT 0x0 -#define GDS_GWS_VMID3__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID4 -#define GDS_GWS_VMID4__BASE__SHIFT 0x0 -#define GDS_GWS_VMID4__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID5 -#define GDS_GWS_VMID5__BASE__SHIFT 0x0 -#define GDS_GWS_VMID5__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID6 -#define GDS_GWS_VMID6__BASE__SHIFT 0x0 -#define GDS_GWS_VMID6__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID7 -#define GDS_GWS_VMID7__BASE__SHIFT 0x0 -#define GDS_GWS_VMID7__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID8 -#define GDS_GWS_VMID8__BASE__SHIFT 0x0 -#define GDS_GWS_VMID8__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID9 -#define GDS_GWS_VMID9__BASE__SHIFT 0x0 -#define GDS_GWS_VMID9__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID10 -#define GDS_GWS_VMID10__BASE__SHIFT 0x0 -#define GDS_GWS_VMID10__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID11 -#define GDS_GWS_VMID11__BASE__SHIFT 0x0 -#define GDS_GWS_VMID11__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID12 -#define GDS_GWS_VMID12__BASE__SHIFT 0x0 -#define GDS_GWS_VMID12__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID13 -#define GDS_GWS_VMID13__BASE__SHIFT 0x0 -#define GDS_GWS_VMID13__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID14 -#define GDS_GWS_VMID14__BASE__SHIFT 0x0 -#define GDS_GWS_VMID14__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID15 -#define GDS_GWS_VMID15__BASE__SHIFT 0x0 -#define GDS_GWS_VMID15__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L -//GDS_OA_VMID0 -#define GDS_OA_VMID0__MASK__SHIFT 0x0 -#define GDS_OA_VMID0__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID1 -#define GDS_OA_VMID1__MASK__SHIFT 0x0 -#define GDS_OA_VMID1__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID2 -#define GDS_OA_VMID2__MASK__SHIFT 0x0 -#define GDS_OA_VMID2__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID3 -#define GDS_OA_VMID3__MASK__SHIFT 0x0 -#define GDS_OA_VMID3__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID4 -#define GDS_OA_VMID4__MASK__SHIFT 0x0 -#define GDS_OA_VMID4__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID5 -#define GDS_OA_VMID5__MASK__SHIFT 0x0 -#define GDS_OA_VMID5__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID6 -#define GDS_OA_VMID6__MASK__SHIFT 0x0 -#define GDS_OA_VMID6__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID7 -#define GDS_OA_VMID7__MASK__SHIFT 0x0 -#define GDS_OA_VMID7__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID8 -#define GDS_OA_VMID8__MASK__SHIFT 0x0 -#define GDS_OA_VMID8__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID9 -#define GDS_OA_VMID9__MASK__SHIFT 0x0 -#define GDS_OA_VMID9__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID10 -#define GDS_OA_VMID10__MASK__SHIFT 0x0 -#define GDS_OA_VMID10__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID11 -#define GDS_OA_VMID11__MASK__SHIFT 0x0 -#define GDS_OA_VMID11__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID12 -#define GDS_OA_VMID12__MASK__SHIFT 0x0 -#define GDS_OA_VMID12__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID13 -#define GDS_OA_VMID13__MASK__SHIFT 0x0 -#define GDS_OA_VMID13__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID14 -#define GDS_OA_VMID14__MASK__SHIFT 0x0 -#define GDS_OA_VMID14__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID15 -#define GDS_OA_VMID15__MASK__SHIFT 0x0 -#define GDS_OA_VMID15__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L -//GDS_GWS_RESET0 -#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 -#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 -#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 -#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 -#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 -#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 -#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 -#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 -#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 -#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 -#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa -#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb -#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc -#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd -#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe -#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf -#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 -#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 -#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 -#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 -#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 -#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 -#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 -#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 -#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 -#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 -#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a -#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b -#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c -#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d -#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e -#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f -#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L -#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L -#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L -#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L -#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L -#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L -#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L -#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L -#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L -#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L -#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L -#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L -#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L -#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L -#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L -#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L -#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L -#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L -#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L -#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L -#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L -#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L -#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L -#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L -#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L -#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L -#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L -#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L -#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L -#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L -#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L -#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L -//GDS_GWS_RESET1 -#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 -#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 -#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 -#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 -#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 -#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 -#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 -#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 -#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 -#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 -#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa -#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb -#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc -#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd -#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe -#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf -#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 -#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 -#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 -#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 -#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 -#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 -#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 -#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 -#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 -#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 -#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a -#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b -#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c -#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d -#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e -#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f -#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L -#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L -#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L -#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L -#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L -#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L -#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L -#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L -#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L -#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L -#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L -#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L -#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L -#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L -#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L -#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L -#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L -#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L -#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L -#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L -#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L -#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L -#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L -#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L -#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L -#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L -#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L -#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L -#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L -#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L -#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L -#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L -//GDS_GWS_RESOURCE_RESET -#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 -#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 -#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L -#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L -//GDS_COMPUTE_MAX_WAVE_ID -#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 -#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL -//GDS_OA_RESET_MASK -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 -#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3 -#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 -#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 -#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 -#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 -#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 -#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 -#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa -#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb -#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L -#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L -#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L -#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L -#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L -#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L -#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L -#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L -#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L -#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L -#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L -//GDS_OA_RESET -#define GDS_OA_RESET__RESET__SHIFT 0x0 -#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 -#define GDS_OA_RESET__RESET_MASK 0x00000001L -#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L -//GDS_ENHANCE -#define GDS_ENHANCE__MISC__SHIFT 0x0 -#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 -#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 -#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12 -#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13 -#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14 -#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15 -#define GDS_ENHANCE__UNUSED__SHIFT 0x16 -#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL -#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L -#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L -#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L -#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L -#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L -#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L -#define GDS_ENHANCE__UNUSED_MASK 0xFFC00000L -//GDS_OA_CGPG_RESTORE -#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 -#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 -#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc -#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 -#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 -#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL -#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L -#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L -#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L -#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L -//GDS_CS_CTXSW_STATUS -#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 -#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 -#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 -#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L -#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L -#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL -//GDS_CS_CTXSW_CNT0 -#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_CS_CTXSW_CNT1 -#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_CS_CTXSW_CNT2 -#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_CS_CTXSW_CNT3 -#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_GFX_CTXSW_STATUS -#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 -#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 -#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 -#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L -#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L -#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL -//GDS_VS_CTXSW_CNT0 -#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_VS_CTXSW_CNT1 -#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_VS_CTXSW_CNT2 -#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_VS_CTXSW_CNT3 -#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS0_CTXSW_CNT0 -#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS0_CTXSW_CNT1 -#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS0_CTXSW_CNT2 -#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS0_CTXSW_CNT3 -#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS1_CTXSW_CNT0 -#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS1_CTXSW_CNT1 -#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS1_CTXSW_CNT2 -#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS1_CTXSW_CNT3 -#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS2_CTXSW_CNT0 -#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS2_CTXSW_CNT1 -#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS2_CTXSW_CNT2 -#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS2_CTXSW_CNT3 -#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS3_CTXSW_CNT0 -#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS3_CTXSW_CNT1 -#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS3_CTXSW_CNT2 -#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS3_CTXSW_CNT3 -#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS4_CTXSW_CNT0 -#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS4_CTXSW_CNT1 -#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS4_CTXSW_CNT2 -#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS4_CTXSW_CNT3 -#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS5_CTXSW_CNT0 -#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS5_CTXSW_CNT1 -#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS5_CTXSW_CNT2 -#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS5_CTXSW_CNT3 -#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS6_CTXSW_CNT0 -#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS6_CTXSW_CNT1 -#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS6_CTXSW_CNT2 -#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS6_CTXSW_CNT3 -#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS7_CTXSW_CNT0 -#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS7_CTXSW_CNT1 -#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS7_CTXSW_CNT2 -#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS7_CTXSW_CNT3 -#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_GS_CTXSW_CNT0 -#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_GS_CTXSW_CNT1 -#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_GS_CTXSW_CNT2 -#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_GS_CTXSW_CNT3 -#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L - - -// addressBlock: gc_rasdec -//RAS_SIGNATURE_CONTROL -#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 -#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L -//RAS_SIGNATURE_MASK -#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 -#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xFFFFFFFFL -//RAS_SX_SIGNATURE0 -#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SX_SIGNATURE1 -#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 -#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SX_SIGNATURE2 -#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 -#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SX_SIGNATURE3 -#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 -#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_DB_SIGNATURE0 -#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_PA_SIGNATURE0 -#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_VGT_SIGNATURE0 -#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SQ_SIGNATURE0 -#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE0 -#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE1 -#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE2 -#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE3 -#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE4 -#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE5 -#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE6 -#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE7 -#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_IA_SIGNATURE0 -#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_IA_SIGNATURE1 -#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 -#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SPI_SIGNATURE0 -#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SPI_SIGNATURE1 -#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 -#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_TA_SIGNATURE0 -#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_TD_SIGNATURE0 -#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_CB_SIGNATURE0 -#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_BCI_SIGNATURE0 -#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_BCI_SIGNATURE1 -#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 -#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_TA_SIGNATURE1 -#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0 -#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL - - -// addressBlock: gc_gfxdec0 -//DB_RENDER_CONTROL -#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 -#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 -#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 -#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 -#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 -#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 -#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 -#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 -#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 -#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc -#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L -#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L -#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L -#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L -#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L -#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L -#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L -#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L -#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L -#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L -//DB_COUNT_CONTROL -#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 -#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 -#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 -#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 -#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc -#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 -#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 -#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 -#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c -#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L -#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L -#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L -#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L -#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L -#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L -#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L -#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L -#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L -//DB_DEPTH_VIEW -#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 -#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd -#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 -#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 -#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a -#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL -#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L -#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L -#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L -//DB_RENDER_OVERRIDE -#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 -#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 -#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 -#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 -#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 -#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa -#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc -#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd -#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf -#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 -#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 -#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 -#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 -#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 -#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a -#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c -#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e -#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f -#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L -#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L -#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L -#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L -#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L -#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L -#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L -#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L -#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L -#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L -#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L -#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L -#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L -#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L -#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L -#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L -#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L -#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L -//DB_RENDER_OVERRIDE2 -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 -#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 -#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 -#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 -#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 -#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 -#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa -#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb -#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 -#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 -#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 -#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 -#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL -#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L -#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L -#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L -#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L -#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L -#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L -#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L -#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L -#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L -#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L -#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L -#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L -//DB_HTILE_DATA_BASE -#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 -#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL -//DB_HTILE_DATA_BASE_HI -#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0 -#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL -//DB_DEPTH_SIZE -#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0 -#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10 -#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL -#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L -//DB_DEPTH_BOUNDS_MIN -#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 -#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL -//DB_DEPTH_BOUNDS_MAX -#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 -#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL -//DB_STENCIL_CLEAR -#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 -#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL -//DB_DEPTH_CLEAR -#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 -#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL -//PA_SC_SCREEN_SCISSOR_TL -#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 -#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 -#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL -#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L -//PA_SC_SCREEN_SCISSOR_BR -#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 -#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 -#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL -#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L -//DB_Z_INFO -#define DB_Z_INFO__FORMAT__SHIFT 0x0 -#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 -#define DB_Z_INFO__SW_MODE__SHIFT 0x4 -#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc -#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd -#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf -#define DB_Z_INFO__MAXMIP__SHIFT 0x10 -#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 -#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b -#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c -#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d -#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e -#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f -#define DB_Z_INFO__FORMAT_MASK 0x00000003L -#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL -#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L -#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L -#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L -#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L -#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L -#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L -#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L -#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L -#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L -#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L -#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L -//DB_STENCIL_INFO -#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 -#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 -#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc -#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd -#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf -#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b -#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d -#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e -#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L -#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L -#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L -#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L -#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L -#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L -#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L -#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L -//DB_Z_READ_BASE -#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 -#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL -//DB_Z_READ_BASE_HI -#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 -#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL -//DB_STENCIL_READ_BASE -#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 -#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL -//DB_STENCIL_READ_BASE_HI -#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 -#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL -//DB_Z_WRITE_BASE -#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 -#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL -//DB_Z_WRITE_BASE_HI -#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 -#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL -//DB_STENCIL_WRITE_BASE -#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 -#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL -//DB_STENCIL_WRITE_BASE_HI -#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 -#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL -//DB_DFSM_CONTROL -#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0 -#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2 -#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3 -#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L -#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L -#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L -//DB_RENDER_FILTER -#define DB_RENDER_FILTER__PS_INVOKE_MASK__SHIFT 0x0 -#define DB_RENDER_FILTER__PS_INVOKE_MASK_MASK 0x0000FFFFL -//DB_Z_INFO2 -#define DB_Z_INFO2__EPITCH__SHIFT 0x0 -#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL -//DB_STENCIL_INFO2 -#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0 -#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL -//TA_BC_BASE_ADDR -#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 -#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL -//TA_BC_BASE_ADDR_HI -#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 -#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL -//COHER_DEST_BASE_HI_0 -#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 -#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL -//COHER_DEST_BASE_HI_1 -#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 -#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL -//COHER_DEST_BASE_HI_2 -#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 -#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL -//COHER_DEST_BASE_HI_3 -#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 -#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL -//COHER_DEST_BASE_2 -#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 -#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL -//COHER_DEST_BASE_3 -#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 -#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL -//PA_SC_WINDOW_OFFSET -#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 -#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 -#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL -#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L -//PA_SC_WINDOW_SCISSOR_TL -#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 -#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 -#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_WINDOW_SCISSOR_BR -#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 -#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 -#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_RULE -#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 -#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL -//PA_SC_CLIPRECT_0_TL -#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_0_BR -#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_1_TL -#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_1_BR -#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_2_TL -#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_2_BR -#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_3_TL -#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_3_BR -#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_EDGERULE -#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 -#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 -#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 -#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc -#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 -#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 -#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c -#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL -#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L -#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L -#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L -#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L -#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L -#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L -//PA_SU_HARDWARE_SCREEN_OFFSET -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L -//CB_TARGET_MASK -#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 -#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 -#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 -#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc -#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 -#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 -#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 -#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c -#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL -#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L -#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L -#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L -#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L -#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L -#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L -#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L -//CB_SHADER_MASK -#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 -#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 -#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 -#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc -#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 -#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 -#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 -#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c -#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL -#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L -#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L -#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L -#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L -#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L -#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L -#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L -//PA_SC_GENERIC_SCISSOR_TL -#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 -#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 -#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_GENERIC_SCISSOR_BR -#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 -#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 -#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L -//COHER_DEST_BASE_0 -#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 -#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL -//COHER_DEST_BASE_1 -#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 -#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL -//PA_SC_VPORT_SCISSOR_0_TL -#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_0_BR -#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_1_TL -#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_1_BR -#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_2_TL -#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_2_BR -#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_3_TL -#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_3_BR -#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_4_TL -#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_4_BR -#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_5_TL -#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_5_BR -#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_6_TL -#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_6_BR -#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_7_TL -#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_7_BR -#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_8_TL -#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_8_BR -#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_9_TL -#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_9_BR -#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_10_TL -#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_10_BR -#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_11_TL -#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_11_BR -#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_12_TL -#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_12_BR -#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_13_TL -#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_13_BR -#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_14_TL -#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_14_BR -#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_15_TL -#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_15_BR -#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_ZMIN_0 -#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_0 -#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_1 -#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_1 -#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_2 -#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_2 -#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_3 -#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_3 -#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_4 -#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_4 -#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_5 -#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_5 -#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_6 -#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_6 -#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_7 -#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_7 -#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_8 -#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_8 -#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_9 -#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_9 -#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_10 -#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_10 -#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_11 -#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_11 -#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_12 -#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_12 -#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_13 -#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_13 -#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_14 -#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_14 -#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_15 -#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_15 -#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_RASTER_CONFIG -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 -#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 -#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 -#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 -#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 -#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa -#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc -#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe -#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 -#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 -#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 -#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 -#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a -#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL -#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L -#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L -#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L -#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L -#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L -#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L -#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L -#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L -#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L -#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L -#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L -#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L -#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L -//PA_SC_RASTER_CONFIG_1 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L -//PA_SC_SCREEN_EXTENT_CONTROL -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL -//PA_SC_TILE_STEERING_OVERRIDE -#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 -#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 -#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 -#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8 -#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L -#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L -#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L -#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L -//CP_PERFMON_CNTX_CNTL -#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f -#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L -//CP_PIPEID -#define CP_PIPEID__PIPE_ID__SHIFT 0x0 -#define CP_PIPEID__PIPE_ID_MASK 0x00000003L -//CP_RINGID -#define CP_RINGID__RINGID__SHIFT 0x0 -#define CP_RINGID__RINGID_MASK 0x00000003L -//CP_VMID -#define CP_VMID__VMID__SHIFT 0x0 -#define CP_VMID__VMID_MASK 0x0000000FL -//PA_SC_RIGHT_VERT_GRID -#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0 -#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8 -#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 -#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 -#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL -#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L -#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L -#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L -//PA_SC_LEFT_VERT_GRID -#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0 -#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8 -#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 -#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 -#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL -#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L -#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L -#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L -//PA_SC_HORIZ_GRID -#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0 -#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8 -#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10 -#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18 -#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL -#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L -#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L -#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L -//PA_SC_FOV_WINDOW_LR -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT__SHIFT 0x0 -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT__SHIFT 0x8 -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT__SHIFT 0x10 -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT__SHIFT 0x18 -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT_MASK 0x000000FFL -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT_MASK 0x0000FF00L -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT_MASK 0x00FF0000L -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT_MASK 0xFF000000L -//PA_SC_FOV_WINDOW_TB -#define PA_SC_FOV_WINDOW_TB__FOV_TOP__SHIFT 0x0 -#define PA_SC_FOV_WINDOW_TB__FOV_BOT__SHIFT 0x8 -#define PA_SC_FOV_WINDOW_TB__FOV_TOP_MASK 0x000000FFL -#define PA_SC_FOV_WINDOW_TB__FOV_BOT_MASK 0x0000FF00L -//VGT_MULTI_PRIM_IB_RESET_INDX -#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 -#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL -//CB_BLEND_RED -#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 -#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL -//CB_BLEND_GREEN -#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 -#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL -//CB_BLEND_BLUE -#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 -#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL -//CB_BLEND_ALPHA -#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 -#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL -//CB_DCC_CONTROL -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1 -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL -//DB_STENCIL_CONTROL -#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 -#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 -#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 -#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc -#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 -#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 -#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL -#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L -#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L -#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L -#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L -#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L -//DB_STENCILREFMASK -#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 -#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 -#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 -#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 -#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL -#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L -#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L -#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L -//DB_STENCILREFMASK_BF -#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 -#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 -#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 -#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 -#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL -#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L -#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L -#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L -//PA_CL_VPORT_XSCALE -#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET -#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE -#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET -#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE -#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET -#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_1 -#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_1 -#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_1 -#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_1 -#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_1 -#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_1 -#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_2 -#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_2 -#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_2 -#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_2 -#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_2 -#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_2 -#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_3 -#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_3 -#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_3 -#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_3 -#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_3 -#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_3 -#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_4 -#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_4 -#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_4 -#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_4 -#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_4 -#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_4 -#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_5 -#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_5 -#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_5 -#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_5 -#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_5 -#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_5 -#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_6 -#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_6 -#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_6 -#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_6 -#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_6 -#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_6 -#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_7 -#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_7 -#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_7 -#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_7 -#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_7 -#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_7 -#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_8 -#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_8 -#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_8 -#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_8 -#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_8 -#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_8 -#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_9 -#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_9 -#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_9 -#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_9 -#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_9 -#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_9 -#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_10 -#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_10 -#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_10 -#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_10 -#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_10 -#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_10 -#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_11 -#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_11 -#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_11 -#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_11 -#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_11 -#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_11 -#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_12 -#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_12 -#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_12 -#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_12 -#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_12 -#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_12 -#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_13 -#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_13 -#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_13 -#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_13 -#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_13 -#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_13 -#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_14 -#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_14 -#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_14 -#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_14 -#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_14 -#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_14 -#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_15 -#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_15 -#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_15 -#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_15 -#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_15 -#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_15 -#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_UCP_0_X -#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_0_Y -#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_0_Z -#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_0_W -#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_1_X -#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_1_Y -#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_1_Z -#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_1_W -#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_2_X -#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_2_Y -#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_2_Z -#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_2_W -#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_3_X -#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_3_Y -#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_3_Z -#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_3_W -#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_4_X -#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_4_Y -#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_4_Z -#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_4_W -#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_5_X -#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_5_Y -#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_5_Z -#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_5_W -#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL -//SPI_PS_INPUT_CNTL_0 -#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_1 -#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_2 -#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_3 -#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_4 -#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_5 -#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_6 -#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_7 -#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_8 -#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_9 -#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_10 -#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_11 -#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_12 -#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_13 -#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_14 -#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_15 -#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_16 -#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_17 -#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_18 -#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_19 -#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_20 -#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_21 -#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_22 -#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_23 -#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_24 -#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_25 -#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_26 -#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_27 -#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_28 -#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_29 -#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_30 -#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_31 -#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L -//SPI_VS_OUT_CONFIG -#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 -#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 -#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL -#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L -//SPI_PS_INPUT_ENA -#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 -#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 -#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 -#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 -#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 -#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 -#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 -#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 -#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 -#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 -#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa -#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb -#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc -#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd -#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe -#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf -#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L -#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L -#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L -#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L -#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L -#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L -#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L -#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L -#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L -#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L -#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L -#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L -#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L -#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L -#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L -#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L -//SPI_PS_INPUT_ADDR -#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 -#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 -#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 -#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 -#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 -#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 -#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 -#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 -#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 -#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 -#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa -#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb -#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc -#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd -#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe -#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf -#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L -#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L -#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L -#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L -#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L -#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L -#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L -#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L -#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L -#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L -#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L -#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L -#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L -#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L -#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L -#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L -//SPI_INTERP_CONTROL_0 -#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe -#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L -//SPI_PS_IN_CONTROL -#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 -#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 -#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7 -#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8 -#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe -#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL -#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L -#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L -#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L -#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L -//SPI_BARYC_CNTL -#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 -#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 -#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 -#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc -#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 -#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 -#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 -#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L -#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L -#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L -#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L -#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L -#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L -#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L -//SPI_TMPRING_SIZE -#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 -#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc -#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL -#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L -//SPI_SHADER_POS_FORMAT -#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 -#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 -#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 -#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc -#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL -#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L -#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L -#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L -//SPI_SHADER_Z_FORMAT -#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 -#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL -//SPI_SHADER_COL_FORMAT -#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 -#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 -#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 -#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc -#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 -#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 -#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 -#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c -#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL -#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L -#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L -#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L -#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L -#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L -#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L -#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L -//SX_PS_DOWNCONVERT -#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 -#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 -#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 -#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc -#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 -#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 -#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 -#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c -#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL -#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L -#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L -#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L -#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L -#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L -#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L -#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L -//SX_BLEND_OPT_EPSILON -#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 -#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 -#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 -#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc -#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 -#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 -#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 -#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c -#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL -#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L -#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L -#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L -#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L -#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L -#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L -#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L -//SX_BLEND_OPT_CONTROL -#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 -#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 -#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 -#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 -#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 -#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 -#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc -#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd -#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 -#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 -#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 -#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 -#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 -#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 -#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c -#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d -#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f -#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L -#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L -#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L -#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L -#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L -#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L -#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L -#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L -#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L -#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L -#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L -#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L -#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L -#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L -#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L -#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L -#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L -//SX_MRT0_BLEND_OPT -#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT1_BLEND_OPT -#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT2_BLEND_OPT -#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT3_BLEND_OPT -#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT4_BLEND_OPT -#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT5_BLEND_OPT -#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT6_BLEND_OPT -#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT7_BLEND_OPT -#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//CB_BLEND0_CONTROL -#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND1_CONTROL -#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND2_CONTROL -#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND3_CONTROL -#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND4_CONTROL -#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND5_CONTROL -#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND6_CONTROL -#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND7_CONTROL -#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_MRT0_EPITCH -#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT1_EPITCH -#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT2_EPITCH -#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT3_EPITCH -#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT4_EPITCH -#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT5_EPITCH -#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT6_EPITCH -#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT7_EPITCH -#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL -//CS_COPY_STATE -#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 -#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L -//GFX_COPY_STATE -#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 -#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L -//PA_CL_POINT_X_RAD -#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_POINT_Y_RAD -#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_POINT_SIZE -#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_POINT_CULL_RAD -#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL -//VGT_DMA_BASE_HI -#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 -#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL -//VGT_DMA_BASE -#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 -#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL -//VGT_DRAW_INITIATOR -#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 -#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 -#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 -#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 -#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 -#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7 -#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8 -#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d -#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L -#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL -#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L -#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L -#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L -#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L -#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L -#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L -//VGT_IMMED_DATA -#define VGT_IMMED_DATA__DATA__SHIFT 0x0 -#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL -//VGT_EVENT_ADDRESS_REG -#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 -#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL -//DB_DEPTH_CONTROL -#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 -#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 -#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 -#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 -#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 -#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 -#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 -#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 -#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e -#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f -#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L -#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L -#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L -#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L -#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L -#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L -#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L -#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L -#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L -#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L -//DB_EQAA -#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 -#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 -#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 -#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc -#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 -#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 -#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 -#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 -#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 -#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 -#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 -#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b -#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L -#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L -#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L -#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L -#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L -#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L -#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L -#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L -#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L -#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L -#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L -#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L -//CB_COLOR_CONTROL -#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 -#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 -#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 -#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 -#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L -#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L -#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L -#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L -//DB_SHADER_CONTROL -#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 -#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 -#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 -#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 -#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 -#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 -#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 -#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 -#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa -#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb -#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc -#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd -#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf -#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 -#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11 -#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14 -#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L -#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L -#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L -#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L -#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L -#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L -#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L -#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L -#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L -#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L -#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L -#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L -#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L -#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L -#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L -#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L -//PA_CL_CLIP_CNTL -#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 -#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 -#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 -#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 -#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 -#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 -#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd -#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe -#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 -#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 -#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 -#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 -#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 -#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 -#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 -#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 -#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 -#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a -#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b -#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L -#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L -#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L -#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L -#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L -#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L -#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L -#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L -#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L -#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L -#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L -#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L -#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L -#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L -#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L -#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L -#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L -#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L -#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L -//PA_SU_SC_MODE_CNTL -#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 -#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 -#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 -#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 -#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 -#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd -#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 -#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 -#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 -#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 -#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 -#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 -#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L -#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L -#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L -#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L -#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L -#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L -#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L -#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L -#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L -#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L -#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L -#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L -//PA_CL_VTE_CNTL -#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 -#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 -#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 -#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 -#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 -#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 -#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 -#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 -#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa -#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb -#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L -#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L -#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L -#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L -#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L -#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L -#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L -#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L -#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L -#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L -//PA_CL_VS_OUT_CNTL -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf -#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 -#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 -#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 -#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 -#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 -#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 -#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a -#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L -//PA_CL_NANINF_CNTL -#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 -#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 -#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 -#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 -#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 -#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 -#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 -#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 -#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 -#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 -#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa -#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb -#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc -#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd -#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe -#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 -#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L -#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L -#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L -#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L -#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L -#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L -#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L -#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L -#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L -#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L -#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L -#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L -#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L -#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L -#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L -#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L -//PA_SU_LINE_STIPPLE_CNTL -#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 -#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 -#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 -#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 -#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L -#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L -#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L -#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L -//PA_SU_LINE_STIPPLE_SCALE -#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 -#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL -//PA_SU_PRIM_FILTER_CNTL -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 -#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 -#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 -#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 -#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 -#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 -#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e -#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L -#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L -#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L -#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L -#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L -#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L -#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L -#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L -//PA_SU_SMALL_PRIM_FILTER_CNTL -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L -//PA_CL_OBJPRIM_ID_CNTL -#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0 -#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1 -#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2 -#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L -#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L -#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L -//PA_CL_NGG_CNTL -#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 -#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 -#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L -#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L -//PA_SU_OVER_RASTERIZATION_CNTL -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 -#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L -#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L -//PA_SU_POINT_SIZE -#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 -#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 -#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL -#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L -//PA_SU_POINT_MINMAX -#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 -#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 -#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL -#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L -//PA_SU_LINE_CNTL -#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 -#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL -//PA_SC_LINE_STIPPLE -#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 -#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 -#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c -#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d -#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL -#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L -#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L -#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L -//VGT_OUTPUT_PATH_CNTL -#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 -#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L -//VGT_HOS_CNTL -#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 -#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L -//VGT_HOS_MAX_TESS_LEVEL -#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 -#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL -//VGT_HOS_MIN_TESS_LEVEL -#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 -#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL -//VGT_HOS_REUSE_DEPTH -#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 -#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL -//VGT_GROUP_PRIM_TYPE -#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 -#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe -#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf -#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 -#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL -#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L -#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L -#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L -//VGT_GROUP_FIRST_DECR -#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 -#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL -//VGT_GROUP_DECR -#define VGT_GROUP_DECR__DECR__SHIFT 0x0 -#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL -//VGT_GROUP_VECT_0_CNTL -#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 -#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 -#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 -#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 -#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 -#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 -#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L -#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L -#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L -#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L -#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L -#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L -//VGT_GROUP_VECT_1_CNTL -#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 -#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 -#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 -#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 -#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 -#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 -#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L -#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L -#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L -#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L -#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L -#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L -//VGT_GROUP_VECT_0_FMT_CNTL -#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 -#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 -#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 -#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c -#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL -#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L -#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L -#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L -//VGT_GROUP_VECT_1_FMT_CNTL -#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 -#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 -#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 -#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c -#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL -#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L -#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L -#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L -//VGT_GS_MODE -#define VGT_GS_MODE__MODE__SHIFT 0x0 -#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 -#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 -#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 -#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb -#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc -#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd -#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe -#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf -#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10 -#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 -#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 -#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 -#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 -#define VGT_GS_MODE__ONCHIP__SHIFT 0x15 -#define VGT_GS_MODE__MODE_MASK 0x00000007L -#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L -#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L -#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L -#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L -#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L -#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L -#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L -#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L -#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L -#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L -#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L -#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L -#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L -#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L -//VGT_GS_ONCHIP_CNTL -#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 -#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb -#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16 -#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL -#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L -#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L -//PA_SC_MODE_CNTL_0 -#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 -#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 -#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 -#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 -#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4 -#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 -#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 -#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L -#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L -#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L -#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L -#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L -#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L -#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L -//PA_SC_MODE_CNTL_1 -#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 -#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 -#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 -#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 -#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 -#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 -#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 -#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 -#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa -#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb -#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc -#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf -#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 -#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 -#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 -#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 -#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 -#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c -#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L -#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L -#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L -#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L -#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L -#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L -#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L -#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L -#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L -#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L -#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L -#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L -#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L -#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L -#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L -#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L -#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L -#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L -//VGT_ENHANCE -#define VGT_ENHANCE__MISC__SHIFT 0x0 -#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL -//VGT_GS_PER_ES -#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 -#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL -//VGT_ES_PER_GS -#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 -#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL -//VGT_GS_PER_VS -#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 -#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL -//VGT_GSVS_RING_OFFSET_1 -#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 -#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL -//VGT_GSVS_RING_OFFSET_2 -#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 -#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL -//VGT_GSVS_RING_OFFSET_3 -#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 -#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL -//VGT_GS_OUT_PRIM_TYPE -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 -#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L -#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L -//IA_ENHANCE -#define IA_ENHANCE__MISC__SHIFT 0x0 -#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL -//VGT_DMA_SIZE -#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 -#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL -//VGT_DMA_MAX_SIZE -#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 -#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL -//VGT_DMA_INDEX_TYPE -#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 -#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 -#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 -#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 -#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 -#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 -#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa -#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L -#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL -#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L -#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L -#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L -#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L -#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L -//WD_ENHANCE -#define WD_ENHANCE__MISC__SHIFT 0x0 -#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL -//VGT_PRIMITIVEID_EN -#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 -#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 -#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 -#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L -#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L -#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L -//VGT_DMA_NUM_INSTANCES -#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 -#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL -//VGT_PRIMITIVEID_RESET -#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 -#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL -//VGT_EVENT_INITIATOR -#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 -#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa -#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b -#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL -#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L -#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L -//VGT_GS_MAX_PRIMS_PER_SUBGROUP -#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0 -#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL -//VGT_DRAW_PAYLOAD_CNTL -#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0 -#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 -#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2 -#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3 -#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L -#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L -#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L -#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L -//VGT_INDEX_PAYLOAD_CNTL -#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN__SHIFT 0x0 -#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN_MASK 0x00000001L -//VGT_INSTANCE_STEP_RATE_0 -#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 -#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL -//VGT_INSTANCE_STEP_RATE_1 -#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 -#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL -//VGT_ESGS_RING_ITEMSIZE -#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 -#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL -//VGT_GSVS_RING_ITEMSIZE -#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 -#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL -//VGT_REUSE_OFF -#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 -#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L -//VGT_VTX_CNT_EN -#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 -#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L -//DB_HTILE_SURFACE -#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 -#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 -#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 -#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 -#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa -#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 -#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 -#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13 -#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L -#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L -#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L -#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L -#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L -#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L -#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L -#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L -//DB_SRESULTS_COMPARE_STATE0 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc -#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L -#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L -#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L -#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L -//DB_SRESULTS_COMPARE_STATE1 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc -#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L -#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L -#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L -#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L -//DB_PRELOAD_CONTROL -#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 -#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 -#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 -#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 -#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL -#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L -#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L -#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L -//VGT_STRMOUT_BUFFER_SIZE_0 -#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_VTX_STRIDE_0 -#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 -#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL -//VGT_STRMOUT_BUFFER_OFFSET_0 -#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL -//VGT_STRMOUT_BUFFER_SIZE_1 -#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_VTX_STRIDE_1 -#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 -#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL -//VGT_STRMOUT_BUFFER_OFFSET_1 -#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL -//VGT_STRMOUT_BUFFER_SIZE_2 -#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_VTX_STRIDE_2 -#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 -#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL -//VGT_STRMOUT_BUFFER_OFFSET_2 -#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL -//VGT_STRMOUT_BUFFER_SIZE_3 -#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_VTX_STRIDE_3 -#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 -#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL -//VGT_STRMOUT_BUFFER_OFFSET_3 -#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL -//VGT_STRMOUT_DRAW_OPAQUE_OFFSET -#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 -#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL -//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE -#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE -#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 -#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL -//VGT_GS_MAX_VERT_OUT -#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 -#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL -//VGT_TESS_DISTRIBUTION -#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 -#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 -#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 -#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 -#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d -#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL -#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L -#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L -#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L -#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L -//VGT_SHADER_STAGES_EN -#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 -#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 -#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 -#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 -#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 -#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb -#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc -#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd -#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe -#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf -#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 -#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L -#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L -#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L -#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L -#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L -#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L -#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L -#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L -#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L -#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L -#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00080000L -//VGT_LS_HS_CONFIG -#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 -#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 -#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe -#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL -#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L -#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L -//VGT_GS_VERT_ITEMSIZE -#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 -#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL -//VGT_GS_VERT_ITEMSIZE_1 -#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 -#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL -//VGT_GS_VERT_ITEMSIZE_2 -#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 -#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL -//VGT_GS_VERT_ITEMSIZE_3 -#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 -#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL -//VGT_TF_PARAM -#define VGT_TF_PARAM__TYPE__SHIFT 0x0 -#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 -#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 -#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 -#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 -#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe -#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf -#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 -#define VGT_TF_PARAM__TYPE_MASK 0x00000003L -#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL -#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L -#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L -#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L -#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L -#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L -#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L -//DB_ALPHA_TO_MASK -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe -#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L -#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L -//VGT_DISPATCH_DRAW_INDEX -#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 -#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL -//PA_SU_POLY_OFFSET_DB_FMT_CNTL -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L -//PA_SU_POLY_OFFSET_CLAMP -#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 -#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL -//PA_SU_POLY_OFFSET_FRONT_SCALE -#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 -#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL -//PA_SU_POLY_OFFSET_FRONT_OFFSET -#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 -#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL -//PA_SU_POLY_OFFSET_BACK_SCALE -#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 -#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL -//PA_SU_POLY_OFFSET_BACK_OFFSET -#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 -#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL -//VGT_GS_INSTANCE_CNT -#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 -#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 -#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L -#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL -//VGT_STRMOUT_CONFIG -#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 -#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 -#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 -#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 -#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 -#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7 -#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 -#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f -#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L -#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L -#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L -#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L -#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L -#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L -#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L -#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L -//VGT_STRMOUT_BUFFER_CONFIG -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L -//VGT_DMA_EVENT_INITIATOR -#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 -#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa -#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b -#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL -#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L -#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L -//PA_SC_CENTROID_PRIORITY_0 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L -//PA_SC_CENTROID_PRIORITY_1 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L -//PA_SC_LINE_CNTL -#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 -#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa -#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb -#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc -#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L -#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L -#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L -#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L -//PA_SC_AA_CONFIG -#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 -#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 -#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd -#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 -#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 -#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a -#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L -#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L -#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L -#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L -#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L -#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L -//PA_SU_VTX_CNTL -#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 -#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 -#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 -#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L -#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L -#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L -//PA_CL_GB_VERT_CLIP_ADJ -#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_GB_VERT_DISC_ADJ -#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_GB_HORZ_CLIP_ADJ -#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_GB_HORZ_DISC_ADJ -#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L -//PA_SC_AA_MASK_X0Y0_X1Y0 -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L -//PA_SC_AA_MASK_X0Y1_X1Y1 -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L -//PA_SC_SHADER_CONTROL -#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 -#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 -#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 -#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L -#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L -#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L -//PA_SC_BINNER_CNTL_0 -#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 -#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa -#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd -#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 -#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 -#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b -#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L -#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L -#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L -#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L -#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L -#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L -//PA_SC_BINNER_CNTL_1 -#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 -#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 -#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL -#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L -//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L -//PA_SC_NGG_MODE_CNTL -#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 -#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL -//VGT_VERTEX_REUSE_BLOCK_CNTL -#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 -#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL -//VGT_OUT_DEALLOC_CNTL -#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 -#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL -//CB_COLOR0_BASE -#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR0_BASE_EXT -#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR0_ATTRIB2 -#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR0_VIEW -#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR0_INFO -#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR0_ATTRIB -#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR0_DCC_CONTROL -#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR0_CMASK -#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR0_CMASK_BASE_EXT -#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR0_FMASK -#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR0_FMASK_BASE_EXT -#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR0_CLEAR_WORD0 -#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR0_CLEAR_WORD1 -#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR0_DCC_BASE -#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR0_DCC_BASE_EXT -#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR1_BASE -#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR1_BASE_EXT -#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR1_ATTRIB2 -#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR1_VIEW -#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR1_INFO -#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR1_ATTRIB -#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR1_DCC_CONTROL -#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR1_CMASK -#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR1_CMASK_BASE_EXT -#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR1_FMASK -#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR1_FMASK_BASE_EXT -#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR1_CLEAR_WORD0 -#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR1_CLEAR_WORD1 -#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR1_DCC_BASE -#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR1_DCC_BASE_EXT -#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR2_BASE -#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR2_BASE_EXT -#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR2_ATTRIB2 -#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR2_VIEW -#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR2_INFO -#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR2_ATTRIB -#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR2_DCC_CONTROL -#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR2_CMASK -#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR2_CMASK_BASE_EXT -#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR2_FMASK -#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR2_FMASK_BASE_EXT -#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR2_CLEAR_WORD0 -#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR2_CLEAR_WORD1 -#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR2_DCC_BASE -#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR2_DCC_BASE_EXT -#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR3_BASE -#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR3_BASE_EXT -#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR3_ATTRIB2 -#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR3_VIEW -#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR3_INFO -#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR3_ATTRIB -#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR3_DCC_CONTROL -#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR3_CMASK -#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR3_CMASK_BASE_EXT -#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR3_FMASK -#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR3_FMASK_BASE_EXT -#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR3_CLEAR_WORD0 -#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR3_CLEAR_WORD1 -#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR3_DCC_BASE -#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR3_DCC_BASE_EXT -#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR4_BASE -#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR4_BASE_EXT -#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR4_ATTRIB2 -#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR4_VIEW -#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR4_INFO -#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR4_ATTRIB -#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR4_DCC_CONTROL -#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR4_CMASK -#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR4_CMASK_BASE_EXT -#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR4_FMASK -#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR4_FMASK_BASE_EXT -#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR4_CLEAR_WORD0 -#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR4_CLEAR_WORD1 -#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR4_DCC_BASE -#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR4_DCC_BASE_EXT -#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR5_BASE -#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR5_BASE_EXT -#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR5_ATTRIB2 -#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR5_VIEW -#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR5_INFO -#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR5_ATTRIB -#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR5_DCC_CONTROL -#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR5_CMASK -#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR5_CMASK_BASE_EXT -#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR5_FMASK -#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR5_FMASK_BASE_EXT -#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR5_CLEAR_WORD0 -#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR5_CLEAR_WORD1 -#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR5_DCC_BASE -#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR5_DCC_BASE_EXT -#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR6_BASE -#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR6_BASE_EXT -#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR6_ATTRIB2 -#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR6_VIEW -#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR6_INFO -#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR6_ATTRIB -#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR6_DCC_CONTROL -#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR6_CMASK -#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR6_CMASK_BASE_EXT -#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR6_FMASK -#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR6_FMASK_BASE_EXT -#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR6_CLEAR_WORD0 -#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR6_CLEAR_WORD1 -#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR6_DCC_BASE -#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR6_DCC_BASE_EXT -#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR7_BASE -#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR7_BASE_EXT -#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR7_ATTRIB2 -#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR7_VIEW -#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR7_INFO -#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR7_ATTRIB -#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR7_DCC_CONTROL -#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR7_CMASK -#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR7_CMASK_BASE_EXT -#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR7_FMASK -#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR7_FMASK_BASE_EXT -#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR7_CLEAR_WORD0 -#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR7_CLEAR_WORD1 -#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR7_DCC_BASE -#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR7_DCC_BASE_EXT -#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL - - -// addressBlock: gc_gfxudec -//CP_EOP_DONE_ADDR_LO -#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 -#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL -//CP_EOP_DONE_ADDR_HI -#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_EOP_DONE_DATA_LO -#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 -#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL -//CP_EOP_DONE_DATA_HI -#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 -#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL -//CP_EOP_LAST_FENCE_LO -#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 -#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL -//CP_EOP_LAST_FENCE_HI -#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 -#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL -//CP_STREAM_OUT_ADDR_LO -#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 -#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL -//CP_STREAM_OUT_ADDR_HI -#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 -#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL -//CP_NUM_PRIM_WRITTEN_COUNT0_LO -#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT0_HI -#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT0_LO -#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT0_HI -#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT1_LO -#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT1_HI -#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT1_LO -#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT1_HI -#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT2_LO -#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT2_HI -#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT2_LO -#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT2_HI -#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT3_LO -#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT3_HI -#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT3_LO -#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT3_HI -#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL -//CP_PIPE_STATS_ADDR_LO -#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 -#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL -//CP_PIPE_STATS_ADDR_HI -#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 -#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL -//CP_VGT_IAVERT_COUNT_LO -#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 -#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_IAVERT_COUNT_HI -#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 -#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL -//CP_VGT_IAPRIM_COUNT_LO -#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 -#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_IAPRIM_COUNT_HI -#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 -#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL -//CP_VGT_GSPRIM_COUNT_LO -#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 -#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_GSPRIM_COUNT_HI -#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 -#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL -//CP_VGT_VSINVOC_COUNT_LO -#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 -#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_VSINVOC_COUNT_HI -#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 -#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL -//CP_VGT_GSINVOC_COUNT_LO -#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 -#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_GSINVOC_COUNT_HI -#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 -#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL -//CP_VGT_HSINVOC_COUNT_LO -#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 -#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_HSINVOC_COUNT_HI -#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 -#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL -//CP_VGT_DSINVOC_COUNT_LO -#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 -#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_DSINVOC_COUNT_HI -#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 -#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL -//CP_PA_CINVOC_COUNT_LO -#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 -#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL -//CP_PA_CINVOC_COUNT_HI -#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 -#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL -//CP_PA_CPRIM_COUNT_LO -#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 -#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL -//CP_PA_CPRIM_COUNT_HI -#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 -#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL -//CP_SC_PSINVOC_COUNT0_LO -#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 -#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL -//CP_SC_PSINVOC_COUNT0_HI -#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 -#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL -//CP_SC_PSINVOC_COUNT1_LO -#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 -#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL -//CP_SC_PSINVOC_COUNT1_HI -#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 -#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL -//CP_VGT_CSINVOC_COUNT_LO -#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 -#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_CSINVOC_COUNT_HI -#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 -#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL -//CP_PIPE_STATS_CONTROL -#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 -#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L -//CP_STREAM_OUT_CONTROL -#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19 -#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L -//CP_STRMOUT_CNTL -#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 -#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L -//SCRATCH_REG0 -#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 -#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL -//SCRATCH_REG1 -#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 -#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL -//SCRATCH_REG2 -#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 -#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL -//SCRATCH_REG3 -#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 -#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL -//SCRATCH_REG4 -#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 -#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL -//SCRATCH_REG5 -#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 -#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL -//SCRATCH_REG6 -#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 -#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL -//SCRATCH_REG7 -#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 -#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL -//CP_APPEND_DATA_HI -#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 -#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL -//CP_APPEND_LAST_CS_FENCE_HI -#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 -#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL -//CP_APPEND_LAST_PS_FENCE_HI -#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 -#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL -//SCRATCH_UMSK -#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 -#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 -#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL -#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L -//SCRATCH_ADDR -#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 -#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL -//CP_PFP_ATOMIC_PREOP_LO -#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 -#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL -//CP_PFP_ATOMIC_PREOP_HI -#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 -#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL -//CP_PFP_GDS_ATOMIC0_PREOP_LO -#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 -#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL -//CP_PFP_GDS_ATOMIC0_PREOP_HI -#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 -#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL -//CP_PFP_GDS_ATOMIC1_PREOP_LO -#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 -#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL -//CP_PFP_GDS_ATOMIC1_PREOP_HI -#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 -#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL -//CP_APPEND_ADDR_LO -#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 -#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL -//CP_APPEND_ADDR_HI -#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 -#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 -#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 -#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d -#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL -#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L -#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L -#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L -//CP_APPEND_DATA_LO -#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 -#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL -//CP_APPEND_LAST_CS_FENCE_LO -#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 -#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL -//CP_APPEND_LAST_PS_FENCE_LO -#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 -#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL -//CP_ATOMIC_PREOP_LO -#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 -#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL -//CP_ME_ATOMIC_PREOP_LO -#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 -#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL -//CP_ATOMIC_PREOP_HI -#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 -#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL -//CP_ME_ATOMIC_PREOP_HI -#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 -#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL -//CP_GDS_ATOMIC0_PREOP_LO -#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 -#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL -//CP_ME_GDS_ATOMIC0_PREOP_LO -#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 -#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL -//CP_GDS_ATOMIC0_PREOP_HI -#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 -#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL -//CP_ME_GDS_ATOMIC0_PREOP_HI -#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 -#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL -//CP_GDS_ATOMIC1_PREOP_LO -#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 -#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL -//CP_ME_GDS_ATOMIC1_PREOP_LO -#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 -#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL -//CP_GDS_ATOMIC1_PREOP_HI -#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 -#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL -//CP_ME_GDS_ATOMIC1_PREOP_HI -#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 -#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL -//CP_ME_MC_WADDR_LO -#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 -#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL -//CP_ME_MC_WADDR_HI -#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 -#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 -#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL -#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L -//CP_ME_MC_WDATA_LO -#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 -#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL -//CP_ME_MC_WDATA_HI -#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 -#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL -//CP_ME_MC_RADDR_LO -#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 -#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL -//CP_ME_MC_RADDR_HI -#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 -#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 -#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL -#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L -//CP_SEM_WAIT_TIMER -#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 -#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL -//CP_SIG_SEM_ADDR_LO -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L -//CP_SIG_SEM_ADDR_HI -#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 -#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 -#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 -#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 -#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d -#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL -#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L -#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L -#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L -#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L -//CP_WAIT_REG_MEM_TIMEOUT -#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 -#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL -//CP_WAIT_SEM_ADDR_LO -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L -//CP_WAIT_SEM_ADDR_HI -#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 -#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 -#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 -#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 -#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d -#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL -#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L -#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L -#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L -#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L -//CP_DMA_PFP_CONTROL -#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa -#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd -#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 -#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 -#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d -#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L -#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L -#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L -#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L -#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L -//CP_DMA_ME_CONTROL -#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa -#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd -#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 -#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 -#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d -#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L -#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L -#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L -#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L -#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L -//CP_COHER_BASE_HI -#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 -#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL -//CP_COHER_START_DELAY -#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 -#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL -//CP_COHER_CNTL -#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 -#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4 -#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5 -#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf -#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 -#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 -#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 -#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 -#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a -#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b -#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c -#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d -#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e -#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L -#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L -#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L -#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L -#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L -#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L -#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L -#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L -#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L -#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L -#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L -#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L -#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L -//CP_COHER_SIZE -#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 -#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL -//CP_COHER_BASE -#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 -#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL -//CP_COHER_STATUS -#define CP_COHER_STATUS__MEID__SHIFT 0x18 -#define CP_COHER_STATUS__STATUS__SHIFT 0x1f -#define CP_COHER_STATUS__MEID_MASK 0x03000000L -#define CP_COHER_STATUS__STATUS_MASK 0x80000000L -//CP_DMA_ME_SRC_ADDR -#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 -#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL -//CP_DMA_ME_SRC_ADDR_HI -#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 -#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL -//CP_DMA_ME_DST_ADDR -#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 -#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL -//CP_DMA_ME_DST_ADDR_HI -#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 -#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL -//CP_DMA_ME_COMMAND -#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 -#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a -#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b -#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c -#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d -#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e -#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f -#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL -#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L -#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L -#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L -#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L -#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L -#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L -//CP_DMA_PFP_SRC_ADDR -#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 -#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL -//CP_DMA_PFP_SRC_ADDR_HI -#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 -#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL -//CP_DMA_PFP_DST_ADDR -#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 -#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL -//CP_DMA_PFP_DST_ADDR_HI -#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 -#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL -//CP_DMA_PFP_COMMAND -#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 -#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a -#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b -#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c -#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d -#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e -#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f -#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL -#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L -#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L -#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L -#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L -#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L -#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L -//CP_DMA_CNTL -#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 -#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 -#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 -#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c -#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d -#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e -#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L -#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L -#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L -#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L -#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L -#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L -//CP_DMA_READ_TAGS -#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 -#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c -#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL -#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L -//CP_COHER_SIZE_HI -#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 -#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL -//CP_PFP_IB_CONTROL -#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 -#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL -//CP_PFP_LOAD_CONTROL -#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 -#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 -#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 -#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 -#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L -#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L -#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L -#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L -//CP_SCRATCH_INDEX -#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 -#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL -//CP_SCRATCH_DATA -#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 -#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL -//CP_RB_OFFSET -#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 -#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL -//CP_IB1_OFFSET -#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 -#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL -//CP_IB2_OFFSET -#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 -#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL -//CP_IB1_PREAMBLE_BEGIN -#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 -#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL -//CP_IB1_PREAMBLE_END -#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 -#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL -//CP_IB2_PREAMBLE_BEGIN -#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 -#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL -//CP_IB2_PREAMBLE_END -#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 -#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL -//CP_CE_IB1_OFFSET -#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 -#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL -//CP_CE_IB2_OFFSET -#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 -#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL -//CP_CE_COUNTER -#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 -#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL -//CP_CE_RB_OFFSET -#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0 -#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL -//CP_CE_INIT_CMD_BUFSZ -#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0 -#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL -//CP_CE_IB1_CMD_BUFSZ -#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 -#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL -//CP_CE_IB2_CMD_BUFSZ -#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 -#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL -//CP_IB1_CMD_BUFSZ -#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 -#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL -//CP_IB2_CMD_BUFSZ -#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 -#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL -//CP_ST_CMD_BUFSZ -#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 -#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL -//CP_CE_INIT_BASE_LO -#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 -#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L -//CP_CE_INIT_BASE_HI -#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 -#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL -//CP_CE_INIT_BUFSZ -#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 -#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL -//CP_CE_IB1_BASE_LO -#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 -#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL -//CP_CE_IB1_BASE_HI -#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 -#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL -//CP_CE_IB1_BUFSZ -#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 -#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL -//CP_CE_IB2_BASE_LO -#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 -#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL -//CP_CE_IB2_BASE_HI -#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 -#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL -//CP_CE_IB2_BUFSZ -#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 -#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL -//CP_IB1_BASE_LO -#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 -#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL -//CP_IB1_BASE_HI -#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 -#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL -//CP_IB1_BUFSZ -#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 -#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL -//CP_IB2_BASE_LO -#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 -#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL -//CP_IB2_BASE_HI -#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 -#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL -//CP_IB2_BUFSZ -#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 -#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL -//CP_ST_BASE_LO -#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 -#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL -//CP_ST_BASE_HI -#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 -#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL -//CP_ST_BUFSZ -#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 -#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL -//CP_EOP_DONE_EVENT_CNTL -#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 -#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc -#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 -#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c -#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL -#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L -#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L -#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L -//CP_EOP_DONE_DATA_CNTL -#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 -#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 -#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d -#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L -#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L -#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L -//CP_EOP_DONE_CNTX_ID -#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 -#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL -//CP_PFP_COMPLETION_STATUS -#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 -#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L -//CP_CE_COMPLETION_STATUS -#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 -#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L -//CP_PRED_NOT_VISIBLE -#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 -#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L -//CP_PFP_METADATA_BASE_ADDR -#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 -#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL -//CP_PFP_METADATA_BASE_ADDR_HI -#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_CE_METADATA_BASE_ADDR -#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 -#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL -//CP_CE_METADATA_BASE_ADDR_HI -#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_DRAW_INDX_INDR_ADDR -#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 -#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL -//CP_DRAW_INDX_INDR_ADDR_HI -#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_DISPATCH_INDR_ADDR -#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 -#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL -//CP_DISPATCH_INDR_ADDR_HI -#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_INDEX_BASE_ADDR -#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 -#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL -//CP_INDEX_BASE_ADDR_HI -#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_INDEX_TYPE -#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 -#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L -//CP_GDS_BKUP_ADDR -#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 -#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL -//CP_GDS_BKUP_ADDR_HI -#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_SAMPLE_STATUS -#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 -#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 -#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 -#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 -#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 -#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 -#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 -#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 -#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L -#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L -#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L -#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L -#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L -#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L -#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L -#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L -//CP_ME_COHER_CNTL -#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 -#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 -#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 -#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 -#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 -#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 -#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa -#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb -#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc -#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd -#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe -#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 -#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 -#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L -#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L -#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L -#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L -#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L -#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L -#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L -#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L -#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L -#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L -#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L -#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L -#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L -//CP_ME_COHER_SIZE -#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 -#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL -//CP_ME_COHER_SIZE_HI -#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 -#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL -//CP_ME_COHER_BASE -#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 -#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL -//CP_ME_COHER_BASE_HI -#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 -#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL -//CP_ME_COHER_STATUS -#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 -#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f -#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL -#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L -//RLC_GPM_PERF_COUNT_0 -#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 -#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 -#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 -#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc -#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 -#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 -#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 -#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 -#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL -#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L -#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L -#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L -#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L -#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L -#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L -#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L -//RLC_GPM_PERF_COUNT_1 -#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 -#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 -#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 -#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc -#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 -#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 -#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 -#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 -#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL -#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L -#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L -#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L -#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L -#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L -#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L -#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L -//GRBM_GFX_INDEX -#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 -#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 -#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 -#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d -#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e -#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f -#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL -#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L -#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L -#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L -#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L -#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L -//VGT_GSVS_RING_SIZE -#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 -#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL -//VGT_PRIMITIVE_TYPE -#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 -#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL -//VGT_INDEX_TYPE -#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 -#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 -#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L -#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L -//VGT_STRMOUT_BUFFER_FILLED_SIZE_0 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_BUFFER_FILLED_SIZE_1 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_BUFFER_FILLED_SIZE_2 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_BUFFER_FILLED_SIZE_3 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL -//VGT_MAX_VTX_INDX -#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 -#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL -//VGT_MIN_VTX_INDX -#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 -#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL -//VGT_INDX_OFFSET -#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 -#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL -//VGT_MULTI_PRIM_IB_RESET_EN -#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 -#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 -#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L -#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L -//VGT_NUM_INDICES -#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 -#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL -//VGT_NUM_INSTANCES -#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 -#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL -//VGT_TF_RING_SIZE -#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 -#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL -//VGT_HS_OFFCHIP_PARAM -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L -//VGT_TF_MEMORY_BASE -#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 -#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL -//VGT_TF_MEMORY_BASE_HI -#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 -#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL -//WD_POS_BUF_BASE -#define WD_POS_BUF_BASE__BASE__SHIFT 0x0 -#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL -//WD_POS_BUF_BASE_HI -#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0 -#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL -//WD_CNTL_SB_BUF_BASE -#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0 -#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL -//WD_CNTL_SB_BUF_BASE_HI -#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0 -#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL -//WD_INDEX_BUF_BASE -#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0 -#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL -//WD_INDEX_BUF_BASE_HI -#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0 -#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL -//IA_MULTI_VGT_PARAM -#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 -#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 -#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 -#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 -#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15 -#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16 -#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17 -#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL -#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L -#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L -#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L -#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L -#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L -#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L -//VGT_OBJECT_ID -#define VGT_OBJECT_ID__REG_OBJ_ID__SHIFT 0x0 -#define VGT_OBJECT_ID__REG_OBJ_ID_MASK 0xFFFFFFFFL -//VGT_INSTANCE_BASE_ID -#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 -#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL -//PA_SU_LINE_STIPPLE_VALUE -#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 -#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL -//PA_SC_LINE_STIPPLE_STATE -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L -//PA_SC_SCREEN_EXTENT_MIN_0 -#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 -#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 -#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL -#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L -//PA_SC_SCREEN_EXTENT_MAX_0 -#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 -#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 -#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL -#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L -//PA_SC_SCREEN_EXTENT_MIN_1 -#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 -#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 -#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL -#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L -//PA_SC_SCREEN_EXTENT_MAX_1 -#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 -#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 -#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL -#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L -//PA_SC_P3D_TRAP_SCREEN_HV_EN -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L -//PA_SC_P3D_TRAP_SCREEN_H -#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 -#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL -//PA_SC_P3D_TRAP_SCREEN_V -#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 -#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL -//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE -#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 -#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL -//PA_SC_P3D_TRAP_SCREEN_COUNT -#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 -#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL -//PA_SC_HP3D_TRAP_SCREEN_HV_EN -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L -//PA_SC_HP3D_TRAP_SCREEN_H -#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 -#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL -//PA_SC_HP3D_TRAP_SCREEN_V -#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 -#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL -//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE -#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 -#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL -//PA_SC_HP3D_TRAP_SCREEN_COUNT -#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 -#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL -//PA_SC_TRAP_SCREEN_HV_EN -#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 -#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 -#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L -#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L -//PA_SC_TRAP_SCREEN_H -#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 -#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL -//PA_SC_TRAP_SCREEN_V -#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 -#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL -//PA_SC_TRAP_SCREEN_OCCURRENCE -#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 -#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL -//PA_SC_TRAP_SCREEN_COUNT -#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 -#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL -//SQ_THREAD_TRACE_BASE -#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 -#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_SIZE -#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 -#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL -//SQ_THREAD_TRACE_MASK -#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 -#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 -#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 -#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 -#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc -#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe -#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf -#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL -#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L -#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L -#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L -#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L -#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L -#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L -//SQ_THREAD_TRACE_TOKEN_MASK -#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 -#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L -//SQ_THREAD_TRACE_PERF_MASK -#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 -#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 -#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL -#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_CTRL -#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f -#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L -//SQ_THREAD_TRACE_MODE -#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 -#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 -#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 -#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 -#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc -#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf -#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 -#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 -#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 -#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 -#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a -#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b -#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d -#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e -#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f -#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L -#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L -#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L -#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L -#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L -#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L -#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L -#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L -#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L -#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L -#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L -#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L -#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L -#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L -#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L -//SQ_THREAD_TRACE_BASE2 -#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 -#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL -//SQ_THREAD_TRACE_TOKEN_MASK2 -#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 -#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_WPTR -#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 -#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e -#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL -#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L -//SQ_THREAD_TRACE_STATUS -#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 -#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 -#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c -#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d -#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e -#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f -#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL -#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L -#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L -#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L -#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L -#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L -//SQ_THREAD_TRACE_HIWATER -#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 -#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L -//SQ_THREAD_TRACE_CNTR -#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 -#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_USERDATA_0 -#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 -#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_USERDATA_1 -#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 -#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_USERDATA_2 -#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 -#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_USERDATA_3 -#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 -#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL -//SQC_CACHES -#define SQC_CACHES__TARGET_INST__SHIFT 0x0 -#define SQC_CACHES__TARGET_DATA__SHIFT 0x1 -#define SQC_CACHES__INVALIDATE__SHIFT 0x2 -#define SQC_CACHES__WRITEBACK__SHIFT 0x3 -#define SQC_CACHES__VOL__SHIFT 0x4 -#define SQC_CACHES__COMPLETE__SHIFT 0x10 -#define SQC_CACHES__TARGET_INST_MASK 0x00000001L -#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L -#define SQC_CACHES__INVALIDATE_MASK 0x00000004L -#define SQC_CACHES__WRITEBACK_MASK 0x00000008L -#define SQC_CACHES__VOL_MASK 0x00000010L -#define SQC_CACHES__COMPLETE_MASK 0x00010000L -//SQC_WRITEBACK -#define SQC_WRITEBACK__DWB__SHIFT 0x0 -#define SQC_WRITEBACK__DIRTY__SHIFT 0x1 -#define SQC_WRITEBACK__DWB_MASK 0x00000001L -#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L -//TA_CS_BC_BASE_ADDR -#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 -#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL -//TA_CS_BC_BASE_ADDR_HI -#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 -#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL -//TA_GRAD_ADJ_UCONFIG -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0__SHIFT 0x0 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1__SHIFT 0x8 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2__SHIFT 0x10 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3__SHIFT 0x18 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0_MASK 0x000000FFL -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1_MASK 0x0000FF00L -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2_MASK 0x00FF0000L -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3_MASK 0xFF000000L -//DB_OCCLUSION_COUNT0_LOW -#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 -#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL -//DB_OCCLUSION_COUNT0_HI -#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 -#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL -//DB_OCCLUSION_COUNT1_LOW -#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 -#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL -//DB_OCCLUSION_COUNT1_HI -#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 -#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL -//DB_OCCLUSION_COUNT2_LOW -#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 -#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL -//DB_OCCLUSION_COUNT2_HI -#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 -#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL -//DB_OCCLUSION_COUNT3_LOW -#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 -#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL -//DB_OCCLUSION_COUNT3_HI -#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 -#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL -//DB_ZPASS_COUNT_LOW -#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 -#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL -//DB_ZPASS_COUNT_HI -#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 -#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL -//GDS_RD_ADDR -#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 -#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL -//GDS_RD_DATA -#define GDS_RD_DATA__READ_DATA__SHIFT 0x0 -#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL -//GDS_RD_BURST_ADDR -#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 -#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL -//GDS_RD_BURST_COUNT -#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 -#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL -//GDS_RD_BURST_DATA -#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 -#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL -//GDS_WR_ADDR -#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 -#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL -//GDS_WR_DATA -#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 -#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL -//GDS_WR_BURST_ADDR -#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 -#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL -//GDS_WR_BURST_DATA -#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 -#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL -//GDS_WRITE_COMPLETE -#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 -#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL -//GDS_ATOM_CNTL -#define GDS_ATOM_CNTL__AINC__SHIFT 0x0 -#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 -#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 -#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa -#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL -#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L -#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L -#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L -//GDS_ATOM_COMPLETE -#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 -#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 -#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L -#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL -//GDS_ATOM_BASE -#define GDS_ATOM_BASE__BASE__SHIFT 0x0 -#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 -#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL -#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L -//GDS_ATOM_SIZE -#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 -#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 -#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL -#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L -//GDS_ATOM_OFFSET0 -#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 -#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 -#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL -#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L -//GDS_ATOM_OFFSET1 -#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 -#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 -#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL -#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L -//GDS_ATOM_DST -#define GDS_ATOM_DST__DST__SHIFT 0x0 -#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL -//GDS_ATOM_OP -#define GDS_ATOM_OP__OP__SHIFT 0x0 -#define GDS_ATOM_OP__UNUSED__SHIFT 0x8 -#define GDS_ATOM_OP__OP_MASK 0x000000FFL -#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L -//GDS_ATOM_SRC0 -#define GDS_ATOM_SRC0__DATA__SHIFT 0x0 -#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_SRC0_U -#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 -#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_SRC1 -#define GDS_ATOM_SRC1__DATA__SHIFT 0x0 -#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_SRC1_U -#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 -#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_READ0 -#define GDS_ATOM_READ0__DATA__SHIFT 0x0 -#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_READ0_U -#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 -#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_READ1 -#define GDS_ATOM_READ1__DATA__SHIFT 0x0 -#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_READ1_U -#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 -#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL -//GDS_GWS_RESOURCE_CNTL -#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 -#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 -#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL -#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L -//GDS_GWS_RESOURCE -#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 -#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 -#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd -#define GDS_GWS_RESOURCE__DED__SHIFT 0xe -#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf -#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 -#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c -#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d -#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1e -#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1f -#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L -#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL -#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L -#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L -#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L -#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x0FFF0000L -#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000L -#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000L -#define GDS_GWS_RESOURCE__HALTED_MASK 0x40000000L -#define GDS_GWS_RESOURCE__UNUSED1_MASK 0x80000000L -//GDS_GWS_RESOURCE_CNT -#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 -#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 -#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL -#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L -//GDS_OA_CNTL -#define GDS_OA_CNTL__INDEX__SHIFT 0x0 -#define GDS_OA_CNTL__UNUSED__SHIFT 0x4 -#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL -#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L -//GDS_OA_COUNTER -#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 -#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL -//GDS_OA_ADDRESS -#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 -#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10 -#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14 -#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16 -#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e -#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f -#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL -#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L -#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L -#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L -#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L -#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L -//GDS_OA_INCDEC -#define GDS_OA_INCDEC__VALUE__SHIFT 0x0 -#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f -#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL -#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L -//GDS_OA_RING_SIZE -#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 -#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL -//SPI_CONFIG_CNTL -#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 -#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 -#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 -#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 -#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a -#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b -#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c -#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d -#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e -#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL -#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L -#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L -#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L -#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L -#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L -#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L -#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L -#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L -//SPI_CONFIG_CNTL_1 -#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 -#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 -#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5 -#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 -#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 -#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa -#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe -#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf -#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 -#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL -#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L -#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L -#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L -#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L -#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L -#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L -#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L -#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L -//SPI_CONFIG_CNTL_2 -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L - - -// addressBlock: gc_perfddec -//CPG_PERFCOUNTER1_LO -#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CPG_PERFCOUNTER1_HI -#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CPG_PERFCOUNTER0_LO -#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CPG_PERFCOUNTER0_HI -#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CPC_PERFCOUNTER1_LO -#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CPC_PERFCOUNTER1_HI -#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CPC_PERFCOUNTER0_LO -#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CPC_PERFCOUNTER0_HI -#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CPF_PERFCOUNTER1_LO -#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CPF_PERFCOUNTER1_HI -#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CPF_PERFCOUNTER0_LO -#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CPF_PERFCOUNTER0_HI -#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CPF_LATENCY_STATS_DATA -#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 -#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL -//CPG_LATENCY_STATS_DATA -#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 -#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL -//CPC_LATENCY_STATS_DATA -#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 -#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL -//GRBM_PERFCOUNTER0_LO -#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GRBM_PERFCOUNTER0_HI -#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GRBM_PERFCOUNTER1_LO -#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GRBM_PERFCOUNTER1_HI -#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GRBM_SE0_PERFCOUNTER_LO -#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GRBM_SE0_PERFCOUNTER_HI -#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GRBM_SE1_PERFCOUNTER_LO -#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GRBM_SE1_PERFCOUNTER_HI -#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GRBM_SE2_PERFCOUNTER_LO -#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GRBM_SE2_PERFCOUNTER_HI -#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GRBM_SE3_PERFCOUNTER_LO -#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GRBM_SE3_PERFCOUNTER_HI -#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER0_LO -#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER0_HI -#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER1_LO -#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER1_HI -#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER2_LO -#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER2_HI -#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER3_LO -#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER3_HI -#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER0_LO -#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER0_HI -#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER1_LO -#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER1_HI -#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER2_LO -#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER2_HI -#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER3_LO -#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER3_HI -#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER0_LO -#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER0_HI -#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER1_LO -#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER1_HI -#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER2_LO -#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER2_HI -#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER3_LO -#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER3_HI -#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SU_PERFCOUNTER0_LO -#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SU_PERFCOUNTER0_HI -#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL -//PA_SU_PERFCOUNTER1_LO -#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SU_PERFCOUNTER1_HI -#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL -//PA_SU_PERFCOUNTER2_LO -#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SU_PERFCOUNTER2_HI -#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL -//PA_SU_PERFCOUNTER3_LO -#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SU_PERFCOUNTER3_HI -#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL -//PA_SC_PERFCOUNTER0_LO -#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER0_HI -#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER1_LO -#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER1_HI -#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER2_LO -#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER2_HI -#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER3_LO -#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER3_HI -#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER4_LO -#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER4_HI -#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER5_LO -#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER5_HI -#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER6_LO -#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER6_HI -#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER7_LO -#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER7_HI -#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER0_HI -#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER0_LO -#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER1_HI -#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER1_LO -#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER2_HI -#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER2_LO -#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER3_HI -#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER3_LO -#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER4_HI -#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER4_LO -#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER5_HI -#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER5_LO -#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER0_LO -#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER0_HI -#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER1_LO -#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER1_HI -#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER2_LO -#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER2_HI -#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER3_LO -#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER3_HI -#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER4_LO -#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER4_HI -#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER5_LO -#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER5_HI -#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER6_LO -#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER6_HI -#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER7_LO -#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER7_HI -#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER8_LO -#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER8_HI -#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER9_LO -#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER9_HI -#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER10_LO -#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER10_HI -#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER11_LO -#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER11_HI -#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER12_LO -#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER12_HI -#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER13_LO -#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER13_HI -#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER14_LO -#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER14_HI -#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER15_LO -#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER15_HI -#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER0_LO -#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER0_HI -#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER1_LO -#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER1_HI -#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER2_LO -#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER2_HI -#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER3_LO -#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER3_HI -#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER0_LO -#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER0_HI -#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER1_LO -#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER1_HI -#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER2_LO -#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER2_HI -#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER3_LO -#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER3_HI -#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TA_PERFCOUNTER0_LO -#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TA_PERFCOUNTER0_HI -#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TA_PERFCOUNTER1_LO -#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TA_PERFCOUNTER1_HI -#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TD_PERFCOUNTER0_LO -#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TD_PERFCOUNTER0_HI -#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TD_PERFCOUNTER1_LO -#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TD_PERFCOUNTER1_HI -#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER0_LO -#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER0_HI -#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER1_LO -#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER1_HI -#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER2_LO -#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER2_HI -#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER3_LO -#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER3_HI -#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER0_LO -#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER0_HI -#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER1_LO -#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER1_HI -#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER2_LO -#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER2_HI -#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER3_LO -#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER3_HI -#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER0_LO -#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER0_HI -#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER1_LO -#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER1_HI -#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER2_LO -#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER2_HI -#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER3_LO -#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER3_HI -#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER0_LO -#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER0_HI -#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER1_LO -#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER1_HI -#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER2_LO -#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER2_HI -#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER3_LO -#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER3_HI -#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER0_LO -#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER0_HI -#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER1_LO -#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER1_HI -#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER2_LO -#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER2_HI -#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER3_LO -#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER3_HI -#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//RLC_PERFCOUNTER0_LO -#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//RLC_PERFCOUNTER0_HI -#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//RLC_PERFCOUNTER1_LO -#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//RLC_PERFCOUNTER1_HI -#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER0_LO -#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER0_HI -#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER1_LO -#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER1_HI -#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER2_LO -#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER2_HI -#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER3_LO -#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER3_HI -#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL - - -// addressBlock: gc_utcl2_atcl2pfcntrdec -//ATC_L2_PERFCOUNTER_LO -#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//ATC_L2_PERFCOUNTER_HI -#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L - - -// addressBlock: gc_utcl2_vml2prdec -//MC_VM_L2_PERFCOUNTER_LO -#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//MC_VM_L2_PERFCOUNTER_HI -#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L - - -// addressBlock: gc_perfsdec -//CPG_PERFCOUNTER1_SELECT -#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 -#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa -#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 -#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 -#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c -#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL -#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L -#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L -#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L -#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L -//CPG_PERFCOUNTER0_SELECT1 -#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 -#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa -#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 -#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c -#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL -#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L -#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L -#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L -//CPG_PERFCOUNTER0_SELECT -#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 -#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa -#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c -#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL -#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L -#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L -//CPC_PERFCOUNTER1_SELECT -#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 -#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa -#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 -#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 -#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c -#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL -#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L -#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L -#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L -#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L -//CPC_PERFCOUNTER0_SELECT1 -#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 -#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa -#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 -#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c -#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL -#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L -#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L -#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L -//CPF_PERFCOUNTER1_SELECT -#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 -#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa -#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 -#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 -#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c -#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL -#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L -#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L -#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L -#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L -//CPF_PERFCOUNTER0_SELECT1 -#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 -#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa -#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 -#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c -#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL -#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L -#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L -#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L -//CPF_PERFCOUNTER0_SELECT -#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 -#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa -#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c -#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL -#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L -#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L -//CP_PERFMON_CNTL -#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 -#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 -#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 -#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa -#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL -#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L -#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L -#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L -//CPC_PERFCOUNTER0_SELECT -#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 -#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa -#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c -#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL -#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L -#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L -//CPF_TC_PERF_COUNTER_WINDOW_SELECT -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L -//CPG_TC_PERF_COUNTER_WINDOW_SELECT -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L -//CPF_LATENCY_STATS_SELECT -#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 -#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e -#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f -#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL -#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L -#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L -//CPG_LATENCY_STATS_SELECT -#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 -#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e -#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f -#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL -#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L -#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L -//CPC_LATENCY_STATS_SELECT -#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 -#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e -#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f -#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L -#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L -#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L -//CP_DRAW_OBJECT -#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 -#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL -//CP_DRAW_OBJECT_COUNTER -#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 -#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL -//CP_DRAW_WINDOW_MASK_HI -#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 -#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL -//CP_DRAW_WINDOW_HI -#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 -#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL -//CP_DRAW_WINDOW_LO -#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 -#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 -#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL -#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L -//CP_DRAW_WINDOW_CNTL -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 -#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L -#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L -//GRBM_PERFCOUNTER0_SELECT -#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa -#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb -#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc -#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd -#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe -#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 -#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 -#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 -#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 -#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 -#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 -#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 -#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 -#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 -#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 -#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a -#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b -#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c -#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d -#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e -#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f -#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL -#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L -#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L -#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L -#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L -#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L -#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L -#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L -#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L -#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L -#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L -//GRBM_PERFCOUNTER1_SELECT -#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa -#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb -#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc -#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd -#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe -#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 -#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 -#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 -#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 -#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 -#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 -#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 -#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 -#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 -#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 -#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a -#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b -#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c -#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d -#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e -#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f -#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL -#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L -#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L -#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L -#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L -#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L -#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L -#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L -#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L -#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L -#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L -//GRBM_SE0_PERFCOUNTER_SELECT -#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb -#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc -#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd -#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf -#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 -#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 -#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 -#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 -#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 -#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -//GRBM_SE1_PERFCOUNTER_SELECT -#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb -#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc -#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd -#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf -#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 -#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 -#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 -#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 -#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 -#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -//GRBM_SE2_PERFCOUNTER_SELECT -#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb -#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc -#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd -#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf -#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 -#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 -#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 -#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 -#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 -#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -//GRBM_SE3_PERFCOUNTER_SELECT -#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb -#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc -#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd -#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf -#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 -#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 -#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 -#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 -#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 -#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -//WD_PERFCOUNTER0_SELECT -#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL -#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//WD_PERFCOUNTER1_SELECT -#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL -#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//WD_PERFCOUNTER2_SELECT -#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL -#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//WD_PERFCOUNTER3_SELECT -#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL -#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//IA_PERFCOUNTER0_SELECT -#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//IA_PERFCOUNTER1_SELECT -#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL -#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//IA_PERFCOUNTER2_SELECT -#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL -#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//IA_PERFCOUNTER3_SELECT -#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL -#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//IA_PERFCOUNTER0_SELECT1 -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//VGT_PERFCOUNTER0_SELECT -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//VGT_PERFCOUNTER1_SELECT -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//VGT_PERFCOUNTER2_SELECT -#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL -#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//VGT_PERFCOUNTER3_SELECT -#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL -#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//VGT_PERFCOUNTER0_SELECT1 -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//VGT_PERFCOUNTER1_SELECT1 -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L -//VGT_PERFCOUNTER_SEID_MASK -#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 -#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL -//PA_SU_PERFCOUNTER0_SELECT -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -//PA_SU_PERFCOUNTER0_SELECT1 -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -//PA_SU_PERFCOUNTER1_SELECT -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -//PA_SU_PERFCOUNTER1_SELECT1 -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -//PA_SU_PERFCOUNTER2_SELECT -#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -//PA_SU_PERFCOUNTER3_SELECT -#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -//PA_SC_PERFCOUNTER0_SELECT -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -//PA_SC_PERFCOUNTER0_SELECT1 -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -//PA_SC_PERFCOUNTER1_SELECT -#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -//PA_SC_PERFCOUNTER2_SELECT -#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -//PA_SC_PERFCOUNTER3_SELECT -#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -//PA_SC_PERFCOUNTER4_SELECT -#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL -//PA_SC_PERFCOUNTER5_SELECT -#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL -//PA_SC_PERFCOUNTER6_SELECT -#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL -//PA_SC_PERFCOUNTER7_SELECT -#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL -//SPI_PERFCOUNTER0_SELECT -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//SPI_PERFCOUNTER1_SELECT -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//SPI_PERFCOUNTER2_SELECT -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa -#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 -#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L -#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//SPI_PERFCOUNTER3_SELECT -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa -#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 -#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L -#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//SPI_PERFCOUNTER0_SELECT1 -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//SPI_PERFCOUNTER1_SELECT1 -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 -#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L -//SPI_PERFCOUNTER2_SELECT1 -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa -#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 -#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L -//SPI_PERFCOUNTER3_SELECT1 -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa -#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 -#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L -//SPI_PERFCOUNTER4_SELECT -#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 -#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL -//SPI_PERFCOUNTER5_SELECT -#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 -#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL -//SPI_PERFCOUNTER_BINS -#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 -#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 -#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 -#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc -#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 -#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 -#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 -#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c -#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL -#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L -#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L -#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L -#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L -#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L -#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L -#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L -//SQ_PERFCOUNTER0_SELECT -#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER1_SELECT -#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER2_SELECT -#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER3_SELECT -#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER4_SELECT -#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER5_SELECT -#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER6_SELECT -#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER7_SELECT -#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER8_SELECT -#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER9_SELECT -#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER10_SELECT -#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER11_SELECT -#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER12_SELECT -#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER13_SELECT -#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER14_SELECT -#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER15_SELECT -#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER_CTRL -#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 -#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 -#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 -#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 -#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 -#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 -#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 -#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 -#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd -#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L -#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L -#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L -#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L -#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L -#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L -#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L -#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L -#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L -//SQ_PERFCOUNTER_MASK -#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 -#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL -#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L -//SQ_PERFCOUNTER_CTRL2 -#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 -#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L -//SX_PERFCOUNTER0_SELECT -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -//SX_PERFCOUNTER1_SELECT -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -//SX_PERFCOUNTER2_SELECT -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -//SX_PERFCOUNTER3_SELECT -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -//SX_PERFCOUNTER0_SELECT1 -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L -//SX_PERFCOUNTER1_SELECT1 -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L -//GDS_PERFCOUNTER0_SELECT -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -//GDS_PERFCOUNTER1_SELECT -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -//GDS_PERFCOUNTER2_SELECT -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -//GDS_PERFCOUNTER3_SELECT -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -//GDS_PERFCOUNTER0_SELECT1 -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L -//TA_PERFCOUNTER0_SELECT -#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL -#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L -#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//TA_PERFCOUNTER0_SELECT1 -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//TA_PERFCOUNTER1_SELECT -#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL -#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L -#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//TD_PERFCOUNTER0_SELECT -#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL -#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L -#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//TD_PERFCOUNTER0_SELECT1 -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//TD_PERFCOUNTER1_SELECT -#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL -#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L -#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//TCP_PERFCOUNTER0_SELECT -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//TCP_PERFCOUNTER0_SELECT1 -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//TCP_PERFCOUNTER1_SELECT -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//TCP_PERFCOUNTER1_SELECT1 -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L -//TCP_PERFCOUNTER2_SELECT -#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//TCP_PERFCOUNTER3_SELECT -#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//TCC_PERFCOUNTER0_SELECT -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//TCC_PERFCOUNTER0_SELECT1 -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L -//TCC_PERFCOUNTER1_SELECT -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//TCC_PERFCOUNTER1_SELECT1 -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L -//TCC_PERFCOUNTER2_SELECT -#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//TCC_PERFCOUNTER3_SELECT -#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//TCA_PERFCOUNTER0_SELECT -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//TCA_PERFCOUNTER0_SELECT1 -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L -//TCA_PERFCOUNTER1_SELECT -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//TCA_PERFCOUNTER1_SELECT1 -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L -//TCA_PERFCOUNTER2_SELECT -#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//TCA_PERFCOUNTER3_SELECT -#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//CB_PERFCOUNTER_FILTER -#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 -#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 -#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L -#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L -//CB_PERFCOUNTER0_SELECT -#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL -#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L -#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//CB_PERFCOUNTER0_SELECT1 -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//CB_PERFCOUNTER1_SELECT -#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL -#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//CB_PERFCOUNTER2_SELECT -#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL -#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//CB_PERFCOUNTER3_SELECT -#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL -#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//DB_PERFCOUNTER0_SELECT -#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//DB_PERFCOUNTER0_SELECT1 -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//DB_PERFCOUNTER1_SELECT -#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//DB_PERFCOUNTER1_SELECT1 -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L -//DB_PERFCOUNTER2_SELECT -#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa -#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 -#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L -#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//DB_PERFCOUNTER3_SELECT -#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa -#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 -#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L -#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//RLC_SPM_PERFMON_CNTL -#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x2 -#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc -#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe -#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 -#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFCL -#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L -#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L -#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L -//RLC_SPM_PERFMON_RING_BASE_LO -#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 -#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL -//RLC_SPM_PERFMON_RING_BASE_HI -#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 -#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 -#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL -#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L -//RLC_SPM_PERFMON_RING_SIZE -#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 -#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL -//RLC_SPM_PERFMON_SEGMENT_SIZE -#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f -#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L -//RLC_SPM_SE_MUXSEL_ADDR -#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 -#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL -//RLC_SPM_SE_MUXSEL_DATA -#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 -#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL -//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_CB_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_DB_PERFMON_SAMPLE_DELAY -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_PA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_IA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_SC_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_TA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_TD_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_SX_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_GLOBAL_MUXSEL_ADDR -#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 -#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL -//RLC_SPM_GLOBAL_MUXSEL_DATA -#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 -#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL -//RLC_SPM_RING_RDPTR -#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 -#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL -//RLC_SPM_SEGMENT_THRESHOLD -#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 -#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL -//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY -#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_PERFMON_CLK_CNTL -#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 -#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L -//RLC_PERFMON_CNTL -#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 -#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa -#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L -#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L -//RLC_PERFCOUNTER0_SELECT -#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL -//RLC_PERFCOUNTER1_SELECT -#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL -//RLC_GPU_IOV_PERF_CNT_CNTL -#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 -#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 -#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 -#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 -#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L -#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L -#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L -#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L -//RLC_GPU_IOV_PERF_CNT_WR_ADDR -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4 -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6 -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L -//RLC_GPU_IOV_PERF_CNT_WR_DATA -#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 -#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL -//RLC_GPU_IOV_PERF_CNT_RD_ADDR -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4 -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6 -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L -//RLC_GPU_IOV_PERF_CNT_RD_DATA -#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 -#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL -//RMI_PERFCOUNTER0_SELECT -#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL -#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L -#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//RMI_PERFCOUNTER0_SELECT1 -#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL -#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L -#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//RMI_PERFCOUNTER1_SELECT -#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL -#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//RMI_PERFCOUNTER2_SELECT -#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa -#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 -#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL -#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L -#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L -#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//RMI_PERFCOUNTER2_SELECT1 -#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 -#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa -#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 -#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c -#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL -#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L -#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L -//RMI_PERFCOUNTER3_SELECT -#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL -#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//RMI_PERF_COUNTER_CNTL -#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 -#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 -#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 -#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 -#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 -#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 -#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a -#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L -#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL -#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L -#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L -#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L -#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L -#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L - - -// addressBlock: gc_utcl2_atcl2pfcntldec -//ATC_L2_PERFCOUNTER0_CFG -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//ATC_L2_PERFCOUNTER1_CFG -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//ATC_L2_PERFCOUNTER_RSLT_CNTL -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - - -// addressBlock: gc_utcl2_vml2pldec -//MC_VM_L2_PERFCOUNTER0_CFG -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER1_CFG -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER2_CFG -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER3_CFG -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER4_CFG -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER5_CFG -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER6_CFG -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER7_CFG -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER_RSLT_CNTL -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - - -// addressBlock: gc_rlcpdec -//RLC_CNTL -#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 -#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 -#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 -#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 -#define RLC_CNTL__RESERVED__SHIFT 0x4 -#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L -#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L -#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L -#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L -#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L -//RLC_STAT -#define RLC_STAT__RLC_BUSY__SHIFT 0x0 -#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1 -#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2 -#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x3 -#define RLC_STAT__MC_BUSY__SHIFT 0x4 -#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 -#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 -#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 -#define RLC_STAT__RESERVED__SHIFT 0x8 -#define RLC_STAT__RLC_BUSY_MASK 0x00000001L -#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L -#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L -#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000008L -#define RLC_STAT__MC_BUSY_MASK 0x00000010L -#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L -#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L -#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L -#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L -//RLC_SAFE_MODE -#define RLC_SAFE_MODE__CMD__SHIFT 0x0 -#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 -#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 -#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 -#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc -#define RLC_SAFE_MODE__CMD_MASK 0x00000001L -#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL -#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L -#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L -#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L -//RLC_MEM_SLP_CNTL -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 -#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 -#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 -#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 -#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L -#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L -#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL -#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L -#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L -//SMU_RLC_RESPONSE -#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 -#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL -//RLC_RLCV_SAFE_MODE -#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 -#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 -#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 -#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 -#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc -#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L -#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL -#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L -#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L -#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L -//RLC_SMU_SAFE_MODE -#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 -#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 -#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 -#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 -#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc -#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L -#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL -#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L -#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L -#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L -//RLC_RLCV_COMMAND -#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 -#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 -#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL -#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L -//RLC_REFCLOCK_TIMESTAMP_LSB -#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 -#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL -//RLC_REFCLOCK_TIMESTAMP_MSB -#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 -#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL -//RLC_GPM_TIMER_INT_0 -#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 -#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL -//RLC_GPM_TIMER_INT_1 -#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 -#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL -//RLC_GPM_TIMER_INT_2 -#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 -#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL -//RLC_GPM_TIMER_CTRL -#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 -#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 -#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 -#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 -#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4 -#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L -#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L -#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L -#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L -#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L -//RLC_LB_CNTR_MAX -#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 -#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL -//RLC_GPM_TIMER_STAT -#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 -#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 -#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 -#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 -#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x4 -#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L -#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L -#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L -#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L -#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFFFF0L -//RLC_GPM_TIMER_INT_3 -#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 -#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL -//RLC_SERDES_WR_NONCU_MASTER_MASK_1 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L -//RLC_SERDES_NONCU_MASTER_BUSY_1 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL -#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L -//RLC_INT_STAT -#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 -#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 -#define RLC_INT_STAT__RESERVED__SHIFT 0x9 -#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL -#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L -#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L -//RLC_LB_CNTL -#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 -#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 -#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 -#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 -#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 -#define RLC_LB_CNTL__RESERVED__SHIFT 0xc -#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L -#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L -#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L -#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L -#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L -#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L -//RLC_MGCG_CTRL -#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 -#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 -#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 -#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 -#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 -#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf -#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10 -#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11 -#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L -#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L -#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L -#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L -#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L -#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L -#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L -#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L -//RLC_LB_CNTR_INIT -#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 -#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL -//RLC_LOAD_BALANCE_CNTR -#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 -#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL -//RLC_JUMP_TABLE_RESTORE -#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 -#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL -//RLC_PG_DELAY_2 -#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 -#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 -#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 -#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL -#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L -#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L -//RLC_GPU_CLOCK_COUNT_LSB -#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 -#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL -//RLC_GPU_CLOCK_COUNT_MSB -#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 -#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL -//RLC_CAPTURE_GPU_CLOCK_COUNT -#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 -#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 -#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L -#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL -//RLC_UCODE_CNTL -#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 -#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL -//RLC_GPM_THREAD_RESET -#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 -#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 -#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 -#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 -#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 -#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L -#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L -#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L -#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L -#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L -//RLC_GPM_CP_DMA_COMPLETE_T0 -#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 -#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 -#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L -#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL -//RLC_GPM_CP_DMA_COMPLETE_T1 -#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 -#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 -#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L -#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL -//RLC_FIREWALL_VIOLATION -#define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x0 -#define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xFFFFFFFFL -//RLC_GPM_STAT -#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 -#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 -#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 -#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 -#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 -#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 -#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 -#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 -#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 -#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 -#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa -#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb -#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc -#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd -#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe -#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf -#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 -#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 -#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 -#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 -#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 -#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 -#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 -#define RLC_GPM_STAT__RESERVED__SHIFT 0x17 -#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 -#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L -#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L -#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L -#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L -#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L -#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L -#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L -#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L -#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L -#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L -#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L -#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L -#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L -#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L -#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L -#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L -#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L -#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L -#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L -#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L -#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L -#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L -#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L -#define RLC_GPM_STAT__RESERVED_MASK 0x00800000L -#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L -//RLC_GPU_CLOCK_32_RES_SEL -#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 -#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 -#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL -#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L -//RLC_GPU_CLOCK_32 -#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 -#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL -//RLC_PG_CNTL -#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 -#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 -#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 -#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 -#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 -#define RLC_PG_CNTL__RESERVED__SHIFT 0x5 -#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe -#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf -#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 -#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13 -#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14 -#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L -#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L -#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L -#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L -#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L -#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L -#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L -#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L -#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L -#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L -#define RLC_PG_CNTL__RESERVED1_MASK 0x00F00000L -//RLC_GPM_THREAD_PRIORITY -#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 -#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 -#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 -#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 -#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL -#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L -#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L -#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L -//RLC_GPM_THREAD_ENABLE -#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 -#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 -#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 -#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 -#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 -#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L -#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L -#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L -#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L -#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L -//RLC_CGTT_MGCG_OVERRIDE -#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE__SHIFT 0x0 -#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 -#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 -#define RLC_CGTT_MGCG_OVERRIDE__RESERVED__SHIFT 0x8 -#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK 0x00000001L -#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L -#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L -#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_MASK 0xFFFFFF00L -//RLC_CGCG_CGLS_CTRL -#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 -#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 -#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 -#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 -#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b -#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c -#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d -#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f -#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L -#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L -#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL -#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L -#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L -#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L -#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L -#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L -//RLC_CGCG_RAMP_CTRL -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 -#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 -#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L -#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L -#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L -//RLC_DYN_PG_STATUS -#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 -#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL -//RLC_DYN_PG_REQUEST -#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 -#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL -//RLC_PG_DELAY -#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 -#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 -#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 -#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 -#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL -#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L -#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L -#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L -//RLC_CU_STATUS -#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 -#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL -//RLC_LB_INIT_CU_MASK -#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 -#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL -//RLC_LB_ALWAYS_ACTIVE_CU_MASK -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL -//RLC_LB_PARAMS -#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 -#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 -#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 -#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 -#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L -#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL -#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L -#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L -//RLC_THREAD1_DELAY -#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 -#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 -#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 -#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 -#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL -#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L -#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L -#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L -//RLC_PG_ALWAYS_ON_CU_MASK -#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 -#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL -//RLC_MAX_PG_CU -#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 -#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 -#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL -#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L -//RLC_AUTO_PG_CTRL -#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 -#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 -#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 -#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 -#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 -#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L -#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L -#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L -#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L -#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L -//RLC_SMU_GRBM_REG_SAVE_CTRL -#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 -#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 -#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L -#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL -//RLC_SERDES_RD_MASTER_INDEX -#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 -#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 -#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc -#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd -#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11 -#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13 -#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL -#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L -#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L -#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L -#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L -#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L -//RLC_SERDES_RD_DATA_0 -#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 -#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL -//RLC_SERDES_RD_DATA_1 -#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 -#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL -//RLC_SERDES_RD_DATA_2 -#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 -#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL -//RLC_SERDES_WR_CU_MASTER_MASK -#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 -#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL -//RLC_SERDES_WR_NONCU_MASTER_MASK -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L -//RLC_SERDES_WR_CTRL -#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 -#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 -#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 -#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa -#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb -#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc -#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd -#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe -#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf -#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10 -#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a -#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b -#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c -#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL -#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L -#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L -#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L -#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L -#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L -#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L -#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L -#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L -#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L -#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L -#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L -#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L -//RLC_SERDES_WR_DATA -#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 -#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL -//RLC_SERDES_CU_MASTER_BUSY -#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 -#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL -//RLC_SERDES_NONCU_MASTER_BUSY -#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17 -#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19 -#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a -#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L -#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L -#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L -//RLC_GPM_GENERAL_0 -#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_1 -#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_2 -#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_3 -#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_4 -#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_5 -#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_6 -#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_7 -#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_SCRATCH_ADDR -#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 -#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 -#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL -#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L -//RLC_GPM_SCRATCH_DATA -#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 -#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL -//RLC_STATIC_PG_STATUS -#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 -#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL -//RLC_SPM_MC_CNTL -#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 -#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4 -#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5 -#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6 -#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7 -#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8 -#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa -#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL -#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L -#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L -#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L -#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L -#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L -#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L -//RLC_SPM_INT_CNTL -#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 -#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 -#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L -#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL -//RLC_SPM_INT_STATUS -#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 -#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 -#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L -#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL -//RLC_SMU_MESSAGE -#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 -#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL -//RLC_GPM_LOG_SIZE -#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 -#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL -//RLC_PG_DELAY_3 -#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 -#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 -#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL -#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L -//RLC_GPR_REG1 -#define RLC_GPR_REG1__DATA__SHIFT 0x0 -#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL -//RLC_GPR_REG2 -#define RLC_GPR_REG2__DATA__SHIFT 0x0 -#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_LOG_CONT -#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 -#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL -//RLC_GPM_INT_DISABLE_TH0 -#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 -#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL -//RLC_GPM_INT_DISABLE_TH1 -#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0 -#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xFFFFFFFFL -//RLC_GPM_INT_FORCE_TH0 -#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 -#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL -//RLC_GPM_INT_FORCE_TH1 -#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0 -#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL -//RLC_SRM_CNTL -#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 -#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 -#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 -#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L -#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L -#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL -//RLC_SRM_ARAM_ADDR -#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 -#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc -#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL -#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L -//RLC_SRM_ARAM_DATA -#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 -#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_DRAM_ADDR -#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 -#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc -#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL -#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L -//RLC_SRM_DRAM_DATA -#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 -#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_GPM_COMMAND -#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 -#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 -#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 -#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d -#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f -#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL -#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0001FFE0L -#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L -#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000L -#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L -//RLC_SRM_GPM_COMMAND_STATUS -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 -#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L -#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL -//RLC_SRM_RLCV_COMMAND -#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 -#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 -#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 -#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 -#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c -#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f -#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L -#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL -#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L -#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L -#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L -#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L -//RLC_SRM_RLCV_COMMAND_STATUS -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 -#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L -#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL -//RLC_SRM_INDEX_CNTL_ADDR_0 -#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_1 -#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_2 -#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_3 -#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_4 -#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_5 -#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_6 -#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_7 -#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_DATA_0 -#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_1 -#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_2 -#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_3 -#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_4 -#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_5 -#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_6 -#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_7 -#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_STAT -#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 -#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1 -#define RLC_SRM_STAT__RESERVED__SHIFT 0x2 -#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L -#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L -#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL -//RLC_SRM_GPM_ABORT -#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 -#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 -#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L -#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL -//RLC_CSIB_ADDR_LO -#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 -#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL -//RLC_CSIB_ADDR_HI -#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 -#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL -//RLC_CSIB_LENGTH -#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 -#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL -//RLC_SMU_COMMAND -#define RLC_SMU_COMMAND__CMD__SHIFT 0x0 -#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL -//RLC_CP_SCHEDULERS -#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 -#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 -#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 -#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 -#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL -#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L -#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L -#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L -//RLC_SMU_ARGUMENT_1 -#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 -#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL -//RLC_SMU_ARGUMENT_2 -#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 -#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_8 -#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_9 -#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_10 -#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_11 -#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_12 -#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_UTCL1_CNTL_0 -#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 -#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 -#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a -#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b -#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c -#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e -#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L -#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L -#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L -#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L -#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L -//RLC_GPM_UTCL1_CNTL_1 -#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18 -#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19 -#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a -#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b -#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c -#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e -#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L -#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L -#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L -#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L -#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L -//RLC_GPM_UTCL1_CNTL_2 -#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18 -#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19 -#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a -#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b -#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c -#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e -#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L -#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L -#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L -#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L -#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L -//RLC_SPM_UTCL1_CNTL -#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e -#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L -//RLC_UTCL1_STATUS_2 -#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 -#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 -#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 -#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 -#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4 -#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5 -#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6 -#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7 -#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8 -#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9 -#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa -#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L -#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L -#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L -#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L -#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L -#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L -#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L -#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L -#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L -#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L -#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L -//RLC_LB_THR_CONFIG_2 -#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0 -#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL -//RLC_LB_THR_CONFIG_3 -#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0 -#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL -//RLC_LB_THR_CONFIG_4 -#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0 -#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL -//RLC_SPM_UTCL1_ERROR_1 -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L -//RLC_SPM_UTCL1_ERROR_2 -#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 -#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL -//RLC_GPM_UTCL1_TH0_ERROR_1 -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L -//RLC_LB_THR_CONFIG_1 -#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0 -#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_UTCL1_TH0_ERROR_2 -#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 -#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL -//RLC_GPM_UTCL1_TH1_ERROR_1 -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0 -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L -//RLC_GPM_UTCL1_TH1_ERROR_2 -#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 -#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL -//RLC_GPM_UTCL1_TH2_ERROR_1 -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0 -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L -//RLC_GPM_UTCL1_TH2_ERROR_2 -#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 -#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL -//RLC_CGCG_CGLS_CTRL_3D -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0 -#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1 -#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c -#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d -#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L -#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L -#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L -#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L -#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L -//RLC_CGCG_RAMP_CTRL_3D -#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0 -#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4 -#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8 -#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc -#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10 -#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c -#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL -#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L -#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L -#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L -#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L -#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L -//RLC_SEMAPHORE_0 -#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 -#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5 -#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL -#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L -//RLC_SEMAPHORE_1 -#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 -#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5 -#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL -#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L -//RLC_CP_EOF_INT -#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 -#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 -#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L -#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL -//RLC_CP_EOF_INT_CNT -#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0 -#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL -//RLC_SPARE_INT -#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0 -#define RLC_SPARE_INT__RESERVED__SHIFT 0x1 -#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L -#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL -//RLC_PREWALKER_UTCL1_CNTL -#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e -#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L -//RLC_PREWALKER_UTCL1_TRIG -#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0 -#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1 -#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5 -#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6 -#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7 -#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8 -#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9 -#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f -#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L -#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL -#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L -#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L -#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L -#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L -#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L -#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L -//RLC_PREWALKER_UTCL1_ADDR_LSB -#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0 -#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL -//RLC_PREWALKER_UTCL1_ADDR_MSB -#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0 -#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL -//RLC_PREWALKER_UTCL1_SIZE_LSB -#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0 -#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL -//RLC_PREWALKER_UTCL1_SIZE_MSB -#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0 -#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L -//RLC_DSM_TRIG -//RLC_UTCL1_STATUS -#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 -#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 -#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe -#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 -#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 -#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 -#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e -#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L -#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L -#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L -#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L -#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L -#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L -#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L -//RLC_R2I_CNTL_0 -#define RLC_R2I_CNTL_0__Data__SHIFT 0x0 -#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL -//RLC_R2I_CNTL_1 -#define RLC_R2I_CNTL_1__Data__SHIFT 0x0 -#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL -//RLC_R2I_CNTL_2 -#define RLC_R2I_CNTL_2__Data__SHIFT 0x0 -#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL -//RLC_R2I_CNTL_3 -#define RLC_R2I_CNTL_3__Data__SHIFT 0x0 -#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL -//RLC_UTCL2_CNTL -#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 -#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1 -#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L -#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL -//RLC_LBPW_CU_STAT -#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0 -#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10 -#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL -#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L -//RLC_DS_CNTL -#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0 -#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1 -#define RLC_DS_CNTL__RESRVED__SHIFT 0x2 -#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10 -#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11 -#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12 -#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L -#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L -#define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL -#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L -#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L -#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L -//RLC_RLCV_SPARE_INT -#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 -#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 -#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L -#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL - - -// addressBlock: gc_pwrdec -//CGTS_SM_CTRL_REG -#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 -#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 -#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc -#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 -#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 -#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 -#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 -#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 -#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL -#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L -#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L -#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L -#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L -#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L -#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L -#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L -//CGTS_RD_CTRL_REG -#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 -#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 -#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL -#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L -//CGTS_RD_REG -#define CGTS_RD_REG__READ_DATA__SHIFT 0x0 -#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL -//CGTS_TCC_DISABLE -#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 -#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L -//CGTS_USER_TCC_DISABLE -#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 -#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L -//CGTS_CU0_SP0_CTRL_REG -#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU0_LDS_SQ_CTRL_REG -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU0_TA_SQC_CTRL_REG -#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU0_SP1_CTRL_REG -#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU0_TD_TCP_CTRL_REG -#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU1_SP0_CTRL_REG -#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU1_LDS_SQ_CTRL_REG -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU1_TA_SQC_CTRL_REG -#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU1_SP1_CTRL_REG -#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU1_TD_TCP_CTRL_REG -#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU2_SP0_CTRL_REG -#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU2_LDS_SQ_CTRL_REG -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU2_TA_SQC_CTRL_REG -#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU2_SP1_CTRL_REG -#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU2_TD_TCP_CTRL_REG -#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU3_SP0_CTRL_REG -#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU3_LDS_SQ_CTRL_REG -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU3_TA_SQC_CTRL_REG -#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU3_SP1_CTRL_REG -#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU3_TD_TCP_CTRL_REG -#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU4_SP0_CTRL_REG -#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU4_LDS_SQ_CTRL_REG -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU4_TA_SQC_CTRL_REG -#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU4_SP1_CTRL_REG -#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU4_TD_TCP_CTRL_REG -#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU5_SP0_CTRL_REG -#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU5_LDS_SQ_CTRL_REG -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU5_TA_SQC_CTRL_REG -#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU5_SP1_CTRL_REG -#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU5_TD_TCP_CTRL_REG -#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU6_SP0_CTRL_REG -#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU6_LDS_SQ_CTRL_REG -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU6_TA_SQC_CTRL_REG -#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU6_SP1_CTRL_REG -#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU6_TD_TCP_CTRL_REG -#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU7_SP0_CTRL_REG -#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU7_LDS_SQ_CTRL_REG -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU7_TA_SQC_CTRL_REG -#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU7_SP1_CTRL_REG -#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU7_TD_TCP_CTRL_REG -#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU8_SP0_CTRL_REG -#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU8_LDS_SQ_CTRL_REG -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU8_TA_SQC_CTRL_REG -#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU8_SP1_CTRL_REG -#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU8_TD_TCP_CTRL_REG -#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU9_SP0_CTRL_REG -#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU9_LDS_SQ_CTRL_REG -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU9_TA_SQC_CTRL_REG -#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU9_SP1_CTRL_REG -#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU9_TD_TCP_CTRL_REG -#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU10_SP0_CTRL_REG -#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU10_LDS_SQ_CTRL_REG -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU10_TA_SQC_CTRL_REG -#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU10_SP1_CTRL_REG -#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU10_TD_TCP_CTRL_REG -#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU11_SP0_CTRL_REG -#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU11_LDS_SQ_CTRL_REG -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU11_TA_SQC_CTRL_REG -#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU11_SP1_CTRL_REG -#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU11_TD_TCP_CTRL_REG -#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU12_SP0_CTRL_REG -#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU12_LDS_SQ_CTRL_REG -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU12_TA_SQC_CTRL_REG -#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU12_SP1_CTRL_REG -#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU12_TD_TCP_CTRL_REG -#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU13_SP0_CTRL_REG -#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU13_LDS_SQ_CTRL_REG -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU13_TA_SQC_CTRL_REG -#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU13_SP1_CTRL_REG -#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU13_TD_TCP_CTRL_REG -#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU14_SP0_CTRL_REG -#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU14_LDS_SQ_CTRL_REG -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU14_TA_SQC_CTRL_REG -#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU14_SP1_CTRL_REG -#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU14_TD_TCP_CTRL_REG -#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU15_SP0_CTRL_REG -#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU15_LDS_SQ_CTRL_REG -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU15_TA_SQC_CTRL_REG -#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU15_SP1_CTRL_REG -#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU15_TD_TCP_CTRL_REG -#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU0_TCPI_CTRL_REG -#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU1_TCPI_CTRL_REG -#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU2_TCPI_CTRL_REG -#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU3_TCPI_CTRL_REG -#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU4_TCPI_CTRL_REG -#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU5_TCPI_CTRL_REG -#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU6_TCPI_CTRL_REG -#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU7_TCPI_CTRL_REG -#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU8_TCPI_CTRL_REG -#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU9_TCPI_CTRL_REG -#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU10_TCPI_CTRL_REG -#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU11_TCPI_CTRL_REG -#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU12_TCPI_CTRL_REG -#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU13_TCPI_CTRL_REG -#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU14_TCPI_CTRL_REG -#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU15_TCPI_CTRL_REG -#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTT_SPI_CLK_CTRL -#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 -#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a -#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b -#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c -#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d -#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e -#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L -#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L -#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L -#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L -#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L -#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L -#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_PC_CLK_CTRL -#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 -#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 -#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19 -#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a -#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b -#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c -#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d -#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e -#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L -#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L -#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L -#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L -#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L -#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L -#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L -#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L -#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_BCI_CLK_CTRL -#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 -#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 -#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a -#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b -#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c -#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d -#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e -#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L -#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L -#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L -#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L -#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L -#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L -#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L -#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_VGT_CLK_CTRL -#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18 -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a -#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b -#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c -#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d -#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e -#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L -#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L -#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L -#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L -#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_IA_CLK_CTRL -#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e -#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_WD_CLK_CTRL -#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a -#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b -#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c -#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d -#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e -#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L -#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L -#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L -#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L -#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L -#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_PA_CLK_CTRL -#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d -#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e -#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f -#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L -#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L -#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L -//CGTT_SC_CLK_CTRL0 -#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0 -#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16 -#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 -#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18 -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19 -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e -#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f -#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL -#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L -#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L -#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L -#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L -//CGTT_SC_CLK_CTRL1 -#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0 -#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 -#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 -#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13 -#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14 -#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 -#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 -#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 -#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a -#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b -#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c -#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d -#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e -#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL -#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L -#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L -#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L -#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L -#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L -#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L -#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L -#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L -#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L -#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L -#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L -#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L -//CGTT_SQ_CLK_CTRL -#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d -#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e -#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L -#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_SQG_CLK_CTRL -#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c -#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d -#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e -#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L -#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L -#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//SQ_ALU_CLK_CTRL -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L -//SQ_TEX_CLK_CTRL -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L -//SQ_LDS_CLK_CTRL -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L -//SQ_POWER_THROTTLE -#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 -#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 -#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e -#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL -#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L -#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L -//SQ_POWER_THROTTLE2 -#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 -#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f -#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L -//CGTT_SX_CLK_CTRL0 -#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 -#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL -#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_SX_CLK_CTRL1 -#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 -#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL -#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_SX_CLK_CTRL2 -#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 -#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL -#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_SX_CLK_CTRL3 -#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 -#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL -#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_SX_CLK_CTRL4 -#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 -#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL -#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L -//TD_CGTT_CTRL -#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 -#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL -#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//TA_CGTT_CTRL -#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 -#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL -#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_TCPI_CLK_CTRL -#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_TCI_CLK_CTRL -#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_GDS_CLK_CTRL -#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//DB_CGTT_CLK_CTRL_0 -#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 -#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 -#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f -#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL -#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L -//CB_CGTT_SCLK_CTRL -#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//TCC_CGTT_SCLK_CTRL -#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 -#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//TCA_CGTT_SCLK_CTRL -#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 -#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_CP_CLK_CTRL -#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f -#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -//CGTT_CPF_CLK_CTRL -#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f -#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -//CGTT_CPC_CLK_CTRL -#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f -#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -//RLC_PWR_CTRL -#define RLC_PWR_CTRL__MON_CGPG_RTN_EN__SHIFT 0x0 -#define RLC_PWR_CTRL__RESERVED__SHIFT 0x1 -#define RLC_PWR_CTRL__DLDO_STATUS__SHIFT 0x8 -#define RLC_PWR_CTRL__MON_CGPG_RTN_EN_MASK 0x00000001L -#define RLC_PWR_CTRL__RESERVED_MASK 0x000000FEL -#define RLC_PWR_CTRL__DLDO_STATUS_MASK 0x00000100L -//CGTT_RLC_CLK_CTRL -#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f -#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -//RLC_GFX_RM_CNTL -#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0 -#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1 -#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L -#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL -//RMI_CGTT_SCLK_CTRL -#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 -#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_TCPF_CLK_CTRL -#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - - -// addressBlock: gc_ea_pwrdec -//GCEA_CGTT_CLK_CTRL -#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e -#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f -#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L -#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L - - -// addressBlock: gc_utcl2_vmsharedhvdec -//MC_VM_FB_SIZE_OFFSET_VF0 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF1 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF2 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF3 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF4 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF5 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF6 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF7 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF8 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF9 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF10 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF11 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF12 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF13 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF14 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF15 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L -//VM_IOMMU_MMIO_CNTRL_1 -#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 -#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L -//MC_VM_MARC_BASE_LO_0 -#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc -#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L -//MC_VM_MARC_BASE_LO_1 -#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc -#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L -//MC_VM_MARC_BASE_LO_2 -#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc -#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L -//MC_VM_MARC_BASE_LO_3 -#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc -#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L -//MC_VM_MARC_BASE_HI_0 -#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 -#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL -//MC_VM_MARC_BASE_HI_1 -#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 -#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL -//MC_VM_MARC_BASE_HI_2 -#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 -#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL -//MC_VM_MARC_BASE_HI_3 -#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 -#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL -//MC_VM_MARC_RELOC_LO_0 -#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 -#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 -#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc -#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L -//MC_VM_MARC_RELOC_LO_1 -#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 -#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 -#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc -#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L -//MC_VM_MARC_RELOC_LO_2 -#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 -#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 -#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc -#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L -//MC_VM_MARC_RELOC_LO_3 -#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 -#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 -#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc -#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L -//MC_VM_MARC_RELOC_HI_0 -#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 -#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL -//MC_VM_MARC_RELOC_HI_1 -#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 -#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL -//MC_VM_MARC_RELOC_HI_2 -#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 -#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL -//MC_VM_MARC_RELOC_HI_3 -#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 -#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL -//MC_VM_MARC_LEN_LO_0 -#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc -#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L -//MC_VM_MARC_LEN_LO_1 -#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc -#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L -//MC_VM_MARC_LEN_LO_2 -#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc -#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L -//MC_VM_MARC_LEN_LO_3 -#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc -#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L -//MC_VM_MARC_LEN_HI_0 -#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 -#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL -//MC_VM_MARC_LEN_HI_1 -#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 -#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL -//MC_VM_MARC_LEN_HI_2 -#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 -#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL -//MC_VM_MARC_LEN_HI_3 -#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 -#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL -//VM_IOMMU_CONTROL_REGISTER -#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 -#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L -//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER -#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd -#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L -//VM_PCIE_ATS_CNTL -#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 -#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L -#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_0 -#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_1 -#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_2 -#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_3 -#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_4 -#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_5 -#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_6 -#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_7 -#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_8 -#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_9 -#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_10 -#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_11 -#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_12 -#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_13 -#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_14 -#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_15 -#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L -//UTCL2_CGTT_CLK_CTRL -#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc -#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 -#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L -#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L - - -// addressBlock: gc_hypdec -//CP_HYP_PFP_UCODE_ADDR -#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL -//CP_PFP_UCODE_ADDR -#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL -//CP_HYP_PFP_UCODE_DATA -#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_PFP_UCODE_DATA -#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_HYP_ME_UCODE_ADDR -#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL -//CP_ME_RAM_RADDR -#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 -#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL -//CP_ME_RAM_WADDR -#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 -#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL -//CP_HYP_ME_UCODE_DATA -#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_ME_RAM_DATA -#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 -#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL -//CP_CE_UCODE_ADDR -#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL -//CP_HYP_CE_UCODE_ADDR -#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL -//CP_CE_UCODE_DATA -#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_HYP_CE_UCODE_DATA -#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_HYP_MEC1_UCODE_ADDR -#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL -//CP_MEC_ME1_UCODE_ADDR -#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL -//CP_HYP_MEC1_UCODE_DATA -#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_MEC_ME1_UCODE_DATA -#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_HYP_MEC2_UCODE_ADDR -#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL -//CP_MEC_ME2_UCODE_ADDR -#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL -//CP_HYP_MEC2_UCODE_DATA -#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_MEC_ME2_UCODE_DATA -#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//RLC_GPM_UCODE_ADDR -#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe -#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL -#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L -//RLC_GPM_UCODE_DATA -#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//GRBM_GFX_INDEX_SR_SELECT -#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 -#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L -//GRBM_GFX_INDEX_SR_DATA -#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 -#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8 -#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 -#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d -#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e -#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f -#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL -#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L -#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L -#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L -#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L -#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L -//GRBM_GFX_CNTL_SR_SELECT -#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 -#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L -//GRBM_GFX_CNTL_SR_DATA -#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 -#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 -#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 -#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 -#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L -#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL -#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L -#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L -//GRBM_CAM_INDEX -#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 -#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L -//GRBM_HYP_CAM_INDEX -#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 -#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L -//GRBM_CAM_DATA -#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 -#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 -#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL -#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L -//GRBM_HYP_CAM_DATA -#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 -#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 -#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL -#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L -//RLC_GPU_IOV_VF_ENABLE -#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 -#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 -#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 -#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L -#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL -#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L -//RLC_GFX_RM_CNTL_ADJ -#define RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID__SHIFT 0x0 -#define RLC_GFX_RM_CNTL_ADJ__RESERVED__SHIFT 0x1 -#define RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID_MASK 0x00000001L -#define RLC_GFX_RM_CNTL_ADJ__RESERVED_MASK 0xFFFFFFFEL -//RLC_GPU_IOV_CFG_REG6 -#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 -#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 -#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 -#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa -#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL -#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L -#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L -#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L -//RLC_GPU_IOV_CFG_REG8 -#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 -#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL -//RLC_RLCV_TIMER_INT_0 -#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0 -#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL -//RLC_RLCV_TIMER_CTRL -#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 -#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x1 -#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L -#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFEL -//RLC_RLCV_TIMER_STAT -#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 -#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x1 -#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L -#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0xFFFFFFFEL -//RLC_GPU_IOV_VF_DOORBELL_STATUS -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L -//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L -//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L -//RLC_GPU_IOV_VF_MASK -#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 -#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10 -#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL -#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L -//RLC_HYP_SEMAPHORE_2 -#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 -#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5 -#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL -#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L -//RLC_HYP_SEMAPHORE_3 -#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 -#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5 -#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL -#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L -//RLC_CLK_CNTL -#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0 -#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x1 -#define RLC_CLK_CNTL__RESERVED__SHIFT 0x2 -#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000001L -#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x00000002L -#define RLC_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL -//RLC_GPU_IOV_SCH_BLOCK -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 -#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L -#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L -//RLC_GPU_IOV_CFG_REG1 -#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 -#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 -#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 -#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 -#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 -#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 -#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 -#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL -#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L -#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L -#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L -#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L -#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L -#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L -//RLC_GPU_IOV_CFG_REG2 -#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 -#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 -#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL -#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L -//RLC_GPU_IOV_VM_BUSY_STATUS -#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 -#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_SCH_0 -#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 -#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_ACTIVE_FCN_ID -#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 -#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 -#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f -#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL -#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L -#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L -//RLC_GPU_IOV_SCH_3 -#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 -#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_SCH_1 -#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 -#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_SCH_2 -#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 -#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_UCODE_ADDR -#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc -#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL -#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L -//RLC_GPU_IOV_UCODE_DATA -#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_SCRATCH_ADDR -#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 -#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9 -#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL -#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L -//RLC_GPU_IOV_SCRATCH_DATA -#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 -#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_F32_CNTL -#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 -#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1 -#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L -#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL -//RLC_GPU_IOV_F32_RESET -#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 -#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1 -#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L -#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL -//RLC_GPU_IOV_SDMA0_STATUS -#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0 -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1 -#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8 -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9 -#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd -#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL -#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L -#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L -//RLC_GPU_IOV_SDMA1_STATUS -#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0 -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1 -#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8 -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9 -#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd -#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL -#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L -#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L -//RLC_GPU_IOV_SMU_RESPONSE -#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 -#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_VIRT_RESET_REQ -#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 -#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10 -#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f -#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL -#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L -#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L -//RLC_GPU_IOV_RLC_RESPONSE -#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 -#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_INT_DISABLE -#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0 -#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_INT_FORCE -#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0 -#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_SDMA0_BUSY_STATUS -#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 -#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_SDMA1_BUSY_STATUS -#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 -#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL - - -// addressBlock: gccacind -//GC_CAC_CNTL -#define GC_CAC_CNTL__CAC_ENABLE__SHIFT 0x0 -#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 -#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 -#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 -#define GC_CAC_CNTL__UNUSED_0__SHIFT 0x1f -#define GC_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L -#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL -#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L -#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L -#define GC_CAC_CNTL__UNUSED_0_MASK 0x80000000L -//GC_CAC_OVR_SEL -#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 -#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL -//GC_CAC_OVR_VAL -#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 -#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL -//GC_CAC_WEIGHT_BCI_0 -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CB_0 -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CB_1 -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CP_0 -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CP_1 -#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_DB_0 -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_DB_1 -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_GDS_0 -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_GDS_1 -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_IA_0 -#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_LDS_0 -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_LDS_1 -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_PA_0 -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_PC_0 -#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SC_0 -#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SPI_0 -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SPI_1 -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SPI_2 -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SQ_0 -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SQ_1 -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SQ_2 -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SQ_3 -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0 -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10 -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SQ_4 -#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0 -#define GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SX_0 -#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SXRB_0 -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TA_0 -#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TCC_0 -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TCC_1 -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TCC_2 -#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TCP_0 -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TCP_1 -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TCP_2 -#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TD_0 -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TD_1 -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TD_2 -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_VGT_0 -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_VGT_1 -#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_WD_0 -#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CU_0 -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CU_1 -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CU_2 -#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CU_3 -#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0 -#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10 -#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CU_4 -#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT 0x0 -#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT 0x10 -#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CU_5 -#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT 0x0 -#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT 0x10 -#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK 0xFFFF0000L -//GC_CAC_ACC_BCI0 -#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CB0 -#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CB1 -#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CB2 -#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CB3 -#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CP0 -#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CP1 -#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CP2 -#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_DB0 -#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_DB1 -#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_DB2 -#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_DB3 -#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_GDS0 -#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_GDS1 -#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_GDS2 -#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_GDS3 -#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_IA0 -#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_LDS0 -#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_LDS1 -#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_LDS2 -#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_LDS3 -#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_PA0 -#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_PA1 -#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_PC0 -#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SC0 -#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SPI0 -#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SPI1 -#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SPI2 -#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SPI3 -#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SPI4 -#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SPI5 -#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_WEIGHT_PG_0 -#define GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_PG_0__unused__SHIFT 0x10 -#define GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_PG_0__unused_MASK 0xFFFF0000L -//GC_CAC_ACC_PG0 -#define GC_CAC_ACC_PG0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_PG0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_OVRD_PG -#define GC_CAC_OVRD_PG__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_PG__OVRRD_VALUE__SHIFT 0x10 -#define GC_CAC_OVRD_PG__OVRRD_SELECT_MASK 0x0000FFFFL -#define GC_CAC_OVRD_PG__OVRRD_VALUE_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_ATCL2_0 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L -//GC_CAC_ACC_EA0 -#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_EA1 -#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_EA2 -#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_EA3 -#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ATCL20 -#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_OVRD_EA -#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6 -#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL -#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L -//GC_CAC_OVRD_UTCL2_ATCL2 -#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5 -#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL -#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L -//GC_CAC_WEIGHT_EA_0 -#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_EA_1 -#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_RMI_0 -#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_RMI_0__UNUSED__SHIFT 0x10 -#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_RMI_0__UNUSED_MASK 0xFFFF0000L -//GC_CAC_ACC_RMI0 -#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_OVRD_RMI -#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_WEIGHT_UTCL2_ATCL2_1 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L -//GC_CAC_ACC_UTCL2_ATCL21 -#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ATCL22 -#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ATCL23 -#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_EA4 -#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_EA5 -#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_WEIGHT_EA_2 -#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L -//GC_CAC_ACC_SQ0_LOWER -#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ0_UPPER -#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ1_LOWER -#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ1_UPPER -#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ2_LOWER -#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ2_UPPER -#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ3_LOWER -#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ3_UPPER -#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ4_LOWER -#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ4_UPPER -#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ5_LOWER -#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ5_UPPER -#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ6_LOWER -#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ6_UPPER -#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ7_LOWER -#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ7_UPPER -#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ8_LOWER -#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ8_UPPER -#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SX0 -#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SXRB0 -#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SXRB1 -#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TA0 -#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCC0 -#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCC1 -#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCC2 -#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCC3 -#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCC4 -#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCP0 -#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCP1 -#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCP2 -#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCP3 -#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCP4 -#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TD0 -#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TD1 -#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TD2 -#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TD3 -#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TD4 -#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TD5 -#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_VGT0 -#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_VGT1 -#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_VGT2 -#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_WD0 -#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU0 -#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU1 -#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU2 -#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU3 -#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU4 -#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU5 -#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU6 -#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU7 -#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU8 -#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU9 -#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU10 -#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_OVRD_BCI -#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2 -#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L -#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL -//GC_CAC_OVRD_CB -#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4 -#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL -#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L -//GC_CAC_OVRD_CP -#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3 -#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L -#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L -//GC_CAC_OVRD_DB -#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4 -#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL -#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L -//GC_CAC_OVRD_GDS -#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4 -#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL -#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L -//GC_CAC_OVRD_IA -#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_LDS -#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4 -#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL -#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L -//GC_CAC_OVRD_PA -#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2 -#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L -#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL -//GC_CAC_OVRD_PC -#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_SC -#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_SPI -#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6 -#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL -#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L -//GC_CAC_OVRD_CU -#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_SQ -#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9 -#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL -#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L -//GC_CAC_OVRD_SX -#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_SXRB -#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_TA -#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_TCC -#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5 -#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL -#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L -//GC_CAC_OVRD_TCP -#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5 -#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL -#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L -//GC_CAC_OVRD_TD -#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6 -#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL -#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L -//GC_CAC_OVRD_VGT -#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3 -#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L -#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L -//GC_CAC_OVRD_WD -#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_ACC_BCI1 -#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_WEIGHT_UTCL2_ATCL2_2 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_ROUTER_0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_ROUTER_1 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_ROUTER_2 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_ROUTER_3 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_ROUTER_4 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_VML2_0 -#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_VML2_1 -#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_VML2_2 -#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5_MASK 0xFFFF0000L -//GC_CAC_ACC_UTCL2_ATCL24 -#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER0 -#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER1 -#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER2 -#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER3 -#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER4 -#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER5 -#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER6 -#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER7 -#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER8 -#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER9 -#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_VML20 -#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_VML21 -#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_VML22 -#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_VML23 -#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_VML24 -#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_OVRD_UTCL2_ROUTER -#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa -#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL -#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L -//GC_CAC_OVRD_UTCL2_VML2 -#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5 -#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL -#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L -//GC_CAC_WEIGHT_UTCL2_WALKER_0 -#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_WALKER_1 -#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_WALKER_2 -#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5_MASK 0xFFFF0000L -//GC_CAC_ACC_UTCL2_WALKER0 -#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_WALKER1 -#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_WALKER2 -#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_WALKER3 -#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_WALKER4 -#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_OVRD_UTCL2_WALKER -#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5 -#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL -#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L - - -// addressBlock: secacind -//SE_CAC_CNTL -#define SE_CAC_CNTL__CAC_ENABLE__SHIFT 0x0 -#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 -#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 -#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 -#define SE_CAC_CNTL__UNUSED_0__SHIFT 0x1f -#define SE_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L -#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL -#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L -#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L -#define SE_CAC_CNTL__UNUSED_0_MASK 0x80000000L -//SE_CAC_OVR_SEL -#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 -#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL -//SE_CAC_OVR_VAL -#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 -#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL - - -// addressBlock: sqind -//SQ_WAVE_MODE -#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 -#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 -#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 -#define SQ_WAVE_MODE__IEEE__SHIFT 0x9 -#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa -#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc -#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 -#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18 -#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19 -#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a -#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b -#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c -#define SQ_WAVE_MODE__CSP__SHIFT 0x1d -#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL -#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L -#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L -#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L -#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L -#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L -#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L -#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L -#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L -#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L -#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L -#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L -#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L -//SQ_WAVE_STATUS -#define SQ_WAVE_STATUS__SCC__SHIFT 0x0 -#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 -#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 -#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 -#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 -#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 -#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 -#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 -#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa -#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb -#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc -#define SQ_WAVE_STATUS__HALT__SHIFT 0xd -#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe -#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf -#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 -#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 -#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 -#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 -#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16 -#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 -#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b -#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L -#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L -#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L -#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L -#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L -#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L -#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L -#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L -#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L -#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L -#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L -#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L -#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L -#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L -#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L -#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L -#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L -#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L -#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L -#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L -#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L -//SQ_WAVE_TRAPSTS -#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 -#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa -#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb -#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc -#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 -#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c -#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d -#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL -#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L -#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L -#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L -#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L -#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L -#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L -//SQ_WAVE_HW_ID -#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 -#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 -#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 -#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 -#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc -#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd -#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 -#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 -#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 -#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b -#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e -#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL -#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L -#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L -#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L -#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L -#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00006000L -#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L -#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L -#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L -#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L -#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L -//SQ_WAVE_GPR_ALLOC -#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 -#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 -#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 -#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 -#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL -#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003F00L -#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003F0000L -#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L -//SQ_WAVE_LDS_ALLOC -#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 -#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc -#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL -#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L -//SQ_WAVE_IB_STS -#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 -#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 -#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 -#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc -#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf -#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 -#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16 -#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL -#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L -#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L -#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L -#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L -#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L -#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L -//SQ_WAVE_PC_LO -#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 -#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL -//SQ_WAVE_PC_HI -#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 -#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL -//SQ_WAVE_INST_DW0 -#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 -#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL -//SQ_WAVE_INST_DW1 -#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 -#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL -//SQ_WAVE_IB_DBG0 -#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 -#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 -#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 -#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 -#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa -#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 -#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18 -#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a -#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b -#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d -#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f -#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L -#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L -#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L -#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L -#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L -#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L -#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L -#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L -#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L -#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L -#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L -//SQ_WAVE_IB_DBG1 -#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0 -#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 -#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 -#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 -#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb -#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12 -#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 -#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L -#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L -#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L -#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L -#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L -#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L -#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L -//SQ_WAVE_FLUSH_IB -#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 -#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP0 -#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP1 -#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP2 -#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP3 -#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP4 -#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP5 -#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP6 -#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP7 -#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP8 -#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP9 -#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP10 -#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP11 -#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP12 -#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP13 -#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP14 -#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP15 -#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_M0 -#define SQ_WAVE_M0__M0__SHIFT 0x0 -#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL -//SQ_WAVE_EXEC_LO -#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 -#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL -//SQ_WAVE_EXEC_HI -#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 -#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL -//SQ_INTERRUPT_WORD_AUTO_CTXID -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L -//SQ_INTERRUPT_WORD_AUTO_HI -#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8 -#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa -#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L -#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L -//SQ_INTERRUPT_WORD_AUTO_LO -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0 -#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1 -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 -#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3 -#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4 -#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5 -#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6 -#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7 -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L -#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L -#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L -#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L -#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L -#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L -#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L -//SQ_INTERRUPT_WORD_CMN_CTXID -#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18 -#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a -#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L -#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L -//SQ_INTERRUPT_WORD_CMN_HI -#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8 -#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa -#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L -#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L -//SQ_INTERRUPT_WORD_WAVE_CTXID -#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0 -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc -#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd -#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12 -#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14 -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18 -#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a -#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L -//SQ_INTERRUPT_WORD_WAVE_HI -#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0 -#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4 -#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8 -#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa -#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL -#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L -#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L -#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L -//SQ_INTERRUPT_WORD_WAVE_LO -#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0 -#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18 -#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19 -#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a -#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e -#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL -#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L -#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L -#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L -#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L - - - - - - - - -// addressBlock: didtind -//DIDT_SQ_CTRL0 -#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 -#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1 -#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 -#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 -#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 -#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 -#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 -#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 -#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 -#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 -#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a -#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x1b -#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L -#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xF8000000L -//DIDT_SQ_CTRL1 -#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 -#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 -#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL -#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L -//DIDT_SQ_CTRL2 -#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 -#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe -#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a -#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f -#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0x0000C000L -#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000L -//DIDT_SQ_STALL_CTRL -#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 -#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 -#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc -#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 -#define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT 0x18 -#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL -#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L -#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L -#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L -#define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK 0xFF000000L -//DIDT_SQ_TUNING_CTRL -#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 -#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe -#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL -#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L -//DIDT_SQ_STALL_AUTO_RELEASE_CTRL -#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 -#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL -//DIDT_SQ_CTRL3 -#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 -#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 -#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2 -#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 -#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe -#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 -#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 -#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 -#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b -#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c -#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL -#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L -#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L -#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L -//DIDT_SQ_STALL_PATTERN_1_2 -#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_SQ_STALL_PATTERN_3_4 -#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_SQ_STALL_PATTERN_5_6 -#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_SQ_STALL_PATTERN_7 -#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_SQ_WEIGHT0_3 -#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 -#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 -#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 -#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 -#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL -#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L -#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L -#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L -//DIDT_SQ_WEIGHT4_7 -#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 -#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 -#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 -#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 -#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL -#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L -#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L -#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L -//DIDT_SQ_WEIGHT8_11 -#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 -#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 -#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 -#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 -#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL -#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L -#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L -#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L -//DIDT_SQ_EDC_CTRL -#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0 -#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 -#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 -#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 -#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 -#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 -#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 -#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 -#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 -#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_SQ_EDC_CTRL__UNUSED_0__SHIFT 0x17 -#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L -#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_SQ_EDC_CTRL__UNUSED_0_MASK 0xFF800000L -//DIDT_SQ_EDC_THRESHOLD -#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 -#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL -//DIDT_SQ_EDC_STALL_PATTERN_1_2 -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_SQ_EDC_STALL_PATTERN_3_4 -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_SQ_EDC_STALL_PATTERN_5_6 -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_SQ_EDC_STALL_PATTERN_7 -#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_SQ_EDC_STATUS -#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 -#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 -#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL -//DIDT_SQ_EDC_STALL_DELAY_1 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x6 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0xc -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x12 -#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x0000003FL -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x00000FC0L -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x0003F000L -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0x00FC0000L -#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L -//DIDT_SQ_EDC_STALL_DELAY_2 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x6 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0xc -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x12 -#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x0000003FL -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x00000FC0L -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x0003F000L -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0x00FC0000L -#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L -//DIDT_SQ_EDC_STALL_DELAY_3 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x6 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT 0xc -#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x0000003FL -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x00000FC0L -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK 0x0003F000L -#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L -//DIDT_SQ_EDC_OVERFLOW -#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 -#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 -#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL -//DIDT_SQ_EDC_ROLLING_POWER_DELTA -#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 -#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL -//DIDT_DB_CTRL0 -#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 -#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1 -#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 -#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 -#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 -#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 -#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 -#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 -#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 -#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 -#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a -#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x1b -#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L -#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xF8000000L -//DIDT_DB_CTRL1 -#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 -#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 -#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL -#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L -//DIDT_DB_CTRL2 -#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 -#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe -#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a -#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f -#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define DIDT_DB_CTRL2__UNUSED_0_MASK 0x0000C000L -#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000L -//DIDT_DB_STALL_CTRL -#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 -#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 -#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc -#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 -#define DIDT_DB_STALL_CTRL__UNUSED_0__SHIFT 0x18 -#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL -#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L -#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L -#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L -#define DIDT_DB_STALL_CTRL__UNUSED_0_MASK 0xFF000000L -//DIDT_DB_TUNING_CTRL -#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 -#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe -#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL -#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L -//DIDT_DB_STALL_AUTO_RELEASE_CTRL -#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 -#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL -//DIDT_DB_CTRL3 -#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 -#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 -#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2 -#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 -#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe -#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 -#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 -#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 -#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b -#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c -#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL -#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L -#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L -#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L -//DIDT_DB_STALL_PATTERN_1_2 -#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_DB_STALL_PATTERN_3_4 -#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_DB_STALL_PATTERN_5_6 -#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_DB_STALL_PATTERN_7 -#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_DB_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_DB_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_DB_WEIGHT0_3 -#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 -#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 -#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 -#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 -#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL -#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L -#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L -#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L -//DIDT_DB_WEIGHT4_7 -#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 -#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 -#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 -#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 -#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL -#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L -#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L -#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L -//DIDT_DB_WEIGHT8_11 -#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 -#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 -#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 -#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 -#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL -#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L -#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L -#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L -//DIDT_DB_EDC_CTRL -#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0 -#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 -#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 -#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 -#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 -#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 -#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 -#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 -#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 -#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_DB_EDC_CTRL__UNUSED_0__SHIFT 0x17 -#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L -#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_DB_EDC_CTRL__UNUSED_0_MASK 0xFF800000L -//DIDT_DB_EDC_THRESHOLD -#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 -#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL -//DIDT_DB_EDC_STALL_PATTERN_1_2 -#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_DB_EDC_STALL_PATTERN_3_4 -#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_DB_EDC_STALL_PATTERN_5_6 -#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_DB_EDC_STALL_PATTERN_7 -#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_DB_EDC_STATUS -#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 -#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 -#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL -//DIDT_DB_EDC_STALL_DELAY_1 -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0 -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x3 -#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x6 -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x00000007L -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x00000038L -#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFC0L -//DIDT_DB_EDC_OVERFLOW -#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 -#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 -#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL -//DIDT_DB_EDC_ROLLING_POWER_DELTA -#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 -#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL -//DIDT_TD_CTRL0 -#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 -#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1 -#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 -#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 -#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 -#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 -#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 -#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 -#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 -#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 -#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a -#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x1b -#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L -#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xF8000000L -//DIDT_TD_CTRL1 -#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 -#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 -#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL -#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L -//DIDT_TD_CTRL2 -#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 -#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe -#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a -#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f -#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define DIDT_TD_CTRL2__UNUSED_0_MASK 0x0000C000L -#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000L -//DIDT_TD_STALL_CTRL -#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 -#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 -#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc -#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 -#define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT 0x18 -#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL -#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L -#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L -#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L -#define DIDT_TD_STALL_CTRL__UNUSED_0_MASK 0xFF000000L -//DIDT_TD_TUNING_CTRL -#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 -#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe -#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL -#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L -//DIDT_TD_STALL_AUTO_RELEASE_CTRL -#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 -#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL -//DIDT_TD_CTRL3 -#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 -#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 -#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2 -#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 -#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe -#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 -#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 -#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 -#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b -#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c -#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL -#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L -#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L -#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L -//DIDT_TD_STALL_PATTERN_1_2 -#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_TD_STALL_PATTERN_3_4 -#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_TD_STALL_PATTERN_5_6 -#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_TD_STALL_PATTERN_7 -#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_TD_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_TD_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_TD_WEIGHT0_3 -#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 -#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 -#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 -#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 -#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL -#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L -#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L -#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L -//DIDT_TD_WEIGHT4_7 -#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 -#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 -#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 -#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 -#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL -#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L -#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L -#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L -//DIDT_TD_WEIGHT8_11 -#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 -#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 -#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 -#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 -#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL -#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L -#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L -#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L -//DIDT_TD_EDC_CTRL -#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0 -#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 -#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 -#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 -#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 -#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 -#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 -#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 -#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 -#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_TD_EDC_CTRL__UNUSED_0__SHIFT 0x17 -#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L -#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_TD_EDC_CTRL__UNUSED_0_MASK 0xFF800000L -//DIDT_TD_EDC_THRESHOLD -#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 -#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL -//DIDT_TD_EDC_STALL_PATTERN_1_2 -#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_TD_EDC_STALL_PATTERN_3_4 -#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_TD_EDC_STALL_PATTERN_5_6 -#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_TD_EDC_STALL_PATTERN_7 -#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_TD_EDC_STATUS -#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 -#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 -#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL -//DIDT_TD_EDC_STALL_DELAY_1 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x6 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0xc -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x12 -#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x0000003FL -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x00000FC0L -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x0003F000L -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0x00FC0000L -#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L -//DIDT_TD_EDC_STALL_DELAY_2 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x6 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0xc -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x12 -#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x0000003FL -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x00000FC0L -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x0003F000L -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0x00FC0000L -#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L -//DIDT_TD_EDC_STALL_DELAY_3 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x6 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT 0xc -#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x0000003FL -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x00000FC0L -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK 0x0003F000L -#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L -//DIDT_TD_EDC_OVERFLOW -#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 -#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 -#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL -//DIDT_TD_EDC_ROLLING_POWER_DELTA -#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 -#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL -//DIDT_TCP_CTRL0 -#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 -#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1 -#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 -#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 -#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 -#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 -#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 -#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 -#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 -#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 -#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a -#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x1b -#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L -#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xF8000000L -//DIDT_TCP_CTRL1 -#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 -#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 -#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL -#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L -//DIDT_TCP_CTRL2 -#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 -#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe -#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a -#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f -#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0x0000C000L -#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000L -//DIDT_TCP_STALL_CTRL -#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 -#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 -#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc -#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 -#define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT 0x18 -#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL -#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L -#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L -#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L -#define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK 0xFF000000L -//DIDT_TCP_TUNING_CTRL -#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 -#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe -#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL -#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L -//DIDT_TCP_STALL_AUTO_RELEASE_CTRL -#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 -#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL -//DIDT_TCP_CTRL3 -#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 -#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 -#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2 -#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 -#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe -#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 -#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 -#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 -#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b -#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c -#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL -#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L -#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L -#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L -//DIDT_TCP_STALL_PATTERN_1_2 -#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_TCP_STALL_PATTERN_3_4 -#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_TCP_STALL_PATTERN_5_6 -#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_TCP_STALL_PATTERN_7 -#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_TCP_WEIGHT0_3 -#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 -#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 -#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 -#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 -#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL -#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L -#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L -#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L -//DIDT_TCP_WEIGHT4_7 -#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 -#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 -#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 -#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 -#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL -#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L -#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L -#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L -//DIDT_TCP_WEIGHT8_11 -#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 -#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 -#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 -#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 -#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL -#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L -#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L -#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L -//DIDT_TCP_EDC_CTRL -#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0 -#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 -#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 -#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 -#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 -#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 -#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 -#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 -#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 -#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_TCP_EDC_CTRL__UNUSED_0__SHIFT 0x17 -#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L -#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_TCP_EDC_CTRL__UNUSED_0_MASK 0xFF800000L -//DIDT_TCP_EDC_THRESHOLD -#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 -#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL -//DIDT_TCP_EDC_STALL_PATTERN_1_2 -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_TCP_EDC_STALL_PATTERN_3_4 -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_TCP_EDC_STALL_PATTERN_5_6 -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_TCP_EDC_STALL_PATTERN_7 -#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_TCP_EDC_STATUS -#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 -#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 -#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL -//DIDT_TCP_EDC_STALL_DELAY_1 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x6 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0xc -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x12 -#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x0000003FL -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x00000FC0L -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x0003F000L -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0x00FC0000L -#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L -//DIDT_TCP_EDC_STALL_DELAY_2 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x6 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0xc -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x12 -#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x0000003FL -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x00000FC0L -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x0003F000L -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0x00FC0000L -#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L -//DIDT_TCP_EDC_STALL_DELAY_3 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x6 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT 0xc -#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x0000003FL -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x00000FC0L -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK 0x0003F000L -#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L -//DIDT_TCP_EDC_OVERFLOW -#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 -#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 -#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL -//DIDT_TCP_EDC_ROLLING_POWER_DELTA -#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 -#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL -//DIDT_DBR_CTRL0 -#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 -#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x1 -#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 -#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 -#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 -#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 -#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 -#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 -#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 -#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 -#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a -#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x1b -#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L -#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xF8000000L -//DIDT_DBR_CTRL1 -#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0 -#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10 -#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0x0000FFFFL -#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xFFFF0000L -//DIDT_DBR_CTRL2 -#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 -#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe -#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a -#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f -#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0x0000C000L -#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000L -//DIDT_DBR_STALL_CTRL -#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 -#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 -#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc -#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 -#define DIDT_DBR_STALL_CTRL__UNUSED_0__SHIFT 0x18 -#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL -#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L -#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L -#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L -#define DIDT_DBR_STALL_CTRL__UNUSED_0_MASK 0xFF000000L -//DIDT_DBR_TUNING_CTRL -#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 -#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe -#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL -#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L -//DIDT_DBR_STALL_AUTO_RELEASE_CTRL -#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 -#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL -//DIDT_DBR_CTRL3 -#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 -#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 -#define DIDT_DBR_CTRL3__THROTTLE_POLICY__SHIFT 0x2 -#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 -#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe -#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 -#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 -#define DIDT_DBR_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 -#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b -#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c -#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_DBR_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL -#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L -#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L -#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_DBR_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L -//DIDT_DBR_STALL_PATTERN_1_2 -#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_DBR_STALL_PATTERN_3_4 -#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_DBR_STALL_PATTERN_5_6 -#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_DBR_STALL_PATTERN_7 -#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_DBR_WEIGHT0_3 -#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0 -#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8 -#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10 -#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18 -#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL -#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L -#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L -#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L -//DIDT_DBR_WEIGHT4_7 -#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0 -#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8 -#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10 -#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18 -#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL -#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L -#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L -#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L -//DIDT_DBR_WEIGHT8_11 -#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0 -#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8 -#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10 -#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18 -#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL -#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L -#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L -#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L -//DIDT_DBR_EDC_CTRL -#define DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT 0x0 -#define DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 -#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 -#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 -#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 -#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 -#define DIDT_DBR_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 -#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 -#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 -#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_DBR_EDC_CTRL__UNUSED_0__SHIFT 0x17 -#define DIDT_DBR_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L -#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_DBR_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_DBR_EDC_CTRL__UNUSED_0_MASK 0xFF800000L -//DIDT_DBR_EDC_THRESHOLD -#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 -#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL -//DIDT_DBR_EDC_STALL_PATTERN_1_2 -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_DBR_EDC_STALL_PATTERN_3_4 -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_DBR_EDC_STALL_PATTERN_5_6 -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_DBR_EDC_STALL_PATTERN_7 -#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_DBR_EDC_STATUS -#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 -#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 -#define DIDT_DBR_EDC_STATUS__UNUSED_0__SHIFT 0x4 -#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL -#define DIDT_DBR_EDC_STATUS__UNUSED_0_MASK 0xFFFFFFF0L -//DIDT_DBR_EDC_STALL_DELAY_1 -#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0__SHIFT 0x0 -#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x1 -#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0_MASK 0x00000001L -#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFFEL -//DIDT_DBR_EDC_OVERFLOW -#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 -#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 -#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL -//DIDT_DBR_EDC_ROLLING_POWER_DELTA -#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 -#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL -//DIDT_SQ_STALL_EVENT_COUNTER -#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 -#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL -//DIDT_DB_STALL_EVENT_COUNTER -#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 -#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL -//DIDT_TD_STALL_EVENT_COUNTER -#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 -#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL -//DIDT_TCP_STALL_EVENT_COUNTER -#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 -#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL -//DIDT_DBR_STALL_EVENT_COUNTER -#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 -#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL - - - - - -#endif -- GitLab From 95c1f7aad241f5a761f7ac236154306b6519c4f8 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Mon, 27 Nov 2017 17:16:06 +0800 Subject: [PATCH 0943/2547] drm/amd/include:cleanup raven1 mmhub header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/raven1/MMHUB folder.Remove unused mmhub_9_1_default.h Signed-off-by: Feifei Xu Acked-by: Christian König Reviewed-by: Junwei Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +- .../MMHUB => mmhub}/mmhub_9_1_offset.h | 0 .../MMHUB => mmhub}/mmhub_9_1_sh_mask.h | 0 .../asic_reg/raven1/MMHUB/mmhub_9_1_default.h | 1028 ----------------- 5 files changed, 4 insertions(+), 1032 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/MMHUB => mmhub}/mmhub_9_1_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/MMHUB => mmhub}/mmhub_9_1_sh_mask.h (100%) delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index ab92cd71d4c7..00eeb8b93303 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -32,8 +32,8 @@ #include "raven1/VCN/vcn_1_0_offset.h" #include "raven1/VCN/vcn_1_0_sh_mask.h" #include "hdp/hdp_4_0_offset.h" -#include "raven1/MMHUB/mmhub_9_1_offset.h" -#include "raven1/MMHUB/mmhub_9_1_sh_mask.h" +#include "mmhub/mmhub_9_1_offset.h" +#include "mmhub/mmhub_9_1_sh_mask.h" static int vcn_v1_0_start(struct amdgpu_device *adev); static int vcn_v1_0_stop(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 278899d72dc5..1e5ca5345504 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -57,8 +57,8 @@ #include "raven1/NBIO/nbio_7_0_offset.h" -#include "raven1/MMHUB/mmhub_9_1_offset.h" -#include "raven1/MMHUB/mmhub_9_1_sh_mask.h" +#include "mmhub/mmhub_9_1_offset.h" +#include "mmhub/mmhub_9_1_sh_mask.h" #include "reg_helper.h" #include "dce/dce_abm.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h deleted file mode 100644 index 392ef7721f53..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h +++ /dev/null @@ -1,1028 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _mmhub_9_1_DEFAULT_HEADER -#define _mmhub_9_1_DEFAULT_HEADER - - -// addressBlock: mmhub_dagbdec -#define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI16_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI17_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI18_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI19_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI20_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI21_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI22_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI23_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI24_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI25_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI26_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI27_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI28_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI29_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI30_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI31_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8 -#define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x0000304f -#define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039 -#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 -#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 -#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3_DEFAULT 0x88888888 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_DEFAULT 0x11111111 -#define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a10408 -#define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 -#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI16_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI17_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI18_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI19_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI20_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI21_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI22_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI23_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI24_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI25_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI26_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI27_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI28_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI29_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI30_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI31_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8 -#define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x0000304f -#define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039 -#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 -#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 -#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3_DEFAULT 0x88888888 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_DEFAULT 0x00000000 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST3_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3_DEFAULT 0x00000000 -#define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x01a10408 -#define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 -#define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x5c626870 -#define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88 -#define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000 -#define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa -#define mmDAGB0_CNTL_MISC2_DEFAULT 0x00000000 -#define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff -#define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000 -#define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x0007ffff -#define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff -#define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmDAGB0_RESERVE0_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE1_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE2_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE3_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE4_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE5_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE6_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE7_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE8_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE9_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE10_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE11_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE12_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE13_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE14_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE15_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE16_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE17_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE18_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE19_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE20_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE21_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE22_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE23_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE24_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE25_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE26_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE27_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE28_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE29_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE30_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE31_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE32_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE33_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE34_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE35_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE36_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE37_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE38_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE39_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE40_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE41_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE42_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE43_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE44_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE45_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE46_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE47_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE48_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE49_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE50_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE51_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE52_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE53_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE54_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE55_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE56_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE57_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE58_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE59_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE60_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE61_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE62_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE63_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE64_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE65_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE66_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE67_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE68_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE69_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE70_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE71_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE72_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE73_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE74_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE75_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE76_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE77_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE78_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE79_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE80_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE81_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE82_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE83_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE84_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE85_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE86_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE87_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE88_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE89_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE90_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE91_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE92_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE93_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE94_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE95_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE96_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE97_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE98_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE99_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE100_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE101_DEFAULT 0x00000000 - - -// addressBlock: mmhub_ea_mmeadec -#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 -#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 -#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 -#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 -#define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 -#define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 -#define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x00000924 -#define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x00000924 -#define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 -#define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 -#define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000 -#define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef -#define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 -#define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 -#define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 -#define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 -#define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03 -#define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 -#define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 -#define mmMMEA0_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmMMEA0_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00102040 -#define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff -#define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 -#define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000 -#define mmMMEA0_SDP_CREDITS_DEFAULT 0x000100bf -#define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000000f -#define mmMMEA0_MISC_DEFAULT 0x00180130 -#define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmMMEA0_EDC_CNT_DEFAULT 0x00000000 -#define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000 -#define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmMMEA0_EDC_MODE_DEFAULT 0x00000000 -#define mmMMEA0_ERR_STATUS_DEFAULT 0x00000000 -#define mmMMEA0_MISC2_DEFAULT 0x00000000 -#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 -#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 -#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 -#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 -#define mmMMEA1_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 -#define mmMMEA1_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 -#define mmMMEA1_DRAM_RD_LAZY_DEFAULT 0x00000924 -#define mmMMEA1_DRAM_WR_LAZY_DEFAULT 0x00000924 -#define mmMMEA1_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 -#define mmMMEA1_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 -#define mmMMEA1_DRAM_PAGE_BURST_DEFAULT 0x20002000 -#define mmMMEA1_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA1_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA1_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA1_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA1_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA1_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA1_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmMMEA1_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA1_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef -#define mmMMEA1_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmMMEA1_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 -#define mmMMEA1_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 -#define mmMMEA1_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 -#define mmMMEA1_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 -#define mmMMEA1_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmMMEA1_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmMMEA1_IO_GROUP_BURST_DEFAULT 0x1f031f03 -#define mmMMEA1_IO_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA1_IO_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA1_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA1_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA1_IO_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA1_IO_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA1_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 -#define mmMMEA1_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 -#define mmMMEA1_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmMMEA1_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA1_SDP_ARB_DRAM_DEFAULT 0x00102040 -#define mmMMEA1_SDP_ARB_FINAL_DEFAULT 0x00007fff -#define mmMMEA1_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 -#define mmMMEA1_SDP_IO_PRIORITY_DEFAULT 0x00000000 -#define mmMMEA1_SDP_CREDITS_DEFAULT 0x000100bf -#define mmMMEA1_SDP_TAG_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA1_SDP_TAG_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA1_SDP_VCC_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA1_SDP_VCC_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA1_SDP_VCD_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA1_SDP_VCD_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA1_SDP_REQ_CNTL_DEFAULT 0x0000000f -#define mmMMEA1_MISC_DEFAULT 0x00180130 -#define mmMMEA1_LATENCY_SAMPLING_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmMMEA1_EDC_CNT_DEFAULT 0x00000000 -#define mmMMEA1_EDC_CNT2_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTL_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTLA_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTLB_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTL2_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTL2A_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTL2B_DEFAULT 0x00000000 -#define mmMMEA1_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmMMEA1_EDC_MODE_DEFAULT 0x00000000 -#define mmMMEA1_ERR_STATUS_DEFAULT 0x00000000 -#define mmMMEA1_MISC2_DEFAULT 0x00000000 - - -// addressBlock: mmhub_pctldec -#define mmPCTL_MISC_DEFAULT 0x00000889 -#define mmPCTL_MMHUB_DEEPSLEEP_DEFAULT 0x00000000 -#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 -#define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 -#define mmPCTL_PG_DAGB_DEFAULT 0x00000000 -#define mmPCTL0_RENG_RAM_INDEX_DEFAULT 0x00000000 -#define mmPCTL0_RENG_RAM_DATA_DEFAULT 0x00000000 -#define mmPCTL0_RENG_EXECUTE_DEFAULT 0x00000000 -#define mmPCTL0_MISC_DEFAULT 0x00001000 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 -#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff -#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff -#define mmPCTL1_RENG_RAM_INDEX_DEFAULT 0x00000000 -#define mmPCTL1_RENG_RAM_DATA_DEFAULT 0x00000000 -#define mmPCTL1_RENG_EXECUTE_DEFAULT 0x00000000 -#define mmPCTL1_MISC_DEFAULT 0x00000800 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x061f05a0 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08590800 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 -#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff -#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff -#define mmPCTL2_RENG_RAM_INDEX_DEFAULT 0x00000000 -#define mmPCTL2_RENG_RAM_DATA_DEFAULT 0x00000000 -#define mmPCTL2_RENG_EXECUTE_DEFAULT 0x00000000 -#define mmPCTL2_MISC_DEFAULT 0x00000800 -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x069f0620 -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08b3085a -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 -#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff -#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff - - -// addressBlock: mmhub_l1tlb_vml1dec -#define mmMC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 - - -// addressBlock: mmhub_l1tlb_vml1pldec -#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - - -// addressBlock: mmhub_l1tlb_vml1prdec -#define mmMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: mmhub_l1tlb_vmtlspfdec -#define mmVM_L2_SAW_CNTL_DEFAULT 0x0c0b8602 -#define mmVM_L2_SAW_CNTL2_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CNTL3_DEFAULT 0x80100004 -#define mmVM_L2_SAW_CNTL4_DEFAULT 0x00000001 -#define mmVM_L2_SAW_CONTEXT0_CNTL_DEFAULT 0x00fffed8 -#define mmVM_L2_SAW_CONTEXT0_CNTL2_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXTS_DISABLE_DEFAULT 0x00000000 -#define mmVM_L2_SAW_PIPES_BUSY_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_atcl2dec -#define mmATC_L2_CNTL_DEFAULT 0x000001c9 -#define mmATC_L2_CNTL2_DEFAULT 0x00000100 -#define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000 -#define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000 -#define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000 -#define mmATC_L2_CNTL3_DEFAULT 0x000001f8 -#define mmATC_L2_STATUS_DEFAULT 0x00000000 -#define mmATC_L2_STATUS2_DEFAULT 0x00000000 -#define mmATC_L2_MISC_CG_DEFAULT 0x00000200 -#define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 -#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: mmhub_utcl2_vml2pfdec -#define mmVM_L2_CNTL_DEFAULT 0x00080602 -#define mmVM_L2_CNTL2_DEFAULT 0x00000000 -#define mmVM_L2_CNTL3_DEFAULT 0x80100007 -#define mmVM_L2_STATUS_DEFAULT 0x00000000 -#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc -#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff -#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CNTL4_DEFAULT 0x000000c1 -#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 -#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 -#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 -#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 -#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: mmhub_utcl2_vml2vcdec -#define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_vml2pldec -#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - - -// addressBlock: mmhub_utcl2_vml2prdec -#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_vmsharedhvdec -#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 -#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 -#define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 -#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 -#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 -#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: mmhub_utcl2_vmsharedpfdec -#define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000 -#define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 -#define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 -#define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008 -#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 -#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 -#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 -#define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmMC_VM_STEERING_DEFAULT 0x00000001 -#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmMC_MEM_POWER_LS_DEFAULT 0x00000208 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 -#define mmMC_VM_APT_CNTL_DEFAULT 0x00000000 -#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 -#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff -#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_vmsharedvcdec -#define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 -#define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 -#define mmMC_VM_AGP_TOP_DEFAULT 0x00000000 -#define mmMC_VM_AGP_BOT_DEFAULT 0x00000000 -#define mmMC_VM_AGP_BASE_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 - - -// addressBlock: mmhub_utcl2_atcl2pfcntrdec -#define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_atcl2pfcntldec -#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - -#endif -- GitLab From a146391bbbc546a0dda0eac60fdf32d6076817b5 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Mon, 27 Nov 2017 17:20:55 +0800 Subject: [PATCH 0944/2547] drm/amd/include:cleanup raven1 mp header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/raven1/MP folder. Signed-off-by: Feifei Xu Acked-by: Christian König Reviewed-by: Junwei Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 2 +- .../include/asic_reg/{raven1/MP => mp}/mp_10_0_default.h | 0 .../amd/include/asic_reg/{raven1/MP => mp}/mp_10_0_offset.h | 0 .../include/asic_reg/{raven1/MP => mp}/mp_10_0_sh_mask.h | 0 drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | 6 +++--- 5 files changed, 4 insertions(+), 4 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/MP => mp}/mp_10_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/MP => mp}/mp_10_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/MP => mp}/mp_10_0_sh_mask.h (100%) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 0cf36acbf51a..78fe3f2917a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -31,7 +31,7 @@ #include "psp_v10_0.h" #include "soc15ip.h" -#include "raven1/MP/mp_10_0_offset.h" +#include "mp/mp_10_0_offset.h" #include "gc/gc_9_1_offset.h" #include "sdma0/sdma0_4_1_offset.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_default.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h rename to drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h index 9a0149370d26..94961c7804d3 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h @@ -25,9 +25,9 @@ #define RAVEN_INC_H -#include "asic_reg/raven1/MP/mp_10_0_default.h" -#include "asic_reg/raven1/MP/mp_10_0_offset.h" -#include "asic_reg/raven1/MP/mp_10_0_sh_mask.h" +#include "asic_reg/mp/mp_10_0_default.h" +#include "asic_reg/mp/mp_10_0_offset.h" +#include "asic_reg/mp/mp_10_0_sh_mask.h" #include "asic_reg/raven1/NBIO/nbio_7_0_default.h" #include "asic_reg/raven1/NBIO/nbio_7_0_offset.h" -- GitLab From 51199920a288b7a75eb1edf00c6b4834ec64b6ca Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Mon, 27 Nov 2017 17:29:29 +0800 Subject: [PATCH 0945/2547] drm/amd/include:cleanup raven1 nbio header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/raven1/NBIO folder. Signed-off-by: Feifei Xu Acked-by: Christian König Reviewed-by: Junwei Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 6 +++--- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- .../asic_reg/{raven1/NBIO => nbio}/nbio_7_0_default.h | 0 .../asic_reg/{raven1/NBIO => nbio}/nbio_7_0_offset.h | 0 .../asic_reg/{raven1/NBIO => nbio}/nbio_7_0_sh_mask.h | 0 drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | 6 +++--- 6 files changed, 7 insertions(+), 7 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/NBIO => nbio}/nbio_7_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/NBIO => nbio}/nbio_7_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/NBIO => nbio}/nbio_7_0_sh_mask.h (100%) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index 8ddc44b503e9..1fb77174e02c 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -25,9 +25,9 @@ #include "nbio_v7_0.h" #include "soc15ip.h" -#include "raven1/NBIO/nbio_7_0_default.h" -#include "raven1/NBIO/nbio_7_0_offset.h" -#include "raven1/NBIO/nbio_7_0_sh_mask.h" +#include "nbio/nbio_7_0_default.h" +#include "nbio/nbio_7_0_offset.h" +#include "nbio/nbio_7_0_sh_mask.h" #include "vega10_enum.h" #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 1e5ca5345504..10cce51d31d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -55,7 +55,7 @@ #include "dcn/dcn_1_0_offset.h" #include "dcn/dcn_1_0_sh_mask.h" -#include "raven1/NBIO/nbio_7_0_offset.h" +#include "nbio/nbio_7_0_offset.h" #include "mmhub/mmhub_9_1_offset.h" #include "mmhub/mmhub_9_1_sh_mask.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_default.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h rename to drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h index 94961c7804d3..5fb38f611554 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h @@ -29,9 +29,9 @@ #include "asic_reg/mp/mp_10_0_offset.h" #include "asic_reg/mp/mp_10_0_sh_mask.h" -#include "asic_reg/raven1/NBIO/nbio_7_0_default.h" -#include "asic_reg/raven1/NBIO/nbio_7_0_offset.h" -#include "asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h" +#include "asic_reg/nbio/nbio_7_0_default.h" +#include "asic_reg/nbio/nbio_7_0_offset.h" +#include "asic_reg/nbio/nbio_7_0_sh_mask.h" #include "asic_reg/raven1/THM/thm_10_0_default.h" #include "asic_reg/raven1/THM/thm_10_0_offset.h" -- GitLab From 6b5b5fea3b767a269c303166fc41eba3dbc1154d Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Mon, 27 Nov 2017 17:32:44 +0800 Subject: [PATCH 0946/2547] drm/amd/include:cleanup raven1 thm header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/raven1/THM folder. Signed-off-by: Feifei Xu Acked-by: Christian König Reviewed-by: Junwei Zhang Signed-off-by: Alex Deucher --- .../include/asic_reg/{raven1/THM => thm}/thm_10_0_default.h | 0 .../include/asic_reg/{raven1/THM => thm}/thm_10_0_offset.h | 0 .../include/asic_reg/{raven1/THM => thm}/thm_10_0_sh_mask.h | 0 drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | 6 +++--- 4 files changed, 3 insertions(+), 3 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/THM => thm}/thm_10_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/THM => thm}/thm_10_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/THM => thm}/thm_10_0_sh_mask.h (100%) diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h index 5fb38f611554..ae59a3fdea8a 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h @@ -33,9 +33,9 @@ #include "asic_reg/nbio/nbio_7_0_offset.h" #include "asic_reg/nbio/nbio_7_0_sh_mask.h" -#include "asic_reg/raven1/THM/thm_10_0_default.h" -#include "asic_reg/raven1/THM/thm_10_0_offset.h" -#include "asic_reg/raven1/THM/thm_10_0_sh_mask.h" +#include "asic_reg/thm/thm_10_0_default.h" +#include "asic_reg/thm/thm_10_0_offset.h" +#include "asic_reg/thm/thm_10_0_sh_mask.h" #define ixDDI_PHY_GEN_STATUS 0x3FCE8 -- GitLab From b1ebd7c0cd0e4fa039e663741e6090858e80cd1d Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Mon, 27 Nov 2017 17:57:30 +0800 Subject: [PATCH 0947/2547] drm/amd/include:cleanup raven1 vcn header files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup asic_reg/raven1/VCN folder. Remove unused vcn_1_0_default.h. Signed-off-by: Feifei Xu Acked-by: Christian König Reviewed-by: Junwei Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 +- .../asic_reg/raven1/VCN/vcn_1_0_default.h | 202 ------------------ .../{raven1/VCN => vcn}/vcn_1_0_offset.h | 0 .../{raven1/VCN => vcn}/vcn_1_0_sh_mask.h | 0 5 files changed, 3 insertions(+), 205 deletions(-) delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h rename drivers/gpu/drm/amd/include/asic_reg/{raven1/VCN => vcn}/vcn_1_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/VCN => vcn}/vcn_1_0_sh_mask.h (100%) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index c22c73f458bc..d7ba048c2f80 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -36,7 +36,7 @@ #include "soc15_common.h" #include "soc15ip.h" -#include "raven1/VCN/vcn_1_0_offset.h" +#include "vcn/vcn_1_0_offset.h" /* 1 second timeout */ #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 00eeb8b93303..e4673f792545 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -29,8 +29,8 @@ #include "soc15_common.h" #include "soc15ip.h" -#include "raven1/VCN/vcn_1_0_offset.h" -#include "raven1/VCN/vcn_1_0_sh_mask.h" +#include "vcn/vcn_1_0_offset.h" +#include "vcn/vcn_1_0_sh_mask.h" #include "hdp/hdp_4_0_offset.h" #include "mmhub/mmhub_9_1_offset.h" #include "mmhub/mmhub_9_1_sh_mask.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h deleted file mode 100644 index 5793a10e3dc2..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _vcn_1_0_DEFAULT_HEADER -#define _vcn_1_0_DEFAULT_HEADER - - -// addressBlock: uvd_uvd_pg_dec -#define mmUVD_PGFSM_CONFIG_DEFAULT 0x00000000 -#define mmUVD_PGFSM_STATUS_DEFAULT 0x002aaaaa -#define mmUVD_POWER_STATUS_DEFAULT 0x00000801 -#define mmCC_UVD_HARVESTING_DEFAULT 0x00000000 -#define mmUVD_SCRATCH1_DEFAULT 0x00000000 -#define mmUVD_SCRATCH2_DEFAULT 0x00000000 -#define mmUVD_SCRATCH3_DEFAULT 0x00000000 -#define mmUVD_SCRATCH4_DEFAULT 0x00000000 -#define mmUVD_SCRATCH5_DEFAULT 0x00000000 -#define mmUVD_SCRATCH6_DEFAULT 0x00000000 -#define mmUVD_SCRATCH7_DEFAULT 0x00000000 -#define mmUVD_SCRATCH8_DEFAULT 0x00000000 -#define mmUVD_SCRATCH9_DEFAULT 0x00000000 -#define mmUVD_SCRATCH10_DEFAULT 0x00000000 -#define mmUVD_SCRATCH11_DEFAULT 0x00000000 -#define mmUVD_SCRATCH12_DEFAULT 0x00000000 -#define mmUVD_SCRATCH13_DEFAULT 0x00000000 -#define mmUVD_SCRATCH14_DEFAULT 0x00000000 -#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_DPG_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000 - - -// addressBlock: uvd_uvdgendec -#define mmUVD_LCM_CGC_CNTRL_DEFAULT 0xa0f00000 - - -// addressBlock: uvd_uvdnpdec -#define mmUVD_JPEG_CNTL_DEFAULT 0x00000004 -#define mmUVD_JPEG_RB_BASE_DEFAULT 0x00000000 -#define mmUVD_JPEG_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_JPEG_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_JPEG_RB_SIZE_DEFAULT 0x00000000 -#define mmUVD_JPEG_UV_TILING_CTRL_DEFAULT 0x02104800 -#define mmUVD_JPEG_TILING_CTRL_DEFAULT 0x02104800 -#define mmUVD_JPEG_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_JPEG_GPCOM_CMD_DEFAULT 0x00000000 -#define mmUVD_JPEG_GPCOM_DATA0_DEFAULT 0x00000000 -#define mmUVD_JPEG_GPCOM_DATA1_DEFAULT 0x00000000 -#define mmUVD_JPEG_JRB_BASE_LO_DEFAULT 0x00000000 -#define mmUVD_JPEG_JRB_BASE_HI_DEFAULT 0x00000000 -#define mmUVD_JPEG_JRB_SIZE_DEFAULT 0x00000000 -#define mmUVD_JPEG_JRB_RPTR_DEFAULT 0x00000000 -#define mmUVD_JPEG_JRB_WPTR_DEFAULT 0x00000000 -#define mmUVD_JPEG_UV_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_SEMA_ADDR_LOW_DEFAULT 0x00000000 -#define mmUVD_SEMA_ADDR_HIGH_DEFAULT 0x00000000 -#define mmUVD_SEMA_CMD_DEFAULT 0x00000080 -#define mmUVD_GPCOM_VCPU_CMD_DEFAULT 0x00000000 -#define mmUVD_GPCOM_VCPU_DATA0_DEFAULT 0x00000000 -#define mmUVD_GPCOM_VCPU_DATA1_DEFAULT 0x00000000 -#define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_UDEC_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_UDEC_DB_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_UDEC_DBW_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_SUVD_CGC_GATE_DEFAULT 0x00000000 -#define mmUVD_SUVD_CGC_STATUS_DEFAULT 0x00000000 -#define mmUVD_SUVD_CGC_CTRL_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_NO_OP_DEFAULT 0x00000000 -#define mmUVD_JPEG_CNTL2_DEFAULT 0x00000000 -#define mmUVD_VERSION_DEFAULT 0x00010000 -#define mmUVD_GP_SCRATCH8_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH9_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH10_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH11_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH12_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH13_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH14_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH15_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH16_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH17_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH18_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH19_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH20_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH21_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH22_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH23_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO2_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI2_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE2_DEFAULT 0x00000000 -#define mmUVD_RB_RPTR2_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR2_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE_DEFAULT 0x00000000 -#define mmUVD_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR4_DEFAULT 0x00000000 -#define mmUVD_JRBC_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000 - - -// addressBlock: uvd_uvddec -#define mmUVD_SEMA_CNTL_DEFAULT 0x00000003 -#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_JRBC_IB_VMID_DEFAULT 0x00000000 -#define mmUVD_JRBC_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_JRBC_RB_CNTL_DEFAULT 0x00000100 -#define mmUVD_JRBC_IB_SIZE_DEFAULT 0x00000000 -#define mmUVD_JRBC_LMI_SWAP_CNTL_DEFAULT 0x00000000 -#define mmUVD_JRBC_SOFT_RESET_DEFAULT 0x00000000 -#define mmUVD_JRBC_STATUS_DEFAULT 0x00000003 -#define mmUVD_RB_RPTR3_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR3_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO3_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI3_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE3_DEFAULT 0x00000000 -#define mmJPEG_CGC_GATE_DEFAULT 0x00300000 -#define mmUVD_CTX_INDEX_DEFAULT 0x00000000 -#define mmUVD_CTX_DATA_DEFAULT 0x00000000 -#define mmUVD_CGC_GATE_DEFAULT 0x000fffff -#define mmUVD_CGC_STATUS_DEFAULT 0x00000000 -#define mmUVD_CGC_CTRL_DEFAULT 0x1fff018d -#define mmUVD_GP_SCRATCH0_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH1_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH2_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH3_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH4_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH5_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH6_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH7_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE_VMID_DEFAULT 0x00000000 -#define mmUVD_LMI_CTRL2_DEFAULT 0x003e0000 -#define mmUVD_MASTINT_EN_DEFAULT 0x00000000 -#define mmJPEG_CGC_CTRL_DEFAULT 0x0000018d -#define mmUVD_LMI_CTRL_DEFAULT 0x00104340 -#define mmUVD_LMI_STATUS_DEFAULT 0x003fff7f -#define mmUVD_LMI_VM_CTRL_DEFAULT 0x00000000 -#define mmUVD_LMI_SWAP_CNTL_DEFAULT 0x00000000 -#define mmUVD_MPC_SET_MUXA0_DEFAULT 0x00002040 -#define mmUVD_MPC_SET_MUXA1_DEFAULT 0x00000000 -#define mmUVD_MPC_SET_MUXB0_DEFAULT 0x00002040 -#define mmUVD_MPC_SET_MUXB1_DEFAULT 0x00000000 -#define mmUVD_MPC_SET_MUX_DEFAULT 0x00000088 -#define mmUVD_MPC_SET_ALU_DEFAULT 0x00000000 -#define mmUVD_GPCOM_SYS_CMD_DEFAULT 0x00000000 -#define mmUVD_GPCOM_SYS_DATA0_DEFAULT 0x00000000 -#define mmUVD_GPCOM_SYS_DATA1_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_SIZE0_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_SIZE1_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_SIZE2_DEFAULT 0x00000000 -#define mmUVD_VCPU_CNTL_DEFAULT 0x0ff20000 -#define mmUVD_SOFT_RESET_DEFAULT 0x00000008 -#define mmUVD_LMI_RBC_IB_VMID_DEFAULT 0x00000000 -#define mmUVD_RBC_IB_SIZE_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_WPTR_CNTL_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_CNTL_DEFAULT 0x01000101 -#define mmUVD_RBC_RB_RPTR_ADDR_DEFAULT 0x00000000 -#define mmUVD_STATUS_DEFAULT 0x00000000 -#define mmUVD_SEMA_TIMEOUT_STATUS_DEFAULT 0x00000000 -#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000 -#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_DEFAULT 0x02000000 -#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000 -#define mmUVD_CONTEXT_ID_DEFAULT 0x00000000 -#define mmUVD_CONTEXT_ID2_DEFAULT 0x00000000 -#define mmUVD_RBC_WPTR_POLL_CNTL_DEFAULT 0x00400100 -#define mmUVD_RBC_WPTR_POLL_ADDR_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO4_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI4_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE4_DEFAULT 0x00000000 -#define mmUVD_RB_RPTR4_DEFAULT 0x00000000 - - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h -- GitLab From 1e88ad0ae390da86574d6336a9fb26a32cc0e473 Mon Sep 17 00:00:00 2001 From: Shirish S Date: Fri, 1 Dec 2017 01:27:04 -0500 Subject: [PATCH 0948/2547] drm/amd/display: remove usage of legacy_cursor_update Currently the atomic check code uses legacy_cursor_update to differnetiate if the cursor plane is being requested by the user, which is not required as we shall be updating plane only if modeset is requested/required. Have tested cursor plane and underlay get updated seamlessly, without any lag or frame drops. Signed-off-by: Shirish S Reviewed-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 43 ++++++------------- 1 file changed, 13 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 82226a337bde..9aff7eea4375 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4739,8 +4739,6 @@ static int dm_update_planes_state(struct dc *dc, static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) { - int i; - int ret; struct amdgpu_device *adev = dev->dev_private; struct dc *dc = adev->dm.dc; struct dm_atomic_state *dm_state = to_dm_atomic_state(state); @@ -4748,6 +4746,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_connector_state *old_con_state, *new_con_state; struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; + int ret, i; /* * This bool will be set for true for any modeset/reset @@ -4759,37 +4758,21 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail; - /* - * legacy_cursor_update should be made false for SoC's having - * a dedicated hardware plane for cursor in amdgpu_dm_atomic_commit(), - * otherwise for software cursor plane, - * we should not add it to list of affected planes. - */ - if (state->legacy_cursor_update) { - for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { - if (new_crtc_state->color_mgmt_changed) { - ret = drm_atomic_add_affected_planes(state, crtc); - if (ret) - goto fail; - } - } - } else { - for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { - if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && - !new_crtc_state->color_mgmt_changed) - continue; + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && + !new_crtc_state->color_mgmt_changed) + continue; - if (!new_crtc_state->enable) - continue; + if (!new_crtc_state->enable) + continue; - ret = drm_atomic_add_affected_connectors(state, crtc); - if (ret) - return ret; + ret = drm_atomic_add_affected_connectors(state, crtc); + if (ret) + return ret; - ret = drm_atomic_add_affected_planes(state, crtc); - if (ret) - goto fail; - } + ret = drm_atomic_add_affected_planes(state, crtc); + if (ret) + goto fail; } dm_state->context = dc_create_state(); -- GitLab From cf7d1bdf2b4338a03e5ba1142c0014b000597a60 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Tue, 28 Nov 2017 11:34:16 -0800 Subject: [PATCH 0949/2547] drm/ttm: Use a static string instead of an array of char * MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make the object a bit smaller by using a simple string instead of a format string and array of char *. $ size drivers/gpu/drm/ttm/ttm_page_alloc_dma.o* text data bss dec hex filename 8820 216 4136 13172 3374 drivers/gpu/drm/ttm/ttm_page_alloc_dma.o.defconfig.new 8910 216 4136 13262 33ce drivers/gpu/drm/ttm/ttm_page_alloc_dma.o.defconfig.old 25383 5044 4384 34811 87fb drivers/gpu/drm/ttm/ttm_page_alloc_dma.o.allyesconfig.new 25797 5428 4384 35609 8b19 drivers/gpu/drm/ttm/ttm_page_alloc_dma.o.allyesconfig.old Miscellanea: o The h array had more entries than were emitted, all are now removed Reviewed-by: Christian König Signed-off-by: Joe Perches Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c index 6b2627fe9bc1..bda00b2ab51c 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c @@ -1244,15 +1244,12 @@ int ttm_dma_page_alloc_debugfs(struct seq_file *m, void *data) { struct device_pools *p; struct dma_pool *pool = NULL; - char *h[] = {"pool", "refills", "pages freed", "inuse", "available", - "name", "virt", "busaddr"}; if (!_manager) { seq_printf(m, "No pool allocator running.\n"); return 0; } - seq_printf(m, "%13s %12s %13s %8s %8s %8s\n", - h[0], h[1], h[2], h[3], h[4], h[5]); + seq_printf(m, " pool refills pages freed inuse available name\n"); mutex_lock(&_manager->lock); list_for_each_entry(p, &_manager->pools, pools) { struct device *dev = p->dev; -- GitLab From d6f068a53b5a7d719e7c66554356a2af6da9cda7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Tue, 28 Nov 2017 12:06:13 +0100 Subject: [PATCH 0950/2547] drm/amd/display: Add dm_logger_append_va API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Same as dm_logger_append, except it takes a va_list instead of a variable number of arguments. dm_logger_append is now a minimal wrapper around dm_logger_append_va. Reviewed-by: Alex Deucher Signed-off-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/basics/logger.c | 17 ++++++++++++----- .../drm/amd/display/include/logger_interface.h | 5 +++++ 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c index 2ff5b467603d..180a9d69d351 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c @@ -311,6 +311,18 @@ void dm_logger_append( struct log_entry *entry, const char *msg, ...) +{ + va_list args; + + va_start(args, msg); + dm_logger_append_va(entry, msg, args); + va_end(args); +} + +void dm_logger_append_va( + struct log_entry *entry, + const char *msg, + va_list args) { struct dal_logger *logger; @@ -325,11 +337,8 @@ void dm_logger_append( dal_logger_should_log(logger, entry->type)) { uint32_t size; - va_list args; char buffer[LOG_MAX_LINE_SIZE]; - va_start(args, msg); - size = dm_log_to_buffer( buffer, LOG_MAX_LINE_SIZE, msg, args); @@ -338,8 +347,6 @@ void dm_logger_append( } else { append_entry(entry, "LOG_ERROR, line too long\n", 27); } - - va_end(args); } } diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 8e1fe70097be..28dee960d509 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -57,6 +57,11 @@ void dm_logger_append( const char *msg, ...); +void dm_logger_append_va( + struct log_entry *entry, + const char *msg, + va_list args); + void dm_logger_open( struct dal_logger *logger, struct log_entry *entry, -- GitLab From 38636603d8768eba027344dfb6b6dcdc0157081e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Tue, 28 Nov 2017 12:06:13 +0100 Subject: [PATCH 0951/2547] drm/amd/display: Don't call dm_log_to_buffer directly in dc_conn_log MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dm_log_to_buffer logs unconditionally, so calling it directly resulted in the main message being logged even when the event type isn't enabled in the event mask. To fix this, use the new dm_logger_append_va API. Fixes spurious messages like [drm] {1920x1200, 2080x1235@154000Khz} in dmesg when a mode is set. v2: * Use new dm_logger_append_va API, fixes incorrect va_list usage in v1 * Just use and decrease entry.buf_offset to get rid of the trailing newline Reviewed-by: Alex Deucher Signed-off-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/basics/log_helpers.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c index 6e43168fbdd6..854678a0c54b 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c @@ -83,15 +83,11 @@ void dc_conn_log(struct dc_context *ctx, link->link_index); va_start(args, msg); - entry.buf_offset += dm_log_to_buffer( - &entry.buf[entry.buf_offset], - LOG_MAX_LINE_SIZE - entry.buf_offset, - msg, args); + dm_logger_append_va(&entry, msg, args); - if (entry.buf[strlen(entry.buf) - 1] == '\n') { - entry.buf[strlen(entry.buf) - 1] = '\0'; + if (entry.buf_offset > 0 && + entry.buf[entry.buf_offset - 1] == '\n') entry.buf_offset--; - } if (hex_data) for (i = 0; i < hex_data_count; i++) -- GitLab From 722570435bb066c17ff42bb40fb0bbe581b2eba5 Mon Sep 17 00:00:00 2001 From: Frank Min Date: Mon, 6 Nov 2017 15:34:55 +0800 Subject: [PATCH 0952/2547] drm/amdgpu: correct vce4.0 fw config for SRIOV (V2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1. program vce 4.0 fw with 48 bit address 2. correct vce 4.0 fw stack and date offset Acked-by: Christian König Signed-off-by: Frank Min Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 38 ++++++++++++++++++--------- 1 file changed, 25 insertions(+), 13 deletions(-) mode change 100644 => 100755 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c old mode 100644 new mode 100755 index d06bafe28c2e..f2f713650074 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -243,37 +243,49 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev) MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0); if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), - adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), - adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_64BIT_BAR0), + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) & 0xff); } else { - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), adev->vce.gpu_addr >> 8); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_64BIT_BAR0), + (adev->vce.gpu_addr >> 40) & 0xff); + } + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), adev->vce.gpu_addr >> 8); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), + (adev->vce.gpu_addr >> 40) & 0xff); + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), adev->vce.gpu_addr >> 8); - } + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), + (adev->vce.gpu_addr >> 40) & 0xff); offset = AMDGPU_VCE_FIRMWARE_OFFSET; size = VCE_V4_0_FW_SIZE; MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), - offset & 0x7FFFFFFF); + offset & ~0x0f000000); MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); - offset += size; + offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? offset + size : 0; size = VCE_V4_0_STACK_SIZE; MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), - offset & 0x7FFFFFFF); + (offset & ~0x0f000000) | (1 << 24)); MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size); offset += size; size = VCE_V4_0_DATA_SIZE; MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), - offset & 0x7FFFFFFF); + (offset & ~0x0f000000) | (2 << 24)); MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size); MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0); -- GitLab From 507831473f126e389039611b309bb5718e38c043 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 27 Nov 2017 14:01:51 +0100 Subject: [PATCH 0953/2547] drm/amdgpu: fix VM PD addr shift MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The block size only affects the leave nodes, everything else is fixed. Signed-off-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 28 +++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 122379dfc7d8..f1e541e9b514 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -138,6 +138,24 @@ struct amdgpu_prt_cb { struct dma_fence_cb cb; }; +/** + * amdgpu_vm_level_shift - return the addr shift for each level + * + * @adev: amdgpu_device pointer + * + * Returns the number of bits the pfn needs to be right shifted for a level. + */ +static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, + unsigned level) +{ + if (level != adev->vm_manager.num_level) + return 9 * (adev->vm_manager.num_level - level - 1) + + adev->vm_manager.block_size; + else + /* For the page tables on the leaves */ + return 0; +} + /** * amdgpu_vm_num_entries - return the number of entries in a PD/PT * @@ -288,8 +306,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, uint64_t saddr, uint64_t eaddr, unsigned level) { - unsigned shift = (adev->vm_manager.num_level - level) * - adev->vm_manager.block_size; + unsigned shift = amdgpu_vm_level_shift(adev, level); unsigned pt_idx, from, to; int r; u64 flags; @@ -1302,18 +1319,19 @@ void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, struct amdgpu_vm_pt **entry, struct amdgpu_vm_pt **parent) { - unsigned idx, level = p->adev->vm_manager.num_level; + unsigned level = 0; *parent = NULL; *entry = &p->vm->root; while ((*entry)->entries) { - idx = addr >> (p->adev->vm_manager.block_size * level--); + unsigned idx = addr >> amdgpu_vm_level_shift(p->adev, level++); + idx %= amdgpu_bo_size((*entry)->base.bo) / 8; *parent = *entry; *entry = &(*entry)->entries[idx]; } - if (level) + if (level != p->adev->vm_manager.num_level) *entry = NULL; } -- GitLab From 0410c5e51443ef8ca9ef6db647b07f2f9a46c09a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 20 Nov 2017 14:29:01 +0100 Subject: [PATCH 0954/2547] drm/amdgpu: fix amdgpu_vm_num_entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The block size only affects the leave nodes, everything else is fixed. Signed-off-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index f1e541e9b514..771995093cac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -166,17 +166,17 @@ static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, unsigned level) { + unsigned shift = amdgpu_vm_level_shift(adev, 0); + if (level == 0) /* For the root directory */ - return adev->vm_manager.max_pfn >> - (adev->vm_manager.block_size * - adev->vm_manager.num_level); - else if (level == adev->vm_manager.num_level) + return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift; + else if (level != adev->vm_manager.num_level) + /* Everything in between */ + return 512; + else /* For the page tables on the leaves */ return AMDGPU_VM_PTE_COUNT(adev); - else - /* Everything in between */ - return 1 << adev->vm_manager.block_size; } /** -- GitLab From b38f41ebb8d0395221e136677387c36bf03fd320 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 22 Nov 2017 17:00:35 +0100 Subject: [PATCH 0955/2547] drm/amdgpu: unify VM size handling of Vega10 with older generation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit One function to rule them all. Signed-off-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 ++++++++++---------------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 +-- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 22 ++++------------- 6 files changed, 22 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 771995093cac..c942f6b4be1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2573,21 +2573,6 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) return ((bits + 3) / 2); } -/** - * amdgpu_vm_set_fragment_size - adjust fragment size in PTE - * - * @adev: amdgpu_device pointer - * @fragment_size_default: the default fragment size if it's set auto - */ -void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, - uint32_t fragment_size_default) -{ - if (amdgpu_vm_fragment_size == -1) - adev->vm_manager.fragment_size = fragment_size_default; - else - adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; -} - /** * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size * @@ -2595,22 +2580,29 @@ void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, * @vm_size: the default vm size if it's set auto */ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, - uint32_t fragment_size_default) + uint32_t fragment_size_default, unsigned max_level) { - /* adjust vm size firstly */ - if (amdgpu_vm_size != -1) + /* adjust vm size first, but only for two level setups for now */ + if (amdgpu_vm_size != -1 && max_level == 1) vm_size = amdgpu_vm_size; adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; + adev->vm_manager.num_level = max_level; - /* block size depends on vm size */ - if (amdgpu_vm_block_size == -1) + /* block size depends on vm size and hw setup*/ + if (adev->vm_manager.num_level > 1) + /* Use fixed block_size for multi level page tables */ + adev->vm_manager.block_size = 9; + else if (amdgpu_vm_block_size == -1) adev->vm_manager.block_size = amdgpu_vm_get_block_size(vm_size); else adev->vm_manager.block_size = amdgpu_vm_block_size; - amdgpu_vm_set_fragment_size(adev, fragment_size_default); + if (amdgpu_vm_fragment_size == -1) + adev->vm_manager.fragment_size = fragment_size_default; + else + adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n", vm_size, adev->vm_manager.block_size, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index c80d45dd2bd3..54e540d5e8d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -324,10 +324,8 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, uint64_t addr); void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va); -void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, - uint32_t fragment_size_default); void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, - uint32_t fragment_size_default); + uint32_t fragment_size_default, unsigned max_level); int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, struct amdgpu_job *job); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 6098c773711f..49224bf38324 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -832,7 +832,7 @@ static int gmc_v6_0_sw_init(void *handle) if (r) return r; - amdgpu_vm_adjust_size(adev, 64, 9); + amdgpu_vm_adjust_size(adev, 64, 9, 1); adev->mc.mc_mask = 0xffffffffffULL; @@ -877,7 +877,6 @@ static int gmc_v6_0_sw_init(void *handle) * amdkfd will use VMIDs 8-15 */ adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; - adev->vm_manager.num_level = 1; amdgpu_vm_manager_init(adev); /* base offset of vram pages */ diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 8b460e9d4431..c39cf8440afd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -971,7 +971,7 @@ static int gmc_v7_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - amdgpu_vm_adjust_size(adev, 64, 9); + amdgpu_vm_adjust_size(adev, 64, 9, 1); /* Set the internal MC address mask * This is the max address of the GPU's @@ -1026,7 +1026,6 @@ static int gmc_v7_0_sw_init(void *handle) * amdkfd will use VMIDs 8-15 */ adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; - adev->vm_manager.num_level = 1; amdgpu_vm_manager_init(adev); /* base offset of vram pages */ diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 1fd7f9daab0a..421e751a0464 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1068,7 +1068,7 @@ static int gmc_v8_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - amdgpu_vm_adjust_size(adev, 64, 9); + amdgpu_vm_adjust_size(adev, 64, 9, 1); /* Set the internal MC address mask * This is the max address of the GPU's @@ -1123,7 +1123,6 @@ static int gmc_v8_0_sw_init(void *handle) * amdkfd will use VMIDs 8-15 */ adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; - adev->vm_manager.num_level = 1; amdgpu_vm_manager_init(adev); /* base offset of vram pages */ diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 30eb625a991c..729e4d591293 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -769,16 +769,11 @@ static int gmc_v9_0_sw_init(void *handle) switch (adev->asic_type) { case CHIP_RAVEN: adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; - if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { - adev->vm_manager.max_pfn = 1ULL << 36; - adev->vm_manager.block_size = 9; - adev->vm_manager.num_level = 3; - amdgpu_vm_set_fragment_size(adev, 9); - } else { + if (adev->rev_id == 0x0 || adev->rev_id == 0x1) + amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3); + else /* vm_size is 64GB for legacy 2-level page support */ - amdgpu_vm_adjust_size(adev, 64, 9); - adev->vm_manager.num_level = 1; - } + amdgpu_vm_adjust_size(adev, 64, 9, 1); break; case CHIP_VEGA10: /* XXX Don't know how to get VRAM type yet. */ @@ -788,19 +783,12 @@ static int gmc_v9_0_sw_init(void *handle) * vm size is 256TB (48bit), maximum size of Vega10, * block size 512 (9bit) */ - adev->vm_manager.max_pfn = 1ULL << 36; - adev->vm_manager.block_size = 9; - adev->vm_manager.num_level = 3; - amdgpu_vm_set_fragment_size(adev, 9); + amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3); break; default: break; } - DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n", - adev->vm_manager.max_pfn >> 18, adev->vm_manager.block_size, - adev->vm_manager.fragment_size); - /* This interrupt is VMC page fault.*/ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, &adev->mc.vm_fault); -- GitLab From 36539dcea3225fb603905fb884446f3173cc0198 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 23 Nov 2017 11:16:05 +0100 Subject: [PATCH 0956/2547] drm/amdgpu: choose number of VM levels based on VM size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows us limiting the VM size for testing even of Vega10. Signed-off-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index c942f6b4be1b..82a6f6c86aaf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2582,12 +2582,17 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, uint32_t fragment_size_default, unsigned max_level) { - /* adjust vm size first, but only for two level setups for now */ - if (amdgpu_vm_size != -1 && max_level == 1) + uint64_t tmp; + + /* adjust vm size first */ + if (amdgpu_vm_size != -1) vm_size = amdgpu_vm_size; adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; - adev->vm_manager.num_level = max_level; + + tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); + tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; + adev->vm_manager.num_level = min(max_level, (unsigned)tmp); /* block size depends on vm size and hw setup*/ if (adev->vm_manager.num_level > 1) @@ -2604,8 +2609,9 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, else adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; - DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n", - vm_size, adev->vm_manager.block_size, + DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n", + vm_size, adev->vm_manager.num_level + 1, + adev->vm_manager.block_size, adev->vm_manager.fragment_size); } -- GitLab From 341b759e642a847c3a88401db4263dec9f36d552 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 23 Nov 2017 11:23:18 +0100 Subject: [PATCH 0957/2547] drm/amdgpu: allow non pot VM size values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The VM size actually doesn't need to be a power of two. Signed-off-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0750b323e03f..748ecd74726d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1184,12 +1184,6 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev) if (amdgpu_vm_size == -1) return; - if (!is_power_of_2(amdgpu_vm_size)) { - dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", - amdgpu_vm_size); - goto def_value; - } - if (amdgpu_vm_size < 1) { dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", amdgpu_vm_size); -- GitLab From f3368128bacece315aa0384b54b7da9e6f0909cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 23 Nov 2017 12:57:18 +0100 Subject: [PATCH 0958/2547] drm/amdgpu: move validation of the VM size into the VM code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This moves validation of the VM size parameter into amdgpu_vm_adjust_size(). Signed-off-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +--------------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 13 +++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +++--- 7 files changed, 20 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 748ecd74726d..cd74beb431c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1187,22 +1187,8 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev) if (amdgpu_vm_size < 1) { dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", amdgpu_vm_size); - goto def_value; + amdgpu_vm_size = -1; } - - /* - * Max GPUVM size for Cayman, SI, CI VI are 40 bits. - */ - if (amdgpu_vm_size > 1024) { - dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", - amdgpu_vm_size); - goto def_value; - } - - return; - -def_value: - amdgpu_vm_size = -1; } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 82a6f6c86aaf..44430c4820cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2580,13 +2580,22 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) * @vm_size: the default vm size if it's set auto */ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, - uint32_t fragment_size_default, unsigned max_level) + uint32_t fragment_size_default, unsigned max_level, + unsigned max_bits) { uint64_t tmp; /* adjust vm size first */ - if (amdgpu_vm_size != -1) + if (amdgpu_vm_size != -1) { + unsigned max_size = 1 << (max_bits - 30); + vm_size = amdgpu_vm_size; + if (vm_size > max_size) { + dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", + amdgpu_vm_size, max_size); + vm_size = max_size; + } + } adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 54e540d5e8d7..43ea131dd411 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -325,7 +325,8 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va); void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, - uint32_t fragment_size_default, unsigned max_level); + uint32_t fragment_size_default, unsigned max_level, + unsigned max_bits); int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, struct amdgpu_job *job); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 49224bf38324..468281f10e8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -832,7 +832,7 @@ static int gmc_v6_0_sw_init(void *handle) if (r) return r; - amdgpu_vm_adjust_size(adev, 64, 9, 1); + amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); adev->mc.mc_mask = 0xffffffffffULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index c39cf8440afd..68a85051f4b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -971,7 +971,7 @@ static int gmc_v7_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - amdgpu_vm_adjust_size(adev, 64, 9, 1); + amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); /* Set the internal MC address mask * This is the max address of the GPU's diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 421e751a0464..46ec97e70e5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1068,7 +1068,7 @@ static int gmc_v8_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - amdgpu_vm_adjust_size(adev, 64, 9, 1); + amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); /* Set the internal MC address mask * This is the max address of the GPU's diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 729e4d591293..cc972153d401 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -770,10 +770,10 @@ static int gmc_v9_0_sw_init(void *handle) case CHIP_RAVEN: adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; if (adev->rev_id == 0x0 || adev->rev_id == 0x1) - amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3); + amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); else /* vm_size is 64GB for legacy 2-level page support */ - amdgpu_vm_adjust_size(adev, 64, 9, 1); + amdgpu_vm_adjust_size(adev, 64, 9, 1, 48); break; case CHIP_VEGA10: /* XXX Don't know how to get VRAM type yet. */ @@ -783,7 +783,7 @@ static int gmc_v9_0_sw_init(void *handle) * vm size is 256TB (48bit), maximum size of Vega10, * block size 512 (9bit) */ - amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3); + amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); break; default: break; -- GitLab From 97489129c220ef67195c886f9f2bad9651edd601 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 27 Nov 2017 16:22:05 +0100 Subject: [PATCH 0959/2547] drm/amdgpu: allow specifying vm_block_size for multi level PDs v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch allows specifying the vm_block_size even when multi level page directories are active. v2: fix signed/unsigned compare warning Signed-off-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +------------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 15 +++++++++------ 2 files changed, 10 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index cd74beb431c4..70c9e5756b02 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1162,20 +1162,8 @@ static void amdgpu_check_block_size(struct amdgpu_device *adev) if (amdgpu_vm_block_size < 9) { dev_warn(adev->dev, "VM page table size (%d) too small\n", amdgpu_vm_block_size); - goto def_value; + amdgpu_vm_block_size = -1; } - - if (amdgpu_vm_block_size > 24 || - (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { - dev_warn(adev->dev, "VM page table size (%d) too large\n", - amdgpu_vm_block_size); - goto def_value; - } - - return; - -def_value: - amdgpu_vm_block_size = -1; } static void amdgpu_check_vm_size(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 44430c4820cc..7de519b86b78 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2600,18 +2600,21 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); + if (amdgpu_vm_block_size != -1) + tmp >>= amdgpu_vm_block_size - 9; tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; adev->vm_manager.num_level = min(max_level, (unsigned)tmp); /* block size depends on vm size and hw setup*/ - if (adev->vm_manager.num_level > 1) - /* Use fixed block_size for multi level page tables */ - adev->vm_manager.block_size = 9; - else if (amdgpu_vm_block_size == -1) + if (amdgpu_vm_block_size != -1) adev->vm_manager.block_size = - amdgpu_vm_get_block_size(vm_size); + min((unsigned)amdgpu_vm_block_size, max_bits + - AMDGPU_GPU_PAGE_SHIFT + - 9 * adev->vm_manager.num_level); + else if (adev->vm_manager.num_level > 1) + adev->vm_manager.block_size = 9; else - adev->vm_manager.block_size = amdgpu_vm_block_size; + adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp); if (amdgpu_vm_fragment_size == -1) adev->vm_manager.fragment_size = fragment_size_default; -- GitLab From cebb52b7bc325863600aff930407bba773010938 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 13 Nov 2017 14:47:52 -0500 Subject: [PATCH 0960/2547] drm/amdgpu: Get rid of dep_sync as a seperate object. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead mark fence as explicit in it's amdgpu_sync_entry. v2: Fix use after free bug and add new parameter description. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 14 +++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 24 +++++++++++------------- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 15 ++++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 ++++++------ 7 files changed, 37 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ecc2e60e5f0c..5e2958a79928 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1121,7 +1121,6 @@ struct amdgpu_job { struct amdgpu_vm *vm; struct amdgpu_ring *ring; struct amdgpu_sync sync; - struct amdgpu_sync dep_sync; struct amdgpu_sync sched_sync; struct amdgpu_ib *ibs; struct dma_fence *fence; /* the hw fence */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 93d3cef66503..4cea9ab237ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -786,7 +786,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) return r; r = amdgpu_sync_fence(adev, &p->job->sync, - fpriv->prt_va->last_pt_update); + fpriv->prt_va->last_pt_update, false); if (r) return r; @@ -800,7 +800,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) return r; f = bo_va->last_pt_update; - r = amdgpu_sync_fence(adev, &p->job->sync, f); + r = amdgpu_sync_fence(adev, &p->job->sync, f, false); if (r) return r; } @@ -823,7 +823,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) return r; f = bo_va->last_pt_update; - r = amdgpu_sync_fence(adev, &p->job->sync, f); + r = amdgpu_sync_fence(adev, &p->job->sync, f, false); if (r) return r; } @@ -834,7 +834,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) if (r) return r; - r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update); + r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false); if (r) return r; @@ -1038,8 +1038,8 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, amdgpu_ctx_put(ctx); return r; } else if (fence) { - r = amdgpu_sync_fence(p->adev, &p->job->dep_sync, - fence); + r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, + true); dma_fence_put(fence); amdgpu_ctx_put(ctx); if (r) @@ -1058,7 +1058,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p, if (r) return r; - r = amdgpu_sync_fence(p->adev, &p->job->dep_sync, fence); + r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true); dma_fence_put(fence); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 659997bfff30..0cf86eb357d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -164,7 +164,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, } if (ring->funcs->emit_pipeline_sync && job && - ((tmp = amdgpu_sync_get_fence(&job->sched_sync)) || + ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) || amdgpu_vm_need_pipeline_sync(ring, job))) { need_pipe_sync = true; dma_fence_put(tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 18770a880393..bdc210ac74f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -60,7 +60,6 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, (*job)->num_ibs = num_ibs; amdgpu_sync_create(&(*job)->sync); - amdgpu_sync_create(&(*job)->dep_sync); amdgpu_sync_create(&(*job)->sched_sync); (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter); @@ -104,7 +103,6 @@ static void amdgpu_job_free_cb(struct amd_sched_job *s_job) amdgpu_ring_priority_put(job->ring, s_job->s_priority); dma_fence_put(job->fence); amdgpu_sync_free(&job->sync); - amdgpu_sync_free(&job->dep_sync); amdgpu_sync_free(&job->sched_sync); kfree(job); } @@ -115,7 +113,6 @@ void amdgpu_job_free(struct amdgpu_job *job) dma_fence_put(job->fence); amdgpu_sync_free(&job->sync); - amdgpu_sync_free(&job->dep_sync); amdgpu_sync_free(&job->sched_sync); kfree(job); } @@ -149,17 +146,18 @@ static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job, { struct amdgpu_job *job = to_amdgpu_job(sched_job); struct amdgpu_vm *vm = job->vm; - - struct dma_fence *fence = amdgpu_sync_get_fence(&job->dep_sync); + bool explicit = false; int r; - - if (amd_sched_dependency_optimized(fence, s_entity)) { - r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence); - if (r) - DRM_ERROR("Error adding fence to sync (%d)\n", r); + struct dma_fence *fence = amdgpu_sync_get_fence(&job->sync, &explicit); + + if (fence && explicit) { + if (amd_sched_dependency_optimized(fence, s_entity)) { + r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence, false); + if (r) + DRM_ERROR("Error adding fence to sync (%d)\n", r); + } } - if (!fence) - fence = amdgpu_sync_get_fence(&job->sync); + while (fence == NULL && vm && !job->vm_id) { struct amdgpu_ring *ring = job->ring; @@ -169,7 +167,7 @@ static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job, if (r) DRM_ERROR("Error getting VM ID (%d)\n", r); - fence = amdgpu_sync_get_fence(&job->sync); + fence = amdgpu_sync_get_fence(&job->sync, NULL); } return fence; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index a4bf21f8f1c1..f3d1a25b660f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -35,6 +35,7 @@ struct amdgpu_sync_entry { struct hlist_node node; struct dma_fence *fence; + bool explicit; }; static struct kmem_cache *amdgpu_sync_slab; @@ -141,7 +142,7 @@ static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f) * */ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, - struct dma_fence *f) + struct dma_fence *f, bool explicit) { struct amdgpu_sync_entry *e; @@ -159,6 +160,8 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, if (!e) return -ENOMEM; + e->explicit = explicit; + hash_add(sync->fences, &e->node, f->context); e->fence = dma_fence_get(f); return 0; @@ -189,7 +192,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, /* always sync to the exclusive fence */ f = reservation_object_get_excl(resv); - r = amdgpu_sync_fence(adev, sync, f); + r = amdgpu_sync_fence(adev, sync, f, false); if (explicit_sync) return r; @@ -220,7 +223,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, continue; } - r = amdgpu_sync_fence(adev, sync, f); + r = amdgpu_sync_fence(adev, sync, f, false); if (r) break; } @@ -275,19 +278,21 @@ struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, * amdgpu_sync_get_fence - get the next fence from the sync object * * @sync: sync object to use + * @explicit: true if the next fence is explicit * * Get and removes the next fence from the sync object not signaled yet. */ -struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync) +struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit) { struct amdgpu_sync_entry *e; struct hlist_node *tmp; struct dma_fence *f; int i; - hash_for_each_safe(sync->fences, i, tmp, e, node) { f = e->fence; + if (explicit) + *explicit = e->explicit; hash_del(&e->node); kmem_cache_free(amdgpu_sync_slab, e); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h index 70d7e3a279a0..7aba38d5c9df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h @@ -41,7 +41,7 @@ struct amdgpu_sync { void amdgpu_sync_create(struct amdgpu_sync *sync); int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, - struct dma_fence *f); + struct dma_fence *f, bool explicit); int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, struct reservation_object *resv, @@ -49,7 +49,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, bool explicit_sync); struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, struct amdgpu_ring *ring); -struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); +struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit); int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr); void amdgpu_sync_free(struct amdgpu_sync *sync); int amdgpu_sync_init(void); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 7de519b86b78..3ecdbdfb04dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -488,7 +488,7 @@ static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, id->pd_gpu_addr = 0; tmp = amdgpu_sync_peek_fence(&id->active, ring); if (tmp) { - r = amdgpu_sync_fence(adev, sync, tmp); + r = amdgpu_sync_fence(adev, sync, tmp, false); return r; } } @@ -496,7 +496,7 @@ static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, /* Good we can use this VMID. Remember this submission as * user of the VMID. */ - r = amdgpu_sync_fence(ring->adev, &id->active, fence); + r = amdgpu_sync_fence(ring->adev, &id->active, fence, false); if (r) goto out; @@ -583,7 +583,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, } - r = amdgpu_sync_fence(ring->adev, sync, &array->base); + r = amdgpu_sync_fence(ring->adev, sync, &array->base, false); dma_fence_put(&array->base); if (r) goto error; @@ -626,7 +626,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, /* Good we can use this VMID. Remember this submission as * user of the VMID. */ - r = amdgpu_sync_fence(ring->adev, &id->active, fence); + r = amdgpu_sync_fence(ring->adev, &id->active, fence, false); if (r) goto error; @@ -646,7 +646,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, id = idle; /* Remember this submission as user of the VMID */ - r = amdgpu_sync_fence(ring->adev, &id->active, fence); + r = amdgpu_sync_fence(ring->adev, &id->active, fence, false); if (r) goto error; @@ -1657,7 +1657,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, addr = 0; } - r = amdgpu_sync_fence(adev, &job->sync, exclusive); + r = amdgpu_sync_fence(adev, &job->sync, exclusive, false); if (r) goto error_free; -- GitLab From 5f97fc0e032594212459f63e9c6229cd79ccb697 Mon Sep 17 00:00:00 2001 From: Roger He Date: Wed, 29 Nov 2017 17:12:03 +0800 Subject: [PATCH 0961/2547] drm/amd/amdgpu: set gtt size according to system memory size only MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 3385694a97cc..952e0bf3bc84 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1330,11 +1330,9 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) struct sysinfo si; si_meminfo(&si); - gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), - adev->mc.mc_vram_size), - ((uint64_t)si.totalram * si.mem_unit * 3/4)); - } - else + gtt_size = max(AMDGPU_DEFAULT_GTT_SIZE_MB << 20, + (uint64_t)si.totalram * si.mem_unit * 3/4); + } else gtt_size = (uint64_t)amdgpu_gtt_size << 20; r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT); if (r) { -- GitLab From fdb1a2236b07948e83e0a777e1795d4f07e52c33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 4 Dec 2017 11:17:54 +0100 Subject: [PATCH 0962/2547] drm/ttm: swap consecutive allocated cached pages v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When we detect consecutive allocation of pages swap them to avoid accidentally freeing them as huge page. v2: use swap v3: check if it's really the first allocated page Signed-off-by: Christian König Reviewed-by: Roger He Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 116897a20514..b6f7ce286fb1 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -877,7 +877,7 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, #endif struct list_head plist; struct page *p = NULL; - unsigned count; + unsigned count, first; int r; /* No pool for cached pages */ @@ -918,6 +918,7 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, } #endif + first = i; while (npages) { p = alloc_page(gfp_flags); if (!p) { @@ -925,6 +926,10 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, return -ENOMEM; } + /* Swap the pages if we detect consecutive order */ + if (i > first && pages[i - 1] == p - 1) + swap(p, pages[i - 1]); + pages[i++] = p; --npages; } -- GitLab From d4b7648d6d1774f961f3f6a758d9b009f1f34f05 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 24 Nov 2017 11:41:52 +0100 Subject: [PATCH 0963/2547] drm/amdgpu: fix amdgpu_sync_resv v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes a bug introduced by AMDGPU_GEM_CREATE_EXPLICIT_SYNC. We still need to wait for pipelined moves in the shared fences list. v2: fix typo Signed-off-by: Christian König Reviewed-by: Andres Rodriguez Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index f3d1a25b660f..ebe1ffbab0c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -194,9 +194,6 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, f = reservation_object_get_excl(resv); r = amdgpu_sync_fence(adev, sync, f, false); - if (explicit_sync) - return r; - flist = reservation_object_get_list(resv); if (!flist || r) return r; @@ -215,11 +212,11 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, (fence_owner == AMDGPU_FENCE_OWNER_VM))) continue; - /* Ignore fence from the same owner as + /* Ignore fence from the same owner and explicit one as * long as it isn't undefined. */ if (owner != AMDGPU_FENCE_OWNER_UNDEFINED && - fence_owner == owner) + (fence_owner == owner || explicit_sync)) continue; } -- GitLab From ae937fe19636067ec5e20d7f1fa10c6cc6000b52 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 4 Dec 2017 11:26:14 +0100 Subject: [PATCH 0964/2547] drm/ttm: swap consecutive allocated pooled pages v4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When we detect consecutive allocation of pages swap them to avoid accidentally freeing them as huge page. v2: use swap v3: check if it's really the first allocated page v4: don't touch the loop variable Signed-off-by: Christian König Reviewed-by: Roger He Reviewed-by: Michel Dänzer Tested-by: Dieter Nützel Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index b6f7ce286fb1..44343a2bf55c 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -958,8 +958,15 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, r = ttm_page_pool_get_pages(pool, &plist, flags, cstate, npages - count, 0); - list_for_each_entry(p, &plist, lru) - pages[count++] = p; + first = count; + list_for_each_entry(p, &plist, lru) { + struct page *tmp = p; + + /* Swap the pages if we detect consecutive order */ + if (count > first && pages[count - 1] == tmp - 1) + swap(tmp, pages[count - 1]); + pages[count++] = tmp; + } if (r) { /* If there is any pages in the list put them back to -- GitLab From 366c1baa87f93e5913e753f45f114823b3c83bfd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Tue, 5 Dec 2017 19:24:54 +0100 Subject: [PATCH 0965/2547] drm/amd/display: Use drm_fb_helper_poll_changed() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can use drm_fb_helper_output_poll_changed() as its .output_poll_changed callback. Cc: Alex Deucher Cc: "Christian König" Signed-off-by: Noralf Trønnes Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9aff7eea4375..ccbf10e3bbb6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -792,7 +792,7 @@ dm_atomic_state_alloc_free(struct drm_atomic_state *state) static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_user_framebuffer_create, - .output_poll_changed = amdgpu_output_poll_changed, + .output_poll_changed = drm_fb_helper_output_poll_changed, .atomic_check = amdgpu_dm_atomic_check, .atomic_commit = amdgpu_dm_atomic_commit, .atomic_state_alloc = dm_atomic_state_alloc, -- GitLab From ab77e02ce98ab8dfb556f2cc0078c6a0bf80ecef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Tue, 5 Dec 2017 19:24:55 +0100 Subject: [PATCH 0966/2547] drm/amdgpu: Use drm_fb_helper_lastclose() and _poll_changed() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can use drm_fb_helper_lastclose() in its .lastclose function. It can also use drm_fb_helper_output_poll_changed() as its .output_poll_changed callback. Remove the unused driver implementations. Cc: Alex Deucher Cc: "Christian König" Signed-off-by: Noralf Trønnes Acked-by: Daniel Vetter Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 ++----- drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 27 --------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 --- 5 files changed, 3 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 138beb550a58..38d47559f098 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -34,6 +34,7 @@ #include #include #include +#include static void amdgpu_flip_callback(struct dma_fence *f, struct dma_fence_cb *cb) { @@ -556,15 +557,9 @@ amdgpu_user_framebuffer_create(struct drm_device *dev, return &amdgpu_fb->base; } -void amdgpu_output_poll_changed(struct drm_device *dev) -{ - struct amdgpu_device *adev = dev->dev_private; - amdgpu_fb_output_poll_changed(adev); -} - const struct drm_mode_config_funcs amdgpu_mode_funcs = { .fb_create = amdgpu_user_framebuffer_create, - .output_poll_changed = amdgpu_output_poll_changed + .output_poll_changed = drm_fb_helper_output_poll_changed, }; static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index 11ae4ab23768..0bcb6c6e0ca9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -27,6 +27,5 @@ struct drm_framebuffer * amdgpu_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd); -void amdgpu_output_poll_changed(struct drm_device *dev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 90fa8e8bc6fb..ff3e9beb7d19 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -283,12 +283,6 @@ static int amdgpufb_create(struct drm_fb_helper *helper, return ret; } -void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev) -{ - if (adev->mode_info.rfbdev) - drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper); -} - static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) { struct amdgpu_framebuffer *rfb = &rfbdev->rfb; @@ -393,24 +387,3 @@ bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) return true; return false; } - -void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev) -{ - struct amdgpu_fbdev *afbdev; - struct drm_fb_helper *fb_helper; - int ret; - - if (!adev) - return; - - afbdev = adev->mode_info.rfbdev; - - if (!afbdev) - return; - - fb_helper = &afbdev->helper; - - ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper); - if (ret) - DRM_DEBUG("failed to restore crtc mode\n"); -} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 3222e1d4636c..bd6e9a40f421 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -788,9 +788,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file */ void amdgpu_driver_lastclose_kms(struct drm_device *dev) { - struct amdgpu_device *adev = dev->dev_private; - - amdgpu_fbdev_restore_mode(adev); + drm_fb_helper_lastclose(dev); vga_switcheroo_process_delayed_switch(); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 126b8b068b7a..54f06c959340 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -658,10 +658,6 @@ void amdgpu_fbdev_fini(struct amdgpu_device *adev); void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); int amdgpu_fbdev_total_size(struct amdgpu_device *adev); bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); -void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev); - -void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev); - int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); -- GitLab From 3997eea57caf542e9327df9b6bb2882a57c4c421 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Tue, 5 Dec 2017 19:25:02 +0100 Subject: [PATCH 0967/2547] drm/radeon: Use drm_fb_helper_lastclose() and _poll_changed() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can use drm_fb_helper_lastclose() in its .lastclose function. It can also use drm_fb_helper_output_poll_changed() as its .output_poll_changed callback. Cc: Alex Deucher Cc: "Christian König" Signed-off-by: Noralf Trønnes Acked-by: Daniel Vetter Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_display.c | 9 ++------- drivers/gpu/drm/radeon/radeon_fb.c | 22 ---------------------- drivers/gpu/drm/radeon/radeon_kms.c | 5 ++--- drivers/gpu/drm/radeon/radeon_mode.h | 3 --- 4 files changed, 4 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index ddfe91efa61e..dfda5e0ed166 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -32,6 +32,7 @@ #include #include +#include #include #include @@ -1362,15 +1363,9 @@ radeon_user_framebuffer_create(struct drm_device *dev, return &radeon_fb->base; } -static void radeon_output_poll_changed(struct drm_device *dev) -{ - struct radeon_device *rdev = dev->dev_private; - radeon_fb_output_poll_changed(rdev); -} - static const struct drm_mode_config_funcs radeon_mode_funcs = { .fb_create = radeon_user_framebuffer_create, - .output_poll_changed = radeon_output_poll_changed + .output_poll_changed = drm_fb_helper_output_poll_changed, }; static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index 33b821d6d018..57c5404a1654 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -306,12 +306,6 @@ static int radeonfb_create(struct drm_fb_helper *helper, return ret; } -void radeon_fb_output_poll_changed(struct radeon_device *rdev) -{ - if (rdev->mode_info.rfbdev) - drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper); -} - static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev) { struct radeon_framebuffer *rfb = &rfbdev->rfb; @@ -422,19 +416,3 @@ void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector if (rdev->mode_info.rfbdev) drm_fb_helper_remove_one_connector(&rdev->mode_info.rfbdev->helper, connector); } - -void radeon_fbdev_restore_mode(struct radeon_device *rdev) -{ - struct radeon_fbdev *rfbdev = rdev->mode_info.rfbdev; - struct drm_fb_helper *fb_helper; - int ret; - - if (!rfbdev) - return; - - fb_helper = &rfbdev->helper; - - ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper); - if (ret) - DRM_DEBUG("failed to restore crtc mode\n"); -} diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index cde037f213d7..dec1e081f529 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -26,6 +26,7 @@ * Jerome Glisse */ #include +#include #include "radeon.h" #include #include "radeon_asic.h" @@ -629,9 +630,7 @@ static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file */ void radeon_driver_lastclose_kms(struct drm_device *dev) { - struct radeon_device *rdev = dev->dev_private; - - radeon_fbdev_restore_mode(rdev); + drm_fb_helper_lastclose(dev); vga_switcheroo_process_delayed_switch(); } diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index ca0a7ed28c9b..3243e5e01432 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -984,9 +984,6 @@ int radeon_fbdev_init(struct radeon_device *rdev); void radeon_fbdev_fini(struct radeon_device *rdev); void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); -void radeon_fbdev_restore_mode(struct radeon_device *rdev); - -void radeon_fb_output_poll_changed(struct radeon_device *rdev); void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); -- GitLab From 071b6d4a5d343046f253a5a8835d477d93992002 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Tue, 5 Dec 2017 14:56:42 +0000 Subject: [PATCH 0968/2547] arm64: fpsimd: Prevent registers leaking from dead tasks Currently, loading of a task's fpsimd state into the CPU registers is skipped if that task's state is already present in the registers of that CPU. However, the code relies on the struct fpsimd_state * (and by extension struct task_struct *) to unambiguously identify a task. There is a particular case in which this doesn't work reliably: when a task exits, its task_struct may be recycled to describe a new task. Consider the following scenario: 1) Task P loads its fpsimd state onto cpu C. per_cpu(fpsimd_last_state, C) := P; P->thread.fpsimd_state.cpu := C; 2) Task X is scheduled onto C and loads its fpsimd state on C. per_cpu(fpsimd_last_state, C) := X; X->thread.fpsimd_state.cpu := C; 3) X exits, causing X's task_struct to be freed. 4) P forks a new child T, which obtains X's recycled task_struct. T == X. T->thread.fpsimd_state.cpu == C (inherited from P). 5) T is scheduled on C. T's fpsimd state is not loaded, because per_cpu(fpsimd_last_state, C) == T (== X) && T->thread.fpsimd_state.cpu == C. (This is the check performed by fpsimd_thread_switch().) So, T gets X's registers because the last registers loaded onto C were those of X, in (2). This patch fixes the problem by ensuring that the sched-in check fails in (5): fpsimd_flush_task_state(T) is called when T is forked, so that T->thread.fpsimd_state.cpu == C cannot be true. This relies on the fact that T is not schedulable until after copy_thread() completes. Once T's fpsimd state has been loaded on some CPU C there may still be other cpus D for which per_cpu(fpsimd_last_state, D) == &X->thread.fpsimd_state. But D is necessarily != C in this case, and the check in (5) must fail. An alternative fix would be to do refcounting on task_struct. This would result in each CPU holding a reference to the last task whose fpsimd state was loaded there. It's not clear whether this is preferable, and it involves higher overhead than the fix proposed in this patch. It would also move all the task_struct freeing work into the context switch critical section, or otherwise some deferred cleanup mechanism would need to be introduced, neither of which seems obviously justified. Cc: Fixes: 005f78cd8849 ("arm64: defer reloading a task's FPSIMD state to userland resume") Signed-off-by: Dave Martin Reviewed-by: Ard Biesheuvel [will: word-smithed the comment so it makes more sense] Signed-off-by: Will Deacon --- arch/arm64/kernel/process.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index b2adcce7bc18..6b7dcf4310ac 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -314,6 +314,15 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start, clear_tsk_thread_flag(p, TIF_SVE); p->thread.sve_state = NULL; + /* + * In case p was allocated the same task_struct pointer as some + * other recently-exited task, make sure p is disassociated from + * any cpu that may have run that now-exited task recently. + * Otherwise we could erroneously skip reloading the FPSIMD + * registers for p. + */ + fpsimd_flush_task_state(p); + if (likely(!(p->flags & PF_KTHREAD))) { *childregs = *current_pt_regs(); childregs->regs[0] = 0; -- GitLab From 8884b7bd7e52de20a801c5f457954ed212c0f625 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Wed, 6 Dec 2017 16:45:46 +0000 Subject: [PATCH 0969/2547] arm64: fpsimd: Abstract out binding of task's fpsimd context to the cpu. There is currently some duplicate logic to associate current's FPSIMD context with the cpu when loading FPSIMD state into the cpu regs. Subsequent patches will update that logic, so in order to ensure it only needs to be done in one place, this patch factors the relevant code out into a new function fpsimd_bind_to_cpu(). Signed-off-by: Dave Martin Reviewed-by: Ard Biesheuvel Signed-off-by: Will Deacon --- arch/arm64/kernel/fpsimd.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 5084e699447a..e330cc0b573d 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -991,6 +991,18 @@ void fpsimd_signal_preserve_current_state(void) sve_to_fpsimd(current); } +/* + * Associate current's FPSIMD context with this cpu + * Preemption must be disabled when calling this function. + */ +static void fpsimd_bind_to_cpu(void) +{ + struct fpsimd_state *st = ¤t->thread.fpsimd_state; + + __this_cpu_write(fpsimd_last_state, st); + st->cpu = smp_processor_id(); +} + /* * Load the userland FPSIMD state of 'current' from memory, but only if the * FPSIMD state already held in the registers is /not/ the most recent FPSIMD @@ -1004,11 +1016,8 @@ void fpsimd_restore_current_state(void) local_bh_disable(); if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) { - struct fpsimd_state *st = ¤t->thread.fpsimd_state; - task_fpsimd_load(); - __this_cpu_write(fpsimd_last_state, st); - st->cpu = smp_processor_id(); + fpsimd_bind_to_cpu(); } local_bh_enable(); @@ -1032,12 +1041,8 @@ void fpsimd_update_current_state(struct fpsimd_state *state) task_fpsimd_load(); - if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) { - struct fpsimd_state *st = ¤t->thread.fpsimd_state; - - __this_cpu_write(fpsimd_last_state, st); - st->cpu = smp_processor_id(); - } + if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) + fpsimd_bind_to_cpu(); local_bh_enable(); } -- GitLab From 0adbdfde8cfc9415aeed2a4955d2d17b3bd9bf13 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 6 Dec 2017 10:42:10 +0000 Subject: [PATCH 0970/2547] arm64: SW PAN: Point saved ttbr0 at the zero page when switching to init_mm update_saved_ttbr0 mandates that mm->pgd is not swapper, since swapper contains kernel mappings and should never be installed into ttbr0. However, this means that callers must avoid passing the init_mm to update_saved_ttbr0 which in turn can cause the saved ttbr0 value to be out-of-date in the context of the idle thread. For example, EFI runtime services may leave the saved ttbr0 pointing at the EFI page table, and kernel threads may end up with stale references to freed page tables. This patch changes update_saved_ttbr0 so that the init_mm points the saved ttbr0 value to the empty zero page, which always exists and never contains valid translations. EFI and switch can then call into update_saved_ttbr0 unconditionally. Cc: Mark Rutland Cc: Ard Biesheuvel Cc: Vinayak Menon Cc: Fixes: 39bc88e5e38e9b21 ("arm64: Disable TTBR0_EL1 during normal kernel execution") Reviewed-by: Catalin Marinas Reviewed-by: Mark Rutland Reported-by: Vinayak Menon Signed-off-by: Will Deacon --- arch/arm64/include/asm/efi.h | 4 +--- arch/arm64/include/asm/mmu_context.h | 22 +++++++++++++--------- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h index 650344d01124..c4cd5081d78b 100644 --- a/arch/arm64/include/asm/efi.h +++ b/arch/arm64/include/asm/efi.h @@ -132,11 +132,9 @@ static inline void efi_set_pgd(struct mm_struct *mm) * Defer the switch to the current thread's TTBR0_EL1 * until uaccess_enable(). Restore the current * thread's saved ttbr0 corresponding to its active_mm - * (if different from init_mm). */ cpu_set_reserved_ttbr0(); - if (current->active_mm != &init_mm) - update_saved_ttbr0(current, current->active_mm); + update_saved_ttbr0(current, current->active_mm); } } } diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index 3257895a9b5e..f7773f90546e 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -174,11 +174,17 @@ enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) static inline void update_saved_ttbr0(struct task_struct *tsk, struct mm_struct *mm) { - if (system_uses_ttbr0_pan()) { - BUG_ON(mm->pgd == swapper_pg_dir); - task_thread_info(tsk)->ttbr0 = - virt_to_phys(mm->pgd) | ASID(mm) << 48; - } + u64 ttbr; + + if (!system_uses_ttbr0_pan()) + return; + + if (mm == &init_mm) + ttbr = __pa_symbol(empty_zero_page); + else + ttbr = virt_to_phys(mm->pgd) | ASID(mm) << 48; + + task_thread_info(tsk)->ttbr0 = ttbr; } #else static inline void update_saved_ttbr0(struct task_struct *tsk, @@ -214,11 +220,9 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, * Update the saved TTBR0_EL1 of the scheduled-in task as the previous * value may have not been initialised yet (activate_mm caller) or the * ASID has changed since the last run (following the context switch - * of another thread of the same process). Avoid setting the reserved - * TTBR0_EL1 to swapper_pg_dir (init_mm; e.g. via idle_task_exit). + * of another thread of the same process). */ - if (next != &init_mm) - update_saved_ttbr0(tsk, next); + update_saved_ttbr0(tsk, next); } #define deactivate_mm(tsk,mm) do { } while (0) -- GitLab From d96cc49bff5a7735576cc6f6f111f875d101cec8 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 6 Dec 2017 10:51:12 +0000 Subject: [PATCH 0971/2547] arm64: SW PAN: Update saved ttbr0 value on enter_lazy_tlb enter_lazy_tlb is called when a kernel thread rides on the back of another mm, due to a context switch or an explicit call to unuse_mm where a call to switch_mm is elided. In these cases, it's important to keep the saved ttbr value up to date with the active mm, otherwise we can end up with a stale value which points to a potentially freed page table. This patch implements enter_lazy_tlb for arm64, so that the saved ttbr0 is kept up-to-date with the active mm for kernel threads. Cc: Mark Rutland Cc: Ard Biesheuvel Cc: Vinayak Menon Cc: Fixes: 39bc88e5e38e9b21 ("arm64: Disable TTBR0_EL1 during normal kernel execution") Reviewed-by: Catalin Marinas Reviewed-by: Mark Rutland Reported-by: Vinayak Menon Signed-off-by: Will Deacon --- arch/arm64/include/asm/mmu_context.h | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index f7773f90546e..9d155fa9a507 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -156,20 +156,6 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu); #define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.id, 0); 0; }) -/* - * This is called when "tsk" is about to enter lazy TLB mode. - * - * mm: describes the currently active mm context - * tsk: task which is entering lazy tlb - * cpu: cpu number which is entering lazy tlb - * - * tsk->mm will be NULL - */ -static inline void -enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ -} - #ifdef CONFIG_ARM64_SW_TTBR0_PAN static inline void update_saved_ttbr0(struct task_struct *tsk, struct mm_struct *mm) @@ -193,6 +179,16 @@ static inline void update_saved_ttbr0(struct task_struct *tsk, } #endif +static inline void +enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) +{ + /* + * We don't actually care about the ttbr0 mapping, so point it at the + * zero page. + */ + update_saved_ttbr0(tsk, &init_mm); +} + static inline void __switch_mm(struct mm_struct *next) { unsigned int cpu = smp_processor_id(); -- GitLab From 5b1ead6800cb2241aeadcba32736c5836e59c7e1 Mon Sep 17 00:00:00 2001 From: Brendan Jackman Date: Wed, 6 Dec 2017 10:59:11 +0000 Subject: [PATCH 0972/2547] cpu/hotplug: Fix state name in takedown_cpu() comment CPUHP_AP_SCHED_MIGRATE_DYING doesn't exist, it looks like this was supposed to refer to CPUHP_AP_SCHED_STARTING's teardown callback, i.e. sched_cpu_dying(). Signed-off-by: Brendan Jackman Cc: Boris Ostrovsky Cc: Dietmar Eggemann Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Quentin Perret Cc: Sebastian Andrzej Siewior Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/20171206105911.28093-1-brendan.jackman@arm.com Signed-off-by: Ingo Molnar --- kernel/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/cpu.c b/kernel/cpu.c index 04892a82f6ac..2a885c5f2429 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -780,8 +780,8 @@ static int takedown_cpu(unsigned int cpu) BUG_ON(cpu_online(cpu)); /* - * The CPUHP_AP_SCHED_MIGRATE_DYING callback will have removed all - * runnable tasks from the cpu, there's only the idle task left now + * The teardown callback for CPUHP_AP_SCHED_STARTING will have removed + * all runnable tasks from the CPU, there's only the idle task left now * that the migration thread is done doing the stop_machine thing. * * Wait for the stop thread to go away. -- GitLab From 5e351ad106997e06b2dc3da9c6b939b95f67fb88 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Wed, 6 Dec 2017 17:32:47 +0100 Subject: [PATCH 0973/2547] locking/lockdep: Fix possible NULL deref We can't invalidate xhlocks when we've not yet allocated any. Reported-by: Dmitry Vyukov Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Fixes: f52be5708076 ("locking/lockdep: Untangle xhlock history save/restore from task independence") Signed-off-by: Ingo Molnar --- kernel/locking/lockdep.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/locking/lockdep.c b/kernel/locking/lockdep.c index 9776da8db180..670d8d7d8087 100644 --- a/kernel/locking/lockdep.c +++ b/kernel/locking/lockdep.c @@ -4790,7 +4790,8 @@ void lockdep_invariant_state(bool force) * Verify the former, enforce the latter. */ WARN_ON_ONCE(!force && current->lockdep_depth); - invalidate_xhlock(&xhlock(current->xhlock_idx)); + if (current->xhlocks) + invalidate_xhlock(&xhlock(current->xhlock_idx)); } static int cross_lock(struct lockdep_map *lock) -- GitLab From c6b9d9a33029014446bd9ed84c1688f6d3d4eab9 Mon Sep 17 00:00:00 2001 From: Omar Sandoval Date: Tue, 5 Dec 2017 23:15:31 -0800 Subject: [PATCH 0974/2547] sched/wait: Fix add_wait_queue() behavioral change The following cleanup commit: 50816c48997a ("sched/wait: Standardize internal naming of wait-queue entries") ... unintentionally changed the behavior of add_wait_queue() from inserting the wait entry at the head of the wait queue to the tail of the wait queue. Beyond a negative performance impact this change in behavior theoretically also breaks wait queues which mix exclusive and non-exclusive waiters, as non-exclusive waiters will not be woken up if they are queued behind enough exclusive waiters. Signed-off-by: Omar Sandoval Reviewed-by: Jens Axboe Acked-by: Peter Zijlstra Cc: Linus Torvalds Cc: Thomas Gleixner Cc: kernel-team@fb.com Fixes: ("sched/wait: Standardize internal naming of wait-queue entries") Link: http://lkml.kernel.org/r/a16c8ccffd39bd08fdaa45a5192294c784b803a7.1512544324.git.osandov@fb.com Signed-off-by: Ingo Molnar --- kernel/sched/wait.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/sched/wait.c b/kernel/sched/wait.c index 98feab7933c7..929ecb7d6b78 100644 --- a/kernel/sched/wait.c +++ b/kernel/sched/wait.c @@ -27,7 +27,7 @@ void add_wait_queue(struct wait_queue_head *wq_head, struct wait_queue_entry *wq wq_entry->flags &= ~WQ_FLAG_EXCLUSIVE; spin_lock_irqsave(&wq_head->lock, flags); - __add_wait_queue_entry_tail(wq_head, wq_entry); + __add_wait_queue(wq_head, wq_entry); spin_unlock_irqrestore(&wq_head->lock, flags); } EXPORT_SYMBOL(add_wait_queue); -- GitLab From a4c3c04974d648ee6e1a09ef4131eb32a02ab494 Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Thu, 16 Nov 2017 15:21:52 +0100 Subject: [PATCH 0975/2547] sched/fair: Update and fix the runnable propagation rule Unlike running, the runnable part can't be directly propagated through the hierarchy when we migrate a task. The main reason is that runnable time can be shared with other sched_entities that stay on the rq and this runnable time will also remain on prev cfs_rq and must not be removed. Instead, we can estimate what should be the new runnable of the prev cfs_rq and check that this estimation stay in a possible range. The prop_runnable_sum is a good estimation when adding runnable_sum but fails most often when we remove it. Instead, we could use the formula below instead: gcfs_rq's runnable_sum = gcfs_rq->avg.load_sum / gcfs_rq->load.weight which assumes that tasks are equally runnable which is not true but easy to compute. Beside these estimates, we have several simple rules that help us to filter out wrong ones: - ge->avg.runnable_sum <= than LOAD_AVG_MAX - ge->avg.runnable_sum >= ge->avg.running_sum (ge->avg.util_sum << LOAD_AVG_MAX) - ge->avg.runnable_sum can't increase when we detach a task The effect of these fixes is better cgroups balancing. Signed-off-by: Vincent Guittot Signed-off-by: Peter Zijlstra (Intel) Acked-by: Peter Zijlstra (Intel) Cc: Ben Segall Cc: Chris Mason Cc: Dietmar Eggemann Cc: Josef Bacik Cc: Linus Torvalds Cc: Mike Galbraith Cc: Morten Rasmussen Cc: Paul Turner Cc: Peter Zijlstra Cc: Tejun Heo Cc: Thomas Gleixner Cc: Yuyang Du Link: http://lkml.kernel.org/r/1510842112-21028-1-git-send-email-vincent.guittot@linaro.org Signed-off-by: Ingo Molnar --- kernel/sched/fair.c | 102 +++++++++++++++++++++++++++++++------------- 1 file changed, 73 insertions(+), 29 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 4037e19bbca2..2fe3aa853e4d 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -3413,9 +3413,9 @@ void set_task_rq_fair(struct sched_entity *se, * _IFF_ we look at the pure running and runnable sums. Because they * represent the very same entity, just at different points in the hierarchy. * - * - * Per the above update_tg_cfs_util() is trivial (and still 'wrong') and - * simply copies the running sum over. + * Per the above update_tg_cfs_util() is trivial and simply copies the running + * sum over (but still wrong, because the group entity and group rq do not have + * their PELT windows aligned). * * However, update_tg_cfs_runnable() is more complex. So we have: * @@ -3424,11 +3424,11 @@ void set_task_rq_fair(struct sched_entity *se, * And since, like util, the runnable part should be directly transferable, * the following would _appear_ to be the straight forward approach: * - * grq->avg.load_avg = grq->load.weight * grq->avg.running_avg (3) + * grq->avg.load_avg = grq->load.weight * grq->avg.runnable_avg (3) * * And per (1) we have: * - * ge->avg.running_avg == grq->avg.running_avg + * ge->avg.runnable_avg == grq->avg.runnable_avg * * Which gives: * @@ -3447,27 +3447,28 @@ void set_task_rq_fair(struct sched_entity *se, * to (shortly) return to us. This only works by keeping the weights as * integral part of the sum. We therefore cannot decompose as per (3). * - * OK, so what then? + * Another reason this doesn't work is that runnable isn't a 0-sum entity. + * Imagine a rq with 2 tasks that each are runnable 2/3 of the time. Then the + * rq itself is runnable anywhere between 2/3 and 1 depending on how the + * runnable section of these tasks overlap (or not). If they were to perfectly + * align the rq as a whole would be runnable 2/3 of the time. If however we + * always have at least 1 runnable task, the rq as a whole is always runnable. * + * So we'll have to approximate.. :/ * - * Another way to look at things is: + * Given the constraint: * - * grq->avg.load_avg = \Sum se->avg.load_avg + * ge->avg.running_sum <= ge->avg.runnable_sum <= LOAD_AVG_MAX * - * Therefore, per (2): + * We can construct a rule that adds runnable to a rq by assuming minimal + * overlap. * - * grq->avg.load_avg = \Sum se->load.weight * se->avg.runnable_avg + * On removal, we'll assume each task is equally runnable; which yields: * - * And the very thing we're propagating is a change in that sum (someone - * joined/left). So we can easily know the runnable change, which would be, per - * (2) the already tracked se->load_avg divided by the corresponding - * se->weight. + * grq->avg.runnable_sum = grq->avg.load_sum / grq->load.weight * - * Basically (4) but in differential form: + * XXX: only do this for the part of runnable > running ? * - * d(runnable_avg) += se->avg.load_avg / se->load.weight - * (5) - * ge->avg.load_avg += ge->load.weight * d(runnable_avg) */ static inline void @@ -3479,6 +3480,14 @@ update_tg_cfs_util(struct cfs_rq *cfs_rq, struct sched_entity *se, struct cfs_rq if (!delta) return; + /* + * The relation between sum and avg is: + * + * LOAD_AVG_MAX - 1024 + sa->period_contrib + * + * however, the PELT windows are not aligned between grq and gse. + */ + /* Set new sched_entity's utilization */ se->avg.util_avg = gcfs_rq->avg.util_avg; se->avg.util_sum = se->avg.util_avg * LOAD_AVG_MAX; @@ -3491,33 +3500,68 @@ update_tg_cfs_util(struct cfs_rq *cfs_rq, struct sched_entity *se, struct cfs_rq static inline void update_tg_cfs_runnable(struct cfs_rq *cfs_rq, struct sched_entity *se, struct cfs_rq *gcfs_rq) { - long runnable_sum = gcfs_rq->prop_runnable_sum; - long runnable_load_avg, load_avg; - s64 runnable_load_sum, load_sum; + long delta_avg, running_sum, runnable_sum = gcfs_rq->prop_runnable_sum; + unsigned long runnable_load_avg, load_avg; + u64 runnable_load_sum, load_sum = 0; + s64 delta_sum; if (!runnable_sum) return; gcfs_rq->prop_runnable_sum = 0; + if (runnable_sum >= 0) { + /* + * Add runnable; clip at LOAD_AVG_MAX. Reflects that until + * the CPU is saturated running == runnable. + */ + runnable_sum += se->avg.load_sum; + runnable_sum = min(runnable_sum, (long)LOAD_AVG_MAX); + } else { + /* + * Estimate the new unweighted runnable_sum of the gcfs_rq by + * assuming all tasks are equally runnable. + */ + if (scale_load_down(gcfs_rq->load.weight)) { + load_sum = div_s64(gcfs_rq->avg.load_sum, + scale_load_down(gcfs_rq->load.weight)); + } + + /* But make sure to not inflate se's runnable */ + runnable_sum = min(se->avg.load_sum, load_sum); + } + + /* + * runnable_sum can't be lower than running_sum + * As running sum is scale with cpu capacity wehreas the runnable sum + * is not we rescale running_sum 1st + */ + running_sum = se->avg.util_sum / + arch_scale_cpu_capacity(NULL, cpu_of(rq_of(cfs_rq))); + runnable_sum = max(runnable_sum, running_sum); + load_sum = (s64)se_weight(se) * runnable_sum; load_avg = div_s64(load_sum, LOAD_AVG_MAX); - add_positive(&se->avg.load_sum, runnable_sum); - add_positive(&se->avg.load_avg, load_avg); + delta_sum = load_sum - (s64)se_weight(se) * se->avg.load_sum; + delta_avg = load_avg - se->avg.load_avg; - add_positive(&cfs_rq->avg.load_avg, load_avg); - add_positive(&cfs_rq->avg.load_sum, load_sum); + se->avg.load_sum = runnable_sum; + se->avg.load_avg = load_avg; + add_positive(&cfs_rq->avg.load_avg, delta_avg); + add_positive(&cfs_rq->avg.load_sum, delta_sum); runnable_load_sum = (s64)se_runnable(se) * runnable_sum; runnable_load_avg = div_s64(runnable_load_sum, LOAD_AVG_MAX); + delta_sum = runnable_load_sum - se_weight(se) * se->avg.runnable_load_sum; + delta_avg = runnable_load_avg - se->avg.runnable_load_avg; - add_positive(&se->avg.runnable_load_sum, runnable_sum); - add_positive(&se->avg.runnable_load_avg, runnable_load_avg); + se->avg.runnable_load_sum = runnable_sum; + se->avg.runnable_load_avg = runnable_load_avg; if (se->on_rq) { - add_positive(&cfs_rq->avg.runnable_load_avg, runnable_load_avg); - add_positive(&cfs_rq->avg.runnable_load_sum, runnable_load_sum); + add_positive(&cfs_rq->avg.runnable_load_avg, delta_avg); + add_positive(&cfs_rq->avg.runnable_load_sum, delta_sum); } } -- GitLab From af97a77bc01ce49a466f9d4c0125479e2e2230b6 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 6 Dec 2017 09:50:08 +0000 Subject: [PATCH 0976/2547] efi: Move some sysfs files to be read-only by root Thanks to the scripts/leaking_addresses.pl script, it was found that some EFI values should not be readable by non-root users. So make them root-only, and to do that, add a __ATTR_RO_MODE() macro to make this easier, and use it in other places at the same time. Reported-by: Linus Torvalds Tested-by: Dave Young Signed-off-by: Greg Kroah-Hartman Signed-off-by: Ard Biesheuvel Cc: H. Peter Anvin Cc: Matt Fleming Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-efi@vger.kernel.org Cc: stable Link: http://lkml.kernel.org/r/20171206095010.24170-2-ard.biesheuvel@linaro.org Signed-off-by: Ingo Molnar --- drivers/firmware/efi/efi.c | 3 +-- drivers/firmware/efi/esrt.c | 15 ++++++--------- drivers/firmware/efi/runtime-map.c | 10 +++++----- include/linux/sysfs.h | 6 ++++++ 4 files changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c index f70febf680c3..c3eefa126e3b 100644 --- a/drivers/firmware/efi/efi.c +++ b/drivers/firmware/efi/efi.c @@ -143,8 +143,7 @@ static ssize_t systab_show(struct kobject *kobj, return str - buf; } -static struct kobj_attribute efi_attr_systab = - __ATTR(systab, 0400, systab_show, NULL); +static struct kobj_attribute efi_attr_systab = __ATTR_RO_MODE(systab, 0400); #define EFI_FIELD(var) efi.var diff --git a/drivers/firmware/efi/esrt.c b/drivers/firmware/efi/esrt.c index bd7ed3c1148a..7aae2483fcb9 100644 --- a/drivers/firmware/efi/esrt.c +++ b/drivers/firmware/efi/esrt.c @@ -106,7 +106,7 @@ static const struct sysfs_ops esre_attr_ops = { }; /* Generic ESRT Entry ("ESRE") support. */ -static ssize_t esre_fw_class_show(struct esre_entry *entry, char *buf) +static ssize_t fw_class_show(struct esre_entry *entry, char *buf) { char *str = buf; @@ -117,18 +117,16 @@ static ssize_t esre_fw_class_show(struct esre_entry *entry, char *buf) return str - buf; } -static struct esre_attribute esre_fw_class = __ATTR(fw_class, 0400, - esre_fw_class_show, NULL); +static struct esre_attribute esre_fw_class = __ATTR_RO_MODE(fw_class, 0400); #define esre_attr_decl(name, size, fmt) \ -static ssize_t esre_##name##_show(struct esre_entry *entry, char *buf) \ +static ssize_t name##_show(struct esre_entry *entry, char *buf) \ { \ return sprintf(buf, fmt "\n", \ le##size##_to_cpu(entry->esre.esre1->name)); \ } \ \ -static struct esre_attribute esre_##name = __ATTR(name, 0400, \ - esre_##name##_show, NULL) +static struct esre_attribute esre_##name = __ATTR_RO_MODE(name, 0400) esre_attr_decl(fw_type, 32, "%u"); esre_attr_decl(fw_version, 32, "%u"); @@ -193,14 +191,13 @@ static int esre_create_sysfs_entry(void *esre, int entry_num) /* support for displaying ESRT fields at the top level */ #define esrt_attr_decl(name, size, fmt) \ -static ssize_t esrt_##name##_show(struct kobject *kobj, \ +static ssize_t name##_show(struct kobject *kobj, \ struct kobj_attribute *attr, char *buf)\ { \ return sprintf(buf, fmt "\n", le##size##_to_cpu(esrt->name)); \ } \ \ -static struct kobj_attribute esrt_##name = __ATTR(name, 0400, \ - esrt_##name##_show, NULL) +static struct kobj_attribute esrt_##name = __ATTR_RO_MODE(name, 0400) esrt_attr_decl(fw_resource_count, 32, "%u"); esrt_attr_decl(fw_resource_count_max, 32, "%u"); diff --git a/drivers/firmware/efi/runtime-map.c b/drivers/firmware/efi/runtime-map.c index 8e64b77aeac9..f377609ff141 100644 --- a/drivers/firmware/efi/runtime-map.c +++ b/drivers/firmware/efi/runtime-map.c @@ -63,11 +63,11 @@ static ssize_t map_attr_show(struct kobject *kobj, struct attribute *attr, return map_attr->show(entry, buf); } -static struct map_attribute map_type_attr = __ATTR_RO(type); -static struct map_attribute map_phys_addr_attr = __ATTR_RO(phys_addr); -static struct map_attribute map_virt_addr_attr = __ATTR_RO(virt_addr); -static struct map_attribute map_num_pages_attr = __ATTR_RO(num_pages); -static struct map_attribute map_attribute_attr = __ATTR_RO(attribute); +static struct map_attribute map_type_attr = __ATTR_RO_MODE(type, 0400); +static struct map_attribute map_phys_addr_attr = __ATTR_RO_MODE(phys_addr, 0400); +static struct map_attribute map_virt_addr_attr = __ATTR_RO_MODE(virt_addr, 0400); +static struct map_attribute map_num_pages_attr = __ATTR_RO_MODE(num_pages, 0400); +static struct map_attribute map_attribute_attr = __ATTR_RO_MODE(attribute, 0400); /* * These are default attributes that are added for every memmap entry. diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h index e32dfe098e82..40839c02d28c 100644 --- a/include/linux/sysfs.h +++ b/include/linux/sysfs.h @@ -117,6 +117,12 @@ struct attribute_group { .show = _name##_show, \ } +#define __ATTR_RO_MODE(_name, _mode) { \ + .attr = { .name = __stringify(_name), \ + .mode = VERIFY_OCTAL_PERMISSIONS(_mode) }, \ + .show = _name##_show, \ +} + #define __ATTR_WO(_name) { \ .attr = { .name = __stringify(_name), .mode = S_IWUSR }, \ .store = _name##_store, \ -- GitLab From 89c5a2d34bda58319e3075e8e7dd727ea25a435c Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Wed, 6 Dec 2017 09:50:09 +0000 Subject: [PATCH 0977/2547] efi/esrt: Use memunmap() instead of kfree() to free the remapping The remapping result of memremap() should be freed with memunmap(), not kfree(). Signed-off-by: Pan Bian Signed-off-by: Ard Biesheuvel Cc: Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Matt Fleming Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-efi@vger.kernel.org Link: http://lkml.kernel.org/r/20171206095010.24170-3-ard.biesheuvel@linaro.org Signed-off-by: Ingo Molnar --- drivers/firmware/efi/esrt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/efi/esrt.c b/drivers/firmware/efi/esrt.c index 7aae2483fcb9..c47e0c6ec00f 100644 --- a/drivers/firmware/efi/esrt.c +++ b/drivers/firmware/efi/esrt.c @@ -428,7 +428,7 @@ static int __init esrt_sysfs_init(void) err_remove_esrt: kobject_put(esrt_kobj); err: - kfree(esrt); + memunmap(esrt); esrt = NULL; return error; } -- GitLab From 0b02e448a2ebb46eb9be4f1bdfc87112bd420cbf Mon Sep 17 00:00:00 2001 From: Dave Young Date: Wed, 6 Dec 2017 09:50:10 +0000 Subject: [PATCH 0978/2547] efi: Add comment to avoid future expanding of sysfs systab /sys/firmware/efi/systab shows several different values, it breaks sysfs one file one value design. But since there are already userspace tools depend on it eg. kexec-tools so add code comment to alert future expanding of this file. Signed-off-by: Dave Young Signed-off-by: Ard Biesheuvel Reviewed-by: Greg Kroah-Hartman Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Matt Fleming Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-efi@vger.kernel.org Link: http://lkml.kernel.org/r/20171206095010.24170-4-ard.biesheuvel@linaro.org Signed-off-by: Ingo Molnar --- drivers/firmware/efi/efi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c index c3eefa126e3b..557a47829d03 100644 --- a/drivers/firmware/efi/efi.c +++ b/drivers/firmware/efi/efi.c @@ -109,6 +109,8 @@ struct kobject *efi_kobj; /* * Let's not leave out systab information that snuck into * the efivars driver + * Note, do not add more fields in systab sysfs file as it breaks sysfs + * one value per file rule! */ static ssize_t systab_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) -- GitLab From d553d03f705721fbbfe3ca1c981812d3e488217e Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Wed, 6 Dec 2017 17:33:58 +0000 Subject: [PATCH 0979/2547] x86: Fix Sparse warnings about non-static functions Functions x86_vector_debug_show(), uv_handle_nmi() and uv_nmi_setup_common() are local to the source and do not need to be in global scope, so make them static. Fixes up various sparse warnings. Signed-off-by: Colin Ian King Acked-by: Mike Travis Cc: H. Peter Anvin Cc: Jiri Kosina Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Russ Anderson Cc: Thomas Gleixner Cc: kernel-janitors@vger.kernel.org Cc: travis@sgi.com Link: http://lkml.kernel.org/r/20171206173358.24388-1-colin.king@canonical.com Signed-off-by: Ingo Molnar --- arch/x86/kernel/apic/vector.c | 4 ++-- arch/x86/platform/uv/uv_nmi.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index 6a823a25eaff..750449152b04 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -542,8 +542,8 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, } #ifdef CONFIG_GENERIC_IRQ_DEBUGFS -void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d, - struct irq_data *irqd, int ind) +static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d, + struct irq_data *irqd, int ind) { unsigned int cpu, vector, prev_cpu, prev_vector; struct apic_chip_data *apicd; diff --git a/arch/x86/platform/uv/uv_nmi.c b/arch/x86/platform/uv/uv_nmi.c index c34bd8233f7c..5f64f30873e2 100644 --- a/arch/x86/platform/uv/uv_nmi.c +++ b/arch/x86/platform/uv/uv_nmi.c @@ -905,7 +905,7 @@ static inline void uv_call_kgdb_kdb(int cpu, struct pt_regs *regs, int master) /* * UV NMI handler */ -int uv_handle_nmi(unsigned int reason, struct pt_regs *regs) +static int uv_handle_nmi(unsigned int reason, struct pt_regs *regs) { struct uv_hub_nmi_s *hub_nmi = uv_hub_nmi; int cpu = smp_processor_id(); @@ -1013,7 +1013,7 @@ void uv_nmi_init(void) } /* Setup HUB NMI info */ -void __init uv_nmi_setup_common(bool hubbed) +static void __init uv_nmi_setup_common(bool hubbed) { int size = sizeof(void *) * (1 << NODES_SHIFT); int cpu; -- GitLab From a821df3f1af72aa6a0d573eea94a7dd2613e9f4e Mon Sep 17 00:00:00 2001 From: Ronnie Sahlberg Date: Tue, 21 Nov 2017 09:36:33 +1100 Subject: [PATCH 0980/2547] cifs: fix NULL deref in SMB2_read Signed-off-by: Ronnie Sahlberg Reviewed-by: Pavel Shilovsky CC: Stable Signed-off-by: Steve French --- fs/cifs/smb2pdu.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c index 5331631386a2..01346b8b6edb 100644 --- a/fs/cifs/smb2pdu.c +++ b/fs/cifs/smb2pdu.c @@ -2678,27 +2678,27 @@ SMB2_read(const unsigned int xid, struct cifs_io_parms *io_parms, cifs_small_buf_release(req); rsp = (struct smb2_read_rsp *)rsp_iov.iov_base; - shdr = get_sync_hdr(rsp); - if (shdr->Status == STATUS_END_OF_FILE) { + if (rc) { + if (rc != -ENODATA) { + cifs_stats_fail_inc(io_parms->tcon, SMB2_READ_HE); + cifs_dbg(VFS, "Send error in read = %d\n", rc); + } free_rsp_buf(resp_buftype, rsp_iov.iov_base); - return 0; + return rc == -ENODATA ? 0 : rc; } - if (rc) { - cifs_stats_fail_inc(io_parms->tcon, SMB2_READ_HE); - cifs_dbg(VFS, "Send error in read = %d\n", rc); - } else { - *nbytes = le32_to_cpu(rsp->DataLength); - if ((*nbytes > CIFS_MAX_MSGSIZE) || - (*nbytes > io_parms->length)) { - cifs_dbg(FYI, "bad length %d for count %d\n", - *nbytes, io_parms->length); - rc = -EIO; - *nbytes = 0; - } + *nbytes = le32_to_cpu(rsp->DataLength); + if ((*nbytes > CIFS_MAX_MSGSIZE) || + (*nbytes > io_parms->length)) { + cifs_dbg(FYI, "bad length %d for count %d\n", + *nbytes, io_parms->length); + rc = -EIO; + *nbytes = 0; } + shdr = get_sync_hdr(rsp); + if (*buf) { memcpy(*buf, (char *)shdr + rsp->DataOffset, *nbytes); free_rsp_buf(resp_buftype, rsp_iov.iov_base); -- GitLab From 5702591fc6a3f409f460def104ee149330dac82d Mon Sep 17 00:00:00 2001 From: Aurelien Aptel Date: Tue, 21 Nov 2017 14:47:56 +0100 Subject: [PATCH 0981/2547] CIFS: don't log STATUS_NOT_FOUND errors for DFS cifs.ko makes DFS queries regardless of the type of the server and non-DFS servers are common. This often results in superfluous logging of non-critical errors. Signed-off-by: Aurelien Aptel Signed-off-by: Steve French Reviewed-by: Ronnie Sahlberg --- fs/cifs/smb2ops.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c index e06740436b92..ed88ab8a4774 100644 --- a/fs/cifs/smb2ops.c +++ b/fs/cifs/smb2ops.c @@ -1406,7 +1406,8 @@ smb2_get_dfs_refer(const unsigned int xid, struct cifs_ses *ses, } while (rc == -EAGAIN); if (rc) { - cifs_dbg(VFS, "ioctl error in smb2_get_dfs_refer rc=%d\n", rc); + if (rc != -ENOENT) + cifs_dbg(VFS, "ioctl error in smb2_get_dfs_refer rc=%d\n", rc); goto out; } -- GitLab From cb968afc789821cdf9e17e79ef08ab90e5bae0f2 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Wed, 6 Dec 2017 16:45:47 +0000 Subject: [PATCH 0982/2547] arm64/sve: Avoid dereference of dead task_struct in KVM guest entry When deciding whether to invalidate FPSIMD state cached in the cpu, the backend function sve_flush_cpu_state() attempts to dereference __this_cpu_read(fpsimd_last_state). However, this is not safe: there is no guarantee that this task_struct pointer is still valid, because the task could have exited in the meantime. This means that we need another means to get the appropriate value of TIF_SVE for the associated task. This patch solves this issue by adding a cached copy of the TIF_SVE flag in fpsimd_last_state, which we can check without dereferencing the task pointer. In particular, although this patch is not a KVM fix per se, this means that this check is now done safely in the KVM world switch path (which is currently the only user of this code). Signed-off-by: Dave Martin Cc: Ard Biesheuvel Cc: Christoffer Dall Cc: Marc Zyngier Signed-off-by: Will Deacon --- arch/arm64/kernel/fpsimd.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index e330cc0b573d..540a1e010eb5 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -114,7 +114,12 @@ * returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so * whatever is in the FPSIMD registers is not saved to memory, but discarded. */ -static DEFINE_PER_CPU(struct fpsimd_state *, fpsimd_last_state); +struct fpsimd_last_state_struct { + struct fpsimd_state *st; + bool sve_in_use; +}; + +static DEFINE_PER_CPU(struct fpsimd_last_state_struct, fpsimd_last_state); /* Default VL for tasks that don't set it explicitly: */ static int sve_default_vl = -1; @@ -905,7 +910,7 @@ void fpsimd_thread_switch(struct task_struct *next) */ struct fpsimd_state *st = &next->thread.fpsimd_state; - if (__this_cpu_read(fpsimd_last_state) == st + if (__this_cpu_read(fpsimd_last_state.st) == st && st->cpu == smp_processor_id()) clear_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE); else @@ -997,9 +1002,12 @@ void fpsimd_signal_preserve_current_state(void) */ static void fpsimd_bind_to_cpu(void) { + struct fpsimd_last_state_struct *last = + this_cpu_ptr(&fpsimd_last_state); struct fpsimd_state *st = ¤t->thread.fpsimd_state; - __this_cpu_write(fpsimd_last_state, st); + last->st = st; + last->sve_in_use = test_thread_flag(TIF_SVE); st->cpu = smp_processor_id(); } @@ -1057,7 +1065,7 @@ void fpsimd_flush_task_state(struct task_struct *t) static inline void fpsimd_flush_cpu_state(void) { - __this_cpu_write(fpsimd_last_state, NULL); + __this_cpu_write(fpsimd_last_state.st, NULL); } /* @@ -1070,14 +1078,10 @@ static inline void fpsimd_flush_cpu_state(void) #ifdef CONFIG_ARM64_SVE void sve_flush_cpu_state(void) { - struct fpsimd_state *const fpstate = __this_cpu_read(fpsimd_last_state); - struct task_struct *tsk; - - if (!fpstate) - return; + struct fpsimd_last_state_struct const *last = + this_cpu_ptr(&fpsimd_last_state); - tsk = container_of(fpstate, struct task_struct, thread.fpsimd_state); - if (test_tsk_thread_flag(tsk, TIF_SVE)) + if (last->st && last->sve_in_use) fpsimd_flush_cpu_state(); } #endif /* CONFIG_ARM64_SVE */ @@ -1272,7 +1276,7 @@ static inline void fpsimd_pm_init(void) { } #ifdef CONFIG_HOTPLUG_CPU static int fpsimd_cpu_dead(unsigned int cpu) { - per_cpu(fpsimd_last_state, cpu) = NULL; + per_cpu(fpsimd_last_state.st, cpu) = NULL; return 0; } -- GitLab From fcf38cdf332a81b20a59e3ebaea81f6b316bbe0c Mon Sep 17 00:00:00 2001 From: Omar Sandoval Date: Tue, 5 Dec 2017 22:57:43 -0800 Subject: [PATCH 0983/2547] kyber: fix another domain token wait queue hang Commit 8cf466602028 ("kyber: fix hang on domain token wait queue") fixed a hang caused by leaving wait entries on the domain token wait queue after the __sbitmap_queue_get() retry succeeded, making that wait entry a "dud" which won't in turn wake more entries up. However, we can also get a dud entry if kyber_get_domain_token() fails once but is then called again and succeeds. This can happen if the hardware queue is rerun for some other reason, or, more likely, kyber_dispatch_request() tries the same domain twice. The fix is to remove our entry from the wait queue whenever we successfully get a token. The only complication is that we might be on one of many wait queues in the struct sbitmap_queue, but that's easily fixed by remembering which wait queue we were put on. While we're here, only initialize the wait queue entry once instead of on every wait, and use spin_lock_irq() instead of spin_lock_irqsave(), since this is always called from process context with irqs enabled. Signed-off-by: Omar Sandoval Signed-off-by: Jens Axboe --- block/kyber-iosched.c | 37 ++++++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/block/kyber-iosched.c b/block/kyber-iosched.c index b4df317c2916..f95c60774ce8 100644 --- a/block/kyber-iosched.c +++ b/block/kyber-iosched.c @@ -100,9 +100,13 @@ struct kyber_hctx_data { unsigned int cur_domain; unsigned int batching; wait_queue_entry_t domain_wait[KYBER_NUM_DOMAINS]; + struct sbq_wait_state *domain_ws[KYBER_NUM_DOMAINS]; atomic_t wait_index[KYBER_NUM_DOMAINS]; }; +static int kyber_domain_wake(wait_queue_entry_t *wait, unsigned mode, int flags, + void *key); + static int rq_sched_domain(const struct request *rq) { unsigned int op = rq->cmd_flags; @@ -385,6 +389,9 @@ static int kyber_init_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) for (i = 0; i < KYBER_NUM_DOMAINS; i++) { INIT_LIST_HEAD(&khd->rqs[i]); + init_waitqueue_func_entry(&khd->domain_wait[i], + kyber_domain_wake); + khd->domain_wait[i].private = hctx; INIT_LIST_HEAD(&khd->domain_wait[i].entry); atomic_set(&khd->wait_index[i], 0); } @@ -524,35 +531,39 @@ static int kyber_get_domain_token(struct kyber_queue_data *kqd, int nr; nr = __sbitmap_queue_get(domain_tokens); - if (nr >= 0) - return nr; /* * If we failed to get a domain token, make sure the hardware queue is * run when one becomes available. Note that this is serialized on * khd->lock, but we still need to be careful about the waker. */ - if (list_empty_careful(&wait->entry)) { - init_waitqueue_func_entry(wait, kyber_domain_wake); - wait->private = hctx; + if (nr < 0 && list_empty_careful(&wait->entry)) { ws = sbq_wait_ptr(domain_tokens, &khd->wait_index[sched_domain]); + khd->domain_ws[sched_domain] = ws; add_wait_queue(&ws->wait, wait); /* * Try again in case a token was freed before we got on the wait - * queue. The waker may have already removed the entry from the - * wait queue, but list_del_init() is okay with that. + * queue. */ nr = __sbitmap_queue_get(domain_tokens); - if (nr >= 0) { - unsigned long flags; + } - spin_lock_irqsave(&ws->wait.lock, flags); - list_del_init(&wait->entry); - spin_unlock_irqrestore(&ws->wait.lock, flags); - } + /* + * If we got a token while we were on the wait queue, remove ourselves + * from the wait queue to ensure that all wake ups make forward + * progress. It's possible that the waker already deleted the entry + * between the !list_empty_careful() check and us grabbing the lock, but + * list_del_init() is okay with that. + */ + if (nr >= 0 && !list_empty_careful(&wait->entry)) { + ws = khd->domain_ws[sched_domain]; + spin_lock_irq(&ws->wait.lock); + list_del_init(&wait->entry); + spin_unlock_irq(&ws->wait.lock); } + return nr; } -- GitLab From 134059fd2775be79e26c2dff87d25cc2f6ea5626 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Wed, 6 Dec 2017 01:04:50 +0100 Subject: [PATCH 0984/2547] net: thunderx: Fix TCP/UDP checksum offload for IPv4 pkts Offload IP header checksum to NIC. This fixes a previous patch which disabled checksum offloading for both IPv4 and IPv6 packets. So L3 checksum offload was getting disabled for IPv4 pkts. And HW is dropping these pkts for some reason. Without this patch, IPv4 TSO appears to be broken: WIthout this patch I get ~16kbyte/s, with patch close to 2mbyte/s when copying files via scp from test box to my home workstation. Looking at tcpdump on sender it looks like hardware drops IPv4 TSO skbs. This patch restores performance for me, ipv6 looks good too. Fixes: fa6d7cb5d76c ("net: thunderx: Fix TCP/UDP checksum offload for IPv6 pkts") Cc: Sunil Goutham Cc: Aleksey Makarov Cc: Eric Dumazet Signed-off-by: Florian Westphal Signed-off-by: David S. Miller --- drivers/net/ethernet/cavium/thunder/nicvf_queues.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c index 8b2c31e2a2b0..a3d12dbde95b 100644 --- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c +++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c @@ -1355,6 +1355,8 @@ nicvf_sq_add_hdr_subdesc(struct nicvf *nic, struct snd_queue *sq, int qentry, /* Offload checksum calculation to HW */ if (skb->ip_summed == CHECKSUM_PARTIAL) { + if (ip.v4->version == 4) + hdr->csum_l3 = 1; /* Enable IP csum calculation */ hdr->l3_offset = skb_network_offset(skb); hdr->l4_offset = skb_transport_offset(skb); -- GitLab From cc10f8712bd688543602f3f3d052b13be4095695 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Tue, 5 Dec 2017 22:40:25 -0800 Subject: [PATCH 0985/2547] xen-netback: Fix logging message with spurious period after newline Using a period after a newline causes bad output. Signed-off-by: Joe Perches Reviewed-by: Paul Durrant Signed-off-by: David S. Miller --- drivers/net/xen-netback/interface.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/xen-netback/interface.c b/drivers/net/xen-netback/interface.c index d6dff347f896..78ebe494fef0 100644 --- a/drivers/net/xen-netback/interface.c +++ b/drivers/net/xen-netback/interface.c @@ -186,7 +186,7 @@ static int xenvif_start_xmit(struct sk_buff *skb, struct net_device *dev) /* Obtain the queue to be used to transmit this packet */ index = skb_get_queue_mapping(skb); if (index >= num_queues) { - pr_warn_ratelimited("Invalid queue %hu for packet on interface %s\n.", + pr_warn_ratelimited("Invalid queue %hu for packet on interface %s\n", index, vif->dev->name); index %= num_queues; } -- GitLab From 88edb57d1e0b262e669c5cad36646dcf5a7f37f5 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 4 Dec 2017 16:01:55 +0100 Subject: [PATCH 0986/2547] x86/vdso: Change time() prototype to match __vdso_time() gcc-8 warns that time() is an alias for __vdso_time() but the two have different prototypes: arch/x86/entry/vdso/vclock_gettime.c:327:5: error: 'time' alias between functions of incompatible types 'int(time_t *)' {aka 'int(long int *)'} and 'time_t(time_t *)' {aka 'long int(long int *)'} [-Werror=attribute-alias] int time(time_t *t) ^~~~ arch/x86/entry/vdso/vclock_gettime.c:318:16: note: aliased declaration here I could not figure out whether this is intentional, but I see that changing it to return time_t avoids the warning. Returning 'int' from time() is also a bit questionable, as it causes an overflow in y2038 even on 64-bit architectures that use a 64-bit time_t type. On 32-bit architecture with 64-bit time_t, time() should always be implement by the C library by calling a (to be added) clock_gettime() variant that takes a sufficiently wide argument. Signed-off-by: Arnd Bergmann Acked-by: Thomas Gleixner Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Mark Rutland Cc: Paul E. McKenney Cc: Peter Zijlstra Cc: Vitaly Kuznetsov Link: http://lkml.kernel.org/r/20171204150203.852959-1-arnd@arndb.de Signed-off-by: Ingo Molnar --- arch/x86/entry/vdso/vclock_gettime.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/entry/vdso/vclock_gettime.c b/arch/x86/entry/vdso/vclock_gettime.c index 11b13c4b43d5..f19856d95c60 100644 --- a/arch/x86/entry/vdso/vclock_gettime.c +++ b/arch/x86/entry/vdso/vclock_gettime.c @@ -324,5 +324,5 @@ notrace time_t __vdso_time(time_t *t) *t = result; return result; } -int time(time_t *t) +time_t time(time_t *t) __attribute__((weak, alias("__vdso_time"))); -- GitLab From 32d3e51a82d453762ef148b2c4fbc8a7ec374a88 Mon Sep 17 00:00:00 2001 From: Chris Dion Date: Wed, 6 Dec 2017 10:50:28 -0500 Subject: [PATCH 0987/2547] net_sched: use macvlan real dev trans_start in dev_trans_start() Macvlan devices are similar to vlans and do not update their own trans_start. In order for arp monitoring to work for a bond device when the slaves are macvlans, obtain its real device. Signed-off-by: Chris Dion Signed-off-by: David S. Miller --- net/sched/sch_generic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c index 3839cbbdc32b..cd1b200acae7 100644 --- a/net/sched/sch_generic.c +++ b/net/sched/sch_generic.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -277,6 +278,8 @@ unsigned long dev_trans_start(struct net_device *dev) if (is_vlan_dev(dev)) dev = vlan_dev_real_dev(dev); + else if (netif_is_macvlan(dev)) + dev = macvlan_dev_real_dev(dev); res = netdev_get_tx_queue(dev, 0)->trans_start; for (i = 1; i < dev->num_tx_queues; i++) { val = netdev_get_tx_queue(dev, i)->trans_start; -- GitLab From f3069c6d33f6ae63a1668737bc78aaaa51bff7ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?H=C3=A5kon=20Bugge?= Date: Wed, 6 Dec 2017 17:18:28 +0100 Subject: [PATCH 0988/2547] rds: Fix NULL pointer dereference in __rds_rdma_map MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a fix for syzkaller719569, where memory registration was attempted without any underlying transport being loaded. Analysis of the case reveals that it is the setsockopt() RDS_GET_MR (2) and RDS_GET_MR_FOR_DEST (7) that are vulnerable. Here is an example stack trace when the bug is hit: BUG: unable to handle kernel NULL pointer dereference at 00000000000000c0 IP: __rds_rdma_map+0x36/0x440 [rds] PGD 2f93d03067 P4D 2f93d03067 PUD 2f93d02067 PMD 0 Oops: 0000 [#1] SMP Modules linked in: bridge stp llc tun rpcsec_gss_krb5 nfsv4 dns_resolver nfs fscache rds binfmt_misc sb_edac intel_powerclamp coretemp kvm_intel kvm irqbypass crct10dif_pclmul c rc32_pclmul ghash_clmulni_intel pcbc aesni_intel crypto_simd glue_helper cryptd iTCO_wdt mei_me sg iTCO_vendor_support ipmi_si mei ipmi_devintf nfsd shpchp pcspkr i2c_i801 ioatd ma ipmi_msghandler wmi lpc_ich mfd_core auth_rpcgss nfs_acl lockd grace sunrpc ip_tables ext4 mbcache jbd2 mgag200 i2c_algo_bit drm_kms_helper ixgbe syscopyarea ahci sysfillrect sysimgblt libahci mdio fb_sys_fops ttm ptp libata sd_mod mlx4_core drm crc32c_intel pps_core megaraid_sas i2c_core dca dm_mirror dm_region_hash dm_log dm_mod CPU: 48 PID: 45787 Comm: repro_set2 Not tainted 4.14.2-3.el7uek.x86_64 #2 Hardware name: Oracle Corporation ORACLE SERVER X5-2L/ASM,MOBO TRAY,2U, BIOS 31110000 03/03/2017 task: ffff882f9190db00 task.stack: ffffc9002b994000 RIP: 0010:__rds_rdma_map+0x36/0x440 [rds] RSP: 0018:ffffc9002b997df0 EFLAGS: 00010202 RAX: 0000000000000000 RBX: ffff882fa2182580 RCX: 0000000000000000 RDX: 0000000000000000 RSI: ffffc9002b997e40 RDI: ffff882fa2182580 RBP: ffffc9002b997e30 R08: 0000000000000000 R09: 0000000000000002 R10: ffff885fb29e3838 R11: 0000000000000000 R12: ffff882fa2182580 R13: ffff882fa2182580 R14: 0000000000000002 R15: 0000000020000ffc FS: 00007fbffa20b700(0000) GS:ffff882fbfb80000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00000000000000c0 CR3: 0000002f98a66006 CR4: 00000000001606e0 Call Trace: rds_get_mr+0x56/0x80 [rds] rds_setsockopt+0x172/0x340 [rds] ? __fget_light+0x25/0x60 ? __fdget+0x13/0x20 SyS_setsockopt+0x80/0xe0 do_syscall_64+0x67/0x1b0 entry_SYSCALL64_slow_path+0x25/0x25 RIP: 0033:0x7fbff9b117f9 RSP: 002b:00007fbffa20aed8 EFLAGS: 00000293 ORIG_RAX: 0000000000000036 RAX: ffffffffffffffda RBX: 00000000000c84a4 RCX: 00007fbff9b117f9 RDX: 0000000000000002 RSI: 0000400000000114 RDI: 000000000000109b RBP: 00007fbffa20af10 R08: 0000000000000020 R09: 00007fbff9dd7860 R10: 0000000020000ffc R11: 0000000000000293 R12: 0000000000000000 R13: 00007fbffa20b9c0 R14: 00007fbffa20b700 R15: 0000000000000021 Code: 41 56 41 55 49 89 fd 41 54 53 48 83 ec 18 8b 87 f0 02 00 00 48 89 55 d0 48 89 4d c8 85 c0 0f 84 2d 03 00 00 48 8b 87 00 03 00 00 <48> 83 b8 c0 00 00 00 00 0f 84 25 03 00 0 0 48 8b 06 48 8b 56 08 The fix is to check the existence of an underlying transport in __rds_rdma_map(). Signed-off-by: Håkon Bugge Reported-by: syzbot Acked-by: Santosh Shilimkar Signed-off-by: David S. Miller --- net/rds/rdma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/rds/rdma.c b/net/rds/rdma.c index 8886f15abe90..bc2f1e0977d6 100644 --- a/net/rds/rdma.c +++ b/net/rds/rdma.c @@ -183,7 +183,7 @@ static int __rds_rdma_map(struct rds_sock *rs, struct rds_get_mr_args *args, long i; int ret; - if (rs->rs_bound_addr == 0) { + if (rs->rs_bound_addr == 0 || !rs->rs_transport) { ret = -ENOTCONN; /* XXX not a great errno */ goto out; } -- GitLab From 30f1e59550363f6be28213393407ef225150e7fe Mon Sep 17 00:00:00 2001 From: Pravin Shedge Date: Wed, 6 Dec 2017 22:28:40 +0530 Subject: [PATCH 0989/2547] drivers: net: dsa: remove duplicate includes These duplicate includes have been found with scripts/checkincludes.pl but they have been removed manually to avoid removing false positives. Signed-off-by: Pravin Shedge Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- drivers/net/dsa/bcm_sf2.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c index ea01f24f15e7..b62d47210db8 100644 --- a/drivers/net/dsa/bcm_sf2.c +++ b/drivers/net/dsa/bcm_sf2.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include -- GitLab From 7912af5c835bd86f2b0347a480e0f40e2fab30d0 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 6 Dec 2017 14:55:05 -0600 Subject: [PATCH 0990/2547] PCI: Add pci_get_domain_bus_and_slot() stub The coretemp driver build fails when CONFIG_PCI is not enabled because it uses a function that does not have a stub for that config case, so add the function stub. ../drivers/hwmon/coretemp.c: In function 'adjust_tjmax': ../drivers/hwmon/coretemp.c:250:9: error: implicit declaration of function 'pci_get_domain_bus_and_slot' [-Werror=implicit-function-declaration] struct pci_dev *host_bridge = pci_get_domain_bus_and_slot(0, 0, devfn); ../drivers/hwmon/coretemp.c:250:32: warning: initialization makes pointer from integer without a cast [enabled by default] struct pci_dev *host_bridge = pci_get_domain_bus_and_slot(0, 0, devfn); Signed-off-by: Randy Dunlap [bhelgaas: identical patch also by Arnd Bergmann ] Signed-off-by: Bjorn Helgaas Acked-by: Guenter Roeck --- include/linux/pci.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 0403894147a3..c170c9250c8b 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1674,6 +1674,9 @@ static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn) { return NULL; } +static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, + unsigned int bus, unsigned int devfn) +{ return NULL; } static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } -- GitLab From 33acc40d00bc66f2d6e84441b6c46e03bd8acfa9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 27 Nov 2017 15:46:27 +0100 Subject: [PATCH 0991/2547] of: unittest: Remove bogus overlay mutex release from overlay_data_add() overlay_data_add() never takes the special overlay mutex, so it must not be released in the error patch. Presumably the call to of_overlay_mutex_unlock() is a relic from v1 of the patch. Fixes: f948d6d8b792bb90 ("of: overlay: avoid race condition between applying multiple overlays") Signed-off-by: Geert Uytterhoeven Reviewed-by: Frank Rowand Signed-off-by: Rob Herring --- drivers/of/unittest.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index e568b1e82501..0f8052f1355c 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -2165,7 +2165,6 @@ static int __init overlay_data_add(int onum) ret = of_overlay_apply(info->np_overlay, &info->overlay_id); if (ret < 0) { pr_err("of_overlay_apply() (ret=%d), %d\n", ret, onum); - of_overlay_mutex_unlock(); goto out_free_np_overlay; } -- GitLab From e9d92e40ac9dea5a9a185fc11227f492f0b74fc7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 28 Nov 2017 09:25:23 +0100 Subject: [PATCH 0992/2547] of: Spelling s/changset/changeset/ Signed-off-by: Geert Uytterhoeven Signed-off-by: Rob Herring --- drivers/of/dynamic.c | 4 ++-- drivers/of/overlay.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/of/dynamic.c b/drivers/of/dynamic.c index c454941b34ec..ab988d88704d 100644 --- a/drivers/of/dynamic.c +++ b/drivers/of/dynamic.c @@ -695,7 +695,7 @@ int __of_changeset_apply_entries(struct of_changeset *ocs, int *ret_revert) /* * Returns 0 on success, a negative error value in case of an error. * - * If multiple changset entry notification errors occur then only the + * If multiple changeset entry notification errors occur then only the * final notification error is reported. */ int __of_changeset_apply_notify(struct of_changeset *ocs) @@ -795,7 +795,7 @@ int __of_changeset_revert_entries(struct of_changeset *ocs, int *ret_apply) } /* - * If multiple changset entry notification errors occur then only the + * If multiple changeset entry notification errors occur then only the * final notification error is reported. */ int __of_changeset_revert_notify(struct of_changeset *ocs) diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c index c150abb9049d..3036f1776efc 100644 --- a/drivers/of/overlay.c +++ b/drivers/of/overlay.c @@ -660,14 +660,14 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs) * A non-zero return value will not have created the changeset if error is from: * - parameter checks * - building the changeset - * - overlay changset pre-apply notifier + * - overlay changeset pre-apply notifier * * If an error is returned by an overlay changeset pre-apply notifier * then no further overlay changeset pre-apply notifier will be called. * * A non-zero return value will have created the changeset if error is from: * - overlay changeset entry notifier - * - overlay changset post-apply notifier + * - overlay changeset post-apply notifier * * If an error is returned by an overlay changeset post-apply notifier * then no further overlay changeset post-apply notifier will be called. @@ -871,7 +871,7 @@ static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs) * * A non-zero return value will not revert the changeset if error is from: * - parameter checks - * - overlay changset pre-remove notifier + * - overlay changeset pre-remove notifier * - overlay changeset entry revert * * If an error is returned by an overlay changeset pre-remove notifier @@ -882,7 +882,7 @@ static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs) * * A non-zero return value will revert the changeset if error is from: * - overlay changeset entry notifier - * - overlay changset post-remove notifier + * - overlay changeset post-remove notifier * * If an error is returned by an overlay changeset post-remove notifier * then no further overlay changeset post-remove notifier will be called. -- GitLab From 6de67de326041c3a450a117b2733cbedd3aab097 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 28 Nov 2017 09:26:33 +0100 Subject: [PATCH 0993/2547] of: overlay: Remove else after goto If an "if" branch is terminated by a "goto", there's no need to have an "else" statement and an indented block of code. Remove the "else" statement to simplify the code flow for the casual reviewer. Signed-off-by: Geert Uytterhoeven Signed-off-by: Rob Herring --- drivers/of/overlay.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c index 3036f1776efc..2b852a39581e 100644 --- a/drivers/of/overlay.c +++ b/drivers/of/overlay.c @@ -580,9 +580,9 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs, of_node_put(fragment->overlay); ret = -EINVAL; goto err_free_fragments; - } else { - cnt++; } + + cnt++; } } @@ -736,14 +736,13 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id) devicetree_state_flags |= DTSF_APPLY_FAIL; } goto err_free_overlay_changeset; - } else { - ret = __of_changeset_apply_notify(&ovcs->cset); - if (ret) - pr_err("overlay changeset entry notify error %d\n", - ret); - /* fall through */ } + ret = __of_changeset_apply_notify(&ovcs->cset); + if (ret) + pr_err("overlay changeset entry notify error %d\n", ret); + /* notify failure is not fatal, continue */ + list_add_tail(&ovcs->ovcs_list, &ovcs_list); *ovcs_id = ovcs->id; @@ -931,15 +930,13 @@ int of_overlay_remove(int *ovcs_id) if (ret_apply) devicetree_state_flags |= DTSF_REVERT_FAIL; goto out_unlock; - } else { - ret = __of_changeset_revert_notify(&ovcs->cset); - if (ret) { - pr_err("overlay changeset entry notify error %d\n", - ret); - /* fall through - changeset was reverted */ - } } + ret = __of_changeset_revert_notify(&ovcs->cset); + if (ret) + pr_err("overlay changeset entry notify error %d\n", ret); + /* notify failure is not fatal, continue */ + *ovcs_id = 0; ret_tmp = overlay_notify(ovcs, OF_OVERLAY_POST_REMOVE); -- GitLab From 4c9847b7375aa9d49681497f7236fdbdab02ba7a Mon Sep 17 00:00:00 2001 From: Mathieu Malaterre Date: Wed, 29 Nov 2017 21:55:15 +0100 Subject: [PATCH 0994/2547] dt-bindings: Remove leading 0x from bindings notation Improve the binding example by removing all the leading 0x to fix the following dtc warnings: Warning (unit_address_format): Node /XXX unit name should not have leading "0x" Converted using the following command: find Documentation/devicetree/bindings -name "*.txt" -exec sed -i -e 's/([^ ])\@0x([0-9a-f])/$1\@$2/g' {} + This is a follow up to commit 48c926cd3414 Signed-off-by: Mathieu Malaterre Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/ccn.txt | 2 +- .../devicetree/bindings/arm/omap/crossbar.txt | 2 +- .../bindings/arm/tegra/nvidia,tegra20-mc.txt | 2 +- .../devicetree/bindings/clock/axi-clkgen.txt | 2 +- .../bindings/clock/brcm,bcm2835-aux-clock.txt | 2 +- .../devicetree/bindings/clock/exynos4-clock.txt | 2 +- .../devicetree/bindings/clock/exynos5250-clock.txt | 2 +- .../devicetree/bindings/clock/exynos5410-clock.txt | 2 +- .../devicetree/bindings/clock/exynos5420-clock.txt | 2 +- .../devicetree/bindings/clock/exynos5440-clock.txt | 2 +- .../bindings/clock/ti-keystone-pllctrl.txt | 2 +- .../devicetree/bindings/clock/zx296702-clk.txt | 4 ++-- .../devicetree/bindings/crypto/fsl-sec4.txt | 4 ++-- .../bindings/devfreq/event/rockchip-dfi.txt | 2 +- .../devicetree/bindings/display/atmel,lcdc.txt | 4 ++-- .../devicetree/bindings/dma/qcom_hidma_mgmt.txt | 4 ++-- Documentation/devicetree/bindings/dma/zxdma.txt | 2 +- .../devicetree/bindings/gpio/gpio-altera.txt | 2 +- Documentation/devicetree/bindings/i2c/i2c-jz4780.txt | 2 +- .../devicetree/bindings/iio/pressure/hp03.txt | 2 +- .../bindings/input/touchscreen/bu21013.txt | 2 +- .../bindings/interrupt-controller/arm,gic.txt | 4 ++-- .../bindings/interrupt-controller/img,meta-intc.txt | 2 +- .../bindings/interrupt-controller/img,pdc-intc.txt | 2 +- .../interrupt-controller/st,spear3xx-shirq.txt | 2 +- .../devicetree/bindings/mailbox/altera-mailbox.txt | 6 +++--- .../bindings/mailbox/brcm,iproc-pdc-mbox.txt | 2 +- .../devicetree/bindings/media/exynos5-gsc.txt | 2 +- .../devicetree/bindings/media/mediatek-vcodec.txt | 2 +- Documentation/devicetree/bindings/media/rcar_vin.txt | 2 +- .../devicetree/bindings/media/samsung-fimc.txt | 2 +- .../devicetree/bindings/media/sh_mobile_ceu.txt | 2 +- .../devicetree/bindings/media/video-interfaces.txt | 10 +++++----- .../bindings/memory-controllers/ti/emif.txt | 2 +- .../devicetree/bindings/mfd/ti-keystone-devctrl.txt | 2 +- .../devicetree/bindings/misc/brcm,kona-smc.txt | 2 +- .../devicetree/bindings/mmc/brcm,kona-sdhci.txt | 2 +- .../devicetree/bindings/mmc/brcm,sdhci-iproc.txt | 2 +- .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 4 ++-- Documentation/devicetree/bindings/mtd/gpmc-nor.txt | 6 +++--- Documentation/devicetree/bindings/mtd/mtk-nand.txt | 2 +- Documentation/devicetree/bindings/net/altera_tse.txt | 4 ++-- Documentation/devicetree/bindings/net/mdio.txt | 2 +- .../devicetree/bindings/net/socfpga-dwmac.txt | 2 +- Documentation/devicetree/bindings/nios2/nios2.txt | 2 +- .../devicetree/bindings/pci/altera-pcie.txt | 2 +- .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 2 +- .../devicetree/bindings/pci/hisilicon-pcie.txt | 2 +- .../devicetree/bindings/phy/sun4i-usb-phy.txt | 2 +- .../bindings/pinctrl/brcm,cygnus-pinmux.txt | 2 +- .../devicetree/bindings/pinctrl/pinctrl-atlas7.txt | 4 ++-- .../devicetree/bindings/pinctrl/pinctrl-sirf.txt | 2 +- .../devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 4 ++-- .../devicetree/bindings/regulator/regulator.txt | 2 +- .../devicetree/bindings/serial/efm32-uart.txt | 2 +- .../bindings/serio/allwinner,sun4i-ps2.txt | 2 +- .../bindings/soc/ti/keystone-navigator-qmss.txt | 2 +- .../devicetree/bindings/sound/adi,axi-i2s.txt | 2 +- .../devicetree/bindings/sound/adi,axi-spdif-tx.txt | 2 +- Documentation/devicetree/bindings/sound/ak4613.txt | 2 +- Documentation/devicetree/bindings/sound/ak4642.txt | 2 +- Documentation/devicetree/bindings/sound/max98371.txt | 2 +- Documentation/devicetree/bindings/sound/max9867.txt | 2 +- .../devicetree/bindings/sound/renesas,fsi.txt | 2 +- .../devicetree/bindings/sound/rockchip-spdif.txt | 2 +- .../devicetree/bindings/sound/st,sti-asoc-card.txt | 8 ++++---- Documentation/devicetree/bindings/spi/efm32-spi.txt | 2 +- .../devicetree/bindings/thermal/thermal.txt | 12 ++++++------ Documentation/devicetree/bindings/ufs/ufs-qcom.txt | 4 ++-- .../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 2 +- Documentation/devicetree/bindings/usb/ehci-st.txt | 2 +- Documentation/devicetree/bindings/usb/ohci-st.txt | 2 +- .../bindings/watchdog/ingenic,jz4740-wdt.txt | 2 +- 73 files changed, 99 insertions(+), 99 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/ccn.txt b/Documentation/devicetree/bindings/arm/ccn.txt index 29801456c9ee..43b5a71a5a9d 100644 --- a/Documentation/devicetree/bindings/arm/ccn.txt +++ b/Documentation/devicetree/bindings/arm/ccn.txt @@ -15,7 +15,7 @@ Required properties: Example: - ccn@0x2000000000 { + ccn@2000000000 { compatible = "arm,ccn-504"; reg = <0x20 0x00000000 0 0x1000000>; interrupts = <0 181 4>; diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt index bb5727ae004a..ecb360ed0e33 100644 --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt @@ -49,7 +49,7 @@ An interrupt consumer on an SoC using crossbar will use: interrupts = Example: - device_x@0x4a023000 { + device_x@4a023000 { /* Crossbar 8 used */ interrupts = ; ... diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt index 866d93421eba..f9632bacbd04 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt @@ -8,7 +8,7 @@ Required properties: - interrupts : Should contain MC General interrupt. Example: - memory-controller@0x7000f000 { + memory-controller@7000f000 { compatible = "nvidia,tegra20-mc"; reg = <0x7000f000 0x024 0x7000f03c 0x3c4>; diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/Documentation/devicetree/bindings/clock/axi-clkgen.txt index fb40da303d25..aca94fe9416f 100644 --- a/Documentation/devicetree/bindings/clock/axi-clkgen.txt +++ b/Documentation/devicetree/bindings/clock/axi-clkgen.txt @@ -17,7 +17,7 @@ Optional properties: - clock-output-names : From common clock binding. Example: - clock@0xff000000 { + clock@ff000000 { compatible = "adi,axi-clkgen"; #clock-cells = <0>; reg = <0xff000000 0x1000>; diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt b/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt index 7a837d2182ac..4acfc8f641b6 100644 --- a/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt +++ b/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt @@ -23,7 +23,7 @@ Example: clocks = <&clk_osc>; }; - aux: aux@0x7e215004 { + aux: aux@7e215004 { compatible = "brcm,bcm2835-aux"; #clock-cells = <1>; reg = <0x7e215000 0x8>; diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index bc61c952cb0b..17bb11365354 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -24,7 +24,7 @@ tree sources. Example 1: An example of a clock controller node is listed below. - clock: clock-controller@0x10030000 { + clock: clock-controller@10030000 { compatible = "samsung,exynos4210-clock"; reg = <0x10030000 0x20000>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 536eacd1063f..aff266a12eeb 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -22,7 +22,7 @@ tree sources. Example 1: An example of a clock controller node is listed below. - clock: clock-controller@0x10010000 { + clock: clock-controller@10010000 { compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt index 4527de3ea205..c68b0d29b3d0 100644 --- a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt @@ -30,7 +30,7 @@ Example 1: An example of a clock controller node is listed below. #clock-cells = <0>; }; - clock: clock-controller@0x10010000 { + clock: clock-controller@10010000 { compatible = "samsung,exynos5410-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index d54f42cf0440..717a7b1531c7 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -23,7 +23,7 @@ tree sources. Example 1: An example of a clock controller node is listed below. - clock: clock-controller@0x10010000 { + clock: clock-controller@10010000 { compatible = "samsung,exynos5420-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt index 5f7005f73058..c7d227c31e95 100644 --- a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt @@ -21,7 +21,7 @@ tree sources. Example: An example of a clock controller node is listed below. - clock: clock-controller@0x10010000 { + clock: clock-controller@10010000 { compatible = "samsung,exynos5440-clock"; reg = <0x160000 0x10000>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt b/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt index 3e6a81e99804..c35cb6c4af4d 100644 --- a/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt +++ b/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt @@ -14,7 +14,7 @@ Required properties: Example: -pllctrl: pll-controller@0x02310000 { +pllctrl: pll-controller@02310000 { compatible = "ti,keystone-pllctrl", "syscon"; reg = <0x02310000 0x200>; }; diff --git a/Documentation/devicetree/bindings/clock/zx296702-clk.txt b/Documentation/devicetree/bindings/clock/zx296702-clk.txt index e85ecb510d56..5c91c9e4f1be 100644 --- a/Documentation/devicetree/bindings/clock/zx296702-clk.txt +++ b/Documentation/devicetree/bindings/clock/zx296702-clk.txt @@ -20,13 +20,13 @@ ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h for the full list of zx296702 clock IDs. -topclk: topcrm@0x09800000 { +topclk: topcrm@09800000 { compatible = "zte,zx296702-topcrm-clk"; reg = <0x09800000 0x1000>; #clock-cells = <1>; }; -uart0: serial@0x09405000 { +uart0: serial@09405000 { compatible = "zte,zx296702-uart"; reg = <0x09405000 0x1000>; interrupts = ; diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt index 7aef0eae58d4..76aec8a3724d 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt @@ -456,7 +456,7 @@ System ON/OFF key driver Definition: this is phandle to the register map node. EXAMPLE: - snvs-pwrkey@0x020cc000 { + snvs-pwrkey@020cc000 { compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = <0 4 0x4> @@ -545,7 +545,7 @@ FULL EXAMPLE interrupts = <93 2>; }; - snvs-pwrkey@0x020cc000 { + snvs-pwrkey@020cc000 { compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&sec_mon>; interrupts = <0 4 0x4>; diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt index 001dd63979a9..148191b0fc15 100644 --- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt +++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt @@ -9,7 +9,7 @@ Required properties: - clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon"; Example: - dfi: dfi@0xff630000 { + dfi: dfi@ff630000 { compatible = "rockchip,rk3399-dfi"; reg = <0x00 0xff630000 0x00 0x4000>; rockchip,pmu = <&pmugrf>; diff --git a/Documentation/devicetree/bindings/display/atmel,lcdc.txt b/Documentation/devicetree/bindings/display/atmel,lcdc.txt index 1a21202778ee..acb5a0132127 100644 --- a/Documentation/devicetree/bindings/display/atmel,lcdc.txt +++ b/Documentation/devicetree/bindings/display/atmel,lcdc.txt @@ -27,7 +27,7 @@ Optional properties: Example: - fb0: fb@0x00500000 { + fb0: fb@00500000 { compatible = "atmel,at91sam9g45-lcdc"; reg = <0x00500000 0x1000>; interrupts = <23 3 0>; @@ -41,7 +41,7 @@ Example: Example for fixed framebuffer memory: - fb0: fb@0x00500000 { + fb0: fb@00500000 { compatible = "atmel,at91sam9263-lcdc"; reg = <0x00700000 0x1000 0x70000000 0x200000>; [...] diff --git a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt index 55492c264d17..b3408cc57be6 100644 --- a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt +++ b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt @@ -73,7 +73,7 @@ Hypervisor OS configuration: max-read-transactions = <31>; channel-reset-timeout-cycles = <0x500>; - hidma_24: dma-controller@0x5c050000 { + hidma_24: dma-controller@5c050000 { compatible = "qcom,hidma-1.0"; reg = <0 0x5c050000 0x0 0x1000>, <0 0x5c0b0000 0x0 0x1000>; @@ -85,7 +85,7 @@ Hypervisor OS configuration: Guest OS configuration: - hidma_24: dma-controller@0x5c050000 { + hidma_24: dma-controller@5c050000 { compatible = "qcom,hidma-1.0"; reg = <0 0x5c050000 0x0 0x1000>, <0 0x5c0b0000 0x0 0x1000>; diff --git a/Documentation/devicetree/bindings/dma/zxdma.txt b/Documentation/devicetree/bindings/dma/zxdma.txt index abec59f35fde..0ab80f69e566 100644 --- a/Documentation/devicetree/bindings/dma/zxdma.txt +++ b/Documentation/devicetree/bindings/dma/zxdma.txt @@ -13,7 +13,7 @@ Required properties: Example: Controller: - dma: dma-controller@0x09c00000{ + dma: dma-controller@09c00000{ compatible = "zte,zx296702-dma"; reg = <0x09c00000 0x1000>; clocks = <&topclk ZX296702_DMA_ACLK>; diff --git a/Documentation/devicetree/bindings/gpio/gpio-altera.txt b/Documentation/devicetree/bindings/gpio/gpio-altera.txt index 826a7208ca93..146e554b3c67 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-altera.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-altera.txt @@ -30,7 +30,7 @@ Optional properties: Example: -gpio_altr: gpio@0xff200000 { +gpio_altr: gpio@ff200000 { compatible = "altr,pio-1.0"; reg = <0xff200000 0x10>; interrupts = <0 45 4>; diff --git a/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt b/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt index 231e4cc4008c..d4a082acf92f 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt @@ -18,7 +18,7 @@ Optional properties: Example / { - i2c4: i2c4@0x10054000 { + i2c4: i2c4@10054000 { compatible = "ingenic,jz4780-i2c"; reg = <0x10054000 0x1000>; diff --git a/Documentation/devicetree/bindings/iio/pressure/hp03.txt b/Documentation/devicetree/bindings/iio/pressure/hp03.txt index 54e7e70bcea5..831dbee7a5c3 100644 --- a/Documentation/devicetree/bindings/iio/pressure/hp03.txt +++ b/Documentation/devicetree/bindings/iio/pressure/hp03.txt @@ -10,7 +10,7 @@ Required properties: Example: -hp03@0x77 { +hp03@77 { compatible = "hoperf,hp03"; reg = <0x77>; xclr-gpio = <&portc 0 0x0>; diff --git a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt index ca5a2c86480c..56d835242af2 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt @@ -15,7 +15,7 @@ Optional properties: Example: i2c@80110000 { - bu21013_tp@0x5c { + bu21013_tp@5c { compatible = "rohm,bu21013_tp"; reg = <0x5c>; touch-gpio = <&gpio2 20 0x4>; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt index 560d8a727b8f..2f3244648646 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt @@ -155,7 +155,7 @@ Example: <0x0 0xe112f000 0 0x02000>, <0x0 0xe1140000 0 0x10000>, <0x0 0xe1160000 0 0x10000>; - v2m0: v2m@0x8000 { + v2m0: v2m@8000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x80000 0 0x1000>; @@ -163,7 +163,7 @@ Example: .... - v2mN: v2m@0x9000 { + v2mN: v2m@9000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x90000 0 0x1000>; diff --git a/Documentation/devicetree/bindings/interrupt-controller/img,meta-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/img,meta-intc.txt index 80994adab392..42431f44697f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/img,meta-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/img,meta-intc.txt @@ -71,7 +71,7 @@ Example 2: * An interrupt generating device that is wired to a Meta external * trigger block. */ - uart1: uart@0x02004c00 { + uart1: uart@02004c00 { // Interrupt source '5' that is level-sensitive. // Note that there are only two cells as specified in the // interrupt parent's '#interrupt-cells' property. diff --git a/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt index a69118550344..5dc2a55ad811 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt @@ -51,7 +51,7 @@ Example 1: /* * TZ1090 PDC block */ - pdc: pdc@0x02006000 { + pdc: pdc@02006000 { // This is an interrupt controller node. interrupt-controller; diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt b/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt index 715a013ed4bd..2ab0ea39867b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt @@ -39,7 +39,7 @@ Example: The following is an example from the SPEAr320 SoC dtsi file. -shirq: interrupt-controller@0xb3000000 { +shirq: interrupt-controller@b3000000 { compatible = "st,spear320-shirq"; reg = <0xb3000000 0x1000>; interrupts = <28 29 30 1>; diff --git a/Documentation/devicetree/bindings/mailbox/altera-mailbox.txt b/Documentation/devicetree/bindings/mailbox/altera-mailbox.txt index c2619797ce0c..49cfc8c337c4 100644 --- a/Documentation/devicetree/bindings/mailbox/altera-mailbox.txt +++ b/Documentation/devicetree/bindings/mailbox/altera-mailbox.txt @@ -14,7 +14,7 @@ Optional properties: depends on the interrupt controller parent. Example: - mbox_tx: mailbox@0x100 { + mbox_tx: mailbox@100 { compatible = "altr,mailbox-1.0"; reg = <0x100 0x8>; interrupt-parent = < &gic_0 >; @@ -22,7 +22,7 @@ Example: #mbox-cells = <1>; }; - mbox_rx: mailbox@0x200 { + mbox_rx: mailbox@200 { compatible = "altr,mailbox-1.0"; reg = <0x200 0x8>; interrupt-parent = < &gic_0 >; @@ -40,7 +40,7 @@ support only one channel).The equivalent "mbox-names" property value can be used to give a name to the communication channel to be used by the client user. Example: - mclient0: mclient0@0x400 { + mclient0: mclient0@400 { compatible = "client-1.0"; reg = <0x400 0x10>; mbox-names = "mbox-tx", "mbox-rx"; diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt index 0f3ee81d92c2..9bcdf2087625 100644 --- a/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt +++ b/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt @@ -15,7 +15,7 @@ Optional properties: - brcm,use-bcm-hdr: present if a BCM header precedes each frame. Example: - pdc0: iproc-pdc0@0x612c0000 { + pdc0: iproc-pdc0@612c0000 { compatible = "brcm,iproc-pdc-mbox"; reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */ interrupts = ; diff --git a/Documentation/devicetree/bindings/media/exynos5-gsc.txt b/Documentation/devicetree/bindings/media/exynos5-gsc.txt index 0d4fdaedc6f1..bc963a6d305a 100644 --- a/Documentation/devicetree/bindings/media/exynos5-gsc.txt +++ b/Documentation/devicetree/bindings/media/exynos5-gsc.txt @@ -17,7 +17,7 @@ Optional properties: Example: -gsc_0: gsc@0x13e00000 { +gsc_0: gsc@13e00000 { compatible = "samsung,exynos5250-gsc"; reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt index 46c15c54175d..2a615d84a682 100644 --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt @@ -68,7 +68,7 @@ vcodec_dec: vcodec@16000000 { "vdec_bus_clk_src"; }; - vcodec_enc: vcodec@0x18002000 { + vcodec_enc: vcodec@18002000 { compatible = "mediatek,mt8173-vcodec-enc"; reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt index 6e4ef8caf759..19357d0bbe65 100644 --- a/Documentation/devicetree/bindings/media/rcar_vin.txt +++ b/Documentation/devicetree/bindings/media/rcar_vin.txt @@ -44,7 +44,7 @@ Device node example vin0 = &vin0; }; - vin0: vin@0xe6ef0000 { + vin0: vin@e6ef0000 { compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; clocks = <&mstp8_clks R8A7790_CLK_VIN0>; reg = <0 0xe6ef0000 0 0x1000>; diff --git a/Documentation/devicetree/bindings/media/samsung-fimc.txt b/Documentation/devicetree/bindings/media/samsung-fimc.txt index e4e15d8d7521..48c599dacbdf 100644 --- a/Documentation/devicetree/bindings/media/samsung-fimc.txt +++ b/Documentation/devicetree/bindings/media/samsung-fimc.txt @@ -138,7 +138,7 @@ Example: }; /* MIPI CSI-2 bus IF sensor */ - s5c73m3: sensor@0x1a { + s5c73m3: sensor@1a { compatible = "samsung,s5c73m3"; reg = <0x1a>; vddio-supply = <...>; diff --git a/Documentation/devicetree/bindings/media/sh_mobile_ceu.txt b/Documentation/devicetree/bindings/media/sh_mobile_ceu.txt index 1ce4e46bcbb7..17a8e81ca0cc 100644 --- a/Documentation/devicetree/bindings/media/sh_mobile_ceu.txt +++ b/Documentation/devicetree/bindings/media/sh_mobile_ceu.txt @@ -8,7 +8,7 @@ Bindings, specific for the sh_mobile_ceu_camera.c driver: Example: -ceu0: ceu@0xfe910000 { +ceu0: ceu@fe910000 { compatible = "renesas,sh-mobile-ceu"; reg = <0xfe910000 0xa0>; interrupt-parent = <&intcs>; diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt index 3994b0143dd1..258b8dfddf48 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.txt +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt @@ -154,7 +154,7 @@ imx074 is linked to ceu0 through the MIPI CSI-2 receiver (csi2). ceu0 has a 'port' node which may indicate that at any time only one of the following data pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0. - ceu0: ceu@0xfe910000 { + ceu0: ceu@fe910000 { compatible = "renesas,sh-mobile-ceu"; reg = <0xfe910000 0xa0>; interrupts = <0x880>; @@ -193,9 +193,9 @@ pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0. }; }; - i2c0: i2c@0xfff20000 { + i2c0: i2c@fff20000 { ... - ov772x_1: camera@0x21 { + ov772x_1: camera@21 { compatible = "ovti,ov772x"; reg = <0x21>; vddio-supply = <®ulator1>; @@ -219,7 +219,7 @@ pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0. }; }; - imx074: camera@0x1a { + imx074: camera@1a { compatible = "sony,imx074"; reg = <0x1a>; vddio-supply = <®ulator1>; @@ -239,7 +239,7 @@ pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0. }; }; - csi2: csi2@0xffc90000 { + csi2: csi2@ffc90000 { compatible = "renesas,sh-mobile-csi2"; reg = <0xffc90000 0x1000>; interrupts = <0x17a0>; diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt index fd823d6091b2..152eeccbde1c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt +++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt @@ -46,7 +46,7 @@ Optional properties: Example: -emif1: emif@0x4c000000 { +emif1: emif@4c000000 { compatible = "ti,emif-4d"; ti,hwmods = "emif2"; phy-type = <1>; diff --git a/Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt b/Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt index 20963c76b4bc..71a1f5963936 100644 --- a/Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt +++ b/Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt @@ -13,7 +13,7 @@ Required properties: Example: -devctrl: device-state-control@0x02620000 { +devctrl: device-state-control@02620000 { compatible = "ti,keystone-devctrl", "syscon"; reg = <0x02620000 0x1000>; }; diff --git a/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt b/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt index 6c9f176f3571..05b47232ed9e 100644 --- a/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt +++ b/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt @@ -9,7 +9,7 @@ Required properties: - reg : Location and size of bounce buffer Example: - smc@0x3404c000 { + smc@3404c000 { compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; reg = <0x3404c000 0x400>; //1 KiB in SRAM }; diff --git a/Documentation/devicetree/bindings/mmc/brcm,kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/brcm,kona-sdhci.txt index aaba2483b4ff..7f5dd83f5bd9 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,kona-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/brcm,kona-sdhci.txt @@ -12,7 +12,7 @@ Refer to clocks/clock-bindings.txt for generic clock consumer properties. Example: -sdio2: sdio@0x3f1a0000 { +sdio2: sdio@3f1a0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1a0000 0x10000>; clocks = <&sdio3_clk>; diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt index 954561d09a8e..fa90d253dc7e 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt @@ -24,7 +24,7 @@ Optional properties: Example: -sdhci0: sdhci@0x18041000 { +sdhci0: sdhci@18041000 { compatible = "brcm,sdhci-iproc-cygnus"; reg = <0x18041000 0x100>; interrupts = ; diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt index 3a4ac401e6f9..19f5508a7569 100644 --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt @@ -55,7 +55,7 @@ Examples: [hwmod populated DMA resources] - mmc1: mmc@0x4809c000 { + mmc1: mmc@4809c000 { compatible = "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; ti,hwmods = "mmc1"; @@ -67,7 +67,7 @@ Examples: [generic DMA request binding] - mmc1: mmc@0x4809c000 { + mmc1: mmc@4809c000 { compatible = "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; ti,hwmods = "mmc1"; diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nor.txt b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt index 131d3a74d0bd..c8567b40fe13 100644 --- a/Documentation/devicetree/bindings/mtd/gpmc-nor.txt +++ b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt @@ -82,15 +82,15 @@ gpmc: gpmc@6e000000 { label = "bootloader-nor"; reg = <0 0x40000>; }; - partition@0x40000 { + partition@40000 { label = "params-nor"; reg = <0x40000 0x40000>; }; - partition@0x80000 { + partition@80000 { label = "kernel-nor"; reg = <0x80000 0x200000>; }; - partition@0x280000 { + partition@280000 { label = "filesystem-nor"; reg = <0x240000 0x7d80000>; }; diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt index dbf9e054c11c..0431841de781 100644 --- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt +++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt @@ -131,7 +131,7 @@ Example: read-only; reg = <0x00000000 0x00400000>; }; - android@0x00400000 { + android@00400000 { label = "android"; reg = <0x00400000 0x12c00000>; }; diff --git a/Documentation/devicetree/bindings/net/altera_tse.txt b/Documentation/devicetree/bindings/net/altera_tse.txt index a706297998e9..0e21df94a53f 100644 --- a/Documentation/devicetree/bindings/net/altera_tse.txt +++ b/Documentation/devicetree/bindings/net/altera_tse.txt @@ -52,7 +52,7 @@ Optional properties: Example: - tse_sub_0_eth_tse_0: ethernet@0x1,00000000 { + tse_sub_0_eth_tse_0: ethernet@1,00000000 { compatible = "altr,tse-msgdma-1.0"; reg = <0x00000001 0x00000000 0x00000400>, <0x00000001 0x00000460 0x00000020>, @@ -90,7 +90,7 @@ Example: }; }; - tse_sub_1_eth_tse_0: ethernet@0x1,00001000 { + tse_sub_1_eth_tse_0: ethernet@1,00001000 { compatible = "altr,tse-msgdma-1.0"; reg = <0x00000001 0x00001000 0x00000400>, <0x00000001 0x00001460 0x00000020>, diff --git a/Documentation/devicetree/bindings/net/mdio.txt b/Documentation/devicetree/bindings/net/mdio.txt index 96a53f89aa6e..e3e1603f256c 100644 --- a/Documentation/devicetree/bindings/net/mdio.txt +++ b/Documentation/devicetree/bindings/net/mdio.txt @@ -18,7 +18,7 @@ Example : This example shows these optional properties, plus other properties required for the TI Davinci MDIO driver. - davinci_mdio: ethernet@0x5c030000 { + davinci_mdio: ethernet@5c030000 { compatible = "ti,davinci_mdio"; reg = <0x5c030000 0x1000>; #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt index b30d04b54ee9..17d6819669c8 100644 --- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt +++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt @@ -28,7 +28,7 @@ Required properties: Example: -gmii_to_sgmii_converter: phy@0x100000240 { +gmii_to_sgmii_converter: phy@100000240 { compatible = "altr,gmii-to-sgmii-2.0"; reg = <0x00000001 0x00000240 0x00000008>, <0x00000001 0x00000200 0x00000040>; diff --git a/Documentation/devicetree/bindings/nios2/nios2.txt b/Documentation/devicetree/bindings/nios2/nios2.txt index d6d0a94cb3bb..b95e831bcba3 100644 --- a/Documentation/devicetree/bindings/nios2/nios2.txt +++ b/Documentation/devicetree/bindings/nios2/nios2.txt @@ -36,7 +36,7 @@ Optional properties: Example: -cpu@0x0 { +cpu@0 { device_type = "cpu"; compatible = "altr,nios2-1.0"; reg = <0>; diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt index 495880193adc..a1dc9366a8fc 100644 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -25,7 +25,7 @@ Optional properties: - bus-range: PCI bus numbers covered Example - pcie_0: pcie@0xc00000000 { + pcie_0: pcie@c00000000 { compatible = "altr,pcie-root-port-1.0"; reg = <0xc0000000 0x20000000>, <0xff220000 0x00004000>; diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 7b1e48bf172b..149d8f7f86b0 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -52,7 +52,7 @@ Additional required properties for imx7d-pcie: Example: - pcie@0x01000000 { + pcie@01000000 { compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; reg = <0x01ffc000 0x04000>, <0x01f00000 0x80000>; diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt index bdb7ab39d2d7..7bf9df047a1e 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -21,7 +21,7 @@ Optional properties: - dma-coherent: Present if DMA operations are coherent. Hip05 Example (note that Hip06 is the same except compatible): - pcie@0xb0080000 { + pcie@b0080000 { compatible = "hisilicon,hip05-pcie", "snps,dw-pcie"; reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>; reg-names = "rc_dbi", "config"; diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt index cbc7847dbf6c..c1ce5a0a652e 100644 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt @@ -45,7 +45,7 @@ Optional properties: - usb3_vbus-supply : regulator phandle for controller usb3 vbus Example: - usbphy: phy@0x01c13400 { + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun4i-a10-usb-phy"; /* phy base regs, phy1 pmu reg, phy2 pmu reg */ diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt index 3600d5c6c4d7..3914529a3214 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt @@ -25,7 +25,7 @@ Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt For example: - pinmux: pinmux@0x0301d0c8 { + pinmux: pinmux@0301d0c8 { compatible = "brcm,cygnus-pinmux"; reg = <0x0301d0c8 0x1b0>; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt index eecf028ff485..bf9b07016c87 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt @@ -96,14 +96,14 @@ For example, pinctrl might have subnodes like the following: For a specific board, if it wants to use sd1, it can add the following to its board-specific .dts file. -sd1: sd@0x12340000 { +sd1: sd@12340000 { pinctrl-names = "default"; pinctrl-0 = <&sd1_pmx0>; } or -sd1: sd@0x12340000 { +sd1: sd@12340000 { pinctrl-names = "default"; pinctrl-0 = <&sd1_pmx1>; } diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt index 5f55be59d914..f8420520e14b 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt @@ -41,7 +41,7 @@ For example, pinctrl might have subnodes like the following: For a specific board, if it wants to use uart2 without hardware flow control, it can add the following to its board-specific .dts file. -uart2: uart@0xb0070000 { +uart2: uart@b0070000 { pinctrl-names = "default"; pinctrl-0 = <&uart2_noflow_pins_a>; } diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index 4864e3a74de3..a01a3b8a2363 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -136,7 +136,7 @@ Example for rk3188: #size-cells = <1>; ranges; - gpio0: gpio0@0x2000a000 { + gpio0: gpio0@2000a000 { compatible = "rockchip,rk3188-gpio-bank0"; reg = <0x2000a000 0x100>; interrupts = ; @@ -149,7 +149,7 @@ Example for rk3188: #interrupt-cells = <2>; }; - gpio1: gpio1@0x2003c000 { + gpio1: gpio1@2003c000 { compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = ; diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index 378f6dc8b8bd..3cbf56ce66ea 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt @@ -107,7 +107,7 @@ regulators (twl_reg1 and twl_reg2), ... }; - mmc: mmc@0x0 { + mmc: mmc@0 { ... ... vmmc-supply = <&twl_reg1>; diff --git a/Documentation/devicetree/bindings/serial/efm32-uart.txt b/Documentation/devicetree/bindings/serial/efm32-uart.txt index 8adbab268ca3..4f8d8fde0c1c 100644 --- a/Documentation/devicetree/bindings/serial/efm32-uart.txt +++ b/Documentation/devicetree/bindings/serial/efm32-uart.txt @@ -12,7 +12,7 @@ Optional properties: Example: -uart@0x4000c400 { +uart@4000c400 { compatible = "energymicro,efm32-uart"; reg = <0x4000c400 0x400>; interrupts = <15>; diff --git a/Documentation/devicetree/bindings/serio/allwinner,sun4i-ps2.txt b/Documentation/devicetree/bindings/serio/allwinner,sun4i-ps2.txt index f311472990a7..75996b6111bb 100644 --- a/Documentation/devicetree/bindings/serio/allwinner,sun4i-ps2.txt +++ b/Documentation/devicetree/bindings/serio/allwinner,sun4i-ps2.txt @@ -14,7 +14,7 @@ Required properties: Example: - ps20: ps2@0x01c2a000 { + ps20: ps2@01c2a000 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a000 0x400>; interrupts = <0 62 4>; diff --git a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt index 64c66a5644e7..77cd42cc5f54 100644 --- a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt +++ b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt @@ -220,7 +220,7 @@ qmss: qmss@2a40000 { #address-cells = <1>; #size-cells = <1>; ranges; - pdsp0@0x2a10000 { + pdsp0@2a10000 { reg = <0x2a10000 0x1000>, <0x2a0f000 0x100>, <0x2a0c000 0x3c8>, diff --git a/Documentation/devicetree/bindings/sound/adi,axi-i2s.txt b/Documentation/devicetree/bindings/sound/adi,axi-i2s.txt index 5875ca459ed1..4248b662deff 100644 --- a/Documentation/devicetree/bindings/sound/adi,axi-i2s.txt +++ b/Documentation/devicetree/bindings/sound/adi,axi-i2s.txt @@ -21,7 +21,7 @@ please check: Example: - i2s: i2s@0x77600000 { + i2s: i2s@77600000 { compatible = "adi,axi-i2s-1.00.a"; reg = <0x77600000 0x1000>; clocks = <&clk 15>, <&audio_clock>; diff --git a/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt b/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt index 4eb7997674a0..7b664e7cb4ae 100644 --- a/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt +++ b/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt @@ -20,7 +20,7 @@ please check: Example: - spdif: spdif@0x77400000 { + spdif: spdif@77400000 { compatible = "adi,axi-spdif-tx-1.00.a"; reg = <0x77600000 0x1000>; clocks = <&clk 15>, <&audio_clock>; diff --git a/Documentation/devicetree/bindings/sound/ak4613.txt b/Documentation/devicetree/bindings/sound/ak4613.txt index 1783f9ef0930..49a2e74fd9cb 100644 --- a/Documentation/devicetree/bindings/sound/ak4613.txt +++ b/Documentation/devicetree/bindings/sound/ak4613.txt @@ -20,7 +20,7 @@ Optional properties: Example: &i2c { - ak4613: ak4613@0x10 { + ak4613: ak4613@10 { compatible = "asahi-kasei,ak4613"; reg = <0x10>; }; diff --git a/Documentation/devicetree/bindings/sound/ak4642.txt b/Documentation/devicetree/bindings/sound/ak4642.txt index 340784db6808..58e48ee97175 100644 --- a/Documentation/devicetree/bindings/sound/ak4642.txt +++ b/Documentation/devicetree/bindings/sound/ak4642.txt @@ -17,7 +17,7 @@ Optional properties: Example 1: &i2c { - ak4648: ak4648@0x12 { + ak4648: ak4648@12 { compatible = "asahi-kasei,ak4642"; reg = <0x12>; }; diff --git a/Documentation/devicetree/bindings/sound/max98371.txt b/Documentation/devicetree/bindings/sound/max98371.txt index 6c285235e64b..8b2b2704b574 100644 --- a/Documentation/devicetree/bindings/sound/max98371.txt +++ b/Documentation/devicetree/bindings/sound/max98371.txt @@ -10,7 +10,7 @@ Required properties: Example: &i2c { - max98371: max98371@0x31 { + max98371: max98371@31 { compatible = "maxim,max98371"; reg = <0x31>; }; diff --git a/Documentation/devicetree/bindings/sound/max9867.txt b/Documentation/devicetree/bindings/sound/max9867.txt index 394cd4eb17ec..b8bd914ee697 100644 --- a/Documentation/devicetree/bindings/sound/max9867.txt +++ b/Documentation/devicetree/bindings/sound/max9867.txt @@ -10,7 +10,7 @@ Required properties: Example: &i2c { - max9867: max9867@0x18 { + max9867: max9867@18 { compatible = "maxim,max9867"; reg = <0x18>; }; diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.txt b/Documentation/devicetree/bindings/sound/renesas,fsi.txt index 0d0ab51105b0..0cf0f819b823 100644 --- a/Documentation/devicetree/bindings/sound/renesas,fsi.txt +++ b/Documentation/devicetree/bindings/sound/renesas,fsi.txt @@ -20,7 +20,7 @@ Required properties: Example: -sh_fsi2: sh_fsi2@0xec230000 { +sh_fsi2: sh_fsi2@ec230000 { compatible = "renesas,sh_fsi2"; reg = <0xec230000 0x400>; interrupts = <0 146 0x4>; diff --git a/Documentation/devicetree/bindings/sound/rockchip-spdif.txt b/Documentation/devicetree/bindings/sound/rockchip-spdif.txt index 0a1dc4e1815c..ec20c1271e92 100644 --- a/Documentation/devicetree/bindings/sound/rockchip-spdif.txt +++ b/Documentation/devicetree/bindings/sound/rockchip-spdif.txt @@ -33,7 +33,7 @@ Required properties on RK3288: Example for the rk3188 SPDIF controller: -spdif: spdif@0x1011e000 { +spdif: spdif@1011e000 { compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; reg = <0x1011e000 0x2000>; interrupts = ; diff --git a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt index 40068ec0e9a5..9c1ee52fed5b 100644 --- a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt +++ b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt @@ -51,7 +51,7 @@ Optional properties: Example: - sti_uni_player1: sti-uni-player@0x8D81000 { + sti_uni_player1: sti-uni-player@8D81000 { compatible = "st,stih407-uni-player-hdmi"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; @@ -63,7 +63,7 @@ Example: st,tdm-mode = <1>; }; - sti_uni_player2: sti-uni-player@0x8D82000 { + sti_uni_player2: sti-uni-player@8D82000 { compatible = "st,stih407-uni-player-pcm-out"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; @@ -74,7 +74,7 @@ Example: dma-names = "tx"; }; - sti_uni_player3: sti-uni-player@0x8D85000 { + sti_uni_player3: sti-uni-player@8D85000 { compatible = "st,stih407-uni-player-spdif"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; @@ -85,7 +85,7 @@ Example: dma-names = "tx"; }; - sti_uni_reader1: sti-uni-reader@0x8D84000 { + sti_uni_reader1: sti-uni-reader@8D84000 { compatible = "st,stih407-uni-reader-hdmi"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; diff --git a/Documentation/devicetree/bindings/spi/efm32-spi.txt b/Documentation/devicetree/bindings/spi/efm32-spi.txt index 2c1e6a43930b..e0fa61a1be0c 100644 --- a/Documentation/devicetree/bindings/spi/efm32-spi.txt +++ b/Documentation/devicetree/bindings/spi/efm32-spi.txt @@ -19,7 +19,7 @@ Recommended properties : Example: -spi1: spi@0x4000c400 { /* USART1 */ +spi1: spi@4000c400 { /* USART1 */ #address-cells = <1>; #size-cells = <0>; compatible = "energymicro,efm32-spi"; diff --git a/Documentation/devicetree/bindings/thermal/thermal.txt b/Documentation/devicetree/bindings/thermal/thermal.txt index 88b6ea1ad290..44d7cb2cb2c0 100644 --- a/Documentation/devicetree/bindings/thermal/thermal.txt +++ b/Documentation/devicetree/bindings/thermal/thermal.txt @@ -239,7 +239,7 @@ cpus { * A simple fan controller which supports 10 speeds of operation * (represented as 0-9). */ - fan0: fan@0x48 { + fan0: fan@48 { ... cooling-min-level = <0>; cooling-max-level = <9>; @@ -252,7 +252,7 @@ ocp { /* * A simple IC with a single bandgap temperature sensor. */ - bandgap0: bandgap@0x0000ED00 { + bandgap0: bandgap@0000ED00 { ... #thermal-sensor-cells = <0>; }; @@ -330,7 +330,7 @@ ocp { /* * A simple IC with several bandgap temperature sensors. */ - bandgap0: bandgap@0x0000ED00 { + bandgap0: bandgap@0000ED00 { ... #thermal-sensor-cells = <1>; }; @@ -447,7 +447,7 @@ one thermal zone. /* * A simple IC with a single temperature sensor. */ - adc: sensor@0x49 { + adc: sensor@49 { ... #thermal-sensor-cells = <0>; }; @@ -458,7 +458,7 @@ ocp { /* * A simple IC with a single bandgap temperature sensor. */ - bandgap0: bandgap@0x0000ED00 { + bandgap0: bandgap@0000ED00 { ... #thermal-sensor-cells = <0>; }; @@ -516,7 +516,7 @@ with many sensors and many cooling devices. /* * An IC with several temperature sensor. */ - adc_dummy: sensor@0x50 { + adc_dummy: sensor@50 { ... #thermal-sensor-cells = <1>; /* sensor internal ID */ }; diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt index 1f69ee1a61ea..21d9a93db2e9 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt @@ -32,7 +32,7 @@ Optional properties: Example: - ufsphy1: ufsphy@0xfc597000 { + ufsphy1: ufsphy@fc597000 { compatible = "qcom,ufs-phy-qmp-20nm"; reg = <0xfc597000 0x800>; reg-names = "phy_mem"; @@ -53,7 +53,7 @@ Example: <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; }; - ufshc@0xfc598000 { + ufshc@fc598000 { ... phys = <&ufsphy1>; phy-names = "ufsphy"; diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index a99ed5565b26..c39dfef76a18 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -46,7 +46,7 @@ Note: If above properties are not defined it can be assumed that the supply regulators or clocks are always on. Example: - ufshc@0xfc598000 { + ufshc@fc598000 { compatible = "jedec,ufs-1.1"; reg = <0xfc598000 0x800>; interrupts = <0 28 0>; diff --git a/Documentation/devicetree/bindings/usb/ehci-st.txt b/Documentation/devicetree/bindings/usb/ehci-st.txt index 9feea6c3e4d9..065c91d955ad 100644 --- a/Documentation/devicetree/bindings/usb/ehci-st.txt +++ b/Documentation/devicetree/bindings/usb/ehci-st.txt @@ -22,7 +22,7 @@ See: Documentation/devicetree/bindings/reset/reset.txt Example: - ehci1: usb@0xfe203e00 { + ehci1: usb@fe203e00 { compatible = "st,st-ehci-300x"; reg = <0xfe203e00 0x100>; interrupts = ; diff --git a/Documentation/devicetree/bindings/usb/ohci-st.txt b/Documentation/devicetree/bindings/usb/ohci-st.txt index d893ec9131c3..44c998c16f85 100644 --- a/Documentation/devicetree/bindings/usb/ohci-st.txt +++ b/Documentation/devicetree/bindings/usb/ohci-st.txt @@ -20,7 +20,7 @@ See: Documentation/devicetree/bindings/reset/reset.txt Example: - ohci0: usb@0xfe1ffc00 { + ohci0: usb@fe1ffc00 { compatible = "st,st-ohci-300x"; reg = <0xfe1ffc00 0x100>; interrupts = ; diff --git a/Documentation/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt b/Documentation/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt index e27763ef0049..3c7a1cd13b10 100644 --- a/Documentation/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt @@ -6,7 +6,7 @@ reg: Register address and length for watchdog registers Example: -watchdog: jz4740-watchdog@0x10002000 { +watchdog: jz4740-watchdog@10002000 { compatible = "ingenic,jz4740-watchdog"; reg = <0x10002000 0x100>; }; -- GitLab From 470195f82e4ea550b7c37736a12bf3fa565295ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 29 Nov 2017 15:12:27 +0100 Subject: [PATCH 0995/2547] x86/PCI: Fix infinite loop in search for 64bit BAR placement MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Break the loop if we can't find some address space for a 64bit BAR. Signed-off-by: Christian König Signed-off-by: Bjorn Helgaas --- arch/x86/pci/fixup.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index 1e996df687a3..5328e86f73eb 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -696,8 +696,13 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev) res->end = 0xfd00000000ull - 1; /* Just grab the free area behind system memory for this */ - while ((conflict = request_resource_conflict(&iomem_resource, res))) + while ((conflict = request_resource_conflict(&iomem_resource, res))) { + if (conflict->end >= res->end) { + kfree(res); + return; + } res->start = conflict->end + 1; + } dev_info(&dev->dev, "adding root bus resource %pR\n", res); -- GitLab From a19e2696135efb471981c1ae1ec3cb2b70c41a2e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 29 Nov 2017 15:12:28 +0100 Subject: [PATCH 0996/2547] x86/PCI: Only enable a 64bit BAR on single-socket AMD Family 15h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When we have a multi-socket system, each CPU core needs the same setup. Since this is tricky to do in the fixup code, don't enable a 64bit BAR on multi-socket systems for now. Signed-off-by: Christian König Signed-off-by: Bjorn Helgaas --- arch/x86/pci/fixup.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index 5328e86f73eb..e663d6bf1328 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -665,6 +665,16 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev) unsigned i; u32 base, limit, high; struct resource *res, *conflict; + struct pci_dev *other; + + /* Check that we are the only device of that type */ + other = pci_get_device(dev->vendor, dev->device, NULL); + if (other != dev || + (other = pci_get_device(dev->vendor, dev->device, other))) { + /* This is a multi-socket system, don't touch it for now */ + pci_dev_put(other); + return; + } for (i = 0; i < 8; i++) { pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base); @@ -719,10 +729,10 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev) pci_bus_add_resource(dev->bus, res, 0); } -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar); -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar); -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar); -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar); #endif -- GitLab From ba341abd5480f41057b424a0047374aebd505f17 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 30 Nov 2017 14:29:45 +0100 Subject: [PATCH 0997/2547] dt-bindings: eeprom: at25: Grammar s/are can/can/ Signed-off-by: Geert Uytterhoeven Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/eeprom/at25.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/eeprom/at25.txt b/Documentation/devicetree/bindings/eeprom/at25.txt index 1d3447165c37..95eb65334d39 100644 --- a/Documentation/devicetree/bindings/eeprom/at25.txt +++ b/Documentation/devicetree/bindings/eeprom/at25.txt @@ -13,7 +13,7 @@ Optional properties: - spi-cpol : SPI inverse clock polarity, as per spi-bus bindings. - read-only : this parameter-less property disables writes to the eeprom -Obsolete legacy properties are can be used in place of "size", "pagesize", +Obsolete legacy properties can be used in place of "size", "pagesize", "address-width", and "read-only": - at25,byte-len : total eeprom size in bytes - at25,addr-mode : addr-mode flags, as defined in include/linux/spi/eeprom.h -- GitLab From 3bcca2c271259ab2c3b539f0afa17d0043854c01 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 30 Nov 2017 14:29:46 +0100 Subject: [PATCH 0998/2547] dt-bindings: eeprom: at25: Document device-specific compatible values Document the recommended presence of a device-specific compatible value, and list examples that are already in use or soon will be. This will allow checkpatch to validate compatible values in DTS. Update the example to match current best practices (generic node name, specific compatible value first). Signed-off-by: Geert Uytterhoeven Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/eeprom/at25.txt | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/eeprom/at25.txt b/Documentation/devicetree/bindings/eeprom/at25.txt index 95eb65334d39..e823d90b802f 100644 --- a/Documentation/devicetree/bindings/eeprom/at25.txt +++ b/Documentation/devicetree/bindings/eeprom/at25.txt @@ -1,7 +1,12 @@ EEPROMs (SPI) compatible with Atmel at25. Required properties: -- compatible : "atmel,at25". +- compatible : Should be ",", and generic value "atmel,at25". + Example "," values: + "microchip,25lc040" + "st,m95m02" + "st,m95256" + - reg : chip select number - spi-max-frequency : max spi frequency to use - pagesize : size of the eeprom page @@ -22,8 +27,8 @@ Obsolete legacy properties can be used in place of "size", "pagesize", Additional compatible properties are also allowed. Example: - at25@0 { - compatible = "atmel,at25", "st,m95256"; + eeprom@0 { + compatible = "st,m95256", "atmel,at25"; reg = <0> spi-max-frequency = <5000000>; spi-cpha; -- GitLab From 14c47b54b0d9389e3ca0718e805cdd90c5a4303a Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Sat, 2 Dec 2017 16:17:44 -0600 Subject: [PATCH 0999/2547] objtool: Fix 64-bit build on 32-bit host The new ORC unwinder breaks the build of a 64-bit kernel on a 32-bit host. Building the kernel on a i386 or x32 host fails with: orc_dump.c: In function 'orc_dump': orc_dump.c:105:26: error: passing argument 2 of 'elf_getshdrnum' from incompatible pointer type [-Werror=incompatible-pointer-types] if (elf_getshdrnum(elf, &nr_sections)) { ^ In file included from /usr/local/include/gelf.h:32:0, from elf.h:22, from warn.h:26, from orc_dump.c:20: /usr/local/include/libelf.h:304:12: note: expected 'size_t * {aka unsigned int *}' but argument is of type 'long unsigned int *' extern int elf_getshdrnum (Elf *__elf, size_t *__dst); ^~~~~~~~~~~~~~ orc_dump.c:190:17: error: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'Elf64_Sxword {aka long long int}' [-Werror=format=] printf("%s+%lx:", name, rela.r_addend); ~~^ ~~~~~~~~~~~~~ %llx Fix the build failure. Another problem is that if the user specifies HOSTCC or HOSTLD variables, they are ignored in the objtool makefile. Change the Makefile to respect these variables. Signed-off-by: Mikulas Patocka Signed-off-by: Josh Poimboeuf Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Sven Joachim Cc: Thomas Gleixner Fixes: 627fce14809b ("objtool: Add ORC unwind table generation") Link: http://lkml.kernel.org/r/19f0e64d8e07e30a7b307cd010eb780c404fe08d.1512252895.git.jpoimboe@redhat.com Signed-off-by: Ingo Molnar --- tools/objtool/Makefile | 8 +++++--- tools/objtool/orc_dump.c | 7 ++++--- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/tools/objtool/Makefile b/tools/objtool/Makefile index 0f94af3ccaaa..ae0272f9a091 100644 --- a/tools/objtool/Makefile +++ b/tools/objtool/Makefile @@ -7,9 +7,11 @@ ARCH := x86 endif # always use the host compiler -CC = gcc -LD = ld -AR = ar +HOSTCC ?= gcc +HOSTLD ?= ld +CC = $(HOSTCC) +LD = $(HOSTLD) +AR = ar ifeq ($(srctree),) srctree := $(patsubst %/,%,$(dir $(CURDIR))) diff --git a/tools/objtool/orc_dump.c b/tools/objtool/orc_dump.c index 36c5bf6a2675..c3343820916a 100644 --- a/tools/objtool/orc_dump.c +++ b/tools/objtool/orc_dump.c @@ -76,7 +76,8 @@ int orc_dump(const char *_objname) int fd, nr_entries, i, *orc_ip = NULL, orc_size = 0; struct orc_entry *orc = NULL; char *name; - unsigned long nr_sections, orc_ip_addr = 0; + size_t nr_sections; + Elf64_Addr orc_ip_addr = 0; size_t shstrtab_idx; Elf *elf; Elf_Scn *scn; @@ -187,10 +188,10 @@ int orc_dump(const char *_objname) return -1; } - printf("%s+%lx:", name, rela.r_addend); + printf("%s+%llx:", name, (unsigned long long)rela.r_addend); } else { - printf("%lx:", orc_ip_addr + (i * sizeof(int)) + orc_ip[i]); + printf("%llx:", (unsigned long long)(orc_ip_addr + (i * sizeof(int)) + orc_ip[i])); } -- GitLab From 34c9ca37aaec2e307b837bb099d3b44f0ea04ddc Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 6 Dec 2017 22:41:53 +0100 Subject: [PATCH 1000/2547] tooling/headers: Synchronize updated s390 and x86 UAPI headers There were two trivial updates to these upstream UAPI headers: arch/s390/include/uapi/asm/kvm.h arch/s390/include/uapi/asm/kvm_perf.h arch/x86/lib/x86-opcode-map.txt Synchronize them with their tooling copies. (The x86 opcode map includes a new instruction pattern now.) Cc: Arnaldo Carvalho de Melo Cc: Peter Zijlstra Cc: Namhyung Kim Cc: Jiri Olsa Cc: Linus Torvalds Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- tools/arch/s390/include/uapi/asm/kvm.h | 4 ---- tools/arch/s390/include/uapi/asm/kvm_perf.h | 4 ---- tools/perf/util/intel-pt-decoder/x86-opcode-map.txt | 2 +- 3 files changed, 1 insertion(+), 9 deletions(-) diff --git a/tools/arch/s390/include/uapi/asm/kvm.h b/tools/arch/s390/include/uapi/asm/kvm.h index 9ad172dcd912..38535a57fef8 100644 --- a/tools/arch/s390/include/uapi/asm/kvm.h +++ b/tools/arch/s390/include/uapi/asm/kvm.h @@ -6,10 +6,6 @@ * * Copyright IBM Corp. 2008 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. - * * Author(s): Carsten Otte * Christian Borntraeger */ diff --git a/tools/arch/s390/include/uapi/asm/kvm_perf.h b/tools/arch/s390/include/uapi/asm/kvm_perf.h index c36c97ffdc6f..84606b8cc49e 100644 --- a/tools/arch/s390/include/uapi/asm/kvm_perf.h +++ b/tools/arch/s390/include/uapi/asm/kvm_perf.h @@ -4,10 +4,6 @@ * * Copyright 2014 IBM Corp. * Author(s): Alexander Yarygin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License (version 2 only) - * as published by the Free Software Foundation. */ #ifndef __LINUX_KVM_PERF_S390_H diff --git a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt index 12e377184ee4..c4d55919fac1 100644 --- a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt +++ b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt @@ -896,7 +896,7 @@ EndTable GrpTable: Grp3_1 0: TEST Eb,Ib -1: +1: TEST Eb,Ib 2: NOT Eb 3: NEG Eb 4: MUL AL,Eb -- GitLab From 1352f09b4cc4f9dce386620b118401738bbf0d5f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 Dec 2017 16:27:02 +0100 Subject: [PATCH 1001/2547] of: overlay: Fix memory leak in of_overlay_apply() error path If of_resolve_phandles() fails, free_overlay_changeset() is called in the error path. However, that function returns early if the list hasn't been initialized yet, before freeing the object. Explicitly calling kfree() instead would solve that issue. However, that complicates matter, by having to consider which of two different methods to use to dispose of the same object. Hence make free_overlay_changeset() consider initialization state of the different parts of the object, making it always safe to call (once!) to dispose of a (partially) initialized overlay_changeset: - Only destroy the changeset if the list was initialized, - Make init_overlay_changeset() store the ID in ovcs->id on success, to avoid calling idr_remove() with an error value or an already released ID. Reported-by: Colin King Fixes: f948d6d8b792bb90 ("of: overlay: avoid race condition between applying multiple overlays") Signed-off-by: Geert Uytterhoeven Reviewed-by: Frank Rowand Signed-off-by: Rob Herring --- drivers/of/overlay.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c index 2b852a39581e..bb3f123ed259 100644 --- a/drivers/of/overlay.c +++ b/drivers/of/overlay.c @@ -522,7 +522,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs, struct device_node *node, *overlay_node; struct fragment *fragment; struct fragment *fragments; - int cnt, ret; + int cnt, id, ret; /* * Warn for some issues. Can not return -EINVAL for these until @@ -543,9 +543,9 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs, of_changeset_init(&ovcs->cset); - ovcs->id = idr_alloc(&ovcs_idr, ovcs, 1, 0, GFP_KERNEL); - if (ovcs->id <= 0) - return ovcs->id; + id = idr_alloc(&ovcs_idr, ovcs, 1, 0, GFP_KERNEL); + if (id <= 0) + return id; cnt = 0; @@ -611,6 +611,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs, goto err_free_fragments; } + ovcs->id = id; ovcs->count = cnt; ovcs->fragments = fragments; @@ -619,7 +620,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs, err_free_fragments: kfree(fragments); err_free_idr: - idr_remove(&ovcs_idr, ovcs->id); + idr_remove(&ovcs_idr, id); pr_err("%s() failed, ret = %d\n", __func__, ret); @@ -630,9 +631,8 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs) { int i; - if (!ovcs->cset.entries.next) - return; - of_changeset_destroy(&ovcs->cset); + if (ovcs->cset.entries.next) + of_changeset_destroy(&ovcs->cset); if (ovcs->id) idr_remove(&ovcs_idr, ovcs->id); -- GitLab From 5e4748175fe942c86cbab840e2fa41a92b4d6cf6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 Dec 2017 16:27:03 +0100 Subject: [PATCH 1002/2547] of: overlay: Fix (un)locking in of_overlay_apply() The special overlay mutex is taken first, hence it should be released last in the error path. of_resolve_phandles() must be called with of_mutex held. Without it, a node and new phandle could be added via of_attach_node(), making the max phandle wrong. free_overlay_changeset() must be called with of_mutex held, if any non-trivial cleanup is to be done. Hence move "mutex_lock(&of_mutex)" up, as suggested by Frank, and merge the two tail statements of the success and error paths, now they became identical. Note that while the two mutexes are adjacent, we still need both: __of_changeset_apply_notify(), which is called by __of_changeset_apply() unlocks of_mutex, then does notifications then locks of_mutex. So the mutex get released in the middle of of_overlay_apply() Fixes: f948d6d8b792bb90 ("of: overlay: avoid race condition between applying multiple overlays") Signed-off-by: Geert Uytterhoeven Reviewed-by: Frank Rowand Signed-off-by: Rob Herring --- drivers/of/overlay.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c index bb3f123ed259..fcce5cdbe229 100644 --- a/drivers/of/overlay.c +++ b/drivers/of/overlay.c @@ -706,12 +706,11 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id) } of_overlay_mutex_lock(); + mutex_lock(&of_mutex); ret = of_resolve_phandles(tree); if (ret) - goto err_overlay_unlock; - - mutex_lock(&of_mutex); + goto err_free_overlay_changeset; ret = init_overlay_changeset(ovcs, tree); if (ret) @@ -754,18 +753,14 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id) ret = ret_tmp; } - mutex_unlock(&of_mutex); - of_overlay_mutex_unlock(); - - goto out; - -err_overlay_unlock: - of_overlay_mutex_unlock(); + goto out_unlock; err_free_overlay_changeset: free_overlay_changeset(ovcs); +out_unlock: mutex_unlock(&of_mutex); + of_overlay_mutex_unlock(); out: pr_debug("%s() err=%d\n", __func__, ret); -- GitLab From c07d35338081d107e57cf37572d8cc931a8e32e2 Mon Sep 17 00:00:00 2001 From: Daniel Thompson Date: Mon, 2 Mar 2015 14:13:36 +0000 Subject: [PATCH 1003/2547] kdb: Fix handling of kallsyms_symbol_next() return value kallsyms_symbol_next() returns a boolean (true on success). Currently kdb_read() tests the return value with an inequality that unconditionally evaluates to true. This is fixed in the obvious way and, since the conditional branch is supposed to be unreachable, we also add a WARN_ON(). Reported-by: Dan Carpenter Signed-off-by: Daniel Thompson Cc: linux-stable Signed-off-by: Jason Wessel --- kernel/debug/kdb/kdb_io.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/debug/kdb/kdb_io.c b/kernel/debug/kdb/kdb_io.c index e74be38245ad..ed5d34925ad0 100644 --- a/kernel/debug/kdb/kdb_io.c +++ b/kernel/debug/kdb/kdb_io.c @@ -350,7 +350,7 @@ static char *kdb_read(char *buffer, size_t bufsize) } kdb_printf("\n"); for (i = 0; i < count; i++) { - if (kallsyms_symbol_next(p_tmp, i) < 0) + if (WARN_ON(!kallsyms_symbol_next(p_tmp, i))) break; kdb_printf("%s ", p_tmp); *(p_tmp + len) = '\0'; -- GitLab From 4e23f78c74934e8ea624b59df58e646e0657608a Mon Sep 17 00:00:00 2001 From: Jason Wessel Date: Tue, 5 Dec 2017 13:26:27 -0600 Subject: [PATCH 1004/2547] kgdb/kdb/debug_core: Add co-maintainer Daniel Thompson Signed-off-by: Jason Wessel --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2811a211632c..74be63be6197 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7659,6 +7659,7 @@ F: security/keys/ KGDB / KDB /debug_core M: Jason Wessel +M: Daniel Thompson W: http://kgdb.wiki.kernel.org/ L: kgdb-bugreport@lists.sourceforge.net T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwessel/kgdb.git -- GitLab From b430b7751286b3acff2d324553c8cec4f1e87764 Mon Sep 17 00:00:00 2001 From: Justin Maggard Date: Mon, 30 Oct 2017 15:29:10 -0700 Subject: [PATCH 1005/2547] btrfs: Fix quota reservation leak on preallocated files Commit c6887cd11149 ("Btrfs: don't do nocow check unless we have to") changed the behavior of __btrfs_buffered_write() so that it first tries to get a data space reservation, and then skips the relatively expensive nocow check if the reservation succeeded. If we have quotas enabled, the data space reservation also includes a quota reservation. But in the rewrite case, the space has already been accounted for in qgroups. So btrfs_check_data_free_space() increases the quota reservation, but it never gets decreased when the data actually gets written and overwrites the pre-existing data. So we're left with both the qgroup and qgroup reservation accounting for the same space. This commit adds the missing btrfs_qgroup_free_data() call in the case of BTRFS_ORDERED_PREALLOC extents. Fixes: c6887cd11149 ("Btrfs: don't do nocow check unless we have to") Signed-off-by: Justin Maggard Reviewed-by: Qu Wenruo Signed-off-by: David Sterba --- fs/btrfs/inode.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index 993061f83067..e1a7f3cb5be9 100644 --- a/fs/btrfs/inode.c +++ b/fs/btrfs/inode.c @@ -3005,6 +3005,8 @@ static int btrfs_finish_ordered_io(struct btrfs_ordered_extent *ordered_extent) compress_type = ordered_extent->compress_type; if (test_bit(BTRFS_ORDERED_PREALLOC, &ordered_extent->flags)) { BUG_ON(compress_type); + btrfs_qgroup_free_data(inode, NULL, ordered_extent->file_offset, + ordered_extent->len); ret = btrfs_mark_extent_written(trans, BTRFS_I(inode), ordered_extent->file_offset, ordered_extent->file_offset + -- GitLab From 692826b2738101549f032a761a9191636e83be4e Mon Sep 17 00:00:00 2001 From: Jeff Mahoney Date: Tue, 21 Nov 2017 13:58:49 -0500 Subject: [PATCH 1006/2547] btrfs: handle errors while updating refcounts in update_ref_for_cow Since commit fb235dc06fa (btrfs: qgroup: Move half of the qgroup accounting time out of commit trans) the assumption that btrfs_add_delayed_{data,tree}_ref can only return 0 or -ENOMEM has been false. The qgroup operations call into btrfs_search_slot and friends and can now return the full spectrum of error codes. Fortunately, the fix here is easy since update_ref_for_cow failing is already handled so we just need to bail early with the error code. Fixes: fb235dc06fa (btrfs: qgroup: Move half of the qgroup accounting ...) Cc: # v4.11+ Signed-off-by: Jeff Mahoney Reviewed-by: Edmund Nadolski Reviewed-by: Qu Wenruo Signed-off-by: David Sterba --- fs/btrfs/ctree.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c index 531e0a8645b0..1e74cf826532 100644 --- a/fs/btrfs/ctree.c +++ b/fs/btrfs/ctree.c @@ -1032,14 +1032,17 @@ static noinline int update_ref_for_cow(struct btrfs_trans_handle *trans, root->root_key.objectid == BTRFS_TREE_RELOC_OBJECTID) && !(flags & BTRFS_BLOCK_FLAG_FULL_BACKREF)) { ret = btrfs_inc_ref(trans, root, buf, 1); - BUG_ON(ret); /* -ENOMEM */ + if (ret) + return ret; if (root->root_key.objectid == BTRFS_TREE_RELOC_OBJECTID) { ret = btrfs_dec_ref(trans, root, buf, 0); - BUG_ON(ret); /* -ENOMEM */ + if (ret) + return ret; ret = btrfs_inc_ref(trans, root, cow, 1); - BUG_ON(ret); /* -ENOMEM */ + if (ret) + return ret; } new_flags |= BTRFS_BLOCK_FLAG_FULL_BACKREF; } else { @@ -1049,7 +1052,8 @@ static noinline int update_ref_for_cow(struct btrfs_trans_handle *trans, ret = btrfs_inc_ref(trans, root, cow, 1); else ret = btrfs_inc_ref(trans, root, cow, 0); - BUG_ON(ret); /* -ENOMEM */ + if (ret) + return ret; } if (new_flags != 0) { int level = btrfs_header_level(buf); @@ -1068,9 +1072,11 @@ static noinline int update_ref_for_cow(struct btrfs_trans_handle *trans, ret = btrfs_inc_ref(trans, root, cow, 1); else ret = btrfs_inc_ref(trans, root, cow, 0); - BUG_ON(ret); /* -ENOMEM */ + if (ret) + return ret; ret = btrfs_dec_ref(trans, root, buf, 1); - BUG_ON(ret); /* -ENOMEM */ + if (ret) + return ret; } clean_tree_block(fs_info, buf); *last_ref = 1; -- GitLab From e19182c0fff451e3744c1107d98f072e7ca377a0 Mon Sep 17 00:00:00 2001 From: Jeff Mahoney Date: Mon, 4 Dec 2017 13:11:45 -0500 Subject: [PATCH 1007/2547] btrfs: fix missing error return in btrfs_drop_snapshot If btrfs_del_root fails in btrfs_drop_snapshot, we'll pick up the error but then return 0 anyway due to mixing err and ret. Fixes: 79787eaab4612 ("btrfs: replace many BUG_ONs with proper error handling") Cc: # v3.4+ Signed-off-by: Jeff Mahoney Reviewed-by: David Sterba Signed-off-by: David Sterba --- fs/btrfs/extent-tree.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c index 784d41e95ed9..16e46ee3cd16 100644 --- a/fs/btrfs/extent-tree.c +++ b/fs/btrfs/extent-tree.c @@ -9220,6 +9220,7 @@ int btrfs_drop_snapshot(struct btrfs_root *root, ret = btrfs_del_root(trans, fs_info, &root->root_key); if (ret) { btrfs_abort_transaction(trans, ret); + err = ret; goto out_end_trans; } -- GitLab From 1b9e619c5bc8235cfba3dc4ced2fb0e3554a05d4 Mon Sep 17 00:00:00 2001 From: Omar Sandoval Date: Tue, 5 Dec 2017 22:54:02 -0800 Subject: [PATCH 1008/2547] Btrfs: disable FUA if mounted with nobarrier I was seeing disk flushes still happening when I mounted a Btrfs filesystem with nobarrier for testing. This is because we use FUA to write out the first super block, and on devices without FUA support, the block layer translates FUA to a flush. Even on devices supporting true FUA, using FUA when we asked for no barriers is surprising. Fixes: 387125fc722a8ed ("Btrfs: fix barrier flushes") Signed-off-by: Omar Sandoval Reviewed-by: Qu Wenruo Reviewed-by: David Sterba Signed-off-by: David Sterba --- fs/btrfs/disk-io.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 10a2a579cc7f..a8ecccfc36de 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -3231,6 +3231,7 @@ static int write_dev_supers(struct btrfs_device *device, int errors = 0; u32 crc; u64 bytenr; + int op_flags; if (max_mirrors == 0) max_mirrors = BTRFS_SUPER_MIRROR_MAX; @@ -3273,13 +3274,10 @@ static int write_dev_supers(struct btrfs_device *device, * we fua the first super. The others we allow * to go down lazy. */ - if (i == 0) { - ret = btrfsic_submit_bh(REQ_OP_WRITE, - REQ_SYNC | REQ_FUA | REQ_META | REQ_PRIO, bh); - } else { - ret = btrfsic_submit_bh(REQ_OP_WRITE, - REQ_SYNC | REQ_META | REQ_PRIO, bh); - } + op_flags = REQ_SYNC | REQ_META | REQ_PRIO; + if (i == 0 && !btrfs_test_opt(device->fs_info, NOBARRIER)) + op_flags |= REQ_FUA; + ret = btrfsic_submit_bh(REQ_OP_WRITE, op_flags, bh); if (ret) errors++; } -- GitLab From c8bcbfbd239ed60a6562964b58034ac8a25f4c31 Mon Sep 17 00:00:00 2001 From: Nikolay Borisov Date: Fri, 1 Dec 2017 11:19:42 +0200 Subject: [PATCH 1009/2547] btrfs: Fix possible off-by-one in btrfs_search_path_in_tree The name char array passed to btrfs_search_path_in_tree is of size BTRFS_INO_LOOKUP_PATH_MAX (4080). So the actual accessible char indexes are in the range of [0, 4079]. Currently the code uses the define but this represents an off-by-one. Implications: Size of btrfs_ioctl_ino_lookup_args is 4096, so the new byte will be written to extra space, not some padding that could be provided by the allocator. btrfs-progs store the arguments on stack, but kernel does own copy of the ioctl buffer and the off-by-one overwrite does not affect userspace, but the ending 0 might be lost. Kernel ioctl buffer is allocated dynamically so we're overwriting somebody else's memory, and the ioctl is privileged if args.objectid is not 256. Which is in most cases, but resolving a subvolume stored in another directory will trigger that path. Before this patch the buffer was one byte larger, but then the -1 was not added. Fixes: ac8e9819d71f907 ("Btrfs: add search and inode lookup ioctls") Signed-off-by: Nikolay Borisov Reviewed-by: David Sterba [ added implications ] Signed-off-by: David Sterba --- fs/btrfs/ioctl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c index fd172a93d11a..1a508fff7afe 100644 --- a/fs/btrfs/ioctl.c +++ b/fs/btrfs/ioctl.c @@ -2206,7 +2206,7 @@ static noinline int btrfs_search_path_in_tree(struct btrfs_fs_info *info, if (!path) return -ENOMEM; - ptr = &name[BTRFS_INO_LOOKUP_PATH_MAX]; + ptr = &name[BTRFS_INO_LOOKUP_PATH_MAX - 1]; key.objectid = tree_id; key.type = BTRFS_ROOT_ITEM_KEY; -- GitLab From 89452d4ab20745002e50ecf90979708f1ce1d077 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 30 Oct 2017 08:28:09 +0100 Subject: [PATCH 1010/2547] drm/exynos: Fix dma-buf import When IOMMU support was enabled, dma-buf import in Exynos DRM was broken since commit f43c35966a5a ("drm/exynos: use real device for DMA-mapping operations") due to using wrong struct device in drm_gem_prime_import() function. This patch fixes following kernel BUG caused by incorrect buffer mapping to DMA address space: exynos-sysmmu 14650000.sysmmu: 14450000.mixer: PAGE FAULT occurred at 0xb2e00000 ------------[ cut here ]------------ kernel BUG at drivers/iommu/exynos-iommu.c:449! Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.14.0-rc4-next-20171016-00033-g990d723669fd #3165 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) task: c0e0b7c0 task.stack: c0e00000 PC is at exynos_sysmmu_irq+0x1d0/0x24c LR is at exynos_sysmmu_irq+0x154/0x24c ------------[ cut here ]------------ Reported-by: Marian Mihailescu Fixes: f43c35966a5a ("drm/exynos: use real device for DMA-mapping operations") Signed-off-by: Marek Szyprowski Reviewed-by: Tobias Jakobi Signed-off-by: Inki Dae --- drivers/gpu/drm/exynos/exynos_drm_drv.c | 2 +- drivers/gpu/drm/exynos/exynos_drm_gem.c | 6 ++++++ drivers/gpu/drm/exynos/exynos_drm_gem.h | 2 ++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index 82b72425a42f..a6ff3a538c8a 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -148,7 +148,7 @@ static struct drm_driver exynos_drm_driver = { .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_export = drm_gem_prime_export, - .gem_prime_import = drm_gem_prime_import, + .gem_prime_import = exynos_drm_gem_prime_import, .gem_prime_get_sg_table = exynos_drm_gem_prime_get_sg_table, .gem_prime_import_sg_table = exynos_drm_gem_prime_import_sg_table, .gem_prime_vmap = exynos_drm_gem_prime_vmap, diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c index 077de014d610..ef35bc23bb36 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c @@ -506,6 +506,12 @@ int exynos_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) } /* low-level interface prime helpers */ +struct drm_gem_object *exynos_drm_gem_prime_import(struct drm_device *dev, + struct dma_buf *dma_buf) +{ + return drm_gem_prime_import_dev(dev, dma_buf, to_dma_dev(dev)); +} + struct sg_table *exynos_drm_gem_prime_get_sg_table(struct drm_gem_object *obj) { struct exynos_drm_gem *exynos_gem = to_exynos_gem(obj); diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h b/drivers/gpu/drm/exynos/exynos_drm_gem.h index e86d1a9518c3..5a4c7de80f65 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.h +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h @@ -117,6 +117,8 @@ int exynos_drm_gem_fault(struct vm_fault *vmf); int exynos_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma); /* low-level interface prime helpers */ +struct drm_gem_object *exynos_drm_gem_prime_import(struct drm_device *dev, + struct dma_buf *dma_buf); struct sg_table *exynos_drm_gem_prime_get_sg_table(struct drm_gem_object *obj); struct drm_gem_object * exynos_drm_gem_prime_import_sg_table(struct drm_device *dev, -- GitLab From 120a264f9c2782682027d931d83dcbd22e01da80 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 22 Nov 2017 14:14:47 +0100 Subject: [PATCH 1011/2547] drm/exynos: gem: Drop NONCONTIG flag for buffers allocated without IOMMU When no IOMMU is available, all GEM buffers allocated by Exynos DRM driver are contiguous, because of the underlying dma_alloc_attrs() function provides only such buffers. In such case it makes no sense to keep BO_NONCONTIG flag for the allocated GEM buffers. This allows to avoid failures for buffer contiguity checks in the subsequent operations on GEM objects. Signed-off-by: Marek Szyprowski Signed-off-by: Inki Dae CC: stable@vger.kernel.org # v4.4+ --- drivers/gpu/drm/exynos/exynos_drm_gem.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c index ef35bc23bb36..11cc01b47bc0 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c @@ -247,6 +247,15 @@ struct exynos_drm_gem *exynos_drm_gem_create(struct drm_device *dev, if (IS_ERR(exynos_gem)) return exynos_gem; + if (!is_drm_iommu_supported(dev) && (flags & EXYNOS_BO_NONCONTIG)) { + /* + * when no IOMMU is available, all allocated buffers are + * contiguous anyway, so drop EXYNOS_BO_NONCONTIG flag + */ + flags &= ~EXYNOS_BO_NONCONTIG; + DRM_WARN("Non-contiguous allocation is not supported without IOMMU, falling back to contiguous buffer\n"); + } + /* set memory type and cache attribute from user side. */ exynos_gem->flags = flags; -- GitLab From 2f0f6dfcf925c3bdc6468599fa33b729fbd9247d Mon Sep 17 00:00:00 2001 From: Inki Dae Date: Thu, 23 Nov 2017 18:32:06 +0900 Subject: [PATCH 1012/2547] drm/exynos: remove unnecessary descrptions Removed two descriptions to 'da_start' and 'da_space_size' from exynos_drm_private structure. These members don't exist anymore. Signed-off-by: Inki Dae --- drivers/gpu/drm/exynos/exynos_drm_drv.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index c6847fa708fa..589d465a7f88 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -194,11 +194,6 @@ struct drm_exynos_file_private { /* * Exynos drm private structure. * - * @da_start: start address to device address space. - * with iommu, device address space starts from this address - * otherwise default one. - * @da_space_size: size of device address space. - * if 0 then default value is used for it. * @pending: the crtcs that have pending updates to finish * @lock: protect access to @pending * @wait: wait an atomic commit to finish -- GitLab From 1cd6ae355bb2092a6a511558334564cb1f4ffd43 Mon Sep 17 00:00:00 2001 From: Inki Dae Date: Thu, 23 Nov 2017 18:27:57 +0900 Subject: [PATCH 1013/2547] drm/exynos: remove unnecessary function declaration Removed exynos_drm_get_dma_device funtion declaration on top of exynos_drm_drv.c file. We can remove this declaration by moving the implementation of this function upwards. Signed-off-by: Inki Dae --- drivers/gpu/drm/exynos/exynos_drm_drv.c | 44 ++++++++++++------------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index a6ff3a538c8a..27e423b87266 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -37,8 +37,6 @@ #define DRIVER_MAJOR 1 #define DRIVER_MINOR 0 -static struct device *exynos_drm_get_dma_device(void); - int exynos_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) { @@ -301,6 +299,27 @@ static struct component_match *exynos_drm_match_add(struct device *dev) return match ?: ERR_PTR(-ENODEV); } +static struct device *exynos_drm_get_dma_device(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(exynos_drm_drivers); ++i) { + struct exynos_drm_driver_info *info = &exynos_drm_drivers[i]; + struct device *dev; + + if (!info->driver || !(info->flags & DRM_DMA_DEVICE)) + continue; + + while ((dev = bus_find_device(&platform_bus_type, NULL, + &info->driver->driver, + (void *)platform_bus_type.match))) { + put_device(dev); + return dev; + } + } + return NULL; +} + static int exynos_drm_bind(struct device *dev) { struct exynos_drm_private *private; @@ -469,27 +488,6 @@ static struct platform_driver exynos_drm_platform_driver = { }, }; -static struct device *exynos_drm_get_dma_device(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(exynos_drm_drivers); ++i) { - struct exynos_drm_driver_info *info = &exynos_drm_drivers[i]; - struct device *dev; - - if (!info->driver || !(info->flags & DRM_DMA_DEVICE)) - continue; - - while ((dev = bus_find_device(&platform_bus_type, NULL, - &info->driver->driver, - (void *)platform_bus_type.match))) { - put_device(dev); - return dev; - } - } - return NULL; -} - static void exynos_drm_unregister_devices(void) { int i; -- GitLab From ba3edf1f770ebc486f9d69824f4a2e069da4d2d4 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Wed, 6 Dec 2017 18:23:27 -0800 Subject: [PATCH 1014/2547] proc: show si_ptr in /proc//timers without hashing It's a user pointer, and while the permissions of the file are pretty questionable (should it really be readable to everybody), hashing the pointer isn't going to be the solution. We should take a closer look at more of the /proc/ file permissions in general. Sure, we do want many of them to often be readable (for 'ps' and friends), but I think we should probably do a few conversions from S_IRUGO to S_IRUSR. Reported-by: Alexey Dobriyan Signed-off-by: Linus Torvalds --- fs/proc/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/proc/base.c b/fs/proc/base.c index 28fa85276eec..60316b52d659 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -2268,7 +2268,7 @@ static int show_timer(struct seq_file *m, void *v) notify = timer->it_sigev_notify; seq_printf(m, "ID: %d\n", timer->it_id); - seq_printf(m, "signal: %d/%p\n", + seq_printf(m, "signal: %d/%px\n", timer->sigq->info.si_signo, timer->sigq->info.si_value.sival_ptr); seq_printf(m, "notify: %s/%s.%d\n", -- GitLab From b638823a7bbd251d442042b0e9522100bdaa5b66 Mon Sep 17 00:00:00 2001 From: Alejandro Mery Date: Tue, 5 Dec 2017 12:34:56 +0000 Subject: [PATCH 1015/2547] ARM: davinci: Use platform_device_register_full() to create pdev for dm365's eDMA Convert the DM365 EDMA platform device creation to use struct platform_device_info XXXXXX __initconst and platform_device_register_full() This will allow us to specify the dma_mask for the device in an upcoming patch. Without this, EDMA on DM365 refuses to probe. Fixes: 7ab388e85faa ("ARM: davinci: Use platform_device_register_full() to create pdev for eDMA") Reviewed-by: Peter Ujfalusi Signed-off-by: Alejandro Mery Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/dm365.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 8be04ec95adf..9bd17bc77b5c 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -925,12 +925,13 @@ static struct resource edma_resources[] = { /* not using TC*_ERR */ }; -static struct platform_device dm365_edma_device = { - .name = "edma", - .id = 0, - .dev.platform_data = &dm365_edma_pdata, - .num_resources = ARRAY_SIZE(edma_resources), - .resource = edma_resources, +static const struct platform_device_info dm365_edma_device __initconst = { + .name = "edma", + .id = 0, + .res = edma_resources, + .num_res = ARRAY_SIZE(edma_resources), + .data = &dm365_edma_pdata, + .size_data = sizeof(dm365_edma_pdata), }; static struct resource dm365_asp_resources[] = { @@ -1428,13 +1429,18 @@ int __init dm365_init_video(struct vpfe_config *vpfe_cfg, static int __init dm365_init_devices(void) { + struct platform_device *edma_pdev; int ret = 0; if (!cpu_is_davinci_dm365()) return 0; davinci_cfg_reg(DM365_INT_EDMA_CC); - platform_device_register(&dm365_edma_device); + edma_pdev = platform_device_register_full(&dm365_edma_device); + if (IS_ERR(edma_pdev)) { + pr_warn("%s: Failed to register eDMA\n", __func__); + return PTR_ERR(edma_pdev); + } platform_device_register(&dm365_mdio_device); platform_device_register(&dm365_emac_device); -- GitLab From 621f96bcb49412010876a1e6e006f748b91d9e75 Mon Sep 17 00:00:00 2001 From: Alejandro Mery Date: Tue, 5 Dec 2017 12:34:57 +0000 Subject: [PATCH 1016/2547] ARM: davinci: Add dma_mask to dm365's eDMA device Add dma_mask to dm365's EDMA device. Without a valid dma_mask, EDMA on DM365 refuses to probe. Fixes: cef5b0da4019 ("ARM: davinci: Add dma_mask to eDMA devices") Reviewed-by: Peter Ujfalusi Signed-off-by: Alejandro Mery Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/dm365.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 9bd17bc77b5c..103316f01a22 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -928,6 +928,7 @@ static struct resource edma_resources[] = { static const struct platform_device_info dm365_edma_device __initconst = { .name = "edma", .id = 0, + .dma_mask = DMA_BIT_MASK(32), .res = edma_resources, .num_res = ARRAY_SIZE(edma_resources), .data = &dm365_edma_pdata, -- GitLab From e779498df587dd2189b30fe5b9245aefab870eb8 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 6 Dec 2017 16:11:27 +0100 Subject: [PATCH 1017/2547] s390: fix compat system call table When wiring up the socket system calls the compat entries were incorrectly set. Not all of them point to the corresponding compat wrapper functions, which clear the upper 33 bits of user space pointers, like it is required. Fixes: 977108f89c989 ("s390: wire up separate socketcalls system calls") Cc: # v4.3+ Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky --- arch/s390/kernel/syscalls.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S index 308a7b63348b..f7fc63385553 100644 --- a/arch/s390/kernel/syscalls.S +++ b/arch/s390/kernel/syscalls.S @@ -370,10 +370,10 @@ SYSCALL(sys_recvmmsg,compat_sys_recvmmsg) SYSCALL(sys_sendmmsg,compat_sys_sendmmsg) SYSCALL(sys_socket,sys_socket) SYSCALL(sys_socketpair,compat_sys_socketpair) /* 360 */ -SYSCALL(sys_bind,sys_bind) -SYSCALL(sys_connect,sys_connect) +SYSCALL(sys_bind,compat_sys_bind) +SYSCALL(sys_connect,compat_sys_connect) SYSCALL(sys_listen,sys_listen) -SYSCALL(sys_accept4,sys_accept4) +SYSCALL(sys_accept4,compat_sys_accept4) SYSCALL(sys_getsockopt,compat_sys_getsockopt) /* 365 */ SYSCALL(sys_setsockopt,compat_sys_setsockopt) SYSCALL(sys_getsockname,compat_sys_getsockname) -- GitLab From c5a88cd2e1c508868922bafa0a5c3365986b98e5 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Sun, 3 Dec 2017 16:04:53 -0600 Subject: [PATCH 1018/2547] ARM: dts: da850-lego-ev3: Fix battery voltage gpio This fixes the battery voltage monitoring gpio-hog settings. When the gpio is low, it turns off the battery voltage to the ADC chip. However, this needs to be on all of the time so that we can monitor battery voltage. Also, there was a typo that prevented pinmuxing from working correctly. Signed-off-by: David Lechner Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-lego-ev3.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts index 413dbd5d9f64..81942ae83e1f 100644 --- a/arch/arm/boot/dts/da850-lego-ev3.dts +++ b/arch/arm/boot/dts/da850-lego-ev3.dts @@ -178,7 +178,7 @@ */ battery { pinctrl-names = "default"; - pintctrl-0 = <&battery_pins>; + pinctrl-0 = <&battery_pins>; compatible = "lego,ev3-battery"; io-channels = <&adc 4>, <&adc 3>; io-channel-names = "voltage", "current"; @@ -392,7 +392,7 @@ batt_volt_en { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; - output-low; + output-high; }; }; -- GitLab From ef78970ace74bb606e641a1f27ea36547716a775 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 22 Nov 2017 17:26:21 +0000 Subject: [PATCH 1019/2547] drm/i915: Call i915_gem_init_userptr() before taking struct_mutex We don't need struct_mutex to initialise userptr (it just allocates a workqueue for itself etc), but we do need struct_mutex later on in i915_gem_init() in order to feed requests onto the HW. This should break the chain [ 385.697902] ====================================================== [ 385.697907] WARNING: possible circular locking dependency detected [ 385.697913] 4.14.0-CI-Patchwork_7234+ #1 Tainted: G U [ 385.697917] ------------------------------------------------------ [ 385.697922] perf_pmu/2631 is trying to acquire lock: [ 385.697927] (&mm->mmap_sem){++++}, at: [] __might_fault+0x3e/0x90 [ 385.697941] but task is already holding lock: [ 385.697946] (&cpuctx_mutex){+.+.}, at: [] perf_event_ctx_lock_nested+0xbc/0x1d0 [ 385.697957] which lock already depends on the new lock. [ 385.697963] the existing dependency chain (in reverse order) is: [ 385.697970] -> #4 (&cpuctx_mutex){+.+.}: [ 385.697980] __mutex_lock+0x86/0x9b0 [ 385.697985] perf_event_init_cpu+0x5a/0x90 [ 385.697991] perf_event_init+0x178/0x1a4 [ 385.697997] start_kernel+0x27f/0x3f1 [ 385.698003] verify_cpu+0x0/0xfb [ 385.698006] -> #3 (pmus_lock){+.+.}: [ 385.698015] __mutex_lock+0x86/0x9b0 [ 385.698020] perf_event_init_cpu+0x21/0x90 [ 385.698025] cpuhp_invoke_callback+0xca/0xc00 [ 385.698030] _cpu_up+0xa7/0x170 [ 385.698035] do_cpu_up+0x57/0x70 [ 385.698039] smp_init+0x62/0xa6 [ 385.698044] kernel_init_freeable+0x97/0x193 [ 385.698050] kernel_init+0xa/0x100 [ 385.698055] ret_from_fork+0x27/0x40 [ 385.698058] -> #2 (cpu_hotplug_lock.rw_sem){++++}: [ 385.698068] cpus_read_lock+0x39/0xa0 [ 385.698073] apply_workqueue_attrs+0x12/0x50 [ 385.698078] __alloc_workqueue_key+0x1d8/0x4d8 [ 385.698134] i915_gem_init_userptr+0x5f/0x80 [i915] [ 385.698176] i915_gem_init+0x7c/0x390 [i915] [ 385.698213] i915_driver_load+0x99e/0x15c0 [i915] [ 385.698250] i915_pci_probe+0x33/0x90 [i915] [ 385.698256] pci_device_probe+0xa1/0x130 [ 385.698262] driver_probe_device+0x293/0x440 [ 385.698267] __driver_attach+0xde/0xe0 [ 385.698272] bus_for_each_dev+0x5c/0x90 [ 385.698277] bus_add_driver+0x16d/0x260 [ 385.698282] driver_register+0x57/0xc0 [ 385.698287] do_one_initcall+0x3e/0x160 [ 385.698292] do_init_module+0x5b/0x1fa [ 385.698297] load_module+0x2374/0x2dc0 [ 385.698302] SyS_finit_module+0xaa/0xe0 [ 385.698307] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 385.698311] -> #1 (&dev->struct_mutex){+.+.}: [ 385.698320] __mutex_lock+0x86/0x9b0 [ 385.698361] i915_mutex_lock_interruptible+0x4c/0x130 [i915] [ 385.698403] i915_gem_fault+0x206/0x760 [i915] [ 385.698409] __do_fault+0x1a/0x70 [ 385.698413] __handle_mm_fault+0x7c4/0xdb0 [ 385.698417] handle_mm_fault+0x154/0x300 [ 385.698440] __do_page_fault+0x2d6/0x570 [ 385.698445] page_fault+0x22/0x30 [ 385.698449] -> #0 (&mm->mmap_sem){++++}: [ 385.698459] lock_acquire+0xaf/0x200 [ 385.698464] __might_fault+0x68/0x90 [ 385.698470] _copy_to_user+0x1e/0x70 [ 385.698475] perf_read+0x1aa/0x290 [ 385.698480] __vfs_read+0x23/0x120 [ 385.698484] vfs_read+0xa3/0x150 [ 385.698488] SyS_read+0x45/0xb0 [ 385.698493] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 385.698497] other info that might help us debug this: [ 385.698505] Chain exists of: &mm->mmap_sem --> pmus_lock --> &cpuctx_mutex [ 385.698517] Possible unsafe locking scenario: [ 385.698522] CPU0 CPU1 [ 385.698526] ---- ---- [ 385.698529] lock(&cpuctx_mutex); [ 385.698553] lock(pmus_lock); [ 385.698558] lock(&cpuctx_mutex); [ 385.698564] lock(&mm->mmap_sem); [ 385.698568] *** DEADLOCK *** [ 385.698574] 1 lock held by perf_pmu/2631: [ 385.698578] #0: (&cpuctx_mutex){+.+.}, at: [] perf_event_ctx_lock_nested+0xbc/0x1d0 [ 385.698589] stack backtrace: [ 385.698595] CPU: 3 PID: 2631 Comm: perf_pmu Tainted: G U 4.14.0-CI-Patchwork_7234+ #1 [ 385.698602] Hardware name: /NUC6CAYB, BIOS AYAPLCEL.86A.0040.2017.0619.1722 06/19/2017 [ 385.698609] Call Trace: [ 385.698615] dump_stack+0x5f/0x86 [ 385.698621] print_circular_bug.isra.18+0x1d0/0x2c0 [ 385.698627] __lock_acquire+0x19c3/0x1b60 [ 385.698634] ? generic_exec_single+0x77/0xe0 [ 385.698640] ? lock_acquire+0xaf/0x200 [ 385.698644] lock_acquire+0xaf/0x200 [ 385.698650] ? __might_fault+0x3e/0x90 [ 385.698655] __might_fault+0x68/0x90 [ 385.698660] ? __might_fault+0x3e/0x90 [ 385.698665] _copy_to_user+0x1e/0x70 [ 385.698670] perf_read+0x1aa/0x290 [ 385.698675] __vfs_read+0x23/0x120 [ 385.698682] ? __fget+0x101/0x1f0 [ 385.698686] vfs_read+0xa3/0x150 [ 385.698691] SyS_read+0x45/0xb0 [ 385.698696] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 385.698701] RIP: 0033:0x7ff1c46876ed [ 385.698705] RSP: 002b:00007fff13552f90 EFLAGS: 00000293 ORIG_RAX: 0000000000000000 [ 385.698712] RAX: ffffffffffffffda RBX: ffffc90000647ff0 RCX: 00007ff1c46876ed [ 385.698718] RDX: 0000000000000010 RSI: 00007fff13552fa0 RDI: 0000000000000005 [ 385.698723] RBP: 000056063d300580 R08: 0000000000000000 R09: 0000000000000060 [ 385.698729] R10: 0000000000000000 R11: 0000000000000293 R12: 0000000000000046 [ 385.698734] R13: 00007fff13552c6f R14: 00007ff1c6279d00 R15: 00007ff1c6279a40 Testcase: igt/perf_pmu Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20171122172621.16158-1-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin (cherry picked from commit ee48700dd57d9ce783ec40f035b324d0b75632e4) Signed-off-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 46bdea2de268..ad4050f7ab3b 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4948,8 +4948,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv) { int ret; - mutex_lock(&dev_priv->drm.struct_mutex); - /* * We need to fallback to 4K pages since gvt gtt handling doesn't * support huge page entries - we will need to check either hypervisor @@ -4969,18 +4967,19 @@ int i915_gem_init(struct drm_i915_private *dev_priv) dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; } + ret = i915_gem_init_userptr(dev_priv); + if (ret) + return ret; + /* This is just a security blanket to placate dragons. * On some systems, we very sporadically observe that the first TLBs * used by the CS may be stale, despite us poking the TLB reset. If * we hold the forcewake during initialisation these problems * just magically go away. */ + mutex_lock(&dev_priv->drm.struct_mutex); intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); - ret = i915_gem_init_userptr(dev_priv); - if (ret) - goto out_unlock; - ret = i915_gem_init_ggtt(dev_priv); if (ret) goto out_unlock; -- GitLab From 5bfd40139d55790cbc8e56ad1ce4f974f1fa186d Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Wed, 22 Nov 2017 21:39:28 +0100 Subject: [PATCH 1020/2547] drm/vc4: Fix false positive WARN() backtrace on refcount_inc() usage With CONFIG_REFCOUNT_FULL enabled, refcount_inc() complains when it's passed a refcount object that has its counter set to 0. In this driver, this is a valid use case since we want to increment ->usecnt only when the BO object starts to be used by real HW components and this is definitely not the case when the BO is created. Fix the problem by using refcount_inc_not_zero() instead of refcount_inc() and fallback to refcount_set(1) when refcount_inc_not_zero() returns false. Note that this 2-steps operation is not racy here because the whole section is protected by a mutex which guarantees that the counter does not change between the refcount_inc_not_zero() and refcount_set() calls. Fixes: b9f19259b84d ("drm/vc4: Add the DRM_IOCTL_VC4_GEM_MADVISE ioctl") Reported-by: Stefan Wahren Signed-off-by: Boris Brezillon Acked-by: Eric Anholt Link: https://patchwork.freedesktop.org/patch/msgid/20171122203928.28135-1-boris.brezillon@free-electrons.com --- drivers/gpu/drm/vc4/vc4_bo.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c index 4ae45d7dac42..2decc8e2c79f 100644 --- a/drivers/gpu/drm/vc4/vc4_bo.c +++ b/drivers/gpu/drm/vc4/vc4_bo.c @@ -637,7 +637,8 @@ int vc4_bo_inc_usecnt(struct vc4_bo *bo) mutex_lock(&bo->madv_lock); switch (bo->madv) { case VC4_MADV_WILLNEED: - refcount_inc(&bo->usecnt); + if (!refcount_inc_not_zero(&bo->usecnt)) + refcount_set(&bo->usecnt, 1); ret = 0; break; case VC4_MADV_DONTNEED: -- GitLab From 947134d9b00f342415af7eddd42a5fce7262a1b9 Mon Sep 17 00:00:00 2001 From: Prarit Bhargava Date: Mon, 4 Dec 2017 11:45:21 -0500 Subject: [PATCH 1021/2547] x86/smpboot: Do not use smp_num_siblings in __max_logical_packages calculation Documentation/x86/topology.txt defines smp_num_siblings as "The number of threads in a core". Since commit bbb65d2d365e ("x86: use cpuid vector 0xb when available for detecting cpu topology") smp_num_siblings is the maximum number of threads in a core. If Simultaneous MultiThreading (SMT) is disabled on a system, smp_num_siblings is 2 and not 1 as expected. Use topology_max_smt_threads(), which contains the active numer of threads, in the __max_logical_packages calculation. On a single socket, single core, single thread system __max_smt_threads has not been updated when the __max_logical_packages calculation happens, so its zero which makes the package estimate fail. Initialize it to one, which is the minimum number of threads on a core. [ tglx: Folded the __max_smt_threads fix in ] Fixes: b4c0a7326f5d ("x86/smpboot: Fix __max_logical_packages estimate") Reported-by: Jakub Kicinski Signed-off-by: Prarit Bhargava Tested-by: Jakub Kicinski Cc: netdev@vger.kernel.org Cc: "netdev@vger.kernel.org" Cc: Clark Williams Link: https://lkml.kernel.org/r/20171204164521.17870-1-prarit@redhat.com --- arch/x86/kernel/smpboot.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 05a97d5fe298..35cb20994e32 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -106,7 +106,7 @@ EXPORT_SYMBOL(__max_logical_packages); static unsigned int logical_packages __read_mostly; /* Maximum number of SMT threads on any online core */ -int __max_smt_threads __read_mostly; +int __read_mostly __max_smt_threads = 1; /* Flag to indicate if a complete sched domain rebuild is required */ bool x86_topology_update; @@ -1304,7 +1304,7 @@ void __init native_smp_cpus_done(unsigned int max_cpus) * Today neither Intel nor AMD support heterogenous systems so * extrapolate the boot cpu's data to all packages. */ - ncpus = cpu_data(0).booted_cores * smp_num_siblings; + ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus); pr_info("Max logical packages: %u\n", __max_logical_packages); -- GitLab From 7a8b70535037a7d8503d12c1a5abbbc8aa5d709a Mon Sep 17 00:00:00 2001 From: Radhakrishna Sripada Date: Wed, 6 Dec 2017 14:25:07 -0800 Subject: [PATCH 1022/2547] Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk" This reverts commit 8f067837c4b713ce2e69be95af7b2a5eb3bd7de8. HSD says "WA withdrawn. It was causing corruption with some images. WA is not strictly necessary since this bug just causes loss of FBC compression with some sizes and images, but doesn't break anything." Fixes: 8f067837c4b7 ("drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk") Cc: Rodrigo Vivi Signed-off-by: Radhakrishna Sripada Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20171117010825.23118-1-radhakrishna.sripada@intel.com (cherry picked from commit 0cfecb7c4b9b45ed1776162e132b43f92564f3f4) Signed-off-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_reg.h | 3 --- drivers/gpu/drm/i915/intel_pm.c | 13 ------------- 2 files changed, 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 68a58cce6ab1..3866c49bc390 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2951,9 +2951,6 @@ enum i915_power_well_id { #define ILK_DPFC_CHICKEN _MMIO(0x43224) #define ILK_DPFC_DISABLE_DUMMY0 (1<<8) #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23) -#define GLK_SKIP_SEG_EN (1<<12) -#define GLK_SKIP_SEG_COUNT_MASK (3<<10) -#define GLK_SKIP_SEG_COUNT(x) ((x)<<10) #define ILK_FBC_RT_BASE _MMIO(0x2128) #define ILK_FBC_RT_VALID (1<<0) #define SNB_FBC_FRONT_BUFFER (1<<1) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f4a4e9496893..f0d0dbab4150 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -124,7 +124,6 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) static void glk_init_clock_gating(struct drm_i915_private *dev_priv) { - u32 val; gen9_init_clock_gating(dev_priv); /* @@ -144,11 +143,6 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(CHICKEN_MISC_2, val); } - /* Display WA #1133: WaFbcSkipSegments:glk */ - val = I915_READ(ILK_DPFC_CHICKEN); - val &= ~GLK_SKIP_SEG_COUNT_MASK; - val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1); - I915_WRITE(ILK_DPFC_CHICKEN, val); } static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) @@ -8517,7 +8511,6 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) { - u32 val; cnp_init_clock_gating(dev_priv); /* This is not an Wa. Enable for better image quality */ @@ -8537,12 +8530,6 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) | SARBUNIT_CLKGATE_DIS); - - /* Display WA #1133: WaFbcSkipSegments:cnl */ - val = I915_READ(ILK_DPFC_CHICKEN); - val &= ~GLK_SKIP_SEG_COUNT_MASK; - val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1); - I915_WRITE(ILK_DPFC_CHICKEN, val); } static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) -- GitLab From 08529078d8d9adf689bf39cc38d53979a0869970 Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Mon, 4 Dec 2017 15:40:55 +0300 Subject: [PATCH 1023/2547] x86/boot/compressed/64: Detect and handle 5-level paging at boot-time Prerequisite for fixing the current problem of instantaneous reboots when a 5-level paging kernel is booted on 4-level paging hardware. At the same time this change prepares the decompression code to boot-time switching between 4- and 5-level paging. [ tglx: Folded the GCC < 5 fix. ] Fixes: 77ef56e4f0fb ("x86: Enable 5-level paging support via CONFIG_X86_5LEVEL=y") Signed-off-by: Kirill A. Shutemov Signed-off-by: Thomas Gleixner Cc: Andi Kleen Cc: stable@vger.kernel.org Cc: Andy Lutomirski Cc: linux-mm@kvack.org Cc: Cyrill Gorcunov Cc: Borislav Petkov Cc: Linus Torvalds Link: https://lkml.kernel.org/r/20171204124059.63515-2-kirill.shutemov@linux.intel.com --- arch/x86/boot/compressed/Makefile | 1 + arch/x86/boot/compressed/head_64.S | 16 +++++++++++---- arch/x86/boot/compressed/pgtable_64.c | 28 +++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 4 deletions(-) create mode 100644 arch/x86/boot/compressed/pgtable_64.c diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile index 1e9c322e973a..f25e1530e064 100644 --- a/arch/x86/boot/compressed/Makefile +++ b/arch/x86/boot/compressed/Makefile @@ -80,6 +80,7 @@ vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/kaslr.o ifdef CONFIG_X86_64 vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/pagetable.o vmlinux-objs-y += $(obj)/mem_encrypt.o + vmlinux-objs-y += $(obj)/pgtable_64.o endif $(obj)/eboot.o: KBUILD_CFLAGS += -fshort-wchar -mno-red-zone diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S index 20919b4f3133..fc313e29fe2c 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -305,10 +305,18 @@ ENTRY(startup_64) leaq boot_stack_end(%rbx), %rsp #ifdef CONFIG_X86_5LEVEL - /* Check if 5-level paging has already enabled */ - movq %cr4, %rax - testl $X86_CR4_LA57, %eax - jnz lvl5 + /* + * Check if we need to enable 5-level paging. + * RSI holds real mode data and need to be preserved across + * a function call. + */ + pushq %rsi + call l5_paging_required + popq %rsi + + /* If l5_paging_required() returned zero, we're done here. */ + cmpq $0, %rax + je lvl5 /* * At this point we are in long mode with 4-level paging enabled, diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c new file mode 100644 index 000000000000..b4469a37e9a1 --- /dev/null +++ b/arch/x86/boot/compressed/pgtable_64.c @@ -0,0 +1,28 @@ +#include + +/* + * __force_order is used by special_insns.h asm code to force instruction + * serialization. + * + * It is not referenced from the code, but GCC < 5 with -fPIE would fail + * due to an undefined symbol. Define it to make these ancient GCCs work. + */ +unsigned long __force_order; + +int l5_paging_required(void) +{ + /* Check if leaf 7 is supported. */ + + if (native_cpuid_eax(0) < 7) + return 0; + + /* Check if la57 is supported. */ + if (!(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) + return 0; + + /* Check if 5-level paging has already been enabled. */ + if (native_read_cr4() & X86_CR4_LA57) + return 0; + + return 1; +} -- GitLab From 6d7e0ba2d2be9e50cccba213baf07e0e183c1b24 Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Mon, 4 Dec 2017 15:40:56 +0300 Subject: [PATCH 1024/2547] x86/boot/compressed/64: Print error if 5-level paging is not supported If the machine does not support the paging mode for which the kernel was compiled, the boot process cannot continue. It's not possible to let the kernel detect the mismatch as it does not even reach the point where cpu features can be evaluted due to a triple fault in the KASLR setup. Instead of instantaneous silent reboot, emit an error message which gives the user the information why the boot fails. Fixes: 77ef56e4f0fb ("x86: Enable 5-level paging support via CONFIG_X86_5LEVEL=y") Reported-by: Borislav Petkov Signed-off-by: Kirill A. Shutemov Signed-off-by: Thomas Gleixner Tested-by: Borislav Petkov Cc: Andi Kleen Cc: stable@vger.kernel.org Cc: Andy Lutomirski Cc: linux-mm@kvack.org Cc: Cyrill Gorcunov Cc: Linus Torvalds Link: https://lkml.kernel.org/r/20171204124059.63515-3-kirill.shutemov@linux.intel.com --- arch/x86/boot/compressed/misc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c index b50c42455e25..98761a1576ce 100644 --- a/arch/x86/boot/compressed/misc.c +++ b/arch/x86/boot/compressed/misc.c @@ -169,6 +169,16 @@ void __puthex(unsigned long value) } } +static bool l5_supported(void) +{ + /* Check if leaf 7 is supported. */ + if (native_cpuid_eax(0) < 7) + return 0; + + /* Check if la57 is supported. */ + return native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)); +} + #if CONFIG_X86_NEED_RELOCS static void handle_relocations(void *output, unsigned long output_len, unsigned long virt_addr) @@ -362,6 +372,12 @@ asmlinkage __visible void *extract_kernel(void *rmode, memptr heap, console_init(); debug_putstr("early console in extract_kernel\n"); + if (IS_ENABLED(CONFIG_X86_5LEVEL) && !l5_supported()) { + error("This linux kernel as configured requires 5-level paging\n" + "This CPU does not support the required 'cr4.la57' feature\n" + "Unable to boot - please use a kernel appropriate for your CPU\n"); + } + free_mem_ptr = heap; /* Heap */ free_mem_end_ptr = heap + BOOT_HEAP_SIZE; -- GitLab From 7cb4774e2d3282d29edd00762167876a27cc7d2a Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 6 Dec 2017 17:54:38 +0100 Subject: [PATCH 1025/2547] HID: core: lower log level for unknown main item tags to warnings Given all the effort distros have done with splash-screens to give users a nice clean boot experience, we really want dmesg --level=err to not print anything unless there is a real problem with either the hardware or the kernel. Buggy HID descriptors unfortunately happen all too often, so lower the log level to warning keep the console clear of error messages such as: [ 441.079664] apple 0005:05AC:0239.0003: unknown main item tag 0x0 Signed-off-by: Hans de Goede Acked-by: Benjamin Tissoires Signed-off-by: Jiri Kosina --- drivers/hid/hid-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c index f3fcb836a1f9..0c3f608131cf 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c @@ -551,7 +551,7 @@ static int hid_parser_main(struct hid_parser *parser, struct hid_item *item) ret = hid_add_field(parser, HID_FEATURE_REPORT, data); break; default: - hid_err(parser->device, "unknown main item tag 0x%x\n", item->tag); + hid_warn(parser->device, "unknown main item tag 0x%x\n", item->tag); ret = 0; } -- GitLab From b860b419d970f286294fbfb2b21a4028fd8ee442 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 6 Dec 2017 12:21:35 +0100 Subject: [PATCH 1026/2547] mfd: Fix RTS5227 (and others) powermanagement Commit 8275b77a1513 ("mfd: rts5249: Add support for RTS5250S power saving") adds powersaving support for device-ids 5249 524a and 525a. But as a side effect it breaks ASPM support for all the other device-ids, causing e.g. the Haswell CPU on a Lenovo T440s to not go into a higher c-state then PC3, while previously it would go to PC7, causing the machine to idle at 7.4W instead of 6.6W! The problem here is the new option.dev_aspm_mode field, which only gets explicitly initialized in the new code for the device-ids 5249 524a and 525a. Leaving the dev_aspm_mode 0 for the other device-ids. The default dev_aspm_mode 0 is mapped to DEV_ASPM_DISABLE, but the old behavior of calling rtsx_pci_enable_aspm() when idle and rtsx_pci_disable_aspm() when busy happens when dev_aspm_mode == DEV_ASPM_DYNAMIC. This commit changes the enum so that 0 = DEV_ASPM_DYNAMIC matching the old default behavior, fixing the pm regression with the other device-ids. Fixes: 8275b77a1513 ("mfd: rts5249: Add support for RTS5250S power saving") Signed-off-by: Hans de Goede Acked-by: Rui Feng Signed-off-by: Lee Jones --- include/linux/mfd/rtsx_pci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h index a2a1318a3d0c..c3d3f04d8cc6 100644 --- a/include/linux/mfd/rtsx_pci.h +++ b/include/linux/mfd/rtsx_pci.h @@ -915,10 +915,10 @@ enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN}; #define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6) enum dev_aspm_mode { - DEV_ASPM_DISABLE = 0, DEV_ASPM_DYNAMIC, DEV_ASPM_BACKDOOR, DEV_ASPM_STATIC, + DEV_ASPM_DISABLE, }; /* -- GitLab From 04271ce9601f1686db480ea11ea1848394d9e6a2 Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Tue, 28 Nov 2017 15:55:07 +0530 Subject: [PATCH 1027/2547] i2c-cht-wc: constify platform_device_id platform_device_id are not supposed to change at runtime. All functions working with platform_device_id provided by work with const platform_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav Reviewed-by: Hans de Goede Signed-off-by: Wolfram Sang --- drivers/i2c/busses/i2c-cht-wc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-cht-wc.c b/drivers/i2c/busses/i2c-cht-wc.c index 0d05dadb2dc5..44cffad43701 100644 --- a/drivers/i2c/busses/i2c-cht-wc.c +++ b/drivers/i2c/busses/i2c-cht-wc.c @@ -379,7 +379,7 @@ static int cht_wc_i2c_adap_i2c_remove(struct platform_device *pdev) return 0; } -static struct platform_device_id cht_wc_i2c_adap_id_table[] = { +static const struct platform_device_id cht_wc_i2c_adap_id_table[] = { { .name = "cht_wcove_ext_chgr" }, {}, }; -- GitLab From b458a3490e46dddd5b63f59b458c9b6d2284a63f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 7 Dec 2017 11:09:21 +0100 Subject: [PATCH 1028/2547] spi: rspi: Do not set SPCR_SPE in qspi_set_config_register() The R-Car Gen2 Hardware User Manual Rev. 2.00 states: If the master/slave mode select bit (MSTR) is modified while the SPI function enable bit (SPE) is set to 1 (that is, this module is enabled), the subsequent operation cannot be guaranteed. Hence do not set SPCR_SPE when setting SPCR_MSTR, just like the .set_config_register() implementations for other RSPI variants do. Note that when booted from QSPI, the boot loader will have set SPCR_MSTR already, hence usually the bit is never modified by the Linux driver. Reported-by: Yoshihiro Shimoda Signed-off-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- drivers/spi/spi-rspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index 2ce875764ca6..0835a8d88fb8 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -377,8 +377,8 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size) /* Sets SPCMD */ rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); - /* Enables SPI function in master mode */ - rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); + /* Sets RSPI mode */ + rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); return 0; } -- GitLab From c810daba0ab5226084a56893a789af427a801146 Mon Sep 17 00:00:00 2001 From: Takuo Koguchi Date: Thu, 7 Dec 2017 16:20:14 +0900 Subject: [PATCH 1029/2547] spi: sun4i: disable clocks in the remove function mclk and hclk need to be disabled. Since pm_runtime_disable does not disable the clocks, use pm_runtime_force_suspend instead. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Takuo Koguchi Acked-by: Maxime Ripard Signed-off-by: Mark Brown --- drivers/spi/spi-sun4i.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c index c5cd635c28f3..41410031f8e9 100644 --- a/drivers/spi/spi-sun4i.c +++ b/drivers/spi/spi-sun4i.c @@ -525,7 +525,7 @@ static int sun4i_spi_probe(struct platform_device *pdev) static int sun4i_spi_remove(struct platform_device *pdev) { - pm_runtime_disable(&pdev->dev); + pm_runtime_force_suspend(&pdev->dev); return 0; } -- GitLab From 866f7ed7d67936dcdbcddc111c8af878c918fe7c Mon Sep 17 00:00:00 2001 From: Jussi Laako Date: Thu, 7 Dec 2017 12:58:33 +0200 Subject: [PATCH 1030/2547] ALSA: usb-audio: Add native DSD support for Esoteric D-05X Adds VID:PID of Esoteric D-05X to the TEAC device id's. Renames the is_teac_50X_dac() function to is_teac_dsd_dac() to cover broader device family from the same corporation sharing the same USB audio implementation. Signed-off-by: Jussi Laako Cc: Signed-off-by: Takashi Iwai --- sound/usb/quirks.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c index 77eecaa4db1f..a66ef5777887 100644 --- a/sound/usb/quirks.c +++ b/sound/usb/quirks.c @@ -1166,10 +1166,11 @@ static bool is_marantz_denon_dac(unsigned int id) /* TEAC UD-501/UD-503/NT-503 USB DACs need a vendor cmd to switch * between PCM/DOP and native DSD mode */ -static bool is_teac_50X_dac(unsigned int id) +static bool is_teac_dsd_dac(unsigned int id) { switch (id) { case USB_ID(0x0644, 0x8043): /* TEAC UD-501/UD-503/NT-503 */ + case USB_ID(0x0644, 0x8044): /* Esoteric D-05X */ return true; } return false; @@ -1202,7 +1203,7 @@ int snd_usb_select_mode_quirk(struct snd_usb_substream *subs, break; } mdelay(20); - } else if (is_teac_50X_dac(subs->stream->chip->usb_id)) { + } else if (is_teac_dsd_dac(subs->stream->chip->usb_id)) { /* Vendor mode switch cmd is required. */ switch (fmt->altsetting) { case 3: /* DSD mode (DSD_U32) requested */ @@ -1392,7 +1393,7 @@ u64 snd_usb_interface_dsd_format_quirks(struct snd_usb_audio *chip, } /* TEAC devices with USB DAC functionality */ - if (is_teac_50X_dac(chip->usb_id)) { + if (is_teac_dsd_dac(chip->usb_id)) { if (fp->altsetting == 3) return SNDRV_PCM_FMTBIT_DSD_U32_BE; } -- GitLab From 2b4584d00a6bc02b63ab3c7213060d41a74bdff1 Mon Sep 17 00:00:00 2001 From: Guneshwor Singh Date: Thu, 7 Dec 2017 18:06:20 +0530 Subject: [PATCH 1031/2547] ALSA: hda - Add vendor id for Cannonlake HDMI codec Cannonlake HDMI codec has the same nid as Geminilake. This adds the codec entry for it. Signed-off-by: Guneshwor Singh Cc: Signed-off-by: Takashi Iwai --- sound/pci/hda/patch_hdmi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c index c19c81d230bd..b4f1b6e88305 100644 --- a/sound/pci/hda/patch_hdmi.c +++ b/sound/pci/hda/patch_hdmi.c @@ -55,10 +55,11 @@ MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b) #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \ ((codec)->core.vendor_id == 0x80862800)) +#define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c) #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \ || is_skylake(codec) || is_broxton(codec) \ - || is_kabylake(codec)) || is_geminilake(codec) - + || is_kabylake(codec)) || is_geminilake(codec) \ + || is_cannonlake(codec) #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882) #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883) #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) @@ -3841,6 +3842,7 @@ HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), +HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), -- GitLab From 51ef7925e10688c57186d438e784532e063492e4 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 23 Nov 2017 17:57:04 +0200 Subject: [PATCH 1032/2547] brcmfmac: Avoid build error with make W=1 When I run make W=1 on gcc (Debian 7.2.0-16) 7.2.0 I got an error for the first run, all next ones are okay. CC [M] drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.o drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c:2078: error: Cannot parse struct or union! scripts/Makefile.build:310: recipe for target 'drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.o' failed Seems like something happened with W=1 and wrong kernel doc format. As a quick fix remove dubious /** in the code. Signed-off-by: Andy Shevchenko Acked-by: Arend van Spriel Signed-off-by: Kalle Valo --- drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c index adf180f338ca..cdf9e4161592 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c @@ -2070,7 +2070,7 @@ static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) return head_pad; } -/** +/* * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for * bus layer usage. */ -- GitLab From 010e3e68cd9cb65ea50c0af605e966cda333cb2a Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 6 Dec 2017 12:49:13 +0000 Subject: [PATCH 1033/2547] drm/i915: Remove vma from object on destroy, not close Originally we translated from the object to the vma by walking obj->vma_list to find the matching vm (for user lookups). Now we process user lookups using the rbtree, and we only use obj->vma_list itself for maintaining state (e.g. ensuring that all vma are flushed or rebound). As such maintenance needs to go on beyond the user's awareness of the vma, defer removal of the vma from the obj->vma_list from i915_vma_close() to i915_vma_destroy() Fixes: 5888fc9eac3c ("drm/i915: Flush pending GTT writes before unbinding") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104155 Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20171206124914.19960-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 3 ++- drivers/gpu/drm/i915/i915_vma.c | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 80b78fb5daac..5504be753092 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3746,7 +3746,8 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, return -EBUSY; } - if (i915_gem_valid_gtt_space(vma, cache_level)) + if (!i915_vma_is_closed(vma) && + i915_gem_valid_gtt_space(vma, cache_level)) continue; ret = i915_vma_unbind(vma); diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index bf6d8d1eaabe..1013403fcfea 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -466,6 +466,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) u64 start, end; int ret; + GEM_BUG_ON(i915_vma_is_closed(vma)); GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND)); GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); @@ -678,7 +679,9 @@ static void i915_vma_destroy(struct i915_vma *vma) GEM_BUG_ON(i915_gem_active_isset(&vma->last_read[i])); GEM_BUG_ON(i915_gem_active_isset(&vma->last_fence)); + list_del(&vma->obj_link); list_del(&vma->vm_link); + if (!i915_vma_is_ggtt(vma)) i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); @@ -690,7 +693,6 @@ void i915_vma_close(struct i915_vma *vma) GEM_BUG_ON(i915_vma_is_closed(vma)); vma->flags |= I915_VMA_CLOSED; - list_del(&vma->obj_link); rb_erase(&vma->obj_node, &vma->obj->vma_tree); if (!i915_vma_is_active(vma) && !i915_vma_is_pinned(vma)) -- GitLab From 7125397b82460d74ae0584bdcdc006deec5e895d Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 6 Dec 2017 12:49:14 +0000 Subject: [PATCH 1034/2547] drm/i915: Track GGTT writes on the vma As writes through the GTT and GGTT PTE updates do not share the same path, they are not strictly ordered and so we must explicitly flush the indirect writes prior to modifying the PTE. We do track outstanding GGTT writes on the object itself, but since the object may have multiple GGTT vma, that is overly coarse as we can track and flush individual vma as required. Whilst here, update the GGTT flushing behaviour for Cannonlake. v2: Hard-code ring offset to allow use during unload (after RCS may have been freed, or never existed!) References: https://bugs.freedesktop.org/show_bug.cgi?id=104002 Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171206124914.19960-2-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem.c | 58 +++++++++++++++++++++++---------- drivers/gpu/drm/i915/i915_vma.c | 22 +++++++++++++ drivers/gpu/drm/i915/i915_vma.h | 19 +++++++++++ 4 files changed, 83 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 02551c781f0a..f9386e793c87 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3887,6 +3887,8 @@ int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, unsigned int flags); int i915_gem_evict_vm(struct i915_address_space *vm); +void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv); + /* belongs in i915_gem_gtt.h */ static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 5504be753092..67dc11effc8e 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -666,17 +666,13 @@ fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain) obj->frontbuffer_ggtt_origin : ORIGIN_CPU); } -static void -flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) +void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(obj->base.dev); - - if (!(obj->base.write_domain & flush_domains)) - return; - - /* No actual flushing is required for the GTT write domain. Writes - * to it "immediately" go to main memory as far as we know, so there's - * no chipset flush. It also doesn't land in render cache. + /* + * No actual flushing is required for the GTT write domain for reads + * from the GTT domain. Writes to it "immediately" go to main memory + * as far as we know, so there's no chipset flush. It also doesn't + * land in the GPU render cache. * * However, we do have to enforce the order so that all writes through * the GTT land before any writes to the device, such as updates to @@ -687,22 +683,46 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) * timing. This issue has only been observed when switching quickly * between GTT writes and CPU reads from inside the kernel on recent hw, * and it appears to only affect discrete GTT blocks (i.e. on LLC - * system agents we cannot reproduce this behaviour). + * system agents we cannot reproduce this behaviour, until Cannonlake + * that was!). */ + wmb(); + intel_runtime_pm_get(dev_priv); + spin_lock_irq(&dev_priv->uncore.lock); + + POSTING_READ_FW(RING_HEAD(RENDER_RING_BASE)); + + spin_unlock_irq(&dev_priv->uncore.lock); + intel_runtime_pm_put(dev_priv); +} + +static void +flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) +{ + struct drm_i915_private *dev_priv = to_i915(obj->base.dev); + struct i915_vma *vma; + + if (!(obj->base.write_domain & flush_domains)) + return; + switch (obj->base.write_domain) { case I915_GEM_DOMAIN_GTT: - if (!HAS_LLC(dev_priv)) { - intel_runtime_pm_get(dev_priv); - spin_lock_irq(&dev_priv->uncore.lock); - POSTING_READ_FW(RING_HEAD(dev_priv->engine[RCS]->mmio_base)); - spin_unlock_irq(&dev_priv->uncore.lock); - intel_runtime_pm_put(dev_priv); - } + i915_gem_flush_ggtt_writes(dev_priv); intel_fb_obj_flush(obj, fb_write_origin(obj, I915_GEM_DOMAIN_GTT)); + + list_for_each_entry(vma, &obj->vma_list, obj_link) { + if (!i915_vma_is_ggtt(vma)) + break; + + if (vma->iomap) + continue; + + i915_vma_unset_ggtt_write(vma); + } break; case I915_GEM_DOMAIN_CPU: @@ -1965,6 +1985,8 @@ int i915_gem_fault(struct vm_fault *vmf) list_add(&obj->userfault_link, &dev_priv->mm.userfault_list); GEM_BUG_ON(!obj->userfault_count); + i915_vma_set_ggtt_write(vma); + err_fence: i915_vma_unpin_fence(vma); err_unpin: diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 1013403fcfea..0ebd75693505 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -322,6 +322,7 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma) if (err) goto err_unpin; + i915_vma_set_ggtt_write(vma); return ptr; err_unpin: @@ -330,12 +331,24 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma) return IO_ERR_PTR(err); } +void i915_vma_flush_writes(struct i915_vma *vma) +{ + if (!i915_vma_has_ggtt_write(vma)) + return; + + i915_gem_flush_ggtt_writes(vma->vm->i915); + + i915_vma_unset_ggtt_write(vma); +} + void i915_vma_unpin_iomap(struct i915_vma *vma) { lockdep_assert_held(&vma->obj->base.dev->struct_mutex); GEM_BUG_ON(vma->iomap == NULL); + i915_vma_flush_writes(vma); + i915_vma_unpin_fence(vma); i915_vma_unpin(vma); } @@ -792,6 +805,15 @@ int i915_vma_unbind(struct i915_vma *vma) GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); if (i915_vma_is_map_and_fenceable(vma)) { + /* + * Check that we have flushed all writes through the GGTT + * before the unbind, other due to non-strict nature of those + * indirect writes they may end up referencing the GGTT PTE + * after the unbind. + */ + i915_vma_flush_writes(vma); + GEM_BUG_ON(i915_vma_has_ggtt_write(vma)); + /* release the fence reg _after_ flushing */ ret = i915_vma_put_fence(vma); if (ret) diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 1e2bc9b3c3ac..f636243eb8f7 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -90,6 +90,7 @@ struct i915_vma { #define I915_VMA_CLOSED BIT(10) #define I915_VMA_USERFAULT_BIT 11 #define I915_VMA_USERFAULT BIT(I915_VMA_USERFAULT_BIT) +#define I915_VMA_GGTT_WRITE BIT(12) unsigned int active; struct i915_gem_active last_read[I915_NUM_ENGINES]; @@ -138,6 +139,24 @@ static inline bool i915_vma_is_ggtt(const struct i915_vma *vma) return vma->flags & I915_VMA_GGTT; } +static inline bool i915_vma_has_ggtt_write(const struct i915_vma *vma) +{ + return vma->flags & I915_VMA_GGTT_WRITE; +} + +static inline void i915_vma_set_ggtt_write(struct i915_vma *vma) +{ + GEM_BUG_ON(!i915_vma_is_ggtt(vma)); + vma->flags |= I915_VMA_GGTT_WRITE; +} + +static inline void i915_vma_unset_ggtt_write(struct i915_vma *vma) +{ + vma->flags &= ~I915_VMA_GGTT_WRITE; +} + +void i915_vma_flush_writes(struct i915_vma *vma); + static inline bool i915_vma_is_map_and_fenceable(const struct i915_vma *vma) { return vma->flags & I915_VMA_CAN_FENCE; -- GitLab From 510353a63796d467b41237ab4f136136f68c297d Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 21 Nov 2017 08:49:36 +0100 Subject: [PATCH 1035/2547] drm/bridge: analogix dp: Fix runtime PM state in get_modes() callback get_modes() callback might be called asynchronously from the DRM core and it is not synchronized with bridge_enable(), which sets proper runtime PM state of the main DP device. Fix this by calling pm_runtime_get_sync() before calling drm_get_edid(), which in turn calls drm_dp_i2c_xfer() and analogix_dp_transfer() to ensure that main DP device is runtime active when doing any access to its registers. This fixes the following kernel issue on Samsung Exynos5250 Snow board: Unhandled fault: imprecise external abort (0x406) at 0x00000000 pgd = c0004000 [00000000] *pgd=00000000 Internal error: : 406 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 62 Comm: kworker/0:2 Not tainted 4.13.0-rc2-00364-g4a97a3da420b #3357 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) Workqueue: events output_poll_execute task: edc14800 task.stack: edcb2000 PC is at analogix_dp_transfer+0x15c/0x2fc LR is at analogix_dp_transfer+0x134/0x2fc pc : [] lr : [] psr: 60000013 sp : edcb3be8 ip : 0000002a fp : 00000001 r10: 00000000 r9 : edcb3cd8 r8 : edcb3c40 r7 : 00000000 r6 : edd3b380 r5 : edd3b010 r4 : 00000064 r3 : 00000000 r2 : f0ad3000 r1 : edcb3c40 r0 : edd3b010 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none Control: 10c5387d Table: 4000406a DAC: 00000051 Process kworker/0:2 (pid: 62, stack limit = 0xedcb2210) Stack: (0xedcb3be8 to 0xedcb4000) [] (analogix_dp_transfer) from [] (drm_dp_i2c_do_msg+0x8c/0x2b4) [] (drm_dp_i2c_do_msg) from [] (drm_dp_i2c_xfer+0x98/0x214) [] (drm_dp_i2c_xfer) from [] (__i2c_transfer+0x140/0x29c) [] (__i2c_transfer) from [] (i2c_transfer+0x70/0xe4) [] (i2c_transfer) from [] (drm_do_probe_ddc_edid+0xb4/0x114) [] (drm_do_probe_ddc_edid) from [] (drm_probe_ddc+0x18/0x28) [] (drm_probe_ddc) from [] (drm_get_edid+0x124/0x2d4) [] (drm_get_edid) from [] (analogix_dp_get_modes+0x90/0x114) [] (analogix_dp_get_modes) from [] (drm_helper_probe_single_connector_modes+0x198/0x68c) [] (drm_helper_probe_single_connector_modes) from [] (drm_setup_crtcs+0x1b4/0xd18) [] (drm_setup_crtcs) from [] (drm_fb_helper_hotplug_event+0x94/0xd0) [] (drm_fb_helper_hotplug_event) from [] (drm_kms_helper_hotplug_event+0x24/0x28) [] (drm_kms_helper_hotplug_event) from [] (output_poll_execute+0x6c/0x174) [] (output_poll_execute) from [] (process_one_work+0x188/0x3fc) [] (process_one_work) from [] (worker_thread+0x30/0x4b8) [] (worker_thread) from [] (kthread+0x128/0x164) [] (kthread) from [] (ret_from_fork+0x14/0x24) Code: 0a000002 ea000009 e2544001 0a00004a (e59537c8) ---[ end trace cddc7919c79f7878 ]--- Reported-by: Misha Komarovskiy CC: stable@vger.kernel.org # v4.10+ Signed-off-by: Marek Szyprowski Signed-off-by: Archit Taneja Link: https://patchwork.freedesktop.org/patch/msgid/20171121074936.22520-1-m.szyprowski@samsung.com --- drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index 5dd3f1cd074a..a8905049b9da 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -946,7 +946,9 @@ static int analogix_dp_get_modes(struct drm_connector *connector) return 0; } + pm_runtime_get_sync(dp->dev); edid = drm_get_edid(connector, &dp->aux.ddc); + pm_runtime_put(dp->dev); if (edid) { drm_mode_connector_update_edid_property(&dp->connector, edid); -- GitLab From c5bbf358b790c8a7850188dea34601db703a97fa Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 9 Nov 2017 16:26:12 -0600 Subject: [PATCH 1036/2547] arm: dts: nspire: Add missing #phy-cells to usb-nop-xceiv "usb-nop-xceiv" is using the phy binding, but is missing #phy-cells property. This is probably because the binding was the precursor to the phy binding. Fixes the following warning in nspire dts files: Warning (phys_property): Missing property '#phy-cells' in node ... Signed-off-by: Rob Herring Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/nspire.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index ec2283b1a638..1a5ae4cd107f 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -56,6 +56,7 @@ usb_phy: usb_phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; vbus_reg: vbus_reg { -- GitLab From 863204cfdae98626a92535ac928ad79f4d6b74ff Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 6 Dec 2017 14:17:17 +0100 Subject: [PATCH 1037/2547] ARM: omap2: hide omap3_save_secure_ram on non-OMAP3 builds In configurations without CONFIG_OMAP3 but with secure RAM support, we now run into a link failure: arch/arm/mach-omap2/omap-secure.o: In function `omap3_save_secure_ram': omap-secure.c:(.text+0x130): undefined reference to `save_secure_ram_context' The omap3_save_secure_ram() function is only called from the OMAP34xx power management code, so we can simply hide that function in the appropriate #ifdef. Fixes: d09220a887f7 ("ARM: OMAP2+: Fix SRAM virt to phys translation for save_secure_ram_context") Acked-by: Tony Lindgren Tested-by: Dan Murphy Signed-off-by: Arnd Bergmann --- arch/arm/mach-omap2/omap-secure.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index 9ff92050053c..fa7f308c9027 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -73,6 +73,7 @@ phys_addr_t omap_secure_ram_mempool_base(void) return omap_secure_memblock_base; } +#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) u32 omap3_save_secure_ram(void __iomem *addr, int size) { u32 ret; @@ -91,6 +92,7 @@ u32 omap3_save_secure_ram(void __iomem *addr, int size) return ret; } +#endif /** * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls -- GitLab From 7eb781b1bbb7136fe78fb8c28c1c223c61fa32b5 Mon Sep 17 00:00:00 2001 From: weiping zhang Date: Wed, 6 Dec 2017 21:59:16 +0800 Subject: [PATCH 1038/2547] virtio_mmio: add cleanup for virtio_mmio_probe As mentioned at drivers/base/core.c: /* * NOTE: _Never_ directly free @dev after calling this function, even * if it returned an error! Always use put_device() to give up the * reference initialized in this function instead. */ so we don't free vm_dev until vm_dev.dev.release be called. Signed-off-by: weiping zhang Signed-off-by: Michael S. Tsirkin Reviewed-by: Cornelia Huck --- drivers/virtio/virtio_mmio.c | 51 +++++++++++++++++++++++++++++------- 1 file changed, 41 insertions(+), 10 deletions(-) diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 74dc7170fd35..ec401042a5d1 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -493,7 +493,16 @@ static const struct virtio_config_ops virtio_mmio_config_ops = { }; -static void virtio_mmio_release_dev_empty(struct device *_d) {} +static void virtio_mmio_release_dev(struct device *_d) +{ + struct virtio_device *vdev = + container_of(_d, struct virtio_device, dev); + struct virtio_mmio_device *vm_dev = + container_of(vdev, struct virtio_mmio_device, vdev); + struct platform_device *pdev = vm_dev->pdev; + + devm_kfree(&pdev->dev, vm_dev); +} /* Platform device */ @@ -513,25 +522,30 @@ static int virtio_mmio_probe(struct platform_device *pdev) return -EBUSY; vm_dev = devm_kzalloc(&pdev->dev, sizeof(*vm_dev), GFP_KERNEL); - if (!vm_dev) - return -ENOMEM; + if (!vm_dev) { + rc = -ENOMEM; + goto free_mem; + } vm_dev->vdev.dev.parent = &pdev->dev; - vm_dev->vdev.dev.release = virtio_mmio_release_dev_empty; + vm_dev->vdev.dev.release = virtio_mmio_release_dev; vm_dev->vdev.config = &virtio_mmio_config_ops; vm_dev->pdev = pdev; INIT_LIST_HEAD(&vm_dev->virtqueues); spin_lock_init(&vm_dev->lock); vm_dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); - if (vm_dev->base == NULL) - return -EFAULT; + if (vm_dev->base == NULL) { + rc = -EFAULT; + goto free_vmdev; + } /* Check magic value */ magic = readl(vm_dev->base + VIRTIO_MMIO_MAGIC_VALUE); if (magic != ('v' | 'i' << 8 | 'r' << 16 | 't' << 24)) { dev_warn(&pdev->dev, "Wrong magic value 0x%08lx!\n", magic); - return -ENODEV; + rc = -ENODEV; + goto unmap; } /* Check device version */ @@ -539,7 +553,8 @@ static int virtio_mmio_probe(struct platform_device *pdev) if (vm_dev->version < 1 || vm_dev->version > 2) { dev_err(&pdev->dev, "Version %ld not supported!\n", vm_dev->version); - return -ENXIO; + rc = -ENXIO; + goto unmap; } vm_dev->vdev.id.device = readl(vm_dev->base + VIRTIO_MMIO_DEVICE_ID); @@ -548,7 +563,8 @@ static int virtio_mmio_probe(struct platform_device *pdev) * virtio-mmio device with an ID 0 is a (dummy) placeholder * with no function. End probing now with no error reported. */ - return -ENODEV; + rc = -ENODEV; + goto unmap; } vm_dev->vdev.id.vendor = readl(vm_dev->base + VIRTIO_MMIO_VENDOR_ID); @@ -573,7 +589,22 @@ static int virtio_mmio_probe(struct platform_device *pdev) platform_set_drvdata(pdev, vm_dev); - return register_virtio_device(&vm_dev->vdev); + rc = register_virtio_device(&vm_dev->vdev); + if (rc) { + iounmap(vm_dev->base); + devm_release_mem_region(&pdev->dev, mem->start, + resource_size(mem)); + put_device(&vm_dev->vdev.dev); + } + return rc; +unmap: + iounmap(vm_dev->base); +free_mem: + devm_release_mem_region(&pdev->dev, mem->start, + resource_size(mem)); +free_vmdev: + devm_kfree(&pdev->dev, vm_dev); + return rc; } static int virtio_mmio_remove(struct platform_device *pdev) -- GitLab From 25f32223bce5c580e0392a176319a587d7a17e95 Mon Sep 17 00:00:00 2001 From: weiping zhang Date: Wed, 6 Dec 2017 21:59:32 +0800 Subject: [PATCH 1039/2547] virtio_mmio: add cleanup for virtio_mmio_remove cleanup all resource allocated by virtio_mmio_probe. Signed-off-by: weiping zhang Signed-off-by: Michael S. Tsirkin Reviewed-by: Cornelia Huck --- drivers/virtio/virtio_mmio.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index ec401042a5d1..a9192fe4f345 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -610,7 +610,13 @@ static int virtio_mmio_probe(struct platform_device *pdev) static int virtio_mmio_remove(struct platform_device *pdev) { struct virtio_mmio_device *vm_dev = platform_get_drvdata(pdev); + struct resource *mem; + iounmap(vm_dev->base); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (mem) + devm_release_mem_region(&pdev->dev, mem->start, + resource_size(mem)); unregister_virtio_device(&vm_dev->vdev); return 0; -- GitLab From 03e9f8a05bce7330bcd9c5cc54c8e42d0fcbf993 Mon Sep 17 00:00:00 2001 From: Yunjian Wang Date: Mon, 4 Dec 2017 14:02:19 +0800 Subject: [PATCH 1040/2547] virtio_net: fix return value check in receive_mergeable() The function virtqueue_get_buf_ctx() could return NULL, the return value 'buf' need to be checked with NULL, not value 'ctx'. Signed-off-by: Yunjian Wang Signed-off-by: Michael S. Tsirkin --- drivers/net/virtio_net.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 511f8339fa96..7927e28f5336 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -714,7 +714,7 @@ static struct sk_buff *receive_mergeable(struct net_device *dev, int num_skb_frags; buf = virtqueue_get_buf_ctx(rq->vq, &len, &ctx); - if (unlikely(!ctx)) { + if (unlikely(!buf)) { pr_debug("%s: rx error: %d buffers out of %d missing\n", dev->name, num_buf, virtio16_to_cpu(vi->vdev, -- GitLab From 54f539086ae8ed0297b02efb757b3be1a64a1cf2 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 5 Dec 2017 08:03:13 -0500 Subject: [PATCH 1041/2547] drm/amdgpu: Fix amdgpu_sync_add_later to preserve explicit flag. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index ebe1ffbab0c1..bb79fd3f3c36 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -120,7 +120,7 @@ static void amdgpu_sync_keep_later(struct dma_fence **keep, * Tries to add the fence to an existing hash entry. Returns true when an entry * was found, false otherwise. */ -static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f) +static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f, bool explicit) { struct amdgpu_sync_entry *e; @@ -129,6 +129,10 @@ static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f) continue; amdgpu_sync_keep_later(&e->fence, f); + + /* Preserve eplicit flag to not loose pipe line sync */ + e->explicit |= explicit; + return true; } return false; @@ -148,12 +152,11 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, if (!f) return 0; - if (amdgpu_sync_same_dev(adev, f) && amdgpu_sync_get_owner(f) == AMDGPU_FENCE_OWNER_VM) amdgpu_sync_keep_later(&sync->last_vm_update, f); - if (amdgpu_sync_add_later(sync, f)) + if (amdgpu_sync_add_later(sync, f, explicit)) return 0; e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL); -- GitLab From 1a09120f83a0f55a5a159b785104a5c8fa13c9ef Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Nov 2017 21:15:50 -0500 Subject: [PATCH 1042/2547] drm/amdgpu: add license to Makefiles MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Was missing license text. Acked-by: Harry Wentland Acked-by: Felix Kuehling Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/acp/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/amdgpu/Makefile | 22 +++++++++++++++++- drivers/gpu/drm/amd/amdkfd/Makefile | 22 +++++++++++++++++- drivers/gpu/drm/amd/display/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/basics/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/bios/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/calcs/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/dce100/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/dce110/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/dce112/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/dce120/Makefile | 23 ++++++++++++++++++- drivers/gpu/drm/amd/display/dc/dce80/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/dml/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/gpio/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/i2caux/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/irq/Makefile | 21 +++++++++++++++++ .../gpu/drm/amd/display/dc/virtual/Makefile | 21 +++++++++++++++++ .../drm/amd/display/modules/freesync/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/lib/Makefile | 21 +++++++++++++++++ drivers/gpu/drm/amd/powerplay/Makefile | 22 +++++++++++++++++- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 22 +++++++++++++++++- drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 22 +++++++++++++++++- 26 files changed, 547 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/acp/Makefile b/drivers/gpu/drm/amd/acp/Makefile index 8a08e81ee90d..d4176a3fb706 100644 --- a/drivers/gpu/drm/amd/acp/Makefile +++ b/drivers/gpu/drm/amd/acp/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the ACP, which is a sub-component # of AMDSOC/AMDGPU drm driver. # It provides the HW control for ACP related functionalities. diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 78d609123420..90202cf4cd1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# # # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 7bb0bc0ca3d6..342c2d937b17 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# # # Makefile for Heterogenous System Architecture support for AMD GPU devices # diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile index 8ba37dd9cf7f..c27c81cdeed3 100644 --- a/drivers/gpu/drm/amd/display/Makefile +++ b/drivers/gpu/drm/amd/display/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the DAL (Display Abstract Layer), which is a sub-component # of the AMDGPU drm driver. # It provides the HW control for display related functionalities. diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile index 4699e47aa76b..2b72009844f8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'dm' sub-component of DAL. # It provides the control and status of dm blocks. diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 4f83e3011743..aed538a4d1ba 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for Display Core (dc) component. # diff --git a/drivers/gpu/drm/amd/display/dc/basics/Makefile b/drivers/gpu/drm/amd/display/dc/basics/Makefile index 43c5ccdeeb72..6af8c8a9ad80 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/Makefile +++ b/drivers/gpu/drm/amd/display/dc/basics/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'utils' sub-component of DAL. # It provides the general basic services required by other DAL # subcomponents. diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile index 6ec815dce9cc..239e86bbec5a 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'bios' sub-component of DAL. # It provides the parsing and executing controls for atom bios image. diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile index 41ef35995b02..7959e382ed28 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'calcs' sub-component of DAL. # It calculates Bandwidth and Watermarks values for HW programming # diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile b/drivers/gpu/drm/amd/display/dc/dce/Makefile index 8abec0bed379..11401fd8e535 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for common 'dce' logic # HW object file under this folder follow similar pattern for HW programming # - register offset and/or shift + mask stored in the dec_hw struct diff --git a/drivers/gpu/drm/amd/display/dc/dce100/Makefile b/drivers/gpu/drm/amd/display/dc/dce100/Makefile index ea40870624b3..a822d4e2a169 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce100/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/dc/dce110/Makefile b/drivers/gpu/drm/amd/display/dc/dce110/Makefile index 98d956e2f218..d564c0eb8b04 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce110/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/dc/dce112/Makefile b/drivers/gpu/drm/amd/display/dc/dce112/Makefile index 265ac4310d85..8e090446d511 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce112/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile index 1779b963525c..37db1f8d45ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce120/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. @@ -8,4 +29,4 @@ dce120_hw_sequencer.o AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120)) -AMD_DISPLAY_FILES += $(AMD_DAL_DCE120) \ No newline at end of file +AMD_DISPLAY_FILES += $(AMD_DAL_DCE120) diff --git a/drivers/gpu/drm/amd/display/dc/dce80/Makefile b/drivers/gpu/drm/amd/display/dc/dce80/Makefile index c1105895e5fa..bc388aa4b2f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce80/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile index a6ca1f97f748..9eac228315b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for DCN. DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \ diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 87bab8e8139f..3488af2b5786 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'utils' sub-component of DAL. # It provides the general basic services required by other DAL # subcomponents. diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile index 70d01a9e9676..562ee189d780 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'gpio' sub-component of DAL. # It provides the control and status of HW GPIO pins. diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile index 55603400acd9..352885cb4d07 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile +++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'i2c' sub-component of DAL. # It provides the control and status of HW i2c engine of the adapter. diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index c7e93f7223bd..498515aad4a5 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'audio' sub-component of DAL. # It provides the control and status of HW adapter resources, # that are global for the ASIC and sharable between pipes. diff --git a/drivers/gpu/drm/amd/display/dc/virtual/Makefile b/drivers/gpu/drm/amd/display/dc/virtual/Makefile index fc0b7318d9cc..07326d244d50 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/Makefile +++ b/drivers/gpu/drm/amd/display/dc/virtual/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the virtual sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/modules/freesync/Makefile b/drivers/gpu/drm/amd/display/modules/freesync/Makefile index db8e0ff6d7a9..fb9a499780e8 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/Makefile +++ b/drivers/gpu/drm/amd/display/modules/freesync/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'freesync' sub-module of DAL. # diff --git a/drivers/gpu/drm/amd/lib/Makefile b/drivers/gpu/drm/amd/lib/Makefile index 87cd7009e80f..690243001e1a 100644 --- a/drivers/gpu/drm/amd/lib/Makefile +++ b/drivers/gpu/drm/amd/lib/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for AMD library routines, which are used by AMD driver # components. # diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile index 8c55c6e254d9..231785a9e24c 100644 --- a/drivers/gpu/drm/amd/powerplay/Makefile +++ b/drivers/gpu/drm/amd/powerplay/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# subdir-ccflags-y += \ -I$(FULL_AMD_PATH)/powerplay/inc/ \ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile index 824fb6fe54ae..a212c27f2e17 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# # # Makefile for the 'hw manager' sub-component of powerplay. # It provides the hardware management services for the driver. diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile index 30d3089d7dba..98e701e4f553 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# # # Makefile for the 'smu manager' sub-component of powerplay. # It provides the smu management services for the driver. -- GitLab From 9ce6aae12c66adf87b5861f8fa5705ea11d0b6ee Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Nov 2017 21:29:47 -0500 Subject: [PATCH 1043/2547] drm/amdgpu: add license to files where it was missing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These files were missing it before. Acked-by: Harry Wentland Acked-by: Felix Kuehling Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 24 ++++++++++++++++++- .../gpu/drm/amd/display/dc/core/dc_debug.c | 22 +++++++++++++++++ .../gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dc_helper.c | 22 +++++++++++++++++ .../amd/display/dc/dce100/dce100_resource.c | 2 +- .../amd/display/dc/dce100/dce100_resource.h | 23 ++++++++++++++++++ .../amd/display/dc/dce110/dce110_resource.c | 2 +- .../dc/dce110/dce110_timing_generator_v.c | 23 ++++++++++++++++++ .../drm/amd/display/dc/inc/hw/link_encoder.h | 22 +++++++++++++++++ .../amd/display/dc/inc/hw/stream_encoder.h | 22 +++++++++++++++++ .../drm/amd/powerplay/hwmgr/pp_overdriver.c | 24 ++++++++++++++++++- drivers/gpu/drm/amd/powerplay/inc/smu72.h | 24 ++++++++++++++++++- .../drm/amd/powerplay/inc/smu72_discrete.h | 24 ++++++++++++++++++- .../gpu/drm/amd/scheduler/gpu_sched_trace.h | 24 ++++++++++++++++++- 15 files changed, 254 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 6f56ff606e43..83205b93e62d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -1,4 +1,6 @@ /* + * Copyright 2017 Advanced Micro Devices, Inc. + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index f337c316ec2c..06525f2c36c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #if !defined(_AMDGPU_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) #define _AMDGPU_TRACE_H_ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 2e509382935f..1babac07bcc9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * dc_debug.c * diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 9c5e879f18b3..ad28eba017f2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1,5 +1,5 @@ /* -* Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index c584252669fd..48e1fcf53d43 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * dc_helper.c * diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 90911258bdb3..3ea43e2a9450 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -1,5 +1,5 @@ /* -* Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h index de8fdf438f9b..2f366d66635d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h @@ -1,3 +1,26 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ /* * dce100_resource.h * diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 5228ee78f7e6..7c4779578fb7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1,5 +1,5 @@ /* -* Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c index 07d9303d5477..59b4cd329715 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c @@ -1,3 +1,26 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #include "dm_services.h" /* include DCE11 register header files */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 8a08f0a97f94..0fd329deacd8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * link_encoder.h * diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 3050afe8e8a9..b5db1692393c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * stream_encoder.h * diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c index 67fae834bc67..8de384bf9a8f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c @@ -1,4 +1,26 @@ -// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #include "pp_overdriver.h" #include diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72.h b/drivers/gpu/drm/amd/powerplay/inc/smu72.h index 08cd70c75d8b..9ad1cefff79f 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu72.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu72.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #ifndef SMU72_H #define SMU72_H diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h index b2edbc0c3c4d..2aefbb85f620 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #ifndef SMU72_DISCRETE_H #define SMU72_DISCRETE_H diff --git a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h index eebe323c7159..b42a78922505 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #if !defined(_GPU_SCHED_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) #define _GPU_SCHED_TRACE_H_ -- GitLab From 1b1f42d8fde4fef1ed7873bf5aa91755f8c3de35 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Dec 2017 17:49:39 +0100 Subject: [PATCH 1044/2547] drm: move amd_gpu_scheduler into common location MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This moves and renames the AMDGPU scheduler to a common location in DRM in order to facilitate re-use by other drivers. This is mostly a straight forward rename with no code changes. One notable exception is the function to_drm_sched_fence(), which is no longer a inline header function to avoid the need to export the drm_sched_fence_ops_scheduled and drm_sched_fence_ops_finished structures. Reviewed-by: Chunming Zhou Tested-by: Dieter Nützel Acked-by: Alex Deucher Signed-off-by: Lucas Stach Signed-off-by: Alex Deucher --- drivers/gpu/drm/Kconfig | 5 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/amd/amdgpu/Makefile | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 38 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 20 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 14 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 12 +- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 20 +- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 14 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 7 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 8 +- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 8 +- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 186 ----------- drivers/gpu/drm/scheduler/Makefile | 4 + .../drm/{amd => }/scheduler/gpu_scheduler.c | 296 +++++++++--------- .../gpu/drm/{amd => }/scheduler/sched_fence.c | 118 ++++--- include/drm/gpu_scheduler.h | 176 +++++++++++ .../drm/gpu_scheduler_trace.h | 14 +- .../scheduler => include/drm}/spsc_queue.h | 7 +- 35 files changed, 530 insertions(+), 517 deletions(-) delete mode 100644 drivers/gpu/drm/amd/scheduler/gpu_scheduler.h create mode 100644 drivers/gpu/drm/scheduler/Makefile rename drivers/gpu/drm/{amd => }/scheduler/gpu_scheduler.c (65%) rename drivers/gpu/drm/{amd => }/scheduler/sched_fence.c (59%) create mode 100644 include/drm/gpu_scheduler.h rename drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h => include/drm/gpu_scheduler_trace.h (89%) rename {drivers/gpu/drm/amd/scheduler => include/drm}/spsc_queue.h (95%) diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 4d9f21831741..ee38a3db1890 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -149,6 +149,10 @@ config DRM_VM bool depends on DRM && MMU +config DRM_SCHED + tristate + depends on DRM + source "drivers/gpu/drm/i2c/Kconfig" source "drivers/gpu/drm/arm/Kconfig" @@ -178,6 +182,7 @@ config DRM_AMDGPU depends on DRM && PCI && MMU select FW_LOADER select DRM_KMS_HELPER + select DRM_SCHED select DRM_TTM select POWER_SUPPLY select HWMON diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index e9500844333e..1f6ba9e34e31 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -101,3 +101,4 @@ obj-$(CONFIG_DRM_MXSFB) += mxsfb/ obj-$(CONFIG_DRM_TINYDRM) += tinydrm/ obj-$(CONFIG_DRM_PL111) += pl111/ obj-$(CONFIG_DRM_TVE200) += tve200/ +obj-$(CONFIG_DRM_SCHED) += scheduler/ diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 90202cf4cd1e..a7391d49ad40 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -135,10 +135,7 @@ amdgpu-y += \ amdgpu-y += amdgpu_cgs.o # GPU scheduler -amdgpu-y += \ - ../scheduler/gpu_scheduler.o \ - ../scheduler/sched_fence.o \ - amdgpu_job.o +amdgpu-y += amdgpu_job.o # ACP componet ifneq ($(CONFIG_DRM_AMD_ACP),) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 5e2958a79928..5c8648ec2cd2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -45,6 +45,7 @@ #include #include #include +#include #include #include "dm_pp_interface.h" @@ -68,7 +69,6 @@ #include "amdgpu_vcn.h" #include "amdgpu_mn.h" #include "amdgpu_dm.h" -#include "gpu_scheduler.h" #include "amdgpu_virt.h" #include "amdgpu_gart.h" @@ -689,7 +689,7 @@ struct amdgpu_ib { uint32_t flags; }; -extern const struct amd_sched_backend_ops amdgpu_sched_ops; +extern const struct drm_sched_backend_ops amdgpu_sched_ops; int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, struct amdgpu_job **job, struct amdgpu_vm *vm); @@ -699,7 +699,7 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, void amdgpu_job_free_resources(struct amdgpu_job *job); void amdgpu_job_free(struct amdgpu_job *job); int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, - struct amd_sched_entity *entity, void *owner, + struct drm_sched_entity *entity, void *owner, struct dma_fence **f); /* @@ -732,7 +732,7 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev, struct amdgpu_ctx_ring { uint64_t sequence; struct dma_fence **fences; - struct amd_sched_entity entity; + struct drm_sched_entity entity; }; struct amdgpu_ctx { @@ -746,8 +746,8 @@ struct amdgpu_ctx { struct dma_fence **fences; struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; bool preamble_presented; - enum amd_sched_priority init_priority; - enum amd_sched_priority override_priority; + enum drm_sched_priority init_priority; + enum drm_sched_priority override_priority; struct mutex lock; atomic_t guilty; }; @@ -767,7 +767,7 @@ int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, uint64_t seq); void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, - enum amd_sched_priority priority); + enum drm_sched_priority priority); int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); @@ -1116,7 +1116,7 @@ struct amdgpu_cs_parser { #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ struct amdgpu_job { - struct amd_sched_job base; + struct drm_sched_job base; struct amdgpu_device *adev; struct amdgpu_vm *vm; struct amdgpu_ring *ring; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 4cea9ab237ac..44523a88ebb2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1150,7 +1150,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs) { struct amdgpu_ring *ring = p->job->ring; - struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity; + struct drm_sched_entity *entity = &p->ctx->rings[ring->idx].entity; struct amdgpu_job *job; unsigned i; uint64_t seq; @@ -1173,7 +1173,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, job = p->job; p->job = NULL; - r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp); + r = drm_sched_job_init(&job->base, &ring->sched, entity, p->filp); if (r) { amdgpu_job_free(job); amdgpu_mn_unlock(p->mn); @@ -1202,7 +1202,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, amdgpu_ring_priority_get(job->ring, job->base.s_priority); trace_amdgpu_cs_ioctl(job); - amd_sched_entity_push_job(&job->base, entity); + drm_sched_entity_push_job(&job->base, entity); ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence); amdgpu_mn_unlock(p->mn); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index d71dc164b469..09d35051fdd6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -28,10 +28,10 @@ #include "amdgpu_sched.h" static int amdgpu_ctx_priority_permit(struct drm_file *filp, - enum amd_sched_priority priority) + enum drm_sched_priority priority) { /* NORMAL and below are accessible by everyone */ - if (priority <= AMD_SCHED_PRIORITY_NORMAL) + if (priority <= DRM_SCHED_PRIORITY_NORMAL) return 0; if (capable(CAP_SYS_NICE)) @@ -44,14 +44,14 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp, } static int amdgpu_ctx_init(struct amdgpu_device *adev, - enum amd_sched_priority priority, + enum drm_sched_priority priority, struct drm_file *filp, struct amdgpu_ctx *ctx) { unsigned i, j; int r; - if (priority < 0 || priority >= AMD_SCHED_PRIORITY_MAX) + if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX) return -EINVAL; r = amdgpu_ctx_priority_permit(filp, priority); @@ -78,19 +78,19 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, ctx->reset_counter_query = ctx->reset_counter; ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter); ctx->init_priority = priority; - ctx->override_priority = AMD_SCHED_PRIORITY_UNSET; + ctx->override_priority = DRM_SCHED_PRIORITY_UNSET; /* create context entity for each ring */ for (i = 0; i < adev->num_rings; i++) { struct amdgpu_ring *ring = adev->rings[i]; - struct amd_sched_rq *rq; + struct drm_sched_rq *rq; rq = &ring->sched.sched_rq[priority]; if (ring == &adev->gfx.kiq.ring) continue; - r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity, + r = drm_sched_entity_init(&ring->sched, &ctx->rings[i].entity, rq, amdgpu_sched_jobs, &ctx->guilty); if (r) goto failed; @@ -104,7 +104,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, failed: for (j = 0; j < i; j++) - amd_sched_entity_fini(&adev->rings[j]->sched, + drm_sched_entity_fini(&adev->rings[j]->sched, &ctx->rings[j].entity); kfree(ctx->fences); ctx->fences = NULL; @@ -126,7 +126,7 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) ctx->fences = NULL; for (i = 0; i < adev->num_rings; i++) - amd_sched_entity_fini(&adev->rings[i]->sched, + drm_sched_entity_fini(&adev->rings[i]->sched, &ctx->rings[i].entity); amdgpu_queue_mgr_fini(adev, &ctx->queue_mgr); @@ -137,7 +137,7 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) static int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, struct drm_file *filp, - enum amd_sched_priority priority, + enum drm_sched_priority priority, uint32_t *id) { struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; @@ -266,7 +266,7 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, { int r; uint32_t id; - enum amd_sched_priority priority; + enum drm_sched_priority priority; union drm_amdgpu_ctx *args = data; struct amdgpu_device *adev = dev->dev_private; @@ -278,8 +278,8 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, /* For backwards compatibility reasons, we need to accept * ioctls with garbage in the priority field */ - if (priority == AMD_SCHED_PRIORITY_INVALID) - priority = AMD_SCHED_PRIORITY_NORMAL; + if (priority == DRM_SCHED_PRIORITY_INVALID) + priority = DRM_SCHED_PRIORITY_NORMAL; switch (args->in.op) { case AMDGPU_CTX_OP_ALLOC_CTX: @@ -385,18 +385,18 @@ struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, } void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, - enum amd_sched_priority priority) + enum drm_sched_priority priority) { int i; struct amdgpu_device *adev = ctx->adev; - struct amd_sched_rq *rq; - struct amd_sched_entity *entity; + struct drm_sched_rq *rq; + struct drm_sched_entity *entity; struct amdgpu_ring *ring; - enum amd_sched_priority ctx_prio; + enum drm_sched_priority ctx_prio; ctx->override_priority = priority; - ctx_prio = (ctx->override_priority == AMD_SCHED_PRIORITY_UNSET) ? + ctx_prio = (ctx->override_priority == DRM_SCHED_PRIORITY_UNSET) ? ctx->init_priority : ctx->override_priority; for (i = 0; i < adev->num_rings; i++) { @@ -407,7 +407,7 @@ void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) continue; - amd_sched_entity_set_rq(entity, rq); + drm_sched_entity_set_rq(entity, rq); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 70c9e5756b02..98cc4df02b14 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3058,7 +3058,7 @@ int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job) continue; kthread_park(ring->sched.thread); - amd_sched_hw_job_reset(&ring->sched, &job->base); + drm_sched_hw_job_reset(&ring->sched, &job->base); /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ amdgpu_fence_driver_force_completion(ring); @@ -3111,7 +3111,7 @@ int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job) if (job && job->ring->idx != i) continue; - amd_sched_job_recovery(&ring->sched); + drm_sched_job_recovery(&ring->sched); kthread_unpark(ring->sched.thread); } } else { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 31383e004947..1d8011bca182 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -912,7 +912,7 @@ static int __init amdgpu_init(void) if (r) goto error_fence; - r = amd_sched_fence_slab_init(); + r = drm_sched_fence_slab_init(); if (r) goto error_sched; @@ -944,7 +944,7 @@ static void __exit amdgpu_exit(void) pci_unregister_driver(pdriver); amdgpu_unregister_atpx_handler(); amdgpu_sync_fini(); - amd_sched_fence_slab_fini(); + drm_sched_fence_slab_fini(); amdgpu_fence_slab_fini(); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 604ac03a42e4..14699637913a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -445,7 +445,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, */ timeout = MAX_SCHEDULE_TIMEOUT; } - r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, + r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, num_hw_submission, amdgpu_job_hang_limit, timeout, ring->name); if (r) { @@ -503,7 +503,7 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev) } amdgpu_irq_put(adev, ring->fence_drv.irq_src, ring->fence_drv.irq_type); - amd_sched_fini(&ring->sched); + drm_sched_fini(&ring->sched); del_timer_sync(&ring->fence_drv.fallback_timer); for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) dma_fence_put(ring->fence_drv.fences[j]); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index bdc210ac74f8..013c0a8cfb60 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -28,7 +28,7 @@ #include "amdgpu.h" #include "amdgpu_trace.h" -static void amdgpu_job_timedout(struct amd_sched_job *s_job) +static void amdgpu_job_timedout(struct drm_sched_job *s_job) { struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base); @@ -96,7 +96,7 @@ void amdgpu_job_free_resources(struct amdgpu_job *job) amdgpu_ib_free(job->adev, &job->ibs[i], f); } -static void amdgpu_job_free_cb(struct amd_sched_job *s_job) +static void amdgpu_job_free_cb(struct drm_sched_job *s_job) { struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base); @@ -118,7 +118,7 @@ void amdgpu_job_free(struct amdgpu_job *job) } int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, - struct amd_sched_entity *entity, void *owner, + struct drm_sched_entity *entity, void *owner, struct dma_fence **f) { int r; @@ -127,7 +127,7 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, if (!f) return -EINVAL; - r = amd_sched_job_init(&job->base, &ring->sched, entity, owner); + r = drm_sched_job_init(&job->base, &ring->sched, entity, owner); if (r) return r; @@ -136,13 +136,13 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, *f = dma_fence_get(&job->base.s_fence->finished); amdgpu_job_free_resources(job); amdgpu_ring_priority_get(job->ring, job->base.s_priority); - amd_sched_entity_push_job(&job->base, entity); + drm_sched_entity_push_job(&job->base, entity); return 0; } -static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job, - struct amd_sched_entity *s_entity) +static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job, + struct drm_sched_entity *s_entity) { struct amdgpu_job *job = to_amdgpu_job(sched_job); struct amdgpu_vm *vm = job->vm; @@ -151,7 +151,7 @@ static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job, struct dma_fence *fence = amdgpu_sync_get_fence(&job->sync, &explicit); if (fence && explicit) { - if (amd_sched_dependency_optimized(fence, s_entity)) { + if (drm_sched_dependency_optimized(fence, s_entity)) { r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence, false); if (r) DRM_ERROR("Error adding fence to sync (%d)\n", r); @@ -173,7 +173,7 @@ static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job, return fence; } -static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job) +static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) { struct dma_fence *fence = NULL, *finished; struct amdgpu_device *adev; @@ -211,7 +211,7 @@ static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job) return fence; } -const struct amd_sched_backend_ops amdgpu_sched_ops = { +const struct drm_sched_backend_ops amdgpu_sched_ops = { .dependency = amdgpu_job_dependency, .run_job = amdgpu_job_run, .timedout_job = amdgpu_job_timedout, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index a98fbbb4739f..41c75f9632dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -164,7 +164,7 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) * Release a request for executing at @priority */ void amdgpu_ring_priority_put(struct amdgpu_ring *ring, - enum amd_sched_priority priority) + enum drm_sched_priority priority) { int i; @@ -175,7 +175,7 @@ void amdgpu_ring_priority_put(struct amdgpu_ring *ring, return; /* no need to restore if the job is already at the lowest priority */ - if (priority == AMD_SCHED_PRIORITY_NORMAL) + if (priority == DRM_SCHED_PRIORITY_NORMAL) return; mutex_lock(&ring->priority_mutex); @@ -184,8 +184,8 @@ void amdgpu_ring_priority_put(struct amdgpu_ring *ring, goto out_unlock; /* decay priority to the next level with a job available */ - for (i = priority; i >= AMD_SCHED_PRIORITY_MIN; i--) { - if (i == AMD_SCHED_PRIORITY_NORMAL + for (i = priority; i >= DRM_SCHED_PRIORITY_MIN; i--) { + if (i == DRM_SCHED_PRIORITY_NORMAL || atomic_read(&ring->num_jobs[i])) { ring->priority = i; ring->funcs->set_priority(ring, i); @@ -206,7 +206,7 @@ void amdgpu_ring_priority_put(struct amdgpu_ring *ring, * Request a ring's priority to be raised to @priority (refcounted). */ void amdgpu_ring_priority_get(struct amdgpu_ring *ring, - enum amd_sched_priority priority) + enum drm_sched_priority priority) { if (!ring->funcs->set_priority) return; @@ -317,12 +317,12 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, } ring->max_dw = max_dw; - ring->priority = AMD_SCHED_PRIORITY_NORMAL; + ring->priority = DRM_SCHED_PRIORITY_NORMAL; mutex_init(&ring->priority_mutex); INIT_LIST_HEAD(&ring->lru_list); amdgpu_ring_lru_touch(adev, ring); - for (i = 0; i < AMD_SCHED_PRIORITY_MAX; ++i) + for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i) atomic_set(&ring->num_jobs[i], 0); if (amdgpu_debugfs_ring_init(adev, ring)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index a6b89e3932a5..641e3fd7ba3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -25,7 +25,7 @@ #define __AMDGPU_RING_H__ #include -#include "gpu_scheduler.h" +#include /* max number of rings */ #define AMDGPU_MAX_RINGS 18 @@ -154,14 +154,14 @@ struct amdgpu_ring_funcs { void (*emit_tmz)(struct amdgpu_ring *ring, bool start); /* priority functions */ void (*set_priority) (struct amdgpu_ring *ring, - enum amd_sched_priority priority); + enum drm_sched_priority priority); }; struct amdgpu_ring { struct amdgpu_device *adev; const struct amdgpu_ring_funcs *funcs; struct amdgpu_fence_driver fence_drv; - struct amd_gpu_scheduler sched; + struct drm_gpu_scheduler sched; struct list_head lru_list; struct amdgpu_bo *ring_obj; @@ -196,7 +196,7 @@ struct amdgpu_ring { unsigned vm_inv_eng; bool has_compute_vm_bug; - atomic_t num_jobs[AMD_SCHED_PRIORITY_MAX]; + atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX]; struct mutex priority_mutex; /* protected by priority_mutex */ int priority; @@ -212,9 +212,9 @@ void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); void amdgpu_ring_commit(struct amdgpu_ring *ring); void amdgpu_ring_undo(struct amdgpu_ring *ring); void amdgpu_ring_priority_get(struct amdgpu_ring *ring, - enum amd_sched_priority priority); + enum drm_sched_priority priority); void amdgpu_ring_priority_put(struct amdgpu_ring *ring, - enum amd_sched_priority priority); + enum drm_sched_priority priority); int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned ring_size, struct amdgpu_irq_src *irq_src, unsigned irq_type); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c index 290cc3f9c433..86a0715d9431 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c @@ -29,29 +29,29 @@ #include "amdgpu_vm.h" -enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority) +enum drm_sched_priority amdgpu_to_sched_priority(int amdgpu_priority) { switch (amdgpu_priority) { case AMDGPU_CTX_PRIORITY_VERY_HIGH: - return AMD_SCHED_PRIORITY_HIGH_HW; + return DRM_SCHED_PRIORITY_HIGH_HW; case AMDGPU_CTX_PRIORITY_HIGH: - return AMD_SCHED_PRIORITY_HIGH_SW; + return DRM_SCHED_PRIORITY_HIGH_SW; case AMDGPU_CTX_PRIORITY_NORMAL: - return AMD_SCHED_PRIORITY_NORMAL; + return DRM_SCHED_PRIORITY_NORMAL; case AMDGPU_CTX_PRIORITY_LOW: case AMDGPU_CTX_PRIORITY_VERY_LOW: - return AMD_SCHED_PRIORITY_LOW; + return DRM_SCHED_PRIORITY_LOW; case AMDGPU_CTX_PRIORITY_UNSET: - return AMD_SCHED_PRIORITY_UNSET; + return DRM_SCHED_PRIORITY_UNSET; default: WARN(1, "Invalid context priority %d\n", amdgpu_priority); - return AMD_SCHED_PRIORITY_INVALID; + return DRM_SCHED_PRIORITY_INVALID; } } static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev, int fd, - enum amd_sched_priority priority) + enum drm_sched_priority priority) { struct file *filp = fcheck(fd); struct drm_file *file; @@ -86,11 +86,11 @@ int amdgpu_sched_ioctl(struct drm_device *dev, void *data, { union drm_amdgpu_sched *args = data; struct amdgpu_device *adev = dev->dev_private; - enum amd_sched_priority priority; + enum drm_sched_priority priority; int r; priority = amdgpu_to_sched_priority(args->in.priority); - if (args->in.flags || priority == AMD_SCHED_PRIORITY_INVALID) + if (args->in.flags || priority == DRM_SCHED_PRIORITY_INVALID) return -EINVAL; switch (args->in.op) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h index b28c067d3822..2a1a0c734bdd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h @@ -27,7 +27,7 @@ #include -enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority); +enum drm_sched_priority amdgpu_to_sched_priority(int amdgpu_priority); int amdgpu_sched_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index bb79fd3f3c36..df65c66dc956 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -64,7 +64,7 @@ void amdgpu_sync_create(struct amdgpu_sync *sync) static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct dma_fence *f) { - struct amd_sched_fence *s_fence = to_amd_sched_fence(f); + struct drm_sched_fence *s_fence = to_drm_sched_fence(f); if (s_fence) { struct amdgpu_ring *ring; @@ -85,7 +85,7 @@ static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, */ static void *amdgpu_sync_get_owner(struct dma_fence *f) { - struct amd_sched_fence *s_fence = to_amd_sched_fence(f); + struct drm_sched_fence *s_fence = to_drm_sched_fence(f); if (s_fence) return s_fence->owner; @@ -248,7 +248,7 @@ struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, hash_for_each_safe(sync->fences, i, tmp, e, node) { struct dma_fence *f = e->fence; - struct amd_sched_fence *s_fence = to_amd_sched_fence(f); + struct drm_sched_fence *s_fence = to_drm_sched_fence(f); if (dma_fence_is_signaled(f)) { hash_del(&e->node); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 952e0bf3bc84..7db9556b389b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -76,7 +76,7 @@ static int amdgpu_ttm_global_init(struct amdgpu_device *adev) { struct drm_global_reference *global_ref; struct amdgpu_ring *ring; - struct amd_sched_rq *rq; + struct drm_sched_rq *rq; int r; adev->mman.mem_global_referenced = false; @@ -108,8 +108,8 @@ static int amdgpu_ttm_global_init(struct amdgpu_device *adev) mutex_init(&adev->mman.gtt_window_lock); ring = adev->mman.buffer_funcs_ring; - rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; - r = amd_sched_entity_init(&ring->sched, &adev->mman.entity, + rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL]; + r = drm_sched_entity_init(&ring->sched, &adev->mman.entity, rq, amdgpu_sched_jobs, NULL); if (r) { DRM_ERROR("Failed setting up TTM BO move run queue.\n"); @@ -131,7 +131,7 @@ static int amdgpu_ttm_global_init(struct amdgpu_device *adev) static void amdgpu_ttm_global_fini(struct amdgpu_device *adev) { if (adev->mman.mem_global_referenced) { - amd_sched_entity_fini(adev->mman.entity.sched, + drm_sched_entity_fini(adev->mman.entity.sched, &adev->mman.entity); mutex_destroy(&adev->mman.gtt_window_lock); drm_global_item_unref(&adev->mman.bo_global_ref.ref); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 4f9433e61406..167856f6080f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -25,7 +25,7 @@ #define __AMDGPU_TTM_H__ #include "amdgpu.h" -#include "gpu_scheduler.h" +#include #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) @@ -55,7 +55,7 @@ struct amdgpu_mman { struct mutex gtt_window_lock; /* Scheduler entity for buffer moves */ - struct amd_sched_entity entity; + struct drm_sched_entity entity; }; struct amdgpu_copy_mem { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 2f2a9e17fdb4..916e51670bfd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -116,7 +116,7 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work); int amdgpu_uvd_sw_init(struct amdgpu_device *adev) { struct amdgpu_ring *ring; - struct amd_sched_rq *rq; + struct drm_sched_rq *rq; unsigned long bo_size; const char *fw_name; const struct common_firmware_header *hdr; @@ -230,8 +230,8 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) } ring = &adev->uvd.ring; - rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; - r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity, + rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; + r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity, rq, amdgpu_sched_jobs, NULL); if (r != 0) { DRM_ERROR("Failed setting up UVD run queue.\n"); @@ -272,7 +272,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) int i; kfree(adev->uvd.saved_bo); - amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); + drm_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo, &adev->uvd.gpu_addr, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h index 845eea993f75..32ea20b99e53 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h @@ -51,8 +51,8 @@ struct amdgpu_uvd { struct amdgpu_irq_src irq; bool address_64_bit; bool use_ctx_buf; - struct amd_sched_entity entity; - struct amd_sched_entity entity_enc; + struct drm_sched_entity entity; + struct drm_sched_entity entity_enc; uint32_t srbm_soft_reset; unsigned num_enc_rings; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index ba6d846b08ff..641deb0527ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -85,7 +85,7 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work); int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) { struct amdgpu_ring *ring; - struct amd_sched_rq *rq; + struct drm_sched_rq *rq; const char *fw_name; const struct common_firmware_header *hdr; unsigned ucode_version, version_major, version_minor, binary_id; @@ -174,8 +174,8 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) } ring = &adev->vce.ring[0]; - rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; - r = amd_sched_entity_init(&ring->sched, &adev->vce.entity, + rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; + r = drm_sched_entity_init(&ring->sched, &adev->vce.entity, rq, amdgpu_sched_jobs, NULL); if (r != 0) { DRM_ERROR("Failed setting up VCE run queue.\n"); @@ -207,7 +207,7 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev) if (adev->vce.vcpu_bo == NULL) return 0; - amd_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity); + drm_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity); amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr, (void **)&adev->vce.cpu_addr); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index 5ce54cde472d..162cae94e3b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -46,7 +46,7 @@ struct amdgpu_vce { struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; struct amdgpu_irq_src irq; unsigned harvest_config; - struct amd_sched_entity entity; + struct drm_sched_entity entity; uint32_t srbm_soft_reset; unsigned num_rings; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index d7ba048c2f80..88e204d537f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -51,7 +51,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work); int amdgpu_vcn_sw_init(struct amdgpu_device *adev) { struct amdgpu_ring *ring; - struct amd_sched_rq *rq; + struct drm_sched_rq *rq; unsigned long bo_size; const char *fw_name; const struct common_firmware_header *hdr; @@ -104,8 +104,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) } ring = &adev->vcn.ring_dec; - rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; - r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_dec, + rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; + r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_dec, rq, amdgpu_sched_jobs, NULL); if (r != 0) { DRM_ERROR("Failed setting up VCN dec run queue.\n"); @@ -113,8 +113,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) } ring = &adev->vcn.ring_enc[0]; - rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; - r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_enc, + rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; + r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_enc, rq, amdgpu_sched_jobs, NULL); if (r != 0) { DRM_ERROR("Failed setting up VCN enc run queue.\n"); @@ -130,9 +130,9 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) kfree(adev->vcn.saved_bo); - amd_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec); + drm_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec); - amd_sched_entity_fini(&adev->vcn.ring_enc[0].sched, &adev->vcn.entity_enc); + drm_sched_entity_fini(&adev->vcn.ring_enc[0].sched, &adev->vcn.entity_enc); amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo, &adev->vcn.gpu_addr, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index d50ba0657854..2fd7db891689 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -56,8 +56,8 @@ struct amdgpu_vcn { struct amdgpu_ring ring_dec; struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS]; struct amdgpu_irq_src irq; - struct amd_sched_entity entity_dec; - struct amd_sched_entity entity_enc; + struct drm_sched_entity entity_dec; + struct drm_sched_entity entity_enc; unsigned num_enc_rings; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 3ecdbdfb04dd..dbe37d621796 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2643,7 +2643,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, AMDGPU_VM_PTE_COUNT(adev) * 8); unsigned ring_instance; struct amdgpu_ring *ring; - struct amd_sched_rq *rq; + struct drm_sched_rq *rq; int r, i; u64 flags; uint64_t init_pde_value = 0; @@ -2663,8 +2663,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); ring_instance %= adev->vm_manager.vm_pte_num_rings; ring = adev->vm_manager.vm_pte_rings[ring_instance]; - rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; - r = amd_sched_entity_init(&ring->sched, &vm->entity, + rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL]; + r = drm_sched_entity_init(&ring->sched, &vm->entity, rq, amdgpu_sched_jobs, NULL); if (r) return r; @@ -2744,7 +2744,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, vm->root.base.bo = NULL; error_free_sched_entity: - amd_sched_entity_fini(&ring->sched, &vm->entity); + drm_sched_entity_fini(&ring->sched, &vm->entity); return r; } @@ -2803,7 +2803,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); } - amd_sched_entity_fini(vm->entity.sched, &vm->entity); + drm_sched_entity_fini(vm->entity.sched, &vm->entity); if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { dev_err(adev->dev, "still active bo inside vm\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 43ea131dd411..159980414964 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -24,10 +24,11 @@ #ifndef __AMDGPU_VM_H__ #define __AMDGPU_VM_H__ -#include #include +#include +#include +#include -#include "gpu_scheduler.h" #include "amdgpu_sync.h" #include "amdgpu_ring.h" @@ -175,7 +176,7 @@ struct amdgpu_vm { spinlock_t freed_lock; /* Scheduler entity for page table updates */ - struct amd_sched_entity entity; + struct drm_sched_entity entity; /* client id and PASID (TODO: replace client_id with PASID) */ u64 client_id; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index d02493cf9175..c7dc69031fb5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -6472,10 +6472,10 @@ static void gfx_v8_0_hqd_set_priority(struct amdgpu_device *adev, mutex_unlock(&adev->srbm_mutex); } static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring, - enum amd_sched_priority priority) + enum drm_sched_priority priority) { struct amdgpu_device *adev = ring->adev; - bool acquire = priority == AMD_SCHED_PRIORITY_HIGH_HW; + bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW; if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) return; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 0e8b887cf03e..86123448a8ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -412,10 +412,10 @@ static int uvd_v6_0_sw_init(void *handle) return r; if (uvd_v6_0_enc_support(adev)) { - struct amd_sched_rq *rq; + struct drm_sched_rq *rq; ring = &adev->uvd.ring_enc[0]; - rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; - r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, + rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; + r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, rq, amdgpu_sched_jobs, NULL); if (r) { DRM_ERROR("Failed setting up UVD ENC run queue.\n"); @@ -456,7 +456,7 @@ static int uvd_v6_0_sw_fini(void *handle) return r; if (uvd_v6_0_enc_support(adev)) { - amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc); + drm_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc); for (i = 0; i < adev->uvd.num_enc_rings; ++i) amdgpu_ring_fini(&adev->uvd.ring_enc[i]); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 660fa41dc877..416611150edd 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -385,7 +385,7 @@ static int uvd_v7_0_early_init(void *handle) static int uvd_v7_0_sw_init(void *handle) { struct amdgpu_ring *ring; - struct amd_sched_rq *rq; + struct drm_sched_rq *rq; int i, r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -416,8 +416,8 @@ static int uvd_v7_0_sw_init(void *handle) } ring = &adev->uvd.ring_enc[0]; - rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; - r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, + rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; + r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, rq, amdgpu_sched_jobs, NULL); if (r) { DRM_ERROR("Failed setting up UVD ENC run queue.\n"); @@ -472,7 +472,7 @@ static int uvd_v7_0_sw_fini(void *handle) if (r) return r; - amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc); + drm_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc); for (i = 0; i < adev->uvd.num_enc_rings; ++i) amdgpu_ring_fini(&adev->uvd.ring_enc[i]); diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h deleted file mode 100644 index b590fcc2786a..000000000000 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _GPU_SCHEDULER_H_ -#define _GPU_SCHEDULER_H_ - -#include -#include -#include "spsc_queue.h" - -struct amd_gpu_scheduler; -struct amd_sched_rq; - -enum amd_sched_priority { - AMD_SCHED_PRIORITY_MIN, - AMD_SCHED_PRIORITY_LOW = AMD_SCHED_PRIORITY_MIN, - AMD_SCHED_PRIORITY_NORMAL, - AMD_SCHED_PRIORITY_HIGH_SW, - AMD_SCHED_PRIORITY_HIGH_HW, - AMD_SCHED_PRIORITY_KERNEL, - AMD_SCHED_PRIORITY_MAX, - AMD_SCHED_PRIORITY_INVALID = -1, - AMD_SCHED_PRIORITY_UNSET = -2 -}; - - -/** - * A scheduler entity is a wrapper around a job queue or a group - * of other entities. Entities take turns emitting jobs from their - * job queues to corresponding hardware ring based on scheduling - * policy. -*/ -struct amd_sched_entity { - struct list_head list; - struct amd_sched_rq *rq; - spinlock_t rq_lock; - struct amd_gpu_scheduler *sched; - - spinlock_t queue_lock; - struct spsc_queue job_queue; - - atomic_t fence_seq; - uint64_t fence_context; - - struct dma_fence *dependency; - struct dma_fence_cb cb; - atomic_t *guilty; /* points to ctx's guilty */ -}; - -/** - * Run queue is a set of entities scheduling command submissions for - * one specific ring. It implements the scheduling policy that selects - * the next entity to emit commands from. -*/ -struct amd_sched_rq { - spinlock_t lock; - struct list_head entities; - struct amd_sched_entity *current_entity; -}; - -struct amd_sched_fence { - struct dma_fence scheduled; - struct dma_fence finished; - struct dma_fence_cb cb; - struct dma_fence *parent; - struct amd_gpu_scheduler *sched; - spinlock_t lock; - void *owner; -}; - -struct amd_sched_job { - struct spsc_node queue_node; - struct amd_gpu_scheduler *sched; - struct amd_sched_fence *s_fence; - struct dma_fence_cb finish_cb; - struct work_struct finish_work; - struct list_head node; - struct delayed_work work_tdr; - uint64_t id; - atomic_t karma; - enum amd_sched_priority s_priority; -}; - -extern const struct dma_fence_ops amd_sched_fence_ops_scheduled; -extern const struct dma_fence_ops amd_sched_fence_ops_finished; -static inline struct amd_sched_fence *to_amd_sched_fence(struct dma_fence *f) -{ - if (f->ops == &amd_sched_fence_ops_scheduled) - return container_of(f, struct amd_sched_fence, scheduled); - - if (f->ops == &amd_sched_fence_ops_finished) - return container_of(f, struct amd_sched_fence, finished); - - return NULL; -} - -static inline bool amd_sched_invalidate_job(struct amd_sched_job *s_job, int threshold) -{ - return (s_job && atomic_inc_return(&s_job->karma) > threshold); -} - -/** - * Define the backend operations called by the scheduler, - * these functions should be implemented in driver side -*/ -struct amd_sched_backend_ops { - struct dma_fence *(*dependency)(struct amd_sched_job *sched_job, - struct amd_sched_entity *s_entity); - struct dma_fence *(*run_job)(struct amd_sched_job *sched_job); - void (*timedout_job)(struct amd_sched_job *sched_job); - void (*free_job)(struct amd_sched_job *sched_job); -}; - -/** - * One scheduler is implemented for each hardware ring -*/ -struct amd_gpu_scheduler { - const struct amd_sched_backend_ops *ops; - uint32_t hw_submission_limit; - long timeout; - const char *name; - struct amd_sched_rq sched_rq[AMD_SCHED_PRIORITY_MAX]; - wait_queue_head_t wake_up_worker; - wait_queue_head_t job_scheduled; - atomic_t hw_rq_count; - atomic64_t job_id_count; - struct task_struct *thread; - struct list_head ring_mirror_list; - spinlock_t job_list_lock; - int hang_limit; -}; - -int amd_sched_init(struct amd_gpu_scheduler *sched, - const struct amd_sched_backend_ops *ops, - uint32_t hw_submission, unsigned hang_limit, long timeout, const char *name); -void amd_sched_fini(struct amd_gpu_scheduler *sched); - -int amd_sched_entity_init(struct amd_gpu_scheduler *sched, - struct amd_sched_entity *entity, - struct amd_sched_rq *rq, - uint32_t jobs, atomic_t* guilty); -void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, - struct amd_sched_entity *entity); -void amd_sched_entity_push_job(struct amd_sched_job *sched_job, - struct amd_sched_entity *entity); -void amd_sched_entity_set_rq(struct amd_sched_entity *entity, - struct amd_sched_rq *rq); - -int amd_sched_fence_slab_init(void); -void amd_sched_fence_slab_fini(void); - -struct amd_sched_fence *amd_sched_fence_create( - struct amd_sched_entity *s_entity, void *owner); -void amd_sched_fence_scheduled(struct amd_sched_fence *fence); -void amd_sched_fence_finished(struct amd_sched_fence *fence); -int amd_sched_job_init(struct amd_sched_job *job, - struct amd_gpu_scheduler *sched, - struct amd_sched_entity *entity, - void *owner); -void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_job *job); -void amd_sched_job_recovery(struct amd_gpu_scheduler *sched); -bool amd_sched_dependency_optimized(struct dma_fence* fence, - struct amd_sched_entity *entity); -void amd_sched_job_kickout(struct amd_sched_job *s_job); - -#endif diff --git a/drivers/gpu/drm/scheduler/Makefile b/drivers/gpu/drm/scheduler/Makefile new file mode 100644 index 000000000000..ed877912d06d --- /dev/null +++ b/drivers/gpu/drm/scheduler/Makefile @@ -0,0 +1,4 @@ +ccflags-y := -Iinclude/drm +gpu-sched-y := gpu_scheduler.o sched_fence.o + +obj-$(CONFIG_DRM_SCHED) += gpu-sched.o diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/scheduler/gpu_scheduler.c similarity index 65% rename from drivers/gpu/drm/amd/scheduler/gpu_scheduler.c rename to drivers/gpu/drm/scheduler/gpu_scheduler.c index dcb987e6d94a..2c18996d59c5 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/scheduler/gpu_scheduler.c @@ -19,37 +19,36 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * - * */ + #include #include #include #include #include -#include "gpu_scheduler.h" - -#include "spsc_queue.h" +#include +#include #define CREATE_TRACE_POINTS -#include "gpu_sched_trace.h" +#include -#define to_amd_sched_job(sched_job) \ - container_of((sched_job), struct amd_sched_job, queue_node) +#define to_drm_sched_job(sched_job) \ + container_of((sched_job), struct drm_sched_job, queue_node) -static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity); -static void amd_sched_wakeup(struct amd_gpu_scheduler *sched); -static void amd_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb); +static bool drm_sched_entity_is_ready(struct drm_sched_entity *entity); +static void drm_sched_wakeup(struct drm_gpu_scheduler *sched); +static void drm_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb); /* Initialize a given run queue struct */ -static void amd_sched_rq_init(struct amd_sched_rq *rq) +static void drm_sched_rq_init(struct drm_sched_rq *rq) { spin_lock_init(&rq->lock); INIT_LIST_HEAD(&rq->entities); rq->current_entity = NULL; } -static void amd_sched_rq_add_entity(struct amd_sched_rq *rq, - struct amd_sched_entity *entity) +static void drm_sched_rq_add_entity(struct drm_sched_rq *rq, + struct drm_sched_entity *entity) { if (!list_empty(&entity->list)) return; @@ -58,8 +57,8 @@ static void amd_sched_rq_add_entity(struct amd_sched_rq *rq, spin_unlock(&rq->lock); } -static void amd_sched_rq_remove_entity(struct amd_sched_rq *rq, - struct amd_sched_entity *entity) +static void drm_sched_rq_remove_entity(struct drm_sched_rq *rq, + struct drm_sched_entity *entity) { if (list_empty(&entity->list)) return; @@ -77,17 +76,17 @@ static void amd_sched_rq_remove_entity(struct amd_sched_rq *rq, * * Try to find a ready entity, returns NULL if none found. */ -static struct amd_sched_entity * -amd_sched_rq_select_entity(struct amd_sched_rq *rq) +static struct drm_sched_entity * +drm_sched_rq_select_entity(struct drm_sched_rq *rq) { - struct amd_sched_entity *entity; + struct drm_sched_entity *entity; spin_lock(&rq->lock); entity = rq->current_entity; if (entity) { list_for_each_entry_continue(entity, &rq->entities, list) { - if (amd_sched_entity_is_ready(entity)) { + if (drm_sched_entity_is_ready(entity)) { rq->current_entity = entity; spin_unlock(&rq->lock); return entity; @@ -97,7 +96,7 @@ amd_sched_rq_select_entity(struct amd_sched_rq *rq) list_for_each_entry(entity, &rq->entities, list) { - if (amd_sched_entity_is_ready(entity)) { + if (drm_sched_entity_is_ready(entity)) { rq->current_entity = entity; spin_unlock(&rq->lock); return entity; @@ -116,22 +115,22 @@ amd_sched_rq_select_entity(struct amd_sched_rq *rq) * Init a context entity used by scheduler when submit to HW ring. * * @sched The pointer to the scheduler - * @entity The pointer to a valid amd_sched_entity + * @entity The pointer to a valid drm_sched_entity * @rq The run queue this entity belongs * @kernel If this is an entity for the kernel * @jobs The max number of jobs in the job queue * * return 0 if succeed. negative error code on failure */ -int amd_sched_entity_init(struct amd_gpu_scheduler *sched, - struct amd_sched_entity *entity, - struct amd_sched_rq *rq, +int drm_sched_entity_init(struct drm_gpu_scheduler *sched, + struct drm_sched_entity *entity, + struct drm_sched_rq *rq, uint32_t jobs, atomic_t *guilty) { if (!(sched && entity && rq)) return -EINVAL; - memset(entity, 0, sizeof(struct amd_sched_entity)); + memset(entity, 0, sizeof(struct drm_sched_entity)); INIT_LIST_HEAD(&entity->list); entity->rq = rq; entity->sched = sched; @@ -146,6 +145,7 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched, return 0; } +EXPORT_SYMBOL(drm_sched_entity_init); /** * Query if entity is initialized @@ -155,8 +155,8 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched, * * return true if entity is initialized, false otherwise */ -static bool amd_sched_entity_is_initialized(struct amd_gpu_scheduler *sched, - struct amd_sched_entity *entity) +static bool drm_sched_entity_is_initialized(struct drm_gpu_scheduler *sched, + struct drm_sched_entity *entity) { return entity->sched == sched && entity->rq != NULL; @@ -169,7 +169,7 @@ static bool amd_sched_entity_is_initialized(struct amd_gpu_scheduler *sched, * * Return true if entity don't has any unscheduled jobs. */ -static bool amd_sched_entity_is_idle(struct amd_sched_entity *entity) +static bool drm_sched_entity_is_idle(struct drm_sched_entity *entity) { rmb(); if (spsc_queue_peek(&entity->job_queue) == NULL) @@ -185,7 +185,7 @@ static bool amd_sched_entity_is_idle(struct amd_sched_entity *entity) * * Return true if entity could provide a job. */ -static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity) +static bool drm_sched_entity_is_ready(struct drm_sched_entity *entity) { if (spsc_queue_peek(&entity->job_queue) == NULL) return false; @@ -204,12 +204,12 @@ static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity) * * Cleanup and free the allocated resources. */ -void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, - struct amd_sched_entity *entity) +void drm_sched_entity_fini(struct drm_gpu_scheduler *sched, + struct drm_sched_entity *entity) { int r; - if (!amd_sched_entity_is_initialized(sched, entity)) + if (!drm_sched_entity_is_initialized(sched, entity)) return; /** * The client will not queue more IBs during this fini, consume existing @@ -219,10 +219,10 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, r = -ERESTARTSYS; else r = wait_event_killable(sched->job_scheduled, - amd_sched_entity_is_idle(entity)); - amd_sched_entity_set_rq(entity, NULL); + drm_sched_entity_is_idle(entity)); + drm_sched_entity_set_rq(entity, NULL); if (r) { - struct amd_sched_job *job; + struct drm_sched_job *job; /* Park the kernel for a moment to make sure it isn't processing * our enity. @@ -236,37 +236,38 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, entity->dependency = NULL; } - while ((job = to_amd_sched_job(spsc_queue_pop(&entity->job_queue)))) { - struct amd_sched_fence *s_fence = job->s_fence; - amd_sched_fence_scheduled(s_fence); + while ((job = to_drm_sched_job(spsc_queue_pop(&entity->job_queue)))) { + struct drm_sched_fence *s_fence = job->s_fence; + drm_sched_fence_scheduled(s_fence); dma_fence_set_error(&s_fence->finished, -ESRCH); - amd_sched_fence_finished(s_fence); + drm_sched_fence_finished(s_fence); WARN_ON(s_fence->parent); dma_fence_put(&s_fence->finished); sched->ops->free_job(job); } } } +EXPORT_SYMBOL(drm_sched_entity_fini); -static void amd_sched_entity_wakeup(struct dma_fence *f, struct dma_fence_cb *cb) +static void drm_sched_entity_wakeup(struct dma_fence *f, struct dma_fence_cb *cb) { - struct amd_sched_entity *entity = - container_of(cb, struct amd_sched_entity, cb); + struct drm_sched_entity *entity = + container_of(cb, struct drm_sched_entity, cb); entity->dependency = NULL; dma_fence_put(f); - amd_sched_wakeup(entity->sched); + drm_sched_wakeup(entity->sched); } -static void amd_sched_entity_clear_dep(struct dma_fence *f, struct dma_fence_cb *cb) +static void drm_sched_entity_clear_dep(struct dma_fence *f, struct dma_fence_cb *cb) { - struct amd_sched_entity *entity = - container_of(cb, struct amd_sched_entity, cb); + struct drm_sched_entity *entity = + container_of(cb, struct drm_sched_entity, cb); entity->dependency = NULL; dma_fence_put(f); } -void amd_sched_entity_set_rq(struct amd_sched_entity *entity, - struct amd_sched_rq *rq) +void drm_sched_entity_set_rq(struct drm_sched_entity *entity, + struct drm_sched_rq *rq) { if (entity->rq == rq) return; @@ -274,37 +275,39 @@ void amd_sched_entity_set_rq(struct amd_sched_entity *entity, spin_lock(&entity->rq_lock); if (entity->rq) - amd_sched_rq_remove_entity(entity->rq, entity); + drm_sched_rq_remove_entity(entity->rq, entity); entity->rq = rq; if (rq) - amd_sched_rq_add_entity(rq, entity); + drm_sched_rq_add_entity(rq, entity); spin_unlock(&entity->rq_lock); } +EXPORT_SYMBOL(drm_sched_entity_set_rq); -bool amd_sched_dependency_optimized(struct dma_fence* fence, - struct amd_sched_entity *entity) +bool drm_sched_dependency_optimized(struct dma_fence* fence, + struct drm_sched_entity *entity) { - struct amd_gpu_scheduler *sched = entity->sched; - struct amd_sched_fence *s_fence; + struct drm_gpu_scheduler *sched = entity->sched; + struct drm_sched_fence *s_fence; if (!fence || dma_fence_is_signaled(fence)) return false; if (fence->context == entity->fence_context) return true; - s_fence = to_amd_sched_fence(fence); + s_fence = to_drm_sched_fence(fence); if (s_fence && s_fence->sched == sched) return true; return false; } +EXPORT_SYMBOL(drm_sched_dependency_optimized); -static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity) +static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity) { - struct amd_gpu_scheduler *sched = entity->sched; + struct drm_gpu_scheduler *sched = entity->sched; struct dma_fence * fence = entity->dependency; - struct amd_sched_fence *s_fence; + struct drm_sched_fence *s_fence; if (fence->context == entity->fence_context) { /* We can ignore fences from ourself */ @@ -312,7 +315,7 @@ static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity) return false; } - s_fence = to_amd_sched_fence(fence); + s_fence = to_drm_sched_fence(fence); if (s_fence && s_fence->sched == sched) { /* @@ -323,7 +326,7 @@ static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity) dma_fence_put(entity->dependency); entity->dependency = fence; if (!dma_fence_add_callback(fence, &entity->cb, - amd_sched_entity_clear_dep)) + drm_sched_entity_clear_dep)) return true; /* Ignore it when it is already scheduled */ @@ -332,25 +335,25 @@ static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity) } if (!dma_fence_add_callback(entity->dependency, &entity->cb, - amd_sched_entity_wakeup)) + drm_sched_entity_wakeup)) return true; dma_fence_put(entity->dependency); return false; } -static struct amd_sched_job * -amd_sched_entity_pop_job(struct amd_sched_entity *entity) +static struct drm_sched_job * +drm_sched_entity_pop_job(struct drm_sched_entity *entity) { - struct amd_gpu_scheduler *sched = entity->sched; - struct amd_sched_job *sched_job = to_amd_sched_job( + struct drm_gpu_scheduler *sched = entity->sched; + struct drm_sched_job *sched_job = to_drm_sched_job( spsc_queue_peek(&entity->job_queue)); if (!sched_job) return NULL; while ((entity->dependency = sched->ops->dependency(sched_job, entity))) - if (amd_sched_entity_add_dependency_cb(entity)) + if (drm_sched_entity_add_dependency_cb(entity)) return NULL; /* skip jobs from entity that marked guilty */ @@ -368,13 +371,13 @@ amd_sched_entity_pop_job(struct amd_sched_entity *entity) * * Returns 0 for success, negative error code otherwise. */ -void amd_sched_entity_push_job(struct amd_sched_job *sched_job, - struct amd_sched_entity *entity) +void drm_sched_entity_push_job(struct drm_sched_job *sched_job, + struct drm_sched_entity *entity) { - struct amd_gpu_scheduler *sched = sched_job->sched; + struct drm_gpu_scheduler *sched = sched_job->sched; bool first = false; - trace_amd_sched_job(sched_job, entity); + trace_drm_sched_job(sched_job, entity); spin_lock(&entity->queue_lock); first = spsc_queue_push(&entity->job_queue, &sched_job->queue_node); @@ -385,25 +388,26 @@ void amd_sched_entity_push_job(struct amd_sched_job *sched_job, if (first) { /* Add the entity to the run queue */ spin_lock(&entity->rq_lock); - amd_sched_rq_add_entity(entity->rq, entity); + drm_sched_rq_add_entity(entity->rq, entity); spin_unlock(&entity->rq_lock); - amd_sched_wakeup(sched); + drm_sched_wakeup(sched); } } +EXPORT_SYMBOL(drm_sched_entity_push_job); /* job_finish is called after hw fence signaled */ -static void amd_sched_job_finish(struct work_struct *work) +static void drm_sched_job_finish(struct work_struct *work) { - struct amd_sched_job *s_job = container_of(work, struct amd_sched_job, + struct drm_sched_job *s_job = container_of(work, struct drm_sched_job, finish_work); - struct amd_gpu_scheduler *sched = s_job->sched; + struct drm_gpu_scheduler *sched = s_job->sched; /* remove job from ring_mirror_list */ spin_lock(&sched->job_list_lock); list_del_init(&s_job->node); if (sched->timeout != MAX_SCHEDULE_TIMEOUT) { - struct amd_sched_job *next; + struct drm_sched_job *next; spin_unlock(&sched->job_list_lock); cancel_delayed_work_sync(&s_job->work_tdr); @@ -411,7 +415,7 @@ static void amd_sched_job_finish(struct work_struct *work) /* queue TDR for next job */ next = list_first_entry_or_null(&sched->ring_mirror_list, - struct amd_sched_job, node); + struct drm_sched_job, node); if (next) schedule_delayed_work(&next->work_tdr, sched->timeout); @@ -421,42 +425,42 @@ static void amd_sched_job_finish(struct work_struct *work) sched->ops->free_job(s_job); } -static void amd_sched_job_finish_cb(struct dma_fence *f, +static void drm_sched_job_finish_cb(struct dma_fence *f, struct dma_fence_cb *cb) { - struct amd_sched_job *job = container_of(cb, struct amd_sched_job, + struct drm_sched_job *job = container_of(cb, struct drm_sched_job, finish_cb); schedule_work(&job->finish_work); } -static void amd_sched_job_begin(struct amd_sched_job *s_job) +static void drm_sched_job_begin(struct drm_sched_job *s_job) { - struct amd_gpu_scheduler *sched = s_job->sched; + struct drm_gpu_scheduler *sched = s_job->sched; dma_fence_add_callback(&s_job->s_fence->finished, &s_job->finish_cb, - amd_sched_job_finish_cb); + drm_sched_job_finish_cb); spin_lock(&sched->job_list_lock); list_add_tail(&s_job->node, &sched->ring_mirror_list); if (sched->timeout != MAX_SCHEDULE_TIMEOUT && list_first_entry_or_null(&sched->ring_mirror_list, - struct amd_sched_job, node) == s_job) + struct drm_sched_job, node) == s_job) schedule_delayed_work(&s_job->work_tdr, sched->timeout); spin_unlock(&sched->job_list_lock); } -static void amd_sched_job_timedout(struct work_struct *work) +static void drm_sched_job_timedout(struct work_struct *work) { - struct amd_sched_job *job = container_of(work, struct amd_sched_job, + struct drm_sched_job *job = container_of(work, struct drm_sched_job, work_tdr.work); job->sched->ops->timedout_job(job); } -void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_job *bad) +void drm_sched_hw_job_reset(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad) { - struct amd_sched_job *s_job; - struct amd_sched_entity *entity, *tmp; + struct drm_sched_job *s_job; + struct drm_sched_entity *entity, *tmp; int i;; spin_lock(&sched->job_list_lock); @@ -471,14 +475,14 @@ void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_jo } spin_unlock(&sched->job_list_lock); - if (bad && bad->s_priority != AMD_SCHED_PRIORITY_KERNEL) { + if (bad && bad->s_priority != DRM_SCHED_PRIORITY_KERNEL) { atomic_inc(&bad->karma); /* don't increase @bad's karma if it's from KERNEL RQ, * becuase sometimes GPU hang would cause kernel jobs (like VM updating jobs) * corrupt but keep in mind that kernel jobs always considered good. */ - for (i = AMD_SCHED_PRIORITY_MIN; i < AMD_SCHED_PRIORITY_KERNEL; i++ ) { - struct amd_sched_rq *rq = &sched->sched_rq[i]; + for (i = DRM_SCHED_PRIORITY_MIN; i < DRM_SCHED_PRIORITY_KERNEL; i++ ) { + struct drm_sched_rq *rq = &sched->sched_rq[i]; spin_lock(&rq->lock); list_for_each_entry_safe(entity, tmp, &rq->entities, list) { @@ -495,30 +499,22 @@ void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_jo } } } +EXPORT_SYMBOL(drm_sched_hw_job_reset); -void amd_sched_job_kickout(struct amd_sched_job *s_job) -{ - struct amd_gpu_scheduler *sched = s_job->sched; - - spin_lock(&sched->job_list_lock); - list_del_init(&s_job->node); - spin_unlock(&sched->job_list_lock); -} - -void amd_sched_job_recovery(struct amd_gpu_scheduler *sched) +void drm_sched_job_recovery(struct drm_gpu_scheduler *sched) { - struct amd_sched_job *s_job, *tmp; + struct drm_sched_job *s_job, *tmp; bool found_guilty = false; int r; spin_lock(&sched->job_list_lock); s_job = list_first_entry_or_null(&sched->ring_mirror_list, - struct amd_sched_job, node); + struct drm_sched_job, node); if (s_job && sched->timeout != MAX_SCHEDULE_TIMEOUT) schedule_delayed_work(&s_job->work_tdr, sched->timeout); list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) { - struct amd_sched_fence *s_fence = s_job->s_fence; + struct drm_sched_fence *s_fence = s_job->s_fence; struct dma_fence *fence; uint64_t guilty_context; @@ -536,45 +532,47 @@ void amd_sched_job_recovery(struct amd_gpu_scheduler *sched) if (fence) { s_fence->parent = dma_fence_get(fence); r = dma_fence_add_callback(fence, &s_fence->cb, - amd_sched_process_job); + drm_sched_process_job); if (r == -ENOENT) - amd_sched_process_job(fence, &s_fence->cb); + drm_sched_process_job(fence, &s_fence->cb); else if (r) DRM_ERROR("fence add callback failed (%d)\n", r); dma_fence_put(fence); } else { - amd_sched_process_job(NULL, &s_fence->cb); + drm_sched_process_job(NULL, &s_fence->cb); } spin_lock(&sched->job_list_lock); } spin_unlock(&sched->job_list_lock); } +EXPORT_SYMBOL(drm_sched_job_recovery); /* init a sched_job with basic field */ -int amd_sched_job_init(struct amd_sched_job *job, - struct amd_gpu_scheduler *sched, - struct amd_sched_entity *entity, +int drm_sched_job_init(struct drm_sched_job *job, + struct drm_gpu_scheduler *sched, + struct drm_sched_entity *entity, void *owner) { job->sched = sched; job->s_priority = entity->rq - sched->sched_rq; - job->s_fence = amd_sched_fence_create(entity, owner); + job->s_fence = drm_sched_fence_create(entity, owner); if (!job->s_fence) return -ENOMEM; job->id = atomic64_inc_return(&sched->job_id_count); - INIT_WORK(&job->finish_work, amd_sched_job_finish); + INIT_WORK(&job->finish_work, drm_sched_job_finish); INIT_LIST_HEAD(&job->node); - INIT_DELAYED_WORK(&job->work_tdr, amd_sched_job_timedout); + INIT_DELAYED_WORK(&job->work_tdr, drm_sched_job_timedout); return 0; } +EXPORT_SYMBOL(drm_sched_job_init); /** * Return ture if we can push more jobs to the hw. */ -static bool amd_sched_ready(struct amd_gpu_scheduler *sched) +static bool drm_sched_ready(struct drm_gpu_scheduler *sched) { return atomic_read(&sched->hw_rq_count) < sched->hw_submission_limit; @@ -583,27 +581,27 @@ static bool amd_sched_ready(struct amd_gpu_scheduler *sched) /** * Wake up the scheduler when it is ready */ -static void amd_sched_wakeup(struct amd_gpu_scheduler *sched) +static void drm_sched_wakeup(struct drm_gpu_scheduler *sched) { - if (amd_sched_ready(sched)) + if (drm_sched_ready(sched)) wake_up_interruptible(&sched->wake_up_worker); } /** * Select next entity to process */ -static struct amd_sched_entity * -amd_sched_select_entity(struct amd_gpu_scheduler *sched) +static struct drm_sched_entity * +drm_sched_select_entity(struct drm_gpu_scheduler *sched) { - struct amd_sched_entity *entity; + struct drm_sched_entity *entity; int i; - if (!amd_sched_ready(sched)) + if (!drm_sched_ready(sched)) return NULL; /* Kernel run queue has higher priority than normal run queue*/ - for (i = AMD_SCHED_PRIORITY_MAX - 1; i >= AMD_SCHED_PRIORITY_MIN; i--) { - entity = amd_sched_rq_select_entity(&sched->sched_rq[i]); + for (i = DRM_SCHED_PRIORITY_MAX - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) { + entity = drm_sched_rq_select_entity(&sched->sched_rq[i]); if (entity) break; } @@ -611,22 +609,22 @@ amd_sched_select_entity(struct amd_gpu_scheduler *sched) return entity; } -static void amd_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb) +static void drm_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb) { - struct amd_sched_fence *s_fence = - container_of(cb, struct amd_sched_fence, cb); - struct amd_gpu_scheduler *sched = s_fence->sched; + struct drm_sched_fence *s_fence = + container_of(cb, struct drm_sched_fence, cb); + struct drm_gpu_scheduler *sched = s_fence->sched; dma_fence_get(&s_fence->finished); atomic_dec(&sched->hw_rq_count); - amd_sched_fence_finished(s_fence); + drm_sched_fence_finished(s_fence); - trace_amd_sched_process_job(s_fence); + trace_drm_sched_process_job(s_fence); dma_fence_put(&s_fence->finished); wake_up_interruptible(&sched->wake_up_worker); } -static bool amd_sched_blocked(struct amd_gpu_scheduler *sched) +static bool drm_sched_blocked(struct drm_gpu_scheduler *sched) { if (kthread_should_park()) { kthread_parkme(); @@ -636,52 +634,52 @@ static bool amd_sched_blocked(struct amd_gpu_scheduler *sched) return false; } -static int amd_sched_main(void *param) +static int drm_sched_main(void *param) { struct sched_param sparam = {.sched_priority = 1}; - struct amd_gpu_scheduler *sched = (struct amd_gpu_scheduler *)param; + struct drm_gpu_scheduler *sched = (struct drm_gpu_scheduler *)param; int r; sched_setscheduler(current, SCHED_FIFO, &sparam); while (!kthread_should_stop()) { - struct amd_sched_entity *entity = NULL; - struct amd_sched_fence *s_fence; - struct amd_sched_job *sched_job; + struct drm_sched_entity *entity = NULL; + struct drm_sched_fence *s_fence; + struct drm_sched_job *sched_job; struct dma_fence *fence; wait_event_interruptible(sched->wake_up_worker, - (!amd_sched_blocked(sched) && - (entity = amd_sched_select_entity(sched))) || + (!drm_sched_blocked(sched) && + (entity = drm_sched_select_entity(sched))) || kthread_should_stop()); if (!entity) continue; - sched_job = amd_sched_entity_pop_job(entity); + sched_job = drm_sched_entity_pop_job(entity); if (!sched_job) continue; s_fence = sched_job->s_fence; atomic_inc(&sched->hw_rq_count); - amd_sched_job_begin(sched_job); + drm_sched_job_begin(sched_job); fence = sched->ops->run_job(sched_job); - amd_sched_fence_scheduled(s_fence); + drm_sched_fence_scheduled(s_fence); if (fence) { s_fence->parent = dma_fence_get(fence); r = dma_fence_add_callback(fence, &s_fence->cb, - amd_sched_process_job); + drm_sched_process_job); if (r == -ENOENT) - amd_sched_process_job(fence, &s_fence->cb); + drm_sched_process_job(fence, &s_fence->cb); else if (r) DRM_ERROR("fence add callback failed (%d)\n", r); dma_fence_put(fence); } else { - amd_sched_process_job(NULL, &s_fence->cb); + drm_sched_process_job(NULL, &s_fence->cb); } wake_up(&sched->job_scheduled); @@ -699,8 +697,8 @@ static int amd_sched_main(void *param) * * Return 0 on success, otherwise error code. */ -int amd_sched_init(struct amd_gpu_scheduler *sched, - const struct amd_sched_backend_ops *ops, +int drm_sched_init(struct drm_gpu_scheduler *sched, + const struct drm_sched_backend_ops *ops, unsigned hw_submission, unsigned hang_limit, long timeout, @@ -712,8 +710,8 @@ int amd_sched_init(struct amd_gpu_scheduler *sched, sched->name = name; sched->timeout = timeout; sched->hang_limit = hang_limit; - for (i = AMD_SCHED_PRIORITY_MIN; i < AMD_SCHED_PRIORITY_MAX; i++) - amd_sched_rq_init(&sched->sched_rq[i]); + for (i = DRM_SCHED_PRIORITY_MIN; i < DRM_SCHED_PRIORITY_MAX; i++) + drm_sched_rq_init(&sched->sched_rq[i]); init_waitqueue_head(&sched->wake_up_worker); init_waitqueue_head(&sched->job_scheduled); @@ -723,7 +721,7 @@ int amd_sched_init(struct amd_gpu_scheduler *sched, atomic64_set(&sched->job_id_count, 0); /* Each scheduler will run on a seperate kernel thread */ - sched->thread = kthread_run(amd_sched_main, sched, sched->name); + sched->thread = kthread_run(drm_sched_main, sched, sched->name); if (IS_ERR(sched->thread)) { DRM_ERROR("Failed to create scheduler for %s.\n", name); return PTR_ERR(sched->thread); @@ -731,14 +729,16 @@ int amd_sched_init(struct amd_gpu_scheduler *sched, return 0; } +EXPORT_SYMBOL(drm_sched_init); /** * Destroy a gpu scheduler * * @sched The pointer to the scheduler */ -void amd_sched_fini(struct amd_gpu_scheduler *sched) +void drm_sched_fini(struct drm_gpu_scheduler *sched) { if (sched->thread) kthread_stop(sched->thread); } +EXPORT_SYMBOL(drm_sched_fini); diff --git a/drivers/gpu/drm/amd/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c similarity index 59% rename from drivers/gpu/drm/amd/scheduler/sched_fence.c rename to drivers/gpu/drm/scheduler/sched_fence.c index 33f54d0a5c4f..f6f2955890c4 100644 --- a/drivers/gpu/drm/amd/scheduler/sched_fence.c +++ b/drivers/gpu/drm/scheduler/sched_fence.c @@ -19,57 +19,36 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * - * */ + #include #include #include #include -#include "gpu_scheduler.h" +#include static struct kmem_cache *sched_fence_slab; -int amd_sched_fence_slab_init(void) +int drm_sched_fence_slab_init(void) { sched_fence_slab = kmem_cache_create( - "amd_sched_fence", sizeof(struct amd_sched_fence), 0, + "drm_sched_fence", sizeof(struct drm_sched_fence), 0, SLAB_HWCACHE_ALIGN, NULL); if (!sched_fence_slab) return -ENOMEM; return 0; } +EXPORT_SYMBOL_GPL(drm_sched_fence_slab_init); -void amd_sched_fence_slab_fini(void) +void drm_sched_fence_slab_fini(void) { rcu_barrier(); kmem_cache_destroy(sched_fence_slab); } +EXPORT_SYMBOL_GPL(drm_sched_fence_slab_fini); -struct amd_sched_fence *amd_sched_fence_create(struct amd_sched_entity *entity, - void *owner) -{ - struct amd_sched_fence *fence = NULL; - unsigned seq; - - fence = kmem_cache_zalloc(sched_fence_slab, GFP_KERNEL); - if (fence == NULL) - return NULL; - - fence->owner = owner; - fence->sched = entity->sched; - spin_lock_init(&fence->lock); - - seq = atomic_inc_return(&entity->fence_seq); - dma_fence_init(&fence->scheduled, &amd_sched_fence_ops_scheduled, - &fence->lock, entity->fence_context, seq); - dma_fence_init(&fence->finished, &amd_sched_fence_ops_finished, - &fence->lock, entity->fence_context + 1, seq); - - return fence; -} - -void amd_sched_fence_scheduled(struct amd_sched_fence *fence) +void drm_sched_fence_scheduled(struct drm_sched_fence *fence) { int ret = dma_fence_signal(&fence->scheduled); @@ -81,7 +60,7 @@ void amd_sched_fence_scheduled(struct amd_sched_fence *fence) "was already signaled\n"); } -void amd_sched_fence_finished(struct amd_sched_fence *fence) +void drm_sched_fence_finished(struct drm_sched_fence *fence) { int ret = dma_fence_signal(&fence->finished); @@ -93,18 +72,18 @@ void amd_sched_fence_finished(struct amd_sched_fence *fence) "was already signaled\n"); } -static const char *amd_sched_fence_get_driver_name(struct dma_fence *fence) +static const char *drm_sched_fence_get_driver_name(struct dma_fence *fence) { - return "amd_sched"; + return "drm_sched"; } -static const char *amd_sched_fence_get_timeline_name(struct dma_fence *f) +static const char *drm_sched_fence_get_timeline_name(struct dma_fence *f) { - struct amd_sched_fence *fence = to_amd_sched_fence(f); + struct drm_sched_fence *fence = to_drm_sched_fence(f); return (const char *)fence->sched->name; } -static bool amd_sched_fence_enable_signaling(struct dma_fence *f) +static bool drm_sched_fence_enable_signaling(struct dma_fence *f) { return true; } @@ -116,10 +95,10 @@ static bool amd_sched_fence_enable_signaling(struct dma_fence *f) * * Free up the fence memory after the RCU grace period. */ -static void amd_sched_fence_free(struct rcu_head *rcu) +static void drm_sched_fence_free(struct rcu_head *rcu) { struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); - struct amd_sched_fence *fence = to_amd_sched_fence(f); + struct drm_sched_fence *fence = to_drm_sched_fence(f); dma_fence_put(fence->parent); kmem_cache_free(sched_fence_slab, fence); @@ -133,11 +112,11 @@ static void amd_sched_fence_free(struct rcu_head *rcu) * This function is called when the reference count becomes zero. * It just RCU schedules freeing up the fence. */ -static void amd_sched_fence_release_scheduled(struct dma_fence *f) +static void drm_sched_fence_release_scheduled(struct dma_fence *f) { - struct amd_sched_fence *fence = to_amd_sched_fence(f); + struct drm_sched_fence *fence = to_drm_sched_fence(f); - call_rcu(&fence->finished.rcu, amd_sched_fence_free); + call_rcu(&fence->finished.rcu, drm_sched_fence_free); } /** @@ -147,27 +126,62 @@ static void amd_sched_fence_release_scheduled(struct dma_fence *f) * * Drop the extra reference from the scheduled fence to the base fence. */ -static void amd_sched_fence_release_finished(struct dma_fence *f) +static void drm_sched_fence_release_finished(struct dma_fence *f) { - struct amd_sched_fence *fence = to_amd_sched_fence(f); + struct drm_sched_fence *fence = to_drm_sched_fence(f); dma_fence_put(&fence->scheduled); } -const struct dma_fence_ops amd_sched_fence_ops_scheduled = { - .get_driver_name = amd_sched_fence_get_driver_name, - .get_timeline_name = amd_sched_fence_get_timeline_name, - .enable_signaling = amd_sched_fence_enable_signaling, +const struct dma_fence_ops drm_sched_fence_ops_scheduled = { + .get_driver_name = drm_sched_fence_get_driver_name, + .get_timeline_name = drm_sched_fence_get_timeline_name, + .enable_signaling = drm_sched_fence_enable_signaling, .signaled = NULL, .wait = dma_fence_default_wait, - .release = amd_sched_fence_release_scheduled, + .release = drm_sched_fence_release_scheduled, }; -const struct dma_fence_ops amd_sched_fence_ops_finished = { - .get_driver_name = amd_sched_fence_get_driver_name, - .get_timeline_name = amd_sched_fence_get_timeline_name, - .enable_signaling = amd_sched_fence_enable_signaling, +const struct dma_fence_ops drm_sched_fence_ops_finished = { + .get_driver_name = drm_sched_fence_get_driver_name, + .get_timeline_name = drm_sched_fence_get_timeline_name, + .enable_signaling = drm_sched_fence_enable_signaling, .signaled = NULL, .wait = dma_fence_default_wait, - .release = amd_sched_fence_release_finished, + .release = drm_sched_fence_release_finished, }; + +struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f) +{ + if (f->ops == &drm_sched_fence_ops_scheduled) + return container_of(f, struct drm_sched_fence, scheduled); + + if (f->ops == &drm_sched_fence_ops_finished) + return container_of(f, struct drm_sched_fence, finished); + + return NULL; +} +EXPORT_SYMBOL(to_drm_sched_fence); + +struct drm_sched_fence *drm_sched_fence_create(struct drm_sched_entity *entity, + void *owner) +{ + struct drm_sched_fence *fence = NULL; + unsigned seq; + + fence = kmem_cache_zalloc(sched_fence_slab, GFP_KERNEL); + if (fence == NULL) + return NULL; + + fence->owner = owner; + fence->sched = entity->sched; + spin_lock_init(&fence->lock); + + seq = atomic_inc_return(&entity->fence_seq); + dma_fence_init(&fence->scheduled, &drm_sched_fence_ops_scheduled, + &fence->lock, entity->fence_context, seq); + dma_fence_init(&fence->finished, &drm_sched_fence_ops_finished, + &fence->lock, entity->fence_context + 1, seq); + + return fence; +} diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h new file mode 100644 index 000000000000..d29da4cbb042 --- /dev/null +++ b/include/drm/gpu_scheduler.h @@ -0,0 +1,176 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _DRM_GPU_SCHEDULER_H_ +#define _DRM_GPU_SCHEDULER_H_ + +#include +#include + +struct drm_gpu_scheduler; +struct drm_sched_rq; + +enum drm_sched_priority { + DRM_SCHED_PRIORITY_MIN, + DRM_SCHED_PRIORITY_LOW = DRM_SCHED_PRIORITY_MIN, + DRM_SCHED_PRIORITY_NORMAL, + DRM_SCHED_PRIORITY_HIGH_SW, + DRM_SCHED_PRIORITY_HIGH_HW, + DRM_SCHED_PRIORITY_KERNEL, + DRM_SCHED_PRIORITY_MAX, + DRM_SCHED_PRIORITY_INVALID = -1, + DRM_SCHED_PRIORITY_UNSET = -2 +}; + +/** + * A scheduler entity is a wrapper around a job queue or a group + * of other entities. Entities take turns emitting jobs from their + * job queues to corresponding hardware ring based on scheduling + * policy. +*/ +struct drm_sched_entity { + struct list_head list; + struct drm_sched_rq *rq; + spinlock_t rq_lock; + struct drm_gpu_scheduler *sched; + + spinlock_t queue_lock; + struct spsc_queue job_queue; + + atomic_t fence_seq; + uint64_t fence_context; + + struct dma_fence *dependency; + struct dma_fence_cb cb; + atomic_t *guilty; /* points to ctx's guilty */ +}; + +/** + * Run queue is a set of entities scheduling command submissions for + * one specific ring. It implements the scheduling policy that selects + * the next entity to emit commands from. +*/ +struct drm_sched_rq { + spinlock_t lock; + struct list_head entities; + struct drm_sched_entity *current_entity; +}; + +struct drm_sched_fence { + struct dma_fence scheduled; + struct dma_fence finished; + struct dma_fence_cb cb; + struct dma_fence *parent; + struct drm_gpu_scheduler *sched; + spinlock_t lock; + void *owner; +}; + +struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f); + +struct drm_sched_job { + struct spsc_node queue_node; + struct drm_gpu_scheduler *sched; + struct drm_sched_fence *s_fence; + struct dma_fence_cb finish_cb; + struct work_struct finish_work; + struct list_head node; + struct delayed_work work_tdr; + uint64_t id; + atomic_t karma; + enum drm_sched_priority s_priority; +}; + +static inline bool drm_sched_invalidate_job(struct drm_sched_job *s_job, + int threshold) +{ + return (s_job && atomic_inc_return(&s_job->karma) > threshold); +} + +/** + * Define the backend operations called by the scheduler, + * these functions should be implemented in driver side +*/ +struct drm_sched_backend_ops { + struct dma_fence *(*dependency)(struct drm_sched_job *sched_job, + struct drm_sched_entity *s_entity); + struct dma_fence *(*run_job)(struct drm_sched_job *sched_job); + void (*timedout_job)(struct drm_sched_job *sched_job); + void (*free_job)(struct drm_sched_job *sched_job); +}; + +/** + * One scheduler is implemented for each hardware ring +*/ +struct drm_gpu_scheduler { + const struct drm_sched_backend_ops *ops; + uint32_t hw_submission_limit; + long timeout; + const char *name; + struct drm_sched_rq sched_rq[DRM_SCHED_PRIORITY_MAX]; + wait_queue_head_t wake_up_worker; + wait_queue_head_t job_scheduled; + atomic_t hw_rq_count; + atomic64_t job_id_count; + struct task_struct *thread; + struct list_head ring_mirror_list; + spinlock_t job_list_lock; + int hang_limit; +}; + +int drm_sched_init(struct drm_gpu_scheduler *sched, + const struct drm_sched_backend_ops *ops, + uint32_t hw_submission, unsigned hang_limit, long timeout, + const char *name); +void drm_sched_fini(struct drm_gpu_scheduler *sched); + +int drm_sched_entity_init(struct drm_gpu_scheduler *sched, + struct drm_sched_entity *entity, + struct drm_sched_rq *rq, + uint32_t jobs, atomic_t *guilty); +void drm_sched_entity_fini(struct drm_gpu_scheduler *sched, + struct drm_sched_entity *entity); +void drm_sched_entity_push_job(struct drm_sched_job *sched_job, + struct drm_sched_entity *entity); +void drm_sched_entity_set_rq(struct drm_sched_entity *entity, + struct drm_sched_rq *rq); + +int drm_sched_fence_slab_init(void); +void drm_sched_fence_slab_fini(void); + +struct drm_sched_fence *drm_sched_fence_create( + struct drm_sched_entity *s_entity, void *owner); +void drm_sched_fence_scheduled(struct drm_sched_fence *fence); +void drm_sched_fence_finished(struct drm_sched_fence *fence); +int drm_sched_job_init(struct drm_sched_job *job, + struct drm_gpu_scheduler *sched, + struct drm_sched_entity *entity, + void *owner); +void drm_sched_hw_job_reset(struct drm_gpu_scheduler *sched, + struct drm_sched_job *job); +void drm_sched_job_recovery(struct drm_gpu_scheduler *sched); +bool drm_sched_dependency_optimized(struct dma_fence* fence, + struct drm_sched_entity *entity); +void drm_sched_job_kickout(struct drm_sched_job *s_job); + +#endif diff --git a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h b/include/drm/gpu_scheduler_trace.h similarity index 89% rename from drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h rename to include/drm/gpu_scheduler_trace.h index b42a78922505..0789e8d0a0e1 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h +++ b/include/drm/gpu_scheduler_trace.h @@ -31,14 +31,14 @@ #include #undef TRACE_SYSTEM -#define TRACE_SYSTEM gpu_sched -#define TRACE_INCLUDE_FILE gpu_sched_trace +#define TRACE_SYSTEM gpu_scheduler +#define TRACE_INCLUDE_FILE gpu_scheduler_trace -TRACE_EVENT(amd_sched_job, - TP_PROTO(struct amd_sched_job *sched_job, struct amd_sched_entity *entity), +TRACE_EVENT(drm_sched_job, + TP_PROTO(struct drm_sched_job *sched_job, struct drm_sched_entity *entity), TP_ARGS(sched_job, entity), TP_STRUCT__entry( - __field(struct amd_sched_entity *, entity) + __field(struct drm_sched_entity *, entity) __field(struct dma_fence *, fence) __field(const char *, name) __field(uint64_t, id) @@ -61,8 +61,8 @@ TRACE_EVENT(amd_sched_job, __entry->job_count, __entry->hw_job_count) ); -TRACE_EVENT(amd_sched_process_job, - TP_PROTO(struct amd_sched_fence *fence), +TRACE_EVENT(drm_sched_process_job, + TP_PROTO(struct drm_sched_fence *fence), TP_ARGS(fence), TP_STRUCT__entry( __field(struct dma_fence *, fence) diff --git a/drivers/gpu/drm/amd/scheduler/spsc_queue.h b/include/drm/spsc_queue.h similarity index 95% rename from drivers/gpu/drm/amd/scheduler/spsc_queue.h rename to include/drm/spsc_queue.h index 5902f35ce759..125f096c88cb 100644 --- a/drivers/gpu/drm/amd/scheduler/spsc_queue.h +++ b/include/drm/spsc_queue.h @@ -21,10 +21,11 @@ * */ -#ifndef AMD_SCHEDULER_SPSC_QUEUE_H_ -#define AMD_SCHEDULER_SPSC_QUEUE_H_ +#ifndef DRM_SCHEDULER_SPSC_QUEUE_H_ +#define DRM_SCHEDULER_SPSC_QUEUE_H_ #include +#include /** SPSC lockless queue */ @@ -118,4 +119,4 @@ static inline struct spsc_node *spsc_queue_pop(struct spsc_queue *queue) -#endif /* AMD_SCHEDULER_SPSC_QUEUE_H_ */ +#endif /* DRM_SCHEDULER_SPSC_QUEUE_H_ */ -- GitLab From 4983e48c8539282be15f660bdd2c4260467b1190 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Dec 2017 17:49:40 +0100 Subject: [PATCH 1045/2547] drm/sched: move fence slab handling to module init/exit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is the only part of the scheduler which must not be called from different drivers. Move it to module init/exit so it is done a single time when loading the scheduler. Reviewed-by: Chunming Zhou Tested-by: Dieter Nützel Acked-by: Alex Deucher Signed-off-by: Lucas Stach Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 -------- drivers/gpu/drm/scheduler/sched_fence.c | 12 ++++++++---- include/drm/gpu_scheduler.h | 3 --- 3 files changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 1d8011bca182..51b76688ab90 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -912,10 +912,6 @@ static int __init amdgpu_init(void) if (r) goto error_fence; - r = drm_sched_fence_slab_init(); - if (r) - goto error_sched; - if (vgacon_text_force()) { DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); return -EINVAL; @@ -928,9 +924,6 @@ static int __init amdgpu_init(void) /* let modprobe override vga console setting */ return pci_register_driver(pdriver); -error_sched: - amdgpu_fence_slab_fini(); - error_fence: amdgpu_sync_fini(); @@ -944,7 +937,6 @@ static void __exit amdgpu_exit(void) pci_unregister_driver(pdriver); amdgpu_unregister_atpx_handler(); amdgpu_sync_fini(); - drm_sched_fence_slab_fini(); amdgpu_fence_slab_fini(); } diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c index f6f2955890c4..69aab086b913 100644 --- a/drivers/gpu/drm/scheduler/sched_fence.c +++ b/drivers/gpu/drm/scheduler/sched_fence.c @@ -29,7 +29,7 @@ static struct kmem_cache *sched_fence_slab; -int drm_sched_fence_slab_init(void) +static int __init drm_sched_fence_slab_init(void) { sched_fence_slab = kmem_cache_create( "drm_sched_fence", sizeof(struct drm_sched_fence), 0, @@ -39,14 +39,12 @@ int drm_sched_fence_slab_init(void) return 0; } -EXPORT_SYMBOL_GPL(drm_sched_fence_slab_init); -void drm_sched_fence_slab_fini(void) +static void __exit drm_sched_fence_slab_fini(void) { rcu_barrier(); kmem_cache_destroy(sched_fence_slab); } -EXPORT_SYMBOL_GPL(drm_sched_fence_slab_fini); void drm_sched_fence_scheduled(struct drm_sched_fence *fence) { @@ -185,3 +183,9 @@ struct drm_sched_fence *drm_sched_fence_create(struct drm_sched_entity *entity, return fence; } + +module_init(drm_sched_fence_slab_init); +module_exit(drm_sched_fence_slab_fini); + +MODULE_DESCRIPTION("DRM GPU scheduler"); +MODULE_LICENSE("GPL and additional rights"); diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index d29da4cbb042..dfd54fb94e10 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_scheduler.h @@ -155,9 +155,6 @@ void drm_sched_entity_push_job(struct drm_sched_job *sched_job, void drm_sched_entity_set_rq(struct drm_sched_entity *entity, struct drm_sched_rq *rq); -int drm_sched_fence_slab_init(void); -void drm_sched_fence_slab_fini(void); - struct drm_sched_fence *drm_sched_fence_create( struct drm_sched_entity *s_entity, void *owner); void drm_sched_fence_scheduled(struct drm_sched_fence *fence); -- GitLab From 8205f8840f753a36038ae76023ceab32e0e43934 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 6 Dec 2017 14:52:08 -0500 Subject: [PATCH 1046/2547] drm/scheduler: add license to the Makefile MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Was missing before. Reviewed-by: Chunming Zhou Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/scheduler/Makefile | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/scheduler/Makefile b/drivers/gpu/drm/scheduler/Makefile index ed877912d06d..bd0377c0d2ee 100644 --- a/drivers/gpu/drm/scheduler/Makefile +++ b/drivers/gpu/drm/scheduler/Makefile @@ -1,3 +1,25 @@ +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# ccflags-y := -Iinclude/drm gpu-sched-y := gpu_scheduler.o sched_fence.o -- GitLab From 589bf32f09852041fbd3b7ce1a9e703f95c230ba Mon Sep 17 00:00:00 2001 From: Tobias Jordan Date: Wed, 6 Dec 2017 15:23:23 +0100 Subject: [PATCH 1047/2547] net: mvmdio: disable/unprepare clocks in EPROBE_DEFER case add appropriate calls to clk_disable_unprepare() by jumping to out_mdio in case orion_mdio_probe() returns -EPROBE_DEFER. Found by Linux Driver Verification project (linuxtesting.org). Fixes: 3d604da1e954 ("net: mvmdio: get and enable optional clock") Signed-off-by: Tobias Jordan Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- drivers/net/ethernet/marvell/mvmdio.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvmdio.c b/drivers/net/ethernet/marvell/mvmdio.c index c9798210fa0f..0495487f7b42 100644 --- a/drivers/net/ethernet/marvell/mvmdio.c +++ b/drivers/net/ethernet/marvell/mvmdio.c @@ -344,7 +344,8 @@ static int orion_mdio_probe(struct platform_device *pdev) dev->regs + MVMDIO_ERR_INT_MASK); } else if (dev->err_interrupt == -EPROBE_DEFER) { - return -EPROBE_DEFER; + ret = -EPROBE_DEFER; + goto out_mdio; } if (pdev->dev.of_node) -- GitLab From e46772a6946a7d1f3fbbc1415871851d6651f1d4 Mon Sep 17 00:00:00 2001 From: Branislav Radocaj Date: Thu, 7 Dec 2017 00:07:38 +0100 Subject: [PATCH 1048/2547] net: ethernet: arc: fix error handling in emac_rockchip_probe If clk_set_rate() fails, we should disable clk before return. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Branislav Radocaj Signed-off-by: David S. Miller --- drivers/net/ethernet/arc/emac_rockchip.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/arc/emac_rockchip.c b/drivers/net/ethernet/arc/emac_rockchip.c index e278e3d96ee0..c6163874e4e7 100644 --- a/drivers/net/ethernet/arc/emac_rockchip.c +++ b/drivers/net/ethernet/arc/emac_rockchip.c @@ -220,9 +220,11 @@ static int emac_rockchip_probe(struct platform_device *pdev) /* RMII TX/RX needs always a rate of 25MHz */ err = clk_set_rate(priv->macclk, 25000000); - if (err) + if (err) { dev_err(dev, "failed to change mac clock rate (%d)\n", err); + goto out_clk_disable_macclk; + } } err = arc_emac_probe(ndev, interface); @@ -232,7 +234,8 @@ static int emac_rockchip_probe(struct platform_device *pdev) } return 0; - +out_clk_disable_macclk: + clk_disable_unprepare(priv->macclk); out_regulator_disable: if (priv->regulator) regulator_disable(priv->regulator); -- GitLab From 3d5fdba1842bdd2eef29364c660558cb4cbb3fe0 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Thu, 7 Dec 2017 01:05:56 +0100 Subject: [PATCH 1049/2547] net: dsa: mv88e6xxx: Fix interrupt masking on removal When removing the interrupt handling code, we should mask the generation of interrupts. The code however unmasked all interrupts. This can then cause a new interrupt. We then get into a deadlock where the interrupt thread is waiting to run, and the code continues, trying to remove the interrupt handler, which means waiting for the thread to complete. On a UP machine this deadlocks. Fix so we really mask interrupts in the hardware. The same error is made in the error path when install the interrupt handling code. Fixes: 3460a5770ce9 ("net: dsa: mv88e6xxx: Mask g1 interrupts and free interrupt") Signed-off-by: Andrew Lunn Reviewed-by: Vivien Didelot Signed-off-by: David S. Miller --- drivers/net/dsa/mv88e6xxx/chip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 8171055fde7a..70004264f60d 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -339,7 +339,7 @@ static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) u16 mask; mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); - mask |= GENMASK(chip->g1_irq.nirqs, 0); + mask &= ~GENMASK(chip->g1_irq.nirqs, 0); mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); free_irq(chip->irq, chip); @@ -395,7 +395,7 @@ static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) return 0; out_disable: - mask |= GENMASK(chip->g1_irq.nirqs, 0); + mask &= ~GENMASK(chip->g1_irq.nirqs, 0); mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); out_mapping: -- GitLab From 3126aeec5313565bfa19e2dd8fd7e3c3390514cb Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Thu, 7 Dec 2017 01:05:57 +0100 Subject: [PATCH 1050/2547] net: dsa: mv88e6xxx: Unregister MDIO bus on error path The MDIO busses need to be unregistered before they are freed, otherwise BUG() is called. Add a call to the unregister code if the registration fails, since we can have multiple busses, of which some may correctly register before one fails. This requires moving the code around a little. Fixes: a3c53be55c95 ("net: dsa: mv88e6xxx: Support multiple MDIO busses") Signed-off-by: Andrew Lunn Reviewed-by: Vivien Didelot Signed-off-by: David S. Miller --- drivers/net/dsa/mv88e6xxx/chip.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 70004264f60d..66d33e97cbc5 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2177,6 +2177,19 @@ static const struct of_device_id mv88e6xxx_mdio_external_match[] = { { }, }; +static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) + +{ + struct mv88e6xxx_mdio_bus *mdio_bus; + struct mii_bus *bus; + + list_for_each_entry(mdio_bus, &chip->mdios, list) { + bus = mdio_bus->bus; + + mdiobus_unregister(bus); + } +} + static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, struct device_node *np) { @@ -2201,27 +2214,16 @@ static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, match = of_match_node(mv88e6xxx_mdio_external_match, child); if (match) { err = mv88e6xxx_mdio_register(chip, child, true); - if (err) + if (err) { + mv88e6xxx_mdios_unregister(chip); return err; + } } } return 0; } -static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) - -{ - struct mv88e6xxx_mdio_bus *mdio_bus; - struct mii_bus *bus; - - list_for_each_entry(mdio_bus, &chip->mdios, list) { - bus = mdio_bus->bus; - - mdiobus_unregister(bus); - } -} - static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) { struct mv88e6xxx_chip *chip = ds->priv; -- GitLab From 74c4b656c3d92ec4c824ea1a4afd726b7b6568c8 Mon Sep 17 00:00:00 2001 From: "Nikita V. Shirokov" Date: Wed, 6 Dec 2017 17:15:43 -0800 Subject: [PATCH 1051/2547] adding missing rcu_read_unlock in ipxip6_rcv commit 8d79266bc48c ("ip6_tunnel: add collect_md mode to IPv6 tunnels") introduced new exit point in ipxip6_rcv. however rcu_read_unlock is missing there. this diff is fixing this v1->v2: instead of doing rcu_read_unlock in place, we are going to "drop" section (to prevent skb leakage) Fixes: 8d79266bc48c ("ip6_tunnel: add collect_md mode to IPv6 tunnels") Signed-off-by: Nikita V. Shirokov Acked-by: Alexei Starovoitov Signed-off-by: David S. Miller --- net/ipv6/ip6_tunnel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/ipv6/ip6_tunnel.c b/net/ipv6/ip6_tunnel.c index 3d3092adf1d2..db84f523656d 100644 --- a/net/ipv6/ip6_tunnel.c +++ b/net/ipv6/ip6_tunnel.c @@ -904,7 +904,7 @@ static int ipxip6_rcv(struct sk_buff *skb, u8 ipproto, if (t->parms.collect_md) { tun_dst = ipv6_tun_rx_dst(skb, 0, 0, 0); if (!tun_dst) - return 0; + goto drop; } ret = __ip6_tnl_rcv(t, skb, tpi, tun_dst, dscp_ecn_decapsulate, log_ecn_error); -- GitLab From 6e237d099fac1f73a7b6d7287bb9191f29585a4e Mon Sep 17 00:00:00 2001 From: David Ahern Date: Wed, 6 Dec 2017 20:09:12 -0800 Subject: [PATCH 1052/2547] netlink: Relax attr validation for fixed length types Commit 28033ae4e0f5 ("net: netlink: Update attr validation to require exact length for some types") requires attributes using types NLA_U* and NLA_S* to have an exact length. This change is exposing bugs in various userspace commands that are sending attributes with an invalid length (e.g., attribute has type NLA_U8 and userspace sends NLA_U32). While the commands are clearly broken and need to be fixed, users are arguing that the sudden change in enforcement is breaking older commands on newer kernels for use cases that otherwise "worked". Relax the validation to print a warning mesage similar to what is done for messages containing extra bytes after parsing. Fixes: 28033ae4e0f5 ("net: netlink: Update attr validation to require exact length for some types") Signed-off-by: David Ahern Reviewed-by: Johannes Berg Signed-off-by: David S. Miller --- lib/nlattr.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/lib/nlattr.c b/lib/nlattr.c index 8bf78b4b78f0..dfa55c873c13 100644 --- a/lib/nlattr.c +++ b/lib/nlattr.c @@ -15,7 +15,11 @@ #include #include -/* for these data types attribute length must be exactly given size */ +/* For these data types, attribute length should be exactly the given + * size. However, to maintain compatibility with broken commands, if the + * attribute length does not match the expected size a warning is emitted + * to the user that the command is sending invalid data and needs to be fixed. + */ static const u8 nla_attr_len[NLA_TYPE_MAX+1] = { [NLA_U8] = sizeof(u8), [NLA_U16] = sizeof(u16), @@ -28,8 +32,16 @@ static const u8 nla_attr_len[NLA_TYPE_MAX+1] = { }; static const u8 nla_attr_minlen[NLA_TYPE_MAX+1] = { + [NLA_U8] = sizeof(u8), + [NLA_U16] = sizeof(u16), + [NLA_U32] = sizeof(u32), + [NLA_U64] = sizeof(u64), [NLA_MSECS] = sizeof(u64), [NLA_NESTED] = NLA_HDRLEN, + [NLA_S8] = sizeof(s8), + [NLA_S16] = sizeof(s16), + [NLA_S32] = sizeof(s32), + [NLA_S64] = sizeof(s64), }; static int validate_nla_bitfield32(const struct nlattr *nla, @@ -69,11 +81,9 @@ static int validate_nla(const struct nlattr *nla, int maxtype, BUG_ON(pt->type > NLA_TYPE_MAX); - /* for data types NLA_U* and NLA_S* require exact length */ - if (nla_attr_len[pt->type]) { - if (attrlen != nla_attr_len[pt->type]) - return -ERANGE; - return 0; + if (nla_attr_len[pt->type] && attrlen != nla_attr_len[pt->type]) { + pr_warn_ratelimited("netlink: '%s': attribute type %d has an invalid length.\n", + current->comm, type); } switch (pt->type) { -- GitLab From 8632385022f2b05a6ca0b9e0f95575865de0e2ce Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 6 Dec 2017 11:08:19 -0800 Subject: [PATCH 1053/2547] tcp: use current time in tcp_rcv_space_adjust() When I switched rcv_rtt_est to high resolution timestamps, I forgot that tp->tcp_mstamp needed to be refreshed in tcp_rcv_space_adjust() Using an old timestamp leads to autotuning lags. Fixes: 645f4c6f2ebd ("tcp: switch rcv_rtt_est and rcvq_space to high resolution timestamps") Signed-off-by: Eric Dumazet Cc: Wei Wang Cc: Neal Cardwell Cc: Yuchung Cheng Acked-by: Neal Cardwell Signed-off-by: David S. Miller --- net/ipv4/tcp_input.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index 734cfc8ff76e..514c00732988 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -579,6 +579,7 @@ void tcp_rcv_space_adjust(struct sock *sk) int time; int copied; + tcp_mstamp_refresh(tp); time = tcp_stamp_us_delta(tp->tcp_mstamp, tp->rcvq_space.time); if (time < (tp->rcv_rtt_est.rtt_us >> 3) || tp->rcv_rtt_est.rtt_us == 0) return; -- GitLab From a4abd7a80addb4a9547f7dfc7812566b60ec505c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= Date: Wed, 6 Dec 2017 20:21:24 +0100 Subject: [PATCH 1054/2547] usbnet: fix alignment for frames with no ethernet header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The qmi_wwan minidriver support a 'raw-ip' mode where frames are received without any ethernet header. This causes alignment issues because the skbs allocated by usbnet are "IP aligned". Fix by allowing minidrivers to disable the additional alignment offset. This is implemented using a per-device flag, since the same minidriver also supports 'ethernet' mode. Fixes: 32f7adf633b9 ("net: qmi_wwan: support "raw IP" mode") Reported-and-tested-by: Jay Foster Signed-off-by: Bjørn Mork Signed-off-by: David S. Miller --- drivers/net/usb/qmi_wwan.c | 2 ++ drivers/net/usb/usbnet.c | 5 ++++- include/linux/usb/usbnet.h | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c index c750cf7c042b..304ec6555cd8 100644 --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c @@ -261,9 +261,11 @@ static void qmi_wwan_netdev_setup(struct net_device *net) net->hard_header_len = 0; net->addr_len = 0; net->flags = IFF_POINTOPOINT | IFF_NOARP | IFF_MULTICAST; + set_bit(EVENT_NO_IP_ALIGN, &dev->flags); netdev_dbg(net, "mode: raw IP\n"); } else if (!net->header_ops) { /* don't bother if already set */ ether_setup(net); + clear_bit(EVENT_NO_IP_ALIGN, &dev->flags); netdev_dbg(net, "mode: Ethernet\n"); } diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c index 80348b6a8646..d56fe32bf48d 100644 --- a/drivers/net/usb/usbnet.c +++ b/drivers/net/usb/usbnet.c @@ -484,7 +484,10 @@ static int rx_submit (struct usbnet *dev, struct urb *urb, gfp_t flags) return -ENOLINK; } - skb = __netdev_alloc_skb_ip_align(dev->net, size, flags); + if (test_bit(EVENT_NO_IP_ALIGN, &dev->flags)) + skb = __netdev_alloc_skb(dev->net, size, flags); + else + skb = __netdev_alloc_skb_ip_align(dev->net, size, flags); if (!skb) { netif_dbg(dev, rx_err, dev->net, "no rx skb\n"); usbnet_defer_kevent (dev, EVENT_RX_MEMORY); diff --git a/include/linux/usb/usbnet.h b/include/linux/usb/usbnet.h index a69877734c4e..e2ec3582e549 100644 --- a/include/linux/usb/usbnet.h +++ b/include/linux/usb/usbnet.h @@ -82,6 +82,7 @@ struct usbnet { # define EVENT_RX_KILL 10 # define EVENT_LINK_CHANGE 11 # define EVENT_SET_RX_MODE 12 +# define EVENT_NO_IP_ALIGN 13 }; static inline struct usb_driver *driver_of(struct usb_interface *intf) -- GitLab From 4cae8ff136782d77b108cb3a5ba53e60597ba3a6 Mon Sep 17 00:00:00 2001 From: Daniel Jurgens Date: Tue, 5 Dec 2017 22:30:01 +0200 Subject: [PATCH 1055/2547] IB/core: Bound check alternate path port number The alternate port number is used as an array index in the IB security implementation, invalid values can result in a kernel panic. Cc: # v4.12 Fixes: d291f1a65232 ("IB/core: Enforce PKey security on QPs") Signed-off-by: Daniel Jurgens Reviewed-by: Parav Pandit Signed-off-by: Leon Romanovsky Signed-off-by: Doug Ledford --- drivers/infiniband/core/uverbs_cmd.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/infiniband/core/uverbs_cmd.c b/drivers/infiniband/core/uverbs_cmd.c index 16d55710b116..d0202bb176a4 100644 --- a/drivers/infiniband/core/uverbs_cmd.c +++ b/drivers/infiniband/core/uverbs_cmd.c @@ -1971,6 +1971,12 @@ static int modify_qp(struct ib_uverbs_file *file, goto release_qp; } + if ((cmd->base.attr_mask & IB_QP_ALT_PATH) && + !rdma_is_port_valid(qp->device, cmd->base.alt_port_num)) { + ret = -EINVAL; + goto release_qp; + } + attr->qp_state = cmd->base.qp_state; attr->cur_qp_state = cmd->base.cur_qp_state; attr->path_mtu = cmd->base.path_mtu; -- GitLab From 0fbe8f575b15585eec3326e43708fbbc024e8486 Mon Sep 17 00:00:00 2001 From: Daniel Jurgens Date: Tue, 5 Dec 2017 22:30:02 +0200 Subject: [PATCH 1056/2547] IB/core: Don't enforce PKey security on SMI MADs Per the infiniband spec an SMI MAD can have any PKey. Checking the pkey on SMI MADs is not necessary, and it seems that some older adapters using the mthca driver don't follow the convention of using the default PKey, resulting in false denials, or errors querying the PKey cache. SMI MAD security is still enforced, only agents allowed to manage the subnet are able to receive or send SMI MADs. Reported-by: Chris Blake Cc: # v4.12 Fixes: 47a2b338fe63 ("IB/core: Enforce security on management datagrams") Signed-off-by: Daniel Jurgens Reviewed-by: Parav Pandit Signed-off-by: Leon Romanovsky Signed-off-by: Doug Ledford --- drivers/infiniband/core/security.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/core/security.c b/drivers/infiniband/core/security.c index a337386652b0..feafdb961c48 100644 --- a/drivers/infiniband/core/security.c +++ b/drivers/infiniband/core/security.c @@ -739,8 +739,11 @@ int ib_mad_enforce_security(struct ib_mad_agent_private *map, u16 pkey_index) if (!rdma_protocol_ib(map->agent.device, map->agent.port_num)) return 0; - if (map->agent.qp->qp_type == IB_QPT_SMI && !map->agent.smp_allowed) - return -EACCES; + if (map->agent.qp->qp_type == IB_QPT_SMI) { + if (!map->agent.smp_allowed) + return -EACCES; + return 0; + } return ib_security_pkey_access(map->agent.device, map->agent.port_num, -- GitLab From 4d02ebd9bbbdde1d524e62b540b0402cee7bbcdf Mon Sep 17 00:00:00 2001 From: Guy Levi Date: Tue, 5 Dec 2017 22:30:03 +0200 Subject: [PATCH 1057/2547] IB/mlx4: Fix RSS hash fields restrictions Mistakenly the driver didn't allow RSS hash fields combinations which involve both IPv4 and IPv6 protocols. This bug caused to failures for user's use cases for RSS. Consequently, this patch fixes this bug and allows any combination that the HW can support. Additionally, the patch fixes the driver to return an error in case the user provides an unsupported mask for RSS hash fields. Fixes: 3078f5f1bd8b ("IB/mlx4: Add support for RSS QP") Signed-off-by: Guy Levi Reviewed-by: Yishai Hadas Signed-off-by: Leon Romanovsky Signed-off-by: Doug Ledford --- drivers/infiniband/hw/mlx4/qp.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c index 013049bcdb53..caf490ab24c8 100644 --- a/drivers/infiniband/hw/mlx4/qp.c +++ b/drivers/infiniband/hw/mlx4/qp.c @@ -666,6 +666,19 @@ static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, return (-EOPNOTSUPP); } + if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 | + MLX4_IB_RX_HASH_DST_IPV4 | + MLX4_IB_RX_HASH_SRC_IPV6 | + MLX4_IB_RX_HASH_DST_IPV6 | + MLX4_IB_RX_HASH_SRC_PORT_TCP | + MLX4_IB_RX_HASH_DST_PORT_TCP | + MLX4_IB_RX_HASH_SRC_PORT_UDP | + MLX4_IB_RX_HASH_DST_PORT_UDP)) { + pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n", + ucmd->rx_hash_fields_mask); + return (-EOPNOTSUPP); + } + if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) && (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { rss_ctx->flags = MLX4_RSS_IPV4; @@ -691,11 +704,11 @@ static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, return (-EOPNOTSUPP); } - if (rss_ctx->flags & MLX4_RSS_IPV4) { + if (rss_ctx->flags & MLX4_RSS_IPV4) rss_ctx->flags |= MLX4_RSS_UDP_IPV4; - } else if (rss_ctx->flags & MLX4_RSS_IPV6) { + if (rss_ctx->flags & MLX4_RSS_IPV6) rss_ctx->flags |= MLX4_RSS_UDP_IPV6; - } else { + if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n"); return (-EOPNOTSUPP); } @@ -707,15 +720,14 @@ static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) && (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { - if (rss_ctx->flags & MLX4_RSS_IPV4) { + if (rss_ctx->flags & MLX4_RSS_IPV4) rss_ctx->flags |= MLX4_RSS_TCP_IPV4; - } else if (rss_ctx->flags & MLX4_RSS_IPV6) { + if (rss_ctx->flags & MLX4_RSS_IPV6) rss_ctx->flags |= MLX4_RSS_TCP_IPV6; - } else { + if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n"); return (-EOPNOTSUPP); } - } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) || (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n"); -- GitLab From d0e312fe3d34c1bc014a7f8ec6540d05e8077483 Mon Sep 17 00:00:00 2001 From: Leon Romanovsky Date: Tue, 5 Dec 2017 22:30:04 +0200 Subject: [PATCH 1058/2547] RDMA/netlink: Fix general protection fault The RDMA netlink core code checks validity of messages by ensuring that type and operand are in range. It works well for almost all clients except NLDEV, which has cb_table less than number of operands. Request to access such operand will trigger the following kernel panic. This patch updates all places where cb_table is declared for the consistency, but only NLDEV is actually need it. general protection fault: 0000 [#1] SMP DEBUG_PAGEALLOC KASAN Modules linked in: CPU: 0 PID: 522 Comm: syz-executor6 Not tainted 4.13.0+ #4 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.7.5-0-ge51488c-20140602_164612-nilsson.home.kraxel.org 04/01/2014 task: ffff8800657799c0 task.stack: ffff8800695d000 RIP: 0010:rdma_nl_rcv_msg+0x13a/0x4c0 RSP: 0018:ffff8800695d7838 EFLAGS: 00010207 RAX: dffffc0000000000 RBX: 1ffff1000d2baf0b RCX: 00000000704ff4d7 RDX: 0000000000000000 RSI: ffffffff81ddb03c RDI: 00000003827fa6bc RBP: ffff8800695d7900 R08: ffffffff82ec0578 R09: 0000000000000000 R10: ffff8800695d7900 R11: 0000000000000001 R12: 000000000000001c R13: ffff880069d31e00 R14: 00000000ffffffff R15: ffff880069d357c0 FS: 00007fee6acb8700(0000) GS:ffff88006ca00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00000000201a9000 CR3: 0000000059766000 CR4: 00000000000006b0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: ? rdma_nl_multicast+0x80/0x80 rdma_nl_rcv+0x36b/0x4d0 ? ibnl_put_attr+0xc0/0xc0 netlink_unicast+0x4bd/0x6d0 ? netlink_sendskb+0x50/0x50 ? drop_futex_key_refs.isra.4+0x68/0xb0 netlink_sendmsg+0x9ab/0xbd0 ? nlmsg_notify+0x140/0x140 ? wake_up_q+0xa1/0xf0 ? drop_futex_key_refs.isra.4+0x68/0xb0 sock_sendmsg+0x88/0xd0 sock_write_iter+0x228/0x3c0 ? sock_sendmsg+0xd0/0xd0 ? do_futex+0x3e5/0xb20 ? iov_iter_init+0xaf/0x1d0 __vfs_write+0x46e/0x640 ? sched_clock_cpu+0x1b/0x190 ? __vfs_read+0x620/0x620 ? __fget+0x23a/0x390 ? rw_verify_area+0xca/0x290 vfs_write+0x192/0x490 SyS_write+0xde/0x1c0 ? SyS_read+0x1c0/0x1c0 ? trace_hardirqs_on_thunk+0x1a/0x1c entry_SYSCALL_64_fastpath+0x18/0xad RIP: 0033:0x7fee6a74a219 RSP: 002b:00007fee6acb7d58 EFLAGS: 00000212 ORIG_RAX: 0000000000000001 RAX: ffffffffffffffda RBX: 0000000000638000 RCX: 00007fee6a74a219 RDX: 0000000000000078 RSI: 0000000020141000 RDI: 0000000000000006 RBP: 0000000000000046 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000212 R12: ffff8800695d7f98 R13: 0000000020141000 R14: 0000000000000006 R15: 00000000ffffffff Code: d6 48 b8 00 00 00 00 00 fc ff df 66 41 81 e4 ff 03 44 8d 72 ff 4a 8d 3c b5 c0 a6 7f 82 44 89 b5 4c ff ff ff 48 89 f9 48 c1 e9 03 <0f> b6 0c 01 48 89 f8 83 e0 07 83 c0 03 38 c8 7c 08 84 c9 0f 85 RIP: rdma_nl_rcv_msg+0x13a/0x4c0 RSP: ffff8800695d7838 ---[ end trace ba085d123959c8ec ]--- Kernel panic - not syncing: Fatal exception Cc: syzkaller Fixes: b4c598a67ea1 ("RDMA/netlink: Implement nldev device dumpit calback") Reviewed-by: Mark Bloch Signed-off-by: Leon Romanovsky Signed-off-by: Doug Ledford --- drivers/infiniband/core/cma.c | 2 +- drivers/infiniband/core/device.c | 2 +- drivers/infiniband/core/iwcm.c | 2 +- drivers/infiniband/core/nldev.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/infiniband/core/cma.c b/drivers/infiniband/core/cma.c index f6983357145d..6294a7001d33 100644 --- a/drivers/infiniband/core/cma.c +++ b/drivers/infiniband/core/cma.c @@ -4458,7 +4458,7 @@ static int cma_get_id_stats(struct sk_buff *skb, struct netlink_callback *cb) return skb->len; } -static const struct rdma_nl_cbs cma_cb_table[] = { +static const struct rdma_nl_cbs cma_cb_table[RDMA_NL_RDMA_CM_NUM_OPS] = { [RDMA_NL_RDMA_CM_ID_STATS] = { .dump = cma_get_id_stats}, }; diff --git a/drivers/infiniband/core/device.c b/drivers/infiniband/core/device.c index 5e1be4949d5f..30914f3baa5f 100644 --- a/drivers/infiniband/core/device.c +++ b/drivers/infiniband/core/device.c @@ -1146,7 +1146,7 @@ struct net_device *ib_get_net_dev_by_params(struct ib_device *dev, } EXPORT_SYMBOL(ib_get_net_dev_by_params); -static const struct rdma_nl_cbs ibnl_ls_cb_table[] = { +static const struct rdma_nl_cbs ibnl_ls_cb_table[RDMA_NL_LS_NUM_OPS] = { [RDMA_NL_LS_OP_RESOLVE] = { .doit = ib_nl_handle_resolve_resp, .flags = RDMA_NL_ADMIN_PERM, diff --git a/drivers/infiniband/core/iwcm.c b/drivers/infiniband/core/iwcm.c index e9e189ec7502..5d676cff41f4 100644 --- a/drivers/infiniband/core/iwcm.c +++ b/drivers/infiniband/core/iwcm.c @@ -80,7 +80,7 @@ const char *__attribute_const__ iwcm_reject_msg(int reason) } EXPORT_SYMBOL(iwcm_reject_msg); -static struct rdma_nl_cbs iwcm_nl_cb_table[] = { +static struct rdma_nl_cbs iwcm_nl_cb_table[RDMA_NL_IWPM_NUM_OPS] = { [RDMA_NL_IWPM_REG_PID] = {.dump = iwpm_register_pid_cb}, [RDMA_NL_IWPM_ADD_MAPPING] = {.dump = iwpm_add_mapping_cb}, [RDMA_NL_IWPM_QUERY_MAPPING] = {.dump = iwpm_add_and_query_mapping_cb}, diff --git a/drivers/infiniband/core/nldev.c b/drivers/infiniband/core/nldev.c index 2fae850a3eff..9a05245a1acf 100644 --- a/drivers/infiniband/core/nldev.c +++ b/drivers/infiniband/core/nldev.c @@ -303,7 +303,7 @@ out: cb->args[0] = idx; return skb->len; } -static const struct rdma_nl_cbs nldev_cb_table[] = { +static const struct rdma_nl_cbs nldev_cb_table[RDMA_NLDEV_NUM_OPS] = { [RDMA_NLDEV_CMD_GET] = { .doit = nldev_get_doit, .dump = nldev_get_dumpit, -- GitLab From 335ebf6fa35ca1c59b73f76fad19b249d3550e86 Mon Sep 17 00:00:00 2001 From: Steve Wise Date: Thu, 30 Nov 2017 09:41:56 -0800 Subject: [PATCH 1059/2547] iw_cxgb4: only clear the ARMED bit if a notification is needed In __flush_qp(), the CQ ARMED bit was being cleared regardless of whether any notification is actually needed. This resulted in the iser termination logic getting stuck in ib_drain_sq() because the CQ was not marked ARMED and thus the drain CQE notification wasn't triggered. This new bug was exposed when this commit was merged: commit cbb40fadd31c ("iw_cxgb4: only call the cq comp_handler when the cq is armed") Signed-off-by: Steve Wise Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/cxgb4/qp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c index 5ee7fe433136..355e288ec969 100644 --- a/drivers/infiniband/hw/cxgb4/qp.c +++ b/drivers/infiniband/hw/cxgb4/qp.c @@ -1285,21 +1285,21 @@ static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, spin_unlock_irqrestore(&rchp->lock, flag); if (schp == rchp) { - if (t4_clear_cq_armed(&rchp->cq) && - (rq_flushed || sq_flushed)) { + if ((rq_flushed || sq_flushed) && + t4_clear_cq_armed(&rchp->cq)) { spin_lock_irqsave(&rchp->comp_handler_lock, flag); (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); } } else { - if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) { + if (rq_flushed && t4_clear_cq_armed(&rchp->cq)) { spin_lock_irqsave(&rchp->comp_handler_lock, flag); (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); } - if (t4_clear_cq_armed(&schp->cq) && sq_flushed) { + if (sq_flushed && t4_clear_cq_armed(&schp->cq)) { spin_lock_irqsave(&schp->comp_handler_lock, flag); (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context); -- GitLab From 96307a0a75d8f1847debefd6a402339aac43e224 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 7 Dec 2017 14:26:09 +0100 Subject: [PATCH 1060/2547] netfilter: ipt_CLUSTERIP: fix clusterip_net_exit build regression The added check produces a build error when CONFIG_PROC_FS is disabled: net/ipv4/netfilter/ipt_CLUSTERIP.c: In function 'clusterip_net_exit': net/ipv4/netfilter/ipt_CLUSTERIP.c:822:28: error: 'cn' undeclared (first use in this function) This moves the variable declaration out of the #ifdef to make it available to the WARN_ON_ONCE(). Fixes: 613d0776d3fe ("netfilter: exit_net cleanup check added") Signed-off-by: Arnd Bergmann Reviewed-by: Vasily Averin Signed-off-by: Pablo Neira Ayuso --- net/ipv4/netfilter/ipt_CLUSTERIP.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/ipv4/netfilter/ipt_CLUSTERIP.c b/net/ipv4/netfilter/ipt_CLUSTERIP.c index e35b8d074f06..69060e3abe85 100644 --- a/net/ipv4/netfilter/ipt_CLUSTERIP.c +++ b/net/ipv4/netfilter/ipt_CLUSTERIP.c @@ -813,8 +813,8 @@ static int clusterip_net_init(struct net *net) static void clusterip_net_exit(struct net *net) { -#ifdef CONFIG_PROC_FS struct clusterip_net *cn = net_generic(net, clusterip_net_id); +#ifdef CONFIG_PROC_FS proc_remove(cn->procdir); cn->procdir = NULL; #endif -- GitLab From e2189dd078a2b83d370ae9cde459e5c6711936de Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 7 Dec 2017 21:14:07 +0000 Subject: [PATCH 1061/2547] drm/i915: Refactor common list iteration over GGTT vma In quite a few places, we have a list iteration over the vma on an object that only want to inspect GGTT vma. By construction, these are placed at the start of the list, so we have copied that knowledge into many callsites. Pull that knowledge back to i915_vma.h and provide a for_each_ggtt_vma() to tidy up the code. v2: Add a backreference from vma_create() to remind ourselves why we put ggtt vma at the head of the obj->vma_list (and ppgtt vma at the tail). v3: Fixup s/vma/V/ Suggested-by: Joonas Lahtinen Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Reviewed-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171207211407.31549-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_debugfs.c | 4 ++-- drivers/gpu/drm/i915/i915_gem.c | 18 ++++-------------- drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +---- drivers/gpu/drm/i915/i915_gem_tiling.c | 10 ++-------- drivers/gpu/drm/i915/i915_vma.c | 6 ++++++ drivers/gpu/drm/i915/i915_vma.h | 16 +++++++++++++++- 6 files changed, 30 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 28294470ae31..7b41a1799a03 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -111,8 +111,8 @@ static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) u64 size = 0; struct i915_vma *vma; - list_for_each_entry(vma, &obj->vma_list, obj_link) { - if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) + for_each_ggtt_vma(vma, obj) { + if (drm_mm_node_allocated(&vma->node)) size += vma->node.size; } diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 67dc11effc8e..c7b5db78fbb4 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -714,10 +714,7 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) intel_fb_obj_flush(obj, fb_write_origin(obj, I915_GEM_DOMAIN_GTT)); - list_for_each_entry(vma, &obj->vma_list, obj_link) { - if (!i915_vma_is_ggtt(vma)) - break; - + for_each_ggtt_vma(vma, obj) { if (vma->iomap) continue; @@ -1569,10 +1566,7 @@ static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); - list_for_each_entry(vma, &obj->vma_list, obj_link) { - if (!i915_vma_is_ggtt(vma)) - break; - + for_each_ggtt_vma(vma, obj) { if (i915_vma_is_active(vma)) continue; @@ -2051,12 +2045,8 @@ static void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj) drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->anon_inode->i_mapping); - list_for_each_entry(vma, &obj->vma_list, obj_link) { - if (!i915_vma_is_ggtt(vma)) - break; - + for_each_ggtt_vma(vma, obj) i915_vma_unset_userfault(vma); - } } /** @@ -3822,7 +3812,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, * dropped the fence as all snoopable access is * supposed to be linear. */ - list_for_each_entry(vma, &obj->vma_list, obj_link) { + for_each_ggtt_vma(vma, obj) { ret = i915_vma_put_fence(vma); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 86fbd67388f3..c4bb02ecd217 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3620,10 +3620,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) bool ggtt_bound = false; struct i915_vma *vma; - list_for_each_entry(vma, &obj->vma_list, obj_link) { - if (vma->vm != &ggtt->base) - continue; - + for_each_ggtt_vma(vma, obj) { if (!i915_vma_unbind(vma)) continue; diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index b85d7ebd9bee..d9dc9df523b5 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -205,10 +205,7 @@ i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj, if (tiling_mode == I915_TILING_NONE) return 0; - list_for_each_entry(vma, &obj->vma_list, obj_link) { - if (!i915_vma_is_ggtt(vma)) - break; - + for_each_ggtt_vma(vma, obj) { if (i915_vma_fence_prepare(vma, tiling_mode, stride)) continue; @@ -285,10 +282,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, } mutex_unlock(&obj->mm.lock); - list_for_each_entry(vma, &obj->vma_list, obj_link) { - if (!i915_vma_is_ggtt(vma)) - break; - + for_each_ggtt_vma(vma, obj) { vma->fence_size = i915_gem_fence_size(i915, vma->size, tiling, stride); vma->fence_alignment = diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 0ebd75693505..92c11e70fea4 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -142,6 +142,12 @@ vma_create(struct drm_i915_gem_object *obj, i915_gem_object_get_stride(obj)); GEM_BUG_ON(!is_power_of_2(vma->fence_alignment)); + /* + * We put the GGTT vma at the start of the vma-list, followed + * by the ppGGTT vma. This allows us to break early when + * iterating over only the GGTT vma for an object, see + * for_each_ggtt_vma() + */ vma->flags |= I915_VMA_GGTT; list_add(&vma->obj_link, &obj->vma_list); } else { diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index f636243eb8f7..fd5b84904f7c 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -408,5 +408,19 @@ i915_vma_unpin_fence(struct i915_vma *vma) __i915_vma_unpin_fence(vma); } -#endif +#define for_each_until(cond) if (cond) break; else + +/** + * for_each_ggtt_vma - Iterate over the GGTT VMA belonging to an object. + * @V: the #i915_vma iterator + * @OBJ: the #drm_i915_gem_object + * + * GGTT VMA are placed at the being of the object's vma_list, see + * vma_create(), so we can stop our walk as soon as we see a ppgtt VMA, + * or the list is empty ofc. + */ +#define for_each_ggtt_vma(V, OBJ) \ + list_for_each_entry(V, &(OBJ)->vma_list, obj_link) \ + for_each_until(!i915_vma_is_ggtt(V)) +#endif -- GitLab From 2fc7a06ad518610d197bafe7d2d3e8a8f9bb181e Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 7 Dec 2017 22:24:34 +0000 Subject: [PATCH 1062/2547] drm/i915/execlists: Cache ELSP register offset Currently on every submission, we recalculate the ELSP register offset for the engine, after chasing the pointers to find the iomem base. Since this is fixed for the lifetime of the driver, record the offset in the execlists struct. In practice the difference is negligible, it just happens to remove 27 bytes of eyesore pointer dancing from next to the hottest instruction (which is itself due to stalling for a cache miss) in perf profiles of the execlists_submission_tasklet(). v2: Trim off one more elsp local. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Mika Kuoppala Reviewed-by: Michel Thierry Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20171207222434.17686-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_lrc.c | 13 ++++++------- drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++++ 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 2a8160f603ab..2e38fbfdf08f 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -431,8 +431,6 @@ static inline void elsp_write(u64 desc, u32 __iomem *elsp) static void execlists_submit_ports(struct intel_engine_cs *engine) { struct execlist_port *port = engine->execlists.port; - u32 __iomem *elsp = - engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine)); unsigned int n; for (n = execlists_num_ports(&engine->execlists); n--; ) { @@ -458,7 +456,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine) desc = 0; } - elsp_write(desc, elsp); + elsp_write(desc, engine->execlists.elsp); } execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK); } @@ -496,8 +494,6 @@ static void inject_preempt_context(struct intel_engine_cs *engine) { struct intel_context *ce = &engine->i915->preempt_context->engine[engine->id]; - u32 __iomem *elsp = - engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine)); unsigned int n; GEM_BUG_ON(engine->i915->preempt_context->hw_id != PREEMPT_ID); @@ -510,9 +506,9 @@ static void inject_preempt_context(struct intel_engine_cs *engine) GEM_TRACE("\n"); for (n = execlists_num_ports(&engine->execlists); --n; ) - elsp_write(0, elsp); + elsp_write(0, engine->execlists.elsp); - elsp_write(ce->lrc_desc, elsp); + elsp_write(ce->lrc_desc, engine->execlists.elsp); execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK); } @@ -1509,6 +1505,9 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine) execlists->csb_head = -1; execlists->active = 0; + execlists->elsp = + dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine)); + /* After a GPU reset, we may have requests to replay */ if (execlists->first) tasklet_schedule(&execlists->tasklet); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 3d097bbeb2d9..21d6ed67a813 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -198,6 +198,11 @@ struct intel_engine_execlists { */ bool no_priolist; + /** + * @elsp: the ExecList Submission Port register + */ + u32 __iomem *elsp; + /** * @port: execlist port states * -- GitLab From 7e70aa789d4a0c89dbfbd2c8a974a4df717475ec Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Tue, 5 Dec 2017 15:52:56 +0800 Subject: [PATCH 1063/2547] scsi: core: run queue if SCSI device queue isn't ready and queue is idle MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Before commit 0df21c86bdbf ("scsi: implement .get_budget and .put_budget for blk-mq"), we run queue after 3ms if queue is idle and SCSI device queue isn't ready, which is done in handling BLK_STS_RESOURCE. After commit 0df21c86bdbf is introduced, queue won't be run any more under this situation. IO hang is observed when timeout happened, and this patch fixes the IO hang issue by running queue after delay in scsi_dev_queue_ready, just like non-mq. This issue can be triggered by the following script[1]. There is another issue which can be covered by running idle queue: when .get_budget() is called on request coming from hctx->dispatch_list, if one request just completes during .get_budget(), we can't depend on SCSI's restart to make progress any more. This patch fixes the race too. With this patch, we basically recover to previous behaviour (before commit 0df21c86bdbf) of handling idle queue when running out of resource. [1] script for test/verify SCSI timeout rmmod scsi_debug modprobe scsi_debug max_queue=1 DEVICE=`ls -d /sys/bus/pseudo/drivers/scsi_debug/adapter*/host*/target*/*/block/* | head -1 | xargs basename` DISK_DIR=`ls -d /sys/block/$DEVICE/device/scsi_disk/*` echo "using scsi device $DEVICE" echo "-1" >/sys/bus/pseudo/drivers/scsi_debug/every_nth echo "temporary write through" >$DISK_DIR/cache_type echo "128" >/sys/bus/pseudo/drivers/scsi_debug/opts echo none > /sys/block/$DEVICE/queue/scheduler dd if=/dev/$DEVICE of=/dev/null bs=1M iflag=direct count=1 & sleep 5 echo "0" >/sys/bus/pseudo/drivers/scsi_debug/opts wait echo "SUCCESS" Fixes: 0df21c86bdbf ("scsi: implement .get_budget and .put_budget for blk-mq") Signed-off-by: Ming Lei Tested-by: Holger Hoffstätte Reviewed-by: Bart Van Assche Signed-off-by: Martin K. Petersen --- drivers/scsi/scsi_lib.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c index 00742c50cd44..d9ca1dfab154 100644 --- a/drivers/scsi/scsi_lib.c +++ b/drivers/scsi/scsi_lib.c @@ -1967,6 +1967,8 @@ static bool scsi_mq_get_budget(struct blk_mq_hw_ctx *hctx) out_put_device: put_device(&sdev->sdev_gendev); out: + if (atomic_read(&sdev->device_busy) == 0 && !scsi_device_blocked(sdev)) + blk_mq_delay_run_hw_queue(hctx, SCSI_QUEUE_DELAY); return false; } -- GitLab From 48d83282db077f93b2cf40de120f4d6f29eb293b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 6 Dec 2017 15:14:18 +0100 Subject: [PATCH 1064/2547] scsi: bfa: fix type conversion warning A regression fix introduced a harmless type mismatch warning: drivers/scsi/bfa/bfad_bsg.c: In function 'bfad_im_bsg_vendor_request': drivers/scsi/bfa/bfad_bsg.c:3137:35: error: initialization of 'struct bfad_im_port_s *' from 'long unsigned int' makes pointer from integer without a cast [-Werror=int-conversion] struct bfad_im_port_s *im_port = shost->hostdata[0]; ^~~~~ drivers/scsi/bfa/bfad_bsg.c: In function 'bfad_im_bsg_els_ct_request': drivers/scsi/bfa/bfad_bsg.c:3353:35: error: initialization of 'struct bfad_im_port_s *' from 'long unsigned int' makes pointer from integer without a cast [-Werror=int-conversion] struct bfad_im_port_s *im_port = shost->hostdata[0]; This changes the code back to shost_priv() once more, but encapsulates it in an inline function to document the rather unusual way of using the private data only as a pointer to the previously allocated structure. I did not try to get rid of the extra indirection level entirely, which would have been rather invasive and required reworking the entire initialization sequence. Fixes: 45349821ab3a ("scsi: bfa: fix access to bfad_im_port_s") Signed-off-by: Arnd Bergmann Reviewed-by: Johannes Thumshirn Reviewed-by: Hannes Reinecke Signed-off-by: Martin K. Petersen --- drivers/scsi/bfa/bfad_bsg.c | 4 ++-- drivers/scsi/bfa/bfad_im.c | 6 ++++-- drivers/scsi/bfa/bfad_im.h | 10 ++++++++++ 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/scsi/bfa/bfad_bsg.c b/drivers/scsi/bfa/bfad_bsg.c index 09ef68c8225f..b2fa195adc7a 100644 --- a/drivers/scsi/bfa/bfad_bsg.c +++ b/drivers/scsi/bfa/bfad_bsg.c @@ -3136,7 +3136,7 @@ bfad_im_bsg_vendor_request(struct bsg_job *job) struct fc_bsg_reply *bsg_reply = job->reply; uint32_t vendor_cmd = bsg_request->rqst_data.h_vendor.vendor_cmd[0]; struct Scsi_Host *shost = fc_bsg_to_shost(job); - struct bfad_im_port_s *im_port = shost->hostdata[0]; + struct bfad_im_port_s *im_port = bfad_get_im_port(shost); struct bfad_s *bfad = im_port->bfad; void *payload_kbuf; int rc = -EINVAL; @@ -3352,7 +3352,7 @@ bfad_im_bsg_els_ct_request(struct bsg_job *job) { struct bfa_bsg_data *bsg_data; struct Scsi_Host *shost = fc_bsg_to_shost(job); - struct bfad_im_port_s *im_port = shost->hostdata[0]; + struct bfad_im_port_s *im_port = bfad_get_im_port(shost); struct bfad_s *bfad = im_port->bfad; bfa_bsg_fcpt_t *bsg_fcpt; struct bfad_fcxp *drv_fcxp; diff --git a/drivers/scsi/bfa/bfad_im.c b/drivers/scsi/bfa/bfad_im.c index 24e657a4ec80..c05d6e91e4bd 100644 --- a/drivers/scsi/bfa/bfad_im.c +++ b/drivers/scsi/bfa/bfad_im.c @@ -546,6 +546,7 @@ int bfad_im_scsi_host_alloc(struct bfad_s *bfad, struct bfad_im_port_s *im_port, struct device *dev) { + struct bfad_im_port_pointer *im_portp; int error = 1; mutex_lock(&bfad_mutex); @@ -564,7 +565,8 @@ bfad_im_scsi_host_alloc(struct bfad_s *bfad, struct bfad_im_port_s *im_port, goto out_free_idr; } - im_port->shost->hostdata[0] = (unsigned long)im_port; + im_portp = shost_priv(im_port->shost); + im_portp->p = im_port; im_port->shost->unique_id = im_port->idr_id; im_port->shost->this_id = -1; im_port->shost->max_id = MAX_FCP_TARGET; @@ -748,7 +750,7 @@ bfad_scsi_host_alloc(struct bfad_im_port_s *im_port, struct bfad_s *bfad) sht->sg_tablesize = bfad->cfg_data.io_max_sge; - return scsi_host_alloc(sht, sizeof(unsigned long)); + return scsi_host_alloc(sht, sizeof(struct bfad_im_port_pointer)); } void diff --git a/drivers/scsi/bfa/bfad_im.h b/drivers/scsi/bfa/bfad_im.h index c81ec2a77ef5..06ce4ba2b7bc 100644 --- a/drivers/scsi/bfa/bfad_im.h +++ b/drivers/scsi/bfa/bfad_im.h @@ -69,6 +69,16 @@ struct bfad_im_port_s { struct fc_vport *fc_vport; }; +struct bfad_im_port_pointer { + struct bfad_im_port_s *p; +}; + +static inline struct bfad_im_port_s *bfad_get_im_port(struct Scsi_Host *host) +{ + struct bfad_im_port_pointer *im_portp = shost_priv(host); + return im_portp->p; +} + enum bfad_itnim_state { ITNIM_STATE_NONE, ITNIM_STATE_ONLINE, -- GitLab From 16c6db3688734b27487a42d0c2a1062d0b2bad03 Mon Sep 17 00:00:00 2001 From: Ray Strode Date: Mon, 27 Nov 2017 16:50:09 -0500 Subject: [PATCH 1065/2547] drm/qxl: unref cursor bo when finished with it qxl_cursor_atomic_update allocs a bo for the cursor that it never frees up at the end of the function. This commit fixes that. Signed-off-by: Ray Strode Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_display.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index 4756b3c9bf2c..7335d99244d5 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -575,7 +575,7 @@ static void qxl_cursor_atomic_update(struct drm_plane *plane, struct qxl_cursor_cmd *cmd; struct qxl_cursor *cursor; struct drm_gem_object *obj; - struct qxl_bo *cursor_bo, *user_bo = NULL; + struct qxl_bo *cursor_bo = NULL, *user_bo = NULL; int ret; void *user_ptr; int size = 64*64*4; @@ -645,6 +645,8 @@ static void qxl_cursor_atomic_update(struct drm_plane *plane, qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false); qxl_release_fence_buffer_objects(release); + qxl_bo_unref(&cursor_bo); + return; out_backoff: -- GitLab From 9428088c90b6f7d5edd2a1b0d742c75339b36f6e Mon Sep 17 00:00:00 2001 From: Ray Strode Date: Mon, 27 Nov 2017 16:50:10 -0500 Subject: [PATCH 1066/2547] drm/qxl: reapply cursor after resetting primary QXL associates mouse state with its primary plane. Destroying a primary plane and putting a new one in place has the side effect of destroying the cursor as well. This commit changes the driver to reapply the cursor any time a new primary is created. It achieves this by keeping a reference to the cursor bo on the qxl_crtc struct. This fix is very similar to commit 4532b241a4b7 ("drm/qxl: reapply cursor after SetCrtc calls") which got implicitly reverted as part of implementing the atomic modeset feature. Cc: Gerd Hoffmann Cc: Dave Airlie Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1512097 Fixes: 1277eed5fecb ("drm: qxl: Atomic phase 1: convert cursor to universal plane") Cc: stable@vger.kernel.org Signed-off-by: Ray Strode Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_display.c | 59 +++++++++++++++++++++++++++++++ drivers/gpu/drm/qxl/qxl_drv.h | 2 ++ 2 files changed, 61 insertions(+) diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index 7335d99244d5..9a9214ae0fb5 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -289,6 +289,7 @@ static void qxl_crtc_destroy(struct drm_crtc *crtc) { struct qxl_crtc *qxl_crtc = to_qxl_crtc(crtc); + qxl_bo_unref(&qxl_crtc->cursor_bo); drm_crtc_cleanup(crtc); kfree(qxl_crtc); } @@ -495,6 +496,53 @@ static int qxl_primary_atomic_check(struct drm_plane *plane, return 0; } +static int qxl_primary_apply_cursor(struct drm_plane *plane) +{ + struct drm_device *dev = plane->dev; + struct qxl_device *qdev = dev->dev_private; + struct drm_framebuffer *fb = plane->state->fb; + struct qxl_crtc *qcrtc = to_qxl_crtc(plane->state->crtc); + struct qxl_cursor_cmd *cmd; + struct qxl_release *release; + int ret = 0; + + if (!qcrtc->cursor_bo) + return 0; + + ret = qxl_alloc_release_reserved(qdev, sizeof(*cmd), + QXL_RELEASE_CURSOR_CMD, + &release, NULL); + if (ret) + return ret; + + ret = qxl_release_list_add(release, qcrtc->cursor_bo); + if (ret) + goto out_free_release; + + ret = qxl_release_reserve_list(release, false); + if (ret) + goto out_free_release; + + cmd = (struct qxl_cursor_cmd *)qxl_release_map(qdev, release); + cmd->type = QXL_CURSOR_SET; + cmd->u.set.position.x = plane->state->crtc_x + fb->hot_x; + cmd->u.set.position.y = plane->state->crtc_y + fb->hot_y; + + cmd->u.set.shape = qxl_bo_physical_address(qdev, qcrtc->cursor_bo, 0); + + cmd->u.set.visible = 1; + qxl_release_unmap(qdev, release, &cmd->release_info); + + qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false); + qxl_release_fence_buffer_objects(release); + + return ret; + +out_free_release: + qxl_release_free(qdev, release); + return ret; +} + static void qxl_primary_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { @@ -510,6 +558,7 @@ static void qxl_primary_atomic_update(struct drm_plane *plane, .x2 = qfb->base.width, .y2 = qfb->base.height }; + int ret; bool same_shadow = false; if (old_state->fb) { @@ -531,6 +580,11 @@ static void qxl_primary_atomic_update(struct drm_plane *plane, if (!same_shadow) qxl_io_destroy_primary(qdev); bo_old->is_primary = false; + + ret = qxl_primary_apply_cursor(plane); + if (ret) + DRM_ERROR( + "could not set cursor after creating primary"); } if (!bo->is_primary) { @@ -571,6 +625,7 @@ static void qxl_cursor_atomic_update(struct drm_plane *plane, struct drm_device *dev = plane->dev; struct qxl_device *qdev = dev->dev_private; struct drm_framebuffer *fb = plane->state->fb; + struct qxl_crtc *qcrtc = to_qxl_crtc(plane->state->crtc); struct qxl_release *release; struct qxl_cursor_cmd *cmd; struct qxl_cursor *cursor; @@ -628,6 +683,10 @@ static void qxl_cursor_atomic_update(struct drm_plane *plane, cmd->u.set.shape = qxl_bo_physical_address(qdev, cursor_bo, 0); cmd->type = QXL_CURSOR_SET; + + qxl_bo_unref(&qcrtc->cursor_bo); + qcrtc->cursor_bo = cursor_bo; + cursor_bo = NULL; } else { ret = qxl_release_reserve_list(release, true); diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h index 08752c0ffb35..00a1a66b052a 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.h +++ b/drivers/gpu/drm/qxl/qxl_drv.h @@ -111,6 +111,8 @@ struct qxl_bo_list { struct qxl_crtc { struct drm_crtc base; int index; + + struct qxl_bo *cursor_bo; }; struct qxl_output { -- GitLab From 75bf50f4aaa1c78d769d854ab3d975884909e4fb Mon Sep 17 00:00:00 2001 From: Antony Antony Date: Thu, 7 Dec 2017 21:54:27 +0100 Subject: [PATCH 1067/2547] xfrm: fix xfrm_do_migrate() with AEAD e.g(AES-GCM) copy geniv when cloning the xfrm state. x->geniv was not copied to the new state and migration would fail. xfrm_do_migrate .. xfrm_state_clone() .. .. esp_init_aead() crypto_alloc_aead() crypto_alloc_tfm() crypto_find_alg() return EAGAIN and failed Signed-off-by: Antony Antony Signed-off-by: Steffen Klassert --- net/xfrm/xfrm_state.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/xfrm/xfrm_state.c b/net/xfrm/xfrm_state.c index 1f5cee2269af..88d0a563e141 100644 --- a/net/xfrm/xfrm_state.c +++ b/net/xfrm/xfrm_state.c @@ -1344,6 +1344,7 @@ static struct xfrm_state *xfrm_state_clone(struct xfrm_state *orig, if (orig->aead) { x->aead = xfrm_algo_aead_clone(orig->aead); + x->geniv = orig->geniv; if (!x->aead) goto error; } -- GitLab From 732706afe1cc46ef48493b3d2b69c98f36314ae4 Mon Sep 17 00:00:00 2001 From: Steffen Klassert Date: Fri, 8 Dec 2017 08:07:25 +0100 Subject: [PATCH 1068/2547] xfrm: Fix stack-out-of-bounds with misconfigured transport mode policies. On policies with a transport mode template, we pass the addresses from the flowi to xfrm_state_find(), assuming that the IP addresses (and address family) don't change during transformation. Unfortunately our policy template validation is not strict enough. It is possible to configure policies with transport mode template where the address family of the template does not match the selectors address family. This lead to stack-out-of-bound reads because we compare arddesses of the wrong family. Fix this by refusing such a configuration, address family can not change on transport mode. We use the assumption that, on transport mode, the first templates address family must match the address family of the policy selector. Subsequent transport mode templates must mach the address family of the previous template. Signed-off-by: Steffen Klassert --- net/xfrm/xfrm_user.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c index ff58c37469d6..bdb48e5dba04 100644 --- a/net/xfrm/xfrm_user.c +++ b/net/xfrm/xfrm_user.c @@ -1419,11 +1419,14 @@ static void copy_templates(struct xfrm_policy *xp, struct xfrm_user_tmpl *ut, static int validate_tmpl(int nr, struct xfrm_user_tmpl *ut, u16 family) { + u16 prev_family; int i; if (nr > XFRM_MAX_DEPTH) return -EINVAL; + prev_family = family; + for (i = 0; i < nr; i++) { /* We never validated the ut->family value, so many * applications simply leave it at zero. The check was @@ -1435,6 +1438,12 @@ static int validate_tmpl(int nr, struct xfrm_user_tmpl *ut, u16 family) if (!ut[i].family) ut[i].family = family; + if ((ut[i].mode == XFRM_MODE_TRANSPORT) && + (ut[i].family != prev_family)) + return -EINVAL; + + prev_family = ut[i].family; + switch (ut[i].family) { case AF_INET: break; -- GitLab From 4447f423ff0822f3eacc31bbaf445226fa312b84 Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Fri, 8 Dec 2017 14:56:20 +0800 Subject: [PATCH 1069/2547] drm/i915/gvt: Refine the ring mmio list definition To improve the readability, let's remove the hard code for each mmio definition. The raw offset remained as a comment, which give us an offset based view. This refine is to make it convenient for new platform enabling. Signed-off-by: Changbin Du Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/render.c | 194 ++++++++++++++++-------------- 1 file changed, 104 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index 0672178548ef..43abca5dbe75 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -45,100 +45,114 @@ struct render_mmio { u32 value; }; +/** + * Defined in Intel Open Source PRM. + * Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms + */ +#define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i)*4) +#define TRNULLDETCT _MMIO(0x4de8) +#define TRINVTILEDETCT _MMIO(0x4dec) +#define TRVADR _MMIO(0x4df0) +#define TRTTE _MMIO(0x4df4) +#define RING_EXCC(base) _MMIO((base) + 0x28) +#define RING_GFX_MODE(base) _MMIO((base) + 0x29c) +#define VF_GUARDBAND _MMIO(0x83a4) + +/* Raw offset is appened to each line for convenience. */ static struct render_mmio gen8_render_mmio_list[] __cacheline_aligned = { - {RCS, _MMIO(0x229c), 0xffff, false}, - {RCS, _MMIO(0x2248), 0x0, false}, - {RCS, _MMIO(0x2098), 0x0, false}, - {RCS, _MMIO(0x20c0), 0xffff, true}, - {RCS, _MMIO(0x24d0), 0, false}, - {RCS, _MMIO(0x24d4), 0, false}, - {RCS, _MMIO(0x24d8), 0, false}, - {RCS, _MMIO(0x24dc), 0, false}, - {RCS, _MMIO(0x24e0), 0, false}, - {RCS, _MMIO(0x24e4), 0, false}, - {RCS, _MMIO(0x24e8), 0, false}, - {RCS, _MMIO(0x24ec), 0, false}, - {RCS, _MMIO(0x24f0), 0, false}, - {RCS, _MMIO(0x24f4), 0, false}, - {RCS, _MMIO(0x24f8), 0, false}, - {RCS, _MMIO(0x24fc), 0, false}, - {RCS, _MMIO(0x7004), 0xffff, true}, - {RCS, _MMIO(0x7008), 0xffff, true}, - {RCS, _MMIO(0x7000), 0xffff, true}, - {RCS, _MMIO(0x7010), 0xffff, true}, - {RCS, _MMIO(0x7300), 0xffff, true}, - {RCS, _MMIO(0x83a4), 0xffff, true}, - - {BCS, _MMIO(0x2229c), 0xffff, false}, - {BCS, _MMIO(0x2209c), 0xffff, false}, - {BCS, _MMIO(0x220c0), 0xffff, false}, - {BCS, _MMIO(0x22098), 0x0, false}, - {BCS, _MMIO(0x22028), 0x0, false}, + {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ + {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ + {RCS, HWSTAM, 0x0, false}, /* 0x2098 */ + {RCS, INSTPM, 0xffff, true}, /* 0x20c0 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ + {RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ + {RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ + {RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ + {RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ + {RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ + {RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ + + {BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ + {BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ + {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ + {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ + {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */ }; static struct render_mmio gen9_render_mmio_list[] __cacheline_aligned = { - {RCS, _MMIO(0x229c), 0xffff, false}, - {RCS, _MMIO(0x2248), 0x0, false}, - {RCS, _MMIO(0x2098), 0x0, false}, - {RCS, _MMIO(0x20c0), 0xffff, true}, - {RCS, _MMIO(0x24d0), 0, false}, - {RCS, _MMIO(0x24d4), 0, false}, - {RCS, _MMIO(0x24d8), 0, false}, - {RCS, _MMIO(0x24dc), 0, false}, - {RCS, _MMIO(0x24e0), 0, false}, - {RCS, _MMIO(0x24e4), 0, false}, - {RCS, _MMIO(0x24e8), 0, false}, - {RCS, _MMIO(0x24ec), 0, false}, - {RCS, _MMIO(0x24f0), 0, false}, - {RCS, _MMIO(0x24f4), 0, false}, - {RCS, _MMIO(0x24f8), 0, false}, - {RCS, _MMIO(0x24fc), 0, false}, - {RCS, _MMIO(0x7004), 0xffff, true}, - {RCS, _MMIO(0x7008), 0xffff, true}, - {RCS, _MMIO(0x7000), 0xffff, true}, - {RCS, _MMIO(0x7010), 0xffff, true}, - {RCS, _MMIO(0x7300), 0xffff, true}, - {RCS, _MMIO(0x83a4), 0xffff, true}, - - {RCS, _MMIO(0x40e0), 0, false}, - {RCS, _MMIO(0x40e4), 0, false}, - {RCS, _MMIO(0x2580), 0xffff, true}, - {RCS, _MMIO(0x7014), 0xffff, true}, - {RCS, _MMIO(0x20ec), 0xffff, false}, - {RCS, _MMIO(0xb118), 0, false}, - {RCS, _MMIO(0xe100), 0xffff, true}, - {RCS, _MMIO(0xe180), 0xffff, true}, - {RCS, _MMIO(0xe184), 0xffff, true}, - {RCS, _MMIO(0xe188), 0xffff, true}, - {RCS, _MMIO(0xe194), 0xffff, true}, - {RCS, _MMIO(0x4de0), 0, false}, - {RCS, _MMIO(0x4de4), 0, false}, - {RCS, _MMIO(0x4de8), 0, false}, - {RCS, _MMIO(0x4dec), 0, false}, - {RCS, _MMIO(0x4df0), 0, false}, - {RCS, _MMIO(0x4df4), 0, false}, - - {BCS, _MMIO(0x2229c), 0xffff, false}, - {BCS, _MMIO(0x2209c), 0xffff, false}, - {BCS, _MMIO(0x220c0), 0xffff, false}, - {BCS, _MMIO(0x22098), 0x0, false}, - {BCS, _MMIO(0x22028), 0x0, false}, - - {VCS2, _MMIO(0x1c028), 0xffff, false}, - - {VECS, _MMIO(0x1a028), 0xffff, false}, - - {RCS, _MMIO(0x7304), 0xffff, true}, - {RCS, _MMIO(0x2248), 0x0, false}, - {RCS, _MMIO(0x940c), 0x0, false}, - {RCS, _MMIO(0x4ab8), 0x0, false}, - - {RCS, _MMIO(0x4ab0), 0x0, false}, - {RCS, _MMIO(0x20d4), 0x0, false}, - - {RCS, _MMIO(0xb004), 0x0, false}, - {RCS, _MMIO(0x20a0), 0x0, false}, - {RCS, _MMIO(0x20e4), 0xffff, false}, + {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ + {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ + {RCS, HWSTAM, 0x0, false}, /* 0x2098 */ + {RCS, INSTPM, 0xffff, true}, /* 0x20c0 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ + {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ + {RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ + {RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ + {RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ + {RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ + {RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ + {RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ + + {RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */ + {RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */ + {RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */ + {RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */ + {RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */ + {RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */ + {RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */ + {RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */ + {RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */ + {RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */ + {RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */ + {RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */ + {RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */ + {RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */ + {RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */ + {RCS, TRVADR, 0, false}, /* 0x4df0 */ + {RCS, TRTTE, 0, false}, /* 0x4df4 */ + + {BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ + {BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ + {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ + {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ + {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */ + + {VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */ + + {VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */ + + {RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */ + {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ + {RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */ + {RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */ + + {RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */ + {RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */ + + {RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */ + {RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */ + {RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */ }; static u32 gen9_render_mocs[I915_NUM_ENGINES][64]; -- GitLab From 83164886e4559f87015a33780852a64cdd6e4e50 Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Fri, 8 Dec 2017 14:56:21 +0800 Subject: [PATCH 1070/2547] drm/i915/gvt: Select appropriate mmio list at initialization time Select appropriate mmio list at initialization time, so we don't need to do duplicated work at where requires the mmio list. V2: - Add a termination mark of mmio list. Signed-off-by: Changbin Du Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/gvt.c | 2 ++ drivers/gpu/drm/i915/gvt/gvt.h | 2 ++ drivers/gpu/drm/i915/gvt/render.c | 60 ++++++++++++++----------------- drivers/gpu/drm/i915/gvt/render.h | 9 +++++ 4 files changed, 40 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c index 9a5dce3aa10a..643bb961d40d 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.c +++ b/drivers/gpu/drm/i915/gvt/gvt.c @@ -386,6 +386,8 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv) if (ret) goto out_clean_idr; + intel_gvt_init_engine_mmio_context(gvt); + ret = intel_gvt_load_firmware(gvt); if (ret) goto out_clean_mmio_info; diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 77df9bad5dea..39c2f3a4588e 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -310,6 +310,8 @@ struct intel_gvt { wait_queue_head_t service_thread_wq; unsigned long service_request; + struct engine_mmio *engine_mmio_list; + struct dentry *debugfs_root; }; diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index 43abca5dbe75..3e675f81815f 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -37,14 +37,6 @@ #include "gvt.h" #include "trace.h" -struct render_mmio { - int ring_id; - i915_reg_t reg; - u32 mask; - bool in_context; - u32 value; -}; - /** * Defined in Intel Open Source PRM. * Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms @@ -59,7 +51,7 @@ struct render_mmio { #define VF_GUARDBAND _MMIO(0x83a4) /* Raw offset is appened to each line for convenience. */ -static struct render_mmio gen8_render_mmio_list[] __cacheline_aligned = { +static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = { {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ {RCS, HWSTAM, 0x0, false}, /* 0x2098 */ @@ -88,9 +80,10 @@ static struct render_mmio gen8_render_mmio_list[] __cacheline_aligned = { {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */ + { /* Terminated */ } }; -static struct render_mmio gen9_render_mmio_list[] __cacheline_aligned = { +static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ {RCS, HWSTAM, 0x0, false}, /* 0x2098 */ @@ -153,6 +146,7 @@ static struct render_mmio gen9_render_mmio_list[] __cacheline_aligned = { {RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */ {RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */ {RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */ + { /* Terminated */ } }; static u32 gen9_render_mocs[I915_NUM_ENGINES][64]; @@ -282,21 +276,14 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) u32 inhibit_mask = _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); i915_reg_t last_reg = _MMIO(0); - struct render_mmio *mmio; + struct engine_mmio *mmio; u32 v; - int i, array_size; - if (IS_SKYLAKE(vgpu->gvt->dev_priv) - || IS_KABYLAKE(vgpu->gvt->dev_priv)) { - mmio = gen9_render_mmio_list; - array_size = ARRAY_SIZE(gen9_render_mmio_list); + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) load_mocs(vgpu, ring_id); - } else { - mmio = gen8_render_mmio_list; - array_size = ARRAY_SIZE(gen8_render_mmio_list); - } - for (i = 0; i < array_size; i++, mmio++) { + mmio = vgpu->gvt->engine_mmio_list; + while (i915_mmio_reg_offset((mmio++)->reg)) { if (mmio->ring_id != ring_id) continue; @@ -326,7 +313,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) } /* Make sure the swiched MMIOs has taken effect. */ - if (likely(INTEL_GVT_MMIO_OFFSET(last_reg))) + if (likely(i915_mmio_reg_offset(last_reg))) I915_READ_FW(last_reg); handle_tlb_pending_event(vgpu, ring_id); @@ -336,21 +323,15 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; - struct render_mmio *mmio; i915_reg_t last_reg = _MMIO(0); + struct engine_mmio *mmio; u32 v; - int i, array_size; - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { - mmio = gen9_render_mmio_list; - array_size = ARRAY_SIZE(gen9_render_mmio_list); + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) restore_mocs(vgpu, ring_id); - } else { - mmio = gen8_render_mmio_list; - array_size = ARRAY_SIZE(gen8_render_mmio_list); - } - for (i = 0; i < array_size; i++, mmio++) { + mmio = vgpu->gvt->engine_mmio_list; + while (i915_mmio_reg_offset((mmio++)->reg)) { if (mmio->ring_id != ring_id) continue; @@ -374,7 +355,7 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) } /* Make sure the swiched MMIOs has taken effect. */ - if (likely(INTEL_GVT_MMIO_OFFSET(last_reg))) + if (likely(i915_mmio_reg_offset(last_reg))) I915_READ_FW(last_reg); } @@ -419,3 +400,16 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre, intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } + +/** + * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list + * @gvt: GVT device + * + */ +void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt) +{ + if (IS_SKYLAKE(gvt->dev_priv) || IS_KABYLAKE(gvt->dev_priv)) + gvt->engine_mmio_list = gen9_engine_mmio_list; + else + gvt->engine_mmio_list = gen8_engine_mmio_list; +} diff --git a/drivers/gpu/drm/i915/gvt/render.h b/drivers/gpu/drm/i915/gvt/render.h index 91db1d39d28f..ca2c6a745673 100644 --- a/drivers/gpu/drm/i915/gvt/render.h +++ b/drivers/gpu/drm/i915/gvt/render.h @@ -36,8 +36,17 @@ #ifndef __GVT_RENDER_H__ #define __GVT_RENDER_H__ +struct engine_mmio { + int ring_id; + i915_reg_t reg; + u32 mask; + bool in_context; + u32 value; +}; + void intel_gvt_switch_mmio(struct intel_vgpu *pre, struct intel_vgpu *next, int ring_id); +void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt); #endif -- GitLab From cf27b950346d5201c291c4e189ed1436a136ae4d Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Fri, 8 Dec 2017 14:56:22 +0800 Subject: [PATCH 1071/2547] drm/i915/gvt: Remove MMIO barrier in MMIO switch After engine mmio switched, software still need write workload submission registers. So we can remove the MMIO barriar in MMIO switch. Signed-off-by: Changbin Du Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/render.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index 3e675f81815f..4c8e1285c607 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -275,7 +275,6 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL]; u32 inhibit_mask = _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); - i915_reg_t last_reg = _MMIO(0); struct engine_mmio *mmio; u32 v; @@ -305,17 +304,12 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) v = vgpu_vreg(vgpu, mmio->reg); I915_WRITE_FW(mmio->reg, v); - last_reg = mmio->reg; trace_render_mmio(vgpu->id, "load", i915_mmio_reg_offset(mmio->reg), mmio->value, v); } - /* Make sure the swiched MMIOs has taken effect. */ - if (likely(i915_mmio_reg_offset(last_reg))) - I915_READ_FW(last_reg); - handle_tlb_pending_event(vgpu, ring_id); } @@ -323,7 +317,6 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; - i915_reg_t last_reg = _MMIO(0); struct engine_mmio *mmio; u32 v; @@ -347,16 +340,11 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) continue; I915_WRITE_FW(mmio->reg, v); - last_reg = mmio->reg; trace_render_mmio(vgpu->id, "restore", i915_mmio_reg_offset(mmio->reg), mmio->value, v); } - - /* Make sure the swiched MMIOs has taken effect. */ - if (likely(i915_mmio_reg_offset(last_reg))) - I915_READ_FW(last_reg); } /** -- GitLab From 1aec75ee327f2f2085a4e2b060a3d999b8f4d925 Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Fri, 8 Dec 2017 14:56:23 +0800 Subject: [PATCH 1072/2547] drm/i915/gvt: Rename file render.{c, h} to mmio_context.{c, h} Rename the files to reflect their real role - to switch the mmio context of each vGPU engine. v2: update Makefile. Signed-off-by: Changbin Du Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/Makefile | 2 +- drivers/gpu/drm/i915/gvt/gvt.h | 2 +- drivers/gpu/drm/i915/gvt/{render.c => mmio_context.c} | 0 drivers/gpu/drm/i915/gvt/{render.h => mmio_context.h} | 0 4 files changed, 2 insertions(+), 2 deletions(-) rename drivers/gpu/drm/i915/gvt/{render.c => mmio_context.c} (100%) rename drivers/gpu/drm/i915/gvt/{render.h => mmio_context.h} (100%) diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile index cae06c1dcdcd..0ee9c6250e90 100644 --- a/drivers/gpu/drm/i915/gvt/Makefile +++ b/drivers/gpu/drm/i915/gvt/Makefile @@ -1,7 +1,7 @@ GVT_DIR := gvt GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \ interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \ - execlist.o scheduler.o sched_policy.o render.o cmd_parser.o debugfs.o \ + execlist.o scheduler.o sched_policy.o mmio_context.o cmd_parser.o debugfs.o \ fb_decoder.o dmabuf.o ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 39c2f3a4588e..b4747c270dcb 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -44,7 +44,7 @@ #include "execlist.h" #include "scheduler.h" #include "sched_policy.h" -#include "render.h" +#include "mmio_context.h" #include "cmd_parser.h" #include "fb_decoder.h" #include "dmabuf.h" diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/mmio_context.c similarity index 100% rename from drivers/gpu/drm/i915/gvt/render.c rename to drivers/gpu/drm/i915/gvt/mmio_context.c diff --git a/drivers/gpu/drm/i915/gvt/render.h b/drivers/gpu/drm/i915/gvt/mmio_context.h similarity index 100% rename from drivers/gpu/drm/i915/gvt/render.h rename to drivers/gpu/drm/i915/gvt/mmio_context.h -- GitLab From 072ec93d50fd4c4b27ea44fff160a95c2b581eb1 Mon Sep 17 00:00:00 2001 From: Pei Zhang Date: Fri, 8 Dec 2017 15:31:12 +0800 Subject: [PATCH 1073/2547] drm/i915/gvt/kvmgt: fill info for ROM/VGA region Both ROM/VGA region are not supported for vGPU in GVT. But if the device model want to get those region, we should return the correct information but not leave the structure with random data. Change to same operation of BAR3-BAR5 which are also not supported by vGPU. Refer to function @intel_vgpu_rw. Signed-off-by: Pei Zhang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/kvmgt.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index b8a85e08091a..f86983d6655b 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -1029,13 +1029,17 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, unsigned int cmd, case VFIO_PCI_BAR3_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX: info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); info.size = 0; - info.flags = 0; + gvt_dbg_core("get region info bar:%d\n", info.index); break; case VFIO_PCI_ROM_REGION_INDEX: case VFIO_PCI_VGA_REGION_INDEX: + info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); + info.size = 0; + info.flags = 0; + gvt_dbg_core("get region info index:%d\n", info.index); break; default: -- GitLab From 6ee942d5f7e3e630d3a2517e75969ce5d07c87d6 Mon Sep 17 00:00:00 2001 From: Tina Zhang Date: Fri, 8 Dec 2017 15:17:38 +0800 Subject: [PATCH 1074/2547] drm/i915/gvt: Refine dmabuf_obj cleanup process In the process of dmabuf_obj cleanup, the dmabuf_obj might be freed during dmabuf_obj_put leaking intel_gvt_hypervisor_put_vfio_device. Move intel_gvt_hypervisor_put_vfio_device and all the other dmabuf_obj ops in front of dmabuf_obj_put and let every dmabuf_obj have a chance to call intel_gvt_hypervisor_put_vfio_device to fix this leaking issue. Fixes: e3a0d7976c53 ("drm/i915/gvt: Handle orphan dmabuf_objs") Signed-off-by: Tina Zhang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/dmabuf.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c index 9c40a67ecdd6..2ab584f97dfb 100644 --- a/drivers/gpu/drm/i915/gvt/dmabuf.c +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c @@ -520,19 +520,18 @@ void intel_vgpu_dmabuf_cleanup(struct intel_vgpu *vgpu) list_for_each_safe(pos, n, &vgpu->dmabuf_obj_list_head) { dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj, list); + dmabuf_obj->vgpu = NULL; + + idr_remove(&vgpu->object_idr, dmabuf_obj->dmabuf_id); + intel_gvt_hypervisor_put_vfio_device(vgpu); + list_del(pos); + + /* dmabuf_obj might be freed in dmabuf_obj_put */ if (dmabuf_obj->initref) { dmabuf_obj->initref = false; dmabuf_obj_put(dmabuf_obj); } - idr_remove(&vgpu->object_idr, dmabuf_obj->dmabuf_id); - - if (dmabuf_obj->vgpu) - intel_gvt_hypervisor_put_vfio_device(vgpu); - - list_del(pos); - dmabuf_obj->vgpu = NULL; - } mutex_unlock(&vgpu->dmabuf_lock); } -- GitLab From c7f33023308f3142433b7379718af5f0c2c322a6 Mon Sep 17 00:00:00 2001 From: Martin Kelly Date: Tue, 5 Dec 2017 10:34:03 -0800 Subject: [PATCH 1075/2547] can: mcba_usb: cancel urb on -EPROTO When we unplug the device, we can see both -EPIPE and -EPROTO depending on exact timing and what system we run on. If we continue to resubmit URBs, they will immediately fail, and they can cause stalls, especially on slower CPUs. Fix this by not resubmitting on -EPROTO, as we already do on -EPIPE. Signed-off-by: Martin Kelly Cc: linux-stable Signed-off-by: Marc Kleine-Budde --- drivers/net/can/usb/mcba_usb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/can/usb/mcba_usb.c b/drivers/net/can/usb/mcba_usb.c index ef417dcddbf7..8d8c2086424d 100644 --- a/drivers/net/can/usb/mcba_usb.c +++ b/drivers/net/can/usb/mcba_usb.c @@ -593,6 +593,7 @@ static void mcba_usb_read_bulk_callback(struct urb *urb) case -ENOENT: case -EPIPE: + case -EPROTO: case -ESHUTDOWN: return; -- GitLab From bd352e1adfe0d02d3ea7c8e3fb19183dc317e679 Mon Sep 17 00:00:00 2001 From: Martin Kelly Date: Tue, 5 Dec 2017 11:15:47 -0800 Subject: [PATCH 1076/2547] can: ems_usb: cancel urb on -EPIPE and -EPROTO In mcba_usb, we have observed that when you unplug the device, the driver will endlessly resubmit failing URBs, which can cause CPU stalls. This issue is fixed in mcba_usb by catching the codes seen on device disconnect (-EPIPE and -EPROTO). This driver also resubmits in the case of -EPIPE and -EPROTO, so fix it in the same way. Signed-off-by: Martin Kelly Cc: linux-stable Signed-off-by: Marc Kleine-Budde --- drivers/net/can/usb/ems_usb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/can/usb/ems_usb.c b/drivers/net/can/usb/ems_usb.c index b3d02759c226..b00358297424 100644 --- a/drivers/net/can/usb/ems_usb.c +++ b/drivers/net/can/usb/ems_usb.c @@ -288,6 +288,8 @@ static void ems_usb_read_interrupt_callback(struct urb *urb) case -ECONNRESET: /* unlink */ case -ENOENT: + case -EPIPE: + case -EPROTO: case -ESHUTDOWN: return; -- GitLab From 7a31ced3de06e9878e4f9c3abe8f87d9344d8144 Mon Sep 17 00:00:00 2001 From: Martin Kelly Date: Tue, 5 Dec 2017 11:15:48 -0800 Subject: [PATCH 1077/2547] can: esd_usb2: cancel urb on -EPIPE and -EPROTO In mcba_usb, we have observed that when you unplug the device, the driver will endlessly resubmit failing URBs, which can cause CPU stalls. This issue is fixed in mcba_usb by catching the codes seen on device disconnect (-EPIPE and -EPROTO). This driver also resubmits in the case of -EPIPE and -EPROTO, so fix it in the same way. Signed-off-by: Martin Kelly Cc: linux-stable Signed-off-by: Marc Kleine-Budde --- drivers/net/can/usb/esd_usb2.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/can/usb/esd_usb2.c b/drivers/net/can/usb/esd_usb2.c index 9fdb0f0bfa06..c6dcf93675c0 100644 --- a/drivers/net/can/usb/esd_usb2.c +++ b/drivers/net/can/usb/esd_usb2.c @@ -393,6 +393,8 @@ static void esd_usb2_read_bulk_callback(struct urb *urb) break; case -ENOENT: + case -EPIPE: + case -EPROTO: case -ESHUTDOWN: return; -- GitLab From 6aa8d5945502baf4687d80de59b7ac865e9e666b Mon Sep 17 00:00:00 2001 From: Martin Kelly Date: Tue, 5 Dec 2017 11:15:49 -0800 Subject: [PATCH 1078/2547] can: kvaser_usb: cancel urb on -EPIPE and -EPROTO In mcba_usb, we have observed that when you unplug the device, the driver will endlessly resubmit failing URBs, which can cause CPU stalls. This issue is fixed in mcba_usb by catching the codes seen on device disconnect (-EPIPE and -EPROTO). This driver also resubmits in the case of -EPIPE and -EPROTO, so fix it in the same way. Signed-off-by: Martin Kelly Cc: linux-stable Signed-off-by: Marc Kleine-Budde --- drivers/net/can/usb/kvaser_usb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/can/usb/kvaser_usb.c b/drivers/net/can/usb/kvaser_usb.c index f95945915d20..63587b8e6825 100644 --- a/drivers/net/can/usb/kvaser_usb.c +++ b/drivers/net/can/usb/kvaser_usb.c @@ -1326,6 +1326,8 @@ static void kvaser_usb_read_bulk_callback(struct urb *urb) case 0: break; case -ENOENT: + case -EPIPE: + case -EPROTO: case -ESHUTDOWN: return; default: -- GitLab From 12147edc434c9e4c7c2f5fee2e5519b2e5ac34ce Mon Sep 17 00:00:00 2001 From: Martin Kelly Date: Tue, 5 Dec 2017 11:15:50 -0800 Subject: [PATCH 1079/2547] can: usb_8dev: cancel urb on -EPIPE and -EPROTO In mcba_usb, we have observed that when you unplug the device, the driver will endlessly resubmit failing URBs, which can cause CPU stalls. This issue is fixed in mcba_usb by catching the codes seen on device disconnect (-EPIPE and -EPROTO). This driver also resubmits in the case of -EPIPE and -EPROTO, so fix it in the same way. Signed-off-by: Martin Kelly Cc: linux-stable Signed-off-by: Marc Kleine-Budde --- drivers/net/can/usb/usb_8dev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/can/usb/usb_8dev.c b/drivers/net/can/usb/usb_8dev.c index d000cb62d6ae..27861c417c94 100644 --- a/drivers/net/can/usb/usb_8dev.c +++ b/drivers/net/can/usb/usb_8dev.c @@ -524,6 +524,8 @@ static void usb_8dev_read_bulk_callback(struct urb *urb) break; case -ENOENT: + case -EPIPE: + case -EPROTO: case -ESHUTDOWN: return; -- GitLab From 91785de6f94b58c3fb6664609e3682f011bd28d2 Mon Sep 17 00:00:00 2001 From: Stephane Grosjean Date: Thu, 7 Dec 2017 16:13:43 +0100 Subject: [PATCH 1080/2547] can: peak/pcie_fd: fix potential bug in restarting tx queue Don't rely on can_get_echo_skb() return value to wake the network tx queue up: can_get_echo_skb() returns 0 if the echo array slot was not occupied, but also when the DLC of the released echo frame was 0. Signed-off-by: Stephane Grosjean Cc: linux-stable Signed-off-by: Marc Kleine-Budde --- drivers/net/can/peak_canfd/peak_canfd.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/net/can/peak_canfd/peak_canfd.c b/drivers/net/can/peak_canfd/peak_canfd.c index 85268be0c913..55513411a82e 100644 --- a/drivers/net/can/peak_canfd/peak_canfd.c +++ b/drivers/net/can/peak_canfd/peak_canfd.c @@ -258,21 +258,18 @@ static int pucan_handle_can_rx(struct peak_canfd_priv *priv, /* if this frame is an echo, */ if ((rx_msg_flags & PUCAN_MSG_LOOPED_BACK) && !(rx_msg_flags & PUCAN_MSG_SELF_RECEIVE)) { - int n; unsigned long flags; spin_lock_irqsave(&priv->echo_lock, flags); - n = can_get_echo_skb(priv->ndev, msg->client); + can_get_echo_skb(priv->ndev, msg->client); spin_unlock_irqrestore(&priv->echo_lock, flags); /* count bytes of the echo instead of skb */ stats->tx_bytes += cf_len; stats->tx_packets++; - if (n) { - /* restart tx queue only if a slot is free */ - netif_wake_queue(priv->ndev); - } + /* restart tx queue (a slot is free) */ + netif_wake_queue(priv->ndev); return 0; } -- GitLab From 040d786032bf59002d374b86d75b04d97624005c Mon Sep 17 00:00:00 2001 From: "Yan, Zheng" Date: Thu, 30 Nov 2017 11:59:22 +0800 Subject: [PATCH 1081/2547] ceph: drop negative child dentries before try pruning inode's alias Negative child dentry holds reference on inode's alias, it makes d_prune_aliases() do nothing. Cc: stable@vger.kernel.org Signed-off-by: "Yan, Zheng" Reviewed-by: Jeff Layton Signed-off-by: Ilya Dryomov --- fs/ceph/mds_client.c | 42 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/fs/ceph/mds_client.c b/fs/ceph/mds_client.c index ab69dcb70e8a..1b468250e947 100644 --- a/fs/ceph/mds_client.c +++ b/fs/ceph/mds_client.c @@ -1440,6 +1440,29 @@ static int __close_session(struct ceph_mds_client *mdsc, return request_close_session(mdsc, session); } +static bool drop_negative_children(struct dentry *dentry) +{ + struct dentry *child; + bool all_negative = true; + + if (!d_is_dir(dentry)) + goto out; + + spin_lock(&dentry->d_lock); + list_for_each_entry(child, &dentry->d_subdirs, d_child) { + if (d_really_is_positive(child)) { + all_negative = false; + break; + } + } + spin_unlock(&dentry->d_lock); + + if (all_negative) + shrink_dcache_parent(dentry); +out: + return all_negative; +} + /* * Trim old(er) caps. * @@ -1490,16 +1513,27 @@ static int trim_caps_cb(struct inode *inode, struct ceph_cap *cap, void *arg) if ((used | wanted) & ~oissued & mine) goto out; /* we need these caps */ - session->s_trim_caps--; if (oissued) { /* we aren't the only cap.. just remove us */ __ceph_remove_cap(cap, true); + session->s_trim_caps--; } else { + struct dentry *dentry; /* try dropping referring dentries */ spin_unlock(&ci->i_ceph_lock); - d_prune_aliases(inode); - dout("trim_caps_cb %p cap %p pruned, count now %d\n", - inode, cap, atomic_read(&inode->i_count)); + dentry = d_find_any_alias(inode); + if (dentry && drop_negative_children(dentry)) { + int count; + dput(dentry); + d_prune_aliases(inode); + count = atomic_read(&inode->i_count); + if (count == 1) + session->s_trim_caps--; + dout("trim_caps_cb %p cap %p pruned, count now %d\n", + inode, cap, count); + } else { + dput(dentry); + } return 0; } -- GitLab From b68763741aa29f2541c7ca58bcb0c2bb6cb5f449 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 5 Dec 2017 13:28:54 +0000 Subject: [PATCH 1082/2547] drm/i915: Restore GT performance in headless mode with DMC loaded It seems that the DMC likes to transition between the DC states a lot when there are no connected displays (no active power domains) during command submission. This activity on DC states has a negative impact on the performance of the chip with huge latencies observed in the interrupt handlers and elsewhere. Simple tests like igt/gem_latency -n 0 are slowed down by a factor of eight. Work around it by introducing a new power domain named, POWER_DOMAIN_GT_IRQ, associtated with the "DC off" power well, which is held for the duration of command submission activity. CNL has the same problem which will be addressed as a follow-up. Doing that requires a fix for a DC6 context corruption problem in the CNL DMC firmware which is yet to be released. v2: * Add commit text as comment in i915_gem_mark_busy. (Chris Wilson) * Protect macro body with braces. (Jani Nikula) v3: * Add dedicated power domain for clarity. (Chris, Imre) * Commit message and comment text updates. * Apply to all big-core GEN9 parts apart for Skylake which is pending DMC firmware release. v4: * Power domain should be inner to device runtime pm. (Chris) * Simplify NEEDS_CSR_GT_PERF_WA macro. (Chris) * Handle async DMC loading by moving the GT_IRQ power domain logic into intel_runtime_pm. (Daniel, Chris) * Include small core GEN9 as well. (Imre) v5 * Special handling for async DMC load is not needed since on failure the power domain reference is kept permanently taken. (Imre) v6: * Drop the NEEDS_CSR_GT_PERF_WA macro since all firmwares have now been deployed. (Imre, Chris) Signed-off-by: Tvrtko Ursulin Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100572 Testcase: igt/gem_exec_nop/headless Cc: Imre Deak Acked-by: Chris Wilson (v2) Cc: Chris Wilson Cc: Dmitry Rogozhkin Reviewed-by: Daniel Vetter (v5) Reviewed-by: Chris Wilson [Imre: Add note about applying the WA on CNL as a follow-up] Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20171205132854.26380-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 3 +++ drivers/gpu/drm/i915/i915_gem_request.c | 14 ++++++++++++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 5 +++++ 4 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f9386e793c87..d57859cfad8e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -398,6 +398,7 @@ enum intel_display_power_domain { POWER_DOMAIN_AUX_D, POWER_DOMAIN_GMBUS, POWER_DOMAIN_MODESET, + POWER_DOMAIN_GT_IRQ, POWER_DOMAIN_INIT, POWER_DOMAIN_NUM, diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index c7b5db78fbb4..fcc9b53864f0 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3386,6 +3386,9 @@ i915_gem_idle_work_handler(struct work_struct *work) if (INTEL_GEN(dev_priv) >= 6) gen6_rps_idle(dev_priv); + + intel_display_power_put(dev_priv, POWER_DOMAIN_GT_IRQ); + intel_runtime_pm_put(dev_priv); out_unlock: mutex_unlock(&dev_priv->drm.struct_mutex); diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index a90bdd26571f..c28a4ceb016d 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -252,6 +252,20 @@ static void mark_busy(struct drm_i915_private *i915) GEM_BUG_ON(!i915->gt.active_requests); intel_runtime_pm_get_noresume(i915); + + /* + * It seems that the DMC likes to transition between the DC states a lot + * when there are no connected displays (no active power domains) during + * command submission. + * + * This activity has negative impact on the performance of the chip with + * huge latencies observed in the interrupt handler and elsewhere. + * + * Work around it by grabbing a GT IRQ power domain whilst there is any + * GT activity, preventing any DC state transitions. + */ + intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ); + i915->gt.awake = true; intel_enable_gt_powersave(i915); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 8315499452dc..96ab74f3d101 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -130,6 +130,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) return "INIT"; case POWER_DOMAIN_MODESET: return "MODESET"; + case POWER_DOMAIN_GT_IRQ: + return "GT_IRQ"; default: MISSING_CASE(domain); return "?"; @@ -1705,6 +1707,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_INIT)) #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ BIT_ULL(POWER_DOMAIN_MODESET) | \ BIT_ULL(POWER_DOMAIN_AUX_A) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -1727,6 +1730,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_INIT)) #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ BIT_ULL(POWER_DOMAIN_MODESET) | \ BIT_ULL(POWER_DOMAIN_AUX_A) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -1785,6 +1789,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_INIT)) #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \ GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ BIT_ULL(POWER_DOMAIN_MODESET) | \ BIT_ULL(POWER_DOMAIN_AUX_A) | \ BIT_ULL(POWER_DOMAIN_INIT)) -- GitLab From 7a1530d7f91fe670b8033aadb1db4dae64512abb Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 7 Dec 2017 15:32:02 +0100 Subject: [PATCH 1083/2547] intel/atomic: Stop updating legacy fb parameters MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Even fbc isn't using this stuff anymore, so time to remove it. Cleaning up one small piece of the atomic conversion cruft at the time ... Quick explanation on why the plane->fb assignment is ok to delete: The core code takes care of the refcounting and legacy ->fb pointer updating, but drivers are allowed to update it ahead of time. Most legacy modeset drivers did that as part of their set_config callback (since that's how the legacy/crtc helpers worked). In i915 we only need that to make the fbc code happy. v2: don't nuke the assignement of intel_crtc->config, I accidentally set CI ablaze :-) Spotted by Maarten. And better explain why nuking the ->fb assignement shouldn't set off alarm bells. Cc: Paulo Zanoni Cc: Ville Syrjälä Cc: Maarten Lankhorst Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171207143202.6021-1-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/intel_display.c | 31 +++------------------------- 1 file changed, 3 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 47a2f6acee50..e355d780a4cd 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10966,31 +10966,6 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, return ret; } -static void -intel_modeset_update_crtc_state(struct drm_atomic_state *state) -{ - struct drm_crtc *crtc; - struct drm_crtc_state *new_crtc_state; - int i; - - /* Double check state. */ - for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { - to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state); - - /* - * Update legacy state to satisfy fbc code. This can - * be removed when fbc uses the atomic state. - */ - if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { - struct drm_plane_state *plane_state = crtc->primary->state; - - crtc->primary->fb = plane_state->fb; - crtc->x = plane_state->src_x >> 16; - crtc->y = plane_state->src_y >> 16; - } - } -} - static bool intel_fuzzy_clock_check(int clock1, int clock2) { int diff; @@ -12363,9 +12338,9 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) } } - /* Only after disabling all output pipelines that will be changed can we - * update the the output configuration. */ - intel_modeset_update_crtc_state(state); + /* FIXME: Eventually get rid of our intel_crtc->config pointer */ + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) + to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state); if (intel_state->modeset) { drm_atomic_helper_update_legacy_modeset_state(state->dev, state); -- GitLab From 451df7d110b82998c04a80d0de0f1e79aaa7792a Mon Sep 17 00:00:00 2001 From: Alejandro Mery Date: Fri, 8 Dec 2017 10:35:58 +0000 Subject: [PATCH 1084/2547] ARM: davinci: fix mmc entries in dm365's dma_slave_map fix mmc entries in dm365's dma_slave_map to match the actual device names Fixes: 0c750e1fe481 ("ARM: davinci: dm365: Add dma_slave_map to edma") Signed-off-by: Alejandro Mery Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/dm365.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 103316f01a22..5ace9380626a 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -868,10 +868,10 @@ static const struct dma_slave_map dm365_edma_map[] = { { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) }, { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) }, { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) }, - { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, - { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, - { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) }, - { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) }, + { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, + { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, + { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) }, + { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) }, }; static struct edma_soc_info dm365_edma_pdata = { -- GitLab From 3e72be177cf19ab3d62b3084d424dce7e71d847f Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 7 Dec 2017 22:00:25 +0000 Subject: [PATCH 1085/2547] drm/i915: Drop fb reference on load_detect_pipe failure path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When intel_modeset_setup_plane_state() fails drop the local framebuffer reference before jumping to the error, otherwise we leak the framebuffer. Signed-off-by: Chris Wilson Cc: Maarten Lankhorst Cc: Ville Syrjälä Cc: Daniel Vetter Fixes: edde361711ef ("drm/i915: Use atomic state to obtain load detection crtc, v3.") Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171207220025.22698-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_display.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e355d780a4cd..be56f0150cd9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9939,11 +9939,10 @@ int intel_get_load_detect_pipe(struct drm_connector *connector, } ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); + drm_framebuffer_put(fb); if (ret) goto fail; - drm_framebuffer_put(fb); - ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); if (ret) goto fail; -- GitLab From 33cd3c07a976e11c3c4cc6b0b3db6760ad1590c5 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 8 Dec 2017 12:16:22 +0000 Subject: [PATCH 1086/2547] drm/armada: fix leak of crtc structure Fix the leak of the CRTC structure in the failure paths of armada_drm_crtc_create(). Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 2e065facdce7..50a3a97b4289 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -1225,17 +1225,13 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc", dcrtc); - if (ret < 0) { - kfree(dcrtc); - return ret; - } + if (ret < 0) + goto err_crtc; if (dcrtc->variant->init) { ret = dcrtc->variant->init(dcrtc, dev); - if (ret) { - kfree(dcrtc); - return ret; - } + if (ret) + goto err_crtc; } /* Ensure AXI pipeline is enabled */ @@ -1246,13 +1242,15 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, dcrtc->crtc.port = port; primary = kzalloc(sizeof(*primary), GFP_KERNEL); - if (!primary) - return -ENOMEM; + if (!primary) { + ret = -ENOMEM; + goto err_crtc; + } ret = armada_drm_plane_init(primary); if (ret) { kfree(primary); - return ret; + goto err_crtc; } ret = drm_universal_plane_init(drm, &primary->base, 0, @@ -1263,7 +1261,7 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, DRM_PLANE_TYPE_PRIMARY, NULL); if (ret) { kfree(primary); - return ret; + goto err_crtc; } ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL, @@ -1282,6 +1280,9 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, err_crtc_init: primary->base.funcs->destroy(&primary->base); +err_crtc: + kfree(dcrtc); + return ret; } -- GitLab From 2bf57436d52b241044133fb0e2c7fd8320c6b02e Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 8 Dec 2017 12:16:22 +0000 Subject: [PATCH 1087/2547] drm/armada: fix SRAM powerdown Avoid powering down the overlay SRAM banks when disabling the primary plane, thereby masking any overlay video. This feature is supposed to allow us to cut the bandwidth required while displaying full-frame overlay video. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 50a3a97b4289..400a133c0576 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -744,15 +744,14 @@ void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, if (plane->fb) drm_framebuffer_put(plane->fb); - /* Power down the Y/U/V FIFOs */ - sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66; - /* Power down most RAMs and FIFOs if this is the primary plane */ if (plane->type == DRM_PLANE_TYPE_PRIMARY) { - sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | - CFG_PDWN32x32 | CFG_PDWN64x66; + sram_para1 = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | + CFG_PDWN32x32 | CFG_PDWN64x66; dma_ctrl0_mask = CFG_GRA_ENA; } else { + /* Power down the Y/U/V FIFOs */ + sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66; dma_ctrl0_mask = CFG_DMA_ENA; } -- GitLab From 9c898c495490b129bd4445630e3c6641e8389fc8 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 8 Dec 2017 12:16:22 +0000 Subject: [PATCH 1088/2547] drm/armada: fix UV swap code The UV swap code was not always programming things correctly when the source origin box has been offset. Fix this. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.h | 2 ++ drivers/gpu/drm/armada/armada_overlay.c | 38 ++++++++++++------------- 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index bab11f483575..bfd3514fbe9b 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -42,6 +42,8 @@ struct armada_plane_work { }; struct armada_plane_state { + u16 src_x; + u16 src_y; u32 src_hw; u32 dst_hw; u32 dst_yx; diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index b411b608821a..aba947696178 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -99,6 +99,7 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, { struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); + const struct drm_format_info *format; struct drm_rect src = { .x1 = src_x, .y1 = src_y, @@ -117,7 +118,7 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, }; uint32_t val, ctrl0; unsigned idx = 0; - bool visible; + bool visible, fb_changed; int ret; trace_armada_ovl_plane_update(plane, crtc, fb, @@ -138,6 +139,18 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, if (!visible) ctrl0 &= ~CFG_DMA_ENA; + /* + * Shifting a YUV packed format image by one pixel causes the U/V + * planes to swap. Compensate for it by also toggling the UV swap. + */ + format = fb->format; + if (format->num_planes == 1 && src.x1 >> 16 & (format->hsub - 1)) + ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV); + + fb_changed = plane->fb != fb || + dplane->base.state.src_x != src.x1 >> 16 || + dplane->base.state.src_y != src.y1 >> 16; + if (!dcrtc->plane) { dcrtc->plane = plane; armada_ovl_update_attr(&dplane->prop, dcrtc); @@ -145,7 +158,7 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, /* FIXME: overlay on an interlaced display */ /* Just updating the position/size? */ - if (plane->fb == fb && dplane->base.state.ctrl0 == ctrl0) { + if (!fb_changed && dplane->base.state.ctrl0 == ctrl0) { val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16; dplane->base.state.src_hw = val; @@ -169,9 +182,8 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0) armada_drm_plane_work_cancel(dcrtc, &dplane->base); - if (plane->fb != fb) { - u32 addrs[3], pixel_format; - int num_planes, hsub; + if (fb_changed) { + u32 addrs[3]; /* * Take a reference on the new framebuffer - we want to @@ -182,23 +194,11 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, if (plane->fb) armada_ovl_retire_fb(dplane, plane->fb); - src_y = src.y1 >> 16; - src_x = src.x1 >> 16; + dplane->base.state.src_y = src_y = src.y1 >> 16; + dplane->base.state.src_x = src_x = src.x1 >> 16; armada_drm_plane_calc_addrs(addrs, fb, src_x, src_y); - pixel_format = fb->format->format; - hsub = drm_format_horz_chroma_subsampling(pixel_format); - num_planes = fb->format->num_planes; - - /* - * Annoyingly, shifting a YUYV-format image by one pixel - * causes the U/V planes to toggle. Toggle the UV swap. - * (Unfortunately, this causes momentary colour flickering.) - */ - if (src_x & (hsub - 1) && num_planes == 1) - ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV); - armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0], LCD_SPU_DMA_START_ADDR_Y0); armada_reg_queue_set(dplane->vbl.regs, idx, addrs[1], -- GitLab From d6a48965db3d5f9b524ebfdd8c1fe3a4175d8e35 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 8 Dec 2017 12:16:22 +0000 Subject: [PATCH 1089/2547] drm/armada: improve efficiency of armada_drm_plane_calc_addrs() Lookup the drm_format_info structure once when computing all the framebuffer plane addresses by using drm_format_info(), rather than repetitive lookups via drm_format_plane_cpp(). Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 400a133c0576..7f7b3e738679 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -168,8 +168,9 @@ static void armada_drm_crtc_update(struct armada_crtc *dcrtc) void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb, int x, int y) { + const struct drm_format_info *format = fb->format; + unsigned int num_planes = format->num_planes; u32 addr = drm_fb_obj(fb)->dev_addr; - int num_planes = fb->format->num_planes; int i; if (num_planes > 3) @@ -177,7 +178,7 @@ void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb, for (i = 0; i < num_planes; i++) addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] + - x * fb->format->cpp[i]; + x * format->cpp[i]; for (; i < 3; i++) addrs[i] = 0; } -- GitLab From de0ea9ad2f548dd9e555cac27cf7ade1db5b26ea Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 8 Dec 2017 12:16:22 +0000 Subject: [PATCH 1090/2547] drm/armada: fix YUV planar format framebuffer offsets We weren't correctly calculating the YUV planar offsets for subsampled chroma planes correctly - fix up the coordinates for planes 1 and 2. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 7f7b3e738679..a0f4d2a2a481 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -176,7 +176,13 @@ void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb, if (num_planes > 3) num_planes = 3; - for (i = 0; i < num_planes; i++) + addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] + + x * format->cpp[0]; + + y /= format->vsub; + x /= format->hsub; + + for (i = 1; i < num_planes; i++) addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] + x * format->cpp[i]; for (; i < 3; i++) -- GitLab From d3b842154383a037cd38cd7e31234c3723c1f31d Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 7 Jul 2017 15:55:40 +0100 Subject: [PATCH 1091/2547] drm/armada: remove armada_drm_plane_work_cancel() return value armada_drm_plane_work_cancel()'s returned work structure is never used or referenced, so it's pointless returning it. It's also pointless because the caller doesn't have a clue what kind of work structure it is. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 8 +++----- drivers/gpu/drm/armada/armada_crtc.h | 4 ++-- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index a0f4d2a2a481..7d2dfdfffb5e 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -254,15 +254,13 @@ int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout) return wait_event_timeout(plane->frame_wait, !plane->work, timeout); } -struct armada_plane_work *armada_drm_plane_work_cancel( - struct armada_crtc *dcrtc, struct armada_plane *plane) +void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc, + struct armada_plane *dplane) { - struct armada_plane_work *work = xchg(&plane->work, NULL); + struct armada_plane_work *work = xchg(&dplane->work, NULL); if (work) drm_crtc_vblank_put(&dcrtc->crtc); - - return work; } static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc, diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index bfd3514fbe9b..a054527eb962 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -62,8 +62,8 @@ int armada_drm_plane_init(struct armada_plane *plane); int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, struct armada_plane *plane, struct armada_plane_work *work); int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout); -struct armada_plane_work *armada_drm_plane_work_cancel( - struct armada_crtc *dcrtc, struct armada_plane *plane); +void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc, + struct armada_plane *plane); void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb, int x, int y); -- GitLab From 901bb88991654537a35ca1da5709ac4bf3a2d01e Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 7 Jul 2017 15:55:45 +0100 Subject: [PATCH 1092/2547] drm/armada: add a common frame work allocator Add and use a common frame work allocator, initialising the frame work to a sane state. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 7d2dfdfffb5e..8606f6e35986 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -293,6 +293,21 @@ static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, kfree(fwork); } +static struct armada_frame_work *armada_drm_crtc_alloc_frame_work(void) +{ + struct armada_frame_work *work; + int i = 0; + + work = kzalloc(sizeof(*work), GFP_KERNEL); + if (!work) + return NULL; + + work->work.fn = armada_drm_crtc_complete_frame_work; + armada_reg_queue_end(work->regs, i); + + return work; +} + static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, struct drm_framebuffer *fb, bool force) { @@ -307,13 +322,9 @@ static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, return; } - work = kmalloc(sizeof(*work), GFP_KERNEL); + work = armada_drm_crtc_alloc_frame_work(); if (work) { - int i = 0; - work->work.fn = armada_drm_crtc_complete_frame_work; - work->event = NULL; work->old_fb = fb; - armada_reg_queue_end(work->regs, i); if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0) return; @@ -1033,11 +1044,10 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, if (fb->format != crtc->primary->fb->format) return -EINVAL; - work = kmalloc(sizeof(*work), GFP_KERNEL); + work = armada_drm_crtc_alloc_frame_work(); if (!work) return -ENOMEM; - work->work.fn = armada_drm_crtc_complete_frame_work; work->event = event; work->old_fb = dcrtc->crtc.primary->fb; -- GitLab From eaab01307554175a004ad60728beb691cc841a8c Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 7 Jul 2017 15:55:53 +0100 Subject: [PATCH 1093/2547] drm/armada: store plane in armada_plane_work Store the plane in the armada_plane_work structure rather than passing it around; it doesn't get used very much in the work structures, so passing it around is a needless expense. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 27 ++++++++++--------------- drivers/gpu/drm/armada/armada_crtc.h | 7 +++---- drivers/gpu/drm/armada/armada_overlay.c | 12 ++++++----- 3 files changed, 21 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 8606f6e35986..4d3db441466e 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -224,7 +224,7 @@ static void armada_drm_plane_work_run(struct armada_crtc *dcrtc, /* Handle any pending frame work. */ if (work) { - work->fn(dcrtc, dplane, work); + work->fn(dcrtc, work); drm_crtc_vblank_put(&dcrtc->crtc); } @@ -232,8 +232,9 @@ static void armada_drm_plane_work_run(struct armada_crtc *dcrtc, } int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, - struct armada_plane *plane, struct armada_plane_work *work) + struct armada_plane_work *work) { + struct armada_plane *plane = drm_to_armada_plane(work->plane); int ret; ret = drm_crtc_vblank_get(&dcrtc->crtc); @@ -263,16 +264,8 @@ void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc, drm_crtc_vblank_put(&dcrtc->crtc); } -static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc, - struct armada_frame_work *work) -{ - struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary); - - return armada_drm_plane_work_queue(dcrtc, plane, &work->work); -} - static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, - struct armada_plane *plane, struct armada_plane_work *work) + struct armada_plane_work *work) { struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work); struct drm_device *dev = dcrtc->crtc.dev; @@ -293,7 +286,8 @@ static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, kfree(fwork); } -static struct armada_frame_work *armada_drm_crtc_alloc_frame_work(void) +static struct armada_frame_work * +armada_drm_crtc_alloc_frame_work(struct drm_plane *plane) { struct armada_frame_work *work; int i = 0; @@ -302,6 +296,7 @@ static struct armada_frame_work *armada_drm_crtc_alloc_frame_work(void) if (!work) return NULL; + work->work.plane = plane; work->work.fn = armada_drm_crtc_complete_frame_work; armada_reg_queue_end(work->regs, i); @@ -322,11 +317,11 @@ static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, return; } - work = armada_drm_crtc_alloc_frame_work(); + work = armada_drm_crtc_alloc_frame_work(dcrtc->crtc.primary); if (work) { work->old_fb = fb; - if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0) + if (armada_drm_plane_work_queue(dcrtc, work) == 0) return; kfree(work); @@ -1044,7 +1039,7 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, if (fb->format != crtc->primary->fb->format) return -EINVAL; - work = armada_drm_crtc_alloc_frame_work(); + work = armada_drm_crtc_alloc_frame_work(dcrtc->crtc.primary); if (!work) return -ENOMEM; @@ -1061,7 +1056,7 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, */ drm_framebuffer_get(fb); - ret = armada_drm_crtc_queue_frame_work(dcrtc, work); + ret = armada_drm_plane_work_queue(dcrtc, work); if (ret) { /* Undo our reference above */ drm_framebuffer_put(fb); diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index a054527eb962..821c0dd21e45 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -36,9 +36,8 @@ struct armada_plane; struct armada_variant; struct armada_plane_work { - void (*fn)(struct armada_crtc *, - struct armada_plane *, - struct armada_plane_work *); + void (*fn)(struct armada_crtc *, struct armada_plane_work *); + struct drm_plane *plane; }; struct armada_plane_state { @@ -60,7 +59,7 @@ struct armada_plane { int armada_drm_plane_init(struct armada_plane *plane); int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, - struct armada_plane *plane, struct armada_plane_work *work); + struct armada_plane_work *work); int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout); void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc, struct armada_plane *plane); diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index aba947696178..1fa8ea8cb2de 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -80,11 +80,12 @@ static void armada_ovl_retire_fb(struct armada_ovl_plane *dplane, /* === Plane support === */ static void armada_ovl_plane_work(struct armada_crtc *dcrtc, - struct armada_plane *plane, struct armada_plane_work *work) + struct armada_plane_work *work) { - struct armada_ovl_plane *dplane = container_of(plane, struct armada_ovl_plane, base); + struct armada_ovl_plane *dplane = container_of(work->plane, + struct armada_ovl_plane, base.base); - trace_armada_ovl_plane_work(&dcrtc->crtc, &plane->base); + trace_armada_ovl_plane_work(&dcrtc->crtc, work->plane); armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs); armada_ovl_retire_fb(dplane, NULL); @@ -252,8 +253,8 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, } if (idx) { armada_reg_queue_end(dplane->vbl.regs, idx); - armada_drm_plane_work_queue(dcrtc, &dplane->base, - &dplane->vbl.work); + /* Queue it for update on the next interrupt if we are enabled */ + armada_drm_plane_work_queue(dcrtc, &dplane->vbl.work); } return 0; } @@ -454,6 +455,7 @@ int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) return ret; } + dplane->vbl.work.plane = &dplane->base.base; dplane->vbl.work.fn = armada_ovl_plane_work; ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs, -- GitLab From 2839d45c7d92a521364347dbd023d218a5913e26 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 7 Jul 2017 15:56:20 +0100 Subject: [PATCH 1094/2547] drm/armada: add work cancel callback Add a work cancel callback, so that work items can add functionality to clean themselves up when they are cancelled. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 23 ++++++++++++++++------- drivers/gpu/drm/armada/armada_crtc.h | 1 + 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 4d3db441466e..f10ab0275ce7 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -216,6 +216,19 @@ static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb, return i; } +static void armada_drm_plane_work_call(struct armada_crtc *dcrtc, + struct armada_plane_work *work, + void (*fn)(struct armada_crtc *, struct armada_plane_work *)) +{ + struct armada_plane *dplane = drm_to_armada_plane(work->plane); + + if (fn) + fn(dcrtc, work); + drm_crtc_vblank_put(&dcrtc->crtc); + + wake_up(&dplane->frame_wait); +} + static void armada_drm_plane_work_run(struct armada_crtc *dcrtc, struct drm_plane *plane) { @@ -223,12 +236,8 @@ static void armada_drm_plane_work_run(struct armada_crtc *dcrtc, struct armada_plane_work *work = xchg(&dplane->work, NULL); /* Handle any pending frame work. */ - if (work) { - work->fn(dcrtc, work); - drm_crtc_vblank_put(&dcrtc->crtc); - } - - wake_up(&dplane->frame_wait); + if (work) + armada_drm_plane_work_call(dcrtc, work, work->fn); } int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, @@ -261,7 +270,7 @@ void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc, struct armada_plane_work *work = xchg(&dplane->work, NULL); if (work) - drm_crtc_vblank_put(&dcrtc->crtc); + armada_drm_plane_work_call(dcrtc, work, work->cancel); } static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index 821c0dd21e45..c26814c2ce08 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -37,6 +37,7 @@ struct armada_variant; struct armada_plane_work { void (*fn)(struct armada_crtc *, struct armada_plane_work *); + void (*cancel)(struct armada_crtc *, struct armada_plane_work *); struct drm_plane *plane; }; -- GitLab From 65724a19438ce50a7cf85bc2d3172ea237ab05de Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 7 Jul 2017 15:56:24 +0100 Subject: [PATCH 1095/2547] drm/armada: wait and cancel any pending frame work at disable Wait for a second, and if we time out, cancel any pending work when disabling the primary plane. This ensures that any pending work is completed or cleaned up prior to the disable taking effect. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 28 +++++++++++++++++++------ drivers/gpu/drm/armada/armada_overlay.c | 2 -- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index f10ab0275ce7..328f030ffbdc 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -273,18 +273,15 @@ void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc, armada_drm_plane_work_call(dcrtc, work, work->cancel); } -static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, +static void armada_drm_crtc_finish_frame_work(struct armada_crtc *dcrtc, struct armada_plane_work *work) { struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work); - struct drm_device *dev = dcrtc->crtc.dev; unsigned long flags; - spin_lock_irqsave(&dcrtc->irq_lock, flags); - armada_drm_crtc_update_regs(dcrtc, fwork->regs); - spin_unlock_irqrestore(&dcrtc->irq_lock, flags); - if (fwork->event) { + struct drm_device *dev = dcrtc->crtc.dev; + spin_lock_irqsave(&dev->event_lock, flags); drm_crtc_send_vblank_event(&dcrtc->crtc, fwork->event); spin_unlock_irqrestore(&dev->event_lock, flags); @@ -295,6 +292,19 @@ static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, kfree(fwork); } +static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, + struct armada_plane_work *work) +{ + struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work); + unsigned long flags; + + spin_lock_irqsave(&dcrtc->irq_lock, flags); + armada_drm_crtc_update_regs(dcrtc, fwork->regs); + spin_unlock_irqrestore(&dcrtc->irq_lock, flags); + + armada_drm_crtc_finish_frame_work(dcrtc, work); +} + static struct armada_frame_work * armada_drm_crtc_alloc_frame_work(struct drm_plane *plane) { @@ -307,6 +317,7 @@ armada_drm_crtc_alloc_frame_work(struct drm_plane *plane) work->work.plane = plane; work->work.fn = armada_drm_crtc_complete_frame_work; + work->work.cancel = armada_drm_crtc_finish_frame_work; armada_reg_queue_end(work->regs, i); return work; @@ -752,6 +763,7 @@ static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, struct drm_plane *plane) { + struct armada_plane *dplane = drm_to_armada_plane(plane); u32 sram_para1, dma_ctrl0_mask; /* @@ -775,6 +787,10 @@ void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, dma_ctrl0_mask = CFG_DMA_ENA; } + /* Wait for any preceding work to complete, but don't wedge */ + if (WARN_ON(!armada_drm_plane_work_wait(dplane, HZ))) + armada_drm_plane_work_cancel(dcrtc, dplane); + spin_lock_irq(&dcrtc->irq_lock); armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0); spin_unlock_irq(&dcrtc->irq_lock); diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 1fa8ea8cb2de..cf8442583bfc 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -270,8 +270,6 @@ static int armada_ovl_plane_disable(struct drm_plane *plane, return 0; dcrtc = drm_to_armada_crtc(dplane->base.base.crtc); - - armada_drm_plane_work_cancel(dcrtc, &dplane->base); armada_drm_crtc_plane_disable(dcrtc, plane); dcrtc->plane = NULL; -- GitLab From 28b304339900027988ace06bcbda8cd4c6a67883 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:16:40 +0100 Subject: [PATCH 1096/2547] drm/armada: allow the primary plane to be disabled Add our own hook to allow the primary plane to be disabled. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 99 +++++++++++++++------------- 1 file changed, 55 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 328f030ffbdc..7f7f21166488 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -341,7 +341,7 @@ static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, if (work) { work->old_fb = fb; - if (armada_drm_plane_work_queue(dcrtc, work) == 0) + if (armada_drm_plane_work_queue(dcrtc, &work->work) == 0) return; kfree(work); @@ -760,51 +760,13 @@ static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, return 0; } -void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, - struct drm_plane *plane) -{ - struct armada_plane *dplane = drm_to_armada_plane(plane); - u32 sram_para1, dma_ctrl0_mask; - - /* - * Drop our reference on any framebuffer attached to this plane. - * We don't need to NULL this out as drm_plane_force_disable(), - * and __setplane_internal() will do so for an overlay plane, and - * __drm_helper_disable_unused_functions() will do so for the - * primary plane. - */ - if (plane->fb) - drm_framebuffer_put(plane->fb); - - /* Power down most RAMs and FIFOs if this is the primary plane */ - if (plane->type == DRM_PLANE_TYPE_PRIMARY) { - sram_para1 = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | - CFG_PDWN32x32 | CFG_PDWN64x66; - dma_ctrl0_mask = CFG_GRA_ENA; - } else { - /* Power down the Y/U/V FIFOs */ - sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66; - dma_ctrl0_mask = CFG_DMA_ENA; - } - - /* Wait for any preceding work to complete, but don't wedge */ - if (WARN_ON(!armada_drm_plane_work_wait(dplane, HZ))) - armada_drm_plane_work_cancel(dcrtc, dplane); - - spin_lock_irq(&dcrtc->irq_lock); - armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0); - spin_unlock_irq(&dcrtc->irq_lock); - - armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1); -} - /* The mode_config.mutex will be held for this call */ static void armada_drm_crtc_disable(struct drm_crtc *crtc) { - struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); - armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); - armada_drm_crtc_plane_disable(dcrtc, crtc->primary); + + /* Disable our primary plane when we disable the CRTC. */ + crtc->primary->funcs->disable_plane(crtc->primary, NULL); } static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = { @@ -1081,7 +1043,7 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, */ drm_framebuffer_get(fb); - ret = armada_drm_plane_work_queue(dcrtc, work); + ret = armada_drm_plane_work_queue(dcrtc, &work->work); if (ret) { /* Undo our reference above */ drm_framebuffer_put(fb); @@ -1161,9 +1123,58 @@ static const struct drm_crtc_funcs armada_crtc_funcs = { .disable_vblank = armada_drm_crtc_disable_vblank, }; +void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, + struct drm_plane *plane) +{ + struct armada_plane *dplane = drm_to_armada_plane(plane); + u32 sram_para1, dma_ctrl0_mask; + + /* + * Drop our reference on any framebuffer attached to this plane. + * We don't need to NULL this out as drm_plane_force_disable(), + * and __setplane_internal() will do so for an overlay plane, and + * __drm_helper_disable_unused_functions() will do so for the + * primary plane. + */ + if (plane->fb) + drm_framebuffer_put(plane->fb); + + /* Power down most RAMs and FIFOs if this is the primary plane */ + if (plane->type == DRM_PLANE_TYPE_PRIMARY) { + sram_para1 = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | + CFG_PDWN32x32 | CFG_PDWN64x66; + dma_ctrl0_mask = CFG_GRA_ENA; + } else { + /* Power down the Y/U/V FIFOs */ + sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66; + dma_ctrl0_mask = CFG_DMA_ENA; + } + + /* Wait for any preceding work to complete, but don't wedge */ + if (WARN_ON(!armada_drm_plane_work_wait(dplane, HZ))) + armada_drm_plane_work_cancel(dcrtc, dplane); + + spin_lock_irq(&dcrtc->irq_lock); + armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0); + spin_unlock_irq(&dcrtc->irq_lock); + + armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1); +} + +static int armada_drm_primary_disable(struct drm_plane *plane, + struct drm_modeset_acquire_ctx *ctx) +{ + if (plane->crtc) { + struct armada_crtc *dcrtc = drm_to_armada_crtc(plane->crtc); + + armada_drm_crtc_plane_disable(dcrtc, plane); + } + return 0; +} + static const struct drm_plane_funcs armada_primary_plane_funcs = { .update_plane = drm_primary_helper_update, - .disable_plane = drm_primary_helper_disable, + .disable_plane = armada_drm_primary_disable, .destroy = drm_primary_helper_destroy, }; -- GitLab From f1f1bffcf01478883f92b69870fd29a4aae6fd64 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:16:42 +0100 Subject: [PATCH 1097/2547] drm/armada: clean up armada_drm_crtc_plane_disable() Merge armada_drm_primary_disable() into armada_drm_crtc_plane_disable() and rename to armada_drm_plane_disable(). Use this to simplify armada_ovl_plane_disable(). Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 21 +++++++++------------ drivers/gpu/drm/armada/armada_crtc.h | 4 ++-- drivers/gpu/drm/armada/armada_overlay.c | 9 +++------ 3 files changed, 14 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 7f7f21166488..3287b72e48cc 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -1123,12 +1123,16 @@ static const struct drm_crtc_funcs armada_crtc_funcs = { .disable_vblank = armada_drm_crtc_disable_vblank, }; -void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, - struct drm_plane *plane) +int armada_drm_plane_disable(struct drm_plane *plane, + struct drm_modeset_acquire_ctx *ctx) { struct armada_plane *dplane = drm_to_armada_plane(plane); + struct armada_crtc *dcrtc; u32 sram_para1, dma_ctrl0_mask; + if (!plane->crtc) + return 0; + /* * Drop our reference on any framebuffer attached to this plane. * We don't need to NULL this out as drm_plane_force_disable(), @@ -1150,6 +1154,8 @@ void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, dma_ctrl0_mask = CFG_DMA_ENA; } + dcrtc = drm_to_armada_crtc(plane->crtc); + /* Wait for any preceding work to complete, but don't wedge */ if (WARN_ON(!armada_drm_plane_work_wait(dplane, HZ))) armada_drm_plane_work_cancel(dcrtc, dplane); @@ -1159,22 +1165,13 @@ void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, spin_unlock_irq(&dcrtc->irq_lock); armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1); -} - -static int armada_drm_primary_disable(struct drm_plane *plane, - struct drm_modeset_acquire_ctx *ctx) -{ - if (plane->crtc) { - struct armada_crtc *dcrtc = drm_to_armada_crtc(plane->crtc); - armada_drm_crtc_plane_disable(dcrtc, plane); - } return 0; } static const struct drm_plane_funcs armada_primary_plane_funcs = { .update_plane = drm_primary_helper_update, - .disable_plane = armada_drm_primary_disable, + .disable_plane = armada_drm_plane_disable, .destroy = drm_primary_helper_destroy, }; diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index c26814c2ce08..521ae5b6ad86 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -106,8 +106,8 @@ struct armada_crtc { void armada_drm_crtc_update_regs(struct armada_crtc *, struct armada_regs *); -void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, - struct drm_plane *plane); +int armada_drm_plane_disable(struct drm_plane *plane, + struct drm_modeset_acquire_ctx *ctx); extern struct platform_driver armada_lcd_platform_driver; diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index cf8442583bfc..a53e7dd26b0b 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -264,15 +264,12 @@ static int armada_ovl_plane_disable(struct drm_plane *plane, { struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); struct drm_framebuffer *fb; - struct armada_crtc *dcrtc; - if (!dplane->base.base.crtc) - return 0; + armada_drm_plane_disable(plane, ctx); - dcrtc = drm_to_armada_crtc(dplane->base.base.crtc); - armada_drm_crtc_plane_disable(dcrtc, plane); + if (dplane->base.base.crtc) + drm_to_armada_crtc(dplane->base.base.crtc)->plane = NULL; - dcrtc->plane = NULL; dplane->base.state.ctrl0 = 0; fb = xchg(&dplane->old_fb, NULL); -- GitLab From d76dcc7236b8b1b8c2c61b380e7d803d47b20ffa Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:16:47 +0100 Subject: [PATCH 1098/2547] drm/armada: clear plane enable bit when disabling Clear the plane enable bit in the software state within armada_drm_plane_disable() when disabling either the primary or overlay planes. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 10 ++++++---- drivers/gpu/drm/armada/armada_overlay.c | 2 -- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 3287b72e48cc..bedcaed81ffa 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -1128,7 +1128,7 @@ int armada_drm_plane_disable(struct drm_plane *plane, { struct armada_plane *dplane = drm_to_armada_plane(plane); struct armada_crtc *dcrtc; - u32 sram_para1, dma_ctrl0_mask; + u32 sram_para1, enable_mask; if (!plane->crtc) return 0; @@ -1147,13 +1147,15 @@ int armada_drm_plane_disable(struct drm_plane *plane, if (plane->type == DRM_PLANE_TYPE_PRIMARY) { sram_para1 = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | CFG_PDWN32x32 | CFG_PDWN64x66; - dma_ctrl0_mask = CFG_GRA_ENA; + enable_mask = CFG_GRA_ENA; } else { /* Power down the Y/U/V FIFOs */ sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66; - dma_ctrl0_mask = CFG_DMA_ENA; + enable_mask = CFG_DMA_ENA; } + dplane->state.ctrl0 &= ~enable_mask; + dcrtc = drm_to_armada_crtc(plane->crtc); /* Wait for any preceding work to complete, but don't wedge */ @@ -1161,7 +1163,7 @@ int armada_drm_plane_disable(struct drm_plane *plane, armada_drm_plane_work_cancel(dcrtc, dplane); spin_lock_irq(&dcrtc->irq_lock); - armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0); + armada_updatel(0, enable_mask, dcrtc->base + LCD_SPU_DMA_CTRL0); spin_unlock_irq(&dcrtc->irq_lock); armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1); diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index a53e7dd26b0b..995463cd542d 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -270,8 +270,6 @@ static int armada_ovl_plane_disable(struct drm_plane *plane, if (dplane->base.base.crtc) drm_to_armada_crtc(dplane->base.base.crtc)->plane = NULL; - dplane->base.state.ctrl0 = 0; - fb = xchg(&dplane->old_fb, NULL); if (fb) drm_framebuffer_put(fb); -- GitLab From a3f6a18f9a74b64209f8ab957dd94ade8bf5a7b2 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:16:48 +0100 Subject: [PATCH 1099/2547] drm/armada: move overlay plane work out from under spinlock Move the overlay plane work out from under the spinlock so that both the primary and overlay planes run their work in the same context. This is necessary so that we can use frame works with the overlay plane. However, we must update the CRTC registers under the spinlock, so fix up the overlay code for that. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 2 +- drivers/gpu/drm/armada/armada_overlay.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index bedcaed81ffa..be3fd82ef516 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -471,11 +471,11 @@ static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) if (stat & VSYNC_IRQ) drm_crtc_handle_vblank(&dcrtc->crtc); - spin_lock(&dcrtc->irq_lock); ovl_plane = dcrtc->plane; if (ovl_plane) armada_drm_plane_work_run(dcrtc, ovl_plane); + spin_lock(&dcrtc->irq_lock); if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { int i = stat & GRA_FRAME_IRQ0 ? 0 : 1; uint32_t val; diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 995463cd542d..04746ade74e6 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -84,10 +84,14 @@ static void armada_ovl_plane_work(struct armada_crtc *dcrtc, { struct armada_ovl_plane *dplane = container_of(work->plane, struct armada_ovl_plane, base.base); + unsigned long flags; trace_armada_ovl_plane_work(&dcrtc->crtc, work->plane); + spin_lock_irqsave(&dcrtc->irq_lock, flags); armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs); + spin_unlock_irqrestore(&dcrtc->irq_lock, flags); + armada_ovl_retire_fb(dplane, NULL); } -- GitLab From b972a80f447da0b69648c33c719fe3089a17dacc Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:16:52 +0100 Subject: [PATCH 1100/2547] drm/armada: move fb retirement into armada_plane_work Both the primary and overlay planes retire framebuffers in a similar manner; this can be consolidated by moving the retirement up to the armada_plane_work layer. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 12 +++++----- drivers/gpu/drm/armada/armada_crtc.h | 1 + drivers/gpu/drm/armada/armada_overlay.c | 30 +++++-------------------- 3 files changed, 13 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index be3fd82ef516..d1f4171966cc 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -24,7 +24,6 @@ struct armada_frame_work { struct armada_plane_work work; struct drm_pending_vblank_event *event; struct armada_regs regs[4]; - struct drm_framebuffer *old_fb; }; enum csc_mode { @@ -221,11 +220,16 @@ static void armada_drm_plane_work_call(struct armada_crtc *dcrtc, void (*fn)(struct armada_crtc *, struct armada_plane_work *)) { struct armada_plane *dplane = drm_to_armada_plane(work->plane); + struct drm_framebuffer *fb = work->old_fb; if (fn) fn(dcrtc, work); drm_crtc_vblank_put(&dcrtc->crtc); + /* Finally, queue the process-half of the cleanup. */ + if (fb) + armada_drm_queue_unref_work(dcrtc->crtc.dev, fb); + wake_up(&dplane->frame_wait); } @@ -287,8 +291,6 @@ static void armada_drm_crtc_finish_frame_work(struct armada_crtc *dcrtc, spin_unlock_irqrestore(&dev->event_lock, flags); } - /* Finally, queue the process-half of the cleanup. */ - __armada_drm_queue_unref_work(dcrtc->crtc.dev, fwork->old_fb); kfree(fwork); } @@ -339,7 +341,7 @@ static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, work = armada_drm_crtc_alloc_frame_work(dcrtc->crtc.primary); if (work) { - work->old_fb = fb; + work->work.old_fb = fb; if (armada_drm_plane_work_queue(dcrtc, &work->work) == 0) return; @@ -1031,7 +1033,7 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, return -ENOMEM; work->event = event; - work->old_fb = dcrtc->crtc.primary->fb; + work->work.old_fb = dcrtc->crtc.primary->fb; i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs, dcrtc->interlaced); diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index 521ae5b6ad86..b40db72c61d8 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -39,6 +39,7 @@ struct armada_plane_work { void (*fn)(struct armada_crtc *, struct armada_plane_work *); void (*cancel)(struct armada_crtc *, struct armada_plane_work *); struct drm_plane *plane; + struct drm_framebuffer *old_fb; }; struct armada_plane_state { diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 04746ade74e6..01087c952916 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -32,7 +32,6 @@ struct armada_ovl_plane_properties { struct armada_ovl_plane { struct armada_plane base; - struct drm_framebuffer *old_fb; struct { struct armada_plane_work work; struct armada_regs regs[13]; @@ -67,17 +66,6 @@ armada_ovl_update_attr(struct armada_ovl_plane_properties *prop, spin_unlock_irq(&dcrtc->irq_lock); } -static void armada_ovl_retire_fb(struct armada_ovl_plane *dplane, - struct drm_framebuffer *fb) -{ - struct drm_framebuffer *old_fb; - - old_fb = xchg(&dplane->old_fb, fb); - - if (old_fb) - armada_drm_queue_unref_work(dplane->base.base.dev, old_fb); -} - /* === Plane support === */ static void armada_ovl_plane_work(struct armada_crtc *dcrtc, struct armada_plane_work *work) @@ -91,8 +79,6 @@ static void armada_ovl_plane_work(struct armada_crtc *dcrtc, spin_lock_irqsave(&dcrtc->irq_lock, flags); armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs); spin_unlock_irqrestore(&dcrtc->irq_lock, flags); - - armada_ovl_retire_fb(dplane, NULL); } static int @@ -196,8 +182,7 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, */ drm_framebuffer_get(fb); - if (plane->fb) - armada_ovl_retire_fb(dplane, plane->fb); + dplane->vbl.work.old_fb = plane->fb; dplane->base.state.src_y = src_y = src.y1 >> 16; dplane->base.state.src_x = src_x = src.x1 >> 16; @@ -223,6 +208,8 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, val = fb->pitches[1] << 16 | fb->pitches[2]; armada_reg_queue_set(dplane->vbl.regs, idx, val, LCD_SPU_DMA_PITCH_UV); + } else { + dplane->vbl.work.old_fb = NULL; } val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16; @@ -266,17 +253,10 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, static int armada_ovl_plane_disable(struct drm_plane *plane, struct drm_modeset_acquire_ctx *ctx) { - struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); - struct drm_framebuffer *fb; - armada_drm_plane_disable(plane, ctx); - if (dplane->base.base.crtc) - drm_to_armada_crtc(dplane->base.base.crtc)->plane = NULL; - - fb = xchg(&dplane->old_fb, NULL); - if (fb) - drm_framebuffer_put(fb); + if (plane->crtc) + drm_to_armada_crtc(plane->crtc)->plane = NULL; return 0; } -- GitLab From eb19be5bbe2aaf84cb347ca2a07ec19f2b92594f Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:16:53 +0100 Subject: [PATCH 1101/2547] drm/armada: move event sending into armada_plane_work Move the sending of events into the armada_plane_work structure, and combine the processing in armada_drm_plane_work_call(). Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 27 +++++++++++++-------------- drivers/gpu/drm/armada/armada_crtc.h | 1 + 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index d1f4171966cc..b043766c416c 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -22,7 +22,6 @@ struct armada_frame_work { struct armada_plane_work work; - struct drm_pending_vblank_event *event; struct armada_regs regs[4]; }; @@ -220,15 +219,24 @@ static void armada_drm_plane_work_call(struct armada_crtc *dcrtc, void (*fn)(struct armada_crtc *, struct armada_plane_work *)) { struct armada_plane *dplane = drm_to_armada_plane(work->plane); + struct drm_pending_vblank_event *event = work->event; struct drm_framebuffer *fb = work->old_fb; if (fn) fn(dcrtc, work); drm_crtc_vblank_put(&dcrtc->crtc); - /* Finally, queue the process-half of the cleanup. */ - if (fb) - armada_drm_queue_unref_work(dcrtc->crtc.dev, fb); + if (event || fb) { + struct drm_device *dev = dcrtc->crtc.dev; + unsigned long flags; + + spin_lock_irqsave(&dev->event_lock, flags); + if (event) + drm_crtc_send_vblank_event(&dcrtc->crtc, event); + if (fb) + __armada_drm_queue_unref_work(dev, fb); + spin_unlock_irqrestore(&dev->event_lock, flags); + } wake_up(&dplane->frame_wait); } @@ -281,15 +289,6 @@ static void armada_drm_crtc_finish_frame_work(struct armada_crtc *dcrtc, struct armada_plane_work *work) { struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work); - unsigned long flags; - - if (fwork->event) { - struct drm_device *dev = dcrtc->crtc.dev; - - spin_lock_irqsave(&dev->event_lock, flags); - drm_crtc_send_vblank_event(&dcrtc->crtc, fwork->event); - spin_unlock_irqrestore(&dev->event_lock, flags); - } kfree(fwork); } @@ -1032,7 +1031,7 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, if (!work) return -ENOMEM; - work->event = event; + work->work.event = event; work->work.old_fb = dcrtc->crtc.primary->fb; i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs, diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index b40db72c61d8..4cdd2f0eabd9 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -40,6 +40,7 @@ struct armada_plane_work { void (*cancel)(struct armada_crtc *, struct armada_plane_work *); struct drm_plane *plane; struct drm_framebuffer *old_fb; + struct drm_pending_vblank_event *event; }; struct armada_plane_state { -- GitLab From eaa66279c3dd65cafede289d2485185fb389b050 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:10 +0100 Subject: [PATCH 1102/2547] drm/armada: move regs into armada_plane_work Move the register update structure out of the overlay private structure into armada_plane_work, as this is common to both the primary and overlay planes. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 42 +++++++++------------- drivers/gpu/drm/armada/armada_crtc.h | 1 + drivers/gpu/drm/armada/armada_overlay.c | 46 +++++++++++-------------- 3 files changed, 39 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index b043766c416c..02eefdc6f062 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -20,11 +20,6 @@ #include "armada_hw.h" #include "armada_trace.h" -struct armada_frame_work { - struct armada_plane_work work; - struct armada_regs regs[4]; -}; - enum csc_mode { CSC_AUTO = 0, CSC_YUV_CCIR601 = 1, @@ -288,37 +283,34 @@ void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc, static void armada_drm_crtc_finish_frame_work(struct armada_crtc *dcrtc, struct armada_plane_work *work) { - struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work); - - kfree(fwork); + kfree(work); } static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, struct armada_plane_work *work) { - struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work); unsigned long flags; spin_lock_irqsave(&dcrtc->irq_lock, flags); - armada_drm_crtc_update_regs(dcrtc, fwork->regs); + armada_drm_crtc_update_regs(dcrtc, work->regs); spin_unlock_irqrestore(&dcrtc->irq_lock, flags); armada_drm_crtc_finish_frame_work(dcrtc, work); } -static struct armada_frame_work * -armada_drm_crtc_alloc_frame_work(struct drm_plane *plane) +static struct armada_plane_work * +armada_drm_crtc_alloc_plane_work(struct drm_plane *plane) { - struct armada_frame_work *work; + struct armada_plane_work *work; int i = 0; work = kzalloc(sizeof(*work), GFP_KERNEL); if (!work) return NULL; - work->work.plane = plane; - work->work.fn = armada_drm_crtc_complete_frame_work; - work->work.cancel = armada_drm_crtc_finish_frame_work; + work->plane = plane; + work->fn = armada_drm_crtc_complete_frame_work; + work->cancel = armada_drm_crtc_finish_frame_work; armada_reg_queue_end(work->regs, i); return work; @@ -327,7 +319,7 @@ armada_drm_crtc_alloc_frame_work(struct drm_plane *plane) static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, struct drm_framebuffer *fb, bool force) { - struct armada_frame_work *work; + struct armada_plane_work *work; if (!fb) return; @@ -338,11 +330,11 @@ static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, return; } - work = armada_drm_crtc_alloc_frame_work(dcrtc->crtc.primary); + work = armada_drm_crtc_alloc_plane_work(dcrtc->crtc.primary); if (work) { - work->work.old_fb = fb; + work->old_fb = fb; - if (armada_drm_plane_work_queue(dcrtc, &work->work) == 0) + if (armada_drm_plane_work_queue(dcrtc, work) == 0) return; kfree(work); @@ -1019,7 +1011,7 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, struct drm_modeset_acquire_ctx *ctx) { struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); - struct armada_frame_work *work; + struct armada_plane_work *work; unsigned i; int ret; @@ -1027,12 +1019,12 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, if (fb->format != crtc->primary->fb->format) return -EINVAL; - work = armada_drm_crtc_alloc_frame_work(dcrtc->crtc.primary); + work = armada_drm_crtc_alloc_plane_work(dcrtc->crtc.primary); if (!work) return -ENOMEM; - work->work.event = event; - work->work.old_fb = dcrtc->crtc.primary->fb; + work->event = event; + work->old_fb = dcrtc->crtc.primary->fb; i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs, dcrtc->interlaced); @@ -1044,7 +1036,7 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, */ drm_framebuffer_get(fb); - ret = armada_drm_plane_work_queue(dcrtc, &work->work); + ret = armada_drm_plane_work_queue(dcrtc, work); if (ret) { /* Undo our reference above */ drm_framebuffer_put(fb); diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index 4cdd2f0eabd9..12ef9688a45a 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -41,6 +41,7 @@ struct armada_plane_work { struct drm_plane *plane; struct drm_framebuffer *old_fb; struct drm_pending_vblank_event *event; + struct armada_regs regs[14]; }; struct armada_plane_state { diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 01087c952916..200223861bfb 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -32,10 +32,7 @@ struct armada_ovl_plane_properties { struct armada_ovl_plane { struct armada_plane base; - struct { - struct armada_plane_work work; - struct armada_regs regs[13]; - } vbl; + struct armada_plane_work work; struct armada_ovl_plane_properties prop; }; #define drm_to_armada_ovl_plane(p) \ @@ -70,14 +67,12 @@ armada_ovl_update_attr(struct armada_ovl_plane_properties *prop, static void armada_ovl_plane_work(struct armada_crtc *dcrtc, struct armada_plane_work *work) { - struct armada_ovl_plane *dplane = container_of(work->plane, - struct armada_ovl_plane, base.base); unsigned long flags; trace_armada_ovl_plane_work(&dcrtc->crtc, work->plane); spin_lock_irqsave(&dcrtc->irq_lock, flags); - armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs); + armada_drm_crtc_update_regs(dcrtc, work->regs); spin_unlock_irqrestore(&dcrtc->irq_lock, flags); } @@ -90,6 +85,7 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, { struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); + struct armada_plane_work *work = &dplane->work; const struct drm_format_info *format; struct drm_rect src = { .x1 = src_x, @@ -182,60 +178,60 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, */ drm_framebuffer_get(fb); - dplane->vbl.work.old_fb = plane->fb; + work->old_fb = plane->fb; dplane->base.state.src_y = src_y = src.y1 >> 16; dplane->base.state.src_x = src_x = src.x1 >> 16; armada_drm_plane_calc_addrs(addrs, fb, src_x, src_y); - armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0], + armada_reg_queue_set(work->regs, idx, addrs[0], LCD_SPU_DMA_START_ADDR_Y0); - armada_reg_queue_set(dplane->vbl.regs, idx, addrs[1], + armada_reg_queue_set(work->regs, idx, addrs[1], LCD_SPU_DMA_START_ADDR_U0); - armada_reg_queue_set(dplane->vbl.regs, idx, addrs[2], + armada_reg_queue_set(work->regs, idx, addrs[2], LCD_SPU_DMA_START_ADDR_V0); - armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0], + armada_reg_queue_set(work->regs, idx, addrs[0], LCD_SPU_DMA_START_ADDR_Y1); - armada_reg_queue_set(dplane->vbl.regs, idx, addrs[1], + armada_reg_queue_set(work->regs, idx, addrs[1], LCD_SPU_DMA_START_ADDR_U1); - armada_reg_queue_set(dplane->vbl.regs, idx, addrs[2], + armada_reg_queue_set(work->regs, idx, addrs[2], LCD_SPU_DMA_START_ADDR_V1); val = fb->pitches[0] << 16 | fb->pitches[0]; - armada_reg_queue_set(dplane->vbl.regs, idx, val, + armada_reg_queue_set(work->regs, idx, val, LCD_SPU_DMA_PITCH_YC); val = fb->pitches[1] << 16 | fb->pitches[2]; - armada_reg_queue_set(dplane->vbl.regs, idx, val, + armada_reg_queue_set(work->regs, idx, val, LCD_SPU_DMA_PITCH_UV); } else { - dplane->vbl.work.old_fb = NULL; + work->old_fb = NULL; } val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16; if (dplane->base.state.src_hw != val) { dplane->base.state.src_hw = val; - armada_reg_queue_set(dplane->vbl.regs, idx, val, + armada_reg_queue_set(work->regs, idx, val, LCD_SPU_DMA_HPXL_VLN); } val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest); if (dplane->base.state.dst_hw != val) { dplane->base.state.dst_hw = val; - armada_reg_queue_set(dplane->vbl.regs, idx, val, + armada_reg_queue_set(work->regs, idx, val, LCD_SPU_DZM_HPXL_VLN); } val = dest.y1 << 16 | dest.x1; if (dplane->base.state.dst_yx != val) { dplane->base.state.dst_yx = val; - armada_reg_queue_set(dplane->vbl.regs, idx, val, + armada_reg_queue_set(work->regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN); } if (dplane->base.state.ctrl0 != ctrl0) { dplane->base.state.ctrl0 = ctrl0; - armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0, + armada_reg_queue_mod(work->regs, idx, ctrl0, CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE | CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE | CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU | @@ -243,9 +239,9 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, LCD_SPU_DMA_CTRL0); } if (idx) { - armada_reg_queue_end(dplane->vbl.regs, idx); + armada_reg_queue_end(work->regs, idx); /* Queue it for update on the next interrupt if we are enabled */ - armada_drm_plane_work_queue(dcrtc, &dplane->vbl.work); + armada_drm_plane_work_queue(dcrtc, work); } return 0; } @@ -432,8 +428,8 @@ int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) return ret; } - dplane->vbl.work.plane = &dplane->base.base; - dplane->vbl.work.fn = armada_ovl_plane_work; + dplane->work.plane = &dplane->base.base; + dplane->work.fn = armada_ovl_plane_work; ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs, &armada_ovl_plane_funcs, -- GitLab From 214612f9b7ae2395d1b9d1c51d1e994fcd598b2c Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:15 +0100 Subject: [PATCH 1103/2547] drm/armada: move writes of LCD_SPU_SRAM_PARA1 under lock Move writes of LCD_SPU_SRAM_PARA1 under the irq lock, so that we can add this to the frame updates at interrupt time when disabling a plane. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 10 ++++++---- drivers/gpu/drm/armada/armada_overlay.c | 5 +++-- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 02eefdc6f062..b0091142a79f 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -657,8 +657,6 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, /* Now compute the divider for real */ dcrtc->variant->compute_clock(dcrtc, adj, &sclk); - /* Ensure graphic fifo is enabled */ - armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1); armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV); if (interlaced ^ dcrtc->interlaced) { @@ -671,6 +669,9 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, spin_lock_irqsave(&dcrtc->irq_lock, flags); + /* Ensure graphic fifo is enabled */ + armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1); + /* Even interlaced/progressive frame */ dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 | adj->crtc_htotal; @@ -869,9 +870,11 @@ static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload) return 0; } + spin_lock_irq(&dcrtc->irq_lock); para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32, dcrtc->base + LCD_SPU_SRAM_PARA1); + spin_unlock_irq(&dcrtc->irq_lock); /* * Initialize the transparency if the SRAM was powered down. @@ -1157,9 +1160,8 @@ int armada_drm_plane_disable(struct drm_plane *plane, spin_lock_irq(&dcrtc->irq_lock); armada_updatel(0, enable_mask, dcrtc->base + LCD_SPU_DMA_CTRL0); - spin_unlock_irq(&dcrtc->irq_lock); - armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1); + spin_unlock_irq(&dcrtc->irq_lock); return 0; } diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 200223861bfb..e02d0d9d4c23 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -162,8 +162,9 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, return 0; } else if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) { /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */ - armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66, - dcrtc->base + LCD_SPU_SRAM_PARA1); + armada_reg_queue_mod(work->regs, idx, + 0, CFG_PDWN16x66 | CFG_PDWN32x66, + LCD_SPU_SRAM_PARA1); } if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0) -- GitLab From 73c51abd9d9371bc02a8c6717b9758bdee38b20e Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:19 +0100 Subject: [PATCH 1104/2547] drm/armada: only enable HSMOOTH if scaling horizontally Only enable the HSMOOTH control bit if we are scaling horizontally, otherwise it makes no sense to enable the horizontal scaler. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 5 +++-- drivers/gpu/drm/armada/armada_overlay.c | 10 +++++----- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index b0091142a79f..401ad854d751 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -583,7 +583,8 @@ static void armada_drm_primary_set(struct drm_crtc *crtc, armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT | CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU | CFG_YUV2RGB) | - CFG_PALETTE_ENA | CFG_GRA_FTOGGLE, + CFG_PALETTE_ENA | CFG_GRA_FTOGGLE | + CFG_GRA_HSMOOTH | CFG_GRA_ENA, LCD_SPU_DMA_CTRL0); armada_reg_queue_end(regs, i); armada_drm_crtc_update_regs(dcrtc, regs); @@ -605,7 +606,7 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE); - val = CFG_GRA_ENA | CFG_GRA_HSMOOTH; + val = CFG_GRA_ENA; val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt); val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod); diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index e02d0d9d4c23..19fce1a7159f 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -120,11 +120,11 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) | CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) | - CFG_CBSH_ENA | CFG_DMA_HSMOOTH | CFG_DMA_ENA; - - /* Does the position/size result in nothing to display? */ - if (!visible) - ctrl0 &= ~CFG_DMA_ENA; + CFG_CBSH_ENA; + if (visible) + ctrl0 |= CFG_DMA_ENA; + if (drm_rect_width(&src) >> 16 != drm_rect_width(&dest)) + ctrl0 |= CFG_DMA_HSMOOTH; /* * Shifting a YUV packed format image by one pixel causes the U/V -- GitLab From 7bfab1ec45b4005d3f12bbb0cc281f0afd29fc3d Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:20 +0100 Subject: [PATCH 1105/2547] drm/armada: use drm_plane_helper_check_state() Use drm_plane_helper_check_state() to check the overlay plane state rather than drm_plane_helper_check_update(), as: (1) using drm_plane_helper_check_state() provides a better migration path to atomic modeset (2) it avoids needless copies of drm rectangle structures, and so is more efficient. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_overlay.c | 61 +++++++++++++------------ 1 file changed, 32 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 19fce1a7159f..010f3e438607 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -87,17 +87,19 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); struct armada_plane_work *work = &dplane->work; const struct drm_format_info *format; - struct drm_rect src = { - .x1 = src_x, - .y1 = src_y, - .x2 = src_x + src_w, - .y2 = src_y + src_h, - }; - struct drm_rect dest = { - .x1 = crtc_x, - .y1 = crtc_y, - .x2 = crtc_x + crtc_w, - .y2 = crtc_y + crtc_h, + struct drm_plane_state state = { + .plane = plane, + .crtc = crtc, + .fb = fb, + .src_x = src_x, + .src_y = src_y, + .src_w = src_w, + .src_h = src_h, + .crtc_x = crtc_x, + .crtc_y = crtc_y, + .crtc_w = crtc_w, + .crtc_h = crtc_h, + .rotation = DRM_MODE_ROTATE_0, }; const struct drm_rect clip = { .x2 = crtc->mode.hdisplay, @@ -105,25 +107,24 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, }; uint32_t val, ctrl0; unsigned idx = 0; - bool visible, fb_changed; + bool fb_changed; int ret; trace_armada_ovl_plane_update(plane, crtc, fb, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h); - ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip, - DRM_MODE_ROTATE_0, - 0, INT_MAX, true, false, &visible); + ret = drm_plane_helper_check_state(&state, &clip, 0, INT_MAX, true, + false); if (ret) return ret; ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) | CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) | CFG_CBSH_ENA; - if (visible) + if (state.visible) ctrl0 |= CFG_DMA_ENA; - if (drm_rect_width(&src) >> 16 != drm_rect_width(&dest)) + if (drm_rect_width(&state.src) >> 16 != drm_rect_width(&state.dst)) ctrl0 |= CFG_DMA_HSMOOTH; /* @@ -131,12 +132,12 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, * planes to swap. Compensate for it by also toggling the UV swap. */ format = fb->format; - if (format->num_planes == 1 && src.x1 >> 16 & (format->hsub - 1)) + if (format->num_planes == 1 && state.src.x1 >> 16 & (format->hsub - 1)) ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV); fb_changed = plane->fb != fb || - dplane->base.state.src_x != src.x1 >> 16 || - dplane->base.state.src_y != src.y1 >> 16; + dplane->base.state.src_x != state.src.x1 >> 16 || + dplane->base.state.src_y != state.src.y1 >> 16; if (!dcrtc->plane) { dcrtc->plane = plane; @@ -146,16 +147,17 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, /* FIXME: overlay on an interlaced display */ /* Just updating the position/size? */ if (!fb_changed && dplane->base.state.ctrl0 == ctrl0) { - val = (drm_rect_height(&src) & 0xffff0000) | - drm_rect_width(&src) >> 16; + val = (drm_rect_height(&state.src) & 0xffff0000) | + drm_rect_width(&state.src) >> 16; dplane->base.state.src_hw = val; writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN); - val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest); + val = drm_rect_height(&state.dst) << 16 | + drm_rect_width(&state.dst); dplane->base.state.dst_hw = val; writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN); - val = dest.y1 << 16 | dest.x1; + val = state.dst.y1 << 16 | state.dst.x1; dplane->base.state.dst_yx = val; writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN); @@ -181,8 +183,8 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, work->old_fb = plane->fb; - dplane->base.state.src_y = src_y = src.y1 >> 16; - dplane->base.state.src_x = src_x = src.x1 >> 16; + dplane->base.state.src_y = src_y = state.src.y1 >> 16; + dplane->base.state.src_x = src_x = state.src.x1 >> 16; armada_drm_plane_calc_addrs(addrs, fb, src_x, src_y); @@ -209,21 +211,22 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, work->old_fb = NULL; } - val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16; + val = (drm_rect_height(&state.src) & 0xffff0000) | + drm_rect_width(&state.src) >> 16; if (dplane->base.state.src_hw != val) { dplane->base.state.src_hw = val; armada_reg_queue_set(work->regs, idx, val, LCD_SPU_DMA_HPXL_VLN); } - val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest); + val = drm_rect_height(&state.dst) << 16 | drm_rect_width(&state.dst); if (dplane->base.state.dst_hw != val) { dplane->base.state.dst_hw = val; armada_reg_queue_set(work->regs, idx, val, LCD_SPU_DZM_HPXL_VLN); } - val = dest.y1 << 16 | dest.x1; + val = state.dst.y1 << 16 | state.dst.x1; if (dplane->base.state.dst_yx != val) { dplane->base.state.dst_yx = val; armada_reg_queue_set(work->regs, idx, val, -- GitLab From c93dfdcd0521cbdfccab147c5c5a615ba9977a89 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:23 +0100 Subject: [PATCH 1106/2547] drm/armada: allow armada_drm_plane_work_queue() to silently fail Avoid printing an error message when armada_drm_plane_work_queue() is unable to get the vblank (eg, because we're doing a modeset.) Continue to report the failure to the caller, so the caller can handle this. Move the error message into armada_ovl_plane_update(). Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 4 +--- drivers/gpu/drm/armada/armada_overlay.c | 4 +++- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 401ad854d751..2f8e45976444 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -254,10 +254,8 @@ int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, int ret; ret = drm_crtc_vblank_get(&dcrtc->crtc); - if (ret) { - DRM_ERROR("failed to acquire vblank counter\n"); + if (ret) return ret; - } ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0; if (ret) diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 010f3e438607..53edf42c5863 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -245,7 +245,9 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, if (idx) { armada_reg_queue_end(work->regs, idx); /* Queue it for update on the next interrupt if we are enabled */ - armada_drm_plane_work_queue(dcrtc, work); + ret = armada_drm_plane_work_queue(dcrtc, work); + if (ret) + DRM_ERROR("failed to queue plane work: %d\n", ret); } return 0; } -- GitLab From d924155dae5c59fc69be98392306970510768d0b Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:25 +0100 Subject: [PATCH 1107/2547] drm/armada: avoid work allocation Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 24 +++++++++++++----------- drivers/gpu/drm/armada/armada_crtc.h | 3 +++ drivers/gpu/drm/armada/armada_overlay.c | 11 +++++++---- 3 files changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 2f8e45976444..98fb955f6889 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -214,13 +214,15 @@ static void armada_drm_plane_work_call(struct armada_crtc *dcrtc, void (*fn)(struct armada_crtc *, struct armada_plane_work *)) { struct armada_plane *dplane = drm_to_armada_plane(work->plane); - struct drm_pending_vblank_event *event = work->event; - struct drm_framebuffer *fb = work->old_fb; + struct drm_pending_vblank_event *event; + struct drm_framebuffer *fb; if (fn) fn(dcrtc, work); drm_crtc_vblank_put(&dcrtc->crtc); + event = work->event; + fb = work->old_fb; if (event || fb) { struct drm_device *dev = dcrtc->crtc.dev; unsigned long flags; @@ -233,6 +235,9 @@ static void armada_drm_plane_work_call(struct armada_crtc *dcrtc, spin_unlock_irqrestore(&dev->event_lock, flags); } + if (work->need_kfree) + kfree(work); + wake_up(&dplane->frame_wait); } @@ -278,12 +283,6 @@ void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc, armada_drm_plane_work_call(dcrtc, work, work->cancel); } -static void armada_drm_crtc_finish_frame_work(struct armada_crtc *dcrtc, - struct armada_plane_work *work) -{ - kfree(work); -} - static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, struct armada_plane_work *work) { @@ -292,8 +291,6 @@ static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, spin_lock_irqsave(&dcrtc->irq_lock, flags); armada_drm_crtc_update_regs(dcrtc, work->regs); spin_unlock_irqrestore(&dcrtc->irq_lock, flags); - - armada_drm_crtc_finish_frame_work(dcrtc, work); } static struct armada_plane_work * @@ -308,7 +305,7 @@ armada_drm_crtc_alloc_plane_work(struct drm_plane *plane) work->plane = plane; work->fn = armada_drm_crtc_complete_frame_work; - work->cancel = armada_drm_crtc_finish_frame_work; + work->need_kfree = true; armada_reg_queue_end(work->regs, i); return work; @@ -1173,6 +1170,11 @@ static const struct drm_plane_funcs armada_primary_plane_funcs = { int armada_drm_plane_init(struct armada_plane *plane) { + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(plane->works); i++) + plane->works[i].plane = &plane->base; + init_waitqueue_head(&plane->frame_wait); return 0; diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index 12ef9688a45a..0c7b519c09e8 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -38,6 +38,7 @@ struct armada_variant; struct armada_plane_work { void (*fn)(struct armada_crtc *, struct armada_plane_work *); void (*cancel)(struct armada_crtc *, struct armada_plane_work *); + bool need_kfree; struct drm_plane *plane; struct drm_framebuffer *old_fb; struct drm_pending_vblank_event *event; @@ -56,6 +57,8 @@ struct armada_plane_state { struct armada_plane { struct drm_plane base; wait_queue_head_t frame_wait; + bool next_work; + struct armada_plane_work works[2]; struct armada_plane_work *work; struct armada_plane_state state; }; diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 53edf42c5863..bad966ae6758 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -32,7 +32,6 @@ struct armada_ovl_plane_properties { struct armada_ovl_plane { struct armada_plane base; - struct armada_plane_work work; struct armada_ovl_plane_properties prop; }; #define drm_to_armada_ovl_plane(p) \ @@ -85,7 +84,7 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, { struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); - struct armada_plane_work *work = &dplane->work; + struct armada_plane_work *work; const struct drm_format_info *format; struct drm_plane_state state = { .plane = plane, @@ -119,6 +118,8 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, if (ret) return ret; + work = &dplane->base.works[dplane->base.next_work]; + ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) | CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) | CFG_CBSH_ENA; @@ -248,6 +249,8 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, ret = armada_drm_plane_work_queue(dcrtc, work); if (ret) DRM_ERROR("failed to queue plane work: %d\n", ret); + + dplane->base.next_work = !dplane->base.next_work; } return 0; } @@ -434,8 +437,8 @@ int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) return ret; } - dplane->work.plane = &dplane->base.base; - dplane->work.fn = armada_ovl_plane_work; + dplane->base.works[0].fn = armada_ovl_plane_work; + dplane->base.works[1].fn = armada_ovl_plane_work; ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs, &armada_ovl_plane_funcs, -- GitLab From 890ca8df5a75b3bfdab86bec03aa60cff90a573e Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:27 +0100 Subject: [PATCH 1108/2547] drm/armada: disable planes at next blanking period Disable planes at the next blanking period rather than immediately. In order to achieve this, we need to delay the clearing of dcrtc->plane until after the next blanking period, so move that into a separate work function. To avoid races, we also need to move its assignment in the overlay code. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 59 ++++++++++++++++++------- drivers/gpu/drm/armada/armada_overlay.c | 23 +++------- 2 files changed, 50 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 98fb955f6889..c38a1409a14e 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -293,6 +293,19 @@ static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, spin_unlock_irqrestore(&dcrtc->irq_lock, flags); } +static void armada_drm_crtc_complete_disable_work(struct armada_crtc *dcrtc, + struct armada_plane_work *work) +{ + unsigned long flags; + + if (dcrtc->plane == work->plane) + dcrtc->plane = NULL; + + spin_lock_irqsave(&dcrtc->irq_lock, flags); + armada_drm_crtc_update_regs(dcrtc, work->regs); + spin_unlock_irqrestore(&dcrtc->irq_lock, flags); +} + static struct armada_plane_work * armada_drm_crtc_alloc_plane_work(struct drm_plane *plane) { @@ -392,8 +405,11 @@ static void armada_drm_crtc_prepare(struct drm_crtc *crtc) * the new mode parameters. */ plane = dcrtc->plane; - if (plane) + if (plane) { drm_plane_force_disable(plane); + WARN_ON(!armada_drm_plane_work_wait(drm_to_armada_plane(plane), + HZ)); + } } /* The mode_config.mutex will be held for this call */ @@ -1120,28 +1136,22 @@ int armada_drm_plane_disable(struct drm_plane *plane, { struct armada_plane *dplane = drm_to_armada_plane(plane); struct armada_crtc *dcrtc; + struct armada_plane_work *work; + unsigned int idx = 0; u32 sram_para1, enable_mask; if (!plane->crtc) return 0; /* - * Drop our reference on any framebuffer attached to this plane. - * We don't need to NULL this out as drm_plane_force_disable(), - * and __setplane_internal() will do so for an overlay plane, and - * __drm_helper_disable_unused_functions() will do so for the - * primary plane. + * Arrange to power down most RAMs and FIFOs if this is the primary + * plane, otherwise just the YUV FIFOs for the overlay plane. */ - if (plane->fb) - drm_framebuffer_put(plane->fb); - - /* Power down most RAMs and FIFOs if this is the primary plane */ if (plane->type == DRM_PLANE_TYPE_PRIMARY) { sram_para1 = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | CFG_PDWN32x32 | CFG_PDWN64x66; enable_mask = CFG_GRA_ENA; } else { - /* Power down the Y/U/V FIFOs */ sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66; enable_mask = CFG_DMA_ENA; } @@ -1150,14 +1160,33 @@ int armada_drm_plane_disable(struct drm_plane *plane, dcrtc = drm_to_armada_crtc(plane->crtc); + /* + * Try to disable the plane and drop our ref on the framebuffer + * at the next frame update. If we fail for any reason, disable + * the plane immediately. + */ + work = &dplane->works[dplane->next_work]; + work->fn = armada_drm_crtc_complete_disable_work; + work->cancel = armada_drm_crtc_complete_disable_work; + work->old_fb = plane->fb; + + armada_reg_queue_mod(work->regs, idx, + 0, enable_mask, LCD_SPU_DMA_CTRL0); + armada_reg_queue_mod(work->regs, idx, + sram_para1, 0, LCD_SPU_SRAM_PARA1); + armada_reg_queue_end(work->regs, idx); + /* Wait for any preceding work to complete, but don't wedge */ if (WARN_ON(!armada_drm_plane_work_wait(dplane, HZ))) armada_drm_plane_work_cancel(dcrtc, dplane); - spin_lock_irq(&dcrtc->irq_lock); - armada_updatel(0, enable_mask, dcrtc->base + LCD_SPU_DMA_CTRL0); - armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1); - spin_unlock_irq(&dcrtc->irq_lock); + if (armada_drm_plane_work_queue(dcrtc, work)) { + work->fn(dcrtc, work); + if (work->old_fb) + drm_framebuffer_unreference(work->old_fb); + } + + dplane->next_work = !dplane->next_work; return 0; } diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index bad966ae6758..0fe3f2db8ff5 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -140,11 +140,6 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, dplane->base.state.src_x != state.src.x1 >> 16 || dplane->base.state.src_y != state.src.y1 >> 16; - if (!dcrtc->plane) { - dcrtc->plane = plane; - armada_ovl_update_attr(&dplane->prop, dcrtc); - } - /* FIXME: overlay on an interlaced display */ /* Just updating the position/size? */ if (!fb_changed && dplane->base.state.ctrl0 == ctrl0) { @@ -173,6 +168,11 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0) armada_drm_plane_work_cancel(dcrtc, &dplane->base); + if (!dcrtc->plane) { + dcrtc->plane = plane; + armada_ovl_update_attr(&dplane->prop, dcrtc); + } + if (fb_changed) { u32 addrs[3]; @@ -255,17 +255,6 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, return 0; } -static int armada_ovl_plane_disable(struct drm_plane *plane, - struct drm_modeset_acquire_ctx *ctx) -{ - armada_drm_plane_disable(plane, ctx); - - if (plane->crtc) - drm_to_armada_crtc(plane->crtc)->plane = NULL; - - return 0; -} - static void armada_ovl_plane_destroy(struct drm_plane *plane) { struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); @@ -345,7 +334,7 @@ static int armada_ovl_plane_set_property(struct drm_plane *plane, static const struct drm_plane_funcs armada_ovl_plane_funcs = { .update_plane = armada_ovl_plane_update, - .disable_plane = armada_ovl_plane_disable, + .disable_plane = armada_drm_plane_disable, .destroy = armada_ovl_plane_destroy, .set_property = armada_ovl_plane_set_property, }; -- GitLab From d19f6ee5051be073939b6a013455355711708215 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:31 +0100 Subject: [PATCH 1109/2547] drm/armada: re-organise overlay register update generation Re-organise overlay register generation so that we do not have to wait for the previous update to complete while creating the new state. This allows the update to be fully prepared before queueing it for the next interrupt. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_overlay.c | 52 +++++++++++-------------- 1 file changed, 22 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 0fe3f2db8ff5..00da2c58701c 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -136,43 +136,18 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, if (format->num_planes == 1 && state.src.x1 >> 16 & (format->hsub - 1)) ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV); - fb_changed = plane->fb != fb || - dplane->base.state.src_x != state.src.x1 >> 16 || - dplane->base.state.src_y != state.src.y1 >> 16; - - /* FIXME: overlay on an interlaced display */ - /* Just updating the position/size? */ - if (!fb_changed && dplane->base.state.ctrl0 == ctrl0) { - val = (drm_rect_height(&state.src) & 0xffff0000) | - drm_rect_width(&state.src) >> 16; - dplane->base.state.src_hw = val; - writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN); - - val = drm_rect_height(&state.dst) << 16 | - drm_rect_width(&state.dst); - dplane->base.state.dst_hw = val; - writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN); - - val = state.dst.y1 << 16 | state.dst.x1; - dplane->base.state.dst_yx = val; - writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN); - - return 0; - } else if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) { + if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) { /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */ armada_reg_queue_mod(work->regs, idx, 0, CFG_PDWN16x66 | CFG_PDWN32x66, LCD_SPU_SRAM_PARA1); } - if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0) - armada_drm_plane_work_cancel(dcrtc, &dplane->base); - - if (!dcrtc->plane) { - dcrtc->plane = plane; - armada_ovl_update_attr(&dplane->prop, dcrtc); - } + fb_changed = plane->fb != fb || + dplane->base.state.src_x != state.src.x1 >> 16 || + dplane->base.state.src_y != state.src.y1 >> 16; + /* FIXME: overlay on an interlaced display */ if (fb_changed) { u32 addrs[3]; @@ -243,6 +218,23 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, CFG_YUV2RGB) | CFG_DMA_ENA, LCD_SPU_DMA_CTRL0); } + + /* Just updating the position/size? */ + if (!fb_changed && dplane->base.state.ctrl0 == ctrl0) { + armada_reg_queue_end(work->regs, idx); + armada_ovl_plane_work(dcrtc, work); + return 0; + } + + /* Wait for pending work to complete */ + if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0) + armada_drm_plane_work_cancel(dcrtc, &dplane->base); + + if (!dcrtc->plane) { + dcrtc->plane = plane; + armada_ovl_update_attr(&dplane->prop, dcrtc); + } + if (idx) { armada_reg_queue_end(work->regs, idx); /* Queue it for update on the next interrupt if we are enabled */ -- GitLab From 65843e9af759eb0d1a0f0ee6dc64b3162793132c Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:33 +0100 Subject: [PATCH 1110/2547] drm/armada: move overlay plane register update generation Move the overlay plane register update generation to a separate function as this is independent of the legacy or atomic update. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.h | 2 + drivers/gpu/drm/armada/armada_overlay.c | 203 +++++++++++++----------- 2 files changed, 112 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index 0c7b519c09e8..445829b8877a 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -52,6 +52,8 @@ struct armada_plane_state { u32 dst_hw; u32 dst_yx; u32 ctrl0; + bool changed; + bool vsync_update; }; struct armada_plane { diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 00da2c58701c..e5fa346f572b 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -75,153 +75,172 @@ static void armada_ovl_plane_work(struct armada_crtc *dcrtc, spin_unlock_irqrestore(&dcrtc->irq_lock, flags); } -static int -armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h, - uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, - struct drm_modeset_acquire_ctx *ctx) +static void armada_ovl_plane_update_state(struct drm_plane_state *state, + struct armada_regs *regs) { - struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); - struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); - struct armada_plane_work *work; + struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(state->plane); + struct armada_framebuffer *dfb = drm_fb_to_armada_fb(state->fb); const struct drm_format_info *format; - struct drm_plane_state state = { - .plane = plane, - .crtc = crtc, - .fb = fb, - .src_x = src_x, - .src_y = src_y, - .src_w = src_w, - .src_h = src_h, - .crtc_x = crtc_x, - .crtc_y = crtc_y, - .crtc_w = crtc_w, - .crtc_h = crtc_h, - .rotation = DRM_MODE_ROTATE_0, - }; - const struct drm_rect clip = { - .x2 = crtc->mode.hdisplay, - .y2 = crtc->mode.vdisplay, - }; - uint32_t val, ctrl0; - unsigned idx = 0; + unsigned int idx = 0; bool fb_changed; - int ret; + u32 val, ctrl0; + u16 src_x, src_y; - trace_armada_ovl_plane_update(plane, crtc, fb, - crtc_x, crtc_y, crtc_w, crtc_h, - src_x, src_y, src_w, src_h); - - ret = drm_plane_helper_check_state(&state, &clip, 0, INT_MAX, true, - false); - if (ret) - return ret; - - work = &dplane->base.works[dplane->base.next_work]; - - ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) | - CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) | - CFG_CBSH_ENA; - if (state.visible) + ctrl0 = CFG_DMA_FMT(dfb->fmt) | CFG_DMA_MOD(dfb->mod) | CFG_CBSH_ENA; + if (state->visible) ctrl0 |= CFG_DMA_ENA; - if (drm_rect_width(&state.src) >> 16 != drm_rect_width(&state.dst)) + if (drm_rect_width(&state->src) >> 16 != drm_rect_width(&state->dst)) ctrl0 |= CFG_DMA_HSMOOTH; /* * Shifting a YUV packed format image by one pixel causes the U/V * planes to swap. Compensate for it by also toggling the UV swap. */ - format = fb->format; - if (format->num_planes == 1 && state.src.x1 >> 16 & (format->hsub - 1)) + format = dfb->fb.format; + if (format->num_planes == 1 && state->src.x1 >> 16 & (format->hsub - 1)) ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV); if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) { /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */ - armada_reg_queue_mod(work->regs, idx, + armada_reg_queue_mod(regs, idx, 0, CFG_PDWN16x66 | CFG_PDWN32x66, LCD_SPU_SRAM_PARA1); } - fb_changed = plane->fb != fb || - dplane->base.state.src_x != state.src.x1 >> 16 || - dplane->base.state.src_y != state.src.y1 >> 16; + fb_changed = dplane->base.base.fb != &dfb->fb || + dplane->base.state.src_x != state->src.x1 >> 16 || + dplane->base.state.src_y != state->src.y1 >> 16; + + dplane->base.state.vsync_update = fb_changed; /* FIXME: overlay on an interlaced display */ if (fb_changed) { u32 addrs[3]; - /* - * Take a reference on the new framebuffer - we want to - * hold on to it while the hardware is displaying it. - */ - drm_framebuffer_get(fb); - - work->old_fb = plane->fb; + dplane->base.state.src_y = src_y = state->src.y1 >> 16; + dplane->base.state.src_x = src_x = state->src.x1 >> 16; - dplane->base.state.src_y = src_y = state.src.y1 >> 16; - dplane->base.state.src_x = src_x = state.src.x1 >> 16; + armada_drm_plane_calc_addrs(addrs, &dfb->fb, src_x, src_y); - armada_drm_plane_calc_addrs(addrs, fb, src_x, src_y); - - armada_reg_queue_set(work->regs, idx, addrs[0], + armada_reg_queue_set(regs, idx, addrs[0], LCD_SPU_DMA_START_ADDR_Y0); - armada_reg_queue_set(work->regs, idx, addrs[1], + armada_reg_queue_set(regs, idx, addrs[1], LCD_SPU_DMA_START_ADDR_U0); - armada_reg_queue_set(work->regs, idx, addrs[2], + armada_reg_queue_set(regs, idx, addrs[2], LCD_SPU_DMA_START_ADDR_V0); - armada_reg_queue_set(work->regs, idx, addrs[0], + armada_reg_queue_set(regs, idx, addrs[0], LCD_SPU_DMA_START_ADDR_Y1); - armada_reg_queue_set(work->regs, idx, addrs[1], + armada_reg_queue_set(regs, idx, addrs[1], LCD_SPU_DMA_START_ADDR_U1); - armada_reg_queue_set(work->regs, idx, addrs[2], + armada_reg_queue_set(regs, idx, addrs[2], LCD_SPU_DMA_START_ADDR_V1); - val = fb->pitches[0] << 16 | fb->pitches[0]; - armada_reg_queue_set(work->regs, idx, val, + val = dfb->fb.pitches[0] << 16 | dfb->fb.pitches[0]; + armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC); - val = fb->pitches[1] << 16 | fb->pitches[2]; - armada_reg_queue_set(work->regs, idx, val, + val = dfb->fb.pitches[1] << 16 | dfb->fb.pitches[2]; + armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV); - } else { - work->old_fb = NULL; } - val = (drm_rect_height(&state.src) & 0xffff0000) | - drm_rect_width(&state.src) >> 16; + val = (drm_rect_height(&state->src) & 0xffff0000) | + drm_rect_width(&state->src) >> 16; if (dplane->base.state.src_hw != val) { dplane->base.state.src_hw = val; - armada_reg_queue_set(work->regs, idx, val, + armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN); } - val = drm_rect_height(&state.dst) << 16 | drm_rect_width(&state.dst); + val = drm_rect_height(&state->dst) << 16 | drm_rect_width(&state->dst); if (dplane->base.state.dst_hw != val) { dplane->base.state.dst_hw = val; - armada_reg_queue_set(work->regs, idx, val, + armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN); } - val = state.dst.y1 << 16 | state.dst.x1; + val = state->dst.y1 << 16 | state->dst.x1; if (dplane->base.state.dst_yx != val) { dplane->base.state.dst_yx = val; - armada_reg_queue_set(work->regs, idx, val, + armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN); } if (dplane->base.state.ctrl0 != ctrl0) { dplane->base.state.ctrl0 = ctrl0; - armada_reg_queue_mod(work->regs, idx, ctrl0, + armada_reg_queue_mod(regs, idx, ctrl0, CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE | CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE | CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU | CFG_YUV2RGB) | CFG_DMA_ENA, LCD_SPU_DMA_CTRL0); + dplane->base.state.vsync_update = true; } + dplane->base.state.changed = idx != 0; + + armada_reg_queue_end(regs, idx); +} + +static int +armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, + struct drm_framebuffer *fb, + int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h, + uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, + struct drm_modeset_acquire_ctx *ctx) +{ + struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); + struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); + struct armada_plane_work *work; + struct drm_plane_state state = { + .plane = plane, + .crtc = crtc, + .fb = fb, + .src_x = src_x, + .src_y = src_y, + .src_w = src_w, + .src_h = src_h, + .crtc_x = crtc_x, + .crtc_y = crtc_y, + .crtc_w = crtc_w, + .crtc_h = crtc_h, + .rotation = DRM_MODE_ROTATE_0, + }; + const struct drm_rect clip = { + .x2 = crtc->mode.hdisplay, + .y2 = crtc->mode.vdisplay, + }; + int ret; + + trace_armada_ovl_plane_update(plane, crtc, fb, + crtc_x, crtc_y, crtc_w, crtc_h, + src_x, src_y, src_w, src_h); + + ret = drm_plane_helper_check_state(&state, &clip, 0, INT_MAX, true, + false); + if (ret) + return ret; + + work = &dplane->base.works[dplane->base.next_work]; + + if (plane->fb != fb) { + /* + * Take a reference on the new framebuffer - we want to + * hold on to it while the hardware is displaying it. + */ + drm_framebuffer_reference(fb); + + work->old_fb = plane->fb; + } else { + work->old_fb = NULL; + } + + armada_ovl_plane_update_state(&state, work->regs); + + if (!dplane->base.state.changed) + return 0; + /* Just updating the position/size? */ - if (!fb_changed && dplane->base.state.ctrl0 == ctrl0) { - armada_reg_queue_end(work->regs, idx); + if (!dplane->base.state.vsync_update) { armada_ovl_plane_work(dcrtc, work); return 0; } @@ -235,15 +254,13 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, armada_ovl_update_attr(&dplane->prop, dcrtc); } - if (idx) { - armada_reg_queue_end(work->regs, idx); - /* Queue it for update on the next interrupt if we are enabled */ - ret = armada_drm_plane_work_queue(dcrtc, work); - if (ret) - DRM_ERROR("failed to queue plane work: %d\n", ret); + /* Queue it for update on the next interrupt if we are enabled */ + ret = armada_drm_plane_work_queue(dcrtc, work); + if (ret) + DRM_ERROR("failed to queue plane work: %d\n", ret); + + dplane->base.next_work = !dplane->base.next_work; - dplane->base.next_work = !dplane->base.next_work; - } return 0; } -- GitLab From 07da3c787a273b6d8478b416a694a740c85bdf72 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:34 +0100 Subject: [PATCH 1111/2547] drm/armada: wait for previous work when moving overlay window We must wait for the previous plane work to complete before moving the overlay window, as it could overwrite our positioning update. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_overlay.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index e5fa346f572b..853f889e84f5 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -239,16 +239,16 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, if (!dplane->base.state.changed) return 0; + /* Wait for pending work to complete */ + if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0) + armada_drm_plane_work_cancel(dcrtc, &dplane->base); + /* Just updating the position/size? */ if (!dplane->base.state.vsync_update) { armada_ovl_plane_work(dcrtc, work); return 0; } - /* Wait for pending work to complete */ - if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0) - armada_drm_plane_work_cancel(dcrtc, &dplane->base); - if (!dcrtc->plane) { dcrtc->plane = plane; armada_ovl_update_attr(&dplane->prop, dcrtc); -- GitLab From 11df53dc5bd832dcc4472bdd5e98ac0d9709e739 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:35 +0100 Subject: [PATCH 1112/2547] drm/armada: extract register generation from armada_drm_primary_set() Extract the register generation from armada_drm_primary_set(), so that it can be re-used. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index c38a1409a14e..9958f2d3d0e8 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -571,18 +571,14 @@ static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc) return val; } -static void armada_drm_primary_set(struct drm_crtc *crtc, - struct drm_plane *plane, int x, int y) +static void armada_drm_gra_plane_regs(struct armada_regs *regs, + struct drm_framebuffer *fb, struct armada_plane_state *state, + int x, int y, bool interlaced) { - struct armada_plane_state *state = &drm_to_armada_plane(plane)->state; - struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); - struct armada_regs regs[8]; - bool interlaced = dcrtc->interlaced; - unsigned i; + unsigned int i; u32 ctrl0; - i = armada_drm_crtc_calc_fb(plane->fb, x, y, regs, interlaced); - + i = armada_drm_crtc_calc_fb(fb, x, y, regs, interlaced); armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN); armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN); armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN); @@ -598,6 +594,17 @@ static void armada_drm_primary_set(struct drm_crtc *crtc, CFG_GRA_HSMOOTH | CFG_GRA_ENA, LCD_SPU_DMA_CTRL0); armada_reg_queue_end(regs, i); +} + +static void armada_drm_primary_set(struct drm_crtc *crtc, + struct drm_plane *plane, int x, int y) +{ + struct armada_plane_state *state = &drm_to_armada_plane(plane)->state; + struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); + struct armada_regs regs[8]; + bool interlaced = dcrtc->interlaced; + + armada_drm_gra_plane_regs(regs, plane->fb, state, x, y, interlaced); armada_drm_crtc_update_regs(dcrtc, regs); } -- GitLab From 950bc137c31294a279fb0cf045e28fdb0a066bcd Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:37 +0100 Subject: [PATCH 1113/2547] drm/armada: implement primary plane update Implement primary plane update without having to go through a modeset to achieve that; the hardware does not require such complexity. This means we treat the primary plane as any other, allowing the format, size, position and scaling to be updated via the normal plane ioctls. This also allows us to seemlessly disable and re-enable the primary plane when (eg) displaying full-frame video without any graphic clipping the overlaid video - which saves wasting memory bandwidth needlessly verifying that the colorkey is indeed filling the entire primary plane. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 118 ++++++++++++++++++++++++++- 1 file changed, 117 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 9958f2d3d0e8..8b66377a4890 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -1138,6 +1138,122 @@ static const struct drm_crtc_funcs armada_crtc_funcs = { .disable_vblank = armada_drm_crtc_disable_vblank, }; +static void armada_drm_primary_update_state(struct drm_plane_state *state, + struct armada_regs *regs) +{ + struct armada_plane *dplane = drm_to_armada_plane(state->plane); + struct armada_crtc *dcrtc = drm_to_armada_crtc(state->crtc); + struct armada_framebuffer *dfb = drm_fb_to_armada_fb(state->fb); + bool was_disabled; + unsigned int idx = 0; + u32 val; + + val = CFG_GRA_FMT(dfb->fmt) | CFG_GRA_MOD(dfb->mod); + if (dfb->fmt > CFG_420) + val |= CFG_PALETTE_ENA; + if (state->visible) + val |= CFG_GRA_ENA; + if (drm_rect_width(&state->src) >> 16 != drm_rect_width(&state->dst)) + val |= CFG_GRA_HSMOOTH; + + was_disabled = !(dplane->state.ctrl0 & CFG_GRA_ENA); + if (was_disabled) + armada_reg_queue_mod(regs, idx, + 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1); + + dplane->state.ctrl0 = val; + dplane->state.src_hw = (drm_rect_height(&state->src) & 0xffff0000) | + drm_rect_width(&state->src) >> 16; + dplane->state.dst_hw = drm_rect_height(&state->dst) << 16 | + drm_rect_width(&state->dst); + dplane->state.dst_yx = state->dst.y1 << 16 | state->dst.x1; + + armada_drm_gra_plane_regs(regs + idx, &dfb->fb, &dplane->state, + state->src.x1 >> 16, state->src.y1 >> 16, + dcrtc->interlaced); + + dplane->state.vsync_update = !was_disabled; + dplane->state.changed = true; +} + +static int armada_drm_primary_update(struct drm_plane *plane, + struct drm_crtc *crtc, struct drm_framebuffer *fb, + int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, + uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, + struct drm_modeset_acquire_ctx *ctx) +{ + struct armada_plane *dplane = drm_to_armada_plane(plane); + struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); + struct armada_plane_work *work; + struct drm_plane_state state = { + .plane = plane, + .crtc = crtc, + .fb = fb, + .src_x = src_x, + .src_y = src_y, + .src_w = src_w, + .src_h = src_h, + .crtc_x = crtc_x, + .crtc_y = crtc_y, + .crtc_w = crtc_w, + .crtc_h = crtc_h, + .rotation = DRM_MODE_ROTATE_0, + }; + const struct drm_rect clip = { + .x2 = crtc->mode.hdisplay, + .y2 = crtc->mode.vdisplay, + }; + int ret; + + ret = drm_plane_helper_check_state(&state, &clip, 0, INT_MAX, true, + false); + if (ret) + return ret; + + work = &dplane->works[dplane->next_work]; + work->fn = armada_drm_crtc_complete_frame_work; + + if (plane->fb != fb) { + /* + * Take a reference on the new framebuffer - we want to + * hold on to it while the hardware is displaying it. + */ + drm_framebuffer_reference(fb); + + work->old_fb = plane->fb; + } else { + work->old_fb = NULL; + } + + armada_drm_primary_update_state(&state, work->regs); + + if (!dplane->state.changed) + return 0; + + /* Wait for pending work to complete */ + if (armada_drm_plane_work_wait(dplane, HZ / 10) == 0) + armada_drm_plane_work_cancel(dcrtc, dplane); + + if (!dplane->state.vsync_update) { + work->fn(dcrtc, work); + if (work->old_fb) + drm_framebuffer_unreference(work->old_fb); + return 0; + } + + /* Queue it for update on the next interrupt if we are enabled */ + ret = armada_drm_plane_work_queue(dcrtc, work); + if (ret) { + work->fn(dcrtc, work); + if (work->old_fb) + drm_framebuffer_unreference(work->old_fb); + } + + dplane->next_work = !dplane->next_work; + + return 0; +} + int armada_drm_plane_disable(struct drm_plane *plane, struct drm_modeset_acquire_ctx *ctx) { @@ -1199,7 +1315,7 @@ int armada_drm_plane_disable(struct drm_plane *plane, } static const struct drm_plane_funcs armada_primary_plane_funcs = { - .update_plane = drm_primary_helper_update, + .update_plane = armada_drm_primary_update, .disable_plane = armada_drm_plane_disable, .destroy = drm_primary_helper_destroy, }; -- GitLab From 27ab688f70b6f6b51da4bf56b1237f7beb64d847 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Jul 2017 10:22:45 +0100 Subject: [PATCH 1114/2547] drm/armada: expand overlay trace entry Add CRTC and source positions to the Armada overlay trace entry. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_trace.h | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_trace.h b/drivers/gpu/drm/armada/armada_trace.h index 8dbfea7a00fe..f03a56bda596 100644 --- a/drivers/gpu/drm/armada/armada_trace.h +++ b/drivers/gpu/drm/armada/armada_trace.h @@ -34,14 +34,34 @@ TRACE_EVENT(armada_ovl_plane_update, __field(struct drm_plane *, plane) __field(struct drm_crtc *, crtc) __field(struct drm_framebuffer *, fb) + __field(int, crtc_x) + __field(int, crtc_y) + __field(unsigned int, crtc_w) + __field(unsigned int, crtc_h) + __field(u32, src_x) + __field(u32, src_y) + __field(u32, src_w) + __field(u32, src_h) ), TP_fast_assign( __entry->plane = plane; __entry->crtc = crtc; __entry->fb = fb; + __entry->crtc_x = crtc_x; + __entry->crtc_y = crtc_y; + __entry->crtc_w = crtc_w; + __entry->crtc_h = crtc_h; + __entry->src_x = src_x; + __entry->src_y = src_y; + __entry->src_w = src_w; + __entry->src_h = src_h; ), - TP_printk("plane %p crtc %p fb %p", - __entry->plane, __entry->crtc, __entry->fb) + TP_printk("plane %p crtc %p fb %p crtc @ (%d,%d, %ux%u) src @ (%u,%u, %ux%u)", + __entry->plane, __entry->crtc, __entry->fb, + __entry->crtc_x, __entry->crtc_y, + __entry->crtc_w, __entry->crtc_h, + __entry->src_x >> 16, __entry->src_y >> 16, + __entry->src_w >> 16, __entry->src_h >> 16) ); TRACE_EVENT(armada_ovl_plane_work, -- GitLab From d4761754b4fb2ef8d9a1e9d121c4bec84e1fe292 Mon Sep 17 00:00:00 2001 From: Yousuk Seung Date: Thu, 7 Dec 2017 13:41:34 -0800 Subject: [PATCH 1115/2547] tcp: invalidate rate samples during SACK reneging Mark tcp_sock during a SACK reneging event and invalidate rate samples while marked. Such rate samples may overestimate bw by including packets that were SACKed before reneging. < ack 6001 win 10000 sack 7001:38001 < ack 7001 win 0 sack 8001:38001 // Reneg detected > seq 7001:8001 // RTO, SACK cleared. < ack 38001 win 10000 In above example the rate sample taken after the last ack will count 7001-38001 as delivered while the actual delivery rate likely could be much lower i.e. 7001-8001. This patch adds a new field tcp_sock.sack_reneg and marks it when we declare SACK reneging and entering TCP_CA_Loss, and unmarks it after the last rate sample was taken before moving back to TCP_CA_Open. This patch also invalidates rate samples taken while tcp_sock.is_sack_reneg is set. Fixes: b9f64820fb22 ("tcp: track data delivery rate for a TCP connection") Signed-off-by: Yousuk Seung Signed-off-by: Neal Cardwell Signed-off-by: Yuchung Cheng Acked-by: Soheil Hassas Yeganeh Acked-by: Eric Dumazet Acked-by: Priyaranjan Jha Signed-off-by: David S. Miller --- include/linux/tcp.h | 3 ++- include/net/tcp.h | 2 +- net/ipv4/tcp.c | 1 + net/ipv4/tcp_input.c | 10 ++++++++-- net/ipv4/tcp_rate.c | 10 +++++++--- 5 files changed, 19 insertions(+), 7 deletions(-) diff --git a/include/linux/tcp.h b/include/linux/tcp.h index df5d97a85e1a..ca4a6361389b 100644 --- a/include/linux/tcp.h +++ b/include/linux/tcp.h @@ -224,7 +224,8 @@ struct tcp_sock { rate_app_limited:1, /* rate_{delivered,interval_us} limited? */ fastopen_connect:1, /* FASTOPEN_CONNECT sockopt */ fastopen_no_cookie:1, /* Allow send/recv SYN+data without a cookie */ - unused:3; + is_sack_reneg:1, /* in recovery from loss with SACK reneg? */ + unused:2; u8 nonagle : 4,/* Disable Nagle algorithm? */ thin_lto : 1,/* Use linear timeouts for thin streams */ unused1 : 1, diff --git a/include/net/tcp.h b/include/net/tcp.h index 6998707e81f3..6da880d2f022 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -1055,7 +1055,7 @@ void tcp_rate_skb_sent(struct sock *sk, struct sk_buff *skb); void tcp_rate_skb_delivered(struct sock *sk, struct sk_buff *skb, struct rate_sample *rs); void tcp_rate_gen(struct sock *sk, u32 delivered, u32 lost, - struct rate_sample *rs); + bool is_sack_reneg, struct rate_sample *rs); void tcp_rate_check_app_limited(struct sock *sk); /* These functions determine how the current flow behaves in respect of SACK diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index bf97317e6c97..f08eebe60446 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -2412,6 +2412,7 @@ int tcp_disconnect(struct sock *sk, int flags) tp->snd_cwnd_cnt = 0; tp->window_clamp = 0; tcp_set_ca_state(sk, TCP_CA_Open); + tp->is_sack_reneg = 0; tcp_clear_retrans(tp); inet_csk_delack_init(sk); /* Initialize rcv_mss to TCP_MIN_MSS to avoid division by 0 diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index 514c00732988..075c559570e6 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -1942,6 +1942,8 @@ void tcp_enter_loss(struct sock *sk) if (is_reneg) { NET_INC_STATS(sock_net(sk), LINUX_MIB_TCPSACKRENEGING); tp->sacked_out = 0; + /* Mark SACK reneging until we recover from this loss event. */ + tp->is_sack_reneg = 1; } tcp_clear_all_retrans_hints(tp); @@ -2365,6 +2367,7 @@ static bool tcp_try_undo_recovery(struct sock *sk) return true; } tcp_set_ca_state(sk, TCP_CA_Open); + tp->is_sack_reneg = 0; return false; } @@ -2398,8 +2401,10 @@ static bool tcp_try_undo_loss(struct sock *sk, bool frto_undo) NET_INC_STATS(sock_net(sk), LINUX_MIB_TCPSPURIOUSRTOS); inet_csk(sk)->icsk_retransmits = 0; - if (frto_undo || tcp_is_sack(tp)) + if (frto_undo || tcp_is_sack(tp)) { tcp_set_ca_state(sk, TCP_CA_Open); + tp->is_sack_reneg = 0; + } return true; } return false; @@ -3496,6 +3501,7 @@ static int tcp_ack(struct sock *sk, const struct sk_buff *skb, int flag) struct tcp_sacktag_state sack_state; struct rate_sample rs = { .prior_delivered = 0 }; u32 prior_snd_una = tp->snd_una; + bool is_sack_reneg = tp->is_sack_reneg; u32 ack_seq = TCP_SKB_CB(skb)->seq; u32 ack = TCP_SKB_CB(skb)->ack_seq; bool is_dupack = false; @@ -3612,7 +3618,7 @@ static int tcp_ack(struct sock *sk, const struct sk_buff *skb, int flag) delivered = tp->delivered - delivered; /* freshly ACKed or SACKed */ lost = tp->lost - lost; /* freshly marked lost */ - tcp_rate_gen(sk, delivered, lost, sack_state.rate); + tcp_rate_gen(sk, delivered, lost, is_sack_reneg, sack_state.rate); tcp_cong_control(sk, ack, delivered, flag, sack_state.rate); tcp_xmit_recovery(sk, rexmit); return 1; diff --git a/net/ipv4/tcp_rate.c b/net/ipv4/tcp_rate.c index 3330a370d306..c61240e43923 100644 --- a/net/ipv4/tcp_rate.c +++ b/net/ipv4/tcp_rate.c @@ -106,7 +106,7 @@ void tcp_rate_skb_delivered(struct sock *sk, struct sk_buff *skb, /* Update the connection delivery information and generate a rate sample. */ void tcp_rate_gen(struct sock *sk, u32 delivered, u32 lost, - struct rate_sample *rs) + bool is_sack_reneg, struct rate_sample *rs) { struct tcp_sock *tp = tcp_sk(sk); u32 snd_us, ack_us; @@ -124,8 +124,12 @@ void tcp_rate_gen(struct sock *sk, u32 delivered, u32 lost, rs->acked_sacked = delivered; /* freshly ACKed or SACKed */ rs->losses = lost; /* freshly marked lost */ - /* Return an invalid sample if no timing information is available. */ - if (!rs->prior_mstamp) { + /* Return an invalid sample if no timing information is available or + * in recovery from loss with SACK reneging. Rate samples taken during + * a SACK reneging event may overestimate bw by including packets that + * were SACKed before the reneg. + */ + if (!rs->prior_mstamp || is_sack_reneg) { rs->delivered = -1; rs->interval_us = -1; return; -- GitLab From a2d8737d5c781d388b553dd085b56d7295fffc6c Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:27 +0000 Subject: [PATCH 1116/2547] KEYS: remove unnecessary get/put of explicit dest_keyring In request_key_and_link(), in the case where the dest_keyring was explicitly specified, there is no need to get another reference to dest_keyring before calling key_link(), then drop it afterwards. This is because by definition, we already have a reference to dest_keyring. This change is useful because we'll be making construct_get_dest_keyring() able to return an error code, and we don't want to have to handle that error here for no reason. Signed-off-by: Eric Biggers Signed-off-by: David Howells --- security/keys/request_key.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/security/keys/request_key.c b/security/keys/request_key.c index e8036cd0ad54..c6880af8b411 100644 --- a/security/keys/request_key.c +++ b/security/keys/request_key.c @@ -546,9 +546,7 @@ struct key *request_key_and_link(struct key_type *type, if (!IS_ERR(key_ref)) { key = key_ref_to_ptr(key_ref); if (dest_keyring) { - construct_get_dest_keyring(&dest_keyring); ret = key_link(dest_keyring, key); - key_put(dest_keyring); if (ret < 0) { key_put(key); key = ERR_PTR(ret); -- GitLab From 4dca6ea1d9432052afb06baf2e3ae78188a4410b Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:27 +0000 Subject: [PATCH 1117/2547] KEYS: add missing permission check for request_key() destination When the request_key() syscall is not passed a destination keyring, it links the requested key (if constructed) into the "default" request-key keyring. This should require Write permission to the keyring. However, there is actually no permission check. This can be abused to add keys to any keyring to which only Search permission is granted. This is because Search permission allows joining the keyring. keyctl_set_reqkey_keyring(KEY_REQKEY_DEFL_SESSION_KEYRING) then will set the default request-key keyring to the session keyring. Then, request_key() can be used to add keys to the keyring. Both negatively and positively instantiated keys can be added using this method. Adding negative keys is trivial. Adding a positive key is a bit trickier. It requires that either /sbin/request-key positively instantiates the key, or that another thread adds the key to the process keyring at just the right time, such that request_key() misses it initially but then finds it in construct_alloc_key(). Fix this bug by checking for Write permission to the keyring in construct_get_dest_keyring() when the default keyring is being used. We don't do the permission check for non-default keyrings because that was already done by the earlier call to lookup_user_key(). Also, request_key_and_link() is currently passed a 'struct key *' rather than a key_ref_t, so the "possessed" bit is unavailable. We also don't do the permission check for the "requestor keyring", to continue to support the use case described by commit 8bbf4976b59f ("KEYS: Alter use of key instantiation link-to-keyring argument") where /sbin/request-key recursively calls request_key() to add keys to the original requestor's destination keyring. (I don't know of any users who actually do that, though...) Fixes: 3e30148c3d52 ("[PATCH] Keys: Make request-key create an authorisation key") Cc: # v2.6.13+ Signed-off-by: Eric Biggers Signed-off-by: David Howells --- security/keys/request_key.c | 46 +++++++++++++++++++++++++++++-------- 1 file changed, 37 insertions(+), 9 deletions(-) diff --git a/security/keys/request_key.c b/security/keys/request_key.c index c6880af8b411..114f7408feee 100644 --- a/security/keys/request_key.c +++ b/security/keys/request_key.c @@ -251,11 +251,12 @@ static int construct_key(struct key *key, const void *callout_info, * The keyring selected is returned with an extra reference upon it which the * caller must release. */ -static void construct_get_dest_keyring(struct key **_dest_keyring) +static int construct_get_dest_keyring(struct key **_dest_keyring) { struct request_key_auth *rka; const struct cred *cred = current_cred(); struct key *dest_keyring = *_dest_keyring, *authkey; + int ret; kenter("%p", dest_keyring); @@ -264,6 +265,8 @@ static void construct_get_dest_keyring(struct key **_dest_keyring) /* the caller supplied one */ key_get(dest_keyring); } else { + bool do_perm_check = true; + /* use a default keyring; falling through the cases until we * find one that we actually have */ switch (cred->jit_keyring) { @@ -278,8 +281,10 @@ static void construct_get_dest_keyring(struct key **_dest_keyring) dest_keyring = key_get(rka->dest_keyring); up_read(&authkey->sem); - if (dest_keyring) + if (dest_keyring) { + do_perm_check = false; break; + } } case KEY_REQKEY_DEFL_THREAD_KEYRING: @@ -314,11 +319,29 @@ static void construct_get_dest_keyring(struct key **_dest_keyring) default: BUG(); } + + /* + * Require Write permission on the keyring. This is essential + * because the default keyring may be the session keyring, and + * joining a keyring only requires Search permission. + * + * However, this check is skipped for the "requestor keyring" so + * that /sbin/request-key can itself use request_key() to add + * keys to the original requestor's destination keyring. + */ + if (dest_keyring && do_perm_check) { + ret = key_permission(make_key_ref(dest_keyring, 1), + KEY_NEED_WRITE); + if (ret) { + key_put(dest_keyring); + return ret; + } + } } *_dest_keyring = dest_keyring; kleave(" [dk %d]", key_serial(dest_keyring)); - return; + return 0; } /* @@ -444,11 +467,15 @@ static struct key *construct_key_and_link(struct keyring_search_context *ctx, if (ctx->index_key.type == &key_type_keyring) return ERR_PTR(-EPERM); - user = key_user_lookup(current_fsuid()); - if (!user) - return ERR_PTR(-ENOMEM); + ret = construct_get_dest_keyring(&dest_keyring); + if (ret) + goto error; - construct_get_dest_keyring(&dest_keyring); + user = key_user_lookup(current_fsuid()); + if (!user) { + ret = -ENOMEM; + goto error_put_dest_keyring; + } ret = construct_alloc_key(ctx, dest_keyring, flags, user, &key); key_user_put(user); @@ -463,7 +490,7 @@ static struct key *construct_key_and_link(struct keyring_search_context *ctx, } else if (ret == -EINPROGRESS) { ret = 0; } else { - goto couldnt_alloc_key; + goto error_put_dest_keyring; } key_put(dest_keyring); @@ -473,8 +500,9 @@ static struct key *construct_key_and_link(struct keyring_search_context *ctx, construction_failed: key_negate_and_link(key, key_negative_timeout, NULL, NULL); key_put(key); -couldnt_alloc_key: +error_put_dest_keyring: key_put(dest_keyring); +error: kleave(" = %d", ret); return ERR_PTR(ret); } -- GitLab From e0058f3a874ebb48b25be7ff79bc3b4e59929f90 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:27 +0000 Subject: [PATCH 1118/2547] ASN.1: fix out-of-bounds read when parsing indefinite length item In asn1_ber_decoder(), indefinitely-sized ASN.1 items were being passed to the action functions before their lengths had been computed, using the bogus length of 0x80 (ASN1_INDEFINITE_LENGTH). This resulted in reading data past the end of the input buffer, when given a specially crafted message. Fix it by rearranging the code so that the indefinite length is resolved before the action is called. This bug was originally found by fuzzing the X.509 parser in userspace using libFuzzer from the LLVM project. KASAN report (cleaned up slightly): BUG: KASAN: slab-out-of-bounds in memcpy ./include/linux/string.h:341 [inline] BUG: KASAN: slab-out-of-bounds in x509_fabricate_name.constprop.1+0x1a4/0x940 crypto/asymmetric_keys/x509_cert_parser.c:366 Read of size 128 at addr ffff880035dd9eaf by task keyctl/195 CPU: 1 PID: 195 Comm: keyctl Not tainted 4.14.0-09238-g1d3b78bbc6e9 #26 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.11.0-20171110_100015-anatol 04/01/2014 Call Trace: __dump_stack lib/dump_stack.c:17 [inline] dump_stack+0xd1/0x175 lib/dump_stack.c:53 print_address_description+0x78/0x260 mm/kasan/report.c:252 kasan_report_error mm/kasan/report.c:351 [inline] kasan_report+0x23f/0x350 mm/kasan/report.c:409 memcpy+0x1f/0x50 mm/kasan/kasan.c:302 memcpy ./include/linux/string.h:341 [inline] x509_fabricate_name.constprop.1+0x1a4/0x940 crypto/asymmetric_keys/x509_cert_parser.c:366 asn1_ber_decoder+0xb4a/0x1fd0 lib/asn1_decoder.c:447 x509_cert_parse+0x1c7/0x620 crypto/asymmetric_keys/x509_cert_parser.c:89 x509_key_preparse+0x61/0x750 crypto/asymmetric_keys/x509_public_key.c:174 asymmetric_key_preparse+0xa4/0x150 crypto/asymmetric_keys/asymmetric_type.c:388 key_create_or_update+0x4d4/0x10a0 security/keys/key.c:850 SYSC_add_key security/keys/keyctl.c:122 [inline] SyS_add_key+0xe8/0x290 security/keys/keyctl.c:62 entry_SYSCALL_64_fastpath+0x1f/0x96 Allocated by task 195: __do_kmalloc_node mm/slab.c:3675 [inline] __kmalloc_node+0x47/0x60 mm/slab.c:3682 kvmalloc ./include/linux/mm.h:540 [inline] SYSC_add_key security/keys/keyctl.c:104 [inline] SyS_add_key+0x19e/0x290 security/keys/keyctl.c:62 entry_SYSCALL_64_fastpath+0x1f/0x96 Fixes: 42d5ec27f873 ("X.509: Add an ASN.1 decoder") Reported-by: Alexander Potapenko Cc: # v3.7+ Signed-off-by: Eric Biggers Signed-off-by: David Howells --- lib/asn1_decoder.c | 47 +++++++++++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 21 deletions(-) diff --git a/lib/asn1_decoder.c b/lib/asn1_decoder.c index 1ef0cec38d78..d77cdfc4b554 100644 --- a/lib/asn1_decoder.c +++ b/lib/asn1_decoder.c @@ -313,42 +313,47 @@ int asn1_ber_decoder(const struct asn1_decoder *decoder, /* Decide how to handle the operation */ switch (op) { - case ASN1_OP_MATCH_ANY_ACT: - case ASN1_OP_MATCH_ANY_ACT_OR_SKIP: - case ASN1_OP_COND_MATCH_ANY_ACT: - case ASN1_OP_COND_MATCH_ANY_ACT_OR_SKIP: - ret = actions[machine[pc + 1]](context, hdr, tag, data + dp, len); - if (ret < 0) - return ret; - goto skip_data; - - case ASN1_OP_MATCH_ACT: - case ASN1_OP_MATCH_ACT_OR_SKIP: - case ASN1_OP_COND_MATCH_ACT_OR_SKIP: - ret = actions[machine[pc + 2]](context, hdr, tag, data + dp, len); - if (ret < 0) - return ret; - goto skip_data; - case ASN1_OP_MATCH: case ASN1_OP_MATCH_OR_SKIP: + case ASN1_OP_MATCH_ACT: + case ASN1_OP_MATCH_ACT_OR_SKIP: case ASN1_OP_MATCH_ANY: case ASN1_OP_MATCH_ANY_OR_SKIP: + case ASN1_OP_MATCH_ANY_ACT: + case ASN1_OP_MATCH_ANY_ACT_OR_SKIP: case ASN1_OP_COND_MATCH_OR_SKIP: + case ASN1_OP_COND_MATCH_ACT_OR_SKIP: case ASN1_OP_COND_MATCH_ANY: case ASN1_OP_COND_MATCH_ANY_OR_SKIP: - skip_data: + case ASN1_OP_COND_MATCH_ANY_ACT: + case ASN1_OP_COND_MATCH_ANY_ACT_OR_SKIP: + if (!(flags & FLAG_CONS)) { if (flags & FLAG_INDEFINITE_LENGTH) { + size_t tmp = dp; + ret = asn1_find_indefinite_length( - data, datalen, &dp, &len, &errmsg); + data, datalen, &tmp, &len, &errmsg); if (ret < 0) goto error; - } else { - dp += len; } pr_debug("- LEAF: %zu\n", len); } + + if (op & ASN1_OP_MATCH__ACT) { + unsigned char act; + + if (op & ASN1_OP_MATCH__ANY) + act = machine[pc + 1]; + else + act = machine[pc + 2]; + ret = actions[act](context, hdr, tag, data + dp, len); + if (ret < 0) + return ret; + } + + if (!(flags & FLAG_CONS)) + dp += len; pc += asn1_op_lengths[op]; goto next_op; -- GitLab From 81a7be2cd69b412ab6aeacfe5ebf1bb6e5bce955 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:27 +0000 Subject: [PATCH 1119/2547] ASN.1: check for error from ASN1_OP_END__ACT actions asn1_ber_decoder() was ignoring errors from actions associated with the opcodes ASN1_OP_END_SEQ_ACT, ASN1_OP_END_SET_ACT, ASN1_OP_END_SEQ_OF_ACT, and ASN1_OP_END_SET_OF_ACT. In practice, this meant the pkcs7_note_signed_info() action (since that was the only user of those opcodes). Fix it by checking for the error, just like the decoder does for actions associated with the other opcodes. This bug allowed users to leak slab memory by repeatedly trying to add a specially crafted "pkcs7_test" key (requires CONFIG_PKCS7_TEST_KEY). In theory, this bug could also be used to bypass module signature verification, by providing a PKCS#7 message that is misparsed such that a signature's ->authattrs do not contain its ->msgdigest. But it doesn't seem practical in normal cases, due to restrictions on the format of the ->authattrs. Fixes: 42d5ec27f873 ("X.509: Add an ASN.1 decoder") Cc: # v3.7+ Signed-off-by: Eric Biggers Signed-off-by: David Howells Reviewed-by: James Morris --- lib/asn1_decoder.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/asn1_decoder.c b/lib/asn1_decoder.c index d77cdfc4b554..dc14beae2c9a 100644 --- a/lib/asn1_decoder.c +++ b/lib/asn1_decoder.c @@ -439,6 +439,8 @@ int asn1_ber_decoder(const struct asn1_decoder *decoder, else act = machine[pc + 1]; ret = actions[act](context, hdr, 0, data + tdp, len); + if (ret < 0) + return ret; } pc += asn1_op_lengths[op]; goto next_op; -- GitLab From 0f30cbea005bd3077bd98cd29277d7fc2699c1da Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:27 +0000 Subject: [PATCH 1120/2547] X.509: reject invalid BIT STRING for subjectPublicKey Adding a specially crafted X.509 certificate whose subjectPublicKey ASN.1 value is zero-length caused x509_extract_key_data() to set the public key size to SIZE_MAX, as it subtracted the nonexistent BIT STRING metadata byte. Then, x509_cert_parse() called kmemdup() with that bogus size, triggering the WARN_ON_ONCE() in kmalloc_slab(). This appears to be harmless, but it still must be fixed since WARNs are never supposed to be user-triggerable. Fix it by updating x509_cert_parse() to validate that the value has a BIT STRING metadata byte, and that the byte is 0 which indicates that the number of bits in the bitstring is a multiple of 8. It would be nice to handle the metadata byte in asn1_ber_decoder() instead. But that would be tricky because in the general case a BIT STRING could be implicitly tagged, and/or could legitimately have a length that is not a whole number of bytes. Here was the WARN (cleaned up slightly): WARNING: CPU: 1 PID: 202 at mm/slab_common.c:971 kmalloc_slab+0x5d/0x70 mm/slab_common.c:971 Modules linked in: CPU: 1 PID: 202 Comm: keyctl Tainted: G B 4.14.0-09238-g1d3b78bbc6e9 #26 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.11.0-20171110_100015-anatol 04/01/2014 task: ffff880033014180 task.stack: ffff8800305c8000 Call Trace: __do_kmalloc mm/slab.c:3706 [inline] __kmalloc_track_caller+0x22/0x2e0 mm/slab.c:3726 kmemdup+0x17/0x40 mm/util.c:118 kmemdup include/linux/string.h:414 [inline] x509_cert_parse+0x2cb/0x620 crypto/asymmetric_keys/x509_cert_parser.c:106 x509_key_preparse+0x61/0x750 crypto/asymmetric_keys/x509_public_key.c:174 asymmetric_key_preparse+0xa4/0x150 crypto/asymmetric_keys/asymmetric_type.c:388 key_create_or_update+0x4d4/0x10a0 security/keys/key.c:850 SYSC_add_key security/keys/keyctl.c:122 [inline] SyS_add_key+0xe8/0x290 security/keys/keyctl.c:62 entry_SYSCALL_64_fastpath+0x1f/0x96 Fixes: 42d5ec27f873 ("X.509: Add an ASN.1 decoder") Cc: # v3.7+ Signed-off-by: Eric Biggers Signed-off-by: David Howells Reviewed-by: James Morris --- crypto/asymmetric_keys/x509_cert_parser.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/crypto/asymmetric_keys/x509_cert_parser.c b/crypto/asymmetric_keys/x509_cert_parser.c index dd03fead1ca3..ce2df8c9c583 100644 --- a/crypto/asymmetric_keys/x509_cert_parser.c +++ b/crypto/asymmetric_keys/x509_cert_parser.c @@ -409,6 +409,8 @@ int x509_extract_key_data(void *context, size_t hdrlen, ctx->cert->pub->pkey_algo = "rsa"; /* Discard the BIT STRING metadata */ + if (vlen < 1 || *(const u8 *)value != 0) + return -EBADMSG; ctx->key = value + 1; ctx->key_size = vlen - 1; return 0; -- GitLab From 47e0a208fb9d91e3f3c86309e752b13a36470ae8 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:28 +0000 Subject: [PATCH 1121/2547] X.509: fix buffer overflow detection in sprint_oid() In sprint_oid(), if the input buffer were to be more than 1 byte too small for the first snprintf(), 'bufsize' would underflow, causing a buffer overflow when printing the remainder of the OID. Fortunately this cannot actually happen currently, because no users pass in a buffer that can be too small for the first snprintf(). Regardless, fix it by checking the snprintf() return value correctly. For consistency also tweak the second snprintf() check to look the same. Fixes: 4f73175d0375 ("X.509: Add utility functions to render OIDs as strings") Cc: Takashi Iwai Signed-off-by: Eric Biggers Signed-off-by: David Howells Reviewed-by: James Morris --- lib/oid_registry.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/oid_registry.c b/lib/oid_registry.c index 41b9e50711a7..5a75d127995d 100644 --- a/lib/oid_registry.c +++ b/lib/oid_registry.c @@ -120,10 +120,10 @@ int sprint_oid(const void *data, size_t datasize, char *buffer, size_t bufsize) n = *v++; ret = count = snprintf(buffer, bufsize, "%u.%u", n / 40, n % 40); + if (count >= bufsize) + return -ENOBUFS; buffer += count; bufsize -= count; - if (bufsize == 0) - return -ENOBUFS; while (v < end) { num = 0; @@ -141,9 +141,9 @@ int sprint_oid(const void *data, size_t datasize, char *buffer, size_t bufsize) } while (n & 0x80); } ret += count = snprintf(buffer, bufsize, ".%lu", num); - buffer += count; - if (bufsize <= count) + if (count >= bufsize) return -ENOBUFS; + buffer += count; bufsize -= count; } -- GitLab From 8dfd2f22d3bf3ab7714f7495ad5d897b8845e8c1 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:28 +0000 Subject: [PATCH 1122/2547] 509: fix printing uninitialized stack memory when OID is empty Callers of sprint_oid() do not check its return value before printing the result. In the case where the OID is zero-length, -EBADMSG was being returned without anything being written to the buffer, resulting in uninitialized stack memory being printed. Fix this by writing "(bad)" to the buffer in the cases where -EBADMSG is returned. Fixes: 4f73175d0375 ("X.509: Add utility functions to render OIDs as strings") Signed-off-by: Eric Biggers Signed-off-by: David Howells --- lib/oid_registry.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/lib/oid_registry.c b/lib/oid_registry.c index 5a75d127995d..0bcac6ccb1b2 100644 --- a/lib/oid_registry.c +++ b/lib/oid_registry.c @@ -116,7 +116,7 @@ int sprint_oid(const void *data, size_t datasize, char *buffer, size_t bufsize) int count; if (v >= end) - return -EBADMSG; + goto bad; n = *v++; ret = count = snprintf(buffer, bufsize, "%u.%u", n / 40, n % 40); @@ -134,7 +134,7 @@ int sprint_oid(const void *data, size_t datasize, char *buffer, size_t bufsize) num = n & 0x7f; do { if (v >= end) - return -EBADMSG; + goto bad; n = *v++; num <<= 7; num |= n & 0x7f; @@ -148,6 +148,10 @@ int sprint_oid(const void *data, size_t datasize, char *buffer, size_t bufsize) } return ret; + +bad: + snprintf(buffer, bufsize, "(bad)"); + return -EBADMSG; } EXPORT_SYMBOL_GPL(sprint_oid); -- GitLab From 8ecb506d3476aa58077e79ef1f75395625458fcc Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:28 +0000 Subject: [PATCH 1123/2547] pkcs7: return correct error code if pkcs7_check_authattrs() fails If pkcs7_check_authattrs() returns an error code, we should pass that error code on, rather than using ENOMEM. Fixes: 99db44350672 ("PKCS#7: Appropriately restrict authenticated attributes and content type") Signed-off-by: Eric Biggers Signed-off-by: David Howells Reviewed-by: James Morris --- crypto/asymmetric_keys/pkcs7_parser.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/crypto/asymmetric_keys/pkcs7_parser.c b/crypto/asymmetric_keys/pkcs7_parser.c index c1ca1e86f5c4..a6dcaa659aa8 100644 --- a/crypto/asymmetric_keys/pkcs7_parser.c +++ b/crypto/asymmetric_keys/pkcs7_parser.c @@ -148,8 +148,10 @@ struct pkcs7_message *pkcs7_parse_message(const void *data, size_t datalen) } ret = pkcs7_check_authattrs(ctx->msg); - if (ret < 0) + if (ret < 0) { + msg = ERR_PTR(ret); goto out; + } msg = ctx->msg; ctx->msg = NULL; -- GitLab From 7204eb8590c750e8c10b47f4acd4efe6e4138452 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:28 +0000 Subject: [PATCH 1124/2547] pkcs7: fix check for self-signed certificate pkcs7_validate_trust_one() used 'x509->next == x509' to identify a self-signed certificate. That's wrong; ->next is simply the link in the linked list of certificates in the PKCS#7 message. It should be checking ->signer instead. Fix it. Fortunately this didn't actually matter because when we re-visited 'x509' on the next iteration via 'x509->signer', it was already seen and not verified, so we returned -ENOKEY anyway. Signed-off-by: Eric Biggers Signed-off-by: David Howells Reviewed-by: James Morris --- crypto/asymmetric_keys/pkcs7_trust.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/crypto/asymmetric_keys/pkcs7_trust.c b/crypto/asymmetric_keys/pkcs7_trust.c index f6a009d88a33..1f4e25f10049 100644 --- a/crypto/asymmetric_keys/pkcs7_trust.c +++ b/crypto/asymmetric_keys/pkcs7_trust.c @@ -69,7 +69,7 @@ static int pkcs7_validate_trust_one(struct pkcs7_message *pkcs7, /* Self-signed certificates form roots of their own, and if we * don't know them, then we can't accept them. */ - if (x509->next == x509) { + if (x509->signer == x509) { kleave(" = -ENOKEY [unknown self-signed]"); return -ENOKEY; } -- GitLab From a80745a6de51a651977a16ef81cba0126f9dd66f Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:28 +0000 Subject: [PATCH 1125/2547] pkcs7: use crypto_shash_digest() Use crypto_shash_digest() instead of crypto_shash_init() followed by crypto_shash_finup(). (For simplicity only; they are equivalent.) Signed-off-by: Eric Biggers Signed-off-by: David Howells --- crypto/asymmetric_keys/pkcs7_verify.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/crypto/asymmetric_keys/pkcs7_verify.c b/crypto/asymmetric_keys/pkcs7_verify.c index 2d93d9eccb4d..255e84abdc69 100644 --- a/crypto/asymmetric_keys/pkcs7_verify.c +++ b/crypto/asymmetric_keys/pkcs7_verify.c @@ -59,11 +59,8 @@ static int pkcs7_digest(struct pkcs7_message *pkcs7, desc->flags = CRYPTO_TFM_REQ_MAY_SLEEP; /* Digest the message [RFC2315 9.3] */ - ret = crypto_shash_init(desc); - if (ret < 0) - goto error; - ret = crypto_shash_finup(desc, pkcs7->data, pkcs7->data_len, - sig->digest); + ret = crypto_shash_digest(desc, pkcs7->data, pkcs7->data_len, + sig->digest); if (ret < 0) goto error; pr_devel("MsgDigest = [%*ph]\n", 8, sig->digest); -- GitLab From 72f9a07b6bfaefdc29fcb75dafa8867a4f6d8317 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:29 +0000 Subject: [PATCH 1126/2547] KEYS: be careful with error codes in public_key_verify_signature() In public_key_verify_signature(), if akcipher_request_alloc() fails, we return -ENOMEM. But that error code was set 25 lines above, and by accident someone could easily insert new code in between that assigns to 'ret', which would introduce a signature verification bypass. Make the code clearer by moving the -ENOMEM down to where it is used. Additionally, the callers of public_key_verify_signature() only consider a negative return value to be an error. This means that if any positive return value is accidentally introduced deeper in the call stack (e.g. 'return EBADMSG' instead of 'return -EBADMSG' somewhere in RSA), signature verification will be bypassed. Make things more robust by having public_key_verify_signature() warn about positive errors and translate them into -EINVAL. Signed-off-by: Eric Biggers Signed-off-by: David Howells --- crypto/asymmetric_keys/public_key.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/crypto/asymmetric_keys/public_key.c b/crypto/asymmetric_keys/public_key.c index bc3035ef27a2..de996586762a 100644 --- a/crypto/asymmetric_keys/public_key.c +++ b/crypto/asymmetric_keys/public_key.c @@ -73,7 +73,7 @@ int public_key_verify_signature(const struct public_key *pkey, char alg_name_buf[CRYPTO_MAX_ALG_NAME]; void *output; unsigned int outlen; - int ret = -ENOMEM; + int ret; pr_devel("==>%s()\n", __func__); @@ -99,6 +99,7 @@ int public_key_verify_signature(const struct public_key *pkey, if (IS_ERR(tfm)) return PTR_ERR(tfm); + ret = -ENOMEM; req = akcipher_request_alloc(tfm, GFP_KERNEL); if (!req) goto error_free_tfm; @@ -127,7 +128,7 @@ int public_key_verify_signature(const struct public_key *pkey, * signature and returns that to us. */ ret = crypto_wait_req(crypto_akcipher_verify(req), &cwait); - if (ret < 0) + if (ret) goto out_free_output; /* Do the actual verification step. */ @@ -142,6 +143,8 @@ int public_key_verify_signature(const struct public_key *pkey, error_free_tfm: crypto_free_akcipher(tfm); pr_devel("<==%s() = %d\n", __func__, ret); + if (WARN_ON_ONCE(ret > 0)) + ret = -EINVAL; return ret; } EXPORT_SYMBOL_GPL(public_key_verify_signature); -- GitLab From aa3300362060525fe1a32de56df9578033530d98 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:29 +0000 Subject: [PATCH 1127/2547] X.509: use crypto_shash_digest() Use crypto_shash_digest() instead of crypto_shash_init() followed by crypto_shash_finup(). (For simplicity only; they are equivalent.) Signed-off-by: Eric Biggers Signed-off-by: David Howells --- crypto/asymmetric_keys/x509_public_key.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/crypto/asymmetric_keys/x509_public_key.c b/crypto/asymmetric_keys/x509_public_key.c index c9013582c026..e67fd29fbd11 100644 --- a/crypto/asymmetric_keys/x509_public_key.c +++ b/crypto/asymmetric_keys/x509_public_key.c @@ -79,11 +79,7 @@ int x509_get_sig_params(struct x509_certificate *cert) desc->tfm = tfm; desc->flags = CRYPTO_TFM_REQ_MAY_SLEEP; - ret = crypto_shash_init(desc); - if (ret < 0) - goto error_2; - might_sleep(); - ret = crypto_shash_finup(desc, cert->tbs, cert->tbs_size, sig->digest); + ret = crypto_shash_digest(desc, cert->tbs, cert->tbs_size, sig->digest); if (ret < 0) goto error_2; -- GitLab From 3d1f0255426af7eeb88bf7221ff683b7ca9e4493 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Fri, 8 Dec 2017 15:13:29 +0000 Subject: [PATCH 1128/2547] security: keys: remove redundant assignment to key_ref Variable key_ref is being assigned a value that is never read; key_ref is being re-assigned a few statements later. Hence this assignment is redundant and can be removed. Signed-off-by: Colin Ian King Signed-off-by: David Howells Reviewed-by: James Morris --- security/keys/key.c | 1 - 1 file changed, 1 deletion(-) diff --git a/security/keys/key.c b/security/keys/key.c index 66049183ad89..d97c9394b5dd 100644 --- a/security/keys/key.c +++ b/security/keys/key.c @@ -833,7 +833,6 @@ key_ref_t key_create_or_update(key_ref_t keyring_ref, key_check(keyring); - key_ref = ERR_PTR(-EPERM); if (!(flags & KEY_ALLOC_BYPASS_RESTRICTION)) restrict_link = keyring->restrict_link; -- GitLab From 18026d866801d0c52e5550210563222bd6c7191d Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:29 +0000 Subject: [PATCH 1129/2547] KEYS: reject NULL restriction string when type is specified keyctl_restrict_keyring() allows through a NULL restriction when the "type" is non-NULL, which causes a NULL pointer dereference in asymmetric_lookup_restriction() when it calls strcmp() on the restriction string. But no key types actually use a "NULL restriction" to mean anything, so update keyctl_restrict_keyring() to reject it with EINVAL. Reported-by: syzbot Fixes: 97d3aa0f3134 ("KEYS: Add a lookup_restriction function for the asymmetric key type") Cc: # v4.12+ Signed-off-by: Eric Biggers Signed-off-by: David Howells --- security/keys/keyctl.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/security/keys/keyctl.c b/security/keys/keyctl.c index 76d22f726ae4..1ffe60bb2845 100644 --- a/security/keys/keyctl.c +++ b/security/keys/keyctl.c @@ -1588,9 +1588,8 @@ long keyctl_session_to_parent(void) * The caller must have Setattr permission to change keyring restrictions. * * The requested type name may be a NULL pointer to reject all attempts - * to link to the keyring. If _type is non-NULL, _restriction can be - * NULL or a pointer to a string describing the restriction. If _type is - * NULL, _restriction must also be NULL. + * to link to the keyring. In this case, _restriction must also be NULL. + * Otherwise, both _type and _restriction must be non-NULL. * * Returns 0 if successful. */ @@ -1598,7 +1597,6 @@ long keyctl_restrict_keyring(key_serial_t id, const char __user *_type, const char __user *_restriction) { key_ref_t key_ref; - bool link_reject = !_type; char type[32]; char *restriction = NULL; long ret; @@ -1607,31 +1605,29 @@ long keyctl_restrict_keyring(key_serial_t id, const char __user *_type, if (IS_ERR(key_ref)) return PTR_ERR(key_ref); + ret = -EINVAL; if (_type) { - ret = key_get_type_from_user(type, _type, sizeof(type)); - if (ret < 0) + if (!_restriction) goto error; - } - if (_restriction) { - if (!_type) { - ret = -EINVAL; + ret = key_get_type_from_user(type, _type, sizeof(type)); + if (ret < 0) goto error; - } restriction = strndup_user(_restriction, PAGE_SIZE); if (IS_ERR(restriction)) { ret = PTR_ERR(restriction); goto error; } + } else { + if (_restriction) + goto error; } - ret = keyring_restrict(key_ref, link_reject ? NULL : type, restriction); + ret = keyring_restrict(key_ref, _type ? type : NULL, restriction); kfree(restriction); - error: key_ref_put(key_ref); - return ret; } -- GitLab From 54c1fb39fe0495f846539ab765925b008f86801c Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Fri, 8 Dec 2017 15:13:29 +0000 Subject: [PATCH 1130/2547] X.509: fix comparisons of ->pkey_algo ->pkey_algo used to be an enum, but was changed to a string by commit 4e8ae72a75aa ("X.509: Make algo identifiers text instead of enum"). But two comparisons were not updated. Fix them to use strcmp(). This bug broke signature verification in certain configurations, depending on whether the string constants were deduplicated or not. Fixes: 4e8ae72a75aa ("X.509: Make algo identifiers text instead of enum") Cc: # v4.6+ Signed-off-by: Eric Biggers Signed-off-by: David Howells --- crypto/asymmetric_keys/pkcs7_verify.c | 2 +- crypto/asymmetric_keys/x509_public_key.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/crypto/asymmetric_keys/pkcs7_verify.c b/crypto/asymmetric_keys/pkcs7_verify.c index 255e84abdc69..39e6de0c2761 100644 --- a/crypto/asymmetric_keys/pkcs7_verify.c +++ b/crypto/asymmetric_keys/pkcs7_verify.c @@ -147,7 +147,7 @@ static int pkcs7_find_key(struct pkcs7_message *pkcs7, pr_devel("Sig %u: Found cert serial match X.509[%u]\n", sinfo->index, certix); - if (x509->pub->pkey_algo != sinfo->sig->pkey_algo) { + if (strcmp(x509->pub->pkey_algo, sinfo->sig->pkey_algo) != 0) { pr_warn("Sig %u: X.509 algo and PKCS#7 sig algo don't match\n", sinfo->index); continue; diff --git a/crypto/asymmetric_keys/x509_public_key.c b/crypto/asymmetric_keys/x509_public_key.c index e67fd29fbd11..9338b4558cdc 100644 --- a/crypto/asymmetric_keys/x509_public_key.c +++ b/crypto/asymmetric_keys/x509_public_key.c @@ -131,7 +131,7 @@ int x509_check_for_self_signed(struct x509_certificate *cert) } ret = -EKEYREJECTED; - if (cert->pub->pkey_algo != cert->sig->pkey_algo) + if (strcmp(cert->pub->pkey_algo, cert->sig->pkey_algo) != 0) goto out; ret = public_key_verify_signature(cert->pub, cert->sig); -- GitLab From 35e691eddca565f475ba69ff84ca0c9db3b3257b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 8 Dec 2017 14:13:02 +0100 Subject: [PATCH 1131/2547] of: overlay: Fix out-of-bounds write in init_overlay_changeset() If an overlay has no "__symbols__" node, but it has nodes without "__overlay__" subnodes at the end (e.g. a "__fixups__" node), after filling in all fragments for nodes with "__overlay__" subnodes, "fragment = &fragments[cnt]" will point beyond the end of the allocated array. Hence writing to "fragment->overlay" will overwrite unallocated memory, which may lead to a crash later. Fix this by deferring both the assignment to "fragment" and the offending write afterwards until we know for sure the node has an "__overlay__" subnode, and thus a valid entry in "fragments[]". Fixes: 61b4de4e0b384f4a ("of: overlay: minor restructuring") Signed-off-by: Geert Uytterhoeven Signed-off-by: Rob Herring --- drivers/of/overlay.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c index fcce5cdbe229..83bb2edfc65c 100644 --- a/drivers/of/overlay.c +++ b/drivers/of/overlay.c @@ -572,9 +572,10 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs, cnt = 0; for_each_child_of_node(tree, node) { - fragment = &fragments[cnt]; - fragment->overlay = of_get_child_by_name(node, "__overlay__"); - if (fragment->overlay) { + overlay_node = of_get_child_by_name(node, "__overlay__"); + if (overlay_node) { + fragment = &fragments[cnt]; + fragment->overlay = overlay_node; fragment->target = find_target_node(node); if (!fragment->target) { of_node_put(fragment->overlay); -- GitLab From 589b754df3f37ca0a1f96fccde7f91c59266f38a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 8 Dec 2017 14:13:03 +0100 Subject: [PATCH 1132/2547] of: overlay: Make node skipping in init_overlay_changeset() clearer Make it more clear that nodes without "__overlay__" subnodes are skipped, by reverting the logic and using continue. This also reduces indentation level. Signed-off-by: Geert Uytterhoeven Signed-off-by: Rob Herring --- drivers/of/overlay.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c index 83bb2edfc65c..3981b7da4fa9 100644 --- a/drivers/of/overlay.c +++ b/drivers/of/overlay.c @@ -573,18 +573,19 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs, cnt = 0; for_each_child_of_node(tree, node) { overlay_node = of_get_child_by_name(node, "__overlay__"); - if (overlay_node) { - fragment = &fragments[cnt]; - fragment->overlay = overlay_node; - fragment->target = find_target_node(node); - if (!fragment->target) { - of_node_put(fragment->overlay); - ret = -EINVAL; - goto err_free_fragments; - } + if (!overlay_node) + continue; - cnt++; + fragment = &fragments[cnt]; + fragment->overlay = overlay_node; + fragment->target = find_target_node(node); + if (!fragment->target) { + of_node_put(fragment->overlay); + ret = -EINVAL; + goto err_free_fragments; } + + cnt++; } /* -- GitLab From 5790eabc6e7c3ce2d6ca2e3bbf4de467ce2b64b3 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Fri, 8 Dec 2017 17:31:37 +0200 Subject: [PATCH 1133/2547] ptr_ring: fix up after recent ptr_ring changes Add more stubs to make it build. Fixes: 81fbfe8a ("ptr_ring: use kmalloc_array()") Signed-off-by: Michael S. Tsirkin --- tools/virtio/ringtest/ptr_ring.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/tools/virtio/ringtest/ptr_ring.c b/tools/virtio/ringtest/ptr_ring.c index 38bb171aceba..e6e81305ef46 100644 --- a/tools/virtio/ringtest/ptr_ring.c +++ b/tools/virtio/ringtest/ptr_ring.c @@ -16,24 +16,41 @@ #define unlikely(x) (__builtin_expect(!!(x), 0)) #define likely(x) (__builtin_expect(!!(x), 1)) #define ALIGN(x, a) (((x) + (a) - 1) / (a) * (a)) +#define SIZE_MAX (~(size_t)0) + typedef pthread_spinlock_t spinlock_t; typedef int gfp_t; -static void *kmalloc(unsigned size, gfp_t gfp) -{ - return memalign(64, size); -} +#define __GFP_ZERO 0x1 -static void *kzalloc(unsigned size, gfp_t gfp) +static void *kmalloc(unsigned size, gfp_t gfp) { void *p = memalign(64, size); if (!p) return p; - memset(p, 0, size); + if (gfp & __GFP_ZERO) + memset(p, 0, size); return p; } +static inline void *kzalloc(unsigned size, gfp_t flags) +{ + return kmalloc(size, flags | __GFP_ZERO); +} + +static inline void *kmalloc_array(size_t n, size_t size, gfp_t flags) +{ + if (size != 0 && n > SIZE_MAX / size) + return NULL; + return kmalloc(n * size, flags); +} + +static inline void *kcalloc(size_t n, size_t size, gfp_t flags) +{ + return kmalloc_array(n, size, flags | __GFP_ZERO); +} + static void kfree(void *p) { if (p) -- GitLab From c1fd0abee0d52eb7e2871194b6c79d54792f515f Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Thu, 7 Dec 2017 22:42:27 -0500 Subject: [PATCH 1134/2547] dm mpath: fix bio-based multipath queue_if_no_path handling Commit ca5beb76 ("dm mpath: micro-optimize the hot path relative to MPATHF_QUEUE_IF_NO_PATH") caused bio-based DM-multipath to fail mptest's "test_02_sdev_delete". Restoring the logic that existed prior to commit ca5beb76 fixes this bio-based DM-multipath regression. Also verified all mptest tests pass with request-based DM-multipath. This commit effectively reverts commit ca5beb76 -- but it does so without reintroducing the need to take the m->lock spinlock in must_push_back_{rq,bio}. Fixes: ca5beb76 ("dm mpath: micro-optimize the hot path relative to MPATHF_QUEUE_IF_NO_PATH") Cc: stable@vger.kernel.org # 4.12+ Signed-off-by: Mike Snitzer --- drivers/md/dm-mpath.c | 49 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/drivers/md/dm-mpath.c b/drivers/md/dm-mpath.c index 35a2a2fa477f..f7810cc869ac 100644 --- a/drivers/md/dm-mpath.c +++ b/drivers/md/dm-mpath.c @@ -457,6 +457,38 @@ do { \ dm_noflush_suspending((m)->ti)); \ } while (0) +/* + * Check whether bios must be queued in the device-mapper core rather + * than here in the target. + * + * If MPATHF_QUEUE_IF_NO_PATH and MPATHF_SAVED_QUEUE_IF_NO_PATH hold + * the same value then we are not between multipath_presuspend() + * and multipath_resume() calls and we have no need to check + * for the DMF_NOFLUSH_SUSPENDING flag. + */ +static bool __must_push_back(struct multipath *m, unsigned long flags) +{ + return ((test_bit(MPATHF_QUEUE_IF_NO_PATH, &flags) != + test_bit(MPATHF_SAVED_QUEUE_IF_NO_PATH, &flags)) && + dm_noflush_suspending(m->ti)); +} + +/* + * Following functions use READ_ONCE to get atomic access to + * all m->flags to avoid taking spinlock + */ +static bool must_push_back_rq(struct multipath *m) +{ + unsigned long flags = READ_ONCE(m->flags); + return test_bit(MPATHF_QUEUE_IF_NO_PATH, &flags) || __must_push_back(m, flags); +} + +static bool must_push_back_bio(struct multipath *m) +{ + unsigned long flags = READ_ONCE(m->flags); + return __must_push_back(m, flags); +} + /* * Map cloned requests (request-based multipath) */ @@ -478,7 +510,7 @@ static int multipath_clone_and_map(struct dm_target *ti, struct request *rq, pgpath = choose_pgpath(m, nr_bytes); if (!pgpath) { - if (test_bit(MPATHF_QUEUE_IF_NO_PATH, &m->flags)) + if (must_push_back_rq(m)) return DM_MAPIO_DELAY_REQUEUE; dm_report_EIO(m); /* Failed */ return DM_MAPIO_KILL; @@ -553,7 +585,7 @@ static int __multipath_map_bio(struct multipath *m, struct bio *bio, struct dm_m } if (!pgpath) { - if (test_bit(MPATHF_QUEUE_IF_NO_PATH, &m->flags)) + if (must_push_back_bio(m)) return DM_MAPIO_REQUEUE; dm_report_EIO(m); return DM_MAPIO_KILL; @@ -651,8 +683,7 @@ static int queue_if_no_path(struct multipath *m, bool queue_if_no_path, assign_bit(MPATHF_SAVED_QUEUE_IF_NO_PATH, &m->flags, (save_old_value && test_bit(MPATHF_QUEUE_IF_NO_PATH, &m->flags)) || (!save_old_value && queue_if_no_path)); - assign_bit(MPATHF_QUEUE_IF_NO_PATH, &m->flags, - queue_if_no_path || dm_noflush_suspending(m->ti)); + assign_bit(MPATHF_QUEUE_IF_NO_PATH, &m->flags, queue_if_no_path); spin_unlock_irqrestore(&m->lock, flags); if (!queue_if_no_path) { @@ -1486,7 +1517,7 @@ static int multipath_end_io(struct dm_target *ti, struct request *clone, fail_path(pgpath); if (atomic_read(&m->nr_valid_paths) == 0 && - !test_bit(MPATHF_QUEUE_IF_NO_PATH, &m->flags)) { + !must_push_back_rq(m)) { if (error == BLK_STS_IOERR) dm_report_EIO(m); /* complete with the original error */ @@ -1521,8 +1552,12 @@ static int multipath_end_io_bio(struct dm_target *ti, struct bio *clone, if (atomic_read(&m->nr_valid_paths) == 0 && !test_bit(MPATHF_QUEUE_IF_NO_PATH, &m->flags)) { - dm_report_EIO(m); - *error = BLK_STS_IOERR; + if (must_push_back_bio(m)) { + r = DM_ENDIO_REQUEUE; + } else { + dm_report_EIO(m); + *error = BLK_STS_IOERR; + } goto done; } -- GitLab From fbc7c07ec23c040179384a1f16b62b6030eb6bdd Mon Sep 17 00:00:00 2001 From: Suren Baghdasaryan Date: Wed, 6 Dec 2017 09:27:30 -0800 Subject: [PATCH 1135/2547] dm bufio: fix shrinker scans when (nr_to_scan < retain_target) When system is under memory pressure it is observed that dm bufio shrinker often reclaims only one buffer per scan. This change fixes the following two issues in dm bufio shrinker that cause this behavior: 1. ((nr_to_scan - freed) <= retain_target) condition is used to terminate slab scan process. This assumes that nr_to_scan is equal to the LRU size, which might not be correct because do_shrink_slab() in vmscan.c calculates nr_to_scan using multiple inputs. As a result when nr_to_scan is less than retain_target (64) the scan will terminate after the first iteration, effectively reclaiming one buffer per scan and making scans very inefficient. This hurts vmscan performance especially because mutex is acquired/released every time dm_bufio_shrink_scan() is called. New implementation uses ((LRU size - freed) <= retain_target) condition for scan termination. LRU size can be safely determined inside __scan() because this function is called after dm_bufio_lock(). 2. do_shrink_slab() uses value returned by dm_bufio_shrink_count() to determine number of freeable objects in the slab. However dm_bufio always retains retain_target buffers in its LRU and will terminate a scan when this mark is reached. Therefore returning the entire LRU size from dm_bufio_shrink_count() is misleading because that does not represent the number of freeable objects that slab will reclaim during a scan. Returning (LRU size - retain_target) better represents the number of freeable objects in the slab. This way do_shrink_slab() returns 0 when (LRU size < retain_target) and vmscan will not try to scan this shrinker avoiding scans that will not reclaim any memory. Test: tested using Android device running /system/extras/alloc-stress that generates memory pressure and causes intensive shrinker scans Signed-off-by: Suren Baghdasaryan Signed-off-by: Mike Snitzer --- drivers/md/dm-bufio.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/md/dm-bufio.c b/drivers/md/dm-bufio.c index b8ac591aaaa7..c546b567f3b5 100644 --- a/drivers/md/dm-bufio.c +++ b/drivers/md/dm-bufio.c @@ -1611,7 +1611,8 @@ static unsigned long __scan(struct dm_bufio_client *c, unsigned long nr_to_scan, int l; struct dm_buffer *b, *tmp; unsigned long freed = 0; - unsigned long count = nr_to_scan; + unsigned long count = c->n_buffers[LIST_CLEAN] + + c->n_buffers[LIST_DIRTY]; unsigned long retain_target = get_retain_buffers(c); for (l = 0; l < LIST_SIZE; l++) { @@ -1647,8 +1648,11 @@ static unsigned long dm_bufio_shrink_count(struct shrinker *shrink, struct shrink_control *sc) { struct dm_bufio_client *c = container_of(shrink, struct dm_bufio_client, shrinker); + unsigned long count = READ_ONCE(c->n_buffers[LIST_CLEAN]) + + READ_ONCE(c->n_buffers[LIST_DIRTY]); + unsigned long retain_target = get_retain_buffers(c); - return READ_ONCE(c->n_buffers[LIST_CLEAN]) + READ_ONCE(c->n_buffers[LIST_DIRTY]); + return (count < retain_target) ? 0 : (count - retain_target); } /* -- GitLab From 4522824c488e93755b10349cf6af0e967fb73186 Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Mon, 27 Nov 2017 13:16:35 -0500 Subject: [PATCH 1136/2547] drm/amdgpu: Dynamic initialize IP base offset The base offsets of the IP blocks may change across asics even though the relative register offsets are the same for an IP. Handle this dynamically. Acked-by: Christian Konig Signed-off-by: Shaoyun Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 27 ++++++++++ drivers/gpu/drm/amd/amdgpu/soc15.c | 10 ++++ drivers/gpu/drm/amd/amdgpu/soc15.h | 2 + drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 56 ++++++++++++++++++++ 5 files changed, 96 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index a7391d49ad40..f778a3b4abe6 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -62,7 +62,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o amdgpu-y += \ - vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o + vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o # add GMC block amdgpu-y += \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 5c8648ec2cd2..9b09e938a802 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1428,6 +1428,30 @@ typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); +/* Define the HW IP blocks will be used in driver , add more if necessary */ +enum amd_hw_ip_block_type { + GC_HWIP = 1, + HDP_HWIP, + SDMA0_HWIP, + SDMA1_HWIP, + MMHUB_HWIP, + ATHUB_HWIP, + NBIO_HWIP, + MP0_HWIP, + UVD_HWIP, + VCN_HWIP = UVD_HWIP, + VCE_HWIP, + DF_HWIP, + DCE_HWIP, + OSSSYS_HWIP, + SMUIO_HWIP, + PWR_HWIP, + NBIF_HWIP, + MAX_HWIP +}; + +#define HWIP_MAX_INSTANCE 6 + struct amd_powerplay { struct cgs_device *cgs_device; void *pp_handle; @@ -1620,6 +1644,9 @@ struct amdgpu_device { /* amdkfd interface */ struct kfd_dev *kfd; + /* soc15 register offset based on ip, instance and segment */ + uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; + /* delayed work_func for deferring clockgating during resume */ struct delayed_work late_init_work; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index f134ca0c093c..7c88bcb6c305 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -516,6 +516,16 @@ static const struct amdgpu_ip_block_version vega10_common_ip_block = int soc15_set_ip_blocks(struct amdgpu_device *adev) { + /* Set IP register base before any HW register access */ + switch (adev->asic_type) { + case CHIP_VEGA10: + case CHIP_RAVEN: + vega10_reg_base_init(adev); + break; + default: + return -EINVAL; + } + nbio_v6_1_detect_hw_virt(adev); if (amdgpu_sriov_vf(adev)) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h index acb3cdb119f2..c34496f1fc78 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h @@ -33,4 +33,6 @@ void soc15_grbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); int soc15_set_ip_blocks(struct amdgpu_device *adev); +int vega10_reg_base_init(struct amdgpu_device *adev); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c new file mode 100644 index 000000000000..b7bdd04793d6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c @@ -0,0 +1,56 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "soc15.h" + +#include "soc15_common.h" +#include "soc15ip.h" + +int vega10_reg_base_init(struct amdgpu_device *adev) +{ + /* HW has more IP blocks, only initialized the blocke beend by our driver */ + uint32_t i; + for (i = 0 ; i < MAX_INSTANCE ; ++i) { + adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); + adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); + adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); + adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); + adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); + adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); + adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); + adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); + adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); + adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); + adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); + adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); + adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); + adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); + adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i])); + adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i])); + + } + return 0; +} + + -- GitLab From b466107e8be15e1727e288639098ef6bfec1a982 Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Mon, 27 Nov 2017 13:20:38 -0500 Subject: [PATCH 1137/2547] drm/amdgpu: Use dynamic IP offset for register access on SOC15 Update the register access macros and functions to take into account the new dynamic IP base offsets. Acked-by: Christian Konig Signed-off-by: Shaoyun Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 126 ++++++++++------------ drivers/gpu/drm/amd/amdgpu/soc15_common.h | 34 ++---- 2 files changed, 65 insertions(+), 95 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 4c55f21e37a8..458667dd8fd7 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -107,23 +107,11 @@ static const u32 golden_settings_sdma_rv1[] = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00000002 }; -static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset) +static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, + u32 instance, u32 offset) { - u32 base = 0; - - switch (instance) { - case 0: - base = SDMA0_BASE.instance[0].segment[0]; - break; - case 1: - base = SDMA1_BASE.instance[0].segment[0]; - break; - default: - BUG(); - break; - } - - return base + internal_offset; + return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : + (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); } static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) @@ -265,8 +253,8 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; wptr = &local_wptr; - lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) >> 2; - highbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; + lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2; + highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", me, highbit, lowbit); @@ -315,8 +303,8 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) lower_32_bits(ring->wptr << 2), me, upper_32_bits(ring->wptr << 2)); - WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); - WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); + WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); + WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); } } @@ -460,12 +448,12 @@ static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); for (i = 0; i < adev->sdma.num_instances; i++) { - rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL)); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); } sdma0->ready = false; @@ -522,18 +510,18 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) } for (i = 0; i < adev->sdma.num_instances; i++) { - f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL)); + f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, AUTO_CTXSW_ENABLE, enable ? 1 : 0); if (enable && amdgpu_sdma_phase_quantum) { - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE0_QUANTUM), + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), phase_quantum); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE1_QUANTUM), + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), phase_quantum); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE2_QUANTUM), + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), phase_quantum); } - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), f32_cntl); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); } } @@ -557,9 +545,9 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) } for (i = 0; i < adev->sdma.num_instances; i++) { - f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL)); + f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), f32_cntl); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); } } @@ -587,48 +575,48 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) ring = &adev->sdma.instance[i].ring; wb_offset = (ring->rptr_offs * 4); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); /* Set ring buffer size in dwords */ rb_bufsz = order_base_2(ring->ring_size / 4); - rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); #ifdef __BIG_ENDIAN rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_SWAP_ENABLE, 1); #endif - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); /* Initialize the ring buffer's read and write pointers */ - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR), 0); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_HI), 0); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), 0); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), 0); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); /* set the wb address whether it's enabled or not */ - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); ring->wptr = 0; /* before programing wptr to a less value, need set minor_ptr_update first */ - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); } - doorbell = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL)); - doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET)); + doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); + doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); if (ring->use_doorbell) { doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); @@ -637,8 +625,8 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) } else { doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); } - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); if (adev->flags & AMD_IS_APU) nbio_v7_0_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); else @@ -648,44 +636,44 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) sdma_v4_0_ring_set_wptr(ring); /* set minor_ptr_update to 0 after wptr programed */ - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); /* set utc l1 enable flag always to 1 */ - temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL)); + temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), temp); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); if (!amdgpu_sriov_vf(adev)) { /* unhalt engine */ - temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL)); + temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); } /* setup the wptr shadow polling */ wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), lower_32_bits(wptr_gpu_addr)); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), upper_32_bits(wptr_gpu_addr)); - wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); + wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); if (amdgpu_sriov_vf(adev)) wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); else wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl); /* enable DMA RB */ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL)); + ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); #ifdef __BIG_ENDIAN ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); #endif /* enable DMA IBs */ - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); ring->ready = true; @@ -816,12 +804,12 @@ static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), 0); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); for (j = 0; j < fw_size; j++) - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); - WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); + WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); } return 0; @@ -1317,7 +1305,7 @@ static bool sdma_v4_0_is_idle(void *handle) u32 i; for (i = 0; i < adev->sdma.num_instances; i++) { - u32 tmp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_STATUS_REG)); + u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) return false; @@ -1333,8 +1321,8 @@ static int sdma_v4_0_wait_for_idle(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { - sdma0 = RREG32(sdma_v4_0_get_reg_offset(0, mmSDMA0_STATUS_REG)); - sdma1 = RREG32(sdma_v4_0_get_reg_offset(1, mmSDMA0_STATUS_REG)); + sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); + sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) return 0; @@ -1358,8 +1346,8 @@ static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, u32 sdma_cntl; u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? - sdma_v4_0_get_reg_offset(0, mmSDMA0_CNTL) : - sdma_v4_0_get_reg_offset(1, mmSDMA0_CNTL); + sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : + sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); sdma_cntl = RREG32(reg_offset); sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index 7a8e4e28abb2..62a6e218e748 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -54,42 +54,24 @@ struct nbio_pcie_index_data { (ip##_BASE__INST##inst##_SEG4 + reg))))) #define WREG32_FIELD15(ip, idx, reg, field, val) \ - WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) + WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ + (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ + & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) #define RREG32_SOC15(ip, inst, reg) \ - RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \ - (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \ - (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \ - (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \ - (ip##_BASE__INST##inst##_SEG4 + reg)))))) + RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \ - RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \ - (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \ - (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \ - (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \ - (ip##_BASE__INST##inst##_SEG4 + reg))))) + offset) + RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset) #define WREG32_SOC15(ip, inst, reg, value) \ - WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \ - (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \ - (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \ - (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \ - (ip##_BASE__INST##inst##_SEG4 + reg))))), value) + WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ - WREG32_NO_KIQ( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \ - (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \ - (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \ - (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \ - (ip##_BASE__INST##inst##_SEG4 + reg))))), value) + WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ - WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \ - (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \ - (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \ - (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \ - (ip##_BASE__INST##inst##_SEG4 + reg))))) + offset, value) + WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value) #endif -- GitLab From 946a4d5b301028621791e6c8b53f64c426dea1a5 Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Tue, 28 Nov 2017 17:01:21 -0500 Subject: [PATCH 1138/2547] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array Handle dynamic offsets correctly in static arrays. Acked-by: Christian Konig Signed-off-by: Shaoyun Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 19 ++ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 233 ++++++++-------------- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 20 +- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 45 +++-- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 3 +- drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 45 +++-- drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h | 3 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 101 +++++----- drivers/gpu/drm/amd/amdgpu/soc15.c | 115 +++++++---- drivers/gpu/drm/amd/amdgpu/soc15.h | 18 ++ drivers/gpu/drm/amd/amdgpu/soc15_common.h | 6 - drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 14 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 15 +- 13 files changed, 354 insertions(+), 283 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 9b09e938a802..e329faa6166f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1428,6 +1428,23 @@ typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); + +/* + * amdgpu nbio functions + * + * Fix me : + * Put more NBIO specifc func wraper here , for now just try to minimize the + * change to avoid use SOC15_REG_OFFSET in the constant array + */ + +struct amdgpu_nbio_funcs { + u32 (*get_hdp_flush_req_offset)(struct amdgpu_device*); + u32 (*get_hdp_flush_done_offset)(struct amdgpu_device*); + u32 (*get_pcie_index_offset)(struct amdgpu_device*); + u32 (*get_pcie_data_offset)(struct amdgpu_device*); +}; + + /* Define the HW IP blocks will be used in driver , add more if necessary */ enum amd_hw_ip_block_type { GC_HWIP = 1, @@ -1647,6 +1664,8 @@ struct amdgpu_device { /* soc15 register offset based on ip, instance and segment */ uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; + const struct amdgpu_nbio_funcs *nbio_funcs; + /* delayed work_func for deferring clockgating during resume */ struct delayed_work late_init_work; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 6c5289ae67be..b6122364565e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -65,152 +65,84 @@ MODULE_FIRMWARE("amdgpu/raven_mec.bin"); MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); -static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = -{ - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)}, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) }, - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), - SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) } +static const struct soc15_reg_golden golden_settings_gc_9_0[] = +{ + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) }; -static const u32 golden_settings_gc_9_0[] = -{ - SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420, - SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000, - SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024, - SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001, - SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000, - SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000, - SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107, - SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000, - SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, - SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68, - SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197, - SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000, - SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff, - SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080 -}; - -static const u32 golden_settings_gc_9_0_vg10[] = +static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = { - SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107, - SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000, - SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042, - SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042, - SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000, - SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000, - SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800 + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800) }; -static const u32 golden_settings_gc_9_1[] = -{ - SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104, - SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420, - SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000, - SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024, - SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001, - SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000, - SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080, - SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, - SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000, - SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120, - SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000, - SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff, - SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080 +static const struct soc15_reg_golden golden_settings_gc_9_1[] = +{ + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) }; -static const u32 golden_settings_gc_9_1_rv1[] = +static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = { - SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000, - SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042, - SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042, - SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000, - SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000, - SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000, - SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800 + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) }; -static const u32 golden_settings_gc_9_x_common[] = +static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = { - SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000, - SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382 + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) }; #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 @@ -230,18 +162,18 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_VEGA10: - amdgpu_program_register_sequence(adev, + soc15_program_register_sequence(adev, golden_settings_gc_9_0, ARRAY_SIZE(golden_settings_gc_9_0)); - amdgpu_program_register_sequence(adev, + soc15_program_register_sequence(adev, golden_settings_gc_9_0_vg10, ARRAY_SIZE(golden_settings_gc_9_0_vg10)); break; case CHIP_RAVEN: - amdgpu_program_register_sequence(adev, + soc15_program_register_sequence(adev, golden_settings_gc_9_1, ARRAY_SIZE(golden_settings_gc_9_1)); - amdgpu_program_register_sequence(adev, + soc15_program_register_sequence(adev, golden_settings_gc_9_1_rv1, ARRAY_SIZE(golden_settings_gc_9_1_rv1)); break; @@ -249,7 +181,7 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) break; } - amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common, + soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); } @@ -1137,7 +1069,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; - adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base; + adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; /* Primitive Buffer */ @@ -1243,7 +1175,7 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) } gfx_v9_0_write_data_to_reg(ring, 0, false, - amdgpu_gds_reg_offset[0].mem_size, + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), (adev->gds.mem.total_size + adev->gfx.ngg.gds_reserve_size) >> AMDGPU_GDS_SHIFT); @@ -1259,7 +1191,7 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) gfx_v9_0_write_data_to_reg(ring, 0, false, - amdgpu_gds_reg_offset[0].mem_size, 0); + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); amdgpu_ring_commit(ring); @@ -3146,6 +3078,8 @@ static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, uint32_t gws_base, uint32_t gws_size, uint32_t oa_base, uint32_t oa_size) { + struct amdgpu_device *adev = ring->adev; + gds_base = gds_base >> AMDGPU_GDS_SHIFT; gds_size = gds_size >> AMDGPU_GDS_SHIFT; @@ -3157,22 +3091,22 @@ static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, /* GDS Base */ gfx_v9_0_write_data_to_reg(ring, 0, false, - amdgpu_gds_reg_offset[vmid].mem_base, + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, gds_base); /* GDS Size */ gfx_v9_0_write_data_to_reg(ring, 0, false, - amdgpu_gds_reg_offset[vmid].mem_size, + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, gds_size); /* GWS */ gfx_v9_0_write_data_to_reg(ring, 0, false, - amdgpu_gds_reg_offset[vmid].gws, + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); /* OA */ gfx_v9_0_write_data_to_reg(ring, 0, false, - amdgpu_gds_reg_offset[vmid].oa, + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, (1 << (oa_size + oa_base)) - (1 << oa_base)); } @@ -3617,6 +3551,7 @@ static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { + struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; const struct nbio_hdp_flush_reg *nbio_hf_reg; @@ -3643,8 +3578,8 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) } gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, - nbio_hf_reg->hdp_flush_req_offset, - nbio_hf_reg->hdp_flush_done_offset, + adev->nbio_funcs->get_hdp_flush_req_offset(adev), + adev->nbio_funcs->get_hdp_flush_done_offset(adev), ref_and_mask, ref_and_mask, 0x20); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index cc972153d401..8e6776f2986e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -35,6 +35,7 @@ #include "mmhub/mmhub_1_0_offset.h" #include "athub/athub_1_0_offset.h" +#include "soc15.h" #include "soc15_common.h" #include "umc/umc_6_0_sh_mask.h" @@ -74,16 +75,16 @@ static const u32 golden_settings_vega10_hdp[] = 0xf6e, 0x0fffffff, 0x00000000, }; -static const u32 golden_settings_mmhub_1_0_0[] = +static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { - SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa, - SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565 + SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), + SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) }; -static const u32 golden_settings_athub_1_0_0[] = +static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { - SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800, - SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008 + SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), + SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) }; /* Ecc related register addresses, (BASE + reg offset) */ @@ -883,17 +884,18 @@ static int gmc_v9_0_sw_fini(void *handle) static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) { + switch (adev->asic_type) { case CHIP_VEGA10: - amdgpu_program_register_sequence(adev, + soc15_program_register_sequence(adev, golden_settings_mmhub_1_0_0, ARRAY_SIZE(golden_settings_mmhub_1_0_0)); - amdgpu_program_register_sequence(adev, + soc15_program_register_sequence(adev, golden_settings_athub_1_0_0, ARRAY_SIZE(golden_settings_athub_1_0_0)); break; case CHIP_RAVEN: - amdgpu_program_register_sequence(adev, + soc15_program_register_sequence(adev, golden_settings_athub_1_0_0, ARRAY_SIZE(golden_settings_athub_1_0_0)); break; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index 76db711097c7..0d3272ef7e57 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -76,16 +76,13 @@ u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE); } -static const u32 nbio_sdma_doorbell_range_reg[] = -{ - SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE), - SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) -}; - void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, bool use_doorbell, int doorbell_index) { - u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]); + u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : + SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); + + u32 doorbell_range = RREG32(reg); if (use_doorbell) { doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); @@ -93,7 +90,8 @@ void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, } else doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); - WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range); + WREG32(reg, doorbell_range); + } void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev, @@ -215,9 +213,27 @@ void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) *flags |= AMD_CG_SUPPORT_BIF_LS; } +static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ); +} + +static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE); +} + +static u32 get_pcie_index_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX); +} + +static u32 get_pcie_data_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA); +} + const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = { - .hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ), - .hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE), .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, @@ -232,11 +248,14 @@ const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = { .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK }; -const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data = { - .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX), - .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA), +const struct amdgpu_nbio_funcs nbio_v6_1_funcs = { + .get_hdp_flush_req_offset = get_hdp_flush_req_offset, + .get_hdp_flush_done_offset = get_hdp_flush_done_offset, + .get_pcie_index_offset = get_pcie_index_offset, + .get_pcie_data_offset = get_pcie_data_offset, }; + void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev) { uint32_t reg; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h index 14ca8d45a46c..973effed27e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h @@ -27,7 +27,8 @@ #include "soc15_common.h" extern const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg; -extern const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data; +extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs; + int nbio_v6_1_init(struct amdgpu_device *adev); u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev, uint32_t idx); diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index 1fb77174e02c..4220648c31ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -32,6 +32,7 @@ #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c + u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev) { u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); @@ -73,16 +74,13 @@ u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); } -static const u32 nbio_sdma_doorbell_range_reg[] = -{ - SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE), - SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) -}; - void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance, bool use_doorbell, int doorbell_index) { - u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]); + u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : + SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); + + u32 doorbell_range = RREG32(reg); if (use_doorbell) { doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); @@ -90,7 +88,7 @@ void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance, } else doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); - WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range); + WREG32(reg, doorbell_range); } void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev, @@ -185,9 +183,27 @@ void nbio_v7_0_ih_control(struct amdgpu_device *adev) WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); } +static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); +} + +static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); +} + +static u32 get_pcie_index_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); +} + +static u32 get_pcie_data_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); +} + const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = { - .hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ), - .hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE), .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, @@ -202,7 +218,10 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = { .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, }; -const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data = { - .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), - .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2) +const struct amdgpu_nbio_funcs nbio_v7_0_funcs = { + .get_hdp_flush_req_offset = get_hdp_flush_req_offset, + .get_hdp_flush_done_offset = get_hdp_flush_done_offset, + .get_pcie_index_offset = get_pcie_index_offset, + .get_pcie_data_offset = get_pcie_data_offset, }; + diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h index df8fa90f40d7..070c3bdf5739 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h @@ -27,7 +27,8 @@ #include "soc15_common.h" extern const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg; -extern const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data; +extern const struct amdgpu_nbio_funcs nbio_v7_0_funcs; + int nbio_v7_0_init(struct amdgpu_device *adev); u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev, uint32_t idx); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 458667dd8fd7..5c98c4dacf07 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -53,58 +53,58 @@ static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); -static const u32 golden_settings_sdma_4[] = { - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL), 0x800f0100, 0x00000100, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0x003ff006, 0x0003c000, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0100, 0x00000100, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0100, 0x00000100, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CHICKEN_BITS), 0xfe931f07, 0x02831f07, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), 0xffffffff, 0x3f000100, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_IB_CNTL), 0x800f0100, 0x00000100, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL), 0x800f0100, 0x00000100, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), 0x003ff000, 0x0003c000, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL), 0x800f0100, 0x00000100, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL), 0x800f0100, 0x00000100, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0 +static const struct soc15_reg_golden golden_settings_sdma_4[] = { + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0) }; -static const u32 golden_settings_sdma_vg10[] = { - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002, - SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002 +static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) }; -static const u32 golden_settings_sdma_4_1[] = +static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0xfc3fffff, 0x40000051, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0111, 0x00000100, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0111, 0x00000100, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0 + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0) }; -static const u32 golden_settings_sdma_rv1[] = +static const struct soc15_reg_golden golden_settings_sdma_rv1[] = { - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00000002, - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00000002 + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) }; static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, @@ -118,18 +118,18 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_VEGA10: - amdgpu_program_register_sequence(adev, + soc15_program_register_sequence(adev, golden_settings_sdma_4, ARRAY_SIZE(golden_settings_sdma_4)); - amdgpu_program_register_sequence(adev, + soc15_program_register_sequence(adev, golden_settings_sdma_vg10, ARRAY_SIZE(golden_settings_sdma_vg10)); break; case CHIP_RAVEN: - amdgpu_program_register_sequence(adev, + soc15_program_register_sequence(adev, golden_settings_sdma_4_1, ARRAY_SIZE(golden_settings_sdma_4_1)); - amdgpu_program_register_sequence(adev, + soc15_program_register_sequence(adev, golden_settings_sdma_rv1, ARRAY_SIZE(golden_settings_sdma_rv1)); break; @@ -358,6 +358,7 @@ static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, */ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { + struct amdgpu_device *adev = ring->adev; u32 ref_and_mask = 0; const struct nbio_hdp_flush_reg *nbio_hf_reg; @@ -374,8 +375,8 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ - amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_done_offset << 2); - amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_req_offset << 2); + amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2); + amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2); amdgpu_ring_write(ring, ref_and_mask); /* reference */ amdgpu_ring_write(ring, ref_and_mask); /* mask */ amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 7c88bcb6c305..fb5f825e8924 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -101,15 +101,8 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) { unsigned long flags, address, data; u32 r; - const struct nbio_pcie_index_data *nbio_pcie_id; - - if (adev->flags & AMD_IS_APU) - nbio_pcie_id = &nbio_v7_0_pcie_index_data; - else - nbio_pcie_id = &nbio_v6_1_pcie_index_data; - - address = nbio_pcie_id->index_offset; - data = nbio_pcie_id->data_offset; + address = adev->nbio_funcs->get_pcie_index_offset(adev); + data = adev->nbio_funcs->get_pcie_data_offset(adev); spin_lock_irqsave(&adev->pcie_idx_lock, flags); WREG32(address, reg); @@ -122,15 +115,9 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags, address, data; - const struct nbio_pcie_index_data *nbio_pcie_id; - - if (adev->flags & AMD_IS_APU) - nbio_pcie_id = &nbio_v7_0_pcie_index_data; - else - nbio_pcie_id = &nbio_v6_1_pcie_index_data; - address = nbio_pcie_id->index_offset; - data = nbio_pcie_id->data_offset; + address = adev->nbio_funcs->get_pcie_index_offset(adev); + data = adev->nbio_funcs->get_pcie_data_offset(adev); spin_lock_irqsave(&adev->pcie_idx_lock, flags); WREG32(address, reg); @@ -332,25 +319,34 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, return true; } -static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = { - { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)}, - { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)}, - { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)}, - { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)}, - { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)}, - { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)}, - { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG)}, - { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG)}, - { SOC15_REG_OFFSET(GC, 0, mmCP_STAT)}, - { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)}, - { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)}, - { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)}, - { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)}, - { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)}, - { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)}, - { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)}, - { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)}, - { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)}, +struct soc15_allowed_register_entry { + uint32_t hwip; + uint32_t inst; + uint32_t seg; + uint32_t reg_offset; + bool grbm_indexed; +}; + + +static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { + { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, + { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, + { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, + { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, + { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, + { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, + { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, + { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, + { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, + { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, + { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, + { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, + { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, + { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, + { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, + { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, + { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, + { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, }; static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, @@ -390,10 +386,13 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) { uint32_t i; + struct soc15_allowed_register_entry *en; *value = 0; for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { - if (reg_offset != soc15_allowed_read_registers[i].reg_offset) + en = &soc15_allowed_read_registers[i]; + if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] + + en->reg_offset)) continue; *value = soc15_get_register_value(adev, @@ -404,6 +403,43 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, return -EINVAL; } + +/** + * soc15_program_register_sequence - program an array of registers. + * + * @adev: amdgpu_device pointer + * @regs: pointer to the register array + * @array_size: size of the register array + * + * Programs an array or registers with and and or masks. + * This is a helper for setting golden registers. + */ + +void soc15_program_register_sequence(struct amdgpu_device *adev, + const struct soc15_reg_golden *regs, + const u32 array_size) +{ + const struct soc15_reg_golden *entry; + u32 tmp, reg; + int i; + + for (i = 0; i < array_size; ++i) { + entry = ®s[i]; + reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; + + if (entry->and_mask == 0xffffffff) { + tmp = entry->or_mask; + } else { + tmp = RREG32(reg); + tmp &= ~(entry->and_mask); + tmp |= entry->or_mask; + } + WREG32(reg, tmp); + } + +} + + static int soc15_asic_reset(struct amdgpu_device *adev) { u32 i; @@ -619,6 +655,11 @@ static int soc15_common_early_init(void *handle) adev->asic_funcs = &soc15_asic_funcs; + if (adev->flags & AMD_IS_APU) + adev->nbio_funcs = &nbio_v7_0_funcs; + else + adev->nbio_funcs = &nbio_v6_1_funcs; + if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) psp_enabled = true; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h index c34496f1fc78..26b3feac5d06 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h @@ -29,10 +29,28 @@ extern const struct amd_ip_funcs soc15_common_ip_funcs; +struct soc15_reg_golden { + u32 hwip; + u32 instance; + u32 segment; + u32 reg; + u32 and_mask; + u32 or_mask; +}; + +#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg + +#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \ + { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask } + void soc15_grbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); int soc15_set_ip_blocks(struct amdgpu_device *adev); +void soc15_program_register_sequence(struct amdgpu_device *adev, + const struct soc15_reg_golden *registers, + const u32 array_size); + int vega10_reg_base_init(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index 62a6e218e748..e2207c5745f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -25,8 +25,6 @@ #define __SOC15_COMMON_H__ struct nbio_hdp_flush_reg { - u32 hdp_flush_req_offset; - u32 hdp_flush_done_offset; u32 ref_and_mask_cp0; u32 ref_and_mask_cp1; u32 ref_and_mask_cp2; @@ -41,10 +39,6 @@ struct nbio_hdp_flush_reg { u32 ref_and_mask_sdma1; }; -struct nbio_pcie_index_data { - u32 index_offset; - u32 data_offset; -}; /* Register Access Macros */ #define SOC15_REG_OFFSET(ip, inst, reg) (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \ diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 416611150edd..dfaf9cb8a320 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -1314,6 +1314,16 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, uvd_v7_0_vm_reg_wait(ring, data0, data1, mask); } +static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) +{ + int i; + struct amdgpu_device *adev = ring->adev; + + for (i = 0; i < count; i++) + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); + +} + static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring) { amdgpu_ring_write(ring, HEVC_ENC_CMD_END); @@ -1681,7 +1691,7 @@ const struct amd_ip_funcs uvd_v7_0_ip_funcs = { static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_UVD, .align_mask = 0xf, - .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0), + .nop = PACKET0(0x81ff, 0), .support_64bit_ptrs = false, .vmhub = AMDGPU_MMHUB, .get_rptr = uvd_v7_0_ring_get_rptr, @@ -1700,7 +1710,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { .emit_hdp_invalidate = uvd_v7_0_ring_emit_hdp_invalidate, .test_ring = uvd_v7_0_ring_test_ring, .test_ib = amdgpu_uvd_ring_test_ib, - .insert_nop = amdgpu_ring_insert_nop, + .insert_nop = uvd_v7_0_ring_insert_nop, .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_uvd_ring_begin_use, .end_use = amdgpu_uvd_ring_end_use, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index e4673f792545..6f7a7676a152 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -1077,6 +1077,17 @@ static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, return 0; } +static void vcn_v1_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) +{ + int i; + struct amdgpu_device *adev = ring->adev; + + for (i = 0; i < count; i++) + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); + +} + + static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { .name = "vcn_v1_0", .early_init = vcn_v1_0_early_init, @@ -1100,7 +1111,7 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_DEC, .align_mask = 0xf, - .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0), + .nop = PACKET0(0x81ff, 0), .support_64bit_ptrs = false, .vmhub = AMDGPU_MMHUB, .get_rptr = vcn_v1_0_dec_ring_get_rptr, @@ -1118,7 +1129,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { .emit_hdp_invalidate = vcn_v1_0_dec_ring_emit_hdp_invalidate, .test_ring = amdgpu_vcn_dec_ring_test_ring, .test_ib = amdgpu_vcn_dec_ring_test_ib, - .insert_nop = amdgpu_ring_insert_nop, + .insert_nop = vcn_v1_0_ring_insert_nop, .insert_start = vcn_v1_0_dec_ring_insert_start, .insert_end = vcn_v1_0_dec_ring_insert_end, .pad_ib = amdgpu_ring_generic_pad_ib, -- GitLab From bd3486ded7a0c313a6575343e6c2b21d14476645 Mon Sep 17 00:00:00 2001 From: Bin Liu Date: Tue, 5 Dec 2017 08:45:30 -0600 Subject: [PATCH 1139/2547] usb: musb: da8xx: fix babble condition handling When babble condition happens, the musb controller might automatically turns off VBUS. On DA8xx platform, the controller generates drvvbus interrupt for turning off VBUS along with the babble interrupt. In this case, we should handle the babble interrupt first and recover from the babble condition. This change ignores the drvvbus interrupt if babble interrupt is also generated at the same time, so the babble recovery routine works properly. Cc: stable@vger.kernel.org # v3.16+ Signed-off-by: Bin Liu Signed-off-by: Greg Kroah-Hartman --- drivers/usb/musb/da8xx.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c index 0397606a211b..6c036de63272 100644 --- a/drivers/usb/musb/da8xx.c +++ b/drivers/usb/musb/da8xx.c @@ -284,7 +284,15 @@ static irqreturn_t da8xx_musb_interrupt(int irq, void *hci) musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; portstate(musb->port1_status |= USB_PORT_STAT_POWER); del_timer(&musb->dev_timer); - } else { + } else if (!(musb->int_usb & MUSB_INTR_BABBLE)) { + /* + * When babble condition happens, drvvbus interrupt + * is also generated. Ignore this drvvbus interrupt + * and let babble interrupt handler recovers the + * controller; otherwise, the host-mode flag is lost + * due to the MUSB_DEV_MODE() call below and babble + * recovery logic will not be called. + */ musb->is_active = 0; MUSB_DEV_MODE(musb); otg->default_a = 0; -- GitLab From 62354454625741f0569c2cbe45b2d192f8fd258e Mon Sep 17 00:00:00 2001 From: David Kozub Date: Tue, 5 Dec 2017 22:40:04 +0100 Subject: [PATCH 1140/2547] USB: uas and storage: Add US_FL_BROKEN_FUA for another JMicron JMS567 ID There is another JMS567-based USB3 UAS enclosure (152d:0578) that fails with the following error: [sda] tag#0 FAILED Result: hostbyte=DID_OK driverbyte=DRIVER_SENSE [sda] tag#0 Sense Key : Illegal Request [current] [sda] tag#0 Add. Sense: Invalid field in cdb The issue occurs both with UAS (occasionally) and mass storage (immediately after mounting a FS on a disk in the enclosure). Enabling US_FL_BROKEN_FUA quirk solves this issue. This patch adds an UNUSUAL_DEV with US_FL_BROKEN_FUA for the enclosure for both UAS and mass storage. Signed-off-by: David Kozub Acked-by: Alan Stern Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/storage/unusual_devs.h | 7 +++++++ drivers/usb/storage/unusual_uas.h | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h index 2968046e7c05..f72d045ee9ef 100644 --- a/drivers/usb/storage/unusual_devs.h +++ b/drivers/usb/storage/unusual_devs.h @@ -2100,6 +2100,13 @@ UNUSUAL_DEV( 0x152d, 0x0567, 0x0114, 0x0116, USB_SC_DEVICE, USB_PR_DEVICE, NULL, US_FL_BROKEN_FUA ), +/* Reported by David Kozub */ +UNUSUAL_DEV(0x152d, 0x0578, 0x0000, 0x9999, + "JMicron", + "JMS567", + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + US_FL_BROKEN_FUA), + /* * Reported by Alexandre Oliva * JMicron responds to USN and several other SCSI ioctls with a diff --git a/drivers/usb/storage/unusual_uas.h b/drivers/usb/storage/unusual_uas.h index d520374a824e..e6127fb21c12 100644 --- a/drivers/usb/storage/unusual_uas.h +++ b/drivers/usb/storage/unusual_uas.h @@ -129,6 +129,13 @@ UNUSUAL_DEV(0x152d, 0x0567, 0x0000, 0x9999, USB_SC_DEVICE, USB_PR_DEVICE, NULL, US_FL_BROKEN_FUA | US_FL_NO_REPORT_OPCODES), +/* Reported-by: David Kozub */ +UNUSUAL_DEV(0x152d, 0x0578, 0x0000, 0x9999, + "JMicron", + "JMS567", + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + US_FL_BROKEN_FUA), + /* Reported-by: Hans de Goede */ UNUSUAL_DEV(0x2109, 0x0711, 0x0000, 0x9999, "VIA", -- GitLab From 82a2b827c96883d8b39a58bba23d222d6b0de7ff Mon Sep 17 00:00:00 2001 From: Julien BOIBESSOT Date: Tue, 5 Dec 2017 16:09:04 +0100 Subject: [PATCH 1141/2547] tools/usbip: fixes potential (minor) "buffer overflow" (detected on recent gcc with -Werror) Fixes following build error: vhci_driver.c: In function 'refresh_imported_device_list': vhci_driver.c:118:37: error: 'snprintf' output may be truncated before the last format character [-Werror=format-truncation=] snprintf(status, sizeof(status), "status.%d", i); ^~~~~~~~~~~ vhci_driver.c:118:4: note: 'snprintf' output between 9 and 18 bytes into a destination of size 17 snprintf(status, sizeof(status), "status.%d", i); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Signed-off-by: Julien BOIBESSOT Acked-by: Shuah Khan Signed-off-by: Greg Kroah-Hartman --- tools/usb/usbip/libsrc/vhci_driver.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/usb/usbip/libsrc/vhci_driver.c b/tools/usb/usbip/libsrc/vhci_driver.c index 8a1cd1616de4..627d1dfc332b 100644 --- a/tools/usb/usbip/libsrc/vhci_driver.c +++ b/tools/usb/usbip/libsrc/vhci_driver.c @@ -106,7 +106,7 @@ static int parse_status(const char *value) return 0; } -#define MAX_STATUS_NAME 16 +#define MAX_STATUS_NAME 18 static int refresh_imported_device_list(void) { -- GitLab From 635f545a7e8be7596b9b2b6a43cab6bbd5a88e43 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Thu, 7 Dec 2017 14:16:47 -0700 Subject: [PATCH 1142/2547] usbip: fix stub_rx: get_pipe() to validate endpoint number get_pipe() routine doesn't validate the input endpoint number and uses to reference ep_in and ep_out arrays. Invalid endpoint number can trigger BUG(). Range check the epnum and returning error instead of calling BUG(). Change caller stub_recv_cmd_submit() to handle the get_pipe() error return. Reported-by: Secunia Research Cc: stable Signed-off-by: Shuah Khan Signed-off-by: Greg Kroah-Hartman --- drivers/usb/usbip/stub_rx.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/usb/usbip/stub_rx.c b/drivers/usb/usbip/stub_rx.c index 536e037f541f..4d61063c259d 100644 --- a/drivers/usb/usbip/stub_rx.c +++ b/drivers/usb/usbip/stub_rx.c @@ -328,15 +328,15 @@ static int get_pipe(struct stub_device *sdev, int epnum, int dir) struct usb_host_endpoint *ep; struct usb_endpoint_descriptor *epd = NULL; + if (epnum < 0 || epnum > 15) + goto err_ret; + if (dir == USBIP_DIR_IN) ep = udev->ep_in[epnum & 0x7f]; else ep = udev->ep_out[epnum & 0x7f]; - if (!ep) { - dev_err(&sdev->udev->dev, "no such endpoint?, %d\n", - epnum); - BUG(); - } + if (!ep) + goto err_ret; epd = &ep->desc; if (usb_endpoint_xfer_control(epd)) { @@ -367,9 +367,10 @@ static int get_pipe(struct stub_device *sdev, int epnum, int dir) return usb_rcvisocpipe(udev, epnum); } +err_ret: /* NOT REACHED */ - dev_err(&sdev->udev->dev, "get pipe, epnum %d\n", epnum); - return 0; + dev_err(&sdev->udev->dev, "get pipe() invalid epnum %d\n", epnum); + return -1; } static void masking_bogus_flags(struct urb *urb) @@ -435,6 +436,9 @@ static void stub_recv_cmd_submit(struct stub_device *sdev, struct usb_device *udev = sdev->udev; int pipe = get_pipe(sdev, pdu->base.ep, pdu->base.direction); + if (pipe == -1) + return; + priv = stub_priv_alloc(sdev, pdu); if (!priv) return; -- GitLab From c6688ef9f29762e65bce325ef4acd6c675806366 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Thu, 7 Dec 2017 14:16:48 -0700 Subject: [PATCH 1143/2547] usbip: fix stub_rx: harden CMD_SUBMIT path to handle malicious input Harden CMD_SUBMIT path to handle malicious input that could trigger large memory allocations. Add checks to validate transfer_buffer_length and number_of_packets to protect against bad input requesting for unbounded memory allocations. Validate early in get_pipe() and return failure. Reported-by: Secunia Research Cc: stable Signed-off-by: Shuah Khan Signed-off-by: Greg Kroah-Hartman --- drivers/usb/usbip/stub_rx.c | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/usb/usbip/stub_rx.c b/drivers/usb/usbip/stub_rx.c index 4d61063c259d..493ac2928391 100644 --- a/drivers/usb/usbip/stub_rx.c +++ b/drivers/usb/usbip/stub_rx.c @@ -322,11 +322,13 @@ static struct stub_priv *stub_priv_alloc(struct stub_device *sdev, return priv; } -static int get_pipe(struct stub_device *sdev, int epnum, int dir) +static int get_pipe(struct stub_device *sdev, struct usbip_header *pdu) { struct usb_device *udev = sdev->udev; struct usb_host_endpoint *ep; struct usb_endpoint_descriptor *epd = NULL; + int epnum = pdu->base.ep; + int dir = pdu->base.direction; if (epnum < 0 || epnum > 15) goto err_ret; @@ -339,6 +341,15 @@ static int get_pipe(struct stub_device *sdev, int epnum, int dir) goto err_ret; epd = &ep->desc; + + /* validate transfer_buffer_length */ + if (pdu->u.cmd_submit.transfer_buffer_length > INT_MAX) { + dev_err(&sdev->udev->dev, + "CMD_SUBMIT: -EMSGSIZE transfer_buffer_length %d\n", + pdu->u.cmd_submit.transfer_buffer_length); + return -1; + } + if (usb_endpoint_xfer_control(epd)) { if (dir == USBIP_DIR_OUT) return usb_sndctrlpipe(udev, epnum); @@ -361,6 +372,21 @@ static int get_pipe(struct stub_device *sdev, int epnum, int dir) } if (usb_endpoint_xfer_isoc(epd)) { + /* validate packet size and number of packets */ + unsigned int maxp, packets, bytes; + + maxp = usb_endpoint_maxp(epd); + maxp *= usb_endpoint_maxp_mult(epd); + bytes = pdu->u.cmd_submit.transfer_buffer_length; + packets = DIV_ROUND_UP(bytes, maxp); + + if (pdu->u.cmd_submit.number_of_packets < 0 || + pdu->u.cmd_submit.number_of_packets > packets) { + dev_err(&sdev->udev->dev, + "CMD_SUBMIT: isoc invalid num packets %d\n", + pdu->u.cmd_submit.number_of_packets); + return -1; + } if (dir == USBIP_DIR_OUT) return usb_sndisocpipe(udev, epnum); else @@ -369,7 +395,7 @@ static int get_pipe(struct stub_device *sdev, int epnum, int dir) err_ret: /* NOT REACHED */ - dev_err(&sdev->udev->dev, "get pipe() invalid epnum %d\n", epnum); + dev_err(&sdev->udev->dev, "CMD_SUBMIT: invalid epnum %d\n", epnum); return -1; } @@ -434,7 +460,7 @@ static void stub_recv_cmd_submit(struct stub_device *sdev, struct stub_priv *priv; struct usbip_device *ud = &sdev->ud; struct usb_device *udev = sdev->udev; - int pipe = get_pipe(sdev, pdu->base.ep, pdu->base.direction); + int pipe = get_pipe(sdev, pdu); if (pipe == -1) return; @@ -456,7 +482,8 @@ static void stub_recv_cmd_submit(struct stub_device *sdev, } /* allocate urb transfer buffer, if needed */ - if (pdu->u.cmd_submit.transfer_buffer_length > 0) { + if (pdu->u.cmd_submit.transfer_buffer_length > 0 && + pdu->u.cmd_submit.transfer_buffer_length <= INT_MAX) { priv->urb->transfer_buffer = kzalloc(pdu->u.cmd_submit.transfer_buffer_length, GFP_KERNEL); -- GitLab From 2f2d0088eb93db5c649d2a5e34a3800a8a935fc5 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Thu, 7 Dec 2017 14:16:49 -0700 Subject: [PATCH 1144/2547] usbip: prevent vhci_hcd driver from leaking a socket pointer address When a client has a USB device attached over IP, the vhci_hcd driver is locally leaking a socket pointer address via the /sys/devices/platform/vhci_hcd/status file (world-readable) and in debug output when "usbip --debug port" is run. Fix it to not leak. The socket pointer address is not used at the moment and it was made visible as a convenient way to find IP address from socket pointer address by looking up /proc/net/{tcp,tcp6}. As this opens a security hole, the fix replaces socket pointer address with sockfd. Reported-by: Secunia Research Cc: stable Signed-off-by: Shuah Khan Signed-off-by: Greg Kroah-Hartman --- drivers/usb/usbip/usbip_common.h | 1 + drivers/usb/usbip/vhci_sysfs.c | 25 ++++++++++++++++--------- tools/usb/usbip/libsrc/vhci_driver.c | 8 ++++---- 3 files changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/usb/usbip/usbip_common.h b/drivers/usb/usbip/usbip_common.h index e5de35c8c505..473fb8a87289 100644 --- a/drivers/usb/usbip/usbip_common.h +++ b/drivers/usb/usbip/usbip_common.h @@ -256,6 +256,7 @@ struct usbip_device { /* lock for status */ spinlock_t lock; + int sockfd; struct socket *tcp_socket; struct task_struct *tcp_rx; diff --git a/drivers/usb/usbip/vhci_sysfs.c b/drivers/usb/usbip/vhci_sysfs.c index e78f7472cac4..091f76b7196d 100644 --- a/drivers/usb/usbip/vhci_sysfs.c +++ b/drivers/usb/usbip/vhci_sysfs.c @@ -17,15 +17,20 @@ /* * output example: - * hub port sta spd dev socket local_busid - * hs 0000 004 000 00000000 c5a7bb80 1-2.3 + * hub port sta spd dev sockfd local_busid + * hs 0000 004 000 00000000 3 1-2.3 * ................................................ - * ss 0008 004 000 00000000 d8cee980 2-3.4 + * ss 0008 004 000 00000000 4 2-3.4 * ................................................ * - * IP address can be retrieved from a socket pointer address by looking - * up /proc/net/{tcp,tcp6}. Also, a userland program may remember a - * port number and its peer IP address. + * Output includes socket fd instead of socket pointer address to avoid + * leaking kernel memory address in: + * /sys/devices/platform/vhci_hcd.0/status and in debug output. + * The socket pointer address is not used at the moment and it was made + * visible as a convenient way to find IP address from socket pointer + * address by looking up /proc/net/{tcp,tcp6}. As this opens a security + * hole, the change is made to use sockfd instead. + * */ static void port_show_vhci(char **out, int hub, int port, struct vhci_device *vdev) { @@ -39,8 +44,8 @@ static void port_show_vhci(char **out, int hub, int port, struct vhci_device *vd if (vdev->ud.status == VDEV_ST_USED) { *out += sprintf(*out, "%03u %08x ", vdev->speed, vdev->devid); - *out += sprintf(*out, "%16p %s", - vdev->ud.tcp_socket, + *out += sprintf(*out, "%u %s", + vdev->ud.sockfd, dev_name(&vdev->udev->dev)); } else { @@ -160,7 +165,8 @@ static ssize_t nports_show(struct device *dev, struct device_attribute *attr, char *s = out; /* - * Half the ports are for SPEED_HIGH and half for SPEED_SUPER, thus the * 2. + * Half the ports are for SPEED_HIGH and half for SPEED_SUPER, + * thus the * 2. */ out += sprintf(out, "%d\n", VHCI_PORTS * vhci_num_controllers); return out - s; @@ -366,6 +372,7 @@ static ssize_t store_attach(struct device *dev, struct device_attribute *attr, vdev->devid = devid; vdev->speed = speed; + vdev->ud.sockfd = sockfd; vdev->ud.tcp_socket = socket; vdev->ud.status = VDEV_ST_NOTASSIGNED; diff --git a/tools/usb/usbip/libsrc/vhci_driver.c b/tools/usb/usbip/libsrc/vhci_driver.c index 627d1dfc332b..c9c81614a66a 100644 --- a/tools/usb/usbip/libsrc/vhci_driver.c +++ b/tools/usb/usbip/libsrc/vhci_driver.c @@ -50,14 +50,14 @@ static int parse_status(const char *value) while (*c != '\0') { int port, status, speed, devid; - unsigned long socket; + int sockfd; char lbusid[SYSFS_BUS_ID_SIZE]; struct usbip_imported_device *idev; char hub[3]; - ret = sscanf(c, "%2s %d %d %d %x %lx %31s\n", + ret = sscanf(c, "%2s %d %d %d %x %u %31s\n", hub, &port, &status, &speed, - &devid, &socket, lbusid); + &devid, &sockfd, lbusid); if (ret < 5) { dbg("sscanf failed: %d", ret); @@ -66,7 +66,7 @@ static int parse_status(const char *value) dbg("hub %s port %d status %d speed %d devid %x", hub, port, status, speed, devid); - dbg("socket %lx lbusid %s", socket, lbusid); + dbg("sockfd %u lbusid %s", sockfd, lbusid); /* if a device is connected, look at it */ idev = &vhci_driver->idev[port]; -- GitLab From be6123df1ea8f01ee2f896a16c2b7be3e4557a5a Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Thu, 7 Dec 2017 14:16:50 -0700 Subject: [PATCH 1145/2547] usbip: fix stub_send_ret_submit() vulnerability to null transfer_buffer stub_send_ret_submit() handles urb with a potential null transfer_buffer, when it replays a packet with potential malicious data that could contain a null buffer. Add a check for the condition when actual_length > 0 and transfer_buffer is null. Reported-by: Secunia Research Cc: stable Signed-off-by: Shuah Khan Signed-off-by: Greg Kroah-Hartman --- drivers/usb/usbip/stub_tx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/usb/usbip/stub_tx.c b/drivers/usb/usbip/stub_tx.c index b18bce96c212..53172b1f6257 100644 --- a/drivers/usb/usbip/stub_tx.c +++ b/drivers/usb/usbip/stub_tx.c @@ -167,6 +167,13 @@ static int stub_send_ret_submit(struct stub_device *sdev) memset(&pdu_header, 0, sizeof(pdu_header)); memset(&msg, 0, sizeof(msg)); + if (urb->actual_length > 0 && !urb->transfer_buffer) { + dev_err(&sdev->udev->dev, + "urb: actual_length %d transfer_buffer null\n", + urb->actual_length); + return -1; + } + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) iovnum = 2 + urb->number_of_packets; else -- GitLab From cd29253f650a6ab27bae8c0b8c17fb8e71f864e8 Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Wed, 29 Nov 2017 13:51:32 -0500 Subject: [PATCH 1146/2547] drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offset Acked-by: Christian Konig Signed-off-by: Shaoyun Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 9 +++++---- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 9 +++++---- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/soc15.c | 7 ++----- drivers/gpu/drm/amd/amdgpu/soc15_common.h | 6 +----- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 +++++++++++++ drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 14 ++++++++++++++ 8 files changed, 46 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index b6122364565e..ec53c23d0f6b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3585,6 +3585,8 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) { + struct amdgpu_device *adev = ring->adev; + gfx_v9_0_write_data_to_reg(ring, 0, true, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); } @@ -3746,6 +3748,8 @@ static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned int flags) { + struct amdgpu_device *adev = ring->adev; + /* we only allocate 32bit for each seq wb address */ BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 78fe3f2917a0..acaf7891eeab 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -298,9 +298,10 @@ int psp_v10_0_cmd_submit(struct psp_context *psp, } static int -psp_v10_0_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, - unsigned int *sram_data_reg_offset, - enum AMDGPU_UCODE_ID ucode_id) +psp_v10_0_sram_map(struct amdgpu_device *adev, + unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, + unsigned int *sram_data_reg_offset, + enum AMDGPU_UCODE_ID ucode_id) { int ret = 0; @@ -395,7 +396,7 @@ bool psp_v10_0_compare_sram_data(struct psp_context *psp, uint32_t *ucode_mem = NULL; struct amdgpu_device *adev = psp->adev; - err = psp_v10_0_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset, + err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, &fw_sram_data_reg_offset, ucode_type); if (err) return false; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index e75a23d858ef..0b22e58733db 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -410,9 +410,10 @@ int psp_v3_1_cmd_submit(struct psp_context *psp, } static int -psp_v3_1_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, - unsigned int *sram_data_reg_offset, - enum AMDGPU_UCODE_ID ucode_id) +psp_v3_1_sram_map(struct amdgpu_device *adev, + unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, + unsigned int *sram_data_reg_offset, + enum AMDGPU_UCODE_ID ucode_id) { int ret = 0; @@ -507,7 +508,7 @@ bool psp_v3_1_compare_sram_data(struct psp_context *psp, uint32_t *ucode_mem = NULL; struct amdgpu_device *adev = psp->adev; - err = psp_v3_1_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset, + err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, &fw_sram_data_reg_offset, ucode_type); if (err) return false; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 5c98c4dacf07..d3b1e5069e65 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -385,6 +385,8 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) { + struct amdgpu_device *adev = ring->adev; + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE)); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index fb5f825e8924..47fafe8540cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -373,12 +373,9 @@ static uint32_t soc15_get_register_value(struct amdgpu_device *adev, if (indexed) { return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); } else { - switch (reg_offset) { - case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG): + if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) return adev->gfx.config.gb_addr_config; - default: - return RREG32(reg_offset); - } + return RREG32(reg_offset); } } diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index e2207c5745f0..413951c33983 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -41,11 +41,7 @@ struct nbio_hdp_flush_reg { /* Register Access Macros */ -#define SOC15_REG_OFFSET(ip, inst, reg) (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \ - (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \ - (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \ - (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \ - (ip##_BASE__INST##inst##_SEG4 + reg))))) +#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) #define WREG32_FIELD15(ip, idx, reg, field, val) \ WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index dfaf9cb8a320..b22adeb39653 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -1086,6 +1086,8 @@ static void uvd_v7_0_stop(struct amdgpu_device *adev) static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) { + struct amdgpu_device *adev = ring->adev; + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); amdgpu_ring_write(ring, @@ -1123,6 +1125,7 @@ static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) { + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); @@ -1141,6 +1144,8 @@ static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, */ static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { + struct amdgpu_device *adev = ring->adev; + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0)); amdgpu_ring_write(ring, 0); @@ -1155,6 +1160,8 @@ static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) */ static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) { + struct amdgpu_device *adev = ring->adev; + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0)); amdgpu_ring_write(ring, 1); } @@ -1214,6 +1221,8 @@ static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib, unsigned vm_id, bool ctx_switch) { + struct amdgpu_device *adev = ring->adev; + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); amdgpu_ring_write(ring, vm_id); @@ -1250,6 +1259,8 @@ static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring, uint32_t data0, uint32_t data1) { + struct amdgpu_device *adev = ring->adev; + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); amdgpu_ring_write(ring, data0); @@ -1264,6 +1275,8 @@ static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring, static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring, uint32_t data0, uint32_t data1, uint32_t mask) { + struct amdgpu_device *adev = ring->adev; + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); amdgpu_ring_write(ring, data0); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 6f7a7676a152..3f1ca8696704 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -744,6 +744,8 @@ static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) */ static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) { + struct amdgpu_device *adev = ring->adev; + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); amdgpu_ring_write(ring, 0); @@ -761,6 +763,8 @@ static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) */ static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) { + struct amdgpu_device *adev = ring->adev; + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); @@ -777,6 +781,8 @@ static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) { + struct amdgpu_device *adev = ring->adev; + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); amdgpu_ring_write(ring, @@ -812,6 +818,8 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 */ static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) { + struct amdgpu_device *adev = ring->adev; + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0)); amdgpu_ring_write(ring, 1); } @@ -828,6 +836,8 @@ static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib, unsigned vm_id, bool ctx_switch) { + struct amdgpu_device *adev = ring->adev; + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); amdgpu_ring_write(ring, vm_id); @@ -846,6 +856,8 @@ static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring, uint32_t data0, uint32_t data1) { + struct amdgpu_device *adev = ring->adev; + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); amdgpu_ring_write(ring, data0); @@ -860,6 +872,8 @@ static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring, static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring, uint32_t data0, uint32_t data1, uint32_t mask) { + struct amdgpu_device *adev = ring->adev; + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); amdgpu_ring_write(ring, data0); -- GitLab From 4fd09a19a6337b1a58d6de8777e2210cec55ae84 Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Wed, 29 Nov 2017 14:04:58 -0500 Subject: [PATCH 1147/2547] drm/admgpu: Reduce the usage of soc15ip.h Remove the header where it's not used. Acked-by: Christian Konig Signed-off-by: Shaoyun Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 - drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 - drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 - drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 1 - drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 1 - drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 1 - drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 1 - drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 1 - drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 - drivers/gpu/drm/amd/amdgpu/soc15.c | 1 - drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 1 - drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 1 - drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 - drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 -- 16 files changed, 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 88e204d537f5..837962118dbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -35,7 +35,6 @@ #include "soc15d.h" #include "soc15_common.h" -#include "soc15ip.h" #include "vcn/vcn_1_0_offset.h" /* 1 second timeout */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ec53c23d0f6b..50a1edb7c32e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -28,7 +28,6 @@ #include "soc15.h" #include "soc15d.h" -#include "soc15ip.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" #include "vega10_enum.h" diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index f1effadfbaa6..1d392f186e0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -23,7 +23,6 @@ #include "amdgpu.h" #include "gfxhub_v1_0.h" -#include "soc15ip.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" #include "gc/gc_9_0_default.h" diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 8e6776f2986e..aef5f70547ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -25,7 +25,6 @@ #include "gmc_v9_0.h" #include "amdgpu_atomfirmware.h" -#include "soc15ip.h" #include "hdp/hdp_4_0_offset.h" #include "hdp/hdp_4_0_sh_mask.h" #include "gc/gc_9_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index bd160d8700e0..0c5a76f88d35 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -23,7 +23,6 @@ #include "amdgpu.h" #include "mmhub_v1_0.h" -#include "soc15ip.h" #include "mmhub/mmhub_1_0_offset.h" #include "mmhub/mmhub_1_0_sh_mask.h" #include "mmhub/mmhub_1_0_default.h" diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index ad9054e3903c..71f56900d6fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -22,7 +22,6 @@ */ #include "amdgpu.h" -#include "soc15ip.h" #include "nbio/nbio_6_1_offset.h" #include "nbio/nbio_6_1_sh_mask.h" #include "gc/gc_9_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index 0d3272ef7e57..9a3546f8b42b 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -24,7 +24,6 @@ #include "amdgpu_atombios.h" #include "nbio_v6_1.h" -#include "soc15ip.h" #include "nbio/nbio_6_1_default.h" #include "nbio/nbio_6_1_offset.h" #include "nbio/nbio_6_1_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index 4220648c31ca..ce869f37a382 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -24,7 +24,6 @@ #include "amdgpu_atombios.h" #include "nbio_v7_0.h" -#include "soc15ip.h" #include "nbio/nbio_7_0_default.h" #include "nbio/nbio_7_0_offset.h" #include "nbio/nbio_7_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index acaf7891eeab..5a9fe24697f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -30,7 +30,6 @@ #include "soc15_common.h" #include "psp_v10_0.h" -#include "soc15ip.h" #include "mp/mp_10_0_offset.h" #include "gc/gc_9_1_offset.h" #include "sdma0/sdma0_4_1_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 0b22e58733db..19bd1934e63d 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -31,7 +31,6 @@ #include "soc15_common.h" #include "psp_v3_1.h" -#include "soc15ip.h" #include "mp/mp_9_0_offset.h" #include "mp/mp_9_0_sh_mask.h" #include "gc/gc_9_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index d3b1e5069e65..1fb51946a718 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -27,7 +27,6 @@ #include "amdgpu_ucode.h" #include "amdgpu_trace.h" -#include "soc15ip.h" #include "sdma0/sdma0_4_0_offset.h" #include "sdma0/sdma0_4_0_sh_mask.h" #include "sdma1/sdma1_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 47fafe8540cb..2752d8d3e5ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -34,7 +34,6 @@ #include "atom.h" #include "amd_pcie.h" -#include "soc15ip.h" #include "uvd/uvd_7_0_offset.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index b22adeb39653..23b446236c80 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -29,7 +29,6 @@ #include "soc15_common.h" #include "mmsch_v1_0.h" -#include "soc15ip.h" #include "uvd/uvd_7_0_offset.h" #include "uvd/uvd_7_0_sh_mask.h" #include "vce/vce_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index f2f713650074..55f01868a9b6 100755 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -32,7 +32,6 @@ #include "soc15_common.h" #include "mmsch_v1_0.h" -#include "soc15ip.h" #include "vce/vce_4_0_offset.h" #include "vce/vce_4_0_default.h" #include "vce/vce_4_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 3f1ca8696704..aa0787de51a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -28,7 +28,6 @@ #include "soc15d.h" #include "soc15_common.h" -#include "soc15ip.h" #include "vcn/vcn_1_0_offset.h" #include "vcn/vcn_1_0_sh_mask.h" #include "hdp/hdp_4_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index ca778cd4e6e8..a1d8bbbb269c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -25,8 +25,6 @@ #include "amdgpu_ih.h" #include "soc15.h" - -#include "soc15ip.h" #include "oss/osssys_4_0_offset.h" #include "oss/osssys_4_0_sh_mask.h" -- GitLab From 50dd2ea8ef67a1617e0c0658bcbec4b9fb03b936 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Fri, 8 Dec 2017 16:15:20 +0000 Subject: [PATCH 1148/2547] ASoC: wm_adsp: Fix validation of firmware and coeff lengths The checks for whether another region/block header could be present are subtracting the size from the current offset. Obviously we should instead subtract the offset from the size. The checks for whether the region/block data fit in the file are adding the data size to the current offset and header size, without checking for integer overflow. Rearrange these so that overflow is impossible. Signed-off-by: Ben Hutchings Acked-by: Charles Keepax Tested-by: Charles Keepax Signed-off-by: Mark Brown Cc: stable@vger.kernel.org --- sound/soc/codecs/wm_adsp.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c index 65c059b5ffd7..66e32f5d2917 100644 --- a/sound/soc/codecs/wm_adsp.c +++ b/sound/soc/codecs/wm_adsp.c @@ -1733,7 +1733,7 @@ static int wm_adsp_load(struct wm_adsp *dsp) le64_to_cpu(footer->timestamp)); while (pos < firmware->size && - pos - firmware->size > sizeof(*region)) { + sizeof(*region) < firmware->size - pos) { region = (void *)&(firmware->data[pos]); region_name = "Unknown"; reg = 0; @@ -1782,8 +1782,8 @@ static int wm_adsp_load(struct wm_adsp *dsp) regions, le32_to_cpu(region->len), offset, region_name); - if ((pos + le32_to_cpu(region->len) + sizeof(*region)) > - firmware->size) { + if (le32_to_cpu(region->len) > + firmware->size - pos - sizeof(*region)) { adsp_err(dsp, "%s.%d: %s region len %d bytes exceeds file length %zu\n", file, regions, region_name, @@ -2253,7 +2253,7 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) blocks = 0; while (pos < firmware->size && - pos - firmware->size > sizeof(*blk)) { + sizeof(*blk) < firmware->size - pos) { blk = (void *)(&firmware->data[pos]); type = le16_to_cpu(blk->type); @@ -2327,8 +2327,8 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) } if (reg) { - if ((pos + le32_to_cpu(blk->len) + sizeof(*blk)) > - firmware->size) { + if (le32_to_cpu(blk->len) > + firmware->size - pos - sizeof(*blk)) { adsp_err(dsp, "%s.%d: %s region len %d bytes exceeds file length %zu\n", file, blocks, region_name, -- GitLab From 5d9b70f7d52eb14bb37861c663bae44de9521c35 Mon Sep 17 00:00:00 2001 From: Mathias Nyman Date: Fri, 8 Dec 2017 18:10:05 +0200 Subject: [PATCH 1149/2547] xhci: Don't add a virt_dev to the devs array before it's fully allocated Avoid null pointer dereference if some function is walking through the devs array accessing members of a new virt_dev that is mid allocation. Add the virt_dev to xhci->devs[i] _after_ the virt_device and all its members are properly allocated. issue found by KASAN: null-ptr-deref in xhci_find_slot_id_by_port "Quick analysis suggests that xhci_alloc_virt_device() is not mutex protected. If so, there is a time frame where xhci->devs[slot_id] is set but not fully initialized. Specifically, xhci->devs[i]->udev can be NULL." Cc: stable Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-mem.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 15f7d422885f..3a29b32a3bd0 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -971,10 +971,9 @@ int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, return 0; } - xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags); - if (!xhci->devs[slot_id]) + dev = kzalloc(sizeof(*dev), flags); + if (!dev) return 0; - dev = xhci->devs[slot_id]; /* Allocate the (output) device context that will be used in the HC. */ dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags); @@ -1015,9 +1014,17 @@ int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, trace_xhci_alloc_virt_device(dev); + xhci->devs[slot_id] = dev; + return 1; fail: - xhci_free_virt_device(xhci, slot_id); + + if (dev->in_ctx) + xhci_free_container_ctx(xhci, dev->in_ctx); + if (dev->out_ctx) + xhci_free_container_ctx(xhci, dev->out_ctx); + kfree(dev); + return 0; } -- GitLab From 72b663a99c074a8d073e7ecdae446cfb024ef551 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Fri, 8 Dec 2017 18:10:06 +0200 Subject: [PATCH 1150/2547] usb: xhci: fix TDS for MTK xHCI1.1 For MTK's xHCI 1.0 or latter, TD size is the number of max packet sized packets remaining in the TD, not including this TRB (following spec). For MTK's xHCI 0.96 and older, TD size is the number of max packet sized packets remaining in the TD, including this TRB (not following spec). Cc: stable Signed-off-by: Chunfeng Yun Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-ring.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 6eb87c6e4d24..c5cbc685c691 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -3112,7 +3112,7 @@ static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, { u32 maxp, total_packet_count; - /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */ + /* MTK xHCI 0.96 contains some features from 1.0 */ if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) return ((td_total_len - transferred) >> 10); @@ -3121,8 +3121,8 @@ static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, trb_buff_len == td_total_len) return 0; - /* for MTK xHCI, TD size doesn't include this TRB */ - if (xhci->quirks & XHCI_MTK_HOST) + /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */ + if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100)) trb_buff_len = 0; maxp = usb_endpoint_maxp(&urb->ep->desc); -- GitLab From b6b5e8a691185606dfffff3198c89e3b4fd9d4f6 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Thu, 7 Dec 2017 18:44:23 +0200 Subject: [PATCH 1151/2547] gianfar: Disable EEE autoneg by default This controller does not support EEE, but it may connect to a PHY which supports EEE and advertises EEE by default, while its link partner also advertises EEE. If this happens, the PHY enters low power mode when the traffic rate is low and causes packet loss. This patch disables EEE advertisement by default for any PHY that gianfar connects to, to prevent the above unwanted outcome. Signed-off-by: Shaohui Xie Tested-by: Yangbo Lu Signed-off-by: Claudiu Manoil Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- drivers/net/ethernet/freescale/gianfar.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c index 81a73af0df31..7f837006bb6a 100644 --- a/drivers/net/ethernet/freescale/gianfar.c +++ b/drivers/net/ethernet/freescale/gianfar.c @@ -1792,6 +1792,7 @@ static int init_phy(struct net_device *dev) GFAR_SUPPORTED_GBIT : 0; phy_interface_t interface; struct phy_device *phydev; + struct ethtool_eee edata; priv->oldlink = 0; priv->oldspeed = 0; @@ -1816,6 +1817,10 @@ static int init_phy(struct net_device *dev) /* Add support for flow control, but don't advertise it by default */ phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause); + /* disable EEE autoneg, EEE not supported by eTSEC */ + memset(&edata, 0, sizeof(struct ethtool_eee)); + phy_ethtool_set_eee(phydev, &edata); + return 0; } -- GitLab From d4a7a8893d4cdbc89d79ac4aa704bf8d4b67b368 Mon Sep 17 00:00:00 2001 From: Bert Kenward Date: Thu, 7 Dec 2017 17:18:58 +0000 Subject: [PATCH 1152/2547] sfc: pass valid pointers from efx_enqueue_unwind The bytes_compl and pkts_compl pointers passed to efx_dequeue_buffers cannot be NULL. Add a paranoid warning to check this condition and fix the one case where they were NULL. efx_enqueue_unwind() is called very rarely, during error handling. Without this fix it would fail with a NULL pointer dereference in efx_dequeue_buffer, with efx_enqueue_skb in the call stack. Fixes: e9117e5099ea ("sfc: Firmware-Assisted TSO version 2") Reported-by: Jarod Wilson Signed-off-by: Bert Kenward Tested-by: Jarod Wilson Acked-by: Jarod Wilson Signed-off-by: David S. Miller --- drivers/net/ethernet/sfc/tx.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/sfc/tx.c b/drivers/net/ethernet/sfc/tx.c index 0ea7e16f2e6e..9937a2450e57 100644 --- a/drivers/net/ethernet/sfc/tx.c +++ b/drivers/net/ethernet/sfc/tx.c @@ -77,6 +77,7 @@ static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue, } if (buffer->flags & EFX_TX_BUF_SKB) { + EFX_WARN_ON_PARANOID(!pkts_compl || !bytes_compl); (*pkts_compl)++; (*bytes_compl) += buffer->skb->len; dev_consume_skb_any((struct sk_buff *)buffer->skb); @@ -426,12 +427,14 @@ static int efx_tx_map_data(struct efx_tx_queue *tx_queue, struct sk_buff *skb, static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue) { struct efx_tx_buffer *buffer; + unsigned int bytes_compl = 0; + unsigned int pkts_compl = 0; /* Work backwards until we hit the original insert pointer value */ while (tx_queue->insert_count != tx_queue->write_count) { --tx_queue->insert_count; buffer = __efx_tx_queue_get_insert_buffer(tx_queue); - efx_dequeue_buffer(tx_queue, buffer, NULL, NULL); + efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); } } -- GitLab From c589e69b508d29ed8e644dfecda453f71c02ec27 Mon Sep 17 00:00:00 2001 From: Neal Cardwell Date: Thu, 7 Dec 2017 12:43:30 -0500 Subject: [PATCH 1153/2547] tcp_bbr: record "full bw reached" decision in new full_bw_reached bit This commit records the "full bw reached" decision in a new full_bw_reached bit. This is a pure refactor that does not change the current behavior, but enables subsequent fixes and improvements. In particular, this enables simple and clean fixes because the full_bw and full_bw_cnt can be unconditionally zeroed without worrying about forgetting that we estimated we filled the pipe in Startup. And it enables future improvements because multiple code paths can be used for estimating that we filled the pipe in Startup; any new code paths only need to set this bit when they think the pipe is full. Note that this fix intentionally reduces the width of the full_bw_cnt counter, since we have never used the most significant bit. Signed-off-by: Neal Cardwell Reviewed-by: Yuchung Cheng Acked-by: Soheil Hassas Yeganeh Signed-off-by: David S. Miller --- net/ipv4/tcp_bbr.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/net/ipv4/tcp_bbr.c b/net/ipv4/tcp_bbr.c index 69ee877574d0..3089c956b9f9 100644 --- a/net/ipv4/tcp_bbr.c +++ b/net/ipv4/tcp_bbr.c @@ -110,7 +110,8 @@ struct bbr { u32 lt_last_lost; /* LT intvl start: tp->lost */ u32 pacing_gain:10, /* current gain for setting pacing rate */ cwnd_gain:10, /* current gain for setting cwnd */ - full_bw_cnt:3, /* number of rounds without large bw gains */ + full_bw_reached:1, /* reached full bw in Startup? */ + full_bw_cnt:2, /* number of rounds without large bw gains */ cycle_idx:3, /* current index in pacing_gain cycle array */ has_seen_rtt:1, /* have we seen an RTT sample yet? */ unused_b:5; @@ -180,7 +181,7 @@ static bool bbr_full_bw_reached(const struct sock *sk) { const struct bbr *bbr = inet_csk_ca(sk); - return bbr->full_bw_cnt >= bbr_full_bw_cnt; + return bbr->full_bw_reached; } /* Return the windowed max recent bandwidth sample, in pkts/uS << BW_SCALE. */ @@ -717,6 +718,7 @@ static void bbr_check_full_bw_reached(struct sock *sk, return; } ++bbr->full_bw_cnt; + bbr->full_bw_reached = bbr->full_bw_cnt >= bbr_full_bw_cnt; } /* If pipe is probably full, drain the queue and then enter steady-state. */ @@ -850,6 +852,7 @@ static void bbr_init(struct sock *sk) bbr->restore_cwnd = 0; bbr->round_start = 0; bbr->idle_restart = 0; + bbr->full_bw_reached = 0; bbr->full_bw = 0; bbr->full_bw_cnt = 0; bbr->cycle_mstamp = 0; -- GitLab From 2f6c498e4f15d27852c04ed46d804a39137ba364 Mon Sep 17 00:00:00 2001 From: Neal Cardwell Date: Thu, 7 Dec 2017 12:43:31 -0500 Subject: [PATCH 1154/2547] tcp_bbr: reset full pipe detection on loss recovery undo Fix BBR so that upon notification of a loss recovery undo BBR resets the full pipe detection (STARTUP exit) state machine. Under high reordering, reordering events can be interpreted as loss. If the reordering and spurious loss estimates are high enough, this could previously cause BBR to spuriously estimate that the pipe is full. Since spurious loss recovery means that our overall sending will have slowed down spuriously, this commit gives a flow more time to probe robustly for bandwidth and decide the pipe is really full. Signed-off-by: Neal Cardwell Reviewed-by: Yuchung Cheng Acked-by: Soheil Hassas Yeganeh Signed-off-by: David S. Miller --- net/ipv4/tcp_bbr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/ipv4/tcp_bbr.c b/net/ipv4/tcp_bbr.c index 3089c956b9f9..ab3ff14ea7f7 100644 --- a/net/ipv4/tcp_bbr.c +++ b/net/ipv4/tcp_bbr.c @@ -874,6 +874,10 @@ static u32 bbr_sndbuf_expand(struct sock *sk) */ static u32 bbr_undo_cwnd(struct sock *sk) { + struct bbr *bbr = inet_csk_ca(sk); + + bbr->full_bw = 0; /* spurious slow-down; reset full pipe detection */ + bbr->full_bw_cnt = 0; return tcp_sk(sk)->snd_cwnd; } -- GitLab From 600647d467c6d04b3954b41a6ee1795b5ae00550 Mon Sep 17 00:00:00 2001 From: Neal Cardwell Date: Thu, 7 Dec 2017 12:43:32 -0500 Subject: [PATCH 1155/2547] tcp_bbr: reset long-term bandwidth sampling on loss recovery undo Fix BBR so that upon notification of a loss recovery undo BBR resets long-term bandwidth sampling. Under high reordering, reordering events can be interpreted as loss. If the reordering and spurious loss estimates are high enough, this can cause BBR to spuriously estimate that we are seeing loss rates high enough to trigger long-term bandwidth estimation. To avoid that problem, this commit resets long-term bandwidth sampling on loss recovery undo events. Signed-off-by: Neal Cardwell Reviewed-by: Yuchung Cheng Acked-by: Soheil Hassas Yeganeh Signed-off-by: David S. Miller --- net/ipv4/tcp_bbr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/ipv4/tcp_bbr.c b/net/ipv4/tcp_bbr.c index ab3ff14ea7f7..8322f26e770e 100644 --- a/net/ipv4/tcp_bbr.c +++ b/net/ipv4/tcp_bbr.c @@ -878,6 +878,7 @@ static u32 bbr_undo_cwnd(struct sock *sk) bbr->full_bw = 0; /* spurious slow-down; reset full pipe detection */ bbr->full_bw_cnt = 0; + bbr_reset_lt_bw_sampling(sk); return tcp_sk(sk)->snd_cwnd; } -- GitLab From 39005e562a88c61fa77acef1d2c0cb81ee6b0423 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 4 Dec 2017 10:04:53 +0100 Subject: [PATCH 1156/2547] ARM64: dts: meson-gx: fix UART pclk clock name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The clock-names for pclk was wrongly set to "core", but the bindings specifies "pclk". This was not cathed until the legacy non-documented bindings were removed. Reported-by: Andreas Färber Fixes: f72d6f6037b7 ("ARM64: dts: meson-gx: use stable UART bindings with correct gate clock") Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index ead895a4e9a5..1fb8b9d6cb4e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -753,12 +753,12 @@ &uart_B { clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "core", "baud"; + clock-names = "xtal", "pclk", "baud"; }; &uart_C { clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "core", "baud"; + clock-names = "xtal", "pclk", "baud"; }; &vpu { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 8ed981f59e5a..6524b89e7115 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -688,7 +688,7 @@ &uart_A { clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "core", "baud"; + clock-names = "xtal", "pclk", "baud"; }; &uart_AO { @@ -703,12 +703,12 @@ &uart_B { clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "core", "baud"; + clock-names = "xtal", "pclk", "baud"; }; &uart_C { clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "core", "baud"; + clock-names = "xtal", "pclk", "baud"; }; &vpu { -- GitLab From e8a70cab253cf4c54855ffc2b1997e501f03e2a4 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 8 Dec 2017 01:22:59 +0000 Subject: [PATCH 1157/2547] drm/i915: Use snprintf to avoid line-break when pretty-printing engines When printing the execlist ports, we first print the ELSP header then follow it with the pretty-printed request. Since switching to drm_printer and show the output via printk, it automatically appends a newline to each call (unlike the old seq_printf output). To avoid the unwanted line break, construct the ELSP request header in a temporary buffer. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171208012303.25504-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_engine_cs.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 86d4c85c8725..dbd188a23cf1 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1674,6 +1674,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m) struct drm_i915_private *dev_priv = engine->i915; struct drm_i915_gem_request *rq; struct rb_node *rb; + char hdr[80]; u64 addr; drm_printf(m, "%s\n", engine->name); @@ -1786,12 +1787,12 @@ void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m) rq = port_unpack(&execlists->port[idx], &count); if (rq) { - drm_printf(m, "\t\tELSP[%d] count=%d, ", - idx, count); - print_request(m, rq, "rq: "); + snprintf(hdr, sizeof(hdr), + "\t\tELSP[%d] count=%d, rq: ", + idx, count); + print_request(m, rq, hdr); } else { - drm_printf(m, "\t\tELSP[%d] idle\n", - idx); + drm_printf(m, "\t\tELSP[%d] idle\n", idx); } } drm_printf(m, "\t\tHW active? 0x%x\n", execlists->active); -- GitLab From 0db18b17c8bca02638dcdc55dd458e04e18947b1 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 8 Dec 2017 01:23:00 +0000 Subject: [PATCH 1158/2547] drm/i915: Make engine state pretty-printer header configurable Pass in a format string (and args) to specify the header to be emitted along with the engine state when pretty-printing. This allows the header to be emitted inside the drm_printer stream, so sharing the same prefix and output characteristics (e.g. debug level and filtering). Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171208012303.25504-2-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/intel_engine_cs.c | 15 ++++++++++++--- drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++++- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 7 ++++--- 4 files changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 7b41a1799a03..9ccc6bcc7069 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3213,7 +3213,7 @@ static int i915_engine_info(struct seq_file *m, void *unused) p = drm_seq_file_printer(m); for_each_engine(engine, dev_priv, id) - intel_engine_dump(engine, &p); + intel_engine_dump(engine, &p, "%s\n", engine->name); intel_runtime_pm_put(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index dbd188a23cf1..60100ab13b42 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1596,7 +1596,7 @@ void intel_engines_park(struct drm_i915_private *i915) dev_err(i915->drm.dev, "%s is not idle before parking\n", engine->name); - intel_engine_dump(engine, &p); + intel_engine_dump(engine, &p, NULL); } if (engine->park) @@ -1666,7 +1666,9 @@ static void print_request(struct drm_printer *m, rq->timeline->common->name); } -void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m) +void intel_engine_dump(struct intel_engine_cs *engine, + struct drm_printer *m, + const char *header, ...) { struct intel_breadcrumbs * const b = &engine->breadcrumbs; const struct intel_engine_execlists * const execlists = &engine->execlists; @@ -1677,7 +1679,14 @@ void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m) char hdr[80]; u64 addr; - drm_printf(m, "%s\n", engine->name); + if (header) { + va_list ap; + + va_start(ap, header); + drm_vprintf(m, header, &ap); + va_end(ap); + } + drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n", intel_engine_get_seqno(engine), intel_engine_last_submit(engine), diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 183165b9b3fb..c5ff203e42d6 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -1013,7 +1013,10 @@ unsigned int intel_engines_has_context_isolation(struct drm_i915_private *i915); bool intel_engine_can_store_dword(struct intel_engine_cs *engine); -void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *p); +__printf(3, 4) +void intel_engine_dump(struct intel_engine_cs *engine, + struct drm_printer *m, + const char *header, ...); struct intel_engine_cs * intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance); diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 1bbb8c46e2d9..f98546b8a7fa 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -619,7 +619,7 @@ static int igt_wait_reset(void *arg) pr_err("Failed to start request %x, at %x\n", rq->fence.seqno, hws_seqno(&h, rq)); - intel_engine_dump(rq->engine, &p); + intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name); i915_reset(i915, 0); i915_gem_set_wedged(i915); @@ -714,7 +714,8 @@ static int igt_reset_queue(void *arg) pr_err("Failed to start request %x, at %x\n", prev->fence.seqno, hws_seqno(&h, prev)); - intel_engine_dump(rq->engine, &p); + intel_engine_dump(prev->engine, &p, + "%s\n", prev->engine->name); i915_gem_request_put(rq); i915_gem_request_put(prev); @@ -820,7 +821,7 @@ static int igt_handle_error(void *arg) pr_err("Failed to start request %x, at %x\n", rq->fence.seqno, hws_seqno(&h, rq)); - intel_engine_dump(rq->engine, &p); + intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name); i915_reset(i915, 0); i915_gem_set_wedged(i915); -- GitLab From 832265d38cf4d27984b84036b38568d71917dc8a Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 8 Dec 2017 01:23:01 +0000 Subject: [PATCH 1159/2547] drm/i915: Include engine state on detecting a missed breadcrumb/seqno Now that we have a common engine state pretty printer, we can use that instead of the adhoc information printed when we miss a breadcrumb. v2: Rearrange intel_engine_disarm_breadcrumbs() to avoid calling intel_engine_dump() under the rb spinlock (Mika) and to pretty-print the error state early so that we include the full list of waiters. v3: Pass missed breadcrumb msg to pretty-printer as the header v4: Preserve DRM_DEBUG_DRIVER filtering. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Tvrtko Ursulin Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171208012303.25504-3-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_breadcrumbs.c | 25 +++++++++++++----------- drivers/gpu/drm/i915/intel_engine_cs.c | 6 ++++++ 2 files changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c index 5ae2d276f7f3..24c6fefdd0b1 100644 --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c @@ -64,12 +64,13 @@ static unsigned long wait_timeout(void) static noinline void missed_breadcrumb(struct intel_engine_cs *engine) { - DRM_DEBUG_DRIVER("%s missed breadcrumb at %pS, irq posted? %s, current seqno=%x, last=%x\n", - engine->name, __builtin_return_address(0), - yesno(test_bit(ENGINE_IRQ_BREADCRUMB, - &engine->irq_posted)), - intel_engine_get_seqno(engine), - intel_engine_last_submit(engine)); + if (drm_debug & DRM_UT_DRIVER) { + struct drm_printer p = drm_debug_printer(__func__); + + intel_engine_dump(engine, &p, + "%s missed breadcrumb at %pS\n", + engine->name, __builtin_return_address(0)); + } set_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings); } @@ -213,28 +214,30 @@ void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine) void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine) { struct intel_breadcrumbs *b = &engine->breadcrumbs; - struct intel_wait *wait, *n, *first; + struct intel_wait *wait, *n; if (!b->irq_armed) return; - /* We only disarm the irq when we are idle (all requests completed), + /* + * We only disarm the irq when we are idle (all requests completed), * so if the bottom-half remains asleep, it missed the request * completion. */ + if (intel_engine_wakeup(engine) & ENGINE_WAKEUP_ASLEEP) + missed_breadcrumb(engine); spin_lock_irq(&b->rb_lock); spin_lock(&b->irq_lock); - first = fetch_and_zero(&b->irq_wait); + b->irq_wait = NULL; if (b->irq_armed) __intel_engine_disarm_breadcrumbs(engine); spin_unlock(&b->irq_lock); rbtree_postorder_for_each_entry_safe(wait, n, &b->waiters, node) { RB_CLEAR_NODE(&wait->node); - if (wake_up_process(wait->tsk) && wait == first) - missed_breadcrumb(engine); + wake_up_process(wait->tsk); } b->waiters = RB_ROOT; diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 60100ab13b42..ac62ca490551 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1836,6 +1836,12 @@ void intel_engine_dump(struct intel_engine_cs *engine, } spin_unlock_irq(&b->rb_lock); + drm_printf(m, "IRQ? 0x%lx (breadcrumbs? %s) (execlists? %s)\n", + engine->irq_posted, + yesno(test_bit(ENGINE_IRQ_BREADCRUMB, + &engine->irq_posted)), + yesno(test_bit(ENGINE_IRQ_EXECLIST, + &engine->irq_posted))); drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine))); drm_printf(m, "\n"); } -- GitLab From 528dd16a7c228e1383a291781744ed2c0ac99429 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 8 Dec 2017 01:23:02 +0000 Subject: [PATCH 1160/2547] drm/i915: Include the global reset count for intel_engine_dump() Since a global reset affects the engine, include that along side the per-engine reset counter when pretty printing the engine state in intel_engine_dump(). Signed-off-by: Chris Wilson Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171208012303.25504-4-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index ac62ca490551..25fae8ff0e67 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1693,8 +1693,9 @@ void intel_engine_dump(struct intel_engine_cs *engine, engine->hangcheck.seqno, jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp), engine->timeline->inflight_seqnos); - drm_printf(m, "\tReset count: %d\n", - i915_reset_engine_count(error, engine)); + drm_printf(m, "\tReset count: %d (global %d)\n", + i915_reset_engine_count(error, engine), + i915_reset_count(error)); rcu_read_lock(); -- GitLab From 2d8d1afb4d7d6d88a1ac19010d9a1a9594188ce3 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 8 Dec 2017 01:23:03 +0000 Subject: [PATCH 1161/2547] drm/i915: Add is-wedged flag to intel_engine_dump() Comparing the state tested by intel_engine_is_idle() and printed by intel_engine_dump(), the only bit not shown is whether or not the device is wedged. Add that little bit of information to the pretty printer so that if the engine fails to idle we can see why. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171208012303.25504-5-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 25fae8ff0e67..04c31475a7ae 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1687,6 +1687,9 @@ void intel_engine_dump(struct intel_engine_cs *engine, va_end(ap); } + if (i915_terminally_wedged(&engine->i915->gpu_error)) + drm_printf(m, "*** WEDGED ***\n"); + drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n", intel_engine_get_seqno(engine), intel_engine_last_submit(engine), -- GitLab From 0f0be40ba59c2d5fdfea48e3ff93f6165d616440 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 8 Dec 2017 15:18:53 +0100 Subject: [PATCH 1162/2547] ASoC: atmel-classd: select correct Kconfig symbol SND_ATMEL_SOC_CLASSD selects SND_ATMEL_SOC_DMA but the driver itself handles its own DMA operations and doesn't need anything from atmel-pcm-dma.c or atmel_ssc_dai.c. Replace SND_ATMEL_SOC_DMA by SND_SOC_GENERIC_DMAENGINE_PCM which is the only one actually required. This may end up in a configuration leading to a link error: sound/soc/atmel/atmel_ssc_dai.o: In function `atmel_ssc_set_audio': atmel_ssc_dai.c:(.text+0x79c): undefined reference to `atmel_pcm_dma_platform_register' atmel_ssc_dai.c:(.text+0x79c): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `atmel_pcm_dma_platform_register' sound/soc/atmel/atmel_ssc_dai.o: In function `atmel_ssc_put_audio': atmel_ssc_dai.c:(.text+0xf24): undefined reference to `atmel_pcm_dma_platform_unregister' atmel_ssc_dai.c:(.text+0xf24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `atmel_pcm_dma_platform_unregister' Tested on sama5d2 xplained with the following configuration where nothing selects SND_ATMEL_SOC_DMA: CONFIG_SND_ATMEL_SOC=y CONFIG_SND_ATMEL_SOC_CLASSD=y Reported-by: Arnd Bergmann Tested-by: Arnd Bergmann Fixes: e0a25b6d1862 ("ASoC: atmel-classd: add the Audio Class D Amplifier") Signed-off-by: Alexandre Belloni Signed-off-by: Mark Brown --- sound/soc/atmel/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/atmel/Kconfig b/sound/soc/atmel/Kconfig index 4a56f3dfba51..dcee145dd179 100644 --- a/sound/soc/atmel/Kconfig +++ b/sound/soc/atmel/Kconfig @@ -64,7 +64,7 @@ config SND_AT91_SOC_SAM9X5_WM8731 config SND_ATMEL_SOC_CLASSD tristate "Atmel ASoC driver for boards using CLASSD" depends on ARCH_AT91 || COMPILE_TEST - select SND_ATMEL_SOC_DMA + select SND_SOC_GENERIC_DMAENGINE_PCM select REGMAP_MMIO help Say Y if you want to add support for Atmel ASoC driver for boards using -- GitLab From 4362934a75ff2a399fd0bcd75937907115770020 Mon Sep 17 00:00:00 2001 From: Naveen Manohar Date: Fri, 8 Dec 2017 09:30:18 +0530 Subject: [PATCH 1163/2547] ASoC: Intel: Change kern log level to avoid unwanted messages patch suppresses the warning message "control load not supported" as this is a debug information to help debug issues in topology. Signed-off-by: Naveen Manohar Acked-By: Vinod Koul Signed-off-by: Mark Brown --- sound/soc/intel/skylake/skl-topology.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/intel/skylake/skl-topology.c b/sound/soc/intel/skylake/skl-topology.c index a072bcf209d2..81923da18ac2 100644 --- a/sound/soc/intel/skylake/skl-topology.c +++ b/sound/soc/intel/skylake/skl-topology.c @@ -2908,7 +2908,7 @@ static int skl_tplg_control_load(struct snd_soc_component *cmpnt, break; default: - dev_warn(bus->dev, "Control load not supported %d:%d:%d\n", + dev_dbg(bus->dev, "Control load not supported %d:%d:%d\n", hdr->ops.get, hdr->ops.put, hdr->ops.info); break; } -- GitLab From 33f801366bdf3f8b67dfe325b84f4051a090d01e Mon Sep 17 00:00:00 2001 From: Jiada Wang Date: Thu, 7 Dec 2017 22:15:38 -0800 Subject: [PATCH 1164/2547] ASoC: rsnd: ssi: fix race condition in rsnd_ssi_pointer_update Currently there is race condition between set of byte_pos and wrap it around when new buffer starts. If .pointer is called in-between it will result in inconsistent pointer position be returned from .pointer callback. This patch increments buffer pointer atomically to avoid this issue. Signed-off-by: Jiada Wang Reviewed-by: Takashi Sakamoto Acked-by: Kuninori Morimoto Signed-off-by: Mark Brown --- sound/soc/sh/rcar/ssi.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c index fece1e5f582f..cbf3bf312d23 100644 --- a/sound/soc/sh/rcar/ssi.c +++ b/sound/soc/sh/rcar/ssi.c @@ -446,25 +446,29 @@ static bool rsnd_ssi_pointer_update(struct rsnd_mod *mod, int byte) { struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod); + bool ret = false; + int byte_pos; - ssi->byte_pos += byte; + byte_pos = ssi->byte_pos + byte; - if (ssi->byte_pos >= ssi->next_period_byte) { + if (byte_pos >= ssi->next_period_byte) { struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); ssi->period_pos++; ssi->next_period_byte += ssi->byte_per_period; if (ssi->period_pos >= runtime->periods) { - ssi->byte_pos = 0; + byte_pos = 0; ssi->period_pos = 0; ssi->next_period_byte = ssi->byte_per_period; } - return true; + ret = true; } - return false; + WRITE_ONCE(ssi->byte_pos, byte_pos); + + return ret; } /* @@ -838,7 +842,7 @@ static int rsnd_ssi_pointer(struct rsnd_mod *mod, struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod); struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); - *pointer = bytes_to_frames(runtime, ssi->byte_pos); + *pointer = bytes_to_frames(runtime, READ_ONCE(ssi->byte_pos)); return 0; } -- GitLab From 2edbdb3159d6f6bd3a9b6e7f789f2b879699a519 Mon Sep 17 00:00:00 2001 From: Calvin Owens Date: Fri, 8 Dec 2017 09:05:26 -0800 Subject: [PATCH 1165/2547] bnxt_en: Fix sources of spurious netpoll warnings After applying 2270bc5da3497945 ("bnxt_en: Fix netpoll handling") and 903649e718f80da2 ("bnxt_en: Improve -ENOMEM logic in NAPI poll loop."), we still see the following WARN fire: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 1875170 at net/core/netpoll.c:165 netpoll_poll_dev+0x15a/0x160 bnxt_poll+0x0/0xd0 exceeded budget in poll Call Trace: [] dump_stack+0x4d/0x70 [] __warn+0xd3/0xf0 [] warn_slowpath_fmt+0x4f/0x60 [] netpoll_poll_dev+0x15a/0x160 [] netpoll_send_skb_on_dev+0x168/0x250 [] netpoll_send_udp+0x2dc/0x440 [] write_ext_msg+0x20e/0x250 [] call_console_drivers.constprop.23+0xa5/0x110 [] console_unlock+0x339/0x5b0 [] vprintk_emit+0x2c8/0x450 [] vprintk_default+0x1f/0x30 [] printk+0x48/0x50 [] edac_raw_mc_handle_error+0x563/0x5c0 [edac_core] [] edac_mc_handle_error+0x42b/0x6e0 [edac_core] [] sbridge_mce_output_error+0x410/0x10d0 [sb_edac] [] sbridge_check_error+0xac/0x130 [sb_edac] [] edac_mc_workq_function+0x3c/0x90 [edac_core] [] process_one_work+0x19b/0x480 [] worker_thread+0x6a/0x520 [] kthread+0xe4/0x100 [] ret_from_fork+0x22/0x40 This happens because we increment rx_pkts on -ENOMEM and -EIO, resulting in rx_pkts > 0. Fix this by only bumping rx_pkts if we were actually given a non-zero budget. Signed-off-by: Calvin Owens Acked-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index 28f5e94274ee..61ca4eb7c6fa 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -1883,7 +1883,7 @@ static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) * here forever if we consistently cannot allocate * buffers. */ - else if (rc == -ENOMEM) + else if (rc == -ENOMEM && budget) rx_pkts++; else if (rc == -EBUSY) /* partial completion */ break; @@ -1969,7 +1969,7 @@ static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event); - if (likely(rc == -EIO)) + if (likely(rc == -EIO) && budget) rx_pkts++; else if (rc == -EBUSY) /* partial completion */ break; -- GitLab From 0ce294d88457bccd7f9991f883fec80022a1ddbd Mon Sep 17 00:00:00 2001 From: Yuchung Cheng Date: Thu, 7 Dec 2017 11:33:30 -0800 Subject: [PATCH 1166/2547] tcp: correctly test congestion state in RACK RACK does not test the loss recovery state correctly to compute the reordering window. It assumes if lost_out is zero then TCP is not in loss recovery. But it can be zero during recovery before calling tcp_rack_detect_loss(): when an ACK acknowledges all packets marked lost before receiving this ACK, but has not yet to discover new ones by tcp_rack_detect_loss(). The fix is to simply test the congestion state directly. Signed-off-by: Yuchung Cheng Reviewed-by: Neal Cardwell Reviewed-by: Priyaranjan Jha Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller --- net/ipv4/tcp_recovery.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/ipv4/tcp_recovery.c b/net/ipv4/tcp_recovery.c index d3ea89020c69..3143664902e9 100644 --- a/net/ipv4/tcp_recovery.c +++ b/net/ipv4/tcp_recovery.c @@ -55,7 +55,8 @@ static void tcp_rack_detect_loss(struct sock *sk, u32 *reo_timeout) * to queuing or delayed ACKs. */ reo_wnd = 1000; - if ((tp->rack.reord || !tp->lost_out) && min_rtt != ~0U) { + if ((tp->rack.reord || inet_csk(sk)->icsk_ca_state < TCP_CA_Recovery) && + min_rtt != ~0U) { reo_wnd = max((min_rtt >> 2) * tp->rack.reo_wnd_steps, reo_wnd); reo_wnd = min(reo_wnd, tp->srtt_us >> 3); } -- GitLab From cd1fc85b4399d47e3d6626301741ba8c38cd475a Mon Sep 17 00:00:00 2001 From: Yuchung Cheng Date: Thu, 7 Dec 2017 11:33:31 -0800 Subject: [PATCH 1167/2547] tcp: always evaluate losses in RACK upon undo When sender detects spurious retransmission, all packets marked lost are remarked to be in-flight. However some may be considered lost based on its timestamps in RACK. This patch forces RACK to re-evaluate, which may be skipped previously if the ACK does not advance RACK timestamp. Signed-off-by: Yuchung Cheng Reviewed-by: Neal Cardwell Reviewed-by: Priyaranjan Jha Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller --- net/ipv4/tcp_input.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index 075c559570e6..9550cc42de2d 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -2329,6 +2329,7 @@ static void tcp_undo_cwnd_reduction(struct sock *sk, bool unmark_loss) } tp->snd_cwnd_stamp = tcp_jiffies32; tp->undo_marker = 0; + tp->rack.advanced = 1; /* Force RACK to re-exam losses */ } static inline bool tcp_may_undo(const struct tcp_sock *tp) -- GitLab From 428aec5e69fa17d223e1495f395833c50770f7ae Mon Sep 17 00:00:00 2001 From: Yuchung Cheng Date: Thu, 7 Dec 2017 11:33:32 -0800 Subject: [PATCH 1168/2547] tcp: fix off-by-one bug in RACK RACK should mark a packet lost when remaining wait time is zero. Signed-off-by: Yuchung Cheng Reviewed-by: Neal Cardwell Reviewed-by: Priyaranjan Jha Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller --- net/ipv4/tcp_recovery.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/net/ipv4/tcp_recovery.c b/net/ipv4/tcp_recovery.c index 3143664902e9..0c182303e62e 100644 --- a/net/ipv4/tcp_recovery.c +++ b/net/ipv4/tcp_recovery.c @@ -80,12 +80,12 @@ static void tcp_rack_detect_loss(struct sock *sk, u32 *reo_timeout) */ remaining = tp->rack.rtt_us + reo_wnd - tcp_stamp_us_delta(tp->tcp_mstamp, skb->skb_mstamp); - if (remaining < 0) { + if (remaining <= 0) { tcp_rack_mark_skb_lost(sk, skb); list_del_init(&skb->tcp_tsorted_anchor); } else { - /* Record maximum wait time (+1 to avoid 0) */ - *reo_timeout = max_t(u32, *reo_timeout, 1 + remaining); + /* Record maximum wait time */ + *reo_timeout = max_t(u32, *reo_timeout, remaining); } } } -- GitLab From 6065fd0d179b96ddc488c76542349bcb148a95fd Mon Sep 17 00:00:00 2001 From: Yuchung Cheng Date: Thu, 7 Dec 2017 11:33:33 -0800 Subject: [PATCH 1169/2547] tcp: evaluate packet losses upon RTT change RACK skips an ACK unless it advances the most recently delivered TX timestamp (rack.mstamp). Since RACK also uses the most recent RTT to decide if a packet is lost, RACK should still run the loss detection whenever the most recent RTT changes. For example, an ACK that does not advance the timestamp but triggers the cwnd undo due to reordering, would then use the most recent (higher) RTT measurement to detect further losses. Signed-off-by: Yuchung Cheng Reviewed-by: Neal Cardwell Reviewed-by: Priyaranjan Jha Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller --- net/ipv4/tcp_recovery.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/net/ipv4/tcp_recovery.c b/net/ipv4/tcp_recovery.c index 0c182303e62e..3a81720ac0c4 100644 --- a/net/ipv4/tcp_recovery.c +++ b/net/ipv4/tcp_recovery.c @@ -117,13 +117,8 @@ void tcp_rack_advance(struct tcp_sock *tp, u8 sacked, u32 end_seq, { u32 rtt_us; - if (tp->rack.mstamp && - !tcp_rack_sent_after(xmit_time, tp->rack.mstamp, - end_seq, tp->rack.end_seq)) - return; - rtt_us = tcp_stamp_us_delta(tp->tcp_mstamp, xmit_time); - if (sacked & TCPCB_RETRANS) { + if (rtt_us < tcp_min_rtt(tp) && (sacked & TCPCB_RETRANS)) { /* If the sacked packet was retransmitted, it's ambiguous * whether the retransmission or the original (or the prior * retransmission) was sacked. @@ -134,13 +129,15 @@ void tcp_rack_advance(struct tcp_sock *tp, u8 sacked, u32 end_seq, * so it's at least one RTT (i.e., retransmission is at least * an RTT later). */ - if (rtt_us < tcp_min_rtt(tp)) - return; + return; } - tp->rack.rtt_us = rtt_us; - tp->rack.mstamp = xmit_time; - tp->rack.end_seq = end_seq; tp->rack.advanced = 1; + tp->rack.rtt_us = rtt_us; + if (tcp_rack_sent_after(xmit_time, tp->rack.mstamp, + end_seq, tp->rack.end_seq)) { + tp->rack.mstamp = xmit_time; + tp->rack.end_seq = end_seq; + } } /* We have waited long enough to accommodate reordering. Mark the expired -- GitLab From 8a7b741e76cd31b6000636f0391e67ba6793ad1c Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Fri, 8 Dec 2017 10:24:20 +0100 Subject: [PATCH 1170/2547] net: mvpp2: fix the RSS table entry offset The macro used to access or set an RSS table entry was using an offset of 8, while it should use an offset of 0. This lead to wrongly configure the RSS table, not accessing the right entries. Fixes: 1d7d15d79fb4 ("net: mvpp2: initialize the RSS tables") Signed-off-by: Antoine Tenart Signed-off-by: David S. Miller --- drivers/net/ethernet/marvell/mvpp2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index fed2b2f909fc..634b2f41cc9e 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -85,7 +85,7 @@ /* RSS Registers */ #define MVPP22_RSS_INDEX 0x1500 -#define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) ((idx) << 8) +#define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) (idx) #define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8) #define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16) #define MVPP22_RSS_TABLE_ENTRY 0x1508 -- GitLab From babc8110057cb9ca542c3c1666cbda4e8ccf9250 Mon Sep 17 00:00:00 2001 From: Stefan Schake Date: Sat, 2 Dec 2017 18:40:39 +0100 Subject: [PATCH 1171/2547] drm/vc4: Release fence after signalling We were never releasing the initial fence reference that is obtained through dma_fence_init. Link: https://github.com/anholt/linux/issues/122 Fixes: cdec4d361323 ("drm/vc4: Expose dma-buf fences for V3D rendering.") Signed-off-by: Stefan Schake Signed-off-by: Eric Anholt Reviewed-by: Eric Anholt Link: https://patchwork.freedesktop.org/patch/msgid/1512236444-301-1-git-send-email-stschake@gmail.com --- drivers/gpu/drm/vc4/vc4_gem.c | 4 +++- drivers/gpu/drm/vc4/vc4_irq.c | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c index 6c32c89a83a9..638540943c61 100644 --- a/drivers/gpu/drm/vc4/vc4_gem.c +++ b/drivers/gpu/drm/vc4/vc4_gem.c @@ -888,8 +888,10 @@ vc4_complete_exec(struct drm_device *dev, struct vc4_exec_info *exec) /* If we got force-completed because of GPU reset rather than * through our IRQ handler, signal the fence now. */ - if (exec->fence) + if (exec->fence) { dma_fence_signal(exec->fence); + dma_fence_put(exec->fence); + } if (exec->bo) { for (i = 0; i < exec->bo_count; i++) { diff --git a/drivers/gpu/drm/vc4/vc4_irq.c b/drivers/gpu/drm/vc4/vc4_irq.c index 61b2e5377993..26eddbb62893 100644 --- a/drivers/gpu/drm/vc4/vc4_irq.c +++ b/drivers/gpu/drm/vc4/vc4_irq.c @@ -139,6 +139,7 @@ vc4_irq_finish_render_job(struct drm_device *dev) list_move_tail(&exec->head, &vc4->job_done_list); if (exec->fence) { dma_fence_signal_locked(exec->fence); + dma_fence_put(exec->fence); exec->fence = NULL; } vc4_submit_next_render_job(dev); -- GitLab From f335195adf043168ee69d78ea72ac3e30f0c57ce Mon Sep 17 00:00:00 2001 From: Michal Hocko Date: Wed, 6 Dec 2017 11:27:57 +0100 Subject: [PATCH 1172/2547] kmemcheck: rip it out for real Commit 4675ff05de2d ("kmemcheck: rip it out") has removed the code but for some reason SPDX header stayed in place. This looks like a rebase mistake in the mmotm tree or the merge mistake. Let's drop those leftovers as well. Signed-off-by: Michal Hocko Signed-off-by: Linus Torvalds --- arch/x86/include/asm/kmemcheck.h | 1 - arch/x86/mm/kmemcheck/error.c | 1 - arch/x86/mm/kmemcheck/error.h | 1 - arch/x86/mm/kmemcheck/opcode.c | 1 - arch/x86/mm/kmemcheck/opcode.h | 1 - arch/x86/mm/kmemcheck/pte.c | 1 - arch/x86/mm/kmemcheck/pte.h | 1 - arch/x86/mm/kmemcheck/selftest.c | 1 - arch/x86/mm/kmemcheck/selftest.h | 1 - arch/x86/mm/kmemcheck/shadow.h | 1 - include/linux/kmemcheck.h | 1 - mm/kmemcheck.c | 1 - tools/include/linux/kmemcheck.h | 1 - 13 files changed, 13 deletions(-) delete mode 100644 arch/x86/include/asm/kmemcheck.h delete mode 100644 arch/x86/mm/kmemcheck/error.c delete mode 100644 arch/x86/mm/kmemcheck/error.h delete mode 100644 arch/x86/mm/kmemcheck/opcode.c delete mode 100644 arch/x86/mm/kmemcheck/opcode.h delete mode 100644 arch/x86/mm/kmemcheck/pte.c delete mode 100644 arch/x86/mm/kmemcheck/pte.h delete mode 100644 arch/x86/mm/kmemcheck/selftest.c delete mode 100644 arch/x86/mm/kmemcheck/selftest.h delete mode 100644 arch/x86/mm/kmemcheck/shadow.h delete mode 100644 include/linux/kmemcheck.h delete mode 100644 mm/kmemcheck.c delete mode 100644 tools/include/linux/kmemcheck.h diff --git a/arch/x86/include/asm/kmemcheck.h b/arch/x86/include/asm/kmemcheck.h deleted file mode 100644 index ea32a7d3cf1b..000000000000 --- a/arch/x86/include/asm/kmemcheck.h +++ /dev/null @@ -1 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ diff --git a/arch/x86/mm/kmemcheck/error.c b/arch/x86/mm/kmemcheck/error.c deleted file mode 100644 index cec594032515..000000000000 --- a/arch/x86/mm/kmemcheck/error.c +++ /dev/null @@ -1 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 diff --git a/arch/x86/mm/kmemcheck/error.h b/arch/x86/mm/kmemcheck/error.h deleted file mode 100644 index ea32a7d3cf1b..000000000000 --- a/arch/x86/mm/kmemcheck/error.h +++ /dev/null @@ -1 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ diff --git a/arch/x86/mm/kmemcheck/opcode.c b/arch/x86/mm/kmemcheck/opcode.c deleted file mode 100644 index cec594032515..000000000000 --- a/arch/x86/mm/kmemcheck/opcode.c +++ /dev/null @@ -1 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 diff --git a/arch/x86/mm/kmemcheck/opcode.h b/arch/x86/mm/kmemcheck/opcode.h deleted file mode 100644 index ea32a7d3cf1b..000000000000 --- a/arch/x86/mm/kmemcheck/opcode.h +++ /dev/null @@ -1 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ diff --git a/arch/x86/mm/kmemcheck/pte.c b/arch/x86/mm/kmemcheck/pte.c deleted file mode 100644 index cec594032515..000000000000 --- a/arch/x86/mm/kmemcheck/pte.c +++ /dev/null @@ -1 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 diff --git a/arch/x86/mm/kmemcheck/pte.h b/arch/x86/mm/kmemcheck/pte.h deleted file mode 100644 index ea32a7d3cf1b..000000000000 --- a/arch/x86/mm/kmemcheck/pte.h +++ /dev/null @@ -1 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ diff --git a/arch/x86/mm/kmemcheck/selftest.c b/arch/x86/mm/kmemcheck/selftest.c deleted file mode 100644 index cec594032515..000000000000 --- a/arch/x86/mm/kmemcheck/selftest.c +++ /dev/null @@ -1 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 diff --git a/arch/x86/mm/kmemcheck/selftest.h b/arch/x86/mm/kmemcheck/selftest.h deleted file mode 100644 index ea32a7d3cf1b..000000000000 --- a/arch/x86/mm/kmemcheck/selftest.h +++ /dev/null @@ -1 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ diff --git a/arch/x86/mm/kmemcheck/shadow.h b/arch/x86/mm/kmemcheck/shadow.h deleted file mode 100644 index ea32a7d3cf1b..000000000000 --- a/arch/x86/mm/kmemcheck/shadow.h +++ /dev/null @@ -1 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ diff --git a/include/linux/kmemcheck.h b/include/linux/kmemcheck.h deleted file mode 100644 index ea32a7d3cf1b..000000000000 --- a/include/linux/kmemcheck.h +++ /dev/null @@ -1 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ diff --git a/mm/kmemcheck.c b/mm/kmemcheck.c deleted file mode 100644 index cec594032515..000000000000 --- a/mm/kmemcheck.c +++ /dev/null @@ -1 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 diff --git a/tools/include/linux/kmemcheck.h b/tools/include/linux/kmemcheck.h deleted file mode 100644 index ea32a7d3cf1b..000000000000 --- a/tools/include/linux/kmemcheck.h +++ /dev/null @@ -1 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -- GitLab From eaf0ec303bd73f6b2c18f48542974a710fadfeb9 Mon Sep 17 00:00:00 2001 From: Pravin Shedge Date: Wed, 6 Dec 2017 10:16:15 -0800 Subject: [PATCH 1173/2547] fs: xfs: remove duplicate includes These duplicate includes have been found with scripts/checkincludes.pl but they have been removed manually to avoid removing false positives. Signed-off-by: Pravin Shedge Reviewed-by: Darrick J. Wong Signed-off-by: Darrick J. Wong --- fs/xfs/scrub/scrub.c | 1 - fs/xfs/scrub/trace.c | 1 - fs/xfs/xfs_reflink.c | 2 -- fs/xfs/xfs_trace.c | 1 - 4 files changed, 5 deletions(-) diff --git a/fs/xfs/scrub/scrub.c b/fs/xfs/scrub/scrub.c index 9c42c4efd01e..ab3aef2ae823 100644 --- a/fs/xfs/scrub/scrub.c +++ b/fs/xfs/scrub/scrub.c @@ -46,7 +46,6 @@ #include "scrub/scrub.h" #include "scrub/common.h" #include "scrub/trace.h" -#include "scrub/scrub.h" #include "scrub/btree.h" /* diff --git a/fs/xfs/scrub/trace.c b/fs/xfs/scrub/trace.c index 472080e75788..86daed0e3a45 100644 --- a/fs/xfs/scrub/trace.c +++ b/fs/xfs/scrub/trace.c @@ -26,7 +26,6 @@ #include "xfs_mount.h" #include "xfs_defer.h" #include "xfs_da_format.h" -#include "xfs_defer.h" #include "xfs_inode.h" #include "xfs_btree.h" #include "xfs_trans.h" diff --git a/fs/xfs/xfs_reflink.c b/fs/xfs/xfs_reflink.c index cc041a29eb70..cf7c8f81bebb 100644 --- a/fs/xfs/xfs_reflink.c +++ b/fs/xfs/xfs_reflink.c @@ -49,8 +49,6 @@ #include "xfs_alloc.h" #include "xfs_quota_defs.h" #include "xfs_quota.h" -#include "xfs_btree.h" -#include "xfs_bmap_btree.h" #include "xfs_reflink.h" #include "xfs_iomap.h" #include "xfs_rmap_btree.h" diff --git a/fs/xfs/xfs_trace.c b/fs/xfs/xfs_trace.c index 5d95fe348294..35f3546b6af5 100644 --- a/fs/xfs/xfs_trace.c +++ b/fs/xfs/xfs_trace.c @@ -24,7 +24,6 @@ #include "xfs_mount.h" #include "xfs_defer.h" #include "xfs_da_format.h" -#include "xfs_defer.h" #include "xfs_inode.h" #include "xfs_btree.h" #include "xfs_da_btree.h" -- GitLab From f59cf5c29919d17b61913c3360a7bd29b72975c1 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 4 Dec 2017 17:32:55 -0800 Subject: [PATCH 1174/2547] xfs: remove "no-allocation" reservations for file creations If we create a new file we will need an inode, and usually some metadata in the parent direction. Aiming for everything to go well despite the lack of a reservation leads to dirty transactions cancelled under a heavy create/delete load. This patch removes those nospace transactions, which will lead to slightly earlier ENOSPC on some workloads, but instead prevent file system shutdowns due to cancelling dirty transactions for others. A customer could observe assertations failures and shutdowns due to cancelation of dirty transactions during heavy NFS workloads as shown below: 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728125] XFS: Assertion failed: error != -ENOSPC, file: fs/xfs/xfs_inode.c, line: 1262 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728222] Call Trace: 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728246] [] dump_stack+0x63/0x81 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728262] [] warn_slowpath_common+0x8a/0xc0 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728264] [] warn_slowpath_null+0x1a/0x20 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728285] [] asswarn+0x33/0x40 [xfs] 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728308] [] xfs_create+0x7be/0x7d0 [xfs] 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728329] [] xfs_generic_create+0x1fb/0x2e0 [xfs] 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728348] [] xfs_vn_mknod+0x14/0x20 [xfs] 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728366] [] xfs_vn_create+0x13/0x20 [xfs] 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728380] [] vfs_create+0xd5/0x140 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728390] [] do_nfsd_create+0x499/0x610 [nfsd] 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728396] [] nfsd3_proc_create+0x135/0x210 [nfsd] 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728401] [] nfsd_dispatch+0xc3/0x210 [nfsd] 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728416] [] svc_process_common+0x453/0x6f0 [sunrpc] 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728423] [] svc_process+0x113/0x1f0 [sunrpc] 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728427] [] nfsd+0x10f/0x180 [nfsd] 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728432] [] ? nfsd_destroy+0x80/0x80 [nfsd] 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728438] [] kthread+0xd8/0xf0 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728441] [] ? kthread_create_on_node+0x1b0/0x1b0 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728451] [] ret_from_fork+0x42/0x70 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728453] [] ? kthread_create_on_node+0x1b0/0x1b0 2017-05-30 21:17:06 kernel: WARNING: [ 2670.728454] ---[ end trace f9822c842fec81d4 ]--- 2017-05-30 21:17:06 kernel: ALERT: [ 2670.728477] XFS (sdb): Internal error xfs_trans_cancel at line 983 of file fs/xfs/xfs_trans.c. Caller xfs_create+0x4ee/0x7d0 [xfs] 2017-05-30 21:17:06 kernel: ALERT: [ 2670.728684] XFS (sdb): Corruption of in-memory data detected. Shutting down filesystem 2017-05-30 21:17:06 kernel: ALERT: [ 2670.728685] XFS (sdb): Please umount the filesystem and rectify the problem(s) Signed-off-by: Christoph Hellwig Reviewed-by: Darrick J. Wong Signed-off-by: Darrick J. Wong --- fs/xfs/libxfs/xfs_ialloc.c | 10 +++------- fs/xfs/libxfs/xfs_ialloc.h | 1 - fs/xfs/xfs_inode.c | 33 +++++++-------------------------- fs/xfs/xfs_inode.h | 2 +- fs/xfs/xfs_qm.c | 4 ++-- fs/xfs/xfs_symlink.c | 15 +-------------- 6 files changed, 14 insertions(+), 51 deletions(-) diff --git a/fs/xfs/libxfs/xfs_ialloc.c b/fs/xfs/libxfs/xfs_ialloc.c index de3f04a98656..3b57ef0f2f76 100644 --- a/fs/xfs/libxfs/xfs_ialloc.c +++ b/fs/xfs/libxfs/xfs_ialloc.c @@ -920,8 +920,7 @@ STATIC xfs_agnumber_t xfs_ialloc_ag_select( xfs_trans_t *tp, /* transaction pointer */ xfs_ino_t parent, /* parent directory inode number */ - umode_t mode, /* bits set to indicate file type */ - int okalloc) /* ok to allocate more space */ + umode_t mode) /* bits set to indicate file type */ { xfs_agnumber_t agcount; /* number of ag's in the filesystem */ xfs_agnumber_t agno; /* current ag number */ @@ -978,9 +977,6 @@ xfs_ialloc_ag_select( return agno; } - if (!okalloc) - goto nextag; - if (!pag->pagf_init) { error = xfs_alloc_pagf_init(mp, tp, agno, flags); if (error) @@ -1680,7 +1676,6 @@ xfs_dialloc( struct xfs_trans *tp, xfs_ino_t parent, umode_t mode, - int okalloc, struct xfs_buf **IO_agbp, xfs_ino_t *inop) { @@ -1692,6 +1687,7 @@ xfs_dialloc( int noroom = 0; xfs_agnumber_t start_agno; struct xfs_perag *pag; + int okalloc = 1; if (*IO_agbp) { /* @@ -1707,7 +1703,7 @@ xfs_dialloc( * We do not have an agbp, so select an initial allocation * group for inode allocation. */ - start_agno = xfs_ialloc_ag_select(tp, parent, mode, okalloc); + start_agno = xfs_ialloc_ag_select(tp, parent, mode); if (start_agno == NULLAGNUMBER) { *inop = NULLFSINO; return 0; diff --git a/fs/xfs/libxfs/xfs_ialloc.h b/fs/xfs/libxfs/xfs_ialloc.h index d2bdcd5e7312..66a8de0b1caa 100644 --- a/fs/xfs/libxfs/xfs_ialloc.h +++ b/fs/xfs/libxfs/xfs_ialloc.h @@ -81,7 +81,6 @@ xfs_dialloc( struct xfs_trans *tp, /* transaction pointer */ xfs_ino_t parent, /* parent inode (directory) */ umode_t mode, /* mode bits for new inode */ - int okalloc, /* ok to allocate more space */ struct xfs_buf **agbp, /* buf for a.g. inode header */ xfs_ino_t *inop); /* inode number allocated */ diff --git a/fs/xfs/xfs_inode.c b/fs/xfs/xfs_inode.c index 801274126648..b41952a4ddd8 100644 --- a/fs/xfs/xfs_inode.c +++ b/fs/xfs/xfs_inode.c @@ -749,7 +749,6 @@ xfs_ialloc( xfs_nlink_t nlink, dev_t rdev, prid_t prid, - int okalloc, xfs_buf_t **ialloc_context, xfs_inode_t **ipp) { @@ -765,7 +764,7 @@ xfs_ialloc( * Call the space management code to pick * the on-disk inode to be allocated. */ - error = xfs_dialloc(tp, pip ? pip->i_ino : 0, mode, okalloc, + error = xfs_dialloc(tp, pip ? pip->i_ino : 0, mode, ialloc_context, &ino); if (error) return error; @@ -957,7 +956,6 @@ xfs_dir_ialloc( xfs_nlink_t nlink, dev_t rdev, prid_t prid, /* project id */ - int okalloc, /* ok to allocate new space */ xfs_inode_t **ipp, /* pointer to inode; it will be locked. */ int *committed) @@ -988,8 +986,8 @@ xfs_dir_ialloc( * transaction commit so that no other process can steal * the inode(s) that we've just allocated. */ - code = xfs_ialloc(tp, dp, mode, nlink, rdev, prid, okalloc, - &ialloc_context, &ip); + code = xfs_ialloc(tp, dp, mode, nlink, rdev, prid, &ialloc_context, + &ip); /* * Return an error if we were unable to allocate a new inode. @@ -1061,7 +1059,7 @@ xfs_dir_ialloc( * this call should always succeed. */ code = xfs_ialloc(tp, dp, mode, nlink, rdev, prid, - okalloc, &ialloc_context, &ip); + &ialloc_context, &ip); /* * If we get an error at this point, return to the caller @@ -1182,11 +1180,6 @@ xfs_create( xfs_flush_inodes(mp); error = xfs_trans_alloc(mp, tres, resblks, 0, 0, &tp); } - if (error == -ENOSPC) { - /* No space at all so try a "no-allocation" reservation */ - resblks = 0; - error = xfs_trans_alloc(mp, tres, 0, 0, 0, &tp); - } if (error) goto out_release_inode; @@ -1203,19 +1196,13 @@ xfs_create( if (error) goto out_trans_cancel; - if (!resblks) { - error = xfs_dir_canenter(tp, dp, name); - if (error) - goto out_trans_cancel; - } - /* * A newly created regular or special file just has one directory * entry pointing to them, but a directory also the "." entry * pointing to itself. */ - error = xfs_dir_ialloc(&tp, dp, mode, is_dir ? 2 : 1, rdev, - prid, resblks > 0, &ip, NULL); + error = xfs_dir_ialloc(&tp, dp, mode, is_dir ? 2 : 1, rdev, prid, &ip, + NULL); if (error) goto out_trans_cancel; @@ -1340,11 +1327,6 @@ xfs_create_tmpfile( tres = &M_RES(mp)->tr_create_tmpfile; error = xfs_trans_alloc(mp, tres, resblks, 0, 0, &tp); - if (error == -ENOSPC) { - /* No space at all so try a "no-allocation" reservation */ - resblks = 0; - error = xfs_trans_alloc(mp, tres, 0, 0, 0, &tp); - } if (error) goto out_release_inode; @@ -1353,8 +1335,7 @@ xfs_create_tmpfile( if (error) goto out_trans_cancel; - error = xfs_dir_ialloc(&tp, dp, mode, 1, 0, - prid, resblks > 0, &ip, NULL); + error = xfs_dir_ialloc(&tp, dp, mode, 1, 0, prid, &ip, NULL); if (error) goto out_trans_cancel; diff --git a/fs/xfs/xfs_inode.h b/fs/xfs/xfs_inode.h index cc13c3763721..b2136af9289f 100644 --- a/fs/xfs/xfs_inode.h +++ b/fs/xfs/xfs_inode.h @@ -428,7 +428,7 @@ xfs_extlen_t xfs_get_extsz_hint(struct xfs_inode *ip); xfs_extlen_t xfs_get_cowextsz_hint(struct xfs_inode *ip); int xfs_dir_ialloc(struct xfs_trans **, struct xfs_inode *, umode_t, - xfs_nlink_t, dev_t, prid_t, int, + xfs_nlink_t, dev_t, prid_t, struct xfs_inode **, int *); /* from xfs_file.c */ diff --git a/fs/xfs/xfs_qm.c b/fs/xfs/xfs_qm.c index 010a13a201aa..ec952dfad359 100644 --- a/fs/xfs/xfs_qm.c +++ b/fs/xfs/xfs_qm.c @@ -793,8 +793,8 @@ xfs_qm_qino_alloc( return error; if (need_alloc) { - error = xfs_dir_ialloc(&tp, NULL, S_IFREG, 1, 0, 0, 1, ip, - &committed); + error = xfs_dir_ialloc(&tp, NULL, S_IFREG, 1, 0, 0, ip, + &committed); if (error) { xfs_trans_cancel(tp); return error; diff --git a/fs/xfs/xfs_symlink.c b/fs/xfs/xfs_symlink.c index 68d3ca2c4968..2e9e793a8f9d 100644 --- a/fs/xfs/xfs_symlink.c +++ b/fs/xfs/xfs_symlink.c @@ -232,11 +232,6 @@ xfs_symlink( resblks = XFS_SYMLINK_SPACE_RES(mp, link_name->len, fs_blocks); error = xfs_trans_alloc(mp, &M_RES(mp)->tr_symlink, resblks, 0, 0, &tp); - if (error == -ENOSPC && fs_blocks == 0) { - resblks = 0; - error = xfs_trans_alloc(mp, &M_RES(mp)->tr_symlink, 0, 0, 0, - &tp); - } if (error) goto out_release_inode; @@ -259,14 +254,6 @@ xfs_symlink( if (error) goto out_trans_cancel; - /* - * Check for ability to enter directory entry, if no space reserved. - */ - if (!resblks) { - error = xfs_dir_canenter(tp, dp, link_name); - if (error) - goto out_trans_cancel; - } /* * Initialize the bmap freelist prior to calling either * bmapi or the directory create code. @@ -277,7 +264,7 @@ xfs_symlink( * Allocate an inode for the symlink. */ error = xfs_dir_ialloc(&tp, dp, S_IFLNK | (mode & ~S_IFMT), 1, 0, - prid, resblks > 0, &ip, NULL); + prid, &ip, NULL); if (error) goto out_trans_cancel; -- GitLab From b7e0b6ff54dd92febbb1914ab93cd6a21622e169 Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Wed, 6 Dec 2017 16:13:35 -0800 Subject: [PATCH 1175/2547] xfs: make iomap_begin functions trim iomaps consistently Historically, the XFS iomap_begin function only returned mappings for exactly the range queried, i.e. it doesn't do XFS_BMAPI_ENTIRE lookups. The current vfs iomap consumers are only set up to deal with trimmed mappings. xfs_xattr_iomap_begin does BMAPI_ENTIRE lookups, which is inconsistent with the current iomap usage. Remove the flag so that both iomap_begin functions behave the same way. FWIW this also fixes a behavioral regression in xattr FIEMAP that was introduced in 4.8 wherein attr fork extents are no longer trimmed like they used to be. Signed-off-by: Darrick J. Wong Reviewed-by: Christoph Hellwig --- fs/xfs/xfs_iomap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/xfs/xfs_iomap.c b/fs/xfs/xfs_iomap.c index 33eb4fb2e3fd..7ab52a8bc0a9 100644 --- a/fs/xfs/xfs_iomap.c +++ b/fs/xfs/xfs_iomap.c @@ -1213,7 +1213,7 @@ xfs_xattr_iomap_begin( ASSERT(ip->i_d.di_aformat != XFS_DINODE_FMT_LOCAL); error = xfs_bmapi_read(ip, offset_fsb, end_fsb - offset_fsb, &imap, - &nimaps, XFS_BMAPI_ENTIRE | XFS_BMAPI_ATTRFORK); + &nimaps, XFS_BMAPI_ATTRFORK); out_unlock: xfs_iunlock(ip, lockmode); -- GitLab From 8cce58fe698a34227b396217556a342c10ae037d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 8 Dec 2017 23:08:39 -0500 Subject: [PATCH 1176/2547] drm/amd: add new interface to query cu info Signed-off-by: Flora Cui Signed-off-by: Harish Kasiviswanathan Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- .../gpu/drm/amd/include/kgd_kfd_interface.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index fe3079a33a3d..3a93ffeae1ae 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -46,6 +46,20 @@ enum kfd_preempt_type { KFD_PREEMPT_TYPE_WAVEFRONT_RESET, }; +struct kfd_cu_info { + uint32_t num_shader_engines; + uint32_t num_shader_arrays_per_engine; + uint32_t num_cu_per_sh; + uint32_t cu_active_number; + uint32_t cu_ao_mask; + uint32_t simd_per_cu; + uint32_t max_waves_per_simd; + uint32_t wave_front_size; + uint32_t max_scratch_slots_per_cu; + uint32_t lds_size; + uint32_t cu_bitmap[4][4]; +}; + enum kgd_memory_pool { KGD_POOL_SYSTEM_CACHEABLE = 1, KGD_POOL_SYSTEM_WRITECOMBINE = 2, @@ -153,6 +167,8 @@ struct tile_config { * * @get_tile_config: Returns GPU-specific tiling mode information * + * @get_cu_info: Retrieves activated cu info + * * This structure contains function pointers to services that the kgd driver * provides to amdkfd driver. * @@ -239,6 +255,9 @@ struct kfd2kgd_calls { void (*set_scratch_backing_va)(struct kgd_dev *kgd, uint64_t va, uint32_t vmid); int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config); + + void (*get_cu_info)(struct kgd_dev *kgd, + struct kfd_cu_info *cu_info); }; /** -- GitLab From ebdebf428ae6b5921cc25913672b954c6897d349 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 8 Dec 2017 23:08:40 -0500 Subject: [PATCH 1177/2547] drm/amdgpu: add amdgpu interface to query cu info Signed-off-by: Flora Cui Signed-off-by: Harish Kasiviswanathan Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 23 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 1 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 7 ++++++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 ++++ 7 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index bbe06e04dcb6..e40c5df55f95 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -959,6 +959,7 @@ struct amdgpu_gfx_config { }; struct amdgpu_cu_info { + uint32_t simd_per_cu; uint32_t max_waves_per_simd; uint32_t wave_front_size; uint32_t max_scratch_slots_per_cu; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 01aa851938f8..48c1675aa342 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -304,3 +304,26 @@ uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd) return amdgpu_dpm_get_sclk(adev, false) / 100; } + +void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_cu_info acu_info = adev->gfx.cu_info; + + memset(cu_info, 0, sizeof(*cu_info)); + if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) + return; + + cu_info->cu_active_number = acu_info.number; + cu_info->cu_ao_mask = acu_info.ao_cu_mask; + memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], + sizeof(acu_info.bitmap)); + cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; + cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; + cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; + cu_info->simd_per_cu = acu_info.simd_per_cu; + cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; + cu_info->wave_front_size = acu_info.wave_front_size; + cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; + cu_info->lds_size = acu_info.lds_size; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 8d689ab7e429..a8fa2253817b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -60,6 +60,7 @@ uint64_t get_vmem_size(struct kgd_dev *kgd); uint64_t get_gpu_clock_counter(struct kgd_dev *kgd); uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd); +void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info); #define read_user_wptr(mmptr, wptr, dst) \ ({ \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index 12feba8091df..c9b98d09a09b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c @@ -200,6 +200,7 @@ static const struct kfd2kgd_calls kfd2kgd = { .get_fw_version = get_fw_version, .set_scratch_backing_va = set_scratch_backing_va, .get_tile_config = get_tile_config, + .get_cu_info = get_cu_info }; struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index b38049569264..c538e3029f6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -161,6 +161,7 @@ static const struct kfd2kgd_calls kfd2kgd = { .get_fw_version = get_fw_version, .set_scratch_backing_va = set_scratch_backing_va, .get_tile_config = get_tile_config, + .get_cu_info = get_cu_info }; struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 83d94c23aa78..9c62ebd5a19c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -48,6 +48,8 @@ #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" +#define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */ + #define GFX7_NUM_GFX_RINGS 1 #define GFX7_MEC_HPD_SIZE 2048 @@ -5277,6 +5279,11 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) cu_info->number = active_cu_number; cu_info->ao_cu_mask = ao_cu_mask; + cu_info->simd_per_cu = NUM_SIMD_PER_CU; + cu_info->max_waves_per_simd = 10; + cu_info->max_scratch_slots_per_cu = 32; + cu_info->wave_front_size = 64; + cu_info->lds_size = 64; } const struct amdgpu_ip_block_version gfx_v7_0_ip_block = diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 46550b588982..e18c2e62a20b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -7116,6 +7116,11 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev) cu_info->number = active_cu_number; cu_info->ao_cu_mask = ao_cu_mask; + cu_info->simd_per_cu = NUM_SIMD_PER_CU; + cu_info->max_waves_per_simd = 10; + cu_info->max_scratch_slots_per_cu = 32; + cu_info->wave_front_size = 64; + cu_info->lds_size = 64; } const struct amdgpu_ip_block_version gfx_v8_0_ip_block = -- GitLab From 4073ed7838efc10b3dcc08ee72918a16ba14de28 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:08:41 -0500 Subject: [PATCH 1178/2547] drm/amd: Add get_local_mem_info to KGD-KFD interface Add get_local_mem_info which provides more information about local memory than get_vmem_size: - public and private framebuffer size - memory clock Signed-off-by: Harish Kasiviswanathan Signed-off-by: Ben Goz Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 3a93ffeae1ae..c58389c88911 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -60,6 +60,14 @@ struct kfd_cu_info { uint32_t cu_bitmap[4][4]; }; +/* For getting GPU local memory information from KGD */ +struct kfd_local_mem_info { + uint64_t local_mem_size_private; + uint64_t local_mem_size_public; + uint32_t vram_width; + uint32_t mem_clk_max; +}; + enum kgd_memory_pool { KGD_POOL_SYSTEM_CACHEABLE = 1, KGD_POOL_SYSTEM_WRITECOMBINE = 2, @@ -122,6 +130,8 @@ struct tile_config { * * @get_vmem_size: Retrieves (physical) size of VRAM * + * @get_local_mem_info: Retrieves information about GPU local memory + * * @get_gpu_clock_counter: Retrieves GPU clock counter * * @get_max_engine_clock_in_mhz: Retrieves maximum GPU clock in MHz @@ -181,6 +191,8 @@ struct kfd2kgd_calls { void (*free_gtt_mem)(struct kgd_dev *kgd, void *mem_obj); uint64_t (*get_vmem_size)(struct kgd_dev *kgd); + void (*get_local_mem_info)(struct kgd_dev *kgd, + struct kfd_local_mem_info *mem_info); uint64_t (*get_gpu_clock_counter)(struct kgd_dev *kgd); uint32_t (*get_max_engine_clock_in_mhz)(struct kgd_dev *kgd); -- GitLab From 30f1c0421ec5f47ab4375eb0fc34e64f79fb0a25 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:08:42 -0500 Subject: [PATCH 1179/2547] drm/amdgpu: Implement get_local_mem_info Implement new kgd-kfd interface function get_local_mem_info. Signed-off-by: Harish Kasiviswanathan Signed-off-by: Ben Goz Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 30 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 ++ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 1 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 1 + 4 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 48c1675aa342..26d5ddc50fef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -285,6 +285,36 @@ uint64_t get_vmem_size(struct kgd_dev *kgd) return adev->mc.real_vram_size; } +void get_local_mem_info(struct kgd_dev *kgd, + struct kfd_local_mem_info *mem_info) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask : + ~((1ULL << 32) - 1); + resource_size_t aper_limit = adev->mc.aper_base + adev->mc.aper_size; + + memset(mem_info, 0, sizeof(*mem_info)); + if (!(adev->mc.aper_base & address_mask || aper_limit & address_mask)) { + mem_info->local_mem_size_public = adev->mc.visible_vram_size; + mem_info->local_mem_size_private = adev->mc.real_vram_size - + adev->mc.visible_vram_size; + } else { + mem_info->local_mem_size_public = 0; + mem_info->local_mem_size_private = adev->mc.real_vram_size; + } + mem_info->vram_width = adev->mc.vram_width; + + pr_debug("Address base: 0x%llx limit 0x%llx public 0x%llx private 0x%llx\n", + adev->mc.aper_base, aper_limit, + mem_info->local_mem_size_public, + mem_info->local_mem_size_private); + + if (amdgpu_sriov_vf(adev)) + mem_info->mem_clk_max = adev->clock.default_mclk / 100; + else + mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; +} + uint64_t get_gpu_clock_counter(struct kgd_dev *kgd) { struct amdgpu_device *adev = (struct amdgpu_device *)kgd; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index a8fa2253817b..bc5385a268b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -57,6 +57,8 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, void **cpu_ptr); void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj); uint64_t get_vmem_size(struct kgd_dev *kgd); +void get_local_mem_info(struct kgd_dev *kgd, + struct kfd_local_mem_info *mem_info); uint64_t get_gpu_clock_counter(struct kgd_dev *kgd); uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index c9b98d09a09b..b705608a9196 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c @@ -174,6 +174,7 @@ static const struct kfd2kgd_calls kfd2kgd = { .init_gtt_mem_allocation = alloc_gtt_mem, .free_gtt_mem = free_gtt_mem, .get_vmem_size = get_vmem_size, + .get_local_mem_info = get_local_mem_info, .get_gpu_clock_counter = get_gpu_clock_counter, .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, .alloc_pasid = amdgpu_vm_alloc_pasid, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index c538e3029f6f..b0e581a8ac5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -133,6 +133,7 @@ static const struct kfd2kgd_calls kfd2kgd = { .init_gtt_mem_allocation = alloc_gtt_mem, .free_gtt_mem = free_gtt_mem, .get_vmem_size = get_vmem_size, + .get_local_mem_info = get_local_mem_info, .get_gpu_clock_counter = get_gpu_clock_counter, .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, .alloc_pasid = amdgpu_vm_alloc_pasid, -- GitLab From 0504cccf34fe3e775fe3e66050b4020e6fea03b7 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:08:43 -0500 Subject: [PATCH 1180/2547] drm/amdkfd: Stop using get_vmem_size KGD-KFD interface get_vmem_size() is deprecated. Instead use get_local_mem_info(). Signed-off-by: Harish Kasiviswanathan Signed-off-by: Ben Goz Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 9d03a56fd9c7..cb0303a323d2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1073,11 +1073,15 @@ static uint32_t kfd_generate_gpu_id(struct kfd_dev *gpu) uint32_t buf[7]; uint64_t local_mem_size; int i; + struct kfd_local_mem_info local_mem_info; if (!gpu) return 0; - local_mem_size = gpu->kfd2kgd->get_vmem_size(gpu->kgd); + gpu->kfd2kgd->get_local_mem_info(gpu->kgd, &local_mem_info); + + local_mem_size = local_mem_info.local_mem_size_private + + local_mem_info.local_mem_size_public; buf[0] = gpu->pdev->devfn; buf[1] = gpu->pdev->subsystem_vendor; -- GitLab From b4ec7757ba9a19f9e1d1b13adaba754f91655c2a Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:08:44 -0500 Subject: [PATCH 1181/2547] drm/amdkfd: Remove deprecated get_vmem_size Signed-off-by: Harish Kasiviswanathan Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 10 ---------- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 1 - 4 files changed, 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 26d5ddc50fef..996d3538f751 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -275,16 +275,6 @@ void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj) kfree(mem); } -uint64_t get_vmem_size(struct kgd_dev *kgd) -{ - struct amdgpu_device *adev = - (struct amdgpu_device *)kgd; - - BUG_ON(kgd == NULL); - - return adev->mc.real_vram_size; -} - void get_local_mem_info(struct kgd_dev *kgd, struct kfd_local_mem_info *mem_info) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index bc5385a268b4..eed7dea5e8ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -56,7 +56,6 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, void **mem_obj, uint64_t *gpu_addr, void **cpu_ptr); void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj); -uint64_t get_vmem_size(struct kgd_dev *kgd); void get_local_mem_info(struct kgd_dev *kgd, struct kfd_local_mem_info *mem_info); uint64_t get_gpu_clock_counter(struct kgd_dev *kgd); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index b705608a9196..c9e2fbe151ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c @@ -173,7 +173,6 @@ static int get_tile_config(struct kgd_dev *kgd, static const struct kfd2kgd_calls kfd2kgd = { .init_gtt_mem_allocation = alloc_gtt_mem, .free_gtt_mem = free_gtt_mem, - .get_vmem_size = get_vmem_size, .get_local_mem_info = get_local_mem_info, .get_gpu_clock_counter = get_gpu_clock_counter, .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index b0e581a8ac5e..72ff6463594d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -132,7 +132,6 @@ static int get_tile_config(struct kgd_dev *kgd, static const struct kfd2kgd_calls kfd2kgd = { .init_gtt_mem_allocation = alloc_gtt_mem, .free_gtt_mem = free_gtt_mem, - .get_vmem_size = get_vmem_size, .get_local_mem_info = get_local_mem_info, .get_gpu_clock_counter = get_gpu_clock_counter, .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, -- GitLab From 4248bd0b102ae832cddf961b94a125385a2dfc92 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:08:45 -0500 Subject: [PATCH 1182/2547] drm/amd: Remove get_vmem_size from KGD-KFD interface Signed-off-by: Harish Kasiviswanathan Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index c58389c88911..0899cee6a60f 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -128,8 +128,6 @@ struct tile_config { * * @free_gtt_mem: Frees a buffer that was allocated on the gart aperture * - * @get_vmem_size: Retrieves (physical) size of VRAM - * * @get_local_mem_info: Retrieves information about GPU local memory * * @get_gpu_clock_counter: Retrieves GPU clock counter @@ -190,7 +188,6 @@ struct kfd2kgd_calls { void (*free_gtt_mem)(struct kgd_dev *kgd, void *mem_obj); - uint64_t (*get_vmem_size)(struct kgd_dev *kgd); void (*get_local_mem_info)(struct kgd_dev *kgd, struct kfd_local_mem_info *mem_info); uint64_t (*get_gpu_clock_counter)(struct kgd_dev *kgd); -- GitLab From f7ce2fade6e143a333dc51d84f2080738d6831bf Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 8 Dec 2017 23:08:46 -0500 Subject: [PATCH 1183/2547] drm/amdkfd: Update number of compute unit from KGD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Overwrite the active simd_count from KGD at driver loading time. This is based on assumption that register GC_USER_SHADER_ARRAY_CONFIG won’t get changed. V2: remove the incorrect simd_count reported at loading module. Signed-off-by: Flora Cui Reviewed by: Yair Shachar< yair.shachar@amd.com> Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index cb0303a323d2..ca2e51a2fe75 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -133,8 +133,7 @@ static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev, dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu; if (cu->hsa_capability & CRAT_CU_FLAGS_HOT_PLUGGABLE) dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE; - pr_info("CU GPU: simds=%d id_base=%d\n", cu->num_simd_cores, - cu->processor_id_low); + pr_info("CU GPU: id_base=%d\n", cu->processor_id_low); } /* kfd_parse_subtype_cu is called when the topology mutex is already acquired */ @@ -1124,6 +1123,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu) { uint32_t gpu_id; struct kfd_topology_device *dev; + struct kfd_cu_info cu_info; int res; gpu_id = kfd_generate_gpu_id(gpu); @@ -1161,6 +1161,9 @@ int kfd_topology_add_device(struct kfd_dev *gpu) dev->gpu_id = gpu_id; gpu->id = gpu_id; + dev->gpu->kfd2kgd->get_cu_info(dev->gpu->kgd, &cu_info); + dev->node_props.simd_count = dev->node_props.simd_per_cu * + cu_info.cu_active_number; dev->node_props.vendor_id = gpu->pdev->vendor; dev->node_props.device_id = gpu->pdev->device; dev->node_props.location_id = (gpu->pdev->bus->number << 24) + -- GitLab From d63f0ba27a3ee33211de4ec7f2c4287a03492cb2 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:08:47 -0500 Subject: [PATCH 1184/2547] drm/amdkfd: Topology: Fix location_id Fix location_id format to match Thunk specification. Signed-off-by: Harish Kasiviswanathan Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index ca2e51a2fe75..b614746c2523 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1166,8 +1166,8 @@ int kfd_topology_add_device(struct kfd_dev *gpu) cu_info.cu_active_number; dev->node_props.vendor_id = gpu->pdev->vendor; dev->node_props.device_id = gpu->pdev->device; - dev->node_props.location_id = (gpu->pdev->bus->number << 24) + - (gpu->pdev->devfn & 0xffffff); + dev->node_props.location_id = PCI_DEVID(gpu->pdev->bus->number, + gpu->pdev->devfn); /* * TODO: Retrieve max engine clock values from KGD */ -- GitLab From 5108d768408abc80e4e8d99f5b406a73cb04056b Mon Sep 17 00:00:00 2001 From: Yong Zhao Date: Fri, 8 Dec 2017 23:08:48 -0500 Subject: [PATCH 1185/2547] drm/amdkfd: Fix memory leaks in kfd topology Kobject created using kobject_create_and_add() can be freed using kobject_put() when there is no referenece any more. However, kobject memory allocated with kzalloc() has to set up a release callback in order to free it when the counter decreases to 0. Otherwise it causes memory leak. Signed-off-by: Yong Zhao Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index b614746c2523..9b9824f97de5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -501,11 +501,17 @@ static ssize_t sysprops_show(struct kobject *kobj, struct attribute *attr, return ret; } +static void kfd_topology_kobj_release(struct kobject *kobj) +{ + kfree(kobj); +} + static const struct sysfs_ops sysprops_ops = { .show = sysprops_show, }; static struct kobj_type sysprops_type = { + .release = kfd_topology_kobj_release, .sysfs_ops = &sysprops_ops, }; @@ -541,6 +547,7 @@ static const struct sysfs_ops iolink_ops = { }; static struct kobj_type iolink_type = { + .release = kfd_topology_kobj_release, .sysfs_ops = &iolink_ops, }; @@ -568,6 +575,7 @@ static const struct sysfs_ops mem_ops = { }; static struct kobj_type mem_type = { + .release = kfd_topology_kobj_release, .sysfs_ops = &mem_ops, }; @@ -607,6 +615,7 @@ static const struct sysfs_ops cache_ops = { }; static struct kobj_type cache_type = { + .release = kfd_topology_kobj_release, .sysfs_ops = &cache_ops, }; @@ -729,6 +738,7 @@ static const struct sysfs_ops node_ops = { }; static struct kobj_type node_type = { + .release = kfd_topology_kobj_release, .sysfs_ops = &node_ops, }; -- GitLab From 174de876d6d02f7159363495a3f34461ba91d3ee Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 8 Dec 2017 23:08:49 -0500 Subject: [PATCH 1186/2547] drm/amdkfd: Group up CRAT related functions Take CRAT related functions out of kfd_topology.c and place them in kfd_crat.c. This is the initial step of supporting more CRAT features, i.e. creating virtual CRAT table for KFD devices without CRAT. v2: Minor cleanup that was missed previously because code moved around Signed-off-by: Amber Lin Signed-off-by: Kent Russell Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/Makefile | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 350 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 5 +- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 334 +-------------------- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 3 +- 5 files changed, 362 insertions(+), 332 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_crat.c diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 67e2c42a5e65..a317e76ffb5e 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -35,7 +35,7 @@ amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \ kfd_process_queue_manager.o kfd_device_queue_manager.o \ kfd_device_queue_manager_cik.o kfd_device_queue_manager_vi.o \ kfd_interrupt.o kfd_events.o cik_event_interrupt.o \ - kfd_dbgdev.o kfd_dbgmgr.o + kfd_dbgdev.o kfd_dbgmgr.o kfd_crat.o amdkfd-$(CONFIG_DEBUG_FS) += kfd_debugfs.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c new file mode 100644 index 000000000000..f2dda6012b77 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -0,0 +1,350 @@ +/* + * Copyright 2015-2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include "kfd_crat.h" +#include "kfd_topology.h" + +static int topology_crat_parsed; +extern struct list_head topology_device_list; +extern struct kfd_system_properties sys_props; + +static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, + struct crat_subtype_computeunit *cu) +{ + dev->node_props.cpu_cores_count = cu->num_cpu_cores; + dev->node_props.cpu_core_id_base = cu->processor_id_low; + if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT) + dev->node_props.capability |= HSA_CAP_ATS_PRESENT; + + pr_info("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores, + cu->processor_id_low); +} + +static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev, + struct crat_subtype_computeunit *cu) +{ + dev->node_props.simd_id_base = cu->processor_id_low; + dev->node_props.simd_count = cu->num_simd_cores; + dev->node_props.lds_size_in_kb = cu->lds_size_in_kb; + dev->node_props.max_waves_per_simd = cu->max_waves_simd; + dev->node_props.wave_front_size = cu->wave_front_size; + dev->node_props.mem_banks_count = cu->num_banks; + dev->node_props.array_count = cu->num_arrays; + dev->node_props.cu_per_simd_array = cu->num_cu_per_array; + dev->node_props.simd_per_cu = cu->num_simd_per_cu; + dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu; + if (cu->hsa_capability & CRAT_CU_FLAGS_HOT_PLUGGABLE) + dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE; + pr_info("CU GPU: id_base=%d\n", cu->processor_id_low); +} + +/* kfd_parse_subtype_cu is called when the topology mutex is already acquired */ +static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu) +{ + struct kfd_topology_device *dev; + int i = 0; + + pr_info("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n", + cu->proximity_domain, cu->hsa_capability); + list_for_each_entry(dev, &topology_device_list, list) { + if (cu->proximity_domain == i) { + if (cu->flags & CRAT_CU_FLAGS_CPU_PRESENT) + kfd_populated_cu_info_cpu(dev, cu); + + if (cu->flags & CRAT_CU_FLAGS_GPU_PRESENT) + kfd_populated_cu_info_gpu(dev, cu); + break; + } + i++; + } + + return 0; +} + +/* + * kfd_parse_subtype_mem is called when the topology mutex is + * already acquired + */ +static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem) +{ + struct kfd_mem_properties *props; + struct kfd_topology_device *dev; + int i = 0; + + pr_info("Found memory entry in CRAT table with proximity_domain=%d\n", + mem->proximity_domain); + list_for_each_entry(dev, &topology_device_list, list) { + if (mem->proximity_domain == i) { + props = kfd_alloc_struct(props); + if (!props) + return -ENOMEM; + + if (dev->node_props.cpu_cores_count == 0) + props->heap_type = HSA_MEM_HEAP_TYPE_FB_PRIVATE; + else + props->heap_type = HSA_MEM_HEAP_TYPE_SYSTEM; + + if (mem->flags & CRAT_MEM_FLAGS_HOT_PLUGGABLE) + props->flags |= HSA_MEM_FLAGS_HOT_PLUGGABLE; + if (mem->flags & CRAT_MEM_FLAGS_NON_VOLATILE) + props->flags |= HSA_MEM_FLAGS_NON_VOLATILE; + + props->size_in_bytes = + ((uint64_t)mem->length_high << 32) + + mem->length_low; + props->width = mem->width; + + dev->mem_bank_count++; + list_add_tail(&props->list, &dev->mem_props); + + break; + } + i++; + } + + return 0; +} + +/* + * kfd_parse_subtype_cache is called when the topology mutex + * is already acquired + */ +static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache) +{ + struct kfd_cache_properties *props; + struct kfd_topology_device *dev; + uint32_t id; + + id = cache->processor_id_low; + + pr_info("Found cache entry in CRAT table with processor_id=%d\n", id); + list_for_each_entry(dev, &topology_device_list, list) + if (id == dev->node_props.cpu_core_id_base || + id == dev->node_props.simd_id_base) { + props = kfd_alloc_struct(props); + if (!props) + return -ENOMEM; + + props->processor_id_low = id; + props->cache_level = cache->cache_level; + props->cache_size = cache->cache_size; + props->cacheline_size = cache->cache_line_size; + props->cachelines_per_tag = cache->lines_per_tag; + props->cache_assoc = cache->associativity; + props->cache_latency = cache->cache_latency; + + if (cache->flags & CRAT_CACHE_FLAGS_DATA_CACHE) + props->cache_type |= HSA_CACHE_TYPE_DATA; + if (cache->flags & CRAT_CACHE_FLAGS_INST_CACHE) + props->cache_type |= HSA_CACHE_TYPE_INSTRUCTION; + if (cache->flags & CRAT_CACHE_FLAGS_CPU_CACHE) + props->cache_type |= HSA_CACHE_TYPE_CPU; + if (cache->flags & CRAT_CACHE_FLAGS_SIMD_CACHE) + props->cache_type |= HSA_CACHE_TYPE_HSACU; + + dev->cache_count++; + dev->node_props.caches_count++; + list_add_tail(&props->list, &dev->cache_props); + + break; + } + + return 0; +} + +/* + * kfd_parse_subtype_iolink is called when the topology mutex + * is already acquired + */ +static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink) +{ + struct kfd_iolink_properties *props; + struct kfd_topology_device *dev; + uint32_t i = 0; + uint32_t id_from; + uint32_t id_to; + + id_from = iolink->proximity_domain_from; + id_to = iolink->proximity_domain_to; + + pr_info("Found IO link entry in CRAT table with id_from=%d\n", id_from); + list_for_each_entry(dev, &topology_device_list, list) { + if (id_from == i) { + props = kfd_alloc_struct(props); + if (!props) + return -ENOMEM; + + props->node_from = id_from; + props->node_to = id_to; + props->ver_maj = iolink->version_major; + props->ver_min = iolink->version_minor; + + /* + * weight factor (derived from CDIR), currently always 1 + */ + props->weight = 1; + + props->min_latency = iolink->minimum_latency; + props->max_latency = iolink->maximum_latency; + props->min_bandwidth = iolink->minimum_bandwidth_mbs; + props->max_bandwidth = iolink->maximum_bandwidth_mbs; + props->rec_transfer_size = + iolink->recommended_transfer_size; + + dev->io_link_count++; + dev->node_props.io_links_count++; + list_add_tail(&props->list, &dev->io_link_props); + + break; + } + i++; + } + + return 0; +} + +static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr) +{ + struct crat_subtype_computeunit *cu; + struct crat_subtype_memory *mem; + struct crat_subtype_cache *cache; + struct crat_subtype_iolink *iolink; + int ret = 0; + + switch (sub_type_hdr->type) { + case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY: + cu = (struct crat_subtype_computeunit *)sub_type_hdr; + ret = kfd_parse_subtype_cu(cu); + break; + case CRAT_SUBTYPE_MEMORY_AFFINITY: + mem = (struct crat_subtype_memory *)sub_type_hdr; + ret = kfd_parse_subtype_mem(mem); + break; + case CRAT_SUBTYPE_CACHE_AFFINITY: + cache = (struct crat_subtype_cache *)sub_type_hdr; + ret = kfd_parse_subtype_cache(cache); + break; + case CRAT_SUBTYPE_TLB_AFFINITY: + /* + * For now, nothing to do here + */ + pr_info("Found TLB entry in CRAT table (not processing)\n"); + break; + case CRAT_SUBTYPE_CCOMPUTE_AFFINITY: + /* + * For now, nothing to do here + */ + pr_info("Found CCOMPUTE entry in CRAT table (not processing)\n"); + break; + case CRAT_SUBTYPE_IOLINK_AFFINITY: + iolink = (struct crat_subtype_iolink *)sub_type_hdr; + ret = kfd_parse_subtype_iolink(iolink); + break; + default: + pr_warn("Unknown subtype %d in CRAT\n", + sub_type_hdr->type); + } + + return ret; +} + +int kfd_parse_crat_table(void *crat_image) +{ + struct kfd_topology_device *top_dev; + struct crat_subtype_generic *sub_type_hdr; + uint16_t node_id; + int ret; + struct crat_header *crat_table = (struct crat_header *)crat_image; + uint16_t num_nodes; + uint32_t image_len; + + if (!crat_image) + return -EINVAL; + + num_nodes = crat_table->num_domains; + image_len = crat_table->length; + + pr_info("Parsing CRAT table with %d nodes\n", num_nodes); + + for (node_id = 0; node_id < num_nodes; node_id++) { + top_dev = kfd_create_topology_device(); + if (!top_dev) { + kfd_release_live_view(); + return -ENOMEM; + } + } + + sys_props.platform_id = + (*((uint64_t *)crat_table->oem_id)) & CRAT_OEMID_64BIT_MASK; + sys_props.platform_oem = *((uint64_t *)crat_table->oem_table_id); + sys_props.platform_rev = crat_table->revision; + + sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1); + while ((char *)sub_type_hdr + sizeof(struct crat_subtype_generic) < + ((char *)crat_image) + image_len) { + if (sub_type_hdr->flags & CRAT_SUBTYPE_FLAGS_ENABLED) { + ret = kfd_parse_subtype(sub_type_hdr); + if (ret != 0) { + kfd_release_live_view(); + return ret; + } + } + + sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + + sub_type_hdr->length); + } + + sys_props.generation_count++; + topology_crat_parsed = 1; + + return 0; +} + +int kfd_topology_get_crat_acpi(void *crat_image, size_t *size) +{ + struct acpi_table_header *crat_table; + acpi_status status; + + if (!size) + return -EINVAL; + + /* + * Fetch the CRAT table from ACPI + */ + status = acpi_get_table(CRAT_SIGNATURE, 0, &crat_table); + if (status == AE_NOT_FOUND) { + pr_warn("CRAT table not found\n"); + return -ENODATA; + } else if (ACPI_FAILURE(status)) { + const char *err = acpi_format_exception(status); + + pr_err("CRAT table error: %s\n", err); + return -EINVAL; + } + + if (*size >= crat_table->length && crat_image != NULL) + memcpy(crat_image, crat_table, crat_table->length); + + *size = crat_table->length; + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h index a374fa3d3ee6..920697b4469b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h @@ -127,7 +127,7 @@ struct crat_subtype_memory { uint8_t length; uint16_t reserved; uint32_t flags; - uint32_t promixity_domain; + uint32_t proximity_domain; uint32_t base_addr_low; uint32_t base_addr_high; uint32_t length_low; @@ -291,4 +291,7 @@ struct cdit_header { #pragma pack() +int kfd_topology_get_crat_acpi(void *crat_image, size_t *size); +int kfd_parse_crat_table(void *crat_image); + #endif /* KFD_CRAT_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 9b9824f97de5..b6cf785d0138 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -34,9 +34,8 @@ #include "kfd_topology.h" #include "kfd_device_queue_manager.h" -static struct list_head topology_device_list; -static int topology_crat_parsed; -static struct kfd_system_properties sys_props; +struct list_head topology_device_list; +struct kfd_system_properties sys_props; static DECLARE_RWSEM(topology_lock); @@ -76,276 +75,6 @@ struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev) return device; } -static int kfd_topology_get_crat_acpi(void *crat_image, size_t *size) -{ - struct acpi_table_header *crat_table; - acpi_status status; - - if (!size) - return -EINVAL; - - /* - * Fetch the CRAT table from ACPI - */ - status = acpi_get_table(CRAT_SIGNATURE, 0, &crat_table); - if (status == AE_NOT_FOUND) { - pr_warn("CRAT table not found\n"); - return -ENODATA; - } else if (ACPI_FAILURE(status)) { - const char *err = acpi_format_exception(status); - - pr_err("CRAT table error: %s\n", err); - return -EINVAL; - } - - if (*size >= crat_table->length && crat_image != NULL) - memcpy(crat_image, crat_table, crat_table->length); - - *size = crat_table->length; - - return 0; -} - -static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, - struct crat_subtype_computeunit *cu) -{ - dev->node_props.cpu_cores_count = cu->num_cpu_cores; - dev->node_props.cpu_core_id_base = cu->processor_id_low; - if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT) - dev->node_props.capability |= HSA_CAP_ATS_PRESENT; - - pr_info("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores, - cu->processor_id_low); -} - -static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev, - struct crat_subtype_computeunit *cu) -{ - dev->node_props.simd_id_base = cu->processor_id_low; - dev->node_props.simd_count = cu->num_simd_cores; - dev->node_props.lds_size_in_kb = cu->lds_size_in_kb; - dev->node_props.max_waves_per_simd = cu->max_waves_simd; - dev->node_props.wave_front_size = cu->wave_front_size; - dev->node_props.mem_banks_count = cu->num_banks; - dev->node_props.array_count = cu->num_arrays; - dev->node_props.cu_per_simd_array = cu->num_cu_per_array; - dev->node_props.simd_per_cu = cu->num_simd_per_cu; - dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu; - if (cu->hsa_capability & CRAT_CU_FLAGS_HOT_PLUGGABLE) - dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE; - pr_info("CU GPU: id_base=%d\n", cu->processor_id_low); -} - -/* kfd_parse_subtype_cu is called when the topology mutex is already acquired */ -static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu) -{ - struct kfd_topology_device *dev; - int i = 0; - - pr_info("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n", - cu->proximity_domain, cu->hsa_capability); - list_for_each_entry(dev, &topology_device_list, list) { - if (cu->proximity_domain == i) { - if (cu->flags & CRAT_CU_FLAGS_CPU_PRESENT) - kfd_populated_cu_info_cpu(dev, cu); - - if (cu->flags & CRAT_CU_FLAGS_GPU_PRESENT) - kfd_populated_cu_info_gpu(dev, cu); - break; - } - i++; - } - - return 0; -} - -/* - * kfd_parse_subtype_mem is called when the topology mutex is - * already acquired - */ -static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem) -{ - struct kfd_mem_properties *props; - struct kfd_topology_device *dev; - int i = 0; - - pr_info("Found memory entry in CRAT table with proximity_domain=%d\n", - mem->promixity_domain); - list_for_each_entry(dev, &topology_device_list, list) { - if (mem->promixity_domain == i) { - props = kfd_alloc_struct(props); - if (props == NULL) - return -ENOMEM; - - if (dev->node_props.cpu_cores_count == 0) - props->heap_type = HSA_MEM_HEAP_TYPE_FB_PRIVATE; - else - props->heap_type = HSA_MEM_HEAP_TYPE_SYSTEM; - - if (mem->flags & CRAT_MEM_FLAGS_HOT_PLUGGABLE) - props->flags |= HSA_MEM_FLAGS_HOT_PLUGGABLE; - if (mem->flags & CRAT_MEM_FLAGS_NON_VOLATILE) - props->flags |= HSA_MEM_FLAGS_NON_VOLATILE; - - props->size_in_bytes = - ((uint64_t)mem->length_high << 32) + - mem->length_low; - props->width = mem->width; - - dev->mem_bank_count++; - list_add_tail(&props->list, &dev->mem_props); - - break; - } - i++; - } - - return 0; -} - -/* - * kfd_parse_subtype_cache is called when the topology mutex - * is already acquired - */ -static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache) -{ - struct kfd_cache_properties *props; - struct kfd_topology_device *dev; - uint32_t id; - - id = cache->processor_id_low; - - pr_info("Found cache entry in CRAT table with processor_id=%d\n", id); - list_for_each_entry(dev, &topology_device_list, list) - if (id == dev->node_props.cpu_core_id_base || - id == dev->node_props.simd_id_base) { - props = kfd_alloc_struct(props); - if (props == NULL) - return -ENOMEM; - - props->processor_id_low = id; - props->cache_level = cache->cache_level; - props->cache_size = cache->cache_size; - props->cacheline_size = cache->cache_line_size; - props->cachelines_per_tag = cache->lines_per_tag; - props->cache_assoc = cache->associativity; - props->cache_latency = cache->cache_latency; - - if (cache->flags & CRAT_CACHE_FLAGS_DATA_CACHE) - props->cache_type |= HSA_CACHE_TYPE_DATA; - if (cache->flags & CRAT_CACHE_FLAGS_INST_CACHE) - props->cache_type |= HSA_CACHE_TYPE_INSTRUCTION; - if (cache->flags & CRAT_CACHE_FLAGS_CPU_CACHE) - props->cache_type |= HSA_CACHE_TYPE_CPU; - if (cache->flags & CRAT_CACHE_FLAGS_SIMD_CACHE) - props->cache_type |= HSA_CACHE_TYPE_HSACU; - - dev->cache_count++; - dev->node_props.caches_count++; - list_add_tail(&props->list, &dev->cache_props); - - break; - } - - return 0; -} - -/* - * kfd_parse_subtype_iolink is called when the topology mutex - * is already acquired - */ -static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink) -{ - struct kfd_iolink_properties *props; - struct kfd_topology_device *dev; - uint32_t i = 0; - uint32_t id_from; - uint32_t id_to; - - id_from = iolink->proximity_domain_from; - id_to = iolink->proximity_domain_to; - - pr_info("Found IO link entry in CRAT table with id_from=%d\n", id_from); - list_for_each_entry(dev, &topology_device_list, list) { - if (id_from == i) { - props = kfd_alloc_struct(props); - if (props == NULL) - return -ENOMEM; - - props->node_from = id_from; - props->node_to = id_to; - props->ver_maj = iolink->version_major; - props->ver_min = iolink->version_minor; - - /* - * weight factor (derived from CDIR), currently always 1 - */ - props->weight = 1; - - props->min_latency = iolink->minimum_latency; - props->max_latency = iolink->maximum_latency; - props->min_bandwidth = iolink->minimum_bandwidth_mbs; - props->max_bandwidth = iolink->maximum_bandwidth_mbs; - props->rec_transfer_size = - iolink->recommended_transfer_size; - - dev->io_link_count++; - dev->node_props.io_links_count++; - list_add_tail(&props->list, &dev->io_link_props); - - break; - } - i++; - } - - return 0; -} - -static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr) -{ - struct crat_subtype_computeunit *cu; - struct crat_subtype_memory *mem; - struct crat_subtype_cache *cache; - struct crat_subtype_iolink *iolink; - int ret = 0; - - switch (sub_type_hdr->type) { - case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY: - cu = (struct crat_subtype_computeunit *)sub_type_hdr; - ret = kfd_parse_subtype_cu(cu); - break; - case CRAT_SUBTYPE_MEMORY_AFFINITY: - mem = (struct crat_subtype_memory *)sub_type_hdr; - ret = kfd_parse_subtype_mem(mem); - break; - case CRAT_SUBTYPE_CACHE_AFFINITY: - cache = (struct crat_subtype_cache *)sub_type_hdr; - ret = kfd_parse_subtype_cache(cache); - break; - case CRAT_SUBTYPE_TLB_AFFINITY: - /* - * For now, nothing to do here - */ - pr_info("Found TLB entry in CRAT table (not processing)\n"); - break; - case CRAT_SUBTYPE_CCOMPUTE_AFFINITY: - /* - * For now, nothing to do here - */ - pr_info("Found CCOMPUTE entry in CRAT table (not processing)\n"); - break; - case CRAT_SUBTYPE_IOLINK_AFFINITY: - iolink = (struct crat_subtype_iolink *)sub_type_hdr; - ret = kfd_parse_subtype_iolink(iolink); - break; - default: - pr_warn("Unknown subtype (%d) in CRAT\n", - sub_type_hdr->type); - } - - return ret; -} - static void kfd_release_topology_device(struct kfd_topology_device *dev) { struct kfd_mem_properties *mem; @@ -380,7 +109,7 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) sys_props.num_devices--; } -static void kfd_release_live_view(void) +void kfd_release_live_view(void) { struct kfd_topology_device *dev; @@ -393,7 +122,7 @@ static void kfd_release_live_view(void) memset(&sys_props, 0, sizeof(sys_props)); } -static struct kfd_topology_device *kfd_create_topology_device(void) +struct kfd_topology_device *kfd_create_topology_device(void) { struct kfd_topology_device *dev; @@ -413,58 +142,6 @@ static struct kfd_topology_device *kfd_create_topology_device(void) return dev; } -static int kfd_parse_crat_table(void *crat_image) -{ - struct kfd_topology_device *top_dev; - struct crat_subtype_generic *sub_type_hdr; - uint16_t node_id; - int ret; - struct crat_header *crat_table = (struct crat_header *)crat_image; - uint16_t num_nodes; - uint32_t image_len; - - if (!crat_image) - return -EINVAL; - - num_nodes = crat_table->num_domains; - image_len = crat_table->length; - - pr_info("Parsing CRAT table with %d nodes\n", num_nodes); - - for (node_id = 0; node_id < num_nodes; node_id++) { - top_dev = kfd_create_topology_device(); - if (!top_dev) { - kfd_release_live_view(); - return -ENOMEM; - } - } - - sys_props.platform_id = - (*((uint64_t *)crat_table->oem_id)) & CRAT_OEMID_64BIT_MASK; - sys_props.platform_oem = *((uint64_t *)crat_table->oem_table_id); - sys_props.platform_rev = crat_table->revision; - - sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1); - while ((char *)sub_type_hdr + sizeof(struct crat_subtype_generic) < - ((char *)crat_image) + image_len) { - if (sub_type_hdr->flags & CRAT_SUBTYPE_FLAGS_ENABLED) { - ret = kfd_parse_subtype(sub_type_hdr); - if (ret != 0) { - kfd_release_live_view(); - return ret; - } - } - - sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + - sub_type_hdr->length); - } - - sys_props.generation_count++; - topology_crat_parsed = 1; - - return 0; -} - #define sysfs_show_gen_prop(buffer, fmt, ...) \ snprintf(buffer, PAGE_SIZE, "%s"fmt, buffer, __VA_ARGS__) @@ -1016,7 +693,6 @@ int kfd_topology_init(void) */ INIT_LIST_HEAD(&topology_device_list); init_rwsem(&topology_lock); - topology_crat_parsed = 0; memset(&sys_props, 0, sizeof(sys_props)); @@ -1219,7 +895,7 @@ int kfd_topology_remove_device(struct kfd_dev *gpu) up_write(&topology_lock); - if (res == 0) + if (!res) kfd_notify_gpu_change(gpu_id, 0); return res; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index c3ddb9b95ff8..999645809028 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -164,6 +164,7 @@ struct kfd_system_properties { struct attribute attr_props; }; - +struct kfd_topology_device *kfd_create_topology_device(void); +void kfd_release_live_view(void); #endif /* __KFD_TOPOLOGY_H__ */ -- GitLab From 8e05247d4c23ff1c91682cf28d2ddb4210808e7d Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:08:51 -0500 Subject: [PATCH 1187/2547] drm/amdkfd: Reorganize CRAT fetching from ACPI Reorganize and rename kfd_topology_get_crat_acpi function. In this way acpi_get_table(..) needs to be called only once. This will also aid in dGPU topology implementation. Signed-off-by: Harish Kasiviswanathan Signed-off-by: Kent Russell Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 41 +++++++++++++++++++---- drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 40 ++++++++++------------ 3 files changed, 54 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index f2dda6012b77..aa754c1ff682 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -319,17 +319,29 @@ int kfd_parse_crat_table(void *crat_image) return 0; } -int kfd_topology_get_crat_acpi(void *crat_image, size_t *size) +/* + * kfd_create_crat_image_acpi - Allocates memory for CRAT image and + * copies CRAT from ACPI (if available). + * NOTE: Call kfd_destroy_crat_image to free CRAT image memory + * + * @crat_image: CRAT read from ACPI. If no CRAT in ACPI then + * crat_image will be NULL + * @size: [OUT] size of crat_image + * + * Return 0 if successful else return error code + */ +int kfd_create_crat_image_acpi(void **crat_image, size_t *size) { struct acpi_table_header *crat_table; acpi_status status; + void *pcrat_image; - if (!size) + if (!crat_image) return -EINVAL; - /* - * Fetch the CRAT table from ACPI - */ + *crat_image = NULL; + + /* Fetch the CRAT table from ACPI */ status = acpi_get_table(CRAT_SIGNATURE, 0, &crat_table); if (status == AE_NOT_FOUND) { pr_warn("CRAT table not found\n"); @@ -341,10 +353,25 @@ int kfd_topology_get_crat_acpi(void *crat_image, size_t *size) return -EINVAL; } - if (*size >= crat_table->length && crat_image != NULL) - memcpy(crat_image, crat_table, crat_table->length); + pcrat_image = kmalloc(crat_table->length, GFP_KERNEL); + if (!pcrat_image) + return -ENOMEM; + + memcpy(pcrat_image, crat_table, crat_table->length); + *crat_image = pcrat_image; *size = crat_table->length; return 0; } + +/* + * kfd_destroy_crat_image + * + * @crat_image: [IN] - crat_image from kfd_create_crat_image_xxx(..) + * + */ +void kfd_destroy_crat_image(void *crat_image) +{ + kfree(crat_image); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h index 920697b4469b..da83105d127d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h @@ -291,7 +291,8 @@ struct cdit_header { #pragma pack() -int kfd_topology_get_crat_acpi(void *crat_image, size_t *size); +int kfd_create_crat_image_acpi(void **crat_image, size_t *size); +void kfd_destroy_crat_image(void *crat_image); int kfd_parse_crat_table(void *crat_image); #endif /* KFD_CRAT_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index b6cf785d0138..35da4af28c87 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -699,35 +699,31 @@ int kfd_topology_init(void) /* * Get the CRAT image from the ACPI */ - ret = kfd_topology_get_crat_acpi(crat_image, &image_size); - if (ret == 0 && image_size > 0) { - pr_info("Found CRAT image with size=%zd\n", image_size); - crat_image = kmalloc(image_size, GFP_KERNEL); - if (!crat_image) { - ret = -ENOMEM; - pr_err("No memory for allocating CRAT image\n"); + ret = kfd_create_crat_image_acpi(&crat_image, &image_size); + if (!ret) { + ret = kfd_parse_crat_table(crat_image); + if (ret) goto err; - } - ret = kfd_topology_get_crat_acpi(crat_image, &image_size); - - if (ret == 0) { - down_write(&topology_lock); - ret = kfd_parse_crat_table(crat_image); - if (ret == 0) - ret = kfd_topology_update_sysfs(); - up_write(&topology_lock); - } else { - pr_err("Couldn't get CRAT table size from ACPI\n"); - } - kfree(crat_image); } else if (ret == -ENODATA) { + /* TODO: Create fake CRAT table */ ret = 0; + goto err; } else { pr_err("Couldn't get CRAT table size from ACPI\n"); + goto err; } + down_write(&topology_lock); + ret = kfd_topology_update_sysfs(); + up_write(&topology_lock); + + if (!ret) + pr_info("Finished initializing topology\n"); + else + pr_err("Failed to update topology in sysfs ret=%d\n", ret); + err: - pr_info("Finished initializing topology ret=%d\n", ret); + kfd_destroy_crat_image(crat_image); return ret; } @@ -747,7 +743,7 @@ static void kfd_debug_print_topology(void) pr_info("Node: %d\n", i); pr_info("\tGPU assigned: %s\n", (dev->gpu ? "yes" : "no")); pr_info("\tCPU count: %d\n", dev->node_props.cpu_cores_count); - pr_info("\tSIMD count: %d", dev->node_props.simd_count); + pr_info("\tSIMD count: %d\n", dev->node_props.simd_count); i++; } } -- GitLab From 4f449311e9aa177bd224e7b13cb0f6a55c524bcb Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:08:52 -0500 Subject: [PATCH 1188/2547] drm/amdkfd: Decouple CRAT parsing from device list update Currently, CRAT parsing is intertwined with topology_device_list and hence repeated calls to kfd_parse_crat_table() will fail. Decouple kfd_parse_crat_table() and topology_device_list. kfd_parse_crat_table() will parse CRAT and add topology devices to a temporary list temp_topology_device_list and then kfd_topology_update_device_list will move contents from temporary list to master list. Signed-off-by: Harish Kasiviswanathan Signed-off-by: Kent Russell Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 118 +++++++++++++--------- drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 84 ++++++++++----- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 6 +- 4 files changed, 132 insertions(+), 79 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index aa754c1ff682..bae91fdeba6d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -23,8 +23,6 @@ #include "kfd_crat.h" #include "kfd_topology.h" -static int topology_crat_parsed; -extern struct list_head topology_device_list; extern struct kfd_system_properties sys_props; static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, @@ -57,16 +55,18 @@ static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev, pr_info("CU GPU: id_base=%d\n", cu->processor_id_low); } -/* kfd_parse_subtype_cu is called when the topology mutex is already acquired */ -static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu) +/* kfd_parse_subtype_cu - parse compute unit subtypes and attach it to correct + * topology device present in the device_list + */ +static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu, + struct list_head *device_list) { struct kfd_topology_device *dev; - int i = 0; pr_info("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n", cu->proximity_domain, cu->hsa_capability); - list_for_each_entry(dev, &topology_device_list, list) { - if (cu->proximity_domain == i) { + list_for_each_entry(dev, device_list, list) { + if (cu->proximity_domain == dev->proximity_domain) { if (cu->flags & CRAT_CU_FLAGS_CPU_PRESENT) kfd_populated_cu_info_cpu(dev, cu); @@ -74,26 +74,24 @@ static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu) kfd_populated_cu_info_gpu(dev, cu); break; } - i++; } return 0; } -/* - * kfd_parse_subtype_mem is called when the topology mutex is - * already acquired +/* kfd_parse_subtype_mem - parse memory subtypes and attach it to correct + * topology device present in the device_list */ -static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem) +static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem, + struct list_head *device_list) { struct kfd_mem_properties *props; struct kfd_topology_device *dev; - int i = 0; pr_info("Found memory entry in CRAT table with proximity_domain=%d\n", mem->proximity_domain); - list_for_each_entry(dev, &topology_device_list, list) { - if (mem->proximity_domain == i) { + list_for_each_entry(dev, device_list, list) { + if (mem->proximity_domain == dev->proximity_domain) { props = kfd_alloc_struct(props); if (!props) return -ENOMEM; @@ -118,17 +116,16 @@ static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem) break; } - i++; } return 0; } -/* - * kfd_parse_subtype_cache is called when the topology mutex - * is already acquired +/* kfd_parse_subtype_cache - parse cache subtypes and attach it to correct + * topology device present in the device_list */ -static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache) +static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache, + struct list_head *device_list) { struct kfd_cache_properties *props; struct kfd_topology_device *dev; @@ -137,7 +134,7 @@ static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache) id = cache->processor_id_low; pr_info("Found cache entry in CRAT table with processor_id=%d\n", id); - list_for_each_entry(dev, &topology_device_list, list) + list_for_each_entry(dev, device_list, list) if (id == dev->node_props.cpu_core_id_base || id == dev->node_props.simd_id_base) { props = kfd_alloc_struct(props); @@ -171,15 +168,14 @@ static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache) return 0; } -/* - * kfd_parse_subtype_iolink is called when the topology mutex - * is already acquired +/* kfd_parse_subtype_iolink - parse iolink subtypes and attach it to correct + * topology device present in the device_list */ -static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink) +static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink, + struct list_head *device_list) { struct kfd_iolink_properties *props; struct kfd_topology_device *dev; - uint32_t i = 0; uint32_t id_from; uint32_t id_to; @@ -187,8 +183,8 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink) id_to = iolink->proximity_domain_to; pr_info("Found IO link entry in CRAT table with id_from=%d\n", id_from); - list_for_each_entry(dev, &topology_device_list, list) { - if (id_from == i) { + list_for_each_entry(dev, device_list, list) { + if (id_from == dev->proximity_domain) { props = kfd_alloc_struct(props); if (!props) return -ENOMEM; @@ -216,13 +212,18 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink) break; } - i++; } return 0; } -static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr) +/* kfd_parse_subtype - parse subtypes and attach it to correct topology device + * present in the device_list + * @sub_type_hdr - subtype section of crat_image + * @device_list - list of topology devices present in this crat_image + */ +static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr, + struct list_head *device_list) { struct crat_subtype_computeunit *cu; struct crat_subtype_memory *mem; @@ -233,15 +234,15 @@ static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr) switch (sub_type_hdr->type) { case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY: cu = (struct crat_subtype_computeunit *)sub_type_hdr; - ret = kfd_parse_subtype_cu(cu); + ret = kfd_parse_subtype_cu(cu, device_list); break; case CRAT_SUBTYPE_MEMORY_AFFINITY: mem = (struct crat_subtype_memory *)sub_type_hdr; - ret = kfd_parse_subtype_mem(mem); + ret = kfd_parse_subtype_mem(mem, device_list); break; case CRAT_SUBTYPE_CACHE_AFFINITY: cache = (struct crat_subtype_cache *)sub_type_hdr; - ret = kfd_parse_subtype_cache(cache); + ret = kfd_parse_subtype_cache(cache, device_list); break; case CRAT_SUBTYPE_TLB_AFFINITY: /* @@ -257,7 +258,7 @@ static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr) break; case CRAT_SUBTYPE_IOLINK_AFFINITY: iolink = (struct crat_subtype_iolink *)sub_type_hdr; - ret = kfd_parse_subtype_iolink(iolink); + ret = kfd_parse_subtype_iolink(iolink, device_list); break; default: pr_warn("Unknown subtype %d in CRAT\n", @@ -267,12 +268,23 @@ static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr) return ret; } -int kfd_parse_crat_table(void *crat_image) +/* kfd_parse_crat_table - parse CRAT table. For each node present in CRAT + * create a kfd_topology_device and add in to device_list. Also parse + * CRAT subtypes and attach it to appropriate kfd_topology_device + * @crat_image - input image containing CRAT + * @device_list - [OUT] list of kfd_topology_device generated after + * parsing crat_image + * @proximity_domain - Proximity domain of the first device in the table + * + * Return - 0 if successful else -ve value + */ +int kfd_parse_crat_table(void *crat_image, struct list_head *device_list, + uint32_t proximity_domain) { struct kfd_topology_device *top_dev; struct crat_subtype_generic *sub_type_hdr; uint16_t node_id; - int ret; + int ret = 0; struct crat_header *crat_table = (struct crat_header *)crat_image; uint16_t num_nodes; uint32_t image_len; @@ -280,17 +292,26 @@ int kfd_parse_crat_table(void *crat_image) if (!crat_image) return -EINVAL; + if (!list_empty(device_list)) { + pr_warn("Error device list should be empty\n"); + return -EINVAL; + } + num_nodes = crat_table->num_domains; image_len = crat_table->length; pr_info("Parsing CRAT table with %d nodes\n", num_nodes); for (node_id = 0; node_id < num_nodes; node_id++) { - top_dev = kfd_create_topology_device(); - if (!top_dev) { - kfd_release_live_view(); - return -ENOMEM; - } + top_dev = kfd_create_topology_device(device_list); + if (!top_dev) + break; + top_dev->proximity_domain = proximity_domain++; + } + + if (!top_dev) { + ret = -ENOMEM; + goto err; } sys_props.platform_id = @@ -302,21 +323,20 @@ int kfd_parse_crat_table(void *crat_image) while ((char *)sub_type_hdr + sizeof(struct crat_subtype_generic) < ((char *)crat_image) + image_len) { if (sub_type_hdr->flags & CRAT_SUBTYPE_FLAGS_ENABLED) { - ret = kfd_parse_subtype(sub_type_hdr); - if (ret != 0) { - kfd_release_live_view(); - return ret; - } + ret = kfd_parse_subtype(sub_type_hdr, device_list); + if (ret) + break; } sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + sub_type_hdr->length); } - sys_props.generation_count++; - topology_crat_parsed = 1; +err: + if (ret) + kfd_release_topology_device_list(device_list); - return 0; + return ret; } /* diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h index da83105d127d..4e683ae2212b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h @@ -293,6 +293,7 @@ struct cdit_header { int kfd_create_crat_image_acpi(void **crat_image, size_t *size); void kfd_destroy_crat_image(void *crat_image); -int kfd_parse_crat_table(void *crat_image); +int kfd_parse_crat_table(void *crat_image, struct list_head *device_list, + uint32_t proximity_domain); #endif /* KFD_CRAT_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 35da4af28c87..f64350b90812 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -34,7 +34,8 @@ #include "kfd_topology.h" #include "kfd_device_queue_manager.h" -struct list_head topology_device_list; +/* topology_device_list - Master list of all topology devices */ +static struct list_head topology_device_list; struct kfd_system_properties sys_props; static DECLARE_RWSEM(topology_lock); @@ -105,24 +106,27 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) } kfree(dev); - - sys_props.num_devices--; } -void kfd_release_live_view(void) +void kfd_release_topology_device_list(struct list_head *device_list) { struct kfd_topology_device *dev; - while (topology_device_list.next != &topology_device_list) { - dev = container_of(topology_device_list.next, - struct kfd_topology_device, list); + while (!list_empty(device_list)) { + dev = list_first_entry(device_list, + struct kfd_topology_device, list); kfd_release_topology_device(dev); + } } +static void kfd_release_live_view(void) +{ + kfd_release_topology_device_list(&topology_device_list); memset(&sys_props, 0, sizeof(sys_props)); } -struct kfd_topology_device *kfd_create_topology_device(void) +struct kfd_topology_device *kfd_create_topology_device( + struct list_head *device_list) { struct kfd_topology_device *dev; @@ -136,8 +140,7 @@ struct kfd_topology_device *kfd_create_topology_device(void) INIT_LIST_HEAD(&dev->cache_props); INIT_LIST_HEAD(&dev->io_link_props); - list_add_tail(&dev->list, &topology_device_list); - sys_props.num_devices++; + list_add_tail(&dev->list, device_list); return dev; } @@ -682,16 +685,32 @@ static void kfd_topology_release_sysfs(void) } } +/* Called with write topology_lock acquired */ +static void kfd_topology_update_device_list(struct list_head *temp_list, + struct list_head *master_list) +{ + while (!list_empty(temp_list)) { + list_move_tail(temp_list->next, master_list); + sys_props.num_devices++; + } +} + int kfd_topology_init(void) { void *crat_image = NULL; size_t image_size = 0; int ret; + struct list_head temp_topology_device_list; - /* - * Initialize the head for the topology device list + /* topology_device_list - Master list of all topology devices + * temp_topology_device_list - temporary list created while parsing CRAT + * or VCRAT. Once parsing is complete the contents of list is moved to + * topology_device_list */ + + /* Initialize the head for the both the lists */ INIT_LIST_HEAD(&topology_device_list); + INIT_LIST_HEAD(&temp_topology_device_list); init_rwsem(&topology_lock); memset(&sys_props, 0, sizeof(sys_props)); @@ -701,7 +720,8 @@ int kfd_topology_init(void) */ ret = kfd_create_crat_image_acpi(&crat_image, &image_size); if (!ret) { - ret = kfd_parse_crat_table(crat_image); + ret = kfd_parse_crat_table(crat_image, + &temp_topology_device_list, 0); if (ret) goto err; } else if (ret == -ENODATA) { @@ -714,12 +734,15 @@ int kfd_topology_init(void) } down_write(&topology_lock); + kfd_topology_update_device_list(&temp_topology_device_list, + &topology_device_list); ret = kfd_topology_update_sysfs(); up_write(&topology_lock); - if (!ret) + if (!ret) { + sys_props.generation_count++; pr_info("Finished initializing topology\n"); - else + } else pr_err("Failed to update topology in sysfs ret=%d\n", ret); err: @@ -729,8 +752,10 @@ int kfd_topology_init(void) void kfd_topology_shutdown(void) { + down_write(&topology_lock); kfd_topology_release_sysfs(); kfd_release_live_view(); + up_write(&topology_lock); } static void kfd_debug_print_topology(void) @@ -806,13 +831,15 @@ int kfd_topology_add_device(struct kfd_dev *gpu) uint32_t gpu_id; struct kfd_topology_device *dev; struct kfd_cu_info cu_info; - int res; + int res = 0; + struct list_head temp_topology_device_list; + + INIT_LIST_HEAD(&temp_topology_device_list); gpu_id = kfd_generate_gpu_id(gpu); pr_debug("Adding new GPU (ID: 0x%x) to topology\n", gpu_id); - down_write(&topology_lock); /* * Try to assign the GPU to existing topology device (generated from * CRAT table @@ -821,11 +848,12 @@ int kfd_topology_add_device(struct kfd_dev *gpu) if (!dev) { pr_info("GPU was not found in the current topology. Extending.\n"); kfd_debug_print_topology(); - dev = kfd_create_topology_device(); + dev = kfd_create_topology_device(&temp_topology_device_list); if (!dev) { res = -ENOMEM; goto err; } + dev->gpu = gpu; /* @@ -833,12 +861,18 @@ int kfd_topology_add_device(struct kfd_dev *gpu) * GPU vBIOS */ + down_write(&topology_lock); + kfd_topology_update_device_list(&temp_topology_device_list, + &topology_device_list); + /* Update the SYSFS tree, since we added another topology * device */ if (kfd_topology_update_sysfs() < 0) kfd_topology_release_sysfs(); + up_write(&topology_lock); + } dev->gpu_id = gpu_id; @@ -859,30 +893,26 @@ int kfd_topology_add_device(struct kfd_dev *gpu) pr_info("Adding doorbell packet type capability\n"); } - res = 0; - -err: - up_write(&topology_lock); - - if (res == 0) + if (!res) kfd_notify_gpu_change(gpu_id, 1); - +err: return res; } int kfd_topology_remove_device(struct kfd_dev *gpu) { - struct kfd_topology_device *dev; + struct kfd_topology_device *dev, *tmp; uint32_t gpu_id; int res = -ENODEV; down_write(&topology_lock); - list_for_each_entry(dev, &topology_device_list, list) + list_for_each_entry_safe(dev, tmp, &topology_device_list, list) if (dev->gpu == gpu) { gpu_id = dev->gpu_id; kfd_remove_sysfs_node_entry(dev); kfd_release_topology_device(dev); + sys_props.num_devices--; res = 0; if (kfd_topology_update_sysfs() < 0) kfd_topology_release_sysfs(); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 999645809028..0d98b61b3312 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -135,6 +135,7 @@ struct kfd_iolink_properties { struct kfd_topology_device { struct list_head list; uint32_t gpu_id; + uint32_t proximity_domain; struct kfd_node_properties node_props; uint32_t mem_bank_count; struct list_head mem_props; @@ -164,7 +165,8 @@ struct kfd_system_properties { struct attribute attr_props; }; -struct kfd_topology_device *kfd_create_topology_device(void); -void kfd_release_live_view(void); +struct kfd_topology_device *kfd_create_topology_device( + struct list_head *device_list); +void kfd_release_topology_device_list(struct list_head *device_list); #endif /* __KFD_TOPOLOGY_H__ */ -- GitLab From 6d82eb0ef209dcf637e2b7fb9a69672d3a455a3f Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:08:53 -0500 Subject: [PATCH 1189/2547] drm/amdkfd: Support enumerating non-GPU devices Modify kfd_topology_enum_kfd_devices(..) function to support non-GPU nodes. The function returned NULL when it encountered non-GPU (say CPU) nodes. This caused kfd_ioctl_create_event and kfd_init_apertures to fail for Intel + Tonga. kfd_topology_enum_kfd_devices will now parse all the nodes and return valid kfd_dev for nodes with GPU. Signed-off-by: Harish Kasiviswanathan Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 7 ++++++- drivers/gpu/drm/amd/amdkfd/kfd_pasid.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 18 +++++++++++------- 4 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c index c59384bbbc5f..7377513050e6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c @@ -300,9 +300,14 @@ int kfd_init_apertures(struct kfd_process *process) struct kfd_process_device *pdd; /*Iterating over all devices*/ - while ((dev = kfd_topology_enum_kfd_devices(id)) != NULL && + while (kfd_topology_enum_kfd_devices(id, &dev) == 0 && id < NUM_OF_SUPPORTED_GPUS) { + if (!dev) { + id++; /* Skip non GPU devices */ + continue; + } + pdd = kfd_create_process_device_data(dev, process); if (!pdd) { pr_err("Failed to create process device data\n"); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c index d6a796144269..15fff4420e53 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c @@ -59,7 +59,7 @@ unsigned int kfd_pasid_alloc(void) struct kfd_dev *dev = NULL; unsigned int i = 0; - while ((dev = kfd_topology_enum_kfd_devices(i)) != NULL) { + while ((kfd_topology_enum_kfd_devices(i, &dev)) == 0) { if (dev && dev->kfd2kgd) { kfd2kgd = dev->kfd2kgd; break; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 0c96a6b3a173..69a6206b67ba 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -670,7 +670,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu); int kfd_topology_remove_device(struct kfd_dev *gpu); struct kfd_dev *kfd_device_by_id(uint32_t gpu_id); struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev); -struct kfd_dev *kfd_topology_enum_kfd_devices(uint8_t idx); +int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_dev **kdev); /* Interrupts */ int kfd_interrupt_init(struct kfd_dev *dev); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index f64350b90812..b2d2b7e10124 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -927,22 +927,26 @@ int kfd_topology_remove_device(struct kfd_dev *gpu) return res; } -/* - * When idx is out of bounds, the function will return NULL +/* kfd_topology_enum_kfd_devices - Enumerate through all devices in KFD + * topology. If GPU device is found @idx, then valid kfd_dev pointer is + * returned through @kdev + * Return - 0: On success (@kdev will be NULL for non GPU nodes) + * -1: If end of list */ -struct kfd_dev *kfd_topology_enum_kfd_devices(uint8_t idx) +int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_dev **kdev) { struct kfd_topology_device *top_dev; - struct kfd_dev *device = NULL; uint8_t device_idx = 0; + *kdev = NULL; down_read(&topology_lock); list_for_each_entry(top_dev, &topology_device_list, list) { if (device_idx == idx) { - device = top_dev->gpu; - break; + *kdev = top_dev->gpu; + up_read(&topology_lock); + return 0; } device_idx++; @@ -950,7 +954,7 @@ struct kfd_dev *kfd_topology_enum_kfd_devices(uint8_t idx) up_read(&topology_lock); - return device; + return -1; } -- GitLab From 4f2937bfff1057700c402438b83d66179283675e Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:08:54 -0500 Subject: [PATCH 1190/2547] drm/amdkfd: sync IOLINK defines to thunk spec Current thunk spec v1.07 dated Feb 1, 2016 v2: fix indentation Signed-off-by: Harish Kasiviswanathan Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h index 4e683ae2212b..c15adbd1461e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h @@ -222,9 +222,12 @@ struct crat_subtype_ccompute { /* * HSA IO Link Affinity structure and definitions */ -#define CRAT_IOLINK_FLAGS_ENABLED 0x00000001 -#define CRAT_IOLINK_FLAGS_COHERENCY 0x00000002 -#define CRAT_IOLINK_FLAGS_RESERVED 0xfffffffc +#define CRAT_IOLINK_FLAGS_ENABLED (1 << 0) +#define CRAT_IOLINK_FLAGS_NON_COHERENT (1 << 1) +#define CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT (1 << 2) +#define CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT (1 << 3) +#define CRAT_IOLINK_FLAGS_NO_PEER_TO_PEER_DMA (1 << 4) +#define CRAT_IOLINK_FLAGS_RESERVED_MASK 0xffffffe0 /* * IO interface types @@ -232,10 +235,18 @@ struct crat_subtype_ccompute { #define CRAT_IOLINK_TYPE_UNDEFINED 0 #define CRAT_IOLINK_TYPE_HYPERTRANSPORT 1 #define CRAT_IOLINK_TYPE_PCIEXPRESS 2 -#define CRAT_IOLINK_TYPE_OTHER 3 +#define CRAT_IOLINK_TYPE_AMBA 3 +#define CRAT_IOLINK_TYPE_MIPI 4 +#define CRAT_IOLINK_TYPE_QPI_1_1 5 +#define CRAT_IOLINK_TYPE_RESERVED1 6 +#define CRAT_IOLINK_TYPE_RESERVED2 7 +#define CRAT_IOLINK_TYPE_RAPID_IO 8 +#define CRAT_IOLINK_TYPE_INFINIBAND 9 +#define CRAT_IOLINK_TYPE_RESERVED3 10 +#define CRAT_IOLINK_TYPE_OTHER 11 #define CRAT_IOLINK_TYPE_MAX 255 -#define CRAT_IOLINK_RESERVED_LENGTH 24 +#define CRAT_IOLINK_RESERVED_LENGTH 24 struct crat_subtype_iolink { uint8_t type; -- GitLab From 42aa8793d795f18d20be3d5505b39aeffa44a954 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 8 Dec 2017 23:08:55 -0500 Subject: [PATCH 1191/2547] drm/amdkfd: Turn verbose topology messages into pr_debug Signed-off-by: Harish Kasiviswanathan Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 17 +++++++++-------- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index bae91fdeba6d..31717971d8dd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -33,7 +33,7 @@ static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT) dev->node_props.capability |= HSA_CAP_ATS_PRESENT; - pr_info("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores, + pr_debug("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores, cu->processor_id_low); } @@ -52,7 +52,7 @@ static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev, dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu; if (cu->hsa_capability & CRAT_CU_FLAGS_HOT_PLUGGABLE) dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE; - pr_info("CU GPU: id_base=%d\n", cu->processor_id_low); + pr_debug("CU GPU: id_base=%d\n", cu->processor_id_low); } /* kfd_parse_subtype_cu - parse compute unit subtypes and attach it to correct @@ -63,7 +63,7 @@ static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu, { struct kfd_topology_device *dev; - pr_info("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n", + pr_debug("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n", cu->proximity_domain, cu->hsa_capability); list_for_each_entry(dev, device_list, list) { if (cu->proximity_domain == dev->proximity_domain) { @@ -88,7 +88,7 @@ static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem, struct kfd_mem_properties *props; struct kfd_topology_device *dev; - pr_info("Found memory entry in CRAT table with proximity_domain=%d\n", + pr_debug("Found memory entry in CRAT table with proximity_domain=%d\n", mem->proximity_domain); list_for_each_entry(dev, device_list, list) { if (mem->proximity_domain == dev->proximity_domain) { @@ -133,7 +133,7 @@ static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache, id = cache->processor_id_low; - pr_info("Found cache entry in CRAT table with processor_id=%d\n", id); + pr_debug("Found cache entry in CRAT table with processor_id=%d\n", id); list_for_each_entry(dev, device_list, list) if (id == dev->node_props.cpu_core_id_base || id == dev->node_props.simd_id_base) { @@ -182,7 +182,8 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink, id_from = iolink->proximity_domain_from; id_to = iolink->proximity_domain_to; - pr_info("Found IO link entry in CRAT table with id_from=%d\n", id_from); + pr_debug("Found IO link entry in CRAT table with id_from=%d\n", + id_from); list_for_each_entry(dev, device_list, list) { if (id_from == dev->proximity_domain) { props = kfd_alloc_struct(props); @@ -248,13 +249,13 @@ static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr, /* * For now, nothing to do here */ - pr_info("Found TLB entry in CRAT table (not processing)\n"); + pr_debug("Found TLB entry in CRAT table (not processing)\n"); break; case CRAT_SUBTYPE_CCOMPUTE_AFFINITY: /* * For now, nothing to do here */ - pr_info("Found CCOMPUTE entry in CRAT table (not processing)\n"); + pr_debug("Found CCOMPUTE entry in CRAT table (not processing)\n"); break; case CRAT_SUBTYPE_IOLINK_AFFINITY: iolink = (struct crat_subtype_iolink *)sub_type_hdr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index b2d2b7e10124..001e47336ab5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -890,7 +890,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu) if (dev->gpu->device_info->asic_family == CHIP_CARRIZO) { dev->node_props.capability |= HSA_CAP_DOORBELL_PACKET_TYPE; - pr_info("Adding doorbell packet type capability\n"); + pr_debug("Adding doorbell packet type capability\n"); } if (!res) -- GitLab From 175b926335c9ce30a531b7a162dde055e7182cbe Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 8 Dec 2017 23:08:56 -0500 Subject: [PATCH 1192/2547] drm/amdkfd: Simplify counting of memory banks Only count memory banks in one place. Ignore redundant num_banks entry in crat_subtype_computeunit. Signed-off-by: Felix Kuehling Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 3 +-- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 14 ++------------ drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 1 - 3 files changed, 3 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index 31717971d8dd..e62493b39041 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -45,7 +45,6 @@ static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev, dev->node_props.lds_size_in_kb = cu->lds_size_in_kb; dev->node_props.max_waves_per_simd = cu->max_waves_simd; dev->node_props.wave_front_size = cu->wave_front_size; - dev->node_props.mem_banks_count = cu->num_banks; dev->node_props.array_count = cu->num_arrays; dev->node_props.cu_per_simd_array = cu->num_cu_per_array; dev->node_props.simd_per_cu = cu->num_simd_per_cu; @@ -111,7 +110,7 @@ static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem, mem->length_low; props->width = mem->width; - dev->mem_bank_count++; + dev->node_props.mem_banks_count++; list_add_tail(&props->list, &dev->mem_props); break; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 001e47336ab5..17e8daf96b4f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -335,18 +335,8 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr, dev->node_props.cpu_cores_count); sysfs_show_32bit_prop(buffer, "simd_count", dev->node_props.simd_count); - - if (dev->mem_bank_count < dev->node_props.mem_banks_count) { - pr_info_once("mem_banks_count truncated from %d to %d\n", - dev->node_props.mem_banks_count, - dev->mem_bank_count); - sysfs_show_32bit_prop(buffer, "mem_banks_count", - dev->mem_bank_count); - } else { - sysfs_show_32bit_prop(buffer, "mem_banks_count", - dev->node_props.mem_banks_count); - } - + sysfs_show_32bit_prop(buffer, "mem_banks_count", + dev->node_props.mem_banks_count); sysfs_show_32bit_prop(buffer, "caches_count", dev->node_props.caches_count); sysfs_show_32bit_prop(buffer, "io_links_count", diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 0d98b61b3312..17b2d4383bf9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -137,7 +137,6 @@ struct kfd_topology_device { uint32_t gpu_id; uint32_t proximity_domain; struct kfd_node_properties node_props; - uint32_t mem_bank_count; struct list_head mem_props; uint32_t cache_count; struct list_head cache_props; -- GitLab From bc0c75a36722be4537a9266940ddcd4f826234c4 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:08:57 -0500 Subject: [PATCH 1193/2547] drm/amdkfd: Fix sibling_map[] size Change kfd_cache_properties.sibling_map[256] to kfd_cache_properties.sibling_map[32]. Since, CRAT uses bitmap for sibling_map, it is more efficient to use bitmap in the kfd structure also. Signed-off-by: Harish Kasiviswanathan Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 20 +++++++++++++------- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 4 +--- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 17e8daf96b4f..622fedaa5b39 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -263,7 +263,7 @@ static ssize_t kfd_cache_show(struct kobject *kobj, struct attribute *attr, char *buffer) { ssize_t ret; - uint32_t i; + uint32_t i, j; struct kfd_cache_properties *cache; /* Making sure that the buffer is an empty string */ @@ -281,12 +281,18 @@ static ssize_t kfd_cache_show(struct kobject *kobj, struct attribute *attr, sysfs_show_32bit_prop(buffer, "latency", cache->cache_latency); sysfs_show_32bit_prop(buffer, "type", cache->cache_type); snprintf(buffer, PAGE_SIZE, "%ssibling_map ", buffer); - for (i = 0; i < KFD_TOPOLOGY_CPU_SIBLINGS; i++) - ret = snprintf(buffer, PAGE_SIZE, "%s%d%s", - buffer, cache->sibling_map[i], - (i == KFD_TOPOLOGY_CPU_SIBLINGS-1) ? - "\n" : ","); - + for (i = 0; i < CRAT_SIBLINGMAP_SIZE; i++) + for (j = 0; j < sizeof(cache->sibling_map[0])*8; j++) { + /* Check each bit */ + if (cache->sibling_map[i] & (1 << j)) + ret = snprintf(buffer, PAGE_SIZE, + "%s%d%s", buffer, 1, ","); + else + ret = snprintf(buffer, PAGE_SIZE, + "%s%d%s", buffer, 0, ","); + } + /* Replace the last "," with end of line */ + *(buffer + strlen(buffer) - 1) = 0xA; return ret; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 17b2d4383bf9..50a741ba51e0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -91,8 +91,6 @@ struct kfd_mem_properties { struct attribute attr; }; -#define KFD_TOPOLOGY_CPU_SIBLINGS 256 - #define HSA_CACHE_TYPE_DATA 0x00000001 #define HSA_CACHE_TYPE_INSTRUCTION 0x00000002 #define HSA_CACHE_TYPE_CPU 0x00000004 @@ -109,7 +107,7 @@ struct kfd_cache_properties { uint32_t cache_assoc; uint32_t cache_latency; uint32_t cache_type; - uint8_t sibling_map[KFD_TOPOLOGY_CPU_SIBLINGS]; + uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE]; struct kobject *kobj; struct attribute attr; }; -- GitLab From 520b8fb755ccfb07d8d743da5753cff1fcb74b9f Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 8 Dec 2017 23:08:58 -0500 Subject: [PATCH 1194/2547] drm/amdkfd: Add topology support for CPUs Currently, the KFD topology information is generated by parsing the CRAT (ACPI) table. However, at present CRAT table is available only for AMD APUs. To support CPUs on systems without a CRAT table, the KFD driver will create a Virtual CRAT (VCRAT) table and then the existing code will parse that table to generate topology. Signed-off-by: Harish Kasiviswanathan Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 321 +++++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 9 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 190 +++++++++++-- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 3 + 5 files changed, 489 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index e62493b39041..c8afbf8015f9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -21,10 +21,9 @@ */ #include #include "kfd_crat.h" +#include "kfd_priv.h" #include "kfd_topology.h" -extern struct kfd_system_properties sys_props; - static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, struct crat_subtype_computeunit *cu) { @@ -281,7 +280,7 @@ static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr, int kfd_parse_crat_table(void *crat_image, struct list_head *device_list, uint32_t proximity_domain) { - struct kfd_topology_device *top_dev; + struct kfd_topology_device *top_dev = NULL; struct crat_subtype_generic *sub_type_hdr; uint16_t node_id; int ret = 0; @@ -314,10 +313,10 @@ int kfd_parse_crat_table(void *crat_image, struct list_head *device_list, goto err; } - sys_props.platform_id = - (*((uint64_t *)crat_table->oem_id)) & CRAT_OEMID_64BIT_MASK; - sys_props.platform_oem = *((uint64_t *)crat_table->oem_table_id); - sys_props.platform_rev = crat_table->revision; + memcpy(top_dev->oem_id, crat_table->oem_id, CRAT_OEMID_LENGTH); + memcpy(top_dev->oem_table_id, crat_table->oem_table_id, + CRAT_OEMTABLEID_LENGTH); + top_dev->oem_revision = crat_table->oem_revision; sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1); while ((char *)sub_type_hdr + sizeof(struct crat_subtype_generic) < @@ -385,8 +384,312 @@ int kfd_create_crat_image_acpi(void **crat_image, size_t *size) return 0; } -/* - * kfd_destroy_crat_image +/* Memory required to create Virtual CRAT. + * Since there is no easy way to predict the amount of memory required, the + * following amount are allocated for CPU and GPU Virtual CRAT. This is + * expected to cover all known conditions. But to be safe additional check + * is put in the code to ensure we don't overwrite. + */ +#define VCRAT_SIZE_FOR_CPU (2 * PAGE_SIZE) +#define VCRAT_SIZE_FOR_GPU (3 * PAGE_SIZE) + +/* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node + * + * @numa_node_id: CPU NUMA node id + * @avail_size: Available size in the memory + * @sub_type_hdr: Memory into which compute info will be filled in + * + * Return 0 if successful else return -ve value + */ +static int kfd_fill_cu_for_cpu(int numa_node_id, int *avail_size, + int proximity_domain, + struct crat_subtype_computeunit *sub_type_hdr) +{ + const struct cpumask *cpumask; + + *avail_size -= sizeof(struct crat_subtype_computeunit); + if (*avail_size < 0) + return -ENOMEM; + + memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit)); + + /* Fill in subtype header data */ + sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY; + sub_type_hdr->length = sizeof(struct crat_subtype_computeunit); + sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED; + + cpumask = cpumask_of_node(numa_node_id); + + /* Fill in CU data */ + sub_type_hdr->flags |= CRAT_CU_FLAGS_CPU_PRESENT; + sub_type_hdr->proximity_domain = proximity_domain; + sub_type_hdr->processor_id_low = kfd_numa_node_to_apic_id(numa_node_id); + if (sub_type_hdr->processor_id_low == -1) + return -EINVAL; + + sub_type_hdr->num_cpu_cores = cpumask_weight(cpumask); + + return 0; +} + +/* kfd_fill_mem_info_for_cpu - Fill in Memory info for the given CPU NUMA node + * + * @numa_node_id: CPU NUMA node id + * @avail_size: Available size in the memory + * @sub_type_hdr: Memory into which compute info will be filled in + * + * Return 0 if successful else return -ve value + */ +static int kfd_fill_mem_info_for_cpu(int numa_node_id, int *avail_size, + int proximity_domain, + struct crat_subtype_memory *sub_type_hdr) +{ + uint64_t mem_in_bytes = 0; + pg_data_t *pgdat; + int zone_type; + + *avail_size -= sizeof(struct crat_subtype_memory); + if (*avail_size < 0) + return -ENOMEM; + + memset(sub_type_hdr, 0, sizeof(struct crat_subtype_memory)); + + /* Fill in subtype header data */ + sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY; + sub_type_hdr->length = sizeof(struct crat_subtype_memory); + sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED; + + /* Fill in Memory Subunit data */ + + /* Unlike si_meminfo, si_meminfo_node is not exported. So + * the following lines are duplicated from si_meminfo_node + * function + */ + pgdat = NODE_DATA(numa_node_id); + for (zone_type = 0; zone_type < MAX_NR_ZONES; zone_type++) + mem_in_bytes += pgdat->node_zones[zone_type].managed_pages; + mem_in_bytes <<= PAGE_SHIFT; + + sub_type_hdr->length_low = lower_32_bits(mem_in_bytes); + sub_type_hdr->length_high = upper_32_bits(mem_in_bytes); + sub_type_hdr->proximity_domain = proximity_domain; + + return 0; +} + +static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size, + uint32_t *num_entries, + struct crat_subtype_iolink *sub_type_hdr) +{ + int nid; + struct cpuinfo_x86 *c = &cpu_data(0); + uint8_t link_type; + + if (c->x86_vendor == X86_VENDOR_AMD) + link_type = CRAT_IOLINK_TYPE_HYPERTRANSPORT; + else + link_type = CRAT_IOLINK_TYPE_QPI_1_1; + + *num_entries = 0; + + /* Create IO links from this node to other CPU nodes */ + for_each_online_node(nid) { + if (nid == numa_node_id) /* node itself */ + continue; + + *avail_size -= sizeof(struct crat_subtype_iolink); + if (*avail_size < 0) + return -ENOMEM; + + memset(sub_type_hdr, 0, sizeof(struct crat_subtype_iolink)); + + /* Fill in subtype header data */ + sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY; + sub_type_hdr->length = sizeof(struct crat_subtype_iolink); + sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED; + + /* Fill in IO link data */ + sub_type_hdr->proximity_domain_from = numa_node_id; + sub_type_hdr->proximity_domain_to = nid; + sub_type_hdr->io_interface_type = link_type; + + (*num_entries)++; + sub_type_hdr++; + } + + return 0; +} + +/* kfd_create_vcrat_image_cpu - Create Virtual CRAT for CPU + * + * @pcrat_image: Fill in VCRAT for CPU + * @size: [IN] allocated size of crat_image. + * [OUT] actual size of data filled in crat_image + */ +static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) +{ + struct crat_header *crat_table = (struct crat_header *)pcrat_image; + struct acpi_table_header *acpi_table; + acpi_status status; + struct crat_subtype_generic *sub_type_hdr; + int avail_size = *size; + int numa_node_id; + uint32_t entries = 0; + int ret = 0; + + if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_CPU) + return -EINVAL; + + /* Fill in CRAT Header. + * Modify length and total_entries as subunits are added. + */ + avail_size -= sizeof(struct crat_header); + if (avail_size < 0) + return -ENOMEM; + + memset(crat_table, 0, sizeof(struct crat_header)); + memcpy(&crat_table->signature, CRAT_SIGNATURE, + sizeof(crat_table->signature)); + crat_table->length = sizeof(struct crat_header); + + status = acpi_get_table("DSDT", 0, &acpi_table); + if (status == AE_NOT_FOUND) + pr_warn("DSDT table not found for OEM information\n"); + else { + crat_table->oem_revision = acpi_table->revision; + memcpy(crat_table->oem_id, acpi_table->oem_id, + CRAT_OEMID_LENGTH); + memcpy(crat_table->oem_table_id, acpi_table->oem_table_id, + CRAT_OEMTABLEID_LENGTH); + } + crat_table->total_entries = 0; + crat_table->num_domains = 0; + + sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1); + + for_each_online_node(numa_node_id) { + if (kfd_numa_node_to_apic_id(numa_node_id) == -1) + continue; + + /* Fill in Subtype: Compute Unit */ + ret = kfd_fill_cu_for_cpu(numa_node_id, &avail_size, + crat_table->num_domains, + (struct crat_subtype_computeunit *)sub_type_hdr); + if (ret < 0) + return ret; + crat_table->length += sub_type_hdr->length; + crat_table->total_entries++; + + sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + + sub_type_hdr->length); + + /* Fill in Subtype: Memory */ + ret = kfd_fill_mem_info_for_cpu(numa_node_id, &avail_size, + crat_table->num_domains, + (struct crat_subtype_memory *)sub_type_hdr); + if (ret < 0) + return ret; + crat_table->length += sub_type_hdr->length; + crat_table->total_entries++; + + sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + + sub_type_hdr->length); + + /* Fill in Subtype: IO Link */ + ret = kfd_fill_iolink_info_for_cpu(numa_node_id, &avail_size, + &entries, + (struct crat_subtype_iolink *)sub_type_hdr); + if (ret < 0) + return ret; + crat_table->length += (sub_type_hdr->length * entries); + crat_table->total_entries += entries; + + sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + + sub_type_hdr->length * entries); + + crat_table->num_domains++; + } + + /* TODO: Add cache Subtype for CPU. + * Currently, CPU cache information is available in function + * detect_cache_attributes(cpu) defined in the file + * ./arch/x86/kernel/cpu/intel_cacheinfo.c. This function is not + * exported and to get the same information the code needs to be + * duplicated. + */ + + *size = crat_table->length; + pr_info("Virtual CRAT table created for CPU\n"); + + return 0; +} + +/* kfd_create_crat_image_virtual - Allocates memory for CRAT image and + * creates a Virtual CRAT (VCRAT) image + * + * NOTE: Call kfd_destroy_crat_image to free CRAT image memory + * + * @crat_image: VCRAT image created because ACPI does not have a + * CRAT for this device + * @size: [OUT] size of virtual crat_image + * @flags: COMPUTE_UNIT_CPU - Create VCRAT for CPU device + * COMPUTE_UNIT_GPU - Create VCRAT for GPU + * (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU) - Create VCRAT for APU + * -- this option is not currently implemented. + * The assumption is that all AMD APUs will have CRAT + * @kdev: Valid kfd_device required if flags contain COMPUTE_UNIT_GPU + * + * Return 0 if successful else return -ve value + */ +int kfd_create_crat_image_virtual(void **crat_image, size_t *size, + int flags, struct kfd_dev *kdev, + uint32_t proximity_domain) +{ + void *pcrat_image = NULL; + int ret = 0; + + if (!crat_image) + return -EINVAL; + + *crat_image = NULL; + + /* Allocate one VCRAT_SIZE_FOR_CPU for CPU virtual CRAT image and + * VCRAT_SIZE_FOR_GPU for GPU virtual CRAT image. This should cover + * all the current conditions. A check is put not to overwrite beyond + * allocated size + */ + switch (flags) { + case COMPUTE_UNIT_CPU: + pcrat_image = kmalloc(VCRAT_SIZE_FOR_CPU, GFP_KERNEL); + if (!pcrat_image) + return -ENOMEM; + *size = VCRAT_SIZE_FOR_CPU; + ret = kfd_create_vcrat_image_cpu(pcrat_image, size); + break; + case COMPUTE_UNIT_GPU: + /* TODO: */ + ret = -EINVAL; + pr_err("VCRAT not implemented for dGPU\n"); + break; + case (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU): + /* TODO: */ + ret = -EINVAL; + pr_err("VCRAT not implemented for APU\n"); + break; + default: + ret = -EINVAL; + } + + if (!ret) + *crat_image = pcrat_image; + else + kfree(pcrat_image); + + return ret; +} + + +/* kfd_destroy_crat_image * * @crat_image: [IN] - crat_image from kfd_create_crat_image_xxx(..) * diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h index c15adbd1461e..1711ab664ec6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h @@ -44,6 +44,10 @@ #define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1) +/* Compute Unit flags */ +#define COMPUTE_UNIT_CPU (1 << 0) /* Create Virtual CRAT for CPU */ +#define COMPUTE_UNIT_GPU (1 << 1) /* Create Virtual CRAT for GPU */ + struct crat_header { uint32_t signature; uint32_t length; @@ -302,9 +306,14 @@ struct cdit_header { #pragma pack() +struct kfd_dev; + int kfd_create_crat_image_acpi(void **crat_image, size_t *size); void kfd_destroy_crat_image(void *crat_image); int kfd_parse_crat_table(void *crat_image, struct list_head *device_list, uint32_t proximity_domain); +int kfd_create_crat_image_virtual(void **crat_image, size_t *size, + int flags, struct kfd_dev *kdev, + uint32_t proximity_domain); #endif /* KFD_CRAT_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 69a6206b67ba..aeee9d42171b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -671,6 +671,7 @@ int kfd_topology_remove_device(struct kfd_dev *gpu); struct kfd_dev *kfd_device_by_id(uint32_t gpu_id); struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev); int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_dev **kdev); +int kfd_numa_node_to_apic_id(int numa_node_id); /* Interrupts */ int kfd_interrupt_init(struct kfd_dev *dev); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 622fedaa5b39..9aa600477fff 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include #include "kfd_priv.h" #include "kfd_crat.h" @@ -36,9 +38,10 @@ /* topology_device_list - Master list of all topology devices */ static struct list_head topology_device_list; -struct kfd_system_properties sys_props; +static struct kfd_system_properties sys_props; static DECLARE_RWSEM(topology_lock); +static atomic_t topology_crat_proximity_domain; struct kfd_dev *kfd_device_by_id(uint32_t gpu_id) { @@ -691,12 +694,92 @@ static void kfd_topology_update_device_list(struct list_head *temp_list, } } +static void kfd_debug_print_topology(void) +{ + struct kfd_topology_device *dev; + + down_read(&topology_lock); + + dev = list_last_entry(&topology_device_list, + struct kfd_topology_device, list); + if (dev) { + if (dev->node_props.cpu_cores_count && + dev->node_props.simd_count) { + pr_info("Topology: Add APU node [0x%0x:0x%0x]\n", + dev->node_props.device_id, + dev->node_props.vendor_id); + } else if (dev->node_props.cpu_cores_count) + pr_info("Topology: Add CPU node\n"); + else if (dev->node_props.simd_count) + pr_info("Topology: Add dGPU node [0x%0x:0x%0x]\n", + dev->node_props.device_id, + dev->node_props.vendor_id); + } + up_read(&topology_lock); +} + +/* Helper function for intializing platform_xx members of + * kfd_system_properties. Uses OEM info from the last CPU/APU node. + */ +static void kfd_update_system_properties(void) +{ + struct kfd_topology_device *dev; + + down_read(&topology_lock); + dev = list_last_entry(&topology_device_list, + struct kfd_topology_device, list); + if (dev) { + sys_props.platform_id = + (*((uint64_t *)dev->oem_id)) & CRAT_OEMID_64BIT_MASK; + sys_props.platform_oem = *((uint64_t *)dev->oem_table_id); + sys_props.platform_rev = dev->oem_revision; + } + up_read(&topology_lock); +} + +static void find_system_memory(const struct dmi_header *dm, + void *private) +{ + struct kfd_mem_properties *mem; + u16 mem_width, mem_clock; + struct kfd_topology_device *kdev = + (struct kfd_topology_device *)private; + const u8 *dmi_data = (const u8 *)(dm + 1); + + if (dm->type == DMI_ENTRY_MEM_DEVICE && dm->length >= 0x15) { + mem_width = (u16)(*(const u16 *)(dmi_data + 0x6)); + mem_clock = (u16)(*(const u16 *)(dmi_data + 0x11)); + list_for_each_entry(mem, &kdev->mem_props, list) { + if (mem_width != 0xFFFF && mem_width != 0) + mem->width = mem_width; + if (mem_clock != 0) + mem->mem_clk_max = mem_clock; + } + } +} +/* kfd_add_non_crat_information - Add information that is not currently + * defined in CRAT but is necessary for KFD topology + * @dev - topology device to which addition info is added + */ +static void kfd_add_non_crat_information(struct kfd_topology_device *kdev) +{ + /* Check if CPU only node. */ + if (!kdev->gpu) { + /* Add system memory information */ + dmi_walk(find_system_memory, kdev); + } + /* TODO: For GPU node, rearrange code from kfd_topology_add_device */ +} + int kfd_topology_init(void) { void *crat_image = NULL; size_t image_size = 0; int ret; struct list_head temp_topology_device_list; + int cpu_only_node = 0; + struct kfd_topology_device *kdev; + int proximity_domain; /* topology_device_list - Master list of all topology devices * temp_topology_device_list - temporary list created while parsing CRAT @@ -711,36 +794,78 @@ int kfd_topology_init(void) memset(&sys_props, 0, sizeof(sys_props)); + /* Proximity domains in ACPI CRAT tables start counting at + * 0. The same should be true for virtual CRAT tables created + * at this stage. GPUs added later in kfd_topology_add_device + * use a counter. + */ + proximity_domain = 0; + /* - * Get the CRAT image from the ACPI + * Get the CRAT image from the ACPI. If ACPI doesn't have one + * create a virtual CRAT. + * NOTE: The current implementation expects all AMD APUs to have + * CRAT. If no CRAT is available, it is assumed to be a CPU */ ret = kfd_create_crat_image_acpi(&crat_image, &image_size); if (!ret) { ret = kfd_parse_crat_table(crat_image, - &temp_topology_device_list, 0); - if (ret) + &temp_topology_device_list, + proximity_domain); + if (ret) { + kfd_release_topology_device_list( + &temp_topology_device_list); + kfd_destroy_crat_image(crat_image); + crat_image = NULL; + } + } + + if (!crat_image) { + ret = kfd_create_crat_image_virtual(&crat_image, &image_size, + COMPUTE_UNIT_CPU, NULL, + proximity_domain); + cpu_only_node = 1; + if (ret) { + pr_err("Error creating VCRAT table for CPU\n"); + return ret; + } + + ret = kfd_parse_crat_table(crat_image, + &temp_topology_device_list, + proximity_domain); + if (ret) { + pr_err("Error parsing VCRAT table for CPU\n"); goto err; - } else if (ret == -ENODATA) { - /* TODO: Create fake CRAT table */ - ret = 0; - goto err; - } else { - pr_err("Couldn't get CRAT table size from ACPI\n"); - goto err; + } } down_write(&topology_lock); kfd_topology_update_device_list(&temp_topology_device_list, &topology_device_list); + atomic_set(&topology_crat_proximity_domain, sys_props.num_devices-1); ret = kfd_topology_update_sysfs(); up_write(&topology_lock); if (!ret) { sys_props.generation_count++; + kfd_update_system_properties(); + kfd_debug_print_topology(); pr_info("Finished initializing topology\n"); } else pr_err("Failed to update topology in sysfs ret=%d\n", ret); + /* For nodes with GPU, this information gets added + * when GPU is detected (kfd_topology_add_device). + */ + if (cpu_only_node) { + /* Add additional information to CPU only node created above */ + down_write(&topology_lock); + kdev = list_first_entry(&topology_device_list, + struct kfd_topology_device, list); + up_write(&topology_lock); + kfd_add_non_crat_information(kdev); + } + err: kfd_destroy_crat_image(crat_image); return ret; @@ -754,21 +879,6 @@ void kfd_topology_shutdown(void) up_write(&topology_lock); } -static void kfd_debug_print_topology(void) -{ - struct kfd_topology_device *dev; - uint32_t i = 0; - - pr_info("DEBUG PRINT OF TOPOLOGY:"); - list_for_each_entry(dev, &topology_device_list, list) { - pr_info("Node: %d\n", i); - pr_info("\tGPU assigned: %s\n", (dev->gpu ? "yes" : "no")); - pr_info("\tCPU count: %d\n", dev->node_props.cpu_cores_count); - pr_info("\tSIMD count: %d\n", dev->node_props.simd_count); - i++; - } -} - static uint32_t kfd_generate_gpu_id(struct kfd_dev *gpu) { uint32_t hashout; @@ -954,6 +1064,34 @@ int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_dev **kdev) } +static int kfd_cpumask_to_apic_id(const struct cpumask *cpumask) +{ + const struct cpuinfo_x86 *cpuinfo; + int first_cpu_of_numa_node; + + if (!cpumask || cpumask == cpu_none_mask) + return -1; + first_cpu_of_numa_node = cpumask_first(cpumask); + if (first_cpu_of_numa_node >= nr_cpu_ids) + return -1; + cpuinfo = &cpu_data(first_cpu_of_numa_node); + + return cpuinfo->apicid; +} + +/* kfd_numa_node_to_apic_id - Returns the APIC ID of the first logical processor + * of the given NUMA node (numa_node_id) + * Return -1 on failure + */ +int kfd_numa_node_to_apic_id(int numa_node_id) +{ + if (numa_node_id == -1) { + pr_warn("Invalid NUMA Node. Use online CPU mask\n"); + return kfd_cpumask_to_apic_id(cpu_online_mask); + } + return kfd_cpumask_to_apic_id(cpumask_of_node(numa_node_id)); +} + #if defined(CONFIG_DEBUG_FS) int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 50a741ba51e0..866818964a9b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -148,6 +148,9 @@ struct kfd_topology_device { struct attribute attr_gpuid; struct attribute attr_name; struct attribute attr_props; + uint8_t oem_id[CRAT_OEMID_LENGTH]; + uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH]; + uint32_t oem_revision; }; struct kfd_system_properties { -- GitLab From 3a87177eb14113bbe8cd95a276af2c412eced6ac Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:08:59 -0500 Subject: [PATCH 1195/2547] drm/amdkfd: Add topology support for dGPUs Generate and parse VCRAT tables for dGPUs in kfd_topology_add_device. Some information that isn't available in the CRAT table is patched into the topology after parsing. HSA_CAP_DOORBELL_TYPE_1_0 is dependent on the ASIC feature CP_HQD_PQ_CONTROL.SLOT_BASED_WPTR, which was not introduced in VI until Carrizo. Report HSA_CAP_DOORBELL_TYPE_PRE_1_0 on Tonga ASICs. v2: Added #include to kfd_crat.c to make it compile Signed-off-by: Harish Kasiviswanathan Signed-off-by: Ben Goz Signed-off-by: Amber Lin Signed-off-by: Jay Cornwall Signed-off-by: Kent Russell Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 596 +++++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 5 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 + drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 188 +++++-- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 8 +- 5 files changed, 748 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index c8afbf8015f9..d00061b75193 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -19,11 +19,120 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ + +#include #include +#include #include "kfd_crat.h" #include "kfd_priv.h" #include "kfd_topology.h" +/* GPU Processor ID base for dGPUs for which VCRAT needs to be created. + * GPU processor ID are expressed with Bit[31]=1. + * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs + * used in the CRAT. + */ +static uint32_t gpu_processor_id_low = 0x80001000; + +/* Return the next available gpu_processor_id and increment it for next GPU + * @total_cu_count - Total CUs present in the GPU including ones + * masked off + */ +static inline unsigned int get_and_inc_gpu_processor_id( + unsigned int total_cu_count) +{ + int current_id = gpu_processor_id_low; + + gpu_processor_id_low += total_cu_count; + return current_id; +} + +/* Static table to describe GPU Cache information */ +struct kfd_gpu_cache_info { + uint32_t cache_size; + uint32_t cache_level; + uint32_t flags; + /* Indicates how many Compute Units share this cache + * Value = 1 indicates the cache is not shared + */ + uint32_t num_cu_shared; +}; + +static struct kfd_gpu_cache_info kaveri_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + + }, + { + /* Scalar L1 Instruction Cache (in SQC module) per bank */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* Scalar L1 Data Cache (in SQC module) per bank */ + .cache_size = 8, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + + /* TODO: Add L2 Cache information */ +}; + + +static struct kfd_gpu_cache_info carrizo_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache (in SQC module) per bank */ + .cache_size = 8, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 4, + }, + { + /* Scalar L1 Data Cache (in SQC module) per bank. */ + .cache_size = 4, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 4, + }, + + /* TODO: Add L2 Cache information */ +}; + +/* NOTE: In future if more information is added to struct kfd_gpu_cache_info + * the following ASICs may need a separate table. + */ +#define hawaii_cache_info kaveri_cache_info +#define tonga_cache_info carrizo_cache_info +#define fiji_cache_info carrizo_cache_info +#define polaris10_cache_info carrizo_cache_info +#define polaris11_cache_info carrizo_cache_info + static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, struct crat_subtype_computeunit *cu) { @@ -44,7 +153,7 @@ static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev, dev->node_props.lds_size_in_kb = cu->lds_size_in_kb; dev->node_props.max_waves_per_simd = cu->max_waves_simd; dev->node_props.wave_front_size = cu->wave_front_size; - dev->node_props.array_count = cu->num_arrays; + dev->node_props.array_count = cu->array_count; dev->node_props.cu_per_simd_array = cu->num_cu_per_array; dev->node_props.simd_per_cu = cu->num_simd_per_cu; dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu; @@ -94,9 +203,16 @@ static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem, if (!props) return -ENOMEM; - if (dev->node_props.cpu_cores_count == 0) - props->heap_type = HSA_MEM_HEAP_TYPE_FB_PRIVATE; - else + /* We're on GPU node */ + if (dev->node_props.cpu_cores_count == 0) { + /* APU */ + if (mem->visibility_type == 0) + props->heap_type = + HSA_MEM_HEAP_TYPE_FB_PRIVATE; + /* dGPU */ + else + props->heap_type = mem->visibility_type; + } else props->heap_type = HSA_MEM_HEAP_TYPE_SYSTEM; if (mem->flags & CRAT_MEM_FLAGS_HOT_PLUGGABLE) @@ -128,13 +244,29 @@ static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache, struct kfd_cache_properties *props; struct kfd_topology_device *dev; uint32_t id; + uint32_t total_num_of_cu; id = cache->processor_id_low; pr_debug("Found cache entry in CRAT table with processor_id=%d\n", id); - list_for_each_entry(dev, device_list, list) - if (id == dev->node_props.cpu_core_id_base || - id == dev->node_props.simd_id_base) { + list_for_each_entry(dev, device_list, list) { + total_num_of_cu = (dev->node_props.array_count * + dev->node_props.cu_per_simd_array); + + /* Cache infomration in CRAT doesn't have proximity_domain + * information as it is associated with a CPU core or GPU + * Compute Unit. So map the cache using CPU core Id or SIMD + * (GPU) ID. + * TODO: This works because currently we can safely assume that + * Compute Units are parsed before caches are parsed. In + * future, remove this dependency + */ + if ((id >= dev->node_props.cpu_core_id_base && + id <= dev->node_props.cpu_core_id_base + + dev->node_props.cpu_cores_count) || + (id >= dev->node_props.simd_id_base && + id < dev->node_props.simd_id_base + + total_num_of_cu)) { props = kfd_alloc_struct(props); if (!props) return -ENOMEM; @@ -146,6 +278,8 @@ static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache, props->cachelines_per_tag = cache->lines_per_tag; props->cache_assoc = cache->associativity; props->cache_latency = cache->cache_latency; + memcpy(props->sibling_map, cache->sibling_map, + sizeof(props->sibling_map)); if (cache->flags & CRAT_CACHE_FLAGS_DATA_CACHE) props->cache_type |= HSA_CACHE_TYPE_DATA; @@ -162,6 +296,7 @@ static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache, break; } + } return 0; } @@ -172,8 +307,8 @@ static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache, static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink, struct list_head *device_list) { - struct kfd_iolink_properties *props; - struct kfd_topology_device *dev; + struct kfd_iolink_properties *props = NULL, *props2; + struct kfd_topology_device *dev, *cpu_dev; uint32_t id_from; uint32_t id_to; @@ -192,11 +327,12 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink, props->node_to = id_to; props->ver_maj = iolink->version_major; props->ver_min = iolink->version_minor; + props->iolink_type = iolink->io_interface_type; - /* - * weight factor (derived from CDIR), currently always 1 - */ - props->weight = 1; + if (props->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS) + props->weight = 20; + else + props->weight = node_distance(id_from, id_to); props->min_latency = iolink->minimum_latency; props->max_latency = iolink->maximum_latency; @@ -208,11 +344,29 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink, dev->io_link_count++; dev->node_props.io_links_count++; list_add_tail(&props->list, &dev->io_link_props); - break; } } + /* CPU topology is created before GPUs are detected, so CPU->GPU + * links are not built at that time. If a PCIe type is discovered, it + * means a GPU is detected and we are adding GPU->CPU to the topology. + * At this time, also add the corresponded CPU->GPU link. + */ + if (props && props->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS) { + cpu_dev = kfd_topology_device_by_proximity_domain(id_to); + if (!cpu_dev) + return -ENODEV; + /* same everything but the other direction */ + props2 = kmemdup(props, sizeof(*props2), GFP_KERNEL); + props2->node_from = id_to; + props2->node_to = id_from; + props2->kobj = NULL; + cpu_dev->io_link_count++; + cpu_dev->node_props.io_links_count++; + list_add_tail(&props2->list, &cpu_dev->io_link_props); + } + return 0; } @@ -338,6 +492,176 @@ int kfd_parse_crat_table(void *crat_image, struct list_head *device_list, return ret; } +/* Helper function. See kfd_fill_gpu_cache_info for parameter description */ +static int fill_in_pcache(struct crat_subtype_cache *pcache, + struct kfd_gpu_cache_info *pcache_info, + struct kfd_cu_info *cu_info, + int mem_available, + int cu_bitmask, + int cache_type, unsigned int cu_processor_id, + int cu_block) +{ + unsigned int cu_sibling_map_mask; + int first_active_cu; + + /* First check if enough memory is available */ + if (sizeof(struct crat_subtype_cache) > mem_available) + return -ENOMEM; + + cu_sibling_map_mask = cu_bitmask; + cu_sibling_map_mask >>= cu_block; + cu_sibling_map_mask &= + ((1 << pcache_info[cache_type].num_cu_shared) - 1); + first_active_cu = ffs(cu_sibling_map_mask); + + /* CU could be inactive. In case of shared cache find the first active + * CU. and incase of non-shared cache check if the CU is inactive. If + * inactive active skip it + */ + if (first_active_cu) { + memset(pcache, 0, sizeof(struct crat_subtype_cache)); + pcache->type = CRAT_SUBTYPE_CACHE_AFFINITY; + pcache->length = sizeof(struct crat_subtype_cache); + pcache->flags = pcache_info[cache_type].flags; + pcache->processor_id_low = cu_processor_id + + (first_active_cu - 1); + pcache->cache_level = pcache_info[cache_type].cache_level; + pcache->cache_size = pcache_info[cache_type].cache_size; + + /* Sibling map is w.r.t processor_id_low, so shift out + * inactive CU + */ + cu_sibling_map_mask = + cu_sibling_map_mask >> (first_active_cu - 1); + + pcache->sibling_map[0] = (uint8_t)(cu_sibling_map_mask & 0xFF); + pcache->sibling_map[1] = + (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF); + pcache->sibling_map[2] = + (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF); + pcache->sibling_map[3] = + (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF); + return 0; + } + return 1; +} + +/* kfd_fill_gpu_cache_info - Fill GPU cache info using kfd_gpu_cache_info + * tables + * + * @kdev - [IN] GPU device + * @gpu_processor_id - [IN] GPU processor ID to which these caches + * associate + * @available_size - [IN] Amount of memory available in pcache + * @cu_info - [IN] Compute Unit info obtained from KGD + * @pcache - [OUT] memory into which cache data is to be filled in. + * @size_filled - [OUT] amount of data used up in pcache. + * @num_of_entries - [OUT] number of caches added + */ +static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, + int gpu_processor_id, + int available_size, + struct kfd_cu_info *cu_info, + struct crat_subtype_cache *pcache, + int *size_filled, + int *num_of_entries) +{ + struct kfd_gpu_cache_info *pcache_info; + int num_of_cache_types = 0; + int i, j, k; + int ct = 0; + int mem_available = available_size; + unsigned int cu_processor_id; + int ret; + + switch (kdev->device_info->asic_family) { + case CHIP_KAVERI: + pcache_info = kaveri_cache_info; + num_of_cache_types = ARRAY_SIZE(kaveri_cache_info); + break; + case CHIP_HAWAII: + pcache_info = hawaii_cache_info; + num_of_cache_types = ARRAY_SIZE(hawaii_cache_info); + break; + case CHIP_CARRIZO: + pcache_info = carrizo_cache_info; + num_of_cache_types = ARRAY_SIZE(carrizo_cache_info); + break; + case CHIP_TONGA: + pcache_info = tonga_cache_info; + num_of_cache_types = ARRAY_SIZE(tonga_cache_info); + break; + case CHIP_FIJI: + pcache_info = fiji_cache_info; + num_of_cache_types = ARRAY_SIZE(fiji_cache_info); + break; + case CHIP_POLARIS10: + pcache_info = polaris10_cache_info; + num_of_cache_types = ARRAY_SIZE(polaris10_cache_info); + break; + case CHIP_POLARIS11: + pcache_info = polaris11_cache_info; + num_of_cache_types = ARRAY_SIZE(polaris11_cache_info); + break; + default: + return -EINVAL; + } + + *size_filled = 0; + *num_of_entries = 0; + + /* For each type of cache listed in the kfd_gpu_cache_info table, + * go through all available Compute Units. + * The [i,j,k] loop will + * if kfd_gpu_cache_info.num_cu_shared = 1 + * will parse through all available CU + * If (kfd_gpu_cache_info.num_cu_shared != 1) + * then it will consider only one CU from + * the shared unit + */ + + for (ct = 0; ct < num_of_cache_types; ct++) { + cu_processor_id = gpu_processor_id; + for (i = 0; i < cu_info->num_shader_engines; i++) { + for (j = 0; j < cu_info->num_shader_arrays_per_engine; + j++) { + for (k = 0; k < cu_info->num_cu_per_sh; + k += pcache_info[ct].num_cu_shared) { + + ret = fill_in_pcache(pcache, + pcache_info, + cu_info, + mem_available, + cu_info->cu_bitmap[i][j], + ct, + cu_processor_id, + k); + + if (ret < 0) + break; + + if (!ret) { + pcache++; + (*num_of_entries)++; + mem_available -= + sizeof(*pcache); + (*size_filled) += + sizeof(*pcache); + } + + /* Move to next CU block */ + cu_processor_id += + pcache_info[ct].num_cu_shared; + } + } + } + } + + pr_debug("Added [%d] GPU cache entries\n", *num_of_entries); + + return 0; +} + /* * kfd_create_crat_image_acpi - Allocates memory for CRAT image and * copies CRAT from ACPI (if available). @@ -624,6 +948,239 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) return 0; } +static int kfd_fill_gpu_memory_affinity(int *avail_size, + struct kfd_dev *kdev, uint8_t type, uint64_t size, + struct crat_subtype_memory *sub_type_hdr, + uint32_t proximity_domain, + const struct kfd_local_mem_info *local_mem_info) +{ + *avail_size -= sizeof(struct crat_subtype_memory); + if (*avail_size < 0) + return -ENOMEM; + + memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_memory)); + sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY; + sub_type_hdr->length = sizeof(struct crat_subtype_memory); + sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED; + + sub_type_hdr->proximity_domain = proximity_domain; + + pr_debug("Fill gpu memory affinity - type 0x%x size 0x%llx\n", + type, size); + + sub_type_hdr->length_low = lower_32_bits(size); + sub_type_hdr->length_high = upper_32_bits(size); + + sub_type_hdr->width = local_mem_info->vram_width; + sub_type_hdr->visibility_type = type; + + return 0; +} + +/* kfd_fill_gpu_direct_io_link - Fill in direct io link from GPU + * to its NUMA node + * @avail_size: Available size in the memory + * @kdev - [IN] GPU device + * @sub_type_hdr: Memory into which io link info will be filled in + * @proximity_domain - proximity domain of the GPU node + * + * Return 0 if successful else return -ve value + */ +static int kfd_fill_gpu_direct_io_link(int *avail_size, + struct kfd_dev *kdev, + struct crat_subtype_iolink *sub_type_hdr, + uint32_t proximity_domain) +{ + *avail_size -= sizeof(struct crat_subtype_iolink); + if (*avail_size < 0) + return -ENOMEM; + + memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink)); + + /* Fill in subtype header data */ + sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY; + sub_type_hdr->length = sizeof(struct crat_subtype_iolink); + sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED; + + /* Fill in IOLINK subtype. + * TODO: Fill-in other fields of iolink subtype + */ + sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS; + sub_type_hdr->proximity_domain_from = proximity_domain; +#ifdef CONFIG_NUMA + if (kdev->pdev->dev.numa_node == NUMA_NO_NODE) + sub_type_hdr->proximity_domain_to = 0; + else + sub_type_hdr->proximity_domain_to = kdev->pdev->dev.numa_node; +#else + sub_type_hdr->proximity_domain_to = 0; +#endif + return 0; +} + +/* kfd_create_vcrat_image_gpu - Create Virtual CRAT for CPU + * + * @pcrat_image: Fill in VCRAT for GPU + * @size: [IN] allocated size of crat_image. + * [OUT] actual size of data filled in crat_image + */ +static int kfd_create_vcrat_image_gpu(void *pcrat_image, + size_t *size, struct kfd_dev *kdev, + uint32_t proximity_domain) +{ + struct crat_header *crat_table = (struct crat_header *)pcrat_image; + struct crat_subtype_generic *sub_type_hdr; + struct crat_subtype_computeunit *cu; + struct kfd_cu_info cu_info; + struct amd_iommu_device_info iommu_info; + int avail_size = *size; + uint32_t total_num_of_cu; + int num_of_cache_entries = 0; + int cache_mem_filled = 0; + int ret = 0; + const u32 required_iommu_flags = AMD_IOMMU_DEVICE_FLAG_ATS_SUP | + AMD_IOMMU_DEVICE_FLAG_PRI_SUP | + AMD_IOMMU_DEVICE_FLAG_PASID_SUP; + struct kfd_local_mem_info local_mem_info; + + if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_GPU) + return -EINVAL; + + /* Fill the CRAT Header. + * Modify length and total_entries as subunits are added. + */ + avail_size -= sizeof(struct crat_header); + if (avail_size < 0) + return -ENOMEM; + + memset(crat_table, 0, sizeof(struct crat_header)); + + memcpy(&crat_table->signature, CRAT_SIGNATURE, + sizeof(crat_table->signature)); + /* Change length as we add more subtypes*/ + crat_table->length = sizeof(struct crat_header); + crat_table->num_domains = 1; + crat_table->total_entries = 0; + + /* Fill in Subtype: Compute Unit + * First fill in the sub type header and then sub type data + */ + avail_size -= sizeof(struct crat_subtype_computeunit); + if (avail_size < 0) + return -ENOMEM; + + sub_type_hdr = (struct crat_subtype_generic *)(crat_table + 1); + memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit)); + + sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY; + sub_type_hdr->length = sizeof(struct crat_subtype_computeunit); + sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED; + + /* Fill CU subtype data */ + cu = (struct crat_subtype_computeunit *)sub_type_hdr; + cu->flags |= CRAT_CU_FLAGS_GPU_PRESENT; + cu->proximity_domain = proximity_domain; + + kdev->kfd2kgd->get_cu_info(kdev->kgd, &cu_info); + cu->num_simd_per_cu = cu_info.simd_per_cu; + cu->num_simd_cores = cu_info.simd_per_cu * cu_info.cu_active_number; + cu->max_waves_simd = cu_info.max_waves_per_simd; + + cu->wave_front_size = cu_info.wave_front_size; + cu->array_count = cu_info.num_shader_arrays_per_engine * + cu_info.num_shader_engines; + total_num_of_cu = (cu->array_count * cu_info.num_cu_per_sh); + cu->processor_id_low = get_and_inc_gpu_processor_id(total_num_of_cu); + cu->num_cu_per_array = cu_info.num_cu_per_sh; + cu->max_slots_scatch_cu = cu_info.max_scratch_slots_per_cu; + cu->num_banks = cu_info.num_shader_engines; + cu->lds_size_in_kb = cu_info.lds_size; + + cu->hsa_capability = 0; + + /* Check if this node supports IOMMU. During parsing this flag will + * translate to HSA_CAP_ATS_PRESENT + */ + iommu_info.flags = 0; + if (amd_iommu_device_info(kdev->pdev, &iommu_info) == 0) { + if ((iommu_info.flags & required_iommu_flags) == + required_iommu_flags) + cu->hsa_capability |= CRAT_CU_FLAGS_IOMMU_PRESENT; + } + + crat_table->length += sub_type_hdr->length; + crat_table->total_entries++; + + /* Fill in Subtype: Memory. Only on systems with large BAR (no + * private FB), report memory as public. On other systems + * report the total FB size (public+private) as a single + * private heap. + */ + kdev->kfd2kgd->get_local_mem_info(kdev->kgd, &local_mem_info); + sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + + sub_type_hdr->length); + + if (local_mem_info.local_mem_size_private == 0) + ret = kfd_fill_gpu_memory_affinity(&avail_size, + kdev, HSA_MEM_HEAP_TYPE_FB_PUBLIC, + local_mem_info.local_mem_size_public, + (struct crat_subtype_memory *)sub_type_hdr, + proximity_domain, + &local_mem_info); + else + ret = kfd_fill_gpu_memory_affinity(&avail_size, + kdev, HSA_MEM_HEAP_TYPE_FB_PRIVATE, + local_mem_info.local_mem_size_public + + local_mem_info.local_mem_size_private, + (struct crat_subtype_memory *)sub_type_hdr, + proximity_domain, + &local_mem_info); + if (ret < 0) + return ret; + + crat_table->length += sizeof(struct crat_subtype_memory); + crat_table->total_entries++; + + /* TODO: Fill in cache information. This information is NOT readily + * available in KGD + */ + sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + + sub_type_hdr->length); + ret = kfd_fill_gpu_cache_info(kdev, cu->processor_id_low, + avail_size, + &cu_info, + (struct crat_subtype_cache *)sub_type_hdr, + &cache_mem_filled, + &num_of_cache_entries); + + if (ret < 0) + return ret; + + crat_table->length += cache_mem_filled; + crat_table->total_entries += num_of_cache_entries; + avail_size -= cache_mem_filled; + + /* Fill in Subtype: IO_LINKS + * Only direct links are added here which is Link from GPU to + * to its NUMA node. Indirect links are added by userspace. + */ + sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + + cache_mem_filled); + ret = kfd_fill_gpu_direct_io_link(&avail_size, kdev, + (struct crat_subtype_iolink *)sub_type_hdr, proximity_domain); + + if (ret < 0) + return ret; + + crat_table->length += sub_type_hdr->length; + crat_table->total_entries++; + + *size = crat_table->length; + pr_info("Virtual CRAT table created for GPU\n"); + + return ret; +} + /* kfd_create_crat_image_virtual - Allocates memory for CRAT image and * creates a Virtual CRAT (VCRAT) image * @@ -667,9 +1224,14 @@ int kfd_create_crat_image_virtual(void **crat_image, size_t *size, ret = kfd_create_vcrat_image_cpu(pcrat_image, size); break; case COMPUTE_UNIT_GPU: - /* TODO: */ - ret = -EINVAL; - pr_err("VCRAT not implemented for dGPU\n"); + if (!kdev) + return -EINVAL; + pcrat_image = kmalloc(VCRAT_SIZE_FOR_GPU, GFP_KERNEL); + if (!pcrat_image) + return -ENOMEM; + *size = VCRAT_SIZE_FOR_GPU; + ret = kfd_create_vcrat_image_gpu(pcrat_image, size, kdev, + proximity_domain); break; case (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU): /* TODO: */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h index 1711ab664ec6..b5cd182b9edd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h @@ -109,7 +109,7 @@ struct crat_subtype_computeunit { uint8_t wave_front_size; uint8_t num_banks; uint16_t micro_engine_id; - uint8_t num_arrays; + uint8_t array_count; uint8_t num_cu_per_array; uint8_t num_simd_per_cu; uint8_t max_slots_scatch_cu; @@ -137,7 +137,8 @@ struct crat_subtype_memory { uint32_t length_low; uint32_t length_high; uint32_t width; - uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH]; + uint8_t visibility_type; /* for virtual (dGPU) CRAT */ + uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1]; }; /* diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index aeee9d42171b..f0327c219879 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -668,6 +668,8 @@ int kfd_topology_init(void); void kfd_topology_shutdown(void); int kfd_topology_add_device(struct kfd_dev *gpu); int kfd_topology_remove_device(struct kfd_dev *gpu); +struct kfd_topology_device *kfd_topology_device_by_proximity_domain( + uint32_t proximity_domain); struct kfd_dev *kfd_device_by_id(uint32_t gpu_id); struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev); int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_dev **kdev); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 9aa600477fff..7fe7ee0670e9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -43,6 +43,25 @@ static struct kfd_system_properties sys_props; static DECLARE_RWSEM(topology_lock); static atomic_t topology_crat_proximity_domain; +struct kfd_topology_device *kfd_topology_device_by_proximity_domain( + uint32_t proximity_domain) +{ + struct kfd_topology_device *top_dev; + struct kfd_topology_device *device = NULL; + + down_read(&topology_lock); + + list_for_each_entry(top_dev, &topology_device_list, list) + if (top_dev->proximity_domain == proximity_domain) { + device = top_dev; + break; + } + + up_read(&topology_lock); + + return device; +} + struct kfd_dev *kfd_device_by_id(uint32_t gpu_id) { struct kfd_topology_device *top_dev; @@ -79,6 +98,7 @@ struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev) return device; } +/* Called with write topology_lock acquired */ static void kfd_release_topology_device(struct kfd_topology_device *dev) { struct kfd_mem_properties *mem; @@ -394,8 +414,7 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr, } sysfs_show_32bit_prop(buffer, "max_engine_clk_fcompute", - dev->gpu->kfd2kgd->get_max_engine_clock_in_mhz( - dev->gpu->kgd)); + dev->node_props.max_engine_clk_fcompute); sysfs_show_64bit_prop(buffer, "local_mem_size", (unsigned long long int) 0); @@ -597,6 +616,7 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, return 0; } +/* Called with write topology lock acquired */ static int kfd_build_sysfs_node_tree(void) { struct kfd_topology_device *dev; @@ -613,6 +633,7 @@ static int kfd_build_sysfs_node_tree(void) return 0; } +/* Called with write topology lock acquired */ static void kfd_remove_sysfs_node_tree(void) { struct kfd_topology_device *dev; @@ -908,19 +929,26 @@ static uint32_t kfd_generate_gpu_id(struct kfd_dev *gpu) return hashout; } - +/* kfd_assign_gpu - Attach @gpu to the correct kfd topology device. If + * the GPU device is not already present in the topology device + * list then return NULL. This means a new topology device has to + * be created for this GPU. + * TODO: Rather than assiging @gpu to first topology device withtout + * gpu attached, it will better to have more stringent check. + */ static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu) { struct kfd_topology_device *dev; struct kfd_topology_device *out_dev = NULL; + down_write(&topology_lock); list_for_each_entry(dev, &topology_device_list, list) if (!dev->gpu && (dev->node_props.simd_count > 0)) { dev->gpu = gpu; out_dev = dev; break; } - + up_write(&topology_lock); return out_dev; } @@ -932,6 +960,45 @@ static void kfd_notify_gpu_change(uint32_t gpu_id, int arrival) */ } +/* kfd_fill_mem_clk_max_info - Since CRAT doesn't have memory clock info, + * patch this after CRAT parsing. + */ +static void kfd_fill_mem_clk_max_info(struct kfd_topology_device *dev) +{ + struct kfd_mem_properties *mem; + struct kfd_local_mem_info local_mem_info; + + if (!dev) + return; + + /* Currently, amdgpu driver (amdgpu_mc) deals only with GPUs with + * single bank of VRAM local memory. + * for dGPUs - VCRAT reports only one bank of Local Memory + * for APUs - If CRAT from ACPI reports more than one bank, then + * all the banks will report the same mem_clk_max information + */ + dev->gpu->kfd2kgd->get_local_mem_info(dev->gpu->kgd, + &local_mem_info); + + list_for_each_entry(mem, &dev->mem_props, list) + mem->mem_clk_max = local_mem_info.mem_clk_max; +} + +static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) +{ + struct kfd_iolink_properties *link; + + if (!dev || !dev->gpu) + return; + + /* GPU only creates direck links so apply flags setting to all */ + if (dev->gpu->device_info->asic_family == CHIP_HAWAII) + list_for_each_entry(link, &dev->io_link_props, list) + link->flags = CRAT_IOLINK_FLAGS_ENABLED | + CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | + CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; +} + int kfd_topology_add_device(struct kfd_dev *gpu) { uint32_t gpu_id; @@ -939,6 +1006,9 @@ int kfd_topology_add_device(struct kfd_dev *gpu) struct kfd_cu_info cu_info; int res = 0; struct list_head temp_topology_device_list; + void *crat_image = NULL; + size_t image_size = 0; + int proximity_domain; INIT_LIST_HEAD(&temp_topology_device_list); @@ -946,27 +1016,33 @@ int kfd_topology_add_device(struct kfd_dev *gpu) pr_debug("Adding new GPU (ID: 0x%x) to topology\n", gpu_id); - /* - * Try to assign the GPU to existing topology device (generated from - * CRAT table + proximity_domain = atomic_inc_return(&topology_crat_proximity_domain); + + /* Check to see if this gpu device exists in the topology_device_list. + * If so, assign the gpu to that device, + * else create a Virtual CRAT for this gpu device and then parse that + * CRAT to create a new topology device. Once created assign the gpu to + * that topology device */ dev = kfd_assign_gpu(gpu); if (!dev) { - pr_info("GPU was not found in the current topology. Extending.\n"); - kfd_debug_print_topology(); - dev = kfd_create_topology_device(&temp_topology_device_list); - if (!dev) { - res = -ENOMEM; + res = kfd_create_crat_image_virtual(&crat_image, &image_size, + COMPUTE_UNIT_GPU, gpu, + proximity_domain); + if (res) { + pr_err("Error creating VCRAT for GPU (ID: 0x%x)\n", + gpu_id); + return res; + } + res = kfd_parse_crat_table(crat_image, + &temp_topology_device_list, + proximity_domain); + if (res) { + pr_err("Error parsing VCRAT for GPU (ID: 0x%x)\n", + gpu_id); goto err; } - dev->gpu = gpu; - - /* - * TODO: Make a call to retrieve topology information from the - * GPU vBIOS - */ - down_write(&topology_lock); kfd_topology_update_device_list(&temp_topology_device_list, &topology_device_list); @@ -974,34 +1050,86 @@ int kfd_topology_add_device(struct kfd_dev *gpu) /* Update the SYSFS tree, since we added another topology * device */ - if (kfd_topology_update_sysfs() < 0) - kfd_topology_release_sysfs(); - + res = kfd_topology_update_sysfs(); up_write(&topology_lock); + if (!res) + sys_props.generation_count++; + else + pr_err("Failed to update GPU (ID: 0x%x) to sysfs topology. res=%d\n", + gpu_id, res); + dev = kfd_assign_gpu(gpu); + if (WARN_ON(!dev)) { + res = -ENODEV; + goto err; + } } dev->gpu_id = gpu_id; gpu->id = gpu_id; + + /* TODO: Move the following lines to function + * kfd_add_non_crat_information + */ + + /* Fill-in additional information that is not available in CRAT but + * needed for the topology + */ + dev->gpu->kfd2kgd->get_cu_info(dev->gpu->kgd, &cu_info); - dev->node_props.simd_count = dev->node_props.simd_per_cu * - cu_info.cu_active_number; + dev->node_props.simd_arrays_per_engine = + cu_info.num_shader_arrays_per_engine; + dev->node_props.vendor_id = gpu->pdev->vendor; dev->node_props.device_id = gpu->pdev->device; dev->node_props.location_id = PCI_DEVID(gpu->pdev->bus->number, gpu->pdev->devfn); - /* - * TODO: Retrieve max engine clock values from KGD - */ - - if (dev->gpu->device_info->asic_family == CHIP_CARRIZO) { - dev->node_props.capability |= HSA_CAP_DOORBELL_PACKET_TYPE; + dev->node_props.max_engine_clk_fcompute = + dev->gpu->kfd2kgd->get_max_engine_clock_in_mhz(dev->gpu->kgd); + dev->node_props.max_engine_clk_ccompute = + cpufreq_quick_get_max(0) / 1000; + + kfd_fill_mem_clk_max_info(dev); + kfd_fill_iolink_non_crat_info(dev); + + switch (dev->gpu->device_info->asic_family) { + case CHIP_KAVERI: + case CHIP_HAWAII: + case CHIP_TONGA: + dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_PRE_1_0 << + HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) & + HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK); + break; + case CHIP_CARRIZO: + case CHIP_FIJI: + case CHIP_POLARIS10: + case CHIP_POLARIS11: pr_debug("Adding doorbell packet type capability\n"); + dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_1_0 << + HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) & + HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK); + break; + default: + WARN(1, "Unexpected ASIC family %u", + dev->gpu->device_info->asic_family); } + /* Fix errors in CZ CRAT. + * simd_count: Carrizo CRAT reports wrong simd_count, probably + * because it doesn't consider masked out CUs + * capability flag: Carrizo CRAT doesn't report IOMMU + * flags. TODO: Fix this. + */ + if (dev->gpu->device_info->asic_family == CHIP_CARRIZO) + dev->node_props.simd_count = + cu_info.simd_per_cu * cu_info.cu_active_number; + + kfd_debug_print_topology(); + if (!res) kfd_notify_gpu_change(gpu_id, 1); err: + kfd_destroy_crat_image(crat_image); return res; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 866818964a9b..55de56fe11c9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -39,8 +39,12 @@ #define HSA_CAP_WATCH_POINTS_SUPPORTED 0x00000080 #define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK 0x00000f00 #define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT 8 -#define HSA_CAP_RESERVED 0xfffff000 -#define HSA_CAP_DOORBELL_PACKET_TYPE 0x00001000 +#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000 +#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT 12 +#define HSA_CAP_RESERVED 0xffffc000 + +#define HSA_CAP_DOORBELL_TYPE_PRE_1_0 0x0 +#define HSA_CAP_DOORBELL_TYPE_1_0 0x1 struct kfd_node_properties { uint32_t cpu_cores_count; -- GitLab From f475734729843d0d7b1cd70b9357285d05ca65e3 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Fri, 8 Dec 2017 23:09:00 -0500 Subject: [PATCH 1196/2547] drm/amdkfd: Add perf counters to topology For hardware blocks whose performance counters are accessed via MMIO registers, KFD provides the support for those privileged blocks. IOMMU is one of those privileged blocks. Most performance counter properties required by Thunk are available at /sys/bus/event_source/devices/amd_iommu. This patch adds properties to topology in KFD sysfs for information not available in /sys/bus/event_source/devices/amd_iommu. They are shown at /sys/devices/virtual/kfd/kfd/topology/nodes/0/perf/iommu/ formatted as /sys/devices/virtual/kfd/kfd/topology/nodes/0/perf//, i.e. /sys/devices/virtual/kfd/kfd/topology/nodes/0/perf/iommu/max_concurrent. For dGPUs, who don't have IOMMU, nothing appears under /sys/devices/virtual/kfd/kfd/topology/nodes/0/perf. Signed-off-by: Amber Lin Signed-off-by: Kent Russell Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 116 +++++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 13 +++ 2 files changed, 127 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 7fe7ee0670e9..52d20f51cad4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -104,6 +104,7 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) struct kfd_mem_properties *mem; struct kfd_cache_properties *cache; struct kfd_iolink_properties *iolink; + struct kfd_perf_properties *perf; list_del(&dev->list); @@ -128,6 +129,13 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) kfree(iolink); } + while (dev->perf_props.next != &dev->perf_props) { + perf = container_of(dev->perf_props.next, + struct kfd_perf_properties, list); + list_del(&perf->list); + kfree(perf); + } + kfree(dev); } @@ -162,6 +170,7 @@ struct kfd_topology_device *kfd_create_topology_device( INIT_LIST_HEAD(&dev->mem_props); INIT_LIST_HEAD(&dev->cache_props); INIT_LIST_HEAD(&dev->io_link_props); + INIT_LIST_HEAD(&dev->perf_props); list_add_tail(&dev->list, device_list); @@ -328,6 +337,39 @@ static struct kobj_type cache_type = { .sysfs_ops = &cache_ops, }; +/****** Sysfs of Performance Counters ******/ + +struct kfd_perf_attr { + struct kobj_attribute attr; + uint32_t data; +}; + +static ssize_t perf_show(struct kobject *kobj, struct kobj_attribute *attrs, + char *buf) +{ + struct kfd_perf_attr *attr; + + buf[0] = 0; + attr = container_of(attrs, struct kfd_perf_attr, attr); + if (!attr->data) /* invalid data for PMC */ + return 0; + else + return sysfs_show_32bit_val(buf, attr->data); +} + +#define KFD_PERF_DESC(_name, _data) \ +{ \ + .attr = __ATTR(_name, 0444, perf_show, NULL), \ + .data = _data, \ +} + +static struct kfd_perf_attr perf_attr_iommu[] = { + KFD_PERF_DESC(max_concurrent, 0), + KFD_PERF_DESC(num_counters, 0), + KFD_PERF_DESC(counter_ids, 0), +}; +/****************************************/ + static ssize_t node_show(struct kobject *kobj, struct attribute *attr, char *buffer) { @@ -452,6 +494,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; + struct kfd_perf_properties *perf; if (dev->kobj_iolink) { list_for_each_entry(iolink, &dev->io_link_props, list) @@ -488,6 +531,16 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) dev->kobj_mem = NULL; } + if (dev->kobj_perf) { + list_for_each_entry(perf, &dev->perf_props, list) { + kfree(perf->attr_group); + perf->attr_group = NULL; + } + kobject_del(dev->kobj_perf); + kobject_put(dev->kobj_perf); + dev->kobj_perf = NULL; + } + if (dev->kobj_node) { sysfs_remove_file(dev->kobj_node, &dev->attr_gpuid); sysfs_remove_file(dev->kobj_node, &dev->attr_name); @@ -504,8 +557,10 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; + struct kfd_perf_properties *perf; int ret; - uint32_t i; + uint32_t i, num_attrs; + struct attribute **attrs; if (WARN_ON(dev->kobj_node)) return -EEXIST; @@ -534,6 +589,10 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (!dev->kobj_iolink) return -ENOMEM; + dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node); + if (!dev->kobj_perf) + return -ENOMEM; + /* * Creating sysfs files for node properties */ @@ -611,7 +670,33 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (ret < 0) return ret; i++; -} + } + + /* All hardware blocks have the same number of attributes. */ + num_attrs = sizeof(perf_attr_iommu)/sizeof(struct kfd_perf_attr); + list_for_each_entry(perf, &dev->perf_props, list) { + perf->attr_group = kzalloc(sizeof(struct kfd_perf_attr) + * num_attrs + sizeof(struct attribute_group), + GFP_KERNEL); + if (!perf->attr_group) + return -ENOMEM; + + attrs = (struct attribute **)(perf->attr_group + 1); + if (!strcmp(perf->block_name, "iommu")) { + /* Information of IOMMU's num_counters and counter_ids is shown + * under /sys/bus/event_source/devices/amd_iommu. We don't + * duplicate here. + */ + perf_attr_iommu[0].data = perf->max_concurrent; + for (i = 0; i < num_attrs; i++) + attrs[i] = &perf_attr_iommu[i].attr.attr; + } + perf->attr_group->name = perf->block_name; + perf->attr_group->attrs = attrs; + ret = sysfs_create_group(dev->kobj_perf, perf->attr_group); + if (ret < 0) + return ret; + } return 0; } @@ -778,6 +863,29 @@ static void find_system_memory(const struct dmi_header *dm, } } } + +/* + * Performance counters information is not part of CRAT but we would like to + * put them in the sysfs under topology directory for Thunk to get the data. + * This function is called before updating the sysfs. + */ +static int kfd_add_perf_to_topology(struct kfd_topology_device *kdev) +{ + struct kfd_perf_properties *props; + + if (amd_iommu_pc_supported()) { + props = kfd_alloc_struct(props); + if (!props) + return -ENOMEM; + strcpy(props->block_name, "iommu"); + props->max_concurrent = amd_iommu_pc_get_max_banks(0) * + amd_iommu_pc_get_max_counters(0); /* assume one iommu */ + list_add_tail(&props->list, &kdev->perf_props); + } + + return 0; +} + /* kfd_add_non_crat_information - Add information that is not currently * defined in CRAT but is necessary for KFD topology * @dev - topology device to which addition info is added @@ -860,6 +968,10 @@ int kfd_topology_init(void) } } + kdev = list_first_entry(&temp_topology_device_list, + struct kfd_topology_device, list); + kfd_add_perf_to_topology(kdev); + down_write(&topology_lock); kfd_topology_update_device_list(&temp_topology_device_list, &topology_device_list); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 55de56fe11c9..b9f3142f4ad4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -134,6 +134,13 @@ struct kfd_iolink_properties { struct attribute attr; }; +struct kfd_perf_properties { + struct list_head list; + char block_name[16]; + uint32_t max_concurrent; + struct attribute_group *attr_group; +}; + struct kfd_topology_device { struct list_head list; uint32_t gpu_id; @@ -144,11 +151,13 @@ struct kfd_topology_device { struct list_head cache_props; uint32_t io_link_count; struct list_head io_link_props; + struct list_head perf_props; struct kfd_dev *gpu; struct kobject *kobj_node; struct kobject *kobj_mem; struct kobject *kobj_cache; struct kobject *kobj_iolink; + struct kobject *kobj_perf; struct attribute attr_gpuid; struct attribute attr_name; struct attribute attr_props; @@ -173,4 +182,8 @@ struct kfd_topology_device *kfd_create_topology_device( struct list_head *device_list); void kfd_release_topology_device_list(struct list_head *device_list); +extern bool amd_iommu_pc_supported(void); +extern u8 amd_iommu_pc_get_max_banks(u16 devid); +extern u8 amd_iommu_pc_get_max_counters(u16 devid); + #endif /* __KFD_TOPOLOGY_H__ */ -- GitLab From 70f372bffcc84c9790acbae07d25d7dd0eca4d9f Mon Sep 17 00:00:00 2001 From: Philip Cox Date: Fri, 8 Dec 2017 23:09:01 -0500 Subject: [PATCH 1197/2547] drm/amdkfd: Fixup incorrect info in the CZ CRAT table * Wrong value for max_waves_per_simd * Missing ATC capability bit Signed-off-by: Philip Cox Signed-off-by: Kent Russell Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 52d20f51cad4..80bc71d2c76a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1229,12 +1229,15 @@ int kfd_topology_add_device(struct kfd_dev *gpu) /* Fix errors in CZ CRAT. * simd_count: Carrizo CRAT reports wrong simd_count, probably * because it doesn't consider masked out CUs - * capability flag: Carrizo CRAT doesn't report IOMMU - * flags. TODO: Fix this. + * max_waves_per_simd: Carrizo reports wrong max_waves_per_simd + * capability flag: Carrizo CRAT doesn't report IOMMU flags */ - if (dev->gpu->device_info->asic_family == CHIP_CARRIZO) + if (dev->gpu->device_info->asic_family == CHIP_CARRIZO) { dev->node_props.simd_count = cu_info.simd_per_cu * cu_info.cu_active_number; + dev->node_props.max_waves_per_simd = 10; + dev->node_props.capability |= HSA_CAP_ATS_PRESENT; + } kfd_debug_print_topology(); -- GitLab From 413e85d5d38f9b000561b6b9adf4182803b50af0 Mon Sep 17 00:00:00 2001 From: Ben Goz Date: Fri, 8 Dec 2017 23:09:02 -0500 Subject: [PATCH 1198/2547] drm/amdkfd: Add AQL Queue Memory flag on topology This is needed for enabling a user-mode workaround for an AQL queue wrapping HW bug on Tonga. Signed-off-by: Ben Goz Signed-off-by: Felix Kuehling Acked-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 ++++ drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 80bc71d2c76a..e7daf2cf8000 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -455,6 +455,10 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr, HSA_CAP_WATCH_POINTS_TOTALBITS_MASK); } + if (dev->gpu->device_info->asic_family == CHIP_TONGA) + dev->node_props.capability |= + HSA_CAP_AQL_QUEUE_DOUBLE_MAP; + sysfs_show_32bit_prop(buffer, "max_engine_clk_fcompute", dev->node_props.max_engine_clk_fcompute); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index b9f3142f4ad4..53fca1f45401 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -45,6 +45,7 @@ #define HSA_CAP_DOORBELL_TYPE_PRE_1_0 0x0 #define HSA_CAP_DOORBELL_TYPE_1_0 0x1 +#define HSA_CAP_AQL_QUEUE_DOUBLE_MAP 0x00004000 struct kfd_node_properties { uint32_t cpu_cores_count; -- GitLab From ebcfd1e276207e4436a6d15a81f7e151a103565c Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 8 Dec 2017 23:09:03 -0500 Subject: [PATCH 1199/2547] drm/amdkfd: Module option to disable CRAT table Some systems have broken CRAT tables. Add a module option to ignore a CRAT table. Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 5 +++++ drivers/gpu/drm/amd/amdkfd/kfd_module.c | 5 +++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 ++++++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index d00061b75193..2bc2816767a7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -696,6 +696,11 @@ int kfd_create_crat_image_acpi(void **crat_image, size_t *size) return -EINVAL; } + if (ignore_crat) { + pr_info("CRAT table disabled by module option\n"); + return -ENODATA; + } + pcrat_image = kmalloc(crat_table->length, GFP_KERNEL); if (!pcrat_image) return -ENOMEM; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index f50e4949a2ed..3ac72bed4f31 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -69,6 +69,11 @@ module_param(send_sigterm, int, 0444); MODULE_PARM_DESC(send_sigterm, "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); +int ignore_crat; +module_param(ignore_crat, int, 0444); +MODULE_PARM_DESC(ignore_crat, + "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); + static int amdkfd_init_completed; int kgd2kfd_init(unsigned int interface_version, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index f0327c219879..6a48d29ada47 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -104,6 +104,12 @@ extern int cwsr_enable; */ extern int send_sigterm; +/* + * Ignore CRAT table during KFD initialization, can be used to work around + * broken CRAT tables on some AMD systems + */ +extern int ignore_crat; + /** * enum kfd_sched_policy * -- GitLab From b441093e40e14d8305f0bee37cbaa3fa2e6ce8d0 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 8 Dec 2017 23:09:04 -0500 Subject: [PATCH 1200/2547] drm/amdkfd: Ignore ACPI CRAT for non-APU systems Some AMD motherboards without an APU have a broken CRAT table which causes KFD initialization failures or incorrect information about NUMA nodes, CPU cores or system memory. Ignore CRAT tables without GPUs and rely on KFD's code to create a CRAT table for the CPU. Signed-off-by: Harish Kasiviswanathan Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 24 +++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index e7daf2cf8000..c6a76090a725 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -904,6 +904,25 @@ static void kfd_add_non_crat_information(struct kfd_topology_device *kdev) /* TODO: For GPU node, rearrange code from kfd_topology_add_device */ } +/* kfd_is_acpi_crat_invalid - CRAT from ACPI is valid only for AMD APU devices. + * Ignore CRAT for all other devices. AMD APU is identified if both CPU + * and GPU cores are present. + * @device_list - topology device list created by parsing ACPI CRAT table. + * @return - TRUE if invalid, FALSE is valid. + */ +static bool kfd_is_acpi_crat_invalid(struct list_head *device_list) +{ + struct kfd_topology_device *dev; + + list_for_each_entry(dev, device_list, list) { + if (dev->node_props.cpu_cores_count && + dev->node_props.simd_count) + return false; + } + pr_info("Ignoring ACPI CRAT on non-APU system\n"); + return true; +} + int kfd_topology_init(void) { void *crat_image = NULL; @@ -936,7 +955,7 @@ int kfd_topology_init(void) /* * Get the CRAT image from the ACPI. If ACPI doesn't have one - * create a virtual CRAT. + * or if ACPI CRAT is invalid create a virtual CRAT. * NOTE: The current implementation expects all AMD APUs to have * CRAT. If no CRAT is available, it is assumed to be a CPU */ @@ -945,7 +964,8 @@ int kfd_topology_init(void) ret = kfd_parse_crat_table(crat_image, &temp_topology_device_list, proximity_domain); - if (ret) { + if (ret || + kfd_is_acpi_crat_invalid(&temp_topology_device_list)) { kfd_release_topology_device_list( &temp_topology_device_list); kfd_destroy_crat_image(crat_image); -- GitLab From 9f0a0b41ffccf9a76b19ea263ae16d2d5888093e Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Fri, 8 Dec 2017 23:09:05 -0500 Subject: [PATCH 1201/2547] drm/amdgpu: Add support for reporting VRAM usage Add functions to report the vram_usage from the amdgpu_device Signed-off-by: Kent Russell Signed-off-by: Felix Kuehling Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 7 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 3 ++- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 3 +++ 5 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 996d3538f751..335e454e2ee1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -347,3 +347,10 @@ void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info) cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; cu_info->lds_size = acu_info.lds_size; } + +uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + + return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index eed7dea5e8ac..2a519f9062ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -62,6 +62,7 @@ uint64_t get_gpu_clock_counter(struct kgd_dev *kgd); uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd); void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info); +uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd); #define read_user_wptr(mmptr, wptr, dst) \ ({ \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index c9e2fbe151ff..3d60e1fd9b68 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c @@ -200,7 +200,8 @@ static const struct kfd2kgd_calls kfd2kgd = { .get_fw_version = get_fw_version, .set_scratch_backing_va = set_scratch_backing_va, .get_tile_config = get_tile_config, - .get_cu_info = get_cu_info + .get_cu_info = get_cu_info, + .get_vram_usage = amdgpu_amdkfd_get_vram_usage }; struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index 72ff6463594d..66b513e96437 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -161,7 +161,8 @@ static const struct kfd2kgd_calls kfd2kgd = { .get_fw_version = get_fw_version, .set_scratch_backing_va = set_scratch_backing_va, .get_tile_config = get_tile_config, - .get_cu_info = get_cu_info + .get_cu_info = get_cu_info, + .get_vram_usage = amdgpu_amdkfd_get_vram_usage }; struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void) diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 0899cee6a60f..a6752bd0c871 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -177,6 +177,8 @@ struct tile_config { * * @get_cu_info: Retrieves activated cu info * + * @get_vram_usage: Returns current VRAM usage + * * This structure contains function pointers to services that the kgd driver * provides to amdkfd driver. * @@ -267,6 +269,7 @@ struct kfd2kgd_calls { void (*get_cu_info)(struct kgd_dev *kgd, struct kfd_cu_info *cu_info); + uint64_t (*get_vram_usage)(struct kgd_dev *kgd); }; /** -- GitLab From d7ee946942bdd12394809305e3df05aa4c8b7b8f Mon Sep 17 00:00:00 2001 From: Markus Trippelsdorf Date: Wed, 11 Oct 2017 07:01:31 +0200 Subject: [PATCH 1202/2547] VFS: Handle lazytime in do_mount() Since commit e462ec50cb5fa ("VFS: Differentiate mount flags (MS_*) from internal superblock flags") the lazytime mount option doesn't get passed on anymore. Fix the issue by handling the option in do_mount(). Reviewed-by: Lukas Czerner Signed-off-by: Markus Trippelsdorf Signed-off-by: Al Viro --- fs/namespace.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/namespace.c b/fs/namespace.c index e158ec6b527b..9d1374ab6e06 100644 --- a/fs/namespace.c +++ b/fs/namespace.c @@ -2826,6 +2826,7 @@ long do_mount(const char *dev_name, const char __user *dir_name, SB_DIRSYNC | SB_SILENT | SB_POSIXACL | + SB_LAZYTIME | SB_I_VERSION); if (flags & MS_REMOUNT) -- GitLab From d70ef22892ed6c066e51e118b225923c9b74af34 Mon Sep 17 00:00:00 2001 From: Jiri Slaby Date: Thu, 30 Nov 2017 15:35:44 +0100 Subject: [PATCH 1203/2547] futex: futex_wake_op, fix sign_extend32 sign bits sign_extend32 counts the sign bit parameter from 0, not from 1. So we have to use "11" for 12th bit, not "12". This mistake means we have not allowed negative op and cmp args since commit 30d6e0a4190d ("futex: Remove duplicated code and fix undefined behaviour") till now. Fixes: 30d6e0a4190d ("futex: Remove duplicated code and fix undefined behaviour") Signed-off-by: Jiri Slaby Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Darren Hart Signed-off-by: Linus Torvalds --- kernel/futex.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/futex.c b/kernel/futex.c index 76ed5921117a..57d0b3657e16 100644 --- a/kernel/futex.c +++ b/kernel/futex.c @@ -1582,8 +1582,8 @@ static int futex_atomic_op_inuser(unsigned int encoded_op, u32 __user *uaddr) { unsigned int op = (encoded_op & 0x70000000) >> 28; unsigned int cmp = (encoded_op & 0x0f000000) >> 24; - int oparg = sign_extend32((encoded_op & 0x00fff000) >> 12, 12); - int cmparg = sign_extend32(encoded_op & 0x00000fff, 12); + int oparg = sign_extend32((encoded_op & 0x00fff000) >> 12, 11); + int cmparg = sign_extend32(encoded_op & 0x00000fff, 11); int oldval, ret; if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) { -- GitLab From 98087c05b9fc4ff8935bfc8f4b71afb4251c8867 Mon Sep 17 00:00:00 2001 From: Jeff Layton Date: Thu, 23 Nov 2017 20:34:40 +0100 Subject: [PATCH 1204/2547] hpfs: don't bother with the i_version counter or f_version HPFS does not set SB_I_VERSION and does not use the i_version counter internally. Signed-off-by: Jeff Layton Signed-off-by: Mikulas Patocka Reviewed-by: Mikulas Patocka Signed-off-by: Linus Torvalds --- fs/hpfs/dir.c | 1 - fs/hpfs/dnode.c | 2 -- fs/hpfs/super.c | 1 - 3 files changed, 4 deletions(-) diff --git a/fs/hpfs/dir.c b/fs/hpfs/dir.c index 8d6b7e35faf9..c83ece7facc5 100644 --- a/fs/hpfs/dir.c +++ b/fs/hpfs/dir.c @@ -150,7 +150,6 @@ static int hpfs_readdir(struct file *file, struct dir_context *ctx) if (unlikely(ret < 0)) goto out; ctx->pos = ((loff_t) hpfs_de_as_down_as_possible(inode->i_sb, hpfs_inode->i_dno) << 4) + 1; - file->f_version = inode->i_version; } next_pos = ctx->pos; if (!(de = map_pos_dirent(inode, &next_pos, &qbh))) { diff --git a/fs/hpfs/dnode.c b/fs/hpfs/dnode.c index 3b834563b1f1..a4ad18afbdec 100644 --- a/fs/hpfs/dnode.c +++ b/fs/hpfs/dnode.c @@ -419,7 +419,6 @@ int hpfs_add_dirent(struct inode *i, c = 1; goto ret; } - i->i_version++; c = hpfs_add_to_dnode(i, dno, name, namelen, new_de, 0); ret: return c; @@ -726,7 +725,6 @@ int hpfs_remove_dirent(struct inode *i, dnode_secno dno, struct hpfs_dirent *de, return 2; } } - i->i_version++; for_all_poss(i, hpfs_pos_del, (t = get_pos(dnode, de)) + 1, 1); hpfs_delete_de(i->i_sb, dnode, de); hpfs_mark_4buffers_dirty(qbh); diff --git a/fs/hpfs/super.c b/fs/hpfs/super.c index c45a3b9b9ac7..f2c3ebcd309c 100644 --- a/fs/hpfs/super.c +++ b/fs/hpfs/super.c @@ -235,7 +235,6 @@ static struct inode *hpfs_alloc_inode(struct super_block *sb) ei = kmem_cache_alloc(hpfs_inode_cachep, GFP_NOFS); if (!ei) return NULL; - ei->vfs_inode.i_version = 1; return &ei->vfs_inode; } -- GitLab From 50c4c4e268a2d7a3e58ebb698ac74da0de40ae36 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sun, 10 Dec 2017 17:56:26 -0800 Subject: [PATCH 1205/2547] Linux 4.15-rc3 --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index c988e46a53cd..3f4d157add54 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ VERSION = 4 PATCHLEVEL = 15 SUBLEVEL = 0 -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = Fearless Coyote # *DOCUMENTATION* -- GitLab From 6f6a23a213be51728502b88741ba6a10cda2441d Mon Sep 17 00:00:00 2001 From: Adam Wallis Date: Mon, 27 Nov 2017 10:45:01 -0500 Subject: [PATCH 1206/2547] dmaengine: dmatest: move callback wait queue to thread context Commit adfa543e7314 ("dmatest: don't use set_freezable_with_signal()") introduced a bug (that is in fact documented by the patch commit text) that leaves behind a dangling pointer. Since the done_wait structure is allocated on the stack, future invocations to the DMATEST can produce undesirable results (e.g., corrupted spinlocks). Commit a9df21e34b42 ("dmaengine: dmatest: warn user when dma test times out") attempted to WARN the user that the stack was likely corrupted but did not fix the actual issue. This patch fixes the issue by pushing the wait queue and callback structs into the the thread structure. If a failure occurs due to time, dmaengine_terminate_all will force the callback to safely call wake_up_all() without possibility of using a freed pointer. Cc: stable@vger.kernel.org Bug: https://bugzilla.kernel.org/show_bug.cgi?id=197605 Fixes: adfa543e7314 ("dmatest: don't use set_freezable_with_signal()") Reviewed-by: Sinan Kaya Suggested-by: Shunyong Yang Signed-off-by: Adam Wallis Signed-off-by: Vinod Koul --- drivers/dma/dmatest.c | 55 ++++++++++++++++++++++++------------------- 1 file changed, 31 insertions(+), 24 deletions(-) diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c index 47edc7fbf91f..ec5f9d2bc820 100644 --- a/drivers/dma/dmatest.c +++ b/drivers/dma/dmatest.c @@ -155,6 +155,12 @@ MODULE_PARM_DESC(run, "Run the test (default: false)"); #define PATTERN_COUNT_MASK 0x1f #define PATTERN_MEMSET_IDX 0x01 +/* poor man's completion - we want to use wait_event_freezable() on it */ +struct dmatest_done { + bool done; + wait_queue_head_t *wait; +}; + struct dmatest_thread { struct list_head node; struct dmatest_info *info; @@ -165,6 +171,8 @@ struct dmatest_thread { u8 **dsts; u8 **udsts; enum dma_transaction_type type; + wait_queue_head_t done_wait; + struct dmatest_done test_done; bool done; }; @@ -342,18 +350,25 @@ static unsigned int dmatest_verify(u8 **bufs, unsigned int start, return error_count; } -/* poor man's completion - we want to use wait_event_freezable() on it */ -struct dmatest_done { - bool done; - wait_queue_head_t *wait; -}; static void dmatest_callback(void *arg) { struct dmatest_done *done = arg; - - done->done = true; - wake_up_all(done->wait); + struct dmatest_thread *thread = + container_of(arg, struct dmatest_thread, done_wait); + if (!thread->done) { + done->done = true; + wake_up_all(done->wait); + } else { + /* + * If thread->done, it means that this callback occurred + * after the parent thread has cleaned up. This can + * happen in the case that driver doesn't implement + * the terminate_all() functionality and a dma operation + * did not occur within the timeout period + */ + WARN(1, "dmatest: Kernel memory may be corrupted!!\n"); + } } static unsigned int min_odd(unsigned int x, unsigned int y) @@ -424,9 +439,8 @@ static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len) */ static int dmatest_func(void *data) { - DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait); struct dmatest_thread *thread = data; - struct dmatest_done done = { .wait = &done_wait }; + struct dmatest_done *done = &thread->test_done; struct dmatest_info *info; struct dmatest_params *params; struct dma_chan *chan; @@ -673,9 +687,9 @@ static int dmatest_func(void *data) continue; } - done.done = false; + done->done = false; tx->callback = dmatest_callback; - tx->callback_param = &done; + tx->callback_param = done; cookie = tx->tx_submit(tx); if (dma_submit_error(cookie)) { @@ -688,21 +702,12 @@ static int dmatest_func(void *data) } dma_async_issue_pending(chan); - wait_event_freezable_timeout(done_wait, done.done, + wait_event_freezable_timeout(thread->done_wait, done->done, msecs_to_jiffies(params->timeout)); status = dma_async_is_tx_complete(chan, cookie, NULL, NULL); - if (!done.done) { - /* - * We're leaving the timed out dma operation with - * dangling pointer to done_wait. To make this - * correct, we'll need to allocate wait_done for - * each test iteration and perform "who's gonna - * free it this time?" dancing. For now, just - * leave it dangling. - */ - WARN(1, "dmatest: Kernel stack may be corrupted!!\n"); + if (!done->done) { dmaengine_unmap_put(um); result("test timed out", total_tests, src_off, dst_off, len, 0); @@ -789,7 +794,7 @@ static int dmatest_func(void *data) dmatest_KBs(runtime, total_len), ret); /* terminate all transfers on specified channels */ - if (ret) + if (ret || failed_tests) dmaengine_terminate_all(chan); thread->done = true; @@ -849,6 +854,8 @@ static int dmatest_add_threads(struct dmatest_info *info, thread->info = info; thread->chan = dtc->chan; thread->type = type; + thread->test_done.wait = &thread->done_wait; + init_waitqueue_head(&thread->done_wait); smp_wmb(); thread->task = kthread_create(dmatest_func, thread, "%s-%s%u", dma_chan_name(chan), op, i); -- GitLab From eb9436966fdc84cebdf222952a99898ab46d9bb0 Mon Sep 17 00:00:00 2001 From: Tobias Jordan Date: Wed, 6 Dec 2017 14:28:27 +0100 Subject: [PATCH 1207/2547] dmaengine: jz4740: disable/unprepare clk if probe fails in error path of jz4740_dma_probe(), call clk_disable_unprepare() to clean up. Found by Linux Driver Verification project (linuxtesting.org). Fixes: 25ce6c35fea0 MIPS: jz4740: Remove custom DMA API Signed-off-by: Tobias Jordan Signed-off-by: Vinod Koul --- drivers/dma/dma-jz4740.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dma-jz4740.c b/drivers/dma/dma-jz4740.c index d50273fed715..afd5e10f8927 100644 --- a/drivers/dma/dma-jz4740.c +++ b/drivers/dma/dma-jz4740.c @@ -555,7 +555,7 @@ static int jz4740_dma_probe(struct platform_device *pdev) ret = dma_async_device_register(dd); if (ret) - return ret; + goto err_clk; irq = platform_get_irq(pdev, 0); ret = request_irq(irq, jz4740_dma_irq, 0, dev_name(&pdev->dev), dmadev); @@ -568,6 +568,8 @@ static int jz4740_dma_probe(struct platform_device *pdev) err_unregister: dma_async_device_unregister(dd); +err_clk: + clk_disable_unprepare(dmadev->clk); return ret; } -- GitLab From 996fc4477a0ea28226b30d175f053fb6f9a4fa36 Mon Sep 17 00:00:00 2001 From: Theodore Ts'o Date: Sun, 10 Dec 2017 23:44:11 -0500 Subject: [PATCH 1208/2547] ext4: add missing error check in __ext4_new_inode() It's possible for ext4_get_acl() to return an ERR_PTR. So we need to add a check for this case in __ext4_new_inode(). Otherwise on an error we can end up oops the kernel. This was getting triggered by xfstests generic/388, which is a test which exercises the shutdown code path. Signed-off-by: Theodore Ts'o Cc: stable@vger.kernel.org --- fs/ext4/ialloc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fs/ext4/ialloc.c b/fs/ext4/ialloc.c index b4267d72f249..b32cf263750d 100644 --- a/fs/ext4/ialloc.c +++ b/fs/ext4/ialloc.c @@ -816,6 +816,8 @@ struct inode *__ext4_new_inode(handle_t *handle, struct inode *dir, #ifdef CONFIG_EXT4_FS_POSIX_ACL struct posix_acl *p = get_acl(dir, ACL_TYPE_DEFAULT); + if (IS_ERR(p)) + return ERR_CAST(p); if (p) { int acl_size = p->a_count * sizeof(ext4_acl_entry); -- GitLab From b9dfda561585b3c1cf4381c9719fee860bfd2428 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 9 Dec 2017 10:44:17 +0000 Subject: [PATCH 1209/2547] drm/i915: Remove debugfs/i915_seqno_info The per-engine seqno info is now available from debugfs/i915_engine_info obsoleting debugfs/i915_seqno_info, so remove it. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171209104418.4223-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_debugfs.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9ccc6bcc7069..bebf33333ae3 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -683,19 +683,6 @@ static void i915_ring_seqno_info(struct seq_file *m, spin_unlock_irq(&b->rb_lock); } -static int i915_gem_seqno_info(struct seq_file *m, void *data) -{ - struct drm_i915_private *dev_priv = node_to_i915(m->private); - struct intel_engine_cs *engine; - enum intel_engine_id id; - - for_each_engine(engine, dev_priv, id) - i915_ring_seqno_info(m, engine); - - return 0; -} - - static int i915_interrupt_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -4672,7 +4659,6 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_gem_objects", i915_gem_object_info, 0}, {"i915_gem_gtt", i915_gem_gtt_info, 0}, {"i915_gem_stolen", i915_gem_stolen_list_info }, - {"i915_gem_seqno", i915_gem_seqno_info, 0}, {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, {"i915_gem_interrupt", i915_interrupt_info, 0}, {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, -- GitLab From d5acadfe7de71fac2a562df0b0a1d37973b50dd3 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 9 Dec 2017 10:44:18 +0000 Subject: [PATCH 1210/2547] drm/i915: Stop showing seqno info from debugfs/i915_interrupt_info Since the seqno information shown from i915_interrupt_info is just a small subset of i915_engine_info, remove it. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171209104418.4223-2-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_debugfs.c | 24 ++---------------------- drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++ 2 files changed, 6 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index bebf33333ae3..f91dd68c53a1 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -664,25 +664,6 @@ static int i915_gem_batch_pool_info(struct seq_file *m, void *data) return 0; } -static void i915_ring_seqno_info(struct seq_file *m, - struct intel_engine_cs *engine) -{ - struct intel_breadcrumbs *b = &engine->breadcrumbs; - struct rb_node *rb; - - seq_printf(m, "Current sequence (%s): %x\n", - engine->name, intel_engine_get_seqno(engine)); - - spin_lock_irq(&b->rb_lock); - for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { - struct intel_wait *w = rb_entry(rb, typeof(*w), node); - - seq_printf(m, "Waiting (%s): %s [%d] on %x\n", - engine->name, w->tsk->comm, w->tsk->pid, w->seqno); - } - spin_unlock_irq(&b->rb_lock); -} - static int i915_interrupt_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -883,13 +864,12 @@ static int i915_interrupt_info(struct seq_file *m, void *data) seq_printf(m, "Graphics Interrupt mask: %08x\n", I915_READ(GTIMR)); } - for_each_engine(engine, dev_priv, id) { - if (INTEL_GEN(dev_priv) >= 6) { + if (INTEL_GEN(dev_priv) >= 6) { + for_each_engine(engine, dev_priv, id) { seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", engine->name, I915_READ_IMR(engine)); } - i915_ring_seqno_info(m, engine); } intel_runtime_pm_put(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 04c31475a7ae..aad353195f17 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1840,6 +1840,10 @@ void intel_engine_dump(struct intel_engine_cs *engine, } spin_unlock_irq(&b->rb_lock); + if (INTEL_GEN(dev_priv) >= 6) { + drm_printf(m, "\tRING_IMR: %08x\n", I915_READ_IMR(engine)); + } + drm_printf(m, "IRQ? 0x%lx (breadcrumbs? %s) (execlists? %s)\n", engine->irq_posted, yesno(test_bit(ENGINE_IRQ_BREADCRUMB, -- GitLab From eb3f05171c2e84f0114403df0fea942479fdaa3e Mon Sep 17 00:00:00 2001 From: Pei Zhang Date: Mon, 11 Dec 2017 17:15:02 +0800 Subject: [PATCH 1211/2547] drm/i915/gvt: refine function emulate_mmio_read/write These 2 functions are coded by multiple person in multiple patches. The 'return' and 'goto err' are mix-used in same place, which cause the function looks disorder. Unify to use only 'goto' so that the gvt lock is acquired in one place and released in one place. Signed-off-by: Pei Zhang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/mmio.c | 36 ++++++++++++++------------------- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c index 4ea0feb5f04d..f7227a3ad469 100644 --- a/drivers/gpu/drm/i915/gvt/mmio.c +++ b/drivers/gpu/drm/i915/gvt/mmio.c @@ -157,7 +157,6 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa, unsigned int offset = 0; int ret = -EINVAL; - if (vgpu->failsafe) { failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true); return 0; @@ -166,8 +165,7 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa, if (vgpu_gpa_is_aperture(vgpu, pa)) { ret = vgpu_aperture_rw(vgpu, pa, p_data, bytes, true); - mutex_unlock(&gvt->lock); - return ret; + goto out; } if (atomic_read(&vgpu->gtt.n_tracked_guest_page)) { @@ -183,8 +181,7 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa, ret, t->gfn, pa, *(u32 *)p_data, bytes); } - mutex_unlock(&gvt->lock); - return ret; + goto out; } } @@ -205,14 +202,12 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa, p_data, bytes); if (ret) goto err; - mutex_unlock(&gvt->lock); - return ret; + goto out; } if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) { ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes); - mutex_unlock(&gvt->lock); - return ret; + goto out; } if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1))) @@ -228,11 +223,13 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa, goto err; intel_gvt_mmio_set_accessed(gvt, offset); - mutex_unlock(&gvt->lock); - return 0; + ret = 0; + goto out; + err: gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n", offset, bytes); +out: mutex_unlock(&gvt->lock); return ret; } @@ -263,8 +260,7 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa, if (vgpu_gpa_is_aperture(vgpu, pa)) { ret = vgpu_aperture_rw(vgpu, pa, p_data, bytes, false); - mutex_unlock(&gvt->lock); - return ret; + goto out; } if (atomic_read(&vgpu->gtt.n_tracked_guest_page)) { @@ -280,8 +276,7 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa, ret, t->gfn, pa, *(u32 *)p_data, bytes); } - mutex_unlock(&gvt->lock); - return ret; + goto out; } } @@ -302,14 +297,12 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa, p_data, bytes); if (ret) goto err; - mutex_unlock(&gvt->lock); - return ret; + goto out; } if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) { ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes); - mutex_unlock(&gvt->lock); - return ret; + goto out; } ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false); @@ -317,11 +310,12 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa, goto err; intel_gvt_mmio_set_accessed(gvt, offset); - mutex_unlock(&gvt->lock); - return 0; + ret = 0; + goto out; err: gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset, bytes); +out: mutex_unlock(&gvt->lock); return ret; } -- GitLab From 461bd6227ede277138bf33c2156b6ebd1fba04c2 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Sat, 9 Dec 2017 00:37:59 -0600 Subject: [PATCH 1212/2547] drm/i915/gvt/fb_decoder: Fix out-of-bounds read In case function skl_format_to_drm returns -EINVAL, fmt turns into a huge number as fmt is of type u32, hence there is an out-of-bounds read when using fmt as an index for array skl_pixel_formats at line 225: plane->bpp = skl_pixel_formats[fmt].bpp; Fix this by comparing the value returned by function skl_format_to_drm against the size of array skl_pixel_formats, so in case it is greater than or equal to the number of items contained in skl_pixel_formats, print an error message and return -EINVAL. Addresses-Coverity-ID: 1462495 Addresses-Coverity-ID: 1462502 ("Out-of-bounds read") Fixes: 9f31d1063b43 ("drm/i915/gvt: Add framebuffer decoder support") Signed-off-by: Gustavo A. R. Silva Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/fb_decoder.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 72f42176f35c..6cc99543693f 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -222,6 +222,12 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, val & PLANE_CTL_ORDER_RGBX, val & PLANE_CTL_ALPHA_MASK, val & PLANE_CTL_YUV422_ORDER_MASK); + + if (fmt >= ARRAY_SIZE(skl_pixel_formats)) { + gvt_vgpu_err("Out-of-bounds pixel format index\n"); + return -EINVAL; + } + plane->bpp = skl_pixel_formats[fmt].bpp; plane->drm_format = skl_pixel_formats[fmt].drm_format; } else { -- GitLab From f5f00e7dcc4161f07b76ff1a854e8b1ea7a1ed41 Mon Sep 17 00:00:00 2001 From: Xiaolin Zhang Date: Tue, 5 Dec 2017 14:45:32 +0800 Subject: [PATCH 1213/2547] drm/i915/gvt: Fix pipe A enable as default for vgpu observed igt drv_module_reload test case failure on 4.15.0 rc2 kernel with panic due to no active pipe available. the gpu will reset during unload/load and make pipe config reg lost which can cause kernel panic issue happen. this patch is to move pipe enabling to emulate_mointor_status_chagne to handle vgpu reset case as well. Fixes: 7e6059020894 ("drm/i915/gvt: enabled pipe A default on creating vgpu") Signed-off-by: Xiaolin Zhang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/display.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 355120865efd..309f3fa6794a 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -266,6 +266,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) /* Clear host CRT status, so guest couldn't detect this host CRT. */ if (IS_BROADWELL(dev_priv)) vgpu_vreg(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; + + vgpu_vreg(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; } static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) @@ -282,7 +284,6 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, int type, unsigned int resolution) { - struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); if (WARN_ON(resolution >= GVT_EDID_NUM)) @@ -308,7 +309,7 @@ static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, port->type = type; emulate_monitor_status_change(vgpu); - vgpu_vreg(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; + return 0; } -- GitLab From 0afe9d4ab9d40c281bdcdd118661fe8e4bdcef18 Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Sat, 9 Dec 2017 21:10:10 +0100 Subject: [PATCH 1214/2547] mac80211: fix locking in ieee80211_sta_tear_down_BA_sessions Due to overlap between commit 1281103770e9 ("mac80211: Simplify locking in ieee80211_sta_tear_down_BA_sessions()") and the way that Luca modified commit 72e2c3438ba3 ("mac80211: tear down RX aggregations first") when sending it upstream from Intel's internal tree, we get the following warning: WARNING: CPU: 0 PID: 5472 at net/mac80211/agg-tx.c:315 ___ieee80211_stop_tx_ba_session+0x158/0x1f0 since there's no appropriate locking around the call to ___ieee80211_stop_tx_ba_session; Sara's original just had a call to the locked __ieee80211_stop_tx_ba_session (one less underscore) but it looks like Luca modified both of the calls when fixing it up for upstream, leading to the problem at hand. Move the locking appropriately to fix this problem. Reported-by: Kalle Valo Reported-by: Pavel Machek Tested-by: Pavel Machek Signed-off-by: Johannes Berg --- net/mac80211/ht.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/net/mac80211/ht.c b/net/mac80211/ht.c index 167f83b853e6..1621b6ab17ba 100644 --- a/net/mac80211/ht.c +++ b/net/mac80211/ht.c @@ -291,16 +291,15 @@ void ieee80211_sta_tear_down_BA_sessions(struct sta_info *sta, int i; mutex_lock(&sta->ampdu_mlme.mtx); - for (i = 0; i < IEEE80211_NUM_TIDS; i++) { + for (i = 0; i < IEEE80211_NUM_TIDS; i++) ___ieee80211_stop_rx_ba_session(sta, i, WLAN_BACK_RECIPIENT, WLAN_REASON_QSTA_LEAVE_QBSS, reason != AGG_STOP_DESTROY_STA && reason != AGG_STOP_PEER_REQUEST); - } - mutex_unlock(&sta->ampdu_mlme.mtx); for (i = 0; i < IEEE80211_NUM_TIDS; i++) ___ieee80211_stop_tx_ba_session(sta, i, reason); + mutex_unlock(&sta->ampdu_mlme.mtx); /* stopping might queue the work again - so cancel only afterwards */ cancel_work_sync(&sta->ampdu_mlme.work); -- GitLab From 438c84c2f0c794f75ab55ce65c505b01bfce4480 Mon Sep 17 00:00:00 2001 From: Miklos Szeredi Date: Mon, 11 Dec 2017 11:28:10 +0100 Subject: [PATCH 1215/2547] ovl: don't follow redirects if redirect_dir=off Overlayfs is following redirects even when redirects are disabled. If this is unintentional (probably the majority of cases) then this can be a problem. E.g. upper layer comes from untrusted USB drive, and attacker crafts a redirect to enable read access to otherwise unreadable directories. If "redirect_dir=off", then turn off following as well as creation of redirects. If "redirect_dir=follow", then turn on following, but turn off creation of redirects (which is what "redirect_dir=off" does now). This is a backward incompatible change, so make it dependent on a config option. Reported-by: David Howells Signed-off-by: Miklos Szeredi --- Documentation/filesystems/overlayfs.txt | 34 +++++++++++++ fs/overlayfs/Kconfig | 10 ++++ fs/overlayfs/namei.c | 16 ++++++ fs/overlayfs/ovl_entry.h | 2 + fs/overlayfs/super.c | 68 ++++++++++++++++++------- 5 files changed, 113 insertions(+), 17 deletions(-) diff --git a/Documentation/filesystems/overlayfs.txt b/Documentation/filesystems/overlayfs.txt index 8caa60734647..e6a5f4912b6d 100644 --- a/Documentation/filesystems/overlayfs.txt +++ b/Documentation/filesystems/overlayfs.txt @@ -156,6 +156,40 @@ handle it in two different ways: root of the overlay. Finally the directory is moved to the new location. +There are several ways to tune the "redirect_dir" feature. + +Kernel config options: + +- OVERLAY_FS_REDIRECT_DIR: + If this is enabled, then redirect_dir is turned on by default. +- OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW: + If this is enabled, then redirects are always followed by default. Enabling + this results in a less secure configuration. Enable this option only when + worried about backward compatibility with kernels that have the redirect_dir + feature and follow redirects even if turned off. + +Module options (can also be changed through /sys/module/overlay/parameters/*): + +- "redirect_dir=BOOL": + See OVERLAY_FS_REDIRECT_DIR kernel config option above. +- "redirect_always_follow=BOOL": + See OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW kernel config option above. +- "redirect_max=NUM": + The maximum number of bytes in an absolute redirect (default is 256). + +Mount options: + +- "redirect_dir=on": + Redirects are enabled. +- "redirect_dir=follow": + Redirects are not created, but followed. +- "redirect_dir=off": + Redirects are not created and only followed if "redirect_always_follow" + feature is enabled in the kernel/module config. +- "redirect_dir=nofollow": + Redirects are not created and not followed (equivalent to "redirect_dir=off" + if "redirect_always_follow" feature is not enabled). + Non-directories --------------- diff --git a/fs/overlayfs/Kconfig b/fs/overlayfs/Kconfig index cbfc196e5dc5..5ac415466861 100644 --- a/fs/overlayfs/Kconfig +++ b/fs/overlayfs/Kconfig @@ -24,6 +24,16 @@ config OVERLAY_FS_REDIRECT_DIR an overlay which has redirects on a kernel that doesn't support this feature will have unexpected results. +config OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW + bool "Overlayfs: follow redirects even if redirects are turned off" + default y + depends on OVERLAY_FS + help + Disable this to get a possibly more secure configuration, but that + might not be backward compatible with previous kernels. + + For more information, see Documentation/filesystems/overlayfs.txt + config OVERLAY_FS_INDEX bool "Overlayfs: turn on inodes index feature by default" depends on OVERLAY_FS diff --git a/fs/overlayfs/namei.c b/fs/overlayfs/namei.c index 625ed8066570..2a12dc2e9840 100644 --- a/fs/overlayfs/namei.c +++ b/fs/overlayfs/namei.c @@ -681,6 +681,22 @@ struct dentry *ovl_lookup(struct inode *dir, struct dentry *dentry, if (d.stop) break; + /* + * Following redirects can have security consequences: it's like + * a symlink into the lower layer without the permission checks. + * This is only a problem if the upper layer is untrusted (e.g + * comes from an USB drive). This can allow a non-readable file + * or directory to become readable. + * + * Only following redirects when redirects are enabled disables + * this attack vector when not necessary. + */ + err = -EPERM; + if (d.redirect && !ofs->config.redirect_follow) { + pr_warn_ratelimited("overlay: refusing to follow redirect for (%pd2)\n", dentry); + goto out_put; + } + if (d.redirect && d.redirect[0] == '/' && poe != roe) { poe = roe; diff --git a/fs/overlayfs/ovl_entry.h b/fs/overlayfs/ovl_entry.h index 752bab645879..9d0bc03bf6e4 100644 --- a/fs/overlayfs/ovl_entry.h +++ b/fs/overlayfs/ovl_entry.h @@ -14,6 +14,8 @@ struct ovl_config { char *workdir; bool default_permissions; bool redirect_dir; + bool redirect_follow; + const char *redirect_mode; bool index; }; diff --git a/fs/overlayfs/super.c b/fs/overlayfs/super.c index 288d20f9a55a..13a8a8617e44 100644 --- a/fs/overlayfs/super.c +++ b/fs/overlayfs/super.c @@ -33,6 +33,13 @@ module_param_named(redirect_dir, ovl_redirect_dir_def, bool, 0644); MODULE_PARM_DESC(ovl_redirect_dir_def, "Default to on or off for the redirect_dir feature"); +static bool ovl_redirect_always_follow = + IS_ENABLED(CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW); +module_param_named(redirect_always_follow, ovl_redirect_always_follow, + bool, 0644); +MODULE_PARM_DESC(ovl_redirect_always_follow, + "Follow redirects even if redirect_dir feature is turned off"); + static bool ovl_index_def = IS_ENABLED(CONFIG_OVERLAY_FS_INDEX); module_param_named(index, ovl_index_def, bool, 0644); MODULE_PARM_DESC(ovl_index_def, @@ -232,6 +239,7 @@ static void ovl_free_fs(struct ovl_fs *ofs) kfree(ofs->config.lowerdir); kfree(ofs->config.upperdir); kfree(ofs->config.workdir); + kfree(ofs->config.redirect_mode); if (ofs->creator_cred) put_cred(ofs->creator_cred); kfree(ofs); @@ -295,6 +303,11 @@ static bool ovl_force_readonly(struct ovl_fs *ofs) return (!ofs->upper_mnt || !ofs->workdir); } +static const char *ovl_redirect_mode_def(void) +{ + return ovl_redirect_dir_def ? "on" : "off"; +} + /** * ovl_show_options * @@ -313,12 +326,10 @@ static int ovl_show_options(struct seq_file *m, struct dentry *dentry) } if (ofs->config.default_permissions) seq_puts(m, ",default_permissions"); - if (ofs->config.redirect_dir != ovl_redirect_dir_def) - seq_printf(m, ",redirect_dir=%s", - ofs->config.redirect_dir ? "on" : "off"); + if (strcmp(ofs->config.redirect_mode, ovl_redirect_mode_def()) != 0) + seq_printf(m, ",redirect_dir=%s", ofs->config.redirect_mode); if (ofs->config.index != ovl_index_def) - seq_printf(m, ",index=%s", - ofs->config.index ? "on" : "off"); + seq_printf(m, ",index=%s", ofs->config.index ? "on" : "off"); return 0; } @@ -348,8 +359,7 @@ enum { OPT_UPPERDIR, OPT_WORKDIR, OPT_DEFAULT_PERMISSIONS, - OPT_REDIRECT_DIR_ON, - OPT_REDIRECT_DIR_OFF, + OPT_REDIRECT_DIR, OPT_INDEX_ON, OPT_INDEX_OFF, OPT_ERR, @@ -360,8 +370,7 @@ static const match_table_t ovl_tokens = { {OPT_UPPERDIR, "upperdir=%s"}, {OPT_WORKDIR, "workdir=%s"}, {OPT_DEFAULT_PERMISSIONS, "default_permissions"}, - {OPT_REDIRECT_DIR_ON, "redirect_dir=on"}, - {OPT_REDIRECT_DIR_OFF, "redirect_dir=off"}, + {OPT_REDIRECT_DIR, "redirect_dir=%s"}, {OPT_INDEX_ON, "index=on"}, {OPT_INDEX_OFF, "index=off"}, {OPT_ERR, NULL} @@ -390,10 +399,37 @@ static char *ovl_next_opt(char **s) return sbegin; } +static int ovl_parse_redirect_mode(struct ovl_config *config, const char *mode) +{ + if (strcmp(mode, "on") == 0) { + config->redirect_dir = true; + /* + * Does not make sense to have redirect creation without + * redirect following. + */ + config->redirect_follow = true; + } else if (strcmp(mode, "follow") == 0) { + config->redirect_follow = true; + } else if (strcmp(mode, "off") == 0) { + if (ovl_redirect_always_follow) + config->redirect_follow = true; + } else if (strcmp(mode, "nofollow") != 0) { + pr_err("overlayfs: bad mount option \"redirect_dir=%s\"\n", + mode); + return -EINVAL; + } + + return 0; +} + static int ovl_parse_opt(char *opt, struct ovl_config *config) { char *p; + config->redirect_mode = kstrdup(ovl_redirect_mode_def(), GFP_KERNEL); + if (!config->redirect_mode) + return -ENOMEM; + while ((p = ovl_next_opt(&opt)) != NULL) { int token; substring_t args[MAX_OPT_ARGS]; @@ -428,12 +464,11 @@ static int ovl_parse_opt(char *opt, struct ovl_config *config) config->default_permissions = true; break; - case OPT_REDIRECT_DIR_ON: - config->redirect_dir = true; - break; - - case OPT_REDIRECT_DIR_OFF: - config->redirect_dir = false; + case OPT_REDIRECT_DIR: + kfree(config->redirect_mode); + config->redirect_mode = match_strdup(&args[0]); + if (!config->redirect_mode) + return -ENOMEM; break; case OPT_INDEX_ON: @@ -458,7 +493,7 @@ static int ovl_parse_opt(char *opt, struct ovl_config *config) config->workdir = NULL; } - return 0; + return ovl_parse_redirect_mode(config, config->redirect_mode); } #define OVL_WORKDIR_NAME "work" @@ -1160,7 +1195,6 @@ static int ovl_fill_super(struct super_block *sb, void *data, int silent) if (!cred) goto out_err; - ofs->config.redirect_dir = ovl_redirect_dir_def; ofs->config.index = ovl_index_def; err = ovl_parse_opt((char *) data, &ofs->config); if (err) -- GitLab From 08d8f8a5b094b66b29936e8751b4a818b8db1207 Mon Sep 17 00:00:00 2001 From: Vivek Goyal Date: Mon, 27 Nov 2017 10:12:44 -0500 Subject: [PATCH 1216/2547] ovl: Pass ovl_get_nlink() parameters in right order Right now we seem to be passing index as "lowerdentry" and origin.dentry as "upperdentry". IIUC, we should pass these parameters in reversed order and this looks like a bug. Signed-off-by: Vivek Goyal Acked-by: Amir Goldstein Fixes: caf70cb2ba5d ("ovl: cleanup orphan index entries") Cc: #v4.13 Signed-off-by: Miklos Szeredi --- fs/overlayfs/namei.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/overlayfs/namei.c b/fs/overlayfs/namei.c index 2a12dc2e9840..beb945e1963c 100644 --- a/fs/overlayfs/namei.c +++ b/fs/overlayfs/namei.c @@ -435,7 +435,7 @@ int ovl_verify_index(struct dentry *index, struct ovl_path *lower, /* Check if index is orphan and don't warn before cleaning it */ if (d_inode(index)->i_nlink == 1 && - ovl_get_nlink(index, origin.dentry, 0) == 0) + ovl_get_nlink(origin.dentry, index, 0) == 0) err = -ENOENT; dput(origin.dentry); -- GitLab From b02a16e6413a2f782e542ef60bad9ff6bf212f8a Mon Sep 17 00:00:00 2001 From: Amir Goldstein Date: Wed, 29 Nov 2017 07:35:21 +0200 Subject: [PATCH 1217/2547] ovl: update ctx->pos on impure dir iteration This fixes a regression with readdir of impure dir in overlayfs that is shared to VM via 9p fs. Reported-by: Miguel Bernal Marin Fixes: 4edb83bb1041 ("ovl: constant d_ino for non-merge dirs") Cc: #4.14 Signed-off-by: Amir Goldstein Tested-by: Miguel Bernal Marin Signed-off-by: Miklos Szeredi --- fs/overlayfs/readdir.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/fs/overlayfs/readdir.c b/fs/overlayfs/readdir.c index 0daa4354fec4..51088849ce97 100644 --- a/fs/overlayfs/readdir.c +++ b/fs/overlayfs/readdir.c @@ -663,7 +663,10 @@ static int ovl_iterate_real(struct file *file, struct dir_context *ctx) return PTR_ERR(rdt.cache); } - return iterate_dir(od->realfile, &rdt.ctx); + err = iterate_dir(od->realfile, &rdt.ctx); + ctx->pos = rdt.ctx.pos; + + return err; } -- GitLab From e8d4bfe3a71537284a90561f77c85dea6c154369 Mon Sep 17 00:00:00 2001 From: Chengguang Xu Date: Wed, 29 Nov 2017 10:01:32 +0800 Subject: [PATCH 1218/2547] ovl: Sync upper dirty data when syncing overlayfs When executing filesystem sync or umount on overlayfs, dirty data does not get synced as expected on upper filesystem. This patch fixes sync filesystem method to keep data consistency for overlayfs. Signed-off-by: Chengguang Xu Fixes: e593b2bf513d ("ovl: properly implement sync_filesystem()") Cc: #4.11 Signed-off-by: Miklos Szeredi --- fs/overlayfs/super.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/fs/overlayfs/super.c b/fs/overlayfs/super.c index 13a8a8617e44..76440feb79f6 100644 --- a/fs/overlayfs/super.c +++ b/fs/overlayfs/super.c @@ -252,6 +252,7 @@ static void ovl_put_super(struct super_block *sb) ovl_free_fs(ofs); } +/* Sync real dirty inodes in upper filesystem (if it exists) */ static int ovl_sync_fs(struct super_block *sb, int wait) { struct ovl_fs *ofs = sb->s_fs_info; @@ -260,14 +261,24 @@ static int ovl_sync_fs(struct super_block *sb, int wait) if (!ofs->upper_mnt) return 0; - upper_sb = ofs->upper_mnt->mnt_sb; - if (!upper_sb->s_op->sync_fs) + + /* + * If this is a sync(2) call or an emergency sync, all the super blocks + * will be iterated, including upper_sb, so no need to do anything. + * + * If this is a syncfs(2) call, then we do need to call + * sync_filesystem() on upper_sb, but enough if we do it when being + * called with wait == 1. + */ + if (!wait) return 0; - /* real inodes have already been synced by sync_filesystem(ovl_sb) */ + upper_sb = ofs->upper_mnt->mnt_sb; + down_read(&upper_sb->s_umount); - ret = upper_sb->s_op->sync_fs(upper_sb, wait); + ret = sync_filesystem(upper_sb); up_read(&upper_sb->s_umount); + return ret; } -- GitLab From 7879cb43f9a75710af439c6bd81c94de1aa3d740 Mon Sep 17 00:00:00 2001 From: Vasyl Gomonovych Date: Tue, 28 Nov 2017 00:09:23 +0100 Subject: [PATCH 1219/2547] ovl: Use PTR_ERR_OR_ZERO() Fix ptr_ret.cocci warnings: fs/overlayfs/overlayfs.h:179:11-17: WARNING: PTR_ERR_OR_ZERO can be used Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR Generated by: scripts/coccinelle/api/ptr_ret.cocci Signed-off-by: Vasyl Gomonovych Signed-off-by: Miklos Szeredi --- fs/overlayfs/overlayfs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/overlayfs/overlayfs.h b/fs/overlayfs/overlayfs.h index 13eab09a6b6f..b489099ccd49 100644 --- a/fs/overlayfs/overlayfs.h +++ b/fs/overlayfs/overlayfs.h @@ -180,7 +180,7 @@ static inline int ovl_do_whiteout(struct inode *dir, struct dentry *dentry) static inline struct dentry *ovl_do_tmpfile(struct dentry *dentry, umode_t mode) { struct dentry *ret = vfs_tmpfile(dentry, mode, 0); - int err = IS_ERR(ret) ? PTR_ERR(ret) : 0; + int err = PTR_ERR_OR_ZERO(ret); pr_debug("tmpfile(%pd2, 0%o) = %i\n", dentry, mode, err); return ret; -- GitLab From 8722e095f5a44d0e409e45c5ddc2ee9cf589c777 Mon Sep 17 00:00:00 2001 From: Vincent Pelletier Date: Thu, 30 Nov 2017 15:31:06 +0000 Subject: [PATCH 1220/2547] usb: dwc3: gadget: Wait longer for controller to end command processing DWC3_DEPCMD_ENDTRANSFER has been witnessed to require around 600 iterations before controller would become idle again after unplugging the USB cable with AIO reads submitted. Bump timeout from 500 iterations to 1000 so dwc3_stop_active_transfer does not receive -ETIMEDOUT and does not WARN: [ 81.326273] ------------[ cut here ]------------ [ 81.335341] WARNING: CPU: 0 PID: 1874 at drivers/usb/dwc3/gadget.c:2627 dwc3_stop_active_transfer.constprop.23+0x69/0xc0 [dwc3] [ 81.347094] Modules linked in: usb_f_fs libcomposite configfs bnep btsdio bluetooth ecdh_generic brcmfmac brcmutil dwc3 intel_powerclamp coretemp ulpi kvm_intel udc_core kvm irqbypass crc32_pclmul crc32c_intel pcbc dwc3_pci aesni_intel aes_i586 crypto_simd cryptd ehci_pci ehci_hcd basincove_gpadc industrialio gpio_keys usbcore usb_common [ 81.378142] CPU: 0 PID: 1874 Comm: irq/34-dwc3 Not tainted 4.14.0-edison+ #119 [ 81.385545] Hardware name: Intel Corporation Merrifield/BODEGA BAY, BIOS 542 2015.01.21:18.19.48 [ 81.394548] task: f5b1be00 task.stack: f420a000 [ 81.399219] EIP: dwc3_stop_active_transfer.constprop.23+0x69/0xc0 [dwc3] [ 81.406086] EFLAGS: 00010086 CPU: 0 [ 81.409672] EAX: 0000001f EBX: f5729800 ECX: c132a2a2 EDX: 00000000 [ 81.416096] ESI: f4054014 EDI: f41cf400 EBP: f420be10 ESP: f420bdf4 [ 81.422521] DS: 007b ES: 007b FS: 00d8 GS: 0000 SS: 0068 [ 81.428061] CR0: 80050033 CR2: b7a3f000 CR3: 01d94000 CR4: 001006d0 [ 81.434483] Call Trace: [ 81.437063] __dwc3_gadget_ep_disable+0xa3/0x2b0 [dwc3] [ 81.442438] ? _raw_spin_lock_irqsave+0x32/0x40 [ 81.447135] dwc3_gadget_ep_disable+0xbf/0xe0 [dwc3] [ 81.452269] usb_ep_disable+0x1c/0xd0 [udc_core] [ 81.457048] ffs_func_eps_disable.isra.15+0x3b/0x90 [usb_f_fs] [ 81.463070] ffs_func_set_alt+0x7d/0x310 [usb_f_fs] [ 81.468132] ffs_func_disable+0x14/0x20 [usb_f_fs] [ 81.473075] reset_config+0x5b/0x90 [libcomposite] [ 81.478023] composite_disconnect+0x2b/0x50 [libcomposite] [ 81.483685] dwc3_disconnect_gadget+0x39/0x50 [dwc3] [ 81.488808] dwc3_gadget_disconnect_interrupt+0x21b/0x250 [dwc3] [ 81.495014] dwc3_thread_interrupt+0x2a8/0xf70 [dwc3] [ 81.500219] ? __schedule+0x78c/0x7e0 [ 81.504027] irq_thread_fn+0x18/0x30 [ 81.507715] ? irq_thread+0xb7/0x180 [ 81.511400] irq_thread+0x111/0x180 [ 81.515000] ? irq_finalize_oneshot+0xe0/0xe0 [ 81.519490] ? wake_threads_waitq+0x30/0x30 [ 81.523806] kthread+0x107/0x110 [ 81.527131] ? disable_percpu_irq+0x50/0x50 [ 81.531439] ? kthread_stop+0x150/0x150 [ 81.535397] ret_from_fork+0x19/0x24 [ 81.539136] Code: 89 d8 c7 45 ec 00 00 00 00 c7 45 f0 00 00 00 00 c7 45 f4 00 00 00 00 e8 56 ef ff ff 85 c0 74 12 50 68 b9 1c 14 f8 e8 64 0f f7 c8 <0f> ff 58 5a 8d 76 00 8b 83 98 00 00 00 c6 83 a0 00 00 00 00 83 [ 81.559295] ---[ end trace f3133eec81a473b8 ]--- Number of iterations measured on 4 consecutive unplugs: [ 1088.799777] dwc3_send_gadget_ep_cmd(cmd=331016, params={0, 0, 0}) iterated 605 times [ 1222.024986] dwc3_send_gadget_ep_cmd(cmd=331016, params={0, 0, 0}) iterated 580 times [ 1317.590452] dwc3_send_gadget_ep_cmd(cmd=331016, params={0, 0, 0}) iterated 598 times [ 1453.218314] dwc3_send_gadget_ep_cmd(cmd=331016, params={0, 0, 0}) iterated 594 times Signed-off-by: Vincent Pelletier Signed-off-by: Felipe Balbi --- drivers/usb/dwc3/gadget.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 981fd986cf82..01e595bb1ff1 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -259,7 +259,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, { const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; struct dwc3 *dwc = dep->dwc; - u32 timeout = 500; + u32 timeout = 1000; u32 reg; int cmd_status = 0; -- GitLab From ded600ea9fb51a495d2fcd21e90351df876488e8 Mon Sep 17 00:00:00 2001 From: Andreas Platschek Date: Thu, 7 Dec 2017 11:32:20 +0100 Subject: [PATCH 1221/2547] usb: dwc3: of-simple: fix missing clk_disable_unprepare If of_clk_get() fails, the clean-up of already initialized clocks should be the same as when clk_prepare_enable() fails. Thus a clk_disable_unprepare() for each clock should be called before the clk_put(). Found by Linux Driver Verification project (linuxtesting.org). Fixes: 16adc674d0d6 ("usb: dwc3: ep0: fix setup_packet_pending initialization") Signed-off-by: Andreas Platschek Signed-off-by: Felipe Balbi --- drivers/usb/dwc3/dwc3-of-simple.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c index c4a4d7bd2766..762370dd7c75 100644 --- a/drivers/usb/dwc3/dwc3-of-simple.c +++ b/drivers/usb/dwc3/dwc3-of-simple.c @@ -51,8 +51,10 @@ static int dwc3_of_simple_clk_init(struct dwc3_of_simple *simple, int count) clk = of_clk_get(np, i); if (IS_ERR(clk)) { - while (--i >= 0) + while (--i >= 0) { + clk_disable_unprepare(simple->clks[i]); clk_put(simple->clks[i]); + } return PTR_ERR(clk); } -- GitLab From a0d8c4cfdf31a9576f683628e50b76714c785ef1 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 7 Dec 2017 13:40:24 +0900 Subject: [PATCH 1222/2547] usb: dwc3: of-simple: set dev_pm_ops dwc3_of_simple_dev_pm_ops has never been used since the initial support by commit 16adc674d0d6 ("usb: dwc3: add generic OF glue layer"). I guess it just missed to set .pm struct member. Signed-off-by: Masahiro Yamada Signed-off-by: Felipe Balbi --- drivers/usb/dwc3/dwc3-of-simple.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c index 762370dd7c75..7ae0eefc7cc7 100644 --- a/drivers/usb/dwc3/dwc3-of-simple.c +++ b/drivers/usb/dwc3/dwc3-of-simple.c @@ -205,6 +205,7 @@ static struct platform_driver dwc3_of_simple_driver = { .driver = { .name = "dwc3-of-simple", .of_match_table = of_dwc3_simple_match, + .pm = &dwc3_of_simple_dev_pm_ops, }, }; -- GitLab From ec5bb87e4e2a1d3a35563a7bcfac9febf67aba9d Mon Sep 17 00:00:00 2001 From: Manu Gautam Date: Wed, 6 Dec 2017 12:49:04 +0530 Subject: [PATCH 1223/2547] usb: dwc3: gadget: Fix PCM1 for ISOC EP with ep->mult less than 3 For isochronous endpoints with ep->mult less than 3, PCM1 value of trb->size in set incorrectly. For ep->mult = 2, this is set to 0/-1 and for ep->mult = 1, this is set to -2. This is because the initial mult is set to ep->mult - 1 instead of 2. Signed-off-by: Manu Gautam Signed-off-by: Felipe Balbi --- drivers/usb/dwc3/gadget.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 01e595bb1ff1..639dd1b163a0 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -912,7 +912,7 @@ static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb, */ if (speed == USB_SPEED_HIGH) { struct usb_ep *ep = &dep->endpoint; - unsigned int mult = ep->mult - 1; + unsigned int mult = 2; unsigned int maxp = usb_endpoint_maxp(ep->desc); if (length <= (2 * maxp)) -- GitLab From 9273083a1530891360e9fe4fad26ae96810db499 Mon Sep 17 00:00:00 2001 From: Minas Harutyunyan Date: Thu, 30 Nov 2017 12:16:37 +0400 Subject: [PATCH 1224/2547] usb: dwc2: Fix TxFIFOn sizes and total TxFIFO size issues In host mode reading from DPTXSIZn returning invalid value in dwc2_check_param_tx_fifo_sizes function. In total TxFIFO size calculations unnecessarily reducing by ep_info. hw->total_fifo_size can be fully allocated for FIFO's. Added num_dev_in_eps member in dwc2_hw_params structure to save number of IN EPs. Added g_tx_fifo_size array in dwc2_hw_params structure to store power on reset values of DPTXSIZn registers in forced device mode. Updated dwc2_hsotg_tx_fifo_count() function to get TxFIFO count from num_dev_in_eps. Updated dwc2_get_dev_hwparams() function to store DPTXFSIZn in g_tx_fifo_size array. dwc2_get_host/dev_hwparams() functions call moved after num_dev_in_eps set from hwcfg4. Modified dwc2_check_param_tx_fifo_sizes() function to check TxFIFOn sizes based on g_tx_fifo_size array. Removed ep_info subtraction during calculation of tx_addr_max in dwc2_hsotg_tx_fifo_total_depth() function. Also removed dwc2_hsotg_ep_info_size() function as no more need. Acked-by: John Youn Signed-off-by: Gevorg Sahakyan Signed-off-by: Minas Harutyunyan Signed-off-by: Felipe Balbi --- drivers/usb/dwc2/core.h | 4 ++++ drivers/usb/dwc2/gadget.c | 42 ++------------------------------------- drivers/usb/dwc2/params.c | 29 +++++++++++++++++---------- 3 files changed, 25 insertions(+), 50 deletions(-) diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h index f66c94130cac..31749c79045f 100644 --- a/drivers/usb/dwc2/core.h +++ b/drivers/usb/dwc2/core.h @@ -537,6 +537,7 @@ struct dwc2_core_params { * 2 - Internal DMA * @power_optimized Are power optimizations enabled? * @num_dev_ep Number of device endpoints available + * @num_dev_in_eps Number of device IN endpoints available * @num_dev_perio_in_ep Number of device periodic IN endpoints * available * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue @@ -565,6 +566,7 @@ struct dwc2_core_params { * 2 - 8 or 16 bits * @snpsid: Value from SNPSID register * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) + * @g_tx_fifo_size[] Power-on values of TxFIFO sizes */ struct dwc2_hw_params { unsigned op_mode:3; @@ -586,12 +588,14 @@ struct dwc2_hw_params { unsigned fs_phy_type:2; unsigned i2c_enable:1; unsigned num_dev_ep:4; + unsigned num_dev_in_eps : 4; unsigned num_dev_perio_in_ep:4; unsigned total_fifo_size:16; unsigned power_optimized:1; unsigned utmi_phy_data_width:2; u32 snpsid; u32 dev_ep_dirs; + u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; }; /* Size of control and EP0 buffers */ diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c index 88529d092503..e4c3ce0de5de 100644 --- a/drivers/usb/dwc2/gadget.c +++ b/drivers/usb/dwc2/gadget.c @@ -195,55 +195,18 @@ int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) { if (hsotg->hw_params.en_multiple_tx_fifo) /* In dedicated FIFO mode we need count of IN EPs */ - return (dwc2_readl(hsotg->regs + GHWCFG4) & - GHWCFG4_NUM_IN_EPS_MASK) >> GHWCFG4_NUM_IN_EPS_SHIFT; + return hsotg->hw_params.num_dev_in_eps; else /* In shared FIFO mode we need count of Periodic IN EPs */ return hsotg->hw_params.num_dev_perio_in_ep; } -/** - * dwc2_hsotg_ep_info_size - return Endpoint Info Control block size in DWORDs - */ -static int dwc2_hsotg_ep_info_size(struct dwc2_hsotg *hsotg) -{ - int val = 0; - int i; - u32 ep_dirs; - - /* - * Don't need additional space for ep info control registers in - * slave mode. - */ - if (!using_dma(hsotg)) { - dev_dbg(hsotg->dev, "Buffer DMA ep info size 0\n"); - return 0; - } - - /* - * Buffer DMA mode - 1 location per endpoit - * Descriptor DMA mode - 4 locations per endpoint - */ - ep_dirs = hsotg->hw_params.dev_ep_dirs; - - for (i = 0; i <= hsotg->hw_params.num_dev_ep; i++) { - val += ep_dirs & 3 ? 1 : 2; - ep_dirs >>= 2; - } - - if (using_desc_dma(hsotg)) - val = val * 4; - - return val; -} - /** * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for * device mode TX FIFOs */ int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) { - int ep_info_size; int addr; int tx_addr_max; u32 np_tx_fifo_size; @@ -252,8 +215,7 @@ int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) hsotg->params.g_np_tx_fifo_size); /* Get Endpoint Info Control block size in DWORDs. */ - ep_info_size = dwc2_hsotg_ep_info_size(hsotg); - tx_addr_max = hsotg->hw_params.total_fifo_size - ep_info_size; + tx_addr_max = hsotg->hw_params.total_fifo_size; addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; if (tx_addr_max <= addr) diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c index ef73af6e03a9..03fd20f0b496 100644 --- a/drivers/usb/dwc2/params.c +++ b/drivers/usb/dwc2/params.c @@ -484,8 +484,7 @@ static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) } for (fifo = 1; fifo <= fifo_count; fifo++) { - dptxfszn = (dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)) & - FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; + dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; if (hsotg->params.g_tx_fifo_size[fifo] < min || hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { @@ -609,6 +608,7 @@ static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) struct dwc2_hw_params *hw = &hsotg->hw_params; bool forced; u32 gnptxfsiz; + int fifo, fifo_count; if (hsotg->dr_mode == USB_DR_MODE_HOST) return; @@ -617,6 +617,14 @@ static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); + fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); + + for (fifo = 1; fifo <= fifo_count; fifo++) { + hw->g_tx_fifo_size[fifo] = + (dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)) & + FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; + } + if (forced) dwc2_clear_force_mode(hsotg); @@ -661,14 +669,6 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); - /* - * Host specific hardware parameters. Reading these parameters - * requires the controller to be in host mode. The mode will - * be forced, if necessary, to read these values. - */ - dwc2_get_host_hwparams(hsotg); - dwc2_get_dev_hwparams(hsotg); - /* hwcfg1 */ hw->dev_ep_dirs = hwcfg1; @@ -711,6 +711,8 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; + hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> + GHWCFG4_NUM_IN_EPS_SHIFT; hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> @@ -719,6 +721,13 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) /* fifo sizes */ hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> GRXFSIZ_DEPTH_SHIFT; + /* + * Host specific hardware parameters. Reading these parameters + * requires the controller to be in host mode. The mode will + * be forced, if necessary, to read these values. + */ + dwc2_get_host_hwparams(hsotg); + dwc2_get_dev_hwparams(hsotg); return 0; } -- GitLab From 8516673a996870ea0ceb337ee4f83c33c5ec3111 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 8 Dec 2017 21:46:16 +0000 Subject: [PATCH 1225/2547] agp/intel: Flush all chipset writes after updating the GGTT Before accessing the GGTT we must flush the PTE writes and make them visible to the chipset, or else the indirect access may end up in the wrong page. In commit 3497971a71d8 ("agp/intel: Flush chipset writes after updating a single PTE"), we noticed corruption of the uploads for pwrite and for capturing GPU error states, but it was presumed that the explicit calls to intel_gtt_chipset_flush() were sufficient for the execbuffer path. However, we have not been flushing the chipset between the PTE writes and access via the GTT itself. For simplicity, do the flush after any PTE update rather than try and batch the flushes on a just-in-time basis. References: 3497971a71d8 ("agp/intel: Flush chipset writes after updating a single PTE") Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Mika Kuoppala Cc: drm-intel-fixes@lists.freedesktop.org Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171208214616.30147-1-chris@chris-wilson.co.uk --- drivers/char/agp/intel-gtt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 9b6b6023193b..dde7caac7f9f 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -872,6 +872,8 @@ void intel_gtt_insert_sg_entries(struct sg_table *st, } } wmb(); + if (intel_private.driver->chipset_flush) + intel_private.driver->chipset_flush(); } EXPORT_SYMBOL(intel_gtt_insert_sg_entries); -- GitLab From 19553d57dcddf659133739cd073bf2049f2b0ea9 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 9 Dec 2017 21:08:35 +0000 Subject: [PATCH 1226/2547] drm/i915/selftests: Free mock_i915->drm.mode_config Even for the mock i915 device, we need to initialise the drm.mode_config, as we may ultimately query whether there are any KMS users deep in the bowels of some paths (e.g. eviction). As we initialise drm.mode_config we must cleanup after ourselves! Signed-off-by: Chris Wilson Cc: Matthew Auld Cc: Joonas Lahtinen Reviewed-by: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20171209210835.32609-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/selftests/mock_gem_device.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 80f152aaedf9..1bc61f3f76fc 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -85,6 +85,8 @@ static void mock_device_release(struct drm_device *dev) i915_gemfs_fini(i915); + drm_mode_config_cleanup(&i915->drm); + drm_dev_fini(&i915->drm); put_device(&i915->drm.pdev->dev); } @@ -187,7 +189,7 @@ struct drm_i915_private *mock_gem_device(void) i915->wq = alloc_ordered_workqueue("mock", 0); if (!i915->wq) - goto put_device; + goto err_drv; mock_init_contexts(i915); @@ -266,6 +268,9 @@ struct drm_i915_private *mock_gem_device(void) kmem_cache_destroy(i915->objects); err_wq: destroy_workqueue(i915->wq); +err_drv: + drm_mode_config_cleanup(&i915->drm); + drm_dev_fini(&i915->drm); put_device: put_device(&pdev->dev); err: -- GitLab From 2b4f27c36bcd46e820ddb9a8e6fe6a63fa4250b8 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Wed, 29 Nov 2017 01:18:57 -0800 Subject: [PATCH 1227/2547] crypto: skcipher - set walk.iv for zero-length inputs All the ChaCha20 algorithms as well as the ARM bit-sliced AES-XTS algorithms call skcipher_walk_virt(), then access the IV (walk.iv) before checking whether any bytes need to be processed (walk.nbytes). But if the input is empty, then skcipher_walk_virt() doesn't set the IV, and the algorithms crash trying to use the uninitialized IV pointer. Fix it by setting the IV earlier in skcipher_walk_virt(). Also fix it for the AEAD walk functions. This isn't a perfect solution because we can't actually align the IV to ->cra_alignmask unless there are bytes to process, for one because the temporary buffer for the aligned IV is freed by skcipher_walk_done(), which is only called when there are bytes to process. Thus, algorithms that require aligned IVs will still need to avoid accessing the IV when walk.nbytes == 0. Still, many algorithms/architectures are fine with IVs having any alignment, and even for those that aren't, a misaligned pointer bug is much less severe than an uninitialized pointer bug. This change also matches the behavior of the older blkcipher_walk API. Fixes: 0cabf2af6f5a ("crypto: skcipher - Fix crash on zero-length input") Reported-by: syzbot Cc: # v4.14+ Signed-off-by: Eric Biggers Signed-off-by: Herbert Xu --- crypto/skcipher.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/crypto/skcipher.c b/crypto/skcipher.c index 778e0ff42bfa..11af5fd6a443 100644 --- a/crypto/skcipher.c +++ b/crypto/skcipher.c @@ -449,6 +449,8 @@ static int skcipher_walk_skcipher(struct skcipher_walk *walk, walk->total = req->cryptlen; walk->nbytes = 0; + walk->iv = req->iv; + walk->oiv = req->iv; if (unlikely(!walk->total)) return 0; @@ -456,9 +458,6 @@ static int skcipher_walk_skcipher(struct skcipher_walk *walk, scatterwalk_start(&walk->in, req->src); scatterwalk_start(&walk->out, req->dst); - walk->iv = req->iv; - walk->oiv = req->iv; - walk->flags &= ~SKCIPHER_WALK_SLEEP; walk->flags |= req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? SKCIPHER_WALK_SLEEP : 0; @@ -510,6 +509,8 @@ static int skcipher_walk_aead_common(struct skcipher_walk *walk, int err; walk->nbytes = 0; + walk->iv = req->iv; + walk->oiv = req->iv; if (unlikely(!walk->total)) return 0; @@ -525,9 +526,6 @@ static int skcipher_walk_aead_common(struct skcipher_walk *walk, scatterwalk_done(&walk->in, 0, walk->total); scatterwalk_done(&walk->out, 0, walk->total); - walk->iv = req->iv; - walk->oiv = req->iv; - if (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) walk->flags |= SKCIPHER_WALK_SLEEP; else -- GitLab From 11edb555966ed2c66c533d17c604f9d7e580a829 Mon Sep 17 00:00:00 2001 From: Stephan Mueller Date: Wed, 29 Nov 2017 12:02:23 +0100 Subject: [PATCH 1228/2547] crypto: af_alg - wait for data at beginning of recvmsg The wait for data is a non-atomic operation that can sleep and therefore potentially release the socket lock. The release of the socket lock allows another thread to modify the context data structure. The waiting operation for new data therefore must be called at the beginning of recvmsg. This prevents a race condition where checks of the members of the context data structure are performed by recvmsg while there is a potential for modification of these values. Fixes: e870456d8e7c ("crypto: algif_skcipher - overhaul memory management") Fixes: d887c52d6ae4 ("crypto: algif_aead - overhaul memory management") Reported-by: syzbot Cc: # v4.14+ Signed-off-by: Stephan Mueller Signed-off-by: Herbert Xu --- crypto/af_alg.c | 6 ------ crypto/algif_aead.c | 6 ++++++ crypto/algif_skcipher.c | 6 ++++++ 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/crypto/af_alg.c b/crypto/af_alg.c index 358749c38894..f1a2caf1b59b 100644 --- a/crypto/af_alg.c +++ b/crypto/af_alg.c @@ -1137,12 +1137,6 @@ int af_alg_get_rsgl(struct sock *sk, struct msghdr *msg, int flags, if (!af_alg_readable(sk)) break; - if (!ctx->used) { - err = af_alg_wait_for_data(sk, flags); - if (err) - return err; - } - seglen = min_t(size_t, (maxsize - len), msg_data_left(msg)); diff --git a/crypto/algif_aead.c b/crypto/algif_aead.c index 805f485ddf1b..c8a32bef208a 100644 --- a/crypto/algif_aead.c +++ b/crypto/algif_aead.c @@ -111,6 +111,12 @@ static int _aead_recvmsg(struct socket *sock, struct msghdr *msg, size_t usedpages = 0; /* [in] RX bufs to be used from user */ size_t processed = 0; /* [in] TX bufs to be consumed */ + if (!ctx->used) { + err = af_alg_wait_for_data(sk, flags); + if (err) + return err; + } + /* * Data length provided by caller via sendmsg/sendpage that has not * yet been processed. diff --git a/crypto/algif_skcipher.c b/crypto/algif_skcipher.c index 30cff827dd8f..6fb595cd63ac 100644 --- a/crypto/algif_skcipher.c +++ b/crypto/algif_skcipher.c @@ -72,6 +72,12 @@ static int _skcipher_recvmsg(struct socket *sock, struct msghdr *msg, int err = 0; size_t len = 0; + if (!ctx->used) { + err = af_alg_wait_for_data(sk, flags); + if (err) + return err; + } + /* Allocate cipher request for current operation. */ areq = af_alg_alloc_areq(sk, sizeof(struct af_alg_async_req) + crypto_skcipher_reqsize(tfm)); -- GitLab From 9abffc6f2efe46c3564c04312e52e07622d40e51 Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Thu, 30 Nov 2017 13:39:27 +0100 Subject: [PATCH 1229/2547] crypto: mcryptd - protect the per-CPU queue with a lock mcryptd_enqueue_request() grabs the per-CPU queue struct and protects access to it with disabled preemption. Then it schedules a worker on the same CPU. The worker in mcryptd_queue_worker() guards access to the same per-CPU variable with disabled preemption. If we take CPU-hotplug into account then it is possible that between queue_work_on() and the actual invocation of the worker the CPU goes down and the worker will be scheduled on _another_ CPU. And here the preempt_disable() protection does not work anymore. The easiest thing is to add a spin_lock() to guard access to the list. Another detail: mcryptd_queue_worker() is not processing more than MCRYPTD_BATCH invocation in a row. If there are still items left, then it will invoke queue_work() to proceed with more later. *I* would suggest to simply drop that check because it does not use a system workqueue and the workqueue is already marked as "CPU_INTENSIVE". And if preemption is required then the scheduler should do it. However if queue_work() is used then the work item is marked as CPU unbound. That means it will try to run on the local CPU but it may run on another CPU as well. Especially with CONFIG_DEBUG_WQ_FORCE_RR_CPU=y. Again, the preempt_disable() won't work here but lock which was introduced will help. In order to keep work-item on the local CPU (and avoid RR) I changed it to queue_work_on(). Cc: stable@vger.kernel.org Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Herbert Xu --- crypto/mcryptd.c | 23 ++++++++++------------- include/crypto/mcryptd.h | 1 + 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/crypto/mcryptd.c b/crypto/mcryptd.c index 4e6472658852..eca04d3729b3 100644 --- a/crypto/mcryptd.c +++ b/crypto/mcryptd.c @@ -81,6 +81,7 @@ static int mcryptd_init_queue(struct mcryptd_queue *queue, pr_debug("cpu_queue #%d %p\n", cpu, queue->cpu_queue); crypto_init_queue(&cpu_queue->queue, max_cpu_qlen); INIT_WORK(&cpu_queue->work, mcryptd_queue_worker); + spin_lock_init(&cpu_queue->q_lock); } return 0; } @@ -104,15 +105,16 @@ static int mcryptd_enqueue_request(struct mcryptd_queue *queue, int cpu, err; struct mcryptd_cpu_queue *cpu_queue; - cpu = get_cpu(); - cpu_queue = this_cpu_ptr(queue->cpu_queue); - rctx->tag.cpu = cpu; + cpu_queue = raw_cpu_ptr(queue->cpu_queue); + spin_lock(&cpu_queue->q_lock); + cpu = smp_processor_id(); + rctx->tag.cpu = smp_processor_id(); err = crypto_enqueue_request(&cpu_queue->queue, request); pr_debug("enqueue request: cpu %d cpu_queue %p request %p\n", cpu, cpu_queue, request); + spin_unlock(&cpu_queue->q_lock); queue_work_on(cpu, kcrypto_wq, &cpu_queue->work); - put_cpu(); return err; } @@ -161,16 +163,11 @@ static void mcryptd_queue_worker(struct work_struct *work) cpu_queue = container_of(work, struct mcryptd_cpu_queue, work); i = 0; while (i < MCRYPTD_BATCH || single_task_running()) { - /* - * preempt_disable/enable is used to prevent - * being preempted by mcryptd_enqueue_request() - */ - local_bh_disable(); - preempt_disable(); + + spin_lock_bh(&cpu_queue->q_lock); backlog = crypto_get_backlog(&cpu_queue->queue); req = crypto_dequeue_request(&cpu_queue->queue); - preempt_enable(); - local_bh_enable(); + spin_unlock_bh(&cpu_queue->q_lock); if (!req) { mcryptd_opportunistic_flush(); @@ -185,7 +182,7 @@ static void mcryptd_queue_worker(struct work_struct *work) ++i; } if (cpu_queue->queue.qlen) - queue_work(kcrypto_wq, &cpu_queue->work); + queue_work_on(smp_processor_id(), kcrypto_wq, &cpu_queue->work); } void mcryptd_flusher(struct work_struct *__work) diff --git a/include/crypto/mcryptd.h b/include/crypto/mcryptd.h index cceafa01f907..b67404fc4b34 100644 --- a/include/crypto/mcryptd.h +++ b/include/crypto/mcryptd.h @@ -27,6 +27,7 @@ static inline struct mcryptd_ahash *__mcryptd_ahash_cast( struct mcryptd_cpu_queue { struct crypto_queue queue; + spinlock_t q_lock; struct work_struct work; }; -- GitLab From d53c5135792319e095bb126bc43b2ee98586f7fe Mon Sep 17 00:00:00 2001 From: Stephan Mueller Date: Fri, 8 Dec 2017 11:50:37 +0100 Subject: [PATCH 1230/2547] crypto: af_alg - fix race accessing cipher request When invoking an asynchronous cipher operation, the invocation of the callback may be performed before the subsequent operations in the initial code path are invoked. The callback deletes the cipher request data structure which implies that after the invocation of the asynchronous cipher operation, this data structure must not be accessed any more. The setting of the return code size with the request data structure must therefore be moved before the invocation of the asynchronous cipher operation. Fixes: e870456d8e7c ("crypto: algif_skcipher - overhaul memory management") Fixes: d887c52d6ae4 ("crypto: algif_aead - overhaul memory management") Reported-by: syzbot Cc: # v4.14+ Signed-off-by: Stephan Mueller Acked-by: Jonathan Cameron Signed-off-by: Herbert Xu --- crypto/algif_aead.c | 10 +++++----- crypto/algif_skcipher.c | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/crypto/algif_aead.c b/crypto/algif_aead.c index c8a32bef208a..b73db2b27656 100644 --- a/crypto/algif_aead.c +++ b/crypto/algif_aead.c @@ -291,6 +291,10 @@ static int _aead_recvmsg(struct socket *sock, struct msghdr *msg, /* AIO operation */ sock_hold(sk); areq->iocb = msg->msg_iocb; + + /* Remember output size that will be generated. */ + areq->outlen = outlen; + aead_request_set_callback(&areq->cra_u.aead_req, CRYPTO_TFM_REQ_MAY_BACKLOG, af_alg_async_cb, areq); @@ -298,12 +302,8 @@ static int _aead_recvmsg(struct socket *sock, struct msghdr *msg, crypto_aead_decrypt(&areq->cra_u.aead_req); /* AIO operation in progress */ - if (err == -EINPROGRESS || err == -EBUSY) { - /* Remember output size that will be generated. */ - areq->outlen = outlen; - + if (err == -EINPROGRESS || err == -EBUSY) return -EIOCBQUEUED; - } sock_put(sk); } else { diff --git a/crypto/algif_skcipher.c b/crypto/algif_skcipher.c index 6fb595cd63ac..baef9bfccdda 100644 --- a/crypto/algif_skcipher.c +++ b/crypto/algif_skcipher.c @@ -125,6 +125,10 @@ static int _skcipher_recvmsg(struct socket *sock, struct msghdr *msg, /* AIO operation */ sock_hold(sk); areq->iocb = msg->msg_iocb; + + /* Remember output size that will be generated. */ + areq->outlen = len; + skcipher_request_set_callback(&areq->cra_u.skcipher_req, CRYPTO_TFM_REQ_MAY_SLEEP, af_alg_async_cb, areq); @@ -133,12 +137,8 @@ static int _skcipher_recvmsg(struct socket *sock, struct msghdr *msg, crypto_skcipher_decrypt(&areq->cra_u.skcipher_req); /* AIO operation in progress */ - if (err == -EINPROGRESS || err == -EBUSY) { - /* Remember output size that will be generated. */ - areq->outlen = len; - + if (err == -EINPROGRESS || err == -EBUSY) return -EIOCBQUEUED; - } sock_put(sk); } else { -- GitLab From 4564b187c16327045d87596e8980c65ba7b84c50 Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Mon, 11 Dec 2017 12:33:47 +0100 Subject: [PATCH 1231/2547] nl80211: fix nl80211_send_iface() error paths Evidently I introduced a locking bug in my change here, the nla_put_failure sometimes needs to unlock. Fix it. Fixes: 44905265bc15 ("nl80211: don't expose wdev->ssid for most interfaces") Signed-off-by: Johannes Berg --- net/wireless/nl80211.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c index b1ac23ca20c8..213d0c498c97 100644 --- a/net/wireless/nl80211.c +++ b/net/wireless/nl80211.c @@ -2610,7 +2610,7 @@ static int nl80211_send_iface(struct sk_buff *msg, u32 portid, u32 seq, int flag case NL80211_IFTYPE_AP: if (wdev->ssid_len && nla_put(msg, NL80211_ATTR_SSID, wdev->ssid_len, wdev->ssid)) - goto nla_put_failure; + goto nla_put_failure_locked; break; case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_P2P_CLIENT: @@ -2623,7 +2623,7 @@ static int nl80211_send_iface(struct sk_buff *msg, u32 portid, u32 seq, int flag if (!ssid_ie) break; if (nla_put(msg, NL80211_ATTR_SSID, ssid_ie[1], ssid_ie + 2)) - goto nla_put_failure; + goto nla_put_failure_locked; break; } default: @@ -2635,6 +2635,8 @@ static int nl80211_send_iface(struct sk_buff *msg, u32 portid, u32 seq, int flag genlmsg_end(msg, hdr); return 0; + nla_put_failure_locked: + wdev_unlock(wdev); nla_put_failure: genlmsg_cancel(msg, hdr); return -EMSGSIZE; -- GitLab From 91516a2a4734614d62ee3ed921f8f88acc67c000 Mon Sep 17 00:00:00 2001 From: Christoph Fritz Date: Sat, 9 Dec 2017 23:47:55 +0100 Subject: [PATCH 1232/2547] mmc: core: apply NO_CMD23 quirk to some specific cards To get an usdhc Apacer and some ATP SD cards work reliable, CMD23 needs to be disabled. This has been tested on i.MX6 (sdhci-esdhc) and rk3288 (dw_mmc-rockchip). Without this patch on i.MX6 (sdhci-esdhc): $ dd if=/dev/urandom of=/mnt/test bs=1M count=10 conv=fsync | | mmc0: starting CMD25 arg 00a71f00 flags 000000b5 | mmc0: blksz 512 blocks 1024 flags 00000100 tsac 3000 ms nsac 0 | mmc0: CMD12 arg 00000000 flags 0000049d | sdhci [sdhci_irq()]: *** mmc0 got interrupt: 0x00000001 | mmc0: Timeout waiting for hardware interrupt. Without this patch on rk3288 (dw_mmc-rockchip): | mmc1: Card stuck in programming state! mmcblk1 card_busy_detect | dwmmc_rockchip ff0c0000.dwmmc: Busy; trying anyway | mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, | actual 400000HZ div = 0) | mmc1: card never left busy state | mmc1: tried to reset card, got error -110 | blk_update_request: I/O error, dev mmcblk1, sector 139778 | Buffer I/O error on dev mmcblk1p1, logical block 131586, lost async | page write Signed-off-by: Christoph Fritz Cc: # v4.14+ Signed-off-by: Ulf Hansson --- drivers/mmc/core/card.h | 2 ++ drivers/mmc/core/quirks.h | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/mmc/core/card.h b/drivers/mmc/core/card.h index f06cd91964ce..79a5b985ccf5 100644 --- a/drivers/mmc/core/card.h +++ b/drivers/mmc/core/card.h @@ -75,9 +75,11 @@ struct mmc_fixup { #define EXT_CSD_REV_ANY (-1u) #define CID_MANFID_SANDISK 0x2 +#define CID_MANFID_ATP 0x9 #define CID_MANFID_TOSHIBA 0x11 #define CID_MANFID_MICRON 0x13 #define CID_MANFID_SAMSUNG 0x15 +#define CID_MANFID_APACER 0x27 #define CID_MANFID_KINGSTON 0x70 #define CID_MANFID_HYNIX 0x90 diff --git a/drivers/mmc/core/quirks.h b/drivers/mmc/core/quirks.h index f664e9cbc9f8..75d317623852 100644 --- a/drivers/mmc/core/quirks.h +++ b/drivers/mmc/core/quirks.h @@ -52,6 +52,14 @@ static const struct mmc_fixup mmc_blk_fixups[] = { MMC_FIXUP("MMC32G", CID_MANFID_TOSHIBA, CID_OEMID_ANY, add_quirk_mmc, MMC_QUIRK_BLK_NO_CMD23), + /* + * Some SD cards lockup while using CMD23 multiblock transfers. + */ + MMC_FIXUP("AF SD", CID_MANFID_ATP, CID_OEMID_ANY, add_quirk_sd, + MMC_QUIRK_BLK_NO_CMD23), + MMC_FIXUP("APUSD", CID_MANFID_APACER, 0x5048, add_quirk_sd, + MMC_QUIRK_BLK_NO_CMD23), + /* * Some MMC cards need longer data read timeout than indicated in CSD. */ -- GitLab From f5b5702ac55b11113a94d6228d191c7f827b7a3b Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Mon, 11 Dec 2017 10:14:27 +0100 Subject: [PATCH 1233/2547] netfilter: exthdr: add missign attributes to policy Add missing netlink attribute policy. Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nft_exthdr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/netfilter/nft_exthdr.c b/net/netfilter/nft_exthdr.c index a0a93d987a3b..47ec1046ad11 100644 --- a/net/netfilter/nft_exthdr.c +++ b/net/netfilter/nft_exthdr.c @@ -214,6 +214,8 @@ static const struct nla_policy nft_exthdr_policy[NFTA_EXTHDR_MAX + 1] = { [NFTA_EXTHDR_OFFSET] = { .type = NLA_U32 }, [NFTA_EXTHDR_LEN] = { .type = NLA_U32 }, [NFTA_EXTHDR_FLAGS] = { .type = NLA_U32 }, + [NFTA_EXTHDR_OP] = { .type = NLA_U32 }, + [NFTA_EXTHDR_SREG] = { .type = NLA_U32 }, }; static int nft_exthdr_init(const struct nft_ctx *ctx, -- GitLab From 3487972d7fa6c5143951436ada5933dcf0ec659d Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Thu, 7 Dec 2017 02:41:18 +0100 Subject: [PATCH 1234/2547] PM / sleep: Avoid excess pm_runtime_enable() calls in device_resume() Middle-layer code doing suspend-time optimizations for devices with the DPM_FLAG_SMART_SUSPEND flag set (currently, the PCI bus type and the ACPI PM domain) needs to make the core skip ->thaw_early and ->thaw callbacks for those devices in some cases and it sets the power.direct_complete flag for them for this purpose. However, it turns out that setting power.direct_complete outside of the PM core is a bad idea as it triggers an excess invocation of pm_runtime_enable() in device_resume(). For this reason, provide a helper to clear power.is_late_suspended and power.is_suspended to be invoked by the middle-layer code in question instead of setting power.direct_complete and make that code call the new helper. Fixes: c4b65157aeef (PCI / PM: Take SMART_SUSPEND driver flag into account) Fixes: 05087360fd7a (ACPI / PM: Take SMART_SUSPEND driver flag into account) Signed-off-by: Rafael J. Wysocki Reviewed-by: Ulf Hansson Acked-by: Bjorn Helgaas --- drivers/acpi/device_pm.c | 2 +- drivers/base/power/main.c | 15 +++++++++++++++ drivers/pci/pci-driver.c | 2 +- include/linux/pm.h | 1 + 4 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c index e4ffaeec9ec2..a4c8ad98560d 100644 --- a/drivers/acpi/device_pm.c +++ b/drivers/acpi/device_pm.c @@ -1138,7 +1138,7 @@ int acpi_subsys_thaw_noirq(struct device *dev) * skip all of the subsequent "thaw" callbacks for the device. */ if (dev_pm_smart_suspend_and_suspended(dev)) { - dev->power.direct_complete = true; + dev_pm_skip_next_resume_phases(dev); return 0; } diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c index db2f04415927..08744b572af6 100644 --- a/drivers/base/power/main.c +++ b/drivers/base/power/main.c @@ -525,6 +525,21 @@ static void dpm_watchdog_clear(struct dpm_watchdog *wd) /*------------------------- Resume routines -------------------------*/ +/** + * dev_pm_skip_next_resume_phases - Skip next system resume phases for device. + * @dev: Target device. + * + * Make the core skip the "early resume" and "resume" phases for @dev. + * + * This function can be called by middle-layer code during the "noirq" phase of + * system resume if necessary, but not by device drivers. + */ +void dev_pm_skip_next_resume_phases(struct device *dev) +{ + dev->power.is_late_suspended = false; + dev->power.is_suspended = false; +} + /** * device_resume_noirq - Execute a "noirq resume" callback for given device. * @dev: Device to handle. diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 7f47bb72bf30..945099d49f8f 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -999,7 +999,7 @@ static int pci_pm_thaw_noirq(struct device *dev) * the subsequent "thaw" callbacks for the device. */ if (dev_pm_smart_suspend_and_suspended(dev)) { - dev->power.direct_complete = true; + dev_pm_skip_next_resume_phases(dev); return 0; } diff --git a/include/linux/pm.h b/include/linux/pm.h index 65d39115f06d..492ed473ba7e 100644 --- a/include/linux/pm.h +++ b/include/linux/pm.h @@ -765,6 +765,7 @@ extern int pm_generic_poweroff_late(struct device *dev); extern int pm_generic_poweroff(struct device *dev); extern void pm_generic_complete(struct device *dev); +extern void dev_pm_skip_next_resume_phases(struct device *dev); extern bool dev_pm_smart_suspend_and_suspended(struct device *dev); #else /* !CONFIG_PM_SLEEP */ -- GitLab From 1ac8aa8d0568606485451ea860a6c6c3fad0d42d Mon Sep 17 00:00:00 2001 From: Corey Minyard Date: Thu, 30 Nov 2017 11:06:15 -0600 Subject: [PATCH 1235/2547] ipmi_si: Fix oops with PCI devices When the IPMI PCI code was split out, some code was consolidated for setting the io_setup field in the io structure. The PCI code needed this set before registration to probe register spacing, though, so restore the old code for that function. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=197999 Signed-off-by: Corey Minyard Tested-by: Meelis Roos --- drivers/char/ipmi/ipmi_si_pci.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/char/ipmi/ipmi_si_pci.c b/drivers/char/ipmi/ipmi_si_pci.c index 99771f5cad07..27dd11c49d21 100644 --- a/drivers/char/ipmi/ipmi_si_pci.c +++ b/drivers/char/ipmi/ipmi_si_pci.c @@ -103,10 +103,13 @@ static int ipmi_pci_probe(struct pci_dev *pdev, io.addr_source_cleanup = ipmi_pci_cleanup; io.addr_source_data = pdev; - if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) + if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) { io.addr_type = IPMI_IO_ADDR_SPACE; - else + io.io_setup = ipmi_si_port_setup; + } else { io.addr_type = IPMI_MEM_ADDR_SPACE; + io.io_setup = ipmi_si_mem_setup; + } io.addr_data = pci_resource_start(pdev, 0); io.regspacing = ipmi_pci_probe_regspacing(&io); -- GitLab From 51614b26a029515dd3bc43a8c0e16a9ee51bbf52 Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Wed, 6 Dec 2017 04:25:44 -0500 Subject: [PATCH 1236/2547] ipmi_si: fix crash on parisc This patch fixes ipmi crash on parisc introduced in the kernel 4.15-rc. The pointer io.io_setup is not initialized and thus it causes crash in try_smi_init when attempting to call new_smi->io.io_setup. Signed-off-by: Mikulas Patocka Signed-off-by: Corey Minyard --- drivers/char/ipmi/ipmi_si_parisc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/char/ipmi/ipmi_si_parisc.c b/drivers/char/ipmi/ipmi_si_parisc.c index 090b073ab441..6b10f0e18a95 100644 --- a/drivers/char/ipmi/ipmi_si_parisc.c +++ b/drivers/char/ipmi/ipmi_si_parisc.c @@ -10,6 +10,8 @@ static int __init ipmi_parisc_probe(struct parisc_device *dev) { struct si_sm_io io; + memset(&io, 0, sizeof(io)); + io.si_type = SI_KCS; io.addr_source = SI_DEVICETREE; io.addr_type = IPMI_MEM_ADDR_SPACE; -- GitLab From 7f6f60a1ba52538c16f26930bfbcfe193d9d746a Mon Sep 17 00:00:00 2001 From: Dave Young Date: Sat, 9 Dec 2017 12:16:10 +0800 Subject: [PATCH 1237/2547] mm/early_ioremap: Fix boot hang with earlyprintk=efi,keep earlyprintk=efi,keep does not work any more with a warning in mm/early_ioremap.c: WARN_ON(system_state != SYSTEM_BOOTING): Boot just hangs because of the earlyprintk within the earlyprintk implementation code itself. This is caused by a new introduced middle state in: 69a78ff226fe ("init: Introduce SYSTEM_SCHEDULING state") early_ioremap() is fine in both SYSTEM_BOOTING and SYSTEM_SCHEDULING states, original condition should be updated accordingly. Signed-off-by: Dave Young Acked-by: Thomas Gleixner Cc: Linus Torvalds Cc: Peter Zijlstra Cc: bp@suse.de Cc: linux-efi@vger.kernel.org Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/20171209041610.GA3249@dhcp-128-65.nay.redhat.com Signed-off-by: Ingo Molnar --- mm/early_ioremap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mm/early_ioremap.c b/mm/early_ioremap.c index d04ac1ec0559..1826f191e72c 100644 --- a/mm/early_ioremap.c +++ b/mm/early_ioremap.c @@ -111,7 +111,7 @@ __early_ioremap(resource_size_t phys_addr, unsigned long size, pgprot_t prot) enum fixed_addresses idx; int i, slot; - WARN_ON(system_state != SYSTEM_BOOTING); + WARN_ON(system_state >= SYSTEM_RUNNING); slot = -1; for (i = 0; i < FIX_BTMAPS_SLOTS; i++) { -- GitLab From 6d60ce384d1d5ca32b595244db4077a419acc687 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Mon, 27 Nov 2017 08:51:39 +0100 Subject: [PATCH 1238/2547] x86/mm/kmmio: Fix mmiotrace for page unaligned addresses If something calls ioremap() with an address not aligned to PAGE_SIZE, the returned address might be not aligned as well. This led to a probe registered on exactly the returned address, but the entire page was armed for mmiotracing. On calling iounmap() the address passed to unregister_kmmio_probe() was PAGE_SIZE aligned by the caller leading to a complete freeze of the machine. We should always page align addresses while (un)registerung mappings, because the mmiotracer works on top of pages, not mappings. We still keep track of the probes based on their real addresses and lengths though, because the mmiotrace still needs to know what are mapped memory regions. Also move the call to mmiotrace_iounmap() prior page aligning the address, so that all probes are unregistered properly, otherwise the kernel ends up failing memory allocations randomly after disabling the mmiotracer. Tested-by: Lyude Signed-off-by: Karol Herbst Acked-by: Pekka Paalanen Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Steven Rostedt Cc: Thomas Gleixner Cc: nouveau@lists.freedesktop.org Link: http://lkml.kernel.org/r/20171127075139.4928-1-kherbst@redhat.com Signed-off-by: Ingo Molnar --- arch/x86/mm/ioremap.c | 4 ++-- arch/x86/mm/kmmio.c | 12 +++++++----- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index 6e4573b1da34..c45b6ec5357b 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c @@ -404,11 +404,11 @@ void iounmap(volatile void __iomem *addr) return; } + mmiotrace_iounmap(addr); + addr = (volatile void __iomem *) (PAGE_MASK & (unsigned long __force)addr); - mmiotrace_iounmap(addr); - /* Use the vm area unlocked, assuming the caller ensures there isn't another iounmap for the same address in parallel. Reuse of the virtual address is prevented by diff --git a/arch/x86/mm/kmmio.c b/arch/x86/mm/kmmio.c index c21c2ed04612..58477ec3d66d 100644 --- a/arch/x86/mm/kmmio.c +++ b/arch/x86/mm/kmmio.c @@ -435,17 +435,18 @@ int register_kmmio_probe(struct kmmio_probe *p) unsigned long flags; int ret = 0; unsigned long size = 0; + unsigned long addr = p->addr & PAGE_MASK; const unsigned long size_lim = p->len + (p->addr & ~PAGE_MASK); unsigned int l; pte_t *pte; spin_lock_irqsave(&kmmio_lock, flags); - if (get_kmmio_probe(p->addr)) { + if (get_kmmio_probe(addr)) { ret = -EEXIST; goto out; } - pte = lookup_address(p->addr, &l); + pte = lookup_address(addr, &l); if (!pte) { ret = -EINVAL; goto out; @@ -454,7 +455,7 @@ int register_kmmio_probe(struct kmmio_probe *p) kmmio_count++; list_add_rcu(&p->list, &kmmio_probes); while (size < size_lim) { - if (add_kmmio_fault_page(p->addr + size)) + if (add_kmmio_fault_page(addr + size)) pr_err("Unable to set page fault.\n"); size += page_level_size(l); } @@ -528,19 +529,20 @@ void unregister_kmmio_probe(struct kmmio_probe *p) { unsigned long flags; unsigned long size = 0; + unsigned long addr = p->addr & PAGE_MASK; const unsigned long size_lim = p->len + (p->addr & ~PAGE_MASK); struct kmmio_fault_page *release_list = NULL; struct kmmio_delayed_release *drelease; unsigned int l; pte_t *pte; - pte = lookup_address(p->addr, &l); + pte = lookup_address(addr, &l); if (!pte) return; spin_lock_irqsave(&kmmio_lock, flags); while (size < size_lim) { - release_kmmio_fault_page(p->addr + size, &release_list); + release_kmmio_fault_page(addr + size, &release_list); size += page_level_size(l); } list_del_rcu(&p->list); -- GitLab From 2064a5ab04707c55003e099e5abbf19a0826bbac Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 3 Dec 2017 13:19:00 -0800 Subject: [PATCH 1239/2547] sched/core: Fix kernel-doc warnings after code movement Fix the following kernel-doc warnings after code restructuring: ../kernel/sched/core.c:5113: warning: No description found for parameter 't' ../kernel/sched/core.c:5113: warning: Excess function parameter 'interval' description in 'sched_rr_get_interval' get rid of set_fs()") Signed-off-by: Randy Dunlap Cc: Al Viro Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Fixes: abca5fc535a3e ("sched_rr_get_interval(): move compat to native, Link: http://lkml.kernel.org/r/995c6ded-b32e-bbe4-d9f5-4d42d121aff1@infradead.org Signed-off-by: Ingo Molnar --- kernel/sched/core.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 75554f366fd3..644fa2e3d993 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5097,17 +5097,6 @@ SYSCALL_DEFINE1(sched_get_priority_min, int, policy) return ret; } -/** - * sys_sched_rr_get_interval - return the default timeslice of a process. - * @pid: pid of the process. - * @interval: userspace pointer to the timeslice value. - * - * this syscall writes the default timeslice value of a given process - * into the user-space timespec buffer. A value of '0' means infinity. - * - * Return: On success, 0 and the timeslice is in @interval. Otherwise, - * an error code. - */ static int sched_rr_get_interval(pid_t pid, struct timespec64 *t) { struct task_struct *p; @@ -5144,6 +5133,17 @@ static int sched_rr_get_interval(pid_t pid, struct timespec64 *t) return retval; } +/** + * sys_sched_rr_get_interval - return the default timeslice of a process. + * @pid: pid of the process. + * @interval: userspace pointer to the timeslice value. + * + * this syscall writes the default timeslice value of a given process + * into the user-space timespec buffer. A value of '0' means infinity. + * + * Return: On success, 0 and the timeslice is in @interval. Otherwise, + * an error code. + */ SYSCALL_DEFINE2(sched_rr_get_interval, pid_t, pid, struct timespec __user *, interval) { -- GitLab From 01dfee9582d9b4403c4902df096ed8b43d55181c Mon Sep 17 00:00:00 2001 From: Sergey Senozhatsky Date: Fri, 8 Dec 2017 11:56:14 +0900 Subject: [PATCH 1240/2547] workqueue: remove unneeded kallsyms include The filw was converted from print_symbol() to %pf some time ago (044c782ce3a901fb "workqueue: fix checkpatch issues"). kallsyms does not seem to be needed anymore. Signed-off-by: Sergey Senozhatsky Cc: Tejun Heo Cc: Lai Jiangshan Signed-off-by: Tejun Heo --- kernel/workqueue.c | 1 - 1 file changed, 1 deletion(-) diff --git a/kernel/workqueue.c b/kernel/workqueue.c index 45ce93f3dd1f..43d18cb46308 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include #include -- GitLab From 776bc27fd8ab67a675cb0041d3af361af5d0e290 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 8 Dec 2017 12:10:33 +0000 Subject: [PATCH 1241/2547] drm/i915: Stop listening to request resubmission from the signaler kthread MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The intent here was that we would be listening to i915_gem_request_unsubmit in order to cancel the signaler quickly and release the reference on the request. Cancelling the signaler is done directly via intel_engine_cancel_signaling (called from unsubmit), but that does not directly wake up the signaling thread, and neither does setting the request->global_seqno back to zero wake up listeners to the request->execute waitqueue. So the only time that listening to the request->execute waitqueue would wake up the signaling kthread would be on the request resubmission, during which time we would already receive wake ups from rejoining the global breadcrumbs wait rbtree. Trying to wake up to release the request remains an issue. If the signaling was cancelled and no other request required signaling, then it is possible for us to shutdown with the reference on the request still held. To ensure that we do not try to shutdown, leaking that request, we kick the signaling threads whenever we disarm the breadcrumbs, i.e. on parking the engine when idle. v2: We do need to be sure to release the last reference on stopping the kthread; asserting that it has been dropped already is insufficient. Fixes: d6a2289d9d6b ("drm/i915: Remove the preempted request from the execution queue") Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Michał Winiarski Link: https://patchwork.freedesktop.org/patch/msgid/20171208121033.5236-1-chris@chris-wilson.co.uk Acked-by: Daniel Vetter Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_breadcrumbs.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c index 24c6fefdd0b1..a7740696114d 100644 --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c @@ -217,7 +217,7 @@ void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine) struct intel_wait *wait, *n; if (!b->irq_armed) - return; + goto wakeup_signaler; /* * We only disarm the irq when we are idle (all requests completed), @@ -242,6 +242,14 @@ void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine) b->waiters = RB_ROOT; spin_unlock_irq(&b->rb_lock); + + /* + * The signaling thread may be asleep holding a reference to a request, + * that had its signaling cancelled prior to being preempted. We need + * to kick the signaler, just in case, to release any such reference. + */ +wakeup_signaler: + wake_up_process(b->signaler); } static bool use_fake_irq(const struct intel_breadcrumbs *b) @@ -686,23 +694,15 @@ static int intel_breadcrumbs_signaler(void *arg) } if (unlikely(do_schedule)) { - DEFINE_WAIT(exec); - if (kthread_should_park()) kthread_parkme(); - if (kthread_should_stop()) { - GEM_BUG_ON(request); + if (unlikely(kthread_should_stop())) { + i915_gem_request_put(request); break; } - if (request) - add_wait_queue(&request->execute, &exec); - schedule(); - - if (request) - remove_wait_queue(&request->execute, &exec); } i915_gem_request_put(request); } while (1); -- GitLab From 86ad5c97ce5ccdda1459d35370fd5e105721bb8d Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sat, 9 Dec 2017 14:49:14 +0300 Subject: [PATCH 1242/2547] RISC-V: Logical vs Bitwise typo In the current code, there is a ! logical NOT where a bitwise ~ NOT was intended. It means that we never return -EINVAL. Signed-off-by: Dan Carpenter Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/sys_riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index a2ae936a093e..79c78668258e 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -70,7 +70,7 @@ SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end, bool local = (flags & SYS_RISCV_FLUSH_ICACHE_LOCAL) != 0; /* Check the reserved flags. */ - if (unlikely(flags & !SYS_RISCV_FLUSH_ICACHE_ALL)) + if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL)) return -EINVAL; flush_icache_mm(mm, local); -- GitLab From 3cfa5008081db845c6c53d531ec34e9c84a9fd99 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Tue, 5 Dec 2017 17:48:11 -0800 Subject: [PATCH 1243/2547] RISC-V: Resurrect smp_mb__after_spinlock() I removed this last week because of an incorrect comment: smp_mb__after_spinlock() is actually still used, and is necessary on RISC-V. It's been resurrected, with a comment that describes what it actually does this time. Thanks to Andrea for finding the bug! Fixes: 3343eb6806f3 ("RISC-V: Remove smb_mb__{before,after}_spinlock()") CC: Andrea Parri Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/barrier.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 773c4e039cd7..c0319cbf1eec 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -38,6 +38,25 @@ #define smp_rmb() RISCV_FENCE(r,r) #define smp_wmb() RISCV_FENCE(w,w) +/* + * This is a very specific barrier: it's currently only used in two places in + * the kernel, both in the scheduler. See include/linux/spinlock.h for the two + * orderings it guarantees, but the "critical section is RCsc" guarantee + * mandates a barrier on RISC-V. The sequence looks like: + * + * lr.aq lock + * sc lock <= LOCKED + * smp_mb__after_spinlock() + * // critical section + * lr lock + * sc.rl lock <= UNLOCKED + * + * The AQ/RL pair provides a RCpc critical section, but there's not really any + * way we can take advantage of that here because the ordering is only enforced + * on that one lock. Thus, we're just doing a full fence. + */ +#define smp_mb__after_spinlock() RISCV_FENCE(rw,rw) + #include #endif /* __ASSEMBLY__ */ -- GitLab From 27b0174525325bf18919597016483a709f3372f8 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Fri, 8 Dec 2017 11:23:23 -0800 Subject: [PATCH 1244/2547] RISC-V: Remove unused CONFIG_HVC_RISCV_SBI code This is code that probably should never have made it into the kernel in the first place: it depends on a driver that hadn't been reviewed yet. During the HVC_SBI_RISCV review process a better way of doing this was suggested, but that means this code is defunct. It's compile-time disabled in 4.15 because the driver isn't in, so I think it's safe to just remove this for now. CC: Greg KH Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/setup.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 8fbb6749910d..cb7b0c63014e 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -38,10 +38,6 @@ #include #include -#ifdef CONFIG_HVC_RISCV_SBI -#include -#endif - #ifdef CONFIG_DUMMY_CONSOLE struct screen_info screen_info = { .orig_video_lines = 30, @@ -212,13 +208,6 @@ static void __init setup_bootmem(void) void __init setup_arch(char **cmdline_p) { -#if defined(CONFIG_HVC_RISCV_SBI) - if (likely(early_console == NULL)) { - early_console = &riscv_sbi_early_console_dev; - register_console(early_console); - } -#endif - #ifdef CONFIG_CMDLINE_BOOL #ifdef CONFIG_CMDLINE_OVERRIDE strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE); -- GitLab From a8ceb5dbfde1092b466936bca0ff3be127ecf38e Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Tue, 5 Dec 2017 21:29:37 +0200 Subject: [PATCH 1245/2547] ptr_ring: add barriers Users of ptr_ring expect that it's safe to give the data structure a pointer and have it be available to consumers, but that actually requires an smb_wmb or a stronger barrier. In absence of such barriers and on architectures that reorder writes, consumer might read an un=initialized value from an skb pointer stored in the skb array. This was observed causing crashes. To fix, add memory barriers. The barrier we use is a wmb, the assumption being that producers do not need to read the value so we do not need to order these reads. Reported-by: George Cherian Suggested-by: Jason Wang Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang Signed-off-by: David S. Miller --- include/linux/ptr_ring.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/ptr_ring.h b/include/linux/ptr_ring.h index 37b4bb2545b3..6866df4f31b5 100644 --- a/include/linux/ptr_ring.h +++ b/include/linux/ptr_ring.h @@ -101,12 +101,18 @@ static inline bool ptr_ring_full_bh(struct ptr_ring *r) /* Note: callers invoking this in a loop must use a compiler barrier, * for example cpu_relax(). Callers must hold producer_lock. + * Callers are responsible for making sure pointer that is being queued + * points to a valid data. */ static inline int __ptr_ring_produce(struct ptr_ring *r, void *ptr) { if (unlikely(!r->size) || r->queue[r->producer]) return -ENOSPC; + /* Make sure the pointer we are storing points to a valid data. */ + /* Pairs with smp_read_barrier_depends in __ptr_ring_consume. */ + smp_wmb(); + r->queue[r->producer++] = ptr; if (unlikely(r->producer >= r->size)) r->producer = 0; @@ -275,6 +281,9 @@ static inline void *__ptr_ring_consume(struct ptr_ring *r) if (ptr) __ptr_ring_discard_one(r); + /* Make sure anyone accessing data through the pointer is up to date. */ + /* Pairs with smp_wmb in __ptr_ring_produce. */ + smp_read_barrier_depends(); return ptr; } -- GitLab From 23715275e4fb6f64358a499d20928a9e93819f2f Mon Sep 17 00:00:00 2001 From: Konstantin Khlebnikov Date: Mon, 11 Dec 2017 18:19:33 +0300 Subject: [PATCH 1246/2547] netfilter: ip6t_MASQUERADE: add dependency on conntrack module After commit 4d3a57f23dec ("netfilter: conntrack: do not enable connection tracking unless needed") conntrack is disabled by default unless some module explicitly declares dependency in particular network namespace. Fixes: a357b3f80bc8 ("netfilter: nat: add dependencies on conntrack module") Signed-off-by: Konstantin Khlebnikov Signed-off-by: Pablo Neira Ayuso --- net/ipv6/netfilter/ip6t_MASQUERADE.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/net/ipv6/netfilter/ip6t_MASQUERADE.c b/net/ipv6/netfilter/ip6t_MASQUERADE.c index 2b1a15846f9a..92c0047e7e33 100644 --- a/net/ipv6/netfilter/ip6t_MASQUERADE.c +++ b/net/ipv6/netfilter/ip6t_MASQUERADE.c @@ -33,13 +33,19 @@ static int masquerade_tg6_checkentry(const struct xt_tgchk_param *par) if (range->flags & NF_NAT_RANGE_MAP_IPS) return -EINVAL; - return 0; + return nf_ct_netns_get(par->net, par->family); +} + +static void masquerade_tg6_destroy(const struct xt_tgdtor_param *par) +{ + nf_ct_netns_put(par->net, par->family); } static struct xt_target masquerade_tg6_reg __read_mostly = { .name = "MASQUERADE", .family = NFPROTO_IPV6, .checkentry = masquerade_tg6_checkentry, + .destroy = masquerade_tg6_destroy, .target = masquerade_tg6, .targetsize = sizeof(struct nf_nat_range), .table = "nat", -- GitLab From f24e5834a2c3f6c5f814a417f858226f0a010ade Mon Sep 17 00:00:00 2001 From: Steve Capper Date: Mon, 4 Dec 2017 14:13:05 +0000 Subject: [PATCH 1247/2547] arm64: Initialise high_memory global variable earlier The high_memory global variable is used by cma_declare_contiguous(.) before it is defined. We don't notice this as we compute __pa(high_memory - 1), and it looks like we're processing a VA from the direct linear map. This problem becomes apparent when we flip the kernel virtual address space and the linear map is moved to the bottom of the kernel VA space. This patch moves the initialisation of high_memory before it used. Cc: Fixes: f7426b983a6a ("mm: cma: adjust address limit to avoid hitting low/high memory boundary") Signed-off-by: Steve Capper Signed-off-by: Will Deacon --- arch/arm64/mm/init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 5960bef0170d..00e7b900ca41 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -476,6 +476,8 @@ void __init arm64_memblock_init(void) reserve_elfcorehdr(); + high_memory = __va(memblock_end_of_DRAM() - 1) + 1; + dma_contiguous_reserve(arm64_dma_phys_limit); memblock_allow_resize(); @@ -502,7 +504,6 @@ void __init bootmem_init(void) sparse_init(); zone_sizes_init(min, max); - high_memory = __va((max << PAGE_SHIFT) - 1) + 1; memblock_dump_all(); } -- GitLab From 8781bcbc5e69d7da69e84c7044ca0284848d5d01 Mon Sep 17 00:00:00 2001 From: Steve Capper Date: Fri, 1 Dec 2017 17:22:14 +0000 Subject: [PATCH 1248/2547] arm64: mm: Fix pte_mkclean, pte_mkdirty semantics On systems with hardware dirty bit management, the ltp madvise09 unit test fails due to dirty bit information being lost and pages being incorrectly freed. This was bisected to: arm64: Ignore hardware dirty bit updates in ptep_set_wrprotect() Reverting this commit leads to a separate problem, that the unit test retains pages that should have been dropped due to the function madvise_free_pte_range(.) not cleaning pte's properly. Currently pte_mkclean only clears the software dirty bit, thus the following code sequence can appear: pte = pte_mkclean(pte); if (pte_dirty(pte)) // this condition can return true with HW DBM! This patch also adjusts pte_mkclean to set PTE_RDONLY thus effectively clearing both the SW and HW dirty information. In order for this to function on systems without HW DBM, we need to also adjust pte_mkdirty to remove the read only bit from writable pte's to avoid infinite fault loops. Cc: Fixes: 64c26841b349 ("arm64: Ignore hardware dirty bit updates in ptep_set_wrprotect()") Reported-by: Bhupinder Thakur Tested-by: Bhupinder Thakur Reviewed-by: Catalin Marinas Signed-off-by: Steve Capper Signed-off-by: Will Deacon --- arch/arm64/include/asm/pgtable.h | 33 +++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 149d05fb9421..3ff03a755c32 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -149,12 +149,20 @@ static inline pte_t pte_mkwrite(pte_t pte) static inline pte_t pte_mkclean(pte_t pte) { - return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); + pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); + pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); + + return pte; } static inline pte_t pte_mkdirty(pte_t pte) { - return set_pte_bit(pte, __pgprot(PTE_DIRTY)); + pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); + + if (pte_write(pte)) + pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); + + return pte; } static inline pte_t pte_mkold(pte_t pte) @@ -641,28 +649,23 @@ static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ /* - * ptep_set_wrprotect - mark read-only while preserving the hardware update of - * the Access Flag. + * ptep_set_wrprotect - mark read-only while trasferring potential hardware + * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. */ #define __HAVE_ARCH_PTEP_SET_WRPROTECT static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) { pte_t old_pte, pte; - /* - * ptep_set_wrprotect() is only called on CoW mappings which are - * private (!VM_SHARED) with the pte either read-only (!PTE_WRITE && - * PTE_RDONLY) or writable and software-dirty (PTE_WRITE && - * !PTE_RDONLY && PTE_DIRTY); see is_cow_mapping() and - * protection_map[]. There is no race with the hardware update of the - * dirty state: clearing of PTE_RDONLY when PTE_WRITE (a.k.a. PTE_DBM) - * is set. - */ - VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(*ptep), - "%s: potential race with hardware DBM", __func__); pte = READ_ONCE(*ptep); do { old_pte = pte; + /* + * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY + * clear), set the PTE_DIRTY bit. + */ + if (pte_hw_dirty(pte)) + pte = pte_mkdirty(pte); pte = pte_wrprotect(pte); pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), pte_val(old_pte), pte_val(pte)); -- GitLab From f1e2400a80ff55eb7c5f4fd9d7eb163fd0de9a2c Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 8 Dec 2017 12:08:11 +0100 Subject: [PATCH 1249/2547] net: phy: meson-gxl: detect LPA corruption The purpose of this change is to fix the incorrect detection of the link partner (LP) advertised capabilities which sometimes happens with this PHY (roughly 1 time in a dozen) This issue may cause the link to be negotiated at 10Mbps/Full or 10Mbps/Half when 100MBps/Full is actually possible. In some case, the link is even completely broken and no communication is possible. To detect the corruption, we must look for a magic undocumented bit in the WOL bank (hint given by the SoC vendor kernel) but this is not enough to cover all cases. We also have to look at the LPA ack. If the LP supports Aneg but did not ack our base code when aneg is completed, we assume something went wrong. The detection of a corrupted LPA triggers a restart of the aneg process. This solves the problem but may take up to 6 retries to complete. Fixes: 7334b3e47aee ("net: phy: Add Meson GXL Internal PHY driver") Signed-off-by: Jerome Brunet Signed-off-by: David S. Miller --- drivers/net/phy/meson-gxl.c | 74 ++++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index 1ea69b7585d9..700007dd4be5 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -22,6 +22,7 @@ #include #include #include +#include static int meson_gxl_config_init(struct phy_device *phydev) { @@ -50,6 +51,77 @@ static int meson_gxl_config_init(struct phy_device *phydev) return 0; } +/* This function is provided to cope with the possible failures of this phy + * during aneg process. When aneg fails, the PHY reports that aneg is done + * but the value found in MII_LPA is wrong: + * - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that + * the link partner (LP) supports aneg but the LP never acked our base + * code word, it is likely that we never sent it to begin with. + * - Late failures: MII_LPA is filled with a value which seems to make sense + * but it actually is not what the LP is advertising. It seems that we + * can detect this using a magic bit in the WOL bank (reg 12 - bit 12). + * If this particular bit is not set when aneg is reported being done, + * it means MII_LPA is likely to be wrong. + * + * In both case, forcing a restart of the aneg process solve the problem. + * When this failure happens, the first retry is usually successful but, + * in some cases, it may take up to 6 retries to get a decent result + */ +int meson_gxl_read_status(struct phy_device *phydev) +{ + int ret, wol, lpa, exp; + + if (phydev->autoneg == AUTONEG_ENABLE) { + ret = genphy_aneg_done(phydev); + if (ret < 0) + return ret; + else if (!ret) + goto read_status_continue; + + /* Need to access WOL bank, make sure the access is open */ + ret = phy_write(phydev, 0x14, 0x0000); + if (ret) + return ret; + ret = phy_write(phydev, 0x14, 0x0400); + if (ret) + return ret; + ret = phy_write(phydev, 0x14, 0x0000); + if (ret) + return ret; + ret = phy_write(phydev, 0x14, 0x0400); + if (ret) + return ret; + + /* Request LPI_STATUS WOL register */ + ret = phy_write(phydev, 0x14, 0x8D80); + if (ret) + return ret; + + /* Read LPI_STATUS value */ + wol = phy_read(phydev, 0x15); + if (wol < 0) + return wol; + + lpa = phy_read(phydev, MII_LPA); + if (lpa < 0) + return lpa; + + exp = phy_read(phydev, MII_EXPANSION); + if (exp < 0) + return exp; + + if (!(wol & BIT(12)) || + ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) { + /* Looks like aneg failed after all */ + phydev_dbg(phydev, "LPA corruption - aneg restart\n"); + return genphy_restart_aneg(phydev); + } + } + +read_status_continue: + return genphy_read_status(phydev); +} + static struct phy_driver meson_gxl_phy[] = { { .phy_id = 0x01814400, @@ -60,7 +132,7 @@ static struct phy_driver meson_gxl_phy[] = { .config_init = meson_gxl_config_init, .config_aneg = genphy_config_aneg, .aneg_done = genphy_aneg_done, - .read_status = genphy_read_status, + .read_status = meson_gxl_read_status, .suspend = genphy_suspend, .resume = genphy_resume, }, -- GitLab From 2aab6b40b03154a263463a5d992ddd7d122a016a Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 8 Dec 2017 16:35:40 +0100 Subject: [PATCH 1250/2547] net: sh_eth: do not advertise Gigabit capabilities when not available Not all variants of the sh_eth hardware have Gigabit support. Unfortunately, the current driver doesn't tell the PHY about the limited MAC capabilities. Due to this, if you have a Gigabit capable PHY, the PHY will advertise its Gigabit capability and establish a link at 1Gbit/s, even though the MAC doesn't support it. In order to avoid this, we use the recently introduced phy_set_max_speed() to tell the PHY to not advertise speed higher than 100 MBit/s. Tested on a SH7786 platform, with a Gigabit PHY. Signed-off-by: Thomas Petazzoni Signed-off-by: David S. Miller --- drivers/net/ethernet/renesas/sh_eth.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c index db72d13cebb9..75323000c364 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c @@ -1892,6 +1892,16 @@ static int sh_eth_phy_init(struct net_device *ndev) return PTR_ERR(phydev); } + /* mask with MAC supported features */ + if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) { + int err = phy_set_max_speed(phydev, SPEED_100); + if (err) { + netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n"); + phy_disconnect(phydev); + return err; + } + } + phy_attached_info(phydev); return 0; -- GitLab From 93c647643b48f0131f02e45da3bd367d80443291 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Wed, 6 Dec 2017 12:12:27 -0800 Subject: [PATCH 1251/2547] netlink: Add netns check on taps Currently, a nlmon link inside a child namespace can observe systemwide netlink activity. Filter the traffic so that nlmon can only sniff netlink messages from its own netns. Test case: vpnns -- bash -c "ip link add nlmon0 type nlmon; \ ip link set nlmon0 up; \ tcpdump -i nlmon0 -q -w /tmp/nlmon.pcap -U" & sudo ip xfrm state add src 10.1.1.1 dst 10.1.1.2 proto esp \ spi 0x1 mode transport \ auth sha1 0x6162633132330000000000000000000000000000 \ enc aes 0x00000000000000000000000000000000 grep --binary abc123 /tmp/nlmon.pcap Signed-off-by: Kevin Cernekee Signed-off-by: David S. Miller --- net/netlink/af_netlink.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c index b9e0ee4e22f5..79cc1bf36e4a 100644 --- a/net/netlink/af_netlink.c +++ b/net/netlink/af_netlink.c @@ -253,6 +253,9 @@ static int __netlink_deliver_tap_skb(struct sk_buff *skb, struct sock *sk = skb->sk; int ret = -ENOMEM; + if (!net_eq(dev_net(dev), sock_net(sk))) + return 0; + dev_hold(dev); if (is_vmalloc_addr(skb->head)) -- GitLab From b92326a04071ed5a02bc31c2359da2cdadde743c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 9 Dec 2017 12:47:10 +0000 Subject: [PATCH 1252/2547] drm/i915: Only report a wakeup if the waiter was truly asleep If we attempt to wake up a waiter, who is currently checking the seqno it will be in the TASK_INTERRUPTIBLE state and ttwu will report success. However, it is actually awake and functioning -- so delay reporting the actual wake up until it sleeps. This fixes some spurious claims of missed_breadcrumbs when running under heavy load; i.e. sufficient load to preempt away the newly woken waiter before they complete their checks. However, it does so at the cost of a rare false negative; where the waiter changes between the check and ttwu -- the only way to fix that would be to extend the reporting from ttwu where the check could be done atomically. v2: Defend against !CONFIG_SMP v3: Don't filter out calls to wake_up_process v4: Drop risky microoptimisation to skip wakeups Testcase: igt/drv_missed_irq # sanity check we do detect missed_breadcrumb() Testcase: igt/gem_concurrent_blit # for generating false positives References: https://bugs.freedesktop.org/show_bug.cgi?id=100007 Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171209124710.1606-1-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_breadcrumbs.c | 26 ++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c index a7740696114d..58c624f982d9 100644 --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c @@ -27,6 +27,12 @@ #include "i915_drv.h" +#ifdef CONFIG_SMP +#define task_asleep(tsk) ((tsk)->state & TASK_NORMAL && !(tsk)->on_cpu) +#else +#define task_asleep(tsk) ((tsk)->state & TASK_NORMAL) +#endif + static unsigned int __intel_breadcrumbs_wakeup(struct intel_breadcrumbs *b) { struct intel_wait *wait; @@ -36,8 +42,20 @@ static unsigned int __intel_breadcrumbs_wakeup(struct intel_breadcrumbs *b) wait = b->irq_wait; if (wait) { + /* + * N.B. Since task_asleep() and ttwu are not atomic, the + * waiter may actually go to sleep after the check, causing + * us to suppress a valid wakeup. We prefer to reduce the + * number of false positive missed_breadcrumb() warnings + * at the expense of a few false negatives, as it it easy + * to trigger a false positive under heavy load. Enough + * signal should remain from genuine missed_breadcrumb() + * for us to detect in CI. + */ + bool was_asleep = task_asleep(wait->tsk); + result = ENGINE_WAKEUP_WAITER; - if (wake_up_process(wait->tsk)) + if (wake_up_process(wait->tsk) && was_asleep) result |= ENGINE_WAKEUP_ASLEEP; } @@ -77,8 +95,8 @@ static noinline void missed_breadcrumb(struct intel_engine_cs *engine) static void intel_breadcrumbs_hangcheck(struct timer_list *t) { - struct intel_engine_cs *engine = from_timer(engine, t, - breadcrumbs.hangcheck); + struct intel_engine_cs *engine = + from_timer(engine, t, breadcrumbs.hangcheck); struct intel_breadcrumbs *b = &engine->breadcrumbs; if (!b->irq_armed) @@ -104,7 +122,7 @@ static void intel_breadcrumbs_hangcheck(struct timer_list *t) */ if (intel_engine_wakeup(engine) & ENGINE_WAKEUP_ASLEEP) { missed_breadcrumb(engine); - mod_timer(&engine->breadcrumbs.fake_irq, jiffies + 1); + mod_timer(&b->fake_irq, jiffies + 1); } else { mod_timer(&b->hangcheck, wait_timeout()); } -- GitLab From f79ce87fa49da778a1ad54c7d3c6755e13cf8489 Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Thu, 30 Nov 2017 22:51:20 +0800 Subject: [PATCH 1253/2547] x86/build: Don't verify mtools configuration file for isoimage If mtools.conf is not generated before, 'make isoimage' could complain: Kernel: arch/x86/boot/bzImage is ready (#597) GENIMAGE arch/x86/boot/image.iso *** Missing file: arch/x86/boot/mtools.conf arch/x86/boot/Makefile:144: recipe for target 'isoimage' failed mtools.conf is not used for isoimage generation, so do not check it. Signed-off-by: Changbin Du Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Fixes: 4366d57af1 ("x86/build: Factor out fdimage/isoimage generation commands to standalone script") Link: http://lkml.kernel.org/r/1512053480-8083-1-git-send-email-changbin.du@intel.com Signed-off-by: Ingo Molnar --- arch/x86/boot/genimage.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/boot/genimage.sh b/arch/x86/boot/genimage.sh index 49f4970f693b..c9e8499fbfe7 100644 --- a/arch/x86/boot/genimage.sh +++ b/arch/x86/boot/genimage.sh @@ -44,9 +44,9 @@ FDINITRD=$6 # Make sure the files actually exist verify "$FBZIMAGE" -verify "$MTOOLSRC" genbzdisk() { + verify "$MTOOLSRC" mformat a: syslinux $FIMAGE echo "$KCMDLINE" | mcopy - a:syslinux.cfg @@ -57,6 +57,7 @@ genbzdisk() { } genfdimage144() { + verify "$MTOOLSRC" dd if=/dev/zero of=$FIMAGE bs=1024 count=1440 2> /dev/null mformat v: syslinux $FIMAGE @@ -68,6 +69,7 @@ genfdimage144() { } genfdimage288() { + verify "$MTOOLSRC" dd if=/dev/zero of=$FIMAGE bs=1024 count=2880 2> /dev/null mformat w: syslinux $FIMAGE -- GitLab From 0a373d4fc248cb707821d7dad54ce6d5bcb0cdfe Mon Sep 17 00:00:00 2001 From: Andrey Ryabinin Date: Thu, 30 Nov 2017 15:35:54 +0300 Subject: [PATCH 1254/2547] x86/unwinder/guess: Prevent using CONFIG_UNWINDER_GUESS=y with CONFIG_STACKDEPOT=y Stackdepot doesn't work well with CONFIG_UNWINDER_GUESS=y. The 'guess' unwinder generate awfully large and inaccurate stacktraces, thus stackdepot can't deduplicate stacktraces because they all look like unique. Eventually stackdepot reaches its capacity limit: WARNING: CPU: 0 PID: 545 at lib/stackdepot.c:119 depot_save_stack+0x28e/0x550 Call Trace: ? kasan_kmalloc+0x144/0x160 ? depot_save_stack+0x1f5/0x550 ? do_raw_spin_unlock+0xda/0xf0 ? preempt_count_sub+0x13/0xc0 <...90 lines...> ? do_raw_spin_unlock+0xda/0xf0 Add a STACKDEPOT=n dependency to UNWINDER_GUESS to avoid the problem. Reported-by: kernel test robot Reported-by: Fengguang Wu Signed-off-by: Andrey Ryabinin Acked-by: Dmitry Vyukov Acked-by: Josh Poimboeuf Cc: Alexander Potapenko Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/20171130123554.4330-1-aryabinin@virtuozzo.com Signed-off-by: Ingo Molnar --- arch/x86/Kconfig.debug | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index 6293a8768a91..672441c008c7 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -400,6 +400,7 @@ config UNWINDER_FRAME_POINTER config UNWINDER_GUESS bool "Guess unwinder" depends on EXPERT + depends on !STACKDEPOT ---help--- This option enables the "guess" unwinder for unwinding kernel stack traces. It scans the stack and reports every kernel text address it -- GitLab From 8f659a03a0ba9289b9aeb9b4470e6fb263d6f483 Mon Sep 17 00:00:00 2001 From: Mohamed Ghannam Date: Sun, 10 Dec 2017 03:50:58 +0000 Subject: [PATCH 1255/2547] net: ipv4: fix for a race condition in raw_sendmsg inet->hdrincl is racy, and could lead to uninitialized stack pointer usage, so its value should be read only once. Fixes: c008ba5bdc9f ("ipv4: Avoid reading user iov twice after raw_probe_proto_opt") Signed-off-by: Mohamed Ghannam Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller --- net/ipv4/raw.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/net/ipv4/raw.c b/net/ipv4/raw.c index 33b70bfd1122..125c1eab3eaa 100644 --- a/net/ipv4/raw.c +++ b/net/ipv4/raw.c @@ -513,11 +513,16 @@ static int raw_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) int err; struct ip_options_data opt_copy; struct raw_frag_vec rfv; + int hdrincl; err = -EMSGSIZE; if (len > 0xFFFF) goto out; + /* hdrincl should be READ_ONCE(inet->hdrincl) + * but READ_ONCE() doesn't work with bit fields + */ + hdrincl = inet->hdrincl; /* * Check the flags. */ @@ -593,7 +598,7 @@ static int raw_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) /* Linux does not mangle headers on raw sockets, * so that IP options + IP_HDRINCL is non-sense. */ - if (inet->hdrincl) + if (hdrincl) goto done; if (ipc.opt->opt.srr) { if (!daddr) @@ -615,12 +620,12 @@ static int raw_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) flowi4_init_output(&fl4, ipc.oif, sk->sk_mark, tos, RT_SCOPE_UNIVERSE, - inet->hdrincl ? IPPROTO_RAW : sk->sk_protocol, + hdrincl ? IPPROTO_RAW : sk->sk_protocol, inet_sk_flowi_flags(sk) | - (inet->hdrincl ? FLOWI_FLAG_KNOWN_NH : 0), + (hdrincl ? FLOWI_FLAG_KNOWN_NH : 0), daddr, saddr, 0, 0, sk->sk_uid); - if (!inet->hdrincl) { + if (!hdrincl) { rfv.msg = msg; rfv.hlen = 0; @@ -645,7 +650,7 @@ static int raw_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) goto do_confirm; back_from_confirm: - if (inet->hdrincl) + if (hdrincl) err = raw_send_hdrinc(sk, &fl4, msg, len, &rt, msg->msg_flags, &ipc.sockc); -- GitLab From 2342b8d95bcae5946e1b9b8d58645f37500ef2e7 Mon Sep 17 00:00:00 2001 From: Xin Long Date: Sun, 10 Dec 2017 15:40:51 +0800 Subject: [PATCH 1256/2547] sctp: make sure stream nums can match optlen in sctp_setsockopt_reset_streams Now in sctp_setsockopt_reset_streams, it only does the check optlen < sizeof(*params) for optlen. But it's not enough, as params->srs_number_streams should also match optlen. If the streams in params->srs_stream_list are less than stream nums in params->srs_number_streams, later when dereferencing the stream list, it could cause a slab-out-of-bounds crash, as reported by syzbot. This patch is to fix it by also checking the stream numbers in sctp_setsockopt_reset_streams to make sure at least it's not greater than the streams in the list. Fixes: 7f9d68ac944e ("sctp: implement sender-side procedures for SSN Reset Request Parameter") Reported-by: Dmitry Vyukov Signed-off-by: Xin Long Acked-by: Marcelo Ricardo Leitner Acked-by: Neil Horman Signed-off-by: David S. Miller --- net/sctp/socket.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/net/sctp/socket.c b/net/sctp/socket.c index eb17a911aa29..3253f724a995 100644 --- a/net/sctp/socket.c +++ b/net/sctp/socket.c @@ -3891,13 +3891,17 @@ static int sctp_setsockopt_reset_streams(struct sock *sk, struct sctp_association *asoc; int retval = -EINVAL; - if (optlen < sizeof(struct sctp_reset_streams)) + if (optlen < sizeof(*params)) return -EINVAL; params = memdup_user(optval, optlen); if (IS_ERR(params)) return PTR_ERR(params); + if (params->srs_number_streams * sizeof(__u16) > + optlen - sizeof(*params)) + goto out; + asoc = sctp_id2assoc(sk, params->srs_assoc_id); if (!asoc) goto out; -- GitLab From 200809716aed1cac586fcac4c0551a688439be1f Mon Sep 17 00:00:00 2001 From: Xin Long Date: Sun, 10 Dec 2017 16:56:00 +0800 Subject: [PATCH 1257/2547] fou: fix some member types in guehdr guehdr struct is used to build or parse gue packets, which are always in big endian. It's better to define all guehdr members as __beXX types. Also, in validate_gue_flags it's not good to use a __be32 variable for both Standard flags(__be16) and Private flags (__be32), and pass it to other funcions. This patch could fix a bunch of sparse warnings from fou. Fixes: 5024c33ac354 ("gue: Add infrastructure for flags and options") Signed-off-by: Xin Long Signed-off-by: David S. Miller --- include/net/gue.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/include/net/gue.h b/include/net/gue.h index 2fdb29ca74c2..fdad41469b65 100644 --- a/include/net/gue.h +++ b/include/net/gue.h @@ -44,10 +44,10 @@ struct guehdr { #else #error "Please fix " #endif - __u8 proto_ctype; - __u16 flags; + __u8 proto_ctype; + __be16 flags; }; - __u32 word; + __be32 word; }; }; @@ -84,11 +84,10 @@ static inline size_t guehdr_priv_flags_len(__be32 flags) * if there is an unknown standard or private flags, or the options length for * the flags exceeds the options length specific in hlen of the GUE header. */ -static inline int validate_gue_flags(struct guehdr *guehdr, - size_t optlen) +static inline int validate_gue_flags(struct guehdr *guehdr, size_t optlen) { + __be16 flags = guehdr->flags; size_t len; - __be32 flags = guehdr->flags; if (flags & ~GUE_FLAGS_ALL) return 1; @@ -101,12 +100,13 @@ static inline int validate_gue_flags(struct guehdr *guehdr, /* Private flags are last four bytes accounted in * guehdr_flags_len */ - flags = *(__be32 *)((void *)&guehdr[1] + len - GUE_LEN_PRIV); + __be32 pflags = *(__be32 *)((void *)&guehdr[1] + + len - GUE_LEN_PRIV); - if (flags & ~GUE_PFLAGS_ALL) + if (pflags & ~GUE_PFLAGS_ALL) return 1; - len += guehdr_priv_flags_len(flags); + len += guehdr_priv_flags_len(pflags); if (len > optlen) return 1; } -- GitLab From 9d5afec6b8bd46d6ed821aa1579634437f58ef1f Mon Sep 17 00:00:00 2001 From: Chandan Rajendra Date: Mon, 11 Dec 2017 15:00:57 -0500 Subject: [PATCH 1258/2547] ext4: fix crash when a directory's i_size is too small On a ppc64 machine, when mounting a fuzzed ext2 image (generated by fsfuzzer) the following call trace is seen, VFS: brelse: Trying to free free buffer WARNING: CPU: 1 PID: 6913 at /root/repos/linux/fs/buffer.c:1165 .__brelse.part.6+0x24/0x40 .__brelse.part.6+0x20/0x40 (unreliable) .ext4_find_entry+0x384/0x4f0 .ext4_lookup+0x84/0x250 .lookup_slow+0xdc/0x230 .walk_component+0x268/0x400 .path_lookupat+0xec/0x2d0 .filename_lookup+0x9c/0x1d0 .vfs_statx+0x98/0x140 .SyS_newfstatat+0x48/0x80 system_call+0x58/0x6c This happens because the directory that ext4_find_entry() looks up has inode->i_size that is less than the block size of the filesystem. This causes 'nblocks' to have a value of zero. ext4_bread_batch() ends up not reading any of the directory file's blocks. This renders the entries in bh_use[] array to continue to have garbage data. buffer_uptodate() on bh_use[0] can then return a zero value upon which brelse() function is invoked. This commit fixes the bug by returning -ENOENT when the directory file has no associated blocks. Reported-by: Abdul Haleem Signed-off-by: Chandan Rajendra Cc: stable@vger.kernel.org --- fs/ext4/namei.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c index 798b3ac680db..e750d68fbcb5 100644 --- a/fs/ext4/namei.c +++ b/fs/ext4/namei.c @@ -1399,6 +1399,10 @@ static struct buffer_head * ext4_find_entry (struct inode *dir, "falling back\n")); } nblocks = dir->i_size >> EXT4_BLOCK_SIZE_BITS(sb); + if (!nblocks) { + ret = NULL; + goto cleanup_and_exit; + } start = EXT4_I(dir)->i_dir_start_lookup; if (start >= nblocks) start = 0; -- GitLab From c058ecf6e455fac7346d46197a02398ead90851f Mon Sep 17 00:00:00 2001 From: Steve Wise Date: Mon, 27 Nov 2017 13:16:32 -0800 Subject: [PATCH 1259/2547] iw_cxgb4: only insert drain cqes if wq is flushed Only insert our special drain CQEs to support ib_drain_sq/rq() after the wq is flushed. Otherwise, existing but not yet polled CQEs can be returned out of order to the user application. This can happen when the QP has exited RTS but not yet flushed the QP, which can happen during a normal close (vs abortive close). In addition never count the drain CQEs when determining how many CQEs need to be synthesized during the flush operation. This latter issue should never happen if the QP is properly flushed before inserting the drain CQE, but I wanted to avoid corrupting the CQ state. So we handle it and log a warning once. Fixes: 4fe7c2962e11 ("iw_cxgb4: refactor sq/rq drain logic") Signed-off-by: Steve Wise Cc: stable@vger.kernel.org Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/cxgb4/cq.c | 5 +++++ drivers/infiniband/hw/cxgb4/qp.c | 14 ++++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/hw/cxgb4/cq.c b/drivers/infiniband/hw/cxgb4/cq.c index ea55e95cd2c5..b7bfc536e00f 100644 --- a/drivers/infiniband/hw/cxgb4/cq.c +++ b/drivers/infiniband/hw/cxgb4/cq.c @@ -395,6 +395,11 @@ void c4iw_flush_hw_cq(struct c4iw_cq *chp) static int cqe_completes_wr(struct t4_cqe *cqe, struct t4_wq *wq) { + if (CQE_OPCODE(cqe) == C4IW_DRAIN_OPCODE) { + WARN_ONCE(1, "Unexpected DRAIN CQE qp id %u!\n", wq->sq.qid); + return 0; + } + if (CQE_OPCODE(cqe) == FW_RI_TERMINATE) return 0; diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c index 355e288ec969..38bddd02a943 100644 --- a/drivers/infiniband/hw/cxgb4/qp.c +++ b/drivers/infiniband/hw/cxgb4/qp.c @@ -868,7 +868,12 @@ int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, qhp = to_c4iw_qp(ibqp); spin_lock_irqsave(&qhp->lock, flag); - if (t4_wq_in_error(&qhp->wq)) { + + /* + * If the qp has been flushed, then just insert a special + * drain cqe. + */ + if (qhp->wq.flushed) { spin_unlock_irqrestore(&qhp->lock, flag); complete_sq_drain_wr(qhp, wr); return err; @@ -1011,7 +1016,12 @@ int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, qhp = to_c4iw_qp(ibqp); spin_lock_irqsave(&qhp->lock, flag); - if (t4_wq_in_error(&qhp->wq)) { + + /* + * If the qp has been flushed, then just insert a special + * drain cqe. + */ + if (qhp->wq.flushed) { spin_unlock_irqrestore(&qhp->lock, flag); complete_rq_drain_wr(qhp, wr); return err; -- GitLab From 68a213d325c23d39f109f4c7c824b906a7d209de Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 2 Nov 2017 21:25:24 +0100 Subject: [PATCH 1260/2547] platform/x86: dell-laptop: Fix keyboard max lighting for Dell Latitude E6410 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This machine reports number of keyboard backlight led levels, instead of value of the last led level index. Therefore max_brightness properly needs to be subtracted by 1 to match led max_brightness API. Signed-off-by: Pali Rohár Reported-by: Gabriel M. Elder Link: https://bugzilla.kernel.org/show_bug.cgi?id=196913 Signed-off-by: Darren Hart (VMware) --- drivers/platform/x86/dell-laptop.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/platform/x86/dell-laptop.c b/drivers/platform/x86/dell-laptop.c index bf897b1832b1..cd4725e7e0b5 100644 --- a/drivers/platform/x86/dell-laptop.c +++ b/drivers/platform/x86/dell-laptop.c @@ -37,6 +37,7 @@ struct quirk_entry { u8 touchpad_led; + u8 kbd_led_levels_off_1; int needs_kbd_timeouts; /* @@ -67,6 +68,10 @@ static struct quirk_entry quirk_dell_xps13_9333 = { .kbd_timeouts = { 0, 5, 15, 60, 5 * 60, 15 * 60, -1 }, }; +static struct quirk_entry quirk_dell_latitude_e6410 = { + .kbd_led_levels_off_1 = 1, +}; + static struct platform_driver platform_driver = { .driver = { .name = "dell-laptop", @@ -269,6 +274,15 @@ static const struct dmi_system_id dell_quirks[] __initconst = { }, .driver_data = &quirk_dell_xps13_9333, }, + { + .callback = dmi_matched, + .ident = "Dell Latitude E6410", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "Latitude E6410"), + }, + .driver_data = &quirk_dell_latitude_e6410, + }, { } }; @@ -1149,6 +1163,9 @@ static int kbd_get_info(struct kbd_info *info) units = (buffer->output[2] >> 8) & 0xFF; info->levels = (buffer->output[2] >> 16) & 0xFF; + if (quirks && quirks->kbd_led_levels_off_1 && info->levels) + info->levels--; + if (units & BIT(0)) info->seconds = (buffer->output[3] >> 0) & 0xFF; if (units & BIT(1)) -- GitLab From bff5bf9db1c9453ffd0a78abed3e2d040c092fd9 Mon Sep 17 00:00:00 2001 From: Peter Hutterer Date: Mon, 4 Dec 2017 10:26:17 +1000 Subject: [PATCH 1261/2547] platform/x86: asus-wireless: send an EV_SYN/SYN_REPORT between state changes Sending the switch state change twice within the same frame is invalid evdev protocol and only works if the client handles keys immediately as well. Processing events immediately is incorrect, it forces a fake order of events that does not exist on the device. Recent versions of libinput changed to only process the device state and SYN_REPORT time, so now the key event is lost. https://bugs.freedesktop.org/show_bug.cgi?id=104041 Signed-off-by: Peter Hutterer Signed-off-by: Darren Hart (VMware) --- drivers/platform/x86/asus-wireless.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/platform/x86/asus-wireless.c b/drivers/platform/x86/asus-wireless.c index f3796164329e..d4aeac3477f5 100644 --- a/drivers/platform/x86/asus-wireless.c +++ b/drivers/platform/x86/asus-wireless.c @@ -118,6 +118,7 @@ static void asus_wireless_notify(struct acpi_device *adev, u32 event) return; } input_report_key(data->idev, KEY_RFKILL, 1); + input_sync(data->idev); input_report_key(data->idev, KEY_RFKILL, 0); input_sync(data->idev); } -- GitLab From 532298b95075144bcccf56d792f3fb3fbef2d5d0 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 11 Dec 2017 13:54:27 +0300 Subject: [PATCH 1262/2547] platform/x86: dell-wmi: check for kmalloc() errors This allocation won't fail in the current kernel because it's small but not checking for kmalloc() failures introduces static checker warnings so let's fix it. Signed-off-by: Dan Carpenter Reviewed-by: Mario Limonciello Signed-off-by: Darren Hart (VMware) --- drivers/platform/x86/dell-wmi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/platform/x86/dell-wmi.c b/drivers/platform/x86/dell-wmi.c index 39d2f4518483..fb25b20df316 100644 --- a/drivers/platform/x86/dell-wmi.c +++ b/drivers/platform/x86/dell-wmi.c @@ -639,6 +639,8 @@ static int dell_wmi_events_set_enabled(bool enable) int ret; buffer = kzalloc(sizeof(struct calling_interface_buffer), GFP_KERNEL); + if (!buffer) + return -ENOMEM; buffer->cmd_class = CLASS_INFO; buffer->cmd_select = SELECT_APP_REGISTRATION; buffer->input[0] = 0x10000; -- GitLab From 621f6401fdeefe96dfe9eab4b167c7c39f552bb0 Mon Sep 17 00:00:00 2001 From: Jason Yan Date: Mon, 11 Dec 2017 15:03:33 +0800 Subject: [PATCH 1263/2547] scsi: libsas: fix length error in sas_smp_handler() The return value of smp_execute_task_sg() is the untransferred residual, but bsg_job_done() requires the length of payload received. This makes SMP passthrough commands from userland by sg ioctl to libsas get a wrong response. The userland tools such as smp_utils failed because of these wrong responses: ~#smp_discover /dev/bsg/expander-2\:13 response too short, len=0 ~#smp_discover /dev/bsg/expander-2\:134 response too short, len=0 Fix this by passing the actual received length to bsg_job_done(). And if smp_execute_task_sg() returns 0, this means received length is exactly the buffer length. [mkp: typo] Fixes: 651a01364994 ("scsi: scsi_transport_sas: switch to bsg-lib for SMP passthrough") Cc: # v4.14+ Signed-off-by: Jason Yan Reported-by: chenqilin Tested-by: chenqilin CC: Christoph Hellwig Signed-off-by: Martin K. Petersen --- drivers/scsi/libsas/sas_expander.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/scsi/libsas/sas_expander.c b/drivers/scsi/libsas/sas_expander.c index 174e5eff6155..c7f21661b3cd 100644 --- a/drivers/scsi/libsas/sas_expander.c +++ b/drivers/scsi/libsas/sas_expander.c @@ -2145,7 +2145,7 @@ void sas_smp_handler(struct bsg_job *job, struct Scsi_Host *shost, struct sas_rphy *rphy) { struct domain_device *dev; - unsigned int reslen = 0; + unsigned int rcvlen = 0; int ret = -EINVAL; /* no rphy means no smp target support (ie aic94xx host) */ @@ -2179,12 +2179,12 @@ void sas_smp_handler(struct bsg_job *job, struct Scsi_Host *shost, ret = smp_execute_task_sg(dev, job->request_payload.sg_list, job->reply_payload.sg_list); - if (ret > 0) { - /* positive number is the untransferred residual */ - reslen = ret; + if (ret >= 0) { + /* bsg_job_done() requires the length received */ + rcvlen = job->reply_payload.payload_len - ret; ret = 0; } out: - bsg_job_done(job, ret, reslen); + bsg_job_done(job, ret, rcvlen); } -- GitLab From 3e5c63565aca5fbd1cc150cb2ca77154fc50fa0c Mon Sep 17 00:00:00 2001 From: Johannes Thumshirn Date: Mon, 11 Dec 2017 10:09:30 +0100 Subject: [PATCH 1264/2547] scsi: MAINTAINERS: change FCoE list to linux-scsi fcoe-devel@open-fcoe.org is defunct and all patches are routed via the SCSI tree anyways. So update MAINTAINERS accordingly. Signed-off-by: Johannes Thumshirn Reviewed-by: Bart Van Assche Signed-off-by: Martin K. Petersen --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index cd7e12dc6af4..37841b52a5b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5352,7 +5352,7 @@ F: drivers/media/tuners/fc2580* FCOE SUBSYSTEM (libfc, libfcoe, fcoe) M: Johannes Thumshirn -L: fcoe-devel@open-fcoe.org +L: linux-scsi@vger.kernel.org W: www.Open-FCoE.org S: Supported F: drivers/scsi/libfc/ -- GitLab From 14e3062fb18532175af4d1c4073597999f7a2248 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Tue, 5 Dec 2017 16:57:51 -0800 Subject: [PATCH 1265/2547] scsi: core: Fix a scsi_show_rq() NULL pointer dereference Avoid that scsi_show_rq() triggers a NULL pointer dereference if called after sd_uninit_command(). Swap the NULL pointer assignment and the mempool_free() call in sd_uninit_command() to make it less likely that scsi_show_rq() triggers a use-after-free. Note: even with these changes scsi_show_rq() can trigger a use-after-free but that's a lesser evil than e.g. suppressing debug information for T10 PI Type 2 commands completely. This patch fixes the following oops: BUG: unable to handle kernel NULL pointer dereference at (null) IP: scsi_format_opcode_name+0x1a/0x1c0 CPU: 1 PID: 1881 Comm: cat Not tainted 4.14.0-rc2.blk_mq_io_hang+ #516 Call Trace: __scsi_format_command+0x27/0xc0 scsi_show_rq+0x5c/0xc0 __blk_mq_debugfs_rq_show+0x116/0x130 blk_mq_debugfs_rq_show+0xe/0x10 seq_read+0xfe/0x3b0 full_proxy_read+0x54/0x90 __vfs_read+0x37/0x160 vfs_read+0x96/0x130 SyS_read+0x55/0xc0 entry_SYSCALL_64_fastpath+0x1a/0xa5 [mkp: added Type 2] Fixes: 0eebd005dd07 ("scsi: Implement blk_mq_ops.show_rq()") Reported-by: Ming Lei Signed-off-by: Bart Van Assche Cc: James E.J. Bottomley Cc: Martin K. Petersen Cc: Ming Lei Cc: Christoph Hellwig Cc: Hannes Reinecke Cc: Johannes Thumshirn Cc: stable@vger.kernel.org Signed-off-by: Martin K. Petersen --- drivers/scsi/scsi_debugfs.c | 6 ++++-- drivers/scsi/sd.c | 4 +++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/scsi/scsi_debugfs.c b/drivers/scsi/scsi_debugfs.c index 01f08c03f2c1..c3765d29fd3f 100644 --- a/drivers/scsi/scsi_debugfs.c +++ b/drivers/scsi/scsi_debugfs.c @@ -8,9 +8,11 @@ void scsi_show_rq(struct seq_file *m, struct request *rq) { struct scsi_cmnd *cmd = container_of(scsi_req(rq), typeof(*cmd), req); int msecs = jiffies_to_msecs(jiffies - cmd->jiffies_at_alloc); - char buf[80]; + const u8 *const cdb = READ_ONCE(cmd->cmnd); + char buf[80] = "(?)"; - __scsi_format_command(buf, sizeof(buf), cmd->cmnd, cmd->cmd_len); + if (cdb) + __scsi_format_command(buf, sizeof(buf), cdb, cmd->cmd_len); seq_printf(m, ", .cmd=%s, .retries=%d, allocated %d.%03d s ago", buf, cmd->retries, msecs / 1000, msecs % 1000); } diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c index 24fe68522716..a028ab3322a9 100644 --- a/drivers/scsi/sd.c +++ b/drivers/scsi/sd.c @@ -1312,6 +1312,7 @@ static int sd_init_command(struct scsi_cmnd *cmd) static void sd_uninit_command(struct scsi_cmnd *SCpnt) { struct request *rq = SCpnt->request; + u8 *cmnd; if (SCpnt->flags & SCMD_ZONE_WRITE_LOCK) sd_zbc_write_unlock_zone(SCpnt); @@ -1320,9 +1321,10 @@ static void sd_uninit_command(struct scsi_cmnd *SCpnt) __free_page(rq->special_vec.bv_page); if (SCpnt->cmnd != scsi_req(rq)->cmd) { - mempool_free(SCpnt->cmnd, sd_cdb_pool); + cmnd = SCpnt->cmnd; SCpnt->cmnd = NULL; SCpnt->cmd_len = 0; + mempool_free(cmnd, sd_cdb_pool); } } -- GitLab From d2950278d2d04ff5314abeb38d9c59c4e7c0ee53 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Mon, 11 Dec 2017 18:23:09 +0100 Subject: [PATCH 1266/2547] xfrm: put policies when reusing pcpu xdst entry We need to put the policies when re-using the pcpu xdst entry, else this leaks the reference. Fixes: ec30d78c14a813db39a647b6a348b428 ("xfrm: add xdst pcpu cache") Signed-off-by: Florian Westphal Signed-off-by: Steffen Klassert --- net/xfrm/xfrm_policy.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c index 038ec68f6901..70aa5cb0c659 100644 --- a/net/xfrm/xfrm_policy.c +++ b/net/xfrm/xfrm_policy.c @@ -1839,6 +1839,7 @@ xfrm_resolve_and_create_bundle(struct xfrm_policy **pols, int num_pols, sizeof(struct xfrm_policy *) * num_pols) == 0 && xfrm_xdst_can_reuse(xdst, xfrm, err)) { dst_hold(&xdst->u.dst); + xfrm_pols_put(pols, num_pols); while (err > 0) xfrm_state_put(xfrm[--err]); return xdst; -- GitLab From d2b3c353595a855794f8b9df5b5bdbe8deb0c413 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Mon, 4 Dec 2017 12:11:02 +0300 Subject: [PATCH 1267/2547] pinctrl: cherryview: Mask all interrupts on Intel_Strago based systems Guenter Roeck reported an interrupt storm on a prototype system which is based on Cyan Chromebook. The root cause turned out to be a incorrectly configured pin that triggers spurious interrupts. This will be fixed in coreboot but currently we need to prevent the interrupt storm from happening by masking all interrupts (but not GPEs) on those systems. Link: https://bugzilla.kernel.org/show_bug.cgi?id=197953 Fixes: bcb48cca23ec ("pinctrl: cherryview: Do not mask all interrupts in probe") Reported-and-tested-by: Guenter Roeck Reported-by: Dmitry Torokhov Signed-off-by: Mika Westerberg Cc: stable@vger.kernel.org Signed-off-by: Linus Walleij --- drivers/pinctrl/intel/pinctrl-cherryview.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index bdedb6325c72..4471fd94e1fe 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1620,6 +1620,22 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) clear_bit(i, chip->irq.valid_mask); } + /* + * The same set of machines in chv_no_valid_mask[] have incorrectly + * configured GPIOs that generate spurious interrupts so we use + * this same list to apply another quirk for them. + * + * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953. + */ + if (!need_valid_mask) { + /* + * Mask all interrupts the community is able to generate + * but leave the ones that can only generate GPEs unmasked. + */ + chv_writel(GENMASK(31, pctrl->community->nirqs), + pctrl->regs + CHV_INTMASK); + } + /* Clear all interrupts */ chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); -- GitLab From f87f3a328dbbb3e79dd53e7e889ced9222512649 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 28 Nov 2017 18:42:18 +0000 Subject: [PATCH 1268/2547] locking/core: Fix deadlock during boot on systems with GENERIC_LOCKBREAK Commit: a8a217c22116 ("locking/core: Remove {read,spin,write}_can_lock()") removed the definition of raw_spin_can_lock(), causing the GENERIC_LOCKBREAK spin_lock() routines to poll the ->break_lock field when waiting on a lock. This has been reported to cause a deadlock during boot on s390, because the ->break_lock field is also set by the waiters, and can potentially remain set indefinitely if no other CPUs come in to take the lock after it has been released. This patch removes the explicit spinning on ->break_lock from the waiters, instead relying on the outer trylock() operation to determine when the lock is available. Reported-by: Sebastian Ott Tested-by: Sebastian Ott Signed-off-by: Will Deacon Acked-by: Peter Zijlstra Cc: Heiko Carstens Cc: Linus Torvalds Cc: Martin Schwidefsky Cc: Thomas Gleixner Fixes: a8a217c22116 ("locking/core: Remove {read,spin,write}_can_lock()") Link: http://lkml.kernel.org/r/1511894539-7988-2-git-send-email-will.deacon@arm.com Signed-off-by: Ingo Molnar --- kernel/locking/spinlock.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/kernel/locking/spinlock.c b/kernel/locking/spinlock.c index 1fd1a7543cdd..0ebb253e2199 100644 --- a/kernel/locking/spinlock.c +++ b/kernel/locking/spinlock.c @@ -68,8 +68,8 @@ void __lockfunc __raw_##op##_lock(locktype##_t *lock) \ \ if (!(lock)->break_lock) \ (lock)->break_lock = 1; \ - while ((lock)->break_lock) \ - arch_##op##_relax(&lock->raw_lock); \ + \ + arch_##op##_relax(&lock->raw_lock); \ } \ (lock)->break_lock = 0; \ } \ @@ -88,8 +88,8 @@ unsigned long __lockfunc __raw_##op##_lock_irqsave(locktype##_t *lock) \ \ if (!(lock)->break_lock) \ (lock)->break_lock = 1; \ - while ((lock)->break_lock) \ - arch_##op##_relax(&lock->raw_lock); \ + \ + arch_##op##_relax(&lock->raw_lock); \ } \ (lock)->break_lock = 0; \ return flags; \ -- GitLab From d89c70356acf11b7cf47ca5cfcafae5062a85451 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 28 Nov 2017 18:42:19 +0000 Subject: [PATCH 1269/2547] locking/core: Remove break_lock field when CONFIG_GENERIC_LOCKBREAK=y When CONFIG_GENERIC_LOCKBEAK=y, locking structures grow an extra int ->break_lock field which is used to implement raw_spin_is_contended() by setting the field to 1 when waiting on a lock and clearing it to zero when holding a lock. However, there are a few problems with this approach: - There is a write-write race between a CPU successfully taking the lock (and subsequently writing break_lock = 0) and a waiter waiting on the lock (and subsequently writing break_lock = 1). This could result in a contended lock being reported as uncontended and vice-versa. - On machines with store buffers, nothing guarantees that the writes to break_lock are visible to other CPUs at any particular time. - READ_ONCE/WRITE_ONCE are not used, so the field is potentially susceptible to harmful compiler optimisations, Consequently, the usefulness of this field is unclear and we'd be better off removing it and allowing architectures to implement raw_spin_is_contended() by providing a definition of arch_spin_is_contended(), as they can when CONFIG_GENERIC_LOCKBREAK=n. Signed-off-by: Will Deacon Acked-by: Peter Zijlstra Cc: Heiko Carstens Cc: Linus Torvalds Cc: Martin Schwidefsky Cc: Sebastian Ott Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/1511894539-7988-3-git-send-email-will.deacon@arm.com Signed-off-by: Ingo Molnar --- include/linux/rwlock_types.h | 3 --- include/linux/spinlock.h | 5 ----- include/linux/spinlock_types.h | 3 --- kernel/locking/spinlock.c | 9 +-------- 4 files changed, 1 insertion(+), 19 deletions(-) diff --git a/include/linux/rwlock_types.h b/include/linux/rwlock_types.h index cc0072e93e36..857a72ceb794 100644 --- a/include/linux/rwlock_types.h +++ b/include/linux/rwlock_types.h @@ -10,9 +10,6 @@ */ typedef struct { arch_rwlock_t raw_lock; -#ifdef CONFIG_GENERIC_LOCKBREAK - unsigned int break_lock; -#endif #ifdef CONFIG_DEBUG_SPINLOCK unsigned int magic, owner_cpu; void *owner; diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h index a39186194cd6..3bf273538840 100644 --- a/include/linux/spinlock.h +++ b/include/linux/spinlock.h @@ -107,16 +107,11 @@ do { \ #define raw_spin_is_locked(lock) arch_spin_is_locked(&(lock)->raw_lock) -#ifdef CONFIG_GENERIC_LOCKBREAK -#define raw_spin_is_contended(lock) ((lock)->break_lock) -#else - #ifdef arch_spin_is_contended #define raw_spin_is_contended(lock) arch_spin_is_contended(&(lock)->raw_lock) #else #define raw_spin_is_contended(lock) (((void)(lock), 0)) #endif /*arch_spin_is_contended*/ -#endif /* * This barrier must provide two things: diff --git a/include/linux/spinlock_types.h b/include/linux/spinlock_types.h index 73548eb13a5d..24b4e6f2c1a2 100644 --- a/include/linux/spinlock_types.h +++ b/include/linux/spinlock_types.h @@ -19,9 +19,6 @@ typedef struct raw_spinlock { arch_spinlock_t raw_lock; -#ifdef CONFIG_GENERIC_LOCKBREAK - unsigned int break_lock; -#endif #ifdef CONFIG_DEBUG_SPINLOCK unsigned int magic, owner_cpu; void *owner; diff --git a/kernel/locking/spinlock.c b/kernel/locking/spinlock.c index 0ebb253e2199..936f3d14dd6b 100644 --- a/kernel/locking/spinlock.c +++ b/kernel/locking/spinlock.c @@ -66,12 +66,8 @@ void __lockfunc __raw_##op##_lock(locktype##_t *lock) \ break; \ preempt_enable(); \ \ - if (!(lock)->break_lock) \ - (lock)->break_lock = 1; \ - \ arch_##op##_relax(&lock->raw_lock); \ } \ - (lock)->break_lock = 0; \ } \ \ unsigned long __lockfunc __raw_##op##_lock_irqsave(locktype##_t *lock) \ @@ -86,12 +82,9 @@ unsigned long __lockfunc __raw_##op##_lock_irqsave(locktype##_t *lock) \ local_irq_restore(flags); \ preempt_enable(); \ \ - if (!(lock)->break_lock) \ - (lock)->break_lock = 1; \ - \ arch_##op##_relax(&lock->raw_lock); \ } \ - (lock)->break_lock = 0; \ + \ return flags; \ } \ \ -- GitLab From 6f9fa996c9bf3d86406df95982c7b3def38eb76f Mon Sep 17 00:00:00 2001 From: Joonas Lahtinen Date: Mon, 11 Dec 2017 15:18:14 +0000 Subject: [PATCH 1270/2547] x86/early-quirks: Extend Intel graphics stolen memory placement to 64bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To give upcoming SKU BIOSes more flexibility in placing the Intel graphics stolen memory, make all variables storing the placement or size compatible with full 64 bit range. Signed-off-by: Joonas Lahtinen Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Ville Syrjälä Cc: Chris Wilson Cc: Paulo Zanoni Cc: Thomas Gleixner Cc: Ingo Molnar Cc: H. Peter Anvin Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Chris Wilson Acked-by: Ingo Molnar Link: https://patchwork.freedesktop.org/patch/msgid/20171211151822.20953-2-matthew.auld@intel.com --- arch/x86/kernel/early-quirks.c | 75 +++++++++++++++++----------------- 1 file changed, 38 insertions(+), 37 deletions(-) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 1e82f787c160..a18de5fb9e68 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -243,7 +243,7 @@ static void __init intel_remapping_check(int num, int slot, int func) #define KB(x) ((x) * 1024UL) #define MB(x) (KB (KB (x))) -static size_t __init i830_tseg_size(void) +static resource_size_t __init i830_tseg_size(void) { u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC); @@ -256,7 +256,7 @@ static size_t __init i830_tseg_size(void) return KB(512); } -static size_t __init i845_tseg_size(void) +static resource_size_t __init i845_tseg_size(void) { u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC); u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK; @@ -273,7 +273,7 @@ static size_t __init i845_tseg_size(void) return 0; } -static size_t __init i85x_tseg_size(void) +static resource_size_t __init i85x_tseg_size(void) { u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC); @@ -283,12 +283,12 @@ static size_t __init i85x_tseg_size(void) return MB(1); } -static size_t __init i830_mem_size(void) +static resource_size_t __init i830_mem_size(void) { return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32); } -static size_t __init i85x_mem_size(void) +static resource_size_t __init i85x_mem_size(void) { return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32); } @@ -297,36 +297,36 @@ static size_t __init i85x_mem_size(void) * On 830/845/85x the stolen memory base isn't available in any * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size. */ -static phys_addr_t __init i830_stolen_base(int num, int slot, int func, - size_t stolen_size) +static resource_size_t __init i830_stolen_base(int num, int slot, int func, + resource_size_t stolen_size) { - return (phys_addr_t)i830_mem_size() - i830_tseg_size() - stolen_size; + return i830_mem_size() - i830_tseg_size() - stolen_size; } -static phys_addr_t __init i845_stolen_base(int num, int slot, int func, - size_t stolen_size) +static resource_size_t __init i845_stolen_base(int num, int slot, int func, + resource_size_t stolen_size) { - return (phys_addr_t)i830_mem_size() - i845_tseg_size() - stolen_size; + return i830_mem_size() - i845_tseg_size() - stolen_size; } -static phys_addr_t __init i85x_stolen_base(int num, int slot, int func, - size_t stolen_size) +static resource_size_t __init i85x_stolen_base(int num, int slot, int func, + resource_size_t stolen_size) { - return (phys_addr_t)i85x_mem_size() - i85x_tseg_size() - stolen_size; + return i85x_mem_size() - i85x_tseg_size() - stolen_size; } -static phys_addr_t __init i865_stolen_base(int num, int slot, int func, - size_t stolen_size) +static resource_size_t __init i865_stolen_base(int num, int slot, int func, + resource_size_t stolen_size) { u16 toud = 0; toud = read_pci_config_16(0, 0, 0, I865_TOUD); - return (phys_addr_t)(toud << 16) + i845_tseg_size(); + return toud * KB(64) + i845_tseg_size(); } -static phys_addr_t __init gen3_stolen_base(int num, int slot, int func, - size_t stolen_size) +static resource_size_t __init gen3_stolen_base(int num, int slot, int func, + resource_size_t stolen_size) { u32 bsm; @@ -337,10 +337,10 @@ static phys_addr_t __init gen3_stolen_base(int num, int slot, int func, */ bsm = read_pci_config(num, slot, func, INTEL_BSM); - return (phys_addr_t)bsm & INTEL_BSM_MASK; + return bsm & INTEL_BSM_MASK; } -static size_t __init i830_stolen_size(int num, int slot, int func) +static resource_size_t __init i830_stolen_size(int num, int slot, int func) { u16 gmch_ctrl; u16 gms; @@ -361,7 +361,7 @@ static size_t __init i830_stolen_size(int num, int slot, int func) return 0; } -static size_t __init gen3_stolen_size(int num, int slot, int func) +static resource_size_t __init gen3_stolen_size(int num, int slot, int func) { u16 gmch_ctrl; u16 gms; @@ -390,7 +390,7 @@ static size_t __init gen3_stolen_size(int num, int slot, int func) return 0; } -static size_t __init gen6_stolen_size(int num, int slot, int func) +static resource_size_t __init gen6_stolen_size(int num, int slot, int func) { u16 gmch_ctrl; u16 gms; @@ -398,10 +398,10 @@ static size_t __init gen6_stolen_size(int num, int slot, int func) gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK; - return (size_t)gms * MB(32); + return gms * MB(32); } -static size_t __init gen8_stolen_size(int num, int slot, int func) +static resource_size_t __init gen8_stolen_size(int num, int slot, int func) { u16 gmch_ctrl; u16 gms; @@ -409,10 +409,10 @@ static size_t __init gen8_stolen_size(int num, int slot, int func) gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK; - return (size_t)gms * MB(32); + return gms * MB(32); } -static size_t __init chv_stolen_size(int num, int slot, int func) +static resource_size_t __init chv_stolen_size(int num, int slot, int func) { u16 gmch_ctrl; u16 gms; @@ -426,14 +426,14 @@ static size_t __init chv_stolen_size(int num, int slot, int func) * 0x17 to 0x1d: 4MB increments start at 36MB */ if (gms < 0x11) - return (size_t)gms * MB(32); + return gms * MB(32); else if (gms < 0x17) - return (size_t)(gms - 0x11 + 2) * MB(4); + return (gms - 0x11 + 2) * MB(4); else - return (size_t)(gms - 0x17 + 9) * MB(4); + return (gms - 0x17 + 9) * MB(4); } -static size_t __init gen9_stolen_size(int num, int slot, int func) +static resource_size_t __init gen9_stolen_size(int num, int slot, int func) { u16 gmch_ctrl; u16 gms; @@ -444,14 +444,15 @@ static size_t __init gen9_stolen_size(int num, int slot, int func) /* 0x0 to 0xef: 32MB increments starting at 0MB */ /* 0xf0 to 0xfe: 4MB increments starting at 4MB */ if (gms < 0xf0) - return (size_t)gms * MB(32); + return gms * MB(32); else - return (size_t)(gms - 0xf0 + 1) * MB(4); + return (gms - 0xf0 + 1) * MB(4); } struct intel_early_ops { - size_t (*stolen_size)(int num, int slot, int func); - phys_addr_t (*stolen_base)(int num, int slot, int func, size_t size); + resource_size_t (*stolen_size)(int num, int slot, int func); + resource_size_t (*stolen_base)(int num, int slot, int func, + resource_size_t size); }; static const struct intel_early_ops i830_early_ops __initconst = { @@ -535,8 +536,8 @@ static void __init intel_graphics_stolen(int num, int slot, int func, const struct intel_early_ops *early_ops) { - phys_addr_t base, end; - size_t size; + resource_size_t base, size; + resource_size_t end; size = early_ops->stolen_size(num, slot, func); base = early_ops->stolen_base(num, slot, func, size); -- GitLab From 55f56fc46020ea59273ddb5de0bdc41b7da45c73 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Mon, 11 Dec 2017 15:18:15 +0000 Subject: [PATCH 1271/2547] x86/early-quirks: export the stolen region as a resource MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We duplicate the stolen discovery code in early-quirks and in i915, however if we just export the region as a resource from early-quirks we can nuke the duplication. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Ville Syrjälä Cc: Chris Wilson Cc: Paulo Zanoni Cc: Thomas Gleixner Cc: Ingo Molnar Cc: H. Peter Anvin Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Chris Wilson Acked-by: Ingo Molnar Signed-off-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171211151822.20953-3-matthew.auld@intel.com --- arch/x86/kernel/early-quirks.c | 11 +++++++++-- include/drm/i915_drm.h | 3 +++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index a18de5fb9e68..6c1624889011 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -532,6 +532,9 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_CNL_IDS(&gen9_early_ops), }; +struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0); +EXPORT_SYMBOL(intel_graphics_stolen_res); + static void __init intel_graphics_stolen(int num, int slot, int func, const struct intel_early_ops *early_ops) @@ -546,8 +549,12 @@ intel_graphics_stolen(int num, int slot, int func, return; end = base + size - 1; - printk(KERN_INFO "Reserving Intel graphics memory at %pa-%pa\n", - &base, &end); + + intel_graphics_stolen_res.start = base; + intel_graphics_stolen_res.end = end; + + printk(KERN_INFO "Reserving Intel graphics memory at %pR\n", + &intel_graphics_stolen_res); /* Mark this space as reserved */ e820__range_add(base, size, E820_TYPE_RESERVED); diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index 4e1b274e1164..c9e5a6621b95 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -36,6 +36,9 @@ extern bool i915_gpu_lower(void); extern bool i915_gpu_busy(void); extern bool i915_gpu_turbo_disable(void); +/* Exported from arch/x86/kernel/early-quirks.c */ +extern struct resource intel_graphics_stolen_res; + /* * The Bridge device's PCI config space has information about the * fb aperture size and the amount of pre-reserved memory. -- GitLab From 3b51b6f31aa81c435601ab7eed244a120731c781 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Mon, 11 Dec 2017 15:18:16 +0000 Subject: [PATCH 1272/2547] x86/early-quirks: replace the magical increment start values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the magical +2, +9 etc. with +MB, which is far easier to read. Suggested-by: Ville Syrjälä Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Ville Syrjälä Cc: Chris Wilson Cc: Paulo Zanoni Cc: Thomas Gleixner Cc: Ingo Molnar Cc: H. Peter Anvin Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Ville Syrjälä Acked-by: Ingo Molnar Signed-off-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171211151822.20953-4-matthew.auld@intel.com --- arch/x86/kernel/early-quirks.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 6c1624889011..3cbb2c78a9df 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -428,9 +428,9 @@ static resource_size_t __init chv_stolen_size(int num, int slot, int func) if (gms < 0x11) return gms * MB(32); else if (gms < 0x17) - return (gms - 0x11 + 2) * MB(4); + return (gms - 0x11) * MB(4) + MB(8); else - return (gms - 0x17 + 9) * MB(4); + return (gms - 0x17) * MB(4) + MB(36); } static resource_size_t __init gen9_stolen_size(int num, int slot, int func) @@ -446,7 +446,7 @@ static resource_size_t __init gen9_stolen_size(int num, int slot, int func) if (gms < 0xf0) return gms * MB(32); else - return (gms - 0xf0 + 1) * MB(4); + return (gms - 0xf0) * MB(4) + MB(4); } struct intel_early_ops { -- GitLab From f773568b6ff8c31fce165d177a968f2ae31d10bb Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Mon, 11 Dec 2017 15:18:17 +0000 Subject: [PATCH 1273/2547] drm/i915: nuke the duplicated stolen discovery We duplicate the stolen discovery code in early-quirks and in i915, however now that the stolen region is exported as a resource from early-quirks we can nuke the duplication. v2: check overflows_type Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Paulo Zanoni Reviewed-by: Chris Wilson Signed-off-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171211151822.20953-5-matthew.auld@intel.com --- drivers/gpu/drm/i915/i915_gem_gtt.c | 51 +----------- drivers/gpu/drm/i915/i915_gem_stolen.c | 109 +------------------------ 2 files changed, 5 insertions(+), 155 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 5e7efbbac9f7..c1b8b1c8401e 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2949,50 +2949,6 @@ static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) return 0; } -static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) -{ - snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; - snb_gmch_ctl &= SNB_GMCH_GMS_MASK; - return (size_t)snb_gmch_ctl << 25; /* 32 MB units */ -} - -static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) -{ - bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; - bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; - return (size_t)bdw_gmch_ctl << 25; /* 32 MB units */ -} - -static size_t chv_get_stolen_size(u16 gmch_ctrl) -{ - gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; - gmch_ctrl &= SNB_GMCH_GMS_MASK; - - /* - * 0x0 to 0x10: 32MB increments starting at 0MB - * 0x11 to 0x16: 4MB increments starting at 8MB - * 0x17 to 0x1d: 4MB increments start at 36MB - */ - if (gmch_ctrl < 0x11) - return (size_t)gmch_ctrl << 25; - else if (gmch_ctrl < 0x17) - return (size_t)(gmch_ctrl - 0x11 + 2) << 22; - else - return (size_t)(gmch_ctrl - 0x17 + 9) << 22; -} - -static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) -{ - gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; - gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; - - if (gen9_gmch_ctl < 0xf0) - return (size_t)gen9_gmch_ctl << 25; /* 32 MB units */ - else - /* 4MB increments starting at 0xf0 for 4MB */ - return (size_t)(gen9_gmch_ctl - 0xf0 + 1) << 22; -} - static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) { struct drm_i915_private *dev_priv = ggtt->base.i915; @@ -3343,14 +3299,13 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); + ggtt->stolen_size = resource_size(&intel_graphics_stolen_res); + if (INTEL_GEN(dev_priv) >= 9) { - ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); size = gen8_get_total_gtt_size(snb_gmch_ctl); } else if (IS_CHERRYVIEW(dev_priv)) { - ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); size = chv_get_total_gtt_size(snb_gmch_ctl); } else { - ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); size = gen8_get_total_gtt_size(snb_gmch_ctl); } @@ -3408,7 +3363,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err); pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); - ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); + ggtt->stolen_size = resource_size(&intel_graphics_stolen_res); size = gen6_get_total_gtt_size(snb_gmch_ctl); ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index 1877ae9a1d9b..f8ac1438c35d 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -30,9 +30,6 @@ #include #include "i915_drv.h" -#define KB(x) ((x) * 1024) -#define MB(x) (KB(x) * 1024) - /* * The BIOS typically reserves some of the system's memory for the exclusive * use of the integrated graphics. This memory is no longer available for @@ -81,113 +78,11 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv) { - struct pci_dev *pdev = dev_priv->drm.pdev; struct i915_ggtt *ggtt = &dev_priv->ggtt; + dma_addr_t base = intel_graphics_stolen_res.start; struct resource *r; - dma_addr_t base; - - /* Almost universally we can find the Graphics Base of Stolen Memory - * at register BSM (0x5c) in the igfx configuration space. On a few - * (desktop) machines this is also mirrored in the bridge device at - * different locations, or in the MCHBAR. - * - * On 865 we just check the TOUD register. - * - * On 830/845/85x the stolen memory base isn't available in any - * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size. - * - */ - base = 0; - if (INTEL_GEN(dev_priv) >= 3) { - u32 bsm; - - pci_read_config_dword(pdev, INTEL_BSM, &bsm); - - base = bsm & INTEL_BSM_MASK; - } else if (IS_I865G(dev_priv)) { - u32 tseg_size = 0; - u16 toud = 0; - u8 tmp; - - pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 0), - I845_ESMRAMC, &tmp); - - if (tmp & TSEG_ENABLE) { - switch (tmp & I845_TSEG_SIZE_MASK) { - case I845_TSEG_SIZE_512K: - tseg_size = KB(512); - break; - case I845_TSEG_SIZE_1M: - tseg_size = MB(1); - break; - } - } - - pci_bus_read_config_word(pdev->bus, PCI_DEVFN(0, 0), - I865_TOUD, &toud); - - base = (toud << 16) + tseg_size; - } else if (IS_I85X(dev_priv)) { - u32 tseg_size = 0; - u32 tom; - u8 tmp; - - pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 0), - I85X_ESMRAMC, &tmp); - - if (tmp & TSEG_ENABLE) - tseg_size = MB(1); - - pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 1), - I85X_DRB3, &tmp); - tom = tmp * MB(32); - - base = tom - tseg_size - ggtt->stolen_size; - } else if (IS_I845G(dev_priv)) { - u32 tseg_size = 0; - u32 tom; - u8 tmp; - - pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 0), - I845_ESMRAMC, &tmp); - - if (tmp & TSEG_ENABLE) { - switch (tmp & I845_TSEG_SIZE_MASK) { - case I845_TSEG_SIZE_512K: - tseg_size = KB(512); - break; - case I845_TSEG_SIZE_1M: - tseg_size = MB(1); - break; - } - } - - pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 0), - I830_DRB3, &tmp); - tom = tmp * MB(32); - base = tom - tseg_size - ggtt->stolen_size; - } else if (IS_I830(dev_priv)) { - u32 tseg_size = 0; - u32 tom; - u8 tmp; - - pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 0), - I830_ESMRAMC, &tmp); - - if (tmp & TSEG_ENABLE) { - if (tmp & I830_TSEG_SIZE_1M) - tseg_size = MB(1); - else - tseg_size = KB(512); - } - - pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 0), - I830_DRB3, &tmp); - tom = tmp * MB(32); - - base = tom - tseg_size - ggtt->stolen_size; - } + GEM_BUG_ON(overflows_type(intel_graphics_stolen_res.start, base)); if (base == 0 || add_overflows(base, ggtt->stolen_size)) return 0; -- GitLab From 7789422665f59982743a32a7728a448c9ddd4003 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Mon, 11 Dec 2017 15:18:18 +0000 Subject: [PATCH 1274/2547] drm/i915: make dsm struct resource centric Now that we are using struct resource to track the stolen region, it is more convenient if we track dsm in a resource as well. v2: check range_overflow when writing to 32b registers (Chris) pepper in some comments (Chris) v3: refit i915_stolen_to_dma() v4: kill ggtt->stolen_size v5: some more polish Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Paulo Zanoni Reviewed-by: Chris Wilson Signed-off-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171211151822.20953-6-matthew.auld@intel.com --- drivers/char/agp/intel-gtt.c | 2 - drivers/gpu/drm/i915/i915_drv.h | 12 ++- drivers/gpu/drm/i915/i915_gem_gtt.c | 8 +- drivers/gpu/drm/i915/i915_gem_gtt.h | 1 - drivers/gpu/drm/i915/i915_gem_stolen.c | 125 ++++++++++++------------- drivers/gpu/drm/i915/intel_fbc.c | 13 ++- drivers/gpu/drm/i915/intel_pm.c | 15 +-- include/drm/intel-gtt.h | 1 - 8 files changed, 89 insertions(+), 88 deletions(-) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index dde7caac7f9f..0c86b4dfd59c 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -1424,12 +1424,10 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, EXPORT_SYMBOL(intel_gmch_probe); void intel_gtt_get(u64 *gtt_total, - u32 *stolen_size, phys_addr_t *mappable_base, u64 *mappable_end) { *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT; - *stolen_size = intel_private.stolen_size; *mappable_base = intel_private.gma_bus_addr; *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d57859cfad8e..1677b7e0d671 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1538,9 +1538,6 @@ struct i915_gem_mm { */ struct pagevec wc_stash; - /** Usable portion of the GTT for GEM */ - dma_addr_t stolen_base; /* limited to low memory (32-bit) */ - /** * tmpfs instance used for shmem backed objects */ @@ -2254,6 +2251,15 @@ struct drm_i915_private { const struct intel_device_info info; + /** + * Data Stolen Memory - aka "i915 stolen memory" gives us the start and + * end of stolen which we can optionally use to create GEM objects + * backed by stolen memory. Note that ggtt->stolen_usable_size tells us + * exactly how much of this we are actually allowed to use, given that + * some portion of it is in fact reserved for use by hardware functions. + */ + struct resource dsm; + void __iomem *regs; struct intel_uncore uncore; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index c1b8b1c8401e..7a5302318d31 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3299,8 +3299,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); - ggtt->stolen_size = resource_size(&intel_graphics_stolen_res); - if (INTEL_GEN(dev_priv) >= 9) { size = gen8_get_total_gtt_size(snb_gmch_ctl); } else if (IS_CHERRYVIEW(dev_priv)) { @@ -3363,8 +3361,6 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err); pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); - ggtt->stolen_size = resource_size(&intel_graphics_stolen_res); - size = gen6_get_total_gtt_size(snb_gmch_ctl); ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; @@ -3410,7 +3406,6 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt) } intel_gtt_get(&ggtt->base.total, - &ggtt->stolen_size, &ggtt->mappable_base, &ggtt->mappable_end); @@ -3482,7 +3477,8 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) DRM_INFO("Memory usable by graphics device = %lluM\n", ggtt->base.total >> 20); DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); - DRM_DEBUG_DRIVER("GTT stolen size = %uM\n", ggtt->stolen_size >> 20); + DRM_DEBUG_DRIVER("GTT stolen size = %lluM\n", + (u64)resource_size(&intel_graphics_stolen_res) >> 20); if (intel_vtd_active()) DRM_INFO("VT-d active for gfx access\n"); diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 93211a96fdad..30a2920b1291 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -381,7 +381,6 @@ struct i915_ggtt { * avoid the first page! The upper end of stolen memory is reserved for * hardware functions and similarly removed from the accessible range. */ - u32 stolen_size; /* Total size of stolen memory */ u32 stolen_usable_size; /* Total size minus reserved ranges */ u32 stolen_reserved_base; u32 stolen_reserved_size; diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index f8ac1438c35d..5b5558fe70cc 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -76,27 +76,26 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, mutex_unlock(&dev_priv->mm.stolen_lock); } -static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv) +static int i915_adjust_stolen(struct drm_i915_private *dev_priv, + struct resource *dsm) { struct i915_ggtt *ggtt = &dev_priv->ggtt; - dma_addr_t base = intel_graphics_stolen_res.start; struct resource *r; - GEM_BUG_ON(overflows_type(intel_graphics_stolen_res.start, base)); + if (dsm->start == 0 || dsm->end <= dsm->start) + return -EINVAL; - if (base == 0 || add_overflows(base, ggtt->stolen_size)) - return 0; + /* + * TODO: We have yet too encounter the case where the GTT wasn't at the + * end of stolen. With that assumption we could simplify this. + */ - /* make sure we don't clobber the GTT if it's within stolen memory */ + /* Make sure we don't clobber the GTT if it's within stolen memory */ if (INTEL_GEN(dev_priv) <= 4 && !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv)) { - struct { - dma_addr_t start, end; - } stolen[2] = { - { .start = base, .end = base + ggtt->stolen_size, }, - { .start = base, .end = base + ggtt->stolen_size, }, - }; - u64 ggtt_start, ggtt_end; + struct resource stolen[2] = {*dsm, *dsm}; + struct resource ggtt_res; + u64 ggtt_start; ggtt_start = I915_READ(PGTBL_CTL); if (IS_GEN4(dev_priv)) @@ -104,70 +103,64 @@ static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv) (ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28; else ggtt_start &= PGTBL_ADDRESS_LO_MASK; - ggtt_end = ggtt_start + ggtt_total_entries(ggtt) * 4; - - if (ggtt_start >= stolen[0].start && ggtt_start < stolen[0].end) - stolen[0].end = ggtt_start; - if (ggtt_end > stolen[1].start && ggtt_end <= stolen[1].end) - stolen[1].start = ggtt_end; - - /* pick the larger of the two chunks */ - if (stolen[0].end - stolen[0].start > - stolen[1].end - stolen[1].start) { - base = stolen[0].start; - ggtt->stolen_size = stolen[0].end - stolen[0].start; - } else { - base = stolen[1].start; - ggtt->stolen_size = stolen[1].end - stolen[1].start; - } + + ggtt_res = + (struct resource) DEFINE_RES_MEM(ggtt_start, + ggtt_total_entries(ggtt) * 4); + + if (ggtt_res.start >= stolen[0].start && ggtt_res.start < stolen[0].end) + stolen[0].end = ggtt_res.start; + if (ggtt_res.end > stolen[1].start && ggtt_res.end <= stolen[1].end) + stolen[1].start = ggtt_res.end; + + /* Pick the larger of the two chunks */ + if (resource_size(&stolen[0]) > resource_size(&stolen[1])) + *dsm = stolen[0]; + else + *dsm = stolen[1]; if (stolen[0].start != stolen[1].start || stolen[0].end != stolen[1].end) { - dma_addr_t end = base + ggtt->stolen_size - 1; - - DRM_DEBUG_KMS("GTT within stolen memory at 0x%llx-0x%llx\n", - (unsigned long long)ggtt_start, - (unsigned long long)ggtt_end - 1); - DRM_DEBUG_KMS("Stolen memory adjusted to %pad - %pad\n", - &base, &end); + DRM_DEBUG_KMS("GTT within stolen memory at %pR\n", &ggtt_res); + DRM_DEBUG_KMS("Stolen memory adjusted to %pR\n", dsm); } } - - /* Verify that nothing else uses this physical address. Stolen + /* + * Verify that nothing else uses this physical address. Stolen * memory should be reserved by the BIOS and hidden from the * kernel. So if the region is already marked as busy, something * is seriously wrong. */ - r = devm_request_mem_region(dev_priv->drm.dev, base, ggtt->stolen_size, + r = devm_request_mem_region(dev_priv->drm.dev, dsm->start, + resource_size(dsm), "Graphics Stolen Memory"); if (r == NULL) { /* * One more attempt but this time requesting region from - * base + 1, as we have seen that this resolves the region + * start + 1, as we have seen that this resolves the region * conflict with the PCI Bus. * This is a BIOS w/a: Some BIOS wrap stolen in the root * PCI bus, but have an off-by-one error. Hence retry the * reservation starting from 1 instead of 0. * There's also BIOS with off-by-one on the other end. */ - r = devm_request_mem_region(dev_priv->drm.dev, base + 1, - ggtt->stolen_size - 2, + r = devm_request_mem_region(dev_priv->drm.dev, dsm->start + 1, + resource_size(dsm) - 2, "Graphics Stolen Memory"); /* * GEN3 firmware likes to smash pci bridges into the stolen * range. Apparently this works. */ if (r == NULL && !IS_GEN3(dev_priv)) { - dma_addr_t end = base + ggtt->stolen_size; + DRM_ERROR("conflict detected with stolen region: %pR\n", + dsm); - DRM_ERROR("conflict detected with stolen region: [%pad - %pad]\n", - &base, &end); - base = 0; + return -EBUSY; } } - return base; + return 0; } void i915_gem_cleanup_stolen(struct drm_device *dev) @@ -183,11 +176,10 @@ void i915_gem_cleanup_stolen(struct drm_device *dev) static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv, dma_addr_t *base, u32 *size) { - struct i915_ggtt *ggtt = &dev_priv->ggtt; uint32_t reg_val = I915_READ(IS_GM45(dev_priv) ? CTG_STOLEN_RESERVED : ELK_STOLEN_RESERVED); - dma_addr_t stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size; + dma_addr_t stolen_top = dev_priv->dsm.end + 1; if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0) { *base = 0; @@ -308,7 +300,6 @@ static void chv_get_stolen_reserved(struct drm_i915_private *dev_priv, static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv, dma_addr_t *base, u32 *size) { - struct i915_ggtt *ggtt = &dev_priv->ggtt; uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED); dma_addr_t stolen_top; @@ -318,7 +309,7 @@ static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv, return; } - stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size; + stolen_top = dev_priv->dsm.end + 1; *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK; @@ -351,14 +342,18 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) return 0; } - if (ggtt->stolen_size == 0) + if (resource_size(&intel_graphics_stolen_res) == 0) return 0; - dev_priv->mm.stolen_base = i915_stolen_to_dma(dev_priv); - if (dev_priv->mm.stolen_base == 0) + dev_priv->dsm = intel_graphics_stolen_res; + + if (i915_adjust_stolen(dev_priv, &dev_priv->dsm)) return 0; - stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size; + GEM_BUG_ON(dev_priv->dsm.start == 0); + GEM_BUG_ON(dev_priv->dsm.end <= dev_priv->dsm.start); + + stolen_top = dev_priv->dsm.end + 1; reserved_base = 0; reserved_size = 0; @@ -399,12 +394,11 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) reserved_base = stolen_top; } - if (reserved_base < dev_priv->mm.stolen_base || + if (reserved_base < dev_priv->dsm.start || reserved_base + reserved_size > stolen_top) { dma_addr_t reserved_top = reserved_base + reserved_size; - DRM_ERROR("Stolen reserved area [%pad - %pad] outside stolen memory [%pad - %pad]\n", - &reserved_base, &reserved_top, - &dev_priv->mm.stolen_base, &stolen_top); + DRM_ERROR("Stolen reserved area [%pad - %pad] outside stolen memory %pR\n", + &reserved_base, &reserved_top, &dev_priv->dsm); return 0; } @@ -415,9 +409,9 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) * memory, so just consider the start. */ reserved_total = stolen_top - reserved_base; - DRM_DEBUG_KMS("Memory reserved for graphics device: %uK, usable: %uK\n", - ggtt->stolen_size >> 10, - (ggtt->stolen_size - reserved_total) >> 10); + DRM_DEBUG_KMS("Memory reserved for graphics device: %lluK, usable: %lluK\n", + (u64)resource_size(&dev_priv->dsm) >> 10, + ((u64)resource_size(&dev_priv->dsm) - reserved_total) >> 10); stolen_usable_start = 0; /* WaSkipStolenMemoryFirstPage:bdw+ */ @@ -425,7 +419,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) stolen_usable_start = 4096; ggtt->stolen_usable_size = - ggtt->stolen_size - reserved_total - stolen_usable_start; + resource_size(&dev_priv->dsm) - reserved_total - stolen_usable_start; /* Basic memrange allocator for stolen space. */ drm_mm_init(&dev_priv->mm.stolen, stolen_usable_start, @@ -442,7 +436,8 @@ i915_pages_create_for_stolen(struct drm_device *dev, struct sg_table *st; struct scatterlist *sg; - GEM_BUG_ON(range_overflows(offset, size, dev_priv->ggtt.stolen_size)); + GEM_BUG_ON(range_overflows_t(resource_size_t, offset, size, + resource_size(&dev_priv->dsm))); /* We hide that we have no struct page backing our stolen object * by wrapping the contiguous physical allocation with a fake @@ -462,7 +457,7 @@ i915_pages_create_for_stolen(struct drm_device *dev, sg->offset = 0; sg->length = size; - sg_dma_address(sg) = (dma_addr_t)dev_priv->mm.stolen_base + offset; + sg_dma_address(sg) = (dma_addr_t)dev_priv->dsm.start + offset; sg_dma_len(sg) = size; return st; diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 4aefc658a5cf..f88c1b5dae4c 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -531,7 +531,6 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, int size, int fb_cpp) { - struct i915_ggtt *ggtt = &dev_priv->ggtt; int compression_threshold = 1; int ret; u64 end; @@ -541,7 +540,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, * If we enable FBC using a CFB on that memory range we'll get FIFO * underruns, even if that range is not reserved by the BIOS. */ if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv)) - end = ggtt->stolen_size - 8 * 1024 * 1024; + end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024; else end = U64_MAX; @@ -615,10 +614,16 @@ static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) fbc->compressed_llb = compressed_llb; + GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start, + fbc->compressed_fb.start, + U32_MAX)); + GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start, + fbc->compressed_llb->start, + U32_MAX)); I915_WRITE(FBC_CFB_BASE, - dev_priv->mm.stolen_base + fbc->compressed_fb.start); + dev_priv->dsm.start + fbc->compressed_fb.start); I915_WRITE(FBC_LL_BASE, - dev_priv->mm.stolen_base + compressed_llb->start); + dev_priv->dsm.start + compressed_llb->start); } DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5836181d6f8a..79b3fd617de0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7020,7 +7020,7 @@ static void valleyview_check_pctx(struct drm_i915_private *dev_priv) { unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; - WARN_ON(pctx_addr != dev_priv->mm.stolen_base + + WARN_ON(pctx_addr != dev_priv->dsm.start + dev_priv->vlv_pctx->stolen->start); } @@ -7035,7 +7035,6 @@ static void cherryview_check_pctx(struct drm_i915_private *dev_priv) static void cherryview_setup_pctx(struct drm_i915_private *dev_priv) { - struct i915_ggtt *ggtt = &dev_priv->ggtt; unsigned long pctx_paddr, paddr; u32 pcbr; int pctx_size = 32*1024; @@ -7043,8 +7042,8 @@ static void cherryview_setup_pctx(struct drm_i915_private *dev_priv) pcbr = I915_READ(VLV_PCBR); if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); - paddr = (dev_priv->mm.stolen_base + - (ggtt->stolen_size - pctx_size)); + paddr = dev_priv->dsm.end + 1 - pctx_size; + GEM_BUG_ON(paddr > U32_MAX); pctx_paddr = (paddr & (~4095)); I915_WRITE(VLV_PCBR, pctx_paddr); @@ -7065,7 +7064,7 @@ static void valleyview_setup_pctx(struct drm_i915_private *dev_priv) /* BIOS set it up already, grab the pre-alloc'd space */ int pcbr_offset; - pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; + pcbr_offset = (pcbr & (~4095)) - dev_priv->dsm.start; pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv, pcbr_offset, I915_GTT_OFFSET_NONE, @@ -7089,7 +7088,11 @@ static void valleyview_setup_pctx(struct drm_i915_private *dev_priv) goto out; } - pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; + GEM_BUG_ON(range_overflows_t(u64, + dev_priv->dsm.start, + pctx->stolen->start, + U32_MAX)); + pctx_paddr = dev_priv->dsm.start + pctx->stolen->start; I915_WRITE(VLV_PCBR, pctx_paddr); out: diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h index c5db7975c640..8c577ca38e2e 100644 --- a/include/drm/intel-gtt.h +++ b/include/drm/intel-gtt.h @@ -5,7 +5,6 @@ #define _DRM_INTEL_GTT_H void intel_gtt_get(u64 *gtt_total, - u32 *stolen_size, phys_addr_t *mappable_base, u64 *mappable_end); -- GitLab From 17a053454b247e056214013a40cca7bdf4e340c2 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Mon, 11 Dec 2017 15:18:19 +0000 Subject: [PATCH 1275/2547] drm/i915: make reserved struct resource centric Now that we are using struct resource to track the stolen region, it is more convenient if we track the reserved portion of that region in a resource as well. v2: s/<= end + 1/< end/ (Chris) v3: prefer DEFINE_RES_MEM Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Paulo Zanoni Reviewed-by: Chris Wilson Signed-off-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171211151822.20953-7-matthew.auld@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 4 ++++ drivers/gpu/drm/i915/i915_gem_gtt.h | 2 -- drivers/gpu/drm/i915/i915_gem_stolen.c | 14 ++++++-------- drivers/gpu/drm/i915/intel_pm.c | 6 ++---- 4 files changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1677b7e0d671..7945af0037f8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2259,6 +2259,10 @@ struct drm_i915_private { * some portion of it is in fact reserved for use by hardware functions. */ struct resource dsm; + /** + * Reseved portion of Data Stolen Memory + */ + struct resource dsm_reserved; void __iomem *regs; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 30a2920b1291..db20c72ecfc8 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -382,8 +382,6 @@ struct i915_ggtt { * hardware functions and similarly removed from the accessible range. */ u32 stolen_usable_size; /* Total size minus reserved ranges */ - u32 stolen_reserved_base; - u32 stolen_reserved_size; /** "Graphics Stolen Memory" holds the global PTEs */ void __iomem *gsm; diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index 5b5558fe70cc..b6cca0d4ecd3 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -394,17 +394,15 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) reserved_base = stolen_top; } - if (reserved_base < dev_priv->dsm.start || - reserved_base + reserved_size > stolen_top) { - dma_addr_t reserved_top = reserved_base + reserved_size; - DRM_ERROR("Stolen reserved area [%pad - %pad] outside stolen memory %pR\n", - &reserved_base, &reserved_top, &dev_priv->dsm); + dev_priv->dsm_reserved = + (struct resource) DEFINE_RES_MEM(reserved_base, reserved_size); + + if (!resource_contains(&dev_priv->dsm, &dev_priv->dsm_reserved)) { + DRM_ERROR("Stolen reserved area %pR outside stolen memory %pR\n", + &dev_priv->dsm_reserved, &dev_priv->dsm); return 0; } - ggtt->stolen_reserved_base = reserved_base; - ggtt->stolen_reserved_size = reserved_size; - /* It is possible for the reserved area to end before the end of stolen * memory, so just consider the start. */ reserved_total = stolen_top - reserved_base; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 79b3fd617de0..57dcf8e1ff30 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6416,7 +6416,6 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv) static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv) { - struct i915_ggtt *ggtt = &dev_priv->ggtt; bool enable_rc6 = true; unsigned long rc6_ctx_base; u32 rc_ctl; @@ -6441,9 +6440,8 @@ static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv) * for this check. */ rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK; - if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) && - (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base + - ggtt->stolen_reserved_size))) { + if (!((rc6_ctx_base >= dev_priv->dsm_reserved.start) && + (rc6_ctx_base + PAGE_SIZE < dev_priv->dsm_reserved.end))) { DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n"); enable_rc6 = false; } -- GitLab From 73ebd503034c1abe31137df02dd4493eb7a522d4 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Mon, 11 Dec 2017 15:18:20 +0000 Subject: [PATCH 1276/2547] drm/i915: make mappable struct resource centric Now that we are using struct resource to track the stolen region, it is more convenient if we track the mappable region in a resource as well. v2: prefer iomap and gmadr naming scheme prefer DEFINE_RES_MEM Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Paulo Zanoni Reviewed-by: Chris Wilson Signed-off-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171211151822.20953-8-matthew.auld@intel.com --- drivers/gpu/drm/i915/gvt/gvt.h | 2 +- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_gem.c | 8 ++--- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 29 ++++++++++++------- drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_vma.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_overlay.c | 4 +-- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +-- drivers/gpu/drm/i915/selftests/mock_gtt.c | 4 +-- 12 files changed, 37 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 77df9bad5dea..103910a24e4b 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -348,7 +348,7 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt); /* Aperture/GM space definitions for GVT device */ #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) -#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base) +#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start) #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total) #define gvt_ggtt_sz(gvt) \ diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 5b1fd5f1defb..54a8fca7e7b2 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -726,7 +726,7 @@ static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) if (!ap) return -ENOMEM; - ap->ranges[0].base = ggtt->mappable_base; + ap->ranges[0].base = ggtt->gmadr.start; ap->ranges[0].size = ggtt->mappable_end; primary = diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fcc9b53864f0..e89496aec857 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1116,7 +1116,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj, page_base += offset & PAGE_MASK; } - if (gtt_user_read(&ggtt->mappable, page_base, page_offset, + if (gtt_user_read(&ggtt->iomap, page_base, page_offset, user_data, page_length)) { ret = -EFAULT; break; @@ -1324,7 +1324,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, * If the object is non-shmem backed, we retry again with the * path that handles page fault. */ - if (ggtt_write(&ggtt->mappable, page_base, page_offset, + if (ggtt_write(&ggtt->iomap, page_base, page_offset, user_data, page_length)) { ret = -EFAULT; break; @@ -1967,9 +1967,9 @@ int i915_gem_fault(struct vm_fault *vmf) /* Finally, remap it using the new GTT offset */ ret = remap_io_mapping(area, area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT), - (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT, + (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT, min_t(u64, vma->size, area->vm_end - area->vm_start), - &ggtt->mappable); + &ggtt->iomap); if (ret) goto err_fence; diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 70ccd63cbf8e..4401068ff468 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1012,7 +1012,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, offset += page << PAGE_SHIFT; } - vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->mappable, + vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap, offset); cache->page = page; cache->vaddr = (unsigned long)vaddr; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 7a5302318d31..fbc1f467273a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2912,7 +2912,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) mutex_unlock(&dev_priv->drm.struct_mutex); arch_phys_wc_del(ggtt->mtrr); - io_mapping_fini(&ggtt->mappable); + io_mapping_fini(&ggtt->iomap); } static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) @@ -3288,8 +3288,10 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) int err; /* TODO: We're not aware of mappable constraints on gen8 yet */ - ggtt->mappable_base = pci_resource_start(pdev, 2); - ggtt->mappable_end = pci_resource_len(pdev, 2); + ggtt->gmadr = + (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2), + pci_resource_len(pdev, 2)); + ggtt->mappable_end = resource_size(&ggtt->gmadr); err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39)); if (!err) @@ -3343,8 +3345,10 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) u16 snb_gmch_ctl; int err; - ggtt->mappable_base = pci_resource_start(pdev, 2); - ggtt->mappable_end = pci_resource_len(pdev, 2); + ggtt->gmadr = + (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2), + pci_resource_len(pdev, 2)); + ggtt->mappable_end = resource_size(&ggtt->gmadr); /* 64/512MB is the current min/max we actually know of, but this is just * a coarse sanity check. @@ -3397,6 +3401,7 @@ static void i915_gmch_remove(struct i915_address_space *vm) static int i915_gmch_probe(struct i915_ggtt *ggtt) { struct drm_i915_private *dev_priv = ggtt->base.i915; + phys_addr_t gmadr_base; int ret; ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); @@ -3406,9 +3411,13 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt) } intel_gtt_get(&ggtt->base.total, - &ggtt->mappable_base, + &gmadr_base, &ggtt->mappable_end); + ggtt->gmadr = + (struct resource) DEFINE_RES_MEM(gmadr_base, + ggtt->mappable_end); + ggtt->do_idle_maps = needs_idle_maps(dev_priv); ggtt->base.insert_page = i915_ggtt_insert_page; ggtt->base.insert_entries = i915_ggtt_insert_entries; @@ -3476,7 +3485,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) /* GMADR is the PCI mmio aperture into the global GTT. */ DRM_INFO("Memory usable by graphics device = %lluM\n", ggtt->base.total >> 20); - DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); + DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20); DRM_DEBUG_DRIVER("GTT stolen size = %lluM\n", (u64)resource_size(&intel_graphics_stolen_res) >> 20); if (intel_vtd_active()) @@ -3507,14 +3516,14 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) ggtt->base.mm.color_adjust = i915_gtt_color_adjust; mutex_unlock(&dev_priv->drm.struct_mutex); - if (!io_mapping_init_wc(&dev_priv->ggtt.mappable, - dev_priv->ggtt.mappable_base, + if (!io_mapping_init_wc(&dev_priv->ggtt.iomap, + dev_priv->ggtt.gmadr.start, dev_priv->ggtt.mappable_end)) { ret = -EIO; goto out_gtt_cleanup; } - ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end); + ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end); /* * Initialise stolen early so that we may reserve preallocated diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index db20c72ecfc8..4a17ce36281a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -368,9 +368,9 @@ i915_vm_has_scratch_64K(struct i915_address_space *vm) */ struct i915_ggtt { struct i915_address_space base; - struct io_mapping mappable; /* Mapping to our CPU mappable region */ - phys_addr_t mappable_base; /* PA of our GMADR */ + struct io_mapping iomap; /* Mapping to our CPU mappable region */ + struct resource gmadr; /* GMADR resource */ u64 mappable_end; /* End offset that we can CPU map */ /* Stolen memory is segmented in hardware with different portions diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 48418fb81066..aba50aa613f1 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -956,7 +956,7 @@ i915_error_object_create(struct drm_i915_private *i915, ggtt->base.insert_page(&ggtt->base, dma, slot, I915_CACHE_NONE, 0); - s = io_mapping_map_atomic_wc(&ggtt->mappable, slot); + s = io_mapping_map_atomic_wc(&ggtt->iomap, slot); ret = compress_page(&compress, (void __force *)s, dst); io_mapping_unmap_atomic(s); diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 92c11e70fea4..e0e7c48f45dc 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -311,7 +311,7 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma) ptr = vma->iomap; if (ptr == NULL) { - ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->mappable, + ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap, vma->node.start, vma->node.size); if (ptr == NULL) { diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f0a8686f0513..f9ff1c7fa054 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14595,7 +14595,7 @@ int intel_modeset_init(struct drm_device *dev) dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; } - dev->mode_config.fb_base = ggtt->mappable_base; + dev->mode_config.fb_base = ggtt->gmadr.start; DRM_DEBUG_KMS("%d display pipe%s available.\n", INTEL_INFO(dev_priv)->num_pipes, diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 1b397b41cb4f..41e9465d44a8 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -219,7 +219,7 @@ intel_overlay_map_regs(struct intel_overlay *overlay) if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr; else - regs = io_mapping_map_wc(&dev_priv->ggtt.mappable, + regs = io_mapping_map_wc(&dev_priv->ggtt.iomap, overlay->flip_addr, PAGE_SIZE); @@ -1508,7 +1508,7 @@ intel_overlay_map_regs_atomic(struct intel_overlay *overlay) regs = (struct overlay_registers __iomem *) overlay->reg_bo->phys_handle->vaddr; else - regs = io_mapping_map_atomic_wc(&dev_priv->ggtt.mappable, + regs = io_mapping_map_atomic_wc(&dev_priv->ggtt.iomap, overlay->flip_addr); return regs; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c index 6491cf0a4f46..4a28d713a7d8 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c @@ -1074,7 +1074,7 @@ static int igt_ggtt_page(void *arg) i915_gem_object_get_dma_address(obj, 0), offset, I915_CACHE_NONE, 0); - vaddr = io_mapping_map_atomic_wc(&ggtt->mappable, offset); + vaddr = io_mapping_map_atomic_wc(&ggtt->iomap, offset); iowrite32(n, vaddr + n); io_mapping_unmap_atomic(vaddr); @@ -1092,7 +1092,7 @@ static int igt_ggtt_page(void *arg) i915_gem_object_get_dma_address(obj, 0), offset, I915_CACHE_NONE, 0); - vaddr = io_mapping_map_atomic_wc(&ggtt->mappable, offset); + vaddr = io_mapping_map_atomic_wc(&ggtt->iomap, offset); val = ioread32(vaddr + n); io_mapping_unmap_atomic(vaddr); diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c index 336e1afb250f..e96873f96116 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gtt.c +++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c @@ -110,8 +110,8 @@ void mock_init_ggtt(struct drm_i915_private *i915) ggtt->base.i915 = i915; - ggtt->mappable_base = 0; - ggtt->mappable_end = 2048 * PAGE_SIZE; + ggtt->gmadr = (struct resource) DEFINE_RES_MEM(0, 2048 * PAGE_SIZE); + ggtt->mappable_end = resource_size(&ggtt->gmadr); ggtt->base.total = 4096 * PAGE_SIZE; ggtt->base.clear_range = nop_clear_range; -- GitLab From b1ace60107e65b915a59b113f2aaeed8587f34fd Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Mon, 11 Dec 2017 15:18:21 +0000 Subject: [PATCH 1277/2547] drm/i915: give stolen_usable_size a more suitable home Kick it out of i915_ggtt and keep it grouped with dsm and dsm_reserved, where it makes the most sense. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Paulo Zanoni Reviewed-by: Chris Wilson Signed-off-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171211151822.20953-9-matthew.auld@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 13 ++++++++++++- drivers/gpu/drm/i915/i915_gem_gtt.h | 10 ---------- drivers/gpu/drm/i915/i915_gem_stolen.c | 5 ++--- drivers/gpu/drm/i915/intel_display.c | 3 +-- drivers/gpu/drm/i915/intel_fbdev.c | 3 +-- 5 files changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7945af0037f8..d71e59e44d50 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2254,7 +2254,7 @@ struct drm_i915_private { /** * Data Stolen Memory - aka "i915 stolen memory" gives us the start and * end of stolen which we can optionally use to create GEM objects - * backed by stolen memory. Note that ggtt->stolen_usable_size tells us + * backed by stolen memory. Note that stolen_usable_size tells us * exactly how much of this we are actually allowed to use, given that * some portion of it is in fact reserved for use by hardware functions. */ @@ -2264,6 +2264,17 @@ struct drm_i915_private { */ struct resource dsm_reserved; + /* + * Stolen memory is segmented in hardware with different portions + * offlimits to certain functions. + * + * The drm_mm is initialised to the total accessible range, as found + * from the PCI config. On Broadwell+, this is further restricted to + * avoid the first page! The upper end of stolen memory is reserved for + * hardware functions and similarly removed from the accessible range. + */ + u32 stolen_usable_size; /* Total size minus reserved ranges */ + void __iomem *regs; struct intel_uncore uncore; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 4a17ce36281a..e5aa07ceb627 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -373,16 +373,6 @@ struct i915_ggtt { struct resource gmadr; /* GMADR resource */ u64 mappable_end; /* End offset that we can CPU map */ - /* Stolen memory is segmented in hardware with different portions - * offlimits to certain functions. - * - * The drm_mm is initialised to the total accessible range, as found - * from the PCI config. On Broadwell+, this is further restricted to - * avoid the first page! The upper end of stolen memory is reserved for - * hardware functions and similarly removed from the accessible range. - */ - u32 stolen_usable_size; /* Total size minus reserved ranges */ - /** "Graphics Stolen Memory" holds the global PTEs */ void __iomem *gsm; void (*invalidate)(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index b6cca0d4ecd3..63d568512db5 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -325,7 +325,6 @@ static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv, int i915_gem_init_stolen(struct drm_i915_private *dev_priv) { - struct i915_ggtt *ggtt = &dev_priv->ggtt; dma_addr_t reserved_base, stolen_top; u32 reserved_total, reserved_size; u32 stolen_usable_start; @@ -416,12 +415,12 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) >= 8) stolen_usable_start = 4096; - ggtt->stolen_usable_size = + dev_priv->stolen_usable_size = resource_size(&dev_priv->dsm) - reserved_total - stolen_usable_start; /* Basic memrange allocator for stolen space. */ drm_mm_init(&dev_priv->mm.stolen, stolen_usable_start, - ggtt->stolen_usable_size); + dev_priv->stolen_usable_size); return 0; } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f9ff1c7fa054..efa6c6d19664 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2639,7 +2639,6 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct i915_ggtt *ggtt = &dev_priv->ggtt; struct drm_i915_gem_object *obj = NULL; struct drm_mode_fb_cmd2 mode_cmd = { 0 }; struct drm_framebuffer *fb = &plane_config->fb->base; @@ -2655,7 +2654,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, /* If the FB is too big, just don't use it since fbdev is not very * important and we should probably use that space with FBC or other * features. */ - if (size_aligned * 2 > ggtt->stolen_usable_size) + if (size_aligned * 2 > dev_priv->stolen_usable_size) return false; mutex_lock(&dev->struct_mutex); diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index ea96682568e8..da48af11eb6b 100644 --- a/drivers/gpu/drm/i915/intel_fbdev.c +++ b/drivers/gpu/drm/i915/intel_fbdev.c @@ -115,7 +115,6 @@ static int intelfb_alloc(struct drm_fb_helper *helper, struct drm_framebuffer *fb; struct drm_device *dev = helper->dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct i915_ggtt *ggtt = &dev_priv->ggtt; struct drm_mode_fb_cmd2 mode_cmd = {}; struct drm_i915_gem_object *obj; int size, ret; @@ -139,7 +138,7 @@ static int intelfb_alloc(struct drm_fb_helper *helper, * important and we should probably use that space with FBC or other * features. */ obj = NULL; - if (size * 2 < ggtt->stolen_usable_size) + if (size * 2 < dev_priv->stolen_usable_size) obj = i915_gem_object_create_stolen(dev_priv, size); if (obj == NULL) obj = i915_gem_object_create(dev_priv, size); -- GitLab From b7128ef125b400e42bab90155777e1def5bfcd31 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Mon, 11 Dec 2017 15:18:22 +0000 Subject: [PATCH 1278/2547] drm/i915: prefer resource_size_t for everything stolen Keeps things consistent now that we make use of struct resource. This should keep us covered in case we ever get huge amounts of stolen memory. v2: bunch of missing conversions (Chris) Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Paulo Zanoni Reviewed-by: Chris Wilson Signed-off-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171211151822.20953-10-matthew.auld@intel.com --- drivers/char/agp/intel-gtt.c | 12 ++++---- drivers/gpu/drm/i915/i915_debugfs.c | 4 +-- drivers/gpu/drm/i915/i915_drv.h | 11 +++---- drivers/gpu/drm/i915/i915_gem_gtt.c | 10 +++---- drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +- drivers/gpu/drm/i915/i915_gem_stolen.c | 40 +++++++++++++------------- drivers/gpu/drm/i915/intel_pm.c | 10 +++---- include/drm/intel-gtt.h | 2 +- 8 files changed, 46 insertions(+), 45 deletions(-) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 0c86b4dfd59c..c6271ce250b3 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -80,7 +80,7 @@ static struct _intel_private { unsigned int needs_dmar : 1; phys_addr_t gma_bus_addr; /* Size of memory reserved for graphics by the BIOS */ - unsigned int stolen_size; + resource_size_t stolen_size; /* Total number of gtt entries. */ unsigned int gtt_total_entries; /* Part of the gtt that is mappable by the cpu, for those chips where @@ -333,13 +333,13 @@ static void i810_write_entry(dma_addr_t addr, unsigned int entry, writel_relaxed(addr | pte_flags, intel_private.gtt + entry); } -static unsigned int intel_gtt_stolen_size(void) +static resource_size_t intel_gtt_stolen_size(void) { u16 gmch_ctrl; u8 rdct; int local = 0; static const int ddt[4] = { 0, 16, 32, 64 }; - unsigned int stolen_size = 0; + resource_size_t stolen_size = 0; if (INTEL_GTT_GEN == 1) return 0; /* no stolen mem on i81x */ @@ -417,8 +417,8 @@ static unsigned int intel_gtt_stolen_size(void) } if (stolen_size > 0) { - dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", - stolen_size / KB(1), local ? "local" : "stolen"); + dev_info(&intel_private.bridge_dev->dev, "detected %lluK %s memory\n", + (u64)stolen_size / KB(1), local ? "local" : "stolen"); } else { dev_info(&intel_private.bridge_dev->dev, "no pre-allocated video memory detected\n"); @@ -1425,7 +1425,7 @@ EXPORT_SYMBOL(intel_gmch_probe); void intel_gtt_get(u64 *gtt_total, phys_addr_t *mappable_base, - u64 *mappable_end) + resource_size_t *mappable_end) { *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT; *mappable_base = intel_private.gma_bus_addr; diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index f91dd68c53a1..d8c6ec3cca71 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -522,8 +522,8 @@ static int i915_gem_object_info(struct seq_file *m, void *data) seq_printf(m, "%u display objects (globally pinned), %llu bytes\n", dpy_count, dpy_size); - seq_printf(m, "%llu [%llu] gtt total\n", - ggtt->base.total, ggtt->mappable_end); + seq_printf(m, "%llu [%pa] gtt total\n", + ggtt->base.total, &ggtt->mappable_end); seq_printf(m, "Supported page sizes: %s\n", stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes, buf, sizeof(buf))); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d71e59e44d50..61196ff93901 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2273,7 +2273,7 @@ struct drm_i915_private { * avoid the first page! The upper end of stolen memory is reserved for * hardware functions and similarly removed from the accessible range. */ - u32 stolen_usable_size; /* Total size minus reserved ranges */ + resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ void __iomem *regs; @@ -3932,12 +3932,13 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, int i915_gem_init_stolen(struct drm_i915_private *dev_priv); void i915_gem_cleanup_stolen(struct drm_device *dev); struct drm_i915_gem_object * -i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size); +i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, + resource_size_t size); struct drm_i915_gem_object * i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv, - u32 stolen_offset, - u32 gtt_offset, - u32 size); + resource_size_t stolen_offset, + resource_size_t gtt_offset, + resource_size_t size); /* i915_gem_internal.c */ struct drm_i915_gem_object * diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index fbc1f467273a..a7fe05666f72 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3354,7 +3354,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) * a coarse sanity check. */ if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { - DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); + DRM_ERROR("Unknown GMADR size (%pa)\n", &ggtt->mappable_end); return -ENXIO; } @@ -3464,7 +3464,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) */ if (USES_GUC(dev_priv)) { ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP); - ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); + ggtt->mappable_end = min_t(u64, ggtt->mappable_end, ggtt->base.total); } if ((ggtt->base.total - 1) >> 32) { @@ -3472,13 +3472,13 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) " of address space! Found %lldM!\n", ggtt->base.total >> 20); ggtt->base.total = 1ULL << 32; - ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); + ggtt->mappable_end = min_t(u64, ggtt->mappable_end, ggtt->base.total); } if (ggtt->mappable_end > ggtt->base.total) { DRM_ERROR("mappable aperture extends past end of GGTT," - " aperture=%llx, total=%llx\n", - ggtt->mappable_end, ggtt->base.total); + " aperture=%pa, total=%llx\n", + &ggtt->mappable_end, ggtt->base.total); ggtt->mappable_end = ggtt->base.total; } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index e5aa07ceb627..a42890d9af38 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -371,7 +371,7 @@ struct i915_ggtt { struct io_mapping iomap; /* Mapping to our CPU mappable region */ struct resource gmadr; /* GMADR resource */ - u64 mappable_end; /* End offset that we can CPU map */ + resource_size_t mappable_end; /* End offset that we can CPU map */ /** "Graphics Stolen Memory" holds the global PTEs */ void __iomem *gsm; diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index 63d568512db5..d3f222fa6356 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -95,7 +95,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv, !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv)) { struct resource stolen[2] = {*dsm, *dsm}; struct resource ggtt_res; - u64 ggtt_start; + resource_size_t ggtt_start; ggtt_start = I915_READ(PGTBL_CTL); if (IS_GEN4(dev_priv)) @@ -174,12 +174,12 @@ void i915_gem_cleanup_stolen(struct drm_device *dev) } static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv, - dma_addr_t *base, u32 *size) + resource_size_t *base, resource_size_t *size) { uint32_t reg_val = I915_READ(IS_GM45(dev_priv) ? CTG_STOLEN_RESERVED : ELK_STOLEN_RESERVED); - dma_addr_t stolen_top = dev_priv->dsm.end + 1; + resource_size_t stolen_top = dev_priv->dsm.end + 1; if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0) { *base = 0; @@ -208,7 +208,7 @@ static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv, } static void gen6_get_stolen_reserved(struct drm_i915_private *dev_priv, - dma_addr_t *base, u32 *size) + resource_size_t *base, resource_size_t *size) { uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED); @@ -240,7 +240,7 @@ static void gen6_get_stolen_reserved(struct drm_i915_private *dev_priv, } static void gen7_get_stolen_reserved(struct drm_i915_private *dev_priv, - dma_addr_t *base, u32 *size) + resource_size_t *base, resource_size_t *size) { uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED); @@ -266,7 +266,7 @@ static void gen7_get_stolen_reserved(struct drm_i915_private *dev_priv, } static void chv_get_stolen_reserved(struct drm_i915_private *dev_priv, - dma_addr_t *base, u32 *size) + resource_size_t *base, resource_size_t *size) { uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED); @@ -298,10 +298,10 @@ static void chv_get_stolen_reserved(struct drm_i915_private *dev_priv, } static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv, - dma_addr_t *base, u32 *size) + resource_size_t *base, resource_size_t *size) { uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED); - dma_addr_t stolen_top; + resource_size_t stolen_top; if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) { *base = 0; @@ -325,9 +325,9 @@ static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv, int i915_gem_init_stolen(struct drm_i915_private *dev_priv) { - dma_addr_t reserved_base, stolen_top; - u32 reserved_total, reserved_size; - u32 stolen_usable_start; + resource_size_t reserved_base, stolen_top; + resource_size_t reserved_total, reserved_size; + resource_size_t stolen_usable_start; mutex_init(&dev_priv->mm.stolen_lock); @@ -427,14 +427,13 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) static struct sg_table * i915_pages_create_for_stolen(struct drm_device *dev, - u32 offset, u32 size) + resource_size_t offset, resource_size_t size) { struct drm_i915_private *dev_priv = to_i915(dev); struct sg_table *st; struct scatterlist *sg; - GEM_BUG_ON(range_overflows_t(resource_size_t, offset, size, - resource_size(&dev_priv->dsm))); + GEM_BUG_ON(range_overflows(offset, size, resource_size(&dev_priv->dsm))); /* We hide that we have no struct page backing our stolen object * by wrapping the contiguous physical allocation with a fake @@ -532,7 +531,8 @@ _i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, } struct drm_i915_gem_object * -i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size) +i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, + resource_size_t size) { struct drm_i915_gem_object *obj; struct drm_mm_node *stolen; @@ -565,9 +565,9 @@ i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size) struct drm_i915_gem_object * i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv, - u32 stolen_offset, - u32 gtt_offset, - u32 size) + resource_size_t stolen_offset, + resource_size_t gtt_offset, + resource_size_t size) { struct i915_ggtt *ggtt = &dev_priv->ggtt; struct drm_i915_gem_object *obj; @@ -580,8 +580,8 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv lockdep_assert_held(&dev_priv->drm.struct_mutex); - DRM_DEBUG_KMS("creating preallocated stolen object: stolen_offset=%x, gtt_offset=%x, size=%x\n", - stolen_offset, gtt_offset, size); + DRM_DEBUG_KMS("creating preallocated stolen object: stolen_offset=%pa, gtt_offset=%pa, size=%pa\n", + &stolen_offset, >t_offset, &size); /* KISS and expect everything to be page-aligned */ if (WARN_ON(size == 0) || diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 57dcf8e1ff30..18779c6eb4bf 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7033,9 +7033,9 @@ static void cherryview_check_pctx(struct drm_i915_private *dev_priv) static void cherryview_setup_pctx(struct drm_i915_private *dev_priv) { - unsigned long pctx_paddr, paddr; + resource_size_t pctx_paddr, paddr; + resource_size_t pctx_size = 32*1024; u32 pcbr; - int pctx_size = 32*1024; pcbr = I915_READ(VLV_PCBR); if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { @@ -7053,14 +7053,14 @@ static void cherryview_setup_pctx(struct drm_i915_private *dev_priv) static void valleyview_setup_pctx(struct drm_i915_private *dev_priv) { struct drm_i915_gem_object *pctx; - unsigned long pctx_paddr; + resource_size_t pctx_paddr; + resource_size_t pctx_size = 24*1024; u32 pcbr; - int pctx_size = 24*1024; pcbr = I915_READ(VLV_PCBR); if (pcbr) { /* BIOS set it up already, grab the pre-alloc'd space */ - int pcbr_offset; + resource_size_t pcbr_offset; pcbr_offset = (pcbr & (~4095)) - dev_priv->dsm.start; pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv, diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h index 8c577ca38e2e..2324c84a25c0 100644 --- a/include/drm/intel-gtt.h +++ b/include/drm/intel-gtt.h @@ -6,7 +6,7 @@ void intel_gtt_get(u64 *gtt_total, phys_addr_t *mappable_base, - u64 *mappable_end); + resource_size_t *mappable_end); int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, struct agp_bridge_data *bridge); -- GitLab From 54eed78c5c831ba696259f7fa69966d699a173b1 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 11 Dec 2017 12:30:14 +0100 Subject: [PATCH 1279/2547] usb: gadget: webcam: fix V4L2 Kconfig dependency Configuring the USB_G_WEBCAM driver as built-in leads to a link error when CONFIG_VIDEO_V4L2 is a loadable module: drivers/usb/gadget/function/f_uvc.o: In function `uvc_function_setup': f_uvc.c:(.text+0xfe): undefined reference to `v4l2_event_queue' drivers/usb/gadget/function/f_uvc.o: In function `uvc_function_ep0_complete': f_uvc.c:(.text+0x188): undefined reference to `v4l2_event_queue' This changes the Kconfig dependency to disallow that configuration, and force it to be a module in that case as well. This is apparently a rather old bug, but very hard to trigger even in thousands of randconfig builds. Signed-off-by: Arnd Bergmann Signed-off-by: Felipe Balbi --- drivers/usb/gadget/legacy/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/legacy/Kconfig b/drivers/usb/gadget/legacy/Kconfig index 9570bbeced4f..487568f2c729 100644 --- a/drivers/usb/gadget/legacy/Kconfig +++ b/drivers/usb/gadget/legacy/Kconfig @@ -487,7 +487,7 @@ endif # or video class gadget drivers), or specific hardware, here. config USB_G_WEBCAM tristate "USB Webcam Gadget" - depends on VIDEO_DEV + depends on VIDEO_V4L2 select USB_LIBCOMPOSITE select VIDEOBUF2_VMALLOC select USB_F_UVC -- GitLab From 9dbe416b656bb015fc49fc17961000ffa418838a Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Tue, 12 Dec 2017 12:44:40 +0200 Subject: [PATCH 1280/2547] Revert "usb: gadget: allow to enable legacy drivers without USB_ETH" This reverts commit 7a9618a22aadffb55027d665491adf466bced61a. Romain Izard recently reported that commit 7a9618a22aad ended up allowing every legacy gadget driver to statically linked to the kernel, however that doesn't work, since only one legacy gadget can be bound to a controller. Because of that, let's revert the original commit and fix the problem. Reported-by: Romain Izard Signed-off-by: Felipe Balbi --- drivers/usb/gadget/Kconfig | 4 ++-- drivers/usb/gadget/legacy/Kconfig | 10 ---------- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 0a19a76645ad..31cce7805eb2 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -508,8 +508,8 @@ choice controller, and the relevant drivers for each function declared by the device. -endchoice - source "drivers/usb/gadget/legacy/Kconfig" +endchoice + endif # USB_GADGET diff --git a/drivers/usb/gadget/legacy/Kconfig b/drivers/usb/gadget/legacy/Kconfig index 487568f2c729..784bf86dad4f 100644 --- a/drivers/usb/gadget/legacy/Kconfig +++ b/drivers/usb/gadget/legacy/Kconfig @@ -13,14 +13,6 @@ # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG). # -menuconfig USB_GADGET_LEGACY - bool "Legacy USB Gadget Support" - help - Legacy USB gadgets are USB gadgets that do not use the USB gadget - configfs interface. - -if USB_GADGET_LEGACY - config USB_ZERO tristate "Gadget Zero (DEVELOPMENT)" select USB_LIBCOMPOSITE @@ -498,5 +490,3 @@ config USB_G_WEBCAM Say "y" to link the driver statically, or "m" to build a dynamically linked module called "g_webcam". - -endif -- GitLab From e966eaeeb623f09975ef362c2866fae6f86844f9 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Tue, 12 Dec 2017 12:31:16 +0100 Subject: [PATCH 1281/2547] locking/lockdep: Remove the cross-release locking checks This code (CONFIG_LOCKDEP_CROSSRELEASE=y and CONFIG_LOCKDEP_COMPLETIONS=y), while it found a number of old bugs initially, was also causing too many false positives that caused people to disable lockdep - which is arguably a worse overall outcome. If we disable cross-release by default but keep the code upstream then in practice the most likely outcome is that we'll allow the situation to degrade gradually, by allowing entropy to introduce more and more false positives, until it overwhelms maintenance capacity. Another bad side effect was that people were trying to work around the false positives by uglifying/complicating unrelated code. There's a marked difference between annotating locking operations and uglifying good code just due to bad lock debugging code ... This gradual decrease in quality happened to a number of debugging facilities in the kernel, and lockdep is pretty complex already, so we cannot risk this outcome. Either cross-release checking can be done right with no false positives, or it should not be included in the upstream kernel. ( Note that it might make sense to maintain it out of tree and go through the false positives every now and then and see whether new bugs were introduced. ) Cc: Byungchul Park Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- Documentation/locking/crossrelease.txt | 874 ------------------------- include/linux/completion.h | 45 -- include/linux/lockdep.h | 125 ---- include/linux/sched.h | 11 - kernel/locking/lockdep.c | 652 +----------------- lib/Kconfig.debug | 33 - 6 files changed, 35 insertions(+), 1705 deletions(-) delete mode 100644 Documentation/locking/crossrelease.txt diff --git a/Documentation/locking/crossrelease.txt b/Documentation/locking/crossrelease.txt deleted file mode 100644 index bdf1423d5f99..000000000000 --- a/Documentation/locking/crossrelease.txt +++ /dev/null @@ -1,874 +0,0 @@ -Crossrelease -============ - -Started by Byungchul Park - -Contents: - - (*) Background - - - What causes deadlock - - How lockdep works - - (*) Limitation - - - Limit lockdep - - Pros from the limitation - - Cons from the limitation - - Relax the limitation - - (*) Crossrelease - - - Introduce crossrelease - - Introduce commit - - (*) Implementation - - - Data structures - - How crossrelease works - - (*) Optimizations - - - Avoid duplication - - Lockless for hot paths - - (*) APPENDIX A: What lockdep does to work aggresively - - (*) APPENDIX B: How to avoid adding false dependencies - - -========== -Background -========== - -What causes deadlock --------------------- - -A deadlock occurs when a context is waiting for an event to happen, -which is impossible because another (or the) context who can trigger the -event is also waiting for another (or the) event to happen, which is -also impossible due to the same reason. - -For example: - - A context going to trigger event C is waiting for event A to happen. - A context going to trigger event A is waiting for event B to happen. - A context going to trigger event B is waiting for event C to happen. - -A deadlock occurs when these three wait operations run at the same time, -because event C cannot be triggered if event A does not happen, which in -turn cannot be triggered if event B does not happen, which in turn -cannot be triggered if event C does not happen. After all, no event can -be triggered since any of them never meets its condition to wake up. - -A dependency might exist between two waiters and a deadlock might happen -due to an incorrect releationship between dependencies. Thus, we must -define what a dependency is first. A dependency exists between them if: - - 1. There are two waiters waiting for each event at a given time. - 2. The only way to wake up each waiter is to trigger its event. - 3. Whether one can be woken up depends on whether the other can. - -Each wait in the example creates its dependency like: - - Event C depends on event A. - Event A depends on event B. - Event B depends on event C. - - NOTE: Precisely speaking, a dependency is one between whether a - waiter for an event can be woken up and whether another waiter for - another event can be woken up. However from now on, we will describe - a dependency as if it's one between an event and another event for - simplicity. - -And they form circular dependencies like: - - -> C -> A -> B - - / \ - \ / - ---------------- - - where 'A -> B' means that event A depends on event B. - -Such circular dependencies lead to a deadlock since no waiter can meet -its condition to wake up as described. - -CONCLUSION - -Circular dependencies cause a deadlock. - - -How lockdep works ------------------ - -Lockdep tries to detect a deadlock by checking dependencies created by -lock operations, acquire and release. Waiting for a lock corresponds to -waiting for an event, and releasing a lock corresponds to triggering an -event in the previous section. - -In short, lockdep does: - - 1. Detect a new dependency. - 2. Add the dependency into a global graph. - 3. Check if that makes dependencies circular. - 4. Report a deadlock or its possibility if so. - -For example, consider a graph built by lockdep that looks like: - - A -> B - - \ - -> E - / - C -> D - - - where A, B,..., E are different lock classes. - -Lockdep will add a dependency into the graph on detection of a new -dependency. For example, it will add a dependency 'E -> C' when a new -dependency between lock E and lock C is detected. Then the graph will be: - - A -> B - - \ - -> E - - / \ - -> C -> D - \ - / / - \ / - ------------------ - - where A, B,..., E are different lock classes. - -This graph contains a subgraph which demonstrates circular dependencies: - - -> E - - / \ - -> C -> D - \ - / / - \ / - ------------------ - - where C, D and E are different lock classes. - -This is the condition under which a deadlock might occur. Lockdep -reports it on detection after adding a new dependency. This is the way -how lockdep works. - -CONCLUSION - -Lockdep detects a deadlock or its possibility by checking if circular -dependencies were created after adding each new dependency. - - -========== -Limitation -========== - -Limit lockdep -------------- - -Limiting lockdep to work on only typical locks e.g. spin locks and -mutexes, which are released within the acquire context, the -implementation becomes simple but its capacity for detection becomes -limited. Let's check pros and cons in next section. - - -Pros from the limitation ------------------------- - -Given the limitation, when acquiring a lock, locks in a held_locks -cannot be released if the context cannot acquire it so has to wait to -acquire it, which means all waiters for the locks in the held_locks are -stuck. It's an exact case to create dependencies between each lock in -the held_locks and the lock to acquire. - -For example: - - CONTEXT X - --------- - acquire A - acquire B /* Add a dependency 'A -> B' */ - release B - release A - - where A and B are different lock classes. - -When acquiring lock A, the held_locks of CONTEXT X is empty thus no -dependency is added. But when acquiring lock B, lockdep detects and adds -a new dependency 'A -> B' between lock A in the held_locks and lock B. -They can be simply added whenever acquiring each lock. - -And data required by lockdep exists in a local structure, held_locks -embedded in task_struct. Forcing to access the data within the context, -lockdep can avoid racy problems without explicit locks while handling -the local data. - -Lastly, lockdep only needs to keep locks currently being held, to build -a dependency graph. However, relaxing the limitation, it needs to keep -even locks already released, because a decision whether they created -dependencies might be long-deferred. - -To sum up, we can expect several advantages from the limitation: - - 1. Lockdep can easily identify a dependency when acquiring a lock. - 2. Races are avoidable while accessing local locks in a held_locks. - 3. Lockdep only needs to keep locks currently being held. - -CONCLUSION - -Given the limitation, the implementation becomes simple and efficient. - - -Cons from the limitation ------------------------- - -Given the limitation, lockdep is applicable only to typical locks. For -example, page locks for page access or completions for synchronization -cannot work with lockdep. - -Can we detect deadlocks below, under the limitation? - -Example 1: - - CONTEXT X CONTEXT Y CONTEXT Z - --------- --------- ---------- - mutex_lock A - lock_page B - lock_page B - mutex_lock A /* DEADLOCK */ - unlock_page B held by X - unlock_page B - mutex_unlock A - mutex_unlock A - - where A and B are different lock classes. - -No, we cannot. - -Example 2: - - CONTEXT X CONTEXT Y - --------- --------- - mutex_lock A - mutex_lock A - wait_for_complete B /* DEADLOCK */ - complete B - mutex_unlock A - mutex_unlock A - - where A is a lock class and B is a completion variable. - -No, we cannot. - -CONCLUSION - -Given the limitation, lockdep cannot detect a deadlock or its -possibility caused by page locks or completions. - - -Relax the limitation --------------------- - -Under the limitation, things to create dependencies are limited to -typical locks. However, synchronization primitives like page locks and -completions, which are allowed to be released in any context, also -create dependencies and can cause a deadlock. So lockdep should track -these locks to do a better job. We have to relax the limitation for -these locks to work with lockdep. - -Detecting dependencies is very important for lockdep to work because -adding a dependency means adding an opportunity to check whether it -causes a deadlock. The more lockdep adds dependencies, the more it -thoroughly works. Thus Lockdep has to do its best to detect and add as -many true dependencies into a graph as possible. - -For example, considering only typical locks, lockdep builds a graph like: - - A -> B - - \ - -> E - / - C -> D - - - where A, B,..., E are different lock classes. - -On the other hand, under the relaxation, additional dependencies might -be created and added. Assuming additional 'FX -> C' and 'E -> GX' are -added thanks to the relaxation, the graph will be: - - A -> B - - \ - -> E -> GX - / - FX -> C -> D - - - where A, B,..., E, FX and GX are different lock classes, and a suffix - 'X' is added on non-typical locks. - -The latter graph gives us more chances to check circular dependencies -than the former. However, it might suffer performance degradation since -relaxing the limitation, with which design and implementation of lockdep -can be efficient, might introduce inefficiency inevitably. So lockdep -should provide two options, strong detection and efficient detection. - -Choosing efficient detection: - - Lockdep works with only locks restricted to be released within the - acquire context. However, lockdep works efficiently. - -Choosing strong detection: - - Lockdep works with all synchronization primitives. However, lockdep - suffers performance degradation. - -CONCLUSION - -Relaxing the limitation, lockdep can add additional dependencies giving -additional opportunities to check circular dependencies. - - -============ -Crossrelease -============ - -Introduce crossrelease ----------------------- - -In order to allow lockdep to handle additional dependencies by what -might be released in any context, namely 'crosslock', we have to be able -to identify those created by crosslocks. The proposed 'crossrelease' -feature provoides a way to do that. - -Crossrelease feature has to do: - - 1. Identify dependencies created by crosslocks. - 2. Add the dependencies into a dependency graph. - -That's all. Once a meaningful dependency is added into graph, then -lockdep would work with the graph as it did. The most important thing -crossrelease feature has to do is to correctly identify and add true -dependencies into the global graph. - -A dependency e.g. 'A -> B' can be identified only in the A's release -context because a decision required to identify the dependency can be -made only in the release context. That is to decide whether A can be -released so that a waiter for A can be woken up. It cannot be made in -other than the A's release context. - -It's no matter for typical locks because each acquire context is same as -its release context, thus lockdep can decide whether a lock can be -released in the acquire context. However for crosslocks, lockdep cannot -make the decision in the acquire context but has to wait until the -release context is identified. - -Therefore, deadlocks by crosslocks cannot be detected just when it -happens, because those cannot be identified until the crosslocks are -released. However, deadlock possibilities can be detected and it's very -worth. See 'APPENDIX A' section to check why. - -CONCLUSION - -Using crossrelease feature, lockdep can work with what might be released -in any context, namely crosslock. - - -Introduce commit ----------------- - -Since crossrelease defers the work adding true dependencies of -crosslocks until they are actually released, crossrelease has to queue -all acquisitions which might create dependencies with the crosslocks. -Then it identifies dependencies using the queued data in batches at a -proper time. We call it 'commit'. - -There are four types of dependencies: - -1. TT type: 'typical lock A -> typical lock B' - - Just when acquiring B, lockdep can see it's in the A's release - context. So the dependency between A and B can be identified - immediately. Commit is unnecessary. - -2. TC type: 'typical lock A -> crosslock BX' - - Just when acquiring BX, lockdep can see it's in the A's release - context. So the dependency between A and BX can be identified - immediately. Commit is unnecessary, too. - -3. CT type: 'crosslock AX -> typical lock B' - - When acquiring B, lockdep cannot identify the dependency because - there's no way to know if it's in the AX's release context. It has - to wait until the decision can be made. Commit is necessary. - -4. CC type: 'crosslock AX -> crosslock BX' - - When acquiring BX, lockdep cannot identify the dependency because - there's no way to know if it's in the AX's release context. It has - to wait until the decision can be made. Commit is necessary. - But, handling CC type is not implemented yet. It's a future work. - -Lockdep can work without commit for typical locks, but commit step is -necessary once crosslocks are involved. Introducing commit, lockdep -performs three steps. What lockdep does in each step is: - -1. Acquisition: For typical locks, lockdep does what it originally did - and queues the lock so that CT type dependencies can be checked using - it at the commit step. For crosslocks, it saves data which will be - used at the commit step and increases a reference count for it. - -2. Commit: No action is reauired for typical locks. For crosslocks, - lockdep adds CT type dependencies using the data saved at the - acquisition step. - -3. Release: No changes are required for typical locks. When a crosslock - is released, it decreases a reference count for it. - -CONCLUSION - -Crossrelease introduces commit step to handle dependencies of crosslocks -in batches at a proper time. - - -============== -Implementation -============== - -Data structures ---------------- - -Crossrelease introduces two main data structures. - -1. hist_lock - - This is an array embedded in task_struct, for keeping lock history so - that dependencies can be added using them at the commit step. Since - it's local data, it can be accessed locklessly in the owner context. - The array is filled at the acquisition step and consumed at the - commit step. And it's managed in circular manner. - -2. cross_lock - - One per lockdep_map exists. This is for keeping data of crosslocks - and used at the commit step. - - -How crossrelease works ----------------------- - -It's the key of how crossrelease works, to defer necessary works to an -appropriate point in time and perform in at once at the commit step. -Let's take a look with examples step by step, starting from how lockdep -works without crossrelease for typical locks. - - acquire A /* Push A onto held_locks */ - acquire B /* Push B onto held_locks and add 'A -> B' */ - acquire C /* Push C onto held_locks and add 'B -> C' */ - release C /* Pop C from held_locks */ - release B /* Pop B from held_locks */ - release A /* Pop A from held_locks */ - - where A, B and C are different lock classes. - - NOTE: This document assumes that readers already understand how - lockdep works without crossrelease thus omits details. But there's - one thing to note. Lockdep pretends to pop a lock from held_locks - when releasing it. But it's subtly different from the original pop - operation because lockdep allows other than the top to be poped. - -In this case, lockdep adds 'the top of held_locks -> the lock to acquire' -dependency every time acquiring a lock. - -After adding 'A -> B', a dependency graph will be: - - A -> B - - where A and B are different lock classes. - -And after adding 'B -> C', the graph will be: - - A -> B -> C - - where A, B and C are different lock classes. - -Let's performs commit step even for typical locks to add dependencies. -Of course, commit step is not necessary for them, however, it would work -well because this is a more general way. - - acquire A - /* - * Queue A into hist_locks - * - * In hist_locks: A - * In graph: Empty - */ - - acquire B - /* - * Queue B into hist_locks - * - * In hist_locks: A, B - * In graph: Empty - */ - - acquire C - /* - * Queue C into hist_locks - * - * In hist_locks: A, B, C - * In graph: Empty - */ - - commit C - /* - * Add 'C -> ?' - * Answer the following to decide '?' - * What has been queued since acquire C: Nothing - * - * In hist_locks: A, B, C - * In graph: Empty - */ - - release C - - commit B - /* - * Add 'B -> ?' - * Answer the following to decide '?' - * What has been queued since acquire B: C - * - * In hist_locks: A, B, C - * In graph: 'B -> C' - */ - - release B - - commit A - /* - * Add 'A -> ?' - * Answer the following to decide '?' - * What has been queued since acquire A: B, C - * - * In hist_locks: A, B, C - * In graph: 'B -> C', 'A -> B', 'A -> C' - */ - - release A - - where A, B and C are different lock classes. - -In this case, dependencies are added at the commit step as described. - -After commits for A, B and C, the graph will be: - - A -> B -> C - - where A, B and C are different lock classes. - - NOTE: A dependency 'A -> C' is optimized out. - -We can see the former graph built without commit step is same as the -latter graph built using commit steps. Of course the former way leads to -earlier finish for building the graph, which means we can detect a -deadlock or its possibility sooner. So the former way would be prefered -when possible. But we cannot avoid using the latter way for crosslocks. - -Let's look at how commit steps work for crosslocks. In this case, the -commit step is performed only on crosslock AX as real. And it assumes -that the AX release context is different from the AX acquire context. - - BX RELEASE CONTEXT BX ACQUIRE CONTEXT - ------------------ ------------------ - acquire A - /* - * Push A onto held_locks - * Queue A into hist_locks - * - * In held_locks: A - * In hist_locks: A - * In graph: Empty - */ - - acquire BX - /* - * Add 'the top of held_locks -> BX' - * - * In held_locks: A - * In hist_locks: A - * In graph: 'A -> BX' - */ - - ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - It must be guaranteed that the following operations are seen after - acquiring BX globally. It can be done by things like barrier. - ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - acquire C - /* - * Push C onto held_locks - * Queue C into hist_locks - * - * In held_locks: C - * In hist_locks: C - * In graph: 'A -> BX' - */ - - release C - /* - * Pop C from held_locks - * - * In held_locks: Empty - * In hist_locks: C - * In graph: 'A -> BX' - */ - acquire D - /* - * Push D onto held_locks - * Queue D into hist_locks - * Add 'the top of held_locks -> D' - * - * In held_locks: A, D - * In hist_locks: A, D - * In graph: 'A -> BX', 'A -> D' - */ - acquire E - /* - * Push E onto held_locks - * Queue E into hist_locks - * - * In held_locks: E - * In hist_locks: C, E - * In graph: 'A -> BX', 'A -> D' - */ - - release E - /* - * Pop E from held_locks - * - * In held_locks: Empty - * In hist_locks: D, E - * In graph: 'A -> BX', 'A -> D' - */ - release D - /* - * Pop D from held_locks - * - * In held_locks: A - * In hist_locks: A, D - * In graph: 'A -> BX', 'A -> D' - */ - commit BX - /* - * Add 'BX -> ?' - * What has been queued since acquire BX: C, E - * - * In held_locks: Empty - * In hist_locks: D, E - * In graph: 'A -> BX', 'A -> D', - * 'BX -> C', 'BX -> E' - */ - - release BX - /* - * In held_locks: Empty - * In hist_locks: D, E - * In graph: 'A -> BX', 'A -> D', - * 'BX -> C', 'BX -> E' - */ - release A - /* - * Pop A from held_locks - * - * In held_locks: Empty - * In hist_locks: A, D - * In graph: 'A -> BX', 'A -> D', - * 'BX -> C', 'BX -> E' - */ - - where A, BX, C,..., E are different lock classes, and a suffix 'X' is - added on crosslocks. - -Crossrelease considers all acquisitions after acqiuring BX are -candidates which might create dependencies with BX. True dependencies -will be determined when identifying the release context of BX. Meanwhile, -all typical locks are queued so that they can be used at the commit step. -And then two dependencies 'BX -> C' and 'BX -> E' are added at the -commit step when identifying the release context. - -The final graph will be, with crossrelease: - - -> C - / - -> BX - - / \ - A - -> E - \ - -> D - - where A, BX, C,..., E are different lock classes, and a suffix 'X' is - added on crosslocks. - -However, the final graph will be, without crossrelease: - - A -> D - - where A and D are different lock classes. - -The former graph has three more dependencies, 'A -> BX', 'BX -> C' and -'BX -> E' giving additional opportunities to check if they cause -deadlocks. This way lockdep can detect a deadlock or its possibility -caused by crosslocks. - -CONCLUSION - -We checked how crossrelease works with several examples. - - -============= -Optimizations -============= - -Avoid duplication ------------------ - -Crossrelease feature uses a cache like what lockdep already uses for -dependency chains, but this time it's for caching CT type dependencies. -Once that dependency is cached, the same will never be added again. - - -Lockless for hot paths ----------------------- - -To keep all locks for later use at the commit step, crossrelease adopts -a local array embedded in task_struct, which makes access to the data -lockless by forcing it to happen only within the owner context. It's -like how lockdep handles held_locks. Lockless implmentation is important -since typical locks are very frequently acquired and released. - - -================================================= -APPENDIX A: What lockdep does to work aggresively -================================================= - -A deadlock actually occurs when all wait operations creating circular -dependencies run at the same time. Even though they don't, a potential -deadlock exists if the problematic dependencies exist. Thus it's -meaningful to detect not only an actual deadlock but also its potential -possibility. The latter is rather valuable. When a deadlock occurs -actually, we can identify what happens in the system by some means or -other even without lockdep. However, there's no way to detect possiblity -without lockdep unless the whole code is parsed in head. It's terrible. -Lockdep does the both, and crossrelease only focuses on the latter. - -Whether or not a deadlock actually occurs depends on several factors. -For example, what order contexts are switched in is a factor. Assuming -circular dependencies exist, a deadlock would occur when contexts are -switched so that all wait operations creating the dependencies run -simultaneously. Thus to detect a deadlock possibility even in the case -that it has not occured yet, lockdep should consider all possible -combinations of dependencies, trying to: - -1. Use a global dependency graph. - - Lockdep combines all dependencies into one global graph and uses them, - regardless of which context generates them or what order contexts are - switched in. Aggregated dependencies are only considered so they are - prone to be circular if a problem exists. - -2. Check dependencies between classes instead of instances. - - What actually causes a deadlock are instances of lock. However, - lockdep checks dependencies between classes instead of instances. - This way lockdep can detect a deadlock which has not happened but - might happen in future by others but the same class. - -3. Assume all acquisitions lead to waiting. - - Although locks might be acquired without waiting which is essential - to create dependencies, lockdep assumes all acquisitions lead to - waiting since it might be true some time or another. - -CONCLUSION - -Lockdep detects not only an actual deadlock but also its possibility, -and the latter is more valuable. - - -================================================== -APPENDIX B: How to avoid adding false dependencies -================================================== - -Remind what a dependency is. A dependency exists if: - - 1. There are two waiters waiting for each event at a given time. - 2. The only way to wake up each waiter is to trigger its event. - 3. Whether one can be woken up depends on whether the other can. - -For example: - - acquire A - acquire B /* A dependency 'A -> B' exists */ - release B - release A - - where A and B are different lock classes. - -A depedency 'A -> B' exists since: - - 1. A waiter for A and a waiter for B might exist when acquiring B. - 2. Only way to wake up each is to release what it waits for. - 3. Whether the waiter for A can be woken up depends on whether the - other can. IOW, TASK X cannot release A if it fails to acquire B. - -For another example: - - TASK X TASK Y - ------ ------ - acquire AX - acquire B /* A dependency 'AX -> B' exists */ - release B - release AX held by Y - - where AX and B are different lock classes, and a suffix 'X' is added - on crosslocks. - -Even in this case involving crosslocks, the same rule can be applied. A -depedency 'AX -> B' exists since: - - 1. A waiter for AX and a waiter for B might exist when acquiring B. - 2. Only way to wake up each is to release what it waits for. - 3. Whether the waiter for AX can be woken up depends on whether the - other can. IOW, TASK X cannot release AX if it fails to acquire B. - -Let's take a look at more complicated example: - - TASK X TASK Y - ------ ------ - acquire B - release B - fork Y - acquire AX - acquire C /* A dependency 'AX -> C' exists */ - release C - release AX held by Y - - where AX, B and C are different lock classes, and a suffix 'X' is - added on crosslocks. - -Does a dependency 'AX -> B' exist? Nope. - -Two waiters are essential to create a dependency. However, waiters for -AX and B to create 'AX -> B' cannot exist at the same time in this -example. Thus the dependency 'AX -> B' cannot be created. - -It would be ideal if the full set of true ones can be considered. But -we can ensure nothing but what actually happened. Relying on what -actually happens at runtime, we can anyway add only true ones, though -they might be a subset of true ones. It's similar to how lockdep works -for typical locks. There might be more true dependencies than what -lockdep has detected in runtime. Lockdep has no choice but to rely on -what actually happens. Crossrelease also relies on it. - -CONCLUSION - -Relying on what actually happens, lockdep can avoid adding false -dependencies. diff --git a/include/linux/completion.h b/include/linux/completion.h index 0662a417febe..94a59ba7d422 100644 --- a/include/linux/completion.h +++ b/include/linux/completion.h @@ -10,9 +10,6 @@ */ #include -#ifdef CONFIG_LOCKDEP_COMPLETIONS -#include -#endif /* * struct completion - structure used to maintain state for a "completion" @@ -29,58 +26,16 @@ struct completion { unsigned int done; wait_queue_head_t wait; -#ifdef CONFIG_LOCKDEP_COMPLETIONS - struct lockdep_map_cross map; -#endif }; -#ifdef CONFIG_LOCKDEP_COMPLETIONS -static inline void complete_acquire(struct completion *x) -{ - lock_acquire_exclusive((struct lockdep_map *)&x->map, 0, 0, NULL, _RET_IP_); -} - -static inline void complete_release(struct completion *x) -{ - lock_release((struct lockdep_map *)&x->map, 0, _RET_IP_); -} - -static inline void complete_release_commit(struct completion *x) -{ - lock_commit_crosslock((struct lockdep_map *)&x->map); -} - -#define init_completion_map(x, m) \ -do { \ - lockdep_init_map_crosslock((struct lockdep_map *)&(x)->map, \ - (m)->name, (m)->key, 0); \ - __init_completion(x); \ -} while (0) - -#define init_completion(x) \ -do { \ - static struct lock_class_key __key; \ - lockdep_init_map_crosslock((struct lockdep_map *)&(x)->map, \ - "(completion)" #x, \ - &__key, 0); \ - __init_completion(x); \ -} while (0) -#else #define init_completion_map(x, m) __init_completion(x) #define init_completion(x) __init_completion(x) static inline void complete_acquire(struct completion *x) {} static inline void complete_release(struct completion *x) {} static inline void complete_release_commit(struct completion *x) {} -#endif -#ifdef CONFIG_LOCKDEP_COMPLETIONS -#define COMPLETION_INITIALIZER(work) \ - { 0, __WAIT_QUEUE_HEAD_INITIALIZER((work).wait), \ - STATIC_CROSS_LOCKDEP_MAP_INIT("(completion)" #work, &(work)) } -#else #define COMPLETION_INITIALIZER(work) \ { 0, __WAIT_QUEUE_HEAD_INITIALIZER((work).wait) } -#endif #define COMPLETION_INITIALIZER_ONSTACK_MAP(work, map) \ (*({ init_completion_map(&(work), &(map)); &(work); })) diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h index a842551fe044..2e75dc34bff5 100644 --- a/include/linux/lockdep.h +++ b/include/linux/lockdep.h @@ -158,12 +158,6 @@ struct lockdep_map { int cpu; unsigned long ip; #endif -#ifdef CONFIG_LOCKDEP_CROSSRELEASE - /* - * Whether it's a crosslock. - */ - int cross; -#endif }; static inline void lockdep_copy_map(struct lockdep_map *to, @@ -267,95 +261,8 @@ struct held_lock { unsigned int hardirqs_off:1; unsigned int references:12; /* 32 bits */ unsigned int pin_count; -#ifdef CONFIG_LOCKDEP_CROSSRELEASE - /* - * Generation id. - * - * A value of cross_gen_id will be stored when holding this, - * which is globally increased whenever each crosslock is held. - */ - unsigned int gen_id; -#endif -}; - -#ifdef CONFIG_LOCKDEP_CROSSRELEASE -#define MAX_XHLOCK_TRACE_ENTRIES 5 - -/* - * This is for keeping locks waiting for commit so that true dependencies - * can be added at commit step. - */ -struct hist_lock { - /* - * Id for each entry in the ring buffer. This is used to - * decide whether the ring buffer was overwritten or not. - * - * For example, - * - * |<----------- hist_lock ring buffer size ------->| - * pppppppppppppppppppppiiiiiiiiiiiiiiiiiiiiiiiiiiiii - * wrapped > iiiiiiiiiiiiiiiiiiiiiiiiiii....................... - * - * where 'p' represents an acquisition in process - * context, 'i' represents an acquisition in irq - * context. - * - * In this example, the ring buffer was overwritten by - * acquisitions in irq context, that should be detected on - * rollback or commit. - */ - unsigned int hist_id; - - /* - * Seperate stack_trace data. This will be used at commit step. - */ - struct stack_trace trace; - unsigned long trace_entries[MAX_XHLOCK_TRACE_ENTRIES]; - - /* - * Seperate hlock instance. This will be used at commit step. - * - * TODO: Use a smaller data structure containing only necessary - * data. However, we should make lockdep code able to handle the - * smaller one first. - */ - struct held_lock hlock; }; -/* - * To initialize a lock as crosslock, lockdep_init_map_crosslock() should - * be called instead of lockdep_init_map(). - */ -struct cross_lock { - /* - * When more than one acquisition of crosslocks are overlapped, - * we have to perform commit for them based on cross_gen_id of - * the first acquisition, which allows us to add more true - * dependencies. - * - * Moreover, when no acquisition of a crosslock is in progress, - * we should not perform commit because the lock might not exist - * any more, which might cause incorrect memory access. So we - * have to track the number of acquisitions of a crosslock. - */ - int nr_acquire; - - /* - * Seperate hlock instance. This will be used at commit step. - * - * TODO: Use a smaller data structure containing only necessary - * data. However, we should make lockdep code able to handle the - * smaller one first. - */ - struct held_lock hlock; -}; - -struct lockdep_map_cross { - struct lockdep_map map; - struct cross_lock xlock; -}; -#endif - /* * Initialization, self-test and debugging-output methods: */ @@ -560,37 +467,6 @@ enum xhlock_context_t { XHLOCK_CTX_NR, }; -#ifdef CONFIG_LOCKDEP_CROSSRELEASE -extern void lockdep_init_map_crosslock(struct lockdep_map *lock, - const char *name, - struct lock_class_key *key, - int subclass); -extern void lock_commit_crosslock(struct lockdep_map *lock); - -/* - * What we essencially have to initialize is 'nr_acquire'. Other members - * will be initialized in add_xlock(). - */ -#define STATIC_CROSS_LOCK_INIT() \ - { .nr_acquire = 0,} - -#define STATIC_CROSS_LOCKDEP_MAP_INIT(_name, _key) \ - { .map.name = (_name), .map.key = (void *)(_key), \ - .map.cross = 1, .xlock = STATIC_CROSS_LOCK_INIT(), } - -/* - * To initialize a lockdep_map statically use this macro. - * Note that _name must not be NULL. - */ -#define STATIC_LOCKDEP_MAP_INIT(_name, _key) \ - { .name = (_name), .key = (void *)(_key), .cross = 0, } - -extern void crossrelease_hist_start(enum xhlock_context_t c); -extern void crossrelease_hist_end(enum xhlock_context_t c); -extern void lockdep_invariant_state(bool force); -extern void lockdep_init_task(struct task_struct *task); -extern void lockdep_free_task(struct task_struct *task); -#else /* !CROSSRELEASE */ #define lockdep_init_map_crosslock(m, n, k, s) do {} while (0) /* * To initialize a lockdep_map statically use this macro. @@ -604,7 +480,6 @@ static inline void crossrelease_hist_end(enum xhlock_context_t c) {} static inline void lockdep_invariant_state(bool force) {} static inline void lockdep_init_task(struct task_struct *task) {} static inline void lockdep_free_task(struct task_struct *task) {} -#endif /* CROSSRELEASE */ #ifdef CONFIG_LOCK_STAT diff --git a/include/linux/sched.h b/include/linux/sched.h index 21991d668d35..9ce6c3001e9f 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -849,17 +849,6 @@ struct task_struct { struct held_lock held_locks[MAX_LOCK_DEPTH]; #endif -#ifdef CONFIG_LOCKDEP_CROSSRELEASE -#define MAX_XHLOCKS_NR 64UL - struct hist_lock *xhlocks; /* Crossrelease history locks */ - unsigned int xhlock_idx; - /* For restoring at history boundaries */ - unsigned int xhlock_idx_hist[XHLOCK_CTX_NR]; - unsigned int hist_id; - /* For overwrite check at each context exit */ - unsigned int hist_id_save[XHLOCK_CTX_NR]; -#endif - #ifdef CONFIG_UBSAN unsigned int in_ubsan; #endif diff --git a/kernel/locking/lockdep.c b/kernel/locking/lockdep.c index 670d8d7d8087..5fa1324a4f29 100644 --- a/kernel/locking/lockdep.c +++ b/kernel/locking/lockdep.c @@ -57,10 +57,6 @@ #define CREATE_TRACE_POINTS #include -#ifdef CONFIG_LOCKDEP_CROSSRELEASE -#include -#endif - #ifdef CONFIG_PROVE_LOCKING int prove_locking = 1; module_param(prove_locking, int, 0644); @@ -75,19 +71,6 @@ module_param(lock_stat, int, 0644); #define lock_stat 0 #endif -#ifdef CONFIG_BOOTPARAM_LOCKDEP_CROSSRELEASE_FULLSTACK -static int crossrelease_fullstack = 1; -#else -static int crossrelease_fullstack; -#endif -static int __init allow_crossrelease_fullstack(char *str) -{ - crossrelease_fullstack = 1; - return 0; -} - -early_param("crossrelease_fullstack", allow_crossrelease_fullstack); - /* * lockdep_lock: protects the lockdep graph, the hashes and the * class/list/hash allocators. @@ -740,18 +723,6 @@ look_up_lock_class(struct lockdep_map *lock, unsigned int subclass) return is_static || static_obj(lock->key) ? NULL : ERR_PTR(-EINVAL); } -#ifdef CONFIG_LOCKDEP_CROSSRELEASE -static void cross_init(struct lockdep_map *lock, int cross); -static int cross_lock(struct lockdep_map *lock); -static int lock_acquire_crosslock(struct held_lock *hlock); -static int lock_release_crosslock(struct lockdep_map *lock); -#else -static inline void cross_init(struct lockdep_map *lock, int cross) {} -static inline int cross_lock(struct lockdep_map *lock) { return 0; } -static inline int lock_acquire_crosslock(struct held_lock *hlock) { return 2; } -static inline int lock_release_crosslock(struct lockdep_map *lock) { return 2; } -#endif - /* * Register a lock's class in the hash-table, if the class is not present * yet. Otherwise we look it up. We cache the result in the lock object @@ -1151,41 +1122,22 @@ print_circular_lock_scenario(struct held_lock *src, printk(KERN_CONT "\n\n"); } - if (cross_lock(tgt->instance)) { - printk(" Possible unsafe locking scenario by crosslock:\n\n"); - printk(" CPU0 CPU1\n"); - printk(" ---- ----\n"); - printk(" lock("); - __print_lock_name(parent); - printk(KERN_CONT ");\n"); - printk(" lock("); - __print_lock_name(target); - printk(KERN_CONT ");\n"); - printk(" lock("); - __print_lock_name(source); - printk(KERN_CONT ");\n"); - printk(" unlock("); - __print_lock_name(target); - printk(KERN_CONT ");\n"); - printk("\n *** DEADLOCK ***\n\n"); - } else { - printk(" Possible unsafe locking scenario:\n\n"); - printk(" CPU0 CPU1\n"); - printk(" ---- ----\n"); - printk(" lock("); - __print_lock_name(target); - printk(KERN_CONT ");\n"); - printk(" lock("); - __print_lock_name(parent); - printk(KERN_CONT ");\n"); - printk(" lock("); - __print_lock_name(target); - printk(KERN_CONT ");\n"); - printk(" lock("); - __print_lock_name(source); - printk(KERN_CONT ");\n"); - printk("\n *** DEADLOCK ***\n\n"); - } + printk(" Possible unsafe locking scenario:\n\n"); + printk(" CPU0 CPU1\n"); + printk(" ---- ----\n"); + printk(" lock("); + __print_lock_name(target); + printk(KERN_CONT ");\n"); + printk(" lock("); + __print_lock_name(parent); + printk(KERN_CONT ");\n"); + printk(" lock("); + __print_lock_name(target); + printk(KERN_CONT ");\n"); + printk(" lock("); + __print_lock_name(source); + printk(KERN_CONT ");\n"); + printk("\n *** DEADLOCK ***\n\n"); } /* @@ -1211,10 +1163,7 @@ print_circular_bug_header(struct lock_list *entry, unsigned int depth, curr->comm, task_pid_nr(curr)); print_lock(check_src); - if (cross_lock(check_tgt->instance)) - pr_warn("\nbut now in release context of a crosslock acquired at the following:\n"); - else - pr_warn("\nbut task is already holding lock:\n"); + pr_warn("\nbut task is already holding lock:\n"); print_lock(check_tgt); pr_warn("\nwhich lock already depends on the new lock.\n\n"); @@ -1244,9 +1193,7 @@ static noinline int print_circular_bug(struct lock_list *this, if (!debug_locks_off_graph_unlock() || debug_locks_silent) return 0; - if (cross_lock(check_tgt->instance)) - this->trace = *trace; - else if (!save_trace(&this->trace)) + if (!save_trace(&this->trace)) return 0; depth = get_lock_depth(target); @@ -1850,9 +1797,6 @@ check_deadlock(struct task_struct *curr, struct held_lock *next, if (nest) return 2; - if (cross_lock(prev->instance)) - continue; - return print_deadlock_bug(curr, prev, next); } return 1; @@ -2018,31 +1962,26 @@ check_prevs_add(struct task_struct *curr, struct held_lock *next) for (;;) { int distance = curr->lockdep_depth - depth + 1; hlock = curr->held_locks + depth - 1; + /* - * Only non-crosslock entries get new dependencies added. - * Crosslock entries will be added by commit later: + * Only non-recursive-read entries get new dependencies + * added: */ - if (!cross_lock(hlock->instance)) { + if (hlock->read != 2 && hlock->check) { + int ret = check_prev_add(curr, hlock, next, distance, &trace, save_trace); + if (!ret) + return 0; + /* - * Only non-recursive-read entries get new dependencies - * added: + * Stop after the first non-trylock entry, + * as non-trylock entries have added their + * own direct dependencies already, so this + * lock is connected to them indirectly: */ - if (hlock->read != 2 && hlock->check) { - int ret = check_prev_add(curr, hlock, next, - distance, &trace, save_trace); - if (!ret) - return 0; - - /* - * Stop after the first non-trylock entry, - * as non-trylock entries have added their - * own direct dependencies already, so this - * lock is connected to them indirectly: - */ - if (!hlock->trylock) - break; - } + if (!hlock->trylock) + break; } + depth--; /* * End of lock-stack? @@ -3292,21 +3231,10 @@ static void __lockdep_init_map(struct lockdep_map *lock, const char *name, void lockdep_init_map(struct lockdep_map *lock, const char *name, struct lock_class_key *key, int subclass) { - cross_init(lock, 0); __lockdep_init_map(lock, name, key, subclass); } EXPORT_SYMBOL_GPL(lockdep_init_map); -#ifdef CONFIG_LOCKDEP_CROSSRELEASE -void lockdep_init_map_crosslock(struct lockdep_map *lock, const char *name, - struct lock_class_key *key, int subclass) -{ - cross_init(lock, 1); - __lockdep_init_map(lock, name, key, subclass); -} -EXPORT_SYMBOL_GPL(lockdep_init_map_crosslock); -#endif - struct lock_class_key __lockdep_no_validate__; EXPORT_SYMBOL_GPL(__lockdep_no_validate__); @@ -3362,7 +3290,6 @@ static int __lock_acquire(struct lockdep_map *lock, unsigned int subclass, int chain_head = 0; int class_idx; u64 chain_key; - int ret; if (unlikely(!debug_locks)) return 0; @@ -3411,8 +3338,7 @@ static int __lock_acquire(struct lockdep_map *lock, unsigned int subclass, class_idx = class - lock_classes + 1; - /* TODO: nest_lock is not implemented for crosslock yet. */ - if (depth && !cross_lock(lock)) { + if (depth) { hlock = curr->held_locks + depth - 1; if (hlock->class_idx == class_idx && nest_lock) { if (hlock->references) { @@ -3500,14 +3426,6 @@ static int __lock_acquire(struct lockdep_map *lock, unsigned int subclass, if (!validate_chain(curr, lock, hlock, chain_head, chain_key)) return 0; - ret = lock_acquire_crosslock(hlock); - /* - * 2 means normal acquire operations are needed. Otherwise, it's - * ok just to return with '0:fail, 1:success'. - */ - if (ret != 2) - return ret; - curr->curr_chain_key = chain_key; curr->lockdep_depth++; check_chain_key(curr); @@ -3745,19 +3663,11 @@ __lock_release(struct lockdep_map *lock, int nested, unsigned long ip) struct task_struct *curr = current; struct held_lock *hlock; unsigned int depth; - int ret, i; + int i; if (unlikely(!debug_locks)) return 0; - ret = lock_release_crosslock(lock); - /* - * 2 means normal release operations are needed. Otherwise, it's - * ok just to return with '0:fail, 1:success'. - */ - if (ret != 2) - return ret; - depth = curr->lockdep_depth; /* * So we're all set to release this lock.. wait what lock? We don't @@ -4675,495 +4585,3 @@ void lockdep_rcu_suspicious(const char *file, const int line, const char *s) dump_stack(); } EXPORT_SYMBOL_GPL(lockdep_rcu_suspicious); - -#ifdef CONFIG_LOCKDEP_CROSSRELEASE - -/* - * Crossrelease works by recording a lock history for each thread and - * connecting those historic locks that were taken after the - * wait_for_completion() in the complete() context. - * - * Task-A Task-B - * - * mutex_lock(&A); - * mutex_unlock(&A); - * - * wait_for_completion(&C); - * lock_acquire_crosslock(); - * atomic_inc_return(&cross_gen_id); - * | - * | mutex_lock(&B); - * | mutex_unlock(&B); - * | - * | complete(&C); - * `-- lock_commit_crosslock(); - * - * Which will then add a dependency between B and C. - */ - -#define xhlock(i) (current->xhlocks[(i) % MAX_XHLOCKS_NR]) - -/* - * Whenever a crosslock is held, cross_gen_id will be increased. - */ -static atomic_t cross_gen_id; /* Can be wrapped */ - -/* - * Make an entry of the ring buffer invalid. - */ -static inline void invalidate_xhlock(struct hist_lock *xhlock) -{ - /* - * Normally, xhlock->hlock.instance must be !NULL. - */ - xhlock->hlock.instance = NULL; -} - -/* - * Lock history stacks; we have 2 nested lock history stacks: - * - * HARD(IRQ) - * SOFT(IRQ) - * - * The thing is that once we complete a HARD/SOFT IRQ the future task locks - * should not depend on any of the locks observed while running the IRQ. So - * what we do is rewind the history buffer and erase all our knowledge of that - * temporal event. - */ - -void crossrelease_hist_start(enum xhlock_context_t c) -{ - struct task_struct *cur = current; - - if (!cur->xhlocks) - return; - - cur->xhlock_idx_hist[c] = cur->xhlock_idx; - cur->hist_id_save[c] = cur->hist_id; -} - -void crossrelease_hist_end(enum xhlock_context_t c) -{ - struct task_struct *cur = current; - - if (cur->xhlocks) { - unsigned int idx = cur->xhlock_idx_hist[c]; - struct hist_lock *h = &xhlock(idx); - - cur->xhlock_idx = idx; - - /* Check if the ring was overwritten. */ - if (h->hist_id != cur->hist_id_save[c]) - invalidate_xhlock(h); - } -} - -/* - * lockdep_invariant_state() is used to annotate independence inside a task, to - * make one task look like multiple independent 'tasks'. - * - * Take for instance workqueues; each work is independent of the last. The - * completion of a future work does not depend on the completion of a past work - * (in general). Therefore we must not carry that (lock) dependency across - * works. - * - * This is true for many things; pretty much all kthreads fall into this - * pattern, where they have an invariant state and future completions do not - * depend on past completions. Its just that since they all have the 'same' - * form -- the kthread does the same over and over -- it doesn't typically - * matter. - * - * The same is true for system-calls, once a system call is completed (we've - * returned to userspace) the next system call does not depend on the lock - * history of the previous system call. - * - * They key property for independence, this invariant state, is that it must be - * a point where we hold no locks and have no history. Because if we were to - * hold locks, the restore at _end() would not necessarily recover it's history - * entry. Similarly, independence per-definition means it does not depend on - * prior state. - */ -void lockdep_invariant_state(bool force) -{ - /* - * We call this at an invariant point, no current state, no history. - * Verify the former, enforce the latter. - */ - WARN_ON_ONCE(!force && current->lockdep_depth); - if (current->xhlocks) - invalidate_xhlock(&xhlock(current->xhlock_idx)); -} - -static int cross_lock(struct lockdep_map *lock) -{ - return lock ? lock->cross : 0; -} - -/* - * This is needed to decide the relationship between wrapable variables. - */ -static inline int before(unsigned int a, unsigned int b) -{ - return (int)(a - b) < 0; -} - -static inline struct lock_class *xhlock_class(struct hist_lock *xhlock) -{ - return hlock_class(&xhlock->hlock); -} - -static inline struct lock_class *xlock_class(struct cross_lock *xlock) -{ - return hlock_class(&xlock->hlock); -} - -/* - * Should we check a dependency with previous one? - */ -static inline int depend_before(struct held_lock *hlock) -{ - return hlock->read != 2 && hlock->check && !hlock->trylock; -} - -/* - * Should we check a dependency with next one? - */ -static inline int depend_after(struct held_lock *hlock) -{ - return hlock->read != 2 && hlock->check; -} - -/* - * Check if the xhlock is valid, which would be false if, - * - * 1. Has not used after initializaion yet. - * 2. Got invalidated. - * - * Remind hist_lock is implemented as a ring buffer. - */ -static inline int xhlock_valid(struct hist_lock *xhlock) -{ - /* - * xhlock->hlock.instance must be !NULL. - */ - return !!xhlock->hlock.instance; -} - -/* - * Record a hist_lock entry. - * - * Irq disable is only required. - */ -static void add_xhlock(struct held_lock *hlock) -{ - unsigned int idx = ++current->xhlock_idx; - struct hist_lock *xhlock = &xhlock(idx); - -#ifdef CONFIG_DEBUG_LOCKDEP - /* - * This can be done locklessly because they are all task-local - * state, we must however ensure IRQs are disabled. - */ - WARN_ON_ONCE(!irqs_disabled()); -#endif - - /* Initialize hist_lock's members */ - xhlock->hlock = *hlock; - xhlock->hist_id = ++current->hist_id; - - xhlock->trace.nr_entries = 0; - xhlock->trace.max_entries = MAX_XHLOCK_TRACE_ENTRIES; - xhlock->trace.entries = xhlock->trace_entries; - - if (crossrelease_fullstack) { - xhlock->trace.skip = 3; - save_stack_trace(&xhlock->trace); - } else { - xhlock->trace.nr_entries = 1; - xhlock->trace.entries[0] = hlock->acquire_ip; - } -} - -static inline int same_context_xhlock(struct hist_lock *xhlock) -{ - return xhlock->hlock.irq_context == task_irq_context(current); -} - -/* - * This should be lockless as far as possible because this would be - * called very frequently. - */ -static void check_add_xhlock(struct held_lock *hlock) -{ - /* - * Record a hist_lock, only in case that acquisitions ahead - * could depend on the held_lock. For example, if the held_lock - * is trylock then acquisitions ahead never depends on that. - * In that case, we don't need to record it. Just return. - */ - if (!current->xhlocks || !depend_before(hlock)) - return; - - add_xhlock(hlock); -} - -/* - * For crosslock. - */ -static int add_xlock(struct held_lock *hlock) -{ - struct cross_lock *xlock; - unsigned int gen_id; - - if (!graph_lock()) - return 0; - - xlock = &((struct lockdep_map_cross *)hlock->instance)->xlock; - - /* - * When acquisitions for a crosslock are overlapped, we use - * nr_acquire to perform commit for them, based on cross_gen_id - * of the first acquisition, which allows to add additional - * dependencies. - * - * Moreover, when no acquisition of a crosslock is in progress, - * we should not perform commit because the lock might not exist - * any more, which might cause incorrect memory access. So we - * have to track the number of acquisitions of a crosslock. - * - * depend_after() is necessary to initialize only the first - * valid xlock so that the xlock can be used on its commit. - */ - if (xlock->nr_acquire++ && depend_after(&xlock->hlock)) - goto unlock; - - gen_id = (unsigned int)atomic_inc_return(&cross_gen_id); - xlock->hlock = *hlock; - xlock->hlock.gen_id = gen_id; -unlock: - graph_unlock(); - return 1; -} - -/* - * Called for both normal and crosslock acquires. Normal locks will be - * pushed on the hist_lock queue. Cross locks will record state and - * stop regular lock_acquire() to avoid being placed on the held_lock - * stack. - * - * Return: 0 - failure; - * 1 - crosslock, done; - * 2 - normal lock, continue to held_lock[] ops. - */ -static int lock_acquire_crosslock(struct held_lock *hlock) -{ - /* - * CONTEXT 1 CONTEXT 2 - * --------- --------- - * lock A (cross) - * X = atomic_inc_return(&cross_gen_id) - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * Y = atomic_read_acquire(&cross_gen_id) - * lock B - * - * atomic_read_acquire() is for ordering between A and B, - * IOW, A happens before B, when CONTEXT 2 see Y >= X. - * - * Pairs with atomic_inc_return() in add_xlock(). - */ - hlock->gen_id = (unsigned int)atomic_read_acquire(&cross_gen_id); - - if (cross_lock(hlock->instance)) - return add_xlock(hlock); - - check_add_xhlock(hlock); - return 2; -} - -static int copy_trace(struct stack_trace *trace) -{ - unsigned long *buf = stack_trace + nr_stack_trace_entries; - unsigned int max_nr = MAX_STACK_TRACE_ENTRIES - nr_stack_trace_entries; - unsigned int nr = min(max_nr, trace->nr_entries); - - trace->nr_entries = nr; - memcpy(buf, trace->entries, nr * sizeof(trace->entries[0])); - trace->entries = buf; - nr_stack_trace_entries += nr; - - if (nr_stack_trace_entries >= MAX_STACK_TRACE_ENTRIES-1) { - if (!debug_locks_off_graph_unlock()) - return 0; - - print_lockdep_off("BUG: MAX_STACK_TRACE_ENTRIES too low!"); - dump_stack(); - - return 0; - } - - return 1; -} - -static int commit_xhlock(struct cross_lock *xlock, struct hist_lock *xhlock) -{ - unsigned int xid, pid; - u64 chain_key; - - xid = xlock_class(xlock) - lock_classes; - chain_key = iterate_chain_key((u64)0, xid); - pid = xhlock_class(xhlock) - lock_classes; - chain_key = iterate_chain_key(chain_key, pid); - - if (lookup_chain_cache(chain_key)) - return 1; - - if (!add_chain_cache_classes(xid, pid, xhlock->hlock.irq_context, - chain_key)) - return 0; - - if (!check_prev_add(current, &xlock->hlock, &xhlock->hlock, 1, - &xhlock->trace, copy_trace)) - return 0; - - return 1; -} - -static void commit_xhlocks(struct cross_lock *xlock) -{ - unsigned int cur = current->xhlock_idx; - unsigned int prev_hist_id = xhlock(cur).hist_id; - unsigned int i; - - if (!graph_lock()) - return; - - if (xlock->nr_acquire) { - for (i = 0; i < MAX_XHLOCKS_NR; i++) { - struct hist_lock *xhlock = &xhlock(cur - i); - - if (!xhlock_valid(xhlock)) - break; - - if (before(xhlock->hlock.gen_id, xlock->hlock.gen_id)) - break; - - if (!same_context_xhlock(xhlock)) - break; - - /* - * Filter out the cases where the ring buffer was - * overwritten and the current entry has a bigger - * hist_id than the previous one, which is impossible - * otherwise: - */ - if (unlikely(before(prev_hist_id, xhlock->hist_id))) - break; - - prev_hist_id = xhlock->hist_id; - - /* - * commit_xhlock() returns 0 with graph_lock already - * released if fail. - */ - if (!commit_xhlock(xlock, xhlock)) - return; - } - } - - graph_unlock(); -} - -void lock_commit_crosslock(struct lockdep_map *lock) -{ - struct cross_lock *xlock; - unsigned long flags; - - if (unlikely(!debug_locks || current->lockdep_recursion)) - return; - - if (!current->xhlocks) - return; - - /* - * Do commit hist_locks with the cross_lock, only in case that - * the cross_lock could depend on acquisitions after that. - * - * For example, if the cross_lock does not have the 'check' flag - * then we don't need to check dependencies and commit for that. - * Just skip it. In that case, of course, the cross_lock does - * not depend on acquisitions ahead, either. - * - * WARNING: Don't do that in add_xlock() in advance. When an - * acquisition context is different from the commit context, - * invalid(skipped) cross_lock might be accessed. - */ - if (!depend_after(&((struct lockdep_map_cross *)lock)->xlock.hlock)) - return; - - raw_local_irq_save(flags); - check_flags(flags); - current->lockdep_recursion = 1; - xlock = &((struct lockdep_map_cross *)lock)->xlock; - commit_xhlocks(xlock); - current->lockdep_recursion = 0; - raw_local_irq_restore(flags); -} -EXPORT_SYMBOL_GPL(lock_commit_crosslock); - -/* - * Return: 0 - failure; - * 1 - crosslock, done; - * 2 - normal lock, continue to held_lock[] ops. - */ -static int lock_release_crosslock(struct lockdep_map *lock) -{ - if (cross_lock(lock)) { - if (!graph_lock()) - return 0; - ((struct lockdep_map_cross *)lock)->xlock.nr_acquire--; - graph_unlock(); - return 1; - } - return 2; -} - -static void cross_init(struct lockdep_map *lock, int cross) -{ - if (cross) - ((struct lockdep_map_cross *)lock)->xlock.nr_acquire = 0; - - lock->cross = cross; - - /* - * Crossrelease assumes that the ring buffer size of xhlocks - * is aligned with power of 2. So force it on build. - */ - BUILD_BUG_ON(MAX_XHLOCKS_NR & (MAX_XHLOCKS_NR - 1)); -} - -void lockdep_init_task(struct task_struct *task) -{ - int i; - - task->xhlock_idx = UINT_MAX; - task->hist_id = 0; - - for (i = 0; i < XHLOCK_CTX_NR; i++) { - task->xhlock_idx_hist[i] = UINT_MAX; - task->hist_id_save[i] = 0; - } - - task->xhlocks = kzalloc(sizeof(struct hist_lock) * MAX_XHLOCKS_NR, - GFP_KERNEL); -} - -void lockdep_free_task(struct task_struct *task) -{ - if (task->xhlocks) { - void *tmp = task->xhlocks; - /* Diable crossrelease for current */ - task->xhlocks = NULL; - kfree(tmp); - } -} -#endif diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index 947d3e2ed5c2..9d5b78aad4c5 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -1099,8 +1099,6 @@ config PROVE_LOCKING select DEBUG_MUTEXES select DEBUG_RT_MUTEXES if RT_MUTEXES select DEBUG_LOCK_ALLOC - select LOCKDEP_CROSSRELEASE - select LOCKDEP_COMPLETIONS select TRACE_IRQFLAGS default n help @@ -1170,37 +1168,6 @@ config LOCK_STAT CONFIG_LOCK_STAT defines "contended" and "acquired" lock events. (CONFIG_LOCKDEP defines "acquire" and "release" events.) -config LOCKDEP_CROSSRELEASE - bool - help - This makes lockdep work for crosslock which is a lock allowed to - be released in a different context from the acquisition context. - Normally a lock must be released in the context acquiring the lock. - However, relexing this constraint helps synchronization primitives - such as page locks or completions can use the lock correctness - detector, lockdep. - -config LOCKDEP_COMPLETIONS - bool - help - A deadlock caused by wait_for_completion() and complete() can be - detected by lockdep using crossrelease feature. - -config BOOTPARAM_LOCKDEP_CROSSRELEASE_FULLSTACK - bool "Enable the boot parameter, crossrelease_fullstack" - depends on LOCKDEP_CROSSRELEASE - default n - help - The lockdep "cross-release" feature needs to record stack traces - (of calling functions) for all acquisitions, for eventual later - use during analysis. By default only a single caller is recorded, - because the unwind operation can be very expensive with deeper - stack chains. - - However a boot parameter, crossrelease_fullstack, was - introduced since sometimes deeper traces are required for full - analysis. This option turns on the boot parameter. - config DEBUG_LOCKDEP bool "Lock dependency engine debugging" depends on DEBUG_KERNEL && LOCKDEP -- GitLab From 86c9e8126e9fbcbf06c36e285168b880369a537c Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 12 Dec 2017 10:48:54 +0000 Subject: [PATCH 1282/2547] arm64: mm: Fix false positives in set_pte_at access/dirty race detection Jiankang reports that our race detection in set_pte_at is firing when copying the page tables in dup_mmap as a result of a fork(). In this situation, the page table isn't actually live and so there is no way that we can race with a concurrent update from the hardware page table walker. This patch reworks the race detection so that we require either the mm to match the current active_mm (i.e. currently installed in our TTBR0) or the mm_users count to be greater than 1, implying that the page table could be live in another CPU. The mm_users check might still be racy, but we'll avoid false positives and it's not realistic to validate that all the necessary locks are held as part of this assertion. Cc: Yisheng Xie Reported-by: Jiankang Chen Tested-by: Jiankang Chen Signed-off-by: Will Deacon --- arch/arm64/include/asm/pgtable.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 3ff03a755c32..bdcc7f1c9d06 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -42,6 +42,8 @@ #include #include #include +#include +#include extern void __pte_error(const char *file, int line, unsigned long val); extern void __pmd_error(const char *file, int line, unsigned long val); @@ -215,9 +217,6 @@ static inline void set_pte(pte_t *ptep, pte_t pte) } } -struct mm_struct; -struct vm_area_struct; - extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); /* @@ -246,7 +245,8 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, * hardware updates of the pte (ptep_set_access_flags safely changes * valid ptes without going through an invalid entry). */ - if (pte_valid(*ptep) && pte_valid(pte)) { + if (IS_ENABLED(CONFIG_DEBUG_VM) && pte_valid(*ptep) && pte_valid(pte) && + (mm == current->active_mm || atomic_read(&mm->mm_users) > 1)) { VM_WARN_ONCE(!pte_young(pte), "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", __func__, pte_val(*ptep), pte_val(pte)); -- GitLab From c622cc013cece073722592cff1ac6643a33b1622 Mon Sep 17 00:00:00 2001 From: Shanker Donthineni Date: Mon, 11 Dec 2017 16:42:31 -0600 Subject: [PATCH 1283/2547] arm64: Define cputype macros for Falkor CPU Add cputype definition macros for Qualcomm Datacenter Technologies Falkor CPU in cputype.h. It's unfortunate that the first revision of the Falkor CPU used the wrong part number 0x800, got fixed in v2 chip with part number 0xC00, and would be used the same value for future revisions. Signed-off-by: Shanker Donthineni Signed-off-by: Will Deacon --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d98261..cbf08d7cbf30 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -91,6 +91,7 @@ #define BRCM_CPU_PART_VULCAN 0x516 #define QCOM_CPU_PART_FALKOR_V1 0x800 +#define QCOM_CPU_PART_FALKOR 0xC00 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) @@ -99,6 +100,7 @@ #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) +#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) #ifndef __ASSEMBLY__ -- GitLab From 932b50c7c1c65e6f23002e075b97ee083c4a9e71 Mon Sep 17 00:00:00 2001 From: Shanker Donthineni Date: Mon, 11 Dec 2017 16:42:32 -0600 Subject: [PATCH 1284/2547] arm64: Add software workaround for Falkor erratum 1041 The ARM architecture defines the memory locations that are permitted to be accessed as the result of a speculative instruction fetch from an exception level for which all stages of translation are disabled. Specifically, the core is permitted to speculatively fetch from the 4KB region containing the current program counter 4K and next 4K. When translation is changed from enabled to disabled for the running exception level (SCTLR_ELn[M] changed from a value of 1 to 0), the Falkor core may errantly speculatively access memory locations outside of the 4KB region permitted by the architecture. The errant memory access may lead to one of the following unexpected behaviors. 1) A System Error Interrupt (SEI) being raised by the Falkor core due to the errant memory access attempting to access a region of memory that is protected by a slave-side memory protection unit. 2) Unpredictable device behavior due to a speculative read from device memory. This behavior may only occur if the instruction cache is disabled prior to or coincident with translation being changed from enabled to disabled. The conditions leading to this erratum will not occur when either of the following occur: 1) A higher exception level disables translation of a lower exception level (e.g. EL2 changing SCTLR_EL1[M] from a value of 1 to 0). 2) An exception level disabling its stage-1 translation if its stage-2 translation is enabled (e.g. EL1 changing SCTLR_EL1[M] from a value of 1 to 0 when HCR_EL2[VM] has a value of 1). To avoid the errant behavior, software must execute an ISB immediately prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0. Signed-off-by: Shanker Donthineni Signed-off-by: Will Deacon --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 12 +++++++++++- arch/arm64/include/asm/assembler.h | 10 ++++++++++ arch/arm64/kernel/cpu-reset.S | 1 + arch/arm64/kernel/efi-entry.S | 2 ++ arch/arm64/kernel/head.S | 1 + arch/arm64/kernel/relocate_kernel.S | 1 + arch/arm64/kvm/hyp-init.S | 1 + 8 files changed, 28 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 304bf22bb83c..fc1c884fea10 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -75,3 +75,4 @@ stable kernels. | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | | Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 | +| Qualcomm Tech. | Falkor v{1,2} | E1041 | QCOM_FALKOR_ERRATUM_1041 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a93339f5178f..c9a7e9e1414f 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -557,7 +557,6 @@ config QCOM_QDF2400_ERRATUM_0065 If unsure, say Y. - config SOCIONEXT_SYNQUACER_PREITS bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" default y @@ -576,6 +575,17 @@ config HISILICON_ERRATUM_161600802 a 128kB offset to be applied to the target address in this commands. If unsure, say Y. + +config QCOM_FALKOR_ERRATUM_E1041 + bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" + default y + help + Falkor CPU may speculatively fetch instructions from an improper + memory location when MMU translation is changed from SCTLR_ELn[M]=1 + to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. + + If unsure, say Y. + endmenu diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index aef72d886677..8b168280976f 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -512,4 +512,14 @@ alternative_else_nop_endif #endif .endm +/** + * Errata workaround prior to disable MMU. Insert an ISB immediately prior + * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0. + */ + .macro pre_disable_mmu_workaround +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041 + isb +#endif + .endm + #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/kernel/cpu-reset.S b/arch/arm64/kernel/cpu-reset.S index 65f42d257414..2a752cb2a0f3 100644 --- a/arch/arm64/kernel/cpu-reset.S +++ b/arch/arm64/kernel/cpu-reset.S @@ -37,6 +37,7 @@ ENTRY(__cpu_soft_restart) mrs x12, sctlr_el1 ldr x13, =SCTLR_ELx_FLAGS bic x12, x12, x13 + pre_disable_mmu_workaround msr sctlr_el1, x12 isb diff --git a/arch/arm64/kernel/efi-entry.S b/arch/arm64/kernel/efi-entry.S index 4e6ad355bd05..6b9736c3fb56 100644 --- a/arch/arm64/kernel/efi-entry.S +++ b/arch/arm64/kernel/efi-entry.S @@ -96,6 +96,7 @@ ENTRY(entry) mrs x0, sctlr_el2 bic x0, x0, #1 << 0 // clear SCTLR.M bic x0, x0, #1 << 2 // clear SCTLR.C + pre_disable_mmu_workaround msr sctlr_el2, x0 isb b 2f @@ -103,6 +104,7 @@ ENTRY(entry) mrs x0, sctlr_el1 bic x0, x0, #1 << 0 // clear SCTLR.M bic x0, x0, #1 << 2 // clear SCTLR.C + pre_disable_mmu_workaround msr sctlr_el1, x0 isb 2: diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 67e86a0f57ac..e3cb9fbf96b6 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -750,6 +750,7 @@ __primary_switch: * to take into account by discarding the current kernel mapping and * creating a new one. */ + pre_disable_mmu_workaround msr sctlr_el1, x20 // disable the MMU isb bl __create_page_tables // recreate kernel mapping diff --git a/arch/arm64/kernel/relocate_kernel.S b/arch/arm64/kernel/relocate_kernel.S index ce704a4aeadd..f407e422a720 100644 --- a/arch/arm64/kernel/relocate_kernel.S +++ b/arch/arm64/kernel/relocate_kernel.S @@ -45,6 +45,7 @@ ENTRY(arm64_relocate_new_kernel) mrs x0, sctlr_el2 ldr x1, =SCTLR_ELx_FLAGS bic x0, x0, x1 + pre_disable_mmu_workaround msr sctlr_el2, x0 isb 1: diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S index 3f9615582377..870828c364c5 100644 --- a/arch/arm64/kvm/hyp-init.S +++ b/arch/arm64/kvm/hyp-init.S @@ -151,6 +151,7 @@ reset: mrs x5, sctlr_el2 ldr x6, =SCTLR_ELx_FLAGS bic x5, x5, x6 // Clear SCTL_M and etc + pre_disable_mmu_workaround msr sctlr_el2, x5 isb -- GitLab From 0e17cada2a5b4dc847082e1db0e3f84599ffd436 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 12 Dec 2017 11:53:26 +0000 Subject: [PATCH 1285/2547] arm64: hw_breakpoint: Use linux/uaccess.h instead of asm/uaccess.h The only inclusion of asm/uaccess.h should be by linux/uaccess.h. All other headers should use the latter. Reported-by: Al Viro Signed-off-by: Will Deacon --- arch/arm64/kernel/hw_breakpoint.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c index 749f81779420..74bb56f656ef 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -36,7 +37,6 @@ #include #include #include -#include /* Breakpoint currently in use for each BRP. */ static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]); -- GitLab From 32fd87b3bbf5f7a045546401dfe2894dbbf4d8c3 Mon Sep 17 00:00:00 2001 From: Andrey Konovalov Date: Mon, 11 Dec 2017 22:48:41 +0100 Subject: [PATCH 1286/2547] USB: core: only clean up what we allocated When cleaning up the configurations, make sure we only free the number of configurations and interfaces that we could have allocated. Reported-by: Andrey Konovalov Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/config.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/usb/core/config.c b/drivers/usb/core/config.c index 55b198ba629b..93b38471754e 100644 --- a/drivers/usb/core/config.c +++ b/drivers/usb/core/config.c @@ -764,18 +764,21 @@ void usb_destroy_configuration(struct usb_device *dev) return; if (dev->rawdescriptors) { - for (i = 0; i < dev->descriptor.bNumConfigurations; i++) + for (i = 0; i < dev->descriptor.bNumConfigurations && + i < USB_MAXCONFIG; i++) kfree(dev->rawdescriptors[i]); kfree(dev->rawdescriptors); dev->rawdescriptors = NULL; } - for (c = 0; c < dev->descriptor.bNumConfigurations; c++) { + for (c = 0; c < dev->descriptor.bNumConfigurations && + c < USB_MAXCONFIG; c++) { struct usb_host_config *cf = &dev->config[c]; kfree(cf->string); - for (i = 0; i < cf->desc.bNumInterfaces; i++) { + for (i = 0; i < cf->desc.bNumInterfaces && + i < USB_MAXINTERFACES; i++) { if (cf->intf_cache[i]) kref_put(&cf->intf_cache[i]->ref, usb_release_interface_cache); -- GitLab From f971e511cb7d6f1b3730248cf2967d3ccdd8874c Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Mon, 27 Nov 2017 10:38:21 +0000 Subject: [PATCH 1287/2547] tools/perf: Convert ACCESS_ONCE() to READ_ONCE() Recently there was a treewide conversion of ACCESS_ONCE() to {READ,WRITE}_ONCE(), but a new use was introduced concurrently by commit: 1695849735752d2a ("perf mmap: Move perf_mmap and methods to separate mmap.[ch] files") Let's convert this over to READ_ONCE() so that we can remove the ACCESS_ONCE() definitions in subsequent patches. Tested-by: Paul E. McKenney Signed-off-by: Mark Rutland Reviewed-by: Paul E. McKenney Cc: Arnaldo Carvalho de Melo Cc: Joe Perches Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: apw@canonical.com Link: http://lkml.kernel.org/r/20171127103824.36526-2-mark.rutland@arm.com Signed-off-by: Ingo Molnar --- tools/perf/util/mmap.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/mmap.h b/tools/perf/util/mmap.h index efd78b827b05..3a5cb5a6e94a 100644 --- a/tools/perf/util/mmap.h +++ b/tools/perf/util/mmap.h @@ -70,7 +70,7 @@ void perf_mmap__read_catchup(struct perf_mmap *md); static inline u64 perf_mmap__read_head(struct perf_mmap *mm) { struct perf_event_mmap_page *pc = mm->base; - u64 head = ACCESS_ONCE(pc->data_head); + u64 head = READ_ONCE(pc->data_head); rmb(); return head; } -- GitLab From 2a22f692bbe0a7933acbd50045479ffc0fdf11f7 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Mon, 27 Nov 2017 10:38:22 +0000 Subject: [PATCH 1288/2547] tools/include: Remove ACCESS_ONCE() There are no longer any usersapce uses of ACCESS_ONCE(), so we can remove the definition from our userspace , which is only used by tools in the kernel directory (i.e. it isn't a uapi header). This patch removes the ACCESS_ONCE() definition, and updates comments which referred to it. At the same time, some inconsistent and redundant whitespace is removed from comments. Tested-by: Paul E. McKenney Signed-off-by: Mark Rutland Cc: Arnaldo Carvalho de Melo Cc: Joe Perches Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: apw@canonical.com Link: http://lkml.kernel.org/r/20171127103824.36526-3-mark.rutland@arm.com Signed-off-by: Ingo Molnar --- tools/include/linux/compiler.h | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/tools/include/linux/compiler.h b/tools/include/linux/compiler.h index 07fd03c74a77..04e32f965ad7 100644 --- a/tools/include/linux/compiler.h +++ b/tools/include/linux/compiler.h @@ -84,8 +84,6 @@ #define uninitialized_var(x) x = *(&(x)) -#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x)) - #include /* @@ -135,20 +133,19 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s /* * Prevent the compiler from merging or refetching reads or writes. The * compiler is also forbidden from reordering successive instances of - * READ_ONCE, WRITE_ONCE and ACCESS_ONCE (see below), but only when the - * compiler is aware of some particular ordering. One way to make the - * compiler aware of ordering is to put the two invocations of READ_ONCE, - * WRITE_ONCE or ACCESS_ONCE() in different C statements. + * READ_ONCE and WRITE_ONCE, but only when the compiler is aware of some + * particular ordering. One way to make the compiler aware of ordering is to + * put the two invocations of READ_ONCE or WRITE_ONCE in different C + * statements. * - * In contrast to ACCESS_ONCE these two macros will also work on aggregate - * data types like structs or unions. If the size of the accessed data - * type exceeds the word size of the machine (e.g., 32 bits or 64 bits) - * READ_ONCE() and WRITE_ONCE() will fall back to memcpy and print a - * compile-time warning. + * These two macros will also work on aggregate data types like structs or + * unions. If the size of the accessed data type exceeds the word size of + * the machine (e.g., 32 bits or 64 bits) READ_ONCE() and WRITE_ONCE() will + * fall back to memcpy and print a compile-time warning. * * Their two major use cases are: (1) Mediating communication between * process-level code and irq/NMI handlers, all running on the same CPU, - * and (2) Ensuring that the compiler does not fold, spindle, or otherwise + * and (2) Ensuring that the compiler does not fold, spindle, or otherwise * mutilate accesses that either do not require ordering or that interact * with an explicit memory barrier or atomic instruction that provides the * required ordering. -- GitLab From b899a850431e2dd0943205a63a68573f3e312d0d Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Mon, 27 Nov 2017 10:38:23 +0000 Subject: [PATCH 1289/2547] compiler.h: Remove ACCESS_ONCE() There are no longer any kernelspace uses of ACCESS_ONCE(), so we can remove the definition from . This patch removes the ACCESS_ONCE() definition, and updates comments which referred to it. At the same time, some inconsistent and redundant whitespace is removed from comments. Tested-by: Paul E. McKenney Signed-off-by: Mark Rutland Cc: Arnaldo Carvalho de Melo Cc: Joe Perches Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: apw@canonical.com Link: http://lkml.kernel.org/r/20171127103824.36526-4-mark.rutland@arm.com Signed-off-by: Ingo Molnar --- include/linux/compiler.h | 47 ++++++++++------------------------------ 1 file changed, 11 insertions(+), 36 deletions(-) diff --git a/include/linux/compiler.h b/include/linux/compiler.h index 188ed9f65517..52e611ab9a6c 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -220,21 +220,21 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s /* * Prevent the compiler from merging or refetching reads or writes. The * compiler is also forbidden from reordering successive instances of - * READ_ONCE, WRITE_ONCE and ACCESS_ONCE (see below), but only when the - * compiler is aware of some particular ordering. One way to make the - * compiler aware of ordering is to put the two invocations of READ_ONCE, - * WRITE_ONCE or ACCESS_ONCE() in different C statements. + * READ_ONCE and WRITE_ONCE, but only when the compiler is aware of some + * particular ordering. One way to make the compiler aware of ordering is to + * put the two invocations of READ_ONCE or WRITE_ONCE in different C + * statements. * - * In contrast to ACCESS_ONCE these two macros will also work on aggregate - * data types like structs or unions. If the size of the accessed data - * type exceeds the word size of the machine (e.g., 32 bits or 64 bits) - * READ_ONCE() and WRITE_ONCE() will fall back to memcpy(). There's at - * least two memcpy()s: one for the __builtin_memcpy() and then one for - * the macro doing the copy of variable - '__u' allocated on the stack. + * These two macros will also work on aggregate data types like structs or + * unions. If the size of the accessed data type exceeds the word size of + * the machine (e.g., 32 bits or 64 bits) READ_ONCE() and WRITE_ONCE() will + * fall back to memcpy(). There's at least two memcpy()s: one for the + * __builtin_memcpy() and then one for the macro doing the copy of variable + * - '__u' allocated on the stack. * * Their two major use cases are: (1) Mediating communication between * process-level code and irq/NMI handlers, all running on the same CPU, - * and (2) Ensuring that the compiler does not fold, spindle, or otherwise + * and (2) Ensuring that the compiler does not fold, spindle, or otherwise * mutilate accesses that either do not require ordering or that interact * with an explicit memory barrier or atomic instruction that provides the * required ordering. @@ -327,29 +327,4 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s compiletime_assert(__native_word(t), \ "Need native word sized stores/loads for atomicity.") -/* - * Prevent the compiler from merging or refetching accesses. The compiler - * is also forbidden from reordering successive instances of ACCESS_ONCE(), - * but only when the compiler is aware of some particular ordering. One way - * to make the compiler aware of ordering is to put the two invocations of - * ACCESS_ONCE() in different C statements. - * - * ACCESS_ONCE will only work on scalar types. For union types, ACCESS_ONCE - * on a union member will work as long as the size of the member matches the - * size of the union and the size is smaller than word size. - * - * The major use cases of ACCESS_ONCE used to be (1) Mediating communication - * between process-level code and irq/NMI handlers, all running on the same CPU, - * and (2) Ensuring that the compiler does not fold, spindle, or otherwise - * mutilate accesses that either do not require ordering or that interact - * with an explicit memory barrier or atomic instruction that provides the - * required ordering. - * - * If possible use READ_ONCE()/WRITE_ONCE() instead. - */ -#define __ACCESS_ONCE(x) ({ \ - __maybe_unused typeof(x) __var = (__force typeof(x)) 0; \ - (volatile typeof(x) *)&(x); }) -#define ACCESS_ONCE(x) (*__ACCESS_ONCE(x)) - #endif /* __LINUX_COMPILER_H */ -- GitLab From 8cb562b1d56fad42cbee44bdc9bc64cea41a0a8c Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Mon, 27 Nov 2017 10:38:24 +0000 Subject: [PATCH 1290/2547] checkpatch: Remove ACCESS_ONCE() warning Now that ACCESS_ONCE() has been excised from the kernel, any uses will result in a build error, and we no longer need to whine about it in checkpatch. This patch removes the newly redundant warning. Tested-by: Paul E. McKenney Signed-off-by: Mark Rutland Acked-by: Joe Perches Cc: Andy Whitcroft Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: acme@redhat.com Link: http://lkml.kernel.org/r/20171127103824.36526-5-mark.rutland@arm.com Signed-off-by: Ingo Molnar --- scripts/checkpatch.pl | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 040aa79e1d9d..31031f10fe56 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -6233,28 +6233,6 @@ sub process { } } -# whine about ACCESS_ONCE - if ($^V && $^V ge 5.10.0 && - $line =~ /\bACCESS_ONCE\s*$balanced_parens\s*(=(?!=))?\s*($FuncArg)?/) { - my $par = $1; - my $eq = $2; - my $fun = $3; - $par =~ s/^\(\s*(.*)\s*\)$/$1/; - if (defined($eq)) { - if (WARN("PREFER_WRITE_ONCE", - "Prefer WRITE_ONCE(, ) over ACCESS_ONCE() = \n" . $herecurr) && - $fix) { - $fixed[$fixlinenr] =~ s/\bACCESS_ONCE\s*\(\s*\Q$par\E\s*\)\s*$eq\s*\Q$fun\E/WRITE_ONCE($par, $fun)/; - } - } else { - if (WARN("PREFER_READ_ONCE", - "Prefer READ_ONCE() over ACCESS_ONCE()\n" . $herecurr) && - $fix) { - $fixed[$fixlinenr] =~ s/\bACCESS_ONCE\s*\(\s*\Q$par\E\s*\)/READ_ONCE($par)/; - } - } - } - # check for mutex_trylock_recursive usage if ($line =~ /mutex_trylock_recursive/) { ERROR("LOCKING", -- GitLab From 0f3922a9b99eca76c6578cd84191573378f2c988 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Fri, 8 Dec 2017 04:17:28 -0700 Subject: [PATCH 1291/2547] x86/Xen: don't report ancient LAPIC version Unconditionally reporting a value seen on the P4 or older invokes functionality like io_apic_get_unique_id() on 32-bit builds, resulting in a panic() with sufficiently many CPUs and/or IO-APICs. Doing what that function does would be the hypervisor's responsibility anyway, so makes no sense to be used when running on Xen. Uniformly report a more modern version; this shouldn't matter much as both LAPIC and IO-APIC are being managed entirely / mostly by the hypervisor. Signed-off-by: Jan Beulich Reviewed-by: Juergen Gross Signed-off-by: Boris Ostrovsky --- arch/x86/xen/apic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/xen/apic.c b/arch/x86/xen/apic.c index b5e48da7fbff..c14048553c18 100644 --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -56,7 +56,7 @@ static u32 xen_apic_read(u32 reg) return 0; if (reg == APIC_LVR) - return 0x10; + return 0x14; #ifdef CONFIG_X86_32 if (reg == APIC_LDR) return SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); -- GitLab From c4f9d9cb2c29ff04c6b4bb09b72802d8aedfc7cb Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Tue, 12 Dec 2017 03:18:11 -0700 Subject: [PATCH 1292/2547] xen: XEN_ACPI_PROCESSOR is Dom0-only Add a respective dependency. Signed-off-by: Jan Beulich Reviewed-by: Juergen Gross Signed-off-by: Boris Ostrovsky --- drivers/xen/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig index d8dd54678ab7..e5d0c28372ea 100644 --- a/drivers/xen/Kconfig +++ b/drivers/xen/Kconfig @@ -269,7 +269,7 @@ config XEN_ACPI_HOTPLUG_CPU config XEN_ACPI_PROCESSOR tristate "Xen ACPI processor" - depends on XEN && X86 && ACPI_PROCESSOR && CPU_FREQ + depends on XEN && XEN_DOM0 && X86 && ACPI_PROCESSOR && CPU_FREQ default m help This ACPI processor uploads Power Management information to the Xen -- GitLab From 0132a1a5d44d2cd32a249dbe999a88c2134a6bd1 Mon Sep 17 00:00:00 2001 From: Markus Heiser Date: Tue, 12 Dec 2017 12:38:37 +0100 Subject: [PATCH 1293/2547] docs: fix, intel_guc_loader.c has been moved to intel_guc_fw.c With commit d9e2e0143c the 'GuC-specific firmware loader' doc section was removed from intel_guc_loader.c without a replacement. So lets remove it from the Kernel-doc:: .. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c :doc: GuC-specific firmware loader With commit e8668bbcb0 intel_guc_loader.c was renamed to to intel_guc_fw.c and to name just one, intel_guc_init_hw() was renamed to intel_guc_fw_upload(). Since we get errors in the Sphinx build like: - Error: Cannot open file ./drivers/gpu/drm/i915/intel_guc_loader.c Change the kernel-doc directive from intel_guc_loader.c to intel_guc_fw.c Signed-off-by: Markus Heiser [danvet: Rebase onto the partial fix 006c23327f8d ("documentation/gpu/i915: fix docs build error after file rename")] Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/1513078717-12373-1-git-send-email-markus.heiser@darmarit.de --- Documentation/gpu/i915.rst | 3 --- 1 file changed, 3 deletions(-) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 84021142a8f3..41dc881b00dc 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -341,9 +341,6 @@ GuC GuC-specific firmware loader ---------------------------- -.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c - :doc: GuC-specific firmware loader - .. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c :internal: -- GitLab From e7fd37ba12170cc414be8b639dfc2c5f7172fac2 Mon Sep 17 00:00:00 2001 From: Ma Shimiao Date: Tue, 12 Dec 2017 09:43:49 +0800 Subject: [PATCH 1294/2547] cgroup: avoid copying strings longer than the buffers cgroup root name and file name have max length limit, we should avoid copying longer name than that to the name. tj: minor update to $SUBJ. Signed-off-by: Ma Shimiao Signed-off-by: Tejun Heo --- kernel/cgroup/cgroup.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c index 0b1ffe147f24..18d71fbd3923 100644 --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c @@ -1397,7 +1397,7 @@ static char *cgroup_file_name(struct cgroup *cgrp, const struct cftype *cft, cgroup_on_dfl(cgrp) ? ss->name : ss->legacy_name, cft->name); else - strncpy(buf, cft->name, CGROUP_FILE_NAME_MAX); + strscpy(buf, cft->name, CGROUP_FILE_NAME_MAX); return buf; } @@ -1864,9 +1864,9 @@ void init_cgroup_root(struct cgroup_root *root, struct cgroup_sb_opts *opts) root->flags = opts->flags; if (opts->release_agent) - strcpy(root->release_agent_path, opts->release_agent); + strscpy(root->release_agent_path, opts->release_agent, PATH_MAX); if (opts->name) - strcpy(root->name, opts->name); + strscpy(root->name, opts->name, MAX_CGROUP_ROOT_NAMELEN); if (opts->cpuset_clone_children) set_bit(CGRP_CPUSET_CLONE_CHILDREN, &root->cgrp.flags); } -- GitLab From 30791ac41927ebd3e75486f9504b6d2280463bf0 Mon Sep 17 00:00:00 2001 From: Christoph Paasch Date: Mon, 11 Dec 2017 00:05:46 -0800 Subject: [PATCH 1295/2547] tcp md5sig: Use skb's saddr when replying to an incoming segment The MD5-key that belongs to a connection is identified by the peer's IP-address. When we are in tcp_v4(6)_reqsk_send_ack(), we are replying to an incoming segment from tcp_check_req() that failed the seq-number checks. Thus, to find the correct key, we need to use the skb's saddr and not the daddr. This bug seems to have been there since quite a while, but probably got unnoticed because the consequences are not catastrophic. We will call tcp_v4_reqsk_send_ack only to send a challenge-ACK back to the peer, thus the connection doesn't really fail. Fixes: 9501f9722922 ("tcp md5sig: Let the caller pass appropriate key for tcp_v{4,6}_do_calc_md5_hash().") Signed-off-by: Christoph Paasch Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller --- net/ipv4/tcp_ipv4.c | 2 +- net/ipv6/tcp_ipv6.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c index 77ea45da0fe9..94e28350f420 100644 --- a/net/ipv4/tcp_ipv4.c +++ b/net/ipv4/tcp_ipv4.c @@ -848,7 +848,7 @@ static void tcp_v4_reqsk_send_ack(const struct sock *sk, struct sk_buff *skb, tcp_time_stamp_raw() + tcp_rsk(req)->ts_off, req->ts_recent, 0, - tcp_md5_do_lookup(sk, (union tcp_md5_addr *)&ip_hdr(skb)->daddr, + tcp_md5_do_lookup(sk, (union tcp_md5_addr *)&ip_hdr(skb)->saddr, AF_INET), inet_rsk(req)->no_srccheck ? IP_REPLY_ARG_NOSRCCHECK : 0, ip_hdr(skb)->tos); diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c index 1f04ec0e4a7a..7178476b3d2f 100644 --- a/net/ipv6/tcp_ipv6.c +++ b/net/ipv6/tcp_ipv6.c @@ -994,7 +994,7 @@ static void tcp_v6_reqsk_send_ack(const struct sock *sk, struct sk_buff *skb, req->rsk_rcv_wnd >> inet_rsk(req)->rcv_wscale, tcp_time_stamp_raw() + tcp_rsk(req)->ts_off, req->ts_recent, sk->sk_bound_dev_if, - tcp_v6_md5_do_lookup(sk, &ipv6_hdr(skb)->daddr), + tcp_v6_md5_do_lookup(sk, &ipv6_hdr(skb)->saddr), 0, 0); } -- GitLab From 17278a91e04f858155d54bee5528ba4fbcec6f87 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Tue, 14 Nov 2017 12:01:20 +0000 Subject: [PATCH 1296/2547] MIPS: CPS: Fix r1 .set mt assembler warning MIPS CPS has a build warning on kernels configured for MIPS32R1 or MIPS64R1, due to the use of .set mt without a prior .set mips{32,64}r2: arch/mips/kernel/cps-vec.S Assembler messages: arch/mips/kernel/cps-vec.S:238: Warning: the `mt' extension requires MIPS32 revision 2 or greater Add .set MIPS_ISA_LEVEL_RAW before .set mt to silence the warning. Fixes: 245a7868d2f2 ("MIPS: smp-cps: rework core/VPE initialisation") Signed-off-by: James Hogan Cc: Paul Burton Cc: James Hogan Cc: James Hogan Cc: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17699/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cps-vec.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index c7ed26029cbb..e68e6e04063a 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -235,6 +235,7 @@ LEAF(mips_cps_core_init) has_mt t0, 3f .set push + .set MIPS_ISA_LEVEL_RAW .set mt /* Only allow 1 TC per VPE to execute... */ @@ -388,6 +389,7 @@ LEAF(mips_cps_boot_vpes) #elif defined(CONFIG_MIPS_MT) .set push + .set MIPS_ISA_LEVEL_RAW .set mt /* If the core doesn't support MT then return */ -- GitLab From 0c31f1d7be1b5c4858b1d714dcefa25f41428cab Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 7 Dec 2017 11:15:19 +0100 Subject: [PATCH 1297/2547] PCI: rcar: Fix use-after-free in probe error path If CONFIG_DEBUG_SLAB=y, and no PCIe card is inserted, the kernel crashes during probe on r8a7791/koelsch: rcar-pcie fe000000.pcie: PCIe link down Unable to handle kernel paging request at virtual address 6b6b6b6b (seeing this message requires earlycon and keep_bootcon). Indeed, pci_free_host_bridge() frees the PCI host bridge, including the embedded rcar_pcie object, so pci_free_resource_list() must not be called afterwards. To fix this, move the call to pci_free_resource_list() up, and update the label name accordingly. Fixes: ddd535f1ea3eb27e ("PCI: rcar: Fix memory leak when no PCIe card is inserted") Signed-off-by: Geert Uytterhoeven Signed-off-by: Bjorn Helgaas Acked-by: Simon Horman Acked-by: Lorenzo Pieralisi --- drivers/pci/host/pcie-rcar.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c index 12796eccb2be..52ab3cb0a0bf 100644 --- a/drivers/pci/host/pcie-rcar.c +++ b/drivers/pci/host/pcie-rcar.c @@ -1128,12 +1128,12 @@ static int rcar_pcie_probe(struct platform_device *pdev) err = rcar_pcie_get_resources(pcie); if (err < 0) { dev_err(dev, "failed to request resources: %d\n", err); - goto err_free_bridge; + goto err_free_resource_list; } err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node); if (err) - goto err_free_bridge; + goto err_free_resource_list; pm_runtime_enable(dev); err = pm_runtime_get_sync(dev); @@ -1176,9 +1176,9 @@ static int rcar_pcie_probe(struct platform_device *pdev) err_pm_disable: pm_runtime_disable(dev); -err_free_bridge: - pci_free_host_bridge(bridge); +err_free_resource_list: pci_free_resource_list(&pcie->resources); + pci_free_host_bridge(bridge); return err; } -- GitLab From 283ca526a9bd75aed7350220d7b1f8027d99c3fd Mon Sep 17 00:00:00 2001 From: Daniel Borkmann Date: Tue, 12 Dec 2017 02:25:30 +0100 Subject: [PATCH 1298/2547] bpf: fix corruption on concurrent perf_event_output calls When tracing and networking programs are both attached in the system and both use event-output helpers that eventually call into perf_event_output(), then we could end up in a situation where the tracing attached program runs in user context while a cls_bpf program is triggered on that same CPU out of softirq context. Since both rely on the same per-cpu perf_sample_data, we could potentially corrupt it. This can only ever happen in a combination of the two types; all tracing programs use a bpf_prog_active counter to bail out in case a program is already running on that CPU out of a different context. XDP and cls_bpf programs by themselves don't have this issue as they run in the same context only. Therefore, split both perf_sample_data so they cannot be accessed from each other. Fixes: 20b9d7ac4852 ("bpf: avoid excessive stack usage for perf_sample_data") Reported-by: Alexei Starovoitov Signed-off-by: Daniel Borkmann Tested-by: Song Liu Acked-by: Alexei Starovoitov Signed-off-by: Alexei Starovoitov --- kernel/trace/bpf_trace.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index 0ce99c379c30..40207c2a4113 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -343,14 +343,13 @@ static const struct bpf_func_proto bpf_perf_event_read_value_proto = { .arg4_type = ARG_CONST_SIZE, }; -static DEFINE_PER_CPU(struct perf_sample_data, bpf_sd); +static DEFINE_PER_CPU(struct perf_sample_data, bpf_trace_sd); static __always_inline u64 __bpf_perf_event_output(struct pt_regs *regs, struct bpf_map *map, - u64 flags, struct perf_raw_record *raw) + u64 flags, struct perf_sample_data *sd) { struct bpf_array *array = container_of(map, struct bpf_array, map); - struct perf_sample_data *sd = this_cpu_ptr(&bpf_sd); unsigned int cpu = smp_processor_id(); u64 index = flags & BPF_F_INDEX_MASK; struct bpf_event_entry *ee; @@ -373,8 +372,6 @@ __bpf_perf_event_output(struct pt_regs *regs, struct bpf_map *map, if (unlikely(event->oncpu != cpu)) return -EOPNOTSUPP; - perf_sample_data_init(sd, 0, 0); - sd->raw = raw; perf_event_output(event, sd, regs); return 0; } @@ -382,6 +379,7 @@ __bpf_perf_event_output(struct pt_regs *regs, struct bpf_map *map, BPF_CALL_5(bpf_perf_event_output, struct pt_regs *, regs, struct bpf_map *, map, u64, flags, void *, data, u64, size) { + struct perf_sample_data *sd = this_cpu_ptr(&bpf_trace_sd); struct perf_raw_record raw = { .frag = { .size = size, @@ -392,7 +390,10 @@ BPF_CALL_5(bpf_perf_event_output, struct pt_regs *, regs, struct bpf_map *, map, if (unlikely(flags & ~(BPF_F_INDEX_MASK))) return -EINVAL; - return __bpf_perf_event_output(regs, map, flags, &raw); + perf_sample_data_init(sd, 0, 0); + sd->raw = &raw; + + return __bpf_perf_event_output(regs, map, flags, sd); } static const struct bpf_func_proto bpf_perf_event_output_proto = { @@ -407,10 +408,12 @@ static const struct bpf_func_proto bpf_perf_event_output_proto = { }; static DEFINE_PER_CPU(struct pt_regs, bpf_pt_regs); +static DEFINE_PER_CPU(struct perf_sample_data, bpf_misc_sd); u64 bpf_event_output(struct bpf_map *map, u64 flags, void *meta, u64 meta_size, void *ctx, u64 ctx_size, bpf_ctx_copy_t ctx_copy) { + struct perf_sample_data *sd = this_cpu_ptr(&bpf_misc_sd); struct pt_regs *regs = this_cpu_ptr(&bpf_pt_regs); struct perf_raw_frag frag = { .copy = ctx_copy, @@ -428,8 +431,10 @@ u64 bpf_event_output(struct bpf_map *map, u64 flags, void *meta, u64 meta_size, }; perf_fetch_caller_regs(regs); + perf_sample_data_init(sd, 0, 0); + sd->raw = &raw; - return __bpf_perf_event_output(regs, map, flags, &raw); + return __bpf_perf_event_output(regs, map, flags, sd); } BPF_CALL_0(bpf_get_current_task) -- GitLab From a23f06f06dbe54696e8d4f156b317e8c9961c345 Mon Sep 17 00:00:00 2001 From: Daniel Borkmann Date: Tue, 12 Dec 2017 02:25:31 +0100 Subject: [PATCH 1299/2547] bpf: fix build issues on um due to mising bpf_perf_event.h Since c895f6f703ad ("bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program type") um (uml) won't build on i386 or x86_64: [...] CC init/main.o In file included from ../include/linux/perf_event.h:18:0, from ../include/linux/trace_events.h:10, from ../include/trace/syscall.h:7, from ../include/linux/syscalls.h:82, from ../init/main.c:20: ../include/uapi/linux/bpf_perf_event.h:11:32: fatal error: asm/bpf_perf_event.h: No such file or directory #include [...] Lets add missing bpf_perf_event.h also to um arch. This seems to be the only one still missing. Fixes: c895f6f703ad ("bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program type") Reported-by: Randy Dunlap Suggested-by: Richard Weinberger Signed-off-by: Daniel Borkmann Tested-by: Randy Dunlap Cc: Hendrik Brueckner Cc: Richard Weinberger Acked-by: Alexei Starovoitov Acked-by: Richard Weinberger Signed-off-by: Alexei Starovoitov --- arch/um/include/asm/Kbuild | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/um/include/asm/Kbuild b/arch/um/include/asm/Kbuild index 50a32c33d729..73c57f614c9e 100644 --- a/arch/um/include/asm/Kbuild +++ b/arch/um/include/asm/Kbuild @@ -1,4 +1,5 @@ generic-y += barrier.h +generic-y += bpf_perf_event.h generic-y += bug.h generic-y += clkdev.h generic-y += current.h -- GitLab From 720f228e8d3128b7ab1d39f51fdd8da07a7640c9 Mon Sep 17 00:00:00 2001 From: Daniel Borkmann Date: Tue, 12 Dec 2017 02:25:32 +0100 Subject: [PATCH 1300/2547] bpf: fix broken BPF selftest build At least on x86_64, the kernel's BPF selftests seemed to have stopped to build due to 618e165b2a8e ("selftests/bpf: sync kernel headers and introduce arch support in Makefile"): [...] In file included from test_verifier.c:29:0: ../../../include/uapi/linux/bpf_perf_event.h:11:32: fatal error: asm/bpf_perf_event.h: No such file or directory #include ^ compilation terminated. [...] While pulling in tools/arch/*/include/uapi/asm/bpf_perf_event.h seems to work fine, there's no automated fall-back logic right now that would do the same out of tools/include/uapi/asm-generic/bpf_perf_event.h. The usual convention today is to add a include/[uapi/]asm/ equivalent that would pull in the correct arch header or generic one as fall-back, all ifdef'ed based on compiler target definition. It's similarly done also in other cases such as tools/include/asm/barrier.h, thus adapt the same here. Fixes: 618e165b2a8e ("selftests/bpf: sync kernel headers and introduce arch support in Makefile") Signed-off-by: Daniel Borkmann Cc: Hendrik Brueckner Cc: Arnaldo Carvalho de Melo Acked-by: Alexei Starovoitov Signed-off-by: Alexei Starovoitov --- tools/include/uapi/asm/bpf_perf_event.h | 7 +++++++ tools/testing/selftests/bpf/Makefile | 13 +------------ 2 files changed, 8 insertions(+), 12 deletions(-) create mode 100644 tools/include/uapi/asm/bpf_perf_event.h diff --git a/tools/include/uapi/asm/bpf_perf_event.h b/tools/include/uapi/asm/bpf_perf_event.h new file mode 100644 index 000000000000..13a58531e6fa --- /dev/null +++ b/tools/include/uapi/asm/bpf_perf_event.h @@ -0,0 +1,7 @@ +#if defined(__aarch64__) +#include "../../arch/arm64/include/uapi/asm/bpf_perf_event.h" +#elif defined(__s390__) +#include "../../arch/s390/include/uapi/asm/bpf_perf_event.h" +#else +#include +#endif diff --git a/tools/testing/selftests/bpf/Makefile b/tools/testing/selftests/bpf/Makefile index 21a2d76b67dc..792af7c3b74f 100644 --- a/tools/testing/selftests/bpf/Makefile +++ b/tools/testing/selftests/bpf/Makefile @@ -1,19 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 -ifeq ($(srctree),) -srctree := $(patsubst %/,%,$(dir $(CURDIR))) -srctree := $(patsubst %/,%,$(dir $(srctree))) -srctree := $(patsubst %/,%,$(dir $(srctree))) -srctree := $(patsubst %/,%,$(dir $(srctree))) -endif -include $(srctree)/tools/scripts/Makefile.arch - -$(call detected_var,SRCARCH) - LIBDIR := ../../../lib BPFDIR := $(LIBDIR)/bpf APIDIR := ../../../include/uapi -ASMDIR:= ../../../arch/$(ARCH)/include/uapi GENDIR := ../../../../include/generated GENHDR := $(GENDIR)/autoconf.h @@ -21,7 +10,7 @@ ifneq ($(wildcard $(GENHDR)),) GENFLAGS := -DHAVE_GENHDR endif -CFLAGS += -Wall -O2 -I$(APIDIR) -I$(ASMDIR) -I$(LIBDIR) -I$(GENDIR) $(GENFLAGS) -I../../../include +CFLAGS += -Wall -O2 -I$(APIDIR) -I$(LIBDIR) -I$(GENDIR) $(GENFLAGS) -I../../../include LDLIBS += -lcap -lelf TEST_GEN_PROGS = test_verifier test_tag test_maps test_lru_map test_lpm_map test_progs \ -- GitLab From a03fe72572c12e98f4173f8a535f32468e48b6ec Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 11 Dec 2017 22:51:35 +0000 Subject: [PATCH 1301/2547] MIPS: Factor out NT_PRFPREG regset access helpers In preparation to fix a commit 72b22bbad1e7 ("MIPS: Don't assume 64-bit FP registers for FP regset") FCSR access regression factor out NT_PRFPREG regset access helpers for the non-MSA and the MSA variants respectively, to avoid having to deal with excessive indentation in the actual fix. No functional change, however use `target->thread.fpu.fpr[0]' rather than `target->thread.fpu.fpr[i]' for FGR holding type size determination as there's no `i' variable to refer to anymore, and for the factored out `i' variable declaration use `unsigned int' rather than `unsigned' as its type, following the common style. Signed-off-by: Maciej W. Rozycki Fixes: 72b22bbad1e7 ("MIPS: Don't assume 64-bit FP registers for FP regset") Cc: James Hogan Cc: Paul Burton Cc: Alex Smith Cc: Dave Martin Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v3.15+ Patchwork: https://patchwork.linux-mips.org/patch/17925/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 108 +++++++++++++++++++++++++++++--------- 1 file changed, 83 insertions(+), 25 deletions(-) diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index efbd8df8b665..62e8ffd9370a 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -419,25 +419,36 @@ static int gpr64_set(struct task_struct *target, #endif /* CONFIG_64BIT */ -static int fpr_get(struct task_struct *target, - const struct user_regset *regset, - unsigned int pos, unsigned int count, - void *kbuf, void __user *ubuf) +/* + * Copy the floating-point context to the supplied NT_PRFPREG buffer, + * !CONFIG_CPU_HAS_MSA variant. FP context's general register slots + * correspond 1:1 to buffer slots. + */ +static int fpr_get_fpa(struct task_struct *target, + unsigned int *pos, unsigned int *count, + void **kbuf, void __user **ubuf) { - unsigned i; - int err; - u64 fpr_val; - - /* XXX fcr31 */ + return user_regset_copyout(pos, count, kbuf, ubuf, + &target->thread.fpu, + 0, sizeof(elf_fpregset_t)); +} - if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t)) - return user_regset_copyout(&pos, &count, &kbuf, &ubuf, - &target->thread.fpu, - 0, sizeof(elf_fpregset_t)); +/* + * Copy the floating-point context to the supplied NT_PRFPREG buffer, + * CONFIG_CPU_HAS_MSA variant. Only lower 64 bits of FP context's + * general register slots are copied to buffer slots. + */ +static int fpr_get_msa(struct task_struct *target, + unsigned int *pos, unsigned int *count, + void **kbuf, void __user **ubuf) +{ + unsigned int i; + u64 fpr_val; + int err; for (i = 0; i < NUM_FPU_REGS; i++) { fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0); - err = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + err = user_regset_copyout(pos, count, kbuf, ubuf, &fpr_val, i * sizeof(elf_fpreg_t), (i + 1) * sizeof(elf_fpreg_t)); if (err) @@ -447,27 +458,54 @@ static int fpr_get(struct task_struct *target, return 0; } -static int fpr_set(struct task_struct *target, +/* Copy the floating-point context to the supplied NT_PRFPREG buffer. */ +static int fpr_get(struct task_struct *target, const struct user_regset *regset, unsigned int pos, unsigned int count, - const void *kbuf, const void __user *ubuf) + void *kbuf, void __user *ubuf) { - unsigned i; int err; - u64 fpr_val; /* XXX fcr31 */ - init_fp_ctx(target); + if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t)) + err = fpr_get_fpa(target, &pos, &count, &kbuf, &ubuf); + else + err = fpr_get_msa(target, &pos, &count, &kbuf, &ubuf); + + return err; +} - if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t)) - return user_regset_copyin(&pos, &count, &kbuf, &ubuf, - &target->thread.fpu, - 0, sizeof(elf_fpregset_t)); +/* + * Copy the supplied NT_PRFPREG buffer to the floating-point context, + * !CONFIG_CPU_HAS_MSA variant. Buffer slots correspond 1:1 to FP + * context's general register slots. + */ +static int fpr_set_fpa(struct task_struct *target, + unsigned int *pos, unsigned int *count, + const void **kbuf, const void __user **ubuf) +{ + return user_regset_copyin(pos, count, kbuf, ubuf, + &target->thread.fpu, + 0, sizeof(elf_fpregset_t)); +} + +/* + * Copy the supplied NT_PRFPREG buffer to the floating-point context, + * CONFIG_CPU_HAS_MSA variant. Buffer slots are copied to lower 64 + * bits only of FP context's general register slots. + */ +static int fpr_set_msa(struct task_struct *target, + unsigned int *pos, unsigned int *count, + const void **kbuf, const void __user **ubuf) +{ + unsigned int i; + u64 fpr_val; + int err; BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t)); - for (i = 0; i < NUM_FPU_REGS && count >= sizeof(elf_fpreg_t); i++) { - err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + for (i = 0; i < NUM_FPU_REGS && *count >= sizeof(elf_fpreg_t); i++) { + err = user_regset_copyin(pos, count, kbuf, ubuf, &fpr_val, i * sizeof(elf_fpreg_t), (i + 1) * sizeof(elf_fpreg_t)); if (err) @@ -478,6 +516,26 @@ static int fpr_set(struct task_struct *target, return 0; } +/* Copy the supplied NT_PRFPREG buffer to the floating-point context. */ +static int fpr_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int err; + + /* XXX fcr31 */ + + init_fp_ctx(target); + + if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t)) + err = fpr_set_fpa(target, &pos, &count, &kbuf, &ubuf); + else + err = fpr_set_msa(target, &pos, &count, &kbuf, &ubuf); + + return err; +} + enum mips_regset { REGSET_GPR, REGSET_FPR, -- GitLab From dc24d0edf33c3e15099688b6bbdf7bdc24bf6e91 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 11 Dec 2017 22:52:15 +0000 Subject: [PATCH 1302/2547] MIPS: Guard against any partial write attempt with PTRACE_SETREGSET Complement commit d614fd58a283 ("mips/ptrace: Preserve previous registers for short regset write") and ensure that no partial register write attempt is made with PTRACE_SETREGSET, as we do not preinitialize any temporaries used to hold incoming register data and consequently random data could be written. It is the responsibility of the caller, such as `ptrace_regset', to arrange for writes to span whole registers only, so here we only assert that it has indeed happened. Signed-off-by: Maciej W. Rozycki Fixes: 72b22bbad1e7 ("MIPS: Don't assume 64-bit FP registers for FP regset") Cc: James Hogan Cc: Paul Burton Cc: Alex Smith Cc: Dave Martin Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v3.15+ Patchwork: https://patchwork.linux-mips.org/patch/17926/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 62e8ffd9370a..7fcadaaf330f 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -516,7 +516,15 @@ static int fpr_set_msa(struct task_struct *target, return 0; } -/* Copy the supplied NT_PRFPREG buffer to the floating-point context. */ +/* + * Copy the supplied NT_PRFPREG buffer to the floating-point context. + * + * We optimize for the case where `count % sizeof(elf_fpreg_t) == 0', + * which is supposed to have been guaranteed by the kernel before + * calling us, e.g. in `ptrace_regset'. We enforce that requirement, + * so that we can safely avoid preinitializing temporaries for + * partial register writes. + */ static int fpr_set(struct task_struct *target, const struct user_regset *regset, unsigned int pos, unsigned int count, @@ -524,6 +532,8 @@ static int fpr_set(struct task_struct *target, { int err; + BUG_ON(count % sizeof(elf_fpreg_t)); + /* XXX fcr31 */ init_fp_ctx(target); -- GitLab From 80b3ffce0196ea50068885d085ff981e4b8396f4 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 11 Dec 2017 22:53:14 +0000 Subject: [PATCH 1303/2547] MIPS: Consistently handle buffer counter with PTRACE_SETREGSET Update commit d614fd58a283 ("mips/ptrace: Preserve previous registers for short regset write") bug and consistently consume all data supplied to `fpr_set_msa' with the ptrace(2) PTRACE_SETREGSET request, such that a zero data buffer counter is returned where insufficient data has been given to fill a whole number of FP general registers. In reality this is not going to happen, as the caller is supposed to only supply data covering a whole number of registers and it is verified in `ptrace_regset' and again asserted in `fpr_set', however structuring code such that the presence of trailing partial FP general register data causes `fpr_set_msa' to return with a non-zero data buffer counter makes it appear that this trailing data will be used if there are subsequent writes made to FP registers, which is going to be the case with the FCSR once the missing write to that register has been fixed. Fixes: d614fd58a283 ("mips/ptrace: Preserve previous registers for short regset write") Signed-off-by: Maciej W. Rozycki Cc: James Hogan Cc: Paul Burton Cc: Alex Smith Cc: Dave Martin Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v4.11+ Patchwork: https://patchwork.linux-mips.org/patch/17927/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 7fcadaaf330f..47a01d5f26ea 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -504,7 +504,7 @@ static int fpr_set_msa(struct task_struct *target, int err; BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t)); - for (i = 0; i < NUM_FPU_REGS && *count >= sizeof(elf_fpreg_t); i++) { + for (i = 0; i < NUM_FPU_REGS && *count > 0; i++) { err = user_regset_copyin(pos, count, kbuf, ubuf, &fpr_val, i * sizeof(elf_fpreg_t), (i + 1) * sizeof(elf_fpreg_t)); -- GitLab From be07a6a1188372b6d19a3307ec33211fc9c9439d Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 11 Dec 2017 22:54:33 +0000 Subject: [PATCH 1304/2547] MIPS: Fix an FCSR access API regression with NT_PRFPREG and MSA Fix a commit 72b22bbad1e7 ("MIPS: Don't assume 64-bit FP registers for FP regset") public API regression, then activated by commit 1db1af84d6df ("MIPS: Basic MSA context switching support"), that caused the FCSR register not to be read or written for CONFIG_CPU_HAS_MSA kernel configurations (regardless of actual presence or absence of the MSA feature in a given processor) with ptrace(2) PTRACE_GETREGSET and PTRACE_SETREGSET requests nor recorded in core dumps. This is because with !CONFIG_CPU_HAS_MSA configurations the whole of `elf_fpregset_t' array is bulk-copied as it is, which includes the FCSR in one half of the last, 33rd slot, whereas with CONFIG_CPU_HAS_MSA configurations array elements are copied individually, and then only the leading 32 FGR slots while the remaining slot is ignored. Correct the code then such that only FGR slots are copied in the respective !MSA and MSA helpers an then the FCSR slot is handled separately in common code. Use `ptrace_setfcr31' to update the FCSR too, so that the read-only mask is respected. Retrieving a correct value of FCSR is important in debugging not only for the human to be able to get the right interpretation of the situation, but for correct operation of GDB as well. This is because the condition code bits in FSCR are used by GDB to determine the location to place a breakpoint at when single-stepping through an FPU branch instruction. If such a breakpoint is placed incorrectly (i.e. with the condition reversed), then it will be missed, likely causing the debuggee to run away from the control of GDB and consequently breaking the process of investigation. Fortunately GDB continues using the older PTRACE_GETFPREGS ptrace(2) request which is unaffected, so the regression only really hits with post-mortem debug sessions using a core dump file, in which case execution, and consequently single-stepping through branches is not possible. Of course core files created by buggy kernels out there will have the value of FCSR recorded clobbered, but such core files cannot be corrected and the person using them simply will have to be aware that the value of FCSR retrieved is not reliable. Which also means we can likely get away without defining a replacement API which would ensure a correct value of FSCR to be retrieved, or none at all. This is based on previous work by Alex Smith, extensively rewritten. Signed-off-by: Alex Smith Signed-off-by: James Hogan Signed-off-by: Maciej W. Rozycki Fixes: 72b22bbad1e7 ("MIPS: Don't assume 64-bit FP registers for FP regset") Cc: Paul Burton Cc: Dave Martin Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v3.15+ Patchwork: https://patchwork.linux-mips.org/patch/17928/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 47 ++++++++++++++++++++++++++++++--------- 1 file changed, 36 insertions(+), 11 deletions(-) diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 47a01d5f26ea..0a939593ccb7 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -422,7 +422,7 @@ static int gpr64_set(struct task_struct *target, /* * Copy the floating-point context to the supplied NT_PRFPREG buffer, * !CONFIG_CPU_HAS_MSA variant. FP context's general register slots - * correspond 1:1 to buffer slots. + * correspond 1:1 to buffer slots. Only general registers are copied. */ static int fpr_get_fpa(struct task_struct *target, unsigned int *pos, unsigned int *count, @@ -430,13 +430,14 @@ static int fpr_get_fpa(struct task_struct *target, { return user_regset_copyout(pos, count, kbuf, ubuf, &target->thread.fpu, - 0, sizeof(elf_fpregset_t)); + 0, NUM_FPU_REGS * sizeof(elf_fpreg_t)); } /* * Copy the floating-point context to the supplied NT_PRFPREG buffer, * CONFIG_CPU_HAS_MSA variant. Only lower 64 bits of FP context's - * general register slots are copied to buffer slots. + * general register slots are copied to buffer slots. Only general + * registers are copied. */ static int fpr_get_msa(struct task_struct *target, unsigned int *pos, unsigned int *count, @@ -458,20 +459,29 @@ static int fpr_get_msa(struct task_struct *target, return 0; } -/* Copy the floating-point context to the supplied NT_PRFPREG buffer. */ +/* + * Copy the floating-point context to the supplied NT_PRFPREG buffer. + * Choose the appropriate helper for general registers, and then copy + * the FCSR register separately. + */ static int fpr_get(struct task_struct *target, const struct user_regset *regset, unsigned int pos, unsigned int count, void *kbuf, void __user *ubuf) { + const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t); int err; - /* XXX fcr31 */ - if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t)) err = fpr_get_fpa(target, &pos, &count, &kbuf, &ubuf); else err = fpr_get_msa(target, &pos, &count, &kbuf, &ubuf); + if (err) + return err; + + err = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &target->thread.fpu.fcr31, + fcr31_pos, fcr31_pos + sizeof(u32)); return err; } @@ -479,7 +489,7 @@ static int fpr_get(struct task_struct *target, /* * Copy the supplied NT_PRFPREG buffer to the floating-point context, * !CONFIG_CPU_HAS_MSA variant. Buffer slots correspond 1:1 to FP - * context's general register slots. + * context's general register slots. Only general registers are copied. */ static int fpr_set_fpa(struct task_struct *target, unsigned int *pos, unsigned int *count, @@ -487,13 +497,14 @@ static int fpr_set_fpa(struct task_struct *target, { return user_regset_copyin(pos, count, kbuf, ubuf, &target->thread.fpu, - 0, sizeof(elf_fpregset_t)); + 0, NUM_FPU_REGS * sizeof(elf_fpreg_t)); } /* * Copy the supplied NT_PRFPREG buffer to the floating-point context, * CONFIG_CPU_HAS_MSA variant. Buffer slots are copied to lower 64 - * bits only of FP context's general register slots. + * bits only of FP context's general register slots. Only general + * registers are copied. */ static int fpr_set_msa(struct task_struct *target, unsigned int *pos, unsigned int *count, @@ -518,6 +529,8 @@ static int fpr_set_msa(struct task_struct *target, /* * Copy the supplied NT_PRFPREG buffer to the floating-point context. + * Choose the appropriate helper for general registers, and then copy + * the FCSR register separately. * * We optimize for the case where `count % sizeof(elf_fpreg_t) == 0', * which is supposed to have been guaranteed by the kernel before @@ -530,18 +543,30 @@ static int fpr_set(struct task_struct *target, unsigned int pos, unsigned int count, const void *kbuf, const void __user *ubuf) { + const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t); + u32 fcr31; int err; BUG_ON(count % sizeof(elf_fpreg_t)); - /* XXX fcr31 */ - init_fp_ctx(target); if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t)) err = fpr_set_fpa(target, &pos, &count, &kbuf, &ubuf); else err = fpr_set_msa(target, &pos, &count, &kbuf, &ubuf); + if (err) + return err; + + if (count > 0) { + err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &fcr31, + fcr31_pos, fcr31_pos + sizeof(u32)); + if (err) + return err; + + ptrace_setfcr31(target, fcr31); + } return err; } -- GitLab From 006501e039eec411842bb3150c41358867d320c2 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 11 Dec 2017 22:55:40 +0000 Subject: [PATCH 1305/2547] MIPS: Also verify sizeof `elf_fpreg_t' with PTRACE_SETREGSET Complement commit d614fd58a283 ("mips/ptrace: Preserve previous registers for short regset write") and like with the PTRACE_GETREGSET ptrace(2) request also apply a BUILD_BUG_ON check for the size of the `elf_fpreg_t' type in the PTRACE_SETREGSET request handler. Signed-off-by: Maciej W. Rozycki Fixes: d614fd58a283 ("mips/ptrace: Preserve previous registers for short regset write") Cc: James Hogan Cc: Paul Burton Cc: Alex Smith Cc: Dave Martin Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v4.11+ Patchwork: https://patchwork.linux-mips.org/patch/17929/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 0a939593ccb7..256908951a7c 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -447,6 +447,7 @@ static int fpr_get_msa(struct task_struct *target, u64 fpr_val; int err; + BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t)); for (i = 0; i < NUM_FPU_REGS; i++) { fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0); err = user_regset_copyout(pos, count, kbuf, ubuf, -- GitLab From c8c5a3a24d395b14447a9a89d61586a913840a3b Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 11 Dec 2017 22:56:54 +0000 Subject: [PATCH 1306/2547] MIPS: Disallow outsized PTRACE_SETREGSET NT_PRFPREG regset accesses Complement commit c23b3d1a5311 ("MIPS: ptrace: Change GP regset to use correct core dump register layout") and also reject outsized PTRACE_SETREGSET requests to the NT_PRFPREG regset, like with the NT_PRSTATUS regset. Signed-off-by: Maciej W. Rozycki Fixes: c23b3d1a5311 ("MIPS: ptrace: Change GP regset to use correct core dump register layout") Cc: James Hogan Cc: Paul Burton Cc: Alex Smith Cc: Dave Martin Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v3.17+ Patchwork: https://patchwork.linux-mips.org/patch/17930/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 256908951a7c..0b23b1ad99e6 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -550,6 +550,9 @@ static int fpr_set(struct task_struct *target, BUG_ON(count % sizeof(elf_fpreg_t)); + if (pos + count > sizeof(elf_fpregset_t)) + return -EIO; + init_fp_ctx(target); if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t)) -- GitLab From 10a6a6975691775bbcc677a04c6fd3120b5c1160 Mon Sep 17 00:00:00 2001 From: Cyrille Pitchen Date: Tue, 12 Dec 2017 14:40:12 +0100 Subject: [PATCH 1307/2547] Revert "dt-bindings: mtd: add sst25wf040b and en25s64 to sip-nor list" This reverts commit b07815d4eaf658b683c345d6e643895a20d92f29. The reverted commit was merged into v4-15-rc1 by mistake: it was taken from the IMX tree but the patch has never been sent to linux-mtd nor reviewed by any spi-nor maintainers. Actually, it would have been rejected since we add new values for the 'compatible' DT property only for SPI NOR memories that don't support the JEDEC READ ID op code (0x9F). Both en25s64 and sst25wf040b support the JEDEC READ ID op code, hence should use the "jedec,spi-nor" string alone as 'compatible' value. See the following link for more details: http://lists.infradead.org/pipermail/linux-mtd/2017-November/077425.html Signed-off-by: Cyrille Pitchen Acked-by: Marek Vasut --- Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt index 376fa2f50e6b..956bb046e599 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt @@ -13,7 +13,6 @@ Required properties: at25df321a at25df641 at26df081a - en25s64 mr25h128 mr25h256 mr25h10 @@ -33,7 +32,6 @@ Required properties: s25fl008k s25fl064k sst25vf040b - sst25wf040b m25p40 m25p80 m25p16 -- GitLab From 763efb6c6f2bd60d68c9ec1815f25d782f57f6f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 6 Dec 2017 15:44:51 +0100 Subject: [PATCH 1308/2547] drm/amdgpu: cleanup debugfs handling a bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the superflous .debugfs_init callback and register all files in amdgpu_device.c in just one function. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 46 ++++++---------------- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 -- 3 files changed, 11 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index e329faa6166f..c6fc67f75ffa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1250,11 +1250,6 @@ int amdgpu_debugfs_add_files(struct amdgpu_device *adev, const struct drm_info_list *files, unsigned nfiles); int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); - -#if defined(CONFIG_DEBUG_FS) -int amdgpu_debugfs_init(struct drm_minor *minor); -#endif - int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 98cc4df02b14..345663a784ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -66,8 +66,7 @@ MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); -static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev); -static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev); +static int amdgpu_debugfs_init(struct amdgpu_device *adev); static const char *amdgpu_asic_name[] = { "TAHITI", @@ -2405,17 +2404,13 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (r) DRM_ERROR("registering register debugfs failed (%d).\n", r); - r = amdgpu_debugfs_test_ib_ring_init(adev); - if (r) - DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r); - r = amdgpu_debugfs_firmware_init(adev); if (r) DRM_ERROR("registering firmware debugfs failed (%d).\n", r); - r = amdgpu_debugfs_vbios_dump_init(adev); + r = amdgpu_debugfs_init(adev); if (r) - DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r); + DRM_ERROR("Creating debugfs files failed (%d).\n", r); if ((amdgpu_testing & 1)) { if (adev->accel_working) @@ -3964,21 +3959,6 @@ static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) return 0; } -static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = { - {"amdgpu_test_ib", &amdgpu_debugfs_test_ib} -}; - -static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) -{ - return amdgpu_debugfs_add_files(adev, - amdgpu_debugfs_test_ib_ring_list, 1); -} - -int amdgpu_debugfs_init(struct drm_minor *minor) -{ - return 0; -} - static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *) m->private; @@ -3989,19 +3969,19 @@ static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data) return 0; } -static const struct drm_info_list amdgpu_vbios_dump_list[] = { - {"amdgpu_vbios", - amdgpu_debugfs_get_vbios_dump, - 0, NULL}, +static const struct drm_info_list amdgpu_debugfs_list[] = { + {"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump}, + {"amdgpu_test_ib", &amdgpu_debugfs_test_ib} }; -static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev) +static int amdgpu_debugfs_init(struct amdgpu_device *adev) { - return amdgpu_debugfs_add_files(adev, - amdgpu_vbios_dump_list, 1); + return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list, + ARRAY_SIZE(amdgpu_debugfs_list)); } + #else -static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) +static int amdgpu_debugfs_init(struct amdgpu_device *adev) { return 0; } @@ -4009,9 +3989,5 @@ static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) { return 0; } -static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev) -{ - return 0; -} static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 51b76688ab90..0b039bdcf84e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -850,9 +850,6 @@ static struct drm_driver kms_driver = { .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, .get_scanout_position = amdgpu_get_crtc_scanout_position, -#if defined(CONFIG_DEBUG_FS) - .debugfs_init = amdgpu_debugfs_init, -#endif .irq_preinstall = amdgpu_irq_preinstall, .irq_postinstall = amdgpu_irq_postinstall, .irq_uninstall = amdgpu_irq_uninstall, -- GitLab From 79588d21ad312d9cd16a867c0d13278e6377a653 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 6 Dec 2017 16:24:49 +0100 Subject: [PATCH 1309/2547] drm/amdgpu: add amdgpu_evict_vram debugfs file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Torture test for MM and VM support, can be used to evict all VRAM while the system is under load. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 345663a784ae..b10aecc7d146 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3969,9 +3969,20 @@ static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data) return 0; } +static int amdgpu_debugfs_evict_vram(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = dev->dev_private; + + seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev)); + return 0; +} + static const struct drm_info_list amdgpu_debugfs_list[] = { {"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump}, - {"amdgpu_test_ib", &amdgpu_debugfs_test_ib} + {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}, + {"amdgpu_evict_vram", &amdgpu_debugfs_evict_vram} }; static int amdgpu_debugfs_init(struct amdgpu_device *adev) -- GitLab From 94c6f5e4d1574094a91b1712536ab5b6a43f7a23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 30 Nov 2017 14:12:53 +0100 Subject: [PATCH 1310/2547] drm/amdgpu: stop joining PDEs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit That doesn't hit any more most of the time anyway. Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 41 +++++--------------------- 1 file changed, 7 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index dbe37d621796..17ae6afdef70 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1076,8 +1076,7 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, struct amdgpu_bo *shadow; struct amdgpu_ring *ring = NULL; uint64_t pd_addr, shadow_addr = 0; - uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; - unsigned count = 0, pt_idx, ndw = 0; + unsigned pt_idx, ndw = 0; struct amdgpu_job *job; struct amdgpu_pte_update_params params; struct dma_fence *fence = NULL; @@ -1149,41 +1148,15 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, parent->entries[pt_idx].addr = pt | AMDGPU_PTE_VALID; - pde = pd_addr + pt_idx * 8; incr = amdgpu_bo_size(bo); - if (((last_pde + 8 * count) != pde) || - ((last_pt + incr * count) != pt) || - (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { - - if (count) { - if (shadow) - params.func(¶ms, - last_shadow, - last_pt, count, - incr, - AMDGPU_PTE_VALID); - - params.func(¶ms, last_pde, - last_pt, count, incr, - AMDGPU_PTE_VALID); - } - - count = 1; - last_pde = pde; - last_shadow = shadow_addr + pt_idx * 8; - last_pt = pt; - } else { - ++count; + if (shadow) { + pde = shadow_addr + pt_idx * 8; + params.func(¶ms, pde, pt, 1, incr, + AMDGPU_PTE_VALID); } - } - if (count) { - if (vm->root.base.bo->shadow) - params.func(¶ms, last_shadow, last_pt, - count, incr, AMDGPU_PTE_VALID); - - params.func(¶ms, last_pde, last_pt, - count, incr, AMDGPU_PTE_VALID); + pde = pd_addr + pt_idx * 8; + params.func(¶ms, pde, pt, 1, incr, AMDGPU_PTE_VALID); } if (!vm->use_cpu_for_update) { -- GitLab From b852f3d3fb5d770f54c10614e6320a29943eb52f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 30 Nov 2017 15:19:50 +0100 Subject: [PATCH 1311/2547] drm/amdgpu: update one PDE at a time v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Horrible inefficient, but avoids problems when the root PD size becomes to big. v2: remove incr as well. Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 80 +++++++++++--------------- 1 file changed, 34 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 17ae6afdef70..1c3dd6e0ed33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1069,18 +1069,20 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, * Makes sure all entries in @parent are up to date. * Returns 0 for success, error for failure. */ -static int amdgpu_vm_update_level(struct amdgpu_device *adev, - struct amdgpu_vm *vm, - struct amdgpu_vm_pt *parent) +static int amdgpu_vm_update_pde(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_vm_pt *parent, + struct amdgpu_vm_pt *entry) { + struct amdgpu_pte_update_params params; + struct amdgpu_bo *bo = entry->base.bo; struct amdgpu_bo *shadow; struct amdgpu_ring *ring = NULL; uint64_t pd_addr, shadow_addr = 0; - unsigned pt_idx, ndw = 0; struct amdgpu_job *job; - struct amdgpu_pte_update_params params; struct dma_fence *fence = NULL; - uint32_t incr; + unsigned ndw = 0; + uint64_t pde, pt; int r; @@ -1102,20 +1104,14 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); - /* padding, etc. */ + /* should be sufficient for two commands plus padding, etc. */ ndw = 64; - /* assume the worst case */ - ndw += parent->last_entry_used * 6; - pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); - - if (shadow) { + if (shadow) shadow_addr = amdgpu_bo_gpu_offset(shadow); - ndw *= 2; - } else { + else shadow_addr = 0; - } r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); if (r) @@ -1125,40 +1121,30 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, params.func = amdgpu_vm_do_set_ptes; } + spin_lock(&vm->status_lock); + list_del_init(&entry->base.vm_status); + spin_unlock(&vm->status_lock); - /* walk over the address space and update the directory */ - for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { - struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; - struct amdgpu_bo *bo = entry->base.bo; - uint64_t pde, pt; - - if (bo == NULL) - continue; - - spin_lock(&vm->status_lock); - list_del_init(&entry->base.vm_status); - spin_unlock(&vm->status_lock); - - pt = amdgpu_bo_gpu_offset(bo); - pt = amdgpu_gart_get_vm_pde(adev, pt); - /* Don't update huge pages here */ - if ((parent->entries[pt_idx].addr & AMDGPU_PDE_PTE) || - parent->entries[pt_idx].addr == (pt | AMDGPU_PTE_VALID)) - continue; - - parent->entries[pt_idx].addr = pt | AMDGPU_PTE_VALID; + pt = amdgpu_bo_gpu_offset(bo); + pt = amdgpu_gart_get_vm_pde(adev, pt); + /* Don't update huge pages here */ + if (entry->addr & AMDGPU_PDE_PTE || + entry->addr == (pt | AMDGPU_PTE_VALID)) { + if (!vm->use_cpu_for_update) + amdgpu_job_free(job); + return 0; + } - incr = amdgpu_bo_size(bo); - if (shadow) { - pde = shadow_addr + pt_idx * 8; - params.func(¶ms, pde, pt, 1, incr, - AMDGPU_PTE_VALID); - } + entry->addr = pt | AMDGPU_PTE_VALID; - pde = pd_addr + pt_idx * 8; - params.func(¶ms, pde, pt, 1, incr, AMDGPU_PTE_VALID); + if (shadow) { + pde = shadow_addr + (entry - parent->entries) * 8; + params.func(¶ms, pde, pt, 1, 0, AMDGPU_PTE_VALID); } + pde = pd_addr + (entry - parent->entries) * 8; + params.func(¶ms, pde, pt, 1, 0, AMDGPU_PTE_VALID); + if (!vm->use_cpu_for_update) { if (params.ib->length_dw == 0) { amdgpu_job_free(job); @@ -1249,14 +1235,16 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev, bo = bo_base->bo->parent; if (bo) { struct amdgpu_vm_bo_base *parent; - struct amdgpu_vm_pt *pt; + struct amdgpu_vm_pt *pt, *entry; parent = list_first_entry(&bo->va, struct amdgpu_vm_bo_base, bo_list); pt = container_of(parent, struct amdgpu_vm_pt, base); + entry = container_of(bo_base, struct amdgpu_vm_pt, + base); - r = amdgpu_vm_update_level(adev, vm, pt); + r = amdgpu_vm_update_pde(adev, vm, pt, entry); if (r) { amdgpu_vm_invalidate_level(vm, &vm->root); return r; -- GitLab From 2ffe31deb27579e2f2c9444e01f4d8abf385d145 Mon Sep 17 00:00:00 2001 From: Pixel Ding Date: Mon, 11 Dec 2017 16:48:33 +0800 Subject: [PATCH 1312/2547] drm/amdgpu: use polling mem to set SDMA3 wptr for VF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Tonga VF, there're 2 sources updating wptr registers for sdma3: 1) polling mem and 2) doorbell. When doorbell and polling mem are both enabled on sdma3, there will be collision hit in occasion between those two sources when ucode and h/w are doing the updating on wptr register in parallel. Issue doesn't happen on CP GFX/Compute since CP drops all doorbell writes when VF is inactive. So enable polling mem and don't use doorbell for SDMA3. Signed-off-by: Pixel Ding Reviewed-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 + drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 27 +++++++++++++++++------- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 641e3fd7ba3c..010f69084af5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -186,6 +186,7 @@ struct amdgpu_ring { uint64_t eop_gpu_addr; u32 doorbell_index; bool use_doorbell; + bool use_pollmem; unsigned wptr_offs; unsigned fence_offs; uint64_t current_ctx; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index c8c93f9dac21..41c60f5ac96e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -355,7 +355,7 @@ static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; u32 wptr; - if (ring->use_doorbell) { + if (ring->use_doorbell || ring->use_pollmem) { /* XXX check if swapping is necessary on BE */ wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; } else { @@ -380,10 +380,13 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) if (ring->use_doorbell) { u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; - /* XXX check if swapping is necessary on BE */ WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); + } else if (ring->use_pollmem) { + u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; + + WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); } else { int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; @@ -718,10 +721,14 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], upper_32_bits(wptr_gpu_addr)); wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); - if (amdgpu_sriov_vf(adev)) - wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); + if (ring->use_pollmem) + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, + SDMA0_GFX_RB_WPTR_POLL_CNTL, + ENABLE, 1); else - wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0); + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, + SDMA0_GFX_RB_WPTR_POLL_CNTL, + ENABLE, 0); WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); /* enable DMA RB */ @@ -1203,9 +1210,13 @@ static int sdma_v3_0_sw_init(void *handle) for (i = 0; i < adev->sdma.num_instances; i++) { ring = &adev->sdma.instance[i].ring; ring->ring_obj = NULL; - ring->use_doorbell = true; - ring->doorbell_index = (i == 0) ? - AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; + if (!amdgpu_sriov_vf(adev)) { + ring->use_doorbell = true; + ring->doorbell_index = (i == 0) ? + AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; + } else { + ring->use_pollmem = true; + } sprintf(ring->name, "sdma%d", i); r = amdgpu_ring_init(adev, ring, 1024, -- GitLab From e3a1b32a12ef83e260a307e678d053d5f4570acd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 1 Dec 2017 13:28:46 +0100 Subject: [PATCH 1313/2547] drm/amdgpu: avoid the modulo in amdgpu_vm_get_entry MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We can do this with a simple mask as well. Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 1c3dd6e0ed33..bd6296a6dab1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1285,11 +1285,11 @@ void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, *parent = NULL; *entry = &p->vm->root; while ((*entry)->entries) { - unsigned idx = addr >> amdgpu_vm_level_shift(p->adev, level++); + unsigned shift = amdgpu_vm_level_shift(p->adev, level++); - idx %= amdgpu_bo_size((*entry)->base.bo) / 8; *parent = *entry; - *entry = &(*entry)->entries[idx]; + *entry = &(*entry)->entries[addr >> shift]; + addr &= (1ULL << shift) - 1; } if (level != p->adev->vm_manager.num_level) -- GitLab From 8f19cd78c986fb0eb24a1847931c096ec9e214a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 30 Nov 2017 15:28:03 +0100 Subject: [PATCH 1314/2547] drm/amdgpu: remove last_entry_used from the VM code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not needed any more. Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 52 ++++++++++++++------------ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 - 2 files changed, 29 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index bd6296a6dab1..25fdcba5681c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -329,9 +329,6 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, to >= amdgpu_vm_num_entries(adev, level)) return -EINVAL; - if (to > parent->last_entry_used) - parent->last_entry_used = to; - ++level; saddr = saddr & ((1 << shift) - 1); eaddr = eaddr & ((1 << shift) - 1); @@ -1184,16 +1181,19 @@ static int amdgpu_vm_update_pde(struct amdgpu_device *adev, * * Mark all PD level as invalid after an error. */ -static void amdgpu_vm_invalidate_level(struct amdgpu_vm *vm, - struct amdgpu_vm_pt *parent) +static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_vm_pt *parent, + unsigned level) { - unsigned pt_idx; + unsigned pt_idx, num_entries; /* * Recurse into the subdirectories. This recursion is harmless because * we only have a maximum of 5 layers. */ - for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { + num_entries = amdgpu_vm_num_entries(adev, level); + for (pt_idx = 0; pt_idx < num_entries; ++pt_idx) { struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; if (!entry->base.bo) @@ -1204,7 +1204,7 @@ static void amdgpu_vm_invalidate_level(struct amdgpu_vm *vm, if (list_empty(&entry->base.vm_status)) list_add(&entry->base.vm_status, &vm->relocated); spin_unlock(&vm->status_lock); - amdgpu_vm_invalidate_level(vm, entry); + amdgpu_vm_invalidate_level(adev, vm, entry, level + 1); } } @@ -1246,7 +1246,8 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev, r = amdgpu_vm_update_pde(adev, vm, pt, entry); if (r) { - amdgpu_vm_invalidate_level(vm, &vm->root); + amdgpu_vm_invalidate_level(adev, vm, + &vm->root, 0); return r; } spin_lock(&vm->status_lock); @@ -1649,7 +1650,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, error_free: amdgpu_job_free(job); - amdgpu_vm_invalidate_level(vm, &vm->root); + amdgpu_vm_invalidate_level(adev, vm, &vm->root, 0); return r; } @@ -2713,26 +2714,31 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, /** * amdgpu_vm_free_levels - free PD/PT levels * - * @level: PD/PT starting level to free + * @adev: amdgpu device structure + * @parent: PD/PT starting level to free + * @level: level of parent structure * * Free the page directory or page table level and all sub levels. */ -static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level) +static void amdgpu_vm_free_levels(struct amdgpu_device *adev, + struct amdgpu_vm_pt *parent, + unsigned level) { - unsigned i; + unsigned i, num_entries = amdgpu_vm_num_entries(adev, level); - if (level->base.bo) { - list_del(&level->base.bo_list); - list_del(&level->base.vm_status); - amdgpu_bo_unref(&level->base.bo->shadow); - amdgpu_bo_unref(&level->base.bo); + if (parent->base.bo) { + list_del(&parent->base.bo_list); + list_del(&parent->base.vm_status); + amdgpu_bo_unref(&parent->base.bo->shadow); + amdgpu_bo_unref(&parent->base.bo); } - if (level->entries) - for (i = 0; i <= level->last_entry_used; i++) - amdgpu_vm_free_levels(&level->entries[i]); + if (parent->entries) + for (i = 0; i < num_entries; i++) + amdgpu_vm_free_levels(adev, &parent->entries[i], + level + 1); - kvfree(level->entries); + kvfree(parent->entries); } /** @@ -2790,7 +2796,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) if (r) { dev_err(adev->dev, "Leaking page tables because BO reservation failed\n"); } else { - amdgpu_vm_free_levels(&vm->root); + amdgpu_vm_free_levels(adev, &vm->root, 0); amdgpu_bo_unreserve(root); } amdgpu_bo_unref(&root); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 159980414964..2f1d0c8c093a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -142,7 +142,6 @@ struct amdgpu_vm_pt { /* array of page tables, one for each directory entry */ struct amdgpu_vm_pt *entries; - unsigned last_entry_used; }; #define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr)) -- GitLab From 78eb2f0c719e6427eb5ac36cebe18df0578421d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 30 Nov 2017 15:41:28 +0100 Subject: [PATCH 1315/2547] drm/amdgpu: remove keeping the addr of the VM PDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No more double house keeping. Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 13 ++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 25fdcba5681c..9e6cf130f832 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -383,7 +383,6 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, spin_lock(&vm->status_lock); list_add(&entry->base.vm_status, &vm->relocated); spin_unlock(&vm->status_lock); - entry->addr = 0; } if (level < adev->vm_manager.num_level) { @@ -1125,15 +1124,12 @@ static int amdgpu_vm_update_pde(struct amdgpu_device *adev, pt = amdgpu_bo_gpu_offset(bo); pt = amdgpu_gart_get_vm_pde(adev, pt); /* Don't update huge pages here */ - if (entry->addr & AMDGPU_PDE_PTE || - entry->addr == (pt | AMDGPU_PTE_VALID)) { + if (entry->huge) { if (!vm->use_cpu_for_update) amdgpu_job_free(job); return 0; } - entry->addr = pt | AMDGPU_PTE_VALID; - if (shadow) { pde = shadow_addr + (entry - parent->entries) * 8; params.func(¶ms, pde, pt, 1, 0, AMDGPU_PTE_VALID); @@ -1199,7 +1195,6 @@ static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev, if (!entry->base.bo) continue; - entry->addr = ~0ULL; spin_lock(&vm->status_lock); if (list_empty(&entry->base.vm_status)) list_add(&entry->base.vm_status, &vm->relocated); @@ -1332,10 +1327,10 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, flags |= AMDGPU_PDE_PTE; } - if (entry->addr == (dst | flags)) + if (!entry->huge && !(flags & AMDGPU_PDE_PTE)) return; - entry->addr = (dst | flags); + entry->huge = !!(flags & AMDGPU_PDE_PTE); if (use_cpu_update) { /* In case a huge page is replaced with a system @@ -1409,7 +1404,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, amdgpu_vm_handle_huge_pages(params, entry, parent, nptes, dst, flags); /* We don't need to update PTEs for huge pages */ - if (entry->addr & AMDGPU_PDE_PTE) + if (entry->huge) continue; pt = entry->base.bo; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 2f1d0c8c093a..e52bf980669f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -138,7 +138,7 @@ struct amdgpu_vm_bo_base { struct amdgpu_vm_pt { struct amdgpu_vm_bo_base base; - uint64_t addr; + bool huge; /* array of page tables, one for each directory entry */ struct amdgpu_vm_pt *entries; -- GitLab From 6989f2460f7d8163fcc4f0c99e47d62d22ea6f28 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 30 Nov 2017 19:08:05 +0100 Subject: [PATCH 1316/2547] drm/amdgpu: batch PDE updates again MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now instead of one submission for each PDE batch them together over all PDs who need an update. Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 203 ++++++++++++------------- 1 file changed, 94 insertions(+), 109 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 9e6cf130f832..2482b5dbe31c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1056,118 +1056,46 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, } /* - * amdgpu_vm_update_level - update a single level in the hierarchy + * amdgpu_vm_update_pde - update a single level in the hierarchy * - * @adev: amdgpu_device pointer + * @param: parameters for the update * @vm: requested vm * @parent: parent directory + * @entry: entry to update * - * Makes sure all entries in @parent are up to date. - * Returns 0 for success, error for failure. + * Makes sure the requested entry in parent is up to date. */ -static int amdgpu_vm_update_pde(struct amdgpu_device *adev, - struct amdgpu_vm *vm, - struct amdgpu_vm_pt *parent, - struct amdgpu_vm_pt *entry) +static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, + struct amdgpu_vm *vm, + struct amdgpu_vm_pt *parent, + struct amdgpu_vm_pt *entry) { - struct amdgpu_pte_update_params params; - struct amdgpu_bo *bo = entry->base.bo; - struct amdgpu_bo *shadow; - struct amdgpu_ring *ring = NULL; + struct amdgpu_bo *bo = entry->base.bo, *shadow = NULL; uint64_t pd_addr, shadow_addr = 0; - struct amdgpu_job *job; - struct dma_fence *fence = NULL; - unsigned ndw = 0; uint64_t pde, pt; - int r; - - if (!parent->entries) - return 0; - - memset(¶ms, 0, sizeof(params)); - params.adev = adev; - shadow = parent->base.bo->shadow; + /* Don't update huge pages here */ + if (entry->huge) + return; if (vm->use_cpu_for_update) { pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); - r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); - if (unlikely(r)) - return r; - - params.func = amdgpu_vm_cpu_set_ptes; } else { - ring = container_of(vm->entity.sched, struct amdgpu_ring, - sched); - - /* should be sufficient for two commands plus padding, etc. */ - ndw = 64; - pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); + shadow = parent->base.bo->shadow; if (shadow) shadow_addr = amdgpu_bo_gpu_offset(shadow); - else - shadow_addr = 0; - - r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); - if (r) - return r; - - params.ib = &job->ibs[0]; - params.func = amdgpu_vm_do_set_ptes; } - spin_lock(&vm->status_lock); - list_del_init(&entry->base.vm_status); - spin_unlock(&vm->status_lock); - pt = amdgpu_bo_gpu_offset(bo); - pt = amdgpu_gart_get_vm_pde(adev, pt); - /* Don't update huge pages here */ - if (entry->huge) { - if (!vm->use_cpu_for_update) - amdgpu_job_free(job); - return 0; - } - + pt = amdgpu_gart_get_vm_pde(params->adev, pt); if (shadow) { pde = shadow_addr + (entry - parent->entries) * 8; - params.func(¶ms, pde, pt, 1, 0, AMDGPU_PTE_VALID); + params->func(params, pde, pt, 1, 0, AMDGPU_PTE_VALID); } pde = pd_addr + (entry - parent->entries) * 8; - params.func(¶ms, pde, pt, 1, 0, AMDGPU_PTE_VALID); - - if (!vm->use_cpu_for_update) { - if (params.ib->length_dw == 0) { - amdgpu_job_free(job); - } else { - amdgpu_ring_pad_ib(ring, params.ib); - amdgpu_sync_resv(adev, &job->sync, - parent->base.bo->tbo.resv, - AMDGPU_FENCE_OWNER_VM, false); - if (shadow) - amdgpu_sync_resv(adev, &job->sync, - shadow->tbo.resv, - AMDGPU_FENCE_OWNER_VM, false); - - WARN_ON(params.ib->length_dw > ndw); - r = amdgpu_job_submit(job, ring, &vm->entity, - AMDGPU_FENCE_OWNER_VM, &fence); - if (r) - goto error_free; - - amdgpu_bo_fence(parent->base.bo, fence, true); - dma_fence_put(vm->last_update); - vm->last_update = fence; - } - } - - return 0; - -error_free: - amdgpu_job_free(job); - return r; + params->func(params, pde, pt, 1, 0, AMDGPU_PTE_VALID); } /* @@ -1215,41 +1143,63 @@ static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev, int amdgpu_vm_update_directories(struct amdgpu_device *adev, struct amdgpu_vm *vm) { + struct amdgpu_pte_update_params params; + struct amdgpu_job *job; + unsigned ndw = 0; int r = 0; + if (list_empty(&vm->relocated)) + return 0; + +restart: + memset(¶ms, 0, sizeof(params)); + params.adev = adev; + + if (vm->use_cpu_for_update) { + r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); + if (unlikely(r)) + return r; + + params.func = amdgpu_vm_cpu_set_ptes; + } else { + ndw = 512 * 8; + r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); + if (r) + return r; + + params.ib = &job->ibs[0]; + params.func = amdgpu_vm_do_set_ptes; + } + spin_lock(&vm->status_lock); while (!list_empty(&vm->relocated)) { - struct amdgpu_vm_bo_base *bo_base; + struct amdgpu_vm_bo_base *bo_base, *parent; + struct amdgpu_vm_pt *pt, *entry; struct amdgpu_bo *bo; bo_base = list_first_entry(&vm->relocated, struct amdgpu_vm_bo_base, vm_status); + list_del_init(&bo_base->vm_status); spin_unlock(&vm->status_lock); bo = bo_base->bo->parent; - if (bo) { - struct amdgpu_vm_bo_base *parent; - struct amdgpu_vm_pt *pt, *entry; - - parent = list_first_entry(&bo->va, - struct amdgpu_vm_bo_base, - bo_list); - pt = container_of(parent, struct amdgpu_vm_pt, base); - entry = container_of(bo_base, struct amdgpu_vm_pt, - base); - - r = amdgpu_vm_update_pde(adev, vm, pt, entry); - if (r) { - amdgpu_vm_invalidate_level(adev, vm, - &vm->root, 0); - return r; - } + if (!bo) { spin_lock(&vm->status_lock); - } else { - spin_lock(&vm->status_lock); - list_del_init(&bo_base->vm_status); + continue; } + + parent = list_first_entry(&bo->va, struct amdgpu_vm_bo_base, + bo_list); + pt = container_of(parent, struct amdgpu_vm_pt, base); + entry = container_of(bo_base, struct amdgpu_vm_pt, base); + + amdgpu_vm_update_pde(¶ms, vm, pt, entry); + + spin_lock(&vm->status_lock); + if (!vm->use_cpu_for_update && + (ndw - params.ib->length_dw) < 32) + break; } spin_unlock(&vm->status_lock); @@ -1257,8 +1207,43 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev, /* Flush HDP */ mb(); amdgpu_gart_flush_gpu_tlb(adev, 0); + } else if (params.ib->length_dw == 0) { + amdgpu_job_free(job); + } else { + struct amdgpu_bo *root = vm->root.base.bo; + struct amdgpu_ring *ring; + struct dma_fence *fence; + + ring = container_of(vm->entity.sched, struct amdgpu_ring, + sched); + + amdgpu_ring_pad_ib(ring, params.ib); + amdgpu_sync_resv(adev, &job->sync, root->tbo.resv, + AMDGPU_FENCE_OWNER_VM, false); + if (root->shadow) + amdgpu_sync_resv(adev, &job->sync, + root->shadow->tbo.resv, + AMDGPU_FENCE_OWNER_VM, false); + + WARN_ON(params.ib->length_dw > ndw); + r = amdgpu_job_submit(job, ring, &vm->entity, + AMDGPU_FENCE_OWNER_VM, &fence); + if (r) + goto error; + + amdgpu_bo_fence(root, fence, true); + dma_fence_put(vm->last_update); + vm->last_update = fence; } + if (!list_empty(&vm->relocated)) + goto restart; + + return 0; + +error: + amdgpu_vm_invalidate_level(adev, vm, &vm->root, 0); + amdgpu_job_free(job); return r; } -- GitLab From 3de676d8e71c0a4094b3e5005a311c36c6b6ffc6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 29 Nov 2017 13:27:26 +0100 Subject: [PATCH 1317/2547] drm/amdgpu: allow get_vm_pde to change flags as well MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit And also provide the level for which we need a PDE. Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 20 +++++++++++++------- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 ++++++---- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 12 +++++++----- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 12 +++++++----- 11 files changed, 54 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c6fc67f75ffa..c8bc1a982dc4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -346,7 +346,8 @@ struct amdgpu_gart_funcs { uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, uint32_t flags); /* get the pde for a given mc addr */ - u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr); + void (*get_vm_pde)(struct amdgpu_device *adev, int level, + u64 *dst, u64 *flags); uint32_t (*get_invalidate_req)(unsigned int vm_id); }; @@ -1826,7 +1827,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) -#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr)) +#define amdgpu_gart_get_vm_pde(adev, level, dst, flags) (adev)->gart.gart_funcs->get_vm_pde((adev), (level), (dst), (flags)) #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 2482b5dbe31c..68039ad3c8e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1070,9 +1070,10 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, struct amdgpu_vm_pt *parent, struct amdgpu_vm_pt *entry) { - struct amdgpu_bo *bo = entry->base.bo, *shadow = NULL; + struct amdgpu_bo *bo = entry->base.bo, *shadow = NULL, *pbo; uint64_t pd_addr, shadow_addr = 0; - uint64_t pde, pt; + uint64_t pde, pt, flags; + unsigned level; /* Don't update huge pages here */ if (entry->huge) @@ -1087,15 +1088,19 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, shadow_addr = amdgpu_bo_gpu_offset(shadow); } + for (level = 0, pbo = parent->base.bo->parent; pbo; ++level) + pbo = pbo->parent; + pt = amdgpu_bo_gpu_offset(bo); - pt = amdgpu_gart_get_vm_pde(params->adev, pt); + flags = AMDGPU_PTE_VALID; + amdgpu_gart_get_vm_pde(params->adev, level, &pt, &flags); if (shadow) { pde = shadow_addr + (entry - parent->entries) * 8; - params->func(params, pde, pt, 1, 0, AMDGPU_PTE_VALID); + params->func(params, pde, pt, 1, 0, flags); } pde = pd_addr + (entry - parent->entries) * 8; - params->func(params, pde, pt, 1, 0, AMDGPU_PTE_VALID); + params->func(params, pde, pt, 1, 0, flags); } /* @@ -1305,7 +1310,6 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, !(flags & AMDGPU_PTE_VALID)) { dst = amdgpu_bo_gpu_offset(entry->base.bo); - dst = amdgpu_gart_get_vm_pde(p->adev, dst); flags = AMDGPU_PTE_VALID; } else { /* Set the huge page flag to stop scanning at this PDE */ @@ -1314,9 +1318,11 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, if (!entry->huge && !(flags & AMDGPU_PDE_PTE)) return; - entry->huge = !!(flags & AMDGPU_PDE_PTE); + amdgpu_gart_get_vm_pde(p->adev, p->adev->vm_manager.num_level - 1, + &dst, &flags); + if (use_cpu_update) { /* In case a huge page is replaced with a system * memory mapping, p->pages_addr != NULL and diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 50a1edb7c32e..58a8ef4f353d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3686,10 +3686,11 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); + uint64_t flags = AMDGPU_PTE_VALID; unsigned eng = ring->vm_inv_eng; - pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); - pd_addr |= AMDGPU_PTE_VALID; + amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; gfx_v9_0_write_data_to_reg(ring, usepfp, true, hub->ctx0_ptb_addr_lo32 + (2 * vm_id), diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 468281f10e8d..279f43a2b1a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -395,10 +395,10 @@ static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev, return pte_flag; } -static uint64_t gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr) +static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level, + uint64_t *addr, uint64_t *flags) { - BUG_ON(addr & 0xFFFFFF0000000FFFULL); - return addr; + BUG_ON(*addr & 0xFFFFFF0000000FFFULL); } static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 68a85051f4b7..9c28e18741ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -480,10 +480,10 @@ static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev, return pte_flag; } -static uint64_t gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr) +static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, + uint64_t *addr, uint64_t *flags) { - BUG_ON(addr & 0xFFFFFF0000000FFFULL); - return addr; + BUG_ON(*addr & 0xFFFFFF0000000FFFULL); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 46ec97e70e5c..efed20ac4a01 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -677,10 +677,10 @@ static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev, return pte_flag; } -static uint64_t gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr) +static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, + uint64_t *addr, uint64_t *flags) { - BUG_ON(addr & 0xFFFFFF0000000FFFULL); - return addr; + BUG_ON(*addr & 0xFFFFFF0000000FFFULL); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index aef5f70547ac..51856e53d8c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -474,11 +474,13 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, return pte_flag; } -static u64 gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, u64 addr) +static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, + uint64_t *addr, uint64_t *flags) { - addr = adev->vm_manager.vram_base_offset + addr - adev->mc.vram_start; - BUG_ON(addr & 0xFFFF00000000003FULL); - return addr; + if (!(*flags & AMDGPU_PDE_PTE)) + *addr = adev->vm_manager.vram_base_offset + *addr - + adev->mc.vram_start; + BUG_ON(*addr & 0xFFFF00000000003FULL); } static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 1fb51946a718..e190ce163e30 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1146,10 +1146,11 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, { struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); + uint64_t flags = AMDGPU_PTE_VALID; unsigned eng = ring->vm_inv_eng; - pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); - pd_addr |= AMDGPU_PTE_VALID; + amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 23b446236c80..4ec4447d33c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -1295,11 +1295,12 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, { struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); - uint32_t data0, data1, mask; + uint64_t flags = AMDGPU_PTE_VALID; unsigned eng = ring->vm_inv_eng; + uint32_t data0, data1, mask; - pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); - pd_addr |= AMDGPU_PTE_VALID; + amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2; data1 = upper_32_bits(pd_addr); @@ -1346,10 +1347,11 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, { struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); + uint64_t flags = AMDGPU_PTE_VALID; unsigned eng = ring->vm_inv_eng; - pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); - pd_addr |= AMDGPU_PTE_VALID; + amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 55f01868a9b6..0071a5c43e3d 100755 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -969,10 +969,11 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring, { struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); + uint64_t flags = AMDGPU_PTE_VALID; unsigned eng = ring->vm_inv_eng; - pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); - pd_addr |= AMDGPU_PTE_VALID; + amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; amdgpu_ring_write(ring, VCE_CMD_REG_WRITE); amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index aa0787de51a3..deb3fba790a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -892,11 +892,12 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, { struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); - uint32_t data0, data1, mask; + uint64_t flags = AMDGPU_PTE_VALID; unsigned eng = ring->vm_inv_eng; + uint32_t data0, data1, mask; - pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); - pd_addr |= AMDGPU_PTE_VALID; + amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2; data1 = upper_32_bits(pd_addr); @@ -1024,10 +1025,11 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, { struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); + uint64_t flags = AMDGPU_PTE_VALID; unsigned eng = ring->vm_inv_eng; - pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); - pd_addr |= AMDGPU_PTE_VALID; + amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); amdgpu_ring_write(ring, -- GitLab From 0aaa59f5256eb2d23f487c3e2c870c7bc0d043de Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Fri, 1 Dec 2017 18:21:34 +0800 Subject: [PATCH 1318/2547] drm/ttm: fix incorrect calculate on shrink_pages MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit shrink_pages is in unit of Order after ttm_page_pool_free, but it is used by nr_free in next round so need change it into native page unit Signed-off-by: Monk Liu Reviewed-by: Roger He Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 44343a2bf55c..71945ccaf012 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -455,6 +455,7 @@ ttm_pool_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) freed += (nr_free_pool - shrink_pages) << pool->order; if (freed >= sc->nr_to_scan) break; + shrink_pages <<= pool->order; } mutex_unlock(&lock); return freed; -- GitLab From a8d25a8629e79ae891cdb81f0d706422e20203fa Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Fri, 1 Dec 2017 18:23:56 +0800 Subject: [PATCH 1319/2547] drm/ttm: max_cpages is in unit of native page MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix calculation. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 71945ccaf012..b5ba6441489f 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -544,7 +544,7 @@ static int ttm_alloc_new_pages(struct list_head *pages, gfp_t gfp_flags, int r = 0; unsigned i, j, cpages; unsigned npages = 1 << order; - unsigned max_cpages = min(count, (unsigned)NUM_PAGES_TO_ALLOC); + unsigned max_cpages = min(count << order, (unsigned)NUM_PAGES_TO_ALLOC); /* allocate array for page caching change */ caching_array = kmalloc(max_cpages*sizeof(struct page *), GFP_KERNEL); -- GitLab From b9141cd3930e390f156739829ca9589fda7926e4 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Wed, 22 Nov 2017 19:21:43 +0800 Subject: [PATCH 1320/2547] drm/amdgpu: no need to evict VRAM in device_fini MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this VRAM evict is not needed and also cost 2seconds to finish because the IRQ is software side disabled before it. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b10aecc7d146..98d62a991b67 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2461,8 +2461,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev) adev->shutdown = true; if (adev->mode_info.mode_config_initialized) drm_crtc_force_disable_all(adev->ddev); - /* evict vram memory */ - amdgpu_bo_evict_vram(adev); + amdgpu_ib_pool_fini(adev); amdgpu_fence_driver_fini(adev); amdgpu_fbdev_fini(adev); -- GitLab From d118a62153000e6141872b99aea8498568b0d361 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Mon, 4 Dec 2017 20:46:17 +0800 Subject: [PATCH 1321/2547] drm/amdgpu: no need with INT for fence polling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are polling so no need for INT. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 14699637913a..7cb71a8e21df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -187,7 +187,7 @@ int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s) seq = ++ring->fence_drv.sync_seq; amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, - seq, AMDGPU_FENCE_FLAG_INT); + seq, 0); *s = seq; -- GitLab From f4534f0654fcaad4bfb4678c9370f315ed30e2f2 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Thu, 23 Nov 2017 18:38:59 +0800 Subject: [PATCH 1322/2547] drm/amdgpu: fix MAP_QUEUES paramter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Should be 0. Signed-off-by: Monk Liu Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 58a8ef4f353d..30b41fc082e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2405,7 +2405,7 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) PACKET3_MAP_QUEUES_PIPE(ring->pipe) | PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ - PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */ + PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */ PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); -- GitLab From 1cb4ca59687dc941d5df56aa63ff9c7fa7f7e92f Mon Sep 17 00:00:00 2001 From: Frank Min Date: Mon, 6 Nov 2017 15:34:55 +0800 Subject: [PATCH 1323/2547] drm/amdgpu: correct vce fw data and stack size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this fix the VCE world switch hang issue Signed-off-by: Frank Min Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 0071a5c43e3d..308949d6edde 100755 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -423,7 +423,7 @@ static int vce_v4_0_sw_init(void *handle) if (r) return r; - size = (VCE_V4_0_STACK_SIZE + VCE_V4_0_DATA_SIZE) * 2; + size = VCE_V4_0_STACK_SIZE + VCE_V4_0_DATA_SIZE; if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) size += VCE_V4_0_FW_SIZE; -- GitLab From 74e1d67c73b93634ce2436c10688a7cfea68678e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 8 Dec 2017 11:39:49 -0500 Subject: [PATCH 1324/2547] drm/amdgpu: make function names consistent in nbio files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All functions should have nbio_v* prefix. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 16 ++++++++-------- drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index 9a3546f8b42b..947d6e4a01f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -212,22 +212,22 @@ void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) *flags |= AMD_CG_SUPPORT_BIF_LS; } -static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev) +static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ); } -static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev) +static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE); } -static u32 get_pcie_index_offset(struct amdgpu_device *adev) +static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX); } -static u32 get_pcie_data_offset(struct amdgpu_device *adev) +static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA); } @@ -248,10 +248,10 @@ const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = { }; const struct amdgpu_nbio_funcs nbio_v6_1_funcs = { - .get_hdp_flush_req_offset = get_hdp_flush_req_offset, - .get_hdp_flush_done_offset = get_hdp_flush_done_offset, - .get_pcie_index_offset = get_pcie_index_offset, - .get_pcie_data_offset = get_pcie_data_offset, + .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset, + .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset, + .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset, + .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset, }; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index ce869f37a382..851f58e0b9d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -182,22 +182,22 @@ void nbio_v7_0_ih_control(struct amdgpu_device *adev) WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); } -static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); } -static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); } -static u32 get_pcie_index_offset(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); } -static u32 get_pcie_data_offset(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); } @@ -218,9 +218,9 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = { }; const struct amdgpu_nbio_funcs nbio_v7_0_funcs = { - .get_hdp_flush_req_offset = get_hdp_flush_req_offset, - .get_hdp_flush_done_offset = get_hdp_flush_done_offset, - .get_pcie_index_offset = get_pcie_index_offset, - .get_pcie_data_offset = get_pcie_data_offset, + .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset, + .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset, + .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset, + .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset, }; -- GitLab From a782fc8cc6bf6909daf3b65630079e2afec316ef Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Fri, 1 Dec 2017 18:21:34 +0800 Subject: [PATCH 1325/2547] drm/ttm: fix incorrect calculate on shrink_pages MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit shrink_pages is in unit of Order after ttm_page_pool_free, but it is used by nr_free in next round so need change it into native page unit Signed-off-by: Monk Liu Reviewed-by: Roger He Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 44343a2bf55c..71945ccaf012 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -455,6 +455,7 @@ ttm_pool_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) freed += (nr_free_pool - shrink_pages) << pool->order; if (freed >= sc->nr_to_scan) break; + shrink_pages <<= pool->order; } mutex_unlock(&lock); return freed; -- GitLab From 13d3fc69a03721d972460fe2bff9b479f7999221 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Fri, 1 Dec 2017 18:23:56 +0800 Subject: [PATCH 1326/2547] drm/ttm: max_cpages is in unit of native page MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix calculation. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_page_alloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 71945ccaf012..b5ba6441489f 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -544,7 +544,7 @@ static int ttm_alloc_new_pages(struct list_head *pages, gfp_t gfp_flags, int r = 0; unsigned i, j, cpages; unsigned npages = 1 << order; - unsigned max_cpages = min(count, (unsigned)NUM_PAGES_TO_ALLOC); + unsigned max_cpages = min(count << order, (unsigned)NUM_PAGES_TO_ALLOC); /* allocate array for page caching change */ caching_array = kmalloc(max_cpages*sizeof(struct page *), GFP_KERNEL); -- GitLab From 0507f438ea19d4280006467ba02956f6a693deca Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Thu, 23 Nov 2017 18:38:59 +0800 Subject: [PATCH 1327/2547] drm/amdgpu: fix MAP_QUEUES paramter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Should be 0. Signed-off-by: Monk Liu Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index da43813d67a4..5aeb5f8816f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2467,7 +2467,7 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) PACKET3_MAP_QUEUES_PIPE(ring->pipe) | PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ - PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */ + PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */ PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); -- GitLab From 3ef98f50ca7cef5cc9b9bf89cd46830afbf4df68 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 11 Dec 2017 20:40:40 +0000 Subject: [PATCH 1328/2547] drm/i915: Print an error message for a reset failure on gen2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since on gen2, we do not universally have a GPU reset implementation, we fail i915_reset() at intel_has_gpu_reset(). However, this is also intentionally disabled for CI testing and so it only has a debug message. Promote that debug message to a user-facing error message that should explain why their machine became unusable following the GPU hang. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171211204040.22858-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_drv.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 54a8fca7e7b2..721ccce1832f 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1903,7 +1903,10 @@ void i915_reset(struct drm_i915_private *i915, unsigned int flags) } if (!intel_has_gpu_reset(i915)) { - DRM_DEBUG_DRIVER("GPU reset disabled\n"); + if (i915_modparams.reset) + dev_err(i915->drm.dev, "GPU reset not supported\n"); + else + DRM_DEBUG_DRIVER("GPU reset disabled\n"); goto error; } -- GitLab From 1875fe7ba15020a0d45856d16c17e57ebcbc0bec Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 12 Dec 2017 11:35:32 +0000 Subject: [PATCH 1329/2547] drm/i915: Downgrade misleading "Memory usable" message It never meant what it said, as it was always the total size of the Global GTT and not a limit upon memory usage. Originally it served as a quick guide to the largest batch that could be submitted by userspace, an approximation to its maximum RSS, but was phrased badly. Today with the 48b ppgtt, it is even more meaningless. Replace with a more specific debug message; those wanting to know how much "video ram" they have should consult the userspace libraries for the relevant approximation. v2: Rebase Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Daniel Vetter Cc: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20171212113532.22574-1-chris@chris-wilson.co.uk Reviewed-by: Matthew Auld Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index a7fe05666f72..a0579b0c8581 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3483,10 +3483,9 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) } /* GMADR is the PCI mmio aperture into the global GTT. */ - DRM_INFO("Memory usable by graphics device = %lluM\n", - ggtt->base.total >> 20); + DRM_DEBUG_DRIVER("GGTT size = %lluM\n", ggtt->base.total >> 20); DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20); - DRM_DEBUG_DRIVER("GTT stolen size = %lluM\n", + DRM_DEBUG_DRIVER("DSM size = %lluM\n", (u64)resource_size(&intel_graphics_stolen_res) >> 20); if (intel_vtd_active()) DRM_INFO("VT-d active for gfx access\n"); -- GitLab From ee42c00e1cb0a421fcf6d502d1ab919e6459ae48 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 11 Dec 2017 19:41:34 +0000 Subject: [PATCH 1330/2547] drm/i915: Bump timeout for wait_for_engines() Extract the timeout we use in i915_gem_idle_work_handler() and reuse it for wait_for_engines() in i915_gem_wait_for_idle(). It too has the same problem in sometimes having to wait for an extended period before the HW settles, so make use of the same timeout. References: 5427f207852d ("drm/i915: Bump wait-times for the final CS interrupt before parking") Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171211194135.27095-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 61196ff93901..7762eabd31c1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1586,6 +1586,8 @@ struct drm_i915_error_state_buf { loff_t pos; }; +#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ + #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e89496aec857..55e4475fabe0 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3333,7 +3333,7 @@ i915_gem_idle_work_handler(struct work_struct *work) * Wait for last execlists context complete, but bail out in case a * new request is submitted. */ - end = ktime_add_ms(ktime_get(), 200); + end = ktime_add_ms(ktime_get(), I915_IDLE_ENGINES_TIMEOUT); do { if (new_requests_since_last_retire(dev_priv)) return; @@ -3533,7 +3533,7 @@ static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) static int wait_for_engines(struct drm_i915_private *i915) { - if (wait_for(intel_engines_are_idle(i915), 50)) { + if (wait_for(intel_engines_are_idle(i915), I915_IDLE_ENGINES_TIMEOUT)) { DRM_ERROR("Failed to idle engines, declaring wedged!\n"); i915_gem_set_wedged(i915); return -EIO; -- GitLab From 59e4b19d622ab22d138862ba287859e3aacd5478 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 11 Dec 2017 19:41:35 +0000 Subject: [PATCH 1331/2547] drm/i915: Dump the engine state before declaring wedged from wait_for_engines() If wait_for_engines() fails and we resort to declaring the HW wedged, dump the engine state for debugging. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171211194135.27095-2-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 55e4475fabe0..8c92fcd6f805 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3534,7 +3534,18 @@ static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) static int wait_for_engines(struct drm_i915_private *i915) { if (wait_for(intel_engines_are_idle(i915), I915_IDLE_ENGINES_TIMEOUT)) { - DRM_ERROR("Failed to idle engines, declaring wedged!\n"); + dev_err(i915->drm.dev, + "Failed to idle engines, declaring wedged!\n"); + if (drm_debug & DRM_UT_DRIVER) { + struct drm_printer p = drm_debug_printer(__func__); + struct intel_engine_cs *engine; + enum intel_engine_id id; + + for_each_engine(engine, i915, id) + intel_engine_dump(engine, &p, + "%s", engine->name); + } + i915_gem_set_wedged(i915); return -EIO; } -- GitLab From 9c41e452188339989c2c9ca5fc54f10935207968 Mon Sep 17 00:00:00 2001 From: Benjamin Gaignard Date: Thu, 30 Nov 2017 09:43:57 +0100 Subject: [PATCH 1332/2547] i2c: stm32: Fix copyrights Uniformize STMicroelectronics copyrights headers and add SPDX identifier. Signed-off-by: Benjamin Gaignard Acked-by: Alexandre TORGUE Acked-by: Pierre-Yves MORDRET Acked-by: M'boumba Cedric Madianga Signed-off-by: Wolfram Sang --- drivers/i2c/busses/i2c-stm32.h | 3 ++- drivers/i2c/busses/i2c-stm32f4.c | 3 ++- drivers/i2c/busses/i2c-stm32f7.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-stm32.h b/drivers/i2c/busses/i2c-stm32.h index dab51761f8c5..d4f9cef251ac 100644 --- a/drivers/i2c/busses/i2c-stm32.h +++ b/drivers/i2c/busses/i2c-stm32.h @@ -1,10 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 /* * i2c-stm32.h * * Copyright (C) M'boumba Cedric Madianga 2017 + * Copyright (C) STMicroelectronics 2017 * Author: M'boumba Cedric Madianga * - * License terms: GNU General Public License (GPL), version 2 */ #ifndef _I2C_STM32_H diff --git a/drivers/i2c/busses/i2c-stm32f4.c b/drivers/i2c/busses/i2c-stm32f4.c index 4ec108496f15..47c8d00de53f 100644 --- a/drivers/i2c/busses/i2c-stm32f4.c +++ b/drivers/i2c/busses/i2c-stm32f4.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Driver for STMicroelectronics STM32 I2C controller * @@ -6,11 +7,11 @@ * http://www.st.com/resource/en/reference_manual/DM00031020.pdf * * Copyright (C) M'boumba Cedric Madianga 2016 + * Copyright (C) STMicroelectronics 2017 * Author: M'boumba Cedric Madianga * * This driver is based on i2c-st.c * - * License terms: GNU General Public License (GPL), version 2 */ #include diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c index d4a6e9c2e9aa..b445b3bb0bb1 100644 --- a/drivers/i2c/busses/i2c-stm32f7.c +++ b/drivers/i2c/busses/i2c-stm32f7.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Driver for STMicroelectronics STM32F7 I2C controller * @@ -7,11 +8,11 @@ * http://www.st.com/resource/en/reference_manual/dm00124865.pdf * * Copyright (C) M'boumba Cedric Madianga 2017 + * Copyright (C) STMicroelectronics 2017 * Author: M'boumba Cedric Madianga * * This driver is based on i2c-stm32f4.c * - * License terms: GNU General Public License (GPL), version 2 */ #include #include -- GitLab From 45fd4470ba86e9ca2837b666a52cc65dc69f0fa3 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Thu, 7 Dec 2017 12:25:45 +0100 Subject: [PATCH 1333/2547] i2c: piix4: Fix port number check on release The port number shift is still hard-coded to 1 while it now depends on the hardware. Thankfully 0 is always 0 no matter how you shift it, so this was a bug without consequences. Signed-off-by: Jean Delvare Fixes: 0fe16195f891 ("i2c: piix4: Fix SMBus port selection for AMD Family 17h chips") Reviewed-by: Guenter Roeck Signed-off-by: Wolfram Sang --- drivers/i2c/busses/i2c-piix4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 174579d32e5f..462948e2c535 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -983,7 +983,7 @@ static void piix4_adap_remove(struct i2c_adapter *adap) if (adapdata->smba) { i2c_del_adapter(adap); - if (adapdata->port == (0 << 1)) { + if (adapdata->port == (0 << piix4_port_shift_sb800)) { release_region(adapdata->smba, SMBIOSIZE); if (adapdata->sb800_main) release_region(SB800_PIIX4_SMB_IDX, 2); -- GitLab From 9147efcbe0b7cc96b18eb64b1a3f0d4bba81443c Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 12 Dec 2017 14:22:39 -0800 Subject: [PATCH 1334/2547] bpf: add schedule points to map alloc/free While using large percpu maps, htab_map_alloc() can hold cpu for hundreds of ms. This patch adds cond_resched() calls to percpu alloc/free call sites, all running in process context. Signed-off-by: Eric Dumazet Signed-off-by: Alexei Starovoitov --- kernel/bpf/hashtab.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/bpf/hashtab.c b/kernel/bpf/hashtab.c index e469e05c8e83..3905d4bc5b80 100644 --- a/kernel/bpf/hashtab.c +++ b/kernel/bpf/hashtab.c @@ -114,6 +114,7 @@ static void htab_free_elems(struct bpf_htab *htab) pptr = htab_elem_get_ptr(get_htab_elem(htab, i), htab->map.key_size); free_percpu(pptr); + cond_resched(); } free_elems: bpf_map_area_free(htab->elems); @@ -159,6 +160,7 @@ static int prealloc_init(struct bpf_htab *htab) goto free_elems; htab_elem_set_ptr(get_htab_elem(htab, i), htab->map.key_size, pptr); + cond_resched(); } skip_percpu_elems: -- GitLab From 964728f9f407eca0b417fdf8e784b7a76979490c Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 13 Nov 2017 11:12:58 +0100 Subject: [PATCH 1335/2547] USB: chipidea: msm: fix ulpi-node lookup Fix child-node lookup during probe, which ended up searching the whole device tree depth-first starting at the parent rather than just matching on its children. Note that the original premature free of the parent node has already been fixed separately, but that fix was apparently never backported to stable. Fixes: 47654a162081 ("usb: chipidea: msm: Restore wrapper settings after reset") Fixes: b74c43156c0c ("usb: chipidea: msm: ci_hdrc_msm_probe() missing of_node_get()") Cc: stable # 4.10: b74c43156c0c Cc: Stephen Boyd Cc: Frank Rowand Signed-off-by: Johan Hovold Signed-off-by: Peter Chen --- drivers/usb/chipidea/ci_hdrc_msm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/chipidea/ci_hdrc_msm.c b/drivers/usb/chipidea/ci_hdrc_msm.c index 3593ce0ec641..880009987460 100644 --- a/drivers/usb/chipidea/ci_hdrc_msm.c +++ b/drivers/usb/chipidea/ci_hdrc_msm.c @@ -247,7 +247,7 @@ static int ci_hdrc_msm_probe(struct platform_device *pdev) if (ret) goto err_mux; - ulpi_node = of_find_node_by_name(of_node_get(pdev->dev.of_node), "ulpi"); + ulpi_node = of_get_child_by_name(pdev->dev.of_node, "ulpi"); if (ulpi_node) { phy_node = of_get_next_available_child(ulpi_node, NULL); ci->hsic = of_device_is_compatible(phy_node, "qcom,usb-hsic-phy"); -- GitLab From f41d84dddc66b164ac16acf3f584c276146f1c48 Mon Sep 17 00:00:00 2001 From: Ravi Bangoria Date: Tue, 12 Dec 2017 17:59:15 +0530 Subject: [PATCH 1336/2547] powerpc/perf: Dereference BHRB entries safely It's theoretically possible that branch instructions recorded in BHRB (Branch History Rolling Buffer) entries have already been unmapped before they are processed by the kernel. Hence, trying to dereference such memory location will result in a crash. eg: Unable to handle kernel paging request for data at address 0xd000000019c41764 Faulting instruction address: 0xc000000000084a14 NIP [c000000000084a14] branch_target+0x4/0x70 LR [c0000000000eb828] record_and_restart+0x568/0x5c0 Call Trace: [c0000000000eb3b4] record_and_restart+0xf4/0x5c0 (unreliable) [c0000000000ec378] perf_event_interrupt+0x298/0x460 [c000000000027964] performance_monitor_exception+0x54/0x70 [c000000000009ba4] performance_monitor_common+0x114/0x120 Fix it by deferefencing the addresses safely. Fixes: 691231846ceb ("powerpc/perf: Fix setting of "to" addresses for BHRB") Cc: stable@vger.kernel.org # v3.10+ Suggested-by: Naveen N. Rao Signed-off-by: Ravi Bangoria Reviewed-by: Naveen N. Rao [mpe: Use probe_kernel_read() which is clearer, tweak change log] Signed-off-by: Michael Ellerman --- arch/powerpc/perf/core-book3s.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 153812966365..fce545774d50 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -410,8 +410,12 @@ static __u64 power_pmu_bhrb_to(u64 addr) int ret; __u64 target; - if (is_kernel_addr(addr)) - return branch_target((unsigned int *)addr); + if (is_kernel_addr(addr)) { + if (probe_kernel_read(&instr, (void *)addr, sizeof(instr))) + return 0; + + return branch_target(&instr); + } /* Userspace: need copy instruction here then translate it */ pagefault_disable(); -- GitLab From ad2b6e01024ef23bddc3ce0bcb115ecd8c520b7e Mon Sep 17 00:00:00 2001 From: Anju T Sudhakar Date: Tue, 5 Dec 2017 11:00:38 +0530 Subject: [PATCH 1337/2547] powerpc/perf/imc: Fix nest-imc cpuhotplug callback failure Oops is observed during boot: Faulting instruction address: 0xc000000000248340 cpu 0x0: Vector: 380 (Data Access Out of Range) at [c000000ff66fb850] pc: c000000000248340: event_function_call+0x50/0x1f0 lr: c00000000024878c: perf_remove_from_context+0x3c/0x100 sp: c000000ff66fbad0 msr: 9000000000009033 dar: 7d20e2a6f92d03c0 pid = 14, comm = cpuhp/0 While registering the cpuhotplug callbacks for nest-imc, if we fail in the cpuhotplug online path for any random node in a multi node system (because the opal call to stop nest-imc counters fails for that node), ppc_nest_imc_cpu_offline() will get invoked for other nodes who successfully returned from cpuhotplug online path. This call trace is generated since in the ppc_nest_imc_cpu_offline() path we are trying to migrate the event context, when nest-imc counters are not even initialized. Patch to add a check to ensure that nest-imc is registered before migrating the event context. Fixes: 885dcd709ba9 ("powerpc/perf: Add nest IMC PMU support") Signed-off-by: Anju T Sudhakar Reviewed-by: Madhavan Srinivasan Signed-off-by: Michael Ellerman --- arch/powerpc/perf/imc-pmu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c index 0ead3cd73caa..f1b940714d65 100644 --- a/arch/powerpc/perf/imc-pmu.c +++ b/arch/powerpc/perf/imc-pmu.c @@ -309,6 +309,19 @@ static int ppc_nest_imc_cpu_offline(unsigned int cpu) if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask)) return 0; + /* + * Check whether nest_imc is registered. We could end up here if the + * cpuhotplug callback registration fails. i.e, callback invokes the + * offline path for all successfully registered nodes. At this stage, + * nest_imc pmu will not be registered and we should return here. + * + * We return with a zero since this is not an offline failure. And + * cpuhp_setup_state() returns the actual failure reason to the caller, + * which in turn will call the cleanup routine. + */ + if (!nest_pmus) + return 0; + /* * Now that this cpu is one of the designated, * find a next cpu a) which is online and b) in same chip. -- GitLab From 110df8bd3e418b3476cae80babe8add48a8ea523 Mon Sep 17 00:00:00 2001 From: Anju T Sudhakar Date: Thu, 7 Dec 2017 22:53:27 +0530 Subject: [PATCH 1338/2547] powerpc/perf: Fix kfree memory allocated for nest pmus imc_common_cpuhp_mem_free() is the common function for all IMC (In-memory Collection counters) domains to unregister cpuhotplug callback and free memory. Since kfree of memory allocated for nest-imc (per_nest_pmu_arr) is in the common code, all domains (core/nest/thread) can do the kfree in the failure case. This could potentially create a call trace as shown below, where core(/thread/nest) imc pmu initialization fails and in the failure path imc_common_cpuhp_mem_free() free the memory(per_nest_pmu_arr), which is allocated by successfully registered nest units. The call trace is generated in a scenario where core-imc initialization is made to fail and a cpuhotplug is performed in a p9 system. During cpuhotplug ppc_nest_imc_cpu_offline() tries to access per_nest_pmu_arr, which is already freed by core-imc. NIP [c000000000cb6a94] mutex_lock+0x34/0x90 LR [c000000000cb6a88] mutex_lock+0x28/0x90 Call Trace: mutex_lock+0x28/0x90 (unreliable) perf_pmu_migrate_context+0x90/0x3a0 ppc_nest_imc_cpu_offline+0x190/0x1f0 cpuhp_invoke_callback+0x160/0x820 cpuhp_thread_fun+0x1bc/0x270 smpboot_thread_fn+0x250/0x290 kthread+0x1a8/0x1b0 ret_from_kernel_thread+0x5c/0x74 To address this scenario do the kfree(per_nest_pmu_arr) only in case of nest-imc initialization failure, and when there is no other nest units registered. Fixes: 73ce9aec65b1 ("powerpc/perf: Fix IMC_MAX_PMU macro") Signed-off-by: Anju T Sudhakar Reviewed-by: Madhavan Srinivasan Signed-off-by: Michael Ellerman --- arch/powerpc/perf/imc-pmu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c index f1b940714d65..be4e7f84f70a 100644 --- a/arch/powerpc/perf/imc-pmu.c +++ b/arch/powerpc/perf/imc-pmu.c @@ -1184,6 +1184,7 @@ static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr) if (nest_pmus == 1) { cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE); kfree(nest_imc_refc); + kfree(per_nest_pmu_arr); } if (nest_pmus > 0) @@ -1208,7 +1209,6 @@ static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr) kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs); kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]); kfree(pmu_ptr); - kfree(per_nest_pmu_arr); return; } @@ -1322,6 +1322,8 @@ int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_id ret = nest_pmu_cpumask_init(); if (ret) { mutex_unlock(&nest_init_lock); + kfree(nest_imc_refc); + kfree(per_nest_pmu_arr); goto err_free; } } -- GitLab From a5f1005517534aeb1fac20180badfbf0896c183c Mon Sep 17 00:00:00 2001 From: Sebastian Ott Date: Fri, 1 Dec 2017 18:47:32 +0100 Subject: [PATCH 1339/2547] s390/pci: handle insufficient resources during dma tlb flush In a virtualized setup lazy flushing can lead to the hypervisor running out of resources when lots of guest pages need to be pinned. In this situation simply trigger a global flush to give the hypervisor a chance to free some of these resources. Signed-off-by: Sebastian Ott Reviewed-by: Gerald Schaefer Reviewed-by: Pierre Morel Signed-off-by: Martin Schwidefsky --- arch/s390/pci/pci_dma.c | 21 +++++++++++++++++++-- arch/s390/pci/pci_insn.c | 3 +++ 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/s390/pci/pci_dma.c b/arch/s390/pci/pci_dma.c index f7aa5a77827e..2d15d84c20ed 100644 --- a/arch/s390/pci/pci_dma.c +++ b/arch/s390/pci/pci_dma.c @@ -181,6 +181,9 @@ static int __dma_update_trans(struct zpci_dev *zdev, unsigned long pa, static int __dma_purge_tlb(struct zpci_dev *zdev, dma_addr_t dma_addr, size_t size, int flags) { + unsigned long irqflags; + int ret; + /* * With zdev->tlb_refresh == 0, rpcit is not required to establish new * translations when previously invalid translation-table entries are @@ -196,8 +199,22 @@ static int __dma_purge_tlb(struct zpci_dev *zdev, dma_addr_t dma_addr, return 0; } - return zpci_refresh_trans((u64) zdev->fh << 32, dma_addr, - PAGE_ALIGN(size)); + ret = zpci_refresh_trans((u64) zdev->fh << 32, dma_addr, + PAGE_ALIGN(size)); + if (ret == -ENOMEM && !s390_iommu_strict) { + /* enable the hypervisor to free some resources */ + if (zpci_refresh_global(zdev)) + goto out; + + spin_lock_irqsave(&zdev->iommu_bitmap_lock, irqflags); + bitmap_andnot(zdev->iommu_bitmap, zdev->iommu_bitmap, + zdev->lazy_bitmap, zdev->iommu_pages); + bitmap_zero(zdev->lazy_bitmap, zdev->iommu_pages); + spin_unlock_irqrestore(&zdev->iommu_bitmap_lock, irqflags); + ret = 0; + } +out: + return ret; } static int dma_update_trans(struct zpci_dev *zdev, unsigned long pa, diff --git a/arch/s390/pci/pci_insn.c b/arch/s390/pci/pci_insn.c index 19bcb3b45a70..f069929e8211 100644 --- a/arch/s390/pci/pci_insn.c +++ b/arch/s390/pci/pci_insn.c @@ -89,6 +89,9 @@ int zpci_refresh_trans(u64 fn, u64 addr, u64 range) if (cc) zpci_err_insn(cc, status, addr, range); + if (cc == 1 && (status == 4 || status == 16)) + return -ENOMEM; + return (cc) ? -EIO : 0; } -- GitLab From faa75e147b583417273902552c61cf3250a44308 Mon Sep 17 00:00:00 2001 From: Dongjiu Geng Date: Wed, 13 Dec 2017 18:36:47 +0800 Subject: [PATCH 1340/2547] arm64: fault: avoid send SIGBUS two times do_sea() calls arm64_notify_die() which will always signal user-space. It also returns whether APEI claimed the external abort as a RAS notification. If it returns failure do_mem_abort() will signal user-space too. do_mem_abort() wants to know if we handled the error, we always call arm64_notify_die() so can always return success. Signed-off-by: Dongjiu Geng Reviewed-by: James Morse Reviewed-by: Xie XiuQi Signed-off-by: Will Deacon --- arch/arm64/mm/fault.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 22168cd0dde7..9b7f89df49db 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -574,7 +574,6 @@ static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) { struct siginfo info; const struct fault_info *inf; - int ret = 0; inf = esr_to_fault_info(esr); pr_err("Synchronous External Abort: %s (0x%08x) at 0x%016lx\n", @@ -589,7 +588,7 @@ static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) if (interrupts_enabled(regs)) nmi_enter(); - ret = ghes_notify_sea(); + ghes_notify_sea(); if (interrupts_enabled(regs)) nmi_exit(); @@ -604,7 +603,7 @@ static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) info.si_addr = (void __user *)addr; arm64_notify_die("", regs, &info, esr); - return ret; + return 0; } static const struct fault_info fault_info[] = { -- GitLab From 92ccc262e485781ff4c0fb3b7c77a619282df49a Mon Sep 17 00:00:00 2001 From: Mengting Zhang Date: Tue, 12 Dec 2017 18:16:57 +0000 Subject: [PATCH 1341/2547] tools/lib/lockdep: Add missing declaration of 'pr_cont()' Commit: 681fbec881de ("lockdep: Use consistent printing primitives") has moved lockdep away from using printk() for printing. The commit added usage of pr_cont() which wasn't wrapped in the userspace headers, causing the following warning for the liblockdep build: ../../../kernel/locking/lockdep.c:3544:2: warning: implicit declaration of function 'pr_cont' [-Wimplicit-function-declaration] Adding an empty declaration of 'pr_cont' fixes the problem. Signed-off-by: Mengting Zhang Signed-off-by: Sasha Levin Reviewed-by: Alexander Sverdlin Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: a.p.zijlstra@chello.nl Link: http://lkml.kernel.org/r/20171212181644.11913-2-alexander.levin@verizon.com Signed-off-by: Ingo Molnar --- tools/include/linux/lockdep.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/include/linux/lockdep.h b/tools/include/linux/lockdep.h index 940c1b075659..6b0c36a58fcb 100644 --- a/tools/include/linux/lockdep.h +++ b/tools/include/linux/lockdep.h @@ -48,6 +48,7 @@ static inline int debug_locks_off(void) #define printk(...) dprintf(STDOUT_FILENO, __VA_ARGS__) #define pr_err(format, ...) fprintf (stderr, format, ## __VA_ARGS__) #define pr_warn pr_err +#define pr_cont pr_err #define list_del_rcu list_del -- GitLab From cf4df407e0d7cde60a45369c2a3414d18e2d4fdd Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 13 Dec 2017 11:59:39 +0100 Subject: [PATCH 1342/2547] Revert "USB: core: only clean up what we allocated" This reverts commit 32fd87b3bbf5f7a045546401dfe2894dbbf4d8c3. Alan wrote a better fix for this... Cc: Andrey Konovalov Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/config.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/usb/core/config.c b/drivers/usb/core/config.c index 93b38471754e..55b198ba629b 100644 --- a/drivers/usb/core/config.c +++ b/drivers/usb/core/config.c @@ -764,21 +764,18 @@ void usb_destroy_configuration(struct usb_device *dev) return; if (dev->rawdescriptors) { - for (i = 0; i < dev->descriptor.bNumConfigurations && - i < USB_MAXCONFIG; i++) + for (i = 0; i < dev->descriptor.bNumConfigurations; i++) kfree(dev->rawdescriptors[i]); kfree(dev->rawdescriptors); dev->rawdescriptors = NULL; } - for (c = 0; c < dev->descriptor.bNumConfigurations && - c < USB_MAXCONFIG; c++) { + for (c = 0; c < dev->descriptor.bNumConfigurations; c++) { struct usb_host_config *cf = &dev->config[c]; kfree(cf->string); - for (i = 0; i < cf->desc.bNumInterfaces && - i < USB_MAXINTERFACES; i++) { + for (i = 0; i < cf->desc.bNumInterfaces; i++) { if (cf->intf_cache[i]) kref_put(&cf->intf_cache[i]->ref, usb_release_interface_cache); -- GitLab From 7d622351c94172a42bfe9b13bdb0fdc2be90ed3b Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 13 Dec 2017 09:48:02 +0000 Subject: [PATCH 1343/2547] drm/i915/fence: Use rcu to defer freeing of irq_work It is illegal to perform an immediate free of the struct irq_work from inside the irq_work callback (as irq_work_run_list modifies work->flags after execution of the work->func()). As we use the irq_work to coordinate the freeing of the callback from two different softirq paths, we need to defer the kfree from inside our irq_work callback, for which we can use kfree_rcu. Fixes: 81c0ed21aa91 ("drm/i915/fence: Avoid del_timer_sync() from inside a timer") Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Joonas Lahtinen Reviewed-by: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20171213094802.28243-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_sw_fence.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c index e8ca67a129d2..ac236b88c99c 100644 --- a/drivers/gpu/drm/i915/i915_sw_fence.c +++ b/drivers/gpu/drm/i915/i915_sw_fence.c @@ -367,6 +367,7 @@ struct i915_sw_dma_fence_cb { struct dma_fence *dma; struct timer_list timer; struct irq_work work; + struct rcu_head rcu; }; static void timer_i915_sw_fence_wake(struct timer_list *t) @@ -406,7 +407,7 @@ static void irq_i915_sw_fence_work(struct irq_work *wrk) del_timer_sync(&cb->timer); dma_fence_put(cb->dma); - kfree(cb); + kfree_rcu(cb, rcu); } int i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence, -- GitLab From d7dc4131eb2a1efd670692b7fb578980d8f41762 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 12 Dec 2017 13:21:48 +0000 Subject: [PATCH 1344/2547] drm/i915: Don't check #active_requests from i915_gem_wait_for_idle() i915_gem_wait_for_idle() is called from inside the shrinker, to ensure that we drain the last resources from the GPU in dire circumstances (OOM). As we may allocate whilst building a request, it is then possible to hit the shrinker with a request under construction, and so we must account for the incomplete request whilst waiting. In particular, we preincrement (in reserve_engine) the i915->gt.active_requests counter and mark the GPU as busy, therefore we can not use that counter for shortcircuiting the wait-for-idle. [ 950.859024] GEM_BUG_ON(i915->gt.active_requests) [ 950.859041] WARNING: CPU: 2 PID: 2178 at drivers/gpu/drm/i915/i915_gem.c:3615 i915_gem_wait_for_idle.part.56+0x166/0x4e0 [ 950.859041] Modules linked in: ccm tun fuse nf_conntrack_netbios_ns nf_conntrack_broadcast ip6t_rpfilter ip6t_REJECT nf_reject_ipv6 nf_conntrack_ipv6 nf_defrag_ipv6 nf_conntrack_ipv4 nf_defrag_ipv4 xt_conntrack nf_conntrack libcrc32c ebtable_nat ebtable_broute bridge stp llc ebtable_filter ebtables ip6table_mangle ip6table_security ip6table_raw ip6table_filter ip6_tables iptable_mangle iptable_security iptable_raw arc4 iwldvm mac80211 snd_hda_codec_hdmi snd_hda_codec_idt snd_hda_codec_generic snd_hda_intel snd_hda_codec btusb snd_hda_core btrtl btbcm iwlwifi snd_hwdep btintel bluetooth snd_seq snd_seq_device snd_pcm ecdh_generic x86_pkg_temp_thermal tpm_infineon coretemp tpm_tis crc32_pclmul wmi_bmof crc32c_intel iTCO_wdt hp_wmi snd_timer iTCO_vendor_support sparse_keymap tpm_tis_core mei_me cfg80211 [ 950.859082] snd joydev tpm mei rfkill pcspkr wmi soundcore lpc_ich hp_accel lis3lv02d input_polldev binfmt_misc e1000e ptp serio_raw pps_core [ 950.859094] CPU: 2 PID: 2178 Comm: gem_exec_nop Tainted: G U 4.15.0-rc2+ #900 [ 950.859102] Hardware name: Hewlett-Packard HP ProBook 6360b/1620, BIOS 68SCF Ver. B.42 12/29/2010 [ 950.859107] task: c5119cb4 task.stack: f3ccb8d8 [ 950.859112] EIP: i915_gem_wait_for_idle.part.56+0x166/0x4e0 [ 950.859113] EFLAGS: 00010296 CPU: 2 [ 950.859114] EAX: 00000024 EBX: f36c1888 ECX: f777a044 EDX: 00000007 [ 950.859115] ESI: f36c1888 EDI: edd53958 EBP: edd53970 ESP: edd53938 [ 950.859116] DS: 007b ES: 007b FS: 00d8 GS: 0033 SS: 0068 [ 950.859117] CR0: 80050033 CR2: b7f39000 CR3: 2f2b3000 CR4: 000406d0 [ 950.859118] Call Trace: [ 950.859125] ? drm_printk+0x70/0x70 [ 950.859129] i915_gem_wait_for_idle+0x18/0x30 [ 950.859133] i915_gem_shrink+0x360/0x410 [ 950.859138] ? vmpressure+0xa8/0xf0 [ 950.859142] ? ktime_get+0x4a/0x100 [ 950.859147] i915_gem_shrink_all+0x21/0x40 [ 950.859151] i915_gem_shrinker_oom+0x23/0x130 [ 950.859156] notifier_call_chain+0x4e/0x70 [ 950.859160] __blocking_notifier_call_chain+0x2f/0x60 [ 950.859164] blocking_notifier_call_chain+0x11/0x20 [ 950.859169] out_of_memory+0x207/0x280 [ 950.859174] __alloc_pages_nodemask+0xd47/0xe60 [ 950.859179] new_slab+0x32d/0x450 [ 950.859183] ___slab_alloc.constprop.81+0x358/0x4e0 [ 950.859189] ? i915_sw_fence_await_dma_fence+0x53/0x160 [ 950.859193] ? __slab_free+0x1fe/0x310 [ 950.859197] ? native_sched_clock+0x1e/0xc0 [ 950.859201] ? i915_gem_request_alloc+0xcf/0x510 [ 950.859205] ? sched_clock+0x9/0x10 [ 950.859209] __slab_alloc.constprop.80+0x29/0x40 [ 950.859212] ? __slab_alloc.constprop.80+0x29/0x40 [ 950.859216] kmem_cache_alloc_trace+0x160/0x1a0 [ 950.859220] ? i915_sw_fence_await_dma_fence+0x53/0x160 [ 950.859224] i915_sw_fence_await_dma_fence+0x53/0x160 [ 950.859229] i915_gem_request_await_dma_fence+0x1eb/0x390 [ 950.859233] i915_gem_request_await_object+0xee/0x230 [ 950.859239] i915_gem_do_execbuffer+0xc16/0x1200 [ 950.859246] ? irqtime_account_irq+0x3e/0xc0 [ 950.859251] ? irq_exit+0x4f/0xb0 [ 950.859257] ? smp_apic_timer_interrupt+0x5f/0x110 [ 950.859261] ? apic_timer_interrupt+0x35/0x3c [ 950.859266] i915_gem_execbuffer2_ioctl+0x212/0x440 [ 950.859270] ? apic_timer_interrupt+0x35/0x3c [ 950.859274] ? i915_gem_do_execbuffer+0x1200/0x1200 [ 950.859279] ? insn_get_seg_base+0x1b/0x50 [ 950.859283] ? i915_gem_do_execbuffer+0x1200/0x1200 [ 950.859287] drm_ioctl_kernel+0x51/0xa0 [ 950.859291] drm_ioctl+0x2a3/0x350 [ 950.859294] ? i915_gem_do_execbuffer+0x1200/0x1200 [ 950.859300] ? sched_clock+0x9/0x10 [ 950.859303] ? drm_getunique+0x70/0x70 [ 950.859308] do_vfs_ioctl+0x7d/0x640 [ 950.859311] ? native_sched_clock+0x1e/0xc0 [ 950.859315] ? sched_clock+0x9/0x10 [ 950.859319] ? sched_clock_cpu+0x13/0x120 [ 950.859323] SyS_ioctl+0x4e/0x80 [ 950.859326] do_fast_syscall_32+0x75/0x250 [ 950.859331] ? irq_exit+0x4f/0xb0 [ 950.859334] entry_SYSENTER_32+0x47/0x71 [ 950.859338] EIP: 0xb7f81d11 [ 950.859339] EFLAGS: 00000296 CPU: 2 [ 950.859340] EAX: ffffffda EBX: 00000003 ECX: 40406469 EDX: bfde4c20 [ 950.859340] ESI: 00000003 EDI: 40406469 EBP: 00000003 ESP: bfde4b38 [ 950.859341] DS: 007b ES: 007b FS: 0000 GS: 0033 SS: 007b [ 950.859343] Code: e8 30 60 01 00 83 c4 10 83 c3 04 39 f3 75 e0 8b 45 d8 8b 80 14 37 00 00 85 c0 74 13 68 dd 33 e4 c0 68 49 6f e3 c0 e8 4a 55 be ff <0f> ff 5e 5f b8 fe ff ff 3f bb 0a 00 00 00 e8 b7 14 c4 ff 8b 15 Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171212132148.8124-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 2 -- drivers/gpu/drm/i915/intel_engine_cs.c | 6 ++---- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 8c92fcd6f805..8c3d801696b7 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3571,9 +3571,7 @@ int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags) if (ret) return ret; } - i915_gem_retire_requests(i915); - GEM_BUG_ON(i915->gt.active_requests); ret = wait_for_engines(i915); } else { diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index aad353195f17..510e0bc3a377 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1513,10 +1513,8 @@ bool intel_engines_are_idle(struct drm_i915_private *dev_priv) struct intel_engine_cs *engine; enum intel_engine_id id; - if (READ_ONCE(dev_priv->gt.active_requests)) - return false; - - /* If the driver is wedged, HW state may be very inconsistent and + /* + * If the driver is wedged, HW state may be very inconsistent and * report that it is still busy, even though we have stopped using it. */ if (i915_terminally_wedged(&dev_priv->gpu_error)) -- GitLab From 48a4ff1c7bb5a32d2e396b03132d20d552c0eca7 Mon Sep 17 00:00:00 2001 From: Alan Stern Date: Tue, 12 Dec 2017 14:25:13 -0500 Subject: [PATCH 1345/2547] USB: core: prevent malicious bNumInterfaces overflow A malicious USB device with crafted descriptors can cause the kernel to access unallocated memory by setting the bNumInterfaces value too high in a configuration descriptor. Although the value is adjusted during parsing, this adjustment is skipped in one of the error return paths. This patch prevents the problem by setting bNumInterfaces to 0 initially. The existing code already sets it to the proper value after parsing is complete. Signed-off-by: Alan Stern Reported-by: Andrey Konovalov CC: Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/config.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/usb/core/config.c b/drivers/usb/core/config.c index 55b198ba629b..78e92d29f8d9 100644 --- a/drivers/usb/core/config.c +++ b/drivers/usb/core/config.c @@ -555,6 +555,9 @@ static int usb_parse_configuration(struct usb_device *dev, int cfgidx, unsigned iad_num = 0; memcpy(&config->desc, buffer, USB_DT_CONFIG_SIZE); + nintf = nintf_orig = config->desc.bNumInterfaces; + config->desc.bNumInterfaces = 0; // Adjusted later + if (config->desc.bDescriptorType != USB_DT_CONFIG || config->desc.bLength < USB_DT_CONFIG_SIZE || config->desc.bLength > size) { @@ -568,7 +571,6 @@ static int usb_parse_configuration(struct usb_device *dev, int cfgidx, buffer += config->desc.bLength; size -= config->desc.bLength; - nintf = nintf_orig = config->desc.bNumInterfaces; if (nintf > USB_MAXINTERFACES) { dev_warn(ddev, "config %d has too many interfaces: %d, " "using maximum allowed: %d\n", -- GitLab From 5843f4e02fbe86a59981e35adc6cabebee46fdc0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 1 Nov 2017 15:20:04 +0100 Subject: [PATCH 1346/2547] drm/fourcc: Fix fourcc_mod_code() definition Avoid a compiler warnings when the val parameter is an expression. Reviewed-by: Daniel Vetter Signed-off-by: Thierry Reding --- include/uapi/drm/drm_fourcc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3ad838d3f93f..a76ed8f9e383 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -188,7 +188,7 @@ extern "C" { #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) #define fourcc_mod_code(vendor, val) \ - ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL)) + ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) /* * Format Modifier tokens: -- GitLab From 268892cb63a822315921a8dab48ac3e4abf7dd03 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 12 Oct 2017 16:39:20 +0200 Subject: [PATCH 1347/2547] drm/tegra: Sanitize format modifiers The existing format modifier definitions were merged prematurely, and recent work has unveiled that the definitions are suboptimal in several ways: - The format specifiers, except for one, are not Tegra specific, but the names don't reflect that. - The number space is split into two, reserving 32 bits for some "parameter" which most of the modifiers are not going to have. - Symbolic names for the modifiers are not using the standard DRM_FORMAT_MOD_* prefix, which makes them awkward to use. - The vendor prefix NV is somewhat ambiguous. Fortunately, nobody's started using these modifiers, so we can still fix the above issues. Do so by using the standard prefix. Also, remove TEGRA from the name of those modifiers that exist on NVIDIA GPUs as well. In case of the block linear modifiers, make the "parameter" smaller (4 bits, though only 6 values are valid) and don't let that leak into any of the other modifiers. Finally, also use the more canonical NVIDIA instead of the ambiguous NV prefix. Acked-by: Daniel Vetter Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/fb.c | 35 ++++++++++++++++++++++++++++------ include/uapi/drm/drm_fourcc.h | 36 ++++++++++++++++++----------------- 2 files changed, 48 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 80540c1c66dc..406e895d82cc 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -54,17 +54,40 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, struct tegra_fb *fb = to_tegra_fb(framebuffer); uint64_t modifier = fb->base.modifier; - switch (fourcc_mod_tegra_mod(modifier)) { - case NV_FORMAT_MOD_TEGRA_TILED: + switch (modifier) { + case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED: tiling->mode = TEGRA_BO_TILING_MODE_TILED; tiling->value = 0; break; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0): + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0): tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; - tiling->value = fourcc_mod_tegra_param(modifier); - if (tiling->value > 5) - return -EINVAL; + tiling->value = 0; + break; + + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1): + tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; + tiling->value = 1; + break; + + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2): + tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; + tiling->value = 2; + break; + + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3): + tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; + tiling->value = 3; + break; + + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4): + tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; + tiling->value = 4; + break; + + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5): + tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; + tiling->value = 5; break; default: diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index a76ed8f9e383..e04613d30a13 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -178,7 +178,7 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_NONE 0 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 -#define DRM_FORMAT_MOD_VENDOR_NV 0x03 +#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 @@ -338,29 +338,17 @@ extern "C" { */ #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) -/* NVIDIA Tegra frame buffer modifiers */ - -/* - * Some modifiers take parameters, for example the number of vertical GOBs in - * a block. Reserve the lower 32 bits for parameters - */ -#define __fourcc_mod_tegra_mode_shift 32 -#define fourcc_mod_tegra_code(val, params) \ - fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params)) -#define fourcc_mod_tegra_mod(m) \ - (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) -#define fourcc_mod_tegra_param(m) \ - (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) +/* NVIDIA frame buffer modifiers */ /* * Tegra Tiled Layout, used by Tegra 2, 3 and 4. * * Pixels are arranged in simple tiles of 16 x 16 bytes. */ -#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0) +#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) /* - * Tegra 16Bx2 Block Linear layout, used by TK1/TX1 + * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later * * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked * vertically by a power of 2 (1 to 32 GOBs) to form a block. @@ -380,7 +368,21 @@ extern "C" { * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format * in full detail. */ -#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ + fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) + +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ + fourcc_mod_code(NVIDIA, 0x10) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ + fourcc_mod_code(NVIDIA, 0x11) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ + fourcc_mod_code(NVIDIA, 0x12) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ + fourcc_mod_code(NVIDIA, 0x13) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ + fourcc_mod_code(NVIDIA, 0x14) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ + fourcc_mod_code(NVIDIA, 0x15) /* * Broadcom VC4 "T" format -- GitLab From 1f876c3fceadecbb8753e9a351ae3591d0de610e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 31 Jul 2017 11:18:44 +0200 Subject: [PATCH 1348/2547] gpu: host1x: Rewrite conditional for better readability The current check is slightly difficult to read, rewrite it to improve that a little. Signed-off-by: Thierry Reding --- drivers/gpu/host1x/dev.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index bf67c3aeb634..1f916b579e95 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x/dev.c @@ -227,11 +227,13 @@ static int host1x_probe(struct platform_device *pdev) return -ENOMEM; err = iommu_attach_device(host->domain, &pdev->dev); - if (err == -ENODEV) { - iommu_domain_free(host->domain); - host->domain = NULL; - goto skip_iommu; - } else if (err) { + if (err) { + if (err == -ENODEV) { + iommu_domain_free(host->domain); + host->domain = NULL; + goto skip_iommu; + } + goto fail_free_domain; } -- GitLab From 8f7da1578e90bf1af30269dc6dd8806c96e9c683 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 8 Nov 2017 13:08:21 +0100 Subject: [PATCH 1349/2547] gpu: host1x: Cleanup on initialization failure When an error happens during the initialization of one of the sub- devices, make sure to properly cleanup all sub-devices that have been initialized up to that point. Signed-off-by: Thierry Reding --- drivers/gpu/host1x/bus.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/host1x/bus.c b/drivers/gpu/host1x/bus.c index 2e57c9cea696..88a3558b7916 100644 --- a/drivers/gpu/host1x/bus.c +++ b/drivers/gpu/host1x/bus.c @@ -211,8 +211,7 @@ int host1x_device_init(struct host1x_device *device) dev_err(&device->dev, "failed to initialize %s: %d\n", dev_name(client->dev), err); - mutex_unlock(&device->clients_lock); - return err; + goto teardown; } } } @@ -220,6 +219,14 @@ int host1x_device_init(struct host1x_device *device) mutex_unlock(&device->clients_lock); return 0; + +teardown: + list_for_each_entry_continue_reverse(client, &device->clients, list) + if (client->ops->exit) + client->ops->exit(client); + + mutex_unlock(&device->clients_lock); + return err; } EXPORT_SYMBOL(host1x_device_init); -- GitLab From 91cc07069291d83b3fa90615373640e028068aaf Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 30 Aug 2017 12:04:07 +0200 Subject: [PATCH 1350/2547] dt-bindings: display: tegra: Update SOR for Tegra186 Update the SOR bindings for Tegra186, in which a new property is required to identify the instance of the SOR interface and the clock tree has slightly changed as well. Signed-off-by: Thierry Reding --- .../display/tegra/nvidia,tegra20-host1x.txt | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 844e0103fb0d..593be44a53c9 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -206,21 +206,33 @@ of the following host1x client modules: - "nvidia,tegra132-sor": for Tegra132 - "nvidia,tegra210-sor": for Tegra210 - "nvidia,tegra210-sor1": for Tegra210 + - "nvidia,tegra186-sor": for Tegra186 + - "nvidia,tegra186-sor1": for Tegra186 - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - sor: clock input for the SOR hardware - - source: source clock for the SOR clock + - out: SOR output clock - parent: input for the pixel clock - dp: reference clock for the SOR clock - safe: safe reference for the SOR clock during power up + + For Tegra186 and later: + - pad: SOR pad output clock (on Tegra186 and later) + + Obsolete: + - source: source clock for the SOR clock (obsolete, use "out" instead) + - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - sor + Required properties on Tegra186 and later: + - nvidia,interface: index of the SOR interface + Optional properties: - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection -- GitLab From cf6824ac7261c5e2cd98bf7aafe5d132431e0d7c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Nov 2017 12:13:22 +0100 Subject: [PATCH 1351/2547] drm/tegra: dc: Move register definitions into a table After commit 67e04d1ab19b ("drm/tegra: dc: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 442 +++++++++++++++++++------------------ 1 file changed, 224 insertions(+), 218 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index fc70351b9017..0c77473d6510 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1383,10 +1383,228 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) return IRQ_HANDLED; } +#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } + +static const struct debugfs_reg32 tegra_dc_regs[] = { + DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT), + DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL), + DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR), + DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT), + DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL), + DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR), + DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT), + DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL), + DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR), + DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT), + DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL), + DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR), + DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC), + DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0), + DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND), + DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE), + DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL), + DEBUGFS_REG32(DC_CMD_INT_STATUS), + DEBUGFS_REG32(DC_CMD_INT_MASK), + DEBUGFS_REG32(DC_CMD_INT_ENABLE), + DEBUGFS_REG32(DC_CMD_INT_TYPE), + DEBUGFS_REG32(DC_CMD_INT_POLARITY), + DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1), + DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2), + DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3), + DEBUGFS_REG32(DC_CMD_STATE_ACCESS), + DEBUGFS_REG32(DC_CMD_STATE_CONTROL), + DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER), + DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL), + DEBUGFS_REG32(DC_COM_CRC_CONTROL), + DEBUGFS_REG32(DC_COM_CRC_CHECKSUM), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)), + DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)), + DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)), + DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)), + DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)), + DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)), + DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)), + DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL), + DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL), + DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE), + DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL), + DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE), + DEBUGFS_REG32(DC_COM_SPI_CONTROL), + DEBUGFS_REG32(DC_COM_SPI_START_BYTE), + DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB), + DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD), + DEBUGFS_REG32(DC_COM_HSPI_CS_DC), + DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A), + DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B), + DEBUGFS_REG32(DC_COM_GPIO_CTRL), + DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER), + DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED), + DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0), + DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1), + DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS), + DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY), + DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER), + DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS), + DEBUGFS_REG32(DC_DISP_REF_TO_SYNC), + DEBUGFS_REG32(DC_DISP_SYNC_WIDTH), + DEBUGFS_REG32(DC_DISP_BACK_PORCH), + DEBUGFS_REG32(DC_DISP_ACTIVE), + DEBUGFS_REG32(DC_DISP_FRONT_PORCH), + DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL), + DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A), + DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B), + DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C), + DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D), + DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL), + DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A), + DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B), + DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C), + DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D), + DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL), + DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A), + DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B), + DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C), + DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D), + DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL), + DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A), + DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B), + DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C), + DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL), + DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A), + DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B), + DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C), + DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL), + DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A), + DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL), + DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A), + DEBUGFS_REG32(DC_DISP_M0_CONTROL), + DEBUGFS_REG32(DC_DISP_M1_CONTROL), + DEBUGFS_REG32(DC_DISP_DI_CONTROL), + DEBUGFS_REG32(DC_DISP_PP_CONTROL), + DEBUGFS_REG32(DC_DISP_PP_SELECT_A), + DEBUGFS_REG32(DC_DISP_PP_SELECT_B), + DEBUGFS_REG32(DC_DISP_PP_SELECT_C), + DEBUGFS_REG32(DC_DISP_PP_SELECT_D), + DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL), + DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL), + DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL), + DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS), + DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS), + DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS), + DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS), + DEBUGFS_REG32(DC_DISP_BORDER_COLOR), + DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER), + DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER), + DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER), + DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER), + DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND), + DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND), + DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR), + DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS), + DEBUGFS_REG32(DC_DISP_CURSOR_POSITION), + DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS), + DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL), + DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A), + DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B), + DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C), + DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D), + DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL), + DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST), + DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST), + DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST), + DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST), + DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL), + DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL), + DEBUGFS_REG32(DC_DISP_SD_CONTROL), + DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF), + DEBUGFS_REG32(DC_DISP_SD_LUT(0)), + DEBUGFS_REG32(DC_DISP_SD_LUT(1)), + DEBUGFS_REG32(DC_DISP_SD_LUT(2)), + DEBUGFS_REG32(DC_DISP_SD_LUT(3)), + DEBUGFS_REG32(DC_DISP_SD_LUT(4)), + DEBUGFS_REG32(DC_DISP_SD_LUT(5)), + DEBUGFS_REG32(DC_DISP_SD_LUT(6)), + DEBUGFS_REG32(DC_DISP_SD_LUT(7)), + DEBUGFS_REG32(DC_DISP_SD_LUT(8)), + DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL), + DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)), + DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)), + DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)), + DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)), + DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)), + DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL), + DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES), + DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES), + DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI), + DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL), + DEBUGFS_REG32(DC_WIN_WIN_OPTIONS), + DEBUGFS_REG32(DC_WIN_BYTE_SWAP), + DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL), + DEBUGFS_REG32(DC_WIN_COLOR_DEPTH), + DEBUGFS_REG32(DC_WIN_POSITION), + DEBUGFS_REG32(DC_WIN_SIZE), + DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE), + DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA), + DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA), + DEBUGFS_REG32(DC_WIN_DDA_INC), + DEBUGFS_REG32(DC_WIN_LINE_STRIDE), + DEBUGFS_REG32(DC_WIN_BUF_STRIDE), + DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE), + DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE), + DEBUGFS_REG32(DC_WIN_DV_CONTROL), + DEBUGFS_REG32(DC_WIN_BLEND_NOKEY), + DEBUGFS_REG32(DC_WIN_BLEND_1WIN), + DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X), + DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y), + DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY), + DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL), + DEBUGFS_REG32(DC_WINBUF_START_ADDR), + DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS), + DEBUGFS_REG32(DC_WINBUF_START_ADDR_U), + DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS), + DEBUGFS_REG32(DC_WINBUF_START_ADDR_V), + DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS), + DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET), + DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS), + DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET), + DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS), + DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS), + DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS), + DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS), + DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS), +}; + static int tegra_dc_show_regs(struct seq_file *s, void *data) { struct drm_info_node *node = s->private; struct tegra_dc *dc = node->info_ent->data; + unsigned int i; int err = 0; drm_modeset_lock(&dc->base.mutex, NULL); @@ -1396,224 +1614,12 @@ static int tegra_dc_show_regs(struct seq_file *s, void *data) goto unlock; } -#define DUMP_REG(name) \ - seq_printf(s, "%-40s %#05x %08x\n", #name, name, \ - tegra_dc_readl(dc, name)) - - DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT); - DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); - DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR); - DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT); - DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL); - DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR); - DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT); - DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL); - DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR); - DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT); - DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL); - DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR); - DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC); - DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0); - DUMP_REG(DC_CMD_DISPLAY_COMMAND); - DUMP_REG(DC_CMD_SIGNAL_RAISE); - DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL); - DUMP_REG(DC_CMD_INT_STATUS); - DUMP_REG(DC_CMD_INT_MASK); - DUMP_REG(DC_CMD_INT_ENABLE); - DUMP_REG(DC_CMD_INT_TYPE); - DUMP_REG(DC_CMD_INT_POLARITY); - DUMP_REG(DC_CMD_SIGNAL_RAISE1); - DUMP_REG(DC_CMD_SIGNAL_RAISE2); - DUMP_REG(DC_CMD_SIGNAL_RAISE3); - DUMP_REG(DC_CMD_STATE_ACCESS); - DUMP_REG(DC_CMD_STATE_CONTROL); - DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER); - DUMP_REG(DC_CMD_REG_ACT_CONTROL); - DUMP_REG(DC_COM_CRC_CONTROL); - DUMP_REG(DC_COM_CRC_CHECKSUM); - DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0)); - DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1)); - DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2)); - DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3)); - DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0)); - DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1)); - DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2)); - DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3)); - DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0)); - DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1)); - DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2)); - DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3)); - DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0)); - DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1)); - DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2)); - DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3)); - DUMP_REG(DC_COM_PIN_INPUT_DATA(0)); - DUMP_REG(DC_COM_PIN_INPUT_DATA(1)); - DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0)); - DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1)); - DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2)); - DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3)); - DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4)); - DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5)); - DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6)); - DUMP_REG(DC_COM_PIN_MISC_CONTROL); - DUMP_REG(DC_COM_PIN_PM0_CONTROL); - DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE); - DUMP_REG(DC_COM_PIN_PM1_CONTROL); - DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE); - DUMP_REG(DC_COM_SPI_CONTROL); - DUMP_REG(DC_COM_SPI_START_BYTE); - DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB); - DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD); - DUMP_REG(DC_COM_HSPI_CS_DC); - DUMP_REG(DC_COM_SCRATCH_REGISTER_A); - DUMP_REG(DC_COM_SCRATCH_REGISTER_B); - DUMP_REG(DC_COM_GPIO_CTRL); - DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER); - DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED); - DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0); - DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1); - DUMP_REG(DC_DISP_DISP_WIN_OPTIONS); - DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY); - DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); - DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS); - DUMP_REG(DC_DISP_REF_TO_SYNC); - DUMP_REG(DC_DISP_SYNC_WIDTH); - DUMP_REG(DC_DISP_BACK_PORCH); - DUMP_REG(DC_DISP_ACTIVE); - DUMP_REG(DC_DISP_FRONT_PORCH); - DUMP_REG(DC_DISP_H_PULSE0_CONTROL); - DUMP_REG(DC_DISP_H_PULSE0_POSITION_A); - DUMP_REG(DC_DISP_H_PULSE0_POSITION_B); - DUMP_REG(DC_DISP_H_PULSE0_POSITION_C); - DUMP_REG(DC_DISP_H_PULSE0_POSITION_D); - DUMP_REG(DC_DISP_H_PULSE1_CONTROL); - DUMP_REG(DC_DISP_H_PULSE1_POSITION_A); - DUMP_REG(DC_DISP_H_PULSE1_POSITION_B); - DUMP_REG(DC_DISP_H_PULSE1_POSITION_C); - DUMP_REG(DC_DISP_H_PULSE1_POSITION_D); - DUMP_REG(DC_DISP_H_PULSE2_CONTROL); - DUMP_REG(DC_DISP_H_PULSE2_POSITION_A); - DUMP_REG(DC_DISP_H_PULSE2_POSITION_B); - DUMP_REG(DC_DISP_H_PULSE2_POSITION_C); - DUMP_REG(DC_DISP_H_PULSE2_POSITION_D); - DUMP_REG(DC_DISP_V_PULSE0_CONTROL); - DUMP_REG(DC_DISP_V_PULSE0_POSITION_A); - DUMP_REG(DC_DISP_V_PULSE0_POSITION_B); - DUMP_REG(DC_DISP_V_PULSE0_POSITION_C); - DUMP_REG(DC_DISP_V_PULSE1_CONTROL); - DUMP_REG(DC_DISP_V_PULSE1_POSITION_A); - DUMP_REG(DC_DISP_V_PULSE1_POSITION_B); - DUMP_REG(DC_DISP_V_PULSE1_POSITION_C); - DUMP_REG(DC_DISP_V_PULSE2_CONTROL); - DUMP_REG(DC_DISP_V_PULSE2_POSITION_A); - DUMP_REG(DC_DISP_V_PULSE3_CONTROL); - DUMP_REG(DC_DISP_V_PULSE3_POSITION_A); - DUMP_REG(DC_DISP_M0_CONTROL); - DUMP_REG(DC_DISP_M1_CONTROL); - DUMP_REG(DC_DISP_DI_CONTROL); - DUMP_REG(DC_DISP_PP_CONTROL); - DUMP_REG(DC_DISP_PP_SELECT_A); - DUMP_REG(DC_DISP_PP_SELECT_B); - DUMP_REG(DC_DISP_PP_SELECT_C); - DUMP_REG(DC_DISP_PP_SELECT_D); - DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL); - DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL); - DUMP_REG(DC_DISP_DISP_COLOR_CONTROL); - DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS); - DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS); - DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS); - DUMP_REG(DC_DISP_LCD_SPI_OPTIONS); - DUMP_REG(DC_DISP_BORDER_COLOR); - DUMP_REG(DC_DISP_COLOR_KEY0_LOWER); - DUMP_REG(DC_DISP_COLOR_KEY0_UPPER); - DUMP_REG(DC_DISP_COLOR_KEY1_LOWER); - DUMP_REG(DC_DISP_COLOR_KEY1_UPPER); - DUMP_REG(DC_DISP_CURSOR_FOREGROUND); - DUMP_REG(DC_DISP_CURSOR_BACKGROUND); - DUMP_REG(DC_DISP_CURSOR_START_ADDR); - DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS); - DUMP_REG(DC_DISP_CURSOR_POSITION); - DUMP_REG(DC_DISP_CURSOR_POSITION_NS); - DUMP_REG(DC_DISP_INIT_SEQ_CONTROL); - DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A); - DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B); - DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C); - DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D); - DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL); - DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST); - DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST); - DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST); - DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST); - DUMP_REG(DC_DISP_DAC_CRT_CTRL); - DUMP_REG(DC_DISP_DISP_MISC_CONTROL); - DUMP_REG(DC_DISP_SD_CONTROL); - DUMP_REG(DC_DISP_SD_CSC_COEFF); - DUMP_REG(DC_DISP_SD_LUT(0)); - DUMP_REG(DC_DISP_SD_LUT(1)); - DUMP_REG(DC_DISP_SD_LUT(2)); - DUMP_REG(DC_DISP_SD_LUT(3)); - DUMP_REG(DC_DISP_SD_LUT(4)); - DUMP_REG(DC_DISP_SD_LUT(5)); - DUMP_REG(DC_DISP_SD_LUT(6)); - DUMP_REG(DC_DISP_SD_LUT(7)); - DUMP_REG(DC_DISP_SD_LUT(8)); - DUMP_REG(DC_DISP_SD_FLICKER_CONTROL); - DUMP_REG(DC_DISP_DC_PIXEL_COUNT); - DUMP_REG(DC_DISP_SD_HISTOGRAM(0)); - DUMP_REG(DC_DISP_SD_HISTOGRAM(1)); - DUMP_REG(DC_DISP_SD_HISTOGRAM(2)); - DUMP_REG(DC_DISP_SD_HISTOGRAM(3)); - DUMP_REG(DC_DISP_SD_HISTOGRAM(4)); - DUMP_REG(DC_DISP_SD_HISTOGRAM(5)); - DUMP_REG(DC_DISP_SD_HISTOGRAM(6)); - DUMP_REG(DC_DISP_SD_HISTOGRAM(7)); - DUMP_REG(DC_DISP_SD_BL_TF(0)); - DUMP_REG(DC_DISP_SD_BL_TF(1)); - DUMP_REG(DC_DISP_SD_BL_TF(2)); - DUMP_REG(DC_DISP_SD_BL_TF(3)); - DUMP_REG(DC_DISP_SD_BL_CONTROL); - DUMP_REG(DC_DISP_SD_HW_K_VALUES); - DUMP_REG(DC_DISP_SD_MAN_K_VALUES); - DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI); - DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL); - DUMP_REG(DC_WIN_WIN_OPTIONS); - DUMP_REG(DC_WIN_BYTE_SWAP); - DUMP_REG(DC_WIN_BUFFER_CONTROL); - DUMP_REG(DC_WIN_COLOR_DEPTH); - DUMP_REG(DC_WIN_POSITION); - DUMP_REG(DC_WIN_SIZE); - DUMP_REG(DC_WIN_PRESCALED_SIZE); - DUMP_REG(DC_WIN_H_INITIAL_DDA); - DUMP_REG(DC_WIN_V_INITIAL_DDA); - DUMP_REG(DC_WIN_DDA_INC); - DUMP_REG(DC_WIN_LINE_STRIDE); - DUMP_REG(DC_WIN_BUF_STRIDE); - DUMP_REG(DC_WIN_UV_BUF_STRIDE); - DUMP_REG(DC_WIN_BUFFER_ADDR_MODE); - DUMP_REG(DC_WIN_DV_CONTROL); - DUMP_REG(DC_WIN_BLEND_NOKEY); - DUMP_REG(DC_WIN_BLEND_1WIN); - DUMP_REG(DC_WIN_BLEND_2WIN_X); - DUMP_REG(DC_WIN_BLEND_2WIN_Y); - DUMP_REG(DC_WIN_BLEND_3WIN_XY); - DUMP_REG(DC_WIN_HP_FETCH_CONTROL); - DUMP_REG(DC_WINBUF_START_ADDR); - DUMP_REG(DC_WINBUF_START_ADDR_NS); - DUMP_REG(DC_WINBUF_START_ADDR_U); - DUMP_REG(DC_WINBUF_START_ADDR_U_NS); - DUMP_REG(DC_WINBUF_START_ADDR_V); - DUMP_REG(DC_WINBUF_START_ADDR_V_NS); - DUMP_REG(DC_WINBUF_ADDR_H_OFFSET); - DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS); - DUMP_REG(DC_WINBUF_ADDR_V_OFFSET); - DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS); - DUMP_REG(DC_WINBUF_UFLOW_STATUS); - DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS); - DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS); - DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS); - -#undef DUMP_REG + for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) { + unsigned int offset = tegra_dc_regs[i].offset; + + seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, + offset, tegra_dc_readl(dc, offset)); + } unlock: drm_modeset_unlock(&dc->base.mutex); -- GitLab From a40051c0fb3c5a655eb014b3b9d66c0c318bcbf9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Nov 2017 12:18:22 +0100 Subject: [PATCH 1352/2547] drm/tegra: dsi: Move register definitions into a table After commit 75af8fa7fd47 ("drm/tegra: dsi: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dsi.c | 170 ++++++++++++++++++------------------ 1 file changed, 83 insertions(+), 87 deletions(-) diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 046649ec9441..4a78af08df82 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -122,12 +122,89 @@ static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, writel(value, dsi->regs + (offset << 2)); } +#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } + +static const struct debugfs_reg32 tegra_dsi_regs[] = { + DEBUGFS_REG32(DSI_INCR_SYNCPT), + DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL), + DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR), + DEBUGFS_REG32(DSI_CTXSW), + DEBUGFS_REG32(DSI_RD_DATA), + DEBUGFS_REG32(DSI_WR_DATA), + DEBUGFS_REG32(DSI_POWER_CONTROL), + DEBUGFS_REG32(DSI_INT_ENABLE), + DEBUGFS_REG32(DSI_INT_STATUS), + DEBUGFS_REG32(DSI_INT_MASK), + DEBUGFS_REG32(DSI_HOST_CONTROL), + DEBUGFS_REG32(DSI_CONTROL), + DEBUGFS_REG32(DSI_SOL_DELAY), + DEBUGFS_REG32(DSI_MAX_THRESHOLD), + DEBUGFS_REG32(DSI_TRIGGER), + DEBUGFS_REG32(DSI_TX_CRC), + DEBUGFS_REG32(DSI_STATUS), + DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7), + DEBUGFS_REG32(DSI_PKT_SEQ_0_LO), + DEBUGFS_REG32(DSI_PKT_SEQ_0_HI), + DEBUGFS_REG32(DSI_PKT_SEQ_1_LO), + DEBUGFS_REG32(DSI_PKT_SEQ_1_HI), + DEBUGFS_REG32(DSI_PKT_SEQ_2_LO), + DEBUGFS_REG32(DSI_PKT_SEQ_2_HI), + DEBUGFS_REG32(DSI_PKT_SEQ_3_LO), + DEBUGFS_REG32(DSI_PKT_SEQ_3_HI), + DEBUGFS_REG32(DSI_PKT_SEQ_4_LO), + DEBUGFS_REG32(DSI_PKT_SEQ_4_HI), + DEBUGFS_REG32(DSI_PKT_SEQ_5_LO), + DEBUGFS_REG32(DSI_PKT_SEQ_5_HI), + DEBUGFS_REG32(DSI_DCS_CMDS), + DEBUGFS_REG32(DSI_PKT_LEN_0_1), + DEBUGFS_REG32(DSI_PKT_LEN_2_3), + DEBUGFS_REG32(DSI_PKT_LEN_4_5), + DEBUGFS_REG32(DSI_PKT_LEN_6_7), + DEBUGFS_REG32(DSI_PHY_TIMING_0), + DEBUGFS_REG32(DSI_PHY_TIMING_1), + DEBUGFS_REG32(DSI_PHY_TIMING_2), + DEBUGFS_REG32(DSI_BTA_TIMING), + DEBUGFS_REG32(DSI_TIMEOUT_0), + DEBUGFS_REG32(DSI_TIMEOUT_1), + DEBUGFS_REG32(DSI_TO_TALLY), + DEBUGFS_REG32(DSI_PAD_CONTROL_0), + DEBUGFS_REG32(DSI_PAD_CONTROL_CD), + DEBUGFS_REG32(DSI_PAD_CD_STATUS), + DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL), + DEBUGFS_REG32(DSI_PAD_CONTROL_1), + DEBUGFS_REG32(DSI_PAD_CONTROL_2), + DEBUGFS_REG32(DSI_PAD_CONTROL_3), + DEBUGFS_REG32(DSI_PAD_CONTROL_4), + DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL), + DEBUGFS_REG32(DSI_GANGED_MODE_START), + DEBUGFS_REG32(DSI_GANGED_MODE_SIZE), + DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT), + DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14), + DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15), +}; + static int tegra_dsi_show_regs(struct seq_file *s, void *data) { struct drm_info_node *node = s->private; struct tegra_dsi *dsi = node->info_ent->data; struct drm_crtc *crtc = dsi->output.encoder.crtc; struct drm_device *drm = node->minor->dev; + unsigned int i; int err = 0; drm_modeset_lock_all(drm); @@ -137,93 +214,12 @@ static int tegra_dsi_show_regs(struct seq_file *s, void *data) goto unlock; } -#define DUMP_REG(name) \ - seq_printf(s, "%-32s %#05x %08x\n", #name, name, \ - tegra_dsi_readl(dsi, name)) - - DUMP_REG(DSI_INCR_SYNCPT); - DUMP_REG(DSI_INCR_SYNCPT_CONTROL); - DUMP_REG(DSI_INCR_SYNCPT_ERROR); - DUMP_REG(DSI_CTXSW); - DUMP_REG(DSI_RD_DATA); - DUMP_REG(DSI_WR_DATA); - DUMP_REG(DSI_POWER_CONTROL); - DUMP_REG(DSI_INT_ENABLE); - DUMP_REG(DSI_INT_STATUS); - DUMP_REG(DSI_INT_MASK); - DUMP_REG(DSI_HOST_CONTROL); - DUMP_REG(DSI_CONTROL); - DUMP_REG(DSI_SOL_DELAY); - DUMP_REG(DSI_MAX_THRESHOLD); - DUMP_REG(DSI_TRIGGER); - DUMP_REG(DSI_TX_CRC); - DUMP_REG(DSI_STATUS); - - DUMP_REG(DSI_INIT_SEQ_CONTROL); - DUMP_REG(DSI_INIT_SEQ_DATA_0); - DUMP_REG(DSI_INIT_SEQ_DATA_1); - DUMP_REG(DSI_INIT_SEQ_DATA_2); - DUMP_REG(DSI_INIT_SEQ_DATA_3); - DUMP_REG(DSI_INIT_SEQ_DATA_4); - DUMP_REG(DSI_INIT_SEQ_DATA_5); - DUMP_REG(DSI_INIT_SEQ_DATA_6); - DUMP_REG(DSI_INIT_SEQ_DATA_7); - - DUMP_REG(DSI_PKT_SEQ_0_LO); - DUMP_REG(DSI_PKT_SEQ_0_HI); - DUMP_REG(DSI_PKT_SEQ_1_LO); - DUMP_REG(DSI_PKT_SEQ_1_HI); - DUMP_REG(DSI_PKT_SEQ_2_LO); - DUMP_REG(DSI_PKT_SEQ_2_HI); - DUMP_REG(DSI_PKT_SEQ_3_LO); - DUMP_REG(DSI_PKT_SEQ_3_HI); - DUMP_REG(DSI_PKT_SEQ_4_LO); - DUMP_REG(DSI_PKT_SEQ_4_HI); - DUMP_REG(DSI_PKT_SEQ_5_LO); - DUMP_REG(DSI_PKT_SEQ_5_HI); - - DUMP_REG(DSI_DCS_CMDS); - - DUMP_REG(DSI_PKT_LEN_0_1); - DUMP_REG(DSI_PKT_LEN_2_3); - DUMP_REG(DSI_PKT_LEN_4_5); - DUMP_REG(DSI_PKT_LEN_6_7); - - DUMP_REG(DSI_PHY_TIMING_0); - DUMP_REG(DSI_PHY_TIMING_1); - DUMP_REG(DSI_PHY_TIMING_2); - DUMP_REG(DSI_BTA_TIMING); - - DUMP_REG(DSI_TIMEOUT_0); - DUMP_REG(DSI_TIMEOUT_1); - DUMP_REG(DSI_TO_TALLY); - - DUMP_REG(DSI_PAD_CONTROL_0); - DUMP_REG(DSI_PAD_CONTROL_CD); - DUMP_REG(DSI_PAD_CD_STATUS); - DUMP_REG(DSI_VIDEO_MODE_CONTROL); - DUMP_REG(DSI_PAD_CONTROL_1); - DUMP_REG(DSI_PAD_CONTROL_2); - DUMP_REG(DSI_PAD_CONTROL_3); - DUMP_REG(DSI_PAD_CONTROL_4); - - DUMP_REG(DSI_GANGED_MODE_CONTROL); - DUMP_REG(DSI_GANGED_MODE_START); - DUMP_REG(DSI_GANGED_MODE_SIZE); - - DUMP_REG(DSI_RAW_DATA_BYTE_COUNT); - DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL); - - DUMP_REG(DSI_INIT_SEQ_DATA_8); - DUMP_REG(DSI_INIT_SEQ_DATA_9); - DUMP_REG(DSI_INIT_SEQ_DATA_10); - DUMP_REG(DSI_INIT_SEQ_DATA_11); - DUMP_REG(DSI_INIT_SEQ_DATA_12); - DUMP_REG(DSI_INIT_SEQ_DATA_13); - DUMP_REG(DSI_INIT_SEQ_DATA_14); - DUMP_REG(DSI_INIT_SEQ_DATA_15); - -#undef DUMP_REG + for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) { + unsigned int offset = tegra_dsi_regs[i].offset; + + seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name, + offset, tegra_dsi_readl(dsi, offset)); + } unlock: drm_modeset_unlock_all(drm); -- GitLab From fbfe16df30817a9d62dfb2633121068361fb7721 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Nov 2017 12:20:46 +0100 Subject: [PATCH 1353/2547] drm/tegra: hdmi: Move register definitions into a table After commit 07a8aab89927 ("drm/tegra: hdmi: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/hdmi.c | 346 ++++++++++++++++++----------------- 1 file changed, 176 insertions(+), 170 deletions(-) diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index 6434b3d3d1ba..a68d80476e46 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -1225,12 +1225,182 @@ static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = { .atomic_check = tegra_hdmi_encoder_atomic_check, }; +#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } + +static const struct debugfs_reg32 tegra_hdmi_regs[] = { + DEBUGFS_REG32(HDMI_CTXSW), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N), + DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK), + DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL), + DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL), + DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH), + DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE), + DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK), + DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT), +}; + static int tegra_hdmi_show_regs(struct seq_file *s, void *data) { struct drm_info_node *node = s->private; struct tegra_hdmi *hdmi = node->info_ent->data; struct drm_crtc *crtc = hdmi->output.encoder.crtc; struct drm_device *drm = node->minor->dev; + unsigned int i; int err = 0; drm_modeset_lock_all(drm); @@ -1240,176 +1410,12 @@ static int tegra_hdmi_show_regs(struct seq_file *s, void *data) goto unlock; } -#define DUMP_REG(name) \ - seq_printf(s, "%-56s %#05x %08x\n", #name, name, \ - tegra_hdmi_readl(hdmi, name)) - - DUMP_REG(HDMI_CTXSW); - DUMP_REG(HDMI_NV_PDISP_SOR_STATE0); - DUMP_REG(HDMI_NV_PDISP_SOR_STATE1); - DUMP_REG(HDMI_NV_PDISP_SOR_STATE2); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB); - DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB); - DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0); - DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0); - DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1); - DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2); - DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); - DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS); - DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER); - DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); - DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS); - DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER); - DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL); - DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS); - DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER); - DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH); - DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL); - DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT); - DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW); - DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL); - DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS); - DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK); - DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1); - DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2); - DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0); - DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1); - DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA); - DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE); - DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1); - DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2); - DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL); - DUMP_REG(HDMI_NV_PDISP_SOR_CAP); - DUMP_REG(HDMI_NV_PDISP_SOR_PWR); - DUMP_REG(HDMI_NV_PDISP_SOR_TEST); - DUMP_REG(HDMI_NV_PDISP_SOR_PLL0); - DUMP_REG(HDMI_NV_PDISP_SOR_PLL1); - DUMP_REG(HDMI_NV_PDISP_SOR_PLL2); - DUMP_REG(HDMI_NV_PDISP_SOR_CSTM); - DUMP_REG(HDMI_NV_PDISP_SOR_LVDS); - DUMP_REG(HDMI_NV_PDISP_SOR_CRCA); - DUMP_REG(HDMI_NV_PDISP_SOR_CRCB); - DUMP_REG(HDMI_NV_PDISP_SOR_BLANK); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14)); - DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15)); - DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0); - DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1); - DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0); - DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1); - DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0); - DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1); - DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0); - DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1); - DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0); - DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1); - DUMP_REG(HDMI_NV_PDISP_SOR_TRIG); - DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK); - DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); - DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0); - DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1); - DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2); - DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0)); - DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1)); - DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2)); - DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3)); - DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4)); - DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5)); - DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6)); - DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH); - DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD); - DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0); - DUMP_REG(HDMI_NV_PDISP_AUDIO_N); - DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING); - DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK); - DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL); - DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL); - DUMP_REG(HDMI_NV_PDISP_SCRATCH); - DUMP_REG(HDMI_NV_PDISP_PE_CURRENT); - DUMP_REG(HDMI_NV_PDISP_KEY_CTRL); - DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0); - DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1); - DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2); - DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0); - DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1); - DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2); - DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3); - DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG); - DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX); - DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0); - DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_SPARE0); - DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0); - DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1); - DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR); - DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE); - DUMP_REG(HDMI_NV_PDISP_INT_STATUS); - DUMP_REG(HDMI_NV_PDISP_INT_MASK); - DUMP_REG(HDMI_NV_PDISP_INT_ENABLE); - DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT); - -#undef DUMP_REG + for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) { + unsigned int offset = tegra_hdmi_regs[i].offset; + + seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name, + offset, tegra_hdmi_readl(hdmi, offset)); + } unlock: drm_modeset_unlock_all(drm); -- GitLab From 062f5b2c423ce6069b385745153938cf74013d4a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Nov 2017 12:21:51 +0100 Subject: [PATCH 1354/2547] drm/tegra: sor: Move register definitions into a table After commit 932f6529139e ("drm/tegra: sor: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 246 ++++++++++++++++++------------------ 1 file changed, 126 insertions(+), 120 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index b0a1dedac802..75b21dbaa8f0 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -1105,12 +1105,132 @@ static int tegra_sor_show_crc(struct seq_file *s, void *data) return err; } +#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } + +static const struct debugfs_reg32 tegra_sor_regs[] = { + DEBUGFS_REG32(SOR_CTXSW), + DEBUGFS_REG32(SOR_SUPER_STATE0), + DEBUGFS_REG32(SOR_SUPER_STATE1), + DEBUGFS_REG32(SOR_STATE0), + DEBUGFS_REG32(SOR_STATE1), + DEBUGFS_REG32(SOR_HEAD_STATE0(0)), + DEBUGFS_REG32(SOR_HEAD_STATE0(1)), + DEBUGFS_REG32(SOR_HEAD_STATE1(0)), + DEBUGFS_REG32(SOR_HEAD_STATE1(1)), + DEBUGFS_REG32(SOR_HEAD_STATE2(0)), + DEBUGFS_REG32(SOR_HEAD_STATE2(1)), + DEBUGFS_REG32(SOR_HEAD_STATE3(0)), + DEBUGFS_REG32(SOR_HEAD_STATE3(1)), + DEBUGFS_REG32(SOR_HEAD_STATE4(0)), + DEBUGFS_REG32(SOR_HEAD_STATE4(1)), + DEBUGFS_REG32(SOR_HEAD_STATE5(0)), + DEBUGFS_REG32(SOR_HEAD_STATE5(1)), + DEBUGFS_REG32(SOR_CRC_CNTRL), + DEBUGFS_REG32(SOR_DP_DEBUG_MVID), + DEBUGFS_REG32(SOR_CLK_CNTRL), + DEBUGFS_REG32(SOR_CAP), + DEBUGFS_REG32(SOR_PWR), + DEBUGFS_REG32(SOR_TEST), + DEBUGFS_REG32(SOR_PLL0), + DEBUGFS_REG32(SOR_PLL1), + DEBUGFS_REG32(SOR_PLL2), + DEBUGFS_REG32(SOR_PLL3), + DEBUGFS_REG32(SOR_CSTM), + DEBUGFS_REG32(SOR_LVDS), + DEBUGFS_REG32(SOR_CRCA), + DEBUGFS_REG32(SOR_CRCB), + DEBUGFS_REG32(SOR_BLANK), + DEBUGFS_REG32(SOR_SEQ_CTL), + DEBUGFS_REG32(SOR_LANE_SEQ_CTL), + DEBUGFS_REG32(SOR_SEQ_INST(0)), + DEBUGFS_REG32(SOR_SEQ_INST(1)), + DEBUGFS_REG32(SOR_SEQ_INST(2)), + DEBUGFS_REG32(SOR_SEQ_INST(3)), + DEBUGFS_REG32(SOR_SEQ_INST(4)), + DEBUGFS_REG32(SOR_SEQ_INST(5)), + DEBUGFS_REG32(SOR_SEQ_INST(6)), + DEBUGFS_REG32(SOR_SEQ_INST(7)), + DEBUGFS_REG32(SOR_SEQ_INST(8)), + DEBUGFS_REG32(SOR_SEQ_INST(9)), + DEBUGFS_REG32(SOR_SEQ_INST(10)), + DEBUGFS_REG32(SOR_SEQ_INST(11)), + DEBUGFS_REG32(SOR_SEQ_INST(12)), + DEBUGFS_REG32(SOR_SEQ_INST(13)), + DEBUGFS_REG32(SOR_SEQ_INST(14)), + DEBUGFS_REG32(SOR_SEQ_INST(15)), + DEBUGFS_REG32(SOR_PWM_DIV), + DEBUGFS_REG32(SOR_PWM_CTL), + DEBUGFS_REG32(SOR_VCRC_A0), + DEBUGFS_REG32(SOR_VCRC_A1), + DEBUGFS_REG32(SOR_VCRC_B0), + DEBUGFS_REG32(SOR_VCRC_B1), + DEBUGFS_REG32(SOR_CCRC_A0), + DEBUGFS_REG32(SOR_CCRC_A1), + DEBUGFS_REG32(SOR_CCRC_B0), + DEBUGFS_REG32(SOR_CCRC_B1), + DEBUGFS_REG32(SOR_EDATA_A0), + DEBUGFS_REG32(SOR_EDATA_A1), + DEBUGFS_REG32(SOR_EDATA_B0), + DEBUGFS_REG32(SOR_EDATA_B1), + DEBUGFS_REG32(SOR_COUNT_A0), + DEBUGFS_REG32(SOR_COUNT_A1), + DEBUGFS_REG32(SOR_COUNT_B0), + DEBUGFS_REG32(SOR_COUNT_B1), + DEBUGFS_REG32(SOR_DEBUG_A0), + DEBUGFS_REG32(SOR_DEBUG_A1), + DEBUGFS_REG32(SOR_DEBUG_B0), + DEBUGFS_REG32(SOR_DEBUG_B1), + DEBUGFS_REG32(SOR_TRIG), + DEBUGFS_REG32(SOR_MSCHECK), + DEBUGFS_REG32(SOR_XBAR_CTRL), + DEBUGFS_REG32(SOR_XBAR_POL), + DEBUGFS_REG32(SOR_DP_LINKCTL0), + DEBUGFS_REG32(SOR_DP_LINKCTL1), + DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0), + DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1), + DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0), + DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1), + DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0), + DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1), + DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0), + DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1), + DEBUGFS_REG32(SOR_LANE_POSTCURSOR0), + DEBUGFS_REG32(SOR_LANE_POSTCURSOR1), + DEBUGFS_REG32(SOR_DP_CONFIG0), + DEBUGFS_REG32(SOR_DP_CONFIG1), + DEBUGFS_REG32(SOR_DP_MN0), + DEBUGFS_REG32(SOR_DP_MN1), + DEBUGFS_REG32(SOR_DP_PADCTL0), + DEBUGFS_REG32(SOR_DP_PADCTL1), + DEBUGFS_REG32(SOR_DP_DEBUG0), + DEBUGFS_REG32(SOR_DP_DEBUG1), + DEBUGFS_REG32(SOR_DP_SPARE0), + DEBUGFS_REG32(SOR_DP_SPARE1), + DEBUGFS_REG32(SOR_DP_AUDIO_CTRL), + DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS), + DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS), + DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER), + DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0), + DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1), + DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2), + DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3), + DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4), + DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5), + DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6), + DEBUGFS_REG32(SOR_DP_TPG), + DEBUGFS_REG32(SOR_DP_TPG_CONFIG), + DEBUGFS_REG32(SOR_DP_LQ_CSTM0), + DEBUGFS_REG32(SOR_DP_LQ_CSTM1), + DEBUGFS_REG32(SOR_DP_LQ_CSTM2), +}; + static int tegra_sor_show_regs(struct seq_file *s, void *data) { struct drm_info_node *node = s->private; struct tegra_sor *sor = node->info_ent->data; struct drm_crtc *crtc = sor->output.encoder.crtc; struct drm_device *drm = node->minor->dev; + unsigned int i; int err = 0; drm_modeset_lock_all(drm); @@ -1120,126 +1240,12 @@ static int tegra_sor_show_regs(struct seq_file *s, void *data) goto unlock; } -#define DUMP_REG(name) \ - seq_printf(s, "%-38s %#05x %08x\n", #name, name, \ - tegra_sor_readl(sor, name)) - - DUMP_REG(SOR_CTXSW); - DUMP_REG(SOR_SUPER_STATE0); - DUMP_REG(SOR_SUPER_STATE1); - DUMP_REG(SOR_STATE0); - DUMP_REG(SOR_STATE1); - DUMP_REG(SOR_HEAD_STATE0(0)); - DUMP_REG(SOR_HEAD_STATE0(1)); - DUMP_REG(SOR_HEAD_STATE1(0)); - DUMP_REG(SOR_HEAD_STATE1(1)); - DUMP_REG(SOR_HEAD_STATE2(0)); - DUMP_REG(SOR_HEAD_STATE2(1)); - DUMP_REG(SOR_HEAD_STATE3(0)); - DUMP_REG(SOR_HEAD_STATE3(1)); - DUMP_REG(SOR_HEAD_STATE4(0)); - DUMP_REG(SOR_HEAD_STATE4(1)); - DUMP_REG(SOR_HEAD_STATE5(0)); - DUMP_REG(SOR_HEAD_STATE5(1)); - DUMP_REG(SOR_CRC_CNTRL); - DUMP_REG(SOR_DP_DEBUG_MVID); - DUMP_REG(SOR_CLK_CNTRL); - DUMP_REG(SOR_CAP); - DUMP_REG(SOR_PWR); - DUMP_REG(SOR_TEST); - DUMP_REG(SOR_PLL0); - DUMP_REG(SOR_PLL1); - DUMP_REG(SOR_PLL2); - DUMP_REG(SOR_PLL3); - DUMP_REG(SOR_CSTM); - DUMP_REG(SOR_LVDS); - DUMP_REG(SOR_CRCA); - DUMP_REG(SOR_CRCB); - DUMP_REG(SOR_BLANK); - DUMP_REG(SOR_SEQ_CTL); - DUMP_REG(SOR_LANE_SEQ_CTL); - DUMP_REG(SOR_SEQ_INST(0)); - DUMP_REG(SOR_SEQ_INST(1)); - DUMP_REG(SOR_SEQ_INST(2)); - DUMP_REG(SOR_SEQ_INST(3)); - DUMP_REG(SOR_SEQ_INST(4)); - DUMP_REG(SOR_SEQ_INST(5)); - DUMP_REG(SOR_SEQ_INST(6)); - DUMP_REG(SOR_SEQ_INST(7)); - DUMP_REG(SOR_SEQ_INST(8)); - DUMP_REG(SOR_SEQ_INST(9)); - DUMP_REG(SOR_SEQ_INST(10)); - DUMP_REG(SOR_SEQ_INST(11)); - DUMP_REG(SOR_SEQ_INST(12)); - DUMP_REG(SOR_SEQ_INST(13)); - DUMP_REG(SOR_SEQ_INST(14)); - DUMP_REG(SOR_SEQ_INST(15)); - DUMP_REG(SOR_PWM_DIV); - DUMP_REG(SOR_PWM_CTL); - DUMP_REG(SOR_VCRC_A0); - DUMP_REG(SOR_VCRC_A1); - DUMP_REG(SOR_VCRC_B0); - DUMP_REG(SOR_VCRC_B1); - DUMP_REG(SOR_CCRC_A0); - DUMP_REG(SOR_CCRC_A1); - DUMP_REG(SOR_CCRC_B0); - DUMP_REG(SOR_CCRC_B1); - DUMP_REG(SOR_EDATA_A0); - DUMP_REG(SOR_EDATA_A1); - DUMP_REG(SOR_EDATA_B0); - DUMP_REG(SOR_EDATA_B1); - DUMP_REG(SOR_COUNT_A0); - DUMP_REG(SOR_COUNT_A1); - DUMP_REG(SOR_COUNT_B0); - DUMP_REG(SOR_COUNT_B1); - DUMP_REG(SOR_DEBUG_A0); - DUMP_REG(SOR_DEBUG_A1); - DUMP_REG(SOR_DEBUG_B0); - DUMP_REG(SOR_DEBUG_B1); - DUMP_REG(SOR_TRIG); - DUMP_REG(SOR_MSCHECK); - DUMP_REG(SOR_XBAR_CTRL); - DUMP_REG(SOR_XBAR_POL); - DUMP_REG(SOR_DP_LINKCTL0); - DUMP_REG(SOR_DP_LINKCTL1); - DUMP_REG(SOR_LANE_DRIVE_CURRENT0); - DUMP_REG(SOR_LANE_DRIVE_CURRENT1); - DUMP_REG(SOR_LANE4_DRIVE_CURRENT0); - DUMP_REG(SOR_LANE4_DRIVE_CURRENT1); - DUMP_REG(SOR_LANE_PREEMPHASIS0); - DUMP_REG(SOR_LANE_PREEMPHASIS1); - DUMP_REG(SOR_LANE4_PREEMPHASIS0); - DUMP_REG(SOR_LANE4_PREEMPHASIS1); - DUMP_REG(SOR_LANE_POSTCURSOR0); - DUMP_REG(SOR_LANE_POSTCURSOR1); - DUMP_REG(SOR_DP_CONFIG0); - DUMP_REG(SOR_DP_CONFIG1); - DUMP_REG(SOR_DP_MN0); - DUMP_REG(SOR_DP_MN1); - DUMP_REG(SOR_DP_PADCTL0); - DUMP_REG(SOR_DP_PADCTL1); - DUMP_REG(SOR_DP_DEBUG0); - DUMP_REG(SOR_DP_DEBUG1); - DUMP_REG(SOR_DP_SPARE0); - DUMP_REG(SOR_DP_SPARE1); - DUMP_REG(SOR_DP_AUDIO_CTRL); - DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS); - DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS); - DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER); - DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0); - DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1); - DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2); - DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3); - DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4); - DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5); - DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6); - DUMP_REG(SOR_DP_TPG); - DUMP_REG(SOR_DP_TPG_CONFIG); - DUMP_REG(SOR_DP_LQ_CSTM0); - DUMP_REG(SOR_DP_LQ_CSTM1); - DUMP_REG(SOR_DP_LQ_CSTM2); - -#undef DUMP_REG + for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) { + unsigned int offset = tegra_sor_regs[i].offset; + + seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name, + offset, tegra_sor_readl(sor, offset)); + } unlock: drm_modeset_unlock_all(drm); -- GitLab From c49c81e21ce1a646c1402597d12137c679ac7f71 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 8 Nov 2017 13:32:05 +0100 Subject: [PATCH 1355/2547] drm/tegra: dc: Reshuffle some code Reshuffle some code so that functions are defined closer to where they are used. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 152 ++++++++++++++++++------------------- 1 file changed, 76 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 0c77473d6510..271357482401 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -909,82 +909,6 @@ static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) return 0; } -static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) -{ - struct tegra_dc *dc = to_tegra_dc(crtc); - - if (dc->syncpt) - return host1x_syncpt_read(dc->syncpt); - - /* fallback to software emulated VBLANK counter */ - return drm_crtc_vblank_count(&dc->base); -} - -static int tegra_dc_enable_vblank(struct drm_crtc *crtc) -{ - struct tegra_dc *dc = to_tegra_dc(crtc); - unsigned long value, flags; - - spin_lock_irqsave(&dc->lock, flags); - - value = tegra_dc_readl(dc, DC_CMD_INT_MASK); - value |= VBLANK_INT; - tegra_dc_writel(dc, value, DC_CMD_INT_MASK); - - spin_unlock_irqrestore(&dc->lock, flags); - - return 0; -} - -static void tegra_dc_disable_vblank(struct drm_crtc *crtc) -{ - struct tegra_dc *dc = to_tegra_dc(crtc); - unsigned long value, flags; - - spin_lock_irqsave(&dc->lock, flags); - - value = tegra_dc_readl(dc, DC_CMD_INT_MASK); - value &= ~VBLANK_INT; - tegra_dc_writel(dc, value, DC_CMD_INT_MASK); - - spin_unlock_irqrestore(&dc->lock, flags); -} - -static void tegra_dc_finish_page_flip(struct tegra_dc *dc) -{ - struct drm_device *drm = dc->base.dev; - struct drm_crtc *crtc = &dc->base; - unsigned long flags, base; - struct tegra_bo *bo; - - spin_lock_irqsave(&drm->event_lock, flags); - - if (!dc->event) { - spin_unlock_irqrestore(&drm->event_lock, flags); - return; - } - - bo = tegra_fb_get_plane(crtc->primary->fb, 0); - - spin_lock(&dc->lock); - - /* check if new start address has been latched */ - tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); - tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); - base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); - tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); - - spin_unlock(&dc->lock); - - if (base == bo->paddr + crtc->primary->fb->offsets[0]) { - drm_crtc_send_vblank_event(crtc, dc->event); - drm_crtc_vblank_put(crtc); - dc->event = NULL; - } - - spin_unlock_irqrestore(&drm->event_lock, flags); -} - static void tegra_dc_destroy(struct drm_crtc *crtc) { drm_crtc_cleanup(crtc); @@ -1035,6 +959,47 @@ static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, kfree(state); } +static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) +{ + struct tegra_dc *dc = to_tegra_dc(crtc); + + if (dc->syncpt) + return host1x_syncpt_read(dc->syncpt); + + /* fallback to software emulated VBLANK counter */ + return drm_crtc_vblank_count(&dc->base); +} + +static int tegra_dc_enable_vblank(struct drm_crtc *crtc) +{ + struct tegra_dc *dc = to_tegra_dc(crtc); + unsigned long value, flags; + + spin_lock_irqsave(&dc->lock, flags); + + value = tegra_dc_readl(dc, DC_CMD_INT_MASK); + value |= VBLANK_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_MASK); + + spin_unlock_irqrestore(&dc->lock, flags); + + return 0; +} + +static void tegra_dc_disable_vblank(struct drm_crtc *crtc) +{ + struct tegra_dc *dc = to_tegra_dc(crtc); + unsigned long value, flags; + + spin_lock_irqsave(&dc->lock, flags); + + value = tegra_dc_readl(dc, DC_CMD_INT_MASK); + value &= ~VBLANK_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_MASK); + + spin_unlock_irqrestore(&dc->lock, flags); +} + static const struct drm_crtc_funcs tegra_crtc_funcs = { .page_flip = drm_atomic_helper_page_flip, .set_config = drm_atomic_helper_set_config, @@ -1342,6 +1307,41 @@ static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { .atomic_disable = tegra_crtc_atomic_disable, }; +static void tegra_dc_finish_page_flip(struct tegra_dc *dc) +{ + struct drm_device *drm = dc->base.dev; + struct drm_crtc *crtc = &dc->base; + unsigned long flags, base; + struct tegra_bo *bo; + + spin_lock_irqsave(&drm->event_lock, flags); + + if (!dc->event) { + spin_unlock_irqrestore(&drm->event_lock, flags); + return; + } + + bo = tegra_fb_get_plane(crtc->primary->fb, 0); + + spin_lock(&dc->lock); + + /* check if new start address has been latched */ + tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); + tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); + base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); + tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); + + spin_unlock(&dc->lock); + + if (base == bo->paddr + crtc->primary->fb->offsets[0]) { + drm_crtc_send_vblank_event(crtc, dc->event); + drm_crtc_vblank_put(crtc); + dc->event = NULL; + } + + spin_unlock_irqrestore(&drm->event_lock, flags); +} + static irqreturn_t tegra_dc_irq(int irq, void *data) { struct tegra_dc *dc = data; -- GitLab From b95800eeef09f4853904ec4e926d098f1ca4698a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 8 Nov 2017 13:40:54 +0100 Subject: [PATCH 1356/2547] drm/tegra: dc: Register debugfs in ->late_register() The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 1120 ++++++++++++++++++------------------ drivers/gpu/drm/tegra/dc.h | 2 - 2 files changed, 546 insertions(+), 576 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 271357482401..29777604df39 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -959,37 +959,370 @@ static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, kfree(state); } -static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) -{ - struct tegra_dc *dc = to_tegra_dc(crtc); - - if (dc->syncpt) - return host1x_syncpt_read(dc->syncpt); +#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } - /* fallback to software emulated VBLANK counter */ - return drm_crtc_vblank_count(&dc->base); -} +static const struct debugfs_reg32 tegra_dc_regs[] = { + DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT), + DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL), + DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR), + DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT), + DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL), + DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR), + DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT), + DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL), + DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR), + DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT), + DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL), + DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR), + DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC), + DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0), + DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND), + DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE), + DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL), + DEBUGFS_REG32(DC_CMD_INT_STATUS), + DEBUGFS_REG32(DC_CMD_INT_MASK), + DEBUGFS_REG32(DC_CMD_INT_ENABLE), + DEBUGFS_REG32(DC_CMD_INT_TYPE), + DEBUGFS_REG32(DC_CMD_INT_POLARITY), + DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1), + DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2), + DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3), + DEBUGFS_REG32(DC_CMD_STATE_ACCESS), + DEBUGFS_REG32(DC_CMD_STATE_CONTROL), + DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER), + DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL), + DEBUGFS_REG32(DC_COM_CRC_CONTROL), + DEBUGFS_REG32(DC_COM_CRC_CHECKSUM), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)), + DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)), + DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)), + DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)), + DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)), + DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)), + DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)), + DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)), + DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL), + DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL), + DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE), + DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL), + DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE), + DEBUGFS_REG32(DC_COM_SPI_CONTROL), + DEBUGFS_REG32(DC_COM_SPI_START_BYTE), + DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB), + DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD), + DEBUGFS_REG32(DC_COM_HSPI_CS_DC), + DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A), + DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B), + DEBUGFS_REG32(DC_COM_GPIO_CTRL), + DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER), + DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED), + DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0), + DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1), + DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS), + DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY), + DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER), + DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS), + DEBUGFS_REG32(DC_DISP_REF_TO_SYNC), + DEBUGFS_REG32(DC_DISP_SYNC_WIDTH), + DEBUGFS_REG32(DC_DISP_BACK_PORCH), + DEBUGFS_REG32(DC_DISP_ACTIVE), + DEBUGFS_REG32(DC_DISP_FRONT_PORCH), + DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL), + DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A), + DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B), + DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C), + DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D), + DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL), + DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A), + DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B), + DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C), + DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D), + DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL), + DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A), + DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B), + DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C), + DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D), + DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL), + DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A), + DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B), + DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C), + DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL), + DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A), + DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B), + DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C), + DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL), + DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A), + DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL), + DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A), + DEBUGFS_REG32(DC_DISP_M0_CONTROL), + DEBUGFS_REG32(DC_DISP_M1_CONTROL), + DEBUGFS_REG32(DC_DISP_DI_CONTROL), + DEBUGFS_REG32(DC_DISP_PP_CONTROL), + DEBUGFS_REG32(DC_DISP_PP_SELECT_A), + DEBUGFS_REG32(DC_DISP_PP_SELECT_B), + DEBUGFS_REG32(DC_DISP_PP_SELECT_C), + DEBUGFS_REG32(DC_DISP_PP_SELECT_D), + DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL), + DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL), + DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL), + DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS), + DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS), + DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS), + DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS), + DEBUGFS_REG32(DC_DISP_BORDER_COLOR), + DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER), + DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER), + DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER), + DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER), + DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND), + DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND), + DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR), + DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS), + DEBUGFS_REG32(DC_DISP_CURSOR_POSITION), + DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS), + DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL), + DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A), + DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B), + DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C), + DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D), + DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL), + DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST), + DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST), + DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST), + DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST), + DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL), + DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL), + DEBUGFS_REG32(DC_DISP_SD_CONTROL), + DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF), + DEBUGFS_REG32(DC_DISP_SD_LUT(0)), + DEBUGFS_REG32(DC_DISP_SD_LUT(1)), + DEBUGFS_REG32(DC_DISP_SD_LUT(2)), + DEBUGFS_REG32(DC_DISP_SD_LUT(3)), + DEBUGFS_REG32(DC_DISP_SD_LUT(4)), + DEBUGFS_REG32(DC_DISP_SD_LUT(5)), + DEBUGFS_REG32(DC_DISP_SD_LUT(6)), + DEBUGFS_REG32(DC_DISP_SD_LUT(7)), + DEBUGFS_REG32(DC_DISP_SD_LUT(8)), + DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL), + DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)), + DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)), + DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)), + DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)), + DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)), + DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)), + DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL), + DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES), + DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES), + DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI), + DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL), + DEBUGFS_REG32(DC_WIN_WIN_OPTIONS), + DEBUGFS_REG32(DC_WIN_BYTE_SWAP), + DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL), + DEBUGFS_REG32(DC_WIN_COLOR_DEPTH), + DEBUGFS_REG32(DC_WIN_POSITION), + DEBUGFS_REG32(DC_WIN_SIZE), + DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE), + DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA), + DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA), + DEBUGFS_REG32(DC_WIN_DDA_INC), + DEBUGFS_REG32(DC_WIN_LINE_STRIDE), + DEBUGFS_REG32(DC_WIN_BUF_STRIDE), + DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE), + DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE), + DEBUGFS_REG32(DC_WIN_DV_CONTROL), + DEBUGFS_REG32(DC_WIN_BLEND_NOKEY), + DEBUGFS_REG32(DC_WIN_BLEND_1WIN), + DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X), + DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y), + DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY), + DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL), + DEBUGFS_REG32(DC_WINBUF_START_ADDR), + DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS), + DEBUGFS_REG32(DC_WINBUF_START_ADDR_U), + DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS), + DEBUGFS_REG32(DC_WINBUF_START_ADDR_V), + DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS), + DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET), + DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS), + DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET), + DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS), + DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS), + DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS), + DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS), + DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS), +}; -static int tegra_dc_enable_vblank(struct drm_crtc *crtc) +static int tegra_dc_show_regs(struct seq_file *s, void *data) { - struct tegra_dc *dc = to_tegra_dc(crtc); - unsigned long value, flags; + struct drm_info_node *node = s->private; + struct tegra_dc *dc = node->info_ent->data; + unsigned int i; + int err = 0; - spin_lock_irqsave(&dc->lock, flags); + drm_modeset_lock(&dc->base.mutex, NULL); - value = tegra_dc_readl(dc, DC_CMD_INT_MASK); - value |= VBLANK_INT; - tegra_dc_writel(dc, value, DC_CMD_INT_MASK); + if (!dc->base.state->active) { + err = -EBUSY; + goto unlock; + } - spin_unlock_irqrestore(&dc->lock, flags); + for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) { + unsigned int offset = tegra_dc_regs[i].offset; - return 0; + seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, + offset, tegra_dc_readl(dc, offset)); + } + +unlock: + drm_modeset_unlock(&dc->base.mutex); + return err; } -static void tegra_dc_disable_vblank(struct drm_crtc *crtc) +static int tegra_dc_show_crc(struct seq_file *s, void *data) { - struct tegra_dc *dc = to_tegra_dc(crtc); - unsigned long value, flags; + struct drm_info_node *node = s->private; + struct tegra_dc *dc = node->info_ent->data; + int err = 0; + u32 value; + + drm_modeset_lock(&dc->base.mutex, NULL); + + if (!dc->base.state->active) { + err = -EBUSY; + goto unlock; + } + + value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE; + tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); + tegra_dc_commit(dc); + + drm_crtc_wait_one_vblank(&dc->base); + drm_crtc_wait_one_vblank(&dc->base); + + value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); + seq_printf(s, "%08x\n", value); + + tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); + +unlock: + drm_modeset_unlock(&dc->base.mutex); + return err; +} + +static int tegra_dc_show_stats(struct seq_file *s, void *data) +{ + struct drm_info_node *node = s->private; + struct tegra_dc *dc = node->info_ent->data; + + seq_printf(s, "frames: %lu\n", dc->stats.frames); + seq_printf(s, "vblank: %lu\n", dc->stats.vblank); + seq_printf(s, "underflow: %lu\n", dc->stats.underflow); + seq_printf(s, "overflow: %lu\n", dc->stats.overflow); + + return 0; +} + +static struct drm_info_list debugfs_files[] = { + { "regs", tegra_dc_show_regs, 0, NULL }, + { "crc", tegra_dc_show_crc, 0, NULL }, + { "stats", tegra_dc_show_stats, 0, NULL }, +}; + +static int tegra_dc_late_register(struct drm_crtc *crtc) +{ + unsigned int i, count = ARRAY_SIZE(debugfs_files); + struct drm_minor *minor = crtc->dev->primary; + struct dentry *root = crtc->debugfs_entry; + struct tegra_dc *dc = to_tegra_dc(crtc); + int err; + + dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), + GFP_KERNEL); + if (!dc->debugfs_files) + return -ENOMEM; + + for (i = 0; i < count; i++) + dc->debugfs_files[i].data = dc; + + err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor); + if (err < 0) + goto free; + + return 0; + +free: + kfree(dc->debugfs_files); + dc->debugfs_files = NULL; + + return err; +} + +static void tegra_dc_early_unregister(struct drm_crtc *crtc) +{ + unsigned int count = ARRAY_SIZE(debugfs_files); + struct drm_minor *minor = crtc->dev->primary; + struct tegra_dc *dc = to_tegra_dc(crtc); + + drm_debugfs_remove_files(dc->debugfs_files, count, minor); + kfree(dc->debugfs_files); + dc->debugfs_files = NULL; +} + +static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) +{ + struct tegra_dc *dc = to_tegra_dc(crtc); + + if (dc->syncpt) + return host1x_syncpt_read(dc->syncpt); + + /* fallback to software emulated VBLANK counter */ + return drm_crtc_vblank_count(&dc->base); +} + +static int tegra_dc_enable_vblank(struct drm_crtc *crtc) +{ + struct tegra_dc *dc = to_tegra_dc(crtc); + unsigned long value, flags; + + spin_lock_irqsave(&dc->lock, flags); + + value = tegra_dc_readl(dc, DC_CMD_INT_MASK); + value |= VBLANK_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_MASK); + + spin_unlock_irqrestore(&dc->lock, flags); + + return 0; +} + +static void tegra_dc_disable_vblank(struct drm_crtc *crtc) +{ + struct tegra_dc *dc = to_tegra_dc(crtc); + unsigned long value, flags; spin_lock_irqsave(&dc->lock, flags); @@ -1007,6 +1340,8 @@ static const struct drm_crtc_funcs tegra_crtc_funcs = { .reset = tegra_crtc_reset, .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, .atomic_destroy_state = tegra_crtc_atomic_destroy_state, + .late_register = tegra_dc_late_register, + .early_unregister = tegra_dc_early_unregister, .get_vblank_counter = tegra_dc_get_vblank_counter, .enable_vblank = tegra_dc_enable_vblank, .disable_vblank = tegra_dc_disable_vblank, @@ -1148,590 +1483,239 @@ static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) -{ - struct tegra_dc *dc = to_tegra_dc(crtc); - u32 value; - - if (!tegra_dc_idle(dc)) { - tegra_dc_stop(dc); - - /* - * Ignore the return value, there isn't anything useful to do - * in case this fails. - */ - tegra_dc_wait_idle(dc, 100); - } - - /* - * This should really be part of the RGB encoder driver, but clearing - * these bits has the side-effect of stopping the display controller. - * When that happens no VBLANK interrupts will be raised. At the same - * time the encoder is disabled before the display controller, so the - * above code is always going to timeout waiting for the controller - * to go idle. - * - * Given the close coupling between the RGB encoder and the display - * controller doing it here is still kind of okay. None of the other - * encoder drivers require these bits to be cleared. - * - * XXX: Perhaps given that the display controller is switched off at - * this point anyway maybe clearing these bits isn't even useful for - * the RGB encoder? - */ - if (dc->rgb) { - value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); - value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | - PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); - tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); - } - - tegra_dc_stats_reset(&dc->stats); - drm_crtc_vblank_off(crtc); - - pm_runtime_put_sync(dc->dev); -} - -static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_crtc_state *old_state) -{ - struct drm_display_mode *mode = &crtc->state->adjusted_mode; - struct tegra_dc_state *state = to_dc_state(crtc->state); - struct tegra_dc *dc = to_tegra_dc(crtc); - u32 value; - - pm_runtime_get_sync(dc->dev); - - /* initialize display controller */ - if (dc->syncpt) { - u32 syncpt = host1x_syncpt_id(dc->syncpt); - - value = SYNCPT_CNTRL_NO_STALL; - tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); - - value = SYNCPT_VSYNC_ENABLE | syncpt; - tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); - } - - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | - WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; - tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); - - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | - WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; - tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); - - /* initialize timer */ - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | - WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); - tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); - - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | - WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); - tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); - - value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | - WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; - tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); - - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | - WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; - tegra_dc_writel(dc, value, DC_CMD_INT_MASK); - - if (dc->soc->supports_border_color) - tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); - - /* apply PLL and pixel clock changes */ - tegra_dc_commit_state(dc, state); - - /* program display mode */ - tegra_dc_set_timings(dc, mode); - - /* interlacing isn't supported yet, so disable it */ - if (dc->soc->supports_interlacing) { - value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); - value &= ~INTERLACE_ENABLE; - tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); - } - - value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); - value &= ~DISP_CTRL_MODE_MASK; - value |= DISP_CTRL_MODE_C_DISPLAY; - tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); - - value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); - value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | - PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; - tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); - - tegra_dc_commit(dc); - - drm_crtc_vblank_on(crtc); -} - -static int tegra_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_crtc_state *state) -{ - return 0; -} - -static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_crtc_state *old_crtc_state) -{ - struct tegra_dc *dc = to_tegra_dc(crtc); - - if (crtc->state->event) { - crtc->state->event->pipe = drm_crtc_index(crtc); - - WARN_ON(drm_crtc_vblank_get(crtc) != 0); - - dc->event = crtc->state->event; - crtc->state->event = NULL; - } -} - -static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_crtc_state *old_crtc_state) -{ - struct tegra_dc_state *state = to_dc_state(crtc->state); - struct tegra_dc *dc = to_tegra_dc(crtc); - - tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL); - tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL); -} - -static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { - .atomic_check = tegra_crtc_atomic_check, - .atomic_begin = tegra_crtc_atomic_begin, - .atomic_flush = tegra_crtc_atomic_flush, - .atomic_enable = tegra_crtc_atomic_enable, - .atomic_disable = tegra_crtc_atomic_disable, -}; - -static void tegra_dc_finish_page_flip(struct tegra_dc *dc) -{ - struct drm_device *drm = dc->base.dev; - struct drm_crtc *crtc = &dc->base; - unsigned long flags, base; - struct tegra_bo *bo; - - spin_lock_irqsave(&drm->event_lock, flags); - - if (!dc->event) { - spin_unlock_irqrestore(&drm->event_lock, flags); - return; - } - - bo = tegra_fb_get_plane(crtc->primary->fb, 0); - - spin_lock(&dc->lock); - - /* check if new start address has been latched */ - tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); - tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); - base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); - tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); - - spin_unlock(&dc->lock); - - if (base == bo->paddr + crtc->primary->fb->offsets[0]) { - drm_crtc_send_vblank_event(crtc, dc->event); - drm_crtc_vblank_put(crtc); - dc->event = NULL; - } - - spin_unlock_irqrestore(&drm->event_lock, flags); -} - -static irqreturn_t tegra_dc_irq(int irq, void *data) -{ - struct tegra_dc *dc = data; - unsigned long status; - - status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); - tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); - - if (status & FRAME_END_INT) { - /* - dev_dbg(dc->dev, "%s(): frame end\n", __func__); - */ - dc->stats.frames++; - } - - if (status & VBLANK_INT) { - /* - dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); - */ - drm_crtc_handle_vblank(&dc->base); - tegra_dc_finish_page_flip(dc); - dc->stats.vblank++; - } - - if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { - /* - dev_dbg(dc->dev, "%s(): underflow\n", __func__); - */ - dc->stats.underflow++; - } - - if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) { - /* - dev_dbg(dc->dev, "%s(): overflow\n", __func__); - */ - dc->stats.overflow++; - } - - return IRQ_HANDLED; -} - -#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } - -static const struct debugfs_reg32 tegra_dc_regs[] = { - DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT), - DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL), - DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR), - DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT), - DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL), - DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR), - DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT), - DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL), - DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR), - DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT), - DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL), - DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR), - DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC), - DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0), - DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND), - DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE), - DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL), - DEBUGFS_REG32(DC_CMD_INT_STATUS), - DEBUGFS_REG32(DC_CMD_INT_MASK), - DEBUGFS_REG32(DC_CMD_INT_ENABLE), - DEBUGFS_REG32(DC_CMD_INT_TYPE), - DEBUGFS_REG32(DC_CMD_INT_POLARITY), - DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1), - DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2), - DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3), - DEBUGFS_REG32(DC_CMD_STATE_ACCESS), - DEBUGFS_REG32(DC_CMD_STATE_CONTROL), - DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER), - DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL), - DEBUGFS_REG32(DC_COM_CRC_CONTROL), - DEBUGFS_REG32(DC_COM_CRC_CHECKSUM), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)), - DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)), - DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)), - DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)), - DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)), - DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)), - DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)), - DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)), - DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL), - DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL), - DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE), - DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL), - DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE), - DEBUGFS_REG32(DC_COM_SPI_CONTROL), - DEBUGFS_REG32(DC_COM_SPI_START_BYTE), - DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB), - DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD), - DEBUGFS_REG32(DC_COM_HSPI_CS_DC), - DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A), - DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B), - DEBUGFS_REG32(DC_COM_GPIO_CTRL), - DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER), - DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED), - DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0), - DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1), - DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS), - DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY), - DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER), - DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS), - DEBUGFS_REG32(DC_DISP_REF_TO_SYNC), - DEBUGFS_REG32(DC_DISP_SYNC_WIDTH), - DEBUGFS_REG32(DC_DISP_BACK_PORCH), - DEBUGFS_REG32(DC_DISP_ACTIVE), - DEBUGFS_REG32(DC_DISP_FRONT_PORCH), - DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL), - DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A), - DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B), - DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C), - DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D), - DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL), - DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A), - DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B), - DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C), - DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D), - DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL), - DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A), - DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B), - DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C), - DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D), - DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL), - DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A), - DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B), - DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C), - DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL), - DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A), - DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B), - DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C), - DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL), - DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A), - DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL), - DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A), - DEBUGFS_REG32(DC_DISP_M0_CONTROL), - DEBUGFS_REG32(DC_DISP_M1_CONTROL), - DEBUGFS_REG32(DC_DISP_DI_CONTROL), - DEBUGFS_REG32(DC_DISP_PP_CONTROL), - DEBUGFS_REG32(DC_DISP_PP_SELECT_A), - DEBUGFS_REG32(DC_DISP_PP_SELECT_B), - DEBUGFS_REG32(DC_DISP_PP_SELECT_C), - DEBUGFS_REG32(DC_DISP_PP_SELECT_D), - DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL), - DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL), - DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL), - DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS), - DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS), - DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS), - DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS), - DEBUGFS_REG32(DC_DISP_BORDER_COLOR), - DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER), - DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER), - DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER), - DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER), - DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND), - DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND), - DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR), - DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS), - DEBUGFS_REG32(DC_DISP_CURSOR_POSITION), - DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS), - DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL), - DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A), - DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B), - DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C), - DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D), - DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL), - DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST), - DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST), - DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST), - DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST), - DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL), - DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL), - DEBUGFS_REG32(DC_DISP_SD_CONTROL), - DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF), - DEBUGFS_REG32(DC_DISP_SD_LUT(0)), - DEBUGFS_REG32(DC_DISP_SD_LUT(1)), - DEBUGFS_REG32(DC_DISP_SD_LUT(2)), - DEBUGFS_REG32(DC_DISP_SD_LUT(3)), - DEBUGFS_REG32(DC_DISP_SD_LUT(4)), - DEBUGFS_REG32(DC_DISP_SD_LUT(5)), - DEBUGFS_REG32(DC_DISP_SD_LUT(6)), - DEBUGFS_REG32(DC_DISP_SD_LUT(7)), - DEBUGFS_REG32(DC_DISP_SD_LUT(8)), - DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL), - DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT), - DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)), - DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)), - DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)), - DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)), - DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)), - DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)), - DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)), - DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)), - DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)), - DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)), - DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)), - DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)), - DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL), - DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES), - DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES), - DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI), - DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL), - DEBUGFS_REG32(DC_WIN_WIN_OPTIONS), - DEBUGFS_REG32(DC_WIN_BYTE_SWAP), - DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL), - DEBUGFS_REG32(DC_WIN_COLOR_DEPTH), - DEBUGFS_REG32(DC_WIN_POSITION), - DEBUGFS_REG32(DC_WIN_SIZE), - DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE), - DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA), - DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA), - DEBUGFS_REG32(DC_WIN_DDA_INC), - DEBUGFS_REG32(DC_WIN_LINE_STRIDE), - DEBUGFS_REG32(DC_WIN_BUF_STRIDE), - DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE), - DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE), - DEBUGFS_REG32(DC_WIN_DV_CONTROL), - DEBUGFS_REG32(DC_WIN_BLEND_NOKEY), - DEBUGFS_REG32(DC_WIN_BLEND_1WIN), - DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X), - DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y), - DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY), - DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL), - DEBUGFS_REG32(DC_WINBUF_START_ADDR), - DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS), - DEBUGFS_REG32(DC_WINBUF_START_ADDR_U), - DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS), - DEBUGFS_REG32(DC_WINBUF_START_ADDR_V), - DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS), - DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET), - DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS), - DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET), - DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS), - DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS), - DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS), - DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS), - DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS), -}; - -static int tegra_dc_show_regs(struct seq_file *s, void *data) -{ - struct drm_info_node *node = s->private; - struct tegra_dc *dc = node->info_ent->data; - unsigned int i; - int err = 0; +{ + struct tegra_dc *dc = to_tegra_dc(crtc); + u32 value; - drm_modeset_lock(&dc->base.mutex, NULL); + if (!tegra_dc_idle(dc)) { + tegra_dc_stop(dc); - if (!dc->base.state->active) { - err = -EBUSY; - goto unlock; + /* + * Ignore the return value, there isn't anything useful to do + * in case this fails. + */ + tegra_dc_wait_idle(dc, 100); } - for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) { - unsigned int offset = tegra_dc_regs[i].offset; - - seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, - offset, tegra_dc_readl(dc, offset)); + /* + * This should really be part of the RGB encoder driver, but clearing + * these bits has the side-effect of stopping the display controller. + * When that happens no VBLANK interrupts will be raised. At the same + * time the encoder is disabled before the display controller, so the + * above code is always going to timeout waiting for the controller + * to go idle. + * + * Given the close coupling between the RGB encoder and the display + * controller doing it here is still kind of okay. None of the other + * encoder drivers require these bits to be cleared. + * + * XXX: Perhaps given that the display controller is switched off at + * this point anyway maybe clearing these bits isn't even useful for + * the RGB encoder? + */ + if (dc->rgb) { + value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); + value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | + PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); + tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); } -unlock: - drm_modeset_unlock(&dc->base.mutex); - return err; + tegra_dc_stats_reset(&dc->stats); + drm_crtc_vblank_off(crtc); + + pm_runtime_put_sync(dc->dev); } -static int tegra_dc_show_crc(struct seq_file *s, void *data) +static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, + struct drm_crtc_state *old_state) { - struct drm_info_node *node = s->private; - struct tegra_dc *dc = node->info_ent->data; - int err = 0; + struct drm_display_mode *mode = &crtc->state->adjusted_mode; + struct tegra_dc_state *state = to_dc_state(crtc->state); + struct tegra_dc *dc = to_tegra_dc(crtc); u32 value; - drm_modeset_lock(&dc->base.mutex, NULL); + pm_runtime_get_sync(dc->dev); - if (!dc->base.state->active) { - err = -EBUSY; - goto unlock; + /* initialize display controller */ + if (dc->syncpt) { + u32 syncpt = host1x_syncpt_id(dc->syncpt); + + value = SYNCPT_CNTRL_NO_STALL; + tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); + + value = SYNCPT_VSYNC_ENABLE | syncpt; + tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); } - value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE; - tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); - tegra_dc_commit(dc); + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | + WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); - drm_crtc_wait_one_vblank(&dc->base); - drm_crtc_wait_one_vblank(&dc->base); + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | + WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); - value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); - seq_printf(s, "%08x\n", value); + /* initialize timer */ + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | + WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); + tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); - tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | + WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); + tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); -unlock: - drm_modeset_unlock(&dc->base.mutex); - return err; + value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | + WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); + + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | + WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_MASK); + + if (dc->soc->supports_border_color) + tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); + + /* apply PLL and pixel clock changes */ + tegra_dc_commit_state(dc, state); + + /* program display mode */ + tegra_dc_set_timings(dc, mode); + + /* interlacing isn't supported yet, so disable it */ + if (dc->soc->supports_interlacing) { + value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); + value &= ~INTERLACE_ENABLE; + tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); + } + + value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); + value &= ~DISP_CTRL_MODE_MASK; + value |= DISP_CTRL_MODE_C_DISPLAY; + tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); + + value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); + value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | + PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; + tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); + + tegra_dc_commit(dc); + + drm_crtc_vblank_on(crtc); } -static int tegra_dc_show_stats(struct seq_file *s, void *data) +static int tegra_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) { - struct drm_info_node *node = s->private; - struct tegra_dc *dc = node->info_ent->data; + return 0; +} - seq_printf(s, "frames: %lu\n", dc->stats.frames); - seq_printf(s, "vblank: %lu\n", dc->stats.vblank); - seq_printf(s, "underflow: %lu\n", dc->stats.underflow); - seq_printf(s, "overflow: %lu\n", dc->stats.overflow); +static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, + struct drm_crtc_state *old_crtc_state) +{ + struct tegra_dc *dc = to_tegra_dc(crtc); - return 0; + if (crtc->state->event) { + crtc->state->event->pipe = drm_crtc_index(crtc); + + WARN_ON(drm_crtc_vblank_get(crtc) != 0); + + dc->event = crtc->state->event; + crtc->state->event = NULL; + } } -static struct drm_info_list debugfs_files[] = { - { "regs", tegra_dc_show_regs, 0, NULL }, - { "crc", tegra_dc_show_crc, 0, NULL }, - { "stats", tegra_dc_show_stats, 0, NULL }, +static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_crtc_state *old_crtc_state) +{ + struct tegra_dc_state *state = to_dc_state(crtc->state); + struct tegra_dc *dc = to_tegra_dc(crtc); + + tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL); + tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL); +} + +static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { + .atomic_check = tegra_crtc_atomic_check, + .atomic_begin = tegra_crtc_atomic_begin, + .atomic_flush = tegra_crtc_atomic_flush, + .atomic_enable = tegra_crtc_atomic_enable, + .atomic_disable = tegra_crtc_atomic_disable, }; -static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) +static void tegra_dc_finish_page_flip(struct tegra_dc *dc) { - unsigned int i; - char *name; - int err; - - name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); - dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); - kfree(name); + struct drm_device *drm = dc->base.dev; + struct drm_crtc *crtc = &dc->base; + unsigned long flags, base; + struct tegra_bo *bo; - if (!dc->debugfs) - return -ENOMEM; + spin_lock_irqsave(&drm->event_lock, flags); - dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), - GFP_KERNEL); - if (!dc->debugfs_files) { - err = -ENOMEM; - goto remove; + if (!dc->event) { + spin_unlock_irqrestore(&drm->event_lock, flags); + return; } - for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) - dc->debugfs_files[i].data = dc; + bo = tegra_fb_get_plane(crtc->primary->fb, 0); - err = drm_debugfs_create_files(dc->debugfs_files, - ARRAY_SIZE(debugfs_files), - dc->debugfs, minor); - if (err < 0) - goto free; + spin_lock(&dc->lock); - dc->minor = minor; + /* check if new start address has been latched */ + tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); + tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); + base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); + tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); - return 0; + spin_unlock(&dc->lock); -free: - kfree(dc->debugfs_files); - dc->debugfs_files = NULL; -remove: - debugfs_remove(dc->debugfs); - dc->debugfs = NULL; + if (base == bo->paddr + crtc->primary->fb->offsets[0]) { + drm_crtc_send_vblank_event(crtc, dc->event); + drm_crtc_vblank_put(crtc); + dc->event = NULL; + } - return err; + spin_unlock_irqrestore(&drm->event_lock, flags); } -static int tegra_dc_debugfs_exit(struct tegra_dc *dc) +static irqreturn_t tegra_dc_irq(int irq, void *data) { - drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), - dc->minor); - dc->minor = NULL; + struct tegra_dc *dc = data; + unsigned long status; - kfree(dc->debugfs_files); - dc->debugfs_files = NULL; + status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); + tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); + + if (status & FRAME_END_INT) { + /* + dev_dbg(dc->dev, "%s(): frame end\n", __func__); + */ + dc->stats.frames++; + } - debugfs_remove(dc->debugfs); - dc->debugfs = NULL; + if (status & VBLANK_INT) { + /* + dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); + */ + drm_crtc_handle_vblank(&dc->base); + tegra_dc_finish_page_flip(dc); + dc->stats.vblank++; + } - return 0; + if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { + /* + dev_dbg(dc->dev, "%s(): underflow\n", __func__); + */ + dc->stats.underflow++; + } + + if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) { + /* + dev_dbg(dc->dev, "%s(): overflow\n", __func__); + */ + dc->stats.overflow++; + } + + return IRQ_HANDLED; } static int tegra_dc_init(struct host1x_client *client) @@ -1797,12 +1781,6 @@ static int tegra_dc_init(struct host1x_client *client) if (err < 0) goto cleanup; - if (IS_ENABLED(CONFIG_DEBUG_FS)) { - err = tegra_dc_debugfs_init(dc, drm->primary); - if (err < 0) - dev_err(dc->dev, "debugfs setup failed: %d\n", err); - } - err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, dev_name(dc->dev), dc); if (err < 0) { @@ -1835,12 +1813,6 @@ static int tegra_dc_exit(struct host1x_client *client) devm_free_irq(dc->dev, dc->irq, dc); - if (IS_ENABLED(CONFIG_DEBUG_FS)) { - err = tegra_dc_debugfs_exit(dc); - if (err < 0) - dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); - } - err = tegra_dc_rgb_exit(dc); if (err) { dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index cb100b6e3282..032c734dd470 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -56,8 +56,6 @@ struct tegra_dc { struct list_head list; struct drm_info_list *debugfs_files; - struct drm_minor *minor; - struct dentry *debugfs; /* page-flip handling */ struct drm_pending_vblank_event *event; -- GitLab From a813d70425061ad59bc8f980ae822f4fc35c9250 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 8 Nov 2017 13:12:44 +0100 Subject: [PATCH 1357/2547] drm/tegra: dsi: Register debugfs in ->late_register() The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dsi.c | 58 ++++++++++++------------------------- 1 file changed, 18 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 4a78af08df82..4d2ed966f9e3 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -65,8 +65,6 @@ struct tegra_dsi { struct clk *clk; struct drm_info_list *debugfs_files; - struct drm_minor *minor; - struct dentry *debugfs; unsigned long flags; enum mipi_dsi_pixel_format format; @@ -230,58 +228,46 @@ static struct drm_info_list debugfs_files[] = { { "regs", tegra_dsi_show_regs, 0, NULL }, }; -static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi, - struct drm_minor *minor) +static int tegra_dsi_late_register(struct drm_connector *connector) { - const char *name = dev_name(dsi->dev); - unsigned int i; + struct tegra_output *output = connector_to_output(connector); + unsigned int i, count = ARRAY_SIZE(debugfs_files); + struct drm_minor *minor = connector->dev->primary; + struct dentry *root = connector->debugfs_entry; + struct tegra_dsi *dsi = to_dsi(output); int err; - dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root); - if (!dsi->debugfs) - return -ENOMEM; - dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), GFP_KERNEL); - if (!dsi->debugfs_files) { - err = -ENOMEM; - goto remove; - } + if (!dsi->debugfs_files) + return -ENOMEM; - for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) + for (i = 0; i < count; i++) dsi->debugfs_files[i].data = dsi; - err = drm_debugfs_create_files(dsi->debugfs_files, - ARRAY_SIZE(debugfs_files), - dsi->debugfs, minor); + err = drm_debugfs_create_files(dsi->debugfs_files, count, root, minor); if (err < 0) goto free; - dsi->minor = minor; - return 0; free: kfree(dsi->debugfs_files); dsi->debugfs_files = NULL; -remove: - debugfs_remove(dsi->debugfs); - dsi->debugfs = NULL; return err; } -static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi) +static void tegra_dsi_early_unregister(struct drm_connector *connector) { - drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files), - dsi->minor); - dsi->minor = NULL; + struct tegra_output *output = connector_to_output(connector); + unsigned int count = ARRAY_SIZE(debugfs_files); + struct tegra_dsi *dsi = to_dsi(output); + drm_debugfs_remove_files(dsi->debugfs_files, count, + connector->dev->primary); kfree(dsi->debugfs_files); dsi->debugfs_files = NULL; - - debugfs_remove(dsi->debugfs); - dsi->debugfs = NULL; } #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) @@ -823,6 +809,8 @@ static const struct drm_connector_funcs tegra_dsi_connector_funcs = { .destroy = tegra_output_connector_destroy, .atomic_duplicate_state = tegra_dsi_connector_duplicate_state, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, + .late_register = tegra_dsi_late_register, + .early_unregister = tegra_dsi_early_unregister, }; static enum drm_mode_status @@ -1076,12 +1064,6 @@ static int tegra_dsi_init(struct host1x_client *client) dsi->output.encoder.possible_crtcs = 0x3; } - if (IS_ENABLED(CONFIG_DEBUG_FS)) { - err = tegra_dsi_debugfs_init(dsi, drm->primary); - if (err < 0) - dev_err(dsi->dev, "debugfs setup failed: %d\n", err); - } - return 0; } @@ -1090,10 +1072,6 @@ static int tegra_dsi_exit(struct host1x_client *client) struct tegra_dsi *dsi = host1x_client_to_dsi(client); tegra_output_exit(&dsi->output); - - if (IS_ENABLED(CONFIG_DEBUG_FS)) - tegra_dsi_debugfs_exit(dsi); - regulator_disable(dsi->vdd); return 0; -- GitLab From 1d60047dd6fcd8bb840f3652ce25ab478a69c7ef Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 8 Nov 2017 13:18:31 +0100 Subject: [PATCH 1358/2547] drm/tegra: hdmi: Register debugfs in ->late_register() The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/hdmi.c | 510 +++++++++++++++++------------------ 1 file changed, 245 insertions(+), 265 deletions(-) diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index a68d80476e46..784739a9f497 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -79,8 +79,6 @@ struct tegra_hdmi { bool dvi; struct drm_info_list *debugfs_files; - struct drm_minor *minor; - struct dentry *debugfs; }; static inline struct tegra_hdmi * @@ -910,6 +908,249 @@ tegra_hdmi_connector_detect(struct drm_connector *connector, bool force) return status; } +#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } + +static const struct debugfs_reg32 tegra_hdmi_regs[] = { + DEBUGFS_REG32(HDMI_CTXSW), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N), + DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK), + DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL), + DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL), + DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH), + DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE), + DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK), + DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT), +}; + +static int tegra_hdmi_show_regs(struct seq_file *s, void *data) +{ + struct drm_info_node *node = s->private; + struct tegra_hdmi *hdmi = node->info_ent->data; + struct drm_crtc *crtc = hdmi->output.encoder.crtc; + struct drm_device *drm = node->minor->dev; + unsigned int i; + int err = 0; + + drm_modeset_lock_all(drm); + + if (!crtc || !crtc->state->active) { + err = -EBUSY; + goto unlock; + } + + for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) { + unsigned int offset = tegra_hdmi_regs[i].offset; + + seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name, + offset, tegra_hdmi_readl(hdmi, offset)); + } + +unlock: + drm_modeset_unlock_all(drm); + return err; +} + +static struct drm_info_list debugfs_files[] = { + { "regs", tegra_hdmi_show_regs, 0, NULL }, +}; + +static int tegra_hdmi_late_register(struct drm_connector *connector) +{ + struct tegra_output *output = connector_to_output(connector); + unsigned int i, count = ARRAY_SIZE(debugfs_files); + struct drm_minor *minor = connector->dev->primary; + struct dentry *root = connector->debugfs_entry; + struct tegra_hdmi *hdmi = to_hdmi(output); + int err; + + hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), + GFP_KERNEL); + if (!hdmi->debugfs_files) + return -ENOMEM; + + for (i = 0; i < count; i++) + hdmi->debugfs_files[i].data = hdmi; + + err = drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor); + if (err < 0) + goto free; + + return 0; + +free: + kfree(hdmi->debugfs_files); + hdmi->debugfs_files = NULL; + + return err; +} + +static void tegra_hdmi_early_unregister(struct drm_connector *connector) +{ + struct tegra_output *output = connector_to_output(connector); + struct drm_minor *minor = connector->dev->primary; + unsigned int count = ARRAY_SIZE(debugfs_files); + struct tegra_hdmi *hdmi = to_hdmi(output); + + drm_debugfs_remove_files(hdmi->debugfs_files, count, minor); + kfree(hdmi->debugfs_files); + hdmi->debugfs_files = NULL; +} + static const struct drm_connector_funcs tegra_hdmi_connector_funcs = { .reset = drm_atomic_helper_connector_reset, .detect = tegra_hdmi_connector_detect, @@ -917,6 +1158,8 @@ static const struct drm_connector_funcs tegra_hdmi_connector_funcs = { .destroy = tegra_output_connector_destroy, .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, + .late_register = tegra_hdmi_late_register, + .early_unregister = tegra_hdmi_early_unregister, }; static enum drm_mode_status @@ -1225,260 +1468,6 @@ static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = { .atomic_check = tegra_hdmi_encoder_atomic_check, }; -#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } - -static const struct debugfs_reg32 tegra_hdmi_regs[] = { - DEBUGFS_REG32(HDMI_CTXSW), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N), - DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK), - DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL), - DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL), - DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH), - DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE), - DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS), - DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK), - DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT), -}; - -static int tegra_hdmi_show_regs(struct seq_file *s, void *data) -{ - struct drm_info_node *node = s->private; - struct tegra_hdmi *hdmi = node->info_ent->data; - struct drm_crtc *crtc = hdmi->output.encoder.crtc; - struct drm_device *drm = node->minor->dev; - unsigned int i; - int err = 0; - - drm_modeset_lock_all(drm); - - if (!crtc || !crtc->state->active) { - err = -EBUSY; - goto unlock; - } - - for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) { - unsigned int offset = tegra_hdmi_regs[i].offset; - - seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name, - offset, tegra_hdmi_readl(hdmi, offset)); - } - -unlock: - drm_modeset_unlock_all(drm); - return err; -} - -static struct drm_info_list debugfs_files[] = { - { "regs", tegra_hdmi_show_regs, 0, NULL }, -}; - -static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi, - struct drm_minor *minor) -{ - unsigned int i; - int err; - - hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root); - if (!hdmi->debugfs) - return -ENOMEM; - - hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), - GFP_KERNEL); - if (!hdmi->debugfs_files) { - err = -ENOMEM; - goto remove; - } - - for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) - hdmi->debugfs_files[i].data = hdmi; - - err = drm_debugfs_create_files(hdmi->debugfs_files, - ARRAY_SIZE(debugfs_files), - hdmi->debugfs, minor); - if (err < 0) - goto free; - - hdmi->minor = minor; - - return 0; - -free: - kfree(hdmi->debugfs_files); - hdmi->debugfs_files = NULL; -remove: - debugfs_remove(hdmi->debugfs); - hdmi->debugfs = NULL; - - return err; -} - -static void tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi) -{ - drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files), - hdmi->minor); - hdmi->minor = NULL; - - kfree(hdmi->debugfs_files); - hdmi->debugfs_files = NULL; - - debugfs_remove(hdmi->debugfs); - hdmi->debugfs = NULL; -} - static int tegra_hdmi_init(struct host1x_client *client) { struct drm_device *drm = dev_get_drvdata(client->parent); @@ -1511,12 +1500,6 @@ static int tegra_hdmi_init(struct host1x_client *client) hdmi->output.encoder.possible_crtcs = 0x3; - if (IS_ENABLED(CONFIG_DEBUG_FS)) { - err = tegra_hdmi_debugfs_init(hdmi, drm->primary); - if (err < 0) - dev_err(client->dev, "debugfs setup failed: %d\n", err); - } - err = regulator_enable(hdmi->hdmi); if (err < 0) { dev_err(client->dev, "failed to enable HDMI regulator: %d\n", @@ -1549,9 +1532,6 @@ static int tegra_hdmi_exit(struct host1x_client *client) regulator_disable(hdmi->pll); regulator_disable(hdmi->hdmi); - if (IS_ENABLED(CONFIG_DEBUG_FS)) - tegra_hdmi_debugfs_exit(hdmi); - return 0; } -- GitLab From d92e600998d83569cc0955a63c5f036867336343 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 12 Oct 2017 19:07:54 +0200 Subject: [PATCH 1359/2547] drm/tegra: sor: Root debugfs files at the connector Rather create new files within the top-level DRM device's debugfs node, add the SOR specific files to the connector's debugfs node. This avoids the need to come up with subdirectory names and is also more intuitive. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 75b21dbaa8f0..f40fc987900c 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -184,7 +184,6 @@ struct tegra_sor { struct drm_info_list *debugfs_files; struct drm_minor *minor; - struct dentry *debugfs; const struct tegra_sor_ops *ops; @@ -1260,14 +1259,10 @@ static const struct drm_info_list debugfs_files[] = { static int tegra_sor_debugfs_init(struct tegra_sor *sor, struct drm_minor *minor) { - const char *name = sor->soc->supports_dp ? "sor1" : "sor"; + struct dentry *root = sor->output.connector.debugfs_entry; unsigned int i; int err; - sor->debugfs = debugfs_create_dir(name, minor->debugfs_root); - if (!sor->debugfs) - return -ENOMEM; - sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), GFP_KERNEL); if (!sor->debugfs_files) { @@ -1280,7 +1275,7 @@ static int tegra_sor_debugfs_init(struct tegra_sor *sor, err = drm_debugfs_create_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files), - sor->debugfs, minor); + root, minor); if (err < 0) goto free; @@ -1292,13 +1287,14 @@ static int tegra_sor_debugfs_init(struct tegra_sor *sor, kfree(sor->debugfs_files); sor->debugfs_files = NULL; remove: - debugfs_remove_recursive(sor->debugfs); - sor->debugfs = NULL; + debugfs_remove_recursive(root); return err; } static void tegra_sor_debugfs_exit(struct tegra_sor *sor) { + struct dentry *root = sor->output.connector.debugfs_entry; + drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files), sor->minor); sor->minor = NULL; @@ -1306,8 +1302,7 @@ static void tegra_sor_debugfs_exit(struct tegra_sor *sor) kfree(sor->debugfs_files); sor->debugfs_files = NULL; - debugfs_remove_recursive(sor->debugfs); - sor->debugfs = NULL; + debugfs_remove_recursive(root); } static void tegra_sor_connector_reset(struct drm_connector *connector) -- GitLab From 5b8e043b6df4caf4aa41921ed584659a0c5ad269 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 8 Nov 2017 13:20:01 +0100 Subject: [PATCH 1360/2547] drm/tegra: sor: Register debugfs in ->late_register() The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 53 +++++++++++++------------------------ 1 file changed, 19 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index f40fc987900c..2fba6c2bd486 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -183,7 +183,6 @@ struct tegra_sor { struct drm_dp_aux *aux; struct drm_info_list *debugfs_files; - struct drm_minor *minor; const struct tegra_sor_ops *ops; @@ -1256,53 +1255,46 @@ static const struct drm_info_list debugfs_files[] = { { "regs", tegra_sor_show_regs, 0, NULL }, }; -static int tegra_sor_debugfs_init(struct tegra_sor *sor, - struct drm_minor *minor) +static int tegra_sor_late_register(struct drm_connector *connector) { - struct dentry *root = sor->output.connector.debugfs_entry; - unsigned int i; + struct tegra_output *output = connector_to_output(connector); + unsigned int i, count = ARRAY_SIZE(debugfs_files); + struct drm_minor *minor = connector->dev->primary; + struct dentry *root = connector->debugfs_entry; + struct tegra_sor *sor = to_sor(output); int err; sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), GFP_KERNEL); - if (!sor->debugfs_files) { - err = -ENOMEM; - goto remove; - } + if (!sor->debugfs_files) + return -ENOMEM; - for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) + for (i = 0; i < count; i++) sor->debugfs_files[i].data = sor; - err = drm_debugfs_create_files(sor->debugfs_files, - ARRAY_SIZE(debugfs_files), - root, minor); + err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor); if (err < 0) goto free; - sor->minor = minor; - return 0; free: kfree(sor->debugfs_files); sor->debugfs_files = NULL; -remove: - debugfs_remove_recursive(root); + return err; } -static void tegra_sor_debugfs_exit(struct tegra_sor *sor) +static void tegra_sor_early_unregister(struct drm_connector *connector) { - struct dentry *root = sor->output.connector.debugfs_entry; - - drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files), - sor->minor); - sor->minor = NULL; + struct tegra_output *output = connector_to_output(connector); + unsigned int count = ARRAY_SIZE(debugfs_files); + struct tegra_sor *sor = to_sor(output); + drm_debugfs_remove_files(sor->debugfs_files, count, + connector->dev->primary); kfree(sor->debugfs_files); sor->debugfs_files = NULL; - - debugfs_remove_recursive(root); } static void tegra_sor_connector_reset(struct drm_connector *connector) @@ -1355,6 +1347,8 @@ static const struct drm_connector_funcs tegra_sor_connector_funcs = { .destroy = tegra_output_connector_destroy, .atomic_duplicate_state = tegra_sor_connector_duplicate_state, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, + .late_register = tegra_sor_late_register, + .early_unregister = tegra_sor_early_unregister, }; static int tegra_sor_connector_get_modes(struct drm_connector *connector) @@ -2347,12 +2341,6 @@ static int tegra_sor_init(struct host1x_client *client) sor->output.encoder.possible_crtcs = 0x3; - if (IS_ENABLED(CONFIG_DEBUG_FS)) { - err = tegra_sor_debugfs_init(sor, drm->primary); - if (err < 0) - dev_err(sor->dev, "debugfs setup failed: %d\n", err); - } - if (sor->aux) { err = drm_dp_aux_attach(sor->aux, &sor->output); if (err < 0) { @@ -2421,9 +2409,6 @@ static int tegra_sor_exit(struct host1x_client *client) clk_disable_unprepare(sor->clk_dp); clk_disable_unprepare(sor->clk); - if (IS_ENABLED(CONFIG_DEBUG_FS)) - tegra_sor_debugfs_exit(sor); - return 0; } -- GitLab From 67485fb8b89389f4475af0596d33bd5c11896522 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 9 Nov 2017 13:17:11 +0100 Subject: [PATCH 1361/2547] drm/tegra: Do not wrap lines unnecessarily The tegra_drm_alloc() function signature fits on a single line, no need to wrap it. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/drm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 52552b9b89ef..de1d122ba820 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -1148,8 +1148,7 @@ int tegra_drm_unregister_client(struct tegra_drm *tegra, return 0; } -void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, - dma_addr_t *dma) +void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma) { struct iova *alloc; void *virt; -- GitLab From 9b49f674eb205f9a01638ffc4b6add49741955ad Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 8 Nov 2017 13:22:17 +0100 Subject: [PATCH 1362/2547] drm/tegra: vic: Properly align arguments Properly align function arguments on subsequent lines with the first argument on the first line. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/vic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c index 18024183aa2b..d9664a34fb43 100644 --- a/drivers/gpu/drm/tegra/vic.c +++ b/drivers/gpu/drm/tegra/vic.c @@ -115,7 +115,7 @@ static int vic_boot(struct vic *vic) } static void *vic_falcon_alloc(struct falcon *falcon, size_t size, - dma_addr_t *iova) + dma_addr_t *iova) { struct tegra_drm *tegra = falcon->data; -- GitLab From 7116e9a8022cd468a6a952e1d0d662da73f75ce5 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Nov 2017 11:20:48 +0100 Subject: [PATCH 1363/2547] drm/tegra: dc: Support background color Starting with Tegra124, the interface to set the background color (the value generated for pixels that are not sourced from any window) is via a different register. Earlier generations called this the border color. Reverse the feature flag and assume that IP revisions that don't have support for background color will support border color instead. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 14 ++++++++------ drivers/gpu/drm/tegra/dc.h | 8 +++++++- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 29777604df39..6cee248601a9 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1572,7 +1572,9 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; tegra_dc_writel(dc, value, DC_CMD_INT_MASK); - if (dc->soc->supports_border_color) + if (dc->soc->supports_background_color) + tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); + else tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); /* apply PLL and pixel clock changes */ @@ -1835,7 +1837,7 @@ static const struct host1x_client_ops dc_client_ops = { }; static const struct tegra_dc_soc_info tegra20_dc_soc_info = { - .supports_border_color = true, + .supports_background_color = false, .supports_interlacing = false, .supports_cursor = false, .supports_block_linear = false, @@ -1845,7 +1847,7 @@ static const struct tegra_dc_soc_info tegra20_dc_soc_info = { }; static const struct tegra_dc_soc_info tegra30_dc_soc_info = { - .supports_border_color = true, + .supports_background_color = false, .supports_interlacing = false, .supports_cursor = false, .supports_block_linear = false, @@ -1855,7 +1857,7 @@ static const struct tegra_dc_soc_info tegra30_dc_soc_info = { }; static const struct tegra_dc_soc_info tegra114_dc_soc_info = { - .supports_border_color = true, + .supports_background_color = false, .supports_interlacing = false, .supports_cursor = false, .supports_block_linear = false, @@ -1865,7 +1867,7 @@ static const struct tegra_dc_soc_info tegra114_dc_soc_info = { }; static const struct tegra_dc_soc_info tegra124_dc_soc_info = { - .supports_border_color = false, + .supports_background_color = true, .supports_interlacing = true, .supports_cursor = true, .supports_block_linear = true, @@ -1875,7 +1877,7 @@ static const struct tegra_dc_soc_info tegra124_dc_soc_info = { }; static const struct tegra_dc_soc_info tegra210_dc_soc_info = { - .supports_border_color = false, + .supports_background_color = true, .supports_interlacing = true, .supports_cursor = true, .supports_block_linear = true, diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 032c734dd470..571a6c78619f 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -26,7 +26,7 @@ struct tegra_dc_stats { }; struct tegra_dc_soc_info { - bool supports_border_color; + bool supports_background_color; bool supports_interlacing; bool supports_cursor; bool supports_block_linear; @@ -447,6 +447,12 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DC_DISP_SD_HW_K_VALUES 0x4dd #define DC_DISP_SD_MAN_K_VALUES 0x4de +#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4 +#define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24) +#define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16) +#define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8) +#define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0) + #define DC_DISP_INTERLACE_CONTROL 0x4e5 #define INTERLACE_STATUS (1 << 2) #define INTERLACE_START (1 << 1) -- GitLab From 31b02caea3b30b044fe39301aad34886f7fd2556 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 12 Oct 2017 17:40:46 +0200 Subject: [PATCH 1364/2547] drm/tegra: Use atomic commit helpers There's no reason not to use them, and they already get all the semantics right, so rip out all of the custom code and replace it by the helpers. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 27 +++++----- drivers/gpu/drm/tegra/dc.h | 2 + drivers/gpu/drm/tegra/drm.c | 99 ++++--------------------------------- drivers/gpu/drm/tegra/drm.h | 6 --- 4 files changed, 27 insertions(+), 107 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 6cee248601a9..b6aa669a7cd8 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1648,8 +1648,8 @@ static void tegra_dc_finish_page_flip(struct tegra_dc *dc) { struct drm_device *drm = dc->base.dev; struct drm_crtc *crtc = &dc->base; - unsigned long flags, base; - struct tegra_bo *bo; + u64 base = 0, phys = 0; + unsigned long flags; spin_lock_irqsave(&drm->event_lock, flags); @@ -1658,19 +1658,24 @@ static void tegra_dc_finish_page_flip(struct tegra_dc *dc) return; } - bo = tegra_fb_get_plane(crtc->primary->fb, 0); + if (crtc->primary->fb) { + struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0); - spin_lock(&dc->lock); + phys = bo->paddr + crtc->primary->fb->offsets[0]; - /* check if new start address has been latched */ - tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); - tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); - base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); - tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); + spin_lock(&dc->lock); - spin_unlock(&dc->lock); + /* check if new start address has been latched */ + tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); + tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); + base = (u64)tegra_dc_readl(dc, DC_WINBUF_START_ADDR_HI) << 32; + base |= tegra_dc_readl(dc, DC_WINBUF_START_ADDR); + tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); + + spin_unlock(&dc->lock); + } - if (base == bo->paddr + crtc->primary->fb->offsets[0]) { + if (base == phys) { drm_crtc_send_vblank_event(crtc, dc->event); drm_crtc_vblank_put(crtc); dc->event = NULL; diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 571a6c78619f..581818064b4f 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -579,6 +579,8 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0) #define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4) +#define DC_WINBUF_START_ADDR_HI 0x80d + #define DC_WINBUF_AD_UFLOW_STATUS 0xbca #define DC_WINBUF_BD_UFLOW_STATUS 0xdca #define DC_WINBUF_CD_UFLOW_STATUS 0xfca diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index de1d122ba820..90d876fc6ea7 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -33,97 +33,18 @@ struct tegra_drm_file { struct mutex lock; }; -static void tegra_atomic_schedule(struct tegra_drm *tegra, - struct drm_atomic_state *state) -{ - tegra->commit.state = state; - schedule_work(&tegra->commit.work); -} - -static void tegra_atomic_complete(struct tegra_drm *tegra, - struct drm_atomic_state *state) -{ - struct drm_device *drm = tegra->drm; - - /* - * Everything below can be run asynchronously without the need to grab - * any modeset locks at all under one condition: It must be guaranteed - * that the asynchronous work has either been cancelled (if the driver - * supports it, which at least requires that the framebuffers get - * cleaned up with drm_atomic_helper_cleanup_planes()) or completed - * before the new state gets committed on the software side with - * drm_atomic_helper_swap_state(). - * - * This scheme allows new atomic state updates to be prepared and - * checked in parallel to the asynchronous completion of the previous - * update. Which is important since compositors need to figure out the - * composition of the next frame right after having submitted the - * current layout. - */ - - drm_atomic_helper_commit_modeset_disables(drm, state); - drm_atomic_helper_commit_modeset_enables(drm, state); - drm_atomic_helper_commit_planes(drm, state, - DRM_PLANE_COMMIT_ACTIVE_ONLY); - - drm_atomic_helper_wait_for_vblanks(drm, state); - - drm_atomic_helper_cleanup_planes(drm, state); - drm_atomic_state_put(state); -} - -static void tegra_atomic_work(struct work_struct *work) -{ - struct tegra_drm *tegra = container_of(work, struct tegra_drm, - commit.work); - - tegra_atomic_complete(tegra, tegra->commit.state); -} - -static int tegra_atomic_commit(struct drm_device *drm, - struct drm_atomic_state *state, bool nonblock) -{ - struct tegra_drm *tegra = drm->dev_private; - int err; - - err = drm_atomic_helper_prepare_planes(drm, state); - if (err) - return err; - - /* serialize outstanding nonblocking commits */ - mutex_lock(&tegra->commit.lock); - flush_work(&tegra->commit.work); - - /* - * This is the point of no return - everything below never fails except - * when the hw goes bonghits. Which means we can commit the new state on - * the software side now. - */ - - err = drm_atomic_helper_swap_state(state, true); - if (err) { - mutex_unlock(&tegra->commit.lock); - drm_atomic_helper_cleanup_planes(drm, state); - return err; - } - - drm_atomic_state_get(state); - if (nonblock) - tegra_atomic_schedule(tegra, state); - else - tegra_atomic_complete(tegra, state); - - mutex_unlock(&tegra->commit.lock); - return 0; -} - -static const struct drm_mode_config_funcs tegra_drm_mode_funcs = { +static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { .fb_create = tegra_fb_create, #ifdef CONFIG_DRM_FBDEV_EMULATION .output_poll_changed = tegra_fb_output_poll_changed, #endif .atomic_check = drm_atomic_helper_check, - .atomic_commit = tegra_atomic_commit, + .atomic_commit = drm_atomic_helper_commit, +}; + +static const struct drm_mode_config_helper_funcs +tegra_drm_mode_config_helpers = { + .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, }; static int tegra_drm_load(struct drm_device *drm, unsigned long flags) @@ -172,9 +93,6 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags) mutex_init(&tegra->clients_lock); INIT_LIST_HEAD(&tegra->clients); - mutex_init(&tegra->commit.lock); - INIT_WORK(&tegra->commit.work, tegra_atomic_work); - drm->dev_private = tegra; tegra->drm = drm; @@ -188,7 +106,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags) drm->mode_config.allow_fb_modifiers = true; - drm->mode_config.funcs = &tegra_drm_mode_funcs; + drm->mode_config.funcs = &tegra_drm_mode_config_funcs; + drm->mode_config.helper_private = &tegra_drm_mode_config_helpers; err = tegra_drm_fb_prepare(drm); if (err < 0) diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index ddae331ad8b6..a3d84c4af357 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -62,12 +62,6 @@ struct tegra_drm { unsigned int pitch_align; - struct { - struct drm_atomic_state *state; - struct work_struct work; - struct mutex lock; - } commit; - struct drm_atomic_state *state; }; -- GitLab From 9d99ab6e5fe27980a2a7cdd1957993099727530f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 12 Oct 2017 17:40:46 +0200 Subject: [PATCH 1365/2547] drm/tegra: Remove custom page-flip handler Tegra display hardware has GO bits and meets all the requirements to use drm_crtc_arm_vblank_event(). Use it instead and get rid of the hand- rolled implementation. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 62 +++++++++++--------------------------- drivers/gpu/drm/tegra/dc.h | 3 -- 2 files changed, 17 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index b6aa669a7cd8..05442d78e13d 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1523,6 +1523,15 @@ static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, tegra_dc_stats_reset(&dc->stats); drm_crtc_vblank_off(crtc); + spin_lock_irq(&crtc->dev->event_lock); + + if (crtc->state->event) { + drm_crtc_send_vblank_event(crtc, crtc->state->event); + crtc->state->event = NULL; + } + + spin_unlock_irq(&crtc->dev->event_lock); + pm_runtime_put_sync(dc->dev); } @@ -1614,14 +1623,18 @@ static int tegra_crtc_atomic_check(struct drm_crtc *crtc, static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { - struct tegra_dc *dc = to_tegra_dc(crtc); + unsigned long flags; if (crtc->state->event) { - crtc->state->event->pipe = drm_crtc_index(crtc); + spin_lock_irqsave(&crtc->dev->event_lock, flags); + + if (drm_crtc_vblank_get(crtc) != 0) + drm_crtc_send_vblank_event(crtc, crtc->state->event); + else + drm_crtc_arm_vblank_event(crtc, crtc->state->event); - WARN_ON(drm_crtc_vblank_get(crtc) != 0); + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - dc->event = crtc->state->event; crtc->state->event = NULL; } } @@ -1644,46 +1657,6 @@ static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { .atomic_disable = tegra_crtc_atomic_disable, }; -static void tegra_dc_finish_page_flip(struct tegra_dc *dc) -{ - struct drm_device *drm = dc->base.dev; - struct drm_crtc *crtc = &dc->base; - u64 base = 0, phys = 0; - unsigned long flags; - - spin_lock_irqsave(&drm->event_lock, flags); - - if (!dc->event) { - spin_unlock_irqrestore(&drm->event_lock, flags); - return; - } - - if (crtc->primary->fb) { - struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0); - - phys = bo->paddr + crtc->primary->fb->offsets[0]; - - spin_lock(&dc->lock); - - /* check if new start address has been latched */ - tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); - tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); - base = (u64)tegra_dc_readl(dc, DC_WINBUF_START_ADDR_HI) << 32; - base |= tegra_dc_readl(dc, DC_WINBUF_START_ADDR); - tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); - - spin_unlock(&dc->lock); - } - - if (base == phys) { - drm_crtc_send_vblank_event(crtc, dc->event); - drm_crtc_vblank_put(crtc); - dc->event = NULL; - } - - spin_unlock_irqrestore(&drm->event_lock, flags); -} - static irqreturn_t tegra_dc_irq(int irq, void *data) { struct tegra_dc *dc = data; @@ -1704,7 +1677,6 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); */ drm_crtc_handle_vblank(&dc->base); - tegra_dc_finish_page_flip(dc); dc->stats.vblank++; } diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 581818064b4f..6e46e4aed10b 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -57,9 +57,6 @@ struct tegra_dc { struct drm_info_list *debugfs_files; - /* page-flip handling */ - struct drm_pending_vblank_event *event; - const struct tegra_dc_soc_info *soc; struct iommu_domain *domain; -- GitLab From 6f70ec54e1c11b916c16ec3caa71e4ed2c248aa3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 30 Aug 2017 18:02:51 +0200 Subject: [PATCH 1366/2547] drm/tegra: dc: Remove tegra_primary_plane_destroy() This function is a simple wrapper around tegra_plane_destroy(), so it can be dropped. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 05442d78e13d..bcdcba78491b 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -417,11 +417,6 @@ static const u32 tegra_primary_plane_formats[] = { DRM_FORMAT_RGB565, }; -static void tegra_primary_plane_destroy(struct drm_plane *plane) -{ - tegra_plane_destroy(plane); -} - static void tegra_plane_reset(struct drm_plane *plane) { struct tegra_plane_state *state; @@ -466,7 +461,7 @@ static void tegra_plane_atomic_destroy_state(struct drm_plane *plane, static const struct drm_plane_funcs tegra_primary_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, - .destroy = tegra_primary_plane_destroy, + .destroy = tegra_plane_destroy, .reset = tegra_plane_reset, .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, .atomic_destroy_state = tegra_plane_atomic_destroy_state, -- GitLab From c1cb4b6171aeaee06a8d70e93ef57f7923f50010 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 30 Aug 2017 18:04:12 +0200 Subject: [PATCH 1367/2547] drm/tegra: dc: Remove duplicate plane funcs Both tegra_primary_plane_funcs and tegra_cursor_plane_funcs are identical. Get rid of the duplicate and use one set of function pointers for all planes. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index bcdcba78491b..a3f2924824dc 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -458,7 +458,7 @@ static void tegra_plane_atomic_destroy_state(struct drm_plane *plane, kfree(state); } -static const struct drm_plane_funcs tegra_primary_plane_funcs = { +static const struct drm_plane_funcs tegra_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, .destroy = tegra_plane_destroy, @@ -655,7 +655,7 @@ static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, formats = tegra_primary_plane_formats; err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, - &tegra_primary_plane_funcs, formats, + &tegra_plane_funcs, formats, num_formats, NULL, DRM_PLANE_TYPE_PRIMARY, NULL); if (err < 0) { @@ -781,15 +781,6 @@ static void tegra_cursor_atomic_disable(struct drm_plane *plane, tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); } -static const struct drm_plane_funcs tegra_cursor_plane_funcs = { - .update_plane = drm_atomic_helper_update_plane, - .disable_plane = drm_atomic_helper_disable_plane, - .destroy = tegra_plane_destroy, - .reset = tegra_plane_reset, - .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, - .atomic_destroy_state = tegra_plane_atomic_destroy_state, -}; - static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { .atomic_check = tegra_cursor_atomic_check, .atomic_update = tegra_cursor_atomic_update, @@ -821,7 +812,7 @@ static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, formats = tegra_cursor_plane_formats; err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, - &tegra_cursor_plane_funcs, formats, + &tegra_plane_funcs, formats, num_formats, NULL, DRM_PLANE_TYPE_CURSOR, NULL); if (err < 0) { -- GitLab From b652ab1db477f8556c098adb2e5951f36ce1f0c4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 30 Aug 2017 18:02:51 +0200 Subject: [PATCH 1368/2547] drm/tegra: dc: Remove tegra_overlay_plane_destroy() This function is a simple wrapper around tegra_plane_destroy(), so it can be dropped. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index a3f2924824dc..e60f44a186bb 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -825,15 +825,10 @@ static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, return &plane->base; } -static void tegra_overlay_plane_destroy(struct drm_plane *plane) -{ - tegra_plane_destroy(plane); -} - static const struct drm_plane_funcs tegra_overlay_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, - .destroy = tegra_overlay_plane_destroy, + .destroy = tegra_plane_destroy, .reset = tegra_plane_reset, .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, .atomic_destroy_state = tegra_plane_atomic_destroy_state, -- GitLab From 301e0ddb3458255ed0fb3bb1f46b9caf186eafb5 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 30 Aug 2017 18:04:12 +0200 Subject: [PATCH 1369/2547] drm/tegra: dc: Remove duplicate plane funcs Both tegra_overlay_plane_funcs is identical to tegra_plane_funcs. Get rid of the duplicate and use one set of function pointers for all planes. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index e60f44a186bb..775e51c7a5c0 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -825,15 +825,6 @@ static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, return &plane->base; } -static const struct drm_plane_funcs tegra_overlay_plane_funcs = { - .update_plane = drm_atomic_helper_update_plane, - .disable_plane = drm_atomic_helper_disable_plane, - .destroy = tegra_plane_destroy, - .reset = tegra_plane_reset, - .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, - .atomic_destroy_state = tegra_plane_atomic_destroy_state, -}; - static const uint32_t tegra_overlay_plane_formats[] = { DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888, @@ -863,7 +854,7 @@ static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, formats = tegra_overlay_plane_formats; err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, - &tegra_overlay_plane_funcs, formats, + &tegra_plane_funcs, formats, num_formats, NULL, DRM_PLANE_TYPE_OVERLAY, NULL); if (err < 0) { -- GitLab From b1415ff21d43e264b32c18faf1c7ae7e53bc235e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Nov 2017 16:00:05 +0100 Subject: [PATCH 1370/2547] drm/tegra: dc: Move state definition to header Move the display controller state definition to the header file so that it can be referenced by other files. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 18 ------------------ drivers/gpu/drm/tegra/dc.h | 18 ++++++++++++++++++ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 775e51c7a5c0..7b017c03feb3 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -34,24 +34,6 @@ static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) return container_of(plane, struct tegra_plane, base); } -struct tegra_dc_state { - struct drm_crtc_state base; - - struct clk *clk; - unsigned long pclk; - unsigned int div; - - u32 planes; -}; - -static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) -{ - if (state) - return container_of(state, struct tegra_dc_state, base); - - return NULL; -} - struct tegra_plane_state { struct drm_plane_state base; diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 6e46e4aed10b..b65dfbb0af89 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -18,6 +18,24 @@ struct tegra_output; +struct tegra_dc_state { + struct drm_crtc_state base; + + struct clk *clk; + unsigned long pclk; + unsigned int div; + + u32 planes; +}; + +static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) +{ + if (state) + return container_of(state, struct tegra_dc_state, base); + + return NULL; +} + struct tegra_dc_stats { unsigned long frames; unsigned long vblank; -- GitLab From 5acd351427361131c583dfb11c7bf4c364c98a9b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Nov 2017 15:27:25 +0100 Subject: [PATCH 1371/2547] drm/tegra: Move common plane code to separate file Subsequent patches will add support for Tegra186 which has a different architecture and needs different plane code but which can share a lot of code with earlier Tegra support. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/Makefile | 1 + drivers/gpu/drm/tegra/dc.c | 199 +-------------------------------- drivers/gpu/drm/tegra/plane.c | 180 +++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/plane.h | 59 ++++++++++ 4 files changed, 245 insertions(+), 194 deletions(-) create mode 100644 drivers/gpu/drm/tegra/plane.c create mode 100644 drivers/gpu/drm/tegra/plane.h diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile index 46d65d39214d..a47784765217 100644 --- a/drivers/gpu/drm/tegra/Makefile +++ b/drivers/gpu/drm/tegra/Makefile @@ -5,6 +5,7 @@ tegra-drm-y := \ drm.o \ gem.o \ fb.o \ + plane.o \ dc.o \ output.o \ rgb.o \ diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 7b017c03feb3..3aa0da6244db 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -19,38 +19,12 @@ #include "dc.h" #include "drm.h" #include "gem.h" +#include "plane.h" #include #include #include -struct tegra_plane { - struct drm_plane base; - unsigned int index; -}; - -static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) -{ - return container_of(plane, struct tegra_plane, base); -} - -struct tegra_plane_state { - struct drm_plane_state base; - - struct tegra_bo_tiling tiling; - u32 format; - u32 swap; -}; - -static inline struct tegra_plane_state * -to_tegra_plane_state(struct drm_plane_state *state) -{ - if (state) - return container_of(state, struct tegra_plane_state, base); - - return NULL; -} - static void tegra_dc_stats_reset(struct tegra_dc_stats *stats) { stats->frames = 0; @@ -97,81 +71,6 @@ void tegra_dc_commit(struct tegra_dc *dc) tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); } -static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap) -{ - /* assume no swapping of fetched data */ - if (swap) - *swap = BYTE_SWAP_NOSWAP; - - switch (fourcc) { - case DRM_FORMAT_XBGR8888: - *format = WIN_COLOR_DEPTH_R8G8B8A8; - break; - - case DRM_FORMAT_XRGB8888: - *format = WIN_COLOR_DEPTH_B8G8R8A8; - break; - - case DRM_FORMAT_RGB565: - *format = WIN_COLOR_DEPTH_B5G6R5; - break; - - case DRM_FORMAT_UYVY: - *format = WIN_COLOR_DEPTH_YCbCr422; - break; - - case DRM_FORMAT_YUYV: - if (swap) - *swap = BYTE_SWAP_SWAP2; - - *format = WIN_COLOR_DEPTH_YCbCr422; - break; - - case DRM_FORMAT_YUV420: - *format = WIN_COLOR_DEPTH_YCbCr420P; - break; - - case DRM_FORMAT_YUV422: - *format = WIN_COLOR_DEPTH_YCbCr422P; - break; - - default: - return -EINVAL; - } - - return 0; -} - -static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar) -{ - switch (format) { - case WIN_COLOR_DEPTH_YCbCr422: - case WIN_COLOR_DEPTH_YUV422: - if (planar) - *planar = false; - - return true; - - case WIN_COLOR_DEPTH_YCbCr420P: - case WIN_COLOR_DEPTH_YUV420P: - case WIN_COLOR_DEPTH_YCbCr422P: - case WIN_COLOR_DEPTH_YUV422P: - case WIN_COLOR_DEPTH_YCbCr422R: - case WIN_COLOR_DEPTH_YUV422R: - case WIN_COLOR_DEPTH_YCbCr422RA: - case WIN_COLOR_DEPTH_YUV422RA: - if (planar) - *planar = true; - - return true; - } - - if (planar) - *planar = false; - - return false; -} - static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, unsigned int bpp) { @@ -223,7 +122,7 @@ static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, * For YUV planar modes, the number of bytes per pixel takes into * account only the luma component and therefore is 1. */ - yuv = tegra_dc_format_is_yuv(window->format, &planar); + yuv = tegra_plane_format_is_yuv(window->format, &planar); if (!yuv) bpp = window->bits_per_pixel / 8; else @@ -385,101 +284,12 @@ static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, spin_unlock_irqrestore(&dc->lock, flags); } -static void tegra_plane_destroy(struct drm_plane *plane) -{ - struct tegra_plane *p = to_tegra_plane(plane); - - drm_plane_cleanup(plane); - kfree(p); -} - static const u32 tegra_primary_plane_formats[] = { DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, }; -static void tegra_plane_reset(struct drm_plane *plane) -{ - struct tegra_plane_state *state; - - if (plane->state) - __drm_atomic_helper_plane_destroy_state(plane->state); - - kfree(plane->state); - plane->state = NULL; - - state = kzalloc(sizeof(*state), GFP_KERNEL); - if (state) { - plane->state = &state->base; - plane->state->plane = plane; - } -} - -static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane) -{ - struct tegra_plane_state *state = to_tegra_plane_state(plane->state); - struct tegra_plane_state *copy; - - copy = kmalloc(sizeof(*copy), GFP_KERNEL); - if (!copy) - return NULL; - - __drm_atomic_helper_plane_duplicate_state(plane, ©->base); - copy->tiling = state->tiling; - copy->format = state->format; - copy->swap = state->swap; - - return ©->base; -} - -static void tegra_plane_atomic_destroy_state(struct drm_plane *plane, - struct drm_plane_state *state) -{ - __drm_atomic_helper_plane_destroy_state(state); - kfree(state); -} - -static const struct drm_plane_funcs tegra_plane_funcs = { - .update_plane = drm_atomic_helper_update_plane, - .disable_plane = drm_atomic_helper_disable_plane, - .destroy = tegra_plane_destroy, - .reset = tegra_plane_reset, - .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, - .atomic_destroy_state = tegra_plane_atomic_destroy_state, -}; - -static int tegra_plane_state_add(struct tegra_plane *plane, - struct drm_plane_state *state) -{ - struct drm_crtc_state *crtc_state; - struct tegra_dc_state *tegra; - struct drm_rect clip; - int err; - - /* Propagate errors from allocation or locking failures. */ - crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); - if (IS_ERR(crtc_state)) - return PTR_ERR(crtc_state); - - clip.x1 = 0; - clip.y1 = 0; - clip.x2 = crtc_state->mode.hdisplay; - clip.y2 = crtc_state->mode.vdisplay; - - /* Check plane state for visibility and calculate clipping bounds */ - err = drm_atomic_helper_check_plane_state(state, crtc_state, &clip, - 0, INT_MAX, true, true); - if (err < 0) - return err; - - tegra = to_dc_state(crtc_state); - - tegra->planes |= WIN_A_ACT_REQ << plane->index; - - return 0; -} - static int tegra_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { @@ -493,8 +303,9 @@ static int tegra_plane_atomic_check(struct drm_plane *plane, if (!state->crtc) return 0; - err = tegra_dc_format(state->fb->format->format, &plane_state->format, - &plane_state->swap); + err = tegra_plane_format(state->fb->format->format, + &plane_state->format, + &plane_state->swap); if (err < 0) return err; diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c new file mode 100644 index 000000000000..78b24aa1ac83 --- /dev/null +++ b/drivers/gpu/drm/tegra/plane.c @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include "dc.h" +#include "plane.h" + +static void tegra_plane_destroy(struct drm_plane *plane) +{ + struct tegra_plane *p = to_tegra_plane(plane); + + drm_plane_cleanup(plane); + kfree(p); +} + +static void tegra_plane_reset(struct drm_plane *plane) +{ + struct tegra_plane_state *state; + + if (plane->state) + __drm_atomic_helper_plane_destroy_state(plane->state); + + kfree(plane->state); + plane->state = NULL; + + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (state) { + plane->state = &state->base; + plane->state->plane = plane; + } +} + +static struct drm_plane_state * +tegra_plane_atomic_duplicate_state(struct drm_plane *plane) +{ + struct tegra_plane_state *state = to_tegra_plane_state(plane->state); + struct tegra_plane_state *copy; + + copy = kmalloc(sizeof(*copy), GFP_KERNEL); + if (!copy) + return NULL; + + __drm_atomic_helper_plane_duplicate_state(plane, ©->base); + copy->tiling = state->tiling; + copy->format = state->format; + copy->swap = state->swap; + + return ©->base; +} + +static void tegra_plane_atomic_destroy_state(struct drm_plane *plane, + struct drm_plane_state *state) +{ + __drm_atomic_helper_plane_destroy_state(state); + kfree(state); +} + +const struct drm_plane_funcs tegra_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .destroy = tegra_plane_destroy, + .reset = tegra_plane_reset, + .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, + .atomic_destroy_state = tegra_plane_atomic_destroy_state, +}; + +int tegra_plane_state_add(struct tegra_plane *plane, + struct drm_plane_state *state) +{ + struct drm_crtc_state *crtc_state; + struct tegra_dc_state *tegra; + struct drm_rect clip; + int err; + + /* Propagate errors from allocation or locking failures. */ + crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + + clip.x1 = 0; + clip.y1 = 0; + clip.x2 = crtc_state->mode.hdisplay; + clip.y2 = crtc_state->mode.vdisplay; + + /* Check plane state for visibility and calculate clipping bounds */ + err = drm_atomic_helper_check_plane_state(state, crtc_state, &clip, + 0, INT_MAX, true, true); + if (err < 0) + return err; + + tegra = to_dc_state(crtc_state); + + tegra->planes |= WIN_A_ACT_REQ << plane->index; + + return 0; +} + +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap) +{ + /* assume no swapping of fetched data */ + if (swap) + *swap = BYTE_SWAP_NOSWAP; + + switch (fourcc) { + case DRM_FORMAT_XBGR8888: + *format = WIN_COLOR_DEPTH_R8G8B8A8; + break; + + case DRM_FORMAT_XRGB8888: + *format = WIN_COLOR_DEPTH_B8G8R8A8; + break; + + case DRM_FORMAT_RGB565: + *format = WIN_COLOR_DEPTH_B5G6R5; + break; + + case DRM_FORMAT_UYVY: + *format = WIN_COLOR_DEPTH_YCbCr422; + break; + + case DRM_FORMAT_YUYV: + if (!swap) + return -EINVAL; + + *format = WIN_COLOR_DEPTH_YCbCr422; + *swap = BYTE_SWAP_SWAP2; + break; + + case DRM_FORMAT_YUV420: + *format = WIN_COLOR_DEPTH_YCbCr420P; + break; + + case DRM_FORMAT_YUV422: + *format = WIN_COLOR_DEPTH_YCbCr422P; + break; + + default: + return -EINVAL; + } + + return 0; +} + +bool tegra_plane_format_is_yuv(unsigned int format, bool *planar) +{ + switch (format) { + case WIN_COLOR_DEPTH_YCbCr422: + case WIN_COLOR_DEPTH_YUV422: + if (planar) + *planar = false; + + return true; + + case WIN_COLOR_DEPTH_YCbCr420P: + case WIN_COLOR_DEPTH_YUV420P: + case WIN_COLOR_DEPTH_YCbCr422P: + case WIN_COLOR_DEPTH_YUV422P: + case WIN_COLOR_DEPTH_YCbCr422R: + case WIN_COLOR_DEPTH_YUV422R: + case WIN_COLOR_DEPTH_YCbCr422RA: + case WIN_COLOR_DEPTH_YUV422RA: + if (planar) + *planar = true; + + return true; + } + + if (planar) + *planar = false; + + return false; +} diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h new file mode 100644 index 000000000000..8237b885acd7 --- /dev/null +++ b/drivers/gpu/drm/tegra/plane.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef TEGRA_PLANE_H +#define TEGRA_PLANE_H 1 + +#include + +struct tegra_bo; + +struct tegra_plane { + struct drm_plane base; + unsigned int index; +}; + +struct tegra_cursor { + struct tegra_plane base; + + struct tegra_bo *bo; + unsigned int width; + unsigned int height; +}; + +static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) +{ + return container_of(plane, struct tegra_plane, base); +} + +struct tegra_plane_state { + struct drm_plane_state base; + + struct tegra_bo_tiling tiling; + u32 format; + u32 swap; +}; + +static inline struct tegra_plane_state * +to_tegra_plane_state(struct drm_plane_state *state) +{ + if (state) + return container_of(state, struct tegra_plane_state, base); + + return NULL; +} + +extern const struct drm_plane_funcs tegra_plane_funcs; + +int tegra_plane_state_add(struct tegra_plane *plane, + struct drm_plane_state *state); + +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap); +bool tegra_plane_format_is_yuv(unsigned int format, bool *planar); + +#endif /* TEGRA_PLANE_H */ -- GitLab From c4755fb9064f64083fe559e92a46df817fc5e07b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Nov 2017 11:08:13 +0100 Subject: [PATCH 1372/2547] drm/tegra: Add Tegra186 display hub support The display architecture has changed in several significant ways with the new Tegra186 SoC. Shared between all display controllers is a set of common resources referred to as the display hub. The hub generates accesses to memory and feeds them into various composition pipelines, each of which being a window that can be assigned to arbitrary heads. Atomic state is subclassed in order to track the global bandwidth requirements and select and adjust the hub clocks appropriately. The plane code is shared to a large degree with earlier SoC generations, except where the programming differs. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/Makefile | 1 + drivers/gpu/drm/tegra/dc.c | 31 ++ drivers/gpu/drm/tegra/dc.h | 114 +++++ drivers/gpu/drm/tegra/drm.c | 67 ++- drivers/gpu/drm/tegra/drm.h | 19 + drivers/gpu/drm/tegra/hub.c | 790 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/hub.h | 82 ++++ drivers/gpu/drm/tegra/plane.h | 2 + 8 files changed, 1103 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/tegra/hub.c create mode 100644 drivers/gpu/drm/tegra/hub.h diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile index a47784765217..2e0d6213f6bc 100644 --- a/drivers/gpu/drm/tegra/Makefile +++ b/drivers/gpu/drm/tegra/Makefile @@ -5,6 +5,7 @@ tegra-drm-y := \ drm.o \ gem.o \ fb.o \ + hub.o \ plane.o \ dc.o \ output.o \ diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 3aa0da6244db..25e998f8f339 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -447,6 +447,15 @@ static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, num_formats = ARRAY_SIZE(tegra_primary_plane_formats); formats = tegra_primary_plane_formats; + /* + * XXX compute offset so that we can directly access windows. + * + * Always use window A as primary window. + */ + plane->offset = 0; + plane->index = 0; + plane->depth = 255; + err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, &tegra_plane_funcs, formats, num_formats, NULL, @@ -641,7 +650,10 @@ static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, if (!plane) return ERR_PTR(-ENOMEM); + /* XXX compute offset so that we can directly access windows */ + plane->offset = 0; plane->index = index; + plane->depth = 0; num_formats = ARRAY_SIZE(tegra_overlay_plane_formats); formats = tegra_overlay_plane_formats; @@ -1382,6 +1394,25 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, static int tegra_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) { + struct tegra_atomic_state *s = to_tegra_atomic_state(state->state); + struct tegra_dc_state *tegra = to_dc_state(state); + + /* + * The display hub display clock needs to be fed by the display clock + * with the highest frequency to ensure proper functioning of all the + * displays. + * + * Note that this isn't used before Tegra186, but it doesn't hurt and + * conditionalizing it would make the code less clean. + */ + if (state->active) { + if (!s->clk_disp || tegra->pclk > s->rate) { + s->dc = to_tegra_dc(crtc); + s->clk_disp = s->dc->clk; + s->rate = tegra->pclk; + } + } + return 0; } diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index b65dfbb0af89..22c5091006bc 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -209,6 +209,8 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define WIN_B_UPDATE (1 << 10) #define WIN_C_UPDATE (1 << 11) #define CURSOR_UPDATE (1 << 15) +#define COMMON_ACTREQ (1 << 16) +#define COMMON_UPDATE (1 << 17) #define NC_HOST_TRIG (1 << 24) #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 @@ -486,6 +488,35 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define CURSOR_SRC_BLEND_MASK (3 << 8) #define CURSOR_ALPHA 0xff +#define DC_WIN_CORE_ACT_CONTROL 0x50e +#define VCOUNTER (0 << 0) +#define HCOUNTER (1 << 0) + +#define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543 +#define LATENCY_CTL_MODE_ENABLE (1 << 2) + +#define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544 +#define WATERMARK_MASK 0x1fffffff + +#define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560 +#define PIPE_METER_INT(x) (((x) & 0xff) << 8) +#define PIPE_METER_FRAC(x) (((x) & 0xff) << 0) + +#define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561 +#define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0) + +#define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562 +#define SLOTS(x) (((x) & 0xff) << 0) + +#define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563 +#define MODE_TWO_LINES (0 << 14) +#define MODE_FOUR_LINES (1 << 14) + +#define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568 +#define THREAD_NUM_MASK (0x1f << 1) +#define THREAD_NUM(x) (((x) & 0x1f) << 1) +#define THREAD_GROUP_ENABLE (1 << 0) + #define DC_WIN_CSC_YOF 0x611 #define DC_WIN_CSC_KYRGB 0x612 #define DC_WIN_CSC_KUR 0x613 @@ -596,8 +627,91 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DC_WINBUF_START_ADDR_HI 0x80d +#define DC_WINBUF_CDE_CONTROL 0x82f +#define ENABLE_SURFACE (1 << 0) + #define DC_WINBUF_AD_UFLOW_STATUS 0xbca #define DC_WINBUF_BD_UFLOW_STATUS 0xdca #define DC_WINBUF_CD_UFLOW_STATUS 0xfca +/* Tegra186 and later */ +#define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702 +#define OWNER_MASK (0xf << 0) +#define OWNER(x) (((x) & 0xf) << 0) + +#define DC_WIN_CROPPED_SIZE 0x706 + +#define DC_WIN_PLANAR_STORAGE 0x709 +#define PITCH(x) (((x) >> 6) & 0x1fff) + +#define DC_WIN_SET_PARAMS 0x70d +#define CLAMP_BEFORE_BLEND (1 << 15) +#define DEGAMMA_NONE (0 << 13) +#define DEGAMMA_SRGB (1 << 13) +#define DEGAMMA_YUV8_10 (2 << 13) +#define DEGAMMA_YUV12 (3 << 13) +#define INPUT_RANGE_BYPASS (0 << 10) +#define INPUT_RANGE_LIMITED (1 << 10) +#define INPUT_RANGE_FULL (2 << 10) +#define COLOR_SPACE_RGB (0 << 8) +#define COLOR_SPACE_YUV_601 (1 << 8) +#define COLOR_SPACE_YUV_709 (2 << 8) +#define COLOR_SPACE_YUV_2020 (3 << 8) + +#define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e +#define HORIZONTAL_TAPS_2 (1 << 3) +#define HORIZONTAL_TAPS_5 (4 << 3) +#define VERTICAL_TAPS_2 (1 << 0) +#define VERTICAL_TAPS_5 (4 << 0) + +#define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711 +#define INPUT_SCALER_USE422 (1 << 2) +#define INPUT_SCALER_VBYPASS (1 << 1) +#define INPUT_SCALER_HBYPASS (1 << 0) + +#define DC_WIN_BLEND_LAYER_CONTROL 0x716 +#define COLOR_KEY_NONE (0 << 25) +#define COLOR_KEY_SRC (1 << 25) +#define COLOR_KEY_DST (2 << 25) +#define BLEND_BYPASS (1 << 24) +#define K2(x) (((x) & 0xff) << 16) +#define K1(x) (((x) & 0xff) << 8) +#define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0) + +#define DC_WIN_BLEND_MATCH_SELECT 0x717 +#define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12) +#define BLEND_FACTOR_DST_ALPHA_ONE (1 << 12) +#define BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC (2 << 12) +#define BLEND_FACTOR_DST_ALPHA_K2 (3 << 12) +#define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8) +#define BLEND_FACTOR_SRC_ALPHA_K1 (1 << 8) +#define BLEND_FACTOR_SRC_ALPHA_K2 (2 << 8) +#define BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST (3 << 8) +#define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4) +#define BLEND_FACTOR_DST_COLOR_ONE (1 << 4) +#define BLEND_FACTOR_DST_COLOR_K1 (2 << 4) +#define BLEND_FACTOR_DST_COLOR_K2 (3 << 4) +#define BLEND_FACTOR_DST_COLOR_K1_TIMES_DST (4 << 4) +#define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST (5 << 4) +#define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC (6 << 4) +#define BLEND_FACTOR_DST_COLOR_NEG_K1 (7 << 4) +#define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0) +#define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0) +#define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0) +#define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0) +#define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0) +#define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0) + +#define DC_WIN_BLEND_NOMATCH_SELECT 0x718 + +#define DC_WIN_PRECOMP_WGRP_PARAMS 0x724 +#define SWAP_UV (1 << 0) + +#define DC_WIN_WINDOW_SET_CONTROL 0x730 +#define CONTROL_CSC_ENABLE (1 << 5) + +#define DC_WINBUF_CROPPED_POINT 0x806 +#define OFFSET_Y(x) (((x) & 0xffff) << 16) +#define OFFSET_X(x) (((x) & 0xffff) << 0) + #endif /* TEGRA_DC_H */ diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 90d876fc6ea7..98a2494b4ed0 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -33,6 +33,35 @@ struct tegra_drm_file { struct mutex lock; }; +static struct drm_atomic_state * +tegra_atomic_state_alloc(struct drm_device *drm) +{ + struct tegra_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); + + if (!state || drm_atomic_state_init(drm, &state->base) < 0) { + kfree(state); + return NULL; + } + + return &state->base; +} + +static void tegra_atomic_state_clear(struct drm_atomic_state *state) +{ + struct tegra_atomic_state *tegra = to_tegra_atomic_state(state); + + drm_atomic_state_default_clear(state); + tegra->clk_disp = NULL; + tegra->dc = NULL; + tegra->rate = 0; +} + +static void tegra_atomic_state_free(struct drm_atomic_state *state) +{ + drm_atomic_state_default_release(state); + kfree(state); +} + static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { .fb_create = tegra_fb_create, #ifdef CONFIG_DRM_FBDEV_EMULATION @@ -40,11 +69,32 @@ static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { #endif .atomic_check = drm_atomic_helper_check, .atomic_commit = drm_atomic_helper_commit, + .atomic_state_alloc = tegra_atomic_state_alloc, + .atomic_state_clear = tegra_atomic_state_clear, + .atomic_state_free = tegra_atomic_state_free, }; +static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) +{ + struct drm_device *drm = old_state->dev; + struct tegra_drm *tegra = drm->dev_private; + + if (tegra->hub) { + drm_atomic_helper_commit_modeset_disables(drm, old_state); + tegra_display_hub_atomic_commit(drm, old_state); + drm_atomic_helper_commit_planes(drm, old_state, 0); + drm_atomic_helper_commit_modeset_enables(drm, old_state); + drm_atomic_helper_commit_hw_done(old_state); + drm_atomic_helper_wait_for_vblanks(drm, old_state); + drm_atomic_helper_cleanup_planes(drm, old_state); + } else { + drm_atomic_helper_commit_tail_rpm(old_state); + } +} + static const struct drm_mode_config_helper_funcs tegra_drm_mode_config_helpers = { - .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, + .atomic_commit_tail = tegra_atomic_commit_tail, }; static int tegra_drm_load(struct drm_device *drm, unsigned long flags) @@ -119,6 +169,12 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags) if (err < 0) goto fbdev; + if (tegra->hub) { + err = tegra_display_hub_prepare(tegra->hub); + if (err < 0) + goto device; + } + /* * We don't use the drm_irq_install() helpers provided by the DRM * core, so we need to set this manually in order to allow the @@ -131,16 +187,19 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags) err = drm_vblank_init(drm, drm->mode_config.num_crtc); if (err < 0) - goto device; + goto hub; drm_mode_config_reset(drm); err = tegra_drm_fb_init(drm); if (err < 0) - goto device; + goto hub; return 0; +hub: + if (tegra->hub) + tegra_display_hub_cleanup(tegra->hub); device: host1x_device_exit(device); fbdev: @@ -1235,6 +1294,7 @@ static const struct of_device_id host1x_drm_subdevs[] = { { .compatible = "nvidia,tegra210-sor", }, { .compatible = "nvidia,tegra210-sor1", }, { .compatible = "nvidia,tegra210-vic", }, + { .compatible = "nvidia,tegra186-display", }, { .compatible = "nvidia,tegra186-vic", }, { /* sentinel */ } }; @@ -1250,6 +1310,7 @@ static struct host1x_driver host1x_drm_driver = { }; static struct platform_driver * const drivers[] = { + &tegra_display_hub_driver, &tegra_dc_driver, &tegra_hdmi_driver, &tegra_dsi_driver, diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index a3d84c4af357..d4dfd239e2a5 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -23,6 +24,7 @@ #include #include "gem.h" +#include "hub.h" #include "trace.h" struct reset_control; @@ -40,6 +42,20 @@ struct tegra_fbdev { }; #endif +struct tegra_atomic_state { + struct drm_atomic_state base; + + struct clk *clk_disp; + struct tegra_dc *dc; + unsigned long rate; +}; + +static inline struct tegra_atomic_state * +to_tegra_atomic_state(struct drm_atomic_state *state) +{ + return container_of(state, struct tegra_atomic_state, base); +} + struct tegra_drm { struct drm_device *drm; @@ -62,6 +78,8 @@ struct tegra_drm { unsigned int pitch_align; + struct tegra_display_hub *hub; + struct drm_atomic_state *state; }; @@ -187,6 +205,7 @@ void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev); void tegra_fb_output_poll_changed(struct drm_device *drm); #endif +extern struct platform_driver tegra_display_hub_driver; extern struct platform_driver tegra_dc_driver; extern struct platform_driver tegra_hdmi_driver; extern struct platform_driver tegra_dsi_driver; diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c new file mode 100644 index 000000000000..33d008fb8745 --- /dev/null +++ b/drivers/gpu/drm/tegra/hub.c @@ -0,0 +1,790 @@ +/* + * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "drm.h" +#include "dc.h" +#include "plane.h" + +static const u32 tegra_shared_plane_formats[] = { + DRM_FORMAT_XBGR8888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB565, +}; + +static inline unsigned int tegra_plane_offset(struct tegra_shared_plane *plane, + unsigned int offset) +{ + struct tegra_plane *p = &plane->base; + + if (offset >= 0x500 && offset <= 0x581) { + offset = 0x000 + (offset - 0x500); + return p->offset + offset; + } + + if (offset >= 0x700 && offset <= 0x73c) { + offset = 0x180 + (offset - 0x700); + return p->offset + offset; + } + + if (offset >= 0x800 && offset <= 0x83e) { + offset = 0x1c0 + (offset - 0x800); + return p->offset + offset; + } + + dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); + + return p->offset + offset; +} + +static inline u32 tegra_plane_readl(struct tegra_shared_plane *plane, + unsigned int offset) +{ + return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); +} + +static inline void tegra_plane_writel(struct tegra_shared_plane *plane, + u32 value, unsigned int offset) +{ + tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); +} + +static int tegra_windowgroup_enable(struct tegra_windowgroup *wgrp) +{ + mutex_lock(&wgrp->lock); + + if (wgrp->usecount == 0) { + pm_runtime_get_sync(wgrp->parent); + reset_control_deassert(wgrp->rst); + } + + wgrp->usecount++; + mutex_unlock(&wgrp->lock); + + return 0; +} + +static void tegra_windowgroup_disable(struct tegra_windowgroup *wgrp) +{ + int err; + + mutex_lock(&wgrp->lock); + + if (wgrp->usecount == 1) { + err = reset_control_assert(wgrp->rst); + if (err < 0) { + pr_err("failed to assert reset for window group %u\n", + wgrp->index); + } + + pm_runtime_put(wgrp->parent); + } + + wgrp->usecount--; + mutex_unlock(&wgrp->lock); +} + +int tegra_display_hub_prepare(struct tegra_display_hub *hub) +{ + unsigned int i; + + /* + * XXX Enabling/disabling windowgroups needs to happen when the owner + * display controller is disabled. There's currently no good point at + * which this could be executed, so unconditionally enable all window + * groups for now. + */ + for (i = 0; i < hub->soc->num_wgrps; i++) { + struct tegra_windowgroup *wgrp = &hub->wgrps[i]; + + tegra_windowgroup_enable(wgrp); + } + + return 0; +} + +void tegra_display_hub_cleanup(struct tegra_display_hub *hub) +{ + unsigned int i; + + /* + * XXX Remove this once window groups can be more fine-grainedly + * enabled and disabled. + */ + for (i = 0; i < hub->soc->num_wgrps; i++) { + struct tegra_windowgroup *wgrp = &hub->wgrps[i]; + + tegra_windowgroup_disable(wgrp); + } +} + +static void tegra_shared_plane_update(struct tegra_shared_plane *plane) +{ + struct tegra_dc *dc = plane->dc; + unsigned long timeout; + u32 mask, value; + + mask = COMMON_UPDATE | WIN_A_UPDATE << plane->base.index; + tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); + + timeout = jiffies + msecs_to_jiffies(1000); + + while (time_before(jiffies, timeout)) { + value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); + if ((value & mask) == 0) + break; + + usleep_range(100, 400); + } +} + +static void tegra_shared_plane_activate(struct tegra_shared_plane *plane) +{ + struct tegra_dc *dc = plane->dc; + unsigned long timeout; + u32 mask, value; + + mask = COMMON_ACTREQ | WIN_A_ACT_REQ << plane->base.index; + tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); + + timeout = jiffies + msecs_to_jiffies(1000); + + while (time_before(jiffies, timeout)) { + value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); + if ((value & mask) == 0) + break; + + usleep_range(100, 400); + } +} + +static unsigned int +tegra_shared_plane_get_owner(struct tegra_shared_plane *plane, + struct tegra_dc *dc) +{ + unsigned int offset = + tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL); + + return tegra_dc_readl(dc, offset) & OWNER_MASK; +} + +static bool tegra_dc_owns_shared_plane(struct tegra_dc *dc, + struct tegra_shared_plane *plane) +{ + struct device *dev = dc->dev; + + if (tegra_shared_plane_get_owner(plane, dc) == dc->pipe) { + if (plane->dc == dc) + return true; + + dev_WARN(dev, "head %u owns window %u but is not attached\n", + dc->pipe, plane->base.index); + } + + return false; +} + +static int tegra_shared_plane_set_owner(struct tegra_shared_plane *plane, + struct tegra_dc *new) +{ + unsigned int offset = + tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL); + struct tegra_dc *old = plane->dc, *dc = new ? new : old; + struct device *dev = new ? new->dev : old->dev; + unsigned int owner, index = plane->base.index; + u32 value; + + value = tegra_dc_readl(dc, offset); + owner = value & OWNER_MASK; + + if (new && (owner != OWNER_MASK && owner != new->pipe)) { + dev_WARN(dev, "window %u owned by head %u\n", index, owner); + return -EBUSY; + } + + /* + * This seems to happen whenever the head has been disabled with one + * or more windows being active. This is harmless because we'll just + * reassign the window to the new head anyway. + */ + if (old && owner == OWNER_MASK) + dev_dbg(dev, "window %u not owned by head %u but %u\n", index, + old->pipe, owner); + + value &= ~OWNER_MASK; + + if (new) + value |= OWNER(new->pipe); + else + value |= OWNER_MASK; + + tegra_dc_writel(dc, value, offset); + + plane->dc = new; + + return 0; +} + +static void tegra_dc_assign_shared_plane(struct tegra_dc *dc, + struct tegra_shared_plane *plane) +{ + u32 value; + int err; + + if (!tegra_dc_owns_shared_plane(dc, plane)) { + err = tegra_shared_plane_set_owner(plane, dc); + if (err < 0) + return; + } + + value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_LINEBUF_CONFIG); + value |= MODE_FOUR_LINES; + tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_LINEBUF_CONFIG); + + value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_FETCH_METER); + value = SLOTS(1); + tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_FETCH_METER); + + /* disable watermark */ + value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA); + value &= ~LATENCY_CTL_MODE_ENABLE; + tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA); + + value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB); + value |= WATERMARK_MASK; + tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB); + + /* pipe meter */ + value = tegra_plane_readl(plane, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER); + value = PIPE_METER_INT(0) | PIPE_METER_FRAC(0); + tegra_plane_writel(plane, value, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER); + + /* mempool entries */ + value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG); + value = MEMPOOL_ENTRIES(0x331); + tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG); + + value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_THREAD_GROUP); + value &= ~THREAD_NUM_MASK; + value |= THREAD_NUM(plane->base.index); + value |= THREAD_GROUP_ENABLE; + tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_THREAD_GROUP); + + tegra_shared_plane_update(plane); + tegra_shared_plane_activate(plane); +} + +static void tegra_dc_remove_shared_plane(struct tegra_dc *dc, + struct tegra_shared_plane *plane) +{ + tegra_shared_plane_set_owner(plane, NULL); +} + +static int tegra_shared_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct tegra_plane_state *plane_state = to_tegra_plane_state(state); + struct tegra_shared_plane *tegra = to_tegra_shared_plane(plane); + struct tegra_bo_tiling *tiling = &plane_state->tiling; + struct tegra_dc *dc = to_tegra_dc(state->crtc); + int err; + + /* no need for further checks if the plane is being disabled */ + if (!state->crtc || !state->fb) + return 0; + + err = tegra_plane_format(state->fb->format->format, + &plane_state->format, + &plane_state->swap); + if (err < 0) + return err; + + err = tegra_fb_get_tiling(state->fb, tiling); + if (err < 0) + return err; + + if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && + !dc->soc->supports_block_linear) { + DRM_ERROR("hardware doesn't support block linear mode\n"); + return -EINVAL; + } + + /* + * Tegra doesn't support different strides for U and V planes so we + * error out if the user tries to display a framebuffer with such a + * configuration. + */ + if (state->fb->format->num_planes > 2) { + if (state->fb->pitches[2] != state->fb->pitches[1]) { + DRM_ERROR("unsupported UV-plane configuration\n"); + return -EINVAL; + } + } + + /* XXX scaling is not yet supported, add a check here */ + + err = tegra_plane_state_add(&tegra->base, state); + if (err < 0) + return err; + + return 0; +} + +static void tegra_shared_plane_atomic_disable(struct drm_plane *plane, + struct drm_plane_state *old_state) +{ + struct tegra_shared_plane *p = to_tegra_shared_plane(plane); + struct tegra_dc *dc = to_tegra_dc(old_state->crtc); + u32 value; + + /* rien ne va plus */ + if (!old_state || !old_state->crtc) + return; + + /* + * XXX Legacy helpers seem to sometimes call ->atomic_disable() even + * on planes that are already disabled. Make sure we fallback to the + * head for this particular state instead of crashing. + */ + if (WARN_ON(p->dc == NULL)) + p->dc = dc; + + pm_runtime_get_sync(dc->dev); + + value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS); + value &= ~WIN_ENABLE; + tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS); + + tegra_dc_remove_shared_plane(dc, p); + + pm_runtime_put(dc->dev); +} + +static void tegra_shared_plane_atomic_update(struct drm_plane *plane, + struct drm_plane_state *old_state) +{ + struct tegra_plane_state *state = to_tegra_plane_state(plane->state); + struct tegra_shared_plane *p = to_tegra_shared_plane(plane); + struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); + struct drm_framebuffer *fb = plane->state->fb; + struct tegra_bo *bo; + dma_addr_t base; + u32 value; + + /* rien ne va plus */ + if (!plane->state->crtc || !plane->state->fb) + return; + + if (!plane->state->visible) { + tegra_shared_plane_atomic_disable(plane, old_state); + return; + } + + pm_runtime_get_sync(dc->dev); + + tegra_dc_assign_shared_plane(dc, p); + + tegra_plane_writel(p, VCOUNTER, DC_WIN_CORE_ACT_CONTROL); + + /* blending */ + value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | + BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | + BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; + tegra_plane_writel(p, value, DC_WIN_BLEND_MATCH_SELECT); + + value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | + BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | + BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; + tegra_plane_writel(p, value, DC_WIN_BLEND_NOMATCH_SELECT); + + value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(p->base.depth); + tegra_plane_writel(p, value, DC_WIN_BLEND_LAYER_CONTROL); + + /* bypass scaling */ + value = HORIZONTAL_TAPS_5 | VERTICAL_TAPS_5; + tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER); + + value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS; + tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE); + + /* disable compression */ + tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL); + + bo = tegra_fb_get_plane(fb, 0); + base = bo->paddr; + + tegra_plane_writel(p, state->format, DC_WIN_COLOR_DEPTH); + tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS); + + value = V_POSITION(plane->state->crtc_y) | + H_POSITION(plane->state->crtc_x); + tegra_plane_writel(p, value, DC_WIN_POSITION); + + value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w); + tegra_plane_writel(p, value, DC_WIN_SIZE); + + value = WIN_ENABLE | COLOR_EXPAND; + tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS); + + value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w); + tegra_plane_writel(p, value, DC_WIN_CROPPED_SIZE); + + tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI); + tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR); + + value = PITCH(fb->pitches[0]); + tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE); + + value = CLAMP_BEFORE_BLEND | DEGAMMA_SRGB | INPUT_RANGE_FULL; + tegra_plane_writel(p, value, DC_WIN_SET_PARAMS); + + value = OFFSET_X(plane->state->src_y >> 16) | + OFFSET_Y(plane->state->src_x >> 16); + tegra_plane_writel(p, value, DC_WINBUF_CROPPED_POINT); + + if (dc->soc->supports_block_linear) { + unsigned long height = state->tiling.value; + + /* XXX */ + switch (state->tiling.mode) { + case TEGRA_BO_TILING_MODE_PITCH: + value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(0) | + DC_WINBUF_SURFACE_KIND_PITCH; + break; + + /* XXX not supported on Tegra186 and later */ + case TEGRA_BO_TILING_MODE_TILED: + value = DC_WINBUF_SURFACE_KIND_TILED; + break; + + case TEGRA_BO_TILING_MODE_BLOCK: + value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | + DC_WINBUF_SURFACE_KIND_BLOCK; + break; + } + + tegra_plane_writel(p, value, DC_WINBUF_SURFACE_KIND); + } + + /* disable gamut CSC */ + value = tegra_plane_readl(p, DC_WIN_WINDOW_SET_CONTROL); + value &= ~CONTROL_CSC_ENABLE; + tegra_plane_writel(p, value, DC_WIN_WINDOW_SET_CONTROL); + + pm_runtime_put(dc->dev); +} + +static const struct drm_plane_helper_funcs tegra_shared_plane_helper_funcs = { + .atomic_check = tegra_shared_plane_atomic_check, + .atomic_update = tegra_shared_plane_atomic_update, + .atomic_disable = tegra_shared_plane_atomic_disable, +}; + +struct drm_plane *tegra_shared_plane_create(struct drm_device *drm, + struct tegra_dc *dc, + unsigned int wgrp, + unsigned int index) +{ + enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY; + struct tegra_drm *tegra = drm->dev_private; + struct tegra_display_hub *hub = tegra->hub; + /* planes can be assigned to arbitrary CRTCs */ + unsigned int possible_crtcs = 0x7; + struct tegra_shared_plane *plane; + unsigned int num_formats; + struct drm_plane *p; + const u32 *formats; + int err; + + plane = kzalloc(sizeof(*plane), GFP_KERNEL); + if (!plane) + return ERR_PTR(-ENOMEM); + + plane->base.offset = 0x0a00 + 0x0300 * index; + plane->base.index = index; + plane->base.depth = 0; + + plane->wgrp = &hub->wgrps[wgrp]; + plane->wgrp->parent = dc->dev; + + p = &plane->base.base; + + num_formats = ARRAY_SIZE(tegra_shared_plane_formats); + formats = tegra_shared_plane_formats; + + err = drm_universal_plane_init(drm, p, possible_crtcs, + &tegra_plane_funcs, formats, + num_formats, NULL, type, NULL); + if (err < 0) { + kfree(plane); + return ERR_PTR(err); + } + + drm_plane_helper_add(p, &tegra_shared_plane_helper_funcs); + + return p; +} + +static void tegra_display_hub_update(struct tegra_dc *dc) +{ + u32 value; + + pm_runtime_get_sync(dc->dev); + + value = tegra_dc_readl(dc, DC_CMD_IHUB_COMMON_MISC_CTL); + value &= ~LATENCY_EVENT; + tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL); + + value = tegra_dc_readl(dc, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER); + value = CURS_SLOTS(1) | WGRP_SLOTS(1); + tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER); + + tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL); + tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); + tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL); + tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); + + pm_runtime_put(dc->dev); +} + +void tegra_display_hub_atomic_commit(struct drm_device *drm, + struct drm_atomic_state *state) +{ + struct tegra_atomic_state *s = to_tegra_atomic_state(state); + struct tegra_drm *tegra = drm->dev_private; + struct tegra_display_hub *hub = tegra->hub; + struct device *dev = hub->client.dev; + int err; + + if (s->clk_disp) { + err = clk_set_rate(s->clk_disp, s->rate); + if (err < 0) + dev_err(dev, "failed to set rate of %pC to %lu Hz\n", + s->clk_disp, s->rate); + + err = clk_set_parent(hub->clk_disp, s->clk_disp); + if (err < 0) + dev_err(dev, "failed to set parent of %pC to %pC: %d\n", + hub->clk_disp, s->clk_disp, err); + } + + if (s->dc) + tegra_display_hub_update(s->dc); +} + +static int tegra_display_hub_init(struct host1x_client *client) +{ + struct tegra_display_hub *hub = to_tegra_display_hub(client); + struct drm_device *drm = dev_get_drvdata(client->parent); + struct tegra_drm *tegra = drm->dev_private; + + tegra->hub = hub; + + return 0; +} + +static int tegra_display_hub_exit(struct host1x_client *client) +{ + struct drm_device *drm = dev_get_drvdata(client->parent); + struct tegra_drm *tegra = drm->dev_private; + + tegra->hub = NULL; + + return 0; +} + +static const struct host1x_client_ops tegra_display_hub_ops = { + .init = tegra_display_hub_init, + .exit = tegra_display_hub_exit, +}; + +static int tegra_display_hub_probe(struct platform_device *pdev) +{ + struct tegra_display_hub *hub; + unsigned int i; + int err; + + hub = devm_kzalloc(&pdev->dev, sizeof(*hub), GFP_KERNEL); + if (!hub) + return -ENOMEM; + + hub->soc = of_device_get_match_data(&pdev->dev); + + hub->clk_disp = devm_clk_get(&pdev->dev, "disp"); + if (IS_ERR(hub->clk_disp)) { + err = PTR_ERR(hub->clk_disp); + return err; + } + + hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc"); + if (IS_ERR(hub->clk_dsc)) { + err = PTR_ERR(hub->clk_dsc); + return err; + } + + hub->clk_hub = devm_clk_get(&pdev->dev, "hub"); + if (IS_ERR(hub->clk_hub)) { + err = PTR_ERR(hub->clk_hub); + return err; + } + + hub->rst = devm_reset_control_get(&pdev->dev, "misc"); + if (IS_ERR(hub->rst)) { + err = PTR_ERR(hub->rst); + return err; + } + + hub->wgrps = devm_kcalloc(&pdev->dev, hub->soc->num_wgrps, + sizeof(*hub->wgrps), GFP_KERNEL); + if (!hub->wgrps) + return -ENOMEM; + + for (i = 0; i < hub->soc->num_wgrps; i++) { + struct tegra_windowgroup *wgrp = &hub->wgrps[i]; + char id[8]; + + snprintf(id, sizeof(id), "wgrp%u", i); + mutex_init(&wgrp->lock); + wgrp->usecount = 0; + wgrp->index = i; + + wgrp->rst = devm_reset_control_get(&pdev->dev, id); + if (IS_ERR(wgrp->rst)) + return PTR_ERR(wgrp->rst); + + err = reset_control_assert(wgrp->rst); + if (err < 0) + return err; + } + + /* XXX: enable clock across reset? */ + err = reset_control_assert(hub->rst); + if (err < 0) + return err; + + platform_set_drvdata(pdev, hub); + pm_runtime_enable(&pdev->dev); + + INIT_LIST_HEAD(&hub->client.list); + hub->client.ops = &tegra_display_hub_ops; + hub->client.dev = &pdev->dev; + + err = host1x_client_register(&hub->client); + if (err < 0) + dev_err(&pdev->dev, "failed to register host1x client: %d\n", + err); + + return err; +} + +static int tegra_display_hub_remove(struct platform_device *pdev) +{ + struct tegra_display_hub *hub = platform_get_drvdata(pdev); + int err; + + err = host1x_client_unregister(&hub->client); + if (err < 0) { + dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", + err); + } + + pm_runtime_disable(&pdev->dev); + + return err; +} + +static int tegra_display_hub_suspend(struct device *dev) +{ + struct tegra_display_hub *hub = dev_get_drvdata(dev); + int err; + + err = reset_control_assert(hub->rst); + if (err < 0) + return err; + + clk_disable_unprepare(hub->clk_hub); + clk_disable_unprepare(hub->clk_dsc); + clk_disable_unprepare(hub->clk_disp); + + return 0; +} + +static int tegra_display_hub_resume(struct device *dev) +{ + struct tegra_display_hub *hub = dev_get_drvdata(dev); + int err; + + err = clk_prepare_enable(hub->clk_disp); + if (err < 0) + return err; + + err = clk_prepare_enable(hub->clk_dsc); + if (err < 0) + goto disable_disp; + + err = clk_prepare_enable(hub->clk_hub); + if (err < 0) + goto disable_dsc; + + err = reset_control_deassert(hub->rst); + if (err < 0) + goto disable_hub; + + return 0; + +disable_hub: + clk_disable_unprepare(hub->clk_hub); +disable_dsc: + clk_disable_unprepare(hub->clk_dsc); +disable_disp: + clk_disable_unprepare(hub->clk_disp); + return err; +} + +static const struct dev_pm_ops tegra_display_hub_pm_ops = { + SET_RUNTIME_PM_OPS(tegra_display_hub_suspend, + tegra_display_hub_resume, NULL) +}; + +static const struct tegra_display_hub_soc tegra186_display_hub = { + .num_wgrps = 6, +}; + +static const struct of_device_id tegra_display_hub_of_match[] = { + { + .compatible = "nvidia,tegra186-display", + .data = &tegra186_display_hub + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, tegra_display_hub_of_match); + +struct platform_driver tegra_display_hub_driver = { + .driver = { + .name = "tegra-display-hub", + .of_match_table = tegra_display_hub_of_match, + .pm = &tegra_display_hub_pm_ops, + }, + .probe = tegra_display_hub_probe, + .remove = tegra_display_hub_remove, +}; diff --git a/drivers/gpu/drm/tegra/hub.h b/drivers/gpu/drm/tegra/hub.h new file mode 100644 index 000000000000..965c333736b0 --- /dev/null +++ b/drivers/gpu/drm/tegra/hub.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef TEGRA_HUB_H +#define TEGRA_HUB_H 1 + +#include +#include + +#include "plane.h" + +struct tegra_dc; + +struct tegra_windowgroup { + unsigned int usecount; + struct mutex lock; + + unsigned int index; + struct device *parent; + struct reset_control *rst; +}; + +struct tegra_shared_plane { + struct tegra_plane base; + struct tegra_windowgroup *wgrp; + struct tegra_dc *dc; +}; + +static inline struct tegra_shared_plane * +to_tegra_shared_plane(struct drm_plane *plane) +{ + return container_of(plane, struct tegra_shared_plane, base.base); +} + +struct tegra_display_hub_soc { + unsigned int num_wgrps; +}; + +struct tegra_display_hub { + struct host1x_client client; + struct clk *clk_disp; + struct clk *clk_dsc; + struct clk *clk_hub; + struct reset_control *rst; + + const struct tegra_display_hub_soc *soc; + struct tegra_windowgroup *wgrps; +}; + +static inline struct tegra_display_hub * +to_tegra_display_hub(struct host1x_client *client) +{ + return container_of(client, struct tegra_display_hub, client); +} + +struct tegra_dc; +struct tegra_plane; + +int tegra_display_hub_prepare(struct tegra_display_hub *hub); +void tegra_display_hub_cleanup(struct tegra_display_hub *hub); + +struct drm_plane *tegra_shared_plane_create(struct drm_device *drm, + struct tegra_dc *dc, + unsigned int wgrp, + unsigned int index); + +void tegra_display_hub_atomic_commit(struct drm_device *drm, + struct drm_atomic_state *state); + +#define DC_CMD_IHUB_COMMON_MISC_CTL 0x068 +#define LATENCY_EVENT (1 << 3) + +#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER 0x451 +#define CURS_SLOTS(x) (((x) & 0xff) << 8) +#define WGRP_SLOTS(x) (((x) & 0xff) << 0) + +#endif /* TEGRA_HUB_H */ diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h index 8237b885acd7..fc7566f630fa 100644 --- a/drivers/gpu/drm/tegra/plane.h +++ b/drivers/gpu/drm/tegra/plane.h @@ -15,7 +15,9 @@ struct tegra_bo; struct tegra_plane { struct drm_plane base; + unsigned int offset; unsigned int index; + unsigned int depth; }; struct tegra_cursor { -- GitLab From 473079549f27eab5ad449f2c4f079014f0fe74a5 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 30 Aug 2017 17:42:54 +0200 Subject: [PATCH 1373/2547] drm/tegra: dc: Add Tegra186 support The display architecture has changed in several signifcant ways with the new Tegra186 SoC. Display controllers are a completely different design, but have been given a frontend that simulates the register interface for earlier chips. Unfortunately the frontend isn't completely backwards compatible, so the driver needs parameterization to take the changes into account. One big change is that the total number of display controllers has been increased to three. At the same time the number of planes available has remained constant. However, planes can now be freely assigned between the display controllers, giving applications more flexibility in making the best use of the available resources. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 250 ++++++++++++++++++++++++++++-------- drivers/gpu/drm/tegra/dc.h | 98 +++++++++----- drivers/gpu/drm/tegra/drm.c | 1 + 3 files changed, 267 insertions(+), 82 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 25e998f8f339..5878d42d153c 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -19,6 +19,7 @@ #include "dc.h" #include "drm.h" #include "gem.h" +#include "hub.h" #include "plane.h" #include @@ -419,8 +420,8 @@ static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = { .atomic_update = tegra_plane_atomic_update, }; -static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, - struct tegra_dc *dc) +static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm, + struct tegra_dc *dc) { /* * Ideally this would use drm_crtc_mask(), but that would require the @@ -435,6 +436,7 @@ static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, * the same as drm_crtc_index() after registration. */ unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc; + enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY; struct tegra_plane *plane; unsigned int num_formats; const u32 *formats; @@ -458,8 +460,7 @@ static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, &tegra_plane_funcs, formats, - num_formats, NULL, - DRM_PLANE_TYPE_PRIMARY, NULL); + num_formats, NULL, type, NULL); if (err < 0) { kfree(plane); return ERR_PTR(err); @@ -672,18 +673,61 @@ static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, return &plane->base; } -static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) +static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm, + struct tegra_dc *dc) +{ + struct drm_plane *plane, *primary = NULL; + unsigned int i, j; + + for (i = 0; i < dc->soc->num_wgrps; i++) { + const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; + + if (wgrp->dc == dc->pipe) { + for (j = 0; j < wgrp->num_windows; j++) { + unsigned int index = wgrp->windows[j]; + + plane = tegra_shared_plane_create(drm, dc, + wgrp->index, + index); + if (IS_ERR(plane)) + return plane; + + /* + * Choose the first shared plane owned by this + * head as the primary plane. + */ + if (!primary) { + plane->type = DRM_PLANE_TYPE_PRIMARY; + primary = plane; + } + } + } + } + + return primary; +} + +static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm, + struct tegra_dc *dc) { - struct drm_plane *plane; + struct drm_plane *plane, *primary; unsigned int i; + primary = tegra_primary_plane_create(drm, dc); + if (IS_ERR(primary)) + return primary; + for (i = 0; i < 2; i++) { plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i); - if (IS_ERR(plane)) - return PTR_ERR(plane); + if (IS_ERR(plane)) { + /* XXX tegra_plane_destroy() */ + drm_plane_cleanup(primary); + kfree(primary); + return plane; + } } - return 0; + return primary; } static void tegra_dc_destroy(struct drm_crtc *crtc) @@ -1073,7 +1117,8 @@ static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) { struct tegra_dc *dc = to_tegra_dc(crtc); - if (dc->syncpt) + /* XXX vblank syncpoints don't work with nvdisplay yet */ + if (dc->syncpt && !dc->soc->has_nvdisplay) return host1x_syncpt_read(dc->syncpt); /* fallback to software emulated VBLANK counter */ @@ -1131,10 +1176,12 @@ static int tegra_dc_set_timings(struct tegra_dc *dc, unsigned int v_ref_to_sync = 1; unsigned long value; - tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); + if (!dc->soc->has_nvdisplay) { + tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); - value = (v_ref_to_sync << 16) | h_ref_to_sync; - tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); + value = (v_ref_to_sync << 16) | h_ref_to_sync; + tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); + } value = ((mode->vsync_end - mode->vsync_start) << 16) | ((mode->hsync_end - mode->hsync_start) << 0); @@ -1213,8 +1260,10 @@ static void tegra_dc_commit_state(struct tegra_dc *dc, state->div); DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); - value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; - tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); + if (!dc->soc->has_nvdisplay) { + value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; + tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); + } err = clk_set_rate(dc->clk, state->pclk); if (err < 0) @@ -1324,39 +1373,66 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, /* initialize display controller */ if (dc->syncpt) { - u32 syncpt = host1x_syncpt_id(dc->syncpt); + u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; + + if (dc->soc->has_nvdisplay) + enable = 1 << 31; + else + enable = 1 << 8; value = SYNCPT_CNTRL_NO_STALL; tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); - value = SYNCPT_VSYNC_ENABLE | syncpt; + value = enable | syncpt; tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); } - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | - WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; - tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); - - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | - WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; - tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); + if (dc->soc->has_nvdisplay) { + value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | + DSC_OBUF_UF_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); - /* initialize timer */ - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | - WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); - tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); + value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | + DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT | + HEAD_UF_INT | MSF_INT | REG_TMOUT_INT | + REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT | + VBLANK_INT | FRAME_END_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | - WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); - tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); + value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT | + FRAME_END_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); - value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | - WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; - tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); + value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_MASK); - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | - WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; - tegra_dc_writel(dc, value, DC_CMD_INT_MASK); + tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); + } else { + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | + WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); + + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | + WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); + + /* initialize timer */ + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | + WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); + tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); + + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | + WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); + tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); + + value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | + WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); + + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | + WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; + tegra_dc_writel(dc, value, DC_CMD_INT_MASK); + } if (dc->soc->supports_background_color) tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); @@ -1381,10 +1457,18 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, value |= DISP_CTRL_MODE_C_DISPLAY; tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); - value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); - value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | - PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; - tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); + if (!dc->soc->has_nvdisplay) { + value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); + value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | + PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; + tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); + } + + /* enable underflow reporting and display red for missing pixels */ + if (dc->soc->has_nvdisplay) { + value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE; + tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); + } tegra_dc_commit(dc); @@ -1440,9 +1524,15 @@ static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, { struct tegra_dc_state *state = to_dc_state(crtc->state); struct tegra_dc *dc = to_tegra_dc(crtc); + u32 value; + + value = state->planes << 8 | GENERAL_UPDATE; + tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); + value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); - tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL); - tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL); + value = state->planes | GENERAL_ACT_REQ; + tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); + value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); } static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { @@ -1490,6 +1580,11 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) dc->stats.overflow++; } + if (status & HEAD_UF_INT) { + dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); + dc->stats.underflow++; + } + return IRQ_HANDLED; } @@ -1518,7 +1613,11 @@ static int tegra_dc_init(struct host1x_client *client) dc->domain = tegra->domain; } - primary = tegra_dc_primary_plane_create(drm, dc); + if (dc->soc->wgrps) + primary = tegra_dc_add_shared_planes(drm, dc); + else + primary = tegra_dc_add_planes(drm, dc); + if (IS_ERR(primary)) { err = PTR_ERR(primary); goto cleanup; @@ -1552,10 +1651,6 @@ static int tegra_dc_init(struct host1x_client *client) goto cleanup; } - err = tegra_dc_add_planes(drm, dc); - if (err < 0) - goto cleanup; - err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, dev_name(dc->dev), dc); if (err < 0) { @@ -1567,10 +1662,10 @@ static int tegra_dc_init(struct host1x_client *client) return 0; cleanup: - if (cursor) + if (!IS_ERR_OR_NULL(cursor)) drm_plane_cleanup(cursor); - if (primary) + if (!IS_ERR(primary)) drm_plane_cleanup(primary); if (tegra->domain) { @@ -1617,6 +1712,7 @@ static const struct tegra_dc_soc_info tegra20_dc_soc_info = { .pitch_align = 8, .has_powergate = false, .broken_reset = true, + .has_nvdisplay = false, }; static const struct tegra_dc_soc_info tegra30_dc_soc_info = { @@ -1627,6 +1723,7 @@ static const struct tegra_dc_soc_info tegra30_dc_soc_info = { .pitch_align = 8, .has_powergate = false, .broken_reset = false, + .has_nvdisplay = false, }; static const struct tegra_dc_soc_info tegra114_dc_soc_info = { @@ -1637,6 +1734,7 @@ static const struct tegra_dc_soc_info tegra114_dc_soc_info = { .pitch_align = 64, .has_powergate = true, .broken_reset = false, + .has_nvdisplay = false, }; static const struct tegra_dc_soc_info tegra124_dc_soc_info = { @@ -1647,6 +1745,7 @@ static const struct tegra_dc_soc_info tegra124_dc_soc_info = { .pitch_align = 64, .has_powergate = true, .broken_reset = false, + .has_nvdisplay = false, }; static const struct tegra_dc_soc_info tegra210_dc_soc_info = { @@ -1657,10 +1756,61 @@ static const struct tegra_dc_soc_info tegra210_dc_soc_info = { .pitch_align = 64, .has_powergate = true, .broken_reset = false, + .has_nvdisplay = false, +}; + +static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = { + { + .index = 0, + .dc = 0, + .windows = (const unsigned int[]) { 0 }, + .num_windows = 1, + }, { + .index = 1, + .dc = 1, + .windows = (const unsigned int[]) { 1 }, + .num_windows = 1, + }, { + .index = 2, + .dc = 1, + .windows = (const unsigned int[]) { 2 }, + .num_windows = 1, + }, { + .index = 3, + .dc = 2, + .windows = (const unsigned int[]) { 3 }, + .num_windows = 1, + }, { + .index = 4, + .dc = 2, + .windows = (const unsigned int[]) { 4 }, + .num_windows = 1, + }, { + .index = 5, + .dc = 2, + .windows = (const unsigned int[]) { 5 }, + .num_windows = 1, + }, +}; + +static const struct tegra_dc_soc_info tegra186_dc_soc_info = { + .supports_background_color = true, + .supports_interlacing = true, + .supports_cursor = true, + .supports_block_linear = true, + .pitch_align = 64, + .has_powergate = false, + .broken_reset = false, + .has_nvdisplay = true, + .wgrps = tegra186_dc_wgrps, + .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), }; static const struct of_device_id tegra_dc_of_match[] = { { + .compatible = "nvidia,tegra186-dc", + .data = &tegra186_dc_soc_info, + }, { .compatible = "nvidia,tegra210-dc", .data = &tegra210_dc_soc_info, }, { diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 22c5091006bc..47f43663adcb 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -43,6 +43,13 @@ struct tegra_dc_stats { unsigned long overflow; }; +struct tegra_windowgroup_soc { + unsigned int index; + unsigned int dc; + const unsigned int *windows; + unsigned int num_windows; +}; + struct tegra_dc_soc_info { bool supports_background_color; bool supports_interlacing; @@ -51,6 +58,9 @@ struct tegra_dc_soc_info { unsigned int pitch_align; bool has_powergate; bool broken_reset; + bool has_nvdisplay; + const struct tegra_windowgroup_soc *wgrps; + unsigned int num_wgrps; }; struct tegra_dc { @@ -180,15 +190,26 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DC_CMD_INT_ENABLE 0x039 #define DC_CMD_INT_TYPE 0x03a #define DC_CMD_INT_POLARITY 0x03b -#define CTXSW_INT (1 << 0) -#define FRAME_END_INT (1 << 1) -#define VBLANK_INT (1 << 2) -#define WIN_A_UF_INT (1 << 8) -#define WIN_B_UF_INT (1 << 9) -#define WIN_C_UF_INT (1 << 10) -#define WIN_A_OF_INT (1 << 14) -#define WIN_B_OF_INT (1 << 15) -#define WIN_C_OF_INT (1 << 16) +#define CTXSW_INT (1 << 0) +#define FRAME_END_INT (1 << 1) +#define VBLANK_INT (1 << 2) +#define V_PULSE3_INT (1 << 4) +#define V_PULSE2_INT (1 << 5) +#define REGION_CRC_INT (1 << 6) +#define REG_TMOUT_INT (1 << 7) +#define WIN_A_UF_INT (1 << 8) +#define WIN_B_UF_INT (1 << 9) +#define WIN_C_UF_INT (1 << 10) +#define MSF_INT (1 << 12) +#define WIN_A_OF_INT (1 << 14) +#define WIN_B_OF_INT (1 << 15) +#define WIN_C_OF_INT (1 << 16) +#define HEAD_UF_INT (1 << 23) +#define SD3_BUCKET_WALK_DONE_INT (1 << 24) +#define DSC_OBUF_UF_INT (1 << 26) +#define DSC_RBUF_UF_INT (1 << 27) +#define DSC_BBUF_UF_INT (1 << 28) +#define DSC_TO_UF_INT (1 << 29) #define DC_CMD_SIGNAL_RAISE1 0x03c #define DC_CMD_SIGNAL_RAISE2 0x03d @@ -253,6 +274,10 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328 #define DC_COM_CRC_CHECKSUM_LATCHED 0x329 +#define DC_COM_RG_UNDERFLOW 0x365 +#define UNDERFLOW_MODE_RED (1 << 8) +#define UNDERFLOW_REPORT_ENABLE (1 << 0) + #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 #define H_PULSE0_ENABLE (1 << 8) #define H_PULSE1_ENABLE (1 << 10) @@ -375,29 +400,33 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DISP_ORDER_BLUE_RED (1 << 9) #define DC_DISP_DISP_COLOR_CONTROL 0x430 -#define BASE_COLOR_SIZE666 (0 << 0) -#define BASE_COLOR_SIZE111 (1 << 0) -#define BASE_COLOR_SIZE222 (2 << 0) -#define BASE_COLOR_SIZE333 (3 << 0) -#define BASE_COLOR_SIZE444 (4 << 0) -#define BASE_COLOR_SIZE555 (5 << 0) -#define BASE_COLOR_SIZE565 (6 << 0) -#define BASE_COLOR_SIZE332 (7 << 0) -#define BASE_COLOR_SIZE888 (8 << 0) +#define BASE_COLOR_SIZE666 ( 0 << 0) +#define BASE_COLOR_SIZE111 ( 1 << 0) +#define BASE_COLOR_SIZE222 ( 2 << 0) +#define BASE_COLOR_SIZE333 ( 3 << 0) +#define BASE_COLOR_SIZE444 ( 4 << 0) +#define BASE_COLOR_SIZE555 ( 5 << 0) +#define BASE_COLOR_SIZE565 ( 6 << 0) +#define BASE_COLOR_SIZE332 ( 7 << 0) +#define BASE_COLOR_SIZE888 ( 8 << 0) +#define BASE_COLOR_SIZE101010 (10 << 0) +#define BASE_COLOR_SIZE121212 (12 << 0) #define DITHER_CONTROL_MASK (3 << 8) #define DITHER_CONTROL_DISABLE (0 << 8) #define DITHER_CONTROL_ORDERED (2 << 8) #define DITHER_CONTROL_ERRDIFF (3 << 8) #define BASE_COLOR_SIZE_MASK (0xf << 0) -#define BASE_COLOR_SIZE_666 (0 << 0) -#define BASE_COLOR_SIZE_111 (1 << 0) -#define BASE_COLOR_SIZE_222 (2 << 0) -#define BASE_COLOR_SIZE_333 (3 << 0) -#define BASE_COLOR_SIZE_444 (4 << 0) -#define BASE_COLOR_SIZE_555 (5 << 0) -#define BASE_COLOR_SIZE_565 (6 << 0) -#define BASE_COLOR_SIZE_332 (7 << 0) -#define BASE_COLOR_SIZE_888 (8 << 0) +#define BASE_COLOR_SIZE_666 ( 0 << 0) +#define BASE_COLOR_SIZE_111 ( 1 << 0) +#define BASE_COLOR_SIZE_222 ( 2 << 0) +#define BASE_COLOR_SIZE_333 ( 3 << 0) +#define BASE_COLOR_SIZE_444 ( 4 << 0) +#define BASE_COLOR_SIZE_555 ( 5 << 0) +#define BASE_COLOR_SIZE_565 ( 6 << 0) +#define BASE_COLOR_SIZE_332 ( 7 << 0) +#define BASE_COLOR_SIZE_888 ( 8 << 0) +#define BASE_COLOR_SIZE_101010 ( 10 << 0) +#define BASE_COLOR_SIZE_121212 ( 12 << 0) #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 #define SC1_H_QUALIFIER_NONE (1 << 16) @@ -571,16 +600,16 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define WIN_COLOR_DEPTH_YUV422RA 25 #define DC_WIN_POSITION 0x704 -#define H_POSITION(x) (((x) & 0x1fff) << 0) -#define V_POSITION(x) (((x) & 0x1fff) << 16) +#define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */ +#define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ #define DC_WIN_SIZE 0x705 -#define H_SIZE(x) (((x) & 0x1fff) << 0) -#define V_SIZE(x) (((x) & 0x1fff) << 16) +#define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */ +#define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ #define DC_WIN_PRESCALED_SIZE 0x706 #define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) -#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) +#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ #define DC_WIN_H_INITIAL_DDA 0x707 #define DC_WIN_V_INITIAL_DDA 0x708 @@ -596,6 +625,7 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0) #define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16) #define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16) + #define DC_WIN_DV_CONTROL 0x70e #define DC_WIN_BLEND_NOKEY 0x70f @@ -635,6 +665,10 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DC_WINBUF_CD_UFLOW_STATUS 0xfca /* Tegra186 and later */ +#define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x)) +#define PROTOCOL_MASK (0xf << 8) +#define PROTOCOL_SINGLE_TMDS_A (0x1 << 8) + #define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702 #define OWNER_MASK (0xf << 0) #define OWNER(x) (((x) & 0xf) << 0) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 98a2494b4ed0..8ade997c2b6c 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -1295,6 +1295,7 @@ static const struct of_device_id host1x_drm_subdevs[] = { { .compatible = "nvidia,tegra210-sor1", }, { .compatible = "nvidia,tegra210-vic", }, { .compatible = "nvidia,tegra186-display", }, + { .compatible = "nvidia,tegra186-dc", }, { .compatible = "nvidia,tegra186-vic", }, { /* sentinel */ } }; -- GitLab From 7772fdaef939891d790c3461a4d1681417e0f51f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 12 Oct 2017 17:30:55 +0200 Subject: [PATCH 1374/2547] drm/tegra: Support ARGB and ABGR formats These formats can easily be supported on all generations of Tegra. Note that the XRGB and XBGR formats that we supported were in fact using the ARGB and ABGR Tegra formats. This happened to work in cases where no alpha was being considered. This change is also a fix for those formats. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 4 ++++ drivers/gpu/drm/tegra/dc.h | 2 ++ drivers/gpu/drm/tegra/plane.c | 8 ++++++++ 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 5878d42d153c..6790e2d869c4 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -287,7 +287,9 @@ static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, static const u32 tegra_primary_plane_formats[] = { DRM_FORMAT_XBGR8888, + DRM_FORMAT_ABGR8888, DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565, }; @@ -630,7 +632,9 @@ static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, static const uint32_t tegra_overlay_plane_formats[] = { DRM_FORMAT_XBGR8888, + DRM_FORMAT_ABGR8888, DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565, DRM_FORMAT_UYVY, DRM_FORMAT_YUYV, diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 47f43663adcb..018fea74fb50 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -598,6 +598,8 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define WIN_COLOR_DEPTH_YUV422R 23 #define WIN_COLOR_DEPTH_YCbCr422RA 24 #define WIN_COLOR_DEPTH_YUV422RA 25 +#define WIN_COLOR_DEPTH_B8G8R8X8 37 +#define WIN_COLOR_DEPTH_R8G8B8X8 38 #define DC_WIN_POSITION 0x704 #define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */ diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c index 78b24aa1ac83..88b5aea4a48e 100644 --- a/drivers/gpu/drm/tegra/plane.c +++ b/drivers/gpu/drm/tegra/plane.c @@ -111,10 +111,18 @@ int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap) switch (fourcc) { case DRM_FORMAT_XBGR8888: + *format = WIN_COLOR_DEPTH_R8G8B8X8; + break; + + case DRM_FORMAT_ABGR8888: *format = WIN_COLOR_DEPTH_R8G8B8A8; break; case DRM_FORMAT_XRGB8888: + *format = WIN_COLOR_DEPTH_B8G8R8X8; + break; + + case DRM_FORMAT_ARGB8888: *format = WIN_COLOR_DEPTH_B8G8R8A8; break; -- GitLab From 880cee0b7ff379ebcf1f3d839fa59d1bcd726797 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 12 Oct 2017 19:04:17 +0200 Subject: [PATCH 1375/2547] drm/tegra: sor: Parameterize register offsets Future Tegra generations have an increased number of display controllers that can drive individual SORs. In order to support that, the offset and layout of some registers has changed in backwards-incompatible ways. Use parameterized register offsets to support this. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 203 ++++++++++++++++++++++-------------- 1 file changed, 127 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 2fba6c2bd486..d51399587aca 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -144,12 +144,29 @@ static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { }; #endif +struct tegra_sor_regs { + unsigned int head_state0; + unsigned int head_state1; + unsigned int head_state2; + unsigned int head_state3; + unsigned int head_state4; + unsigned int head_state5; + unsigned int pll0; + unsigned int pll1; + unsigned int pll2; + unsigned int pll3; + unsigned int dp_padctl0; + unsigned int dp_padctl2; +}; + struct tegra_sor_soc { bool supports_edp; bool supports_lvds; bool supports_hdmi; bool supports_dp; + const struct tegra_sor_regs *regs; + const struct tegra_sor_hdmi_settings *settings; unsigned int num_settings; @@ -387,23 +404,23 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor, /* disable LVDS mode */ tegra_sor_writel(sor, 0, SOR_LVDS); - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value |= SOR_DP_PADCTL_TX_PU_ENABLE; value &= ~SOR_DP_PADCTL_TX_PU_MASK; value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); usleep_range(10, 100); - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B); if (err < 0) @@ -895,31 +912,31 @@ static void tegra_sor_mode_set(struct tegra_sor *sor, */ value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); - tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); + tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); /* sync end = sync width - 1 */ vse = mode->vsync_end - mode->vsync_start - 1; hse = mode->hsync_end - mode->hsync_start - 1; value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); - tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); + tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); /* blank end = sync end + back porch */ vbe = vse + (mode->vtotal - mode->vsync_end); hbe = hse + (mode->htotal - mode->hsync_end); value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); - tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); + tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); /* blank start = blank end + active */ vbs = vbe + mode->vdisplay; hbs = hbe + mode->hdisplay; value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); - tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); + tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); /* XXX interlacing support */ - tegra_sor_writel(sor, 0x001, SOR_HEAD_STATE5(dc->pipe)); + tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); } static int tegra_sor_detach(struct tegra_sor *sor) @@ -1001,10 +1018,10 @@ static int tegra_sor_power_down(struct tegra_sor *sor) return err; } - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); /* stop lane sequencer */ value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | @@ -1024,20 +1041,20 @@ static int tegra_sor_power_down(struct tegra_sor *sor) if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) return -ETIMEDOUT; - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value |= SOR_PLL2_PORT_POWERDOWN; - tegra_sor_writel(sor, value, SOR_PLL2); + tegra_sor_writel(sor, value, sor->soc->regs->pll2); usleep_range(20, 100); - value = tegra_sor_readl(sor, SOR_PLL0); + value = tegra_sor_readl(sor, sor->soc->regs->pll0); value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; - tegra_sor_writel(sor, value, SOR_PLL0); + tegra_sor_writel(sor, value, sor->soc->regs->pll0); - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value |= SOR_PLL2_SEQ_PLLCAPPD; value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; - tegra_sor_writel(sor, value, SOR_PLL2); + tegra_sor_writel(sor, value, sor->soc->regs->pll2); usleep_range(20, 100); @@ -1528,40 +1545,40 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; tegra_sor_writel(sor, value, SOR_CLK_CNTRL); - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value &= ~SOR_PLL2_BANDGAP_POWERDOWN; - tegra_sor_writel(sor, value, SOR_PLL2); + tegra_sor_writel(sor, value, sor->soc->regs->pll2); usleep_range(20, 100); - value = tegra_sor_readl(sor, SOR_PLL3); + value = tegra_sor_readl(sor, sor->soc->regs->pll3); value |= SOR_PLL3_PLL_VDD_MODE_3V3; - tegra_sor_writel(sor, value, SOR_PLL3); + tegra_sor_writel(sor, value, sor->soc->regs->pll3); value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT; - tegra_sor_writel(sor, value, SOR_PLL0); + tegra_sor_writel(sor, value, sor->soc->regs->pll0); - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value |= SOR_PLL2_SEQ_PLLCAPPD; value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; value |= SOR_PLL2_LVDS_ENABLE; - tegra_sor_writel(sor, value, SOR_PLL2); + tegra_sor_writel(sor, value, sor->soc->regs->pll2); value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; - tegra_sor_writel(sor, value, SOR_PLL1); + tegra_sor_writel(sor, value, sor->soc->regs->pll1); while (true) { - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) break; usleep_range(250, 1000); } - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; value &= ~SOR_PLL2_PORT_POWERDOWN; - tegra_sor_writel(sor, value, SOR_PLL2); + tegra_sor_writel(sor, value, sor->soc->regs->pll2); /* * power up @@ -1574,18 +1591,18 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) tegra_sor_writel(sor, value, SOR_CLK_CNTRL); /* step 1 */ - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | SOR_PLL2_BANDGAP_POWERDOWN; - tegra_sor_writel(sor, value, SOR_PLL2); + tegra_sor_writel(sor, value, sor->soc->regs->pll2); - value = tegra_sor_readl(sor, SOR_PLL0); + value = tegra_sor_readl(sor, sor->soc->regs->pll0); value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; - tegra_sor_writel(sor, value, SOR_PLL0); + tegra_sor_writel(sor, value, sor->soc->regs->pll0); - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value &= ~SOR_DP_PADCTL_PAD_CAL_PD; - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); /* step 2 */ err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); @@ -1595,28 +1612,28 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) usleep_range(5, 100); /* step 3 */ - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value &= ~SOR_PLL2_BANDGAP_POWERDOWN; - tegra_sor_writel(sor, value, SOR_PLL2); + tegra_sor_writel(sor, value, sor->soc->regs->pll2); usleep_range(20, 100); /* step 4 */ - value = tegra_sor_readl(sor, SOR_PLL0); + value = tegra_sor_readl(sor, sor->soc->regs->pll0); value &= ~SOR_PLL0_VCOPD; value &= ~SOR_PLL0_PWR; - tegra_sor_writel(sor, value, SOR_PLL0); + tegra_sor_writel(sor, value, sor->soc->regs->pll0); - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; - tegra_sor_writel(sor, value, SOR_PLL2); + tegra_sor_writel(sor, value, sor->soc->regs->pll2); usleep_range(200, 1000); /* step 5 */ - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value &= ~SOR_PLL2_PORT_POWERDOWN; - tegra_sor_writel(sor, value, SOR_PLL2); + tegra_sor_writel(sor, value, sor->soc->regs->pll2); /* XXX not in TRM */ for (value = 0, i = 0; i < 5; i++) @@ -1632,7 +1649,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) dev_err(sor->dev, "failed to set parent clock: %d\n", err); /* power DP lanes */ - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); if (link.num_lanes <= 2) value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); @@ -1649,7 +1666,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) else value |= SOR_DP_PADCTL_PD_TXD_0; - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; @@ -1693,9 +1710,9 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) tegra_sor_writel(sor, value, SOR_DP_TPG); /* enable pad calibration logic */ - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value |= SOR_DP_PADCTL_PAD_CAL_PD; - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); err = drm_dp_link_probe(sor->aux, &link); if (err < 0) @@ -2017,38 +2034,38 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) usleep_range(20, 100); - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value &= ~SOR_PLL2_BANDGAP_POWERDOWN; - tegra_sor_writel(sor, value, SOR_PLL2); + tegra_sor_writel(sor, value, sor->soc->regs->pll2); usleep_range(20, 100); - value = tegra_sor_readl(sor, SOR_PLL3); + value = tegra_sor_readl(sor, sor->soc->regs->pll3); value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; - tegra_sor_writel(sor, value, SOR_PLL3); + tegra_sor_writel(sor, value, sor->soc->regs->pll3); - value = tegra_sor_readl(sor, SOR_PLL0); + value = tegra_sor_readl(sor, sor->soc->regs->pll0); value &= ~SOR_PLL0_VCOPD; value &= ~SOR_PLL0_PWR; - tegra_sor_writel(sor, value, SOR_PLL0); + tegra_sor_writel(sor, value, sor->soc->regs->pll0); - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; - tegra_sor_writel(sor, value, SOR_PLL2); + tegra_sor_writel(sor, value, sor->soc->regs->pll2); usleep_range(200, 400); - value = tegra_sor_readl(sor, SOR_PLL2); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; value &= ~SOR_PLL2_PORT_POWERDOWN; - tegra_sor_writel(sor, value, SOR_PLL2); + tegra_sor_writel(sor, value, sor->soc->regs->pll2); usleep_range(20, 100); - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); while (true) { value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); @@ -2166,9 +2183,9 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) tegra_sor_writel(sor, value, SOR_STATE1); /* power up pad calibration */ - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value &= ~SOR_DP_PADCTL_PAD_CAL_PD; - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); /* production settings */ settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); @@ -2178,24 +2195,24 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) return; } - value = tegra_sor_readl(sor, SOR_PLL0); + value = tegra_sor_readl(sor, sor->soc->regs->pll0); value &= ~SOR_PLL0_ICHPMP_MASK; value &= ~SOR_PLL0_VCOCAP_MASK; value |= SOR_PLL0_ICHPMP(settings->ichpmp); value |= SOR_PLL0_VCOCAP(settings->vcocap); - tegra_sor_writel(sor, value, SOR_PLL0); + tegra_sor_writel(sor, value, sor->soc->regs->pll0); tegra_sor_dp_term_calibrate(sor); - value = tegra_sor_readl(sor, SOR_PLL1); + value = tegra_sor_readl(sor, sor->soc->regs->pll1); value &= ~SOR_PLL1_LOADADJ_MASK; value |= SOR_PLL1_LOADADJ(settings->loadadj); - tegra_sor_writel(sor, value, SOR_PLL1); + tegra_sor_writel(sor, value, sor->soc->regs->pll1); - value = tegra_sor_readl(sor, SOR_PLL3); + value = tegra_sor_readl(sor, sor->soc->regs->pll3); value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref); - tegra_sor_writel(sor, value, SOR_PLL3); + tegra_sor_writel(sor, value, sor->soc->regs->pll3); value = settings->drive_current[0] << 24 | settings->drive_current[1] << 16 | @@ -2209,16 +2226,16 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) settings->preemphasis[3] << 0; tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value &= ~SOR_DP_PADCTL_TX_PU_MASK; value |= SOR_DP_PADCTL_TX_PU_ENABLE; value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu); - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); /* power down pad calibration */ - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value |= SOR_DP_PADCTL_PAD_CAL_PD; - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); /* miscellaneous display controller settings */ value = VSYNC_H_POSITION(1); @@ -2250,16 +2267,16 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) dev_err(sor->dev, "failed to power up SOR: %d\n", err); /* configure dynamic range of output */ - value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); + value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; - tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); + tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); /* configure colorspace */ - value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); + value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; value |= SOR_HEAD_STATE_COLORSPACE_RGB; - tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); + tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); tegra_sor_mode_set(sor, mode, state); @@ -2488,19 +2505,51 @@ static const u8 tegra124_sor_xbar_cfg[5] = { 0, 1, 2, 3, 4 }; +static const struct tegra_sor_regs tegra124_sor_regs = { + .head_state0 = 0x05, + .head_state1 = 0x07, + .head_state2 = 0x09, + .head_state3 = 0x0b, + .head_state4 = 0x0d, + .head_state5 = 0x0f, + .pll0 = 0x17, + .pll1 = 0x18, + .pll2 = 0x19, + .pll3 = 0x1a, + .dp_padctl0 = 0x5c, + .dp_padctl2 = 0x73, +}; + static const struct tegra_sor_soc tegra124_sor = { .supports_edp = true, .supports_lvds = true, .supports_hdmi = false, .supports_dp = false, + .regs = &tegra124_sor_regs, .xbar_cfg = tegra124_sor_xbar_cfg, }; +static const struct tegra_sor_regs tegra210_sor_regs = { + .head_state0 = 0x05, + .head_state1 = 0x07, + .head_state2 = 0x09, + .head_state3 = 0x0b, + .head_state4 = 0x0d, + .head_state5 = 0x0f, + .pll0 = 0x17, + .pll1 = 0x18, + .pll2 = 0x19, + .pll3 = 0x1a, + .dp_padctl0 = 0x5c, + .dp_padctl2 = 0x73, +}; + static const struct tegra_sor_soc tegra210_sor = { .supports_edp = true, .supports_lvds = false, .supports_hdmi = false, .supports_dp = false, + .regs = &tegra210_sor_regs, .xbar_cfg = tegra124_sor_xbar_cfg, }; @@ -2514,6 +2563,8 @@ static const struct tegra_sor_soc tegra210_sor1 = { .supports_hdmi = true, .supports_dp = true, + .regs = &tegra210_sor_regs, + .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), .settings = tegra210_sor_hdmi_defaults, -- GitLab From e30a7581bfc2d5619fed03ec7321c9e4ffb7e36f Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 12 Dec 2017 18:06:50 +0000 Subject: [PATCH 1376/2547] drm/i915: Mark up potential allocation paths within i915_sw_fence as might_sleep As kmalloc is allowed to block (if given the right flags), mark up the two i915_sw_fence routines that may call kmalloc as potential sleeping routines. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171212180652.22061-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_sw_fence.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c index ac236b88c99c..3669f5eeb91e 100644 --- a/drivers/gpu/drm/i915/i915_sw_fence.c +++ b/drivers/gpu/drm/i915/i915_sw_fence.c @@ -303,6 +303,7 @@ static int __i915_sw_fence_await_sw_fence(struct i915_sw_fence *fence, int pending; debug_fence_assert(fence); + might_sleep_if(gfpflags_allow_blocking(gfp)); if (i915_sw_fence_done(signaler)) return 0; @@ -419,6 +420,7 @@ int i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence, int ret; debug_fence_assert(fence); + might_sleep_if(gfpflags_allow_blocking(gfp)); if (dma_fence_is_signaled(dma)) return 0; @@ -465,6 +467,7 @@ int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, int ret = 0, pending; debug_fence_assert(fence); + might_sleep_if(gfpflags_allow_blocking(gfp)); if (write) { struct dma_fence **shared; -- GitLab From 2abe2f844645402e5d47012a04839d1c5cbffd0d Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 12 Dec 2017 18:06:51 +0000 Subject: [PATCH 1377/2547] drm/i915: Allow fence allocations to fail If a fence allocation fails in a blocking context, we will sleep on the fence as a last resort. We can therefore allow ourselves to fail and sleep on the fence instead of triggering a system-wide oom. This allows us to throttle malicious clients that are consuming lots of system resources by capping the amount of memory used by fences. Testcase: igt/gem_shrink/execbufX Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171212180652.22061-2-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem_clflush.c | 2 +- drivers/gpu/drm/i915/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/i915_gem_request.c | 6 +++--- drivers/gpu/drm/i915/i915_gem_request.h | 2 ++ 4 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.c b/drivers/gpu/drm/i915/i915_gem_clflush.c index f663cd919795..b9b53ac14176 100644 --- a/drivers/gpu/drm/i915/i915_gem_clflush.c +++ b/drivers/gpu/drm/i915/i915_gem_clflush.c @@ -167,7 +167,7 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, i915_sw_fence_await_reservation(&clflush->wait, obj->resv, NULL, true, I915_FENCE_TIMEOUT, - GFP_KERNEL); + I915_FENCE_GFP); reservation_object_lock(obj->resv, NULL); reservation_object_add_excl_fence(obj->resv, &clflush->dma); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 21ce374d9924..648e7536ff51 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -617,7 +617,7 @@ int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv) if (prev) i915_sw_fence_await_sw_fence_gfp(&req->submit, &prev->submit, - GFP_KERNEL); + I915_FENCE_GFP); } /* diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index c28a4ceb016d..4d5e2b714382 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -782,7 +782,7 @@ i915_gem_request_await_request(struct drm_i915_gem_request *to, if (to->engine == from->engine) { ret = i915_sw_fence_await_sw_fence_gfp(&to->submit, &from->submit, - GFP_KERNEL); + I915_FENCE_GFP); return ret < 0 ? ret : 0; } @@ -810,7 +810,7 @@ i915_gem_request_await_request(struct drm_i915_gem_request *to, await_dma_fence: ret = i915_sw_fence_await_dma_fence(&to->submit, &from->fence, 0, - GFP_KERNEL); + I915_FENCE_GFP); return ret < 0 ? ret : 0; } @@ -861,7 +861,7 @@ i915_gem_request_await_dma_fence(struct drm_i915_gem_request *req, else ret = i915_sw_fence_await_dma_fence(&req->submit, fence, I915_FENCE_TIMEOUT, - GFP_KERNEL); + I915_FENCE_GFP); if (ret < 0) return ret; diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h index 26249f39de67..0d6d39f19506 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.h +++ b/drivers/gpu/drm/i915/i915_gem_request.h @@ -204,6 +204,8 @@ struct drm_i915_gem_request { struct list_head client_link; }; +#define I915_FENCE_GFP (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) + extern const struct dma_fence_ops i915_fence_ops; static inline bool dma_fence_is_i915(const struct dma_fence *fence) -- GitLab From 31c70f97bec3107805df0f491485e7eacbc3a3ae Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 12 Dec 2017 18:06:52 +0000 Subject: [PATCH 1378/2547] drm/i915: Ratelimit request allocation under oom If we fail to allocate a request, we can reap the outstanding requests and push them to the request's slab's freelist before trying again. This forces us to ratelimit malicious clients that tie up all of the system resources in requests, instead of causing a system-wide oom. Testcase: igt/gem_shrink/execbuf1 Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171212180652.22061-3-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem_request.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 4d5e2b714382..59f023bb7015 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -677,10 +677,21 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, * * Do not use kmem_cache_zalloc() here! */ - req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL); - if (!req) { - ret = -ENOMEM; - goto err_unreserve; + req = kmem_cache_alloc(dev_priv->requests, + GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); + if (unlikely(!req)) { + /* Ratelimit ourselves to prevent oom from malicious clients */ + ret = i915_gem_wait_for_idle(dev_priv, + I915_WAIT_LOCKED | + I915_WAIT_INTERRUPTIBLE); + if (ret) + goto err_unreserve; + + req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL); + if (!req) { + ret = -ENOMEM; + goto err_unreserve; + } } req->timeline = i915_gem_context_lookup_timeline(ctx, engine); -- GitLab From c57997bce423fb71334a1fefa524569e48a1718f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 12 Oct 2017 19:12:57 +0200 Subject: [PATCH 1379/2547] drm/tegra: sor: Add Tegra186 support The SOR found on Tegra186 is very similar to the one found on Tegra210 and earlier. However, due to some changes in the display architecture, some programming sequences have changed and some register have moved around. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 13 + drivers/gpu/drm/tegra/dc.h | 5 +- drivers/gpu/drm/tegra/drm.c | 2 + drivers/gpu/drm/tegra/drm.h | 2 + drivers/gpu/drm/tegra/output.c | 24 ++ drivers/gpu/drm/tegra/sor.c | 487 +++++++++++++++++++++++++-------- drivers/gpu/drm/tegra/sor.h | 12 + 7 files changed, 422 insertions(+), 123 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 6790e2d869c4..906752d86622 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -54,6 +54,19 @@ static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) return value; } +bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) +{ + struct device_node *np = dc->dev->of_node; + struct of_phandle_iterator it; + int err; + + of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0) + if (it.node == dev->of_node) + return true; + + return false; +} + /* * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 018fea74fb50..336d2c22f521 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -141,6 +141,7 @@ struct tegra_dc_window { }; /* from dc.c */ +bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev); void tegra_dc_commit(struct tegra_dc *dc); int tegra_dc_state_setup_clock(struct tegra_dc *dc, struct drm_crtc_state *crtc_state, @@ -289,10 +290,10 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define HDMI_ENABLE (1 << 30) #define DSI_ENABLE (1 << 29) #define SOR1_TIMING_CYA (1 << 27) -#define SOR1_ENABLE (1 << 26) -#define SOR_ENABLE (1 << 25) #define CURSOR_ENABLE (1 << 16) +#define SOR_ENABLE(x) (1 << (25 + (x))) + #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) #define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 8ade997c2b6c..2fa1b48e14d2 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -1296,6 +1296,8 @@ static const struct of_device_id host1x_drm_subdevs[] = { { .compatible = "nvidia,tegra210-vic", }, { .compatible = "nvidia,tegra186-display", }, { .compatible = "nvidia,tegra186-dc", }, + { .compatible = "nvidia,tegra186-sor", }, + { .compatible = "nvidia,tegra186-sor1", }, { .compatible = "nvidia,tegra186-vic", }, { /* sentinel */ } }; diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index d4dfd239e2a5..c52bc5978d1c 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -164,6 +164,8 @@ int tegra_output_probe(struct tegra_output *output); void tegra_output_remove(struct tegra_output *output); int tegra_output_init(struct drm_device *drm, struct tegra_output *output); void tegra_output_exit(struct tegra_output *output); +void tegra_output_find_possible_crtcs(struct tegra_output *output, + struct drm_device *drm); int tegra_output_connector_get_modes(struct drm_connector *connector); enum drm_connector_status diff --git a/drivers/gpu/drm/tegra/output.c b/drivers/gpu/drm/tegra/output.c index 24f8a3b712b4..ffe34bd0bb9d 100644 --- a/drivers/gpu/drm/tegra/output.c +++ b/drivers/gpu/drm/tegra/output.c @@ -9,7 +9,9 @@ #include #include + #include "drm.h" +#include "dc.h" #include @@ -218,3 +220,25 @@ void tegra_output_exit(struct tegra_output *output) if (output->panel) drm_panel_detach(output->panel); } + +void tegra_output_find_possible_crtcs(struct tegra_output *output, + struct drm_device *drm) +{ + struct device *dev = output->dev; + struct drm_crtc *crtc; + unsigned int mask = 0; + + drm_for_each_crtc(crtc, drm) { + struct tegra_dc *dc = to_tegra_dc(crtc); + + if (tegra_dc_has_output(dc, dev)) + mask |= drm_crtc_mask(crtc); + } + + if (mask == 0) { + dev_warn(dev, "missing output definition for heads in DT\n"); + mask = 0x3; + } + + output->encoder.possible_crtcs = mask; +} diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index d51399587aca..1d7f24df0b10 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -28,17 +28,30 @@ #include "sor.h" #include "trace.h" +/* + * XXX Remove this after the commit adding it to soc/tegra/pmc.h has been + * merged. Having this around after the commit is merged should be safe since + * the preprocessor will effectively replace all occurrences and therefore no + * duplicate will be defined. + */ +#define TEGRA_IO_PAD_HDMI_DP0 26 + #define SOR_REKEY 0x38 struct tegra_sor_hdmi_settings { unsigned long frequency; u8 vcocap; + u8 filter; u8 ichpmp; u8 loadadj; - u8 termadj; - u8 tx_pu; - u8 bg_vref; + u8 tmds_termadj; + u8 tx_pu_value; + u8 bg_temp_coef; + u8 bg_vref_level; + u8 avdd10_level; + u8 avdd14_level; + u8 sparepll; u8 drive_current[4]; u8 preemphasis[4]; @@ -49,51 +62,76 @@ static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { { .frequency = 54000000, .vcocap = 0x0, + .filter = 0x0, .ichpmp = 0x1, .loadadj = 0x3, - .termadj = 0x9, - .tx_pu = 0x10, - .bg_vref = 0x8, + .tmds_termadj = 0x9, + .tx_pu_value = 0x10, + .bg_temp_coef = 0x3, + .bg_vref_level = 0x8, + .avdd10_level = 0x4, + .avdd14_level = 0x4, + .sparepll = 0x0, .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, }, { .frequency = 75000000, .vcocap = 0x3, + .filter = 0x0, .ichpmp = 0x1, .loadadj = 0x3, - .termadj = 0x9, - .tx_pu = 0x40, - .bg_vref = 0x8, + .tmds_termadj = 0x9, + .tx_pu_value = 0x40, + .bg_temp_coef = 0x3, + .bg_vref_level = 0x8, + .avdd10_level = 0x4, + .avdd14_level = 0x4, + .sparepll = 0x0, .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, }, { .frequency = 150000000, .vcocap = 0x3, + .filter = 0x0, .ichpmp = 0x1, .loadadj = 0x3, - .termadj = 0x9, - .tx_pu = 0x66, - .bg_vref = 0x8, + .tmds_termadj = 0x9, + .tx_pu_value = 0x66, + .bg_temp_coef = 0x3, + .bg_vref_level = 0x8, + .avdd10_level = 0x4, + .avdd14_level = 0x4, + .sparepll = 0x0, .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, }, { .frequency = 300000000, .vcocap = 0x3, + .filter = 0x0, .ichpmp = 0x1, .loadadj = 0x3, - .termadj = 0x9, - .tx_pu = 0x66, - .bg_vref = 0xa, + .tmds_termadj = 0x9, + .tx_pu_value = 0x66, + .bg_temp_coef = 0x3, + .bg_vref_level = 0xa, + .avdd10_level = 0x4, + .avdd14_level = 0x4, + .sparepll = 0x0, .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, }, { .frequency = 600000000, .vcocap = 0x3, + .filter = 0x0, .ichpmp = 0x1, .loadadj = 0x3, - .termadj = 0x9, - .tx_pu = 0x66, - .bg_vref = 0x8, + .tmds_termadj = 0x9, + .tx_pu_value = 0x66, + .bg_temp_coef = 0x3, + .bg_vref_level = 0x8, + .avdd10_level = 0x4, + .avdd14_level = 0x4, + .sparepll = 0x0, .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, }, @@ -103,47 +141,146 @@ static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { { .frequency = 75000000, .vcocap = 0x3, + .filter = 0x0, .ichpmp = 0x1, .loadadj = 0x3, - .termadj = 0x9, - .tx_pu = 0x40, - .bg_vref = 0x8, + .tmds_termadj = 0x9, + .tx_pu_value = 0x40, + .bg_temp_coef = 0x3, + .bg_vref_level = 0x8, + .avdd10_level = 0x4, + .avdd14_level = 0x4, + .sparepll = 0x0, .drive_current = { 0x29, 0x29, 0x29, 0x29 }, .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, }, { .frequency = 150000000, .vcocap = 0x3, + .filter = 0x0, .ichpmp = 0x1, .loadadj = 0x3, - .termadj = 0x9, - .tx_pu = 0x66, - .bg_vref = 0x8, + .tmds_termadj = 0x9, + .tx_pu_value = 0x66, + .bg_temp_coef = 0x3, + .bg_vref_level = 0x8, + .avdd10_level = 0x4, + .avdd14_level = 0x4, + .sparepll = 0x0, .drive_current = { 0x30, 0x37, 0x37, 0x37 }, .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, }, { .frequency = 300000000, .vcocap = 0x3, + .filter = 0x0, .ichpmp = 0x6, .loadadj = 0x3, - .termadj = 0x9, - .tx_pu = 0x66, - .bg_vref = 0xf, + .tmds_termadj = 0x9, + .tx_pu_value = 0x66, + .bg_temp_coef = 0x3, + .bg_vref_level = 0xf, + .avdd10_level = 0x4, + .avdd14_level = 0x4, + .sparepll = 0x0, .drive_current = { 0x30, 0x37, 0x37, 0x37 }, .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, }, { .frequency = 600000000, .vcocap = 0x3, + .filter = 0x0, .ichpmp = 0xa, .loadadj = 0x3, - .termadj = 0xb, - .tx_pu = 0x66, - .bg_vref = 0xe, + .tmds_termadj = 0xb, + .tx_pu_value = 0x66, + .bg_temp_coef = 0x3, + .bg_vref_level = 0xe, + .avdd10_level = 0x4, + .avdd14_level = 0x4, + .sparepll = 0x0, .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, }, }; #endif +static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = { + { + .frequency = 54000000, + .vcocap = 0, + .filter = 5, + .ichpmp = 5, + .loadadj = 3, + .tmds_termadj = 0xf, + .tx_pu_value = 0, + .bg_temp_coef = 3, + .bg_vref_level = 8, + .avdd10_level = 4, + .avdd14_level = 4, + .sparepll = 0x54, + .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, + .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, + }, { + .frequency = 75000000, + .vcocap = 1, + .filter = 5, + .ichpmp = 5, + .loadadj = 3, + .tmds_termadj = 0xf, + .tx_pu_value = 0, + .bg_temp_coef = 3, + .bg_vref_level = 8, + .avdd10_level = 4, + .avdd14_level = 4, + .sparepll = 0x44, + .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, + .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, + }, { + .frequency = 150000000, + .vcocap = 3, + .filter = 5, + .ichpmp = 5, + .loadadj = 3, + .tmds_termadj = 15, + .tx_pu_value = 0x66 /* 0 */, + .bg_temp_coef = 3, + .bg_vref_level = 8, + .avdd10_level = 4, + .avdd14_level = 4, + .sparepll = 0x00, /* 0x34 */ + .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, + .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, + }, { + .frequency = 300000000, + .vcocap = 3, + .filter = 5, + .ichpmp = 5, + .loadadj = 3, + .tmds_termadj = 15, + .tx_pu_value = 64, + .bg_temp_coef = 3, + .bg_vref_level = 8, + .avdd10_level = 4, + .avdd14_level = 4, + .sparepll = 0x34, + .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, + .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, + }, { + .frequency = 600000000, + .vcocap = 3, + .filter = 5, + .ichpmp = 5, + .loadadj = 3, + .tmds_termadj = 12, + .tx_pu_value = 96, + .bg_temp_coef = 3, + .bg_vref_level = 8, + .avdd10_level = 4, + .avdd14_level = 4, + .sparepll = 0x34, + .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, + .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, + } +}; + struct tegra_sor_regs { unsigned int head_state0; unsigned int head_state1; @@ -166,6 +303,7 @@ struct tegra_sor_soc { bool supports_dp; const struct tegra_sor_regs *regs; + bool has_nvdisplay; const struct tegra_sor_hdmi_settings *settings; unsigned int num_settings; @@ -188,6 +326,7 @@ struct tegra_sor { const struct tegra_sor_soc *soc; void __iomem *regs; + unsigned int index; struct reset_control *rst; struct clk *clk_parent; @@ -202,6 +341,7 @@ struct tegra_sor { struct drm_info_list *debugfs_files; const struct tegra_sor_ops *ops; + enum tegra_io_pad pad; /* for HDMI 2.0 */ struct tegra_sor_hdmi_settings *settings; @@ -480,47 +620,6 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor, return 0; } -static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) -{ - u32 mask = 0x08, adj = 0, value; - - /* enable pad calibration logic */ - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); - value &= ~SOR_DP_PADCTL_PAD_CAL_PD; - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); - - value = tegra_sor_readl(sor, SOR_PLL1); - value |= SOR_PLL1_TMDS_TERM; - tegra_sor_writel(sor, value, SOR_PLL1); - - while (mask) { - adj |= mask; - - value = tegra_sor_readl(sor, SOR_PLL1); - value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; - value |= SOR_PLL1_TMDS_TERMADJ(adj); - tegra_sor_writel(sor, value, SOR_PLL1); - - usleep_range(100, 200); - - value = tegra_sor_readl(sor, SOR_PLL1); - if (value & SOR_PLL1_TERM_COMPOUT) - adj &= ~mask; - - mask >>= 1; - } - - value = tegra_sor_readl(sor, SOR_PLL1); - value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; - value |= SOR_PLL1_TMDS_TERMADJ(adj); - tegra_sor_writel(sor, value, SOR_PLL1); - - /* disable pad calibration logic */ - value = tegra_sor_readl(sor, SOR_DP_PADCTL0); - value |= SOR_DP_PADCTL_PAD_CAL_PD; - tegra_sor_writel(sor, value, SOR_DP_PADCTL0); -} - static void tegra_sor_super_update(struct tegra_sor *sor) { tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); @@ -1217,6 +1316,7 @@ static const struct debugfs_reg32 tegra_sor_regs[] = { DEBUGFS_REG32(SOR_DP_MN1), DEBUGFS_REG32(SOR_DP_PADCTL0), DEBUGFS_REG32(SOR_DP_PADCTL1), + DEBUGFS_REG32(SOR_DP_PADCTL2), DEBUGFS_REG32(SOR_DP_DEBUG0), DEBUGFS_REG32(SOR_DP_DEBUG1), DEBUGFS_REG32(SOR_DP_SPARE0), @@ -1429,7 +1529,7 @@ static void tegra_sor_edp_disable(struct drm_encoder *encoder) */ if (dc) { value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); - value &= ~SOR_ENABLE; + value &= ~SOR_ENABLE(0); tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); tegra_dc_commit(dc); @@ -1445,9 +1545,9 @@ static void tegra_sor_edp_disable(struct drm_encoder *encoder) dev_err(sor->dev, "failed to disable DP: %d\n", err); } - err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); + err = tegra_io_pad_power_disable(sor->pad); if (err < 0) - dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); + dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); if (output->panel) drm_panel_unprepare(output->panel); @@ -1605,9 +1705,9 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); /* step 2 */ - err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); + err = tegra_io_pad_power_enable(sor->pad); if (err < 0) - dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); + dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); usleep_range(5, 100); @@ -1785,7 +1885,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) tegra_sor_update(sor); value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); - value |= SOR_ENABLE; + value |= SOR_ENABLE(0); tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); tegra_dc_commit(dc); @@ -1984,8 +2084,12 @@ static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) /* disable display to SOR clock */ value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); - value &= ~SOR1_TIMING_CYA; - value &= ~SOR1_ENABLE; + + if (!sor->soc->has_nvdisplay) + value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1)); + else + value &= ~SOR_ENABLE(sor->index); + tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); tegra_dc_commit(dc); @@ -1994,9 +2098,9 @@ static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) if (err < 0) dev_err(sor->dev, "failed to power down SOR: %d\n", err); - err = tegra_io_rail_power_off(TEGRA_IO_RAIL_HDMI); + err = tegra_io_pad_power_disable(sor->pad); if (err < 0) - dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err); + dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); pm_runtime_put(sor->dev); } @@ -2028,9 +2132,9 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) div = clk_get_rate(sor->clk) / 1000000 * 4; - err = tegra_io_rail_power_on(TEGRA_IO_RAIL_HDMI); + err = tegra_io_pad_power_enable(sor->pad); if (err < 0) - dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err); + dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); usleep_range(20, 100); @@ -2099,10 +2203,19 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; tegra_sor_writel(sor, value, SOR_CLK_CNTRL); + /* SOR pad PLL stabilization time */ + usleep_range(250, 1000); + + value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); + value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; + value |= SOR_DP_LINKCTL_LANE_COUNT(4); + tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); + value = tegra_sor_readl(sor, SOR_DP_SPARE0); - value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; + value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; value &= ~SOR_DP_SPARE_PANEL_INTERNAL; - value |= SOR_DP_SPARE_SEQ_ENABLE; + value &= ~SOR_DP_SPARE_SEQ_ENABLE; + value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; tegra_sor_writel(sor, value, SOR_DP_SPARE0); value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | @@ -2114,9 +2227,11 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); - /* program the reference clock */ - value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); - tegra_sor_writel(sor, value, SOR_REFCLK); + if (!sor->soc->has_nvdisplay) { + /* program the reference clock */ + value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); + tegra_sor_writel(sor, value, SOR_REFCLK); + } /* XXX not in TRM */ for (value = 0, i = 0; i < 5; i++) @@ -2139,13 +2254,16 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) return; } - value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); - /* XXX is this the proper check? */ - if (mode->clock < 75000) - value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; + if (!sor->soc->has_nvdisplay) { + value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); + + /* XXX is this the proper check? */ + if (mode->clock < 75000) + value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; - tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); + tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); + } max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; @@ -2153,20 +2271,23 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); tegra_sor_writel(sor, value, SOR_HDMI_CTRL); - /* H_PULSE2 setup */ - pulse_start = h_ref_to_sync + (mode->hsync_end - mode->hsync_start) + - (mode->htotal - mode->hsync_end) - 10; + if (!dc->soc->has_nvdisplay) { + /* H_PULSE2 setup */ + pulse_start = h_ref_to_sync + + (mode->hsync_end - mode->hsync_start) + + (mode->htotal - mode->hsync_end) - 10; - value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | - PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; - tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); + value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | + PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; + tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); - value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); - tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); + value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); + tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); - value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); - value |= H_PULSE2_ENABLE; - tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); + value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); + value |= H_PULSE2_ENABLE; + tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); + } /* infoframe setup */ err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); @@ -2197,49 +2318,66 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) value = tegra_sor_readl(sor, sor->soc->regs->pll0); value &= ~SOR_PLL0_ICHPMP_MASK; + value &= ~SOR_PLL0_FILTER_MASK; value &= ~SOR_PLL0_VCOCAP_MASK; value |= SOR_PLL0_ICHPMP(settings->ichpmp); + value |= SOR_PLL0_FILTER(settings->filter); value |= SOR_PLL0_VCOCAP(settings->vcocap); tegra_sor_writel(sor, value, sor->soc->regs->pll0); - tegra_sor_dp_term_calibrate(sor); - + /* XXX not in TRM */ value = tegra_sor_readl(sor, sor->soc->regs->pll1); value &= ~SOR_PLL1_LOADADJ_MASK; + value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; value |= SOR_PLL1_LOADADJ(settings->loadadj); + value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); + value |= SOR_PLL1_TMDS_TERM; tegra_sor_writel(sor, value, sor->soc->regs->pll1); value = tegra_sor_readl(sor, sor->soc->regs->pll3); + value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; - value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref); + value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; + value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; + value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); + value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); + value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); + value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); tegra_sor_writel(sor, value, sor->soc->regs->pll3); - value = settings->drive_current[0] << 24 | - settings->drive_current[1] << 16 | - settings->drive_current[2] << 8 | - settings->drive_current[3] << 0; + value = settings->drive_current[3] << 24 | + settings->drive_current[2] << 16 | + settings->drive_current[1] << 8 | + settings->drive_current[0] << 0; tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); - value = settings->preemphasis[0] << 24 | - settings->preemphasis[1] << 16 | - settings->preemphasis[2] << 8 | - settings->preemphasis[3] << 0; + value = settings->preemphasis[3] << 24 | + settings->preemphasis[2] << 16 | + settings->preemphasis[1] << 8 | + settings->preemphasis[0] << 0; tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value &= ~SOR_DP_PADCTL_TX_PU_MASK; value |= SOR_DP_PADCTL_TX_PU_ENABLE; - value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu); + value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); + value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; + value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); + /* power down pad calibration */ value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value |= SOR_DP_PADCTL_PAD_CAL_PD; tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); - /* miscellaneous display controller settings */ - value = VSYNC_H_POSITION(1); - tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); + if (!dc->soc->has_nvdisplay) { + /* miscellaneous display controller settings */ + value = VSYNC_H_POSITION(1); + tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); + } value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); value &= ~DITHER_CONTROL_MASK; @@ -2254,6 +2392,14 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) value |= BASE_COLOR_SIZE_888; break; + case 10: + value |= BASE_COLOR_SIZE_101010; + break; + + case 12: + value |= BASE_COLOR_SIZE_121212; + break; + default: WARN(1, "%u bits-per-color not supported\n", state->bpc); value |= BASE_COLOR_SIZE_888; @@ -2262,6 +2408,12 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); + /* XXX set display head owner */ + value = tegra_sor_readl(sor, SOR_STATE1); + value &= ~SOR_STATE_ASY_OWNER_MASK; + value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); + tegra_sor_writel(sor, value, SOR_STATE1); + err = tegra_sor_power_up(sor, 250); if (err < 0) dev_err(sor->dev, "failed to power up SOR: %d\n", err); @@ -2282,15 +2434,32 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) tegra_sor_update(sor); + /* program preamble timing in SOR (XXX) */ + value = tegra_sor_readl(sor, SOR_DP_SPARE0); + value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; + tegra_sor_writel(sor, value, SOR_DP_SPARE0); + err = tegra_sor_attach(sor); if (err < 0) dev_err(sor->dev, "failed to attach SOR: %d\n", err); /* enable display to SOR clock and generate HDMI preamble */ value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); - value |= SOR1_ENABLE | SOR1_TIMING_CYA; + + if (!sor->soc->has_nvdisplay) + value |= SOR_ENABLE(1) | SOR1_TIMING_CYA; + else + value |= SOR_ENABLE(sor->index); + tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); + if (dc->soc->has_nvdisplay) { + value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); + value &= ~PROTOCOL_MASK; + value |= PROTOCOL_SINGLE_TMDS_A; + tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); + } + tegra_dc_commit(dc); err = tegra_sor_wakeup(sor); @@ -2356,7 +2525,7 @@ static int tegra_sor_init(struct host1x_client *client) return err; } - sor->output.encoder.possible_crtcs = 0x3; + tegra_output_find_possible_crtcs(&sor->output, drm); if (sor->aux) { err = drm_dp_aux_attach(sor->aux, &sor->output); @@ -2526,6 +2695,7 @@ static const struct tegra_sor_soc tegra124_sor = { .supports_hdmi = false, .supports_dp = false, .regs = &tegra124_sor_regs, + .has_nvdisplay = false, .xbar_cfg = tegra124_sor_xbar_cfg, }; @@ -2550,6 +2720,7 @@ static const struct tegra_sor_soc tegra210_sor = { .supports_hdmi = false, .supports_dp = false, .regs = &tegra210_sor_regs, + .has_nvdisplay = false, .xbar_cfg = tegra124_sor_xbar_cfg, }; @@ -2564,6 +2735,7 @@ static const struct tegra_sor_soc tegra210_sor1 = { .supports_dp = true, .regs = &tegra210_sor_regs, + .has_nvdisplay = false, .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), .settings = tegra210_sor_hdmi_defaults, @@ -2571,7 +2743,51 @@ static const struct tegra_sor_soc tegra210_sor1 = { .xbar_cfg = tegra210_sor_xbar_cfg, }; +static const struct tegra_sor_regs tegra186_sor_regs = { + .head_state0 = 0x151, + .head_state1 = 0x154, + .head_state2 = 0x157, + .head_state3 = 0x15a, + .head_state4 = 0x15d, + .head_state5 = 0x160, + .pll0 = 0x163, + .pll1 = 0x164, + .pll2 = 0x165, + .pll3 = 0x166, + .dp_padctl0 = 0x168, + .dp_padctl2 = 0x16a, +}; + +static const struct tegra_sor_soc tegra186_sor = { + .supports_edp = false, + .supports_lvds = false, + .supports_hdmi = false, + .supports_dp = true, + + .regs = &tegra186_sor_regs, + .has_nvdisplay = true, + + .xbar_cfg = tegra124_sor_xbar_cfg, +}; + +static const struct tegra_sor_soc tegra186_sor1 = { + .supports_edp = false, + .supports_lvds = false, + .supports_hdmi = true, + .supports_dp = true, + + .regs = &tegra186_sor_regs, + .has_nvdisplay = true, + + .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults), + .settings = tegra186_sor_hdmi_defaults, + + .xbar_cfg = tegra124_sor_xbar_cfg, +}; + static const struct of_device_id tegra_sor_of_match[] = { + { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 }, + { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, @@ -2579,6 +2795,29 @@ static const struct of_device_id tegra_sor_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra_sor_of_match); +static int tegra_sor_parse_dt(struct tegra_sor *sor) +{ + struct device_node *np = sor->dev->of_node; + u32 value; + int err; + + if (sor->soc->has_nvdisplay) { + err = of_property_read_u32(np, "nvidia,interface", &value); + if (err < 0) + return err; + + sor->index = value; + + /* + * override the default that we already set for Tegra210 and + * earlier + */ + sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; + } + + return 0; +} + static int tegra_sor_probe(struct platform_device *pdev) { struct device_node *np; @@ -2614,6 +2853,7 @@ static int tegra_sor_probe(struct platform_device *pdev) if (!sor->aux) { if (sor->soc->supports_hdmi) { sor->ops = &tegra_sor_hdmi_ops; + sor->pad = TEGRA_IO_PAD_HDMI; } else if (sor->soc->supports_lvds) { dev_err(&pdev->dev, "LVDS not supported yet\n"); return -ENODEV; @@ -2624,6 +2864,7 @@ static int tegra_sor_probe(struct platform_device *pdev) } else { if (sor->soc->supports_edp) { sor->ops = &tegra_sor_edp_ops; + sor->pad = TEGRA_IO_PAD_LVDS; } else if (sor->soc->supports_dp) { dev_err(&pdev->dev, "DisplayPort not supported yet\n"); return -ENODEV; @@ -2633,6 +2874,10 @@ static int tegra_sor_probe(struct platform_device *pdev) } } + err = tegra_sor_parse_dt(sor); + if (err < 0) + return err; + err = tegra_output_probe(&sor->output); if (err < 0) { dev_err(&pdev->dev, "failed to probe output: %d\n", err); diff --git a/drivers/gpu/drm/tegra/sor.h b/drivers/gpu/drm/tegra/sor.h index 865c73b48968..e85ffc8d98e4 100644 --- a/drivers/gpu/drm/tegra/sor.h +++ b/drivers/gpu/drm/tegra/sor.h @@ -89,6 +89,8 @@ #define SOR_PLL0 0x17 #define SOR_PLL0_ICHPMP_MASK (0xf << 24) #define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24) +#define SOR_PLL0_FILTER_MASK (0xf << 16) +#define SOR_PLL0_FILTER(x) (((x) & 0xf) << 16) #define SOR_PLL0_VCOCAP_MASK (0xf << 8) #define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8) #define SOR_PLL0_VCOCAP_RST SOR_PLL0_VCOCAP(3) @@ -122,10 +124,16 @@ #define SOR_PLL2_SEQ_PLL_PULLDOWN (1 << 16) #define SOR_PLL3 0x1a +#define SOR_PLL3_BG_TEMP_COEF_MASK (0xf << 28) +#define SOR_PLL3_BG_TEMP_COEF(x) (((x) & 0xf) << 28) #define SOR_PLL3_BG_VREF_LEVEL_MASK (0xf << 24) #define SOR_PLL3_BG_VREF_LEVEL(x) (((x) & 0xf) << 24) #define SOR_PLL3_PLL_VDD_MODE_1V8 (0 << 13) #define SOR_PLL3_PLL_VDD_MODE_3V3 (1 << 13) +#define SOR_PLL3_AVDD10_LEVEL_MASK (0xf << 8) +#define SOR_PLL3_AVDD10_LEVEL(x) (((x) & 0xf) << 8) +#define SOR_PLL3_AVDD14_LEVEL_MASK (0xf << 4) +#define SOR_PLL3_AVDD14_LEVEL(x) (((x) & 0xf) << 4) #define SOR_CSTM 0x1b #define SOR_CSTM_ROTCLK_MASK (0xf << 24) @@ -334,6 +342,10 @@ #define SOR_DP_LQ_CSTM1 0x70 #define SOR_DP_LQ_CSTM2 0x71 +#define SOR_DP_PADCTL2 0x73 +#define SOR_DP_PADCTL_SPAREPLL_MASK (0xff << 24) +#define SOR_DP_PADCTL_SPAREPLL(x) (((x) & 0xff) << 24) + #define SOR_HDMI_AUDIO_INFOFRAME_CTRL 0x9a #define SOR_HDMI_AUDIO_INFOFRAME_STATUS 0x9b #define SOR_HDMI_AUDIO_INFOFRAME_HEADER 0x9c -- GitLab From 36e90221acf37dd0eb5dee70cd189cc60f2e501a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 12 Oct 2017 19:14:21 +0200 Subject: [PATCH 1380/2547] drm/tegra: sor: Support HDMI 2.0 modes In addition to using the SCDC helpers to enable support for scrambling for HDMI 2.0 modes, take into account the high pixel clocks when programming some of the registers. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 121 ++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/tegra/sor.h | 4 ++ 2 files changed, 119 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 1d7f24df0b10..f6313c4d612e 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "dc.h" #include "drm.h" @@ -350,11 +351,16 @@ struct tegra_sor { struct regulator *avdd_io_supply; struct regulator *vdd_pll_supply; struct regulator *hdmi_supply; + + struct delayed_work scdc; + bool scdc_enabled; }; struct tegra_sor_state { struct drm_connector_state base; + unsigned int link_speed; + unsigned long pclk; unsigned int bpc; }; @@ -1489,10 +1495,6 @@ static enum drm_mode_status tegra_sor_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { - /* HDMI 2.0 modes are not yet supported */ - if (mode->clock > 340000) - return MODE_NOCLOCK; - return MODE_OK; } @@ -1917,6 +1919,18 @@ tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, info = &output->connector.display_info; + /* + * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so + * the pixel clock must be corrected accordingly. + */ + if (pclk >= 340000000) { + state->link_speed = 20; + state->pclk = pclk / 2; + } else { + state->link_speed = 10; + state->pclk = pclk; + } + err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, pclk, 0); if (err < 0) { @@ -2067,6 +2081,81 @@ tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) return NULL; } +static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) +{ + u32 value; + + value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); + value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; + value &= ~SOR_HDMI2_CTRL_SCRAMBLE; + tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); +} + +static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) +{ + struct i2c_adapter *ddc = sor->output.ddc; + + drm_scdc_set_high_tmds_clock_ratio(ddc, false); + drm_scdc_set_scrambling(ddc, false); + + tegra_sor_hdmi_disable_scrambling(sor); +} + +static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) +{ + if (sor->scdc_enabled) { + cancel_delayed_work_sync(&sor->scdc); + tegra_sor_hdmi_scdc_disable(sor); + } +} + +static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) +{ + u32 value; + + value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); + value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; + value |= SOR_HDMI2_CTRL_SCRAMBLE; + tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); +} + +static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) +{ + struct i2c_adapter *ddc = sor->output.ddc; + + drm_scdc_set_high_tmds_clock_ratio(ddc, true); + drm_scdc_set_scrambling(ddc, true); + + tegra_sor_hdmi_enable_scrambling(sor); +} + +static void tegra_sor_hdmi_scdc_work(struct work_struct *work) +{ + struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); + struct i2c_adapter *ddc = sor->output.ddc; + + if (!drm_scdc_get_scrambling_status(ddc)) { + DRM_DEBUG_KMS("SCDC not scrambled\n"); + tegra_sor_hdmi_scdc_enable(sor); + } + + schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); +} + +static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) +{ + struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; + struct drm_display_mode *mode; + + mode = &sor->output.encoder.crtc->state->adjusted_mode; + + if (mode->clock >= 340000 && scdc->supported) { + schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); + tegra_sor_hdmi_scdc_enable(sor); + sor->scdc_enabled = true; + } +} + static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) { struct tegra_output *output = encoder_to_output(encoder); @@ -2075,6 +2164,8 @@ static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) u32 value; int err; + tegra_sor_hdmi_scdc_stop(sor); + err = tegra_sor_detach(sor); if (err < 0) dev_err(sor->dev, "failed to detach SOR: %d\n", err); @@ -2114,12 +2205,14 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) struct tegra_sor *sor = to_sor(output); struct tegra_sor_state *state; struct drm_display_mode *mode; + unsigned long rate, pclk; unsigned int div, i; u32 value; int err; state = to_sor_state(output->connector.state); mode = &encoder->crtc->state->adjusted_mode; + pclk = mode->clock * 1000; pm_runtime_get_sync(sor->dev); @@ -2195,10 +2288,13 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; - if (mode->clock < 340000) + if (mode->clock < 340000) { + DRM_DEBUG_KMS("setting 2.7 GHz link speed\n"); value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; - else + } else { + DRM_DEBUG_KMS("setting 5.4 GHz link speed\n"); value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; + } value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; tegra_sor_writel(sor, value, SOR_CLK_CNTRL); @@ -2254,6 +2350,15 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) return; } + /* adjust clock rate for HDMI 2.0 modes */ + rate = clk_get_rate(sor->clk_parent); + + if (mode->clock >= 340000) + rate /= 2; + + DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk); + + clk_set_rate(sor->clk, rate); if (!sor->soc->has_nvdisplay) { value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); @@ -2465,6 +2570,8 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) err = tegra_sor_wakeup(sor); if (err < 0) dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); + + tegra_sor_hdmi_scdc_start(sor); } static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { @@ -2652,6 +2759,8 @@ static int tegra_sor_hdmi_probe(struct tegra_sor *sor) return err; } + INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); + return 0; } diff --git a/drivers/gpu/drm/tegra/sor.h b/drivers/gpu/drm/tegra/sor.h index e85ffc8d98e4..fb0854d92a27 100644 --- a/drivers/gpu/drm/tegra/sor.h +++ b/drivers/gpu/drm/tegra/sor.h @@ -382,4 +382,8 @@ #define SOR_HDMI_VSI_INFOFRAME_STATUS 0x124 #define SOR_HDMI_VSI_INFOFRAME_HEADER 0x125 +#define SOR_HDMI2_CTRL 0x13e +#define SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4 (1 << 1) +#define SOR_HDMI2_CTRL_SCRAMBLE (1 << 0) + #endif -- GitLab From 82b81b3ec1a796d10206fd8333437db20ef215fc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 12 Oct 2017 17:32:52 +0200 Subject: [PATCH 1381/2547] drm/tegra: dpaux: Implement runtime PM Move clock and reset management into runtime PM callbacks and hook them up. This cleans up the code structure so that power management code does not clutter up the rest. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dpaux.c | 116 ++++++++++++++++++++++------------ 1 file changed, 76 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index e4da041ba89b..2cd671b1a9cc 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -467,52 +468,37 @@ static int tegra_dpaux_probe(struct platform_device *pdev) return PTR_ERR(dpaux->clk); } - err = clk_prepare_enable(dpaux->clk); - if (err < 0) { - dev_err(&pdev->dev, "failed to enable module clock: %d\n", - err); - return err; - } - - if (dpaux->rst) - reset_control_deassert(dpaux->rst); - dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent"); if (IS_ERR(dpaux->clk_parent)) { dev_err(&pdev->dev, "failed to get parent clock: %ld\n", PTR_ERR(dpaux->clk_parent)); - err = PTR_ERR(dpaux->clk_parent); - goto assert_reset; - } - - err = clk_prepare_enable(dpaux->clk_parent); - if (err < 0) { - dev_err(&pdev->dev, "failed to enable parent clock: %d\n", - err); - goto assert_reset; + return PTR_ERR(dpaux->clk_parent); } err = clk_set_rate(dpaux->clk_parent, 270000000); if (err < 0) { dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n", err); - goto disable_parent_clk; + return err; } dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd"); if (IS_ERR(dpaux->vdd)) { dev_err(&pdev->dev, "failed to get VDD supply: %ld\n", PTR_ERR(dpaux->vdd)); - err = PTR_ERR(dpaux->vdd); - goto disable_parent_clk; + return PTR_ERR(dpaux->vdd); } + platform_set_drvdata(pdev, dpaux); + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0, dev_name(dpaux->dev), dpaux); if (err < 0) { dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n", dpaux->irq, err); - goto disable_parent_clk; + return err; } disable_irq(dpaux->irq); @@ -522,7 +508,7 @@ static int tegra_dpaux_probe(struct platform_device *pdev) err = drm_dp_aux_register(&dpaux->aux); if (err < 0) - goto disable_parent_clk; + return err; /* * Assume that by default the DPAUX/I2C pads will be used for HDMI, @@ -560,45 +546,94 @@ static int tegra_dpaux_probe(struct platform_device *pdev) list_add_tail(&dpaux->list, &dpaux_list); mutex_unlock(&dpaux_lock); - platform_set_drvdata(pdev, dpaux); - return 0; - -disable_parent_clk: - clk_disable_unprepare(dpaux->clk_parent); -assert_reset: - if (dpaux->rst) - reset_control_assert(dpaux->rst); - - clk_disable_unprepare(dpaux->clk); - - return err; } static int tegra_dpaux_remove(struct platform_device *pdev) { struct tegra_dpaux *dpaux = platform_get_drvdata(pdev); + cancel_work_sync(&dpaux->work); + /* make sure pads are powered down when not in use */ tegra_dpaux_pad_power_down(dpaux); + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); + drm_dp_aux_unregister(&dpaux->aux); mutex_lock(&dpaux_lock); list_del(&dpaux->list); mutex_unlock(&dpaux_lock); - cancel_work_sync(&dpaux->work); + return 0; +} - clk_disable_unprepare(dpaux->clk_parent); +#ifdef CONFIG_PM +static int tegra_dpaux_suspend(struct device *dev) +{ + struct tegra_dpaux *dpaux = dev_get_drvdata(dev); + int err = 0; + + if (dpaux->rst) { + err = reset_control_assert(dpaux->rst); + if (err < 0) { + dev_err(dev, "failed to assert reset: %d\n", err); + return err; + } + } - if (dpaux->rst) - reset_control_assert(dpaux->rst); + usleep_range(1000, 2000); + clk_disable_unprepare(dpaux->clk_parent); clk_disable_unprepare(dpaux->clk); + return err; +} + +static int tegra_dpaux_resume(struct device *dev) +{ + struct tegra_dpaux *dpaux = dev_get_drvdata(dev); + int err; + + err = clk_prepare_enable(dpaux->clk); + if (err < 0) { + dev_err(dev, "failed to enable clock: %d\n", err); + return err; + } + + err = clk_prepare_enable(dpaux->clk_parent); + if (err < 0) { + dev_err(dev, "failed to enable parent clock: %d\n", err); + goto disable_clk; + } + + usleep_range(1000, 2000); + + if (dpaux->rst) { + err = reset_control_deassert(dpaux->rst); + if (err < 0) { + dev_err(dev, "failed to deassert reset: %d\n", err); + goto disable_parent; + } + + usleep_range(1000, 2000); + } + return 0; + +disable_parent: + clk_disable_unprepare(dpaux->clk_parent); +disable_clk: + clk_disable_unprepare(dpaux->clk); + return err; } +#endif + +static const struct dev_pm_ops tegra_dpaux_pm_ops = { + SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL) +}; static const struct of_device_id tegra_dpaux_of_match[] = { { .compatible = "nvidia,tegra210-dpaux", }, @@ -611,6 +646,7 @@ struct platform_driver tegra_dpaux_driver = { .driver = { .name = "tegra-dpaux", .of_match_table = tegra_dpaux_of_match, + .pm = &tegra_dpaux_pm_ops, }, .probe = tegra_dpaux_probe, .remove = tegra_dpaux_remove, -- GitLab From 7b2c2845e5d59db1d9dfa822436a71b2de18a7ee Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 12 Oct 2017 17:34:11 +0200 Subject: [PATCH 1382/2547] drm/tegra: dpaux: Add Tegra186 support DPAUX is the same as on previous generations. Supporting it is as simple as adding the compatible string so that the driver will bind to any of the devices. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dpaux.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index 2cd671b1a9cc..312b93c0323c 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -636,6 +636,7 @@ static const struct dev_pm_ops tegra_dpaux_pm_ops = { }; static const struct of_device_id tegra_dpaux_of_match[] = { + { .compatible = "nvidia,tegra186-dpaux", }, { .compatible = "nvidia,tegra210-dpaux", }, { .compatible = "nvidia,tegra124-dpaux", }, { }, -- GitLab From 71835caa00e8a64ada3c2e30c56468c39c81f60c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 14 Nov 2017 16:09:30 +0100 Subject: [PATCH 1383/2547] drm/tegra: fb: Force alpha formats Tegra20 and Tegra30 don't actually support the 24-bit RGB formats that don't have an alpha component. In order to allow the fbdev emulation to run on those chips, force the 32-bit RGBA formats. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/fb.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 406e895d82cc..1af4ef9241f1 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -253,6 +253,19 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper, cmd.height = sizes->surface_height; cmd.pitches[0] = round_up(sizes->surface_width * bytes_per_pixel, tegra->pitch_align); + + /* + * Early generations of Tegra (Tegra20 and Tegra30) do not support any + * of the X* or *X formats, only their A* or *A equivalents. Force the + * legacy framebuffer format to include an alpha component so that the + * framebuffer emulation can be supported on all generations. + */ + if (sizes->surface_bpp == 32 && sizes->surface_depth == 24) + sizes->surface_depth = 32; + + if (sizes->surface_bpp == 16 && sizes->surface_depth == 15) + sizes->surface_depth = 16; + cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, sizes->surface_depth); -- GitLab From 4b4df570b41dbb421f52605357d5d56c872df6d9 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 13 Dec 2017 00:44:26 -0800 Subject: [PATCH 1384/2547] drm: Update edid-derived drm_display_info fields at edid property set [v2] There are a set of values in the drm_display_info structure for each connector which hold information derived from EDID. These are computed in drm_add_display_info. Before this patch, that was only called in drm_add_edid_modes. This meant that they were only set when EDID was present and never reset when EDID was not, as happened when the display was disconnected. One of these fields, non_desktop, is used from drm_mode_connector_update_edid_property, the function responsible for assigning the new edid value to the application-visible property. Various drivers call these two functions (drm_add_edid_modes and drm_mode_connector_update_edid_property) in different orders. This means that even when EDID is present, the drm_display_info fields may not have been computed at the time that drm_mode_connector_update_edid_property used the non_desktop value to set the non_desktop property. I've added a public function (drm_reset_display_info) that resets the drm_display_info field values to default values and then made the drm_add_display_info function public. These two functions are now called directly from drm_mode_connector_update_edid_property so that the drm_display_info fields are always computed from the current EDID information before being used in that function. This means that the drm_display_info values are often computed twice, once when the EDID property it set and a second time when EDID is used to compute modes for the device. The alternative would be to uniformly ensure that the values were computed once before being used, which would require that all drivers reliably invoke the two paths in the same order. The computation is inexpensive enough that it seems more maintainable in the long term to simply compute them in both paths. The API to drm_add_display_info has been changed so that it no longer takes the set of edid-based quirks as a parameter. Rather, it now computes those quirks itself and returns them for further use by drm_add_edid_modes. This patch also includes a number of 'const' additions caused by drm_mode_connector_update_edid_property taking a 'const struct edid *' parameter and wanting to pass that along to drm_add_display_info. v2: after review by Daniel Vetter Removed EXPORT_SYMBOL_GPL for drm_reset_display_info and drm_add_display_info. Added FIXME in drm_mode_connector_update_edid_property about potentially merging that with drm_add_edid_modes to avoid the need for two driver calls. Signed-off-by: Keith Packard Reviewed-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171213084427.31199-1-keithp@keithp.com (danvet: cherry picked from commit 12a889bf4bca ("drm: rework delayed connector cleanup in connector_iter") from drm-misc-next since functional conflict with changes in -next and we need to make sure both have the right version and nothing gets lost.) Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_connector.c | 13 +++++++++ drivers/gpu/drm/drm_edid.c | 52 ++++++++++++++++++++++++--------- include/drm/drm_edid.h | 2 ++ 3 files changed, 53 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index 482014137953..c4dfcbc861a1 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -1231,6 +1231,19 @@ int drm_mode_connector_update_edid_property(struct drm_connector *connector, if (edid) size = EDID_LENGTH * (1 + edid->extensions); + /* Set the display info, using edid if available, otherwise + * reseting the values to defaults. This duplicates the work + * done in drm_add_edid_modes, but that function is not + * consistently called before this one in all drivers and the + * computation is cheap enough that it seems better to + * duplicate it rather than attempt to ensure some arbitrary + * ordering of calls. + */ + if (edid) + drm_add_display_info(connector, edid); + else + drm_reset_display_info(connector); + drm_object_property_set_value(&connector->base, dev->mode_config.non_desktop_property, connector->display_info.non_desktop); diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 5dfe14763871..cb487148359a 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1731,7 +1731,7 @@ EXPORT_SYMBOL(drm_edid_duplicate); * * Returns true if @vendor is in @edid, false otherwise */ -static bool edid_vendor(struct edid *edid, const char *vendor) +static bool edid_vendor(const struct edid *edid, const char *vendor) { char edid_vendor[3]; @@ -1749,7 +1749,7 @@ static bool edid_vendor(struct edid *edid, const char *vendor) * * This tells subsequent routines what fixes they need to apply. */ -static u32 edid_get_quirks(struct edid *edid) +static u32 edid_get_quirks(const struct edid *edid) { const struct edid_quirk *quirk; int i; @@ -2813,7 +2813,7 @@ add_detailed_modes(struct drm_connector *connector, struct edid *edid, /* * Search EDID for CEA extension block. */ -static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) +static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) { u8 *edid_ext = NULL; int i; @@ -2835,12 +2835,12 @@ static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) return edid_ext; } -static u8 *drm_find_cea_extension(struct edid *edid) +static u8 *drm_find_cea_extension(const struct edid *edid) { return drm_find_edid_extension(edid, CEA_EXT); } -static u8 *drm_find_displayid_extension(struct edid *edid) +static u8 *drm_find_displayid_extension(const struct edid *edid) { return drm_find_edid_extension(edid, DISPLAYID_EXT); } @@ -4363,7 +4363,7 @@ drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) } static void drm_parse_cea_ext(struct drm_connector *connector, - struct edid *edid) + const struct edid *edid) { struct drm_display_info *info = &connector->display_info; const u8 *edid_ext; @@ -4397,11 +4397,33 @@ static void drm_parse_cea_ext(struct drm_connector *connector, } } -static void drm_add_display_info(struct drm_connector *connector, - struct edid *edid, u32 quirks) +/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset + * all of the values which would have been set from EDID + */ +void +drm_reset_display_info(struct drm_connector *connector) { struct drm_display_info *info = &connector->display_info; + info->width_mm = 0; + info->height_mm = 0; + + info->bpc = 0; + info->color_formats = 0; + info->cea_rev = 0; + info->max_tmds_clock = 0; + info->dvi_dual = false; + + info->non_desktop = 0; +} +EXPORT_SYMBOL_GPL(drm_reset_display_info); + +u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) +{ + struct drm_display_info *info = &connector->display_info; + + u32 quirks = edid_get_quirks(edid); + info->width_mm = edid->width_cm * 10; info->height_mm = edid->height_cm * 10; @@ -4414,11 +4436,13 @@ static void drm_add_display_info(struct drm_connector *connector, info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); + DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); + if (edid->revision < 3) - return; + return quirks; if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) - return; + return quirks; drm_parse_cea_ext(connector, edid); @@ -4438,7 +4462,7 @@ static void drm_add_display_info(struct drm_connector *connector, /* Only defined for 1.4 with digital displays */ if (edid->revision < 4) - return; + return quirks; switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { case DRM_EDID_DIGITAL_DEPTH_6: @@ -4473,7 +4497,9 @@ static void drm_add_display_info(struct drm_connector *connector, info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; + return quirks; } +EXPORT_SYMBOL_GPL(drm_add_display_info); static int validate_displayid(u8 *displayid, int length, int idx) { @@ -4627,14 +4653,12 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) return 0; } - quirks = edid_get_quirks(edid); - /* * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. * To avoid multiple parsing of same block, lets parse that map * from sink info, before parsing CEA modes. */ - drm_add_display_info(connector, edid, quirks); + quirks = drm_add_display_info(connector, edid); /* * EDID spec says modes should be preferred in this order: diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 2ec41d032e56..efe6d5a8e834 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -465,6 +465,8 @@ struct edid *drm_get_edid(struct drm_connector *connector, struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, struct i2c_adapter *adapter); struct edid *drm_edid_duplicate(const struct edid *edid); +void drm_reset_display_info(struct drm_connector *connector); +u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid); int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); u8 drm_match_cea_mode(const struct drm_display_mode *to_match); -- GitLab From 366d8216488319ed29308b977cd62b7964a779b7 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 13 Dec 2017 09:21:59 +0100 Subject: [PATCH 1385/2547] s390/sclp: disable FORTIFY_SOURCE for early sclp code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Michal Suchánek reported the following compile error with FORTIFY_SOURCE enabled: drivers/s390/char/sclp_early_core.o: In function `memcpy': include/linux/string.h:340: undefined reference to `fortify_panic' To fix this simply disable FORTIFY_SOURCE on the early sclp code as well, which I forgot on the initial commit. Fixes: 79962038dffa ("s390: add support for FORTIFY_SOURCE") Reported-by: Michal Suchánek Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky --- drivers/s390/char/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/s390/char/Makefile b/drivers/s390/char/Makefile index 05ac6ba15a53..614b44e70a28 100644 --- a/drivers/s390/char/Makefile +++ b/drivers/s390/char/Makefile @@ -17,6 +17,8 @@ CFLAGS_REMOVE_sclp_early_core.o += $(CC_FLAGS_MARCH) CFLAGS_sclp_early_core.o += -march=z900 endif +CFLAGS_sclp_early_core.o += -D__NO_FORTIFY + obj-y += ctrlchar.o keyboard.o defkeymap.o sclp.o sclp_rw.o sclp_quiesce.o \ sclp_cmd.o sclp_config.o sclp_cpi_sys.o sclp_ocf.o sclp_ctl.o \ sclp_early.o sclp_early_core.o -- GitLab From 3a9016ba0e8f3cf4196eae99b5b18172c9b71045 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 2 Nov 2017 09:33:45 +0000 Subject: [PATCH 1386/2547] drm/msm: fix spelling mistake: "ringubffer" -> "ringbuffer" Trivial fix to spelling mistake in DRM_DEV_ERROR error message Signed-off-by: Colin Ian King Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index e2ffecce59a3..2f0610f8fc8d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -461,7 +461,7 @@ void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) { if (spin_until(ring_freewords(ring) >= ndwords)) DRM_DEV_ERROR(ring->gpu->dev->dev, - "timeout waiting for space in ringubffer %d\n", + "timeout waiting for space in ringbuffer %d\n", ring->id); } -- GitLab From e6756d7c1a7ebe04def1b24b45ce01ef6c4175bc Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 2 Nov 2017 12:21:32 +0100 Subject: [PATCH 1387/2547] drm/msm: fix msm_rd_dump_submit prototype The prototype of msm_rd_dump_submit() has recently changed. However, we have two declarations of this functions, and the other one remains the old version, leading to this: drivers/gpu/drm/msm/msm_gpu.c: In function 'recover_worker': drivers/gpu/drm/msm/msm_gpu.c:295:23: error: passing argument 1 of 'msm_rd_dump_submit' from incompatible pointer type [-Werror=incompatible-pointer-types] This changes the second one to match the first again. Fixes: 2165e2b9cba2 ("drm/msm: split rd debugfs file") Signed-off-by: Arnd Bergmann Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_drv.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index c646843d8822..0a653dd2e618 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -303,7 +303,8 @@ int msm_perf_debugfs_init(struct drm_minor *minor); void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); #else static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } -static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {} +static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, + const char *fmt, ...) {} static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} #endif -- GitLab From 2d2bccef7192fcb18cc447c1dbbb0e059116b8e7 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 13 Nov 2017 12:53:53 -0500 Subject: [PATCH 1388/2547] drm/msm: free kstrdup'd cmdline Fixes: 18bb8a6 'drm/msm: show task cmdline in gpu recovery messages' Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_gpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 232201403439..a335ad43c4eb 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -294,6 +294,8 @@ static void recover_worker(struct work_struct *work) msm_rd_dump_submit(priv->hangrd, submit, "offending task: %s (%s)", task->comm, cmd); + + kfree(cmd); } else { msm_rd_dump_submit(priv->hangrd, submit, NULL); } -- GitLab From 73fc251f66bce75d652726a20a1f81877d32560a Mon Sep 17 00:00:00 2001 From: Nicolas Dechesne Date: Thu, 23 Nov 2017 11:32:49 +0100 Subject: [PATCH 1389/2547] drm/msm: update adreno firmware path in MODULE_FIRMWARE The preferred location for Adreno firmware files is now in qcom/ subfolder, especially now that we are adding some of them in linux-firmware. Reported-by: Ben Hutchings Signed-off-by: Nicolas Dechesne Reviewed-by: Rob Clark Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_device.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 05022ea2a007..3c1d23b9ddc3 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -90,14 +90,14 @@ static const struct adreno_info gpulist[] = { }, }; -MODULE_FIRMWARE("a300_pm4.fw"); -MODULE_FIRMWARE("a300_pfp.fw"); -MODULE_FIRMWARE("a330_pm4.fw"); -MODULE_FIRMWARE("a330_pfp.fw"); -MODULE_FIRMWARE("a420_pm4.fw"); -MODULE_FIRMWARE("a420_pfp.fw"); -MODULE_FIRMWARE("a530_fm4.fw"); -MODULE_FIRMWARE("a530_pfp.fw"); +MODULE_FIRMWARE("qcom/a300_pm4.fw"); +MODULE_FIRMWARE("qcom/a300_pfp.fw"); +MODULE_FIRMWARE("qcom/a330_pm4.fw"); +MODULE_FIRMWARE("qcom/a330_pfp.fw"); +MODULE_FIRMWARE("qcom/a420_pm4.fw"); +MODULE_FIRMWARE("qcom/a420_pfp.fw"); +MODULE_FIRMWARE("qcom/a530_fm4.fw"); +MODULE_FIRMWARE("qcom/a530_pfp.fw"); static inline bool _rev_match(uint8_t entry, uint8_t id) { -- GitLab From ad40dfdcfd52abb4038db3bf0676296286655e12 Mon Sep 17 00:00:00 2001 From: Nicolas Dechesne Date: Thu, 23 Nov 2017 20:49:48 +0100 Subject: [PATCH 1390/2547] drm/msm: add missing MODULE_FIRMWARE declarations * some a5xx files were missing * fixup for an existing typo Signed-off-by: Nicolas Dechesne Reviewed-by: Rob Clark Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_device.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 3c1d23b9ddc3..ef4baa919135 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -96,8 +96,13 @@ MODULE_FIRMWARE("qcom/a330_pm4.fw"); MODULE_FIRMWARE("qcom/a330_pfp.fw"); MODULE_FIRMWARE("qcom/a420_pm4.fw"); MODULE_FIRMWARE("qcom/a420_pfp.fw"); -MODULE_FIRMWARE("qcom/a530_fm4.fw"); +MODULE_FIRMWARE("qcom/a530_pm4.fw"); MODULE_FIRMWARE("qcom/a530_pfp.fw"); +MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); +MODULE_FIRMWARE("qcom/a530_zap.mdt"); +MODULE_FIRMWARE("qcom/a530_zap.b00"); +MODULE_FIRMWARE("qcom/a530_zap.b01"); +MODULE_FIRMWARE("qcom/a530_zap.b02"); static inline bool _rev_match(uint8_t entry, uint8_t id) { -- GitLab From 8dcbde0f230594eada5646191bdb4a29be1876f6 Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Sat, 25 Nov 2017 11:10:19 +0100 Subject: [PATCH 1391/2547] drm/msm/mdp4: Deduplicate bus_find_device() by name matching No need to reinvent the wheel, we have bus_find_device_by_name(). Signed-off-by: Lukas Wunner Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h index 940de51ac5cd..a1b3e31e959e 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h @@ -234,10 +234,6 @@ static inline struct clk *mpd4_lvds_pll_init(struct drm_device *dev) #endif #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING -static inline int match_dev_name(struct device *dev, void *data) -{ - return !strcmp(dev_name(dev), data); -} /* bus scaling data is associated with extra pointless platform devices, * "dtv", etc.. this is a bit of a hack, but we need a way for encoders * to find their pdata to make the bus-scaling stuff work. @@ -245,8 +241,7 @@ static inline int match_dev_name(struct device *dev, void *data) static inline void *mdp4_find_pdata(const char *devname) { struct device *dev; - dev = bus_find_device(&platform_bus_type, NULL, - (void *)devname, match_dev_name); + dev = bus_find_device_by_name(&platform_bus_type, NULL, devname); return dev ? dev->platform_data : NULL; } #endif -- GitLab From a1ed6def4410451eeb2ce85b4270e6fe9d3c902c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 4 Dec 2017 15:44:23 +0100 Subject: [PATCH 1392/2547] drm/msm: avoid false-positive -Wmaybe-uninitialized warning gcc-8 -fsanitize-coverage=trace-pc produces a false-positive warning: drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c: In function 'mdp5_plane_mode_set.isra.8': drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c:1053:3: error: 'crtc_x_r' may be used uninitialized in this function [-Werror=maybe-uninitialized] It's relatively clear from reading the source that this cannot happen, and older compilers get it right. This rearranges the code remove the two affected variables, which reliably avoids the problem. Signed-off-by: Arnd Bergmann Acked-by: Laurent Pinchart Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c index ee41423baeb7..29678876fc09 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c @@ -966,8 +966,6 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, uint32_t src_x, src_y; uint32_t src_w, src_h; uint32_t src_img_w, src_img_h; - uint32_t src_x_r; - int crtc_x_r; int ret; nplanes = fb->format->num_planes; @@ -1012,9 +1010,6 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, crtc_w /= 2; src_w /= 2; src_img_w /= 2; - - crtc_x_r = crtc_x + crtc_w; - src_x_r = src_x + src_w; } ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x); @@ -1054,9 +1049,9 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, if (right_hwpipe) mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe, config, hdecm, vdecm, hflip, vflip, - crtc_x_r, crtc_y, crtc_w, crtc_h, + crtc_x + crtc_w, crtc_y, crtc_w, crtc_h, src_img_w, src_img_h, - src_x_r, src_y, src_w, src_h); + src_x + src_w, src_y, src_w, src_h); plane->fb = fb; -- GitLab From 62e3a3e342af3c313ab38603811ecdb1fcc79edb Mon Sep 17 00:00:00 2001 From: Prakash Kamliya Date: Mon, 4 Dec 2017 19:10:15 +0530 Subject: [PATCH 1393/2547] drm/msm: fix leak in failed get_pages get_pages doesn't keep a reference of the pages allocated when it fails later in the code path. This can lead to a memory leak. Keep reference of the allocated pages so that it can be freed when msm_gem_free_object gets called later during cleanup. Signed-off-by: Prakash Kamliya Signed-off-by: Sharat Masetty Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_gem.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 81fe6d6740ce..07376de9ff4c 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -93,14 +93,17 @@ static struct page **get_pages(struct drm_gem_object *obj) return p; } + msm_obj->pages = p; + msm_obj->sgt = drm_prime_pages_to_sg(p, npages); if (IS_ERR(msm_obj->sgt)) { + void *ptr = ERR_CAST(msm_obj->sgt); + dev_err(dev->dev, "failed to allocate sgt\n"); - return ERR_CAST(msm_obj->sgt); + msm_obj->sgt = NULL; + return ptr; } - msm_obj->pages = p; - /* For non-cached buffers, ensure the new pages are clean * because display controller, GPU, etc. are not coherent: */ @@ -135,7 +138,10 @@ static void put_pages(struct drm_gem_object *obj) if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED)) dma_unmap_sg(obj->dev->dev, msm_obj->sgt->sgl, msm_obj->sgt->nents, DMA_BIDIRECTIONAL); - sg_free_table(msm_obj->sgt); + + if (msm_obj->sgt) + sg_free_table(msm_obj->sgt); + kfree(msm_obj->sgt); if (use_pages(obj)) -- GitLab From 6b782f43d34974c7909306fd9af06241d658a1f7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 11 Dec 2017 09:54:09 +0100 Subject: [PATCH 1394/2547] Revert "ravb: add workaround for clock when resuming with WoL enabled" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit fbf3d034f2ff6264183cfa6845770e8cc2a986c8. As of commit 560869100b99a3da ("clk: renesas: cpg-mssr: Restore module clocks during resume"), the workaround is no longer needed. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Acked-by: Sergei Shtylyov Signed-off-by: David S. Miller --- drivers/net/ethernet/renesas/ravb_main.c | 27 ++---------------------- 1 file changed, 2 insertions(+), 25 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 2b962d349f5f..009780df664b 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2308,32 +2308,9 @@ static int __maybe_unused ravb_resume(struct device *dev) struct ravb_private *priv = netdev_priv(ndev); int ret = 0; - if (priv->wol_enabled) { - /* Reduce the usecount of the clock to zero and then - * restore it to its original value. This is done to force - * the clock to be re-enabled which is a workaround - * for renesas-cpg-mssr driver which do not enable clocks - * when resuming from PSCI suspend/resume. - * - * Without this workaround the driver fails to communicate - * with the hardware if WoL was enabled when the system - * entered PSCI suspend. This is due to that if WoL is enabled - * we explicitly keep the clock from being turned off when - * suspending, but in PSCI sleep power is cut so the clock - * is disabled anyhow, the clock driver is not aware of this - * so the clock is not turned back on when resuming. - * - * TODO: once the renesas-cpg-mssr suspend/resume is working - * this clock dance should be removed. - */ - clk_disable(priv->clk); - clk_disable(priv->clk); - clk_enable(priv->clk); - clk_enable(priv->clk); - - /* Set reset mode to rearm the WoL logic */ + /* If WoL is enabled set reset mode to rearm the WoL logic */ + if (priv->wol_enabled) ravb_write(ndev, CCC_OPC_RESET, CCC); - } /* All register have been reset to default values. * Restore all registers which where setup at probe time and -- GitLab From 9d98e19ba08f6aa33a4a1414f3dfe8440e67530c Mon Sep 17 00:00:00 2001 From: Yuval Shaia Date: Wed, 13 Dec 2017 12:25:19 +0200 Subject: [PATCH 1395/2547] IB/ipoib: Restore MM behavior in case of tx_ring allocation failure memalloc_noio_save modifies the behavior of MM, we must restore it after we are done. Fixes: d83187dda9b9 ("IB/IPoIB: Convert IPoIB to memalloc_noio_* calls") Signed-off-by: Yuval Shaia Signed-off-by: Jason Gunthorpe --- drivers/infiniband/ulp/ipoib/ipoib_cm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/infiniband/ulp/ipoib/ipoib_cm.c b/drivers/infiniband/ulp/ipoib/ipoib_cm.c index 87f4bd99cdf7..2c13123bfd69 100644 --- a/drivers/infiniband/ulp/ipoib/ipoib_cm.c +++ b/drivers/infiniband/ulp/ipoib/ipoib_cm.c @@ -1145,6 +1145,7 @@ static int ipoib_cm_tx_init(struct ipoib_cm_tx *p, u32 qpn, noio_flag = memalloc_noio_save(); p->tx_ring = vzalloc(ipoib_sendq_size * sizeof(*p->tx_ring)); if (!p->tx_ring) { + memalloc_noio_restore(noio_flag); ret = -ENOMEM; goto err_tx; } -- GitLab From b9b312a7a451e9c098921856e7cfbc201120e1a7 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Mon, 11 Dec 2017 07:03:38 -0800 Subject: [PATCH 1396/2547] ipv6: mcast: better catch silly mtu values syzkaller reported crashes in IPv6 stack [1] Xin Long found that lo MTU was set to silly values. IPv6 stack reacts to changes to small MTU, by disabling itself under RTNL. But there is a window where threads not using RTNL can see a wrong device mtu. This can lead to surprises, in mld code where it is assumed the mtu is suitable. Fix this by reading device mtu once and checking IPv6 minimal MTU. [1] skbuff: skb_over_panic: text:0000000010b86b8d len:196 put:20 head:000000003b477e60 data:000000000e85441e tail:0xd4 end:0xc0 dev:lo ------------[ cut here ]------------ kernel BUG at net/core/skbuff.c:104! invalid opcode: 0000 [#1] SMP KASAN Dumping ftrace buffer: (ftrace buffer empty) Modules linked in: CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.15.0-rc2-mm1+ #39 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 RIP: 0010:skb_panic+0x15c/0x1f0 net/core/skbuff.c:100 RSP: 0018:ffff8801db307508 EFLAGS: 00010286 RAX: 0000000000000082 RBX: ffff8801c517e840 RCX: 0000000000000000 RDX: 0000000000000082 RSI: 1ffff1003b660e61 RDI: ffffed003b660e95 RBP: ffff8801db307570 R08: 1ffff1003b660e23 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000000 R12: ffffffff85bd4020 R13: ffffffff84754ed2 R14: 0000000000000014 R15: ffff8801c4e26540 FS: 0000000000000000(0000) GS:ffff8801db300000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000463610 CR3: 00000001c6698000 CR4: 00000000001406e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: skb_over_panic net/core/skbuff.c:109 [inline] skb_put+0x181/0x1c0 net/core/skbuff.c:1694 add_grhead.isra.24+0x42/0x3b0 net/ipv6/mcast.c:1695 add_grec+0xa55/0x1060 net/ipv6/mcast.c:1817 mld_send_cr net/ipv6/mcast.c:1903 [inline] mld_ifc_timer_expire+0x4d2/0x770 net/ipv6/mcast.c:2448 call_timer_fn+0x23b/0x840 kernel/time/timer.c:1320 expire_timers kernel/time/timer.c:1357 [inline] __run_timers+0x7e1/0xb60 kernel/time/timer.c:1660 run_timer_softirq+0x4c/0xb0 kernel/time/timer.c:1686 __do_softirq+0x29d/0xbb2 kernel/softirq.c:285 invoke_softirq kernel/softirq.c:365 [inline] irq_exit+0x1d3/0x210 kernel/softirq.c:405 exiting_irq arch/x86/include/asm/apic.h:540 [inline] smp_apic_timer_interrupt+0x16b/0x700 arch/x86/kernel/apic/apic.c:1052 apic_timer_interrupt+0xa9/0xb0 arch/x86/entry/entry_64.S:920 Signed-off-by: Eric Dumazet Reported-by: syzbot Tested-by: Xin Long Signed-off-by: David S. Miller --- net/ipv6/mcast.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/net/ipv6/mcast.c b/net/ipv6/mcast.c index fc6d7d143f2c..844642682b83 100644 --- a/net/ipv6/mcast.c +++ b/net/ipv6/mcast.c @@ -1682,16 +1682,16 @@ static int grec_size(struct ifmcaddr6 *pmc, int type, int gdel, int sdel) } static struct sk_buff *add_grhead(struct sk_buff *skb, struct ifmcaddr6 *pmc, - int type, struct mld2_grec **ppgr) + int type, struct mld2_grec **ppgr, unsigned int mtu) { - struct net_device *dev = pmc->idev->dev; struct mld2_report *pmr; struct mld2_grec *pgr; - if (!skb) - skb = mld_newpack(pmc->idev, dev->mtu); - if (!skb) - return NULL; + if (!skb) { + skb = mld_newpack(pmc->idev, mtu); + if (!skb) + return NULL; + } pgr = skb_put(skb, sizeof(struct mld2_grec)); pgr->grec_type = type; pgr->grec_auxwords = 0; @@ -1714,10 +1714,15 @@ static struct sk_buff *add_grec(struct sk_buff *skb, struct ifmcaddr6 *pmc, struct mld2_grec *pgr = NULL; struct ip6_sf_list *psf, *psf_next, *psf_prev, **psf_list; int scount, stotal, first, isquery, truncate; + unsigned int mtu; if (pmc->mca_flags & MAF_NOREPORT) return skb; + mtu = READ_ONCE(dev->mtu); + if (mtu < IPV6_MIN_MTU) + return skb; + isquery = type == MLD2_MODE_IS_INCLUDE || type == MLD2_MODE_IS_EXCLUDE; truncate = type == MLD2_MODE_IS_EXCLUDE || @@ -1738,7 +1743,7 @@ static struct sk_buff *add_grec(struct sk_buff *skb, struct ifmcaddr6 *pmc, AVAILABLE(skb) < grec_size(pmc, type, gdeleted, sdeleted)) { if (skb) mld_sendpack(skb); - skb = mld_newpack(idev, dev->mtu); + skb = mld_newpack(idev, mtu); } } first = 1; @@ -1774,12 +1779,12 @@ static struct sk_buff *add_grec(struct sk_buff *skb, struct ifmcaddr6 *pmc, pgr->grec_nsrcs = htons(scount); if (skb) mld_sendpack(skb); - skb = mld_newpack(idev, dev->mtu); + skb = mld_newpack(idev, mtu); first = 1; scount = 0; } if (first) { - skb = add_grhead(skb, pmc, type, &pgr); + skb = add_grhead(skb, pmc, type, &pgr, mtu); first = 0; } if (!skb) @@ -1814,7 +1819,7 @@ static struct sk_buff *add_grec(struct sk_buff *skb, struct ifmcaddr6 *pmc, mld_sendpack(skb); skb = NULL; /* add_grhead will get a new one */ } - skb = add_grhead(skb, pmc, type, &pgr); + skb = add_grhead(skb, pmc, type, &pgr, mtu); } } if (pgr) -- GitLab From b5476022bbada3764609368f03329ca287528dc8 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Mon, 11 Dec 2017 07:17:39 -0800 Subject: [PATCH 1397/2547] ipv4: igmp: guard against silly MTU values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit IPv4 stack reacts to changes to small MTU, by disabling itself under RTNL. But there is a window where threads not using RTNL can see a wrong device mtu. This can lead to surprises, in igmp code where it is assumed the mtu is suitable. Fix this by reading device mtu once and checking IPv4 minimal MTU. This patch adds missing IPV4_MIN_MTU define, to not abuse ETH_MIN_MTU anymore. Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller --- include/net/ip.h | 1 + net/ipv4/devinet.c | 2 +- net/ipv4/igmp.c | 24 +++++++++++++++--------- net/ipv4/ip_tunnel.c | 4 ++-- 4 files changed, 19 insertions(+), 12 deletions(-) diff --git a/include/net/ip.h b/include/net/ip.h index 9896f46cbbf1..af8addbaa3c1 100644 --- a/include/net/ip.h +++ b/include/net/ip.h @@ -34,6 +34,7 @@ #include #define IPV4_MAX_PMTU 65535U /* RFC 2675, Section 5.1 */ +#define IPV4_MIN_MTU 68 /* RFC 791 */ struct sock; diff --git a/net/ipv4/devinet.c b/net/ipv4/devinet.c index a4573bccd6da..7a93359fbc72 100644 --- a/net/ipv4/devinet.c +++ b/net/ipv4/devinet.c @@ -1428,7 +1428,7 @@ static void inetdev_changename(struct net_device *dev, struct in_device *in_dev) static bool inetdev_valid_mtu(unsigned int mtu) { - return mtu >= 68; + return mtu >= IPV4_MIN_MTU; } static void inetdev_send_gratuitous_arp(struct net_device *dev, diff --git a/net/ipv4/igmp.c b/net/ipv4/igmp.c index d1f8f302dbf3..50448a220a1f 100644 --- a/net/ipv4/igmp.c +++ b/net/ipv4/igmp.c @@ -404,16 +404,17 @@ static int grec_size(struct ip_mc_list *pmc, int type, int gdel, int sdel) } static struct sk_buff *add_grhead(struct sk_buff *skb, struct ip_mc_list *pmc, - int type, struct igmpv3_grec **ppgr) + int type, struct igmpv3_grec **ppgr, unsigned int mtu) { struct net_device *dev = pmc->interface->dev; struct igmpv3_report *pih; struct igmpv3_grec *pgr; - if (!skb) - skb = igmpv3_newpack(dev, dev->mtu); - if (!skb) - return NULL; + if (!skb) { + skb = igmpv3_newpack(dev, mtu); + if (!skb) + return NULL; + } pgr = skb_put(skb, sizeof(struct igmpv3_grec)); pgr->grec_type = type; pgr->grec_auxwords = 0; @@ -436,12 +437,17 @@ static struct sk_buff *add_grec(struct sk_buff *skb, struct ip_mc_list *pmc, struct igmpv3_grec *pgr = NULL; struct ip_sf_list *psf, *psf_next, *psf_prev, **psf_list; int scount, stotal, first, isquery, truncate; + unsigned int mtu; if (pmc->multiaddr == IGMP_ALL_HOSTS) return skb; if (ipv4_is_local_multicast(pmc->multiaddr) && !net->ipv4.sysctl_igmp_llm_reports) return skb; + mtu = READ_ONCE(dev->mtu); + if (mtu < IPV4_MIN_MTU) + return skb; + isquery = type == IGMPV3_MODE_IS_INCLUDE || type == IGMPV3_MODE_IS_EXCLUDE; truncate = type == IGMPV3_MODE_IS_EXCLUDE || @@ -462,7 +468,7 @@ static struct sk_buff *add_grec(struct sk_buff *skb, struct ip_mc_list *pmc, AVAILABLE(skb) < grec_size(pmc, type, gdeleted, sdeleted)) { if (skb) igmpv3_sendpack(skb); - skb = igmpv3_newpack(dev, dev->mtu); + skb = igmpv3_newpack(dev, mtu); } } first = 1; @@ -498,12 +504,12 @@ static struct sk_buff *add_grec(struct sk_buff *skb, struct ip_mc_list *pmc, pgr->grec_nsrcs = htons(scount); if (skb) igmpv3_sendpack(skb); - skb = igmpv3_newpack(dev, dev->mtu); + skb = igmpv3_newpack(dev, mtu); first = 1; scount = 0; } if (first) { - skb = add_grhead(skb, pmc, type, &pgr); + skb = add_grhead(skb, pmc, type, &pgr, mtu); first = 0; } if (!skb) @@ -538,7 +544,7 @@ static struct sk_buff *add_grec(struct sk_buff *skb, struct ip_mc_list *pmc, igmpv3_sendpack(skb); skb = NULL; /* add_grhead will get a new one */ } - skb = add_grhead(skb, pmc, type, &pgr); + skb = add_grhead(skb, pmc, type, &pgr, mtu); } } if (pgr) diff --git a/net/ipv4/ip_tunnel.c b/net/ipv4/ip_tunnel.c index fe6fee728ce4..5ddb1cb52bd4 100644 --- a/net/ipv4/ip_tunnel.c +++ b/net/ipv4/ip_tunnel.c @@ -349,8 +349,8 @@ static int ip_tunnel_bind_dev(struct net_device *dev) dev->needed_headroom = t_hlen + hlen; mtu -= (dev->hard_header_len + t_hlen); - if (mtu < 68) - mtu = 68; + if (mtu < IPV4_MIN_MTU) + mtu = IPV4_MIN_MTU; return mtu; } -- GitLab From 83593010d3b87601e775f240ce46c53ddf25828d Mon Sep 17 00:00:00 2001 From: Pravin Shedge Date: Mon, 11 Dec 2017 22:09:46 +0530 Subject: [PATCH 1398/2547] net: remove duplicate includes These duplicate includes have been found with scripts/checkincludes.pl but they have been removed manually to avoid removing false positives. Signed-off-by: Pravin Shedge Acked-by: Pablo Neira Ayuso Signed-off-by: David S. Miller --- net/core/netprio_cgroup.c | 1 - net/dsa/slave.c | 1 - net/netfilter/nf_conntrack_netlink.c | 1 - net/sched/act_meta_mark.c | 1 - net/sched/act_meta_skbtcindex.c | 1 - net/sched/cls_api.c | 1 - net/sched/cls_u32.c | 1 - 7 files changed, 7 deletions(-) diff --git a/net/core/netprio_cgroup.c b/net/core/netprio_cgroup.c index 1c4810919a0a..b9057478d69c 100644 --- a/net/core/netprio_cgroup.c +++ b/net/core/netprio_cgroup.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/net/dsa/slave.c b/net/dsa/slave.c index d6e7a642493b..a95a55f79137 100644 --- a/net/dsa/slave.c +++ b/net/dsa/slave.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c index 59c08997bfdf..332b51870ed7 100644 --- a/net/netfilter/nf_conntrack_netlink.c +++ b/net/netfilter/nf_conntrack_netlink.c @@ -45,7 +45,6 @@ #include #include #include -#include #include #ifdef CONFIG_NF_NAT_NEEDED #include diff --git a/net/sched/act_meta_mark.c b/net/sched/act_meta_mark.c index 1e3f10e5da99..6445184b2759 100644 --- a/net/sched/act_meta_mark.c +++ b/net/sched/act_meta_mark.c @@ -22,7 +22,6 @@ #include #include #include -#include static int skbmark_encode(struct sk_buff *skb, void *skbdata, struct tcf_meta_info *e) diff --git a/net/sched/act_meta_skbtcindex.c b/net/sched/act_meta_skbtcindex.c index 2ea1f26c9e96..7221437ca3a6 100644 --- a/net/sched/act_meta_skbtcindex.c +++ b/net/sched/act_meta_skbtcindex.c @@ -22,7 +22,6 @@ #include #include #include -#include static int skbtcindex_encode(struct sk_buff *skb, void *skbdata, struct tcf_meta_info *e) diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c index ddcf04b4ab43..f40256a3e7f0 100644 --- a/net/sched/cls_api.c +++ b/net/sched/cls_api.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/net/sched/cls_u32.c b/net/sched/cls_u32.c index ac152b4f4247..507859cdd1cb 100644 --- a/net/sched/cls_u32.c +++ b/net/sched/cls_u32.c @@ -45,7 +45,6 @@ #include #include #include -#include #include struct tc_u_knode { -- GitLab From c545a945d0d9ea2ea2c7d23d43cf0d86e32cd7cf Mon Sep 17 00:00:00 2001 From: Jon Maloy Date: Mon, 11 Dec 2017 19:11:55 +0100 Subject: [PATCH 1399/2547] tipc: eliminate potential memory leak In the function tipc_sk_mcast_rcv() we call refcount_dec(&skb->users) on received sk_buffers. Since the reference counter might hit zero at this point, we have a potential memory leak. We fix this by replacing refcount_dec() with kfree_skb(). Signed-off-by: Jon Maloy Signed-off-by: David S. Miller --- net/tipc/socket.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/tipc/socket.c b/net/tipc/socket.c index 5d18c0caa92b..41127d0b925e 100644 --- a/net/tipc/socket.c +++ b/net/tipc/socket.c @@ -1140,7 +1140,7 @@ void tipc_sk_mcast_rcv(struct net *net, struct sk_buff_head *arrvq, __skb_dequeue(arrvq); __skb_queue_tail(inputq, skb); } - refcount_dec(&skb->users); + kfree_skb(skb); spin_unlock_bh(&inputq->lock); continue; } -- GitLab From a46182b00290839fa3fa159d54fd3237bd8669f0 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Mon, 11 Dec 2017 11:13:45 -0800 Subject: [PATCH 1400/2547] net: igmp: Use correct source address on IGMPv3 reports Closing a multicast socket after the final IPv4 address is deleted from an interface can generate a membership report that uses the source IP from a different interface. The following test script, run from an isolated netns, reproduces the issue: #!/bin/bash ip link add dummy0 type dummy ip link add dummy1 type dummy ip link set dummy0 up ip link set dummy1 up ip addr add 10.1.1.1/24 dev dummy0 ip addr add 192.168.99.99/24 dev dummy1 tcpdump -U -i dummy0 & socat EXEC:"sleep 2" \ UDP4-DATAGRAM:239.101.1.68:8889,ip-add-membership=239.0.1.68:10.1.1.1 & sleep 1 ip addr del 10.1.1.1/24 dev dummy0 sleep 5 kill %tcpdump RFC 3376 specifies that the report must be sent with a valid IP source address from the destination subnet, or from address 0.0.0.0. Add an extra check to make sure this is the case. Signed-off-by: Kevin Cernekee Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- net/ipv4/igmp.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/net/ipv4/igmp.c b/net/ipv4/igmp.c index 50448a220a1f..726f6b608274 100644 --- a/net/ipv4/igmp.c +++ b/net/ipv4/igmp.c @@ -89,6 +89,7 @@ #include #include #include +#include #include #include @@ -321,6 +322,23 @@ igmp_scount(struct ip_mc_list *pmc, int type, int gdeleted, int sdeleted) return scount; } +/* source address selection per RFC 3376 section 4.2.13 */ +static __be32 igmpv3_get_srcaddr(struct net_device *dev, + const struct flowi4 *fl4) +{ + struct in_device *in_dev = __in_dev_get_rcu(dev); + + if (!in_dev) + return htonl(INADDR_ANY); + + for_ifa(in_dev) { + if (inet_ifa_match(fl4->saddr, ifa)) + return fl4->saddr; + } endfor_ifa(in_dev); + + return htonl(INADDR_ANY); +} + static struct sk_buff *igmpv3_newpack(struct net_device *dev, unsigned int mtu) { struct sk_buff *skb; @@ -368,7 +386,7 @@ static struct sk_buff *igmpv3_newpack(struct net_device *dev, unsigned int mtu) pip->frag_off = htons(IP_DF); pip->ttl = 1; pip->daddr = fl4.daddr; - pip->saddr = fl4.saddr; + pip->saddr = igmpv3_get_srcaddr(dev, &fl4); pip->protocol = IPPROTO_IGMP; pip->tot_len = 0; /* filled in later */ ip_select_ident(net, skb, NULL); -- GitLab From 6ca9a2beb54a385c8cc5e39a9d2ef49945896c64 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 13 Dec 2017 13:43:47 +0000 Subject: [PATCH 1401/2547] drm/i915: Unwind i915_gem_init() failure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since Michal introduced new user controllable errors other than -EIO during i915_gem_init(), we need to actually unwind on the error path as we have to abort the module load (and we expect to do so cleanly!). As we now teardown key state and then mark the driver as wedged (on EIO), we have to be careful to not allow ourselves to resume and unwedge, thus attempting to use the uninitialised driver. v2: Try not to free driver state for the suppressed EIO v3: Use load-fault-injection to test both error/recovery paths. References: 8620eb1dbbf2 ("drm/i915/uc: Don't use -EIO to report missing firmware") Signed-off-by: Chris Wilson Cc: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Sagar Arun Kamble Reviewed-by: Michał Winiarski Link: https://patchwork.freedesktop.org/patch/msgid/20171213134347.4608-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem.c | 80 +++++++++++++++++++++++++++------ 1 file changed, 66 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 8c3d801696b7..13fa26238e89 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4865,7 +4865,8 @@ void i915_gem_resume(struct drm_i915_private *i915) i915_gem_restore_gtt_mappings(i915); i915_gem_restore_fences(i915); - /* As we didn't flush the kernel context before suspend, we cannot + /* + * As we didn't flush the kernel context before suspend, we cannot * guarantee that the context image is complete. So let's just reset * it and start again. */ @@ -4886,8 +4887,10 @@ void i915_gem_resume(struct drm_i915_private *i915) return; err_wedged: - DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); - i915_gem_set_wedged(i915); + if (!i915_terminally_wedged(&i915->gpu_error)) { + DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); + i915_gem_set_wedged(i915); + } goto out_unlock; } @@ -5170,22 +5173,28 @@ int i915_gem_init(struct drm_i915_private *dev_priv) intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); ret = i915_gem_init_ggtt(dev_priv); - if (ret) - goto out_unlock; + if (ret) { + GEM_BUG_ON(ret == -EIO); + goto err_unlock; + } ret = i915_gem_contexts_init(dev_priv); - if (ret) - goto out_unlock; + if (ret) { + GEM_BUG_ON(ret == -EIO); + goto err_ggtt; + } ret = intel_engines_init(dev_priv); - if (ret) - goto out_unlock; + if (ret) { + GEM_BUG_ON(ret == -EIO); + goto err_context; + } intel_init_gt_powersave(dev_priv); ret = i915_gem_init_hw(dev_priv); if (ret) - goto out_unlock; + goto err_pm; /* * Despite its name intel_init_clock_gating applies both display @@ -5199,9 +5208,53 @@ int i915_gem_init(struct drm_i915_private *dev_priv) intel_init_clock_gating(dev_priv); ret = __intel_engines_record_defaults(dev_priv); -out_unlock: + if (ret) + goto err_init_hw; + + if (i915_inject_load_failure()) { + ret = -ENODEV; + goto err_init_hw; + } + + if (i915_inject_load_failure()) { + ret = -EIO; + goto err_init_hw; + } + + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + mutex_unlock(&dev_priv->drm.struct_mutex); + + return 0; + + /* + * Unwinding is complicated by that we want to handle -EIO to mean + * disable GPU submission but keep KMS alive. We want to mark the + * HW as irrevisibly wedged, but keep enough state around that the + * driver doesn't explode during runtime. + */ +err_init_hw: + i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED); + i915_gem_contexts_lost(dev_priv); + intel_uc_fini_hw(dev_priv); +err_pm: + if (ret != -EIO) { + intel_cleanup_gt_powersave(dev_priv); + i915_gem_cleanup_engines(dev_priv); + } +err_context: + if (ret != -EIO) + i915_gem_contexts_fini(dev_priv); +err_ggtt: +err_unlock: + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + mutex_unlock(&dev_priv->drm.struct_mutex); + + if (ret != -EIO) + i915_gem_cleanup_userptr(dev_priv); + if (ret == -EIO) { - /* Allow engine initialisation to fail by marking the GPU as + /* + * Allow engine initialisation to fail by marking the GPU as * wedged. But we only want to do this where the GPU is angry, * for all other failure, such as an allocation failure, bail. */ @@ -5211,9 +5264,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv) } ret = 0; } - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); - mutex_unlock(&dev_priv->drm.struct_mutex); + i915_gem_drain_freed_objects(dev_priv); return ret; } -- GitLab From aceef61ee56898cfa7b6960fb60b9326c3860441 Mon Sep 17 00:00:00 2001 From: Sebastian Sjoholm Date: Mon, 11 Dec 2017 21:51:14 +0100 Subject: [PATCH 1402/2547] net: qmi_wwan: add Sierra EM7565 1199:9091 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sierra Wireless EM7565 is an Qualcomm MDM9x50 based M.2 modem. The USB id is added to qmi_wwan.c to allow QMI communication with the EM7565. Signed-off-by: Sebastian Sjoholm Acked-by: Bjørn Mork Signed-off-by: David S. Miller --- drivers/net/usb/qmi_wwan.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c index 304ec6555cd8..d2ca5a202e8d 100644 --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c @@ -1204,6 +1204,7 @@ static const struct usb_device_id products[] = { {QMI_FIXED_INTF(0x1199, 0x9079, 10)}, /* Sierra Wireless EM74xx */ {QMI_FIXED_INTF(0x1199, 0x907b, 8)}, /* Sierra Wireless EM74xx */ {QMI_FIXED_INTF(0x1199, 0x907b, 10)}, /* Sierra Wireless EM74xx */ + {QMI_FIXED_INTF(0x1199, 0x9091, 8)}, /* Sierra Wireless EM7565 */ {QMI_FIXED_INTF(0x1bbb, 0x011e, 4)}, /* Telekom Speedstick LTE II (Alcatel One Touch L100V LTE) */ {QMI_FIXED_INTF(0x1bbb, 0x0203, 2)}, /* Alcatel L800MA */ {QMI_FIXED_INTF(0x2357, 0x0201, 4)}, /* TP-LINK HSUPA Modem MA180 */ -- GitLab From 2a9ee696c72a24d63529c76483fcd92d04b1d2b7 Mon Sep 17 00:00:00 2001 From: Branislav Radocaj Date: Tue, 12 Dec 2017 00:13:38 +0100 Subject: [PATCH 1403/2547] net: ethernet: arc: fix error handling in emac_rockchip_probe If clk_set_rate() fails, we should disable clk before return. Found by Linux Driver Verification project (linuxtesting.org). Changes since v2 [1]: * Merged with latest code changes Changes since v1: Update made thanks to David's review, much appreciated David. * Improved inconsistent failure handling of clock rate setting * For completeness of usecase, added arc_emac_probe error handling Signed-off-by: Branislav Radocaj Signed-off-by: David S. Miller --- drivers/net/ethernet/arc/emac_rockchip.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/arc/emac_rockchip.c b/drivers/net/ethernet/arc/emac_rockchip.c index c6163874e4e7..16f9bee992fe 100644 --- a/drivers/net/ethernet/arc/emac_rockchip.c +++ b/drivers/net/ethernet/arc/emac_rockchip.c @@ -199,9 +199,11 @@ static int emac_rockchip_probe(struct platform_device *pdev) /* RMII interface needs always a rate of 50MHz */ err = clk_set_rate(priv->refclk, 50000000); - if (err) + if (err) { dev_err(dev, "failed to change reference clock rate (%d)\n", err); + goto out_regulator_disable; + } if (priv->soc_data->need_div_macclk) { priv->macclk = devm_clk_get(dev, "macclk"); @@ -230,12 +232,14 @@ static int emac_rockchip_probe(struct platform_device *pdev) err = arc_emac_probe(ndev, interface); if (err) { dev_err(dev, "failed to probe arc emac (%d)\n", err); - goto out_regulator_disable; + goto out_clk_disable_macclk; } return 0; + out_clk_disable_macclk: - clk_disable_unprepare(priv->macclk); + if (priv->soc_data->need_div_macclk) + clk_disable_unprepare(priv->macclk); out_regulator_disable: if (priv->regulator) regulator_disable(priv->regulator); -- GitLab From 6e266610eb6553cfb7e7eb5d11914bd01509c406 Mon Sep 17 00:00:00 2001 From: Jia-Ju Bai Date: Tue, 12 Dec 2017 16:49:52 +0800 Subject: [PATCH 1404/2547] hippi: Fix a Fix a possible sleep-in-atomic bug in rr_close The driver may sleep under a spinlock. The function call path is: rr_close (acquire the spinlock) free_irq --> may sleep To fix it, free_irq is moved to the place without holding the spinlock. This bug is found by my static analysis tool(DSAC) and checked by my code review. Signed-off-by: Jia-Ju Bai Signed-off-by: David S. Miller --- drivers/net/hippi/rrunner.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/hippi/rrunner.c b/drivers/net/hippi/rrunner.c index 8483f03d5a41..1ab97d99b9ba 100644 --- a/drivers/net/hippi/rrunner.c +++ b/drivers/net/hippi/rrunner.c @@ -1379,8 +1379,8 @@ static int rr_close(struct net_device *dev) rrpriv->info_dma); rrpriv->info = NULL; - free_irq(pdev->irq, dev); spin_unlock_irqrestore(&rrpriv->lock, flags); + free_irq(pdev->irq, dev); return 0; } -- GitLab From 2e51a8dc7fdc9d06c52a0a0e442cc813357ea44d Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 12 Dec 2017 09:29:46 +0000 Subject: [PATCH 1405/2547] net: dsa: allow XAUI phy interface mode XGMII is a 32-bit bus plus two clock signals per direction. XAUI is four serial lanes per direction. The 88e6190 supports XAUI but not XGMII as it doesn't have enough pins. The same is true of 88e6176. Match on PHY_INTERFACE_MODE_XAUI for the XAUI port type, but keep accepting XGMII for backwards compatibility. Signed-off-by: Russell King Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- drivers/net/dsa/mv88e6xxx/port.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c index a7801f6668a5..6315774d72b3 100644 --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c @@ -338,6 +338,7 @@ int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; break; case PHY_INTERFACE_MODE_XGMII: + case PHY_INTERFACE_MODE_XAUI: cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; break; case PHY_INTERFACE_MODE_RXAUI: -- GitLab From cd8165c3d5fb07667328434835f2968a87caee67 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 12 Dec 2017 09:29:51 +0000 Subject: [PATCH 1406/2547] ARM: dts: vf610-zii-dev: use XAUI for DSA link ports Use XAUI rather than XGMII for DSA link ports, as this is the interface mode that the switches actually use. XAUI is the 4 lane bus with clock per direction, whereas XGMII is a 32 bit bus with clock. Signed-off-by: Russell King Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- arch/arm/boot/dts/vf610-zii-dev-rev-c.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts index 02a6227c717c..15a685dc2aa2 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts @@ -121,7 +121,7 @@ switch0port10: port@10 { reg = <10>; label = "dsa"; - phy-mode = "xgmii"; + phy-mode = "xaui"; link = <&switch1port10>; }; }; @@ -208,7 +208,7 @@ switch1port10: port@10 { reg = <10>; label = "dsa"; - phy-mode = "xgmii"; + phy-mode = "xaui"; link = <&switch0port10>; }; }; -- GitLab From f5e64032a799d4f54decc7eb6aafcdffb67f9ad9 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 12 Dec 2017 10:45:36 +0000 Subject: [PATCH 1407/2547] net: phy: fix resume handling When a PHY has the BMCR_PDOWN bit set, it may decide to ignore writes to other registers, or reset the registers to power-on defaults. Micrel PHYs do this for their interrupt registers. The current structure of phylib tries to enable interrupts before resuming (and releasing) the BMCR_PDOWN bit. This fails, causing Micrel PHYs to stop working after a suspend/resume sequence if they are using interrupts. Fix this by ensuring that the PHY driver resume methods do not take the phydev->lock mutex themselves, but the callers of phy_resume() take that lock. This then allows us to move the call to phy_resume() before we enable interrupts in phy_start(). Signed-off-by: Russell King Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- drivers/net/phy/at803x.c | 4 ---- drivers/net/phy/phy.c | 9 +++------ drivers/net/phy/phy_device.c | 10 ++++++---- 3 files changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 5f93e6add563..e911e4990b20 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -239,14 +239,10 @@ static int at803x_resume(struct phy_device *phydev) { int value; - mutex_lock(&phydev->lock); - value = phy_read(phydev, MII_BMCR); value &= ~(BMCR_PDOWN | BMCR_ISOLATE); phy_write(phydev, MII_BMCR, value); - mutex_unlock(&phydev->lock); - return 0; } diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 2b1e67bc1e73..ed10d1fc8f59 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -828,7 +828,6 @@ EXPORT_SYMBOL(phy_stop); */ void phy_start(struct phy_device *phydev) { - bool do_resume = false; int err = 0; mutex_lock(&phydev->lock); @@ -841,6 +840,9 @@ void phy_start(struct phy_device *phydev) phydev->state = PHY_UP; break; case PHY_HALTED: + /* if phy was suspended, bring the physical link up again */ + phy_resume(phydev); + /* make sure interrupts are re-enabled for the PHY */ if (phydev->irq != PHY_POLL) { err = phy_enable_interrupts(phydev); @@ -849,17 +851,12 @@ void phy_start(struct phy_device *phydev) } phydev->state = PHY_RESUMING; - do_resume = true; break; default: break; } mutex_unlock(&phydev->lock); - /* if phy was suspended, bring the physical link up again */ - if (do_resume) - phy_resume(phydev); - phy_trigger_machine(phydev, true); } EXPORT_SYMBOL(phy_start); diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 67f25ac29025..b15b31ca2618 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -135,7 +135,9 @@ static int mdio_bus_phy_resume(struct device *dev) if (!mdio_bus_phy_may_suspend(phydev)) goto no_resume; + mutex_lock(&phydev->lock); ret = phy_resume(phydev); + mutex_unlock(&phydev->lock); if (ret < 0) return ret; @@ -1026,7 +1028,9 @@ int phy_attach_direct(struct net_device *dev, struct phy_device *phydev, if (err) goto error; + mutex_lock(&phydev->lock); phy_resume(phydev); + mutex_unlock(&phydev->lock); phy_led_triggers_register(phydev); return err; @@ -1157,6 +1161,8 @@ int phy_resume(struct phy_device *phydev) struct phy_driver *phydrv = to_phy_driver(phydev->mdio.dev.driver); int ret = 0; + WARN_ON(!mutex_is_locked(&phydev->lock)); + if (phydev->drv && phydrv->resume) ret = phydrv->resume(phydev); @@ -1639,13 +1645,9 @@ int genphy_resume(struct phy_device *phydev) { int value; - mutex_lock(&phydev->lock); - value = phy_read(phydev, MII_BMCR); phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); - mutex_unlock(&phydev->lock); - return 0; } EXPORT_SYMBOL(genphy_resume); -- GitLab From 94a5ef1b77da4674a6bc1d3de3051b758859d106 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 12 Dec 2017 10:49:15 +0000 Subject: [PATCH 1408/2547] of_mdio / mdiobus: ensure mdio devices have fwnode correctly populated Ensure that all mdio devices populate the struct device fwnode pointer as well as the of_node pointer to allow drivers that wish to use fwnode APIs to work. Signed-off-by: Russell King Reviewed-by: Rob Herring Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- drivers/net/phy/mdio_bus.c | 1 + drivers/of/of_mdio.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c index 2df7b62c1a36..54d00a1d2bef 100644 --- a/drivers/net/phy/mdio_bus.c +++ b/drivers/net/phy/mdio_bus.c @@ -270,6 +270,7 @@ static void of_mdiobus_link_mdiodev(struct mii_bus *bus, if (addr == mdiodev->addr) { dev->of_node = child; + dev->fwnode = of_fwnode_handle(child); return; } } diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c index 98258583abb0..3481e69738b5 100644 --- a/drivers/of/of_mdio.c +++ b/drivers/of/of_mdio.c @@ -81,6 +81,7 @@ static int of_mdiobus_register_phy(struct mii_bus *mdio, * can be looked up later */ of_node_get(child); phy->mdio.dev.of_node = child; + phy->mdio.dev.fwnode = of_fwnode_handle(child); /* All data is now stored in the phy struct; * register it */ @@ -111,6 +112,7 @@ static int of_mdiobus_register_device(struct mii_bus *mdio, */ of_node_get(child); mdiodev->dev.of_node = child; + mdiodev->dev.fwnode = of_fwnode_handle(child); /* All data is now stored in the mdiodev struct; register it. */ rc = mdio_device_register(mdiodev); @@ -206,6 +208,7 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np) mdio->phy_mask = ~0; mdio->dev.of_node = np; + mdio->dev.fwnode = of_fwnode_handle(np); /* Get bus level PHY reset GPIO details */ mdio->reset_delay_us = DEFAULT_GPIO_RESET_DELAY; -- GitLab From 3b3397e2031564db07022e99f04d4b9f3df6fced Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 12 Dec 2017 13:03:11 +0000 Subject: [PATCH 1409/2547] net: phy: meson-gxl: make function meson_gxl_read_status static The function meson_gxl_read_status is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: symbol 'meson_gxl_read_status' was not declared. Should it be static? Signed-off-by: Colin Ian King Reviewed-by: Jerome Brunet Signed-off-by: David S. Miller --- drivers/net/phy/meson-gxl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index 700007dd4be5..842eb871a6e3 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -67,7 +67,7 @@ static int meson_gxl_config_init(struct phy_device *phydev) * When this failure happens, the first retry is usually successful but, * in some cases, it may take up to 6 retries to get a decent result */ -int meson_gxl_read_status(struct phy_device *phydev) +static int meson_gxl_read_status(struct phy_device *phydev) { int ret, wol, lpa, exp; -- GitLab From c009cb842fcc0f84536a9d2692e6f063af5ac5c6 Mon Sep 17 00:00:00 2001 From: Stephen Hemminger Date: Tue, 12 Dec 2017 10:30:29 -0800 Subject: [PATCH 1410/2547] skge: remove redundunt free_irq under spinlock The code to handle multi-port SKGE boards was freeing IRQ twice. The first one was under lock and might sleep. Signed-off-by: Stephen Hemminger Signed-off-by: David S. Miller --- drivers/net/ethernet/marvell/skge.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/skge.c b/drivers/net/ethernet/marvell/skge.c index 6e423f098a60..31efc47c847e 100644 --- a/drivers/net/ethernet/marvell/skge.c +++ b/drivers/net/ethernet/marvell/skge.c @@ -4081,7 +4081,6 @@ static void skge_remove(struct pci_dev *pdev) if (hw->ports > 1) { skge_write32(hw, B0_IMSK, 0); skge_read32(hw, B0_IMSK); - free_irq(pdev->irq, hw); } spin_unlock_irq(&hw->hw_lock); -- GitLab From 7ddae82e12593ff3d44e628c02fbfa765508aa48 Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Wed, 13 Dec 2017 13:45:44 -0700 Subject: [PATCH 1411/2547] drm/msm: gpu: Only sync fences on rings that exist The fault recovery code tries to sync fences on all possible rings instead of only the rings that actually exist which will fault the kernel when the number of rings are less than the maximum amount. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index a335ad43c4eb..6fbc2fc259ce 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -308,7 +308,7 @@ static void recover_worker(struct work_struct *work) * needs to happen after msm_rd_dump_submit() to ensure that the * bo's referenced by the offending submit are still around. */ - for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { + for (i = 0; i < gpu->nr_rings; i++) { struct msm_ringbuffer *ring = gpu->rb[i]; uint32_t fence = ring->memptrs->fence; -- GitLab From 9ee11bd03cb1a5c3ca33c2bb70e7ed325f68890f Mon Sep 17 00:00:00 2001 From: Wei Wang Date: Tue, 12 Dec 2017 16:28:58 -0800 Subject: [PATCH 1412/2547] tcp: fix potential underestimation on rcv_rtt When ms timestamp is used, current logic uses 1us in tcp_rcv_rtt_update() when the real rcv_rtt is within 1 - 999us. This could cause rcv_rtt underestimation. Fix it by always using a min value of 1ms if ms timestamp is used. Fixes: 645f4c6f2ebd ("tcp: switch rcv_rtt_est and rcvq_space to high resolution timestamps") Signed-off-by: Wei Wang Signed-off-by: Eric Dumazet Acked-by: Neal Cardwell Signed-off-by: David S. Miller --- net/ipv4/tcp_input.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index 9550cc42de2d..45f750e85714 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -508,9 +508,6 @@ static void tcp_rcv_rtt_update(struct tcp_sock *tp, u32 sample, int win_dep) u32 new_sample = tp->rcv_rtt_est.rtt_us; long m = sample; - if (m == 0) - m = 1; - if (new_sample != 0) { /* If we sample in larger samples in the non-timestamp * case, we could grossly overestimate the RTT especially @@ -547,6 +544,8 @@ static inline void tcp_rcv_rtt_measure(struct tcp_sock *tp) if (before(tp->rcv_nxt, tp->rcv_rtt_est.seq)) return; delta_us = tcp_stamp_us_delta(tp->tcp_mstamp, tp->rcv_rtt_est.time); + if (!delta_us) + delta_us = 1; tcp_rcv_rtt_update(tp, delta_us, 1); new_measure: @@ -563,8 +562,11 @@ static inline void tcp_rcv_rtt_measure_ts(struct sock *sk, (TCP_SKB_CB(skb)->end_seq - TCP_SKB_CB(skb)->seq >= inet_csk(sk)->icsk_ack.rcv_mss)) { u32 delta = tcp_time_stamp(tp) - tp->rx_opt.rcv_tsecr; - u32 delta_us = delta * (USEC_PER_SEC / TCP_TS_HZ); + u32 delta_us; + if (!delta) + delta = 1; + delta_us = delta * (USEC_PER_SEC / TCP_TS_HZ); tcp_rcv_rtt_update(tp, delta_us, 0); } } -- GitLab From 4688eb7cf3ae2c2721d1dacff5c1384cba47d176 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 12 Dec 2017 18:22:52 -0800 Subject: [PATCH 1413/2547] tcp: refresh tcp_mstamp from timers callbacks Only the retransmit timer currently refreshes tcp_mstamp We should do the same for delayed acks and keepalives. Even if RFC 7323 does not request it, this is consistent to what linux did in the past, when TS values were based on jiffies. Fixes: 385e20706fac ("tcp: use tp->tcp_mstamp in output path") Signed-off-by: Eric Dumazet Cc: Soheil Hassas Yeganeh Cc: Mike Maloney Cc: Neal Cardwell Acked-by: Neal Cardwell Acked-by: Soheil Hassas Yeganeh Acked-by: Mike Maloney Signed-off-by: David S. Miller --- net/ipv4/tcp_timer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/ipv4/tcp_timer.c b/net/ipv4/tcp_timer.c index 16df6dd44b98..968fda198376 100644 --- a/net/ipv4/tcp_timer.c +++ b/net/ipv4/tcp_timer.c @@ -264,6 +264,7 @@ void tcp_delack_timer_handler(struct sock *sk) icsk->icsk_ack.pingpong = 0; icsk->icsk_ack.ato = TCP_ATO_MIN; } + tcp_mstamp_refresh(tcp_sk(sk)); tcp_send_ack(sk); __NET_INC_STATS(sock_net(sk), LINUX_MIB_DELAYEDACKS); } @@ -632,6 +633,7 @@ static void tcp_keepalive_timer (struct timer_list *t) goto out; } + tcp_mstamp_refresh(tp); if (sk->sk_state == TCP_FIN_WAIT2 && sock_flag(sk, SOCK_DEAD)) { if (tp->linger2 >= 0) { const int tmo = tcp_fin_time(sk) - TCP_TIMEWAIT_LEN; -- GitLab From 53c64870d03edfa5c554ac2f750c5d6b38e3680a Mon Sep 17 00:00:00 2001 From: Jie Deng Date: Wed, 13 Dec 2017 12:04:12 +0800 Subject: [PATCH 1414/2547] dwc-xlgmac: Add co-maintainer Jose Abreu will join to maintain dwc-xlgmac. He will help with new feature development for this driver. Thanks Jose and welcome on board! Signed-off-by: Jie Deng Signed-off-by: David S. Miller --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9e0045e3ee0c..51497dc05333 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13117,6 +13117,7 @@ F: drivers/dma/dw/ SYNOPSYS DESIGNWARE ENTERPRISE ETHERNET DRIVER M: Jie Deng +M: Jose Abreu L: netdev@vger.kernel.org S: Supported F: drivers/net/ethernet/synopsys/ -- GitLab From de9c4e06bbe872d725f306e34f3eea21155488e2 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 13 Dec 2017 09:22:03 +0000 Subject: [PATCH 1415/2547] net: phy: marvell: avoid configuring fiber page for SGMII-to-Copper When in SGMII-to-Copper mode, the fiber page is used for the MAC facing link, and does not require configuration of the fiber auto-negotiation settings. Avoid trying. Signed-off-by: Russell King Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- drivers/net/phy/marvell.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 4d02b27df044..b5a8f750e433 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -637,6 +637,10 @@ static int m88e1510_config_aneg(struct phy_device *phydev) if (err < 0) goto error; + /* Do not touch the fiber page if we're in copper->sgmii mode */ + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) + return 0; + /* Then the fiber link */ err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE); if (err < 0) -- GitLab From 78034f5fdd622520eb843301cf35ce6c626543a7 Mon Sep 17 00:00:00 2001 From: Eugenia Emantayev Date: Wed, 13 Dec 2017 18:12:09 +0200 Subject: [PATCH 1416/2547] net/mlx4_en: Fix selftest for small MTUs Set the minimal MTU threshold for running loopback selftest. MTU should be big enough to include packet payload, NET_IP_ALIGN, Ethernet headers and preamble length. Fixes: e7c1c2c46201 ("mlx4_en: Added self diagnostics test implementation") Signed-off-by: Eugenia Emantayev Signed-off-by: Tariq Toukan Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlx4/en_selftest.c | 2 +- drivers/net/ethernet/mellanox/mlx4/mlx4_en.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx4/en_selftest.c b/drivers/net/ethernet/mellanox/mlx4/en_selftest.c index 88699b181946..946d9db7c8c2 100644 --- a/drivers/net/ethernet/mellanox/mlx4/en_selftest.c +++ b/drivers/net/ethernet/mellanox/mlx4/en_selftest.c @@ -185,7 +185,7 @@ void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf) if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) { buf[3] = mlx4_en_test_registers(priv); - if (priv->port_up) + if (priv->port_up && dev->mtu >= MLX4_SELFTEST_LB_MIN_MTU) buf[4] = mlx4_en_test_loopback(priv); } diff --git a/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h b/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h index 1856e279a7e0..2b72677eccd4 100644 --- a/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h +++ b/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h @@ -153,6 +153,9 @@ #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) +#define PREAMBLE_LEN 8 +#define MLX4_SELFTEST_LB_MIN_MTU (MLX4_LOOPBACK_TEST_PAYLOAD + NET_IP_ALIGN + \ + ETH_HLEN + PREAMBLE_LEN) #define MLX4_EN_MIN_MTU 46 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple -- GitLab From 0bb9fc4f5429ac970181c073aa32e521e20f7b73 Mon Sep 17 00:00:00 2001 From: Eran Ben Elisha Date: Wed, 13 Dec 2017 18:12:10 +0200 Subject: [PATCH 1417/2547] net/mlx4_core: Fix wrong calculation of free counters The field res_free indicates the total number of counters which are available for allocation (reserved and unreserved). Fixed a bug where the reserved counters were subtracted from res_free before any allocation was performed. Before this fix, free counters which were not reserved could not be allocated. Fixes: 9de92c60beaa ("net/mlx4_core: Adjust counter grant policy in the resource tracker") Signed-off-by: Eran Ben Elisha Reviewed-by: Jack Morgenstein Signed-off-by: Tariq Toukan Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlx4/resource_tracker.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx4/resource_tracker.c b/drivers/net/ethernet/mellanox/mlx4/resource_tracker.c index 04304dd894c6..606a0e0beeae 100644 --- a/drivers/net/ethernet/mellanox/mlx4/resource_tracker.c +++ b/drivers/net/ethernet/mellanox/mlx4/resource_tracker.c @@ -611,7 +611,6 @@ int mlx4_init_resource_tracker(struct mlx4_dev *dev) MLX4_MAX_PORTS; else res_alloc->guaranteed[t] = 0; - res_alloc->res_free -= res_alloc->guaranteed[t]; break; default: break; -- GitLab From 5a1647c391ba543a77a400dddf89053ec5c2b7a4 Mon Sep 17 00:00:00 2001 From: Eran Ben Elisha Date: Wed, 13 Dec 2017 18:12:11 +0200 Subject: [PATCH 1418/2547] net/mlx4_en: Fill all counters under one call of stats lock Before this patch, the stats_lock was acquired twice. In between the locks Driver sent command to gather some more statistics (per priority and counter statistics). If the stats lock was acquired by get statistics NDO in between we would have report out of sync counters. Fix this by collecting all stats from Firmware in advance and then fill the Software structs under one lock. Fixes: 0b131561a7d6 ("net/mlx4_en: Add Flow control statistics display via ethtool") Signed-off-by: Eran Ben Elisha Signed-off-by: Tariq Toukan Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlx4/en_port.c | 57 +++++++++++--------- 1 file changed, 31 insertions(+), 26 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx4/en_port.c b/drivers/net/ethernet/mellanox/mlx4/en_port.c index e0eb695318e6..1fa4849a6f56 100644 --- a/drivers/net/ethernet/mellanox/mlx4/en_port.c +++ b/drivers/net/ethernet/mellanox/mlx4/en_port.c @@ -188,7 +188,7 @@ int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset) struct net_device *dev = mdev->pndev[port]; struct mlx4_en_priv *priv = netdev_priv(dev); struct net_device_stats *stats = &dev->stats; - struct mlx4_cmd_mailbox *mailbox; + struct mlx4_cmd_mailbox *mailbox, *mailbox_priority; u64 in_mod = reset << 8 | port; int err; int i, counter_index; @@ -198,6 +198,13 @@ int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset) mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); if (IS_ERR(mailbox)) return PTR_ERR(mailbox); + + mailbox_priority = mlx4_alloc_cmd_mailbox(mdev->dev); + if (IS_ERR(mailbox_priority)) { + mlx4_free_cmd_mailbox(mdev->dev, mailbox); + return PTR_ERR(mailbox_priority); + } + err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0, MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); @@ -206,6 +213,28 @@ int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset) mlx4_en_stats = mailbox->buf; + memset(&tmp_counter_stats, 0, sizeof(tmp_counter_stats)); + counter_index = mlx4_get_default_counter_index(mdev->dev, port); + err = mlx4_get_counter_stats(mdev->dev, counter_index, + &tmp_counter_stats, reset); + + /* 0xffs indicates invalid value */ + memset(mailbox_priority->buf, 0xff, + sizeof(*flowstats) * MLX4_NUM_PRIORITIES); + + if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN) { + memset(mailbox_priority->buf, 0, + sizeof(*flowstats) * MLX4_NUM_PRIORITIES); + err = mlx4_cmd_box(mdev->dev, 0, mailbox_priority->dma, + in_mod | MLX4_DUMP_ETH_STATS_FLOW_CONTROL, + 0, MLX4_CMD_DUMP_ETH_STATS, + MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); + if (err) + goto out; + } + + flowstats = mailbox_priority->buf; + spin_lock_bh(&priv->stats_lock); mlx4_en_fold_software_stats(dev); @@ -345,31 +374,6 @@ int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset) priv->pkstats.tx_prio[8][0] = be64_to_cpu(mlx4_en_stats->TTOT_novlan); priv->pkstats.tx_prio[8][1] = be64_to_cpu(mlx4_en_stats->TOCT_novlan); - spin_unlock_bh(&priv->stats_lock); - - memset(&tmp_counter_stats, 0, sizeof(tmp_counter_stats)); - counter_index = mlx4_get_default_counter_index(mdev->dev, port); - err = mlx4_get_counter_stats(mdev->dev, counter_index, - &tmp_counter_stats, reset); - - /* 0xffs indicates invalid value */ - memset(mailbox->buf, 0xff, sizeof(*flowstats) * MLX4_NUM_PRIORITIES); - - if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN) { - memset(mailbox->buf, 0, - sizeof(*flowstats) * MLX4_NUM_PRIORITIES); - err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, - in_mod | MLX4_DUMP_ETH_STATS_FLOW_CONTROL, - 0, MLX4_CMD_DUMP_ETH_STATS, - MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); - if (err) - goto out; - } - - flowstats = mailbox->buf; - - spin_lock_bh(&priv->stats_lock); - if (tmp_counter_stats.counter_mode == 0) { priv->pf_stats.rx_bytes = be64_to_cpu(tmp_counter_stats.rx_bytes); priv->pf_stats.tx_bytes = be64_to_cpu(tmp_counter_stats.tx_bytes); @@ -410,6 +414,7 @@ int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset) out: mlx4_free_cmd_mailbox(mdev->dev, mailbox); + mlx4_free_cmd_mailbox(mdev->dev, mailbox_priority); return err; } -- GitLab From ea497bb92064875497554ee7cdf10df7fb7393fc Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 13 Dec 2017 13:49:36 +0100 Subject: [PATCH 1419/2547] drm: rework delayed connector cleanup in connector_iter PROBE_DEFER also uses system_wq to reprobe drivers, which means when that again fails, and we try to flush the overall system_wq (to get all the delayed connectore cleanup work_struct completed), we deadlock. Fix this by using just a single cleanup work, so that we can only flush that one and don't block on anything else. That means a free list plus locking, a standard pattern. v2: - Correctly free connectors only on last ref. Oops (Chris). - use llist_head/node (Chris). v3 - Add init_llist_head (Chris). Fixes: a703c55004e1 ("drm: safely free connectors from connector_iter") Fixes: 613051dac40d ("drm: locking&new iterators for connector_list") Cc: Ben Widawsky Cc: Dave Airlie Cc: Chris Wilson Cc: Sean Paul Cc: # v4.11+: 613051dac40d ("drm: locking&new iterators for connector_list" Cc: # v4.11+ Cc: Daniel Vetter Cc: Jani Nikula Cc: Gustavo Padovan Cc: David Airlie Cc: Javier Martinez Canillas Cc: Shuah Khan Cc: Guillaume Tucker Cc: Mark Brown Cc: Kevin Hilman Cc: Matt Hart Cc: Thierry Escande Cc: Tomeu Vizoso Cc: Enric Balletbo i Serra Tested-by: Marek Szyprowski Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171213124936.17914-1-daniel.vetter@ffwll.ch --- drivers/gpu/drm/drm_connector.c | 50 ++++++++++++++++++++--------- drivers/gpu/drm/drm_crtc_internal.h | 1 + drivers/gpu/drm/drm_mode_config.c | 5 ++- include/drm/drm_connector.h | 10 +++--- include/drm/drm_mode_config.h | 18 ++++++++++- 5 files changed, 63 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index c4dfcbc861a1..9ae236036e32 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -152,14 +152,23 @@ static void drm_connector_free(struct kref *kref) connector->funcs->destroy(connector); } -static void drm_connector_free_work_fn(struct work_struct *work) +void drm_connector_free_work_fn(struct work_struct *work) { - struct drm_connector *connector = - container_of(work, struct drm_connector, free_work); - struct drm_device *dev = connector->dev; + struct drm_connector *connector, *n; + struct drm_device *dev = + container_of(work, struct drm_device, mode_config.connector_free_work); + struct drm_mode_config *config = &dev->mode_config; + unsigned long flags; + struct llist_node *freed; - drm_mode_object_unregister(dev, &connector->base); - connector->funcs->destroy(connector); + spin_lock_irqsave(&config->connector_list_lock, flags); + freed = llist_del_all(&config->connector_free_list); + spin_unlock_irqrestore(&config->connector_list_lock, flags); + + llist_for_each_entry_safe(connector, n, freed, free_node) { + drm_mode_object_unregister(dev, &connector->base); + connector->funcs->destroy(connector); + } } /** @@ -191,8 +200,6 @@ int drm_connector_init(struct drm_device *dev, if (ret) return ret; - INIT_WORK(&connector->free_work, drm_connector_free_work_fn); - connector->base.properties = &connector->properties; connector->dev = dev; connector->funcs = funcs; @@ -547,10 +554,17 @@ EXPORT_SYMBOL(drm_connector_list_iter_begin); * actually release the connector when dropping our final reference. */ static void -drm_connector_put_safe(struct drm_connector *conn) +__drm_connector_put_safe(struct drm_connector *conn) { - if (refcount_dec_and_test(&conn->base.refcount.refcount)) - schedule_work(&conn->free_work); + struct drm_mode_config *config = &conn->dev->mode_config; + + lockdep_assert_held(&config->connector_list_lock); + + if (!refcount_dec_and_test(&conn->base.refcount.refcount)) + return; + + llist_add(&conn->free_node, &config->connector_free_list); + schedule_work(&config->connector_free_work); } /** @@ -582,10 +596,10 @@ drm_connector_list_iter_next(struct drm_connector_list_iter *iter) /* loop until it's not a zombie connector */ } while (!kref_get_unless_zero(&iter->conn->base.refcount)); - spin_unlock_irqrestore(&config->connector_list_lock, flags); if (old_conn) - drm_connector_put_safe(old_conn); + __drm_connector_put_safe(old_conn); + spin_unlock_irqrestore(&config->connector_list_lock, flags); return iter->conn; } @@ -602,9 +616,15 @@ EXPORT_SYMBOL(drm_connector_list_iter_next); */ void drm_connector_list_iter_end(struct drm_connector_list_iter *iter) { + struct drm_mode_config *config = &iter->dev->mode_config; + unsigned long flags; + iter->dev = NULL; - if (iter->conn) - drm_connector_put_safe(iter->conn); + if (iter->conn) { + spin_lock_irqsave(&config->connector_list_lock, flags); + __drm_connector_put_safe(iter->conn); + spin_unlock_irqrestore(&config->connector_list_lock, flags); + } lock_release(&connector_list_iter_dep_map, 0, _RET_IP_); } EXPORT_SYMBOL(drm_connector_list_iter_end); diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h index 9ebb8841778c..af00f42ba269 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -142,6 +142,7 @@ int drm_mode_connector_set_obj_prop(struct drm_mode_object *obj, uint64_t value); int drm_connector_create_standard_properties(struct drm_device *dev); const char *drm_get_connector_force_name(enum drm_connector_force force); +void drm_connector_free_work_fn(struct work_struct *work); /* IOCTL */ int drm_mode_connector_property_set_ioctl(struct drm_device *dev, diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c index cc78b3d9e5e4..256de7313612 100644 --- a/drivers/gpu/drm/drm_mode_config.c +++ b/drivers/gpu/drm/drm_mode_config.c @@ -382,6 +382,9 @@ void drm_mode_config_init(struct drm_device *dev) ida_init(&dev->mode_config.connector_ida); spin_lock_init(&dev->mode_config.connector_list_lock); + init_llist_head(&dev->mode_config.connector_free_list); + INIT_WORK(&dev->mode_config.connector_free_work, drm_connector_free_work_fn); + drm_mode_create_standard_properties(dev); /* Just to be sure */ @@ -432,7 +435,7 @@ void drm_mode_config_cleanup(struct drm_device *dev) } drm_connector_list_iter_end(&conn_iter); /* connector_iter drops references in a work item. */ - flush_scheduled_work(); + flush_work(&dev->mode_config.connector_free_work); if (WARN_ON(!list_empty(&dev->mode_config.connector_list))) { drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index a4649c56ca2f..5971577016a2 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -24,6 +24,7 @@ #define __DRM_CONNECTOR_H__ #include +#include #include #include #include @@ -918,12 +919,13 @@ struct drm_connector { uint16_t tile_h_size, tile_v_size; /** - * @free_work: + * @free_node: * - * Work used only by &drm_connector_iter to be able to clean up a - * connector from any context. + * List used only by &drm_connector_iter to be able to clean up a + * connector from any context, in conjunction with + * &drm_mode_config.connector_free_work. */ - struct work_struct free_work; + struct llist_node free_node; }; #define obj_to_connector(x) container_of(x, struct drm_connector, base) diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index b21e827c5c78..b0ce26d71296 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -27,6 +27,7 @@ #include #include #include +#include #include @@ -393,7 +394,7 @@ struct drm_mode_config { /** * @connector_list_lock: Protects @num_connector and - * @connector_list. + * @connector_list and @connector_free_list. */ spinlock_t connector_list_lock; /** @@ -413,6 +414,21 @@ struct drm_mode_config { * &struct drm_connector_list_iter to walk this list. */ struct list_head connector_list; + /** + * @connector_free_list: + * + * List of connector objects linked with &drm_connector.free_head. + * Protected by @connector_list_lock. Used by + * drm_for_each_connector_iter() and + * &struct drm_connector_list_iter to savely free connectors using + * @connector_free_work. + */ + struct llist_head connector_free_list; + /** + * @connector_free_work: Work to clean up @connector_free_list. + */ + struct work_struct connector_free_work; + /** * @num_encoder: * -- GitLab From bf383fb64e7c8ccc96d382e38e829737389708a7 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 8 Dec 2017 13:07:58 -0500 Subject: [PATCH 1420/2547] drm/amdgpu: convert nbio to use callbacks (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleans up and consolidates all of the per-asic logic. v2: squash in "drm/amdgpu: fix NULL err for sriov detect" (Chunming) Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 50 +++++++++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 15 +--- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 81 ++++++++++------- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 25 ------ drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 105 ++++++++++++++++++---- drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h | 19 ---- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 13 +-- drivers/gpu/drm/amd/amdgpu/soc15.c | 50 ++++------- drivers/gpu/drm/amd/amdgpu/soc15_common.h | 16 ---- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 11 +-- 11 files changed, 209 insertions(+), 183 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c8bc1a982dc4..c73eca86c9f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1428,16 +1428,52 @@ typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, u /* * amdgpu nbio functions * - * Fix me : - * Put more NBIO specifc func wraper here , for now just try to minimize the - * change to avoid use SOC15_REG_OFFSET in the constant array */ +struct nbio_hdp_flush_reg { + u32 ref_and_mask_cp0; + u32 ref_and_mask_cp1; + u32 ref_and_mask_cp2; + u32 ref_and_mask_cp3; + u32 ref_and_mask_cp4; + u32 ref_and_mask_cp5; + u32 ref_and_mask_cp6; + u32 ref_and_mask_cp7; + u32 ref_and_mask_cp8; + u32 ref_and_mask_cp9; + u32 ref_and_mask_sdma0; + u32 ref_and_mask_sdma1; +}; struct amdgpu_nbio_funcs { - u32 (*get_hdp_flush_req_offset)(struct amdgpu_device*); - u32 (*get_hdp_flush_done_offset)(struct amdgpu_device*); - u32 (*get_pcie_index_offset)(struct amdgpu_device*); - u32 (*get_pcie_data_offset)(struct amdgpu_device*); + const struct nbio_hdp_flush_reg *hdp_flush_reg; + u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); + u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); + u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); + u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); + u32 (*get_rev_id)(struct amdgpu_device *adev); + u32 (*get_atombios_scratch_regs)(struct amdgpu_device *adev, uint32_t idx); + void (*set_atombios_scratch_regs)(struct amdgpu_device *adev, + uint32_t idx, uint32_t val); + void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); + void (*hdp_flush)(struct amdgpu_device *adev); + u32 (*get_memsize)(struct amdgpu_device *adev); + void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, + bool use_doorbell, int doorbell_index); + void (*enable_doorbell_aperture)(struct amdgpu_device *adev, + bool enable); + void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, + bool enable); + void (*ih_doorbell_range)(struct amdgpu_device *adev, + bool use_doorbell, int doorbell_index); + void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, + bool enable); + void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, + bool enable); + void (*get_clockgating_state)(struct amdgpu_device *adev, + u32 *flags); + void (*ih_control)(struct amdgpu_device *adev); + void (*init_registers)(struct amdgpu_device *adev); + void (*detect_hw_virt)(struct amdgpu_device *adev); }; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 30b41fc082e6..e9a668bae194 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3552,12 +3552,7 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; - const struct nbio_hdp_flush_reg *nbio_hf_reg; - - if (ring->adev->flags & AMD_IS_APU) - nbio_hf_reg = &nbio_v7_0_hdp_flush_reg; - else - nbio_hf_reg = &nbio_v6_1_hdp_flush_reg; + const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { switch (ring->me) { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 51856e53d8c4..1b5dfccfd5d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -38,8 +38,6 @@ #include "soc15_common.h" #include "umc/umc_6_0_sh_mask.h" -#include "nbio_v6_1.h" -#include "nbio_v7_0.h" #include "gfxhub_v1_0.h" #include "mmhub_v1_0.h" @@ -332,10 +330,7 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, unsigned i, j; /* flush hdp cache */ - if (adev->flags & AMD_IS_APU) - nbio_v7_0_hdp_flush(adev); - else - nbio_v6_1_hdp_flush(adev); + adev->nbio_funcs->hdp_flush(adev); spin_lock(&adev->mc.invalidate_lock); @@ -702,8 +697,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) /* size in MB on si */ adev->mc.mc_vram_size = - ((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) : - nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL; + adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; adev->mc.real_vram_size = adev->mc.mc_vram_size; if (!(adev->flags & AMD_IS_APU)) { @@ -951,10 +945,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); /* After HDP is initialized, flush HDP.*/ - if (adev->flags & AMD_IS_APU) - nbio_v7_0_hdp_flush(adev); - else - nbio_v6_1_hdp_flush(adev); + adev->nbio_funcs->hdp_flush(adev); if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) value = false; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index 947d6e4a01f7..0d3514808092 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -33,7 +33,7 @@ #define smnPCIE_CNTL2 0x11180070 #define smnPCIE_CONFIG_CNTL 0x11180044 -u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) +static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) { u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); @@ -43,19 +43,19 @@ u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) return tmp; } -u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev, - uint32_t idx) +static u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev, + uint32_t idx) { return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx); } -void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev, - uint32_t idx, uint32_t val) +static void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev, + uint32_t idx, uint32_t val) { WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val); } -void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) +static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) { if (enable) WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, @@ -65,17 +65,17 @@ void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); } -void nbio_v6_1_hdp_flush(struct amdgpu_device *adev) +static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev) { WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0); } -u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) +static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) { return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE); } -void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, +static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, bool use_doorbell, int doorbell_index) { u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : @@ -93,14 +93,14 @@ void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, } -void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev, - bool enable) +static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev, + bool enable) { WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); } -void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, - bool enable) +static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, + bool enable) { u32 tmp = 0; @@ -119,8 +119,8 @@ void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, } -void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, - bool use_doorbell, int doorbell_index) +static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, + bool use_doorbell, int doorbell_index) { u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); @@ -133,7 +133,7 @@ void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); } -void nbio_v6_1_ih_control(struct amdgpu_device *adev) +static void nbio_v6_1_ih_control(struct amdgpu_device *adev) { u32 interrupt_cntl; @@ -149,8 +149,8 @@ void nbio_v6_1_ih_control(struct amdgpu_device *adev) WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); } -void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, - bool enable) +static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) { uint32_t def, data; @@ -177,8 +177,8 @@ void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, WREG32_PCIE(smnCPM_CONTROL, data); } -void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, - bool enable) +static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, + bool enable) { uint32_t def, data; @@ -197,7 +197,8 @@ void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, WREG32_PCIE(smnPCIE_CNTL2, data); } -void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) +static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, + u32 *flags) { int data; @@ -232,7 +233,7 @@ static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev) return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA); } -const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = { +static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = { .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, @@ -247,15 +248,7 @@ const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = { .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK }; -const struct amdgpu_nbio_funcs nbio_v6_1_funcs = { - .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset, - .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset, - .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset, - .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset, -}; - - -void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev) +static void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev) { uint32_t reg; @@ -272,7 +265,7 @@ void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev) } } -void nbio_v6_1_init_registers(struct amdgpu_device *adev) +static void nbio_v6_1_init_registers(struct amdgpu_device *adev) { uint32_t def, data; @@ -283,3 +276,27 @@ void nbio_v6_1_init_registers(struct amdgpu_device *adev) if (def != data) WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); } + +const struct amdgpu_nbio_funcs nbio_v6_1_funcs = { + .hdp_flush_reg = &nbio_v6_1_hdp_flush_reg, + .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset, + .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset, + .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset, + .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset, + .get_rev_id = nbio_v6_1_get_rev_id, + .get_atombios_scratch_regs = nbio_v6_1_get_atombios_scratch_regs, + .set_atombios_scratch_regs = nbio_v6_1_set_atombios_scratch_regs, + .mc_access_enable = nbio_v6_1_mc_access_enable, + .hdp_flush = nbio_v6_1_hdp_flush, + .get_memsize = nbio_v6_1_get_memsize, + .sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range, + .enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture, + .enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture, + .ih_doorbell_range = nbio_v6_1_ih_doorbell_range, + .update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating, + .update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep, + .get_clockgating_state = nbio_v6_1_get_clockgating_state, + .ih_control = nbio_v6_1_ih_control, + .init_registers = nbio_v6_1_init_registers, + .detect_hw_virt = nbio_v6_1_detect_hw_virt, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h index 973effed27e5..0743a6f016f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h @@ -26,31 +26,6 @@ #include "soc15_common.h" -extern const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg; extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs; -int nbio_v6_1_init(struct amdgpu_device *adev); -u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev, - uint32_t idx); -void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev, - uint32_t idx, uint32_t val); -void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable); -void nbio_v6_1_hdp_flush(struct amdgpu_device *adev); -u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev); -void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, - bool use_doorbell, int doorbell_index); -void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev, - bool enable); -void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, - bool enable); -void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, - bool use_doorbell, int doorbell_index); -void nbio_v6_1_ih_control(struct amdgpu_device *adev); -u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev); -void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable); -void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable); -void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); -void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev); -void nbio_v6_1_init_registers(struct amdgpu_device *adev); - #endif diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index 851f58e0b9d9..29d7b4fd7a88 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -31,8 +31,10 @@ #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c +#define smnCPM_CONTROL 0x11180460 +#define smnPCIE_CNTL2 0x11180070 -u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev) { u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); @@ -42,19 +44,19 @@ u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev) return tmp; } -u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev, +static u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev, uint32_t idx) { return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx); } -void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev, - uint32_t idx, uint32_t val) +static void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev, + uint32_t idx, uint32_t val) { WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val); } -void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable) +static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable) { if (enable) WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, @@ -63,18 +65,18 @@ void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable) WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); } -void nbio_v7_0_hdp_flush(struct amdgpu_device *adev) +static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev) { WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); } -u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) { return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); } -void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance, - bool use_doorbell, int doorbell_index) +static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance, + bool use_doorbell, int doorbell_index) { u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); @@ -90,14 +92,20 @@ void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance, WREG32(reg, doorbell_range); } -void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev, - bool enable) +static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev, + bool enable) { WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); } -void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev, - bool use_doorbell, int doorbell_index) +static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, + bool enable) +{ + +} + +static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev, + bool use_doorbell, int doorbell_index) { u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); @@ -127,8 +135,8 @@ static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t o WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data); } -void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, - bool enable) +static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) { uint32_t def, data; @@ -166,7 +174,43 @@ void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data); } -void nbio_v7_0_ih_control(struct amdgpu_device *adev) +static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data; + + def = data = RREG32_PCIE(smnPCIE_CNTL2); + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { + data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | + PCIE_CNTL2__MST_MEM_LS_EN_MASK | + PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); + } else { + data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | + PCIE_CNTL2__MST_MEM_LS_EN_MASK | + PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); + } + + if (def != data) + WREG32_PCIE(smnPCIE_CNTL2, data); +} + +static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev, + u32 *flags) +{ + int data; + + /* AMD_CG_SUPPORT_BIF_MGCG */ + data = RREG32_PCIE(smnCPM_CONTROL); + if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) + *flags |= AMD_CG_SUPPORT_BIF_MGCG; + + /* AMD_CG_SUPPORT_BIF_LS */ + data = RREG32_PCIE(smnPCIE_CNTL2); + if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) + *flags |= AMD_CG_SUPPORT_BIF_LS; +} + +static void nbio_v7_0_ih_control(struct amdgpu_device *adev) { u32 interrupt_cntl; @@ -217,10 +261,37 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = { .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, }; +static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev) +{ + if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ + adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; +} + +static void nbio_v7_0_init_registers(struct amdgpu_device *adev) +{ + +} + const struct amdgpu_nbio_funcs nbio_v7_0_funcs = { + .hdp_flush_reg = &nbio_v7_0_hdp_flush_reg, .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset, .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset, .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset, .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset, + .get_rev_id = nbio_v7_0_get_rev_id, + .get_atombios_scratch_regs = nbio_v7_0_get_atombios_scratch_regs, + .set_atombios_scratch_regs = nbio_v7_0_set_atombios_scratch_regs, + .mc_access_enable = nbio_v7_0_mc_access_enable, + .hdp_flush = nbio_v7_0_hdp_flush, + .get_memsize = nbio_v7_0_get_memsize, + .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range, + .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture, + .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture, + .ih_doorbell_range = nbio_v7_0_ih_doorbell_range, + .update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating, + .update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep, + .get_clockgating_state = nbio_v7_0_get_clockgating_state, + .ih_control = nbio_v7_0_ih_control, + .init_registers = nbio_v7_0_init_registers, + .detect_hw_virt = nbio_v7_0_detect_hw_virt, }; - diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h index 070c3bdf5739..508d549c5029 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h @@ -26,25 +26,6 @@ #include "soc15_common.h" -extern const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg; extern const struct amdgpu_nbio_funcs nbio_v7_0_funcs; -int nbio_v7_0_init(struct amdgpu_device *adev); -u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev, - uint32_t idx); -void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev, - uint32_t idx, uint32_t val); -void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable); -void nbio_v7_0_hdp_flush(struct amdgpu_device *adev); -u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev); -void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance, - bool use_doorbell, int doorbell_index); -void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev, - bool enable); -void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev, - bool use_doorbell, int doorbell_index); -void nbio_v7_0_ih_control(struct amdgpu_device *adev); -u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev); -void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, - bool enable); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index e190ce163e30..79e82bf35f7d 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -359,12 +359,7 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask = 0; - const struct nbio_hdp_flush_reg *nbio_hf_reg; - - if (ring->adev->flags & AMD_IS_APU) - nbio_hf_reg = &nbio_v7_0_hdp_flush_reg; - else - nbio_hf_reg = &nbio_v6_1_hdp_flush_reg; + const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; if (ring == &ring->adev->sdma.instance[0].ring) ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; @@ -629,10 +624,8 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) } WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); - if (adev->flags & AMD_IS_APU) - nbio_v7_0_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); - else - nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); + adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, + ring->doorbell_index); if (amdgpu_sriov_vf(adev)) sdma_v4_0_ring_set_wptr(ring); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 2752d8d3e5ae..873813fcc084 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -228,10 +228,7 @@ static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) static u32 soc15_get_config_memsize(struct amdgpu_device *adev) { - if (adev->flags & AMD_IS_APU) - return nbio_v7_0_get_memsize(adev); - else - return nbio_v6_1_get_memsize(adev); + return adev->nbio_funcs->get_memsize(adev); } static const u32 vega10_golden_init[] = @@ -460,9 +457,8 @@ static int soc15_asic_reset(struct amdgpu_device *adev) /* wait for asic to come out of reset */ for (i = 0; i < adev->usec_timeout; i++) { - u32 memsize = (adev->flags & AMD_IS_APU) ? - nbio_v7_0_get_memsize(adev) : - nbio_v6_1_get_memsize(adev); + u32 memsize = adev->nbio_funcs->get_memsize(adev); + if (memsize != 0xffffffff) break; udelay(1); @@ -527,14 +523,10 @@ static void soc15_program_aspm(struct amdgpu_device *adev) } static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, - bool enable) + bool enable) { - if (adev->flags & AMD_IS_APU) { - nbio_v7_0_enable_doorbell_aperture(adev, enable); - } else { - nbio_v6_1_enable_doorbell_aperture(adev, enable); - nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable); - } + adev->nbio_funcs->enable_doorbell_aperture(adev, enable); + adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable); } static const struct amdgpu_ip_block_version vega10_common_ip_block = @@ -558,7 +550,12 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) return -EINVAL; } - nbio_v6_1_detect_hw_virt(adev); + if (adev->flags & AMD_IS_APU) + adev->nbio_funcs = &nbio_v7_0_funcs; + else + adev->nbio_funcs = &nbio_v6_1_funcs; + + adev->nbio_funcs->detect_hw_virt(adev); if (amdgpu_sriov_vf(adev)) adev->virt.ops = &xgpu_ai_virt_ops; @@ -612,10 +609,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) { - if (adev->flags & AMD_IS_APU) - return nbio_v7_0_get_rev_id(adev); - else - return nbio_v6_1_get_rev_id(adev); + return adev->nbio_funcs->get_rev_id(adev); } static const struct amdgpu_asic_funcs soc15_asic_funcs = @@ -651,11 +645,6 @@ static int soc15_common_early_init(void *handle) adev->asic_funcs = &soc15_asic_funcs; - if (adev->flags & AMD_IS_APU) - adev->nbio_funcs = &nbio_v7_0_funcs; - else - adev->nbio_funcs = &nbio_v6_1_funcs; - if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) psp_enabled = true; @@ -763,8 +752,7 @@ static int soc15_common_hw_init(void *handle) /* enable aspm */ soc15_program_aspm(adev); /* setup nbio registers */ - if (!(adev->flags & AMD_IS_APU)) - nbio_v6_1_init_registers(adev); + adev->nbio_funcs->init_registers(adev); /* enable the doorbell aperture */ soc15_enable_doorbell_aperture(adev, true); @@ -925,9 +913,9 @@ static int soc15_common_set_clockgating_state(void *handle, switch (adev->asic_type) { case CHIP_VEGA10: - nbio_v6_1_update_medium_grain_clock_gating(adev, + adev->nbio_funcs->update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); - nbio_v6_1_update_medium_grain_light_sleep(adev, + adev->nbio_funcs->update_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE ? true : false); soc15_update_hdp_light_sleep(adev, state == AMD_CG_STATE_GATE ? true : false); @@ -941,9 +929,9 @@ static int soc15_common_set_clockgating_state(void *handle, state == AMD_CG_STATE_GATE ? true : false); break; case CHIP_RAVEN: - nbio_v7_0_update_medium_grain_clock_gating(adev, + adev->nbio_funcs->update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); - nbio_v6_1_update_medium_grain_light_sleep(adev, + adev->nbio_funcs->update_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE ? true : false); soc15_update_hdp_light_sleep(adev, state == AMD_CG_STATE_GATE ? true : false); @@ -968,7 +956,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags) if (amdgpu_sriov_vf(adev)) *flags = 0; - nbio_v6_1_get_clockgating_state(adev, flags); + adev->nbio_funcs->get_clockgating_state(adev, flags); /* AMD_CG_SUPPORT_HDP_LS */ data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index 413951c33983..def865067edd 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -24,22 +24,6 @@ #ifndef __SOC15_COMMON_H__ #define __SOC15_COMMON_H__ -struct nbio_hdp_flush_reg { - u32 ref_and_mask_cp0; - u32 ref_and_mask_cp1; - u32 ref_and_mask_cp2; - u32 ref_and_mask_cp3; - u32 ref_and_mask_cp4; - u32 ref_and_mask_cp5; - u32 ref_and_mask_cp6; - u32 ref_and_mask_cp7; - u32 ref_and_mask_cp8; - u32 ref_and_mask_cp9; - u32 ref_and_mask_sdma0; - u32 ref_and_mask_sdma1; -}; - - /* Register Access Macros */ #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index a1d8bbbb269c..e1d7dae0989b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -95,10 +95,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) /* disable irqs */ vega10_ih_disable_interrupts(adev); - if (adev->flags & AMD_IS_APU) - nbio_v7_0_ih_control(adev); - else - nbio_v6_1_ih_control(adev); + adev->nbio_funcs->ih_control(adev); ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ @@ -149,10 +146,8 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) ENABLE, 0); } WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); - if (adev->flags & AMD_IS_APU) - nbio_v7_0_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); - else - nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); + adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, + adev->irq.ih.doorbell_index); tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, -- GitLab From 670b603c111387bb875d747a71927d764af1021d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 8 Dec 2017 13:11:33 -0500 Subject: [PATCH 1421/2547] drm/amdgpu: drop the bios scratch reg callbacks from nbio MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit They are not used any longer. We get the scratch register locations from the vbios directly now. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 --- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 14 -------------- drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 14 -------------- 3 files changed, 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c73eca86c9f1..c31c5496dc5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1451,9 +1451,6 @@ struct amdgpu_nbio_funcs { u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); u32 (*get_rev_id)(struct amdgpu_device *adev); - u32 (*get_atombios_scratch_regs)(struct amdgpu_device *adev, uint32_t idx); - void (*set_atombios_scratch_regs)(struct amdgpu_device *adev, - uint32_t idx, uint32_t val); void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); void (*hdp_flush)(struct amdgpu_device *adev); u32 (*get_memsize)(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index 0d3514808092..d4da663d5eb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -43,18 +43,6 @@ static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) return tmp; } -static u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev, - uint32_t idx) -{ - return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx); -} - -static void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev, - uint32_t idx, uint32_t val) -{ - WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val); -} - static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) { if (enable) @@ -284,8 +272,6 @@ const struct amdgpu_nbio_funcs nbio_v6_1_funcs = { .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset, .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset, .get_rev_id = nbio_v6_1_get_rev_id, - .get_atombios_scratch_regs = nbio_v6_1_get_atombios_scratch_regs, - .set_atombios_scratch_regs = nbio_v6_1_set_atombios_scratch_regs, .mc_access_enable = nbio_v6_1_mc_access_enable, .hdp_flush = nbio_v6_1_hdp_flush, .get_memsize = nbio_v6_1_get_memsize, diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index 29d7b4fd7a88..17a9131a4598 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -44,18 +44,6 @@ static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev) return tmp; } -static u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev, - uint32_t idx) -{ - return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx); -} - -static void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev, - uint32_t idx, uint32_t val) -{ - WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val); -} - static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable) { if (enable) @@ -279,8 +267,6 @@ const struct amdgpu_nbio_funcs nbio_v7_0_funcs = { .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset, .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset, .get_rev_id = nbio_v7_0_get_rev_id, - .get_atombios_scratch_regs = nbio_v7_0_get_atombios_scratch_regs, - .set_atombios_scratch_regs = nbio_v7_0_set_atombios_scratch_regs, .mc_access_enable = nbio_v7_0_mc_access_enable, .hdp_flush = nbio_v7_0_hdp_flush, .get_memsize = nbio_v7_0_get_memsize, -- GitLab From 2dd744e0ce2a34cb6b77a80385eee827a6a1ee24 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 8 Dec 2017 13:18:23 -0500 Subject: [PATCH 1422/2547] drm/amdgpu: drop soc15_init_golden_registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The golden register arrays were empty so the function was effectively useless. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 31 ------------------------------ 1 file changed, 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 873813fcc084..49ff552cd6fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -231,35 +231,6 @@ static u32 soc15_get_config_memsize(struct amdgpu_device *adev) return adev->nbio_funcs->get_memsize(adev); } -static const u32 vega10_golden_init[] = -{ -}; - -static const u32 raven_golden_init[] = -{ -}; - -static void soc15_init_golden_registers(struct amdgpu_device *adev) -{ - /* Some of the registers might be dependent on GRBM_GFX_INDEX */ - mutex_lock(&adev->grbm_idx_mutex); - - switch (adev->asic_type) { - case CHIP_VEGA10: - amdgpu_program_register_sequence(adev, - vega10_golden_init, - ARRAY_SIZE(vega10_golden_init)); - break; - case CHIP_RAVEN: - amdgpu_program_register_sequence(adev, - raven_golden_init, - ARRAY_SIZE(raven_golden_init)); - break; - default: - break; - } - mutex_unlock(&adev->grbm_idx_mutex); -} static u32 soc15_get_xclk(struct amdgpu_device *adev) { return adev->clock.spll.reference_freq; @@ -745,8 +716,6 @@ static int soc15_common_hw_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - /* move the golden regs per IP block */ - soc15_init_golden_registers(adev); /* enable pcie gen2/3 link */ soc15_pcie_gen3_enable(adev); /* enable aspm */ -- GitLab From e466c2935fe196f4c9d512650f1224f194a00b51 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 8 Dec 2017 17:02:24 -0500 Subject: [PATCH 1423/2547] drm/amdgpu: remove some old gc 9.x registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Leftover from bring up. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h | 8 ++-- .../amd/include/asic_reg/gc/gc_9_0_default.h | 7 --- .../amd/include/asic_reg/gc/gc_9_0_offset.h | 14 ------ .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 45 ------------------- .../amd/include/asic_reg/gc/gc_9_1_offset.h | 14 ------ 5 files changed, 4 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h index 003a131bad47..567a904804bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h +++ b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h @@ -48,7 +48,7 @@ static const unsigned int gfx9_SECT_CONTEXT_def_1[] = 0x00000000, // DB_STENCIL_WRITE_BASE 0x00000000, // DB_STENCIL_WRITE_BASE_HI 0x00000000, // DB_DFSM_CONTROL - 0x00000000, // DB_RENDER_FILTER + 0, // HOLE 0x00000000, // DB_Z_INFO2 0x00000000, // DB_STENCIL_INFO2 0, // HOLE @@ -259,8 +259,8 @@ static const unsigned int gfx9_SECT_CONTEXT_def_2[] = 0x00000000, // PA_SC_RIGHT_VERT_GRID 0x00000000, // PA_SC_LEFT_VERT_GRID 0x00000000, // PA_SC_HORIZ_GRID - 0x00000000, // PA_SC_FOV_WINDOW_LR - 0x00000000, // PA_SC_FOV_WINDOW_TB + 0, // HOLE + 0, // HOLE 0, // HOLE 0, // HOLE 0, // HOLE @@ -701,7 +701,7 @@ static const unsigned int gfx9_SECT_CONTEXT_def_7[] = { 0x00000000, // VGT_GS_MAX_PRIMS_PER_SUBGROUP 0x00000000, // VGT_DRAW_PAYLOAD_CNTL - 0x00000000, // VGT_INDEX_PAYLOAD_CNTL + 0, // HOLE 0x00000000, // VGT_INSTANCE_STEP_RATE_0 0x00000000, // VGT_INSTANCE_STEP_RATE_1 0, // HOLE diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h index 663d3af35baf..5bf84c6d0ec3 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h @@ -436,7 +436,6 @@ #define mmTA_CNTL_DEFAULT 0x8004d850 #define mmTA_CNTL_AUX_DEFAULT 0x00000000 #define mmTA_RESERVED_010C_DEFAULT 0x00000000 -#define mmTA_GRAD_ADJ_DEFAULT 0x40000040 #define mmTA_STATUS_DEFAULT 0x00000000 #define mmTA_SCRATCH_DEFAULT 0x00000000 @@ -1700,7 +1699,6 @@ #define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000 #define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000 #define mmDB_DFSM_CONTROL_DEFAULT 0x00000000 -#define mmDB_RENDER_FILTER_DEFAULT 0x00000000 #define mmDB_Z_INFO2_DEFAULT 0x00000000 #define mmDB_STENCIL_INFO2_DEFAULT 0x00000000 #define mmTA_BC_BASE_ADDR_DEFAULT 0x00000000 @@ -1806,8 +1804,6 @@ #define mmPA_SC_RIGHT_VERT_GRID_DEFAULT 0x00000000 #define mmPA_SC_LEFT_VERT_GRID_DEFAULT 0x00000000 #define mmPA_SC_HORIZ_GRID_DEFAULT 0x00000000 -#define mmPA_SC_FOV_WINDOW_LR_DEFAULT 0x00000000 -#define mmPA_SC_FOV_WINDOW_TB_DEFAULT 0x00000000 #define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000 #define mmCB_BLEND_RED_DEFAULT 0x00000000 #define mmCB_BLEND_GREEN_DEFAULT 0x00000000 @@ -2072,7 +2068,6 @@ #define mmVGT_EVENT_INITIATOR_DEFAULT 0x00000000 #define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT 0x00000000 #define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000 -#define mmVGT_INDEX_PAYLOAD_CNTL_DEFAULT 0x00000000 #define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 0x00000000 #define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 0x00000000 #define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000 @@ -2490,7 +2485,6 @@ #define mmWD_INDEX_BUF_BASE_DEFAULT 0x00000000 #define mmWD_INDEX_BUF_BASE_HI_DEFAULT 0x00000000 #define mmIA_MULTI_VGT_PARAM_DEFAULT 0x006000ff -#define mmVGT_OBJECT_ID_DEFAULT 0x00000000 #define mmVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000 #define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000 #define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000 @@ -2534,7 +2528,6 @@ #define mmSQC_WRITEBACK_DEFAULT 0x00000000 #define mmTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000 #define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmTA_GRAD_ADJ_UCONFIG_DEFAULT 0x40000040 #define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000 #define mmDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000 #define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h index e6d6171aa8b9..4ce090db7ef7 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h @@ -841,8 +841,6 @@ #define mmTA_CNTL_AUX_BASE_IDX 0 #define mmTA_RESERVED_010C 0x0543 #define mmTA_RESERVED_010C_BASE_IDX 0 -#define mmTA_GRAD_ADJ 0x0544 -#define mmTA_GRAD_ADJ_BASE_IDX 0 #define mmTA_STATUS 0x0548 #define mmTA_STATUS_BASE_IDX 0 #define mmTA_SCRATCH 0x0564 @@ -3330,8 +3328,6 @@ #define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 #define mmDB_DFSM_CONTROL 0x0018 #define mmDB_DFSM_CONTROL_BASE_IDX 1 -#define mmDB_RENDER_FILTER 0x0019 -#define mmDB_RENDER_FILTER_BASE_IDX 1 #define mmDB_Z_INFO2 0x001a #define mmDB_Z_INFO2_BASE_IDX 1 #define mmDB_STENCIL_INFO2 0x001b @@ -3542,10 +3538,6 @@ #define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1 #define mmPA_SC_HORIZ_GRID 0x00ea #define mmPA_SC_HORIZ_GRID_BASE_IDX 1 -#define mmPA_SC_FOV_WINDOW_LR 0x00eb -#define mmPA_SC_FOV_WINDOW_LR_BASE_IDX 1 -#define mmPA_SC_FOV_WINDOW_TB 0x00ec -#define mmPA_SC_FOV_WINDOW_TB_BASE_IDX 1 #define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 #define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 #define mmCB_BLEND_RED 0x0105 @@ -4074,8 +4066,6 @@ #define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 #define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6 #define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 -#define mmVGT_INDEX_PAYLOAD_CNTL 0x02a7 -#define mmVGT_INDEX_PAYLOAD_CNTL_BASE_IDX 1 #define mmVGT_INSTANCE_STEP_RATE_0 0x02a8 #define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 #define mmVGT_INSTANCE_STEP_RATE_1 0x02a9 @@ -4908,8 +4898,6 @@ #define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1 #define mmIA_MULTI_VGT_PARAM 0x2258 #define mmIA_MULTI_VGT_PARAM_BASE_IDX 1 -#define mmVGT_OBJECT_ID 0x2259 -#define mmVGT_OBJECT_ID_BASE_IDX 1 #define mmVGT_INSTANCE_BASE_ID 0x225a #define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1 #define mmPA_SU_LINE_STIPPLE_VALUE 0x2280 @@ -4996,8 +4984,6 @@ #define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1 #define mmTA_CS_BC_BASE_ADDR_HI 0x2381 #define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 -#define mmTA_GRAD_ADJ_UCONFIG 0x2382 -#define mmTA_GRAD_ADJ_UCONFIG_BASE_IDX 1 #define mmDB_OCCLUSION_COUNT0_LOW 0x23c0 #define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 #define mmDB_OCCLUSION_COUNT0_HI 0x23c1 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h index 5c5e9b445432..2e1214be67a2 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h @@ -4576,15 +4576,6 @@ //TA_RESERVED_010C #define TA_RESERVED_010C__Unused__SHIFT 0x0 #define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL -//TA_GRAD_ADJ -#define TA_GRAD_ADJ__GRAD_ADJ_0__SHIFT 0x0 -#define TA_GRAD_ADJ__GRAD_ADJ_1__SHIFT 0x8 -#define TA_GRAD_ADJ__GRAD_ADJ_2__SHIFT 0x10 -#define TA_GRAD_ADJ__GRAD_ADJ_3__SHIFT 0x18 -#define TA_GRAD_ADJ__GRAD_ADJ_0_MASK 0x000000FFL -#define TA_GRAD_ADJ__GRAD_ADJ_1_MASK 0x0000FF00L -#define TA_GRAD_ADJ__GRAD_ADJ_2_MASK 0x00FF0000L -#define TA_GRAD_ADJ__GRAD_ADJ_3_MASK 0xFF000000L //TA_STATUS #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd @@ -14459,9 +14450,6 @@ #define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L -//DB_RENDER_FILTER -#define DB_RENDER_FILTER__PS_INVOKE_MASK__SHIFT 0x0 -#define DB_RENDER_FILTER__PS_INVOKE_MASK_MASK 0x0000FFFFL //DB_Z_INFO2 #define DB_Z_INFO2__EPITCH__SHIFT 0x0 #define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL @@ -14959,11 +14947,9 @@ #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 -#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8 #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L -#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L //CP_PERFMON_CNTX_CNTL #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L @@ -15003,20 +14989,6 @@ #define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L #define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L #define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L -//PA_SC_FOV_WINDOW_LR -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT__SHIFT 0x0 -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT__SHIFT 0x8 -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT__SHIFT 0x10 -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT__SHIFT 0x18 -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT_MASK 0x000000FFL -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT_MASK 0x0000FF00L -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT_MASK 0x00FF0000L -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT_MASK 0xFF000000L -//PA_SC_FOV_WINDOW_TB -#define PA_SC_FOV_WINDOW_TB__FOV_TOP__SHIFT 0x0 -#define PA_SC_FOV_WINDOW_TB__FOV_BOT__SHIFT 0x8 -#define PA_SC_FOV_WINDOW_TB__FOV_TOP_MASK 0x000000FFL -#define PA_SC_FOV_WINDOW_TB__FOV_BOT_MASK 0x0000FF00L //VGT_MULTI_PRIM_IB_RESET_INDX #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL @@ -17010,13 +16982,11 @@ #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L //PA_CL_OBJPRIM_ID_CNTL #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0 #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1 @@ -17345,9 +17315,6 @@ #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L #define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L -//VGT_INDEX_PAYLOAD_CNTL -#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN__SHIFT 0x0 -#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN_MASK 0x00000001L //VGT_INSTANCE_STEP_RATE_0 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL @@ -19849,9 +19816,6 @@ #define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L #define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L #define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L -//VGT_OBJECT_ID -#define VGT_OBJECT_ID__REG_OBJ_ID__SHIFT 0x0 -#define VGT_OBJECT_ID__REG_OBJ_ID_MASK 0xFFFFFFFFL //VGT_INSTANCE_BASE_ID #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL @@ -20067,15 +20031,6 @@ //TA_CS_BC_BASE_ADDR_HI #define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 #define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL -//TA_GRAD_ADJ_UCONFIG -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0__SHIFT 0x0 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1__SHIFT 0x8 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2__SHIFT 0x10 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3__SHIFT 0x18 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0_MASK 0x000000FFL -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1_MASK 0x0000FF00L -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2_MASK 0x00FF0000L -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3_MASK 0xFF000000L //DB_OCCLUSION_COUNT0_LOW #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h index db7ef5ede0e5..030e0020902b 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h @@ -815,8 +815,6 @@ #define mmTA_CNTL_AUX_BASE_IDX 0 #define mmTA_RESERVED_010C 0x0543 #define mmTA_RESERVED_010C_BASE_IDX 0 -#define mmTA_GRAD_ADJ 0x0544 -#define mmTA_GRAD_ADJ_BASE_IDX 0 #define mmTA_STATUS 0x0548 #define mmTA_STATUS_BASE_IDX 0 #define mmTA_SCRATCH 0x0564 @@ -3617,8 +3615,6 @@ #define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 #define mmDB_DFSM_CONTROL 0x0018 #define mmDB_DFSM_CONTROL_BASE_IDX 1 -#define mmDB_RENDER_FILTER 0x0019 -#define mmDB_RENDER_FILTER_BASE_IDX 1 #define mmDB_Z_INFO2 0x001a #define mmDB_Z_INFO2_BASE_IDX 1 #define mmDB_STENCIL_INFO2 0x001b @@ -3829,10 +3825,6 @@ #define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1 #define mmPA_SC_HORIZ_GRID 0x00ea #define mmPA_SC_HORIZ_GRID_BASE_IDX 1 -#define mmPA_SC_FOV_WINDOW_LR 0x00eb -#define mmPA_SC_FOV_WINDOW_LR_BASE_IDX 1 -#define mmPA_SC_FOV_WINDOW_TB 0x00ec -#define mmPA_SC_FOV_WINDOW_TB_BASE_IDX 1 #define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 #define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 #define mmCB_BLEND_RED 0x0105 @@ -4361,8 +4353,6 @@ #define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 #define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6 #define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 -#define mmVGT_INDEX_PAYLOAD_CNTL 0x02a7 -#define mmVGT_INDEX_PAYLOAD_CNTL_BASE_IDX 1 #define mmVGT_INSTANCE_STEP_RATE_0 0x02a8 #define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 #define mmVGT_INSTANCE_STEP_RATE_1 0x02a9 @@ -5195,8 +5185,6 @@ #define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1 #define mmIA_MULTI_VGT_PARAM 0x2258 #define mmIA_MULTI_VGT_PARAM_BASE_IDX 1 -#define mmVGT_OBJECT_ID 0x2259 -#define mmVGT_OBJECT_ID_BASE_IDX 1 #define mmVGT_INSTANCE_BASE_ID 0x225a #define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1 #define mmPA_SU_LINE_STIPPLE_VALUE 0x2280 @@ -5283,8 +5271,6 @@ #define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1 #define mmTA_CS_BC_BASE_ADDR_HI 0x2381 #define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 -#define mmTA_GRAD_ADJ_UCONFIG 0x2382 -#define mmTA_GRAD_ADJ_UCONFIG_BASE_IDX 1 #define mmDB_OCCLUSION_COUNT0_LOW 0x23c0 #define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 #define mmDB_OCCLUSION_COUNT0_HI 0x23c1 -- GitLab From 4ec6ecf48c64d1da82a008f6fb0be86c4044287d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 12 Dec 2017 15:20:22 -0500 Subject: [PATCH 1424/2547] drm/amdgpu: drop scratch regs save and restore from S3/S4 handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The expectation is that the base driver doesn't mess with these. Some components interact with these directly so let the components handle these directly. Reviewed-by: Harry Wentland Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 98d62a991b67..ca1cf8a71dda 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2577,7 +2577,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) */ amdgpu_bo_evict_vram(adev); - amdgpu_atombios_scratch_regs_save(adev); pci_save_state(dev->pdev); if (suspend) { /* Shut down the device */ @@ -2626,7 +2625,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) if (r) goto unlock; } - amdgpu_atombios_scratch_regs_restore(adev); /* post card */ if (amdgpu_need_post(adev)) { -- GitLab From 88bc1e3c38aaadbedd1df96e8bbe62b06f7cda1f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 12 Dec 2017 15:22:56 -0500 Subject: [PATCH 1425/2547] drm/amdgpu: drop scratch regs save and restore from GPU reset handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The expectation is that the base driver doesn't mess with these. Some components interact with these directly so let the components handle these directly. Reviewed-by: Harry Wentland Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ca1cf8a71dda..046b9d5bc14d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2896,9 +2896,7 @@ static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags) r = amdgpu_suspend(adev); retry: - amdgpu_atombios_scratch_regs_save(adev); r = amdgpu_asic_reset(adev); - amdgpu_atombios_scratch_regs_restore(adev); /* post card */ amdgpu_atom_asic_init(adev->mode_info.atom_context); -- GitLab From 44da0d57db175b02f36a2ecf3c9b89cf24a476c4 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 12 Dec 2017 15:26:10 -0500 Subject: [PATCH 1426/2547] drm/amdgpu: drop amdgpu_atombios_scratch_regs_save/restore MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No longer used. Reviewed-by: Harry Wentland Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 22 -------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 2 -- 2 files changed, 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 39f4d0df1ada..ffaf0534e33c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1721,28 +1721,6 @@ void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev) WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch); } -void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev) -{ - int i; - - for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) - adev->bios_scratch[i] = RREG32(adev->bios_scratch_reg_offset + i); -} - -void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev) -{ - int i; - - /* - * VBIOS will check ASIC_INIT_COMPLETE bit to decide if - * execute ASIC_Init posting via driver - */ - adev->bios_scratch[7] &= ~ATOM_S7_ASIC_INIT_COMPLETE_MASK; - - for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) - WREG32(adev->bios_scratch_reg_offset + i, adev->bios_scratch[i]); -} - void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev, bool hung) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h index b0d5d1d7fdba..58507f9ff856 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h @@ -196,8 +196,6 @@ bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev); void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock); void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev); -void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev); -void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev); void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev, bool hung); bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev); -- GitLab From c4c3351783cb1758801a5928c98b0dcb2074c082 Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Mon, 11 Dec 2017 15:55:03 +0800 Subject: [PATCH 1427/2547] drm/amdgpu: fix huge page setting for ATS case MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 68039ad3c8e0..709587d8a77f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -343,7 +343,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, if (vm->pte_support_ats) { init_value = AMDGPU_PTE_DEFAULT_ATC; - if (level != adev->vm_manager.num_level - 1) + if (level != adev->vm_manager.num_level) init_value |= AMDGPU_PDE_PTE; } -- GitLab From 7364d60882bfe87aa170a5e69a84872692469088 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Tue, 12 Dec 2017 15:06:10 +0800 Subject: [PATCH 1428/2547] drm/amd/pp: implement dpm_get_sclk/mclk for RV RV implementation was missing these callbacks. Used to fetch the clock values for other components. Reviewed-by: Alex Deucher Reviewed-by: Evan Quan Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- .../gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 25 +++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c index 3e0b267c74a8..027fd630355a 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c @@ -523,12 +523,33 @@ static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, static uint32_t rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) { - return 0; + struct rv_hwmgr *data; + + if (hwmgr == NULL) + return -EINVAL; + + data = (struct rv_hwmgr *)(hwmgr->backend); + + if (low) + return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; + else + return data->clock_vol_info.vdd_dep_on_fclk->entries[ + data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk; } static uint32_t rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) { - return 0; + struct rv_hwmgr *data; + + if (hwmgr == NULL) + return -EINVAL; + + data = (struct rv_hwmgr *)(hwmgr->backend); + + if (low) + return data->gfx_min_freq_limit; + else + return data->gfx_max_freq_limit; } static int rv_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, -- GitLab From bd36d3bab2e3d08f80766c86487090dbceed4651 Mon Sep 17 00:00:00 2001 From: Marius Vlad Date: Wed, 13 Dec 2017 20:10:48 +0200 Subject: [PATCH 1429/2547] drm/drm_lease: Prevent deadlock in case drm_lease_create() fails This case can been seen when creating the lease with the same objects passed. [ 605.515097] 2 locks held by testapp/3337: [ 605.519027] #0: (&dev->mode_config.idr_mutex){......}, at: [] drm_mode_create_lease_ioctl+0x384/0x858 [ 605.530045] #1: (&dev->mode_config.idr_mutex){......}, at: [] drm_lease_destroy+0x2c/0x110 Which was causing the process to hang: [ 605.398827] [] __switch_to+0x94/0xa8 [ 605.404030] [] __schedule+0x1b0/0x698 [ 605.409322] [] schedule+0x3c/0xa8 [ 605.414260] [] schedule_preempt_disabled+0x20/0x38 [ 605.420677] [] mutex_lock_nested+0x158/0x340 [ 605.426572] [] drm_lease_destroy+0x2c/0x110 [ 605.432389] [] drm_master_put+0xc0/0xc8 [ 605.437845] [] drm_mode_create_lease_ioctl+0x47c/0x858 [ 605.444612] [] drm_ioctl+0x198/0x448 [ 605.449811] [] do_vfs_ioctl+0xa4/0x748 [ 605.455192] [] SyS_ioctl+0x8c/0xa0 [ 605.460216] [] __sys_trace_return+0x0/0x4 drm_mode_create_lease_ioctl() calls drm_lease_create() which acquires a lock on dev->mode_config.idr_mutex. In case of failure, drm_lease_create() calls drm_master_put() which in turn tries to acquire the same lock when calling drm_lease_destroy(). v2: - Reverse the order at exit in case of fail, so that unlocking takes place before dropping the reference. - Include detail information about deadlock (Daniel Vetter) Signed-off-by: Marius Vlad Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20171213181048.32719-1-marius-cristian.vlad@nxp.com --- drivers/gpu/drm/drm_lease.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_lease.c b/drivers/gpu/drm/drm_lease.c index d1eb56a1eff4..59849f02e2ad 100644 --- a/drivers/gpu/drm/drm_lease.c +++ b/drivers/gpu/drm/drm_lease.c @@ -254,10 +254,10 @@ static struct drm_master *drm_lease_create(struct drm_master *lessor, struct idr return lessee; out_lessee: - drm_master_put(&lessee); - mutex_unlock(&dev->mode_config.idr_mutex); + drm_master_put(&lessee); + return ERR_PTR(error); } -- GitLab From 1bbbca0db722d137ed426368bff42b17808ad11e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= Date: Wed, 13 Dec 2017 23:13:46 +0100 Subject: [PATCH 1430/2547] drm/i915/guc: Move shared data allocation away from submission path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need shared data for actions (e.g. guc suspend/resume), and we're using those with GuC submission disabled. Let's introduce intel_guc_init and move shared data alloc there. This fixes GPF during module unload with HuC, but without GuC submission: BUG: unable to handle kernel NULL pointer dereference at 000000005aee7809 IP: intel_guc_suspend+0x34/0x140 [i915] PGD 0 P4D 0 Oops: 0000 [#1] PREEMPT SMP Modules linked in: i915(O-) netconsole x86_pkg_temp_thermal intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel mei_me i2c_i801 mei prime_numbers [last unloaded: i915] CPU: 2 PID: 2794 Comm: rmmod Tainted: G U W O 4.15.0-rc2+ #297 Hardware name: /NUC6i5SYB, BIOS SYSKLi35.86A.0054.2016.0930.1102 09/30/2016 task: 0000000055945c61 task.stack: 00000000264ccb43 RIP: 0010:intel_guc_suspend+0x34/0x140 [i915] RSP: 0018:ffffc90000483df8 EFLAGS: 00010286 RAX: 0000000000000000 RBX: ffff880829180000 RCX: 0000000000000000 RDX: 0000000000000006 RSI: ffff880844c2c938 RDI: ffff880844c2c000 RBP: ffff880829180000 R08: 00000000a29c58c1 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000000 R12: ffffffffa040ba40 R13: ffffffffa040bab0 R14: ffff88084a195060 R15: 000055df3ef357a0 FS: 00007ff43c043740(0000) GS:ffff88084e200000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00000000000000f9 CR3: 000000083f179005 CR4: 00000000003606e0 Call Trace: i915_gem_suspend+0x9d/0x130 [i915] ? i915_driver_unload+0x68/0x180 [i915] i915_driver_unload+0x70/0x180 [i915] i915_pci_remove+0x15/0x20 [i915] pci_device_remove+0x36/0xb0 device_release_driver_internal+0x15f/0x220 driver_detach+0x3a/0x80 bus_remove_driver+0x58/0xd0 pci_unregister_driver+0x29/0x90 SyS_delete_module+0x150/0x1e0 entry_SYSCALL_64_fastpath+0x23/0x9a RIP: 0033:0x7ff43b51b5c7 RSP: 002b:00007ffe6825a758 EFLAGS: 00000206 ORIG_RAX: 00000000000000b0 RAX: ffffffffffffffda RBX: 0000000000000003 RCX: 00007ff43b51b5c7 RDX: 000000000000000a RSI: 0000000000000800 RDI: 000055df3ef35808 RBP: 0000000000000000 R08: 00007ffe682596d1 R09: 0000000000000000 R10: 00007ff43b594880 R11: 0000000000000206 R12: 000055df3ef357a0 R13: 00007ffe68259740 R14: 000055df3ef35260 R15: 000055df3ef357a0 Code: 00 00 02 74 03 31 c0 c3 53 48 89 fb 48 83 ec 10 e8 52 0f f8 ff 48 b8 01 05 00 00 02 00 00 00 48 89 44 24 04 48 8b 83 00 12 00 00 80 f9 00 00 00 01 0f 84 a7 00 00 00 f6 80 98 00 00 00 01 0f RIP: intel_guc_suspend+0x34/0x140 [i915] RSP: ffffc90000483df8 CR2: 00000000000000f9 ---[ end trace 23a192a61d937a3e ]--- Fixes: b8e5eb960b28 ("drm/i915/guc: Allocate separate shared data object for GuC communication") Signed-off-by: Michał Winiarski Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Michal Wajdeczko Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171213221352.7173-1-michal.winiarski@intel.com --- drivers/gpu/drm/i915/intel_guc.c | 51 +++++++++++++++++++++ drivers/gpu/drm/i915/intel_guc.h | 2 + drivers/gpu/drm/i915/intel_guc_submission.c | 37 +-------------- drivers/gpu/drm/i915/intel_uc.c | 10 ++-- 4 files changed, 60 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 177ee69ca9b1..92ed22f38fc4 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -69,6 +69,57 @@ void intel_guc_init_early(struct intel_guc *guc) guc->notify = gen8_guc_raise_irq; } +static int guc_shared_data_create(struct intel_guc *guc) +{ + struct i915_vma *vma; + void *vaddr; + + vma = intel_guc_allocate_vma(guc, PAGE_SIZE); + if (IS_ERR(vma)) + return PTR_ERR(vma); + + vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); + if (IS_ERR(vaddr)) { + i915_vma_unpin_and_release(&vma); + return PTR_ERR(vaddr); + } + + guc->shared_data = vma; + guc->shared_data_vaddr = vaddr; + + return 0; +} + +static void guc_shared_data_destroy(struct intel_guc *guc) +{ + i915_gem_object_unpin_map(guc->shared_data->obj); + i915_vma_unpin_and_release(&guc->shared_data); +} + +int intel_guc_init(struct intel_guc *guc) +{ + struct drm_i915_private *dev_priv = guc_to_i915(guc); + int ret; + + ret = guc_shared_data_create(guc); + if (ret) + return ret; + GEM_BUG_ON(!guc->shared_data); + + /* We need to notify the guc whenever we change the GGTT */ + i915_ggtt_enable_guc(dev_priv); + + return 0; +} + +void intel_guc_fini(struct intel_guc *guc) +{ + struct drm_i915_private *dev_priv = guc_to_i915(guc); + + i915_ggtt_disable_guc(dev_priv); + guc_shared_data_destroy(guc); +} + static u32 get_gt_type(struct drm_i915_private *dev_priv) { /* XXX: GT type based on PCI device ID? field seems unused by fw */ diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 59856726d2bc..81659e223e11 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -119,6 +119,8 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma) void intel_guc_init_early(struct intel_guc *guc); void intel_guc_init_send_regs(struct intel_guc *guc); void intel_guc_init_params(struct intel_guc *guc); +int intel_guc_init(struct intel_guc *guc); +void intel_guc_fini(struct intel_guc *guc); int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len); int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len); int intel_guc_sample_forcewake(struct intel_guc *guc); diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index 912ff143d531..c020560c395e 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -447,33 +447,6 @@ static void guc_stage_desc_fini(struct intel_guc *guc, memset(desc, 0, sizeof(*desc)); } -static int guc_shared_data_create(struct intel_guc *guc) -{ - struct i915_vma *vma; - void *vaddr; - - vma = intel_guc_allocate_vma(guc, PAGE_SIZE); - if (IS_ERR(vma)) - return PTR_ERR(vma); - - vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); - if (IS_ERR(vaddr)) { - i915_vma_unpin_and_release(&vma); - return PTR_ERR(vaddr); - } - - guc->shared_data = vma; - guc->shared_data_vaddr = vaddr; - - return 0; -} - -static void guc_shared_data_destroy(struct intel_guc *guc) -{ - i915_gem_object_unpin_map(guc->shared_data->obj); - i915_vma_unpin_and_release(&guc->shared_data); -} - /* Construct a Work Item and append it to the GuC's Work Queue */ static void guc_wq_item_append(struct intel_guc_client *client, u32 target_engine, u32 context_desc, @@ -1279,14 +1252,9 @@ int intel_guc_submission_init(struct intel_guc *guc) */ GEM_BUG_ON(!guc->stage_desc_pool); - ret = guc_shared_data_create(guc); - if (ret) - goto err_stage_desc_pool; - GEM_BUG_ON(!guc->shared_data); - ret = intel_guc_log_create(guc); if (ret < 0) - goto err_shared_data; + goto err_stage_desc_pool; ret = guc_preempt_work_create(guc); if (ret) @@ -1304,8 +1272,6 @@ int intel_guc_submission_init(struct intel_guc *guc) guc_preempt_work_destroy(guc); err_log: intel_guc_log_destroy(guc); -err_shared_data: - guc_shared_data_destroy(guc); err_stage_desc_pool: guc_stage_desc_pool_destroy(guc); return ret; @@ -1316,7 +1282,6 @@ void intel_guc_submission_fini(struct intel_guc *guc) guc_ads_destroy(guc); guc_preempt_work_destroy(guc); intel_guc_log_destroy(guc); - guc_shared_data_destroy(guc); guc_stage_desc_pool_destroy(guc); } diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 461047c86e0d..3040a0e00142 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -24,6 +24,7 @@ #include "intel_uc.h" #include "intel_guc_submission.h" +#include "intel_guc.h" #include "i915_drv.h" /* Reset GuC providing us with fresh state for both GuC and HuC. @@ -204,8 +205,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) guc_disable_communication(guc); gen9_reset_guc_interrupts(dev_priv); - /* We need to notify the guc whenever we change the GGTT */ - i915_ggtt_enable_guc(dev_priv); + ret = intel_guc_init(guc); + if (ret) + goto err_out; if (USES_GUC_SUBMISSION(dev_priv)) { /* @@ -298,7 +300,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) if (USES_GUC_SUBMISSION(dev_priv)) intel_guc_submission_fini(guc); err_guc: - i915_ggtt_disable_guc(dev_priv); + intel_guc_fini(guc); err_out: /* * Note that there is no fallback as either user explicitly asked for @@ -330,5 +332,5 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv) intel_guc_submission_fini(guc); } - i915_ggtt_disable_guc(dev_priv); + intel_guc_fini(guc); } -- GitLab From 3176ff49bc3e56871ec9f338cac759dacd0135e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= Date: Wed, 13 Dec 2017 23:13:47 +0100 Subject: [PATCH 1431/2547] drm/i915/guc: Move GuC workqueue allocations outside of the mutex MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This gets rid of the following lockdep splat: ====================================================== WARNING: possible circular locking dependency detected 4.15.0-rc2-CI-Patchwork_7428+ #1 Not tainted ------------------------------------------------------ debugfs_test/1351 is trying to acquire lock: (&dev->struct_mutex){+.+.}, at: [<000000009d90d1a3>] i915_mutex_lock_interruptible+0x47/0x130 [i915] but task is already holding lock: (&mm->mmap_sem){++++}, at: [<000000005df01c1e>] __do_page_fault+0x106/0x560 which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #6 (&mm->mmap_sem){++++}: __might_fault+0x63/0x90 _copy_to_user+0x1e/0x70 filldir+0x8c/0xf0 dcache_readdir+0xeb/0x160 iterate_dir+0xe6/0x150 SyS_getdents+0xa0/0x130 entry_SYSCALL_64_fastpath+0x1c/0x89 -> #5 (&sb->s_type->i_mutex_key#5){++++}: lockref_get+0x9/0x20 -> #4 ((completion)&req.done){+.+.}: wait_for_common+0x54/0x210 devtmpfs_create_node+0x130/0x150 device_add+0x5ad/0x5e0 device_create_groups_vargs+0xd4/0xe0 device_create+0x35/0x40 msr_device_create+0x22/0x40 cpuhp_invoke_callback+0xc5/0xbf0 cpuhp_thread_fun+0x167/0x210 smpboot_thread_fn+0x17f/0x270 kthread+0x173/0x1b0 ret_from_fork+0x24/0x30 -> #3 (cpuhp_state-up){+.+.}: cpuhp_issue_call+0x132/0x1c0 __cpuhp_setup_state_cpuslocked+0x12f/0x2a0 __cpuhp_setup_state+0x3a/0x50 page_writeback_init+0x3a/0x5c start_kernel+0x393/0x3e2 secondary_startup_64+0xa5/0xb0 -> #2 (cpuhp_state_mutex){+.+.}: __mutex_lock+0x81/0x9b0 __cpuhp_setup_state_cpuslocked+0x4b/0x2a0 __cpuhp_setup_state+0x3a/0x50 page_alloc_init+0x1f/0x26 start_kernel+0x139/0x3e2 secondary_startup_64+0xa5/0xb0 -> #1 (cpu_hotplug_lock.rw_sem){++++}: cpus_read_lock+0x34/0xa0 apply_workqueue_attrs+0xd/0x40 __alloc_workqueue_key+0x2c7/0x4e1 intel_guc_submission_init+0x10c/0x650 [i915] intel_uc_init_hw+0x29e/0x460 [i915] i915_gem_init_hw+0xca/0x290 [i915] i915_gem_init+0x115/0x3a0 [i915] i915_driver_load+0x9a8/0x16c0 [i915] i915_pci_probe+0x2e/0x90 [i915] pci_device_probe+0x9c/0x120 driver_probe_device+0x2a3/0x480 __driver_attach+0xd9/0xe0 bus_for_each_dev+0x57/0x90 bus_add_driver+0x168/0x260 driver_register+0x52/0xc0 do_one_initcall+0x39/0x150 do_init_module+0x56/0x1ef load_module+0x231c/0x2d70 SyS_finit_module+0xa5/0xe0 entry_SYSCALL_64_fastpath+0x1c/0x89 -> #0 (&dev->struct_mutex){+.+.}: lock_acquire+0xaf/0x200 __mutex_lock+0x81/0x9b0 i915_mutex_lock_interruptible+0x47/0x130 [i915] i915_gem_fault+0x201/0x760 [i915] __do_fault+0x15/0x70 __handle_mm_fault+0x85b/0xe40 handle_mm_fault+0x14f/0x2f0 __do_page_fault+0x2d1/0x560 page_fault+0x22/0x30 other info that might help us debug this: Chain exists of: &dev->struct_mutex --> &sb->s_type->i_mutex_key#5 --> &mm->mmap_sem Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&mm->mmap_sem); lock(&sb->s_type->i_mutex_key#5); lock(&mm->mmap_sem); lock(&dev->struct_mutex); *** DEADLOCK *** 1 lock held by debugfs_test/1351: #0: (&mm->mmap_sem){++++}, at: [<000000005df01c1e>] __do_page_fault+0x106/0x560 stack backtrace: CPU: 2 PID: 1351 Comm: debugfs_test Not tainted 4.15.0-rc2-CI-Patchwork_7428+ #1 Hardware name: /NUC6i5SYB, BIOS SYSKLi35.86A.0057.2017.0119.1758 01/19/2017 Call Trace: dump_stack+0x5f/0x86 print_circular_bug+0x230/0x3b0 check_prev_add+0x439/0x7b0 ? lockdep_init_map_crosslock+0x20/0x20 ? unwind_get_return_address+0x16/0x30 ? __lock_acquire+0x1385/0x15a0 __lock_acquire+0x1385/0x15a0 lock_acquire+0xaf/0x200 ? i915_mutex_lock_interruptible+0x47/0x130 [i915] __mutex_lock+0x81/0x9b0 ? i915_mutex_lock_interruptible+0x47/0x130 [i915] ? i915_mutex_lock_interruptible+0x47/0x130 [i915] ? i915_mutex_lock_interruptible+0x47/0x130 [i915] i915_mutex_lock_interruptible+0x47/0x130 [i915] ? __pm_runtime_resume+0x4f/0x80 i915_gem_fault+0x201/0x760 [i915] __do_fault+0x15/0x70 __handle_mm_fault+0x85b/0xe40 handle_mm_fault+0x14f/0x2f0 __do_page_fault+0x2d1/0x560 page_fault+0x22/0x30 RIP: 0033:0x7f98d6f49116 RSP: 002b:00007ffd6ffc3278 EFLAGS: 00010283 RAX: 00007f98d39a2bc0 RBX: 0000000000000000 RCX: 0000000000001680 RDX: 0000000000001680 RSI: 00007ffd6ffc3400 RDI: 00007f98d39a2bc0 RBP: 00007ffd6ffc33a0 R08: 0000000000000000 R09: 00000000000005a0 R10: 000055e847c2a830 R11: 0000000000000002 R12: 0000000000000001 R13: 000055e847c1d040 R14: 00007ffd6ffc3400 R15: 00007f98d6752ba0 v2: Init preempt_work unconditionally (Chris) v3: Mention that we need the enable_guc=1 for lockdep splat (Chris) Testcase: igt/debugfs_test/read_all_entries # with i915.enable_guc=1 Signed-off-by: Michał Winiarski Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Michal Wajdeczko Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171213221352.7173-2-michal.winiarski@intel.com --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_gem.c | 4 ++ drivers/gpu/drm/i915/intel_guc.c | 57 +++++++++++++++++ drivers/gpu/drm/i915/intel_guc.h | 2 + drivers/gpu/drm/i915/intel_guc_log.c | 23 ------- drivers/gpu/drm/i915/intel_guc_submission.c | 70 +++++---------------- drivers/gpu/drm/i915/intel_guc_submission.h | 2 + drivers/gpu/drm/i915/intel_uc.c | 26 ++++++++ drivers/gpu/drm/i915/intel_uc.h | 2 + 9 files changed, 110 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 721ccce1832f..285c8b238bff 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -621,6 +621,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv) i915_gem_contexts_fini(dev_priv); mutex_unlock(&dev_priv->drm.struct_mutex); + intel_uc_fini_wq(dev_priv); i915_gem_cleanup_userptr(dev_priv); i915_gem_drain_freed_objects(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 13fa26238e89..2c13e3a4f45a 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5163,6 +5163,10 @@ int i915_gem_init(struct drm_i915_private *dev_priv) if (ret) return ret; + ret = intel_uc_init_wq(dev_priv); + if (ret) + return ret; + /* This is just a security blanket to placate dragons. * On some systems, we very sporadically observe that the first TLBs * used by the CS may be stale, despite us poking the TLB reset. If diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 92ed22f38fc4..3c6bf5a34c3c 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -69,6 +69,63 @@ void intel_guc_init_early(struct intel_guc *guc) guc->notify = gen8_guc_raise_irq; } +int intel_guc_init_wq(struct intel_guc *guc) +{ + struct drm_i915_private *dev_priv = guc_to_i915(guc); + + /* + * GuC log buffer flush work item has to do register access to + * send the ack to GuC and this work item, if not synced before + * suspend, can potentially get executed after the GFX device is + * suspended. + * By marking the WQ as freezable, we don't have to bother about + * flushing of this work item from the suspend hooks, the pending + * work item if any will be either executed before the suspend + * or scheduled later on resume. This way the handling of work + * item can be kept same between system suspend & rpm suspend. + */ + guc->log.runtime.flush_wq = alloc_ordered_workqueue("i915-guc_log", + WQ_HIGHPRI | WQ_FREEZABLE); + if (!guc->log.runtime.flush_wq) + return -ENOMEM; + + /* + * Even though both sending GuC action, and adding a new workitem to + * GuC workqueue are serialized (each with its own locking), since + * we're using mutliple engines, it's possible that we're going to + * issue a preempt request with two (or more - each for different + * engine) workitems in GuC queue. In this situation, GuC may submit + * all of them, which will make us very confused. + * Our preemption contexts may even already be complete - before we + * even had the chance to sent the preempt action to GuC!. Rather + * than introducing yet another lock, we can just use ordered workqueue + * to make sure we're always sending a single preemption request with a + * single workitem. + */ + if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) && + USES_GUC_SUBMISSION(dev_priv)) { + guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt", + WQ_HIGHPRI); + if (!guc->preempt_wq) { + destroy_workqueue(guc->log.runtime.flush_wq); + return -ENOMEM; + } + } + + return 0; +} + +void intel_guc_fini_wq(struct intel_guc *guc) +{ + struct drm_i915_private *dev_priv = guc_to_i915(guc); + + if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) && + USES_GUC_SUBMISSION(dev_priv)) + destroy_workqueue(guc->preempt_wq); + + destroy_workqueue(guc->log.runtime.flush_wq); +} + static int guc_shared_data_create(struct intel_guc *guc) { struct i915_vma *vma; diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 81659e223e11..52856a97477d 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -119,6 +119,8 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma) void intel_guc_init_early(struct intel_guc *guc); void intel_guc_init_send_regs(struct intel_guc *guc); void intel_guc_init_params(struct intel_guc *guc); +int intel_guc_init_wq(struct intel_guc *guc); +void intel_guc_fini_wq(struct intel_guc *guc); int intel_guc_init(struct intel_guc *guc); void intel_guc_fini(struct intel_guc *guc); int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len); diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c index 1a2c5eed9929..eaedd63e3819 100644 --- a/drivers/gpu/drm/i915/intel_guc_log.c +++ b/drivers/gpu/drm/i915/intel_guc_log.c @@ -411,30 +411,8 @@ static int guc_log_runtime_create(struct intel_guc *guc) guc->log.runtime.relay_chan = guc_log_relay_chan; INIT_WORK(&guc->log.runtime.flush_work, capture_logs_work); - - /* - * GuC log buffer flush work item has to do register access to - * send the ack to GuC and this work item, if not synced before - * suspend, can potentially get executed after the GFX device is - * suspended. - * By marking the WQ as freezable, we don't have to bother about - * flushing of this work item from the suspend hooks, the pending - * work item if any will be either executed before the suspend - * or scheduled later on resume. This way the handling of work - * item can be kept same between system suspend & rpm suspend. - */ - guc->log.runtime.flush_wq = alloc_ordered_workqueue("i915-guc_log", - WQ_HIGHPRI | WQ_FREEZABLE); - if (!guc->log.runtime.flush_wq) { - DRM_ERROR("Couldn't allocate the wq for GuC logging\n"); - ret = -ENOMEM; - goto err_relaychan; - } - return 0; -err_relaychan: - relay_close(guc->log.runtime.relay_chan); err_vaddr: i915_gem_object_unpin_map(guc->log.vma->obj); guc->log.runtime.buf_addr = NULL; @@ -450,7 +428,6 @@ static void guc_log_runtime_destroy(struct intel_guc *guc) if (!guc_log_has_runtime(guc)) return; - destroy_workqueue(guc->log.runtime.flush_wq); relay_close(guc->log.runtime.relay_chan); i915_gem_object_unpin_map(guc->log.vma->obj); guc->log.runtime.buf_addr = NULL; diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index c020560c395e..8f4b274d66a7 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -1187,57 +1187,15 @@ static void guc_ads_destroy(struct intel_guc *guc) i915_vma_unpin_and_release(&guc->ads_vma); } -static int guc_preempt_work_create(struct intel_guc *guc) -{ - struct drm_i915_private *dev_priv = guc_to_i915(guc); - struct intel_engine_cs *engine; - enum intel_engine_id id; - - /* - * Even though both sending GuC action, and adding a new workitem to - * GuC workqueue are serialized (each with its own locking), since - * we're using mutliple engines, it's possible that we're going to - * issue a preempt request with two (or more - each for different - * engine) workitems in GuC queue. In this situation, GuC may submit - * all of them, which will make us very confused. - * Our preemption contexts may even already be complete - before we - * even had the chance to sent the preempt action to GuC!. Rather - * than introducing yet another lock, we can just use ordered workqueue - * to make sure we're always sending a single preemption request with a - * single workitem. - */ - guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt", - WQ_HIGHPRI); - if (!guc->preempt_wq) - return -ENOMEM; - - for_each_engine(engine, dev_priv, id) { - guc->preempt_work[id].engine = engine; - INIT_WORK(&guc->preempt_work[id].work, inject_preempt_context); - } - - return 0; -} - -static void guc_preempt_work_destroy(struct intel_guc *guc) -{ - struct drm_i915_private *dev_priv = guc_to_i915(guc); - struct intel_engine_cs *engine; - enum intel_engine_id id; - - for_each_engine(engine, dev_priv, id) - cancel_work_sync(&guc->preempt_work[id].work); - - destroy_workqueue(guc->preempt_wq); - guc->preempt_wq = NULL; -} - /* * Set up the memory resources to be shared with the GuC (via the GGTT) * at firmware loading time. */ int intel_guc_submission_init(struct intel_guc *guc) { + struct drm_i915_private *dev_priv = guc_to_i915(guc); + struct intel_engine_cs *engine; + enum intel_engine_id id; int ret; if (guc->stage_desc_pool) @@ -1256,20 +1214,18 @@ int intel_guc_submission_init(struct intel_guc *guc) if (ret < 0) goto err_stage_desc_pool; - ret = guc_preempt_work_create(guc); - if (ret) - goto err_log; - GEM_BUG_ON(!guc->preempt_wq); - ret = guc_ads_create(guc); if (ret < 0) - goto err_wq; + goto err_log; GEM_BUG_ON(!guc->ads_vma); + for_each_engine(engine, dev_priv, id) { + guc->preempt_work[id].engine = engine; + INIT_WORK(&guc->preempt_work[id].work, inject_preempt_context); + } + return 0; -err_wq: - guc_preempt_work_destroy(guc); err_log: intel_guc_log_destroy(guc); err_stage_desc_pool: @@ -1279,8 +1235,14 @@ int intel_guc_submission_init(struct intel_guc *guc) void intel_guc_submission_fini(struct intel_guc *guc) { + struct drm_i915_private *dev_priv = guc_to_i915(guc); + struct intel_engine_cs *engine; + enum intel_engine_id id; + + for_each_engine(engine, dev_priv, id) + cancel_work_sync(&guc->preempt_work[id].work); + guc_ads_destroy(guc); - guc_preempt_work_destroy(guc); intel_guc_log_destroy(guc); guc_stage_desc_pool_destroy(guc); } diff --git a/drivers/gpu/drm/i915/intel_guc_submission.h b/drivers/gpu/drm/i915/intel_guc_submission.h index 021fe85c8f71..fb081cefef93 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.h +++ b/drivers/gpu/drm/i915/intel_guc_submission.h @@ -77,5 +77,7 @@ int intel_guc_submission_init(struct intel_guc *guc); int intel_guc_submission_enable(struct intel_guc *guc); void intel_guc_submission_disable(struct intel_guc *guc); void intel_guc_submission_fini(struct intel_guc *guc); +int intel_guc_preempt_work_create(struct intel_guc *guc); +void intel_guc_preempt_work_destroy(struct intel_guc *guc); #endif diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 3040a0e00142..785850838a44 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -188,6 +188,32 @@ static void guc_disable_communication(struct intel_guc *guc) guc->send = intel_guc_send_nop; } +int intel_uc_init_wq(struct drm_i915_private *dev_priv) +{ + int ret; + + if (!USES_GUC(dev_priv)) + return 0; + + ret = intel_guc_init_wq(&dev_priv->guc); + if (ret) { + DRM_ERROR("Couldn't allocate workqueues for GuC\n"); + return ret; + } + + return 0; +} + +void intel_uc_fini_wq(struct drm_i915_private *dev_priv) +{ + if (!USES_GUC(dev_priv)) + return; + + GEM_BUG_ON(!HAS_GUC(dev_priv)); + + intel_guc_fini_wq(&dev_priv->guc); +} + int intel_uc_init_hw(struct drm_i915_private *dev_priv) { struct intel_guc *guc = &dev_priv->guc; diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 7a59e2486e9e..53edfeaf56b0 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -33,6 +33,8 @@ void intel_uc_init_early(struct drm_i915_private *dev_priv); void intel_uc_init_mmio(struct drm_i915_private *dev_priv); void intel_uc_init_fw(struct drm_i915_private *dev_priv); void intel_uc_fini_fw(struct drm_i915_private *dev_priv); +int intel_uc_init_wq(struct drm_i915_private *dev_priv); +void intel_uc_fini_wq(struct drm_i915_private *dev_priv); int intel_uc_init_hw(struct drm_i915_private *dev_priv); void intel_uc_fini_hw(struct drm_i915_private *dev_priv); -- GitLab From 61b5c1587dd82a8493d7838bb2f9289fd0903364 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= Date: Wed, 13 Dec 2017 23:13:48 +0100 Subject: [PATCH 1432/2547] drm/i915/guc: Extract guc_init from guc_init_hw MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After GPU reset, GuC HW needs to be reinitialized (with FW reload). Unfortunately, we're doing some extra work there (mostly allocating stuff), work that can be moved to guc_init and called once at driver load time. As a side effect we're no longer hitting an assert in i915_ggtt_enable_guc on suspend/resume. v2: Do not duplicate disable_communication / reset_guc_interrupts v3: Add proper teardown after rebase References: 04f7b24eccdf ("drm/i915/guc: Assert that we switch between known ggtt->invalidate functions") Signed-off-by: Michał Winiarski Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Michal Wajdeczko Cc: Sagar Arun Kamble Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171213221352.7173-3-michal.winiarski@intel.com --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_gem.c | 8 +++- drivers/gpu/drm/i915/intel_uc.c | 71 +++++++++++++++++++++------------ drivers/gpu/drm/i915/intel_uc.h | 2 + 4 files changed, 56 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 285c8b238bff..ca9f4b2862eb 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -617,6 +617,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv) mutex_lock(&dev_priv->drm.struct_mutex); intel_uc_fini_hw(dev_priv); + intel_uc_fini(dev_priv); i915_gem_cleanup_engines(dev_priv); i915_gem_contexts_fini(dev_priv); mutex_unlock(&dev_priv->drm.struct_mutex); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 2c13e3a4f45a..4a7f5579a7a5 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5196,10 +5196,14 @@ int i915_gem_init(struct drm_i915_private *dev_priv) intel_init_gt_powersave(dev_priv); - ret = i915_gem_init_hw(dev_priv); + ret = intel_uc_init(dev_priv); if (ret) goto err_pm; + ret = i915_gem_init_hw(dev_priv); + if (ret) + goto err_uc_init; + /* * Despite its name intel_init_clock_gating applies both display * clock gating workarounds; GT mmio workarounds and the occasional @@ -5240,6 +5244,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv) i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED); i915_gem_contexts_lost(dev_priv); intel_uc_fini_hw(dev_priv); +err_uc_init: + intel_uc_fini(dev_priv); err_pm: if (ret != -EIO) { intel_cleanup_gt_powersave(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 785850838a44..907deac6e3fa 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -214,26 +214,20 @@ void intel_uc_fini_wq(struct drm_i915_private *dev_priv) intel_guc_fini_wq(&dev_priv->guc); } -int intel_uc_init_hw(struct drm_i915_private *dev_priv) +int intel_uc_init(struct drm_i915_private *dev_priv) { struct intel_guc *guc = &dev_priv->guc; - struct intel_huc *huc = &dev_priv->huc; - int ret, attempts; + int ret; if (!USES_GUC(dev_priv)) return 0; - if (!HAS_GUC(dev_priv)) { - ret = -ENODEV; - goto err_out; - } - - guc_disable_communication(guc); - gen9_reset_guc_interrupts(dev_priv); + if (!HAS_GUC(dev_priv)) + return -ENODEV; ret = intel_guc_init(guc); if (ret) - goto err_out; + return ret; if (USES_GUC_SUBMISSION(dev_priv)) { /* @@ -241,10 +235,44 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) * if we are planning to enable submission later */ ret = intel_guc_submission_init(guc); - if (ret) - goto err_guc; + if (ret) { + intel_guc_fini(guc); + return ret; + } } + return 0; +} + +void intel_uc_fini(struct drm_i915_private *dev_priv) +{ + struct intel_guc *guc = &dev_priv->guc; + + if (!USES_GUC(dev_priv)) + return; + + GEM_BUG_ON(!HAS_GUC(dev_priv)); + + if (USES_GUC_SUBMISSION(dev_priv)) + intel_guc_submission_fini(guc); + + intel_guc_fini(guc); +} + +int intel_uc_init_hw(struct drm_i915_private *dev_priv) +{ + struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; + int ret, attempts; + + if (!USES_GUC(dev_priv)) + return 0; + + GEM_BUG_ON(!HAS_GUC(dev_priv)); + + guc_disable_communication(guc); + gen9_reset_guc_interrupts(dev_priv); + /* init WOPCM */ I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv)); I915_WRITE(DMA_GUC_WOPCM_OFFSET, @@ -264,12 +292,12 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) */ ret = __intel_uc_reset_hw(dev_priv); if (ret) - goto err_submission; + goto err_out; if (USES_HUC(dev_priv)) { ret = intel_huc_init_hw(huc); if (ret) - goto err_submission; + goto err_out; } intel_guc_init_params(guc); @@ -322,11 +350,6 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) guc_disable_communication(guc); err_log_capture: guc_capture_load_err_log(guc); -err_submission: - if (USES_GUC_SUBMISSION(dev_priv)) - intel_guc_submission_fini(guc); -err_guc: - intel_guc_fini(guc); err_out: /* * Note that there is no fallback as either user explicitly asked for @@ -348,15 +371,13 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv) if (!USES_GUC(dev_priv)) return; + GEM_BUG_ON(!HAS_GUC(dev_priv)); + if (USES_GUC_SUBMISSION(dev_priv)) intel_guc_submission_disable(guc); guc_disable_communication(guc); - if (USES_GUC_SUBMISSION(dev_priv)) { + if (USES_GUC_SUBMISSION(dev_priv)) gen9_disable_guc_interrupts(dev_priv); - intel_guc_submission_fini(guc); - } - - intel_guc_fini(guc); } diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 53edfeaf56b0..8a7249722ef1 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -37,6 +37,8 @@ int intel_uc_init_wq(struct drm_i915_private *dev_priv); void intel_uc_fini_wq(struct drm_i915_private *dev_priv); int intel_uc_init_hw(struct drm_i915_private *dev_priv); void intel_uc_fini_hw(struct drm_i915_private *dev_priv); +int intel_uc_init(struct drm_i915_private *dev_priv); +void intel_uc_fini(struct drm_i915_private *dev_priv); static inline bool intel_uc_is_using_guc(void) { -- GitLab From aeb950bd97e1f66a109430e05a3066e547bce916 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= Date: Wed, 13 Dec 2017 23:13:49 +0100 Subject: [PATCH 1433/2547] drm/i915/guc: Call invalidate after changing the vfunc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To make this operation a bit cleaner, we should make sure that the HW can catch up by calling the new implementation right away. Note that currently we're only touching the vfunc at module load time (before GuC is even loaded), so this shouldn't cause any functional changes. Suggested-by: Chris Wilson Signed-off-by: Michał Winiarski Cc: Chris Wilson Cc: Michal Wajdeczko Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171213221352.7173-4-michal.winiarski@intel.com --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index a0579b0c8581..c5f393870532 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3552,6 +3552,8 @@ void i915_ggtt_enable_guc(struct drm_i915_private *i915) GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate); i915->ggtt.invalidate = guc_ggtt_invalidate; + + i915_ggtt_invalidate(i915); } void i915_ggtt_disable_guc(struct drm_i915_private *i915) @@ -3560,6 +3562,8 @@ void i915_ggtt_disable_guc(struct drm_i915_private *i915) GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate); i915->ggtt.invalidate = gen6_ggtt_invalidate; + + i915_ggtt_invalidate(i915); } void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) -- GitLab From 9192d4fb811e1e7d07c8fa1a576d2935826daa91 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= Date: Wed, 13 Dec 2017 23:13:50 +0100 Subject: [PATCH 1434/2547] drm/i915/guc: Extract doorbell creation from client allocation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Full GPU reset causes GuC to be reset. This means that every time we're doing a reset, we need to talk to GuC and tell it about doorbells. Let's separate the communication part (create_doorbell) from our internal bookkeeping (reserve_doorbell) so that we can cleanly separate the initialization done at module load from reinitialization done at reset in the following patch. While I'm here, let's also add a proper (although slightly asymetric) cleanup that doesn't try to communicate with GuC after it's already gone, getting rid of "expected" warnings caused by GuC action failures on module unload. Note that I've also removed one of the tests (bitmap out of sync), since it doesn't make much sense anymore - bitmaps are now not expected to change during the lifetime of a client. Signed-off-by: Michał Winiarski Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Michal Wajdeczko Cc: Michel Thierry Reviewed-by: Michel Thierry Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171213221352.7173-5-michal.winiarski@intel.com --- drivers/gpu/drm/i915/intel_guc_submission.c | 151 ++++++-------------- drivers/gpu/drm/i915/selftests/intel_guc.c | 110 ++++++-------- 2 files changed, 88 insertions(+), 173 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index 8f4b274d66a7..c74e78b6ba41 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -88,7 +88,7 @@ static inline bool is_high_priority(struct intel_guc_client *client) client->priority == GUC_CLIENT_PRIORITY_HIGH); } -static int __reserve_doorbell(struct intel_guc_client *client) +static int reserve_doorbell(struct intel_guc_client *client) { unsigned long offset; unsigned long end; @@ -120,7 +120,7 @@ static int __reserve_doorbell(struct intel_guc_client *client) return 0; } -static void __unreserve_doorbell(struct intel_guc_client *client) +static void unreserve_doorbell(struct intel_guc_client *client) { GEM_BUG_ON(client->doorbell_id == GUC_DOORBELL_INVALID); @@ -188,32 +188,21 @@ static bool has_doorbell(struct intel_guc_client *client) return test_bit(client->doorbell_id, client->guc->doorbell_bitmap); } -static int __create_doorbell(struct intel_guc_client *client) +static void __create_doorbell(struct intel_guc_client *client) { struct guc_doorbell_info *doorbell; - int err; doorbell = __get_doorbell(client); doorbell->db_status = GUC_DOORBELL_ENABLED; doorbell->cookie = 0; - - err = __guc_allocate_doorbell(client->guc, client->stage_id); - if (err) { - doorbell->db_status = GUC_DOORBELL_DISABLED; - DRM_ERROR("Couldn't create client %u doorbell: %d\n", - client->stage_id, err); - } - - return err; } -static int __destroy_doorbell(struct intel_guc_client *client) +static void __destroy_doorbell(struct intel_guc_client *client) { struct drm_i915_private *dev_priv = guc_to_i915(client->guc); struct guc_doorbell_info *doorbell; u16 db_id = client->doorbell_id; - GEM_BUG_ON(db_id >= GUC_DOORBELL_INVALID); doorbell = __get_doorbell(client); doorbell->db_status = GUC_DOORBELL_DISABLED; @@ -225,50 +214,42 @@ static int __destroy_doorbell(struct intel_guc_client *client) */ if (wait_for_us(!(I915_READ(GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID), 10)) WARN_ONCE(true, "Doorbell never became invalid after disable\n"); - - return __guc_deallocate_doorbell(client->guc, client->stage_id); } static int create_doorbell(struct intel_guc_client *client) { int ret; - ret = __reserve_doorbell(client); - if (ret) - return ret; - __update_doorbell_desc(client, client->doorbell_id); + __create_doorbell(client); - ret = __create_doorbell(client); - if (ret) - goto err; + ret = __guc_allocate_doorbell(client->guc, client->stage_id); + if (ret) { + __destroy_doorbell(client); + __update_doorbell_desc(client, GUC_DOORBELL_INVALID); + DRM_ERROR("Couldn't create client %u doorbell: %d\n", + client->stage_id, ret); + return ret; + } return 0; - -err: - __update_doorbell_desc(client, GUC_DOORBELL_INVALID); - __unreserve_doorbell(client); - return ret; } static int destroy_doorbell(struct intel_guc_client *client) { - int err; + int ret; GEM_BUG_ON(!has_doorbell(client)); - /* XXX: wait for any interrupts */ - /* XXX: wait for workqueue to drain */ - - err = __destroy_doorbell(client); - if (err) - return err; + __destroy_doorbell(client); + ret = __guc_deallocate_doorbell(client->guc, client->stage_id); + if (ret) + DRM_ERROR("Couldn't destroy client %u doorbell: %d\n", + client->stage_id, ret); __update_doorbell_desc(client, GUC_DOORBELL_INVALID); - __unreserve_doorbell(client); - - return 0; + return ret; } static unsigned long __select_cacheline(struct intel_guc *guc) @@ -839,73 +820,18 @@ static bool doorbell_ok(struct intel_guc *guc, u16 db_id) return false; } -/* - * If the GuC thinks that the doorbell is unassigned (e.g. because we reset and - * reloaded the GuC FW) we can use this function to tell the GuC to reassign the - * doorbell to the rightful owner. - */ -static int __reset_doorbell(struct intel_guc_client *client, u16 db_id) -{ - int err; - - __update_doorbell_desc(client, db_id); - err = __create_doorbell(client); - if (!err) - err = __destroy_doorbell(client); - - return err; -} - -/* - * Set up & tear down each unused doorbell in turn, to ensure that all doorbell - * HW is (re)initialised. For that end, we might have to borrow the first - * client. Also, tell GuC about all the doorbells in use by all clients. - * We do this because the KMD, the GuC and the doorbell HW can easily go out of - * sync (e.g. we can reset the GuC, but not the doorbel HW). - */ -static int guc_init_doorbell_hw(struct intel_guc *guc) +static int guc_clients_doorbell_init(struct intel_guc *guc) { - struct intel_guc_client *client = guc->execbuf_client; - bool recreate_first_client = false; u16 db_id; int ret; - /* For unused doorbells, make sure they are disabled */ - for_each_clear_bit(db_id, guc->doorbell_bitmap, GUC_NUM_DOORBELLS) { - if (doorbell_ok(guc, db_id)) - continue; - - if (has_doorbell(client)) { - /* Borrow execbuf_client (we will recreate it later) */ - destroy_doorbell(client); - recreate_first_client = true; - } - - ret = __reset_doorbell(client, db_id); - WARN(ret, "Doorbell %u reset failed, err %d\n", db_id, ret); - } - - if (recreate_first_client) { - ret = __reserve_doorbell(client); - if (unlikely(ret)) { - DRM_ERROR("Couldn't re-reserve first client db: %d\n", - ret); - return ret; - } - - __update_doorbell_desc(client, client->doorbell_id); - } - - /* Now for every client (and not only execbuf_client) make sure their - * doorbells are known by the GuC - */ - ret = __create_doorbell(guc->execbuf_client); + ret = create_doorbell(guc->execbuf_client); if (ret) return ret; - ret = __create_doorbell(guc->preempt_client); + ret = create_doorbell(guc->preempt_client); if (ret) { - __destroy_doorbell(guc->execbuf_client); + destroy_doorbell(guc->execbuf_client); return ret; } @@ -916,6 +842,19 @@ static int guc_init_doorbell_hw(struct intel_guc *guc) return 0; } +static void guc_clients_doorbell_fini(struct intel_guc *guc) +{ + /* + * By the time we're here, GuC has already been reset. + * Instead of trying (in vain) to communicate with it, let's just + * cleanup the doorbell HW and our internal state. + */ + __destroy_doorbell(guc->preempt_client); + __update_doorbell_desc(guc->preempt_client, GUC_DOORBELL_INVALID); + __destroy_doorbell(guc->execbuf_client); + __update_doorbell_desc(guc->execbuf_client, GUC_DOORBELL_INVALID); +} + /** * guc_client_alloc() - Allocate an intel_guc_client * @dev_priv: driver private data structure @@ -991,7 +930,7 @@ guc_client_alloc(struct drm_i915_private *dev_priv, guc_proc_desc_init(guc, client); guc_stage_desc_init(guc, client); - ret = create_doorbell(client); + ret = reserve_doorbell(client); if (ret) goto err_vaddr; @@ -1015,16 +954,7 @@ guc_client_alloc(struct drm_i915_private *dev_priv, static void guc_client_free(struct intel_guc_client *client) { - /* - * XXX: wait for any outstanding submissions before freeing memory. - * Be sure to drop any locks - */ - - /* FIXME: in many cases, by the time we get here the GuC has been - * reset, so we cannot destroy the doorbell properly. Ignore the - * error message for now - */ - destroy_doorbell(client); + unreserve_doorbell(client); guc_stage_desc_fini(client->guc, client); i915_gem_object_unpin_map(client->vma->obj); i915_vma_unpin_and_release(&client->vma); @@ -1366,7 +1296,7 @@ int intel_guc_submission_enable(struct intel_guc *guc) if (err) goto err_free_clients; - err = guc_init_doorbell_hw(guc); + err = guc_clients_doorbell_init(guc); if (err) goto err_free_clients; @@ -1398,6 +1328,7 @@ void intel_guc_submission_disable(struct intel_guc *guc) GEM_BUG_ON(dev_priv->gt.awake); /* GT should be parked first */ guc_interrupts_release(dev_priv); + guc_clients_doorbell_fini(guc); /* Revert back to manual ELSP submission */ intel_engines_reset_default_submission(dev_priv); diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c index 68d6a69c738f..3f9016466dea 100644 --- a/drivers/gpu/drm/i915/selftests/intel_guc.c +++ b/drivers/gpu/drm/i915/selftests/intel_guc.c @@ -85,21 +85,26 @@ static int validate_client(struct intel_guc_client *client, return 0; } +static bool client_doorbell_in_sync(struct intel_guc_client *client) +{ + return doorbell_ok(client->guc, client->doorbell_id); +} + /* - * Check that guc_init_doorbell_hw is doing what it should. + * Check that we're able to synchronize guc_clients with their doorbells * - * During GuC submission enable, we create GuC clients and their doorbells, - * but after resetting the microcontroller (resume & gpu reset), these - * GuC clients are still around, but the status of their doorbells may be - * incorrect. This is the reason behind validating that the doorbells status - * expected by the driver matches what the GuC/HW have. + * We're creating clients and reserving doorbells once, at module load. During + * module lifetime, GuC, doorbell HW, and i915 state may go out of sync due to + * GuC being reset. In other words - GuC clients are still around, but the + * status of their doorbells may be incorrect. This is the reason behind + * validating that the doorbells status expected by the driver matches what the + * GuC/HW have. */ -static int igt_guc_init_doorbell_hw(void *args) +static int igt_guc_clients(void *args) { struct drm_i915_private *dev_priv = args; struct intel_guc *guc; - DECLARE_BITMAP(db_bitmap_bk, GUC_NUM_DOORBELLS); - int i, err = 0; + int err = 0; GEM_BUG_ON(!HAS_GUC(dev_priv)); mutex_lock(&dev_priv->drm.struct_mutex); @@ -148,10 +153,21 @@ static int igt_guc_init_doorbell_hw(void *args) goto out; } - /* each client should have received a doorbell during alloc */ + /* each client should now have reserved a doorbell */ if (!has_doorbell(guc->execbuf_client) || !has_doorbell(guc->preempt_client)) { - pr_err("guc_clients_create didn't create doorbells\n"); + pr_err("guc_clients_create didn't reserve doorbells\n"); + err = -EINVAL; + goto out; + } + + /* Now create the doorbells */ + guc_clients_doorbell_init(guc); + + /* each client should now have received a doorbell */ + if (!client_doorbell_in_sync(guc->execbuf_client) || + !client_doorbell_in_sync(guc->preempt_client)) { + pr_err("failed to initialize the doorbells\n"); err = -EINVAL; goto out; } @@ -160,25 +176,26 @@ static int igt_guc_init_doorbell_hw(void *args) * Basic test - an attempt to reallocate a valid doorbell to the * client it is currently assigned should not cause a failure. */ - err = guc_init_doorbell_hw(guc); + err = guc_clients_doorbell_init(guc); if (err) goto out; /* * Negative test - a client with no doorbell (invalid db id). - * Each client gets a doorbell when it is created, after destroying - * the doorbell, the db id is changed to GUC_DOORBELL_INVALID and the - * firmware will reject any attempt to allocate a doorbell with an - * invalid id (db has to be reserved before allocation). + * After destroying the doorbell, the db id is changed to + * GUC_DOORBELL_INVALID and the firmware will reject any attempt to + * allocate a doorbell with an invalid id (db has to be reserved before + * allocation). */ destroy_doorbell(guc->execbuf_client); - if (has_doorbell(guc->execbuf_client)) { + if (client_doorbell_in_sync(guc->execbuf_client)) { pr_err("destroy db did not work\n"); err = -EINVAL; goto out; } - err = guc_init_doorbell_hw(guc); + unreserve_doorbell(guc->execbuf_client); + err = guc_clients_doorbell_init(guc); if (err != -EIO) { pr_err("unexpected (err = %d)", err); goto out; @@ -191,33 +208,13 @@ static int igt_guc_init_doorbell_hw(void *args) } /* clean after test */ - err = create_doorbell(guc->execbuf_client); - if (err) { - pr_err("recreate doorbell failed\n"); - goto out; - } - - /* - * Negative test - doorbell_bitmap out of sync, will trigger a few of - * WARN_ON(!doorbell_ok(guc, db_id)) but that's ok as long as the - * doorbells from our clients don't fail. - */ - bitmap_copy(db_bitmap_bk, guc->doorbell_bitmap, GUC_NUM_DOORBELLS); - for (i = 0; i < GUC_NUM_DOORBELLS; i++) - if (i % 2) - test_and_change_bit(i, guc->doorbell_bitmap); - - err = guc_init_doorbell_hw(guc); + err = reserve_doorbell(guc->execbuf_client); if (err) { - pr_err("out of sync doorbell caused an error\n"); - goto out; + pr_err("failed to reserve back the doorbell back\n"); } - - /* restore 'correct' db bitmap */ - bitmap_copy(guc->doorbell_bitmap, db_bitmap_bk, GUC_NUM_DOORBELLS); - err = guc_init_doorbell_hw(guc); + err = create_doorbell(guc->execbuf_client); if (err) { - pr_err("restored doorbell caused an error\n"); + pr_err("recreate doorbell failed\n"); goto out; } @@ -226,8 +223,11 @@ static int igt_guc_init_doorbell_hw(void *args) * Leave clean state for other test, plus the driver always destroy the * clients during unload. */ + destroy_doorbell(guc->execbuf_client); + destroy_doorbell(guc->preempt_client); guc_clients_destroy(guc); guc_clients_create(guc); + guc_clients_doorbell_init(guc); unlock: mutex_unlock(&dev_priv->drm.struct_mutex); return err; @@ -309,25 +309,7 @@ static int igt_guc_doorbells(void *arg) db_id = clients[i]->doorbell_id; - /* - * Client alloc gives us a doorbell, but we want to exercise - * this ourselves (this resembles guc_init_doorbell_hw) - */ - destroy_doorbell(clients[i]); - if (clients[i]->doorbell_id != GUC_DOORBELL_INVALID) { - pr_err("[%d] destroy db did not work!\n", i); - err = -EINVAL; - goto out; - } - - err = __reserve_doorbell(clients[i]); - if (err) { - pr_err("[%d] Failed to reserve a doorbell\n", i); - goto out; - } - - __update_doorbell_desc(clients[i], clients[i]->doorbell_id); - err = __create_doorbell(clients[i]); + err = create_doorbell(clients[i]); if (err) { pr_err("[%d] Failed to create a doorbell\n", i); goto out; @@ -348,8 +330,10 @@ static int igt_guc_doorbells(void *arg) out: for (i = 0; i < ATTEMPTS; i++) - if (!IS_ERR_OR_NULL(clients[i])) + if (!IS_ERR_OR_NULL(clients[i])) { + destroy_doorbell(clients[i]); guc_client_free(clients[i]); + } unlock: mutex_unlock(&dev_priv->drm.struct_mutex); return err; @@ -358,7 +342,7 @@ static int igt_guc_doorbells(void *arg) int intel_guc_live_selftest(struct drm_i915_private *dev_priv) { static const struct i915_subtest tests[] = { - SUBTEST(igt_guc_init_doorbell_hw), + SUBTEST(igt_guc_clients), SUBTEST(igt_guc_doorbells), }; -- GitLab From 8ec52ec8dc6827ea7aed524ed5af7aedcfbc553b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= Date: Wed, 13 Dec 2017 23:13:51 +0100 Subject: [PATCH 1435/2547] drm/i915/guc: Extract clients allocation to submission_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We can now move the clients allocation to submission_init path, rather than keeping the condition inside submission_enable called on every reset. Signed-off-by: Michał Winiarski Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Michal Wajdeczko Reviewed-by: Michel Thierry Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171213221352.7173-6-michal.winiarski@intel.com --- drivers/gpu/drm/i915/intel_guc_submission.c | 33 +++++++-------------- 1 file changed, 11 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index c74e78b6ba41..488110602e7e 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -1149,6 +1149,10 @@ int intel_guc_submission_init(struct intel_guc *guc) goto err_log; GEM_BUG_ON(!guc->ads_vma); + ret = guc_clients_create(guc); + if (ret) + return ret; + for_each_engine(engine, dev_priv, id) { guc->preempt_work[id].engine = engine; INIT_WORK(&guc->preempt_work[id].work, inject_preempt_context); @@ -1172,6 +1176,7 @@ void intel_guc_submission_fini(struct intel_guc *guc) for_each_engine(engine, dev_priv, id) cancel_work_sync(&guc->preempt_work[id].work); + guc_clients_destroy(guc); guc_ads_destroy(guc); intel_guc_log_destroy(guc); guc_stage_desc_pool_destroy(guc); @@ -1277,28 +1282,18 @@ int intel_guc_submission_enable(struct intel_guc *guc) sizeof(struct guc_wq_item) * I915_NUM_ENGINES > GUC_WQ_SIZE); - /* - * We're being called on both module initialization and on reset, - * until this flow is changed, we're using regular client presence to - * determine which case are we in, and whether we should allocate new - * clients or just reset their workqueues. - */ - if (!guc->execbuf_client) { - err = guc_clients_create(guc); - if (err) - return err; - } else { - guc_reset_wq(guc->execbuf_client); - guc_reset_wq(guc->preempt_client); - } + GEM_BUG_ON(!guc->execbuf_client); + + guc_reset_wq(guc->execbuf_client); + guc_reset_wq(guc->preempt_client); err = intel_guc_sample_forcewake(guc); if (err) - goto err_free_clients; + return err; err = guc_clients_doorbell_init(guc); if (err) - goto err_free_clients; + return err; /* Take over from manual control of ELSP (execlists) */ guc_interrupts_capture(dev_priv); @@ -1315,10 +1310,6 @@ int intel_guc_submission_enable(struct intel_guc *guc) } return 0; - -err_free_clients: - guc_clients_destroy(guc); - return err; } void intel_guc_submission_disable(struct intel_guc *guc) @@ -1332,8 +1323,6 @@ void intel_guc_submission_disable(struct intel_guc *guc) /* Revert back to manual ELSP submission */ intel_engines_reset_default_submission(dev_priv); - - guc_clients_destroy(guc); } #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) -- GitLab From a00cfc959ccbda94873f49bf4494edc00200d05d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= Date: Wed, 13 Dec 2017 23:13:52 +0100 Subject: [PATCH 1436/2547] drm/i915/guc: Extract doorbell verification into a function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We have the selftest that's checking doorbell create/destroy, so there's no need to check all doorbells delaying the reset every time. We do want to have that extra sanity check at module load/unload though. Signed-off-by: Michał Winiarski Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Michal Wajdeczko Reviewed-by: Michal Wajdeczko Reviewed-by: Michel Thierry Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171213221352.7173-7-michal.winiarski@intel.com --- drivers/gpu/drm/i915/intel_guc_submission.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index 488110602e7e..4d2409466a3a 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -820,9 +820,19 @@ static bool doorbell_ok(struct intel_guc *guc, u16 db_id) return false; } -static int guc_clients_doorbell_init(struct intel_guc *guc) +static bool guc_verify_doorbells(struct intel_guc *guc) { u16 db_id; + + for (db_id = 0; db_id < GUC_NUM_DOORBELLS; ++db_id) + if (!doorbell_ok(guc, db_id)) + return false; + + return true; +} + +static int guc_clients_doorbell_init(struct intel_guc *guc) +{ int ret; ret = create_doorbell(guc->execbuf_client); @@ -835,10 +845,6 @@ static int guc_clients_doorbell_init(struct intel_guc *guc) return ret; } - /* Read back & verify all (used & unused) doorbell registers */ - for (db_id = 0; db_id < GUC_NUM_DOORBELLS; ++db_id) - WARN_ON(!doorbell_ok(guc, db_id)); - return 0; } @@ -1149,6 +1155,7 @@ int intel_guc_submission_init(struct intel_guc *guc) goto err_log; GEM_BUG_ON(!guc->ads_vma); + WARN_ON(!guc_verify_doorbells(guc)); ret = guc_clients_create(guc); if (ret) return ret; @@ -1177,6 +1184,8 @@ void intel_guc_submission_fini(struct intel_guc *guc) cancel_work_sync(&guc->preempt_work[id].work); guc_clients_destroy(guc); + WARN_ON(!guc_verify_doorbells(guc)); + guc_ads_destroy(guc); intel_guc_log_destroy(guc); guc_stage_desc_pool_destroy(guc); -- GitLab From ed52870f4676489124d8697fd00e6ae6c504e586 Mon Sep 17 00:00:00 2001 From: Wanpeng Li Date: Mon, 4 Dec 2017 22:21:30 -0800 Subject: [PATCH 1437/2547] KVM: MMU: Fix infinite loop when there is no available mmu page MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The below test case can cause infinite loop in kvm when ept=0. #include #include #include #include #include #include #include long r[5]; int main() { r[2] = open("/dev/kvm", O_RDONLY); r[3] = ioctl(r[2], KVM_CREATE_VM, 0); r[4] = ioctl(r[3], KVM_CREATE_VCPU, 7); ioctl(r[4], KVM_RUN, 0); } It doesn't setup the memory regions, mmu_alloc_shadow/direct_roots() in kvm return 1 when kvm fails to allocate root page table which can result in beblow infinite loop: vcpu_run() { for (;;) { r = vcpu_enter_guest()::kvm_mmu_reload() returns 1 if (r <= 0) break; if (need_resched()) cond_resched(); } } This patch fixes it by returning -ENOSPC when there is no available kvm mmu page for root page table. Cc: Paolo Bonzini Cc: Radim Krčmář Cc: stable@vger.kernel.org Fixes: 26eeb53cf0f (KVM: MMU: Bail out immediately if there is no available mmu page) Signed-off-by: Wanpeng Li Signed-off-by: Paolo Bonzini --- arch/x86/kvm/mmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index e5e66e5c6640..c4deb1f34faa 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -3395,7 +3395,7 @@ static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) spin_lock(&vcpu->kvm->mmu_lock); if(make_mmu_pages_available(vcpu) < 0) { spin_unlock(&vcpu->kvm->mmu_lock); - return 1; + return -ENOSPC; } sp = kvm_mmu_get_page(vcpu, 0, 0, vcpu->arch.mmu.shadow_root_level, 1, ACC_ALL); @@ -3410,7 +3410,7 @@ static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) spin_lock(&vcpu->kvm->mmu_lock); if (make_mmu_pages_available(vcpu) < 0) { spin_unlock(&vcpu->kvm->mmu_lock); - return 1; + return -ENOSPC; } sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL); @@ -3450,7 +3450,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) spin_lock(&vcpu->kvm->mmu_lock); if (make_mmu_pages_available(vcpu) < 0) { spin_unlock(&vcpu->kvm->mmu_lock); - return 1; + return -ENOSPC; } sp = kvm_mmu_get_page(vcpu, root_gfn, 0, vcpu->arch.mmu.shadow_root_level, 0, ACC_ALL); @@ -3487,7 +3487,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) spin_lock(&vcpu->kvm->mmu_lock); if (make_mmu_pages_available(vcpu) < 0) { spin_unlock(&vcpu->kvm->mmu_lock); - return 1; + return -ENOSPC; } sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, 0, ACC_ALL); -- GitLab From d73235d17ba63b53dc0e1051dbc10a1f1be91b71 Mon Sep 17 00:00:00 2001 From: Wanpeng Li Date: Thu, 7 Dec 2017 00:30:08 -0800 Subject: [PATCH 1438/2547] KVM: X86: Fix load RFLAGS w/o the fixed bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit *** Guest State *** CR0: actual=0x0000000000000030, shadow=0x0000000060000010, gh_mask=fffffffffffffff7 CR4: actual=0x0000000000002050, shadow=0x0000000000000000, gh_mask=ffffffffffffe871 CR3 = 0x00000000fffbc000 RSP = 0x0000000000000000 RIP = 0x0000000000000000 RFLAGS=0x00000000 DR7 = 0x0000000000000400 ^^^^^^^^^^ The failed vmentry is triggered by the following testcase when ept=Y: #include #include #include #include #include #include #include long r[5]; int main() { r[2] = open("/dev/kvm", O_RDONLY); r[3] = ioctl(r[2], KVM_CREATE_VM, 0); r[4] = ioctl(r[3], KVM_CREATE_VCPU, 7); struct kvm_regs regs = { .rflags = 0, }; ioctl(r[4], KVM_SET_REGS, ®s); ioctl(r[4], KVM_RUN, 0); } X86 RFLAGS bit 1 is fixed set, userspace can simply clearing bit 1 of RFLAGS with KVM_SET_REGS ioctl which results in vmentry fails. This patch fixes it by oring X86_EFLAGS_FIXED during ioctl. Cc: stable@vger.kernel.org Suggested-by: Jim Mattson Reviewed-by: David Hildenbrand Reviewed-by: Quan Xu Cc: Paolo Bonzini Cc: Radim Krčmář Cc: Jim Mattson Cc: stable@vger.kernel.org Signed-off-by: Wanpeng Li Signed-off-by: Paolo Bonzini --- arch/x86/kvm/x86.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index faf843c9b916..154ea27746e9 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -7384,7 +7384,7 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) #endif kvm_rip_write(vcpu, regs->rip); - kvm_set_rflags(vcpu, regs->rflags); + kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); vcpu->arch.exception.pending = false; -- GitLab From 5663d8f9bbe4bf15488f7351efb61ea20fa6de06 Mon Sep 17 00:00:00 2001 From: Peter Xu Date: Tue, 12 Dec 2017 17:15:02 +0100 Subject: [PATCH 1439/2547] kvm: x86: fix WARN due to uninitialized guest FPU state ------------[ cut here ]------------ Bad FPU state detected at kvm_put_guest_fpu+0xd8/0x2d0 [kvm], reinitializing FPU registers. WARNING: CPU: 1 PID: 4594 at arch/x86/mm/extable.c:103 ex_handler_fprestore+0x88/0x90 CPU: 1 PID: 4594 Comm: qemu-system-x86 Tainted: G B OE 4.15.0-rc2+ #10 RIP: 0010:ex_handler_fprestore+0x88/0x90 Call Trace: fixup_exception+0x4e/0x60 do_general_protection+0xff/0x270 general_protection+0x22/0x30 RIP: 0010:kvm_put_guest_fpu+0xd8/0x2d0 [kvm] RSP: 0018:ffff8803d5627810 EFLAGS: 00010246 kvm_vcpu_reset+0x3b4/0x3c0 [kvm] kvm_apic_accept_events+0x1c0/0x240 [kvm] kvm_arch_vcpu_ioctl_run+0x1658/0x2fb0 [kvm] kvm_vcpu_ioctl+0x479/0x880 [kvm] do_vfs_ioctl+0x142/0x9a0 SyS_ioctl+0x74/0x80 do_syscall_64+0x15f/0x600 where kvm_put_guest_fpu is called without a prior kvm_load_guest_fpu. To fix it, move kvm_load_guest_fpu to the very beginning of kvm_arch_vcpu_ioctl_run. Cc: stable@vger.kernel.org Fixes: f775b13eedee2f7f3c6fdd4e90fb79090ce5d339 Signed-off-by: Peter Xu Signed-off-by: Paolo Bonzini --- arch/x86/kvm/x86.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 154ea27746e9..56d036b9ad75 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -7264,13 +7264,12 @@ static int complete_emulated_mmio(struct kvm_vcpu *vcpu) int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) { - struct fpu *fpu = ¤t->thread.fpu; int r; - fpu__initialize(fpu); - kvm_sigset_activate(vcpu); + kvm_load_guest_fpu(vcpu); + if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { if (kvm_run->immediate_exit) { r = -EINTR; @@ -7296,14 +7295,12 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) } } - kvm_load_guest_fpu(vcpu); - if (unlikely(vcpu->arch.complete_userspace_io)) { int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; vcpu->arch.complete_userspace_io = NULL; r = cui(vcpu); if (r <= 0) - goto out_fpu; + goto out; } else WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); @@ -7312,9 +7309,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) else r = vcpu_run(vcpu); -out_fpu: - kvm_put_guest_fpu(vcpu); out: + kvm_put_guest_fpu(vcpu); post_kvm_run_save(vcpu); kvm_sigset_deactivate(vcpu); -- GitLab From 19e8e54f4309eaa438237aa1973fe40c331903d4 Mon Sep 17 00:00:00 2001 From: Stefan Raspl Date: Mon, 11 Dec 2017 12:25:19 +0100 Subject: [PATCH 1440/2547] tools/kvm_stat: fix command line option '-g' Specifying a guest via '-g foo' always results in an error: $ kvm_stat -g foo Usage: kvm_stat [options] kvm_stat: error: Error while searching for guest "foo", use "-p" to specify a pid instead Reason is that Tui.get_pid_from_gname() is not static, as it is supposed to be. Signed-off-by: Stefan Raspl Tested-by: Christian Borntraeger Signed-off-by: Paolo Bonzini --- tools/kvm/kvm_stat/kvm_stat | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tools/kvm/kvm_stat/kvm_stat b/tools/kvm/kvm_stat/kvm_stat index 217cf6f95c36..884a74b8ca87 100755 --- a/tools/kvm/kvm_stat/kvm_stat +++ b/tools/kvm/kvm_stat/kvm_stat @@ -950,7 +950,8 @@ class Tui(object): curses.nocbreak() curses.endwin() - def get_all_gnames(self): + @staticmethod + def get_all_gnames(): """Returns a list of (pid, gname) tuples of all running guests""" res = [] try: @@ -963,7 +964,7 @@ class Tui(object): # perform a sanity check before calling the more expensive # function to possibly extract the guest name if ' -name ' in line[1]: - res.append((line[0], self.get_gname_from_pid(line[0]))) + res.append((line[0], Tui.get_gname_from_pid(line[0]))) child.stdout.close() return res @@ -984,7 +985,8 @@ class Tui(object): except Exception: self.screen.addstr(row + 1, 2, 'Not available') - def get_pid_from_gname(self, gname): + @staticmethod + def get_pid_from_gname(gname): """Fuzzy function to convert guest name to QEMU process pid. Returns a list of potential pids, can be empty if no match found. @@ -992,7 +994,7 @@ class Tui(object): """ pids = [] - for line in self.get_all_gnames(): + for line in Tui.get_all_gnames(): if gname == line[1]: pids.append(int(line[0])) -- GitLab From faa06650418bf28d07426fcfdc5213782fb131f6 Mon Sep 17 00:00:00 2001 From: Stefan Raspl Date: Mon, 11 Dec 2017 12:25:20 +0100 Subject: [PATCH 1441/2547] tools/kvm_stat: fix drilldown in events-by-guests mode When displaying debugfs events listed by guests, an attempt to switch to reporting of stats for individual child trace events results in garbled output. Reason is that when toggling drilldown, the update of the stats doesn't honor when events are displayed by guests, as indicated by Tui._display_guests. To reproduce, run 'kvm_stat -d' and press 'b' followed by 'x'. Signed-off-by: Stefan Raspl Signed-off-by: Paolo Bonzini --- tools/kvm/kvm_stat/kvm_stat | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/kvm/kvm_stat/kvm_stat b/tools/kvm/kvm_stat/kvm_stat index 884a74b8ca87..6347ad5d0d35 100755 --- a/tools/kvm/kvm_stat/kvm_stat +++ b/tools/kvm/kvm_stat/kvm_stat @@ -1360,7 +1360,7 @@ class Tui(object): if char == 'x': self.update_drilldown() # prevents display of current values on next refresh - self.stats.get() + self.stats.get(self._display_guests) except KeyboardInterrupt: break except curses.error: -- GitLab From 67c162b0892ac481e47bef06d9c6231ee993843a Mon Sep 17 00:00:00 2001 From: Stefan Raspl Date: Mon, 11 Dec 2017 12:25:21 +0100 Subject: [PATCH 1442/2547] tools/kvm_stat: fix missing field update after filter change When updating the fields filter, tracepoint events of fields previously not visible were not enabled, as TracepointProvider.update_fields() updated the member variable directly instead of using the setter, which triggers the event enable/disable. To reproduce, run 'kvm_stat -f kvm_exit', press 'c' to remove the filter, and notice that no add'l fields that do not match the regex 'kvm_exit' will appear. This issue was introduced by commit c469117df059 ("tools/kvm_stat: simplify initializers"). Signed-off-by: Stefan Raspl Signed-off-by: Paolo Bonzini --- tools/kvm/kvm_stat/kvm_stat | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/kvm/kvm_stat/kvm_stat b/tools/kvm/kvm_stat/kvm_stat index 6347ad5d0d35..f133755fdde2 100755 --- a/tools/kvm/kvm_stat/kvm_stat +++ b/tools/kvm/kvm_stat/kvm_stat @@ -549,8 +549,8 @@ class TracepointProvider(Provider): def update_fields(self, fields_filter): """Refresh fields, applying fields_filter""" - self._fields = [field for field in self.get_available_fields() - if self.is_field_wanted(fields_filter, field)] + self.fields = [field for field in self.get_available_fields() + if self.is_field_wanted(fields_filter, field)] @staticmethod def get_online_cpus(): -- GitLab From b74faa930deb2e37ed5caa0abfc687c8c532e946 Mon Sep 17 00:00:00 2001 From: Stefan Raspl Date: Mon, 11 Dec 2017 12:25:22 +0100 Subject: [PATCH 1443/2547] tools/kvm_stat: fix extra handling of 'help' with fields filter Commit 67fbcd62f54d ("tools/kvm_stat: add '-f help' to get the available event list") added support for '-f help'. However, the extra handling of 'help' will also take effect when 'help' is specified as a regex in interactive mode via 'f'. This results in display of all events while only those matching this regex should be shown. Signed-off-by: Stefan Raspl Signed-off-by: Paolo Bonzini --- tools/kvm/kvm_stat/kvm_stat | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/kvm/kvm_stat/kvm_stat b/tools/kvm/kvm_stat/kvm_stat index f133755fdde2..4faf9f85a00e 100755 --- a/tools/kvm/kvm_stat/kvm_stat +++ b/tools/kvm/kvm_stat/kvm_stat @@ -478,7 +478,7 @@ class Provider(object): @staticmethod def is_field_wanted(fields_filter, field): """Indicate whether field is valid according to fields_filter.""" - if not fields_filter or fields_filter == "help": + if not fields_filter: return True return re.match(fields_filter, field) is not None @@ -1567,6 +1567,7 @@ def main(): stats = Stats(options) if options.fields == "help": + stats.fields_filter = None event_list = "\n" s = stats.get() for key in s.keys(): -- GitLab From fff8c9eb48aa58259071b5df0e6d4c1c0bc1ba51 Mon Sep 17 00:00:00 2001 From: Stefan Raspl Date: Mon, 11 Dec 2017 12:25:23 +0100 Subject: [PATCH 1444/2547] tools/kvm_stat: fix child trace events accounting Child trace events were included in calculation of the overall total, which is used for calculation of the percentages of the '%Total' column. However, the parent trace envents' stats summarize the child trace events, hence we'd incorrectly account for them twice, leading to slightly wrong stats. With this fix, we use the correct total. Consequently, the sum of the child trace events' '%Total' column values is identical to the respective value of the respective parent event. However, this also means that the sum of the '%Total' column values will aggregate to more than 100 percent. Signed-off-by: Stefan Raspl Signed-off-by: Paolo Bonzini --- tools/kvm/kvm_stat/kvm_stat | 6 +++--- tools/kvm/kvm_stat/kvm_stat.txt | 2 ++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/tools/kvm/kvm_stat/kvm_stat b/tools/kvm/kvm_stat/kvm_stat index 4faf9f85a00e..90f0445d7808 100755 --- a/tools/kvm/kvm_stat/kvm_stat +++ b/tools/kvm/kvm_stat/kvm_stat @@ -1092,14 +1092,14 @@ class Tui(object): # sort by totals return (0, -stats[x][0]) total = 0. - for val in stats.values(): - total += val[0] + for key in stats.keys(): + if key.find('(') is -1: + total += stats[key][0] if self._sorting == SORT_DEFAULT: sortkey = sortCurAvg else: sortkey = sortTotal for key in sorted(stats.keys(), key=sortkey): - if row >= self.screen.getmaxyx()[0]: break values = stats[key] diff --git a/tools/kvm/kvm_stat/kvm_stat.txt b/tools/kvm/kvm_stat/kvm_stat.txt index e5cf836be8a1..75368a3c285f 100644 --- a/tools/kvm/kvm_stat/kvm_stat.txt +++ b/tools/kvm/kvm_stat/kvm_stat.txt @@ -50,6 +50,8 @@ INTERACTIVE COMMANDS *s*:: set update interval *x*:: toggle reporting of stats for child trace events + :: *Note*: The stats for the parents summarize the respective child trace + events Press any other key to refresh statistics immediately. -- GitLab From f3d11b0e8619bbb053d3e13f2271819fb01c1e2a Mon Sep 17 00:00:00 2001 From: Stefan Raspl Date: Mon, 11 Dec 2017 12:25:24 +0100 Subject: [PATCH 1445/2547] tools/kvm_stat: add hint on '-f help' to man page The man page update for this new functionality was omitted. Signed-off-by: Stefan Raspl Signed-off-by: Paolo Bonzini --- tools/kvm/kvm_stat/kvm_stat.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/kvm/kvm_stat/kvm_stat.txt b/tools/kvm/kvm_stat/kvm_stat.txt index 75368a3c285f..b5b3810c9e94 100644 --- a/tools/kvm/kvm_stat/kvm_stat.txt +++ b/tools/kvm/kvm_stat/kvm_stat.txt @@ -88,7 +88,7 @@ OPTIONS -f:: --fields=:: - fields to display (regex) + fields to display (regex), "-f help" for a list of available events -h:: --help:: -- GitLab From 08e20a6300e106d5feb89c9e47ea479533fec46f Mon Sep 17 00:00:00 2001 From: Stefan Raspl Date: Mon, 11 Dec 2017 12:25:25 +0100 Subject: [PATCH 1446/2547] tools/kvm_stat: handle invalid regular expressions Passing an invalid regular expression on the command line results in a traceback. Note that interactive specification of invalid regular expressions is not affected To reproduce, run "kvm_stat -f '*'". Signed-off-by: Stefan Raspl Signed-off-by: Paolo Bonzini --- tools/kvm/kvm_stat/kvm_stat | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tools/kvm/kvm_stat/kvm_stat b/tools/kvm/kvm_stat/kvm_stat index 90f0445d7808..29c56f3a05dc 100755 --- a/tools/kvm/kvm_stat/kvm_stat +++ b/tools/kvm/kvm_stat/kvm_stat @@ -1521,6 +1521,13 @@ Press any other key to refresh statistics immediately. callback=cb_guest_to_pid, ) (options, _) = optparser.parse_args(sys.argv) + try: + # verify that we were passed a valid regex up front + re.compile(options.fields) + except re.error: + sys.exit('Error: "' + options.fields + '" is not a valid regular ' + 'expression') + return options -- GitLab From 822cfe3e4813c8f52199362b0e689fba9459ddc9 Mon Sep 17 00:00:00 2001 From: Stefan Raspl Date: Mon, 11 Dec 2017 12:25:26 +0100 Subject: [PATCH 1447/2547] tools/kvm_stat: suppress usage information on command line errors Errors while parsing the '-g' command line argument result in display of usage information prior to the error message. This is a bit confusing, as the command line is syntactically correct. To reproduce, run 'kvm_stat -g' and specify a non-existing or inactive guest. Signed-off-by: Stefan Raspl Signed-off-by: Paolo Bonzini --- tools/kvm/kvm_stat/kvm_stat | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/tools/kvm/kvm_stat/kvm_stat b/tools/kvm/kvm_stat/kvm_stat index 29c56f3a05dc..bf65531570f5 100755 --- a/tools/kvm/kvm_stat/kvm_stat +++ b/tools/kvm/kvm_stat/kvm_stat @@ -1453,16 +1453,13 @@ Press any other key to refresh statistics immediately. try: pids = Tui.get_pid_from_gname(val) except: - raise optparse.OptionValueError('Error while searching for guest ' - '"{}", use "-p" to specify a pid ' - 'instead'.format(val)) + sys.exit('Error while searching for guest "{}". Use "-p" to ' + 'specify a pid instead?'.format(val)) if len(pids) == 0: - raise optparse.OptionValueError('No guest by the name "{}" ' - 'found'.format(val)) + sys.exit('Error: No guest by the name "{}" found'.format(val)) if len(pids) > 1: - raise optparse.OptionValueError('Multiple processes found (pids: ' - '{}) - use "-p" to specify a pid ' - 'instead'.format(" ".join(pids))) + sys.exit('Error: Multiple processes found (pids: {}). Use "-p" ' + 'to specify the desired pid'.format(" ".join(pids))) parser.values.pid = pids[0] optparser = optparse.OptionParser(description=description_text, -- GitLab From 73fab6ffbd83795e38974bb438e7afce0242c61a Mon Sep 17 00:00:00 2001 From: Stefan Raspl Date: Mon, 11 Dec 2017 12:25:27 +0100 Subject: [PATCH 1448/2547] tools/kvm_stat: stop ignoring unhandled arguments Unhandled arguments, which could easily include typos, are simply ignored. We should be strict to avoid undetected typos. To reproduce start kvm_stat with an extra argument, e.g. 'kvm_stat -d bnuh5ol' and note that this will actually work. Signed-off-by: Stefan Raspl Signed-off-by: Paolo Bonzini --- tools/kvm/kvm_stat/kvm_stat | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/kvm/kvm_stat/kvm_stat b/tools/kvm/kvm_stat/kvm_stat index bf65531570f5..aa3bc47af1d0 100755 --- a/tools/kvm/kvm_stat/kvm_stat +++ b/tools/kvm/kvm_stat/kvm_stat @@ -1517,7 +1517,9 @@ Press any other key to refresh statistics immediately. help='restrict statistics to guest by name', callback=cb_guest_to_pid, ) - (options, _) = optparser.parse_args(sys.argv) + options, unkn = optparser.parse_args(sys.argv) + if len(unkn) != 1: + sys.exit('Error: Extra argument(s): ' + ' '.join(unkn[1:])) try: # verify that we were passed a valid regex up front re.compile(options.fields) -- GitLab From cf656c76614c6ec5b016233cac29738881c83c08 Mon Sep 17 00:00:00 2001 From: Stefan Raspl Date: Mon, 11 Dec 2017 12:25:29 +0100 Subject: [PATCH 1449/2547] tools/kvm_stat: add line for totals Add a line for the total number of events and current average at the bottom of the body. Note that both values exclude child trace events. I.e. if drilldown is activated via interactive command 'x', only the totals are accounted, or we'd be counting these twice (see previous commit "tools/kvm_stat: fix child trace events accounting"). Signed-off-by: Stefan Raspl Signed-off-by: Paolo Bonzini --- tools/kvm/kvm_stat/kvm_stat | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tools/kvm/kvm_stat/kvm_stat b/tools/kvm/kvm_stat/kvm_stat index aa3bc47af1d0..566a70ddd005 100755 --- a/tools/kvm/kvm_stat/kvm_stat +++ b/tools/kvm/kvm_stat/kvm_stat @@ -1099,8 +1099,9 @@ class Tui(object): sortkey = sortCurAvg else: sortkey = sortTotal + tavg = 0 for key in sorted(stats.keys(), key=sortkey): - if row >= self.screen.getmaxyx()[0]: + if row >= self.screen.getmaxyx()[0] - 1: break values = stats[key] if not values[0] and not values[1]: @@ -1112,9 +1113,15 @@ class Tui(object): self.screen.addstr(row, 1, '%-40s %10d%7.1f %8s' % (key, values[0], values[0] * 100 / total, cur)) + if cur is not '' and key.find('(') is -1: + tavg += cur row += 1 if row == 3: self.screen.addstr(4, 1, 'No matching events reported yet') + else: + self.screen.addstr(row, 1, '%-40s %10d %8s' % + ('Total', total, tavg if tavg else ''), + curses.A_BOLD) self.screen.refresh() def show_msg(self, text): -- GitLab From 2797c4a11f373b2545c2398ccb02e362ee66a142 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 4 Dec 2017 13:25:13 +0000 Subject: [PATCH 1450/2547] drm/i915: Flush pending GTT writes before unbinding From the shrinker paths, we want to relinquish the GPU and GGTT access to the object, releasing the backing storage back to the system for swapout. As a part of that process we would unpin the pages, marking them for access by the CPU (for the swapout/swapin). However, if that process was interrupted after unbind the vma, we missed a flush of the inflight GGTT writes before we made that GTT space available again for reuse, with the prospect that we would redirect them to another page. The bug dates back to the introduction of multiple GGTT vma, but the code itself dates to commit 02bef8f98d26 ("drm/i915: Unbind closed vma for i915_gem_object_unbind()"). Fixes: 02bef8f98d26 ("drm/i915: Unbind closed vma for i915_gem_object_unbind()") Fixes: c5ad54cf7dd8 ("drm/i915: Use partial view in mmap fault handler") Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: stable@vger.kernel.org Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171204132513.7303-1-chris@chris-wilson.co.uk (cherry picked from commit 5888fc9eac3c2ff96e76aeeb865fdb46ab2d711e) Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_gem.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index ad4050f7ab3b..18de6569d04a 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -330,17 +330,10 @@ int i915_gem_object_unbind(struct drm_i915_gem_object *obj) * must wait for all rendering to complete to the object (as unbinding * must anyway), and retire the requests. */ - ret = i915_gem_object_wait(obj, - I915_WAIT_INTERRUPTIBLE | - I915_WAIT_LOCKED | - I915_WAIT_ALL, - MAX_SCHEDULE_TIMEOUT, - NULL); + ret = i915_gem_object_set_to_cpu_domain(obj, false); if (ret) return ret; - i915_gem_retire_requests(to_i915(obj->base.dev)); - while ((vma = list_first_entry_or_null(&obj->vma_list, struct i915_vma, obj_link))) { -- GitLab From 2b3a2e9f400acff4a4a9a2316e3e13b36b76b0e9 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 7 Dec 2017 22:00:25 +0000 Subject: [PATCH 1451/2547] drm/i915: Drop fb reference on load_detect_pipe failure path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When intel_modeset_setup_plane_state() fails drop the local framebuffer reference before jumping to the error, otherwise we leak the framebuffer. Signed-off-by: Chris Wilson Cc: Maarten Lankhorst Cc: Ville Syrjälä Cc: Daniel Vetter Fixes: edde361711ef ("drm/i915: Use atomic state to obtain load detection crtc, v3.") Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171207220025.22698-1-chris@chris-wilson.co.uk (cherry picked from commit 3e72be177cf19ab3d62b3084d424dce7e71d847f) Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_display.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e8ccf89cb17b..ff9397030092 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9944,11 +9944,10 @@ int intel_get_load_detect_pipe(struct drm_connector *connector, } ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); + drm_framebuffer_put(fb); if (ret) goto fail; - drm_framebuffer_put(fb); - ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); if (ret) goto fail; -- GitLab From 74c7b0782b15bc2478f557cea34b3fe34d452dc6 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 8 Dec 2017 12:10:33 +0000 Subject: [PATCH 1452/2547] drm/i915: Stop listening to request resubmission from the signaler kthread MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The intent here was that we would be listening to i915_gem_request_unsubmit in order to cancel the signaler quickly and release the reference on the request. Cancelling the signaler is done directly via intel_engine_cancel_signaling (called from unsubmit), but that does not directly wake up the signaling thread, and neither does setting the request->global_seqno back to zero wake up listeners to the request->execute waitqueue. So the only time that listening to the request->execute waitqueue would wake up the signaling kthread would be on the request resubmission, during which time we would already receive wake ups from rejoining the global breadcrumbs wait rbtree. Trying to wake up to release the request remains an issue. If the signaling was cancelled and no other request required signaling, then it is possible for us to shutdown with the reference on the request still held. To ensure that we do not try to shutdown, leaking that request, we kick the signaling threads whenever we disarm the breadcrumbs, i.e. on parking the engine when idle. v2: We do need to be sure to release the last reference on stopping the kthread; asserting that it has been dropped already is insufficient. Fixes: d6a2289d9d6b ("drm/i915: Remove the preempted request from the execution queue") Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Michał Winiarski Link: https://patchwork.freedesktop.org/patch/msgid/20171208121033.5236-1-chris@chris-wilson.co.uk Acked-by: Daniel Vetter Reviewed-by: Tvrtko Ursulin (cherry picked from commit 776bc27fd8ab67a675cb0041d3af361af5d0e290) Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_breadcrumbs.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c index 5f8b9f1f40f1..bcbc7abe6693 100644 --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c @@ -186,7 +186,7 @@ void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine) struct intel_wait *wait, *n, *first; if (!b->irq_armed) - return; + goto wakeup_signaler; /* We only disarm the irq when we are idle (all requests completed), * so if the bottom-half remains asleep, it missed the request @@ -208,6 +208,14 @@ void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine) b->waiters = RB_ROOT; spin_unlock_irq(&b->rb_lock); + + /* + * The signaling thread may be asleep holding a reference to a request, + * that had its signaling cancelled prior to being preempted. We need + * to kick the signaler, just in case, to release any such reference. + */ +wakeup_signaler: + wake_up_process(b->signaler); } static bool use_fake_irq(const struct intel_breadcrumbs *b) @@ -651,23 +659,15 @@ static int intel_breadcrumbs_signaler(void *arg) } if (unlikely(do_schedule)) { - DEFINE_WAIT(exec); - if (kthread_should_park()) kthread_parkme(); - if (kthread_should_stop()) { - GEM_BUG_ON(request); + if (unlikely(kthread_should_stop())) { + i915_gem_request_put(request); break; } - if (request) - add_wait_queue(&request->execute, &exec); - schedule(); - - if (request) - remove_wait_queue(&request->execute, &exec); } i915_gem_request_put(request); } while (1); -- GitLab From 2cf654db8d7eafb973d28eb3cddf043d353e1345 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 13 Dec 2017 09:48:02 +0000 Subject: [PATCH 1453/2547] drm/i915/fence: Use rcu to defer freeing of irq_work It is illegal to perform an immediate free of the struct irq_work from inside the irq_work callback (as irq_work_run_list modifies work->flags after execution of the work->func()). As we use the irq_work to coordinate the freeing of the callback from two different softirq paths, we need to defer the kfree from inside our irq_work callback, for which we can use kfree_rcu. Fixes: 81c0ed21aa91 ("drm/i915/fence: Avoid del_timer_sync() from inside a timer") Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Joonas Lahtinen Reviewed-by: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20171213094802.28243-1-chris@chris-wilson.co.uk (cherry picked from commit 7d622351c94172a42bfe9b13bdb0fdc2be90ed3b) Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_sw_fence.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c index e8ca67a129d2..ac236b88c99c 100644 --- a/drivers/gpu/drm/i915/i915_sw_fence.c +++ b/drivers/gpu/drm/i915/i915_sw_fence.c @@ -367,6 +367,7 @@ struct i915_sw_dma_fence_cb { struct dma_fence *dma; struct timer_list timer; struct irq_work work; + struct rcu_head rcu; }; static void timer_i915_sw_fence_wake(struct timer_list *t) @@ -406,7 +407,7 @@ static void irq_i915_sw_fence_work(struct irq_work *wrk) del_timer_sync(&cb->timer); dma_fence_put(cb->dma); - kfree(cb); + kfree_rcu(cb, rcu); } int i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence, -- GitLab From da2e6b7eeda8919f677c790ef51161dd02e513a6 Mon Sep 17 00:00:00 2001 From: Amir Goldstein Date: Wed, 22 Nov 2017 20:27:34 +0200 Subject: [PATCH 1454/2547] ovl: fix overlay: warning prefix Conform two stray warning messages to the standard overlayfs: prefix. Signed-off-by: Amir Goldstein Signed-off-by: Miklos Szeredi --- fs/overlayfs/dir.c | 3 ++- fs/overlayfs/readdir.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/fs/overlayfs/dir.c b/fs/overlayfs/dir.c index e13921824c70..f9788bc116a8 100644 --- a/fs/overlayfs/dir.c +++ b/fs/overlayfs/dir.c @@ -887,7 +887,8 @@ static int ovl_set_redirect(struct dentry *dentry, bool samedir) spin_unlock(&dentry->d_lock); } else { kfree(redirect); - pr_warn_ratelimited("overlay: failed to set redirect (%i)\n", err); + pr_warn_ratelimited("overlayfs: failed to set redirect (%i)\n", + err); /* Fall back to userspace copy-up */ err = -EXDEV; } diff --git a/fs/overlayfs/readdir.c b/fs/overlayfs/readdir.c index 51088849ce97..8c98578d27a1 100644 --- a/fs/overlayfs/readdir.c +++ b/fs/overlayfs/readdir.c @@ -499,7 +499,7 @@ static int ovl_cache_update_ino(struct path *path, struct ovl_cache_entry *p) return err; fail: - pr_warn_ratelimited("overlay: failed to look up (%s) for ino (%i)\n", + pr_warn_ratelimited("overlayfs: failed to look up (%s) for ino (%i)\n", p->name, err); goto out; } -- GitLab From 1d08a044cf12aee37dfd54837558e3295287b343 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Wed, 13 Dec 2017 11:45:42 +0000 Subject: [PATCH 1455/2547] arm64: fix CONFIG_DEBUG_WX address reporting In ptdump_check_wx(), we pass walk_pgd() a start address of 0 (rather than VA_START) for the init_mm. This means that any reported W&X addresses are offset by VA_START, which is clearly wrong and can make them appear like userspace addresses. Fix this by telling the ptdump code that we're walking init_mm starting at VA_START. We don't need to update the addr_markers, since these are still valid bounds regardless. Cc: Fixes: 1404d6f13e47 ("arm64: dump: Add checking for writable and exectuable pages") Signed-off-by: Mark Rutland Cc: Kees Cook Cc: Laura Abbott Reported-by: Timur Tabi Signed-off-by: Will Deacon --- arch/arm64/mm/dump.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/mm/dump.c b/arch/arm64/mm/dump.c index ca74a2aace42..7b60d62ac593 100644 --- a/arch/arm64/mm/dump.c +++ b/arch/arm64/mm/dump.c @@ -389,7 +389,7 @@ void ptdump_check_wx(void) .check_wx = true, }; - walk_pgd(&st, &init_mm, 0); + walk_pgd(&st, &init_mm, VA_START); note_page(&st, 0, 0, 0); if (st.wx_pages || st.uxn_pages) pr_warn("Checked W+X mappings: FAILED, %lu W+X pages found, %lu non-UXN pages found\n", -- GitLab From 958d022e326810fd762505bd02007aced79ffcbc Mon Sep 17 00:00:00 2001 From: "oder_chiou@realtek.com" Date: Thu, 14 Dec 2017 09:54:07 +0800 Subject: [PATCH 1456/2547] ASoC: rt5663: Fix the wrong result of the first jack detection In the first jack detection while booting, the result will always show as headset, even we insert the headphone. Signed-off-by: Oder Chiou Signed-off-by: Mark Brown --- sound/soc/codecs/rt5663.c | 4 ++++ sound/soc/codecs/rt5663.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/sound/soc/codecs/rt5663.c b/sound/soc/codecs/rt5663.c index b036c9dc0c8c..d329bf719d80 100644 --- a/sound/soc/codecs/rt5663.c +++ b/sound/soc/codecs/rt5663.c @@ -1560,6 +1560,10 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert) RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN); snd_soc_update_bits(codec, RT5663_IRQ_1, RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN); + snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1, + RT5663_EM_JD_MASK, RT5663_EM_JD_RST); + snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1, + RT5663_EM_JD_MASK, RT5663_EM_JD_NOR); while (true) { regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val); diff --git a/sound/soc/codecs/rt5663.h b/sound/soc/codecs/rt5663.h index c5a9b69579ad..03adc8004ba9 100644 --- a/sound/soc/codecs/rt5663.h +++ b/sound/soc/codecs/rt5663.h @@ -1029,6 +1029,10 @@ #define RT5663_POL_EXT_JD_SHIFT 10 #define RT5663_POL_EXT_JD_EN (0x1 << 10) #define RT5663_POL_EXT_JD_DIS (0x0 << 10) +#define RT5663_EM_JD_MASK (0x1 << 7) +#define RT5663_EM_JD_SHIFT 7 +#define RT5663_EM_JD_NOR (0x1 << 7) +#define RT5663_EM_JD_RST (0x0 << 7) /* DACREF LDO Control (0x0112)*/ #define RT5663_PWR_LDO_DACREFL_MASK (0x1 << 9) -- GitLab From fe66e92888a1cc0275d98be2d62ba81a097ec3f5 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 13 Dec 2017 17:11:54 +0000 Subject: [PATCH 1457/2547] drm/i915: make CS frequency read support missing more obvious As suggested by Chris, we should make this more obvious for people working with newer generations. Suggested-by: Chris Wilson Signed-off-by: Lionel Landwerlin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171213171154.6201-1-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/intel_device_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 405d70124a46..f478be3ae0ba 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -416,7 +416,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) return freq; } - DRM_ERROR("Unknown gen, unable to compute command stream timestamp frequency\n"); + MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n"); return 0; } -- GitLab From 84ef3a727e32ac32380e28198c3fdc6dcf941ec6 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 14 Dec 2017 12:26:13 +0000 Subject: [PATCH 1458/2547] drm/i915: Show engine state when hangcheck detects a stall Knowing the state of the engine when hangcheck thinks it is stalling is useful for both debugging hangcheck itself and the potential cause of an unwanted stall. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171214122613.26134-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_hangcheck.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c index 95bbb5a79c4f..0acd9dd3ed5c 100644 --- a/drivers/gpu/drm/i915/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/intel_hangcheck.c @@ -349,13 +349,18 @@ static void hangcheck_accumulate_sample(struct intel_engine_cs *engine, case ENGINE_ACTIVE_HEAD: case ENGINE_ACTIVE_SUBUNITS: - /* Seqno stuck with still active engine gets leeway, + /* + * Seqno stuck with still active engine gets leeway, * in hopes that it is just a long shader. */ timeout = I915_SEQNO_DEAD_TIMEOUT; break; case ENGINE_DEAD: + if (drm_debug & DRM_UT_DRIVER) { + struct drm_printer p = drm_debug_printer("hangcheck"); + intel_engine_dump(engine, &p, "%s", engine->name); + } break; default: -- GitLab From 3fab39997a98b97138c886978af660c4f6c7e9e6 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Thu, 14 Dec 2017 14:03:44 +0000 Subject: [PATCH 1459/2547] arm64/sve: Report SVE to userspace via CPUID only if supported Currently, the SVE field in ID_AA64PFR0_EL1 is visible unconditionally to userspace via the CPU ID register emulation, irrespective of the kernel config. This means that if a kernel configured with CONFIG_ARM64_SVE=n is run on SVE-capable hardware, userspace will see SVE reported as present in the ID regs even though the kernel forbids execution of SVE instructions. This patch makes the exposure of the SVE field in ID_AA64PFR0_EL1 conditional on CONFIG_ARM64_SVE=y. Since future architecture features are likely to encounter a similar requirement, this patch adds a suitable helper macros for use when declaring config-conditional ID register fields. Fixes: 43994d824e84 ("arm64/sve: Detect SVE and activate runtime support") Reviewed-by: Suzuki K Poulose Reported-by: Mark Rutland Signed-off-by: Dave Martin Cc: Suzuki Poulose Signed-off-by: Will Deacon --- arch/arm64/include/asm/cpufeature.h | 3 +++ arch/arm64/kernel/cpufeature.c | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index ac67cfc2585a..060e3a4008ab 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -60,6 +60,9 @@ enum ftr_type { #define FTR_VISIBLE true /* Feature visible to the user space */ #define FTR_HIDDEN false /* Feature is hidden from the user */ +#define FTR_VISIBLE_IF_IS_ENABLED(config) \ + (IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN) + struct arm64_ftr_bits { bool sign; /* Value is signed ? */ bool visible; diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c5ba0097887f..a73a5928f09b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -145,7 +145,8 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), -- GitLab From 5cc636846d23ed817fdda9f00faa56284759d444 Mon Sep 17 00:00:00 2001 From: Roger He Date: Thu, 7 Dec 2017 12:51:19 +0800 Subject: [PATCH 1460/2547] drm/ttm: init locked again to prevent incorrect unlock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Roger He Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 97c3da6d5f17..7a9abc2a3a98 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -737,6 +737,7 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev, place)) { if (locked) reservation_object_unlock(bo->resv); + locked = false; continue; } break; -- GitLab From ebe0dce655b6d0b1adec54cd6feac9bf15af7fdf Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Wed, 13 Dec 2017 17:39:07 +0800 Subject: [PATCH 1461/2547] drm/amd/pp: reset dpm level when adjust power state Acked-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c index ffa44bbb218e..ab852b2cdf54 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c @@ -244,7 +244,7 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip, } phm_notify_smc_display_config_after_ps_adjustment(hwmgr); - + phm_force_dpm_levels(hwmgr, hwmgr->dpm_level); return 0; } -- GitLab From 096480eac61ca8aa1834ba7ceda165d397e29ca0 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Wed, 15 Nov 2017 16:06:15 -0500 Subject: [PATCH 1462/2547] drm/amd/display: Remove unnecessary wait mpcc idle. Before power gate plane, mpcc idle wait is processed, no need to wait another time. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index d1488d5ee028..18fc5e792d5c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1178,12 +1178,6 @@ static void commit_planes_for_stream(struct dc *dc, if (update_type == UPDATE_TYPE_FULL) { dc->hwss.set_bandwidth(dc, context, false); context_clock_trace(dc, context); - - for (j = 0; j < dc->res_pool->pipe_count; j++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - - dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); - } } if (surface_count == 0) { -- GitLab From c984d06b7bca3b0451faa5e0c323e4ff16b365b3 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 15 Nov 2017 18:27:31 -0500 Subject: [PATCH 1463/2547] drm/amd/display: fix seq issue: turn on clock before programming afmt. Signed-off-by: Charlene Liu Reviewed-by: Krunoslav Kovac Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index 83bae207371d..327a0a76266b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -87,8 +87,10 @@ static void dce110_update_generic_info_packet( */ uint32_t max_retries = 50; + REG_GET(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, ®val); /*we need turn on clock before programming AFMT block*/ - REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); + if (regval != 1) + REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); if (REG(AFMT_VBI_PACKET_CONTROL1)) { if (packet_index >= 8) -- GitLab From f033680df696be9020fcc85bc649879988415c64 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 15 Nov 2017 18:55:57 -0500 Subject: [PATCH 1464/2547] drm/amd/display: try to find matching audio inst for enc inst first [Description] in eDP+ HDMI/DP clone or extended configuration, audio inst changed from inst 1 to inst0. No failure related this though, just playback device endpoint inst changed. Also remove one addition register read. Signed-off-by: Charlene Liu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index 327a0a76266b..83bae207371d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -87,10 +87,8 @@ static void dce110_update_generic_info_packet( */ uint32_t max_retries = 50; - REG_GET(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, ®val); /*we need turn on clock before programming AFMT block*/ - if (regval != 1) - REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); + REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); if (REG(AFMT_VBI_PACKET_CONTROL1)) { if (packet_index >= 8) -- GitLab From 4b87d3a87daecd6a828eeb05814482d97b16df31 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Wed, 15 Nov 2017 23:58:20 -0500 Subject: [PATCH 1465/2547] drm/amd/display: dal 3.1.21 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index c99ed85ba9a2..71f1802a25d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.20" +#define DC_VER "3.1.21" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From feb4a3cd8eb007f4749dc8323110f42fb4682ae0 Mon Sep 17 00:00:00 2001 From: Eric Bernstein Date: Mon, 6 Nov 2017 16:38:55 -0500 Subject: [PATCH 1466/2547] drm/amd/display: Integrating MPC pseudocode Integrating MPC pseudocode to support new blending cases with secondary MPCC list. This includes a design change to MPC data structures and interfaces. Signed-off-by: Eric Bernstein Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 - .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 144 +++-- .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 535 ++++++++++-------- .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 93 ++- .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 9 +- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 164 +++++- drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 3 +- 7 files changed, 594 insertions(+), 356 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 587c0bb3d4ac..03029f72dc3f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -579,8 +579,6 @@ enum dc_timing_standard { TIMING_STANDARD_MAX }; - - enum dc_color_depth { COLOR_DEPTH_UNDEFINED, COLOR_DEPTH_666, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 8e2ddbc2129c..3abd6d92aae0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -573,28 +573,25 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) int fe_idx = pipe_ctx->pipe_idx; struct hubp *hubp = dc->res_pool->hubps[fe_idx]; struct mpc *mpc = dc->res_pool->mpc; - int opp_id, z_idx; - int mpcc_id = -1; + int opp_id; + struct mpc_tree *mpc_tree_params; + struct mpcc *mpcc_to_remove = NULL; /* look at tree rather than mi here to know if we already reset */ for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) { struct output_pixel_processor *opp = dc->res_pool->opps[opp_id]; - for (z_idx = 0; z_idx < opp->mpc_tree.num_pipes; z_idx++) { - if (opp->mpc_tree.dpp[z_idx] == fe_idx) { - mpcc_id = opp->mpc_tree.mpcc[z_idx]; - break; - } - } - if (mpcc_id != -1) + mpc_tree_params = &(opp->mpc_tree_params); + mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, fe_idx); + if (mpcc_to_remove != NULL) break; } + /*Already reset*/ if (opp_id == dc->res_pool->pipe_count) return; - mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree), - dc->res_pool->opps[opp_id]->inst, fe_idx); + mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove); if (hubp->funcs->hubp_disconnect) hubp->funcs->hubp_disconnect(hubp); @@ -652,7 +649,7 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) REG_UPDATE(DPP_CONTROL[fe_idx], DPP_CLOCK_ENABLE, 0); - if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0) + if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree_params.opp_list == NULL) REG_UPDATE(OPP_PIPE_CONTROL[opp_id], OPP_PIPE_CLOCK_EN, 0); @@ -677,7 +674,7 @@ static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) static void dcn10_init_hw(struct dc *dc) { - int i; + int i, opp_id; struct abm *abm = dc->res_pool->abm; struct dmcu *dmcu = dc->res_pool->dmcu; struct dce_hwseq *hws = dc->hwseq; @@ -740,17 +737,19 @@ static void dcn10_init_hw(struct dc *dc) } } + /* Initialize MPC tree based on HW values */ + for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) { + struct output_pixel_processor *opp = dc->res_pool->opps[opp_id]; + struct mpc_tree *mpc_tree_params = &(opp->mpc_tree_params); + + dc->res_pool->mpc->funcs->init_mpcc_list_from_hw(dc->res_pool->mpc, mpc_tree_params); + } + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct timing_generator *tg = dc->res_pool->timing_generators[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - struct output_pixel_processor *opp = dc->res_pool->opps[i]; - struct mpc_tree_cfg *mpc_tree = &opp->mpc_tree; struct hubp *hubp = dc->res_pool->hubps[i]; - mpc_tree->dpp[0] = i; - mpc_tree->mpcc[0] = i; - mpc_tree->num_pipes = 1; - pipe_ctx->stream_res.tg = tg; pipe_ctx->pipe_idx = i; @@ -1694,38 +1693,6 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, } } -static void set_mpc_output_csc(struct dc *dc, - struct pipe_ctx *pipe_ctx, - enum dc_color_space colorspace, - uint16_t *matrix, - int opp_id) -{ - struct mpc *mpc = dc->res_pool->mpc; - int i; - struct out_csc_color_matrix tbl_entry; - enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; - - - if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { - //uint16_t matrix[12]; - for (i = 0; i < 12; i++) - tbl_entry.regval[i] = matrix[i]; - tbl_entry.color_space = colorspace; - - if (mpc->funcs->set_output_csc != NULL) - mpc->funcs->set_output_csc(mpc, - opp_id, - &tbl_entry, - ocsc_mode); - } else { - if (mpc->funcs->set_ocsc_default != NULL) - mpc->funcs->set_ocsc_default(mpc, - opp_id, - colorspace, - ocsc_mode); - } -} - static void program_output_csc(struct dc *dc, struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace, @@ -1736,13 +1703,6 @@ static void program_output_csc(struct dc *dc, program_csc_matrix(pipe_ctx, colorspace, matrix); - else - set_mpc_output_csc(dc, - pipe_ctx, - colorspace, - matrix, - opp_id); - } static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) @@ -1914,35 +1874,73 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) { - struct mpcc_cfg mpcc_cfg = {0}; struct hubp *hubp = pipe_ctx->plane_res.hubp; - struct pipe_ctx *top_pipe; - bool per_pixel_alpha = - pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; + struct mpcc_blnd_cfg blnd_cfg; + bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; + int mpcc_id; + struct mpcc *new_mpcc; + struct mpc *mpc = dc->res_pool->mpc; + struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); /* TODO: proper fix once fpga works */ - mpcc_cfg.dpp_id = hubp->inst; - mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst; - mpcc_cfg.tree_cfg = &(pipe_ctx->stream_res.opp->mpc_tree); - for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe) - mpcc_cfg.z_index++; if (dc->debug.surface_visual_confirm) dcn10_get_surface_visual_confirm_color( - pipe_ctx, &mpcc_cfg.black_color); + pipe_ctx, &blnd_cfg.black_color); else color_space_to_black_color( dc, pipe_ctx->stream->output_color_space, - &mpcc_cfg.black_color); - mpcc_cfg.per_pixel_alpha = per_pixel_alpha; + &blnd_cfg.black_color); + + if (per_pixel_alpha) + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; + else + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; + + blnd_cfg.overlap_only = false; + blnd_cfg.global_alpha = 0xff; + blnd_cfg.global_gain = 0xff; + /* DCN1.0 has output CM before MPC which seems to screw with * pre-multiplied alpha. */ - mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace( + blnd_cfg.pre_multiplied_alpha = is_rgb_cspace( pipe_ctx->stream->output_color_space) && per_pixel_alpha; - hubp->mpcc_id = dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg); - hubp->opp_id = mpcc_cfg.opp_id; + + /* + * TODO: remove hack + * Note: currently there is a bug in init_hw such that + * on resume from hibernate, BIOS sets up MPCC0, and + * we do mpcc_remove but the mpcc cannot go to idle + * after remove. This cause us to pick mpcc1 here, + * which causes a pstate hang for yet unknown reason. + */ + mpcc_id = hubp->inst; + + /* check if this MPCC is already being used */ + new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); + /* remove MPCC if being used */ + if (new_mpcc != NULL) + mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); + + if (dc->debug.sanity_checks) + mpc->funcs->assert_mpcc_idle_before_connect( + dc->res_pool->mpc, mpcc_id); + + /* Call MPC to insert new plane */ + new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, + mpc_tree_params, + &blnd_cfg, + NULL, + NULL, + hubp->inst, + mpcc_id); + + ASSERT(new_mpcc != NULL); + + hubp->opp_id = pipe_ctx->stream_res.opp->inst; + hubp->mpcc_id = mpcc_id; } static void update_scaler(struct pipe_ctx *pipe_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index b016f4cbd45c..e926c29993f9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -25,8 +25,6 @@ #include "reg_helper.h" #include "dcn10_mpc.h" -#include "dc.h" -#include "mem_input.h" #define REG(reg)\ mpc10->mpc_regs->reg @@ -38,17 +36,13 @@ #define FN(reg_name, field_name) \ mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name -#define MODE_TOP_ONLY 1 -#define MODE_BLEND 3 -#define BLND_PP_ALPHA 0 -#define BLND_GLOBAL_ALPHA 2 - -static void mpc10_set_bg_color( - struct dcn10_mpc *mpc10, +void mpc1_set_bg_color(struct mpc *mpc, struct tg_color *bg_color, - int id) + int mpcc_id) { + struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); + /* mpc color is 12 bit. tg_color is 10 bit */ /* todo: might want to use 16 bit to represent color and have each * hw block translate to correct color depth. @@ -57,15 +51,47 @@ static void mpc10_set_bg_color( uint32_t bg_g_y = bg_color->color_g_y << 2; uint32_t bg_b_cb = bg_color->color_b_cb << 2; - REG_SET(MPCC_BG_R_CR[id], 0, + REG_SET(MPCC_BG_R_CR[mpcc_id], 0, MPCC_BG_R_CR, bg_r_cr); - REG_SET(MPCC_BG_G_Y[id], 0, + REG_SET(MPCC_BG_G_Y[mpcc_id], 0, MPCC_BG_G_Y, bg_g_y); - REG_SET(MPCC_BG_B_CB[id], 0, + REG_SET(MPCC_BG_B_CB[mpcc_id], 0, MPCC_BG_B_CB, bg_b_cb); } -void mpc10_assert_idle_mpcc(struct mpc *mpc, int id) +static void mpc1_update_blending( + struct mpc *mpc, + struct mpcc_blnd_cfg *blnd_cfg, + int mpcc_id) +{ + struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); + + REG_UPDATE_5(MPCC_CONTROL[mpcc_id], + MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, + MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha, + MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only, + MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha, + MPCC_GLOBAL_GAIN, blnd_cfg->global_gain); + + mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id); +} + +void mpc1_update_stereo_mix( + struct mpc *mpc, + struct mpcc_sm_cfg *sm_cfg, + int mpcc_id) +{ + struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); + + REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id], + MPCC_SM_EN, sm_cfg->enable, + MPCC_SM_MODE, sm_cfg->sm_mode, + MPCC_SM_FRAME_ALT, sm_cfg->frame_alt, + MPCC_SM_FIELD_ALT, sm_cfg->field_alt, + MPCC_SM_FORCE_NEXT_FRAME_POL, sm_cfg->force_next_frame_porlarity, + MPCC_SM_FORCE_NEXT_TOP_POL, sm_cfg->force_next_field_polarity); +} +void mpc1_assert_idle_mpcc(struct mpc *mpc, int id) { struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); @@ -75,39 +101,62 @@ void mpc10_assert_idle_mpcc(struct mpc *mpc, int id) 1, 100000); } -static int mpc10_get_idle_mpcc_id(struct dcn10_mpc *mpc10) +static int mpc1_get_opp_id(struct mpc *mpc, int mpcc_id) { - int i; - int last_free_mpcc_id = -1; + struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); + unsigned int opp_id = 0xF; - for (i = 0; i < mpc10->num_mpcc; i++) { - uint32_t is_idle = 0; + REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); - if (mpc10->mpcc_in_use_mask & 1 << i) - continue; + return opp_id; +} - last_free_mpcc_id = i; - REG_GET(MPCC_STATUS[i], MPCC_IDLE, &is_idle); - if (is_idle) - return i; - } +struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) +{ + struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); - /* This assert should never trigger, we have mpcc leak if it does */ - ASSERT(last_free_mpcc_id != -1); + ASSERT(mpcc_id < mpc10->num_mpcc); + return &(mpc->mpcc_array[mpcc_id]); +} + +struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id) +{ + struct mpcc *tmp_mpcc = tree->opp_list; + + while (tmp_mpcc != NULL) { + if (tmp_mpcc->dpp_id == dpp_id) + return tmp_mpcc; + tmp_mpcc = tmp_mpcc->mpcc_bot; + } + return NULL; +} - mpc10_assert_idle_mpcc(&mpc10->base, last_free_mpcc_id); - return last_free_mpcc_id; +bool mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id) +{ + struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); + unsigned int top_sel; + unsigned int opp_id; + unsigned int idle; + + REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); + REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); + REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); + if (top_sel == 0xf && opp_id == 0xf && idle) + return true; + else + return false; } -static void mpc10_assert_mpcc_idle_before_connect(struct dcn10_mpc *mpc10, int id) +void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) { + struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); unsigned int top_sel, mpc_busy, mpc_idle; - REG_GET(MPCC_TOP_SEL[id], + REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); if (top_sel == 0xf) { - REG_GET_2(MPCC_STATUS[id], + REG_GET_2(MPCC_STATUS[mpcc_id], MPCC_BUSY, &mpc_busy, MPCC_IDLE, &mpc_idle); @@ -116,241 +165,258 @@ static void mpc10_assert_mpcc_idle_before_connect(struct dcn10_mpc *mpc10, int i } } -void mpc10_mpcc_remove( - struct mpc *mpc, - struct mpc_tree_cfg *tree_cfg, - int opp_id, - int dpp_id) -{ - struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); - int mpcc_id, z_idx; - - /* find z_idx for the dpp to be removed */ - for (z_idx = 0; z_idx < tree_cfg->num_pipes; z_idx++) - if (tree_cfg->dpp[z_idx] == dpp_id) - break; - - if (z_idx == tree_cfg->num_pipes) { - /* In case of resume from S3/S4, remove mpcc from bios left over */ - REG_SET(MPCC_OPP_ID[dpp_id], 0, - MPCC_OPP_ID, 0xf); - REG_SET(MPCC_TOP_SEL[dpp_id], 0, - MPCC_TOP_SEL, 0xf); - REG_SET(MPCC_BOT_SEL[dpp_id], 0, - MPCC_BOT_SEL, 0xf); - return; - } - - mpcc_id = tree_cfg->mpcc[z_idx]; - - REG_SET(MPCC_OPP_ID[mpcc_id], 0, - MPCC_OPP_ID, 0xf); - REG_SET(MPCC_TOP_SEL[mpcc_id], 0, - MPCC_TOP_SEL, 0xf); - REG_SET(MPCC_BOT_SEL[mpcc_id], 0, - MPCC_BOT_SEL, 0xf); - - if (z_idx > 0) { - int top_mpcc_id = tree_cfg->mpcc[z_idx - 1]; - - if (z_idx + 1 < tree_cfg->num_pipes) - /* mpcc to be removed is in the middle of the tree */ - REG_SET(MPCC_BOT_SEL[top_mpcc_id], 0, - MPCC_BOT_SEL, tree_cfg->mpcc[z_idx + 1]); - else { - /* mpcc to be removed is at the bottom of the tree */ - REG_SET(MPCC_BOT_SEL[top_mpcc_id], 0, - MPCC_BOT_SEL, 0xf); - REG_UPDATE(MPCC_CONTROL[top_mpcc_id], - MPCC_MODE, MODE_TOP_ONLY); - } - } else if (tree_cfg->num_pipes > 1) - /* mpcc to be removed is at the top of the tree */ - REG_SET(MUX[opp_id], 0, - MPC_OUT_MUX, tree_cfg->mpcc[z_idx + 1]); - else - /* mpcc to be removed is the only one in the tree */ - REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, 0xf); - - /* mark this mpcc as not in use */ - mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id); - tree_cfg->num_pipes--; - for (; z_idx < tree_cfg->num_pipes; z_idx++) { - tree_cfg->dpp[z_idx] = tree_cfg->dpp[z_idx + 1]; - tree_cfg->mpcc[z_idx] = tree_cfg->mpcc[z_idx + 1]; - } - tree_cfg->dpp[tree_cfg->num_pipes] = 0xdeadbeef; - tree_cfg->mpcc[tree_cfg->num_pipes] = 0xdeadbeef; -} - -static void mpc10_add_to_tree_cfg( +/* + * Insert DPP into MPC tree based on specified blending position. + * Only used for planes that are part of blending chain for OPP output + * + * Parameters: + * [in/out] mpc - MPC context. + * [in/out] tree - MPC tree structure that plane will be added to. + * [in] blnd_cfg - MPCC blending configuration for the new blending layer. + * [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. + * stereo mix must disable for the very bottom layer of the tree config. + * [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane. + * [in] dpp_id - DPP instance for the plane to be added. + * [in] mpcc_id - The MPCC physical instance to use for blending. + * + * Return: struct mpcc* - MPCC that was added. + */ +struct mpcc *mpc1_insert_plane( struct mpc *mpc, - struct mpcc_cfg *cfg, + struct mpc_tree *tree, + struct mpcc_blnd_cfg *blnd_cfg, + struct mpcc_sm_cfg *sm_cfg, + struct mpcc *insert_above_mpcc, + int dpp_id, int mpcc_id) { struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); - int mpcc_mode = MODE_TOP_ONLY; - int position = cfg->z_index; - struct mpc_tree_cfg *tree_cfg = cfg->tree_cfg; - int alpha_blnd_mode = cfg->per_pixel_alpha ? - BLND_PP_ALPHA : BLND_GLOBAL_ALPHA; - int z_idx; + struct mpcc *new_mpcc = NULL; - REG_SET(MPCC_OPP_ID[mpcc_id], 0, - MPCC_OPP_ID, cfg->opp_id); + /* sanity check parameters */ + ASSERT(mpcc_id < mpc10->num_mpcc); + ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id)); - REG_SET(MPCC_TOP_SEL[mpcc_id], 0, - MPCC_TOP_SEL, cfg->dpp_id); + if (insert_above_mpcc) { + /* check insert_above_mpcc exist in tree->opp_list */ + struct mpcc *temp_mpcc = tree->opp_list; - if (position == 0) { - /* idle dpp/mpcc is added to the top layer of tree */ + while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) + temp_mpcc = temp_mpcc->mpcc_bot; + if (temp_mpcc == NULL) + return NULL; + } - if (tree_cfg->num_pipes > 0) { - /* get instance of previous top mpcc */ - int prev_top_mpcc_id = tree_cfg->mpcc[0]; + /* Get and update MPCC struct parameters */ + new_mpcc = mpc1_get_mpcc(mpc, mpcc_id); + new_mpcc->dpp_id = dpp_id; - REG_SET(MPCC_BOT_SEL[mpcc_id], 0, - MPCC_BOT_SEL, prev_top_mpcc_id); - mpcc_mode = MODE_BLEND; + /* program mux and MPCC_MODE */ + if (insert_above_mpcc) { + new_mpcc->mpcc_bot = insert_above_mpcc; + REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); + REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING); + } else { + new_mpcc->mpcc_bot = NULL; + REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); + REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH); + } + REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); + REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); + + /* update mpc tree mux setting */ + if (tree->opp_list == insert_above_mpcc) { + /* insert the toppest mpcc */ + tree->opp_list = new_mpcc; + REG_SET(MUX[tree->opp_id], 0, MPC_OUT_MUX, mpcc_id); + } else { + /* find insert position */ + struct mpcc *temp_mpcc = tree->opp_list; + + while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) + temp_mpcc = temp_mpcc->mpcc_bot; + if (temp_mpcc && temp_mpcc->mpcc_bot == insert_above_mpcc) { + REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id); + temp_mpcc->mpcc_bot = new_mpcc; + if (!insert_above_mpcc) + REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id], + MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING); } + } - /* opp will get new output. from new added mpcc */ - REG_SET(MUX[cfg->opp_id], 0, MPC_OUT_MUX, mpcc_id); - - } else if (position == tree_cfg->num_pipes) { - /* idle dpp/mpcc is added to the bottom layer of tree */ - - /* get instance of previous bottom mpcc, set to middle layer */ - int prev_bot_mpcc_id = tree_cfg->mpcc[tree_cfg->num_pipes - 1]; - - REG_SET(MPCC_BOT_SEL[prev_bot_mpcc_id], 0, - MPCC_BOT_SEL, mpcc_id); - REG_UPDATE(MPCC_CONTROL[prev_bot_mpcc_id], - MPCC_MODE, MODE_BLEND); - - /* mpcc_id become new bottom mpcc*/ - REG_SET(MPCC_BOT_SEL[mpcc_id], 0, - MPCC_BOT_SEL, 0xf); + /* update the blending configuration */ + new_mpcc->blnd_cfg = *blnd_cfg; + mpc->funcs->update_blending(mpc, &new_mpcc->blnd_cfg, mpcc_id); - } else { - /* idle dpp/mpcc is added to middle of tree */ - int above_mpcc_id = tree_cfg->mpcc[position - 1]; - int below_mpcc_id = tree_cfg->mpcc[position]; - - /* mpcc above new mpcc_id has new bottom mux*/ - REG_SET(MPCC_BOT_SEL[above_mpcc_id], 0, - MPCC_BOT_SEL, mpcc_id); - REG_UPDATE(MPCC_CONTROL[above_mpcc_id], - MPCC_MODE, MODE_BLEND); - - /* mpcc_id bottom mux is from below mpcc*/ - REG_SET(MPCC_BOT_SEL[mpcc_id], 0, - MPCC_BOT_SEL, below_mpcc_id); - mpcc_mode = MODE_BLEND; + /* update the stereo mix settings, if provided */ + if (sm_cfg != NULL) { + new_mpcc->sm_cfg = *sm_cfg; + mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id); } - REG_SET_4(MPCC_CONTROL[mpcc_id], 0xffffffff, - MPCC_MODE, mpcc_mode, - MPCC_ALPHA_BLND_MODE, alpha_blnd_mode, - MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha, - MPCC_BLND_ACTIVE_OVERLAP_ONLY, false); + /* mark this mpcc as in use */ + mpc10->mpcc_in_use_mask |= 1 << mpcc_id; - /* update mpc_tree_cfg with new mpcc */ - for (z_idx = tree_cfg->num_pipes; z_idx > position; z_idx--) { - tree_cfg->dpp[z_idx] = tree_cfg->dpp[z_idx - 1]; - tree_cfg->mpcc[z_idx] = tree_cfg->mpcc[z_idx - 1]; - } - tree_cfg->dpp[position] = cfg->dpp_id; - tree_cfg->mpcc[position] = mpcc_id; - tree_cfg->num_pipes++; + return new_mpcc; } -int mpc10_mpcc_add(struct mpc *mpc, struct mpcc_cfg *cfg) +/* + * Remove a specified MPCC from the MPC tree. + * + * Parameters: + * [in/out] mpc - MPC context. + * [in/out] tree - MPC tree structure that plane will be removed from. + * [in/out] mpcc - MPCC to be removed from tree. + * + * Return: void + */ +void mpc1_remove_mpcc( + struct mpc *mpc, + struct mpc_tree *tree, + struct mpcc *mpcc_to_remove) { struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); - int mpcc_id, z_idx; - - ASSERT(cfg->z_index < mpc10->num_mpcc); - - /* check in dpp already exists in mpc tree */ - for (z_idx = 0; z_idx < cfg->tree_cfg->num_pipes; z_idx++) - if (cfg->tree_cfg->dpp[z_idx] == cfg->dpp_id) - break; - if (z_idx == cfg->tree_cfg->num_pipes) { - ASSERT(cfg->z_index <= cfg->tree_cfg->num_pipes); - mpcc_id = mpc10_get_idle_mpcc_id(mpc10); - - /* - * TODO: remove hack - * Note: currently there is a bug in init_hw such that - * on resume from hibernate, BIOS sets up MPCC0, and - * we do mpcc_remove but the mpcc cannot go to idle - * after remove. This cause us to pick mpcc1 here, - * which causes a pstate hang for yet unknown reason. - */ - mpcc_id = cfg->dpp_id; - /* end hack*/ - - ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id)); - - if (mpc->ctx->dc->debug.sanity_checks) - mpc10_assert_mpcc_idle_before_connect(mpc10, mpcc_id); + bool found = false; + int mpcc_id = mpcc_to_remove->mpcc_id; + + if (tree->opp_list == mpcc_to_remove) { + found = true; + /* remove MPCC from top of tree */ + if (mpcc_to_remove->mpcc_bot) { + /* set the next MPCC in list to be the top MPCC */ + tree->opp_list = mpcc_to_remove->mpcc_bot; + REG_SET(MUX[tree->opp_id], 0, MPC_OUT_MUX, tree->opp_list->mpcc_id); + } else { + /* there are no other MPCC is list */ + tree->opp_list = NULL; + REG_SET(MUX[tree->opp_id], 0, MPC_OUT_MUX, 0xf); + } } else { - ASSERT(cfg->z_index < cfg->tree_cfg->num_pipes); - mpcc_id = cfg->tree_cfg->mpcc[z_idx]; - mpc10_mpcc_remove(mpc, cfg->tree_cfg, cfg->opp_id, cfg->dpp_id); + /* find mpcc to remove MPCC list */ + struct mpcc *temp_mpcc = tree->opp_list; + + while (temp_mpcc && temp_mpcc->mpcc_bot != mpcc_to_remove) + temp_mpcc = temp_mpcc->mpcc_bot; + + if (temp_mpcc && temp_mpcc->mpcc_bot == mpcc_to_remove) { + found = true; + if (mpcc_to_remove->mpcc_bot) { + /* remove MPCC in middle of list */ + REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, + MPCC_BOT_SEL, mpcc_to_remove->mpcc_bot->mpcc_id); + temp_mpcc->mpcc_bot = mpcc_to_remove->mpcc_bot; + } else { + /* remove MPCC from bottom of list */ + REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, + MPCC_BOT_SEL, 0xf); + REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id], + MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH); + } + } } - /* add dpp/mpcc pair to mpc_tree_cfg and update mpcc registers */ - mpc10_add_to_tree_cfg(mpc, cfg, mpcc_id); - - /* set background color */ - mpc10_set_bg_color(mpc10, &cfg->black_color, mpcc_id); - - /* mark this mpcc as in use */ - mpc10->mpcc_in_use_mask |= 1 << mpcc_id; + if (found) { + /* turn off MPCC mux registers */ + REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); + REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); + REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); - return mpcc_id; + /* mark this mpcc as not in use */ + mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id); + mpcc_to_remove->dpp_id = 0xf; + mpcc_to_remove->mpcc_bot = NULL; + } else { + /* In case of resume from S3/S4, remove mpcc from bios left over */ + REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); + REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); + REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); + } } -void mpc10_update_blend_mode( - struct mpc *mpc, - struct mpcc_cfg *cfg) +/* + * Reset the MPCC HW status by disconnecting all muxes. + * + * Parameters: + * [in/out] mpc - MPC context. + * [in] mpcc_id - The MPCC physical instance to reset. + * + * Return: void + */ +void mpc1_reset_mpcc( + struct mpc *mpc, + int mpcc_id) { struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); - int mpcc_id, z_idx; - int alpha_blnd_mode = cfg->per_pixel_alpha ? - BLND_PP_ALPHA : BLND_GLOBAL_ALPHA; - - /* find z_idx for the dpp that requires blending mode update*/ - for (z_idx = 0; z_idx < cfg->tree_cfg->num_pipes; z_idx++) - if (cfg->tree_cfg->dpp[z_idx] == cfg->dpp_id) - break; - ASSERT(z_idx < cfg->tree_cfg->num_pipes); - mpcc_id = cfg->tree_cfg->mpcc[z_idx]; - - REG_UPDATE_2(MPCC_CONTROL[mpcc_id], - MPCC_ALPHA_BLND_MODE, alpha_blnd_mode, - MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha); + REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); + REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); + REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); } -int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id) +void mpc1_init_mpcc_list_from_hw( + struct mpc *mpc, + struct mpc_tree *tree) { struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); - int opp_id = 0xF; - - REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); + unsigned int opp_id; + unsigned int top_sel; + unsigned int bot_sel; + unsigned int out_mux; + struct mpcc *mpcc; + int mpcc_id; + int bot_mpcc_id; + + REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); + + if (out_mux != 0xf) { + for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) { + REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); + REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); + REG_GET(MPCC_STATUS[mpcc_id], MPCC_BOT_SEL, &bot_sel); + + if ((opp_id == tree->opp_id) && (top_sel != 0xf)) { + mpcc = mpc1_get_mpcc(mpc, mpcc_id); + mpcc->dpp_id = top_sel; + mpc10->mpcc_in_use_mask |= 1 << mpcc_id; + + if (out_mux == mpcc_id) + tree->opp_list = mpcc; + if (bot_sel != 0xf && bot_sel < mpc10->num_mpcc) { + bot_mpcc_id = bot_sel; + REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id); + REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel); + if ((opp_id == tree->opp_id) && (top_sel != 0xf)) { + struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id); + + mpcc->mpcc_bot = mpcc_bottom; + } + } + } + } + } +} - return opp_id; +static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) +{ + mpcc->mpcc_id = mpcc_inst; + mpcc->dpp_id = 0xf; + mpcc->mpcc_bot = NULL; + mpcc->blnd_cfg.overlap_only = false; + mpcc->blnd_cfg.global_alpha = 0xff; + mpcc->blnd_cfg.global_gain = 0xff; + mpcc->sm_cfg.enable = false; } const struct mpc_funcs dcn10_mpc_funcs = { - .add = mpc10_mpcc_add, - .remove = mpc10_mpcc_remove, - .wait_for_idle = mpc10_assert_idle_mpcc, - .update_blend_mode = mpc10_update_blend_mode, - .get_opp_id = mpc10_get_opp_id, + .insert_plane = mpc1_insert_plane, + .remove_mpcc = mpc1_remove_mpcc, + .reset_mpcc = mpc1_reset_mpcc, + .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, + .wait_for_idle = mpc1_assert_idle_mpcc, + .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect, + .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw, + .update_blending = mpc1_update_blending, + .get_opp_id = mpc1_get_opp_id, }; void dcn10_mpc_construct(struct dcn10_mpc *mpc10, @@ -360,6 +426,8 @@ void dcn10_mpc_construct(struct dcn10_mpc *mpc10, const struct dcn_mpc_mask *mpc_mask, int num_mpcc) { + int i; + mpc10->base.ctx = ctx; mpc10->base.funcs = &dcn10_mpc_funcs; @@ -370,5 +438,8 @@ void dcn10_mpc_construct(struct dcn10_mpc *mpc10, mpc10->mpcc_in_use_mask = 0; mpc10->num_mpcc = num_mpcc; + + for (i = 0; i < MAX_MPCC; i++) + mpc1_init_mpcc(&mpc10->base.mpcc_array[i], i); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h index e85e1f342266..aa2cd40dc022 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h @@ -30,9 +30,6 @@ #define TO_DCN10_MPC(mpc_base) \ container_of(mpc_base, struct dcn10_mpc, base) -#define MAX_MPCC 6 -#define MAX_OPP 6 - #define MPC_COMMON_REG_LIST_DCN1_0(inst) \ SRII(MPCC_TOP_SEL, MPCC, inst),\ SRII(MPCC_BOT_SEL, MPCC, inst),\ @@ -42,7 +39,8 @@ SRII(MPCC_BG_G_Y, MPCC, inst),\ SRII(MPCC_BG_R_CR, MPCC, inst),\ SRII(MPCC_BG_B_CB, MPCC, inst),\ - SRII(MPCC_BG_B_CB, MPCC, inst) + SRII(MPCC_BG_B_CB, MPCC, inst),\ + SRII(MPCC_SM_CONTROL, MPCC, inst) #define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \ SRII(MUX, MPC_OUT, inst) @@ -56,6 +54,7 @@ uint32_t MPCC_BG_G_Y[MAX_MPCC]; \ uint32_t MPCC_BG_R_CR[MAX_MPCC]; \ uint32_t MPCC_BG_B_CB[MAX_MPCC]; \ + uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \ uint32_t MUX[MAX_OPP]; #define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ @@ -65,12 +64,20 @@ SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\ SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\ SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\ SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\ SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\ SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\ SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\ SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\ SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\ SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh) #define MPC_REG_FIELD_LIST(type) \ @@ -80,12 +87,20 @@ type MPCC_ALPHA_BLND_MODE;\ type MPCC_ALPHA_MULTIPLIED_MODE;\ type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\ + type MPCC_GLOBAL_ALPHA;\ + type MPCC_GLOBAL_GAIN;\ type MPCC_IDLE;\ type MPCC_BUSY;\ type MPCC_OPP_ID;\ type MPCC_BG_G_Y;\ type MPCC_BG_R_CR;\ type MPCC_BG_B_CB;\ + type MPCC_SM_EN;\ + type MPCC_SM_MODE;\ + type MPCC_SM_FRAME_ALT;\ + type MPCC_SM_FIELD_ALT;\ + type MPCC_SM_FORCE_NEXT_FRAME_POL;\ + type MPCC_SM_FORCE_NEXT_TOP_POL;\ type MPC_OUT_MUX; struct dcn_mpc_registers { @@ -117,23 +132,57 @@ void dcn10_mpc_construct(struct dcn10_mpc *mpcc10, const struct dcn_mpc_mask *mpc_mask, int num_mpcc); -int mpc10_mpcc_add( - struct mpc *mpc, - struct mpcc_cfg *cfg); - -void mpc10_mpcc_remove( - struct mpc *mpc, - struct mpc_tree_cfg *tree_cfg, - int opp_id, - int dpp_id); - -void mpc10_assert_idle_mpcc( - struct mpc *mpc, - int id); - -void mpc10_update_blend_mode( - struct mpc *mpc, - struct mpcc_cfg *cfg); -int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id); +struct mpcc *mpc1_insert_plane( + struct mpc *mpc, + struct mpc_tree *tree, + struct mpcc_blnd_cfg *blnd_cfg, + struct mpcc_sm_cfg *sm_cfg, + struct mpcc *insert_above_mpcc, + int dpp_id, + int mpcc_id); + +void mpc1_remove_mpcc( + struct mpc *mpc, + struct mpc_tree *tree, + struct mpcc *mpcc); + +void mpc1_reset_mpcc( + struct mpc *mpc, + int mpcc_id); + + +void mpc1_assert_idle_mpcc( + struct mpc *mpc, + int id); + +void mpc1_set_bg_color( + struct mpc *mpc, + struct tg_color *bg_color, + int id); + +void mpc1_update_stereo_mix( + struct mpc *mpc, + struct mpcc_sm_cfg *sm_cfg, + int mpcc_id); + +bool mpc1_is_mpcc_idle( + struct mpc *mpc, + int mpcc_id); + +void mpc1_assert_mpcc_idle_before_connect( + struct mpc *mpc, + int mpcc_id); + +void mpc1_init_mpcc_list_from_hw( + struct mpc *mpc, + struct mpc_tree *tree); + +struct mpcc *mpc1_get_mpcc( + struct mpc *mpc, + int mpcc_id); + +struct mpcc *mpc1_get_mpcc_for_dpp( + struct mpc_tree *tree, + int dpp_id); #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index 6d6f67b7d30e..20d78cf46ab0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -330,12 +330,19 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10, const struct dcn10_opp_shift *opp_shift, const struct dcn10_opp_mask *opp_mask) { + int i; + oppn10->base.ctx = ctx; oppn10->base.inst = inst; oppn10->base.funcs = &dcn10_opp_funcs; + oppn10->base.mpc_tree_params.opp_id = inst; + oppn10->base.mpc_tree_params.opp_list = NULL; + + for (i = 0; i < MAX_PIPES; i++) + oppn10->base.mpcc_disconnect_pending[i] = false; + oppn10->regs = regs; oppn10->opp_shift = opp_shift; oppn10->opp_mask = opp_mask; } - diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index 72ea33526a5c..2396b15befb0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -26,7 +26,10 @@ #define __DC_MPCC_H__ #include "dc_hw_types.h" -#include "opp.h" +#include "hw_shared.h" + +#define MAX_MPCC 6 +#define MAX_OPP 6 enum mpc_output_csc_mode { MPC_OUTPUT_CSC_DISABLE = 0, @@ -34,45 +37,156 @@ enum mpc_output_csc_mode { MPC_OUTPUT_CSC_COEF_B }; -struct mpcc_cfg { - int dpp_id; - int opp_id; - struct mpc_tree_cfg *tree_cfg; - unsigned int z_index; - struct tg_color black_color; - bool per_pixel_alpha; - bool pre_multiplied_alpha; +enum mpcc_blend_mode { + MPCC_BLEND_MODE_BYPASS, + MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH, + MPCC_BLEND_MODE_TOP_LAYER_ONLY, + MPCC_BLEND_MODE_TOP_BOT_BLENDING +}; + +enum mpcc_alpha_blend_mode { + MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA, + MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN, + MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA +}; + +/* + * MPCC blending configuration + */ +struct mpcc_blnd_cfg { + struct tg_color black_color; /* background color */ + enum mpcc_alpha_blend_mode alpha_mode; /* alpha blend mode */ + bool pre_multiplied_alpha; /* alpha pre-multiplied mode flag */ + int global_gain; + int global_alpha; + bool overlap_only; + +}; + +struct mpcc_sm_cfg { + bool enable; + /* 0-single plane,2-row subsampling,4-column subsampling,6-checkboard subsampling */ + int sm_mode; + /* 0- disable frame alternate, 1- enable frame alternate */ + bool frame_alt; + /* 0- disable field alternate, 1- enable field alternate */ + bool field_alt; + /* 0-no force,2-force frame polarity from top,3-force frame polarity from bottom */ + int force_next_frame_porlarity; + /* 0-no force,2-force field polarity from top,3-force field polarity from bottom */ + int force_next_field_polarity; +}; + +/* + * MPCC connection and blending configuration for a single MPCC instance. + * This struct is used as a node in an MPC tree. + */ +struct mpcc { + int mpcc_id; /* MPCC physical instance */ + int dpp_id; /* DPP input to this MPCC */ + struct mpcc *mpcc_bot; /* pointer to bottom layer MPCC. NULL when not connected */ + struct mpcc_blnd_cfg blnd_cfg; /* The blending configuration for this MPCC */ + struct mpcc_sm_cfg sm_cfg; /* stereo mix setting for this MPCC */ +}; + +/* + * MPC tree represents all MPCC connections for a pipe. + */ +struct mpc_tree { + int opp_id; /* The OPP instance that owns this MPC tree */ + struct mpcc *opp_list; /* The top MPCC layer of the MPC tree that outputs to OPP endpoint */ }; struct mpc { const struct mpc_funcs *funcs; struct dc_context *ctx; + + struct mpcc mpcc_array[MAX_MPCC]; }; struct mpc_funcs { - int (*add)(struct mpc *mpc, struct mpcc_cfg *cfg); + /* + * Insert DPP into MPC tree based on specified blending position. + * Only used for planes that are part of blending chain for OPP output + * + * Parameters: + * [in/out] mpc - MPC context. + * [in/out] tree - MPC tree structure that plane will be added to. + * [in] blnd_cfg - MPCC blending configuration for the new blending layer. + * [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. + * stereo mix must disable for the very bottom layer of the tree config. + * [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane. + * [in] dpp_id - DPP instance for the plane to be added. + * [in] mpcc_id - The MPCC physical instance to use for blending. + * + * Return: struct mpcc* - MPCC that was added. + */ + struct mpcc* (*insert_plane)( + struct mpc *mpc, + struct mpc_tree *tree, + struct mpcc_blnd_cfg *blnd_cfg, + struct mpcc_sm_cfg *sm_cfg, + struct mpcc *insert_above_mpcc, + int dpp_id, + int mpcc_id); - void (*remove)(struct mpc *mpc, - struct mpc_tree_cfg *tree_cfg, - int opp_id, - int mpcc_inst); + /* + * Remove a specified MPCC from the MPC tree. + * + * Parameters: + * [in/out] mpc - MPC context. + * [in/out] tree - MPC tree structure that plane will be removed from. + * [in/out] mpcc - MPCC to be removed from tree. + * + * Return: void + */ + void (*remove_mpcc)( + struct mpc *mpc, + struct mpc_tree *tree, + struct mpcc *mpcc); - void (*wait_for_idle)(struct mpc *mpc, int id); + /* + * Reset the MPCC HW status by disconnecting all muxes. + * + * Parameters: + * [in/out] mpc - MPC context. + * [in] mpcc_id - The MPCC physical instance to reset. + * + * Return: void + */ + void (*reset_mpcc)( + struct mpc *mpc, + int mpcc_id); - void (*update_blend_mode)(struct mpc *mpc, struct mpcc_cfg *cfg); + /* + * Update the blending configuration for a specified MPCC. + * + * Parameters: + * [in/out] mpc - MPC context. + * [in] blnd_cfg - MPCC blending configuration. + * [in] mpcc_id - The MPCC physical instance. + * + * Return: void + */ + void (*update_blending)( + struct mpc *mpc, + struct mpcc_blnd_cfg *blnd_cfg, + int mpcc_id); - int (*get_opp_id)(struct mpc *mpc, int mpcc_id); + struct mpcc* (*get_mpcc_for_dpp)( + struct mpc_tree *tree, + int dpp_id); + + void (*wait_for_idle)(struct mpc *mpc, int id); - void (*set_output_csc)(struct mpc *mpc, - int opp_id, - const struct out_csc_color_matrix *tbl_entry, - enum mpc_output_csc_mode ocsc_mode); + void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id); - void (*set_ocsc_default)(struct mpc *mpc, - int opp_id, - enum dc_color_space color_space, - enum mpc_output_csc_mode ocsc_mode); + void (*init_mpcc_list_from_hw)( + struct mpc *mpc, + struct mpc_tree *tree); + + int (*get_opp_id)(struct mpc *mpc, int mpcc_id); }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 579d1059a3d4..8c3a302fcd65 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -29,6 +29,7 @@ #include "hw_shared.h" #include "dc_hw_types.h" #include "transform.h" +#include "mpc.h" struct fixed31_32; @@ -204,7 +205,7 @@ struct output_pixel_processor { struct dc_context *ctx; uint32_t inst; struct pwl_params regamma_params; - struct mpc_tree_cfg mpc_tree; + struct mpc_tree mpc_tree_params; bool mpcc_disconnect_pending[MAX_PIPES]; const struct opp_funcs *funcs; }; -- GitLab From 492c378aaa63e0ba65e6ee9645022e2b83703f25 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 10 Nov 2017 20:01:38 -0500 Subject: [PATCH 1467/2547] drm/amd/display: Remove PSR functions in Linux NULL check issue found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:1976 dc_link_setup_psr() warn: variable dereferenced before check 'link' (see line 1970) We don't use these functions so might as well remove them. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 138 ------------------ 1 file changed, 138 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 7b0e43c0685c..0b7058fddc2e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1952,144 +1952,6 @@ bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait) return true; } -bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) -{ - struct dc *core_dc = link->ctx->dc; - struct dmcu *dmcu = core_dc->res_pool->dmcu; - - if (dmcu != NULL && link->psr_enabled) - dmcu->funcs->get_psr_state(dmcu, psr_state); - - return true; -} - -bool dc_link_setup_psr(struct dc_link *link, - const struct dc_stream_state *stream, struct psr_config *psr_config, - struct psr_context *psr_context) -{ - struct dc *core_dc = link->ctx->dc; - struct dmcu *dmcu = core_dc->res_pool->dmcu; - int i; - - psr_context->controllerId = CONTROLLER_ID_UNDEFINED; - - if (link != NULL && - dmcu != NULL) { - /* updateSinkPsrDpcdConfig*/ - union dpcd_psr_configuration psr_configuration; - - memset(&psr_configuration, 0, sizeof(psr_configuration)); - - psr_configuration.bits.ENABLE = 1; - psr_configuration.bits.CRC_VERIFICATION = 1; - psr_configuration.bits.FRAME_CAPTURE_INDICATION = - psr_config->psr_frame_capture_indication_req; - - /* Check for PSR v2*/ - if (psr_config->psr_version == 0x2) { - /* For PSR v2 selective update. - * Indicates whether sink should start capturing - * immediately following active scan line, - * or starting with the 2nd active scan line. - */ - psr_configuration.bits.LINE_CAPTURE_INDICATION = 0; - /*For PSR v2, determines whether Sink should generate - * IRQ_HPD when CRC mismatch is detected. - */ - psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1; - } - - dm_helpers_dp_write_dpcd( - link->ctx, - link, - 368, - &psr_configuration.raw, - sizeof(psr_configuration.raw)); - - psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel; - psr_context->transmitterId = link->link_enc->transmitter; - psr_context->engineId = link->link_enc->preferred_engine; - - for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_state->res_ctx.pipe_ctx[i].stream - == stream) { - /* dmcu -1 for all controller id values, - * therefore +1 here - */ - psr_context->controllerId = - core_dc->current_state->res_ctx. - pipe_ctx[i].stream_res.tg->inst + 1; - break; - } - } - - /* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/ - psr_context->phyType = PHY_TYPE_UNIPHY; - /*PhyId is associated with the transmitter id*/ - psr_context->smuPhyId = link->link_enc->transmitter; - - psr_context->crtcTimingVerticalTotal = stream->timing.v_total; - psr_context->vsyncRateHz = div64_u64(div64_u64((stream-> - timing.pix_clk_khz * 1000), - stream->timing.v_total), - stream->timing.h_total); - - psr_context->psrSupportedDisplayConfig = true; - psr_context->psrExitLinkTrainingRequired = - psr_config->psr_exit_link_training_required; - psr_context->sdpTransmitLineNumDeadline = - psr_config->psr_sdp_transmit_line_num_deadline; - psr_context->psrFrameCaptureIndicationReq = - psr_config->psr_frame_capture_indication_req; - - psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */ - - psr_context->numberOfControllers = - link->dc->res_pool->res_cap->num_timing_generator; - - psr_context->rfb_update_auto_en = true; - - /* 2 frames before enter PSR. */ - psr_context->timehyst_frames = 2; - /* half a frame - * (units in 100 lines, i.e. a value of 1 represents 100 lines) - */ - psr_context->hyst_lines = stream->timing.v_total / 2 / 100; - psr_context->aux_repeats = 10; - - psr_context->psr_level.u32all = 0; - -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - /*skip power down the single pipe since it blocks the cstate*/ - if (ASIC_REV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev)) - psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; -#endif - - /* SMU will perform additional powerdown sequence. - * For unsupported ASICs, set psr_level flag to skip PSR - * static screen notification to SMU. - * (Always set for DAL2, did not check ASIC) - */ - psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION = 1; - - /* Complete PSR entry before aborting to prevent intermittent - * freezes on certain eDPs - */ - psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1; - - /* Controls additional delay after remote frame capture before - * continuing power down, default = 0 - */ - psr_context->frame_delay = 0; - - link->psr_enabled = true; - dmcu->funcs->setup_psr(dmcu, link, psr_context); - return true; - } else - return false; - -} - const struct dc_link_status *dc_link_get_status(const struct dc_link *link) { return &link->link_status; -- GitLab From ede569844a1b11b368a88269545a9d83cf98063c Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 10 Nov 2017 12:00:41 -0500 Subject: [PATCH 1468/2547] drm/amd/display: Remove plane_res.mi check in dce110_apply_ctx_for_surface plane_res.mi (memory interface) can never be NULL for DCE110 Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2881 dce110_apply_ctx_for_surface() error: we previously assumed 'pipe_ctx->plane_res.mi' could be null (see line 2873) Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index e650bdcd9423..da2e44058cc2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2872,13 +2872,12 @@ static void dce110_apply_ctx_for_surface( continue; /* Need to allocate mem before program front end for Fiji */ - if (pipe_ctx->plane_res.mi != NULL) - pipe_ctx->plane_res.mi->funcs->allocate_mem_input( - pipe_ctx->plane_res.mi, - pipe_ctx->stream->timing.h_total, - pipe_ctx->stream->timing.v_total, - pipe_ctx->stream->timing.pix_clk_khz, - context->stream_count); + pipe_ctx->plane_res.mi->funcs->allocate_mem_input( + pipe_ctx->plane_res.mi, + pipe_ctx->stream->timing.h_total, + pipe_ctx->stream->timing.v_total, + pipe_ctx->stream->timing.pix_clk_khz, + context->stream_count); dce110_program_front_end_for_pipe(dc, pipe_ctx); -- GitLab From 34996173c88ca69f276eb2979586016fbbaa34ca Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 10 Nov 2017 12:08:13 -0500 Subject: [PATCH 1469/2547] drm/amd/display: Remove redundant checks in set_default_colors pipe_ctx->stream and pipe_ctx->plane_state are never NULL Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2111 set_default_colors() error: we previously assumed 'pipe_ctx->stream' could be null (see line 2101) Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index da2e44058cc2..981bcd291602 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2095,16 +2095,8 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) struct default_adjustment default_adjust = { 0 }; default_adjust.force_hw_default = false; - if (pipe_ctx->plane_state == NULL) - default_adjust.in_color_space = COLOR_SPACE_SRGB; - else - default_adjust.in_color_space = - pipe_ctx->plane_state->color_space; - if (pipe_ctx->stream == NULL) - default_adjust.out_color_space = COLOR_SPACE_SRGB; - else - default_adjust.out_color_space = - pipe_ctx->stream->output_color_space; + default_adjust.in_color_space = pipe_ctx->plane_state->color_space; + default_adjust.out_color_space = pipe_ctx->stream->output_color_space; default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; -- GitLab From 52924dc3d0daf725a63f5c749cb263aad06f928a Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 10 Nov 2017 20:17:03 -0500 Subject: [PATCH 1470/2547] drm/amd/display: Fix potential mem leak in DC construct Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dc_ctx' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dc_vbios' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dcn_ip' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dcn_soc' Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 34 +++++++++++++----------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 18fc5e792d5c..98eff80acffa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -283,19 +283,17 @@ static bool construct(struct dc *dc, const struct dc_init_data *init_params) { struct dal_logger *logger; - struct dc_context *dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL); - struct bw_calcs_dceip *dc_dceip = kzalloc(sizeof(*dc_dceip), - GFP_KERNEL); - struct bw_calcs_vbios *dc_vbios = kzalloc(sizeof(*dc_vbios), - GFP_KERNEL); + struct dc_context *dc_ctx; + struct bw_calcs_dceip *dc_dceip; + struct bw_calcs_vbios *dc_vbios; #ifdef CONFIG_DRM_AMD_DC_DCN1_0 - struct dcn_soc_bounding_box *dcn_soc = kzalloc(sizeof(*dcn_soc), - GFP_KERNEL); - struct dcn_ip_params *dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL); + struct dcn_soc_bounding_box *dcn_soc; + struct dcn_ip_params *dcn_ip; #endif enum dce_version dc_version = DCE_VERSION_UNKNOWN; + dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL); if (!dc_dceip) { dm_error("%s: failed to create dceip\n", __func__); goto fail; @@ -303,6 +301,7 @@ static bool construct(struct dc *dc, dc->bw_dceip = dc_dceip; + dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL); if (!dc_vbios) { dm_error("%s: failed to create vbios\n", __func__); goto fail; @@ -310,6 +309,7 @@ static bool construct(struct dc *dc, dc->bw_vbios = dc_vbios; #ifdef CONFIG_DRM_AMD_DC_DCN1_0 + dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL); if (!dcn_soc) { dm_error("%s: failed to create dcn_soc\n", __func__); goto fail; @@ -317,6 +317,7 @@ static bool construct(struct dc *dc, dc->dcn_soc = dcn_soc; + dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL); if (!dcn_ip) { dm_error("%s: failed to create dcn_ip\n", __func__); goto fail; @@ -325,11 +326,18 @@ static bool construct(struct dc *dc, dc->dcn_ip = dcn_ip; #endif + dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL); if (!dc_ctx) { dm_error("%s: failed to create ctx\n", __func__); goto fail; } + dc_ctx->cgs_device = init_params->cgs_device; + dc_ctx->driver_context = init_params->driver; + dc_ctx->dc = dc; + dc_ctx->asic_id = init_params->asic_id; + dc->ctx = dc_ctx; + dc->current_state = dc_create_state(); if (!dc->current_state) { @@ -337,11 +345,6 @@ static bool construct(struct dc *dc, goto fail; } - dc_ctx->cgs_device = init_params->cgs_device; - dc_ctx->driver_context = init_params->driver; - dc_ctx->dc = dc; - dc_ctx->asic_id = init_params->asic_id; - /* Create logger */ logger = dal_logger_create(dc_ctx, init_params->log_mask); @@ -351,11 +354,10 @@ static bool construct(struct dc *dc, goto fail; } dc_ctx->logger = logger; - dc->ctx = dc_ctx; - dc->ctx->dce_environment = init_params->dce_environment; + dc_ctx->dce_environment = init_params->dce_environment; dc_version = resource_parse_asic_id(init_params->asic_id); - dc->ctx->dce_version = dc_version; + dc_ctx->dce_version = dc_version; #if defined(CONFIG_DRM_AMD_DC_FBC) dc->ctx->fbc_gpu_addr = init_params->fbc_gpu_addr; -- GitLab From c1fba8204b909d195f9dc4a638921260ac792124 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Thu, 16 Nov 2017 12:43:59 -0500 Subject: [PATCH 1471/2547] drm/amd/display: Fixed read wrong reg to get bot_sel. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index e926c29993f9..a13d25d1c568 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -372,7 +372,7 @@ void mpc1_init_mpcc_list_from_hw( for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) { REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); - REG_GET(MPCC_STATUS[mpcc_id], MPCC_BOT_SEL, &bot_sel); + REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); if ((opp_id == tree->opp_id) && (top_sel != 0xf)) { mpcc = mpc1_get_mpcc(mpc, mpcc_id); -- GitLab From 49fac0b46a689519c13efafba9e754525d420136 Mon Sep 17 00:00:00 2001 From: Eric Bernstein Date: Thu, 16 Nov 2017 14:29:10 -0500 Subject: [PATCH 1472/2547] drm/amd/display: MPC updates Fix update_mpcc logic to only call assert_mpcc_idle_before_connect if mpcc is not already being used (and required removal). Update set_out_rate_control to include optional flow control parameter. In init_mpcc_from_hw check for case where bot_sel is same as mpcc_id. Signed-off-by: Eric Bernstein Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 ++++---- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 5 ++++- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 3abd6d92aae0..14d1cffa84d9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1923,10 +1923,10 @@ static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) /* remove MPCC if being used */ if (new_mpcc != NULL) mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); - - if (dc->debug.sanity_checks) - mpc->funcs->assert_mpcc_idle_before_connect( - dc->res_pool->mpc, mpcc_id); + else + if (dc->debug.sanity_checks) + mpc->funcs->assert_mpcc_idle_before_connect( + dc->res_pool->mpc, mpcc_id); /* Call MPC to insert new plane */ new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index a13d25d1c568..d6606180b50a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -300,11 +300,11 @@ void mpc1_remove_mpcc( if (temp_mpcc && temp_mpcc->mpcc_bot == mpcc_to_remove) { found = true; + temp_mpcc->mpcc_bot = mpcc_to_remove->mpcc_bot; if (mpcc_to_remove->mpcc_bot) { /* remove MPCC in middle of list */ REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_to_remove->mpcc_bot->mpcc_id); - temp_mpcc->mpcc_bot = mpcc_to_remove->mpcc_bot; } else { /* remove MPCC from bottom of list */ REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, @@ -374,6 +374,9 @@ void mpc1_init_mpcc_list_from_hw( REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); + if (bot_sel == mpcc_id) + bot_sel = 0xf; + if ((opp_id == tree->opp_id) && (top_sel != 0xf)) { mpcc = mpc1_get_mpcc(mpc, mpcc_id); mpcc->dpp_id = top_sel; -- GitLab From c1cfd9025cc394fd137a01159d74335c5ac978ce Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Thu, 14 Dec 2017 16:44:12 +0100 Subject: [PATCH 1473/2547] ALSA: rawmidi: Avoid racy info ioctl via ctl device The rawmidi also allows to obtaining the information via ioctl of ctl API. It means that user can issue an ioctl to the rawmidi device even when it's being removed as long as the control device is present. Although the code has some protection via the global register_mutex, its range is limited to the search of the corresponding rawmidi object, and the mutex is already unlocked at accessing the rawmidi object. This may lead to a use-after-free. For avoiding it, this patch widens the application of register_mutex to the whole snd_rawmidi_info_select() function. We have another mutex per rawmidi object, but this operation isn't very hot path, so it shouldn't matter from the performance POV. Cc: Signed-off-by: Takashi Iwai --- sound/core/rawmidi.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/sound/core/rawmidi.c b/sound/core/rawmidi.c index b3b353d72527..f055ca10bbc1 100644 --- a/sound/core/rawmidi.c +++ b/sound/core/rawmidi.c @@ -579,15 +579,14 @@ static int snd_rawmidi_info_user(struct snd_rawmidi_substream *substream, return 0; } -int snd_rawmidi_info_select(struct snd_card *card, struct snd_rawmidi_info *info) +static int __snd_rawmidi_info_select(struct snd_card *card, + struct snd_rawmidi_info *info) { struct snd_rawmidi *rmidi; struct snd_rawmidi_str *pstr; struct snd_rawmidi_substream *substream; - mutex_lock(®ister_mutex); rmidi = snd_rawmidi_search(card, info->device); - mutex_unlock(®ister_mutex); if (!rmidi) return -ENXIO; if (info->stream < 0 || info->stream > 1) @@ -603,6 +602,16 @@ int snd_rawmidi_info_select(struct snd_card *card, struct snd_rawmidi_info *info } return -ENXIO; } + +int snd_rawmidi_info_select(struct snd_card *card, struct snd_rawmidi_info *info) +{ + int ret; + + mutex_lock(®ister_mutex); + ret = __snd_rawmidi_info_select(card, info); + mutex_unlock(®ister_mutex); + return ret; +} EXPORT_SYMBOL(snd_rawmidi_info_select); static int snd_rawmidi_info_select_user(struct snd_card *card, -- GitLab From 1ccda80ff4547dafd14ad20dd401d0aa08a9852a Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Wed, 15 Nov 2017 16:12:19 -0500 Subject: [PATCH 1474/2547] drm/amd/display: Use same wait mpcc idle function. There is already wait mpcc idle function. It is better to use the same function for all wait mpcc idle. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 27 +++++++++---------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 14d1cffa84d9..d41f571ad8b6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -592,19 +592,13 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) return; mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove); + dc->res_pool->opps[opp_id]->mpcc_disconnect_pending[fe_idx] = true; if (hubp->funcs->hubp_disconnect) hubp->funcs->hubp_disconnect(hubp); if (dc->debug.sanity_checks) dcn10_verify_allow_pstate_change_high(dc); - - pipe_ctx->stream = NULL; - memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); - memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); - pipe_ctx->top_pipe = NULL; - pipe_ctx->bottom_pipe = NULL; - pipe_ctx->plane_state = NULL; } static void plane_atomic_power_down(struct dc *dc, int fe_idx) @@ -633,16 +627,9 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) int fe_idx = pipe_ctx->pipe_idx; struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = dc->res_pool->hubps[fe_idx]; - struct mpc *mpc = dc->res_pool->mpc; int opp_id = hubp->opp_id; - struct output_pixel_processor *opp; - if (opp_id != 0xf) { - mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id); - opp = dc->res_pool->opps[hubp->opp_id]; - opp->mpcc_disconnect_pending[hubp->mpcc_id] = false; - hubp->funcs->set_blank(hubp, true); - } + dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); REG_UPDATE(HUBP_CLK_CNTL[fe_idx], HUBP_CLOCK_ENABLE, 0); @@ -656,6 +643,13 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) hubp->power_gated = true; plane_atomic_power_down(dc, fe_idx); + + pipe_ctx->stream = NULL; + memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); + memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); + pipe_ctx->top_pipe = NULL; + pipe_ctx->bottom_pipe = NULL; + pipe_ctx->plane_state = NULL; } static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) @@ -758,6 +752,9 @@ static void dcn10_init_hw(struct dc *dc) hubp->opp_id = dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i); hubp->power_gated = false; + if (hubp->opp_id != 0xf) + pipe_ctx->stream_res.opp = dc->res_pool->opps[hubp->opp_id]; + plane_atomic_disconnect(dc, pipe_ctx); } -- GitLab From 4010472575f48787085aa66279275255e7919078 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 22 Nov 2017 15:59:39 -0500 Subject: [PATCH 1475/2547] drm/amd/display: Add optimized_required flag Signed-off-by: Harry Wentland Reviewed-by: Leo (Sunpeng) Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++ drivers/gpu/drm/amd/display/dc/dc.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 98eff80acffa..19d96aeaa113 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -788,6 +788,8 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]); } + dc->optimized_required = false; + /* 3rd param should be true, temp w/a for RV*/ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) dc->hwss.set_bandwidth(dc, context, dc->ctx->dce_version < DCN_VERSION_1_0); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 71f1802a25d7..9fbcfd7b5f8d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -250,6 +250,8 @@ struct dc { */ struct dm_pp_display_configuration prev_display_config; + bool optimized_required; + /* FBC compressor */ #if defined(CONFIG_DRM_AMD_DC_FBC) struct compressor *fbc_compressor; -- GitLab From 82c026d14fd2b8b0a56168227c81386a3bc0e3e1 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Thu, 16 Nov 2017 15:51:21 -0500 Subject: [PATCH 1476/2547] drm/amd/display: Change optimized_required logic Rather than setting it every time there's a full update with surface count > 0, set it when we need to do plane_atomic_disconnect. Also make sure that we unset the flag in plane_atomic_disable, so that in the event we run through a sequence where we do disconnect followed by an immediate disable, we do not do unnecessarily request a passive flip to do the optimization. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index d41f571ad8b6..e08808b7e2d6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -594,6 +594,8 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove); dc->res_pool->opps[opp_id]->mpcc_disconnect_pending[fe_idx] = true; + dc->optimized_required = true; + if (hubp->funcs->hubp_disconnect) hubp->funcs->hubp_disconnect(hubp); @@ -641,6 +643,7 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) OPP_PIPE_CLOCK_EN, 0); hubp->power_gated = true; + dc->optimized_required = false; /* We're powering off, no need to optimize */ plane_atomic_power_down(dc, fe_idx); -- GitLab From 5cc2687c13eecd36a66e8e22948f281dbfc38970 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Wed, 15 Nov 2017 16:21:34 -0500 Subject: [PATCH 1477/2547] drm/amd/display: Implement work around for optc underflow. Work around for a hw bug causing optc underflow if blank data double buffer disable and remove mpcc. Checking optc status after otg unlock, after wait mpcc idle check status again, if optc underflow just happens after wait mpcc idle, clear underflow status and enable blank data double buffer. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 38 ++++++++++++++++++- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + .../display/dc/dcn10/dcn10_timing_generator.c | 31 ++++++++++----- .../amd/display/dc/inc/hw/timing_generator.h | 2 + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 + 5 files changed, 62 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e08808b7e2d6..8e2520ba6bed 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -425,6 +425,34 @@ static void bios_golden_init(struct dc *dc) } } +static void false_optc_underflow_wa( + struct dc *dc, + const struct dc_stream_state *stream, + struct timing_generator *tg) +{ + int i; + bool underflow; + + if (!dc->hwseq->wa.false_optc_underflow) + return; + + underflow = tg->funcs->is_optc_underflow_occurred(tg); + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (old_pipe_ctx->stream != stream) + continue; + + dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx); + } + + tg->funcs->set_blank_data_double_buffer(tg, true); + + if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow) + tg->funcs->clear_optc_underflow(tg); +} + static enum dc_status dcn10_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, struct dc_state *context, @@ -493,8 +521,11 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( pipe_ctx->stream_res.tg, &black_color); - pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); - hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg); + if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) { + pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); + hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg); + false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg); + } /* VTG is within DCHUB command block. DCFCLK is always on */ if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { @@ -2252,6 +2283,9 @@ static void dcn10_apply_ctx_for_surface( tg->funcs->unlock(tg); + if (num_planes == 0) + false_optc_underflow_wa(dc, stream, tg); + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 10cce51d31d2..a9a5d176cb70 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -678,6 +678,7 @@ static struct dce_hwseq *dcn10_hwseq_create( hws->shifts = &hwseq_shift; hws->masks = &hwseq_mask; hws->wa.DEGVIDCN10_253 = true; + hws->wa.false_optc_underflow = true; } return hws; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index 73ff78f9cae1..4940fdbc6e80 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -336,13 +336,6 @@ static void tgn10_blank_crtc(struct timing_generator *tg) OTG_BLANK_DATA_EN, 1, OTG_BLANK_DE_MODE, 0); - /* todo: why are we waiting for BLANK_DATA_EN? shouldn't we be waiting - * for status? - */ - REG_WAIT(OTG_BLANK_CONTROL, - OTG_BLANK_DATA_EN, 1, - 1, 100000); - tgn10_set_blank_data_double_buffer(tg, false); } @@ -1199,14 +1192,19 @@ void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); } -static void tgn10_tg_init(struct timing_generator *tg) +static void tgn10_clear_optc_underflow(struct timing_generator *tg) { struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); - tgn10_set_blank_data_double_buffer(tg, true); REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); } +static void tgn10_tg_init(struct timing_generator *tg) +{ + tgn10_set_blank_data_double_buffer(tg, true); + tgn10_clear_optc_underflow(tg); +} + static bool tgn10_is_tg_enabled(struct timing_generator *tg) { struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); @@ -1217,6 +1215,19 @@ static bool tgn10_is_tg_enabled(struct timing_generator *tg) return (otg_enabled != 0); } + +static bool tgn10_is_optc_underflow_occurred(struct timing_generator *tg) +{ + struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + uint32_t underflow_occurred = 0; + + REG_GET(OPTC_INPUT_GLOBAL_CONTROL, + OPTC_UNDERFLOW_OCCURRED_STATUS, + &underflow_occurred); + + return (underflow_occurred == 1); +} + static const struct timing_generator_funcs dcn10_tg_funcs = { .validate_timing = tgn10_validate_timing, .program_timing = tgn10_program_timing, @@ -1249,6 +1260,8 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { .set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer, .tg_init = tgn10_tg_init, .is_tg_enabled = tgn10_is_tg_enabled, + .is_optc_underflow_occurred = tgn10_is_optc_underflow_occurred, + .clear_optc_underflow = tgn10_clear_optc_underflow, }; void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 860259913d78..e5c7e0e1db14 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -187,6 +187,8 @@ struct timing_generator_funcs { void (*tg_init)(struct timing_generator *tg); bool (*is_tg_enabled)(struct timing_generator *tg); + bool (*is_optc_underflow_occurred)(struct timing_generator *tg); + void (*clear_optc_underflow)(struct timing_generator *tg); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 5dc4ecf618ff..03431134c088 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -40,6 +40,7 @@ enum pipe_gating_control { struct dce_hwseq_wa { bool blnd_crtc_trigger; bool DEGVIDCN10_253; + bool false_optc_underflow; }; struct hwseq_wa_state { -- GitLab From e9dd9223c6d633a33fd2125ed1b1ec9d5bcbb5a7 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Thu, 16 Nov 2017 17:08:44 -0500 Subject: [PATCH 1478/2547] drm/amd/display: Add dcc_change surface update flag Program the DCC registers when dcc_change is true. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++++ drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 + 3 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 19d96aeaa113..ab875ea8aba4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -985,6 +985,11 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) update_flags->bits.per_pixel_alpha_change = 1; + if (u->plane_info->dcc.enable != u->surface->dcc.enable + || u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks + || u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch) + update_flags->bits.dcc_change = 1; + if (pixel_format_to_bpp(u->plane_info->format) != pixel_format_to_bpp(u->surface->format)) /* different bytes per element will require full bandwidth diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9fbcfd7b5f8d..597bd8b4cb1e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -387,6 +387,7 @@ union surface_update_flags { struct { /* Medium updates */ + uint32_t dcc_change:1; uint32_t color_space_change:1; uint32_t input_tf_change:1; uint32_t horizontal_mirror_change:1; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 8e2520ba6bed..1ebe980bfb6d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2066,6 +2066,7 @@ static void update_dchubp_dpp( plane_state->update_flags.bits.horizontal_mirror_change || plane_state->update_flags.bits.rotation_change || plane_state->update_flags.bits.swizzle_change || + plane_state->update_flags.bits.dcc_change || plane_state->update_flags.bits.bpp_change) { hubp->funcs->hubp_program_surface_config( hubp, -- GitLab From 77bb51eba9cf148965a9dad9dcad7b7c736039bf Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Thu, 16 Nov 2017 18:03:52 -0500 Subject: [PATCH 1479/2547] drm/amd/display: dal 3.1.22 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 597bd8b4cb1e..96559925bea7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.21" +#define DC_VER "3.1.22" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From 4d06ccd0af1ea5f3a3b74ca421b9cd9840d5e5c6 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 10 Nov 2017 12:12:40 -0500 Subject: [PATCH 1480/2547] drm/amd/display: Fix access of wrong array element TF format conversion Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:357 convert_to_custom_float() error: buffer overflow 'arr_points' 2 <= 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:358 convert_to_custom_float() warn: buffer overflow 'arr_points' 2 <= 2 Regression: drm/amd/display: Remove extra arr_points element Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 981bcd291602..21fc27aab909 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -354,8 +354,8 @@ static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, return false; } - if (!convert_to_custom_float_format(arr_points[2].slope, &fmt, - &arr_points[2].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, + &arr_points[1].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } -- GitLab From 963aa22dc983f11d19f0e106ee7d9fddb229abda Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 15 Nov 2017 19:27:37 -0500 Subject: [PATCH 1481/2547] drm/amd/display: Clean up os_types.h a bit Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/os_types.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h index a87c0329541f..68ce2ab8f455 100644 --- a/drivers/gpu/drm/amd/display/dc/os_types.h +++ b/drivers/gpu/drm/amd/display/dc/os_types.h @@ -26,8 +26,6 @@ #ifndef _OS_TYPES_H_ #define _OS_TYPES_H_ -#if defined __KERNEL__ - #include #include #include @@ -54,6 +52,8 @@ #define dm_vlog(fmt, args) vprintk(fmt, args) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include #endif /* @@ -89,8 +89,4 @@ BREAK_TO_DEBUGGER(); \ } while (0) -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) -#include -#endif - #endif /* _OS_TYPES_H_ */ -- GitLab From 9168a586e865083646e737a19ab38db8f1dcff3e Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Thu, 16 Nov 2017 23:37:10 -0500 Subject: [PATCH 1482/2547] drm/amd/display: dal 3.1.23 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 96559925bea7..f785d4a679df 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.22" +#define DC_VER "3.1.23" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From 8e504bccc11663c3b334ef1a7698e18a967de920 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Fri, 17 Nov 2017 10:44:15 -0500 Subject: [PATCH 1483/2547] drm/amd/display: Disable plane right after disconnected HDR display playing video underflow is observed when switching to full screen due to program a lower watermark right after unlock otg. Instead of disable plane in next flip coming, if there is a plane disconnected, after otg unlock wait for mpcc idle and disable the plane, then program watermark. So there is enough warter mark to make sure current frame data pass through. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 1ebe980bfb6d..d542e4db5495 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2297,7 +2297,7 @@ static void dcn10_apply_ctx_for_surface( pipe_ctx->plane_state->update_flags.bits.full_update) program_water_mark = true; - if (removed_pipe[i] && num_planes == 0) + if (removed_pipe[i]) dcn10_disable_plane(dc, old_pipe_ctx); } @@ -2306,6 +2306,7 @@ static void dcn10_apply_ctx_for_surface( /* pstate stuck check after watermark update */ dcn10_verify_allow_pstate_change_high(dc); } + /* watermark is for all pipes */ hubbub1_program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, ref_clk_mhz); -- GitLab From 9a0beb3944f28d9d3d1864ca2145a940bc829295 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Tue, 14 Nov 2017 12:13:27 -0500 Subject: [PATCH 1484/2547] drm/amd/display: CNVC pseudocode review follow up Signed-off-by: Yue Hin Lau Reviewed-by: Eric Bernstein Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/core/dc_stream.c | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 3 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 484 +++++++++--------- drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 2 +- 4 files changed, 244 insertions(+), 247 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 375fb457e223..e39568b4460c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -226,7 +226,7 @@ bool dc_stream_set_cursor_attributes( if (pipe_ctx->plane_res.dpp != NULL && pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes != NULL) pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes( - pipe_ctx->plane_res.dpp, attributes); + pipe_ctx->plane_res.dpp, attributes->color_format); } stream->cursor_attributes = *attributes; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 8df3945370cf..5a95fa03bc17 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -386,10 +386,9 @@ void dpp1_cnv_setup ( void dpp1_set_cursor_attributes( struct dpp *dpp_base, - const struct dc_cursor_attributes *attr) + enum dc_cursor_color_format color_format) { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); - enum dc_cursor_color_format color_format = attr->color_format; REG_UPDATE_2(CURSOR0_CONTROL, CUR0_MODE, color_format, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index ad71fb50f8a5..41f0c84bfa09 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -1005,258 +1005,256 @@ type CM_BYPASS; \ type FORMAT_CONTROL__ALPHA_EN; \ type CUR0_COLOR0; \ - type CUR0_COLOR1 - - + type CUR0_COLOR1; struct dcn_dpp_shift { - TF_REG_FIELD_LIST(uint8_t); + TF_REG_FIELD_LIST(uint8_t) }; struct dcn_dpp_mask { - TF_REG_FIELD_LIST(uint32_t); + TF_REG_FIELD_LIST(uint32_t) }; - - +#define DPP_COMMON_REG_VARIABLE_LIST \ + uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT; \ + uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; \ + uint32_t OTG_H_BLANK; \ + uint32_t OTG_V_BLANK; \ + uint32_t SCL_MODE; \ + uint32_t LB_DATA_FORMAT; \ + uint32_t LB_MEMORY_CTRL; \ + uint32_t DSCL_AUTOCAL; \ + uint32_t SCL_BLACK_OFFSET; \ + uint32_t SCL_TAP_CONTROL; \ + uint32_t SCL_COEF_RAM_TAP_SELECT; \ + uint32_t SCL_COEF_RAM_TAP_DATA; \ + uint32_t DSCL_2TAP_CONTROL; \ + uint32_t MPC_SIZE; \ + uint32_t SCL_HORZ_FILTER_SCALE_RATIO; \ + uint32_t SCL_VERT_FILTER_SCALE_RATIO; \ + uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C; \ + uint32_t SCL_VERT_FILTER_SCALE_RATIO_C; \ + uint32_t SCL_HORZ_FILTER_INIT; \ + uint32_t SCL_HORZ_FILTER_INIT_C; \ + uint32_t SCL_VERT_FILTER_INIT; \ + uint32_t SCL_VERT_FILTER_INIT_BOT; \ + uint32_t SCL_VERT_FILTER_INIT_C; \ + uint32_t SCL_VERT_FILTER_INIT_BOT_C; \ + uint32_t RECOUT_START; \ + uint32_t RECOUT_SIZE; \ + uint32_t CM_GAMUT_REMAP_CONTROL; \ + uint32_t CM_GAMUT_REMAP_C11_C12; \ + uint32_t CM_GAMUT_REMAP_C33_C34; \ + uint32_t CM_COMA_C11_C12; \ + uint32_t CM_COMA_C33_C34; \ + uint32_t CM_COMB_C11_C12; \ + uint32_t CM_COMB_C33_C34; \ + uint32_t CM_OCSC_CONTROL; \ + uint32_t CM_OCSC_C11_C12; \ + uint32_t CM_OCSC_C33_C34; \ + uint32_t CM_MEM_PWR_CTRL; \ + uint32_t CM_RGAM_LUT_DATA; \ + uint32_t CM_RGAM_LUT_WRITE_EN_MASK; \ + uint32_t CM_RGAM_LUT_INDEX; \ + uint32_t CM_RGAM_RAMB_START_CNTL_B; \ + uint32_t CM_RGAM_RAMB_START_CNTL_G; \ + uint32_t CM_RGAM_RAMB_START_CNTL_R; \ + uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; \ + uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; \ + uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; \ + uint32_t CM_RGAM_RAMB_END_CNTL1_B; \ + uint32_t CM_RGAM_RAMB_END_CNTL2_B; \ + uint32_t CM_RGAM_RAMB_END_CNTL1_G; \ + uint32_t CM_RGAM_RAMB_END_CNTL2_G; \ + uint32_t CM_RGAM_RAMB_END_CNTL1_R; \ + uint32_t CM_RGAM_RAMB_END_CNTL2_R; \ + uint32_t CM_RGAM_RAMB_REGION_0_1; \ + uint32_t CM_RGAM_RAMB_REGION_32_33; \ + uint32_t CM_RGAM_RAMA_START_CNTL_B; \ + uint32_t CM_RGAM_RAMA_START_CNTL_G; \ + uint32_t CM_RGAM_RAMA_START_CNTL_R; \ + uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; \ + uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; \ + uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; \ + uint32_t CM_RGAM_RAMA_END_CNTL1_B; \ + uint32_t CM_RGAM_RAMA_END_CNTL2_B; \ + uint32_t CM_RGAM_RAMA_END_CNTL1_G; \ + uint32_t CM_RGAM_RAMA_END_CNTL2_G; \ + uint32_t CM_RGAM_RAMA_END_CNTL1_R; \ + uint32_t CM_RGAM_RAMA_END_CNTL2_R; \ + uint32_t CM_RGAM_RAMA_REGION_0_1; \ + uint32_t CM_RGAM_RAMA_REGION_32_33; \ + uint32_t CM_RGAM_CONTROL; \ + uint32_t CM_CMOUT_CONTROL; \ + uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; \ + uint32_t CM_BLNDGAM_CONTROL; \ + uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; \ + uint32_t CM_BLNDGAM_RAMB_START_CNTL_G; \ + uint32_t CM_BLNDGAM_RAMB_START_CNTL_R; \ + uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B; \ + uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G; \ + uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R; \ + uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B; \ + uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B; \ + uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G; \ + uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G; \ + uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R; \ + uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R; \ + uint32_t CM_BLNDGAM_RAMB_REGION_0_1; \ + uint32_t CM_BLNDGAM_RAMB_REGION_2_3; \ + uint32_t CM_BLNDGAM_RAMB_REGION_4_5; \ + uint32_t CM_BLNDGAM_RAMB_REGION_6_7; \ + uint32_t CM_BLNDGAM_RAMB_REGION_8_9; \ + uint32_t CM_BLNDGAM_RAMB_REGION_10_11; \ + uint32_t CM_BLNDGAM_RAMB_REGION_12_13; \ + uint32_t CM_BLNDGAM_RAMB_REGION_14_15; \ + uint32_t CM_BLNDGAM_RAMB_REGION_16_17; \ + uint32_t CM_BLNDGAM_RAMB_REGION_18_19; \ + uint32_t CM_BLNDGAM_RAMB_REGION_20_21; \ + uint32_t CM_BLNDGAM_RAMB_REGION_22_23; \ + uint32_t CM_BLNDGAM_RAMB_REGION_24_25; \ + uint32_t CM_BLNDGAM_RAMB_REGION_26_27; \ + uint32_t CM_BLNDGAM_RAMB_REGION_28_29; \ + uint32_t CM_BLNDGAM_RAMB_REGION_30_31; \ + uint32_t CM_BLNDGAM_RAMB_REGION_32_33; \ + uint32_t CM_BLNDGAM_RAMA_START_CNTL_B; \ + uint32_t CM_BLNDGAM_RAMA_START_CNTL_G; \ + uint32_t CM_BLNDGAM_RAMA_START_CNTL_R; \ + uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B; \ + uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G; \ + uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R; \ + uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B; \ + uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B; \ + uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G; \ + uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G; \ + uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R; \ + uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R; \ + uint32_t CM_BLNDGAM_RAMA_REGION_0_1; \ + uint32_t CM_BLNDGAM_RAMA_REGION_2_3; \ + uint32_t CM_BLNDGAM_RAMA_REGION_4_5; \ + uint32_t CM_BLNDGAM_RAMA_REGION_6_7; \ + uint32_t CM_BLNDGAM_RAMA_REGION_8_9; \ + uint32_t CM_BLNDGAM_RAMA_REGION_10_11; \ + uint32_t CM_BLNDGAM_RAMA_REGION_12_13; \ + uint32_t CM_BLNDGAM_RAMA_REGION_14_15; \ + uint32_t CM_BLNDGAM_RAMA_REGION_16_17; \ + uint32_t CM_BLNDGAM_RAMA_REGION_18_19; \ + uint32_t CM_BLNDGAM_RAMA_REGION_20_21; \ + uint32_t CM_BLNDGAM_RAMA_REGION_22_23; \ + uint32_t CM_BLNDGAM_RAMA_REGION_24_25; \ + uint32_t CM_BLNDGAM_RAMA_REGION_26_27; \ + uint32_t CM_BLNDGAM_RAMA_REGION_28_29; \ + uint32_t CM_BLNDGAM_RAMA_REGION_30_31; \ + uint32_t CM_BLNDGAM_RAMA_REGION_32_33; \ + uint32_t CM_BLNDGAM_LUT_INDEX; \ + uint32_t CM_BLNDGAM_LUT_DATA; \ + uint32_t CM_3DLUT_MODE; \ + uint32_t CM_3DLUT_INDEX; \ + uint32_t CM_3DLUT_DATA; \ + uint32_t CM_3DLUT_DATA_30BIT; \ + uint32_t CM_3DLUT_READ_WRITE_CONTROL; \ + uint32_t CM_SHAPER_LUT_WRITE_EN_MASK; \ + uint32_t CM_SHAPER_CONTROL; \ + uint32_t CM_SHAPER_RAMB_START_CNTL_B; \ + uint32_t CM_SHAPER_RAMB_START_CNTL_G; \ + uint32_t CM_SHAPER_RAMB_START_CNTL_R; \ + uint32_t CM_SHAPER_RAMB_END_CNTL_B; \ + uint32_t CM_SHAPER_RAMB_END_CNTL_G; \ + uint32_t CM_SHAPER_RAMB_END_CNTL_R; \ + uint32_t CM_SHAPER_RAMB_REGION_0_1; \ + uint32_t CM_SHAPER_RAMB_REGION_2_3; \ + uint32_t CM_SHAPER_RAMB_REGION_4_5; \ + uint32_t CM_SHAPER_RAMB_REGION_6_7; \ + uint32_t CM_SHAPER_RAMB_REGION_8_9; \ + uint32_t CM_SHAPER_RAMB_REGION_10_11; \ + uint32_t CM_SHAPER_RAMB_REGION_12_13; \ + uint32_t CM_SHAPER_RAMB_REGION_14_15; \ + uint32_t CM_SHAPER_RAMB_REGION_16_17; \ + uint32_t CM_SHAPER_RAMB_REGION_18_19; \ + uint32_t CM_SHAPER_RAMB_REGION_20_21; \ + uint32_t CM_SHAPER_RAMB_REGION_22_23; \ + uint32_t CM_SHAPER_RAMB_REGION_24_25; \ + uint32_t CM_SHAPER_RAMB_REGION_26_27; \ + uint32_t CM_SHAPER_RAMB_REGION_28_29; \ + uint32_t CM_SHAPER_RAMB_REGION_30_31; \ + uint32_t CM_SHAPER_RAMB_REGION_32_33; \ + uint32_t CM_SHAPER_RAMA_START_CNTL_B; \ + uint32_t CM_SHAPER_RAMA_START_CNTL_G; \ + uint32_t CM_SHAPER_RAMA_START_CNTL_R; \ + uint32_t CM_SHAPER_RAMA_END_CNTL_B; \ + uint32_t CM_SHAPER_RAMA_END_CNTL_G; \ + uint32_t CM_SHAPER_RAMA_END_CNTL_R; \ + uint32_t CM_SHAPER_RAMA_REGION_0_1; \ + uint32_t CM_SHAPER_RAMA_REGION_2_3; \ + uint32_t CM_SHAPER_RAMA_REGION_4_5; \ + uint32_t CM_SHAPER_RAMA_REGION_6_7; \ + uint32_t CM_SHAPER_RAMA_REGION_8_9; \ + uint32_t CM_SHAPER_RAMA_REGION_10_11; \ + uint32_t CM_SHAPER_RAMA_REGION_12_13; \ + uint32_t CM_SHAPER_RAMA_REGION_14_15; \ + uint32_t CM_SHAPER_RAMA_REGION_16_17; \ + uint32_t CM_SHAPER_RAMA_REGION_18_19; \ + uint32_t CM_SHAPER_RAMA_REGION_20_21; \ + uint32_t CM_SHAPER_RAMA_REGION_22_23; \ + uint32_t CM_SHAPER_RAMA_REGION_24_25; \ + uint32_t CM_SHAPER_RAMA_REGION_26_27; \ + uint32_t CM_SHAPER_RAMA_REGION_28_29; \ + uint32_t CM_SHAPER_RAMA_REGION_30_31; \ + uint32_t CM_SHAPER_RAMA_REGION_32_33; \ + uint32_t CM_SHAPER_LUT_INDEX; \ + uint32_t CM_SHAPER_LUT_DATA; \ + uint32_t CM_ICSC_CONTROL; \ + uint32_t CM_ICSC_C11_C12; \ + uint32_t CM_ICSC_C33_C34; \ + uint32_t CM_BNS_VALUES_R; \ + uint32_t CM_BNS_VALUES_G; \ + uint32_t CM_BNS_VALUES_B; \ + uint32_t CM_DGAM_RAMB_START_CNTL_B; \ + uint32_t CM_DGAM_RAMB_START_CNTL_G; \ + uint32_t CM_DGAM_RAMB_START_CNTL_R; \ + uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; \ + uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; \ + uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; \ + uint32_t CM_DGAM_RAMB_END_CNTL1_B; \ + uint32_t CM_DGAM_RAMB_END_CNTL2_B; \ + uint32_t CM_DGAM_RAMB_END_CNTL1_G; \ + uint32_t CM_DGAM_RAMB_END_CNTL2_G; \ + uint32_t CM_DGAM_RAMB_END_CNTL1_R; \ + uint32_t CM_DGAM_RAMB_END_CNTL2_R; \ + uint32_t CM_DGAM_RAMB_REGION_0_1; \ + uint32_t CM_DGAM_RAMB_REGION_14_15; \ + uint32_t CM_DGAM_RAMA_START_CNTL_B; \ + uint32_t CM_DGAM_RAMA_START_CNTL_G; \ + uint32_t CM_DGAM_RAMA_START_CNTL_R; \ + uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; \ + uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; \ + uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; \ + uint32_t CM_DGAM_RAMA_END_CNTL1_B; \ + uint32_t CM_DGAM_RAMA_END_CNTL2_B; \ + uint32_t CM_DGAM_RAMA_END_CNTL1_G; \ + uint32_t CM_DGAM_RAMA_END_CNTL2_G; \ + uint32_t CM_DGAM_RAMA_END_CNTL1_R; \ + uint32_t CM_DGAM_RAMA_END_CNTL2_R; \ + uint32_t CM_DGAM_RAMA_REGION_0_1; \ + uint32_t CM_DGAM_RAMA_REGION_14_15; \ + uint32_t CM_DGAM_LUT_WRITE_EN_MASK; \ + uint32_t CM_DGAM_LUT_INDEX; \ + uint32_t CM_DGAM_LUT_DATA; \ + uint32_t CM_CONTROL; \ + uint32_t CM_DGAM_CONTROL; \ + uint32_t CM_IGAM_CONTROL; \ + uint32_t CM_IGAM_LUT_RW_CONTROL; \ + uint32_t CM_IGAM_LUT_RW_INDEX; \ + uint32_t CM_IGAM_LUT_SEQ_COLOR; \ + uint32_t FORMAT_CONTROL; \ + uint32_t CNVC_SURFACE_PIXEL_FORMAT; \ + uint32_t CURSOR_CONTROL; \ + uint32_t CURSOR0_CONTROL; \ + uint32_t CURSOR0_COLOR0; \ + uint32_t CURSOR0_COLOR1; struct dcn_dpp_registers { - uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT; - uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; - uint32_t OTG_H_BLANK; - uint32_t OTG_V_BLANK; - uint32_t SCL_MODE; - uint32_t LB_DATA_FORMAT; - uint32_t LB_MEMORY_CTRL; - uint32_t DSCL_AUTOCAL; - uint32_t SCL_BLACK_OFFSET; - uint32_t SCL_TAP_CONTROL; - uint32_t SCL_COEF_RAM_TAP_SELECT; - uint32_t SCL_COEF_RAM_TAP_DATA; - uint32_t DSCL_2TAP_CONTROL; - uint32_t MPC_SIZE; - uint32_t SCL_HORZ_FILTER_SCALE_RATIO; - uint32_t SCL_VERT_FILTER_SCALE_RATIO; - uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C; - uint32_t SCL_VERT_FILTER_SCALE_RATIO_C; - uint32_t SCL_HORZ_FILTER_INIT; - uint32_t SCL_HORZ_FILTER_INIT_C; - uint32_t SCL_VERT_FILTER_INIT; - uint32_t SCL_VERT_FILTER_INIT_BOT; - uint32_t SCL_VERT_FILTER_INIT_C; - uint32_t SCL_VERT_FILTER_INIT_BOT_C; - uint32_t RECOUT_START; - uint32_t RECOUT_SIZE; - uint32_t CM_GAMUT_REMAP_CONTROL; - uint32_t CM_GAMUT_REMAP_C11_C12; - uint32_t CM_GAMUT_REMAP_C33_C34; - uint32_t CM_COMA_C11_C12; - uint32_t CM_COMA_C33_C34; - uint32_t CM_COMB_C11_C12; - uint32_t CM_COMB_C33_C34; - uint32_t CM_OCSC_CONTROL; - uint32_t CM_OCSC_C11_C12; - uint32_t CM_OCSC_C33_C34; - uint32_t CM_MEM_PWR_CTRL; - uint32_t CM_RGAM_LUT_DATA; - uint32_t CM_RGAM_LUT_WRITE_EN_MASK; - uint32_t CM_RGAM_LUT_INDEX; - uint32_t CM_RGAM_RAMB_START_CNTL_B; - uint32_t CM_RGAM_RAMB_START_CNTL_G; - uint32_t CM_RGAM_RAMB_START_CNTL_R; - uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; - uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; - uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; - uint32_t CM_RGAM_RAMB_END_CNTL1_B; - uint32_t CM_RGAM_RAMB_END_CNTL2_B; - uint32_t CM_RGAM_RAMB_END_CNTL1_G; - uint32_t CM_RGAM_RAMB_END_CNTL2_G; - uint32_t CM_RGAM_RAMB_END_CNTL1_R; - uint32_t CM_RGAM_RAMB_END_CNTL2_R; - uint32_t CM_RGAM_RAMB_REGION_0_1; - uint32_t CM_RGAM_RAMB_REGION_32_33; - uint32_t CM_RGAM_RAMA_START_CNTL_B; - uint32_t CM_RGAM_RAMA_START_CNTL_G; - uint32_t CM_RGAM_RAMA_START_CNTL_R; - uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; - uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; - uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; - uint32_t CM_RGAM_RAMA_END_CNTL1_B; - uint32_t CM_RGAM_RAMA_END_CNTL2_B; - uint32_t CM_RGAM_RAMA_END_CNTL1_G; - uint32_t CM_RGAM_RAMA_END_CNTL2_G; - uint32_t CM_RGAM_RAMA_END_CNTL1_R; - uint32_t CM_RGAM_RAMA_END_CNTL2_R; - uint32_t CM_RGAM_RAMA_REGION_0_1; - uint32_t CM_RGAM_RAMA_REGION_32_33; - uint32_t CM_RGAM_CONTROL; - uint32_t CM_CMOUT_CONTROL; - uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; - uint32_t CM_BLNDGAM_CONTROL; - uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; - uint32_t CM_BLNDGAM_RAMB_START_CNTL_G; - uint32_t CM_BLNDGAM_RAMB_START_CNTL_R; - uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B; - uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G; - uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R; - uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B; - uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B; - uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G; - uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G; - uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R; - uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R; - uint32_t CM_BLNDGAM_RAMB_REGION_0_1; - uint32_t CM_BLNDGAM_RAMB_REGION_2_3; - uint32_t CM_BLNDGAM_RAMB_REGION_4_5; - uint32_t CM_BLNDGAM_RAMB_REGION_6_7; - uint32_t CM_BLNDGAM_RAMB_REGION_8_9; - uint32_t CM_BLNDGAM_RAMB_REGION_10_11; - uint32_t CM_BLNDGAM_RAMB_REGION_12_13; - uint32_t CM_BLNDGAM_RAMB_REGION_14_15; - uint32_t CM_BLNDGAM_RAMB_REGION_16_17; - uint32_t CM_BLNDGAM_RAMB_REGION_18_19; - uint32_t CM_BLNDGAM_RAMB_REGION_20_21; - uint32_t CM_BLNDGAM_RAMB_REGION_22_23; - uint32_t CM_BLNDGAM_RAMB_REGION_24_25; - uint32_t CM_BLNDGAM_RAMB_REGION_26_27; - uint32_t CM_BLNDGAM_RAMB_REGION_28_29; - uint32_t CM_BLNDGAM_RAMB_REGION_30_31; - uint32_t CM_BLNDGAM_RAMB_REGION_32_33; - uint32_t CM_BLNDGAM_RAMA_START_CNTL_B; - uint32_t CM_BLNDGAM_RAMA_START_CNTL_G; - uint32_t CM_BLNDGAM_RAMA_START_CNTL_R; - uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B; - uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G; - uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R; - uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B; - uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B; - uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G; - uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G; - uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R; - uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R; - uint32_t CM_BLNDGAM_RAMA_REGION_0_1; - uint32_t CM_BLNDGAM_RAMA_REGION_2_3; - uint32_t CM_BLNDGAM_RAMA_REGION_4_5; - uint32_t CM_BLNDGAM_RAMA_REGION_6_7; - uint32_t CM_BLNDGAM_RAMA_REGION_8_9; - uint32_t CM_BLNDGAM_RAMA_REGION_10_11; - uint32_t CM_BLNDGAM_RAMA_REGION_12_13; - uint32_t CM_BLNDGAM_RAMA_REGION_14_15; - uint32_t CM_BLNDGAM_RAMA_REGION_16_17; - uint32_t CM_BLNDGAM_RAMA_REGION_18_19; - uint32_t CM_BLNDGAM_RAMA_REGION_20_21; - uint32_t CM_BLNDGAM_RAMA_REGION_22_23; - uint32_t CM_BLNDGAM_RAMA_REGION_24_25; - uint32_t CM_BLNDGAM_RAMA_REGION_26_27; - uint32_t CM_BLNDGAM_RAMA_REGION_28_29; - uint32_t CM_BLNDGAM_RAMA_REGION_30_31; - uint32_t CM_BLNDGAM_RAMA_REGION_32_33; - uint32_t CM_BLNDGAM_LUT_INDEX; - uint32_t CM_BLNDGAM_LUT_DATA; - uint32_t CM_3DLUT_MODE; - uint32_t CM_3DLUT_INDEX; - uint32_t CM_3DLUT_DATA; - uint32_t CM_3DLUT_DATA_30BIT; - uint32_t CM_3DLUT_READ_WRITE_CONTROL; - uint32_t CM_SHAPER_LUT_WRITE_EN_MASK; - uint32_t CM_SHAPER_CONTROL; - uint32_t CM_SHAPER_RAMB_START_CNTL_B; - uint32_t CM_SHAPER_RAMB_START_CNTL_G; - uint32_t CM_SHAPER_RAMB_START_CNTL_R; - uint32_t CM_SHAPER_RAMB_END_CNTL_B; - uint32_t CM_SHAPER_RAMB_END_CNTL_G; - uint32_t CM_SHAPER_RAMB_END_CNTL_R; - uint32_t CM_SHAPER_RAMB_REGION_0_1; - uint32_t CM_SHAPER_RAMB_REGION_2_3; - uint32_t CM_SHAPER_RAMB_REGION_4_5; - uint32_t CM_SHAPER_RAMB_REGION_6_7; - uint32_t CM_SHAPER_RAMB_REGION_8_9; - uint32_t CM_SHAPER_RAMB_REGION_10_11; - uint32_t CM_SHAPER_RAMB_REGION_12_13; - uint32_t CM_SHAPER_RAMB_REGION_14_15; - uint32_t CM_SHAPER_RAMB_REGION_16_17; - uint32_t CM_SHAPER_RAMB_REGION_18_19; - uint32_t CM_SHAPER_RAMB_REGION_20_21; - uint32_t CM_SHAPER_RAMB_REGION_22_23; - uint32_t CM_SHAPER_RAMB_REGION_24_25; - uint32_t CM_SHAPER_RAMB_REGION_26_27; - uint32_t CM_SHAPER_RAMB_REGION_28_29; - uint32_t CM_SHAPER_RAMB_REGION_30_31; - uint32_t CM_SHAPER_RAMB_REGION_32_33; - uint32_t CM_SHAPER_RAMA_START_CNTL_B; - uint32_t CM_SHAPER_RAMA_START_CNTL_G; - uint32_t CM_SHAPER_RAMA_START_CNTL_R; - uint32_t CM_SHAPER_RAMA_END_CNTL_B; - uint32_t CM_SHAPER_RAMA_END_CNTL_G; - uint32_t CM_SHAPER_RAMA_END_CNTL_R; - uint32_t CM_SHAPER_RAMA_REGION_0_1; - uint32_t CM_SHAPER_RAMA_REGION_2_3; - uint32_t CM_SHAPER_RAMA_REGION_4_5; - uint32_t CM_SHAPER_RAMA_REGION_6_7; - uint32_t CM_SHAPER_RAMA_REGION_8_9; - uint32_t CM_SHAPER_RAMA_REGION_10_11; - uint32_t CM_SHAPER_RAMA_REGION_12_13; - uint32_t CM_SHAPER_RAMA_REGION_14_15; - uint32_t CM_SHAPER_RAMA_REGION_16_17; - uint32_t CM_SHAPER_RAMA_REGION_18_19; - uint32_t CM_SHAPER_RAMA_REGION_20_21; - uint32_t CM_SHAPER_RAMA_REGION_22_23; - uint32_t CM_SHAPER_RAMA_REGION_24_25; - uint32_t CM_SHAPER_RAMA_REGION_26_27; - uint32_t CM_SHAPER_RAMA_REGION_28_29; - uint32_t CM_SHAPER_RAMA_REGION_30_31; - uint32_t CM_SHAPER_RAMA_REGION_32_33; - uint32_t CM_SHAPER_LUT_INDEX; - uint32_t CM_SHAPER_LUT_DATA; - uint32_t CM_ICSC_CONTROL; - uint32_t CM_ICSC_C11_C12; - uint32_t CM_ICSC_C33_C34; - uint32_t CM_BNS_VALUES_R; - uint32_t CM_BNS_VALUES_G; - uint32_t CM_BNS_VALUES_B; - uint32_t CM_DGAM_RAMB_START_CNTL_B; - uint32_t CM_DGAM_RAMB_START_CNTL_G; - uint32_t CM_DGAM_RAMB_START_CNTL_R; - uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; - uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; - uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; - uint32_t CM_DGAM_RAMB_END_CNTL1_B; - uint32_t CM_DGAM_RAMB_END_CNTL2_B; - uint32_t CM_DGAM_RAMB_END_CNTL1_G; - uint32_t CM_DGAM_RAMB_END_CNTL2_G; - uint32_t CM_DGAM_RAMB_END_CNTL1_R; - uint32_t CM_DGAM_RAMB_END_CNTL2_R; - uint32_t CM_DGAM_RAMB_REGION_0_1; - uint32_t CM_DGAM_RAMB_REGION_14_15; - uint32_t CM_DGAM_RAMA_START_CNTL_B; - uint32_t CM_DGAM_RAMA_START_CNTL_G; - uint32_t CM_DGAM_RAMA_START_CNTL_R; - uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; - uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; - uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; - uint32_t CM_DGAM_RAMA_END_CNTL1_B; - uint32_t CM_DGAM_RAMA_END_CNTL2_B; - uint32_t CM_DGAM_RAMA_END_CNTL1_G; - uint32_t CM_DGAM_RAMA_END_CNTL2_G; - uint32_t CM_DGAM_RAMA_END_CNTL1_R; - uint32_t CM_DGAM_RAMA_END_CNTL2_R; - uint32_t CM_DGAM_RAMA_REGION_0_1; - uint32_t CM_DGAM_RAMA_REGION_14_15; - uint32_t CM_DGAM_LUT_WRITE_EN_MASK; - uint32_t CM_DGAM_LUT_INDEX; - uint32_t CM_DGAM_LUT_DATA; - uint32_t CM_CONTROL; - uint32_t CM_DGAM_CONTROL; - uint32_t CM_IGAM_CONTROL; - uint32_t CM_IGAM_LUT_RW_CONTROL; - uint32_t CM_IGAM_LUT_RW_INDEX; - uint32_t CM_IGAM_LUT_SEQ_COLOR; - uint32_t FORMAT_CONTROL; - uint32_t CNVC_SURFACE_PIXEL_FORMAT; - uint32_t CURSOR_CONTROL; - uint32_t CURSOR0_CONTROL; - uint32_t CURSOR0_COLOR0; - uint32_t CURSOR0_COLOR1; + DPP_COMMON_REG_VARIABLE_LIST }; struct dcn10_dpp { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index ccb4896975c2..6ccc90ffb0f2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -122,7 +122,7 @@ struct dpp_funcs { void (*set_cursor_attributes)( struct dpp *dpp_base, - const struct dc_cursor_attributes *attr); + enum dc_cursor_color_format color_format); void (*set_cursor_position)( struct dpp *dpp_base, -- GitLab From 4e1c1875c79b14a05b2bab45aee9b907f805447d Mon Sep 17 00:00:00 2001 From: Eric Bernstein Date: Thu, 16 Nov 2017 15:34:50 -0500 Subject: [PATCH 1485/2547] drm/amd/display: Reset MPCC muxes during init During HW initialization, instead of assuming or detecting the existing MPCC mux configuration and then removing existing planes, reset all the MPCC muxes. Signed-off-by: Eric Bernstein Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 13 ++--- .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 58 +++++++++---------- .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 6 +- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 7 +-- 4 files changed, 35 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index d542e4db5495..7376514a162e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -702,7 +702,7 @@ static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) static void dcn10_init_hw(struct dc *dc) { - int i, opp_id; + int i; struct abm *abm = dc->res_pool->abm; struct dmcu *dmcu = dc->res_pool->dmcu; struct dce_hwseq *hws = dc->hwseq; @@ -765,13 +765,8 @@ static void dcn10_init_hw(struct dc *dc) } } - /* Initialize MPC tree based on HW values */ - for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) { - struct output_pixel_processor *opp = dc->res_pool->opps[opp_id]; - struct mpc_tree *mpc_tree_params = &(opp->mpc_tree_params); - - dc->res_pool->mpc->funcs->init_mpcc_list_from_hw(dc->res_pool->mpc, mpc_tree_params); - } + /* Reset all MPCC muxes */ + dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc); for (i = 0; i < dc->res_pool->pipe_count; i++) { struct timing_generator *tg = dc->res_pool->timing_generators[i]; @@ -783,7 +778,7 @@ static void dcn10_init_hw(struct dc *dc) pipe_ctx->plane_res.hubp = hubp; hubp->mpcc_id = i; - hubp->opp_id = dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i); + hubp->opp_id = 0xf; hubp->power_gated = false; if (hubp->opp_id != 0xf) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index d6606180b50a..1e72bd42dca4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -101,16 +101,6 @@ void mpc1_assert_idle_mpcc(struct mpc *mpc, int id) 1, 100000); } -static int mpc1_get_opp_id(struct mpc *mpc, int mpcc_id) -{ - struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); - unsigned int opp_id = 0xF; - - REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); - - return opp_id; -} - struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) { struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); @@ -333,24 +323,44 @@ void mpc1_remove_mpcc( } } +static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) +{ + mpcc->mpcc_id = mpcc_inst; + mpcc->dpp_id = 0xf; + mpcc->mpcc_bot = NULL; + mpcc->blnd_cfg.overlap_only = false; + mpcc->blnd_cfg.global_alpha = 0xff; + mpcc->blnd_cfg.global_gain = 0xff; + mpcc->sm_cfg.enable = false; +} + /* * Reset the MPCC HW status by disconnecting all muxes. * * Parameters: * [in/out] mpc - MPC context. - * [in] mpcc_id - The MPCC physical instance to reset. * * Return: void */ -void mpc1_reset_mpcc( - struct mpc *mpc, - int mpcc_id) +void mpc1_mpc_init(struct mpc *mpc) { struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); + int mpcc_id; + int opp_id; - REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); - REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); - REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); + mpc10->mpcc_in_use_mask = 0; + for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) { + REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); + REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); + REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); + + mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id); + } + + for (opp_id = 0; opp_id < MAX_OPP; opp_id++) { + if (REG(MUX[opp_id])) + REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, 0xf); + } } void mpc1_init_mpcc_list_from_hw( @@ -399,27 +409,15 @@ void mpc1_init_mpcc_list_from_hw( } } -static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) -{ - mpcc->mpcc_id = mpcc_inst; - mpcc->dpp_id = 0xf; - mpcc->mpcc_bot = NULL; - mpcc->blnd_cfg.overlap_only = false; - mpcc->blnd_cfg.global_alpha = 0xff; - mpcc->blnd_cfg.global_gain = 0xff; - mpcc->sm_cfg.enable = false; -} - const struct mpc_funcs dcn10_mpc_funcs = { .insert_plane = mpc1_insert_plane, .remove_mpcc = mpc1_remove_mpcc, - .reset_mpcc = mpc1_reset_mpcc, + .mpc_init = mpc1_mpc_init, .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, .wait_for_idle = mpc1_assert_idle_mpcc, .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect, .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw, .update_blending = mpc1_update_blending, - .get_opp_id = mpc1_get_opp_id, }; void dcn10_mpc_construct(struct dcn10_mpc *mpc10, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h index aa2cd40dc022..267a2995ef6e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h @@ -146,10 +146,8 @@ void mpc1_remove_mpcc( struct mpc_tree *tree, struct mpcc *mpcc); -void mpc1_reset_mpcc( - struct mpc *mpc, - int mpcc_id); - +void mpc1_mpc_init( + struct mpc *mpc); void mpc1_assert_idle_mpcc( struct mpc *mpc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index 2396b15befb0..23a8d5e53a89 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -151,13 +151,10 @@ struct mpc_funcs { * * Parameters: * [in/out] mpc - MPC context. - * [in] mpcc_id - The MPCC physical instance to reset. * * Return: void */ - void (*reset_mpcc)( - struct mpc *mpc, - int mpcc_id); + void (*mpc_init)(struct mpc *mpc); /* * Update the blending configuration for a specified MPCC. @@ -186,8 +183,6 @@ struct mpc_funcs { struct mpc *mpc, struct mpc_tree *tree); - int (*get_opp_id)(struct mpc *mpc, int mpcc_id); - }; #endif -- GitLab From b629596072e5fa901c84f9e88d845a696ee32942 Mon Sep 17 00:00:00 2001 From: Vitaly Prosyak Date: Tue, 14 Nov 2017 17:12:52 -0600 Subject: [PATCH 1486/2547] drm/amd/display: Build unity lut for shaper Add color module to diagnostic compilation Signed-off-by: Vitaly Prosyak Reviewed-by: Charlene Liu Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/basics/fixpt31_32.c | 12 + drivers/gpu/drm/amd/display/dc/dc.h | 3 +- .../amd/display/dc/dcn10/dcn10_cm_common.c | 292 +++++++++++++++++- .../amd/display/dc/dcn10/dcn10_cm_common.h | 10 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 275 +---------------- .../gpu/drm/amd/display/include/fixed31_32.h | 7 + 6 files changed, 325 insertions(+), 274 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c index 26936892c6f5..13f8b8c02212 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c +++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c @@ -565,3 +565,15 @@ uint32_t dal_fixed31_32_u0d19( { return ux_dy(arg.value, 0, 19); } + +uint32_t dal_fixed31_32_u0d14( + struct fixed31_32 arg) +{ + return ux_dy(arg.value, 1, 14); +} + +uint32_t dal_fixed31_32_u0d10( + struct fixed31_32 arg) +{ + return ux_dy(arg.value, 1, 10); +} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f785d4a679df..ee8af9fa66f8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -342,7 +342,8 @@ struct dc_hdr_static_metadata { enum dc_transfer_func_type { TF_TYPE_PREDEFINED, TF_TYPE_DISTRIBUTED_POINTS, - TF_TYPE_BYPASS + TF_TYPE_BYPASS, + TF_TYPE_UNITY }; struct dc_transfer_func_distributed_points { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c index 7f579cb19f4b..e132d0163787 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c @@ -22,11 +22,12 @@ * Authors: AMD * */ - +#include "dc.h" #include "reg_helper.h" #include "dcn10_dpp.h" #include "dcn10_cm_common.h" +#include "custom_float.h" #define REG(reg) reg @@ -121,3 +122,292 @@ void cm_helper_program_xfer_func( } } + + + +bool cm_helper_convert_to_custom_float( + struct pwl_result_data *rgb_resulted, + struct curve_points *arr_points, + uint32_t hw_points_num, + bool fixpoint) +{ + struct custom_float_format fmt; + + struct pwl_result_data *rgb = rgb_resulted; + + uint32_t i = 0; + + fmt.exponenta_bits = 6; + fmt.mantissa_bits = 12; + fmt.sign = false; + + if (!convert_to_custom_float_format(arr_points[0].x, &fmt, + &arr_points[0].custom_float_x)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, + &arr_points[0].custom_float_offset)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, + &arr_points[0].custom_float_slope)) { + BREAK_TO_DEBUGGER(); + return false; + } + + fmt.mantissa_bits = 10; + fmt.sign = false; + + if (!convert_to_custom_float_format(arr_points[1].x, &fmt, + &arr_points[1].custom_float_x)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format(arr_points[1].y, &fmt, + &arr_points[1].custom_float_y)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, + &arr_points[1].custom_float_slope)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (hw_points_num == 0 || rgb_resulted == NULL || fixpoint == true) + return true; + + fmt.mantissa_bits = 12; + fmt.sign = true; + + while (i != hw_points_num) { + if (!convert_to_custom_float_format(rgb->red, &fmt, + &rgb->red_reg)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format(rgb->green, &fmt, + &rgb->green_reg)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format(rgb->blue, &fmt, + &rgb->blue_reg)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format(rgb->delta_red, &fmt, + &rgb->delta_red_reg)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format(rgb->delta_green, &fmt, + &rgb->delta_green_reg)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, + &rgb->delta_blue_reg)) { + BREAK_TO_DEBUGGER(); + return false; + } + + ++rgb; + ++i; + } + + return true; +} + + +#define MAX_REGIONS_NUMBER 34 +#define MAX_LOW_POINT 25 +#define NUMBER_SEGMENTS 32 + +bool cm_helper_translate_curve_to_hw_format( + const struct dc_transfer_func *output_tf, + struct pwl_params *lut_params, bool fixpoint) +{ + struct curve_points *arr_points; + struct pwl_result_data *rgb_resulted; + struct pwl_result_data *rgb; + struct pwl_result_data *rgb_plus_1; + struct fixed31_32 y_r; + struct fixed31_32 y_g; + struct fixed31_32 y_b; + struct fixed31_32 y1_min; + struct fixed31_32 y3_max; + + int32_t segment_start, segment_end; + int32_t i; + uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; + + if (output_tf == NULL || lut_params == NULL || output_tf->type == TF_TYPE_BYPASS) + return false; + + PERF_TRACE(); + + arr_points = lut_params->arr_points; + rgb_resulted = lut_params->rgb_resulted; + hw_points = 0; + + memset(lut_params, 0, sizeof(struct pwl_params)); + memset(seg_distr, 0, sizeof(seg_distr)); + + if (output_tf->tf == TRANSFER_FUNCTION_PQ) { + /* 32 segments + * segments are from 2^-25 to 2^7 + */ + for (i = 0; i < 32 ; i++) + seg_distr[i] = 3; + + segment_start = -25; + segment_end = 7; + } else { + /* 10 segments + * segment is from 2^-10 to 2^0 + * There are less than 256 points, for optimization + */ + seg_distr[0] = 3; + seg_distr[1] = 4; + seg_distr[2] = 4; + seg_distr[3] = 4; + seg_distr[4] = 4; + seg_distr[5] = 4; + seg_distr[6] = 4; + seg_distr[7] = 4; + seg_distr[8] = 5; + seg_distr[9] = 5; + + segment_start = -10; + segment_end = 0; + } + + for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++) + seg_distr[i] = -1; + + for (k = 0; k < MAX_REGIONS_NUMBER; k++) { + if (seg_distr[k] != -1) + hw_points += (1 << seg_distr[k]); + } + + j = 0; + for (k = 0; k < (segment_end - segment_start); k++) { + increment = NUMBER_SEGMENTS / (1 << seg_distr[k]); + start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS; + for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) { + if (j == hw_points - 1) + break; + rgb_resulted[j].red = output_tf->tf_pts.red[i]; + rgb_resulted[j].green = output_tf->tf_pts.green[i]; + rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; + j++; + } + } + + /* last point */ + start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS; + rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; + rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; + rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; + + arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), + dal_fixed31_32_from_int(segment_start)); + arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), + dal_fixed31_32_from_int(segment_end)); + + y_r = rgb_resulted[0].red; + y_g = rgb_resulted[0].green; + y_b = rgb_resulted[0].blue; + + y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); + + arr_points[0].y = y1_min; + arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, arr_points[0].x); + y_r = rgb_resulted[hw_points - 1].red; + y_g = rgb_resulted[hw_points - 1].green; + y_b = rgb_resulted[hw_points - 1].blue; + + /* see comment above, m_arrPoints[1].y should be the Y value for the + * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) + */ + y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); + + arr_points[1].y = y3_max; + + arr_points[1].slope = dal_fixed31_32_zero; + + if (output_tf->tf == TRANSFER_FUNCTION_PQ) { + /* for PQ, we want to have a straight line from last HW X point, + * and the slope to be such that we hit 1.0 at 10000 nits. + */ + const struct fixed31_32 end_value = + dal_fixed31_32_from_int(125); + + arr_points[1].slope = dal_fixed31_32_div( + dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), + dal_fixed31_32_sub(end_value, arr_points[1].x)); + } + + lut_params->hw_points_num = hw_points; + + i = 1; + for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) { + if (seg_distr[k] != -1) { + lut_params->arr_curve_points[k].segments_num = + seg_distr[k]; + lut_params->arr_curve_points[i].offset = + lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]); + } + i++; + } + + if (seg_distr[k] != -1) + lut_params->arr_curve_points[k].segments_num = seg_distr[k]; + + rgb = rgb_resulted; + rgb_plus_1 = rgb_resulted + 1; + + i = 1; + while (i != hw_points + 1) { + if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red)) + rgb_plus_1->red = rgb->red; + if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green)) + rgb_plus_1->green = rgb->green; + if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) + rgb_plus_1->blue = rgb->blue; + + rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red); + rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green); + rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue); + + if (fixpoint == true) { + rgb->delta_red_reg = dal_fixed31_32_u0d10(rgb->delta_red); + rgb->delta_green_reg = dal_fixed31_32_u0d10(rgb->delta_green); + rgb->delta_blue_reg = dal_fixed31_32_u0d10(rgb->delta_blue); + rgb->red_reg = dal_fixed31_32_u0d14(rgb->red); + rgb->green_reg = dal_fixed31_32_u0d14(rgb->green); + rgb->blue_reg = dal_fixed31_32_u0d14(rgb->blue); + } + + ++rgb_plus_1; + ++rgb; + ++i; + } + cm_helper_convert_to_custom_float(rgb_resulted, + lut_params->arr_points, + hw_points, fixpoint); + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h index 64836dcf21f2..64e476b83bcb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h @@ -96,4 +96,14 @@ void cm_helper_program_xfer_func( const struct pwl_params *params, const struct xfer_func_reg *reg); +bool cm_helper_convert_to_custom_float( + struct pwl_result_data *rgb_resulted, + struct curve_points *arr_points, + uint32_t hw_points_num, + bool fixpoint); + +bool cm_helper_translate_curve_to_hw_format( + const struct dc_transfer_func *output_tf, + struct pwl_params *lut_params, bool fixpoint); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7376514a162e..e29111eb64e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -43,6 +43,7 @@ #include "custom_float.h" #include "dcn10_hubp.h" #include "dcn10_hubbub.h" +#include "dcn10_cm_common.h" #define CTX \ hws->ctx @@ -954,280 +955,10 @@ static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx, return result; } -/*modify the method to handle rgb for arr_points*/ -static bool convert_to_custom_float( - struct pwl_result_data *rgb_resulted, - struct curve_points *arr_points, - uint32_t hw_points_num) -{ - struct custom_float_format fmt; - - struct pwl_result_data *rgb = rgb_resulted; - - uint32_t i = 0; - - fmt.exponenta_bits = 6; - fmt.mantissa_bits = 12; - fmt.sign = false; - - if (!convert_to_custom_float_format(arr_points[0].x, &fmt, - &arr_points[0].custom_float_x)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, - &arr_points[0].custom_float_offset)) { - BREAK_TO_DEBUGGER(); - return false; - } - if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, - &arr_points[0].custom_float_slope)) { - BREAK_TO_DEBUGGER(); - return false; - } - fmt.mantissa_bits = 10; - fmt.sign = false; - if (!convert_to_custom_float_format(arr_points[1].x, &fmt, - &arr_points[1].custom_float_x)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format(arr_points[1].y, &fmt, - &arr_points[1].custom_float_y)) { - BREAK_TO_DEBUGGER(); - return false; - } - if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, - &arr_points[1].custom_float_slope)) { - BREAK_TO_DEBUGGER(); - return false; - } - - fmt.mantissa_bits = 12; - fmt.sign = true; - - while (i != hw_points_num) { - if (!convert_to_custom_float_format(rgb->red, &fmt, - &rgb->red_reg)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format(rgb->green, &fmt, - &rgb->green_reg)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format(rgb->blue, &fmt, - &rgb->blue_reg)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format(rgb->delta_red, &fmt, - &rgb->delta_red_reg)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format(rgb->delta_green, &fmt, - &rgb->delta_green_reg)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, - &rgb->delta_blue_reg)) { - BREAK_TO_DEBUGGER(); - return false; - } - - ++rgb; - ++i; - } - - return true; -} -#define MAX_REGIONS_NUMBER 34 -#define MAX_LOW_POINT 25 -#define NUMBER_SEGMENTS 32 - -static bool -dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, - struct pwl_params *regamma_params) -{ - struct curve_points *arr_points; - struct pwl_result_data *rgb_resulted; - struct pwl_result_data *rgb; - struct pwl_result_data *rgb_plus_1; - struct fixed31_32 y_r; - struct fixed31_32 y_g; - struct fixed31_32 y_b; - struct fixed31_32 y1_min; - struct fixed31_32 y3_max; - - int32_t segment_start, segment_end; - int32_t i; - uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; - - if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) - return false; - - PERF_TRACE(); - - arr_points = regamma_params->arr_points; - rgb_resulted = regamma_params->rgb_resulted; - hw_points = 0; - - memset(regamma_params, 0, sizeof(struct pwl_params)); - memset(seg_distr, 0, sizeof(seg_distr)); - - if (output_tf->tf == TRANSFER_FUNCTION_PQ) { - /* 32 segments - * segments are from 2^-25 to 2^7 - */ - for (i = 0; i < 32 ; i++) - seg_distr[i] = 3; - - segment_start = -25; - segment_end = 7; - } else { - /* 10 segments - * segment is from 2^-10 to 2^0 - * There are less than 256 points, for optimization - */ - seg_distr[0] = 3; - seg_distr[1] = 4; - seg_distr[2] = 4; - seg_distr[3] = 4; - seg_distr[4] = 4; - seg_distr[5] = 4; - seg_distr[6] = 4; - seg_distr[7] = 4; - seg_distr[8] = 5; - seg_distr[9] = 5; - - segment_start = -10; - segment_end = 0; - } - - for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++) - seg_distr[i] = -1; - - for (k = 0; k < MAX_REGIONS_NUMBER; k++) { - if (seg_distr[k] != -1) - hw_points += (1 << seg_distr[k]); - } - - j = 0; - for (k = 0; k < (segment_end - segment_start); k++) { - increment = NUMBER_SEGMENTS / (1 << seg_distr[k]); - start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS; - for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) { - if (j == hw_points - 1) - break; - rgb_resulted[j].red = output_tf->tf_pts.red[i]; - rgb_resulted[j].green = output_tf->tf_pts.green[i]; - rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; - j++; - } - } - - /* last point */ - start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS; - rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; - rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; - rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; - - arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_start)); - arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); - - y_r = rgb_resulted[0].red; - y_g = rgb_resulted[0].green; - y_b = rgb_resulted[0].blue; - - y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); - - arr_points[0].y = y1_min; - arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, arr_points[0].x); - y_r = rgb_resulted[hw_points - 1].red; - y_g = rgb_resulted[hw_points - 1].green; - y_b = rgb_resulted[hw_points - 1].blue; - - /* see comment above, m_arrPoints[1].y should be the Y value for the - * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) - */ - y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); - - arr_points[1].y = y3_max; - - arr_points[1].slope = dal_fixed31_32_zero; - - if (output_tf->tf == TRANSFER_FUNCTION_PQ) { - /* for PQ, we want to have a straight line from last HW X point, - * and the slope to be such that we hit 1.0 at 10000 nits. - */ - const struct fixed31_32 end_value = - dal_fixed31_32_from_int(125); - - arr_points[1].slope = dal_fixed31_32_div( - dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), - dal_fixed31_32_sub(end_value, arr_points[1].x)); - } - - regamma_params->hw_points_num = hw_points; - - i = 1; - for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) { - if (seg_distr[k] != -1) { - regamma_params->arr_curve_points[k].segments_num = - seg_distr[k]; - regamma_params->arr_curve_points[i].offset = - regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); - } - i++; - } - - if (seg_distr[k] != -1) - regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; - - rgb = rgb_resulted; - rgb_plus_1 = rgb_resulted + 1; - - i = 1; - - while (i != hw_points + 1) { - if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red)) - rgb_plus_1->red = rgb->red; - if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green)) - rgb_plus_1->green = rgb->green; - if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) - rgb_plus_1->blue = rgb->blue; - - rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red); - rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green); - rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue); - - ++rgb_plus_1; - ++rgb; - ++i; - } - - convert_to_custom_float(rgb_resulted, arr_points, hw_points); - - PERF_TRACE(); - - return true; -} static bool dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx, @@ -1248,9 +979,9 @@ dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx, /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full * update. */ - else if (dcn10_translate_regamma_to_hw_format( + else if (cm_helper_translate_curve_to_hw_format( stream->out_transfer_func, - &dpp->regamma_params)) { + &dpp->regamma_params, false)) { dpp->funcs->dpp_program_regamma_pwl( dpp, &dpp->regamma_params, OPP_REGAMMA_USER); diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h index 3248f699daf2..c4848fadc70e 100644 --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h @@ -463,4 +463,11 @@ uint32_t dal_fixed31_32_u2d19( uint32_t dal_fixed31_32_u0d19( struct fixed31_32 arg); + +uint32_t dal_fixed31_32_u0d14( + struct fixed31_32 arg); + +uint32_t dal_fixed31_32_u0d10( + struct fixed31_32 arg); + #endif -- GitLab From f7f36c1f547751d1ea8b45f4b9dfa4a65ec271fb Mon Sep 17 00:00:00 2001 From: Eric Bernstein Date: Fri, 17 Nov 2017 17:21:26 -0500 Subject: [PATCH 1487/2547] drm/amd/display: OPP DPG test pattern Create opp_set_test_pattern function with similar interface and implementation as timing generator test pattern. Signed-off-by: Eric Bernstein Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 37 ++++++++++++++++++ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 5 ++- .../amd/display/dc/inc/hw/timing_generator.h | 39 +------------------ 3 files changed, 43 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index ddc56700109b..d7d027c7ae51 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -178,4 +178,41 @@ struct dc_bias_and_scale { uint16_t bias_blue; }; +enum test_pattern_dyn_range { + TEST_PATTERN_DYN_RANGE_VESA = 0, + TEST_PATTERN_DYN_RANGE_CEA +}; + +enum test_pattern_mode { + TEST_PATTERN_MODE_COLORSQUARES_RGB = 0, + TEST_PATTERN_MODE_COLORSQUARES_YCBCR601, + TEST_PATTERN_MODE_COLORSQUARES_YCBCR709, + TEST_PATTERN_MODE_VERTICALBARS, + TEST_PATTERN_MODE_HORIZONTALBARS, + TEST_PATTERN_MODE_SINGLERAMP_RGB, + TEST_PATTERN_MODE_DUALRAMP_RGB +}; + +enum test_pattern_color_format { + TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0, + TEST_PATTERN_COLOR_FORMAT_BPC_8, + TEST_PATTERN_COLOR_FORMAT_BPC_10, + TEST_PATTERN_COLOR_FORMAT_BPC_12 +}; + +enum controller_dp_test_pattern { + CONTROLLER_DP_TEST_PATTERN_D102 = 0, + CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR, + CONTROLLER_DP_TEST_PATTERN_PRBS7, + CONTROLLER_DP_TEST_PATTERN_COLORSQUARES, + CONTROLLER_DP_TEST_PATTERN_VERTICALBARS, + CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS, + CONTROLLER_DP_TEST_PATTERN_COLORRAMP, + CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, + CONTROLLER_DP_TEST_PATTERN_RESERVED_8, + CONTROLLER_DP_TEST_PATTERN_RESERVED_9, + CONTROLLER_DP_TEST_PATTERN_RESERVED_A, + CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA +}; + #endif /* __DAL_HW_SHARED_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 8c3a302fcd65..42f2bb29a5fc 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -284,7 +284,10 @@ struct opp_funcs { void (*opp_set_test_pattern)( struct output_pixel_processor *opp, - bool enable); + enum controller_dp_test_pattern test_pattern, + enum dc_color_depth color_depth, + int width, + int height); void (*opp_dpg_blank_enable)( struct output_pixel_processor *opp, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index e5c7e0e1db14..11a1d3672584 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -26,6 +26,8 @@ #ifndef __DAL_TIMING_GENERATOR_TYPES_H__ #define __DAL_TIMING_GENERATOR_TYPES_H__ +#include "hw_shared.h" + struct dc_bios; /* Contains CRTC vertical/horizontal pixel counters */ @@ -50,43 +52,6 @@ struct drr_params { #define LEFT_EYE_3D_PRIMARY_SURFACE 1 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0 -enum test_pattern_dyn_range { - TEST_PATTERN_DYN_RANGE_VESA = 0, - TEST_PATTERN_DYN_RANGE_CEA -}; - -enum test_pattern_mode { - TEST_PATTERN_MODE_COLORSQUARES_RGB = 0, - TEST_PATTERN_MODE_COLORSQUARES_YCBCR601, - TEST_PATTERN_MODE_COLORSQUARES_YCBCR709, - TEST_PATTERN_MODE_VERTICALBARS, - TEST_PATTERN_MODE_HORIZONTALBARS, - TEST_PATTERN_MODE_SINGLERAMP_RGB, - TEST_PATTERN_MODE_DUALRAMP_RGB -}; - -enum test_pattern_color_format { - TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0, - TEST_PATTERN_COLOR_FORMAT_BPC_8, - TEST_PATTERN_COLOR_FORMAT_BPC_10, - TEST_PATTERN_COLOR_FORMAT_BPC_12 -}; - -enum controller_dp_test_pattern { - CONTROLLER_DP_TEST_PATTERN_D102 = 0, - CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR, - CONTROLLER_DP_TEST_PATTERN_PRBS7, - CONTROLLER_DP_TEST_PATTERN_COLORSQUARES, - CONTROLLER_DP_TEST_PATTERN_VERTICALBARS, - CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS, - CONTROLLER_DP_TEST_PATTERN_COLORRAMP, - CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, - CONTROLLER_DP_TEST_PATTERN_RESERVED_8, - CONTROLLER_DP_TEST_PATTERN_RESERVED_9, - CONTROLLER_DP_TEST_PATTERN_RESERVED_A, - CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA -}; - enum crtc_state { CRTC_STATE_VBLANK = 0, CRTC_STATE_VACTIVE -- GitLab From ee016c4b5a0f150e8a71a7ed9efb1477fdf090ca Mon Sep 17 00:00:00 2001 From: Eric Murphy-Zaremba Date: Fri, 17 Nov 2017 16:29:00 -0500 Subject: [PATCH 1488/2547] drm/amd/display: Add is_tiling_rotated flag to plane_state Signed-off-by: Eric Murphy-Zaremba Reviewed-by: Aric Cyr Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ee8af9fa66f8..269d5634e6ee 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -440,6 +440,7 @@ struct dc_plane_state { enum dc_rotation_angle rotation; enum plane_stereo_format stereo_format; + bool is_tiling_rotated; bool per_pixel_alpha; bool visible; bool flip_immediate; -- GitLab From 0c31a8218b80da4220757a0eff2d4f7c1229842d Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 21 Nov 2017 13:45:51 -0500 Subject: [PATCH 1489/2547] drm/amd/display: fix recout_skip calculation when rotating 180 or 270 Fixed fliped landscape and fliped portrait hard hang. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/core/dc_resource.c | 94 ++++++++++++------- 1 file changed, 60 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ad28eba017f2..ae9312df0a1c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -498,26 +498,15 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div; /* Handle hsplit */ - if (pri_split || sec_split) { - /* HMirror XOR Secondary_pipe XOR Rotation_180 */ - bool right_view = (sec_split != plane_state->horizontal_mirror) != - (plane_state->rotation == ROTATION_ANGLE_180); - - if (plane_state->rotation == ROTATION_ANGLE_90 - || plane_state->rotation == ROTATION_ANGLE_270) - /* Secondary_pipe XOR Rotation_270 */ - right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split; - - if (right_view) { - data->viewport.x += data->viewport.width / 2; - data->viewport_c.x += data->viewport_c.width / 2; - /* Ceil offset pipe */ - data->viewport.width = (data->viewport.width + 1) / 2; - data->viewport_c.width = (data->viewport_c.width + 1) / 2; - } else { - data->viewport.width /= 2; - data->viewport_c.width /= 2; - } + if (sec_split) { + data->viewport.x += data->viewport.width / 2; + data->viewport_c.x += data->viewport_c.width / 2; + /* Ceil offset pipe */ + data->viewport.width = (data->viewport.width + 1) / 2; + data->viewport_c.width = (data->viewport_c.width + 1) / 2; + } else if (pri_split) { + data->viewport.width /= 2; + data->viewport_c.width /= 2; } if (plane_state->rotation == ROTATION_ANGLE_90 || @@ -534,6 +523,16 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip struct rect surf_src = plane_state->src_rect; struct rect surf_clip = plane_state->clip_rect; int recout_full_x, recout_full_y; + bool pri_split = pipe_ctx->bottom_pipe && + pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state; + bool sec_split = pipe_ctx->top_pipe && + pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; + + if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || + stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { + pri_split = false; + sec_split = false; + } if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) @@ -569,23 +568,35 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip /* Handle h & vsplit */ if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == - pipe_ctx->plane_state) { - if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { - pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height / 2; - /* Floor primary pipe, ceil 2ndary pipe */ - pipe_ctx->plane_res.scl_data.recout.height = (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2; - } else { - pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width / 2; - pipe_ctx->plane_res.scl_data.recout.width = (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2; - } + pipe_ctx->plane_state && stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { + pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height / 2; + /* Floor primary pipe, ceil 2ndary pipe */ + pipe_ctx->plane_res.scl_data.recout.height = (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2; } else if (pipe_ctx->bottom_pipe && - pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) { - if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) - pipe_ctx->plane_res.scl_data.recout.height /= 2; - else + pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state + && stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) + pipe_ctx->plane_res.scl_data.recout.height /= 2; + + if (pri_split || sec_split) { + /* HMirror XOR Secondary_pipe XOR Rotation_180 */ + bool right_view = (sec_split != plane_state->horizontal_mirror) != + (plane_state->rotation == ROTATION_ANGLE_180); + + if (plane_state->rotation == ROTATION_ANGLE_90 + || plane_state->rotation == ROTATION_ANGLE_270) + /* Secondary_pipe XOR Rotation_270 */ + right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split; + + if (right_view) { + pipe_ctx->plane_res.scl_data.recout.x += + pipe_ctx->plane_res.scl_data.recout.width / 2; + /* Ceil offset pipe */ + pipe_ctx->plane_res.scl_data.recout.width = + (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2; + } else { pipe_ctx->plane_res.scl_data.recout.width /= 2; + } } - /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset) * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl * ratio) @@ -601,6 +612,21 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - recout_full_x; recout_skip->height = pipe_ctx->plane_res.scl_data.recout.y - recout_full_y; + + /*Adjust recout_skip for rotation */ + if ((pri_split || sec_split) && (plane_state->rotation == ROTATION_ANGLE_270 || plane_state->rotation == ROTATION_ANGLE_180)) { + bool right_view = (sec_split != plane_state->horizontal_mirror) != + (plane_state->rotation == ROTATION_ANGLE_180); + + if (plane_state->rotation == ROTATION_ANGLE_90 + || plane_state->rotation == ROTATION_ANGLE_270) + /* Secondary_pipe XOR Rotation_270 */ + right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split; + if (!right_view) + recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x + pipe_ctx->plane_res.scl_data.recout.width / 2 - recout_full_x; + else + recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - pipe_ctx->plane_res.scl_data.recout.width / 2 - recout_full_x; + } } static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) -- GitLab From 457fbe76ecc5a28072aeb0d17d3ea6c8a9c2a304 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 21 Nov 2017 15:42:17 -0500 Subject: [PATCH 1490/2547] drm/amd/display: Program cursor regs after context swapped. Cursor is abnormal after pipe_ctx is changed in context. Cause: cursor attributes is programmed right after front end programming, but it use old pipe_ctx to program which is not updated yet. Solution: Program cursor regs after context swapped. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e29111eb64e4..e9ecbcb66e80 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1992,22 +1992,9 @@ static void dcn10_apply_ctx_for_surface( } } - if (num_planes > 0) { + if (num_planes > 0) program_all_pipe_in_tree(dc, top_pipe_to_program, context); - /* TODO: this is a hack w/a for switching from mpo to pipe split */ - if (stream->cursor_attributes.address.quad_part != 0) { - struct dc_cursor_position position = { 0 }; - - dc_stream_set_cursor_position( - (struct dc_stream_state *)stream, - &position); - dc_stream_set_cursor_attributes( - (struct dc_stream_state *)stream, - &stream->cursor_attributes); - } - } - tg->funcs->unlock(tg); if (num_planes == 0) -- GitLab From ea783c31e270dbdd82d5b9d40de4e6336e92e5b2 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 21 Nov 2017 16:12:23 -0500 Subject: [PATCH 1491/2547] drm/amd/display: Cache cursor position. When programming cursor position after front end programmed, if position is already set previously, it doesn't make sense to program position with all 0. Cache position and use the parameter after front end programming. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 ++ drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index e39568b4460c..261811e0c094 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -301,6 +301,8 @@ bool dc_stream_set_cursor_position( } + stream->cursor_position = *position; + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index fed0e5ea9625..01c60f11b2bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -86,6 +86,7 @@ struct dc_stream_state { struct dc_stream_status status; struct dc_cursor_attributes cursor_attributes; + struct dc_cursor_position cursor_position; /* from stream struct */ struct kref refcount; -- GitLab From 16a29dd3bb18ea23d9676e6a3b1c6464dba620c3 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Tue, 21 Nov 2017 15:59:42 -0500 Subject: [PATCH 1492/2547] drm/amd/display: Refine update flags usage in update_dchubp_dpp - Only update DPP clock if it's a full update. - Program viewport on position change. This caused SLS regressions. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e9ecbcb66e80..7846534cd6d5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1726,7 +1726,7 @@ static void update_dchubp_dpp( union plane_size size = plane_state->plane_size; /* depends on DML calculation, DPP clock value may change dynamically */ - if (pipe_ctx->plane_state->update_flags.raw != 0) { + if (plane_state->update_flags.bits.full_update) { enable_dppclk( dc->hwseq, pipe_ctx->pipe_idx, @@ -1770,7 +1770,8 @@ static void update_dchubp_dpp( } if (plane_state->update_flags.bits.full_update || - plane_state->update_flags.bits.scaling_change) { + plane_state->update_flags.bits.scaling_change || + plane_state->update_flags.bits.position_change) { hubp->funcs->mem_program_viewport( hubp, &pipe_ctx->plane_res.scl_data.viewport, -- GitLab From cc55b1f5c31aba89c9b504b7400d0e247e8ce1da Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Tue, 21 Nov 2017 17:51:50 -0500 Subject: [PATCH 1493/2547] drm/amd/display: Set mpcc_disconnect_pending during MPC reset This prevents an issue where the MPCC will not go to idle due to us not waiting for it to become idle during disable plane. Signed-off-by: Andrew Jiang Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 18 ++++++++++++++---- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 ++-- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c index 584e82cc5df3..1984ac2eb740 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -42,15 +42,25 @@ void hubp1_set_blank(struct hubp *hubp, bool blank) { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); uint32_t blank_en = blank ? 1 : 0; + uint32_t reg_val = 0; - REG_UPDATE_2(DCHUBP_CNTL, + reg_val = REG_UPDATE_2(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en, HUBP_TTU_DISABLE, blank_en); if (blank) { - REG_WAIT(DCHUBP_CNTL, - HUBP_NO_OUTSTANDING_REQ, 1, - 1, 200); + if (reg_val) { + /* init sequence workaround: in case HUBP is + * power gated, this wait would timeout. + * + * we just wrote reg_val to non-0, if it stay 0 + * it means HUBP is gated + */ + REG_WAIT(DCHUBP_CNTL, + HUBP_NO_OUTSTANDING_REQ, 1, + 1, 200); + } + hubp->mpcc_id = 0xf; hubp->opp_id = 0xf; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7846534cd6d5..a4d756c1b97a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -782,8 +782,8 @@ static void dcn10_init_hw(struct dc *dc) hubp->opp_id = 0xf; hubp->power_gated = false; - if (hubp->opp_id != 0xf) - pipe_ctx->stream_res.opp = dc->res_pool->opps[hubp->opp_id]; + dc->res_pool->opps[i]->mpcc_disconnect_pending[i] = true; + pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; plane_atomic_disconnect(dc, pipe_ctx); } -- GitLab From fdc72e7df9a42fe206d024f980def5a099aeea1d Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Tue, 21 Nov 2017 21:40:34 -0500 Subject: [PATCH 1494/2547] drm/amd/display: dal 3.1.24 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 269d5634e6ee..74286d3001ae 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.23" +#define DC_VER "3.1.24" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From 3f4e3a282e1235a9ab46d063b0902c00b6afc6a9 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 29 Nov 2017 10:16:51 -0500 Subject: [PATCH 1495/2547] drm/amd/display: Use macro for isnan check In code provided by HW teams we do a NaN check on floats by comparing the number against itself. This confuses most people including myself. Macro it out to make it self-explanatory. Don't do a NaN check for int. v2: parantheses around 'number' expression Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/calcs/dcn_calc_math.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c index b6abe0f3bb15..ae38cdb80915 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c @@ -25,37 +25,35 @@ #include "dcn_calc_math.h" +#define isNaN(number) ((number) != (number)) + float dcn_bw_mod(const float arg1, const float arg2) { - if (arg1 != arg1) + if (isNaN(arg1)) return arg2; - if (arg2 != arg2) + if (isNaN(arg2)) return arg1; return arg1 - arg1 * ((int) (arg1 / arg2)); } float dcn_bw_min2(const float arg1, const float arg2) { - if (arg1 != arg1) + if (isNaN(arg1)) return arg2; - if (arg2 != arg2) + if (isNaN(arg2)) return arg1; return arg1 < arg2 ? arg1 : arg2; } unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2) { - if (arg1 != arg1) - return arg2; - if (arg2 != arg2) - return arg1; return arg1 > arg2 ? arg1 : arg2; } float dcn_bw_max2(const float arg1, const float arg2) { - if (arg1 != arg1) + if (isNaN(arg1)) return arg2; - if (arg2 != arg2) + if (isNaN(arg2)) return arg1; return arg1 > arg2 ? arg1 : arg2; } -- GitLab From a018298ff850effd3a8494c839449150aef0934a Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 29 Nov 2017 10:28:29 -0500 Subject: [PATCH 1496/2547] drm/amd/display: Add disclaimer to BW and DML code provided by HW This code can sometimes look troubling but we trust it as it comes from HW teams with a guarantee of correctness. Add a note to these files to explain this. v2: thing -> things Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 9 +++++++++ drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 9 +++++++++ drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 9 +++++++++ drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 9 +++++++++ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 9 +++++++++ .../gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c | 9 +++++++++ .../drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c | 9 +++++++++ drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c | 10 ++++++++++ 8 files changed, 73 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 6347712db834..2e11fac2a63d 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -29,6 +29,15 @@ #include "core_types.h" #include "dal_asic_id.h" +/* + * NOTE: + * This file is gcc-parseable HW gospel, coming straight from HW engineers. + * + * It doesn't adhere to Linux kernel style and sometimes will do things in odd + * ways. Unless there is something clearly wrong with it the code should + * remain as-is as it provides us with a guarantee from HW that it is correct. + */ + /******************************************************************************* * Private Functions ******************************************************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c index 626f9cf8aad2..366aace8c323 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c @@ -27,6 +27,15 @@ #include "dcn_calc_auto.h" #include "dcn_calc_math.h" +/* + * NOTE: + * This file is gcc-parseable HW gospel, coming straight from HW engineers. + * + * It doesn't adhere to Linux kernel style and sometimes will do things in odd + * ways. Unless there is something clearly wrong with it the code should + * remain as-is as it provides us with a guarantee from HW that it is correct. + */ + /*REVISION#250*/ void scaler_settings_calculation(struct dcn_bw_internal_vars *v) { diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c index ae38cdb80915..7600a4a4abc7 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c @@ -27,6 +27,15 @@ #define isNaN(number) ((number) != (number)) +/* + * NOTE: + * This file is gcc-parseable HW gospel, coming straight from HW engineers. + * + * It doesn't adhere to Linux kernel style and sometimes will do things in odd + * ways. Unless there is something clearly wrong with it the code should + * remain as-is as it provides us with a guarantee from HW that it is correct. + */ + float dcn_bw_mod(const float arg1, const float arg2) { if (isNaN(arg1)) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index a4fbca34bcdf..b5bc9159f48e 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -33,6 +33,15 @@ #include "dcn10/dcn10_resource.h" #include "dcn_calc_math.h" +/* + * NOTE: + * This file is gcc-parseable HW gospel, coming straight from HW engineers. + * + * It doesn't adhere to Linux kernel style and sometimes will do things in odd + * ways. Unless there is something clearly wrong with it the code should + * remain as-is as it provides us with a guarantee from HW that it is correct. + */ + /* Defaults from spreadsheet rev#247 */ const struct dcn_soc_bounding_box dcn10_soc_defaults = { /* latencies */ diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c index 1f337ecfeab0..260e113fcc02 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -28,6 +28,15 @@ #include "dml_inline_defs.h" +/* + * NOTE: + * This file is gcc-parseable HW gospel, coming straight from HW engineers. + * + * It doesn't adhere to Linux kernel style and sometimes will do things in odd + * ways. Unless there is something clearly wrong with it the code should + * remain as-is as it provides us with a guarantee from HW that it is correct. + */ + #define BPP_INVALID 0 #define BPP_BLENDED_PIPE 0xffffffff static const unsigned int NumberOfStates = DC__VOLTAGE_STATES; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c index 8ba962df42e6..325dd2b757d6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c @@ -27,6 +27,15 @@ #include "display_mode_vba.h" #include "display_rq_dlg_calc.h" +/* + * NOTE: + * This file is gcc-parseable HW gospel, coming straight from HW engineers. + * + * It doesn't adhere to Linux kernel style and sometimes will do things in odd + * ways. Unless there is something clearly wrong with it the code should + * remain as-is as it provides us with a guarantee from HW that it is correct. + */ + static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, double *refcyc_per_req_delivery_pre_cur, double *refcyc_per_req_delivery_cur, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c index 1e4b1e383401..c2037daa8e66 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c @@ -28,6 +28,15 @@ #include "dml_inline_defs.h" +/* + * NOTE: + * This file is gcc-parseable HW gospel, coming straight from HW engineers. + * + * It doesn't adhere to Linux kernel style and sometimes will do things in odd + * ways. Unless there is something clearly wrong with it the code should + * remain as-is as it provides us with a guarantee from HW that it is correct. + */ + static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma) { unsigned int ret_val = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c b/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c index bc7d8c707221..324239c77958 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c +++ b/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c @@ -27,6 +27,16 @@ #include "dc_features.h" #include "dml_inline_defs.h" + +/* + * NOTE: + * This file is gcc-parseable HW gospel, coming straight from HW engineers. + * + * It doesn't adhere to Linux kernel style and sometimes will do things in odd + * ways. Unless there is something clearly wrong with it the code should + * remain as-is as it provides us with a guarantee from HW that it is correct. + */ + void dml_socbb_set_latencies(soc_bounding_box_st *to_box, soc_bounding_box_st *from_box) { to_box->dram_clock_change_latency_us = from_box->dram_clock_change_latency_us; -- GitLab From 75c2dec31a100daee4d3d9a1c2042918c9561f04 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Wed, 22 Nov 2017 11:51:30 -0500 Subject: [PATCH 1497/2547] drm/amd/display: really fix time out in init sequence REG_UPDATE_2 return the reg value it write out through MMIO we need to do a REG_READ to confirm the value is written out Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c index 1984ac2eb740..2d843b2d5f86 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -42,13 +42,14 @@ void hubp1_set_blank(struct hubp *hubp, bool blank) { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); uint32_t blank_en = blank ? 1 : 0; - uint32_t reg_val = 0; - reg_val = REG_UPDATE_2(DCHUBP_CNTL, + REG_UPDATE_2(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en, HUBP_TTU_DISABLE, blank_en); if (blank) { + uint32_t reg_val = REG_READ(DCHUBP_CNTL); + if (reg_val) { /* init sequence workaround: in case HUBP is * power gated, this wait would timeout. -- GitLab From 76121231cf4a40b7c06a3bb73235a1d7da058343 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 21 Nov 2017 13:19:32 -0500 Subject: [PATCH 1498/2547] drm/amd/display: Print DC_VER at DC init This has proven helpful on other OSes to give a quick state of the DC driver when a bug is reported. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ccbf10e3bbb6..8e7621931b92 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -431,9 +431,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) adev->dm.dc = dc_create(&init_data); if (adev->dm.dc) { - DRM_INFO("Display Core initialized!\n"); + DRM_INFO("Display Core initialized with v%s!\n", DC_VER); } else { - DRM_INFO("Display Core failed to initialize!\n"); + DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); goto error; } -- GitLab From bce14857bd1b2d6849336f56e7a1926ab937c5ef Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Mon, 13 Nov 2017 17:03:53 -0500 Subject: [PATCH 1499/2547] drm/amd/display: set chroma taps to 1 when not scaling Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 9 +++++++++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 9 ++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index b5bc9159f48e..453ec1c6c181 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -897,6 +897,15 @@ bool dcn_validate_bandwidth( v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c; v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c; + /* + * Spreadsheet doesn't handle taps_c is one properly, + * need to force Chroma to always be scaled to pass + * bandwidth validation. + */ + if (v->override_hta_pschroma[input_idx] == 1) + v->override_hta_pschroma[input_idx] = 2; + if (v->override_vta_pschroma[input_idx] == 1) + v->override_vta_pschroma[input_idx] = 2; v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; } if (v->is_line_buffer_bpp_fixed == dcn_bw_yes) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 5a95fa03bc17..6db1839d7155 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -159,11 +159,10 @@ bool dpp_get_optimal_number_of_taps( scl_data->taps.h_taps = 1; if (IDENTITY_RATIO(scl_data->ratios.vert)) scl_data->taps.v_taps = 1; - /* - * Spreadsheet doesn't handle taps_c is one properly, - * need to force Chroma to always be scaled to pass - * bandwidth validation. - */ + if (IDENTITY_RATIO(scl_data->ratios.horz_c)) + scl_data->taps.h_taps_c = 1; + if (IDENTITY_RATIO(scl_data->ratios.vert_c)) + scl_data->taps.v_taps_c = 1; } return true; -- GitLab From 96d923887994eb7c97b44afceaeac6640ba22653 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 14 Nov 2017 11:52:11 -0500 Subject: [PATCH 1500/2547] drm/amd/display: Add dppclk to dcn_bw_clocks Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 3 ++- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 - drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 3b0db253ac22..b73db9e78437 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -582,7 +582,8 @@ struct dce_hwseq_registers { type DOMAIN7_PGFSM_PWR_STATUS; \ type DCFCLK_GATE_DIS; \ type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ - type DENTIST_DPPCLK_WDIVIDER; + type DENTIST_DPPCLK_WDIVIDER; \ + type DENTIST_DISPCLK_WDIVIDER; struct dce_hwseq_shift { HWSEQ_REG_FIELD_LIST(uint8_t) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index a4d756c1b97a..39a4d1a86583 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1335,7 +1335,6 @@ static void dcn10_enable_plane( /* make sure OPP_PIPE_CLOCK_EN = 1 */ REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst], OPP_PIPE_CLOCK_EN, 1); - /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/ /* TODO: enable/disable in dm as per update type. if (plane_state) { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index d680b565af6f..9cc6bbb20714 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -241,6 +241,7 @@ struct dce_bw_output { struct dcn_bw_clocks { int dispclk_khz; + int dppclk_khz; bool dppclk_div; int dcfclk_khz; int dcfclk_deep_sleep_khz; -- GitLab From 7bc6f1ca9dbe8261d05dd4b63dacc26d4229415f Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Thu, 23 Nov 2017 12:08:13 -0500 Subject: [PATCH 1501/2547] drm/amd/display: add assert to verify dcn_calc input validity This reverts commit 978482d0de86 Revert noisy assert messages Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 453ec1c6c181..47dbc953a3a9 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -887,6 +887,17 @@ bool dcn_validate_bandwidth( + pipe->bottom_pipe->plane_res.scl_data.recout.width; } + if (pipe->plane_state->rotation % 2 == 0) { + ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dal_fixed31_32_one.value + || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]); + ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dal_fixed31_32_one.value + || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]); + } else { + ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dal_fixed31_32_one.value + || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]); + ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dal_fixed31_32_one.value + || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]); + } v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs( pipe->plane_state->format); -- GitLab From 493942cd250c62f459f12a3a8a45639e360f4312 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Thu, 23 Nov 2017 11:32:18 -0500 Subject: [PATCH 1502/2547] drm/amd/display: dpp clean up Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 4 +++- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 7 +------ 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index 4c90043e7b8c..4f5125398bbc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -49,6 +49,8 @@ #define FN(reg_name, field_name) \ dpp->tf_shift->field_name, dpp->tf_mask->field_name +#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) + struct dcn10_input_csc_matrix { enum dc_color_space color_space; uint16_t regval[12]; @@ -270,7 +272,7 @@ void dpp1_cm_set_output_csc_default( struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); struct out_csc_color_matrix tbl_entry; int i, j; - int arr_size = sizeof(output_csc_matrix) / sizeof(struct output_csc_matrix); + int arr_size = NUM_ELEMENTS(output_csc_matrix); uint32_t ocsc_mode = 4; tbl_entry.color_space = colorspace; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index d7d027c7ae51..0f70f36a3ebe 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -131,12 +131,7 @@ struct out_csc_color_matrix { uint16_t regval[12]; }; -struct output_csc_matrix { - enum dc_color_space color_space; - uint16_t regval[12]; -}; - -static const struct output_csc_matrix output_csc_matrix[] = { +static const struct out_csc_color_matrix output_csc_matrix[] = { { COLOR_SPACE_SRGB, { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, { COLOR_SPACE_SRGB_LIMITED, -- GitLab From 79086a55defa83c0735c5a3ee30e573f5076eb66 Mon Sep 17 00:00:00 2001 From: Vitaly Prosyak Date: Thu, 23 Nov 2017 09:42:22 -0600 Subject: [PATCH 1503/2547] drm/amd/display: Move unity TF type to predefined types Also handle fixpoint y values for CM curves Signed-off-by: Vitaly Prosyak Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 6 ++++-- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 3 +-- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 74286d3001ae..939fa6f85826 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -343,7 +343,6 @@ enum dc_transfer_func_type { TF_TYPE_PREDEFINED, TF_TYPE_DISTRIBUTED_POINTS, TF_TYPE_BYPASS, - TF_TYPE_UNITY }; struct dc_transfer_func_distributed_points { @@ -362,6 +361,7 @@ enum dc_transfer_func_predefined { TRANSFER_FUNCTION_BT709, TRANSFER_FUNCTION_PQ, TRANSFER_FUNCTION_LINEAR, + TRANSFER_FUNCTION_UNITY, }; struct dc_transfer_func { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c index e132d0163787..352ae7bf9a3f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c @@ -168,8 +168,10 @@ bool cm_helper_convert_to_custom_float( return false; } - if (!convert_to_custom_float_format(arr_points[1].y, &fmt, - &arr_points[1].custom_float_y)) { + if (fixpoint == true) + arr_points[1].custom_float_y = dal_fixed31_32_u0d14(arr_points[1].y); + else if (!convert_to_custom_float_format(arr_points[1].y, &fmt, + &arr_points[1].custom_float_y)) { BREAK_TO_DEBUGGER(); return false; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 41f0c84bfa09..b6d526067cb5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -731,7 +731,7 @@ type CM_BLNDGAM_LUT_WRITE_EN_MASK; \ type CM_BLNDGAM_LUT_WRITE_SEL; \ type CM_BLNDGAM_LUT_INDEX; \ - type CM_BLNDGAM_LUT_DATA; \ + type BLNDGAM_MEM_PWR_FORCE; \ type CM_3DLUT_MODE; \ type CM_3DLUT_SIZE; \ type CM_3DLUT_INDEX; \ @@ -1147,7 +1147,6 @@ struct dcn_dpp_mask { uint32_t CM_BLNDGAM_RAMA_REGION_30_31; \ uint32_t CM_BLNDGAM_RAMA_REGION_32_33; \ uint32_t CM_BLNDGAM_LUT_INDEX; \ - uint32_t CM_BLNDGAM_LUT_DATA; \ uint32_t CM_3DLUT_MODE; \ uint32_t CM_3DLUT_INDEX; \ uint32_t CM_3DLUT_DATA; \ -- GitLab From 40e045a9733f3c032ff957d9663c106c82fd5343 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Wed, 22 Nov 2017 16:48:35 -0500 Subject: [PATCH 1504/2547] drm/amd/display: OPTC cleanup/implementation Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 10 +- .../display/dc/dcn10/dcn10_timing_generator.c | 316 +++++++++--------- .../display/dc/dcn10/dcn10_timing_generator.h | 90 ++++- 4 files changed, 244 insertions(+), 174 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 39a4d1a86583..7ec87fcb22be 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -159,7 +159,7 @@ void dcn10_log_hw_state(struct dc *dc) struct timing_generator *tg = pool->timing_generators[i]; struct dcn_otg_state s = {0}; - tgn10_read_otg_state(DCN10TG_FROM_TG(tg), &s); + optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); //only print if OTG master is enabled if ((s.otg_enabled & 1) == 0) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index a9a5d176cb70..65ce96ba6443 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -348,18 +348,18 @@ static const struct dcn_mpc_mask mpc_mask = { #define tg_regs(id)\ [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} -static const struct dcn_tg_registers tg_regs[] = { +static const struct dcn_optc_registers tg_regs[] = { tg_regs(0), tg_regs(1), tg_regs(2), tg_regs(3), }; -static const struct dcn_tg_shift tg_shift = { +static const struct dcn_optc_shift tg_shift = { TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) }; -static const struct dcn_tg_mask tg_mask = { +static const struct dcn_optc_mask tg_mask = { TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) }; @@ -553,8 +553,8 @@ static struct timing_generator *dcn10_timing_generator_create( struct dc_context *ctx, uint32_t instance) { - struct dcn10_timing_generator *tgn10 = - kzalloc(sizeof(struct dcn10_timing_generator), GFP_KERNEL); + struct optc *tgn10 = + kzalloc(sizeof(struct optc), GFP_KERNEL); if (!tgn10) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index 4940fdbc6e80..f73752c7de1a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -28,14 +28,14 @@ #include "dc.h" #define REG(reg)\ - tgn10->tg_regs->reg + optc1->tg_regs->reg #define CTX \ - tgn10->base.ctx + optc1->base.ctx #undef FN #define FN(reg_name, field_name) \ - tgn10->tg_shift->field_name, tgn10->tg_mask->field_name + optc1->tg_shift->field_name, optc1->tg_mask->field_name #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 @@ -45,8 +45,8 @@ * This is a workaround for a bug that has existed since R5xx and has not been * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. */ -static void tgn10_apply_front_porch_workaround( - struct timing_generator *tg, +static void optc1_apply_front_porch_workaround( + struct timing_generator *optc, struct dc_crtc_timing *timing) { if (timing->flags.INTERLACE == 1) { @@ -58,30 +58,30 @@ static void tgn10_apply_front_porch_workaround( } } -static void tgn10_program_global_sync( - struct timing_generator *tg) +void optc1_program_global_sync( + struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); - if (tg->dlg_otg_param.vstartup_start == 0) { + if (optc->dlg_otg_param.vstartup_start == 0) { BREAK_TO_DEBUGGER(); return; } REG_SET(OTG_VSTARTUP_PARAM, 0, - VSTARTUP_START, tg->dlg_otg_param.vstartup_start); + VSTARTUP_START, optc->dlg_otg_param.vstartup_start); REG_SET_2(OTG_VUPDATE_PARAM, 0, - VUPDATE_OFFSET, tg->dlg_otg_param.vupdate_offset, - VUPDATE_WIDTH, tg->dlg_otg_param.vupdate_width); + VUPDATE_OFFSET, optc->dlg_otg_param.vupdate_offset, + VUPDATE_WIDTH, optc->dlg_otg_param.vupdate_width); REG_SET(OTG_VREADY_PARAM, 0, - VREADY_OFFSET, tg->dlg_otg_param.vready_offset); + VREADY_OFFSET, optc->dlg_otg_param.vready_offset); } -static void tgn10_disable_stereo(struct timing_generator *tg) +static void optc1_disable_stereo(struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); REG_SET(OTG_STEREO_CONTROL, 0, OTG_STEREO_EN, 0); @@ -102,8 +102,8 @@ static void tgn10_disable_stereo(struct timing_generator *tg) * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. * Including SYNC. Call BIOS command table to program Timings. */ -static void tgn10_program_timing( - struct timing_generator *tg, +void optc1_program_timing( + struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing, bool use_vbios) { @@ -121,10 +121,10 @@ static void tgn10_program_timing( uint32_t h_div_2; int32_t vertical_line_start; - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); patched_crtc_timing = *dc_crtc_timing; - tgn10_apply_front_porch_workaround(tg, &patched_crtc_timing); + optc1_apply_front_porch_workaround(optc, &patched_crtc_timing); /* Load horizontal timing */ @@ -217,7 +217,7 @@ static void tgn10_program_timing( /* Use OTG_VERTICAL_INTERRUPT2 replace VUPDATE interrupt, * program the reg for interrupt postition. */ - vertical_line_start = asic_blank_end - tg->dlg_otg_param.vstartup_start + 1; + vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1; if (vertical_line_start < 0) { ASSERT(0); vertical_line_start = 0; @@ -233,23 +233,23 @@ static void tgn10_program_timing( OTG_V_SYNC_A_POL, v_sync_polarity); v_init = asic_blank_start; - if (tg->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT || - tg->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST || - tg->dlg_otg_param.signal == SIGNAL_TYPE_EDP) { + if (optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT || + optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST || + optc->dlg_otg_param.signal == SIGNAL_TYPE_EDP) { start_point = 1; if (patched_crtc_timing.flags.INTERLACE == 1) field_num = 1; } v_fp2 = 0; - if (tg->dlg_otg_param.vstartup_start > asic_blank_end) - v_fp2 = tg->dlg_otg_param.vstartup_start > asic_blank_end; + if (optc->dlg_otg_param.vstartup_start > asic_blank_end) + v_fp2 = optc->dlg_otg_param.vstartup_start > asic_blank_end; /* Interlace */ if (patched_crtc_timing.flags.INTERLACE == 1) { REG_UPDATE(OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, 1); v_init = v_init / 2; - if ((tg->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end) + if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end) v_fp2 = v_fp2 / 2; } else @@ -270,13 +270,13 @@ static void tgn10_program_timing( OTG_START_POINT_CNTL, start_point, OTG_FIELD_NUMBER_CNTL, field_num); - tgn10_program_global_sync(tg); + optc1_program_global_sync(optc); /* TODO * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 * program_horz_count_by_2 * for DVI 30bpp mode, 0 otherwise - * program_horz_count_by_2(tg, &patched_crtc_timing); + * program_horz_count_by_2(optc, &patched_crtc_timing); */ /* Enable stereo - only when we need to pack 3D frame. Other types @@ -290,9 +290,9 @@ static void tgn10_program_timing( } -static void tgn10_set_blank_data_double_buffer(struct timing_generator *tg, bool enable) +static void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; @@ -304,9 +304,9 @@ static void tgn10_set_blank_data_double_buffer(struct timing_generator *tg, bool * unblank_crtc * Call ASIC Control Object to UnBlank CRTC. */ -static void tgn10_unblank_crtc(struct timing_generator *tg) +static void optc1_unblank_crtc(struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); uint32_t vertical_interrupt_enable = 0; REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL, @@ -316,7 +316,7 @@ static void tgn10_unblank_crtc(struct timing_generator *tg) * this check will be removed. */ if (vertical_interrupt_enable) - tgn10_set_blank_data_double_buffer(tg, true); + optc1_set_blank_data_double_buffer(optc, true); REG_UPDATE_2(OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, 0, @@ -328,29 +328,29 @@ static void tgn10_unblank_crtc(struct timing_generator *tg) * Call ASIC Control Object to Blank CRTC. */ -static void tgn10_blank_crtc(struct timing_generator *tg) +static void optc1_blank_crtc(struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); REG_UPDATE_2(OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, 1, OTG_BLANK_DE_MODE, 0); - tgn10_set_blank_data_double_buffer(tg, false); + optc1_set_blank_data_double_buffer(optc, false); } -static void tgn10_set_blank(struct timing_generator *tg, +void optc1_set_blank(struct timing_generator *optc, bool enable_blanking) { if (enable_blanking) - tgn10_blank_crtc(tg); + optc1_blank_crtc(optc); else - tgn10_unblank_crtc(tg); + optc1_unblank_crtc(optc); } -static bool tgn10_is_blanked(struct timing_generator *tg) +bool optc1_is_blanked(struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); uint32_t blank_en; uint32_t blank_state; @@ -361,9 +361,9 @@ static bool tgn10_is_blanked(struct timing_generator *tg) return blank_en && blank_state; } -static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) +void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); if (enable) { REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, @@ -396,19 +396,19 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) * Enable CRTC * Enable CRTC - call ASIC Control Object to enable Timing generator. */ -static bool tgn10_enable_crtc(struct timing_generator *tg) +static bool optc1_enable_crtc(struct timing_generator *optc) { /* TODO FPGA wait for answer * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK */ - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); /* opp instance for OTG. For DCN1.0, ODM is remoed. * OPP and OPTC should 1:1 mapping */ REG_UPDATE(OPTC_DATA_SOURCE_SELECT, - OPTC_SRC_SEL, tg->inst); + OPTC_SRC_SEL, optc->inst); /* VTG enable first is for HW workaround */ REG_UPDATE(CONTROL, @@ -423,9 +423,9 @@ static bool tgn10_enable_crtc(struct timing_generator *tg) } /* disable_crtc - call ASIC Control Object to disable Timing generator. */ -static bool tgn10_disable_crtc(struct timing_generator *tg) +bool optc1_disable_crtc(struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); /* disable otg request until end of the first line * in the vertical blank region @@ -446,11 +446,11 @@ static bool tgn10_disable_crtc(struct timing_generator *tg) } -static void tgn10_program_blank_color( - struct timing_generator *tg, +void optc1_program_blank_color( + struct timing_generator *optc, const struct tg_color *black_color) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); REG_SET_3(OTG_BLACK_COLOR, 0, OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, @@ -458,15 +458,15 @@ static void tgn10_program_blank_color( OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); } -static bool tgn10_validate_timing( - struct timing_generator *tg, +bool optc1_validate_timing( + struct timing_generator *optc, const struct dc_crtc_timing *timing) { uint32_t interlace_factor; uint32_t v_blank; uint32_t h_blank; uint32_t min_v_blank; - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); ASSERT(timing != NULL); @@ -496,19 +496,19 @@ static bool tgn10_validate_timing( * needs more than 8192 horizontal and * more than 8192 vertical total pixels) */ - if (timing->h_total > tgn10->max_h_total || - timing->v_total > tgn10->max_v_total) + if (timing->h_total > optc1->max_h_total || + timing->v_total > optc1->max_v_total) return false; - if (h_blank < tgn10->min_h_blank) + if (h_blank < optc1->min_h_blank) return false; - if (timing->h_sync_width < tgn10->min_h_sync_width || - timing->v_sync_width < tgn10->min_v_sync_width) + if (timing->h_sync_width < optc1->min_h_sync_width || + timing->v_sync_width < optc1->min_v_sync_width) return false; - min_v_blank = timing->flags.INTERLACE?tgn10->min_v_blank_interlace:tgn10->min_v_blank; + min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; if (v_blank < min_v_blank) return false; @@ -525,15 +525,15 @@ static bool tgn10_validate_timing( * holds the counter of frames. * * @param - * struct timing_generator *tg - [in] timing generator which controls the + * struct timing_generator *optc - [in] timing generator which controls the * desired CRTC * * @return * Counter of frames, which should equal to number of vblanks. */ -static uint32_t tgn10_get_vblank_counter(struct timing_generator *tg) +uint32_t optc1_get_vblank_counter(struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); uint32_t frame_count; REG_GET(OTG_STATUS_FRAME_COUNT, @@ -542,34 +542,34 @@ static uint32_t tgn10_get_vblank_counter(struct timing_generator *tg) return frame_count; } -static void tgn10_lock(struct timing_generator *tg) +void optc1_lock(struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); REG_SET(OTG_GLOBAL_CONTROL0, 0, - OTG_MASTER_UPDATE_LOCK_SEL, tg->inst); + OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK, 1); /* Should be fast, status does not update on maximus */ - if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) REG_WAIT(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, 1, 1, 10); } -static void tgn10_unlock(struct timing_generator *tg) +void optc1_unlock(struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK, 0); } -static void tgn10_get_position(struct timing_generator *tg, +void optc1_get_position(struct timing_generator *optc, struct crtc_position *position) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); REG_GET_2(OTG_STATUS_POSITION, OTG_HORZ_COUNT, &position->horizontal_count, @@ -579,12 +579,12 @@ static void tgn10_get_position(struct timing_generator *tg, OTG_VERT_COUNT_NOM, &position->nominal_vcount); } -static bool tgn10_is_counter_moving(struct timing_generator *tg) +bool optc1_is_counter_moving(struct timing_generator *optc) { struct crtc_position position1, position2; - tg->funcs->get_position(tg, &position1); - tg->funcs->get_position(tg, &position2); + optc->funcs->get_position(optc, &position1); + optc->funcs->get_position(optc, &position2); if (position1.horizontal_count == position2.horizontal_count && position1.vertical_count == position2.vertical_count) @@ -593,10 +593,10 @@ static bool tgn10_is_counter_moving(struct timing_generator *tg) return true; } -static bool tgn10_did_triggered_reset_occur( - struct timing_generator *tg) +bool optc1_did_triggered_reset_occur( + struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); uint32_t occurred_force, occurred_vsync; REG_GET(OTG_FORCE_COUNT_NOW_CNTL, @@ -608,9 +608,9 @@ static bool tgn10_did_triggered_reset_occur( return occurred_vsync != 0 || occurred_force != 0; } -static void tgn10_disable_reset_trigger(struct timing_generator *tg) +void optc1_disable_reset_trigger(struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); REG_WRITE(OTG_TRIGA_CNTL, 0); @@ -621,9 +621,9 @@ static void tgn10_disable_reset_trigger(struct timing_generator *tg) OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); } -static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_tg_inst) +void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); uint32_t falling_edge; REG_GET(OTG_V_SYNC_A_CNTL, @@ -655,12 +655,12 @@ static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_t OTG_FORCE_COUNT_NOW_MODE, 2); } -void tgn10_enable_crtc_reset( - struct timing_generator *tg, +void optc1_enable_crtc_reset( + struct timing_generator *optc, int source_tg_inst, struct crtc_trigger_info *crtc_tp) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); uint32_t falling_edge = 0; uint32_t rising_edge = 0; @@ -700,10 +700,10 @@ void tgn10_enable_crtc_reset( } } -static void tgn10_wait_for_state(struct timing_generator *tg, +void optc1_wait_for_state(struct timing_generator *optc, enum crtc_state state) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); switch (state) { case CRTC_STATE_VBLANK: @@ -723,8 +723,8 @@ static void tgn10_wait_for_state(struct timing_generator *tg, } } -static void tgn10_set_early_control( - struct timing_generator *tg, +void optc1_set_early_control( + struct timing_generator *optc, uint32_t early_cntl) { /* asic design change, do not need this control @@ -733,11 +733,11 @@ static void tgn10_set_early_control( } -static void tgn10_set_static_screen_control( - struct timing_generator *tg, +void optc1_set_static_screen_control( + struct timing_generator *optc, uint32_t value) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); /* Bit 8 is no longer applicable in RV for PSR case, * set bit 8 to 0 if given @@ -762,11 +762,11 @@ static void tgn10_set_static_screen_control( * ***************************************************************************** */ -static void tgn10_set_drr( - struct timing_generator *tg, +void optc1_set_drr( + struct timing_generator *optc, const struct drr_params *params) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); if (params != NULL && params->vertical_total_max > 0 && @@ -799,15 +799,15 @@ static void tgn10_set_drr( } } -static void tgn10_set_test_pattern( - struct timing_generator *tg, +static void optc1_set_test_pattern( + struct timing_generator *optc, /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' * because this is not DP-specific (which is probably somewhere in DP * encoder) */ enum controller_dp_test_pattern test_pattern, enum dc_color_depth color_depth) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); enum test_pattern_color_format bit_depth; enum test_pattern_dyn_range dyn_range; enum test_pattern_mode mode; @@ -1058,21 +1058,21 @@ static void tgn10_set_test_pattern( } } -static void tgn10_get_crtc_scanoutpos( - struct timing_generator *tg, +void optc1_get_crtc_scanoutpos( + struct timing_generator *optc, uint32_t *v_blank_start, uint32_t *v_blank_end, uint32_t *h_position, uint32_t *v_position) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); struct crtc_position position; REG_GET_2(OTG_V_BLANK_START_END, OTG_V_BLANK_START, v_blank_start, OTG_V_BLANK_END, v_blank_end); - tgn10_get_position(tg, &position); + optc1_get_position(optc, &position); *h_position = position.horizontal_count; *v_position = position.vertical_count; @@ -1080,10 +1080,10 @@ static void tgn10_get_crtc_scanoutpos( -static void tgn10_enable_stereo(struct timing_generator *tg, +static void optc1_enable_stereo(struct timing_generator *optc, const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); uint32_t active_width = timing->h_addressable; uint32_t space1_size = timing->v_total - timing->v_addressable; @@ -1122,21 +1122,21 @@ static void tgn10_enable_stereo(struct timing_generator *tg, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size); } -static void tgn10_program_stereo(struct timing_generator *tg, +void optc1_program_stereo(struct timing_generator *optc, const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) { if (flags->PROGRAM_STEREO) - tgn10_enable_stereo(tg, timing, flags); + optc1_enable_stereo(optc, timing, flags); else - tgn10_disable_stereo(tg); + optc1_disable_stereo(optc); } -static bool tgn10_is_stereo_left_eye(struct timing_generator *tg) +bool optc1_is_stereo_left_eye(struct timing_generator *optc) { bool ret = false; uint32_t left_eye = 0; - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); REG_GET(OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, &left_eye); @@ -1148,7 +1148,7 @@ static bool tgn10_is_stereo_left_eye(struct timing_generator *tg) return ret; } -void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, +void optc1_read_otg_state(struct optc *optc1, struct dcn_otg_state *s) { REG_GET(OTG_CONTROL, @@ -1192,22 +1192,22 @@ void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); } -static void tgn10_clear_optc_underflow(struct timing_generator *tg) +static void optc1_clear_optc_underflow(struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); } -static void tgn10_tg_init(struct timing_generator *tg) +static void optc1_tg_init(struct timing_generator *optc) { - tgn10_set_blank_data_double_buffer(tg, true); - tgn10_clear_optc_underflow(tg); + optc1_set_blank_data_double_buffer(optc, true); + optc1_clear_optc_underflow(optc); } -static bool tgn10_is_tg_enabled(struct timing_generator *tg) +static bool optc1_is_tg_enabled(struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); uint32_t otg_enabled = 0; REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); @@ -1216,9 +1216,9 @@ static bool tgn10_is_tg_enabled(struct timing_generator *tg) } -static bool tgn10_is_optc_underflow_occurred(struct timing_generator *tg) +static bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) { - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + struct optc *optc1 = DCN10TG_FROM_TG(optc); uint32_t underflow_occurred = 0; REG_GET(OPTC_INPUT_GLOBAL_CONTROL, @@ -1229,51 +1229,51 @@ static bool tgn10_is_optc_underflow_occurred(struct timing_generator *tg) } static const struct timing_generator_funcs dcn10_tg_funcs = { - .validate_timing = tgn10_validate_timing, - .program_timing = tgn10_program_timing, - .program_global_sync = tgn10_program_global_sync, - .enable_crtc = tgn10_enable_crtc, - .disable_crtc = tgn10_disable_crtc, + .validate_timing = optc1_validate_timing, + .program_timing = optc1_program_timing, + .program_global_sync = optc1_program_global_sync, + .enable_crtc = optc1_enable_crtc, + .disable_crtc = optc1_disable_crtc, /* used by enable_timing_synchronization. Not need for FPGA */ - .is_counter_moving = tgn10_is_counter_moving, - .get_position = tgn10_get_position, - .get_frame_count = tgn10_get_vblank_counter, - .get_scanoutpos = tgn10_get_crtc_scanoutpos, - .set_early_control = tgn10_set_early_control, + .is_counter_moving = optc1_is_counter_moving, + .get_position = optc1_get_position, + .get_frame_count = optc1_get_vblank_counter, + .get_scanoutpos = optc1_get_crtc_scanoutpos, + .set_early_control = optc1_set_early_control, /* used by enable_timing_synchronization. Not need for FPGA */ - .wait_for_state = tgn10_wait_for_state, - .set_blank = tgn10_set_blank, - .is_blanked = tgn10_is_blanked, - .set_blank_color = tgn10_program_blank_color, - .did_triggered_reset_occur = tgn10_did_triggered_reset_occur, - .enable_reset_trigger = tgn10_enable_reset_trigger, - .enable_crtc_reset = tgn10_enable_crtc_reset, - .disable_reset_trigger = tgn10_disable_reset_trigger, - .lock = tgn10_lock, - .unlock = tgn10_unlock, - .enable_optc_clock = tgn10_enable_optc_clock, - .set_drr = tgn10_set_drr, - .set_static_screen_control = tgn10_set_static_screen_control, - .set_test_pattern = tgn10_set_test_pattern, - .program_stereo = tgn10_program_stereo, - .is_stereo_left_eye = tgn10_is_stereo_left_eye, - .set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer, - .tg_init = tgn10_tg_init, - .is_tg_enabled = tgn10_is_tg_enabled, - .is_optc_underflow_occurred = tgn10_is_optc_underflow_occurred, - .clear_optc_underflow = tgn10_clear_optc_underflow, + .wait_for_state = optc1_wait_for_state, + .set_blank = optc1_set_blank, + .is_blanked = optc1_is_blanked, + .set_blank_color = optc1_program_blank_color, + .did_triggered_reset_occur = optc1_did_triggered_reset_occur, + .enable_reset_trigger = optc1_enable_reset_trigger, + .enable_crtc_reset = optc1_enable_crtc_reset, + .disable_reset_trigger = optc1_disable_reset_trigger, + .lock = optc1_lock, + .unlock = optc1_unlock, + .enable_optc_clock = optc1_enable_optc_clock, + .set_drr = optc1_set_drr, + .set_static_screen_control = optc1_set_static_screen_control, + .set_test_pattern = optc1_set_test_pattern, + .program_stereo = optc1_program_stereo, + .is_stereo_left_eye = optc1_is_stereo_left_eye, + .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, + .tg_init = optc1_tg_init, + .is_tg_enabled = optc1_is_tg_enabled, + .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, + .clear_optc_underflow = optc1_clear_optc_underflow, }; -void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10) +void dcn10_timing_generator_init(struct optc *optc1) { - tgn10->base.funcs = &dcn10_tg_funcs; + optc1->base.funcs = &dcn10_tg_funcs; - tgn10->max_h_total = tgn10->tg_mask->OTG_H_TOTAL + 1; - tgn10->max_v_total = tgn10->tg_mask->OTG_V_TOTAL + 1; + optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; + optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; - tgn10->min_h_blank = 32; - tgn10->min_v_blank = 3; - tgn10->min_v_blank_interlace = 5; - tgn10->min_h_sync_width = 8; - tgn10->min_v_sync_width = 1; + optc1->min_h_blank = 32; + optc1->min_v_blank = 3; + optc1->min_v_blank_interlace = 5; + optc1->min_h_sync_width = 8; + optc1->min_v_sync_width = 1; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h index bb1cbfdc3554..a9ce97fd7f09 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h @@ -29,7 +29,7 @@ #include "timing_generator.h" #define DCN10TG_FROM_TG(tg)\ - container_of(tg, struct dcn10_timing_generator, base) + container_of(tg, struct optc, base) #define TG_COMMON_REG_LIST_DCN(inst) \ SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ @@ -84,7 +84,7 @@ SRI(OTG_TEST_PATTERN_COLOR, OTG, inst) -struct dcn_tg_registers { +struct dcn_optc_registers { uint32_t OTG_VERT_SYNC_CONTROL; uint32_t OTG_MASTER_UPDATE_MODE; uint32_t OTG_GSL_CONTROL; @@ -348,20 +348,20 @@ struct dcn_tg_registers { type OTG_GSL_FORCE_DELAY;\ type OTG_GSL_CHECK_ALL_FIELDS; -struct dcn_tg_shift { +struct dcn_optc_shift { TG_REG_FIELD_LIST(uint8_t) }; -struct dcn_tg_mask { +struct dcn_optc_mask { TG_REG_FIELD_LIST(uint32_t) }; -struct dcn10_timing_generator { +struct optc { struct timing_generator base; - const struct dcn_tg_registers *tg_regs; - const struct dcn_tg_shift *tg_shift; - const struct dcn_tg_mask *tg_mask; + const struct dcn_optc_registers *tg_regs; + const struct dcn_optc_shift *tg_shift; + const struct dcn_optc_mask *tg_mask; enum controller_id controller_id; @@ -376,7 +376,7 @@ struct dcn10_timing_generator { uint32_t min_v_blank_interlace; }; -void dcn10_timing_generator_init(struct dcn10_timing_generator *tg); +void dcn10_timing_generator_init(struct optc *optc); struct dcn_otg_state { uint32_t v_blank_start; @@ -397,7 +397,77 @@ struct dcn_otg_state { uint32_t otg_enabled; }; -void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, +void optc1_read_otg_state(struct optc *optc1, struct dcn_otg_state *s); +bool optc1_validate_timing( + struct timing_generator *optc, + const struct dc_crtc_timing *timing); + +void optc1_program_timing( + struct timing_generator *optc, + const struct dc_crtc_timing *dc_crtc_timing, + bool use_vbios); + +void optc1_program_global_sync( + struct timing_generator *optc); + +bool optc1_disable_crtc(struct timing_generator *optc); + +bool optc1_is_counter_moving(struct timing_generator *optc); + +void optc1_get_position(struct timing_generator *optc, + struct crtc_position *position); + +uint32_t optc1_get_vblank_counter(struct timing_generator *optc); + +void optc1_get_crtc_scanoutpos( + struct timing_generator *optc, + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position); + +void optc1_set_early_control( + struct timing_generator *optc, + uint32_t early_cntl); + +void optc1_wait_for_state(struct timing_generator *optc, + enum crtc_state state); + +void optc1_set_blank(struct timing_generator *optc, + bool enable_blanking); + +bool optc1_is_blanked(struct timing_generator *optc); + +void optc1_program_blank_color( + struct timing_generator *optc, + const struct tg_color *black_color); + +bool optc1_did_triggered_reset_occur( + struct timing_generator *optc); + +void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst); + +void optc1_disable_reset_trigger(struct timing_generator *optc); + +void optc1_lock(struct timing_generator *optc); + +void optc1_unlock(struct timing_generator *optc); + +void optc1_enable_optc_clock(struct timing_generator *optc, bool enable); + +void optc1_set_drr( + struct timing_generator *optc, + const struct drr_params *params); + +void optc1_set_static_screen_control( + struct timing_generator *optc, + uint32_t value); + +void optc1_program_stereo(struct timing_generator *optc, + const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); + +bool optc1_is_stereo_left_eye(struct timing_generator *optc); + #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */ -- GitLab From 508f60e36a4288beb920b921924742c2b3e12a0d Mon Sep 17 00:00:00 2001 From: Vitaly Prosyak Date: Fri, 24 Nov 2017 15:52:33 -0600 Subject: [PATCH 1505/2547] drm/amd/display: Correct fixed point calculation. When convert from fixed31_32 to other fixed point format use math operation round instead of floor. Signed-off-by: Vitaly Prosyak Reviewed-by: Roman Li Reviewed-by: Krunoslav Kovac Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/basics/conversion.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/basics/conversion.c b/drivers/gpu/drm/amd/display/dc/basics/conversion.c index 23c9a0ec0181..310964915a83 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/conversion.c +++ b/drivers/gpu/drm/amd/display/dc/basics/conversion.c @@ -46,7 +46,7 @@ uint16_t fixed_point_to_int_frac( arg)); if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor)) - numerator = (uint16_t)dal_fixed31_32_floor( + numerator = (uint16_t)dal_fixed31_32_round( dal_fixed31_32_mul_int( arg, divisor)); -- GitLab From 043b19bdedf5d76d4a614f508baaf83aaf7c4b6e Mon Sep 17 00:00:00 2001 From: Eric Bernstein Date: Mon, 27 Nov 2017 10:55:52 -0500 Subject: [PATCH 1506/2547] drm/amd/display: use REG_UPDATE for MPC mux Use REG_UPDATE instead of REG_SET for programming MPC out mux. Signed-off-by: Eric Bernstein Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index 1e72bd42dca4..179890b1a8c4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -218,7 +218,7 @@ struct mpcc *mpc1_insert_plane( if (tree->opp_list == insert_above_mpcc) { /* insert the toppest mpcc */ tree->opp_list = new_mpcc; - REG_SET(MUX[tree->opp_id], 0, MPC_OUT_MUX, mpcc_id); + REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id); } else { /* find insert position */ struct mpcc *temp_mpcc = tree->opp_list; @@ -275,11 +275,11 @@ void mpc1_remove_mpcc( if (mpcc_to_remove->mpcc_bot) { /* set the next MPCC in list to be the top MPCC */ tree->opp_list = mpcc_to_remove->mpcc_bot; - REG_SET(MUX[tree->opp_id], 0, MPC_OUT_MUX, tree->opp_list->mpcc_id); + REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id); } else { /* there are no other MPCC is list */ tree->opp_list = NULL; - REG_SET(MUX[tree->opp_id], 0, MPC_OUT_MUX, 0xf); + REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf); } } else { /* find mpcc to remove MPCC list */ @@ -359,7 +359,7 @@ void mpc1_mpc_init(struct mpc *mpc) for (opp_id = 0; opp_id < MAX_OPP; opp_id++) { if (REG(MUX[opp_id])) - REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, 0xf); + REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf); } } -- GitLab From f23d558466cf14e58ec7f666a3af1a6708681bcc Mon Sep 17 00:00:00 2001 From: Eric Bernstein Date: Fri, 24 Nov 2017 17:51:34 -0500 Subject: [PATCH 1507/2547] drm/amd/display: Move OPP mpc tree initialization to hw_init Move OPP initialization of mpc tree parameters to hw_init function. Signed-off-by: Eric Bernstein Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 7 ------- drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 + 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7ec87fcb22be..f0be2b872668 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -782,6 +782,8 @@ static void dcn10_init_hw(struct dc *dc) hubp->opp_id = 0xf; hubp->power_gated = false; + dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; + dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; dc->res_pool->opps[i]->mpcc_disconnect_pending[i] = true; pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index 20d78cf46ab0..5f078868676c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -330,18 +330,11 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10, const struct dcn10_opp_shift *opp_shift, const struct dcn10_opp_mask *opp_mask) { - int i; oppn10->base.ctx = ctx; oppn10->base.inst = inst; oppn10->base.funcs = &dcn10_opp_funcs; - oppn10->base.mpc_tree_params.opp_id = inst; - oppn10->base.mpc_tree_params.opp_list = NULL; - - for (i = 0; i < MAX_PIPES; i++) - oppn10->base.mpcc_disconnect_pending[i] = false; - oppn10->regs = regs; oppn10->opp_shift = opp_shift; oppn10->opp_mask = opp_mask; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 42f2bb29a5fc..6da125de9507 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -300,6 +300,7 @@ struct opp_funcs { struct output_pixel_processor *opp, bool enable, bool polarity); + }; #endif -- GitLab From 73da927b083737a8923c1bbc850274adffca1257 Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Fri, 10 Nov 2017 10:44:24 -0500 Subject: [PATCH 1508/2547] drm/amd/display: fix missing pixel clock adjustment for dongle Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Reviewed-by: Andrew Jiang Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 0b7058fddc2e..13995893cac5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1801,7 +1801,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal) link->link_enc->funcs->disable_output(link->link_enc, signal); } -bool dp_active_dongle_validate_timing( +static bool dp_active_dongle_validate_timing( const struct dc_crtc_timing *timing, const struct dc_dongle_caps *dongle_caps) { @@ -1833,6 +1833,8 @@ bool dp_active_dongle_validate_timing( /* Check Color Depth and Pixel Clock */ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) required_pix_clk /= 2; + else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) + required_pix_clk = required_pix_clk * 2 / 3; switch (timing->display_color_depth) { case COLOR_DEPTH_666: -- GitLab From 904623ee5936e2226009b2f238f28781aecd2565 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Fri, 24 Nov 2017 16:31:03 -0500 Subject: [PATCH 1509/2547] drm/amd/display: Move wait for hpd ready out from edp power control. It may take over 200ms for wait hpd ready. To optimize the resume time, we can power on eDP in init_hw, wait for hpd ready when doing link training. also create separate eDP enable function to make sure eDP is powered up before doing and DPCD access, as HPD low will result in DPDC transaction failure. After optimization, setpowerstate 145ms -> 9.8ms, DPMS 387ms -> 18.9ms Signed-off-by: Yongqiang Sun Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 25 ++++++++++++++++++- .../drm/amd/display/dc/core/dc_link_hwss.c | 11 +------- .../drm/amd/display/dc/dce/dce_link_encoder.c | 15 ----------- .../display/dc/dce110/dce110_hw_sequencer.c | 16 +++--------- .../display/dc/dce110/dce110_hw_sequencer.h | 4 +++ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++- .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 + 7 files changed, 36 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 13995893cac5..00130152f366 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1271,6 +1271,24 @@ static enum dc_status enable_link_dp( return status; } +static enum dc_status enable_link_edp( + struct dc_state *state, + struct pipe_ctx *pipe_ctx) +{ + enum dc_status status; + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->sink->link; + + link->dc->hwss.edp_power_control(link, true); + link->dc->hwss.edp_wait_for_hpd_ready(link, true); + + status = enable_link_dp(state, pipe_ctx); + + link->dc->hwss.edp_backlight_control(link, true); + + return status; +} + static enum dc_status enable_link_dp_mst( struct dc_state *state, struct pipe_ctx *pipe_ctx) @@ -1746,9 +1764,11 @@ static enum dc_status enable_link( enum dc_status status = DC_ERROR_UNEXPECTED; switch (pipe_ctx->stream->signal) { case SIGNAL_TYPE_DISPLAY_PORT: - case SIGNAL_TYPE_EDP: status = enable_link_dp(state, pipe_ctx); break; + case SIGNAL_TYPE_EDP: + status = enable_link_edp(state, pipe_ctx); + break; case SIGNAL_TYPE_DISPLAY_PORT_MST: status = enable_link_dp_mst(state, pipe_ctx); msleep(200); @@ -2282,6 +2302,9 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option) if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) deallocate_mst_payload(pipe_ctx); + if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) + core_dc->hwss.edp_backlight_control(pipe_ctx->stream->sink->link, false); + core_dc->hwss.disable_stream(pipe_ctx, option); disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index f2902569be2e..2096f2a179f2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -88,15 +88,7 @@ void dp_enable_link_phy( } if (dc_is_dp_sst_signal(signal)) { - if (signal == SIGNAL_TYPE_EDP) { - link->dc->hwss.edp_power_control(link, true); - link_enc->funcs->enable_dp_output( - link_enc, - link_settings, - clock_source); - link->dc->hwss.edp_backlight_control(link, true); - } else - link_enc->funcs->enable_dp_output( + link_enc->funcs->enable_dp_output( link_enc, link_settings, clock_source); @@ -138,7 +130,6 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) dp_receiver_power_ctrl(link, false); if (signal == SIGNAL_TYPE_EDP) { - link->dc->hwss.edp_backlight_control(link, false); edp_receiver_ready_T9(link); link->link_enc->funcs->disable_output(link->link_enc, signal); link->dc->hwss.edp_power_control(link, false); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index bad70c6b3aad..a266e3f5e75f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1072,21 +1072,6 @@ void dce110_link_encoder_disable_output( /* disable encoder */ if (dc_is_dp_signal(signal)) link_encoder_disable(enc110); - - /* - * TODO: Power control cause regression, we should implement - * it properly, for now just comment it. - */ -// if (enc110->base.connector.id == CONNECTOR_ID_EDP) { -// /* power down eDP panel */ -// link_encoder_edp_wait_for_hpd_ready( -// enc, -// enc->connector, -// false); -// -// link_encoder_edp_power_control( -// enc, false); -// } } void dce110_link_encoder_dp_set_lane_settings( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 21fc27aab909..dd8386778361 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -870,8 +870,6 @@ void hwss_edp_power_control( "%s: Skipping Panel Power action: %s\n", __func__, (power_up ? "On":"Off")); } - - hwss_edp_wait_for_hpd_ready(link, true); } /*todo: cloned in stream enc, fix*/ @@ -972,11 +970,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) } /* blank at encoder level */ - if (dc_is_dp_signal(pipe_ctx->stream->signal)) { - if (pipe_ctx->stream->sink->link->connector_signal == SIGNAL_TYPE_EDP) - hwss_edp_backlight_control(link, false); + if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); - } + link->link_enc->funcs->connect_dig_be_to_fe( link->link_enc, pipe_ctx->stream_res.stream_enc->id, @@ -988,15 +984,12 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings) { struct encoder_unblank_param params = { { 0 } }; - struct dc_link *link = pipe_ctx->stream->sink->link; /* only 3 items below are used by unblank */ params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz; params.link_settings.link_rate = link_settings->link_rate; pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); - if (link->connector_signal == SIGNAL_TYPE_EDP) - hwss_edp_backlight_control(link, true); } @@ -1342,10 +1335,8 @@ static void power_down_encoders(struct dc *dc) if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) dp_receiver_power_ctrl(dc->links[i], false); - if (connector_id == CONNECTOR_ID_EDP) { + if (connector_id == CONNECTOR_ID_EDP) signal = SIGNAL_TYPE_EDP; - hwss_edp_backlight_control(dc->links[i], false); - } } dc->links[i]->link_enc->funcs->disable_output( @@ -2976,6 +2967,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .pplib_apply_display_requirements = pplib_apply_display_requirements, .edp_backlight_control = hwss_edp_backlight_control, .edp_power_control = hwss_edp_power_control, + .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, }; void dce110_hw_sequencer_construct(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index 2dd6ac637572..fc637647f643 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -77,5 +77,9 @@ void hwss_edp_backlight_control( struct dc_link *link, bool enable); +void hwss_edp_wait_for_hpd_ready( + struct dc_link *link, + bool power_up); + #endif /* __DC_HWSS_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index f0be2b872668..31fd6ae8f61f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2368,7 +2368,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .pplib_apply_display_requirements = dcn10_pplib_apply_display_requirements, .edp_backlight_control = hwss_edp_backlight_control, - .edp_power_control = hwss_edp_power_control + .edp_power_control = hwss_edp_power_control, + .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 03431134c088..b6215ba514d8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -199,6 +199,7 @@ struct hw_sequencer_funcs { void (*edp_backlight_control)( struct dc_link *link, bool enable); + void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); }; -- GitLab From 51ca0b036223660e0db10e2bf6097a0689f5fa44 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Tue, 28 Nov 2017 12:05:08 -0500 Subject: [PATCH 1510/2547] drm/amd/display: remove format_control from set_cursor_attributes Signed-off-by: Yue Hin Lau Reviewed-by: Eric Bernstein Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 6db1839d7155..f2a08b156cf0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -400,13 +400,6 @@ void dpp1_set_cursor_attributes( REG_UPDATE(CURSOR0_COLOR1, CUR0_COLOR1, 0xFFFFFFFF); } - - /* TODO: Fixed vs float */ - - REG_UPDATE_3(FORMAT_CONTROL, - CNVC_BYPASS, 0, - FORMAT_CONTROL__ALPHA_EN, 1, - FORMAT_EXPANSION_MODE, 0); } -- GitLab From 78b56c52349596374dd47584d1f1db4d08609b7b Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 28 Nov 2017 16:20:45 -0500 Subject: [PATCH 1511/2547] drm/amd/display: use clamping rather than truncation for CM fp conversions Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/basics/fixpt31_32.c | 24 +++++++++++++++---- .../amd/display/dc/dcn10/dcn10_cm_common.c | 14 +++++------ .../gpu/drm/amd/display/include/fixed31_32.h | 4 ++-- 3 files changed, 29 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c index 13f8b8c02212..011a97f82fb6 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c +++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c @@ -554,6 +554,22 @@ static inline uint32_t ux_dy( return result | fractional_part; } +static inline uint32_t clamp_ux_dy( + int64_t value, + uint32_t integer_bits, + uint32_t fractional_bits, + uint32_t min_clamp) +{ + uint32_t truncated_val = ux_dy(value, integer_bits, fractional_bits); + + if (value >= (1LL << (integer_bits + FIXED31_32_BITS_PER_FRACTIONAL_PART))) + return (1 << (integer_bits + fractional_bits)) - 1; + else if (truncated_val > min_clamp) + return truncated_val; + else + return min_clamp; +} + uint32_t dal_fixed31_32_u2d19( struct fixed31_32 arg) { @@ -566,14 +582,14 @@ uint32_t dal_fixed31_32_u0d19( return ux_dy(arg.value, 0, 19); } -uint32_t dal_fixed31_32_u0d14( +uint32_t dal_fixed31_32_clamp_u0d14( struct fixed31_32 arg) { - return ux_dy(arg.value, 1, 14); + return clamp_ux_dy(arg.value, 0, 14, 1); } -uint32_t dal_fixed31_32_u0d10( +uint32_t dal_fixed31_32_clamp_u0d10( struct fixed31_32 arg) { - return ux_dy(arg.value, 1, 10); + return clamp_ux_dy(arg.value, 0, 10, 1); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c index 352ae7bf9a3f..53ba3600ee6a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c @@ -169,7 +169,7 @@ bool cm_helper_convert_to_custom_float( } if (fixpoint == true) - arr_points[1].custom_float_y = dal_fixed31_32_u0d14(arr_points[1].y); + arr_points[1].custom_float_y = dal_fixed31_32_clamp_u0d14(arr_points[1].y); else if (!convert_to_custom_float_format(arr_points[1].y, &fmt, &arr_points[1].custom_float_y)) { BREAK_TO_DEBUGGER(); @@ -395,12 +395,12 @@ bool cm_helper_translate_curve_to_hw_format( rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue); if (fixpoint == true) { - rgb->delta_red_reg = dal_fixed31_32_u0d10(rgb->delta_red); - rgb->delta_green_reg = dal_fixed31_32_u0d10(rgb->delta_green); - rgb->delta_blue_reg = dal_fixed31_32_u0d10(rgb->delta_blue); - rgb->red_reg = dal_fixed31_32_u0d14(rgb->red); - rgb->green_reg = dal_fixed31_32_u0d14(rgb->green); - rgb->blue_reg = dal_fixed31_32_u0d14(rgb->blue); + rgb->delta_red_reg = dal_fixed31_32_clamp_u0d10(rgb->delta_red); + rgb->delta_green_reg = dal_fixed31_32_clamp_u0d10(rgb->delta_green); + rgb->delta_blue_reg = dal_fixed31_32_clamp_u0d10(rgb->delta_blue); + rgb->red_reg = dal_fixed31_32_clamp_u0d14(rgb->red); + rgb->green_reg = dal_fixed31_32_clamp_u0d14(rgb->green); + rgb->blue_reg = dal_fixed31_32_clamp_u0d14(rgb->blue); } ++rgb_plus_1; diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h index c4848fadc70e..4badaedbaadd 100644 --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h @@ -464,10 +464,10 @@ uint32_t dal_fixed31_32_u0d19( struct fixed31_32 arg); -uint32_t dal_fixed31_32_u0d14( +uint32_t dal_fixed31_32_clamp_u0d14( struct fixed31_32 arg); -uint32_t dal_fixed31_32_u0d10( +uint32_t dal_fixed31_32_clamp_u0d10( struct fixed31_32 arg); #endif -- GitLab From 5b92d9d409e742ca09a4cb924e3f781eddbf7d81 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 22 Nov 2017 21:05:55 -0500 Subject: [PATCH 1512/2547] drm/amd/display: Remove redundant NULL check in DCE11 HWSS We already check this a couple lines earlier. Signed-off-by: Harry Wentland Reviewed-by: Jordan Lazare Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index dd8386778361..80d36610c302 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2017,8 +2017,7 @@ enum dc_status dce110_apply_ctx_to_hw( if (pipe_ctx->stream == pipe_ctx_old->stream) continue; - if (pipe_ctx->stream && pipe_ctx_old->stream - && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) + if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) continue; if (pipe_ctx->top_pipe) -- GitLab From aff10cfe646b975b358b01f0f8469c76a9f153da Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 23 Nov 2017 10:31:50 -0500 Subject: [PATCH 1513/2547] drm/amd/display: Remove grph_object_id.c and move function to bios_parser Signed-off-by: Harry Wentland Reviewed-by: Jordan Lazare Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/basics/Makefile | 2 +- .../amd/display/dc/basics/grph_object_id.c | 75 ------------------- .../gpu/drm/amd/display/dc/bios/bios_parser.c | 46 ++++++++++++ .../drm/amd/display/include/grph_object_id.h | 4 - 4 files changed, 47 insertions(+), 80 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c diff --git a/drivers/gpu/drm/amd/display/dc/basics/Makefile b/drivers/gpu/drm/amd/display/dc/basics/Makefile index 6af8c8a9ad80..bca33bd9a0d2 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/Makefile +++ b/drivers/gpu/drm/amd/display/dc/basics/Makefile @@ -24,7 +24,7 @@ # It provides the general basic services required by other DAL # subcomponents. -BASICS = conversion.o fixpt31_32.o fixpt32_32.o grph_object_id.o \ +BASICS = conversion.o fixpt31_32.o fixpt32_32.o \ logger.o log_helpers.o vector.o AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS)) diff --git a/drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c b/drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c deleted file mode 100644 index 147822545252..000000000000 --- a/drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "include/grph_object_id.h" - -static bool dal_graphics_object_id_is_valid(struct graphics_object_id id) -{ - bool rc = true; - - switch (id.type) { - case OBJECT_TYPE_UNKNOWN: - rc = false; - break; - case OBJECT_TYPE_GPU: - case OBJECT_TYPE_ENGINE: - /* do NOT check for id.id == 0 */ - if (id.enum_id == ENUM_ID_UNKNOWN) - rc = false; - break; - default: - if (id.id == 0 || id.enum_id == ENUM_ID_UNKNOWN) - rc = false; - break; - } - - return rc; -} - -bool dal_graphics_object_id_is_equal( - struct graphics_object_id id1, - struct graphics_object_id id2) -{ - if (false == dal_graphics_object_id_is_valid(id1)) { - dm_output_to_console( - "%s: Warning: comparing invalid object 'id1'!\n", __func__); - return false; - } - - if (false == dal_graphics_object_id_is_valid(id2)) { - dm_output_to_console( - "%s: Warning: comparing invalid object 'id2'!\n", __func__); - return false; - } - - if (id1.id == id2.id && id1.enum_id == id2.enum_id - && id1.type == id2.type) - return true; - - return false; -} - - diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 86e6438c5cf3..21fb78e8048d 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -2254,6 +2254,52 @@ static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, return BP_RESULT_OK; } +static bool dal_graphics_object_id_is_valid(struct graphics_object_id id) +{ + bool rc = true; + + switch (id.type) { + case OBJECT_TYPE_UNKNOWN: + rc = false; + break; + case OBJECT_TYPE_GPU: + case OBJECT_TYPE_ENGINE: + /* do NOT check for id.id == 0 */ + if (id.enum_id == ENUM_ID_UNKNOWN) + rc = false; + break; + default: + if (id.id == 0 || id.enum_id == ENUM_ID_UNKNOWN) + rc = false; + break; + } + + return rc; +} + +static bool dal_graphics_object_id_is_equal( + struct graphics_object_id id1, + struct graphics_object_id id2) +{ + if (false == dal_graphics_object_id_is_valid(id1)) { + dm_output_to_console( + "%s: Warning: comparing invalid object 'id1'!\n", __func__); + return false; + } + + if (false == dal_graphics_object_id_is_valid(id2)) { + dm_output_to_console( + "%s: Warning: comparing invalid object 'id2'!\n", __func__); + return false; + } + + if (id1.id == id2.id && id1.enum_id == id2.enum_id + && id1.type == id2.type) + return true; + + return false; +} + static ATOM_OBJECT *get_bios_object(struct bios_parser *bp, struct graphics_object_id id) { diff --git a/drivers/gpu/drm/amd/display/include/grph_object_id.h b/drivers/gpu/drm/amd/display/include/grph_object_id.h index 03a7a9ca95ea..c4197432eb7c 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_id.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_id.h @@ -233,10 +233,6 @@ static inline struct graphics_object_id dal_graphics_object_id_init( return result; } -bool dal_graphics_object_id_is_equal( - struct graphics_object_id id1, - struct graphics_object_id id2); - /* Based on internal data members memory layout */ static inline uint32_t dal_graphics_object_id_to_uint( struct graphics_object_id id) -- GitLab From cf3d1a8c77a1c24085932b8f8260357a0d88a02b Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 23 Nov 2017 10:37:29 -0500 Subject: [PATCH 1514/2547] drm/amd/display: Add TODO item to remove vector.c Signed-off-by: Harry Wentland Reviewed-by: Jordan Lazare Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/TODO | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/TODO b/drivers/gpu/drm/amd/display/TODO index 46464678f2b3..357d59648401 100644 --- a/drivers/gpu/drm/amd/display/TODO +++ b/drivers/gpu/drm/amd/display/TODO @@ -105,3 +105,6 @@ useless with filtering output. dynamic debug printing might be an option. 20. Use kernel i2c device to program HDMI retimer. Some boards have an HDMI retimer that we need to program to pass PHY compliance. Currently that's bypassing the i2c device and goes directly to HW. This should be changed. + +21. Remove vector.c from dc/basics. It's used in DDC code which can probably +be simplified enough to no longer need a vector implementation. -- GitLab From a53d45d8e40a39a5c34ce5257359614d41529048 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Tue, 28 Nov 2017 10:10:48 -0500 Subject: [PATCH 1515/2547] drm/amd/display: dal 3.1.25 Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 939fa6f85826..3b49ca3027b6 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.24" +#define DC_VER "3.1.25" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- GitLab From 196f74897ba79f6d586894519f09796447d95be5 Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Wed, 13 Dec 2017 14:22:54 +0800 Subject: [PATCH 1516/2547] drm/amdgpu: add enumerate for PDB/PTB v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v2: remove SUBPTB member v3: remove last_level, use AMDGPU_VM_PTB directly instead. Signed-off-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 69 +++++++++++++++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 11 ++++ 2 files changed, 61 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 709587d8a77f..564e1b1962f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -148,12 +148,23 @@ struct amdgpu_prt_cb { static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, unsigned level) { - if (level != adev->vm_manager.num_level) - return 9 * (adev->vm_manager.num_level - level - 1) + + unsigned shift = 0xff; + + switch (level) { + case AMDGPU_VM_PDB2: + case AMDGPU_VM_PDB1: + case AMDGPU_VM_PDB0: + shift = 9 * (AMDGPU_VM_PDB0 - level) + adev->vm_manager.block_size; - else - /* For the page tables on the leaves */ - return 0; + break; + case AMDGPU_VM_PTB: + shift = 0; + break; + default: + dev_err(adev->dev, "the level%d isn't supported.\n", level); + } + + return shift; } /** @@ -166,12 +177,13 @@ static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, unsigned level) { - unsigned shift = amdgpu_vm_level_shift(adev, 0); + unsigned shift = amdgpu_vm_level_shift(adev, + adev->vm_manager.root_level); - if (level == 0) + if (level == adev->vm_manager.root_level) /* For the root directory */ return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift; - else if (level != adev->vm_manager.num_level) + else if (level != AMDGPU_VM_PTB) /* Everything in between */ return 512; else @@ -343,7 +355,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, if (vm->pte_support_ats) { init_value = AMDGPU_PTE_DEFAULT_ATC; - if (level != adev->vm_manager.num_level) + if (level != AMDGPU_VM_PTB) init_value |= AMDGPU_PDE_PTE; } @@ -385,7 +397,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, spin_unlock(&vm->status_lock); } - if (level < adev->vm_manager.num_level) { + if (level < AMDGPU_VM_PTB) { uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; uint64_t sub_eaddr = (pt_idx == to) ? eaddr : ((1 << shift) - 1); @@ -431,7 +443,8 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, saddr /= AMDGPU_GPU_PAGE_SIZE; eaddr /= AMDGPU_GPU_PAGE_SIZE; - return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0); + return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, + adev->vm_manager.root_level); } /** @@ -1091,6 +1104,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, for (level = 0, pbo = parent->base.bo->parent; pbo; ++level) pbo = pbo->parent; + level += params->adev->vm_manager.root_level; pt = amdgpu_bo_gpu_offset(bo); flags = AMDGPU_PTE_VALID; amdgpu_gart_get_vm_pde(params->adev, level, &pt, &flags); @@ -1247,7 +1261,8 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev, return 0; error: - amdgpu_vm_invalidate_level(adev, vm, &vm->root, 0); + amdgpu_vm_invalidate_level(adev, vm, &vm->root, + adev->vm_manager.root_level); amdgpu_job_free(job); return r; } @@ -1266,7 +1281,7 @@ void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, struct amdgpu_vm_pt **entry, struct amdgpu_vm_pt **parent) { - unsigned level = 0; + unsigned level = p->adev->vm_manager.root_level; *parent = NULL; *entry = &p->vm->root; @@ -1278,7 +1293,7 @@ void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, addr &= (1ULL << shift) - 1; } - if (level != p->adev->vm_manager.num_level) + if (level != AMDGPU_VM_PTB) *entry = NULL; } @@ -1320,7 +1335,7 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, return; entry->huge = !!(flags & AMDGPU_PDE_PTE); - amdgpu_gart_get_vm_pde(p->adev, p->adev->vm_manager.num_level - 1, + amdgpu_gart_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags); if (use_cpu_update) { @@ -1636,7 +1651,8 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, error_free: amdgpu_job_free(job); - amdgpu_vm_invalidate_level(adev, vm, &vm->root, 0); + amdgpu_vm_invalidate_level(adev, vm, &vm->root, + adev->vm_manager.root_level); return r; } @@ -2552,7 +2568,19 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, tmp >>= amdgpu_vm_block_size - 9; tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; adev->vm_manager.num_level = min(max_level, (unsigned)tmp); - + switch (adev->vm_manager.num_level) { + case 3: + adev->vm_manager.root_level = AMDGPU_VM_PDB2; + break; + case 2: + adev->vm_manager.root_level = AMDGPU_VM_PDB1; + break; + case 1: + adev->vm_manager.root_level = AMDGPU_VM_PDB0; + break; + default: + dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n"); + } /* block size depends on vm size and hw setup*/ if (amdgpu_vm_block_size != -1) adev->vm_manager.block_size = @@ -2646,7 +2674,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | AMDGPU_GEM_CREATE_SHADOW); - r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, + r = amdgpu_bo_create(adev, + amdgpu_vm_bo_size(adev, adev->vm_manager.root_level), + align, true, AMDGPU_GEM_DOMAIN_VRAM, flags, NULL, NULL, init_pde_value, &vm->root.base.bo); @@ -2782,7 +2812,8 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) if (r) { dev_err(adev->dev, "Leaking page tables because BO reservation failed\n"); } else { - amdgpu_vm_free_levels(adev, &vm->root, 0); + amdgpu_vm_free_levels(adev, &vm->root, + adev->vm_manager.root_level); amdgpu_bo_unreserve(root); } amdgpu_bo_unref(&root); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index e52bf980669f..1056484de0e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -120,6 +120,16 @@ struct amdgpu_bo_list_entry; #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) +/* VMPT level enumerate, and the hiberachy is: + * PDB2->PDB1->PDB0->PTB + */ +enum amdgpu_vm_level { + AMDGPU_VM_PDB2, + AMDGPU_VM_PDB1, + AMDGPU_VM_PDB0, + AMDGPU_VM_PTB +}; + /* base structure for tracking BO usage in a VM */ struct amdgpu_vm_bo_base { /* constant after initialization */ @@ -236,6 +246,7 @@ struct amdgpu_vm_manager { uint32_t num_level; uint32_t block_size; uint32_t fragment_size; + enum amdgpu_vm_level root_level; /* vram base address for page table entry */ u64 vram_base_offset; /* vm pte handling */ -- GitLab From b7b2846fe26f2c0d7f317c874a13d3ecf22670ff Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Thu, 7 Dec 2017 19:07:02 -0800 Subject: [PATCH 1517/2547] xfs: add the ability to join a held buffer to a defer_ops In certain cases, defer_ops callers will lock a buffer and want to hold the lock across transaction rolls. Similar to ijoined inodes, we want to dirty & join the buffer with each transaction roll in defer_finish so that afterwards the caller still owns the buffer lock and we haven't inadvertently pinned the log. Signed-off-by: Darrick J. Wong Reviewed-by: Christoph Hellwig --- fs/xfs/libxfs/xfs_defer.c | 39 ++++++++++++++++++++++++++++++++++++--- fs/xfs/libxfs/xfs_defer.h | 5 ++++- 2 files changed, 40 insertions(+), 4 deletions(-) diff --git a/fs/xfs/libxfs/xfs_defer.c b/fs/xfs/libxfs/xfs_defer.c index 072ebfe1d6ae..087fea02c389 100644 --- a/fs/xfs/libxfs/xfs_defer.c +++ b/fs/xfs/libxfs/xfs_defer.c @@ -249,6 +249,10 @@ xfs_defer_trans_roll( for (i = 0; i < XFS_DEFER_OPS_NR_INODES && dop->dop_inodes[i]; i++) xfs_trans_log_inode(*tp, dop->dop_inodes[i], XFS_ILOG_CORE); + /* Hold the (previously bjoin'd) buffer locked across the roll. */ + for (i = 0; i < XFS_DEFER_OPS_NR_BUFS && dop->dop_bufs[i]; i++) + xfs_trans_dirty_buf(*tp, dop->dop_bufs[i]); + trace_xfs_defer_trans_roll((*tp)->t_mountp, dop); /* Roll the transaction. */ @@ -264,6 +268,12 @@ xfs_defer_trans_roll( for (i = 0; i < XFS_DEFER_OPS_NR_INODES && dop->dop_inodes[i]; i++) xfs_trans_ijoin(*tp, dop->dop_inodes[i], 0); + /* Rejoin the buffers and dirty them so the log moves forward. */ + for (i = 0; i < XFS_DEFER_OPS_NR_BUFS && dop->dop_bufs[i]; i++) { + xfs_trans_bjoin(*tp, dop->dop_bufs[i]); + xfs_trans_bhold(*tp, dop->dop_bufs[i]); + } + return error; } @@ -295,6 +305,31 @@ xfs_defer_ijoin( } } + ASSERT(0); + return -EFSCORRUPTED; +} + +/* + * Add this buffer to the deferred op. Each joined buffer is relogged + * each time we roll the transaction. + */ +int +xfs_defer_bjoin( + struct xfs_defer_ops *dop, + struct xfs_buf *bp) +{ + int i; + + for (i = 0; i < XFS_DEFER_OPS_NR_BUFS; i++) { + if (dop->dop_bufs[i] == bp) + return 0; + else if (dop->dop_bufs[i] == NULL) { + dop->dop_bufs[i] = bp; + return 0; + } + } + + ASSERT(0); return -EFSCORRUPTED; } @@ -493,9 +528,7 @@ xfs_defer_init( struct xfs_defer_ops *dop, xfs_fsblock_t *fbp) { - dop->dop_committed = false; - dop->dop_low = false; - memset(&dop->dop_inodes, 0, sizeof(dop->dop_inodes)); + memset(dop, 0, sizeof(struct xfs_defer_ops)); *fbp = NULLFSBLOCK; INIT_LIST_HEAD(&dop->dop_intake); INIT_LIST_HEAD(&dop->dop_pending); diff --git a/fs/xfs/libxfs/xfs_defer.h b/fs/xfs/libxfs/xfs_defer.h index d4f046dd44bd..045beacdd37d 100644 --- a/fs/xfs/libxfs/xfs_defer.h +++ b/fs/xfs/libxfs/xfs_defer.h @@ -59,6 +59,7 @@ enum xfs_defer_ops_type { }; #define XFS_DEFER_OPS_NR_INODES 2 /* join up to two inodes */ +#define XFS_DEFER_OPS_NR_BUFS 2 /* join up to two buffers */ struct xfs_defer_ops { bool dop_committed; /* did any trans commit? */ @@ -66,8 +67,9 @@ struct xfs_defer_ops { struct list_head dop_intake; /* unlogged pending work */ struct list_head dop_pending; /* logged pending work */ - /* relog these inodes with each roll */ + /* relog these with each roll */ struct xfs_inode *dop_inodes[XFS_DEFER_OPS_NR_INODES]; + struct xfs_buf *dop_bufs[XFS_DEFER_OPS_NR_BUFS]; }; void xfs_defer_add(struct xfs_defer_ops *dop, enum xfs_defer_ops_type type, @@ -77,6 +79,7 @@ void xfs_defer_cancel(struct xfs_defer_ops *dop); void xfs_defer_init(struct xfs_defer_ops *dop, xfs_fsblock_t *fbp); bool xfs_defer_has_unfinished_work(struct xfs_defer_ops *dop); int xfs_defer_ijoin(struct xfs_defer_ops *dop, struct xfs_inode *ip); +int xfs_defer_bjoin(struct xfs_defer_ops *dop, struct xfs_buf *bp); /* Description of a deferred type. */ struct xfs_defer_op_type { -- GitLab From 6e643cd094de3bd0f97edcc1db0089afa24d909f Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Thu, 7 Dec 2017 19:07:02 -0800 Subject: [PATCH 1518/2547] xfs: hold xfs_buf locked between shortform->leaf conversion and the addition of an attribute The new attribute leaf buffer is not held locked across the transaction roll between the shortform->leaf modification and the addition of the new entry. As a result, the attribute buffer modification being made is not atomic from an operational perspective. Hence the AIL push can grab it in the transient state of "just created" after the initial transaction is rolled, because the buffer has been released. This leads to xfs_attr3_leaf_verify() asserting that hdr.count is zero, treating this as in-memory corruption, and shutting down the filesystem. Darrick ported the original patch to 4.15 and reworked it use the xfs_defer_bjoin helper and hold/join the buffer correctly across the second transaction roll. Signed-off-by: Alex Lyakas Signed-off-by: Darrick J. Wong Reviewed-by: Christoph Hellwig --- fs/xfs/libxfs/xfs_attr.c | 20 +++++++++++++++----- fs/xfs/libxfs/xfs_attr_leaf.c | 9 ++++++--- fs/xfs/libxfs/xfs_attr_leaf.h | 3 ++- 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/fs/xfs/libxfs/xfs_attr.c b/fs/xfs/libxfs/xfs_attr.c index 6249c92671de..a76914db72ef 100644 --- a/fs/xfs/libxfs/xfs_attr.c +++ b/fs/xfs/libxfs/xfs_attr.c @@ -212,6 +212,7 @@ xfs_attr_set( int flags) { struct xfs_mount *mp = dp->i_mount; + struct xfs_buf *leaf_bp = NULL; struct xfs_da_args args; struct xfs_defer_ops dfops; struct xfs_trans_res tres; @@ -327,9 +328,16 @@ xfs_attr_set( * GROT: another possible req'mt for a double-split btree op. */ xfs_defer_init(args.dfops, args.firstblock); - error = xfs_attr_shortform_to_leaf(&args); + error = xfs_attr_shortform_to_leaf(&args, &leaf_bp); if (error) goto out_defer_cancel; + /* + * Prevent the leaf buffer from being unlocked so that a + * concurrent AIL push cannot grab the half-baked leaf + * buffer and run into problems with the write verifier. + */ + xfs_trans_bhold(args.trans, leaf_bp); + xfs_defer_bjoin(args.dfops, leaf_bp); xfs_defer_ijoin(args.dfops, dp); error = xfs_defer_finish(&args.trans, args.dfops); if (error) @@ -337,13 +345,14 @@ xfs_attr_set( /* * Commit the leaf transformation. We'll need another (linked) - * transaction to add the new attribute to the leaf. + * transaction to add the new attribute to the leaf, which + * means that we have to hold & join the leaf buffer here too. */ - error = xfs_trans_roll_inode(&args.trans, dp); if (error) goto out; - + xfs_trans_bjoin(args.trans, leaf_bp); + leaf_bp = NULL; } if (xfs_bmap_one_block(dp, XFS_ATTR_FORK)) @@ -374,8 +383,9 @@ xfs_attr_set( out_defer_cancel: xfs_defer_cancel(&dfops); - args.trans = NULL; out: + if (leaf_bp) + xfs_trans_brelse(args.trans, leaf_bp); if (args.trans) xfs_trans_cancel(args.trans); xfs_iunlock(dp, XFS_ILOCK_EXCL); diff --git a/fs/xfs/libxfs/xfs_attr_leaf.c b/fs/xfs/libxfs/xfs_attr_leaf.c index 53cc8b986eac..601eaa36f1ad 100644 --- a/fs/xfs/libxfs/xfs_attr_leaf.c +++ b/fs/xfs/libxfs/xfs_attr_leaf.c @@ -735,10 +735,13 @@ xfs_attr_shortform_getvalue(xfs_da_args_t *args) } /* - * Convert from using the shortform to the leaf. + * Convert from using the shortform to the leaf. On success, return the + * buffer so that we can keep it locked until we're totally done with it. */ int -xfs_attr_shortform_to_leaf(xfs_da_args_t *args) +xfs_attr_shortform_to_leaf( + struct xfs_da_args *args, + struct xfs_buf **leaf_bp) { xfs_inode_t *dp; xfs_attr_shortform_t *sf; @@ -818,7 +821,7 @@ xfs_attr_shortform_to_leaf(xfs_da_args_t *args) sfe = XFS_ATTR_SF_NEXTENTRY(sfe); } error = 0; - + *leaf_bp = bp; out: kmem_free(tmpbuffer); return error; diff --git a/fs/xfs/libxfs/xfs_attr_leaf.h b/fs/xfs/libxfs/xfs_attr_leaf.h index f7dda0c237b0..894124efb421 100644 --- a/fs/xfs/libxfs/xfs_attr_leaf.h +++ b/fs/xfs/libxfs/xfs_attr_leaf.h @@ -48,7 +48,8 @@ void xfs_attr_shortform_create(struct xfs_da_args *args); void xfs_attr_shortform_add(struct xfs_da_args *args, int forkoff); int xfs_attr_shortform_lookup(struct xfs_da_args *args); int xfs_attr_shortform_getvalue(struct xfs_da_args *args); -int xfs_attr_shortform_to_leaf(struct xfs_da_args *args); +int xfs_attr_shortform_to_leaf(struct xfs_da_args *args, + struct xfs_buf **leaf_bp); int xfs_attr_shortform_remove(struct xfs_da_args *args); int xfs_attr_shortform_allfit(struct xfs_buf *bp, struct xfs_inode *dp); int xfs_attr_shortform_bytesfit(struct xfs_inode *dp, int bytes); -- GitLab From 8c57b88637d78a723e0854fc3d06c6d4c31a1e0c Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Sun, 10 Dec 2017 18:03:53 -0800 Subject: [PATCH 1519/2547] xfs: account for null transactions in bunmapi In e1a4e37cc7b665 ("xfs: try to avoid blowing out the transaction reservation when bunmaping a shared extent"), we try to constrain the amount of real extents we unmap from the data fork in a given call so that we don't blow out transaction reservations. However, not all bunmapi operations require a transaction -- if we're only removing a delalloc extent, no transaction is needed, so we have to code against that. Signed-off-by: Darrick J. Wong Reviewed-by: Christoph Hellwig --- fs/xfs/libxfs/xfs_bmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/xfs/libxfs/xfs_bmap.c b/fs/xfs/libxfs/xfs_bmap.c index 1210f684d3c2..1bddbba6b80c 100644 --- a/fs/xfs/libxfs/xfs_bmap.c +++ b/fs/xfs/libxfs/xfs_bmap.c @@ -5136,7 +5136,7 @@ __xfs_bunmapi( * blowing out the transaction with a mix of EFIs and reflink * adjustments. */ - if (xfs_is_reflink_inode(ip) && whichfork == XFS_DATA_FORK) + if (tp && xfs_is_reflink_inode(ip) && whichfork == XFS_DATA_FORK) max_len = min(len, xfs_refcount_max_unmap(tp->t_log_res)); else max_len = len; -- GitLab From c54854a437a447a6bb1dcb11f60dd01cef3fa597 Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Sun, 10 Dec 2017 18:03:54 -0800 Subject: [PATCH 1520/2547] xfs: move xfs_iext_insert tracepoint to report useful information Move the tracepoint in xfs_iext_insert to after the point where we've inserted the extent because otherwise we report stale extent data in the ftrace output. Signed-off-by: Darrick J. Wong Reviewed-by: Christoph Hellwig --- fs/xfs/libxfs/xfs_iext_tree.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/xfs/libxfs/xfs_iext_tree.c b/fs/xfs/libxfs/xfs_iext_tree.c index 89bf16b4d937..b0f31791c7e6 100644 --- a/fs/xfs/libxfs/xfs_iext_tree.c +++ b/fs/xfs/libxfs/xfs_iext_tree.c @@ -632,8 +632,6 @@ xfs_iext_insert( struct xfs_iext_leaf *new = NULL; int nr_entries, i; - trace_xfs_iext_insert(ip, cur, state, _RET_IP_); - if (ifp->if_height == 0) xfs_iext_alloc_root(ifp, cur); else if (ifp->if_height == 1) @@ -661,6 +659,8 @@ xfs_iext_insert( xfs_iext_set(cur_rec(cur), irec); ifp->if_bytes += sizeof(struct xfs_iext_rec); + trace_xfs_iext_insert(ip, cur, state, _RET_IP_); + if (new) xfs_iext_insert_node(ifp, xfs_iext_leaf_key(new, 0), new, 2); } -- GitLab From 5c989a0ee06eb77a44baffd1779a5dbb9a7e873f Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Sun, 10 Dec 2017 18:03:54 -0800 Subject: [PATCH 1521/2547] xfs: remove dest file's post-eof preallocations before reflinking If we try to reflink into a file with post-eof preallocations at an offset well past the preallocations, we increase i_size as one would expect. However, those allocations do not have page cache backing them, so they won't get cleaned out on their own. This leads to asserts in the collapse/insert range code and xfs_destroy_inode when they encounter delalloc extents they weren't expecting to find. Since there are plenty of other places where we dump those post-eof blocks, do the same to the reflink destination file before we start remapping extents. This was found by adding clonerange support to fsstress and running it in write-only mode. Signed-off-by: Darrick J. Wong Reviewed-by: Christoph Hellwig --- fs/xfs/xfs_reflink.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/fs/xfs/xfs_reflink.c b/fs/xfs/xfs_reflink.c index cf7c8f81bebb..e13f5ad57a03 100644 --- a/fs/xfs/xfs_reflink.c +++ b/fs/xfs/xfs_reflink.c @@ -1291,6 +1291,17 @@ xfs_reflink_remap_range( trace_xfs_reflink_remap_range(src, pos_in, len, dest, pos_out); + /* + * Clear out post-eof preallocations because we don't have page cache + * backing the delayed allocations and they'll never get freed on + * their own. + */ + if (xfs_can_free_eofblocks(dest, true)) { + ret = xfs_free_eofblocks(dest); + if (ret) + goto out_unlock; + } + /* Set flags and remap blocks. */ ret = xfs_reflink_set_inode_flag(src, dest); if (ret) -- GitLab From 73353f486c9b5b2407ec32be1004174dbbaf6c18 Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Sun, 10 Dec 2017 18:03:55 -0800 Subject: [PATCH 1522/2547] xfs: relax is_reflink_inode assert in xfs_reflink_find_cow_mapping We don't hold the ilock through the entire sequence of xfs_writepage_map -> xfs_map_cow -> xfs_reflink_find_cow_mapping. This means that we can race with another thread that is trying to clear the inode reflink flag, with the result that the flag is set for the xfs_map_cow check but cleared before we get to the assert in find_cow_mapping. When this happens, we blow the assert even though everything is fine. Signed-off-by: Darrick J. Wong Reviewed-by: Christoph Hellwig --- fs/xfs/xfs_reflink.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/xfs/xfs_reflink.c b/fs/xfs/xfs_reflink.c index e13f5ad57a03..99c5852f9fe7 100644 --- a/fs/xfs/xfs_reflink.c +++ b/fs/xfs/xfs_reflink.c @@ -490,8 +490,9 @@ xfs_reflink_find_cow_mapping( struct xfs_iext_cursor icur; ASSERT(xfs_isilocked(ip, XFS_ILOCK_EXCL | XFS_ILOCK_SHARED)); - ASSERT(xfs_is_reflink_inode(ip)); + if (!xfs_is_reflink_inode(ip)) + return false; offset_fsb = XFS_B_TO_FSBT(ip->i_mount, offset); if (!xfs_iext_lookup_extent(ip, ifp, offset_fsb, &icur, &got)) return false; -- GitLab From 9d40fba8b2056773b9744a95df9ddd6cc33a4f83 Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Sun, 10 Dec 2017 18:03:55 -0800 Subject: [PATCH 1523/2547] xfs: avoid infinite loop when cancelling CoW blocks after writeback failure When we're cancelling a cow range, we don't always delete each extent that we iterate, so we have to move icur backwards in the list to avoid an infinite loop. Signed-off-by: Darrick J. Wong Reviewed-by: Christoph Hellwig --- fs/xfs/xfs_reflink.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/xfs/xfs_reflink.c b/fs/xfs/xfs_reflink.c index 99c5852f9fe7..6931b0c79cac 100644 --- a/fs/xfs/xfs_reflink.c +++ b/fs/xfs/xfs_reflink.c @@ -611,6 +611,9 @@ xfs_reflink_cancel_cow_blocks( /* Remove the mapping from the CoW fork. */ xfs_bmap_del_extent_cow(ip, &icur, &got, &del); + } else { + /* Didn't do anything, push cursor back. */ + xfs_iext_prev(ifp, &icur); } next_extent: if (!xfs_iext_get_extent(ifp, &icur, &got)) -- GitLab From a192de265b26c525672884630d5376c405e83b2a Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Sun, 10 Dec 2017 18:03:56 -0800 Subject: [PATCH 1524/2547] xfs: allow CoW remap transactions to use reserve blocks Since we as yet have no way of holding on to the indlen blocks that are reserved as part of CoW fork delalloc reservations, let the CoW remap transaction dip into the reserves so that we avoid failing writes. Signed-off-by: Darrick J. Wong Reviewed-by: Christoph Hellwig --- fs/xfs/xfs_reflink.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/xfs/xfs_reflink.c b/fs/xfs/xfs_reflink.c index 6931b0c79cac..e49e6db415f7 100644 --- a/fs/xfs/xfs_reflink.c +++ b/fs/xfs/xfs_reflink.c @@ -729,7 +729,7 @@ xfs_reflink_end_cow( (unsigned int)(end_fsb - offset_fsb), XFS_DATA_FORK); error = xfs_trans_alloc(ip->i_mount, &M_RES(ip->i_mount)->tr_write, - resblks, 0, 0, &tp); + resblks, 0, XFS_TRANS_RESERVE, &tp); if (error) goto out; -- GitLab From 8d8c46fad4a15cd8a9811ab74a14de0ee1d6c66b Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Thu, 14 Dec 2017 15:10:09 +0200 Subject: [PATCH 1525/2547] drm/i915: properly init lockdep class The code has an ifdef and uses two functions to either init the bare spinlock or init it and set a lock-class. It is possible to do the same thing without an ifdef. With this patch (in debug case) we first use the "default" lock class which is later overwritten to the supplied one. Without lockdep the set name/class function vanishes. Reported-by: kbuild test robot Signed-off-by: Sebastian Andrzej Siewior Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171214131009.7479-1-joonas.lahtinen@linux.intel.com Signed-off-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_timeline.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_timeline.c b/drivers/gpu/drm/i915/i915_gem_timeline.c index c01905d6450c..e9fd87604067 100644 --- a/drivers/gpu/drm/i915/i915_gem_timeline.c +++ b/drivers/gpu/drm/i915/i915_gem_timeline.c @@ -33,11 +33,8 @@ static void __intel_timeline_init(struct intel_timeline *tl, { tl->fence_context = context; tl->common = parent; -#ifdef CONFIG_DEBUG_SPINLOCK - __raw_spin_lock_init(&tl->lock.rlock, lockname, lockclass); -#else spin_lock_init(&tl->lock); -#endif + lockdep_set_class_and_name(&tl->lock, lockclass, lockname); init_request_active(&tl->last_request, NULL); INIT_LIST_HEAD(&tl->requests); i915_syncmap_init(&tl->sync); -- GitLab From c2e90800aef22e7ea14ea7560ba99993f11d3616 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Tue, 12 Dec 2017 13:45:50 +0000 Subject: [PATCH 1526/2547] virtio_mmio: fix devm cleanup Recent rework of the virtio_mmio probe/remove paths balanced a devm_ioremap() with an iounmap() rather than its devm variant. This ends up corrupting the devm datastructures, and results in the following boot-time splat on arm64 under QEMU 2.9.0: [ 3.450397] ------------[ cut here ]------------ [ 3.453822] Trying to vfree() nonexistent vm area (00000000c05b4844) [ 3.460534] WARNING: CPU: 1 PID: 1 at mm/vmalloc.c:1525 __vunmap+0x1b8/0x220 [ 3.475898] Kernel panic - not syncing: panic_on_warn set ... [ 3.475898] [ 3.493933] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.15.0-rc3 #1 [ 3.513109] Hardware name: linux,dummy-virt (DT) [ 3.525382] Call trace: [ 3.531683] dump_backtrace+0x0/0x368 [ 3.543921] show_stack+0x20/0x30 [ 3.547767] dump_stack+0x108/0x164 [ 3.559584] panic+0x25c/0x51c [ 3.569184] __warn+0x29c/0x31c [ 3.576023] report_bug+0x1d4/0x290 [ 3.586069] bug_handler.part.2+0x40/0x100 [ 3.597820] bug_handler+0x4c/0x88 [ 3.608400] brk_handler+0x11c/0x218 [ 3.613430] do_debug_exception+0xe8/0x318 [ 3.627370] el1_dbg+0x18/0x78 [ 3.634037] __vunmap+0x1b8/0x220 [ 3.648747] vunmap+0x6c/0xc0 [ 3.653864] __iounmap+0x44/0x58 [ 3.659771] devm_ioremap_release+0x34/0x68 [ 3.672983] release_nodes+0x404/0x880 [ 3.683543] devres_release_all+0x6c/0xe8 [ 3.695692] driver_probe_device+0x250/0x828 [ 3.706187] __driver_attach+0x190/0x210 [ 3.717645] bus_for_each_dev+0x14c/0x1f0 [ 3.728633] driver_attach+0x48/0x78 [ 3.740249] bus_add_driver+0x26c/0x5b8 [ 3.752248] driver_register+0x16c/0x398 [ 3.757211] __platform_driver_register+0xd8/0x128 [ 3.770860] virtio_mmio_init+0x1c/0x24 [ 3.782671] do_one_initcall+0xe0/0x398 [ 3.791890] kernel_init_freeable+0x594/0x660 [ 3.798514] kernel_init+0x18/0x190 [ 3.810220] ret_from_fork+0x10/0x18 To fix this, we can simply rip out the explicit cleanup that the devm infrastructure will do for us when our probe function returns an error code, or when our remove function returns. We only need to ensure that we call put_device() if a call to register_virtio_device() fails in the probe path. Signed-off-by: Mark Rutland Fixes: 7eb781b1bbb7136f ("virtio_mmio: add cleanup for virtio_mmio_probe") Fixes: 25f32223bce5c580 ("virtio_mmio: add cleanup for virtio_mmio_remove") Cc: Cornelia Huck Cc: Michael S. Tsirkin Cc: weiping zhang Cc: virtualization@lists.linux-foundation.org Signed-off-by: Michael S. Tsirkin Reviewed-by: Cornelia Huck --- drivers/virtio/virtio_mmio.c | 43 ++++++++---------------------------- 1 file changed, 9 insertions(+), 34 deletions(-) diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index a9192fe4f345..c92131edfaba 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -522,10 +522,8 @@ static int virtio_mmio_probe(struct platform_device *pdev) return -EBUSY; vm_dev = devm_kzalloc(&pdev->dev, sizeof(*vm_dev), GFP_KERNEL); - if (!vm_dev) { - rc = -ENOMEM; - goto free_mem; - } + if (!vm_dev) + return -ENOMEM; vm_dev->vdev.dev.parent = &pdev->dev; vm_dev->vdev.dev.release = virtio_mmio_release_dev; @@ -535,17 +533,14 @@ static int virtio_mmio_probe(struct platform_device *pdev) spin_lock_init(&vm_dev->lock); vm_dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); - if (vm_dev->base == NULL) { - rc = -EFAULT; - goto free_vmdev; - } + if (vm_dev->base == NULL) + return -EFAULT; /* Check magic value */ magic = readl(vm_dev->base + VIRTIO_MMIO_MAGIC_VALUE); if (magic != ('v' | 'i' << 8 | 'r' << 16 | 't' << 24)) { dev_warn(&pdev->dev, "Wrong magic value 0x%08lx!\n", magic); - rc = -ENODEV; - goto unmap; + return -ENODEV; } /* Check device version */ @@ -553,8 +548,7 @@ static int virtio_mmio_probe(struct platform_device *pdev) if (vm_dev->version < 1 || vm_dev->version > 2) { dev_err(&pdev->dev, "Version %ld not supported!\n", vm_dev->version); - rc = -ENXIO; - goto unmap; + return -ENXIO; } vm_dev->vdev.id.device = readl(vm_dev->base + VIRTIO_MMIO_DEVICE_ID); @@ -563,8 +557,7 @@ static int virtio_mmio_probe(struct platform_device *pdev) * virtio-mmio device with an ID 0 is a (dummy) placeholder * with no function. End probing now with no error reported. */ - rc = -ENODEV; - goto unmap; + return -ENODEV; } vm_dev->vdev.id.vendor = readl(vm_dev->base + VIRTIO_MMIO_VENDOR_ID); @@ -590,33 +583,15 @@ static int virtio_mmio_probe(struct platform_device *pdev) platform_set_drvdata(pdev, vm_dev); rc = register_virtio_device(&vm_dev->vdev); - if (rc) { - iounmap(vm_dev->base); - devm_release_mem_region(&pdev->dev, mem->start, - resource_size(mem)); + if (rc) put_device(&vm_dev->vdev.dev); - } - return rc; -unmap: - iounmap(vm_dev->base); -free_mem: - devm_release_mem_region(&pdev->dev, mem->start, - resource_size(mem)); -free_vmdev: - devm_kfree(&pdev->dev, vm_dev); + return rc; } static int virtio_mmio_remove(struct platform_device *pdev) { struct virtio_mmio_device *vm_dev = platform_get_drvdata(pdev); - struct resource *mem; - - iounmap(vm_dev->base); - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (mem) - devm_release_mem_region(&pdev->dev, mem->start, - resource_size(mem)); unregister_virtio_device(&vm_dev->vdev); return 0; -- GitLab From ee5b5bf351ec8cd8f11c631cb76b30f602e866ee Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Thu, 14 Dec 2017 12:10:02 -0800 Subject: [PATCH 1527/2547] drm/i915: Update DRIVER_DATE to 20171214 Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7762eabd31c1..1aba5657f5f0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -80,8 +80,8 @@ #define DRIVER_NAME "i915" #define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20171201" -#define DRIVER_TIMESTAMP 1512176839 +#define DRIVER_DATE "20171214" +#define DRIVER_TIMESTAMP 1513282202 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and * WARN_ON()) for hw state sanity checks to check for unexpected conditions -- GitLab From c47d7f56e914900410f65835933f9fc4374d0a2b Mon Sep 17 00:00:00 2001 From: Wei Wang Date: Thu, 14 Dec 2017 15:32:24 -0800 Subject: [PATCH 1528/2547] include/linux/idr.h: add #include The was removed from radix-tree.h by commit f5bba9d11a25 ("include/linux/radix-tree.h: remove unneeded #include "). Since that commit, tools/testing/radix-tree/ couldn't pass compilation due to tools/testing/radix-tree/idr.c:17: undefined reference to WARN_ON_ONCE. This patch adds the bug.h header to idr.h to solve the issue. Link: http://lkml.kernel.org/r/1511963726-34070-2-git-send-email-wei.w.wang@intel.com Fixes: f5bba9d11a2 ("include/linux/radix-tree.h: remove unneeded #include ") Signed-off-by: Wei Wang Cc: Matthew Wilcox Cc: Jan Kara Cc: Eric Biggers Cc: Tejun Heo Cc: Masahiro Yamada Cc: Michal Hocko Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/idr.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/idr.h b/include/linux/idr.h index 7c3a365f7e12..fa14f834e4ed 100644 --- a/include/linux/idr.h +++ b/include/linux/idr.h @@ -15,6 +15,7 @@ #include #include #include +#include struct idr { struct radix_tree_root idr_rt; -- GitLab From 338f1d9d1b829fec494d053f62820a2ee625b1ec Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 14 Dec 2017 15:32:28 -0800 Subject: [PATCH 1529/2547] lib/rbtree,drm/mm: add rbtree_replace_node_cached() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a variant of rbtree_replace_node() that maintains the leftmost cache of struct rbtree_root_cached when replacing nodes within the rbtree. As drm_mm is the only rb_replace_node() being used on an interval tree, the mistake looks fairly self-contained. Furthermore the only user of drm_mm_replace_node() is its testsuite... Testcase: igt/drm_mm/replace Link: http://lkml.kernel.org/r/20171122100729.3742-1-chris@chris-wilson.co.uk Link: https://patchwork.freedesktop.org/patch/msgid/20171109212435.9265-1-chris@chris-wilson.co.uk Fixes: f808c13fd373 ("lib/interval_tree: fast overlap detection") Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen Acked-by: Davidlohr Bueso Cc: Jérôme Glisse Cc: Joonas Lahtinen Cc: Daniel Vetter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/gpu/drm/drm_mm.c | 8 +++++--- include/linux/rbtree.h | 2 ++ lib/rbtree.c | 10 ++++++++++ 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index 61a1c8ea74bc..c3c79ee6119e 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -575,21 +575,23 @@ EXPORT_SYMBOL(drm_mm_remove_node); */ void drm_mm_replace_node(struct drm_mm_node *old, struct drm_mm_node *new) { + struct drm_mm *mm = old->mm; + DRM_MM_BUG_ON(!old->allocated); *new = *old; list_replace(&old->node_list, &new->node_list); - rb_replace_node(&old->rb, &new->rb, &old->mm->interval_tree.rb_root); + rb_replace_node_cached(&old->rb, &new->rb, &mm->interval_tree); if (drm_mm_hole_follows(old)) { list_replace(&old->hole_stack, &new->hole_stack); rb_replace_node(&old->rb_hole_size, &new->rb_hole_size, - &old->mm->holes_size); + &mm->holes_size); rb_replace_node(&old->rb_hole_addr, &new->rb_hole_addr, - &old->mm->holes_addr); + &mm->holes_addr); } old->allocated = false; diff --git a/include/linux/rbtree.h b/include/linux/rbtree.h index d574361943ea..fcbeed4053ef 100644 --- a/include/linux/rbtree.h +++ b/include/linux/rbtree.h @@ -99,6 +99,8 @@ extern void rb_replace_node(struct rb_node *victim, struct rb_node *new, struct rb_root *root); extern void rb_replace_node_rcu(struct rb_node *victim, struct rb_node *new, struct rb_root *root); +extern void rb_replace_node_cached(struct rb_node *victim, struct rb_node *new, + struct rb_root_cached *root); static inline void rb_link_node(struct rb_node *node, struct rb_node *parent, struct rb_node **rb_link) diff --git a/lib/rbtree.c b/lib/rbtree.c index ba4a9d165f1b..d3ff682fd4b8 100644 --- a/lib/rbtree.c +++ b/lib/rbtree.c @@ -603,6 +603,16 @@ void rb_replace_node(struct rb_node *victim, struct rb_node *new, } EXPORT_SYMBOL(rb_replace_node); +void rb_replace_node_cached(struct rb_node *victim, struct rb_node *new, + struct rb_root_cached *root) +{ + rb_replace_node(victim, new, &root->rb_root); + + if (root->rb_leftmost == victim) + root->rb_leftmost = new; +} +EXPORT_SYMBOL(rb_replace_node_cached); + void rb_replace_node_rcu(struct rb_node *victim, struct rb_node *new, struct rb_root *root) { -- GitLab From 13ab183d138f607d885e995d625e58d47678bf97 Mon Sep 17 00:00:00 2001 From: Andrew Morton Date: Thu, 14 Dec 2017 15:32:31 -0800 Subject: [PATCH 1530/2547] mm/kmemleak.c: make cond_resched() rate-limiting more efficient Commit bde5f6bc68db ("kmemleak: add scheduling point to kmemleak_scan()") tries to rate-limit the frequency of cond_resched() calls, but does it in a way which might incur an expensive division operation in the inner loop. Simplify this. Fixes: bde5f6bc68db5 ("kmemleak: add scheduling point to kmemleak_scan()") Suggested-by: Linus Torvalds Cc: Yisheng Xie Cc: Catalin Marinas Cc: Michal Hocko Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- mm/kmemleak.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mm/kmemleak.c b/mm/kmemleak.c index 3d4781756d50..d73c14294f3a 100644 --- a/mm/kmemleak.c +++ b/mm/kmemleak.c @@ -1523,7 +1523,7 @@ static void kmemleak_scan(void) if (page_count(page) == 0) continue; scan_block(page, page + 1, NULL); - if (!(pfn % (MAX_SCAN_SIZE / sizeof(*page)))) + if (!(pfn & 63)) cond_resched(); } } -- GitLab From 146734b091430c80d80bb96b1139a96fb4bc830e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 14 Dec 2017 15:32:34 -0800 Subject: [PATCH 1531/2547] string.h: workaround for increased stack usage The hardened strlen() function causes rather large stack usage in at least one file in the kernel, in particular when CONFIG_KASAN is enabled: drivers/media/usb/em28xx/em28xx-dvb.c: In function 'em28xx_dvb_init': drivers/media/usb/em28xx/em28xx-dvb.c:2062:1: error: the frame size of 3256 bytes is larger than 204 bytes [-Werror=frame-larger-than=] Analyzing this problem led to the discovery that gcc fails to merge the stack slots for the i2c_board_info[] structures after we strlcpy() into them, due to the 'noreturn' attribute on the source string length check. I reported this as a gcc bug, but it is unlikely to get fixed for gcc-8, since it is relatively easy to work around, and it gets triggered rarely. An earlier workaround I did added an empty inline assembly statement before the call to fortify_panic(), which works surprisingly well, but is really ugly and unintuitive. This is a new approach to the same problem, this time addressing it by not calling the 'extern __real_strnlen()' function for string constants where __builtin_strlen() is a compile-time constant and therefore known to be safe. We do this by checking if the last character in the string is a compile-time constant '\0'. If it is, we can assume that strlen() of the string is also constant. As a side-effect, this should also improve the object code output for any other call of strlen() on a string constant. [akpm@linux-foundation.org: add comment] Link: http://lkml.kernel.org/r/20171205215143.3085755-1-arnd@arndb.de Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365 Link: https://patchwork.kernel.org/patch/9980413/ Link: https://patchwork.kernel.org/patch/9974047/ Fixes: 6974f0c4555 ("include/linux/string.h: add the option of fortified string.h functions") Signed-off-by: Arnd Bergmann Cc: Kees Cook Cc: Mauro Carvalho Chehab Cc: Dmitry Vyukov Cc: Alexander Potapenko Cc: Andrey Ryabinin Cc: Daniel Micay Cc: Greg Kroah-Hartman Cc: Martin Wilck Cc: Dan Williams Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/string.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/linux/string.h b/include/linux/string.h index 410ecf17de3c..cfd83eb2f926 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -259,7 +259,10 @@ __FORTIFY_INLINE __kernel_size_t strlen(const char *p) { __kernel_size_t ret; size_t p_size = __builtin_object_size(p, 0); - if (p_size == (size_t)-1) + + /* Work around gcc excess stack consumption issue */ + if (p_size == (size_t)-1 || + (__builtin_constant_p(p[p_size - 1]) && p[p_size - 1] == '\0')) return __builtin_strlen(p); ret = strnlen(p, p_size); if (p_size <= ret) -- GitLab From 302ec300ef8a545a7fc7f667e5fd743b091c2eeb Mon Sep 17 00:00:00 2001 From: NeilBrown Date: Thu, 14 Dec 2017 15:32:38 -0800 Subject: [PATCH 1532/2547] autofs: fix careless error in recent commit Commit ecc0c469f277 ("autofs: don't fail mount for transient error") was meant to replace an 'if' with a 'switch', but instead added the 'switch' leaving the case in place. Link: http://lkml.kernel.org/r/87zi6wstmw.fsf@notabene.neil.brown.name Fixes: ecc0c469f277 ("autofs: don't fail mount for transient error") Reported-by: Ben Hutchings Signed-off-by: NeilBrown Cc: Ian Kent Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- fs/autofs4/waitq.c | 1 - 1 file changed, 1 deletion(-) diff --git a/fs/autofs4/waitq.c b/fs/autofs4/waitq.c index 8fc41705c7cd..961a12dc6dc8 100644 --- a/fs/autofs4/waitq.c +++ b/fs/autofs4/waitq.c @@ -170,7 +170,6 @@ static void autofs4_notify_daemon(struct autofs_sb_info *sbi, mutex_unlock(&sbi->wq_mutex); - if (autofs4_write(sbi, pipe, &pkt, pktsz)) switch (ret = autofs4_write(sbi, pipe, &pkt, pktsz)) { case 0: break; -- GitLab From 3756f6401c302617c5e091081ca4d26ab604bec5 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 14 Dec 2017 15:32:41 -0800 Subject: [PATCH 1533/2547] exec: avoid gcc-8 warning for get_task_comm gcc-8 warns about using strncpy() with the source size as the limit: fs/exec.c:1223:32: error: argument to 'sizeof' in 'strncpy' call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] This is indeed slightly suspicious, as it protects us from source arguments without NUL-termination, but does not guarantee that the destination is terminated. This keeps the strncpy() to ensure we have properly padded target buffer, but ensures that we use the correct length, by passing the actual length of the destination buffer as well as adding a build-time check to ensure it is exactly TASK_COMM_LEN. There are only 23 callsites which I all reviewed to ensure this is currently the case. We could get away with doing only the check or passing the right length, but it doesn't hurt to do both. Link: http://lkml.kernel.org/r/20171205151724.1764896-1-arnd@arndb.de Signed-off-by: Arnd Bergmann Suggested-by: Kees Cook Acked-by: Kees Cook Acked-by: Ingo Molnar Cc: Alexander Viro Cc: Peter Zijlstra Cc: Serge Hallyn Cc: James Morris Cc: Aleksa Sarai Cc: "Eric W. Biederman" Cc: Frederic Weisbecker Cc: Thomas Gleixner Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- fs/exec.c | 7 +++---- include/linux/sched.h | 6 +++++- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/fs/exec.c b/fs/exec.c index 6be2aa0ab26f..156f56acfe8e 100644 --- a/fs/exec.c +++ b/fs/exec.c @@ -1216,15 +1216,14 @@ static int de_thread(struct task_struct *tsk) return -EAGAIN; } -char *get_task_comm(char *buf, struct task_struct *tsk) +char *__get_task_comm(char *buf, size_t buf_size, struct task_struct *tsk) { - /* buf must be at least sizeof(tsk->comm) in size */ task_lock(tsk); - strncpy(buf, tsk->comm, sizeof(tsk->comm)); + strncpy(buf, tsk->comm, buf_size); task_unlock(tsk); return buf; } -EXPORT_SYMBOL_GPL(get_task_comm); +EXPORT_SYMBOL_GPL(__get_task_comm); /* * These functions flushes out all traces of the currently running executable diff --git a/include/linux/sched.h b/include/linux/sched.h index 21991d668d35..5124ba709830 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1503,7 +1503,11 @@ static inline void set_task_comm(struct task_struct *tsk, const char *from) __set_task_comm(tsk, from, false); } -extern char *get_task_comm(char *to, struct task_struct *tsk); +extern char *__get_task_comm(char *to, size_t len, struct task_struct *tsk); +#define get_task_comm(buf, tsk) ({ \ + BUILD_BUG_ON(sizeof(buf) != TASK_COMM_LEN); \ + __get_task_comm(buf, sizeof(buf), tsk); \ +}) #ifdef CONFIG_SMP void scheduler_ipi(void); -- GitLab From 51f73fffbf30b335d036ab356b67b05e16e26585 Mon Sep 17 00:00:00 2001 From: Srividya Desireddy Date: Thu, 14 Dec 2017 15:32:45 -0800 Subject: [PATCH 1534/2547] Documentation/vm/zswap.txt: update with same-value filled page feature Update zswap document with details on same-value filled pages identification feature. The usage of zswap.same_filled_pages_enabled module parameter is explained. Link: http://lkml.kernel.org/r/20171206114852epcms5p6973b02a9f455d5d3c765eafda0fe2631@epcms5p6 Signed-off-by: Srividya Desireddy Acked-by: Dan Streetman Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/vm/zswap.txt | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/Documentation/vm/zswap.txt b/Documentation/vm/zswap.txt index 89fff7d611cc..0b3a1148f9f0 100644 --- a/Documentation/vm/zswap.txt +++ b/Documentation/vm/zswap.txt @@ -98,5 +98,25 @@ request is made for a page in an old zpool, it is uncompressed using its original compressor. Once all pages are removed from an old zpool, the zpool and its compressor are freed. +Some of the pages in zswap are same-value filled pages (i.e. contents of the +page have same value or repetitive pattern). These pages include zero-filled +pages and they are handled differently. During store operation, a page is +checked if it is a same-value filled page before compressing it. If true, the +compressed length of the page is set to zero and the pattern or same-filled +value is stored. + +Same-value filled pages identification feature is enabled by default and can be +disabled at boot time by setting the "same_filled_pages_enabled" attribute to 0, +e.g. zswap.same_filled_pages_enabled=0. It can also be enabled and disabled at +runtime using the sysfs "same_filled_pages_enabled" attribute, e.g. + +echo 1 > /sys/module/zswap/parameters/same_filled_pages_enabled + +When zswap same-filled page identification is disabled at runtime, it will stop +checking for the same-value filled pages during store operation. However, the +existing pages which are marked as same-value filled pages remain stored +unchanged in zswap until they are either loaded or invalidated. + A debugfs interface is provided for various statistic about pool size, number -of pages stored, and various counters for the reasons pages are rejected. +of pages stored, same-value filled pages and various counters for the reasons +pages are rejected. -- GitLab From 4cc90b4cc3d4955f79eae4f7f9d64e67e17b468e Mon Sep 17 00:00:00 2001 From: "Liu, Changcheng" Date: Thu, 14 Dec 2017 15:32:48 -0800 Subject: [PATCH 1535/2547] scripts/faddr2line: fix CROSS_COMPILE unset error faddr2line hit var unbound error when CROSS_COMPILE isn't set since nounset option is set in bash script. Link: http://lkml.kernel.org/r/20171206013022.GA83929@sofia Fixes: 95a879825419 ("scripts/faddr2line: extend usage on generic arch") Signed-off-by: Liu Changcheng Reported-by: Richard Weinberger Reviewed-by: Richard Weinberger Cc: Thomas Gleixner Cc: Greg Kroah-Hartman Cc: Philippe Ombredanne Cc: NeilBrown Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- scripts/faddr2line | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/scripts/faddr2line b/scripts/faddr2line index 39e07d8574dd..7721d5b2b0c0 100755 --- a/scripts/faddr2line +++ b/scripts/faddr2line @@ -44,10 +44,10 @@ set -o errexit set -o nounset -READELF="${CROSS_COMPILE}readelf" -ADDR2LINE="${CROSS_COMPILE}addr2line" -SIZE="${CROSS_COMPILE}size" -NM="${CROSS_COMPILE}nm" +READELF="${CROSS_COMPILE:-}readelf" +ADDR2LINE="${CROSS_COMPILE:-}addr2line" +SIZE="${CROSS_COMPILE:-}size" +NM="${CROSS_COMPILE:-}nm" command -v awk >/dev/null 2>&1 || die "awk isn't installed" command -v ${READELF} >/dev/null 2>&1 || die "readelf isn't installed" -- GitLab From 183f24aa5b76e37da690b2def41cc70f0792ce09 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 14 Dec 2017 15:32:52 -0800 Subject: [PATCH 1536/2547] mm/memory.c: mark wp_huge_pmd() inline to prevent build failure With gcc 4.1.2: mm/memory.o: In function `wp_huge_pmd': memory.c:(.text+0x9b4): undefined reference to `do_huge_pmd_wp_page' Interestingly, wp_huge_pmd() is emitted in the assembler output, but never called. Apparently replacing the call to pmd_write() in __handle_mm_fault() by a call to the more complex pmd_access_permitted() reduced the ability of the compiler to remove unused code. Fix this by marking wp_huge_pmd() inline, like was done in commit 91a90140f998 ("mm/memory.c: mark create_huge_pmd() inline to prevent build failure") for a similar problem. [akpm@linux-foundation.org: add comment] Link: http://lkml.kernel.org/r/1512335500-10889-1-git-send-email-geert@linux-m68k.org Fixes: c7da82b894e9eef6 ("mm: replace pmd_write with pmd_access_permitted in fault + gup paths") Signed-off-by: Geert Uytterhoeven Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- mm/memory.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/mm/memory.c b/mm/memory.c index 5eb3d2524bdc..cfaba6287702 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -3831,7 +3831,8 @@ static inline int create_huge_pmd(struct vm_fault *vmf) return VM_FAULT_FALLBACK; } -static int wp_huge_pmd(struct vm_fault *vmf, pmd_t orig_pmd) +/* `inline' is required to avoid gcc 4.1.2 build error */ +static inline int wp_huge_pmd(struct vm_fault *vmf, pmd_t orig_pmd) { if (vma_is_anonymous(vmf->vma)) return do_huge_pmd_wp_page(vmf, orig_pmd); -- GitLab From c24ad77d962c31af92f2b731dad2104cbf3fbb03 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 14 Dec 2017 15:32:55 -0800 Subject: [PATCH 1537/2547] mm/page_alloc.c: avoid excessive IRQ disabled times in free_unref_page_list() Since commit 9cca35d42eb6 ("mm, page_alloc: enable/disable IRQs once when freeing a list of pages") we see excessive IRQ disabled times of up to 25ms on an embedded ARM system (tracing overhead included). This is due to graphics buffers being freed back to the system via release_pages(). Graphics buffers can be huge, so it's not hard to hit cases where the list of pages to free has 2048 entries. Disabling IRQs while freeing all those pages is clearly not a good idea. Introduce a batch limit, which allows IRQ servicing once every few pages. The batch count is the same as used in other parts of the MM subsystem when dealing with IRQ disabled regions. Link: http://lkml.kernel.org/r/20171207170314.4419-1-l.stach@pengutronix.de Fixes: 9cca35d42eb6 ("mm, page_alloc: enable/disable IRQs once when freeing a list of pages") Signed-off-by: Lucas Stach Acked-by: Mel Gorman Cc: Michal Hocko Cc: Vlastimil Babka Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- mm/page_alloc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 73f5d4556b3d..7e5e775e97f4 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -2684,6 +2684,7 @@ void free_unref_page_list(struct list_head *list) { struct page *page, *next; unsigned long flags, pfn; + int batch_count = 0; /* Prepare pages for freeing */ list_for_each_entry_safe(page, next, list, lru) { @@ -2700,6 +2701,16 @@ void free_unref_page_list(struct list_head *list) set_page_private(page, 0); trace_mm_page_free_batched(page); free_unref_page_commit(page, pfn); + + /* + * Guard against excessive IRQ disabled times when we get + * a large list of pages to free. + */ + if (++batch_count == SWAP_CLUSTER_MAX) { + local_irq_restore(flags); + batch_count = 0; + local_irq_save(flags); + } } local_irq_restore(flags); } -- GitLab From 85c3e4a5a185f22649c6bf33bdce7bb1ac890921 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 14 Dec 2017 15:32:58 -0800 Subject: [PATCH 1538/2547] mm/slab.c: do not hash pointers when debugging slab If CONFIG_DEBUG_SLAB/CONFIG_DEBUG_SLAB_LEAK are enabled, the slab code prints extra debug information when e.g. corruption is detected. This includes pointers, which are not very useful when hashed. Fix this by using %px to print unhashed pointers instead where it makes sense, and by removing the printing of a last user pointer referring to code. [geert+renesas@glider.be: v2] Link: http://lkml.kernel.org/r/1513179267-2509-1-git-send-email-geert+renesas@glider.be Link: http://lkml.kernel.org/r/1512641861-5113-1-git-send-email-geert+renesas@glider.be Fixes: ad67b74d2469d9b8 ("printk: hash addresses printed with %p") Signed-off-by: Geert Uytterhoeven Acked-by: Christoph Lameter Acked-by: Linus Torvalds Cc: Pekka Enberg Cc: David Rientjes Cc: Joonsoo Kim Cc: "Tobin C . Harding" Cc: Kees Cook Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- mm/slab.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/mm/slab.c b/mm/slab.c index 183e996dde5f..4e51ef954026 100644 --- a/mm/slab.c +++ b/mm/slab.c @@ -1584,11 +1584,8 @@ static void print_objinfo(struct kmem_cache *cachep, void *objp, int lines) *dbg_redzone2(cachep, objp)); } - if (cachep->flags & SLAB_STORE_USER) { - pr_err("Last user: [<%p>](%pSR)\n", - *dbg_userword(cachep, objp), - *dbg_userword(cachep, objp)); - } + if (cachep->flags & SLAB_STORE_USER) + pr_err("Last user: (%pSR)\n", *dbg_userword(cachep, objp)); realobj = (char *)objp + obj_offset(cachep); size = cachep->object_size; for (i = 0; i < size && lines; i += 16, lines--) { @@ -1621,7 +1618,7 @@ static void check_poison_obj(struct kmem_cache *cachep, void *objp) /* Mismatch ! */ /* Print header */ if (lines == 0) { - pr_err("Slab corruption (%s): %s start=%p, len=%d\n", + pr_err("Slab corruption (%s): %s start=%px, len=%d\n", print_tainted(), cachep->name, realobj, size); print_objinfo(cachep, objp, 0); @@ -1650,13 +1647,13 @@ static void check_poison_obj(struct kmem_cache *cachep, void *objp) if (objnr) { objp = index_to_obj(cachep, page, objnr - 1); realobj = (char *)objp + obj_offset(cachep); - pr_err("Prev obj: start=%p, len=%d\n", realobj, size); + pr_err("Prev obj: start=%px, len=%d\n", realobj, size); print_objinfo(cachep, objp, 2); } if (objnr + 1 < cachep->num) { objp = index_to_obj(cachep, page, objnr + 1); realobj = (char *)objp + obj_offset(cachep); - pr_err("Next obj: start=%p, len=%d\n", realobj, size); + pr_err("Next obj: start=%px, len=%d\n", realobj, size); print_objinfo(cachep, objp, 2); } } @@ -2608,7 +2605,7 @@ static void slab_put_obj(struct kmem_cache *cachep, /* Verify double free bug */ for (i = page->active; i < cachep->num; i++) { if (get_free_obj(page, i) == objnr) { - pr_err("slab: double free detected in cache '%s', objp %p\n", + pr_err("slab: double free detected in cache '%s', objp %px\n", cachep->name, objp); BUG(); } @@ -2772,7 +2769,7 @@ static inline void verify_redzone_free(struct kmem_cache *cache, void *obj) else slab_error(cache, "memory outside object was overwritten"); - pr_err("%p: redzone 1:0x%llx, redzone 2:0x%llx\n", + pr_err("%px: redzone 1:0x%llx, redzone 2:0x%llx\n", obj, redzone1, redzone2); } @@ -3078,7 +3075,7 @@ static void *cache_alloc_debugcheck_after(struct kmem_cache *cachep, if (*dbg_redzone1(cachep, objp) != RED_INACTIVE || *dbg_redzone2(cachep, objp) != RED_INACTIVE) { slab_error(cachep, "double free, or memory outside object was overwritten"); - pr_err("%p: redzone 1:0x%llx, redzone 2:0x%llx\n", + pr_err("%px: redzone 1:0x%llx, redzone 2:0x%llx\n", objp, *dbg_redzone1(cachep, objp), *dbg_redzone2(cachep, objp)); } @@ -3091,7 +3088,7 @@ static void *cache_alloc_debugcheck_after(struct kmem_cache *cachep, cachep->ctor(objp); if (ARCH_SLAB_MINALIGN && ((unsigned long)objp & (ARCH_SLAB_MINALIGN-1))) { - pr_err("0x%p: not aligned to ARCH_SLAB_MINALIGN=%d\n", + pr_err("0x%px: not aligned to ARCH_SLAB_MINALIGN=%d\n", objp, (int)ARCH_SLAB_MINALIGN); } return objp; @@ -4283,7 +4280,7 @@ static void show_symbol(struct seq_file *m, unsigned long address) return; } #endif - seq_printf(m, "%p", (void *)address); + seq_printf(m, "%px", (void *)address); } static int leaks_show(struct seq_file *m, void *p) -- GitLab From 689d77f001cd22da31cc943170e1f6f2e8197035 Mon Sep 17 00:00:00 2001 From: Dmitry Vyukov Date: Thu, 14 Dec 2017 15:33:02 -0800 Subject: [PATCH 1539/2547] kcov: fix comparison callback signature Fix a silly copy-paste bug. We truncated u32 args to u16. Link: http://lkml.kernel.org/r/20171207101134.107168-1-dvyukov@google.com Fixes: ded97d2c2b2c ("kcov: support comparison operands collection") Signed-off-by: Dmitry Vyukov Cc: syzkaller@googlegroups.com Cc: Alexander Potapenko Cc: Vegard Nossum Cc: Quentin Casasnovas Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- kernel/kcov.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/kcov.c b/kernel/kcov.c index 15f33faf4013..7594c033d98a 100644 --- a/kernel/kcov.c +++ b/kernel/kcov.c @@ -157,7 +157,7 @@ void notrace __sanitizer_cov_trace_cmp2(u16 arg1, u16 arg2) } EXPORT_SYMBOL(__sanitizer_cov_trace_cmp2); -void notrace __sanitizer_cov_trace_cmp4(u16 arg1, u16 arg2) +void notrace __sanitizer_cov_trace_cmp4(u32 arg1, u32 arg2) { write_comp_data(KCOV_CMP_SIZE(2), arg1, arg2, _RET_IP_); } @@ -183,7 +183,7 @@ void notrace __sanitizer_cov_trace_const_cmp2(u16 arg1, u16 arg2) } EXPORT_SYMBOL(__sanitizer_cov_trace_const_cmp2); -void notrace __sanitizer_cov_trace_const_cmp4(u16 arg1, u16 arg2) +void notrace __sanitizer_cov_trace_const_cmp4(u32 arg1, u32 arg2) { write_comp_data(KCOV_CMP_SIZE(2) | KCOV_CMP_CONST, arg1, arg2, _RET_IP_); -- GitLab From 0b265c3b3b721dca03e82719ac0e15bc2c89aa3a Mon Sep 17 00:00:00 2001 From: "Liu, Changcheng" Date: Thu, 14 Dec 2017 15:33:05 -0800 Subject: [PATCH 1540/2547] tools/slabinfo-gnuplot: force to use bash shell On some linux distributions, the default link of sh is dash which deoesn't support split array like "${var//,/ }" It's better to force to use bash shell directly. Link: http://lkml.kernel.org/r/20171208093751.GA175471@sofia Signed-off-by: Liu Changcheng Reviewed-by: Sergey Senozhatsky Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- tools/vm/slabinfo-gnuplot.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/vm/slabinfo-gnuplot.sh b/tools/vm/slabinfo-gnuplot.sh index 35b039864b77..0cf28aa6f21c 100644 --- a/tools/vm/slabinfo-gnuplot.sh +++ b/tools/vm/slabinfo-gnuplot.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/bash # Sergey Senozhatsky, 2015 # sergey.senozhatsky.work@gmail.com -- GitLab From 1f704fd0d14043e76e80f6b8b2251b9b2cedcca6 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Thu, 14 Dec 2017 15:33:08 -0800 Subject: [PATCH 1541/2547] mm/frame_vector.c: release a semaphore in 'get_vaddr_frames()' A semaphore is acquired before this check, so we must release it before leaving. Link: http://lkml.kernel.org/r/20171211211009.4971-1-christophe.jaillet@wanadoo.fr Fixes: b7f0554a56f2 ("mm: fail get_vaddr_frames() for filesystem-dax mappings") Signed-off-by: Christophe JAILLET Acked-by: Michal Hocko Cc: Dan Williams Cc: Christian Borntraeger Cc: David Sterba Cc: Greg Kroah-Hartman Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- mm/frame_vector.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/mm/frame_vector.c b/mm/frame_vector.c index 297c7238f7d4..c64dca6e27c2 100644 --- a/mm/frame_vector.c +++ b/mm/frame_vector.c @@ -62,8 +62,10 @@ int get_vaddr_frames(unsigned long start, unsigned int nr_frames, * get_user_pages_longterm() and disallow it for filesystem-dax * mappings. */ - if (vma_is_fsdax(vma)) - return -EOPNOTSUPP; + if (vma_is_fsdax(vma)) { + ret = -EOPNOTSUPP; + goto out; + } if (!(vma->vm_flags & (VM_IO | VM_PFNMAP))) { vec->got_ref = true; -- GitLab From bdcf0a423ea1c40bbb40e7ee483b50fc8aa3d758 Mon Sep 17 00:00:00 2001 From: Thiago Rafael Becker Date: Thu, 14 Dec 2017 15:33:12 -0800 Subject: [PATCH 1542/2547] kernel: make groups_sort calling a responsibility group_info allocators In testing, we found that nfsd threads may call set_groups in parallel for the same entry cached in auth.unix.gid, racing in the call of groups_sort, corrupting the groups for that entry and leading to permission denials for the client. This patch: - Make groups_sort globally visible. - Move the call to groups_sort to the modifiers of group_info - Remove the call to groups_sort from set_groups Link: http://lkml.kernel.org/r/20171211151420.18655-1-thiago.becker@gmail.com Signed-off-by: Thiago Rafael Becker Reviewed-by: Matthew Wilcox Reviewed-by: NeilBrown Acked-by: "J. Bruce Fields" Cc: Al Viro Cc: Martin Schwidefsky Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/s390/kernel/compat_linux.c | 1 + fs/nfsd/auth.c | 3 +++ include/linux/cred.h | 1 + kernel/groups.c | 5 +++-- kernel/uid16.c | 1 + net/sunrpc/auth_gss/gss_rpc_xdr.c | 1 + net/sunrpc/auth_gss/svcauth_gss.c | 1 + net/sunrpc/svcauth_unix.c | 2 ++ 8 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/s390/kernel/compat_linux.c b/arch/s390/kernel/compat_linux.c index f04db3779b34..59eea9c65d3e 100644 --- a/arch/s390/kernel/compat_linux.c +++ b/arch/s390/kernel/compat_linux.c @@ -263,6 +263,7 @@ COMPAT_SYSCALL_DEFINE2(s390_setgroups16, int, gidsetsize, u16 __user *, grouplis return retval; } + groups_sort(group_info); retval = set_current_groups(group_info); put_group_info(group_info); diff --git a/fs/nfsd/auth.c b/fs/nfsd/auth.c index 697f8ae7792d..f650e475d8f0 100644 --- a/fs/nfsd/auth.c +++ b/fs/nfsd/auth.c @@ -60,6 +60,9 @@ int nfsd_setuser(struct svc_rqst *rqstp, struct svc_export *exp) gi->gid[i] = exp->ex_anon_gid; else gi->gid[i] = rqgi->gid[i]; + + /* Each thread allocates its own gi, no race */ + groups_sort(gi); } } else { gi = get_group_info(rqgi); diff --git a/include/linux/cred.h b/include/linux/cred.h index 099058e1178b..631286535d0f 100644 --- a/include/linux/cred.h +++ b/include/linux/cred.h @@ -83,6 +83,7 @@ extern int set_current_groups(struct group_info *); extern void set_groups(struct cred *, struct group_info *); extern int groups_search(const struct group_info *, kgid_t); extern bool may_setgroups(void); +extern void groups_sort(struct group_info *); /* * The security context of a task diff --git a/kernel/groups.c b/kernel/groups.c index e357bc800111..daae2f2dc6d4 100644 --- a/kernel/groups.c +++ b/kernel/groups.c @@ -86,11 +86,12 @@ static int gid_cmp(const void *_a, const void *_b) return gid_gt(a, b) - gid_lt(a, b); } -static void groups_sort(struct group_info *group_info) +void groups_sort(struct group_info *group_info) { sort(group_info->gid, group_info->ngroups, sizeof(*group_info->gid), gid_cmp, NULL); } +EXPORT_SYMBOL(groups_sort); /* a simple bsearch */ int groups_search(const struct group_info *group_info, kgid_t grp) @@ -122,7 +123,6 @@ int groups_search(const struct group_info *group_info, kgid_t grp) void set_groups(struct cred *new, struct group_info *group_info) { put_group_info(new->group_info); - groups_sort(group_info); get_group_info(group_info); new->group_info = group_info; } @@ -206,6 +206,7 @@ SYSCALL_DEFINE2(setgroups, int, gidsetsize, gid_t __user *, grouplist) return retval; } + groups_sort(group_info); retval = set_current_groups(group_info); put_group_info(group_info); diff --git a/kernel/uid16.c b/kernel/uid16.c index ce74a4901d2b..ef1da2a5f9bd 100644 --- a/kernel/uid16.c +++ b/kernel/uid16.c @@ -192,6 +192,7 @@ SYSCALL_DEFINE2(setgroups16, int, gidsetsize, old_gid_t __user *, grouplist) return retval; } + groups_sort(group_info); retval = set_current_groups(group_info); put_group_info(group_info); diff --git a/net/sunrpc/auth_gss/gss_rpc_xdr.c b/net/sunrpc/auth_gss/gss_rpc_xdr.c index c4778cae58ef..444380f968f1 100644 --- a/net/sunrpc/auth_gss/gss_rpc_xdr.c +++ b/net/sunrpc/auth_gss/gss_rpc_xdr.c @@ -231,6 +231,7 @@ static int gssx_dec_linux_creds(struct xdr_stream *xdr, goto out_free_groups; creds->cr_group_info->gid[i] = kgid; } + groups_sort(creds->cr_group_info); return 0; out_free_groups: diff --git a/net/sunrpc/auth_gss/svcauth_gss.c b/net/sunrpc/auth_gss/svcauth_gss.c index 5dd4e6c9fef2..26531193fce4 100644 --- a/net/sunrpc/auth_gss/svcauth_gss.c +++ b/net/sunrpc/auth_gss/svcauth_gss.c @@ -481,6 +481,7 @@ static int rsc_parse(struct cache_detail *cd, goto out; rsci.cred.cr_group_info->gid[i] = kgid; } + groups_sort(rsci.cred.cr_group_info); /* mech name */ len = qword_get(&mesg, buf, mlen); diff --git a/net/sunrpc/svcauth_unix.c b/net/sunrpc/svcauth_unix.c index 740b67d5a733..af7f28fb8102 100644 --- a/net/sunrpc/svcauth_unix.c +++ b/net/sunrpc/svcauth_unix.c @@ -520,6 +520,7 @@ static int unix_gid_parse(struct cache_detail *cd, ug.gi->gid[i] = kgid; } + groups_sort(ug.gi); ugp = unix_gid_lookup(cd, uid); if (ugp) { struct cache_head *ch; @@ -819,6 +820,7 @@ svcauth_unix_accept(struct svc_rqst *rqstp, __be32 *authp) kgid_t kgid = make_kgid(&init_user_ns, svc_getnl(argv)); cred->cr_group_info->gid[i] = kgid; } + groups_sort(cred->cr_group_info); if (svc_getu32(argv) != htonl(RPC_AUTH_NULL) || svc_getu32(argv) != 0) { *authp = rpc_autherr_badverf; return SVC_DENIED; -- GitLab From 4837fe37adff1d159904f0c013471b1ecbcb455e Mon Sep 17 00:00:00 2001 From: Michal Hocko Date: Thu, 14 Dec 2017 15:33:15 -0800 Subject: [PATCH 1543/2547] mm, oom_reaper: fix memory corruption David Rientjes has reported the following memory corruption while the oom reaper tries to unmap the victims address space BUG: Bad page map in process oom_reaper pte:6353826300000000 pmd:00000000 addr:00007f50cab1d000 vm_flags:08100073 anon_vma:ffff9eea335603f0 mapping: (null) index:7f50cab1d file: (null) fault: (null) mmap: (null) readpage: (null) CPU: 2 PID: 1001 Comm: oom_reaper Call Trace: unmap_page_range+0x1068/0x1130 __oom_reap_task_mm+0xd5/0x16b oom_reaper+0xff/0x14c kthread+0xc1/0xe0 Tetsuo Handa has noticed that the synchronization inside exit_mmap is insufficient. We only synchronize with the oom reaper if tsk_is_oom_victim which is not true if the final __mmput is called from a different context than the oom victim exit path. This can trivially happen from context of any task which has grabbed mm reference (e.g. to read /proc// file which requires mm etc.). The race would look like this oom_reaper oom_victim task mmget_not_zero do_exit mmput __oom_reap_task_mm mmput __mmput exit_mmap remove_vma unmap_page_range Fix this issue by providing a new mm_is_oom_victim() helper which operates on the mm struct rather than a task. Any context which operates on a remote mm struct should use this helper in place of tsk_is_oom_victim. The flag is set in mark_oom_victim and never cleared so it is stable in the exit_mmap path. Debugged by Tetsuo Handa. Link: http://lkml.kernel.org/r/20171210095130.17110-1-mhocko@kernel.org Fixes: 212925802454 ("mm: oom: let oom_reap_task and exit_mmap run concurrently") Signed-off-by: Michal Hocko Reported-by: David Rientjes Acked-by: David Rientjes Cc: Tetsuo Handa Cc: Andrea Argangeli Cc: [4.14] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/oom.h | 9 +++++++++ include/linux/sched/coredump.h | 1 + mm/mmap.c | 10 +++++----- mm/oom_kill.c | 4 +++- 4 files changed, 18 insertions(+), 6 deletions(-) diff --git a/include/linux/oom.h b/include/linux/oom.h index 01c91d874a57..5bad038ac012 100644 --- a/include/linux/oom.h +++ b/include/linux/oom.h @@ -66,6 +66,15 @@ static inline bool tsk_is_oom_victim(struct task_struct * tsk) return tsk->signal->oom_mm; } +/* + * Use this helper if tsk->mm != mm and the victim mm needs a special + * handling. This is guaranteed to stay true after once set. + */ +static inline bool mm_is_oom_victim(struct mm_struct *mm) +{ + return test_bit(MMF_OOM_VICTIM, &mm->flags); +} + /* * Checks whether a page fault on the given mm is still reliable. * This is no longer true if the oom reaper started to reap the diff --git a/include/linux/sched/coredump.h b/include/linux/sched/coredump.h index 9c8847395b5e..ec912d01126f 100644 --- a/include/linux/sched/coredump.h +++ b/include/linux/sched/coredump.h @@ -70,6 +70,7 @@ static inline int get_dumpable(struct mm_struct *mm) #define MMF_UNSTABLE 22 /* mm is unstable for copy_from_user */ #define MMF_HUGE_ZERO_PAGE 23 /* mm has ever used the global huge zero page */ #define MMF_DISABLE_THP 24 /* disable THP for all VMAs */ +#define MMF_OOM_VICTIM 25 /* mm is the oom victim */ #define MMF_DISABLE_THP_MASK (1 << MMF_DISABLE_THP) #define MMF_INIT_MASK (MMF_DUMPABLE_MASK | MMF_DUMP_FILTER_MASK |\ diff --git a/mm/mmap.c b/mm/mmap.c index a4d546821214..9efdc021ad22 100644 --- a/mm/mmap.c +++ b/mm/mmap.c @@ -3019,20 +3019,20 @@ void exit_mmap(struct mm_struct *mm) /* Use -1 here to ensure all VMAs in the mm are unmapped */ unmap_vmas(&tlb, vma, 0, -1); - set_bit(MMF_OOM_SKIP, &mm->flags); - if (unlikely(tsk_is_oom_victim(current))) { + if (unlikely(mm_is_oom_victim(mm))) { /* * Wait for oom_reap_task() to stop working on this * mm. Because MMF_OOM_SKIP is already set before * calling down_read(), oom_reap_task() will not run * on this "mm" post up_write(). * - * tsk_is_oom_victim() cannot be set from under us - * either because current->mm is already set to NULL + * mm_is_oom_victim() cannot be set from under us + * either because victim->mm is already set to NULL * under task_lock before calling mmput and oom_mm is - * set not NULL by the OOM killer only if current->mm + * set not NULL by the OOM killer only if victim->mm * is found not NULL while holding the task_lock. */ + set_bit(MMF_OOM_SKIP, &mm->flags); down_write(&mm->mmap_sem); up_write(&mm->mmap_sem); } diff --git a/mm/oom_kill.c b/mm/oom_kill.c index c957be32b27a..29f855551efe 100644 --- a/mm/oom_kill.c +++ b/mm/oom_kill.c @@ -683,8 +683,10 @@ static void mark_oom_victim(struct task_struct *tsk) return; /* oom_mm is bound to the signal struct life time. */ - if (!cmpxchg(&tsk->signal->oom_mm, NULL, mm)) + if (!cmpxchg(&tsk->signal->oom_mm, NULL, mm)) { mmgrab(tsk->signal->oom_mm); + set_bit(MMF_OOM_VICTIM, &mm->flags); + } /* * Make sure that the task is woken up from uninterruptible sleep -- GitLab From 7c2c11b208be09c156573fc0076b7b3646e05219 Mon Sep 17 00:00:00 2001 From: Sudip Mukherjee Date: Thu, 14 Dec 2017 15:33:19 -0800 Subject: [PATCH 1544/2547] arch: define weak abort() gcc toggle -fisolate-erroneous-paths-dereference (default at -O2 onwards) isolates faulty code paths such as null pointer access, divide by zero etc. If gcc port doesnt implement __builtin_trap, an abort() is generated which causes kernel link error. In this case, gcc is generating abort due to 'divide by zero' in lib/mpi/mpih-div.c. Currently 'frv' and 'arc' are failing. Previously other arch was also broken like m32r was fixed by commit d22e3d69ee1a ("m32r: fix build failure"). Let's define this weak function which is common for all arch and fix the problem permanently. We can even remove the arch specific 'abort' after this is done. Link: http://lkml.kernel.org/r/1513118956-8718-1-git-send-email-sudipm.mukherjee@gmail.com Signed-off-by: Sudip Mukherjee Cc: Alexey Brodkin Cc: Vineet Gupta Cc: Sudip Mukherjee Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- kernel/exit.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/kernel/exit.c b/kernel/exit.c index 6b4298a41167..df0c91d5606c 100644 --- a/kernel/exit.c +++ b/kernel/exit.c @@ -1755,3 +1755,11 @@ COMPAT_SYSCALL_DEFINE5(waitid, return -EFAULT; } #endif + +__weak void abort(void) +{ + BUG(); + + /* if that doesn't kill us, halt */ + panic("Oops failed to kill thread"); +} -- GitLab From b00d607bb188e187c7b60074d2fa91a6f1985029 Mon Sep 17 00:00:00 2001 From: "Steven Rostedt (VMware)" Date: Tue, 5 Dec 2017 04:41:51 -0500 Subject: [PATCH 1545/2547] tracing: Have stack trace not record if RCU is not watching The stack tracer records a stack dump whenever it sees a stack usage that is more than what it ever saw before. This can happen at any function that is being traced. If it happens when the CPU is going idle (or other strange locations), RCU may not be watching, and in this case, the recording of the stack trace will trigger a warning. There's been lots of efforts to make hacks to allow stack tracing to proceed even if RCU is not watching, but this only causes more issues to appear. Simply do not trace a stack if RCU is not watching. It probably isn't a bad stack anyway. Acked-by: "Paul E. McKenney" Signed-off-by: Steven Rostedt (VMware) --- kernel/trace/trace_stack.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/kernel/trace/trace_stack.c b/kernel/trace/trace_stack.c index 734accc02418..3c7bfc4bf5e9 100644 --- a/kernel/trace/trace_stack.c +++ b/kernel/trace/trace_stack.c @@ -209,6 +209,10 @@ stack_trace_call(unsigned long ip, unsigned long parent_ip, if (__this_cpu_read(disable_stack_tracer) != 1) goto out; + /* If rcu is not watching, then save stack trace can fail */ + if (!rcu_is_watching()) + goto out; + ip += MCOUNT_INSN_SIZE; check_stack(ip, &stack); -- GitLab From 093b8886f446c9351c4de512cb1d4afe30e37f6f Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Tue, 12 Dec 2017 10:23:28 -0800 Subject: [PATCH 1546/2547] scsi: core: Use blist_flags_t consistently Use the type blist_flags_t for all variables that represent blacklist flags. Additionally, suppress recently introduced sparse warnings related to blacklist flags. [mkp: fixed commit id] Fixes: 5ebde4694e3b ("scsi: Use 'blist_flags_t' for scsi_devinfo flags") Signed-off-by: Bart Van Assche Reviewed-by: Christoph Hellwig Cc: Hannes Reinecke Cc: Johannes Thumshirn Signed-off-by: Martin K. Petersen --- drivers/scsi/scsi_devinfo.c | 6 ++---- drivers/scsi/scsi_scan.c | 13 +++++++------ drivers/scsi/scsi_sysfs.c | 5 +++-- drivers/scsi/scsi_transport_spi.c | 12 +++++++----- 4 files changed, 19 insertions(+), 17 deletions(-) diff --git a/drivers/scsi/scsi_devinfo.c b/drivers/scsi/scsi_devinfo.c index 449ef5adbb2b..dfb8da83fa50 100644 --- a/drivers/scsi/scsi_devinfo.c +++ b/drivers/scsi/scsi_devinfo.c @@ -374,10 +374,8 @@ int scsi_dev_info_list_add_keyed(int compatible, char *vendor, char *model, model, compatible); if (strflags) - devinfo->flags = simple_strtoul(strflags, NULL, 0); - else - devinfo->flags = flags; - + flags = (__force blist_flags_t)simple_strtoul(strflags, NULL, 0); + devinfo->flags = flags; devinfo->compatible = compatible; if (compatible) diff --git a/drivers/scsi/scsi_scan.c b/drivers/scsi/scsi_scan.c index be5e919db0e8..0880d975eed3 100644 --- a/drivers/scsi/scsi_scan.c +++ b/drivers/scsi/scsi_scan.c @@ -770,7 +770,7 @@ static int scsi_probe_lun(struct scsi_device *sdev, unsigned char *inq_result, * SCSI_SCAN_LUN_PRESENT: a new scsi_device was allocated and initialized **/ static int scsi_add_lun(struct scsi_device *sdev, unsigned char *inq_result, - int *bflags, int async) + blist_flags_t *bflags, int async) { int ret; @@ -1049,14 +1049,15 @@ static unsigned char *scsi_inq_str(unsigned char *buf, unsigned char *inq, * - SCSI_SCAN_LUN_PRESENT: a new scsi_device was allocated and initialized **/ static int scsi_probe_and_add_lun(struct scsi_target *starget, - u64 lun, int *bflagsp, + u64 lun, blist_flags_t *bflagsp, struct scsi_device **sdevp, enum scsi_scan_mode rescan, void *hostdata) { struct scsi_device *sdev; unsigned char *result; - int bflags, res = SCSI_SCAN_NO_RESPONSE, result_len = 256; + blist_flags_t bflags; + int res = SCSI_SCAN_NO_RESPONSE, result_len = 256; struct Scsi_Host *shost = dev_to_shost(starget->dev.parent); /* @@ -1201,7 +1202,7 @@ static int scsi_probe_and_add_lun(struct scsi_target *starget, * Modifies sdevscan->lun. **/ static void scsi_sequential_lun_scan(struct scsi_target *starget, - int bflags, int scsi_level, + blist_flags_t bflags, int scsi_level, enum scsi_scan_mode rescan) { uint max_dev_lun; @@ -1292,7 +1293,7 @@ static void scsi_sequential_lun_scan(struct scsi_target *starget, * 0: scan completed (or no memory, so further scanning is futile) * 1: could not scan with REPORT LUN **/ -static int scsi_report_lun_scan(struct scsi_target *starget, int bflags, +static int scsi_report_lun_scan(struct scsi_target *starget, blist_flags_t bflags, enum scsi_scan_mode rescan) { unsigned char scsi_cmd[MAX_COMMAND_SIZE]; @@ -1538,7 +1539,7 @@ static void __scsi_scan_target(struct device *parent, unsigned int channel, unsigned int id, u64 lun, enum scsi_scan_mode rescan) { struct Scsi_Host *shost = dev_to_shost(parent); - int bflags = 0; + blist_flags_t bflags = 0; int res; struct scsi_target *starget; diff --git a/drivers/scsi/scsi_sysfs.c b/drivers/scsi/scsi_sysfs.c index 50e7d7e4a861..a9996c16f4ae 100644 --- a/drivers/scsi/scsi_sysfs.c +++ b/drivers/scsi/scsi_sysfs.c @@ -967,7 +967,8 @@ sdev_show_wwid(struct device *dev, struct device_attribute *attr, } static DEVICE_ATTR(wwid, S_IRUGO, sdev_show_wwid, NULL); -#define BLIST_FLAG_NAME(name) [ilog2(BLIST_##name)] = #name +#define BLIST_FLAG_NAME(name) \ + [ilog2((__force unsigned int)BLIST_##name)] = #name static const char *const sdev_bflags_name[] = { #include "scsi_devinfo_tbl.c" }; @@ -984,7 +985,7 @@ sdev_show_blacklist(struct device *dev, struct device_attribute *attr, for (i = 0; i < sizeof(sdev->sdev_bflags) * BITS_PER_BYTE; i++) { const char *name = NULL; - if (!(sdev->sdev_bflags & BIT(i))) + if (!(sdev->sdev_bflags & (__force blist_flags_t)BIT(i))) continue; if (i < ARRAY_SIZE(sdev_bflags_name) && sdev_bflags_name[i]) name = sdev_bflags_name[i]; diff --git a/drivers/scsi/scsi_transport_spi.c b/drivers/scsi/scsi_transport_spi.c index d0219e36080c..10ebb213ddb3 100644 --- a/drivers/scsi/scsi_transport_spi.c +++ b/drivers/scsi/scsi_transport_spi.c @@ -50,14 +50,14 @@ /* Our blacklist flags */ enum { - SPI_BLIST_NOIUS = 0x1, + SPI_BLIST_NOIUS = (__force blist_flags_t)0x1, }; /* blacklist table, modelled on scsi_devinfo.c */ static struct { char *vendor; char *model; - unsigned flags; + blist_flags_t flags; } spi_static_device_list[] __initdata = { {"HP", "Ultrium 3-SCSI", SPI_BLIST_NOIUS }, {"IBM", "ULTRIUM-TD3", SPI_BLIST_NOIUS }, @@ -221,9 +221,11 @@ static int spi_device_configure(struct transport_container *tc, { struct scsi_device *sdev = to_scsi_device(dev); struct scsi_target *starget = sdev->sdev_target; - unsigned bflags = scsi_get_device_flags_keyed(sdev, &sdev->inquiry[8], - &sdev->inquiry[16], - SCSI_DEVINFO_SPI); + blist_flags_t bflags; + + bflags = scsi_get_device_flags_keyed(sdev, &sdev->inquiry[8], + &sdev->inquiry[16], + SCSI_DEVINFO_SPI); /* Populate the target capability fields with the values * gleaned from the device inquiry */ -- GitLab From 5771cfffdffe709ae9b403b6f80438ca40bf850e Mon Sep 17 00:00:00 2001 From: Prasad B Munirathnam Date: Tue, 12 Dec 2017 11:40:10 -0800 Subject: [PATCH 1547/2547] scsi: aacraid: Fix I/O drop during reset "FIB_CONTEXT_FLAG_TIMEDOUT" flag is set in aac_eh_abort to indicate command timeout. Using the same flag in reset handler causes the command to time out and the I/Os were dropped. Define a new flag "FIB_CONTEXT_FLAG_EH_RESET" to make sure I/O is properly handled in eh_reset handler. [mkp: tweaked commit message] Signed-off-by: Prasad B Munirathnam Reviewed-by: Raghava Aditya Renukunta Signed-off-by: Martin K. Petersen --- drivers/scsi/aacraid/aacraid.h | 1 + drivers/scsi/aacraid/linit.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/aacraid/aacraid.h b/drivers/scsi/aacraid/aacraid.h index 6e3d81969a77..d52265416da2 100644 --- a/drivers/scsi/aacraid/aacraid.h +++ b/drivers/scsi/aacraid/aacraid.h @@ -1725,6 +1725,7 @@ struct aac_dev #define FIB_CONTEXT_FLAG_NATIVE_HBA (0x00000010) #define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020) #define FIB_CONTEXT_FLAG_SCSI_CMD (0x00000040) +#define FIB_CONTEXT_FLAG_EH_RESET (0x00000080) /* * Define the command values diff --git a/drivers/scsi/aacraid/linit.c b/drivers/scsi/aacraid/linit.c index bdf127aaab41..d55332de08f9 100644 --- a/drivers/scsi/aacraid/linit.c +++ b/drivers/scsi/aacraid/linit.c @@ -1037,7 +1037,7 @@ static int aac_eh_bus_reset(struct scsi_cmnd* cmd) info = &aac->hba_map[bus][cid]; if (bus >= AAC_MAX_BUSES || cid >= AAC_MAX_TARGETS || info->devtype != AAC_DEVTYPE_NATIVE_RAW) { - fib->flags |= FIB_CONTEXT_FLAG_TIMED_OUT; + fib->flags |= FIB_CONTEXT_FLAG_EH_RESET; cmd->SCp.phase = AAC_OWNER_ERROR_HANDLER; } } -- GitLab From 2610acf46b9ed528ec2cacd717bc9d354e452b73 Mon Sep 17 00:00:00 2001 From: Andreas Platschek Date: Thu, 14 Dec 2017 12:50:51 +0100 Subject: [PATCH 1548/2547] dmaengine: fsl-edma: disable clks on all error paths Previously enabled clks are only disabled if clk_prepare_enable() fails. However, there are other error paths were the previously enabled clocks are not disabled. To fix the problem, fsl_disable_clocks() now takes the number of clocks that shall be disabled + unprepared. For existing calls were all clocks were already successfully prepared + enabled, DMAMUX_NR is passed to disable + unprepare all clocks. In error paths were only some clocks were successfully prepared + enabled the loop counter is passed, in order to disable + unprepare all successfully prepared + enabled clocks. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Andreas Platschek Signed-off-by: Vinod Koul --- drivers/dma/fsl-edma.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c index 6775f2c74e25..c7568869284e 100644 --- a/drivers/dma/fsl-edma.c +++ b/drivers/dma/fsl-edma.c @@ -863,11 +863,11 @@ static void fsl_edma_irq_exit( } } -static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma) +static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) { int i; - for (i = 0; i < DMAMUX_NR; i++) + for (i = 0; i < nr_clocks; i++) clk_disable_unprepare(fsl_edma->muxclk[i]); } @@ -904,25 +904,25 @@ static int fsl_edma_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i); fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(fsl_edma->muxbase[i])) + if (IS_ERR(fsl_edma->muxbase[i])) { + /* on error: disable all previously enabled clks */ + fsl_disable_clocks(fsl_edma, i); return PTR_ERR(fsl_edma->muxbase[i]); + } sprintf(clkname, "dmamux%d", i); fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname); if (IS_ERR(fsl_edma->muxclk[i])) { dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); + /* on error: disable all previously enabled clks */ + fsl_disable_clocks(fsl_edma, i); return PTR_ERR(fsl_edma->muxclk[i]); } ret = clk_prepare_enable(fsl_edma->muxclk[i]); - if (ret) { - /* disable only clks which were enabled on error */ - for (; i >= 0; i--) - clk_disable_unprepare(fsl_edma->muxclk[i]); - - dev_err(&pdev->dev, "DMAMUX clk block failed.\n"); - return ret; - } + if (ret) + /* on error: disable all previously enabled clks */ + fsl_disable_clocks(fsl_edma, i); } @@ -976,7 +976,7 @@ static int fsl_edma_probe(struct platform_device *pdev) if (ret) { dev_err(&pdev->dev, "Can't register Freescale eDMA engine. (%d)\n", ret); - fsl_disable_clocks(fsl_edma); + fsl_disable_clocks(fsl_edma, DMAMUX_NR); return ret; } @@ -985,7 +985,7 @@ static int fsl_edma_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Can't register Freescale eDMA of_dma. (%d)\n", ret); dma_async_device_unregister(&fsl_edma->dma_dev); - fsl_disable_clocks(fsl_edma); + fsl_disable_clocks(fsl_edma, DMAMUX_NR); return ret; } @@ -1015,7 +1015,7 @@ static int fsl_edma_remove(struct platform_device *pdev) fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); of_dma_controller_free(np); dma_async_device_unregister(&fsl_edma->dma_dev); - fsl_disable_clocks(fsl_edma); + fsl_disable_clocks(fsl_edma, DMAMUX_NR); return 0; } -- GitLab From 08933099e6404f588f81c2050bfec7313e06eeaf Mon Sep 17 00:00:00 2001 From: Daniele Palmas Date: Thu, 14 Dec 2017 16:54:45 +0100 Subject: [PATCH 1549/2547] USB: serial: option: add support for Telit ME910 PID 0x1101 This patch adds support for PID 0x1101 of Telit ME910. Signed-off-by: Daniele Palmas Cc: stable Signed-off-by: Johan Hovold --- drivers/usb/serial/option.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index 3b3513874cfd..b02fb576b856 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -280,6 +280,7 @@ static void option_instat_callback(struct urb *urb); #define TELIT_PRODUCT_LE922_USBCFG3 0x1043 #define TELIT_PRODUCT_LE922_USBCFG5 0x1045 #define TELIT_PRODUCT_ME910 0x1100 +#define TELIT_PRODUCT_ME910_DUAL_MODEM 0x1101 #define TELIT_PRODUCT_LE920 0x1200 #define TELIT_PRODUCT_LE910 0x1201 #define TELIT_PRODUCT_LE910_USBCFG4 0x1206 @@ -645,6 +646,11 @@ static const struct option_blacklist_info telit_me910_blacklist = { .reserved = BIT(1) | BIT(3), }; +static const struct option_blacklist_info telit_me910_dual_modem_blacklist = { + .sendsetup = BIT(0), + .reserved = BIT(3), +}; + static const struct option_blacklist_info telit_le910_blacklist = { .sendsetup = BIT(0), .reserved = BIT(1) | BIT(2), @@ -1244,6 +1250,8 @@ static const struct usb_device_id option_ids[] = { .driver_info = (kernel_ulong_t)&telit_le922_blacklist_usbcfg0 }, { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_ME910), .driver_info = (kernel_ulong_t)&telit_me910_blacklist }, + { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_ME910_DUAL_MODEM), + .driver_info = (kernel_ulong_t)&telit_me910_dual_modem_blacklist }, { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE910), .driver_info = (kernel_ulong_t)&telit_le910_blacklist }, { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE910_USBCFG4), -- GitLab From 92a18a657fb2e2ffbfa0659af32cc18fd2346516 Mon Sep 17 00:00:00 2001 From: Reinhard Speyerer Date: Fri, 15 Dec 2017 00:39:27 +0100 Subject: [PATCH 1550/2547] USB: serial: qcserial: add Sierra Wireless EM7565 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sierra Wireless EM7565 devices use the QCSERIAL_SWI layout for their serial ports T: Bus=01 Lev=03 Prnt=29 Port=01 Cnt=02 Dev#= 31 Spd=480 MxCh= 0 D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 P: Vendor=1199 ProdID=9091 Rev= 0.06 S: Manufacturer=Sierra Wireless, Incorporated S: Product=Sierra Wireless EM7565 Qualcomm Snapdragon X16 LTE-A S: SerialNumber=xxxxxxxx C:* #Ifs= 4 Cfg#= 1 Atr=a0 MxPwr=500mA I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=qcserial E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=qcserial E: Ad=83(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 3 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=qcserial E: Ad=85(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 8 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=qmi_wwan E: Ad=86(I) Atr=03(Int.) MxPS= 8 Ivl=32ms E: Ad=8e(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=0f(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms but need sendsetup = true for the NMEA port to make it work properly. Simplify the patch compared to v1 as suggested by Bjørn Mork by taking advantage of the fact that existing devices work with sendsetup = true too. Use sendsetup = true for the NMEA interface of QCSERIAL_SWI and add DEVICE_SWI entries for the EM7565 PID 0x9091 and the EM7565 QDL PID 0x9090. Tests with several MC73xx/MC74xx/MC77xx devices have been performed in order to verify backward compatibility. Signed-off-by: Reinhard Speyerer Cc: stable Signed-off-by: Johan Hovold --- drivers/usb/serial/qcserial.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/serial/qcserial.c b/drivers/usb/serial/qcserial.c index e3892541a489..613f91add03d 100644 --- a/drivers/usb/serial/qcserial.c +++ b/drivers/usb/serial/qcserial.c @@ -162,6 +162,8 @@ static const struct usb_device_id id_table[] = { {DEVICE_SWI(0x1199, 0x9079)}, /* Sierra Wireless EM74xx */ {DEVICE_SWI(0x1199, 0x907a)}, /* Sierra Wireless EM74xx QDL */ {DEVICE_SWI(0x1199, 0x907b)}, /* Sierra Wireless EM74xx */ + {DEVICE_SWI(0x1199, 0x9090)}, /* Sierra Wireless EM7565 QDL */ + {DEVICE_SWI(0x1199, 0x9091)}, /* Sierra Wireless EM7565 */ {DEVICE_SWI(0x413c, 0x81a2)}, /* Dell Wireless 5806 Gobi(TM) 4G LTE Mobile Broadband Card */ {DEVICE_SWI(0x413c, 0x81a3)}, /* Dell Wireless 5570 HSPA+ (42Mbps) Mobile Broadband Card */ {DEVICE_SWI(0x413c, 0x81a4)}, /* Dell Wireless 5570e HSPA+ (42Mbps) Mobile Broadband Card */ @@ -342,6 +344,7 @@ static int qcprobe(struct usb_serial *serial, const struct usb_device_id *id) break; case 2: dev_dbg(dev, "NMEA GPS interface found\n"); + sendsetup = true; break; case 3: dev_dbg(dev, "Modem port found\n"); -- GitLab From 967a6a07e95c58eb9c1581d22a1d9c2d1929843f Mon Sep 17 00:00:00 2001 From: Masaharu Hayakawa Date: Wed, 13 Dec 2017 11:33:00 +0900 Subject: [PATCH 1551/2547] mmc: renesas_sdhi: Add MODULE_LICENSE The following error occurs when loading renesas_sdhi_core.c module, so add MODULE_LICENSE("GPL v2"). renesas_sdhi_core: module license 'unspecified' taints kernel. Signed-off-by: Masaharu Hayakawa Fixes: 9d08428afb72 ("mmc: renesas-sdhi: make renesas_sdhi_sys_dmac main module file") Cc: # v4.13+ [Shimoda: Added Fixes tag and Cc to the stable ML] Signed-off-by: Yoshihiro Shimoda Reviewed-by: Simon Horman Acked-by: Wolfram Sang Signed-off-by: Ulf Hansson --- drivers/mmc/host/renesas_sdhi_core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index fcf7235d5742..157e1d9e7725 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -667,3 +668,5 @@ int renesas_sdhi_remove(struct platform_device *pdev) return 0; } EXPORT_SYMBOL_GPL(renesas_sdhi_remove); + +MODULE_LICENSE("GPL v2"); -- GitLab From f29810335965ac1f7bcb501ee2af5f039f792416 Mon Sep 17 00:00:00 2001 From: Lan Tianyu Date: Thu, 14 Dec 2017 03:01:52 -0500 Subject: [PATCH 1552/2547] KVM/x86: Check input paging mode when cs.l is set MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reported by syzkaller: WARNING: CPU: 0 PID: 27962 at arch/x86/kvm/emulate.c:5631 x86_emulate_insn+0x557/0x15f0 [kvm] Modules linked in: kvm_intel kvm [last unloaded: kvm] CPU: 0 PID: 27962 Comm: syz-executor Tainted: G B W 4.15.0-rc2-next-20171208+ #32 Hardware name: Intel Corporation S1200SP/S1200SP, BIOS S1200SP.86B.01.03.0006.040720161253 04/07/2016 RIP: 0010:x86_emulate_insn+0x557/0x15f0 [kvm] RSP: 0018:ffff8807234476d0 EFLAGS: 00010282 RAX: 0000000000000000 RBX: ffff88072d0237a0 RCX: ffffffffa0065c4d RDX: 1ffff100e5a046f9 RSI: 0000000000000003 RDI: ffff88072d0237c8 RBP: ffff880723447728 R08: ffff88072d020000 R09: ffffffffa008d240 R10: 0000000000000002 R11: ffffed00e7d87db3 R12: ffff88072d0237c8 R13: ffff88072d023870 R14: ffff88072d0238c2 R15: ffffffffa008d080 FS: 00007f8a68666700(0000) GS:ffff880802200000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 000000002009506c CR3: 000000071fec4005 CR4: 00000000003626f0 Call Trace: x86_emulate_instruction+0x3bc/0xb70 [kvm] ? reexecute_instruction.part.162+0x130/0x130 [kvm] vmx_handle_exit+0x46d/0x14f0 [kvm_intel] ? trace_event_raw_event_kvm_entry+0xe7/0x150 [kvm] ? handle_vmfunc+0x2f0/0x2f0 [kvm_intel] ? wait_lapic_expire+0x25/0x270 [kvm] vcpu_enter_guest+0x720/0x1ef0 [kvm] ... When CS.L is set, vcpu should run in the 64 bit paging mode. Current kvm set_sregs function doesn't have such check when userspace inputs sreg values. This will lead unexpected behavior. This patch is to add checks for CS.L, EFER.LME, EFER.LMA and CR4.PAE when get SREG inputs from userspace in order to avoid unexpected behavior. Suggested-by: Paolo Bonzini Reported-by: Dmitry Vyukov Cc: Paolo Bonzini Cc: Radim Krčmář Cc: Dmitry Vyukov Cc: Jim Mattson Signed-off-by: Tianyu Lan Signed-off-by: Paolo Bonzini --- arch/x86/kvm/x86.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 56d036b9ad75..3a82f2d4333b 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -7494,6 +7494,29 @@ int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, } EXPORT_SYMBOL_GPL(kvm_task_switch); +int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) +{ + if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG_BIT)) { + /* + * When EFER.LME and CR0.PG are set, the processor is in + * 64-bit mode (though maybe in a 32-bit code segment). + * CR4.PAE and EFER.LMA must be set. + */ + if (!(sregs->cr4 & X86_CR4_PAE_BIT) + || !(sregs->efer & EFER_LMA)) + return -EINVAL; + } else { + /* + * Not in 64-bit mode: EFER.LMA is clear and the code + * segment cannot be 64-bit. + */ + if (sregs->efer & EFER_LMA || sregs->cs.l) + return -EINVAL; + } + + return 0; +} + int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) { @@ -7506,6 +7529,9 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, (sregs->cr4 & X86_CR4_OSXSAVE)) return -EINVAL; + if (kvm_valid_sregs(vcpu, sregs)) + return -EINVAL; + apic_base_msr.data = sregs->apic_base; apic_base_msr.host_initiated = true; if (kvm_set_apic_base(vcpu, &apic_base_msr)) -- GitLab From cef31d9af908243421258f1df35a4a644604efbe Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Fri, 15 Dec 2017 10:32:03 +0100 Subject: [PATCH 1553/2547] posix-timer: Properly check sigevent->sigev_notify timer_create() specifies via sigevent->sigev_notify the signal delivery for the new timer. The valid modes are SIGEV_NONE, SIGEV_SIGNAL, SIGEV_THREAD and (SIGEV_SIGNAL | SIGEV_THREAD_ID). The sanity check in good_sigevent() is only checking the valid combination for the SIGEV_THREAD_ID bit, i.e. SIGEV_SIGNAL, but if SIGEV_THREAD_ID is not set it accepts any random value. This has no real effects on the posix timer and signal delivery code, but it affects show_timer() which handles the output of /proc/$PID/timers. That function uses a string array to pretty print sigev_notify. The access to that array has no bound checks, so random sigev_notify cause access beyond the array bounds. Add proper checks for the valid notify modes and remove the SIGEV_THREAD_ID masking from various code pathes as SIGEV_NONE can never be set in combination with SIGEV_THREAD_ID. Reported-by: Eric Biggers Reported-by: Dmitry Vyukov Reported-by: Alexey Dobriyan Signed-off-by: Thomas Gleixner Cc: John Stultz Cc: stable@vger.kernel.org --- kernel/time/posix-timers.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/kernel/time/posix-timers.c b/kernel/time/posix-timers.c index 13d6881f908b..ec999f32c840 100644 --- a/kernel/time/posix-timers.c +++ b/kernel/time/posix-timers.c @@ -434,17 +434,22 @@ static struct pid *good_sigevent(sigevent_t * event) { struct task_struct *rtn = current->group_leader; - if ((event->sigev_notify & SIGEV_THREAD_ID ) && - (!(rtn = find_task_by_vpid(event->sigev_notify_thread_id)) || - !same_thread_group(rtn, current) || - (event->sigev_notify & ~SIGEV_THREAD_ID) != SIGEV_SIGNAL)) + switch (event->sigev_notify) { + case SIGEV_SIGNAL | SIGEV_THREAD_ID: + rtn = find_task_by_vpid(event->sigev_notify_thread_id); + if (!rtn || !same_thread_group(rtn, current)) + return NULL; + /* FALLTHRU */ + case SIGEV_SIGNAL: + case SIGEV_THREAD: + if (event->sigev_signo <= 0 || event->sigev_signo > SIGRTMAX) + return NULL; + /* FALLTHRU */ + case SIGEV_NONE: + return task_pid(rtn); + default: return NULL; - - if (((event->sigev_notify & ~SIGEV_THREAD_ID) != SIGEV_NONE) && - ((event->sigev_signo <= 0) || (event->sigev_signo > SIGRTMAX))) - return NULL; - - return task_pid(rtn); + } } static struct k_itimer * alloc_posix_timer(void) @@ -669,7 +674,7 @@ void common_timer_get(struct k_itimer *timr, struct itimerspec64 *cur_setting) struct timespec64 ts64; bool sig_none; - sig_none = (timr->it_sigev_notify & ~SIGEV_THREAD_ID) == SIGEV_NONE; + sig_none = timr->it_sigev_notify == SIGEV_NONE; iv = timr->it_interval; /* interval timer ? */ @@ -856,7 +861,7 @@ int common_timer_set(struct k_itimer *timr, int flags, timr->it_interval = timespec64_to_ktime(new_setting->it_interval); expires = timespec64_to_ktime(new_setting->it_value); - sigev_none = (timr->it_sigev_notify & ~SIGEV_THREAD_ID) == SIGEV_NONE; + sigev_none = timr->it_sigev_notify == SIGEV_NONE; kc->timer_arm(timr, expires, flags & TIMER_ABSTIME, sigev_none); timr->it_active = !sigev_none; -- GitLab From 046046737bd35bed047460f080ea47e186be731e Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 15 Nov 2017 10:43:16 +0100 Subject: [PATCH 1554/2547] phy: tegra: fix device-tree node lookups Fix child-node lookups during probe, which ended up searching the whole device tree depth-first starting at the parents rather than just matching on their children. To make things worse, some parent nodes could end up being being prematurely freed (by tegra_xusb_pad_register()) as of_find_node_by_name() drops a reference to its first argument. Fixes: 53d2a715c240 ("phy: Add Tegra XUSB pad controller support") Cc: stable # 4.7 Cc: Thierry Reding Signed-off-by: Johan Hovold Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/tegra/xusb.c | 58 ++++++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index 4307bf0013e1..63e916d4d069 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -75,14 +75,14 @@ MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match); static struct device_node * tegra_xusb_find_pad_node(struct tegra_xusb_padctl *padctl, const char *name) { - /* - * of_find_node_by_name() drops a reference, so make sure to grab one. - */ - struct device_node *np = of_node_get(padctl->dev->of_node); + struct device_node *pads, *np; + + pads = of_get_child_by_name(padctl->dev->of_node, "pads"); + if (!pads) + return NULL; - np = of_find_node_by_name(np, "pads"); - if (np) - np = of_find_node_by_name(np, name); + np = of_get_child_by_name(pads, name); + of_node_put(pads); return np; } @@ -90,16 +90,16 @@ tegra_xusb_find_pad_node(struct tegra_xusb_padctl *padctl, const char *name) static struct device_node * tegra_xusb_pad_find_phy_node(struct tegra_xusb_pad *pad, unsigned int index) { - /* - * of_find_node_by_name() drops a reference, so make sure to grab one. - */ - struct device_node *np = of_node_get(pad->dev.of_node); + struct device_node *np, *lanes; - np = of_find_node_by_name(np, "lanes"); - if (!np) + lanes = of_get_child_by_name(pad->dev.of_node, "lanes"); + if (!lanes) return NULL; - return of_find_node_by_name(np, pad->soc->lanes[index].name); + np = of_get_child_by_name(lanes, pad->soc->lanes[index].name); + of_node_put(lanes); + + return np; } static int @@ -195,7 +195,7 @@ int tegra_xusb_pad_register(struct tegra_xusb_pad *pad, unsigned int i; int err; - children = of_find_node_by_name(pad->dev.of_node, "lanes"); + children = of_get_child_by_name(pad->dev.of_node, "lanes"); if (!children) return -ENODEV; @@ -444,21 +444,21 @@ static struct device_node * tegra_xusb_find_port_node(struct tegra_xusb_padctl *padctl, const char *type, unsigned int index) { - /* - * of_find_node_by_name() drops a reference, so make sure to grab one. - */ - struct device_node *np = of_node_get(padctl->dev->of_node); + struct device_node *ports, *np; + char *name; - np = of_find_node_by_name(np, "ports"); - if (np) { - char *name; + ports = of_get_child_by_name(padctl->dev->of_node, "ports"); + if (!ports) + return NULL; - name = kasprintf(GFP_KERNEL, "%s-%u", type, index); - if (!name) - return ERR_PTR(-ENOMEM); - np = of_find_node_by_name(np, name); - kfree(name); + name = kasprintf(GFP_KERNEL, "%s-%u", type, index); + if (!name) { + of_node_put(ports); + return ERR_PTR(-ENOMEM); } + np = of_get_child_by_name(ports, name); + kfree(name); + of_node_put(ports); return np; } @@ -847,7 +847,7 @@ static void tegra_xusb_remove_ports(struct tegra_xusb_padctl *padctl) static int tegra_xusb_padctl_probe(struct platform_device *pdev) { - struct device_node *np = of_node_get(pdev->dev.of_node); + struct device_node *np = pdev->dev.of_node; const struct tegra_xusb_padctl_soc *soc; struct tegra_xusb_padctl *padctl; const struct of_device_id *match; @@ -855,7 +855,7 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev) int err; /* for backwards compatibility with old device trees */ - np = of_find_node_by_name(np, "pads"); + np = of_get_child_by_name(np, "pads"); if (!np) { dev_warn(&pdev->dev, "deprecated DT, using legacy driver\n"); return tegra_xusb_padctl_legacy_probe(pdev); -- GitLab From e796cc6a3a9186c92092e2f5929cf8f65b56cf01 Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Fri, 17 Nov 2017 16:55:35 +0530 Subject: [PATCH 1555/2547] phy: cpcap-usb: Fix platform_get_irq_byname's error checking. The platform_get_irq_byname() function returns negative if an error occurs. zero or positive number on success. platform_get_irq_byname() error checking for zero is not correct. Fixes: 6d6ce40f63af ("phy: cpcap-usb: Add CPCAP PMIC USB support") Signed-off-by: Arvind Yadav Reviewed-by: Sebastian Reichel Acked-by: Tony Lindgren Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/motorola/phy-cpcap-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/motorola/phy-cpcap-usb.c b/drivers/phy/motorola/phy-cpcap-usb.c index accaaaccb662..6601ad0dfb3a 100644 --- a/drivers/phy/motorola/phy-cpcap-usb.c +++ b/drivers/phy/motorola/phy-cpcap-usb.c @@ -310,7 +310,7 @@ static int cpcap_usb_init_irq(struct platform_device *pdev, int irq, error; irq = platform_get_irq_byname(pdev, name); - if (!irq) + if (irq < 0) return -ENODEV; error = devm_request_threaded_irq(ddata->dev, irq, NULL, -- GitLab From 3cb0ab6e008f2a9ffe2d1be4246984003caed7e2 Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Thu, 8 Sep 2016 10:38:11 -0700 Subject: [PATCH 1556/2547] phy: rockchip-typec: add pm_runtime_disable in err case Add pm_runtime_disable in err case to make the pm_runtime_enable/disable is invoked balanced. Signed-off-by: Chris Zhong Reviewed-by: Brian Norris Reviewed-by: Douglas Anderson Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/rockchip/phy-rockchip-typec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index ee85fa0ca4b0..7492c8978217 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -1137,6 +1137,7 @@ static int rockchip_typec_phy_probe(struct platform_device *pdev) if (IS_ERR(phy)) { dev_err(dev, "failed to create phy: %s\n", child_np->name); + pm_runtime_disable(dev); return PTR_ERR(phy); } @@ -1146,6 +1147,7 @@ static int rockchip_typec_phy_probe(struct platform_device *pdev) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); if (IS_ERR(phy_provider)) { dev_err(dev, "Failed to register phy provider\n"); + pm_runtime_disable(dev); return PTR_ERR(phy_provider); } -- GitLab From 2b88212c4cc67ff33dec5bb4d690044b97a5f979 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 2 Nov 2017 12:56:36 +0100 Subject: [PATCH 1557/2547] phy: rcar-gen3-usb2: select USB_COMMON When USB is disabled, we get a link error for this driver because of the added OTG support drivers/phy/renesas/phy-rcar-gen3-usb2.o: In function `rcar_gen3_phy_usb2_probe': phy-rcar-gen3-usb2.c:(.text+0x250): undefined reference to `of_usb_get_dr_mode_by_phy' Other phy drivers select USB_COMMON for this, so let's do the same here. Fixes: 7e0540f41332 ("phy: rcar-gen3-usb2: check dr_mode for otg mode") Signed-off-by: Arnd Bergmann Acked-by: Yoshihiro Shimoda Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/renesas/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/renesas/Kconfig b/drivers/phy/renesas/Kconfig index cb09245e9b4c..c845facacb06 100644 --- a/drivers/phy/renesas/Kconfig +++ b/drivers/phy/renesas/Kconfig @@ -12,7 +12,9 @@ config PHY_RCAR_GEN3_USB2 tristate "Renesas R-Car generation 3 USB 2.0 PHY driver" depends on ARCH_RENESAS depends on EXTCON + depends on USB_SUPPORT select GENERIC_PHY + select USB_COMMON help Support for USB 2.0 PHY found on Renesas R-Car generation 3 SoCs. -- GitLab From 090edbe23ff57940fca7f57d9165ce57a826bd7a Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Thu, 14 Dec 2017 13:19:05 -0800 Subject: [PATCH 1558/2547] x86/power/64: Use struct desc_ptr for the IDT in struct saved_context x86_64's saved_context nonsensically used separate idt_limit and idt_base fields and then cast &idt_limit to struct desc_ptr *. This was correct (with -fno-strict-aliasing), but it's confusing, served no purpose, and required #ifdeffery. Simplify this by using struct desc_ptr directly. No change in functionality. Tested-by: Jarkko Nikula Signed-off-by: Andy Lutomirski Acked-by: Rafael J. Wysocki Acked-by: Thomas Gleixner Cc: Borislav Petkov Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Pavel Machek Cc: Peter Zijlstra Cc: Rafael J. Wysocki Cc: Zhang Rui Link: http://lkml.kernel.org/r/967909ce38d341b01d45eff53e278e2728a3a93a.1513286253.git.luto@kernel.org Signed-off-by: Ingo Molnar --- arch/x86/include/asm/suspend_64.h | 3 +-- arch/x86/power/cpu.c | 11 +---------- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/suspend_64.h b/arch/x86/include/asm/suspend_64.h index 7306e911faee..600e9e0aea51 100644 --- a/arch/x86/include/asm/suspend_64.h +++ b/arch/x86/include/asm/suspend_64.h @@ -30,8 +30,7 @@ struct saved_context { u16 gdt_pad; /* Unused */ struct desc_ptr gdt_desc; u16 idt_pad; - u16 idt_limit; - unsigned long idt_base; + struct desc_ptr idt; u16 ldt; u16 tss; unsigned long tr; diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index 5191de14f4df..472bc8c8212b 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -82,12 +82,8 @@ static void __save_processor_state(struct saved_context *ctxt) /* * descriptor tables */ -#ifdef CONFIG_X86_32 store_idt(&ctxt->idt); -#else -/* CONFIG_X86_64 */ - store_idt((struct desc_ptr *)&ctxt->idt_limit); -#endif + /* * We save it here, but restore it only in the hibernate case. * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit @@ -219,12 +215,7 @@ static void notrace __restore_processor_state(struct saved_context *ctxt) * now restore the descriptor tables to their proper values * ltr is done i fix_processor_context(). */ -#ifdef CONFIG_X86_32 load_idt(&ctxt->idt); -#else -/* CONFIG_X86_64 */ - load_idt((const struct desc_ptr *)&ctxt->idt_limit); -#endif #ifdef CONFIG_X86_64 /* -- GitLab From 896c80bef4d3b357814a476663158aaf669d0fb3 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Thu, 14 Dec 2017 13:19:06 -0800 Subject: [PATCH 1559/2547] x86/power/32: Move SYSENTER MSR restoration to fix_processor_context() x86_64 restores system call MSRs in fix_processor_context(), and x86_32 restored them along with segment registers. The 64-bit variant makes more sense, so move the 32-bit code to match the 64-bit code. No side effects are expected to runtime behavior. Tested-by: Jarkko Nikula Signed-off-by: Andy Lutomirski Acked-by: Rafael J. Wysocki Acked-by: Thomas Gleixner Cc: Borislav Petkov Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Pavel Machek Cc: Peter Zijlstra Cc: Rafael J. Wysocki Cc: Zhang Rui Link: http://lkml.kernel.org/r/65158f8d7ee64dd6bbc6c1c83b3b34aaa854e3ae.1513286253.git.luto@kernel.org Signed-off-by: Ingo Molnar --- arch/x86/power/cpu.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index 472bc8c8212b..033c61e6891b 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -174,6 +174,9 @@ static void fix_processor_context(void) write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS); syscall_init(); /* This sets MSR_*STAR and related */ +#else + if (boot_cpu_has(X86_FEATURE_SEP)) + enable_sep_cpu(); #endif load_TR_desc(); /* This does ltr */ load_mm_ldt(current->active_mm); /* This does lldt */ @@ -237,12 +240,6 @@ static void notrace __restore_processor_state(struct saved_context *ctxt) loadsegment(fs, ctxt->fs); loadsegment(gs, ctxt->gs); loadsegment(ss, ctxt->ss); - - /* - * sysenter MSRs - */ - if (boot_cpu_has(X86_FEATURE_SEP)) - enable_sep_cpu(); #else /* CONFIG_X86_64 */ asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds)); -- GitLab From 7ee18d677989e99635027cee04c878950e0752b9 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Thu, 14 Dec 2017 13:19:07 -0800 Subject: [PATCH 1560/2547] x86/power: Make restore_processor_context() sane My previous attempt to fix a couple of bugs in __restore_processor_context(): 5b06bbcfc2c6 ("x86/power: Fix some ordering bugs in __restore_processor_context()") ... introduced yet another bug, breaking suspend-resume. Rather than trying to come up with a minimal fix, let's try to clean it up for real. This patch fixes quite a few things: - The old code saved a nonsensical subset of segment registers. The only registers that need to be saved are those that contain userspace state or those that can't be trivially restored without percpu access working. (On x86_32, we can restore percpu access by writing __KERNEL_PERCPU to %fs. On x86_64, it's easier to save and restore the kernel's GSBASE.) With this patch, we restore hardcoded values to the kernel state where applicable and explicitly restore the user state after fixing all the descriptor tables. - We used to use an unholy mix of inline asm and C helpers for segment register access. Let's get rid of the inline asm. This fixes the reported s2ram hangs and make the code all around more logical. Analyzed-by: Linus Torvalds Reported-by: Jarkko Nikula Reported-by: Pavel Machek Tested-by: Jarkko Nikula Tested-by: Pavel Machek Signed-off-by: Andy Lutomirski Acked-by: Rafael J. Wysocki Acked-by: Thomas Gleixner Cc: Borislav Petkov Cc: Josh Poimboeuf Cc: Peter Zijlstra Cc: Rafael J. Wysocki Cc: Zhang Rui Fixes: 5b06bbcfc2c6 ("x86/power: Fix some ordering bugs in __restore_processor_context()") Link: http://lkml.kernel.org/r/398ee68e5c0f766425a7b746becfc810840770ff.1513286253.git.luto@kernel.org Signed-off-by: Ingo Molnar --- arch/x86/include/asm/suspend_32.h | 8 +++- arch/x86/include/asm/suspend_64.h | 16 ++++++- arch/x86/power/cpu.c | 79 ++++++++++++++++--------------- 3 files changed, 62 insertions(+), 41 deletions(-) diff --git a/arch/x86/include/asm/suspend_32.h b/arch/x86/include/asm/suspend_32.h index 982c325dad33..8be6afb58471 100644 --- a/arch/x86/include/asm/suspend_32.h +++ b/arch/x86/include/asm/suspend_32.h @@ -12,7 +12,13 @@ /* image of the saved processor state */ struct saved_context { - u16 es, fs, gs, ss; + /* + * On x86_32, all segment registers, with the possible exception of + * gs, are saved at kernel entry in pt_regs. + */ +#ifdef CONFIG_X86_32_LAZY_GS + u16 gs; +#endif unsigned long cr0, cr2, cr3, cr4; u64 misc_enable; bool misc_enable_saved; diff --git a/arch/x86/include/asm/suspend_64.h b/arch/x86/include/asm/suspend_64.h index 600e9e0aea51..a7af9f53c0cb 100644 --- a/arch/x86/include/asm/suspend_64.h +++ b/arch/x86/include/asm/suspend_64.h @@ -20,8 +20,20 @@ */ struct saved_context { struct pt_regs regs; - u16 ds, es, fs, gs, ss; - unsigned long gs_base, gs_kernel_base, fs_base; + + /* + * User CS and SS are saved in current_pt_regs(). The rest of the + * segment selectors need to be saved and restored here. + */ + u16 ds, es, fs, gs; + + /* + * Usermode FSBASE and GSBASE may not match the fs and gs selectors, + * so we save them separately. We save the kernelmode GSBASE to + * restore percpu access after resume. + */ + unsigned long kernelmode_gs_base, usermode_gs_base, fs_base; + unsigned long cr0, cr2, cr3, cr4, cr8; u64 misc_enable; bool misc_enable_saved; diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index 033c61e6891b..36a28eddb435 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -99,22 +99,18 @@ static void __save_processor_state(struct saved_context *ctxt) /* * segment registers */ -#ifdef CONFIG_X86_32 - savesegment(es, ctxt->es); - savesegment(fs, ctxt->fs); +#ifdef CONFIG_X86_32_LAZY_GS savesegment(gs, ctxt->gs); - savesegment(ss, ctxt->ss); -#else -/* CONFIG_X86_64 */ - asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds)); - asm volatile ("movw %%es, %0" : "=m" (ctxt->es)); - asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs)); - asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs)); - asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss)); +#endif +#ifdef CONFIG_X86_64 + savesegment(gs, ctxt->gs); + savesegment(fs, ctxt->fs); + savesegment(ds, ctxt->ds); + savesegment(es, ctxt->es); rdmsrl(MSR_FS_BASE, ctxt->fs_base); - rdmsrl(MSR_GS_BASE, ctxt->gs_base); - rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); + rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); + rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); mtrr_save_fixed_ranges(NULL); rdmsrl(MSR_EFER, ctxt->efer); @@ -189,9 +185,12 @@ static void fix_processor_context(void) } /** - * __restore_processor_state - restore the contents of CPU registers saved - * by __save_processor_state() - * @ctxt - structure to load the registers contents from + * __restore_processor_state - restore the contents of CPU registers saved + * by __save_processor_state() + * @ctxt - structure to load the registers contents from + * + * The asm code that gets us here will have restored a usable GDT, although + * it will be pointing to the wrong alias. */ static void notrace __restore_processor_state(struct saved_context *ctxt) { @@ -214,46 +213,50 @@ static void notrace __restore_processor_state(struct saved_context *ctxt) write_cr2(ctxt->cr2); write_cr0(ctxt->cr0); + /* Restore the IDT. */ + load_idt(&ctxt->idt); + /* - * now restore the descriptor tables to their proper values - * ltr is done i fix_processor_context(). + * Just in case the asm code got us here with the SS, DS, or ES + * out of sync with the GDT, update them. */ - load_idt(&ctxt->idt); + loadsegment(ss, __KERNEL_DS); + loadsegment(ds, __USER_DS); + loadsegment(es, __USER_DS); -#ifdef CONFIG_X86_64 /* - * We need GSBASE restored before percpu access can work. - * percpu access can happen in exception handlers or in complicated - * helpers like load_gs_index(). + * Restore percpu access. Percpu access can happen in exception + * handlers or in complicated helpers like load_gs_index(). */ - wrmsrl(MSR_GS_BASE, ctxt->gs_base); +#ifdef CONFIG_X86_64 + wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); +#else + loadsegment(fs, __KERNEL_PERCPU); + loadsegment(gs, __KERNEL_STACK_CANARY); #endif + /* Restore the TSS, RO GDT, LDT, and usermode-relevant MSRs. */ fix_processor_context(); /* - * Restore segment registers. This happens after restoring the GDT - * and LDT, which happen in fix_processor_context(). + * Now that we have descriptor tables fully restored and working + * exception handling, restore the usermode segments. */ -#ifdef CONFIG_X86_32 +#ifdef CONFIG_X86_64 + loadsegment(ds, ctxt->es); loadsegment(es, ctxt->es); loadsegment(fs, ctxt->fs); - loadsegment(gs, ctxt->gs); - loadsegment(ss, ctxt->ss); -#else -/* CONFIG_X86_64 */ - asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds)); - asm volatile ("movw %0, %%es" :: "r" (ctxt->es)); - asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs)); load_gs_index(ctxt->gs); - asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss)); /* - * Restore FSBASE and user GSBASE after reloading the respective - * segment selectors. + * Restore FSBASE and GSBASE after restoring the selectors, since + * restoring the selectors clobbers the bases. Keep in mind + * that MSR_KERNEL_GS_BASE is horribly misnamed. */ wrmsrl(MSR_FS_BASE, ctxt->fs_base); - wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); + wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); +#elif defined(CONFIG_X86_32_LAZY_GS) + loadsegment(gs, ctxt->gs); #endif do_fpu_end(); -- GitLab From ee2202d73b4c9977ce0120fc8631a1c90bfbd77c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 15 Dec 2017 10:17:53 +0000 Subject: [PATCH 1561/2547] drm/i915: Allow internal page allocations to fail Internal objects consistent of scratch pages not subject to the persistence guarantees of user facing objects. They are used for example, in ring buffers where they are only required for temporary storage of commands that will be rewritten every time. As they are temporary constructs, quietly report -ENOMEM back along the callchain rather than subject the system to oomkiller if an allocation fails. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Matthew Auld Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171215101753.1519-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem_internal.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_internal.c b/drivers/gpu/drm/i915/i915_gem_internal.c index ee83ec838ee7..a1d6956734f7 100644 --- a/drivers/gpu/drm/i915/i915_gem_internal.c +++ b/drivers/gpu/drm/i915/i915_gem_internal.c @@ -27,6 +27,7 @@ #include "i915_drv.h" #define QUIET (__GFP_NORETRY | __GFP_NOWARN) +#define MAYFAIL (__GFP_RETRY_MAYFAIL | __GFP_NOWARN) /* convert swiotlb segment size into sensible units (pages)! */ #define IO_TLB_SEGPAGES (IO_TLB_SEGSIZE << IO_TLB_SHIFT >> PAGE_SHIFT) @@ -95,7 +96,8 @@ static int i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj) struct page *page; do { - page = alloc_pages(gfp | (order ? QUIET : 0), order); + page = alloc_pages(gfp | (order ? QUIET : MAYFAIL), + order); if (page) break; if (!order--) -- GitLab From 99cd05c43baac8ef56c20eb1776a15b02c81ccc3 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 13 Dec 2017 18:28:58 +0000 Subject: [PATCH 1562/2547] drm/i915/lpe: Remove double-encapsulation of info string Just printk the string, or at least do not double up on the newlines! Fixes: eef57324d926 ("drm/i915: setup bridge for HDMI LPE audio driver") Signed-off-by: Chris Wilson Cc: Pierre-Louis Bossart Cc: Jerome Anand Cc: Jani Nikula Cc: Takashi Iwai Reviewed-by: Dhinakaran Pandiyan Link: https://patchwork.freedesktop.org/patch/msgid/20171213182858.2159-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_lpe_audio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_lpe_audio.c b/drivers/gpu/drm/i915/intel_lpe_audio.c index 3bf65288ffff..5809b29044fc 100644 --- a/drivers/gpu/drm/i915/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/intel_lpe_audio.c @@ -193,7 +193,7 @@ static bool lpe_audio_detect(struct drm_i915_private *dev_priv) }; if (!pci_dev_present(atom_hdaudio_ids)) { - DRM_INFO("%s\n", "HDaudio controller not detected, using LPE audio instead\n"); + DRM_INFO("HDaudio controller not detected, using LPE audio instead\n"); lpe_present = true; } } -- GitLab From f5b5fab1780c98b74526dbac527574bd02dc16f8 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Mon, 11 Dec 2017 10:38:36 -0800 Subject: [PATCH 1563/2547] x86/decoder: Fix and update the opcodes map Update x86-opcode-map.txt based on the October 2017 Intel SDM publication. Fix INVPID to INVVPID. Add UD0 and UD1 instruction opcodes. Also sync the objtool and perf tooling copies of this file. Signed-off-by: Randy Dunlap Acked-by: Masami Hiramatsu Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Masami Hiramatsu Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/aac062d7-c0f6-96e3-5c92-ed299e2bd3da@infradead.org Signed-off-by: Ingo Molnar --- arch/x86/lib/x86-opcode-map.txt | 13 +++++++++++-- tools/objtool/arch/x86/insn/x86-opcode-map.txt | 15 ++++++++++++--- .../perf/util/intel-pt-decoder/x86-opcode-map.txt | 15 ++++++++++++--- 3 files changed, 35 insertions(+), 8 deletions(-) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index c4d55919fac1..e0b85930dd77 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -607,7 +607,7 @@ fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(v1) fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1) fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1) fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1) -ff: +ff: UD0 EndTable Table: 3-byte opcode 1 (0x0f 0x38) @@ -717,7 +717,7 @@ AVXcode: 2 7e: vpermt2d/q Vx,Hx,Wx (66),(ev) 7f: vpermt2ps/d Vx,Hx,Wx (66),(ev) 80: INVEPT Gy,Mdq (66) -81: INVPID Gy,Mdq (66) +81: INVVPID Gy,Mdq (66) 82: INVPCID Gy,Mdq (66) 83: vpmultishiftqb Vx,Hx,Wx (66),(ev) 88: vexpandps/d Vpd,Wpd (66),(ev) @@ -970,6 +970,15 @@ GrpTable: Grp9 EndTable GrpTable: Grp10 +# all are UD1 +0: UD1 +1: UD1 +2: UD1 +3: UD1 +4: UD1 +5: UD1 +6: UD1 +7: UD1 EndTable # Grp11A and Grp11B are expressed as Grp11 in Intel SDM diff --git a/tools/objtool/arch/x86/insn/x86-opcode-map.txt b/tools/objtool/arch/x86/insn/x86-opcode-map.txt index 12e377184ee4..e0b85930dd77 100644 --- a/tools/objtool/arch/x86/insn/x86-opcode-map.txt +++ b/tools/objtool/arch/x86/insn/x86-opcode-map.txt @@ -607,7 +607,7 @@ fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(v1) fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1) fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1) fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1) -ff: +ff: UD0 EndTable Table: 3-byte opcode 1 (0x0f 0x38) @@ -717,7 +717,7 @@ AVXcode: 2 7e: vpermt2d/q Vx,Hx,Wx (66),(ev) 7f: vpermt2ps/d Vx,Hx,Wx (66),(ev) 80: INVEPT Gy,Mdq (66) -81: INVPID Gy,Mdq (66) +81: INVVPID Gy,Mdq (66) 82: INVPCID Gy,Mdq (66) 83: vpmultishiftqb Vx,Hx,Wx (66),(ev) 88: vexpandps/d Vpd,Wpd (66),(ev) @@ -896,7 +896,7 @@ EndTable GrpTable: Grp3_1 0: TEST Eb,Ib -1: +1: TEST Eb,Ib 2: NOT Eb 3: NEG Eb 4: MUL AL,Eb @@ -970,6 +970,15 @@ GrpTable: Grp9 EndTable GrpTable: Grp10 +# all are UD1 +0: UD1 +1: UD1 +2: UD1 +3: UD1 +4: UD1 +5: UD1 +6: UD1 +7: UD1 EndTable # Grp11A and Grp11B are expressed as Grp11 in Intel SDM diff --git a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt index 12e377184ee4..e0b85930dd77 100644 --- a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt +++ b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt @@ -607,7 +607,7 @@ fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(v1) fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1) fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1) fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1) -ff: +ff: UD0 EndTable Table: 3-byte opcode 1 (0x0f 0x38) @@ -717,7 +717,7 @@ AVXcode: 2 7e: vpermt2d/q Vx,Hx,Wx (66),(ev) 7f: vpermt2ps/d Vx,Hx,Wx (66),(ev) 80: INVEPT Gy,Mdq (66) -81: INVPID Gy,Mdq (66) +81: INVVPID Gy,Mdq (66) 82: INVPCID Gy,Mdq (66) 83: vpmultishiftqb Vx,Hx,Wx (66),(ev) 88: vexpandps/d Vpd,Wpd (66),(ev) @@ -896,7 +896,7 @@ EndTable GrpTable: Grp3_1 0: TEST Eb,Ib -1: +1: TEST Eb,Ib 2: NOT Eb 3: NEG Eb 4: MUL AL,Eb @@ -970,6 +970,15 @@ GrpTable: Grp9 EndTable GrpTable: Grp10 +# all are UD1 +0: UD1 +1: UD1 +2: UD1 +3: UD1 +4: UD1 +5: UD1 +6: UD1 +7: UD1 EndTable # Grp11A and Grp11B are expressed as Grp11 in Intel SDM -- GitLab From 215eada73e77ede7e15531d99f712481ddd429be Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Fri, 15 Dec 2017 13:36:56 +0100 Subject: [PATCH 1564/2547] objtool: Resync objtool's instruction decoder source code copy with the kernel's latest version This fixes the following warning: warning: objtool: x86 instruction decoder differs from kernel Note that there are cleanups queued up for v4.16 that will make this warning more informative and will make the syncing easier as well. Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- tools/objtool/arch/x86/insn/inat.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/objtool/arch/x86/insn/inat.h b/tools/objtool/arch/x86/insn/inat.h index 125ecd2a300d..52dc8d911173 100644 --- a/tools/objtool/arch/x86/insn/inat.h +++ b/tools/objtool/arch/x86/insn/inat.h @@ -97,6 +97,16 @@ #define INAT_MAKE_GROUP(grp) ((grp << INAT_GRP_OFFS) | INAT_MODRM) #define INAT_MAKE_IMM(imm) (imm << INAT_IMM_OFFS) +/* Identifiers for segment registers */ +#define INAT_SEG_REG_IGNORE 0 +#define INAT_SEG_REG_DEFAULT 1 +#define INAT_SEG_REG_CS 2 +#define INAT_SEG_REG_SS 3 +#define INAT_SEG_REG_DS 4 +#define INAT_SEG_REG_ES 5 +#define INAT_SEG_REG_FS 6 +#define INAT_SEG_REG_GS 7 + /* Attribute search APIs */ extern insn_attr_t inat_get_opcode_attribute(insn_byte_t opcode); extern int inat_get_last_prefix_id(insn_byte_t last_pfx); -- GitLab From 643e345c95f0b4a4082c60755e06e3e635658da6 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Fri, 15 Dec 2017 13:47:51 +0100 Subject: [PATCH 1565/2547] tools/headers: Synchronize kernel <-> tooling headers Two kernel headers got modified recently, which are used by tooling as well: tools/include/uapi/linux/kvm.h arch/x86/include/asm/cpufeatures.h None of those changes have an effect on tooling, so do a plain copy. Cc: Arnaldo Carvalho de Melo Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Peter Zijlstra Cc: Namhyung Kim Cc: Jiri Olsa Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- tools/arch/x86/include/asm/cpufeatures.h | 1 + tools/include/uapi/linux/kvm.h | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index c0b0e9e8aa66..800104c8a3ed 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -266,6 +266,7 @@ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ +#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ diff --git a/tools/include/uapi/linux/kvm.h b/tools/include/uapi/linux/kvm.h index 282d7613fce8..496e59a2738b 100644 --- a/tools/include/uapi/linux/kvm.h +++ b/tools/include/uapi/linux/kvm.h @@ -630,9 +630,9 @@ struct kvm_s390_irq { struct kvm_s390_irq_state { __u64 buf; - __u32 flags; + __u32 flags; /* will stay unused for compatibility reasons */ __u32 len; - __u32 reserved[4]; + __u32 reserved[4]; /* will stay unused for compatibility reasons */ }; /* for KVM_SET_GUEST_DEBUG */ -- GitLab From 50034ed49645463a16327cad05694e201e6b4126 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 15 Dec 2017 05:09:47 -0800 Subject: [PATCH 1566/2547] cgroup: use strlcpy() instead of strscpy() to avoid spurious warning As long as cft->name is guaranteed to be NUL-terminated, using strlcpy() would work just as well and avoid that warning, so the change below could be folded into that commit. Signed-off-by: Arnd Bergmann Signed-off-by: Tejun Heo --- kernel/cgroup/cgroup.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c index 18d71fbd3923..f4c2f8cb5748 100644 --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c @@ -1397,7 +1397,7 @@ static char *cgroup_file_name(struct cgroup *cgrp, const struct cftype *cft, cgroup_on_dfl(cgrp) ? ss->name : ss->legacy_name, cft->name); else - strscpy(buf, cft->name, CGROUP_FILE_NAME_MAX); + strlcpy(buf, cft->name, CGROUP_FILE_NAME_MAX); return buf; } @@ -1864,9 +1864,9 @@ void init_cgroup_root(struct cgroup_root *root, struct cgroup_sb_opts *opts) root->flags = opts->flags; if (opts->release_agent) - strscpy(root->release_agent_path, opts->release_agent, PATH_MAX); + strlcpy(root->release_agent_path, opts->release_agent, PATH_MAX); if (opts->name) - strscpy(root->name, opts->name, MAX_CGROUP_ROOT_NAMELEN); + strlcpy(root->name, opts->name, MAX_CGROUP_ROOT_NAMELEN); if (opts->cpuset_clone_children) set_bit(CGRP_CPUSET_CLONE_CHILDREN, &root->cgrp.flags); } -- GitLab From 2d17d8d79e77ff3f1b35b87522fc72fa562260ff Mon Sep 17 00:00:00 2001 From: Song Liu Date: Thu, 14 Dec 2017 17:17:56 -0800 Subject: [PATCH 1567/2547] xdp: linearize skb in netif_receive_generic_xdp() In netif_receive_generic_xdp(), it is necessary to linearize all nonlinear skb. However, in current implementation, skb with troom <= 0 are not linearized. This patch fixes this by calling skb_linearize() for all nonlinear skb. Fixes: de8f3a83b0a0 ("bpf: add meta pointer for direct access") Signed-off-by: Song Liu Acked-by: Martin KaFai Lau Cc: Daniel Borkmann Cc: Alexei Starovoitov Signed-off-by: Daniel Borkmann --- net/core/dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/core/dev.c b/net/core/dev.c index f47e96b62308..01ee854454a8 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -3904,7 +3904,7 @@ static u32 netif_receive_generic_xdp(struct sk_buff *skb, hroom > 0 ? ALIGN(hroom, NET_SKB_PAD) : 0, troom > 0 ? troom + 128 : 0, GFP_ATOMIC)) goto do_drop; - if (troom > 0 && __skb_linearize(skb)) + if (skb_linearize(skb)) goto do_drop; } -- GitLab From 9f37e797547cca9d14fe1f0f43f5c89b261ff0b0 Mon Sep 17 00:00:00 2001 From: Martin Schwidefsky Date: Fri, 15 Dec 2017 14:16:04 +0100 Subject: [PATCH 1568/2547] s390: fix preemption race in disable_sacf_uaccess With CONFIG_PREEMPT=y there is a possible race in disable_sacf_uaccess. The new set_fs value needs to be stored the the task structure first, the control register update needs to be second. Otherwise a preemptive schedule may interrupt the code right after the control register update has been done and the next time the task is scheduled we get an incorrect value in the control register due to the old set_fs setting. Fixes: 0aaba41b58 ("s390: remove all code using the access register mode") Signed-off-by: Martin Schwidefsky --- arch/s390/lib/uaccess.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/s390/lib/uaccess.c b/arch/s390/lib/uaccess.c index cae5a1e16cbd..c4f8039a35e8 100644 --- a/arch/s390/lib/uaccess.c +++ b/arch/s390/lib/uaccess.c @@ -89,11 +89,11 @@ EXPORT_SYMBOL(enable_sacf_uaccess); void disable_sacf_uaccess(mm_segment_t old_fs) { + current->thread.mm_segment = old_fs; if (old_fs == USER_DS && test_facility(27)) { __ctl_load(S390_lowcore.user_asce, 1, 1); clear_cpu_flag(CIF_ASCE_PRIMARY); } - current->thread.mm_segment = old_fs; } EXPORT_SYMBOL(disable_sacf_uaccess); -- GitLab From b224f6134d72e3493a023b5bea917f9a6beea0c8 Mon Sep 17 00:00:00 2001 From: David Disseldorp Date: Fri, 24 Nov 2017 16:30:53 +0100 Subject: [PATCH 1569/2547] nvme: set discard_alignment to zero Similar to 7c084289795b ("rbd: set discard_alignment to zero"), NVMe devices are currently incorrectly initialised with the block queue discard_alignment set to the NVMe stream alignment. As per Documentation/ABI/testing/sysfs-block: The discard_alignment parameter indicates how many bytes the beginning of the device is offset from the internal allocation unit's natural alignment. Correcting the discard_alignment parameter to zero has no effect on how discard requests are propagated through the block layer - @alignment in __blkdev_issue_discard() remains zero. However, it does fix other consumers, such as LIO's Block Limits VPD response. Signed-off-by: David Disseldorp Reviewed-by: Jens Axboe Reviewed-by: Martin K. Petersen Signed-off-by: Christoph Hellwig --- drivers/nvme/host/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index f837d666cbd4..67f2f94cf86e 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -1287,7 +1287,7 @@ static void nvme_config_discard(struct nvme_ctrl *ctrl, BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) < NVME_DSM_MAX_RANGES); - queue->limits.discard_alignment = size; + queue->limits.discard_alignment = 0; queue->limits.discard_granularity = size; blk_queue_max_discard_sectors(queue, UINT_MAX); -- GitLab From 4596e752db02d47038cd7c965419789ab15d1985 Mon Sep 17 00:00:00 2001 From: James Smart Date: Wed, 29 Nov 2017 15:11:37 -0800 Subject: [PATCH 1570/2547] nvme-fc: remove double put reference if admin connect fails There are two put references in the failure case of initial create_association. The first put actually frees the controller, thus the second put references freed memory. Remove the unnecessary 2nd put. Signed-off-by: James Smart Signed-off-by: Christoph Hellwig --- drivers/nvme/host/fc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/nvme/host/fc.c b/drivers/nvme/host/fc.c index 0a8af4daef89..794e66e4aa20 100644 --- a/drivers/nvme/host/fc.c +++ b/drivers/nvme/host/fc.c @@ -3221,7 +3221,6 @@ nvme_fc_init_ctrl(struct device *dev, struct nvmf_ctrl_options *opts, /* initiate nvme ctrl ref counting teardown */ nvme_uninit_ctrl(&ctrl->ctrl); - nvme_put_ctrl(&ctrl->ctrl); /* Remove core ctrl ref. */ nvme_put_ctrl(&ctrl->ctrl); -- GitLab From bd9f5d65769b9fe5e72110d4cbc9097b53b01613 Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Wed, 6 Dec 2017 18:30:09 +0800 Subject: [PATCH 1571/2547] nvme: call blk_integrity_unregister after queue is cleaned up During IO complete path, bio_integrity_advance() is often called, and blk_get_integrity() is called in this function. But in blk_integrity_unregister, the buffer pointed by queue->integrity is cleared, and blk_integrity->profile becomes NULL, then blk_get_integrity returns NULL, and causes kernel oops[1] finally. This patch fixes this issue by calling blk_integrity_unregister() after blk_cleanup_queue(). [1] kernel oops log [ 122.068007] BUG: unable to handle kernel NULL pointer dereference at 000000000000000a [ 122.076760] IP: bio_integrity_advance+0x3d/0xf0 [ 122.081815] PGD 0 P4D 0 [ 122.084641] Oops: 0000 [#1] SMP [ 122.088142] Modules linked in: sunrpc ipmi_ssif intel_rapl vfat fat x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel kvm irqbypass mei_me ipmi_si crct10dif_pclmul crc32_pclmul sg mei ghash_clmulni_intel mxm_wmi ipmi_devintf iTCO_wdt intel_cstate intel_uncore pcspkr intel_rapl_perf iTCO_vendor_support dcdbas ipmi_msghandler lpc_ich acpi_power_meter shpchp wmi dm_multipath ip_tables xfs libcrc32c sd_mod mgag200 i2c_algo_bit drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops ttm drm crc32c_intel ahci nvme tg3 libahci nvme_core i2c_core libata ptp megaraid_sas pps_core dm_mirror dm_region_hash dm_log dm_mod [ 122.149577] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.14.0-11.el7a.x86_64 #1 [ 122.157635] Hardware name: Dell Inc. PowerEdge R730xd/072T6D, BIOS 2.5.5 08/16/2017 [ 122.166179] task: ffff8802ff1e8000 task.stack: ffffc90000130000 [ 122.172785] RIP: 0010:bio_integrity_advance+0x3d/0xf0 [ 122.178419] RSP: 0018:ffff88047fc03d70 EFLAGS: 00010006 [ 122.184248] RAX: ffff880473b08000 RBX: ffff880458c71a80 RCX: ffff880473b08248 [ 122.192209] RDX: 0000000000000000 RSI: 000000000000003c RDI: ffffc900038d7ba0 [ 122.200171] RBP: ffff88047fc03d78 R08: 0000000000000001 R09: ffffffffa01a78b5 [ 122.208132] R10: ffff88047fc1eda0 R11: ffff880458c71ad0 R12: 0000000000007800 [ 122.216094] R13: 0000000000000000 R14: 0000000000007800 R15: ffff880473a39b40 [ 122.224056] FS: 0000000000000000(0000) GS:ffff88047fc00000(0000) knlGS:0000000000000000 [ 122.233083] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 122.239494] CR2: 000000000000000a CR3: 0000000001c09002 CR4: 00000000001606e0 [ 122.247455] Call Trace: [ 122.250183] [ 122.252429] bio_advance+0x28/0xf0 [ 122.256217] blk_update_request+0xa1/0x310 [ 122.260778] blk_mq_end_request+0x1e/0x70 [ 122.265256] nvme_complete_rq+0x1c/0xd0 [nvme_core] [ 122.270699] nvme_pci_complete_rq+0x85/0x130 [nvme] [ 122.276140] __blk_mq_complete_request+0x8d/0x140 [ 122.281387] blk_mq_complete_request+0x16/0x20 [ 122.286345] nvme_process_cq+0xdd/0x1c0 [nvme] [ 122.291301] nvme_irq+0x23/0x50 [nvme] [ 122.295485] __handle_irq_event_percpu+0x3c/0x190 [ 122.300725] handle_irq_event_percpu+0x32/0x80 [ 122.305683] handle_irq_event+0x3b/0x60 [ 122.309964] handle_edge_irq+0x8f/0x190 [ 122.314247] handle_irq+0xab/0x120 [ 122.318043] do_IRQ+0x48/0xd0 [ 122.321355] common_interrupt+0x9d/0x9d [ 122.325625] [ 122.327967] RIP: 0010:cpuidle_enter_state+0xe9/0x280 [ 122.333504] RSP: 0018:ffffc90000133e68 EFLAGS: 00000246 ORIG_RAX: ffffffffffffff35 [ 122.341952] RAX: ffff88047fc1b900 RBX: ffff88047fc24400 RCX: 000000000000001f [ 122.349913] RDX: 0000000000000000 RSI: fffffcf2e6007295 RDI: 0000000000000000 [ 122.357874] RBP: ffffc90000133ea0 R08: 000000000000062e R09: 0000000000000253 [ 122.365836] R10: 0000000000000225 R11: 0000000000000018 R12: 0000000000000002 [ 122.373797] R13: 0000000000000001 R14: ffff88047fc24400 R15: 0000001c6bd1d263 [ 122.381762] ? cpuidle_enter_state+0xc5/0x280 [ 122.386623] cpuidle_enter+0x17/0x20 [ 122.390611] call_cpuidle+0x23/0x40 [ 122.394501] do_idle+0x17e/0x1f0 [ 122.398101] cpu_startup_entry+0x73/0x80 [ 122.402478] start_secondary+0x178/0x1c0 [ 122.406854] secondary_startup_64+0xa5/0xa5 [ 122.411520] Code: 48 8b 5f 68 48 8b 47 08 31 d2 4c 8b 5b 48 48 8b 80 d0 03 00 00 48 83 b8 48 02 00 00 00 48 8d 88 48 02 00 00 48 0f 45 d1 c1 ee 09 <0f> b6 4a 0a 0f b6 52 09 89 f0 48 01 73 08 83 e9 09 d3 e8 0f af [ 122.432604] RIP: bio_integrity_advance+0x3d/0xf0 RSP: ffff88047fc03d70 [ 122.439888] CR2: 000000000000000a Reported-by: Zhang Yi Tested-by: Zhang Yi Signed-off-by: Ming Lei Reviewed-by: Sagi Grimberg Signed-off-by: Christoph Hellwig --- drivers/nvme/host/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index 67f2f94cf86e..2cc6192ef275 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -2965,8 +2965,6 @@ static void nvme_ns_remove(struct nvme_ns *ns) return; if (ns->disk && ns->disk->flags & GENHD_FL_UP) { - if (blk_get_integrity(ns->disk)) - blk_integrity_unregister(ns->disk); nvme_mpath_remove_disk_links(ns); sysfs_remove_group(&disk_to_dev(ns->disk)->kobj, &nvme_ns_id_attr_group); @@ -2974,6 +2972,8 @@ static void nvme_ns_remove(struct nvme_ns *ns) nvme_nvm_unregister_sysfs(ns); del_gendisk(ns->disk); blk_cleanup_queue(ns->queue); + if (blk_get_integrity(ns->disk)) + blk_integrity_unregister(ns->disk); } mutex_lock(&ns->ctrl->subsys->lock); -- GitLab From 249159c5f15812140fa216f9997d799ac0023a1f Mon Sep 17 00:00:00 2001 From: Keith Busch Date: Thu, 14 Dec 2017 11:20:14 -0700 Subject: [PATCH 1572/2547] nvme: check hw sectors before setting chunk sectors Some devices with IDs matching the "stripe" quirk don't actually have this quirk, and don't have an MDTS value. When MDTS is not set, the driver sets the max sectors to UINT_MAX, which is not a power of 2, hitting a BUG_ON from blk_queue_chunk_sectors. This patch skips setting chunk sectors for such devices. Signed-off-by: Keith Busch Reviewed-by: Martin K. Petersen Signed-off-by: Christoph Hellwig --- drivers/nvme/host/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index 2cc6192ef275..eab812dd2429 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -1705,7 +1705,8 @@ static void nvme_set_queue_limits(struct nvme_ctrl *ctrl, blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors); blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX)); } - if (ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) + if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) && + is_power_of_2(ctrl->max_hw_sectors)) blk_queue_chunk_sectors(q, ctrl->max_hw_sectors); blk_queue_virt_boundary(q, ctrl->page_size - 1); if (ctrl->vwc & NVME_CTRL_VWC_PRESENT) -- GitLab From 654b4a4acd8b52a4272114b95896e9a10d382cde Mon Sep 17 00:00:00 2001 From: Keith Busch Date: Thu, 14 Dec 2017 11:20:32 -0700 Subject: [PATCH 1573/2547] nvme: setup streams after initializing namespace head Fixes a NULL pointer dereference. Reported-by: Arnav Dawn Signed-off-by: Keith Busch Reviewed-by: Martin K. Petersen Signed-off-by: Christoph Hellwig --- drivers/nvme/host/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index eab812dd2429..1e46e60b8f10 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -2870,7 +2870,6 @@ static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid) blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); nvme_set_queue_limits(ctrl, ns->queue); - nvme_setup_streams_ns(ctrl, ns); id = nvme_identify_ns(ctrl, nsid); if (!id) @@ -2881,6 +2880,7 @@ static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid) if (nvme_init_ns_head(ns, nsid, id, &new)) goto out_free_id; + nvme_setup_streams_ns(ctrl, ns); #ifdef CONFIG_NVME_MULTIPATH /* -- GitLab From f73c52a5bcd1710994e53fbccc378c42b97a06b6 Mon Sep 17 00:00:00 2001 From: Steven Rostedt Date: Sat, 2 Dec 2017 13:04:54 -0500 Subject: [PATCH 1574/2547] sched/rt: Do not pull from current CPU if only one CPU to pull Daniel Wagner reported a crash on the BeagleBone Black SoC. This is a single CPU architecture, and does not have a functional arch_send_call_function_single_ipi() implementation which can crash the kernel if that is called. As it only has one CPU, it shouldn't be called, but if the kernel is compiled for SMP, the push/pull RT scheduling logic now calls it for irq_work if the one CPU is overloaded, it can use that function to call itself and crash the kernel. Ideally, we should disable the SCHED_FEAT(RT_PUSH_IPI) if the system only has a single CPU. But SCHED_FEAT is a constant if sched debugging is turned off. Another fix can also be used, and this should also help with normal SMP machines. That is, do not initiate the pull code if there's only one RT overloaded CPU, and that CPU happens to be the current CPU that is scheduling in a lower priority task. Even on a system with many CPUs, if there's many RT tasks waiting to run on a single CPU, and that CPU schedules in another RT task of lower priority, it will initiate the PULL logic in case there's a higher priority RT task on another CPU that is waiting to run. But if there is no other CPU with waiting RT tasks, it will initiate the RT pull logic on itself (as it still has RT tasks waiting to run). This is a wasted effort. Not only does this help with SMP code where the current CPU is the only one with RT overloaded tasks, it should also solve the issue that Daniel encountered, because it will prevent the PULL logic from executing, as there's only one CPU on the system, and the check added here will cause it to exit the RT pull code. Reported-by: Daniel Wagner Signed-off-by: Steven Rostedt (VMware) Acked-by: Peter Zijlstra Cc: Linus Torvalds Cc: Sebastian Andrzej Siewior Cc: Thomas Gleixner Cc: linux-rt-users Cc: stable@vger.kernel.org Fixes: 4bdced5c9 ("sched/rt: Simplify the IPI based RT balancing logic") Link: http://lkml.kernel.org/r/20171202130454.4cbbfe8d@vmware.local.home Signed-off-by: Ingo Molnar --- kernel/sched/rt.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/kernel/sched/rt.c b/kernel/sched/rt.c index 4056c19ca3f0..665ace2fc558 100644 --- a/kernel/sched/rt.c +++ b/kernel/sched/rt.c @@ -2034,8 +2034,9 @@ static void pull_rt_task(struct rq *this_rq) bool resched = false; struct task_struct *p; struct rq *src_rq; + int rt_overload_count = rt_overloaded(this_rq); - if (likely(!rt_overloaded(this_rq))) + if (likely(!rt_overload_count)) return; /* @@ -2044,6 +2045,11 @@ static void pull_rt_task(struct rq *this_rq) */ smp_rmb(); + /* If we are the only overloaded CPU do nothing */ + if (rt_overload_count == 1 && + cpumask_test_cpu(this_rq->cpu, this_rq->rd->rto_mask)) + return; + #ifdef HAVE_RT_PUSH_IPI if (sched_feat(RT_PUSH_IPI)) { tell_cpu_to_push(this_rq); -- GitLab From fccff0862838908d21eaf956d57e09c6c189f7c5 Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Fri, 15 Dec 2017 08:44:21 +0100 Subject: [PATCH 1575/2547] mlxsw: spectrum: Disable MAC learning for ovs port Learning is currently enabled for ports which are OVS slaves - even though OVS doesn't need this indication. Since we're not associating a fid with the port, HW would continuously notify driver of learned [& aged] MACs which would be logged as errors. Fixes: 2b94e58df58c ("mlxsw: spectrum: Allow ports to work under OVS master") Signed-off-by: Yuval Mintz Reviewed-by: Ido Schimmel Signed-off-by: Jiri Pirko Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlxsw/spectrum.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c index 2d0897b7d860..9bd8d28de152 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c @@ -4300,6 +4300,7 @@ static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) { + u16 vid = 1; int err; err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); @@ -4312,8 +4313,19 @@ static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) true, false); if (err) goto err_port_vlan_set; + + for (; vid <= VLAN_N_VID - 1; vid++) { + err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, + vid, false); + if (err) + goto err_vid_learning_set; + } + return 0; +err_vid_learning_set: + for (vid--; vid >= 1; vid--) + mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); err_port_vlan_set: mlxsw_sp_port_stp_set(mlxsw_sp_port, false); err_port_stp_set: @@ -4323,6 +4335,12 @@ static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) { + u16 vid; + + for (vid = VLAN_N_VID - 1; vid >= 1; vid--) + mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, + vid, true); + mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, false, false); mlxsw_sp_port_stp_set(mlxsw_sp_port, false); -- GitLab From c739f930be1dd5fd949030e3475a884fe06dae9b Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Tue, 12 Dec 2017 07:56:36 -0800 Subject: [PATCH 1576/2547] x86/espfix/64: Fix espfix double-fault handling on 5-level systems Using PGDIR_SHIFT to identify espfix64 addresses on 5-level systems was wrong, and it resulted in panics due to unhandled double faults. Use P4D_SHIFT instead, which is correct on 4-level and 5-level machines. This fixes a panic when running x86 selftests on 5-level machines. Signed-off-by: Andy Lutomirski Acked-by: Kirill A. Shutemov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: David Laight Cc: Kees Cook Cc: Kirill A. Shutemov Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: stable@vger.kernel.org Fixes: 1d33b219563f ("x86/espfix: Add support for 5-level paging") Link: http://lkml.kernel.org/r/24c898b4f44fdf8c22d93703850fb384ef87cfdc.1513035461.git.luto@kernel.org Signed-off-by: Ingo Molnar --- arch/x86/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index b7b0f74a2150..c751518936ac 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -355,7 +355,7 @@ dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) * * No need for ist_enter here because we don't use RCU. */ - if (((long)regs->sp >> PGDIR_SHIFT) == ESPFIX_PGD_ENTRY && + if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY && regs->cs == __KERNEL_CS && regs->ip == (unsigned long)native_irq_return_iret) { -- GitLab From a4544831370618cb3627e27ffcc27d1cc857868f Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 15 Dec 2017 16:07:22 +0000 Subject: [PATCH 1577/2547] arm64: fpsimd: Fix copying of FP state from signal frame into task struct Commit 9de52a755cfb6da5 ("arm64: fpsimd: Fix failure to restore FPSIMD state after signals") fixed an issue reported in our FPSIMD signal restore code but inadvertently introduced another issue which tends to manifest as random SEGVs in userspace. The problem is that when we copy the struct fpsimd_state from the kernel stack (populated from the signal frame) into the struct held in the current thread_struct, we blindly copy uninitialised stack into the "cpu" field, which means that context-switching of the FP registers is no longer reliable. This patch fixes the problem by copying only the user_fpsimd member of struct fpsimd_state. We should really rework the function prototypes to take struct user_fpsimd_state * instead, but let's just get this fixed for now. Cc: Dave Martin Fixes: 9de52a755cfb6da5 ("arm64: fpsimd: Fix failure to restore FPSIMD state after signals") Reported-by: Geert Uytterhoeven Signed-off-by: Will Deacon --- arch/arm64/kernel/fpsimd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 540a1e010eb5..fae81f7964b4 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -1043,7 +1043,7 @@ void fpsimd_update_current_state(struct fpsimd_state *state) local_bh_disable(); - current->thread.fpsimd_state = *state; + current->thread.fpsimd_state.user_fpsimd = state->user_fpsimd; if (system_supports_sve() && test_thread_flag(TIF_SVE)) fpsimd_to_sve(current); -- GitLab From 7fbd9493f0eeae8cef58300505a9ef5c8fce6313 Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Wed, 13 Dec 2017 18:56:29 +0100 Subject: [PATCH 1578/2547] s390/qeth: apply takeover changes when mode is toggled Just as for an explicit enable/disable, toggling the takeover mode also requires that the IP addresses get updated. Otherwise all IPs that were added to the table before the mode-toggle, get registered with the old settings. Signed-off-by: Julian Wiedmann Signed-off-by: David S. Miller --- drivers/s390/net/qeth_core.h | 2 +- drivers/s390/net/qeth_core_main.c | 2 +- drivers/s390/net/qeth_l3_sys.c | 35 +++++++++++++++---------------- 3 files changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/s390/net/qeth_core.h b/drivers/s390/net/qeth_core.h index 15015a24f8ad..51c618d9fefe 100644 --- a/drivers/s390/net/qeth_core.h +++ b/drivers/s390/net/qeth_core.h @@ -565,7 +565,7 @@ enum qeth_cq { }; struct qeth_ipato { - int enabled; + bool enabled; int invert4; int invert6; struct list_head entries; diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c index 430e3214f7e2..8d18675e60e2 100644 --- a/drivers/s390/net/qeth_core_main.c +++ b/drivers/s390/net/qeth_core_main.c @@ -1480,7 +1480,7 @@ static int qeth_setup_card(struct qeth_card *card) qeth_set_intial_options(card); /* IP address takeover */ INIT_LIST_HEAD(&card->ipato.entries); - card->ipato.enabled = 0; + card->ipato.enabled = false; card->ipato.invert4 = 0; card->ipato.invert6 = 0; /* init QDIO stuff */ diff --git a/drivers/s390/net/qeth_l3_sys.c b/drivers/s390/net/qeth_l3_sys.c index bd12fdf678be..198717f71b3d 100644 --- a/drivers/s390/net/qeth_l3_sys.c +++ b/drivers/s390/net/qeth_l3_sys.c @@ -372,6 +372,7 @@ static ssize_t qeth_l3_dev_ipato_enable_store(struct device *dev, struct qeth_card *card = dev_get_drvdata(dev); struct qeth_ipaddr *addr; int i, rc = 0; + bool enable; if (!card) return -EINVAL; @@ -384,25 +385,23 @@ static ssize_t qeth_l3_dev_ipato_enable_store(struct device *dev, } if (sysfs_streq(buf, "toggle")) { - card->ipato.enabled = (card->ipato.enabled)? 0 : 1; - } else if (sysfs_streq(buf, "1")) { - card->ipato.enabled = 1; - hash_for_each(card->ip_htable, i, addr, hnode) { - if ((addr->type == QETH_IP_TYPE_NORMAL) && - qeth_l3_is_addr_covered_by_ipato(card, addr)) - addr->set_flags |= - QETH_IPA_SETIP_TAKEOVER_FLAG; - } - } else if (sysfs_streq(buf, "0")) { - card->ipato.enabled = 0; - hash_for_each(card->ip_htable, i, addr, hnode) { - if (addr->set_flags & - QETH_IPA_SETIP_TAKEOVER_FLAG) - addr->set_flags &= - ~QETH_IPA_SETIP_TAKEOVER_FLAG; - } - } else + enable = !card->ipato.enabled; + } else if (kstrtobool(buf, &enable)) { rc = -EINVAL; + goto out; + } + + if (card->ipato.enabled == enable) + goto out; + card->ipato.enabled = enable; + + hash_for_each(card->ip_htable, i, addr, hnode) { + if (!enable) + addr->set_flags &= ~QETH_IPA_SETIP_TAKEOVER_FLAG; + else if (addr->type == QETH_IP_TYPE_NORMAL && + qeth_l3_is_addr_covered_by_ipato(card, addr)) + addr->set_flags |= QETH_IPA_SETIP_TAKEOVER_FLAG; + } out: mutex_unlock(&card->conf_mutex); return rc ? rc : count; -- GitLab From b22d73d6689fd902a66c08ebe71ab2f3b351e22f Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Wed, 13 Dec 2017 18:56:30 +0100 Subject: [PATCH 1579/2547] s390/qeth: don't apply takeover changes to RXIP When takeover is switched off, current code clears the 'TAKEOVER' flag on all IPs. But the flag is also used for RXIP addresses, and those should not be affected by the takeover mode. Fix the behaviour by consistenly applying takover logic to NORMAL addresses only. Signed-off-by: Julian Wiedmann Signed-off-by: David S. Miller --- drivers/s390/net/qeth_l3_main.c | 5 +++-- drivers/s390/net/qeth_l3_sys.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/s390/net/qeth_l3_main.c b/drivers/s390/net/qeth_l3_main.c index 6a73894b0cb5..4a4be81800eb 100644 --- a/drivers/s390/net/qeth_l3_main.c +++ b/drivers/s390/net/qeth_l3_main.c @@ -174,6 +174,8 @@ int qeth_l3_is_addr_covered_by_ipato(struct qeth_card *card, if (!card->ipato.enabled) return 0; + if (addr->type != QETH_IP_TYPE_NORMAL) + return 0; qeth_l3_convert_addr_to_bits((u8 *) &addr->u, addr_bits, (addr->proto == QETH_PROT_IPV4)? 4:16); @@ -290,8 +292,7 @@ int qeth_l3_add_ip(struct qeth_card *card, struct qeth_ipaddr *tmp_addr) memcpy(addr, tmp_addr, sizeof(struct qeth_ipaddr)); addr->ref_counter = 1; - if (addr->type == QETH_IP_TYPE_NORMAL && - qeth_l3_is_addr_covered_by_ipato(card, addr)) { + if (qeth_l3_is_addr_covered_by_ipato(card, addr)) { QETH_CARD_TEXT(card, 2, "tkovaddr"); addr->set_flags |= QETH_IPA_SETIP_TAKEOVER_FLAG; } diff --git a/drivers/s390/net/qeth_l3_sys.c b/drivers/s390/net/qeth_l3_sys.c index 198717f71b3d..e256928092e5 100644 --- a/drivers/s390/net/qeth_l3_sys.c +++ b/drivers/s390/net/qeth_l3_sys.c @@ -396,10 +396,11 @@ static ssize_t qeth_l3_dev_ipato_enable_store(struct device *dev, card->ipato.enabled = enable; hash_for_each(card->ip_htable, i, addr, hnode) { + if (addr->type != QETH_IP_TYPE_NORMAL) + continue; if (!enable) addr->set_flags &= ~QETH_IPA_SETIP_TAKEOVER_FLAG; - else if (addr->type == QETH_IP_TYPE_NORMAL && - qeth_l3_is_addr_covered_by_ipato(card, addr)) + else if (qeth_l3_is_addr_covered_by_ipato(card, addr)) addr->set_flags |= QETH_IPA_SETIP_TAKEOVER_FLAG; } out: -- GitLab From 8a03a3692b100d84785ee7a834e9215e304c9e00 Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Wed, 13 Dec 2017 18:56:31 +0100 Subject: [PATCH 1580/2547] s390/qeth: lock IP table while applying takeover changes Modifying the flags of an IP addr object needs to be protected against eg. concurrent removal of the same object from the IP table. Fixes: 5f78e29ceebf ("qeth: optimize IP handling in rx_mode callback") Signed-off-by: Julian Wiedmann Signed-off-by: David S. Miller --- drivers/s390/net/qeth_l3_sys.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/s390/net/qeth_l3_sys.c b/drivers/s390/net/qeth_l3_sys.c index e256928092e5..aa676b4090da 100644 --- a/drivers/s390/net/qeth_l3_sys.c +++ b/drivers/s390/net/qeth_l3_sys.c @@ -395,6 +395,7 @@ static ssize_t qeth_l3_dev_ipato_enable_store(struct device *dev, goto out; card->ipato.enabled = enable; + spin_lock_bh(&card->ip_lock); hash_for_each(card->ip_htable, i, addr, hnode) { if (addr->type != QETH_IP_TYPE_NORMAL) continue; @@ -403,6 +404,7 @@ static ssize_t qeth_l3_dev_ipato_enable_store(struct device *dev, else if (qeth_l3_is_addr_covered_by_ipato(card, addr)) addr->set_flags |= QETH_IPA_SETIP_TAKEOVER_FLAG; } + spin_unlock_bh(&card->ip_lock); out: mutex_unlock(&card->conf_mutex); return rc ? rc : count; -- GitLab From 02f510f326501470348a5df341e8232c3497bbbb Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Wed, 13 Dec 2017 18:56:32 +0100 Subject: [PATCH 1581/2547] s390/qeth: update takeover IPs after configuration change Any modification to the takeover IP-ranges requires that we re-evaluate which IP addresses are takeover-eligible. Otherwise we might do takeover for some addresses when we no longer should, or vice-versa. Signed-off-by: Julian Wiedmann Signed-off-by: David S. Miller --- drivers/s390/net/qeth_core.h | 4 +- drivers/s390/net/qeth_core_main.c | 4 +- drivers/s390/net/qeth_l3.h | 2 +- drivers/s390/net/qeth_l3_main.c | 31 +++++++++++++-- drivers/s390/net/qeth_l3_sys.c | 63 +++++++++++++++++-------------- 5 files changed, 67 insertions(+), 37 deletions(-) diff --git a/drivers/s390/net/qeth_core.h b/drivers/s390/net/qeth_core.h index 51c618d9fefe..badf42acbf95 100644 --- a/drivers/s390/net/qeth_core.h +++ b/drivers/s390/net/qeth_core.h @@ -566,8 +566,8 @@ enum qeth_cq { struct qeth_ipato { bool enabled; - int invert4; - int invert6; + bool invert4; + bool invert6; struct list_head entries; }; diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c index 8d18675e60e2..6c815207f4f5 100644 --- a/drivers/s390/net/qeth_core_main.c +++ b/drivers/s390/net/qeth_core_main.c @@ -1481,8 +1481,8 @@ static int qeth_setup_card(struct qeth_card *card) /* IP address takeover */ INIT_LIST_HEAD(&card->ipato.entries); card->ipato.enabled = false; - card->ipato.invert4 = 0; - card->ipato.invert6 = 0; + card->ipato.invert4 = false; + card->ipato.invert6 = false; /* init QDIO stuff */ qeth_init_qdio_info(card); INIT_DELAYED_WORK(&card->buffer_reclaim_work, qeth_buffer_reclaim_work); diff --git a/drivers/s390/net/qeth_l3.h b/drivers/s390/net/qeth_l3.h index 194ae9b577cc..e5833837b799 100644 --- a/drivers/s390/net/qeth_l3.h +++ b/drivers/s390/net/qeth_l3.h @@ -82,7 +82,7 @@ void qeth_l3_del_vipa(struct qeth_card *, enum qeth_prot_versions, const u8 *); int qeth_l3_add_rxip(struct qeth_card *, enum qeth_prot_versions, const u8 *); void qeth_l3_del_rxip(struct qeth_card *card, enum qeth_prot_versions, const u8 *); -int qeth_l3_is_addr_covered_by_ipato(struct qeth_card *, struct qeth_ipaddr *); +void qeth_l3_update_ipato(struct qeth_card *card); struct qeth_ipaddr *qeth_l3_get_addr_buffer(enum qeth_prot_versions); int qeth_l3_add_ip(struct qeth_card *, struct qeth_ipaddr *); int qeth_l3_delete_ip(struct qeth_card *, struct qeth_ipaddr *); diff --git a/drivers/s390/net/qeth_l3_main.c b/drivers/s390/net/qeth_l3_main.c index 4a4be81800eb..ef0961e18686 100644 --- a/drivers/s390/net/qeth_l3_main.c +++ b/drivers/s390/net/qeth_l3_main.c @@ -164,8 +164,8 @@ static void qeth_l3_convert_addr_to_bits(u8 *addr, u8 *bits, int len) } } -int qeth_l3_is_addr_covered_by_ipato(struct qeth_card *card, - struct qeth_ipaddr *addr) +static bool qeth_l3_is_addr_covered_by_ipato(struct qeth_card *card, + struct qeth_ipaddr *addr) { struct qeth_ipato_entry *ipatoe; u8 addr_bits[128] = {0, }; @@ -606,6 +606,27 @@ int qeth_l3_setrouting_v6(struct qeth_card *card) /* * IP address takeover related functions */ + +/** + * qeth_l3_update_ipato() - Update 'takeover' property, for all NORMAL IPs. + * + * Caller must hold ip_lock. + */ +void qeth_l3_update_ipato(struct qeth_card *card) +{ + struct qeth_ipaddr *addr; + unsigned int i; + + hash_for_each(card->ip_htable, i, addr, hnode) { + if (addr->type != QETH_IP_TYPE_NORMAL) + continue; + if (qeth_l3_is_addr_covered_by_ipato(card, addr)) + addr->set_flags |= QETH_IPA_SETIP_TAKEOVER_FLAG; + else + addr->set_flags &= ~QETH_IPA_SETIP_TAKEOVER_FLAG; + } +} + static void qeth_l3_clear_ipato_list(struct qeth_card *card) { struct qeth_ipato_entry *ipatoe, *tmp; @@ -617,6 +638,7 @@ static void qeth_l3_clear_ipato_list(struct qeth_card *card) kfree(ipatoe); } + qeth_l3_update_ipato(card); spin_unlock_bh(&card->ip_lock); } @@ -641,8 +663,10 @@ int qeth_l3_add_ipato_entry(struct qeth_card *card, } } - if (!rc) + if (!rc) { list_add_tail(&new->entry, &card->ipato.entries); + qeth_l3_update_ipato(card); + } spin_unlock_bh(&card->ip_lock); @@ -665,6 +689,7 @@ void qeth_l3_del_ipato_entry(struct qeth_card *card, (proto == QETH_PROT_IPV4)? 4:16) && (ipatoe->mask_bits == mask_bits)) { list_del(&ipatoe->entry); + qeth_l3_update_ipato(card); kfree(ipatoe); } } diff --git a/drivers/s390/net/qeth_l3_sys.c b/drivers/s390/net/qeth_l3_sys.c index aa676b4090da..6ea2b528a64e 100644 --- a/drivers/s390/net/qeth_l3_sys.c +++ b/drivers/s390/net/qeth_l3_sys.c @@ -370,9 +370,8 @@ static ssize_t qeth_l3_dev_ipato_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct qeth_card *card = dev_get_drvdata(dev); - struct qeth_ipaddr *addr; - int i, rc = 0; bool enable; + int rc = 0; if (!card) return -EINVAL; @@ -391,20 +390,12 @@ static ssize_t qeth_l3_dev_ipato_enable_store(struct device *dev, goto out; } - if (card->ipato.enabled == enable) - goto out; - card->ipato.enabled = enable; - - spin_lock_bh(&card->ip_lock); - hash_for_each(card->ip_htable, i, addr, hnode) { - if (addr->type != QETH_IP_TYPE_NORMAL) - continue; - if (!enable) - addr->set_flags &= ~QETH_IPA_SETIP_TAKEOVER_FLAG; - else if (qeth_l3_is_addr_covered_by_ipato(card, addr)) - addr->set_flags |= QETH_IPA_SETIP_TAKEOVER_FLAG; + if (card->ipato.enabled != enable) { + card->ipato.enabled = enable; + spin_lock_bh(&card->ip_lock); + qeth_l3_update_ipato(card); + spin_unlock_bh(&card->ip_lock); } - spin_unlock_bh(&card->ip_lock); out: mutex_unlock(&card->conf_mutex); return rc ? rc : count; @@ -430,20 +421,27 @@ static ssize_t qeth_l3_dev_ipato_invert4_store(struct device *dev, const char *buf, size_t count) { struct qeth_card *card = dev_get_drvdata(dev); + bool invert; int rc = 0; if (!card) return -EINVAL; mutex_lock(&card->conf_mutex); - if (sysfs_streq(buf, "toggle")) - card->ipato.invert4 = (card->ipato.invert4)? 0 : 1; - else if (sysfs_streq(buf, "1")) - card->ipato.invert4 = 1; - else if (sysfs_streq(buf, "0")) - card->ipato.invert4 = 0; - else + if (sysfs_streq(buf, "toggle")) { + invert = !card->ipato.invert4; + } else if (kstrtobool(buf, &invert)) { rc = -EINVAL; + goto out; + } + + if (card->ipato.invert4 != invert) { + card->ipato.invert4 = invert; + spin_lock_bh(&card->ip_lock); + qeth_l3_update_ipato(card); + spin_unlock_bh(&card->ip_lock); + } +out: mutex_unlock(&card->conf_mutex); return rc ? rc : count; } @@ -609,20 +607,27 @@ static ssize_t qeth_l3_dev_ipato_invert6_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct qeth_card *card = dev_get_drvdata(dev); + bool invert; int rc = 0; if (!card) return -EINVAL; mutex_lock(&card->conf_mutex); - if (sysfs_streq(buf, "toggle")) - card->ipato.invert6 = (card->ipato.invert6)? 0 : 1; - else if (sysfs_streq(buf, "1")) - card->ipato.invert6 = 1; - else if (sysfs_streq(buf, "0")) - card->ipato.invert6 = 0; - else + if (sysfs_streq(buf, "toggle")) { + invert = !card->ipato.invert6; + } else if (kstrtobool(buf, &invert)) { rc = -EINVAL; + goto out; + } + + if (card->ipato.invert6 != invert) { + card->ipato.invert6 = invert; + spin_lock_bh(&card->ip_lock); + qeth_l3_update_ipato(card); + spin_unlock_bh(&card->ip_lock); + } +out: mutex_unlock(&card->conf_mutex); return rc ? rc : count; } -- GitLab From 35b99dffc3f710cafceee6c8c6ac6a98eb2cb4bf Mon Sep 17 00:00:00 2001 From: Willem de Bruijn Date: Wed, 13 Dec 2017 14:41:06 -0500 Subject: [PATCH 1582/2547] sock: free skb in skb_complete_tx_timestamp on error skb_complete_tx_timestamp must ingest the skb it is passed. Call kfree_skb if the skb cannot be enqueued. Fixes: b245be1f4db1 ("net-timestamp: no-payload only sysctl") Fixes: 9ac25fc06375 ("net: fix socket refcounting in skb_complete_tx_timestamp()") Reported-by: Richard Cochran Signed-off-by: Willem de Bruijn Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller --- net/core/skbuff.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/net/core/skbuff.c b/net/core/skbuff.c index 6b0ff396fa9d..a592ca025fc4 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -4293,7 +4293,7 @@ void skb_complete_tx_timestamp(struct sk_buff *skb, struct sock *sk = skb->sk; if (!skb_may_tx_timestamp(sk, false)) - return; + goto err; /* Take a reference to prevent skb_orphan() from freeing the socket, * but only if the socket refcount is not zero. @@ -4302,7 +4302,11 @@ void skb_complete_tx_timestamp(struct sk_buff *skb, *skb_hwtstamps(skb) = *hwtstamps; __skb_complete_tx_timestamp(skb, sk, SCM_TSTAMP_SND, false); sock_put(sk); + return; } + +err: + kfree_skb(skb); } EXPORT_SYMBOL_GPL(skb_complete_tx_timestamp); -- GitLab From 6d59b7dbf72ed20d0138e2f9b75ca3d4a9d4faca Mon Sep 17 00:00:00 2001 From: Daniel Borkmann Date: Thu, 14 Dec 2017 21:07:23 +0100 Subject: [PATCH 1583/2547] bpf, s390x: do not reload skb pointers in non-skb context The assumption of unconditionally reloading skb pointers on BPF helper calls where bpf_helper_changes_pkt_data() holds true is wrong. There can be different contexts where the BPF helper would enforce a reload such as in case of XDP. Here, we do have a struct xdp_buff instead of struct sk_buff as context, thus this will access garbage. JITs only ever need to deal with cached skb pointer reload when ld_abs/ind was seen, therefore guard the reload behind SEEN_SKB only. Tested on s390x. Fixes: 9db7f2b81880 ("s390/bpf: recache skb->data/hlen for skb_vlan_push/pop") Signed-off-by: Daniel Borkmann Acked-by: Alexei Starovoitov Cc: Michael Holzheu Signed-off-by: Alexei Starovoitov --- arch/s390/net/bpf_jit_comp.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/s390/net/bpf_jit_comp.c b/arch/s390/net/bpf_jit_comp.c index e81c16838b90..9557d8b516df 100644 --- a/arch/s390/net/bpf_jit_comp.c +++ b/arch/s390/net/bpf_jit_comp.c @@ -55,8 +55,7 @@ struct bpf_jit { #define SEEN_LITERAL 8 /* code uses literals */ #define SEEN_FUNC 16 /* calls C functions */ #define SEEN_TAIL_CALL 32 /* code uses tail calls */ -#define SEEN_SKB_CHANGE 64 /* code changes skb data */ -#define SEEN_REG_AX 128 /* code uses constant blinding */ +#define SEEN_REG_AX 64 /* code uses constant blinding */ #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB) /* @@ -448,12 +447,12 @@ static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth) EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15, 152); } - if (jit->seen & SEEN_SKB) + if (jit->seen & SEEN_SKB) { emit_load_skb_data_hlen(jit); - if (jit->seen & SEEN_SKB_CHANGE) /* stg %b1,ST_OFF_SKBP(%r0,%r15) */ EMIT6_DISP_LH(0xe3000000, 0x0024, BPF_REG_1, REG_0, REG_15, STK_OFF_SKBP); + } } /* @@ -983,8 +982,8 @@ static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i EMIT2(0x0d00, REG_14, REG_W1); /* lgr %b0,%r2: load return value into %b0 */ EMIT4(0xb9040000, BPF_REG_0, REG_2); - if (bpf_helper_changes_pkt_data((void *)func)) { - jit->seen |= SEEN_SKB_CHANGE; + if ((jit->seen & SEEN_SKB) && + bpf_helper_changes_pkt_data((void *)func)) { /* lg %b1,ST_OFF_SKBP(%r15) */ EMIT6_DISP_LH(0xe3000000, 0x0004, BPF_REG_1, REG_0, REG_15, STK_OFF_SKBP); -- GitLab From 87338c8e2cbb317b5f757e6172f94e2e3799cd20 Mon Sep 17 00:00:00 2001 From: Daniel Borkmann Date: Thu, 14 Dec 2017 21:07:24 +0100 Subject: [PATCH 1584/2547] bpf, ppc64: do not reload skb pointers in non-skb context The assumption of unconditionally reloading skb pointers on BPF helper calls where bpf_helper_changes_pkt_data() holds true is wrong. There can be different contexts where the helper would enforce a reload such as in case of XDP. Here, we do have a struct xdp_buff instead of struct sk_buff as context, thus this will access garbage. JITs only ever need to deal with cached skb pointer reload when ld_abs/ind was seen, therefore guard the reload behind SEEN_SKB. Fixes: 156d0e290e96 ("powerpc/ebpf/jit: Implement JIT compiler for extended BPF") Signed-off-by: Daniel Borkmann Reviewed-by: Naveen N. Rao Acked-by: Alexei Starovoitov Tested-by: Sandipan Das Signed-off-by: Alexei Starovoitov --- arch/powerpc/net/bpf_jit_comp64.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c index 46d74e81aff1..d183b4801bdb 100644 --- a/arch/powerpc/net/bpf_jit_comp64.c +++ b/arch/powerpc/net/bpf_jit_comp64.c @@ -763,7 +763,8 @@ static int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, func = (u8 *) __bpf_call_base + imm; /* Save skb pointer if we need to re-cache skb data */ - if (bpf_helper_changes_pkt_data(func)) + if ((ctx->seen & SEEN_SKB) && + bpf_helper_changes_pkt_data(func)) PPC_BPF_STL(3, 1, bpf_jit_stack_local(ctx)); bpf_jit_emit_func_call(image, ctx, (u64)func); @@ -772,7 +773,8 @@ static int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, PPC_MR(b2p[BPF_REG_0], 3); /* refresh skb cache */ - if (bpf_helper_changes_pkt_data(func)) { + if ((ctx->seen & SEEN_SKB) && + bpf_helper_changes_pkt_data(func)) { /* reload skb pointer to r3 */ PPC_BPF_LL(3, 1, bpf_jit_stack_local(ctx)); bpf_jit_emit_skb_loads(image, ctx); -- GitLab From 04514d13222f2c4c91adf0ecb21004cec3388795 Mon Sep 17 00:00:00 2001 From: Daniel Borkmann Date: Thu, 14 Dec 2017 21:07:25 +0100 Subject: [PATCH 1585/2547] bpf: guarantee r1 to be ctx in case of bpf_helper_changes_pkt_data Some JITs don't cache skb context on stack in prologue, so when LD_ABS/IND is used and helper calls yield bpf_helper_changes_pkt_data() as true, then they temporarily save/restore skb pointer. However, the assumption that skb always has to be in r1 is a bit of a gamble. Right now it turned out to be true for all helpers listed in bpf_helper_changes_pkt_data(), but lets enforce that from verifier side, so that we make this a guarantee and bail out if the func proto is misconfigured in future helpers. In case of BPF helper calls from cBPF, bpf_helper_changes_pkt_data() is completely unrelevant here (since cBPF is context read-only) and therefore always false. Signed-off-by: Daniel Borkmann Acked-by: Alexei Starovoitov Signed-off-by: Alexei Starovoitov --- kernel/bpf/verifier.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c index d4593571c404..e39b01317b6f 100644 --- a/kernel/bpf/verifier.c +++ b/kernel/bpf/verifier.c @@ -1674,7 +1674,13 @@ static int check_call(struct bpf_verifier_env *env, int func_id, int insn_idx) return -EINVAL; } + /* With LD_ABS/IND some JITs save/restore skb from r1. */ changes_data = bpf_helper_changes_pkt_data(fn->func); + if (changes_data && fn->arg1_type != ARG_PTR_TO_CTX) { + verbose(env, "kernel subsystem misconfigured func %s#%d: r1 != ctx\n", + func_id_name(func_id), func_id); + return -EINVAL; + } memset(&meta, 0, sizeof(meta)); meta.pkt_access = fn->pkt_access; -- GitLab From 07aee94394547721ac168cbf4e1c09c14a5fe671 Mon Sep 17 00:00:00 2001 From: Daniel Borkmann Date: Thu, 14 Dec 2017 21:07:26 +0100 Subject: [PATCH 1586/2547] bpf, sparc: fix usage of wrong reg for load_skb_regs after call When LD_ABS/IND is used in the program, and we have a BPF helper call that changes packet data (bpf_helper_changes_pkt_data() returns true), then in case of sparc JIT, we try to reload cached skb data from bpf2sparc[BPF_REG_6]. However, there is no such guarantee or assumption that skb sits in R6 at this point, all helpers changing skb data only have a guarantee that skb sits in R1. Therefore, store BPF R1 in L7 temporarily and after procedure call use L7 to reload cached skb data. skb sitting in R6 is only true at the time when LD_ABS/IND is executed. Fixes: 7a12b5031c6b ("sparc64: Add eBPF JIT.") Signed-off-by: Daniel Borkmann Acked-by: David S. Miller Acked-by: Alexei Starovoitov Signed-off-by: Alexei Starovoitov --- arch/sparc/net/bpf_jit_comp_64.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/sparc/net/bpf_jit_comp_64.c b/arch/sparc/net/bpf_jit_comp_64.c index 5765e7e711f7..ff5f9cb3039a 100644 --- a/arch/sparc/net/bpf_jit_comp_64.c +++ b/arch/sparc/net/bpf_jit_comp_64.c @@ -1245,14 +1245,16 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx) u8 *func = ((u8 *)__bpf_call_base) + imm; ctx->saw_call = true; + if (ctx->saw_ld_abs_ind && bpf_helper_changes_pkt_data(func)) + emit_reg_move(bpf2sparc[BPF_REG_1], L7, ctx); emit_call((u32 *)func, ctx); emit_nop(ctx); emit_reg_move(O0, bpf2sparc[BPF_REG_0], ctx); - if (bpf_helper_changes_pkt_data(func) && ctx->saw_ld_abs_ind) - load_skb_regs(ctx, bpf2sparc[BPF_REG_6]); + if (ctx->saw_ld_abs_ind && bpf_helper_changes_pkt_data(func)) + load_skb_regs(ctx, L7); break; } -- GitLab From 87ab8194303e73af2898e9e1c8b3b9bcfe91e7a9 Mon Sep 17 00:00:00 2001 From: Daniel Borkmann Date: Thu, 14 Dec 2017 21:07:27 +0100 Subject: [PATCH 1587/2547] bpf: add test case for ld_abs and helper changing pkt data Add a test that i) uses LD_ABS, ii) zeroing R6 before call, iii) calls a helper that triggers reload of cached skb data, iv) uses LD_ABS again. It's added for test_bpf in order to do runtime testing after JITing as well as test_verifier to test that the sequence is allowed. Signed-off-by: Daniel Borkmann Acked-by: Alexei Starovoitov Signed-off-by: Alexei Starovoitov --- lib/test_bpf.c | 43 +++++++++++++++++++++ tools/testing/selftests/bpf/test_verifier.c | 24 ++++++++++++ 2 files changed, 67 insertions(+) diff --git a/lib/test_bpf.c b/lib/test_bpf.c index aa8812ae6776..9e9748089270 100644 --- a/lib/test_bpf.c +++ b/lib/test_bpf.c @@ -435,6 +435,41 @@ static int bpf_fill_ld_abs_vlan_push_pop(struct bpf_test *self) return 0; } +static int bpf_fill_ld_abs_vlan_push_pop2(struct bpf_test *self) +{ + struct bpf_insn *insn; + + insn = kmalloc_array(16, sizeof(*insn), GFP_KERNEL); + if (!insn) + return -ENOMEM; + + /* Due to func address being non-const, we need to + * assemble this here. + */ + insn[0] = BPF_MOV64_REG(R6, R1); + insn[1] = BPF_LD_ABS(BPF_B, 0); + insn[2] = BPF_LD_ABS(BPF_H, 0); + insn[3] = BPF_LD_ABS(BPF_W, 0); + insn[4] = BPF_MOV64_REG(R7, R6); + insn[5] = BPF_MOV64_IMM(R6, 0); + insn[6] = BPF_MOV64_REG(R1, R7); + insn[7] = BPF_MOV64_IMM(R2, 1); + insn[8] = BPF_MOV64_IMM(R3, 2); + insn[9] = BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, + bpf_skb_vlan_push_proto.func - __bpf_call_base); + insn[10] = BPF_MOV64_REG(R6, R7); + insn[11] = BPF_LD_ABS(BPF_B, 0); + insn[12] = BPF_LD_ABS(BPF_H, 0); + insn[13] = BPF_LD_ABS(BPF_W, 0); + insn[14] = BPF_MOV64_IMM(R0, 42); + insn[15] = BPF_EXIT_INSN(); + + self->u.ptr.insns = insn; + self->u.ptr.len = 16; + + return 0; +} + static int bpf_fill_jump_around_ld_abs(struct bpf_test *self) { unsigned int len = BPF_MAXINSNS; @@ -6066,6 +6101,14 @@ static struct bpf_test tests[] = { {}, { {0x1, 0x42 } }, }, + { + "LD_ABS with helper changing skb data", + { }, + INTERNAL, + { 0x34 }, + { { ETH_HLEN, 42 } }, + .fill_helper = bpf_fill_ld_abs_vlan_push_pop2, + }, }; static struct net_device dev; diff --git a/tools/testing/selftests/bpf/test_verifier.c b/tools/testing/selftests/bpf/test_verifier.c index 3c64f30cf63c..b03ecfd7185b 100644 --- a/tools/testing/selftests/bpf/test_verifier.c +++ b/tools/testing/selftests/bpf/test_verifier.c @@ -6116,6 +6116,30 @@ static struct bpf_test tests[] = { }, .result = ACCEPT, }, + { + "ld_abs: tests on r6 and skb data reload helper", + .insns = { + BPF_MOV64_REG(BPF_REG_6, BPF_REG_1), + BPF_LD_ABS(BPF_B, 0), + BPF_LD_ABS(BPF_H, 0), + BPF_LD_ABS(BPF_W, 0), + BPF_MOV64_REG(BPF_REG_7, BPF_REG_6), + BPF_MOV64_IMM(BPF_REG_6, 0), + BPF_MOV64_REG(BPF_REG_1, BPF_REG_7), + BPF_MOV64_IMM(BPF_REG_2, 1), + BPF_MOV64_IMM(BPF_REG_3, 2), + BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, + BPF_FUNC_skb_vlan_push), + BPF_MOV64_REG(BPF_REG_6, BPF_REG_7), + BPF_LD_ABS(BPF_B, 0), + BPF_LD_ABS(BPF_H, 0), + BPF_LD_ABS(BPF_W, 0), + BPF_MOV64_IMM(BPF_REG_0, 42), + BPF_EXIT_INSN(), + }, + .prog_type = BPF_PROG_TYPE_SCHED_CLS, + .result = ACCEPT, + }, { "ld_ind: check calling conv, r1", .insns = { -- GitLab From e4d02ca04c6d48ab2226342a1c4ed54f1dbb72bd Mon Sep 17 00:00:00 2001 From: Igor Russkikh Date: Thu, 14 Dec 2017 12:34:40 +0300 Subject: [PATCH 1588/2547] net: aquantia: Fix actual speed capabilities reporting Different hardware device Ids correspond to different maximum speed available. Extra checks were added for devices D108 and D109 to remove unsupported speeds from these device capabilities list. Signed-off-by: Igor Russkikh Signed-off-by: David S. Miller --- drivers/net/ethernet/aquantia/atlantic/aq_hw.h | 4 +++- drivers/net/ethernet/aquantia/atlantic/aq_nic.c | 7 ++++--- drivers/net/ethernet/aquantia/atlantic/aq_nic.h | 2 +- .../net/ethernet/aquantia/atlantic/aq_pci_func.c | 5 +++-- .../ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c | 13 ++++++++++++- .../ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c | 13 ++++++++++++- 6 files changed, 35 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h index 0207927dc8a6..4ebd53b3c7da 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h @@ -85,7 +85,9 @@ struct aq_hw_ops { void (*destroy)(struct aq_hw_s *self); int (*get_hw_caps)(struct aq_hw_s *self, - struct aq_hw_caps_s *aq_hw_caps); + struct aq_hw_caps_s *aq_hw_caps, + unsigned short device, + unsigned short subsystem_device); int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, unsigned int frags); diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c index 78dfb2ab78ce..a360ccc298b9 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c @@ -222,7 +222,7 @@ static struct net_device *aq_nic_ndev_alloc(void) struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops, const struct ethtool_ops *et_ops, - struct device *dev, + struct pci_dev *pdev, struct aq_pci_func_s *aq_pci_func, unsigned int port, const struct aq_hw_ops *aq_hw_ops) @@ -242,7 +242,7 @@ struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops, ndev->netdev_ops = ndev_ops; ndev->ethtool_ops = et_ops; - SET_NETDEV_DEV(ndev, dev); + SET_NETDEV_DEV(ndev, &pdev->dev); ndev->if_port = port; self->ndev = ndev; @@ -254,7 +254,8 @@ struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops, self->aq_hw = self->aq_hw_ops.create(aq_pci_func, self->port, &self->aq_hw_ops); - err = self->aq_hw_ops.get_hw_caps(self->aq_hw, &self->aq_hw_caps); + err = self->aq_hw_ops.get_hw_caps(self->aq_hw, &self->aq_hw_caps, + pdev->device, pdev->subsystem_device); if (err < 0) goto err_exit; diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.h b/drivers/net/ethernet/aquantia/atlantic/aq_nic.h index 4309983acdd6..3c9f8db03d5f 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.h @@ -71,7 +71,7 @@ struct aq_nic_cfg_s { struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops, const struct ethtool_ops *et_ops, - struct device *dev, + struct pci_dev *pdev, struct aq_pci_func_s *aq_pci_func, unsigned int port, const struct aq_hw_ops *aq_hw_ops); diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c index cadaa646c89f..58c29d04b186 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c @@ -51,7 +51,8 @@ struct aq_pci_func_s *aq_pci_func_alloc(struct aq_hw_ops *aq_hw_ops, pci_set_drvdata(pdev, self); self->pdev = pdev; - err = aq_hw_ops->get_hw_caps(NULL, &self->aq_hw_caps); + err = aq_hw_ops->get_hw_caps(NULL, &self->aq_hw_caps, pdev->device, + pdev->subsystem_device); if (err < 0) goto err_exit; @@ -59,7 +60,7 @@ struct aq_pci_func_s *aq_pci_func_alloc(struct aq_hw_ops *aq_hw_ops, for (port = 0; port < self->ports; ++port) { struct aq_nic_s *aq_nic = aq_nic_alloc_cold(ndev_ops, eth_ops, - &pdev->dev, self, + pdev, self, port, aq_hw_ops); if (!aq_nic) { diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c index 07b3c49a16a4..b0abd187cead 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c @@ -18,9 +18,20 @@ #include "hw_atl_a0_internal.h" static int hw_atl_a0_get_hw_caps(struct aq_hw_s *self, - struct aq_hw_caps_s *aq_hw_caps) + struct aq_hw_caps_s *aq_hw_caps, + unsigned short device, + unsigned short subsystem_device) { memcpy(aq_hw_caps, &hw_atl_a0_hw_caps_, sizeof(*aq_hw_caps)); + + if (device == HW_ATL_DEVICE_ID_D108 && subsystem_device == 0x0001) + aq_hw_caps->link_speed_msk &= ~HW_ATL_A0_RATE_10G; + + if (device == HW_ATL_DEVICE_ID_D109 && subsystem_device == 0x0001) { + aq_hw_caps->link_speed_msk &= ~HW_ATL_A0_RATE_10G; + aq_hw_caps->link_speed_msk &= ~HW_ATL_A0_RATE_5G; + } + return 0; } diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index ec68c20efcbd..e4e3b8e2d67e 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -18,9 +18,20 @@ #include "hw_atl_b0_internal.h" static int hw_atl_b0_get_hw_caps(struct aq_hw_s *self, - struct aq_hw_caps_s *aq_hw_caps) + struct aq_hw_caps_s *aq_hw_caps, + unsigned short device, + unsigned short subsystem_device) { memcpy(aq_hw_caps, &hw_atl_b0_hw_caps_, sizeof(*aq_hw_caps)); + + if (device == HW_ATL_DEVICE_ID_D108 && subsystem_device == 0x0001) + aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_10G; + + if (device == HW_ATL_DEVICE_ID_D109 && subsystem_device == 0x0001) { + aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_10G; + aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_5G; + } + return 0; } -- GitLab From 1e366161510f266516107a69db91f1f2edaea11c Mon Sep 17 00:00:00 2001 From: Igor Russkikh Date: Thu, 14 Dec 2017 12:34:41 +0300 Subject: [PATCH 1589/2547] net: aquantia: Fix hardware DMA stream overload on large MRRS Systems with large MRRS on device (2K, 4K) with high data rates and/or large MTU, atlantic observes DMA packet buffer overflow. On some systems that causes PCIe transaction errors, hardware NMIs or datapath freeze. This patch 1) Limits MRRS from device side to 2K (thats maximum our hardware supports) 2) Limit maximum size of outstanding TX DMA data read requests. This makes hardware buffers running fine. Signed-off-by: Pavel Belous Signed-off-by: Igor Russkikh Signed-off-by: David S. Miller --- .../ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c | 12 ++++++++++++ .../aquantia/atlantic/hw_atl/hw_atl_llh_internal.h | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index e4e3b8e2d67e..36fddb199160 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -16,6 +16,7 @@ #include "hw_atl_utils.h" #include "hw_atl_llh.h" #include "hw_atl_b0_internal.h" +#include "hw_atl_llh_internal.h" static int hw_atl_b0_get_hw_caps(struct aq_hw_s *self, struct aq_hw_caps_s *aq_hw_caps, @@ -368,6 +369,7 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self, }; int err = 0; + u32 val; self->aq_nic_cfg = aq_nic_cfg; @@ -385,6 +387,16 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self, hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss); hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss); + /* Force limit MRRS on RDM/TDM to 2K */ + val = aq_hw_read_reg(self, pci_reg_control6_adr); + aq_hw_write_reg(self, pci_reg_control6_adr, (val & ~0x707) | 0x404); + + /* TX DMA total request limit. B0 hardware is not capable to + * handle more than (8K-MRRS) incoming DMA data. + * Value 24 in 256byte units + */ + aq_hw_write_reg(self, tx_dma_total_req_limit_adr, 24); + err = aq_hw_err_from_flags(self); if (err < 0) goto err_exit; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h index 5527fc0e5942..93450ec930e8 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h @@ -2343,6 +2343,9 @@ #define tx_dma_desc_base_addrmsw_adr(descriptor) \ (0x00007c04u + (descriptor) * 0x40) +/* tx dma total request limit */ +#define tx_dma_total_req_limit_adr 0x00007b20u + /* tx interrupt moderation control register definitions * Preprocessor definitions for TX Interrupt Moderation Control Register * Base Address: 0x00008980 @@ -2369,6 +2372,9 @@ /* default value of bitfield reg_res_dsbl */ #define pci_reg_res_dsbl_default 0x1 +/* PCI core control register */ +#define pci_reg_control6_adr 0x1014u + /* global microprocessor scratch pad definitions */ #define glb_cpu_scratch_scp_adr(scratch_scp) (0x00000300u + (scratch_scp) * 0x4) -- GitLab From be08d839d9ef1c9b0e4ed809ec852ff100f9970d Mon Sep 17 00:00:00 2001 From: Igor Russkikh Date: Thu, 14 Dec 2017 12:34:42 +0300 Subject: [PATCH 1590/2547] net: aquantia: Extend stat counters to 64bit values Device hardware provides only 32bit counters. Using these directly causes byte counters to overflow soon. A separate nic level structure with 64 bit counters is now used to collect incrementally all the stats and report these counters to ethtool stats and ndev stats. Signed-off-by: Igor Russkikh Signed-off-by: David S. Miller --- .../net/ethernet/aquantia/atlantic/aq_hw.h | 25 +++++- .../net/ethernet/aquantia/atlantic/aq_nic.c | 35 ++++++-- .../aquantia/atlantic/hw_atl/hw_atl_utils.c | 80 ++++++------------- .../aquantia/atlantic/hw_atl/hw_atl_utils.h | 6 +- 4 files changed, 79 insertions(+), 67 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h index 4ebd53b3c7da..b3825de6cdfb 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h @@ -46,6 +46,28 @@ struct aq_hw_link_status_s { unsigned int mbps; }; +struct aq_stats_s { + u64 uprc; + u64 mprc; + u64 bprc; + u64 erpt; + u64 uptc; + u64 mptc; + u64 bptc; + u64 erpr; + u64 mbtc; + u64 bbtc; + u64 mbrc; + u64 bbrc; + u64 ubrc; + u64 ubtc; + u64 dpc; + u64 dma_pkt_rc; + u64 dma_pkt_tc; + u64 dma_oct_rc; + u64 dma_oct_tc; +}; + #define AQ_HW_IRQ_INVALID 0U #define AQ_HW_IRQ_LEGACY 1U #define AQ_HW_IRQ_MSI 2U @@ -166,8 +188,7 @@ struct aq_hw_ops { int (*hw_update_stats)(struct aq_hw_s *self); - int (*hw_get_hw_stats)(struct aq_hw_s *self, u64 *data, - unsigned int *p_count); + struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self); int (*hw_get_fw_version)(struct aq_hw_s *self, u32 *fw_version); diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c index a360ccc298b9..28cbe9d43df6 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c @@ -750,16 +750,40 @@ int aq_nic_get_regs_count(struct aq_nic_s *self) void aq_nic_get_stats(struct aq_nic_s *self, u64 *data) { - struct aq_vec_s *aq_vec = NULL; unsigned int i = 0U; unsigned int count = 0U; - int err = 0; + struct aq_vec_s *aq_vec = NULL; + struct aq_stats_s *stats = self->aq_hw_ops.hw_get_hw_stats(self->aq_hw); - err = self->aq_hw_ops.hw_get_hw_stats(self->aq_hw, data, &count); - if (err < 0) + if (!stats) goto err_exit; - data += count; + data[i] = stats->uprc + stats->mprc + stats->bprc; + data[++i] = stats->uprc; + data[++i] = stats->mprc; + data[++i] = stats->bprc; + data[++i] = stats->erpt; + data[++i] = stats->uptc + stats->mptc + stats->bptc; + data[++i] = stats->uptc; + data[++i] = stats->mptc; + data[++i] = stats->bptc; + data[++i] = stats->ubrc; + data[++i] = stats->ubtc; + data[++i] = stats->mbrc; + data[++i] = stats->mbtc; + data[++i] = stats->bbrc; + data[++i] = stats->bbtc; + data[++i] = stats->ubrc + stats->mbrc + stats->bbrc; + data[++i] = stats->ubtc + stats->mbtc + stats->bbtc; + data[++i] = stats->dma_pkt_rc; + data[++i] = stats->dma_pkt_tc; + data[++i] = stats->dma_oct_rc; + data[++i] = stats->dma_oct_tc; + data[++i] = stats->dpc; + + i++; + + data += i; count = 0U; for (i = 0U, aq_vec = self->aq_vec[0]; @@ -769,7 +793,6 @@ void aq_nic_get_stats(struct aq_nic_s *self, u64 *data) } err_exit:; - (void)err; } void aq_nic_get_link_ksettings(struct aq_nic_s *self, diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c index 1fe016fc4bc7..f2ce12ed4218 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c @@ -503,73 +503,43 @@ int hw_atl_utils_update_stats(struct aq_hw_s *self) struct hw_atl_s *hw_self = PHAL_ATLANTIC; struct hw_aq_atl_utils_mbox mbox; - if (!self->aq_link_status.mbps) - return 0; - hw_atl_utils_mpi_read_stats(self, &mbox); #define AQ_SDELTA(_N_) (hw_self->curr_stats._N_ += \ mbox.stats._N_ - hw_self->last_stats._N_) - - AQ_SDELTA(uprc); - AQ_SDELTA(mprc); - AQ_SDELTA(bprc); - AQ_SDELTA(erpt); - - AQ_SDELTA(uptc); - AQ_SDELTA(mptc); - AQ_SDELTA(bptc); - AQ_SDELTA(erpr); - - AQ_SDELTA(ubrc); - AQ_SDELTA(ubtc); - AQ_SDELTA(mbrc); - AQ_SDELTA(mbtc); - AQ_SDELTA(bbrc); - AQ_SDELTA(bbtc); - AQ_SDELTA(dpc); - + if (self->aq_link_status.mbps) { + AQ_SDELTA(uprc); + AQ_SDELTA(mprc); + AQ_SDELTA(bprc); + AQ_SDELTA(erpt); + + AQ_SDELTA(uptc); + AQ_SDELTA(mptc); + AQ_SDELTA(bptc); + AQ_SDELTA(erpr); + + AQ_SDELTA(ubrc); + AQ_SDELTA(ubtc); + AQ_SDELTA(mbrc); + AQ_SDELTA(mbtc); + AQ_SDELTA(bbrc); + AQ_SDELTA(bbtc); + AQ_SDELTA(dpc); + } #undef AQ_SDELTA + hw_self->curr_stats.dma_pkt_rc = stats_rx_dma_good_pkt_counterlsw_get(self); + hw_self->curr_stats.dma_pkt_tc = stats_tx_dma_good_pkt_counterlsw_get(self); + hw_self->curr_stats.dma_oct_rc = stats_rx_dma_good_octet_counterlsw_get(self); + hw_self->curr_stats.dma_oct_tc = stats_tx_dma_good_octet_counterlsw_get(self); memcpy(&hw_self->last_stats, &mbox.stats, sizeof(mbox.stats)); return 0; } -int hw_atl_utils_get_hw_stats(struct aq_hw_s *self, - u64 *data, unsigned int *p_count) +struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self) { - struct hw_atl_s *hw_self = PHAL_ATLANTIC; - struct hw_atl_stats_s *stats = &hw_self->curr_stats; - int i = 0; - - data[i] = stats->uprc + stats->mprc + stats->bprc; - data[++i] = stats->uprc; - data[++i] = stats->mprc; - data[++i] = stats->bprc; - data[++i] = stats->erpt; - data[++i] = stats->uptc + stats->mptc + stats->bptc; - data[++i] = stats->uptc; - data[++i] = stats->mptc; - data[++i] = stats->bptc; - data[++i] = stats->ubrc; - data[++i] = stats->ubtc; - data[++i] = stats->mbrc; - data[++i] = stats->mbtc; - data[++i] = stats->bbrc; - data[++i] = stats->bbtc; - data[++i] = stats->ubrc + stats->mbrc + stats->bbrc; - data[++i] = stats->ubtc + stats->mbtc + stats->bbtc; - data[++i] = stats_rx_dma_good_pkt_counterlsw_get(self); - data[++i] = stats_tx_dma_good_pkt_counterlsw_get(self); - data[++i] = stats_rx_dma_good_octet_counterlsw_get(self); - data[++i] = stats_tx_dma_good_octet_counterlsw_get(self); - data[++i] = stats->dpc; - - if (p_count) - *p_count = ++i; - - return 0; + return &PHAL_ATLANTIC->curr_stats; } static const u32 hw_atl_utils_hw_mac_regs[] = { diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h index c99cc690e425..21aeca6908d3 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h @@ -129,7 +129,7 @@ struct __packed hw_aq_atl_utils_mbox { struct __packed hw_atl_s { struct aq_hw_s base; struct hw_atl_stats_s last_stats; - struct hw_atl_stats_s curr_stats; + struct aq_stats_s curr_stats; u64 speed; unsigned int chip_features; u32 fw_ver_actual; @@ -207,8 +207,6 @@ int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version); int hw_atl_utils_update_stats(struct aq_hw_s *self); -int hw_atl_utils_get_hw_stats(struct aq_hw_s *self, - u64 *data, - unsigned int *p_count); +struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self); #endif /* HW_ATL_UTILS_H */ -- GitLab From 9f8a2203a542f5f3cdeb17f40250c49bb87aa7e3 Mon Sep 17 00:00:00 2001 From: Igor Russkikh Date: Thu, 14 Dec 2017 12:34:43 +0300 Subject: [PATCH 1591/2547] net: aquantia: Fill ndev stat couters from hardware Originally they were filled from ring sw counters. These sometimes incorrectly calculate byte and packet amounts when using LRO/LSO and jumboframes. Filling ndev counters from hardware makes them precise. Signed-off-by: Igor Russkikh Signed-off-by: David S. Miller --- .../net/ethernet/aquantia/atlantic/aq_nic.c | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c index 28cbe9d43df6..307caac68731 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c @@ -37,6 +37,8 @@ static unsigned int aq_itr_rx; module_param_named(aq_itr_rx, aq_itr_rx, uint, 0644); MODULE_PARM_DESC(aq_itr_rx, "RX interrupt throttle rate"); +static void aq_nic_update_ndev_stats(struct aq_nic_s *self); + static void aq_nic_rss_init(struct aq_nic_s *self, unsigned int num_rss_queues) { struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; @@ -166,11 +168,7 @@ static int aq_nic_update_link_status(struct aq_nic_s *self) static void aq_nic_service_timer_cb(struct timer_list *t) { struct aq_nic_s *self = from_timer(self, t, service_timer); - struct net_device *ndev = aq_nic_get_ndev(self); int err = 0; - unsigned int i = 0U; - struct aq_ring_stats_rx_s stats_rx; - struct aq_ring_stats_tx_s stats_tx; if (aq_utils_obj_test(&self->header.flags, AQ_NIC_FLAGS_IS_NOT_READY)) goto err_exit; @@ -182,19 +180,8 @@ static void aq_nic_service_timer_cb(struct timer_list *t) if (self->aq_hw_ops.hw_update_stats) self->aq_hw_ops.hw_update_stats(self->aq_hw); - memset(&stats_rx, 0U, sizeof(struct aq_ring_stats_rx_s)); - memset(&stats_tx, 0U, sizeof(struct aq_ring_stats_tx_s)); - for (i = AQ_DIMOF(self->aq_vec); i--;) { - if (self->aq_vec[i]) - aq_vec_add_stats(self->aq_vec[i], &stats_rx, &stats_tx); - } + aq_nic_update_ndev_stats(self); - ndev->stats.rx_packets = stats_rx.packets; - ndev->stats.rx_bytes = stats_rx.bytes; - ndev->stats.rx_errors = stats_rx.errors; - ndev->stats.tx_packets = stats_tx.packets; - ndev->stats.tx_bytes = stats_tx.bytes; - ndev->stats.tx_errors = stats_tx.errors; err_exit: mod_timer(&self->service_timer, @@ -795,6 +782,19 @@ void aq_nic_get_stats(struct aq_nic_s *self, u64 *data) err_exit:; } +static void aq_nic_update_ndev_stats(struct aq_nic_s *self) +{ + struct net_device *ndev = self->ndev; + struct aq_stats_s *stats = self->aq_hw_ops.hw_get_hw_stats(self->aq_hw); + + ndev->stats.rx_packets = stats->uprc + stats->mprc + stats->bprc; + ndev->stats.rx_bytes = stats->ubrc + stats->mbrc + stats->bbrc; + ndev->stats.rx_errors = stats->erpr; + ndev->stats.tx_packets = stats->uptc + stats->mptc + stats->bptc; + ndev->stats.tx_bytes = stats->ubtc + stats->mbtc + stats->bbtc; + ndev->stats.tx_errors = stats->erpt; +} + void aq_nic_get_link_ksettings(struct aq_nic_s *self, struct ethtool_link_ksettings *cmd) { -- GitLab From 45cc1c7ad47c4d166d15c7bce449d2de4daef0c5 Mon Sep 17 00:00:00 2001 From: Igor Russkikh Date: Thu, 14 Dec 2017 12:34:44 +0300 Subject: [PATCH 1592/2547] net: aquantia: Fill in multicast counter in ndev stats from hardware This metric comes from HW and is also diff-calculated, like other counters Signed-off-by: Igor Russkikh Signed-off-by: David S. Miller --- drivers/net/ethernet/aquantia/atlantic/aq_nic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c index 307caac68731..b3a5d1fbc713 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c @@ -793,6 +793,7 @@ static void aq_nic_update_ndev_stats(struct aq_nic_s *self) ndev->stats.tx_packets = stats->uptc + stats->mptc + stats->bptc; ndev->stats.tx_bytes = stats->ubtc + stats->mbtc + stats->bbtc; ndev->stats.tx_errors = stats->erpt; + ndev->stats.multicast = stats->mprc; } void aq_nic_get_link_ksettings(struct aq_nic_s *self, -- GitLab From fdb4a0830e74acfbe84d4d4e6772ea09c96786ad Mon Sep 17 00:00:00 2001 From: Igor Russkikh Date: Thu, 14 Dec 2017 12:34:45 +0300 Subject: [PATCH 1593/2547] net: aquantia: Improve link state and statistics check interval callback Reduce timeout from 2 secs to 1 sec. If link is down, reduce it to 500msec. This speeds up link detection. Signed-off-by: Igor Russkikh Signed-off-by: David S. Miller --- drivers/net/ethernet/aquantia/atlantic/aq_cfg.h | 2 +- drivers/net/ethernet/aquantia/atlantic/aq_nic.c | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h b/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h index 57e796870595..73b93a7b4800 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h @@ -50,7 +50,7 @@ #define AQ_CFG_PCI_FUNC_MSIX_IRQS 9U #define AQ_CFG_PCI_FUNC_PORTS 2U -#define AQ_CFG_SERVICE_TIMER_INTERVAL (2 * HZ) +#define AQ_CFG_SERVICE_TIMER_INTERVAL (1 * HZ) #define AQ_CFG_POLLING_TIMER_INTERVAL ((unsigned int)(2 * HZ)) #define AQ_CFG_SKB_FRAGS_MAX 32U diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c index b3a5d1fbc713..75a894a9251c 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c @@ -168,6 +168,7 @@ static int aq_nic_update_link_status(struct aq_nic_s *self) static void aq_nic_service_timer_cb(struct timer_list *t) { struct aq_nic_s *self = from_timer(self, t, service_timer); + int ctimer = AQ_CFG_SERVICE_TIMER_INTERVAL; int err = 0; if (aq_utils_obj_test(&self->header.flags, AQ_NIC_FLAGS_IS_NOT_READY)) @@ -182,10 +183,12 @@ static void aq_nic_service_timer_cb(struct timer_list *t) aq_nic_update_ndev_stats(self); + /* If no link - use faster timer rate to detect link up asap */ + if (!netif_carrier_ok(self->ndev)) + ctimer = max(ctimer / 2, 1); err_exit: - mod_timer(&self->service_timer, - jiffies + AQ_CFG_SERVICE_TIMER_INTERVAL); + mod_timer(&self->service_timer, jiffies + ctimer); } static void aq_nic_polling_timer_cb(struct timer_list *t) -- GitLab From f3e2778429c2ad8555e888858e0f0e98c86c4b0f Mon Sep 17 00:00:00 2001 From: Igor Russkikh Date: Thu, 14 Dec 2017 12:34:46 +0300 Subject: [PATCH 1594/2547] net: aquantia: Update hw counters on hw init On very first start we should read out current HW counter values to make diff based calculations later. This also should be done each time NIC gets down/up or wakes up after sleep state. We reset link state explicitly to prevent diffs from being summed this first time. Signed-off-by: Igor Russkikh Signed-off-by: David S. Miller --- drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c | 4 ++++ drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c index b0abd187cead..f18dce14c93c 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c @@ -344,6 +344,10 @@ static int hw_atl_a0_hw_init(struct aq_hw_s *self, hw_atl_a0_hw_rss_set(self, &aq_nic_cfg->aq_rss); hw_atl_a0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss); + /* Reset link status and read out initial hardware counters */ + self->aq_link_status.mbps = 0; + hw_atl_utils_update_stats(self); + err = aq_hw_err_from_flags(self); if (err < 0) goto err_exit; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index 36fddb199160..e4a22ce7bf09 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -397,6 +397,10 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self, */ aq_hw_write_reg(self, tx_dma_total_req_limit_adr, 24); + /* Reset link status and read out initial hardware counters */ + self->aq_link_status.mbps = 0; + hw_atl_utils_update_stats(self); + err = aq_hw_err_from_flags(self); if (err < 0) goto err_exit; -- GitLab From 98bc036de40489416d61ab175bb417c094e7783c Mon Sep 17 00:00:00 2001 From: Igor Russkikh Date: Thu, 14 Dec 2017 12:34:47 +0300 Subject: [PATCH 1595/2547] net: aquantia: Fix typo in ethtool statistics names Signed-off-by: Igor Russkikh Signed-off-by: David S. Miller --- .../net/ethernet/aquantia/atlantic/aq_ethtool.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c index 70efb7467bf3..f2d8063a2cef 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c @@ -66,14 +66,14 @@ static const char aq_ethtool_stat_names[][ETH_GSTRING_LEN] = { "OutUCast", "OutMCast", "OutBCast", - "InUCastOctects", - "OutUCastOctects", - "InMCastOctects", - "OutMCastOctects", - "InBCastOctects", - "OutBCastOctects", - "InOctects", - "OutOctects", + "InUCastOctets", + "OutUCastOctets", + "InMCastOctets", + "OutMCastOctets", + "InBCastOctets", + "OutBCastOctets", + "InOctets", + "OutOctets", "InPacketsDma", "OutPacketsDma", "InOctetsDma", -- GitLab From d4c242d4ba5730b62579969804cd8fcf58b9c84f Mon Sep 17 00:00:00 2001 From: Igor Russkikh Date: Thu, 14 Dec 2017 12:34:48 +0300 Subject: [PATCH 1596/2547] net: aquantia: Increment driver version Add a suffix to distinguish kernel mainline version and aquantia releases Signed-off-by: Igor Russkikh Signed-off-by: David S. Miller --- drivers/net/ethernet/aquantia/atlantic/aq_cfg.h | 3 ++- drivers/net/ethernet/aquantia/atlantic/ver.h | 6 ++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h b/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h index 73b93a7b4800..105fdb958cef 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h @@ -80,6 +80,7 @@ #define AQ_CFG_DRV_VERSION __stringify(NIC_MAJOR_DRIVER_VERSION)"."\ __stringify(NIC_MINOR_DRIVER_VERSION)"."\ __stringify(NIC_BUILD_DRIVER_VERSION)"."\ - __stringify(NIC_REVISION_DRIVER_VERSION) + __stringify(NIC_REVISION_DRIVER_VERSION) \ + AQ_CFG_DRV_VERSION_SUFFIX #endif /* AQ_CFG_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/ver.h b/drivers/net/ethernet/aquantia/atlantic/ver.h index 0de858d215c2..9009f2651e70 100644 --- a/drivers/net/ethernet/aquantia/atlantic/ver.h +++ b/drivers/net/ethernet/aquantia/atlantic/ver.h @@ -11,8 +11,10 @@ #define VER_H #define NIC_MAJOR_DRIVER_VERSION 1 -#define NIC_MINOR_DRIVER_VERSION 5 -#define NIC_BUILD_DRIVER_VERSION 345 +#define NIC_MINOR_DRIVER_VERSION 6 +#define NIC_BUILD_DRIVER_VERSION 13 #define NIC_REVISION_DRIVER_VERSION 0 +#define AQ_CFG_DRV_VERSION_SUFFIX "-kern" + #endif /* VER_H */ -- GitLab From 7a4fa29106d9a38ef005f5ab15d493c259f269c0 Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Thu, 14 Dec 2017 15:54:29 +0200 Subject: [PATCH 1597/2547] net: sched: Add TCA_HW_OFFLOAD Qdiscs can be offloaded to HW, but current implementation isn't uniform. Instead, qdiscs either pass information about offload status via their TCA_OPTIONS or omit it altogether. Introduce a new attribute - TCA_HW_OFFLOAD that would form a uniform uAPI for the offloading status of qdiscs. Signed-off-by: Yuval Mintz Acked-by: Jiri Pirko Signed-off-by: David S. Miller --- include/net/sch_generic.h | 1 + include/uapi/linux/rtnetlink.h | 1 + net/sched/sch_api.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h index 65d0d25f2648..83a3e47d5845 100644 --- a/include/net/sch_generic.h +++ b/include/net/sch_generic.h @@ -71,6 +71,7 @@ struct Qdisc { * qdisc_tree_decrease_qlen() should stop. */ #define TCQ_F_INVISIBLE 0x80 /* invisible by default in dump */ +#define TCQ_F_OFFLOADED 0x200 /* qdisc is offloaded to HW */ u32 limit; const struct Qdisc_ops *ops; struct qdisc_size_table __rcu *stab; diff --git a/include/uapi/linux/rtnetlink.h b/include/uapi/linux/rtnetlink.h index d8b5f80c2ea6..843e29aa3cac 100644 --- a/include/uapi/linux/rtnetlink.h +++ b/include/uapi/linux/rtnetlink.h @@ -557,6 +557,7 @@ enum { TCA_PAD, TCA_DUMP_INVISIBLE, TCA_CHAIN, + TCA_HW_OFFLOAD, __TCA_MAX }; diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c index b6c4f536876b..0f1eab99ff4e 100644 --- a/net/sched/sch_api.c +++ b/net/sched/sch_api.c @@ -795,6 +795,8 @@ static int tc_fill_qdisc(struct sk_buff *skb, struct Qdisc *q, u32 clid, tcm->tcm_info = refcount_read(&q->refcnt); if (nla_put_string(skb, TCA_KIND, q->ops->id)) goto nla_put_failure; + if (nla_put_u8(skb, TCA_HW_OFFLOAD, !!(q->flags & TCQ_F_OFFLOADED))) + goto nla_put_failure; if (q->ops->dump && q->ops->dump(q, skb) < 0) goto nla_put_failure; qlen = q->q.qlen; -- GitLab From 428a68af3a7c3a3380ff1f750a24d213f370f89f Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Thu, 14 Dec 2017 15:54:30 +0200 Subject: [PATCH 1598/2547] net: sched: Move to new offload indication in RED Let RED utilize the new internal flag, TCQ_F_OFFLOADED, to mark a given qdisc as offloaded instead of using a dedicated indication. Also, change internal logic into looking at said flag when possible. Fixes: 602f3baf2218 ("net_sch: red: Add offload ability to RED qdisc") Signed-off-by: Yuval Mintz Acked-by: Jiri Pirko Signed-off-by: David S. Miller --- net/sched/sch_red.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/net/sched/sch_red.c b/net/sched/sch_red.c index 9d874e60e032..f0747eb87dc4 100644 --- a/net/sched/sch_red.c +++ b/net/sched/sch_red.c @@ -157,6 +157,7 @@ static int red_offload(struct Qdisc *sch, bool enable) .handle = sch->handle, .parent = sch->parent, }; + int err; if (!tc_can_offload(dev) || !dev->netdev_ops->ndo_setup_tc) return -EOPNOTSUPP; @@ -171,7 +172,14 @@ static int red_offload(struct Qdisc *sch, bool enable) opt.command = TC_RED_DESTROY; } - return dev->netdev_ops->ndo_setup_tc(dev, TC_SETUP_QDISC_RED, &opt); + err = dev->netdev_ops->ndo_setup_tc(dev, TC_SETUP_QDISC_RED, &opt); + + if (!err && enable) + sch->flags |= TCQ_F_OFFLOADED; + else + sch->flags &= ~TCQ_F_OFFLOADED; + + return err; } static void red_destroy(struct Qdisc *sch) @@ -274,7 +282,7 @@ static int red_init(struct Qdisc *sch, struct nlattr *opt) return red_change(sch, opt); } -static int red_dump_offload(struct Qdisc *sch, struct tc_red_qopt *opt) +static int red_dump_offload_stats(struct Qdisc *sch, struct tc_red_qopt *opt) { struct net_device *dev = qdisc_dev(sch); struct tc_red_qopt_offload hw_stats = { @@ -286,21 +294,12 @@ static int red_dump_offload(struct Qdisc *sch, struct tc_red_qopt *opt) .stats.qstats = &sch->qstats, }, }; - int err; - opt->flags &= ~TC_RED_OFFLOADED; - if (!tc_can_offload(dev) || !dev->netdev_ops->ndo_setup_tc) - return 0; - - err = dev->netdev_ops->ndo_setup_tc(dev, TC_SETUP_QDISC_RED, - &hw_stats); - if (err == -EOPNOTSUPP) + if (!(sch->flags & TCQ_F_OFFLOADED)) return 0; - if (!err) - opt->flags |= TC_RED_OFFLOADED; - - return err; + return dev->netdev_ops->ndo_setup_tc(dev, TC_SETUP_QDISC_RED, + &hw_stats); } static int red_dump(struct Qdisc *sch, struct sk_buff *skb) @@ -319,7 +318,7 @@ static int red_dump(struct Qdisc *sch, struct sk_buff *skb) int err; sch->qstats.backlog = q->qdisc->qstats.backlog; - err = red_dump_offload(sch, &opt); + err = red_dump_offload_stats(sch, &opt); if (err) goto nla_put_failure; @@ -347,7 +346,7 @@ static int red_dump_stats(struct Qdisc *sch, struct gnet_dump *d) .marked = q->stats.prob_mark + q->stats.forced_mark, }; - if (tc_can_offload(dev) && dev->netdev_ops->ndo_setup_tc) { + if (sch->flags & TCQ_F_OFFLOADED) { struct red_stats hw_stats = {0}; struct tc_red_qopt_offload hw_stats_request = { .command = TC_RED_XSTATS, -- GitLab From 4a98795bc8ea148b1ebbbf001283e06430cffe36 Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Thu, 14 Dec 2017 15:54:31 +0200 Subject: [PATCH 1599/2547] pkt_sched: Remove TC_RED_OFFLOADED from uapi Following the previous patch, RED is now using the new uniform uapi for indicating it's offloaded. As a result, TC_RED_OFFLOADED is no longer utilized by kernel and can be removed [as it's still not part of any stable release]. Fixes: 602f3baf2218 ("net_sch: red: Add offload ability to RED qdisc") Signed-off-by: Yuval Mintz Acked-by: Jiri Pirko Signed-off-by: David S. Miller --- include/uapi/linux/pkt_sched.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/uapi/linux/pkt_sched.h b/include/uapi/linux/pkt_sched.h index af3cc2f4e1ad..37b5096ae97b 100644 --- a/include/uapi/linux/pkt_sched.h +++ b/include/uapi/linux/pkt_sched.h @@ -256,7 +256,6 @@ struct tc_red_qopt { #define TC_RED_ECN 1 #define TC_RED_HARDDROP 2 #define TC_RED_ADAPTATIVE 4 -#define TC_RED_OFFLOADED 8 }; struct tc_red_xstats { -- GitLab From c647c0d62c82eb3ddf78a0d8b3d58819d9f552aa Mon Sep 17 00:00:00 2001 From: Daniele Palmas Date: Thu, 14 Dec 2017 16:56:14 +0100 Subject: [PATCH 1600/2547] net: usb: qmi_wwan: add Telit ME910 PID 0x1101 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds support for Telit ME910 PID 0x1101. Signed-off-by: Daniele Palmas Acked-by: Bjørn Mork Signed-off-by: David S. Miller --- drivers/net/usb/qmi_wwan.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c index d2ca5a202e8d..3000ddd1c7e2 100644 --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c @@ -1211,6 +1211,7 @@ static const struct usb_device_id products[] = { {QMI_FIXED_INTF(0x2357, 0x9000, 4)}, /* TP-LINK MA260 */ {QMI_QUIRK_SET_DTR(0x1bc7, 0x1040, 2)}, /* Telit LE922A */ {QMI_FIXED_INTF(0x1bc7, 0x1100, 3)}, /* Telit ME910 */ + {QMI_FIXED_INTF(0x1bc7, 0x1101, 3)}, /* Telit ME910 dual modem */ {QMI_FIXED_INTF(0x1bc7, 0x1200, 5)}, /* Telit LE920 */ {QMI_QUIRK_SET_DTR(0x1bc7, 0x1201, 2)}, /* Telit LE920, LE920A4 */ {QMI_FIXED_INTF(0x1c9e, 0x9801, 3)}, /* Telewell TW-3G HSPA+ */ -- GitLab From f57ab9a01a36ef3454333251cc57e3a9948b17bf Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 17 Nov 2017 11:56:41 +0000 Subject: [PATCH 1601/2547] drivers: base: cacheinfo: fix cache type for non-architected system cache Commit dfea747d2aba ("drivers: base: cacheinfo: support DT overrides for cache properties") doesn't initialise the cache type if it's present only in DT and the architecture is not aware of it. They are unified system level cache which are generally transparent. This patch check if the cache type is set to NOCACHE but the DT node indicates that it's unified cache and sets the cache type accordingly. Fixes: dfea747d2aba ("drivers: base: cacheinfo: support DT overrides for cache properties") Reported-and-tested-by: Tan Xiaojun Cc: Greg Kroah-Hartman Signed-off-by: Sudeep Holla Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/base/cacheinfo.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index eb3af2739537..07532d83be0b 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -186,6 +186,11 @@ static void cache_associativity(struct cacheinfo *this_leaf) this_leaf->ways_of_associativity = (size / nr_sets) / line_size; } +static bool cache_node_is_unified(struct cacheinfo *this_leaf) +{ + return of_property_read_bool(this_leaf->of_node, "cache-unified"); +} + static void cache_of_override_properties(unsigned int cpu) { int index; @@ -194,6 +199,14 @@ static void cache_of_override_properties(unsigned int cpu) for (index = 0; index < cache_leaves(cpu); index++) { this_leaf = this_cpu_ci->info_list + index; + /* + * init_cache_level must setup the cache level correctly + * overriding the architecturally specified levels, so + * if type is NONE at this stage, it should be unified + */ + if (this_leaf->type == CACHE_TYPE_NOCACHE && + cache_node_is_unified(this_leaf)) + this_leaf->type = CACHE_TYPE_UNIFIED; cache_size(this_leaf); cache_get_line_size(this_leaf); cache_nr_sets(this_leaf); -- GitLab From c05fad5713b81b049ec6ac4eb2d304030b1efdce Mon Sep 17 00:00:00 2001 From: Haishuang Yan Date: Fri, 15 Dec 2017 10:46:16 +0800 Subject: [PATCH 1602/2547] ip_gre: fix wrong return value of erspan_rcv If pskb_may_pull return failed, return PACKET_REJECT instead of -ENOMEM. Fixes: 84e54fe0a5ea ("gre: introduce native tunnel support for ERSPAN") Cc: William Tu Signed-off-by: Haishuang Yan Acked-by: William Tu Signed-off-by: David S. Miller --- net/ipv4/ip_gre.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/ipv4/ip_gre.c b/net/ipv4/ip_gre.c index bb6239169b1a..9c1735632c8c 100644 --- a/net/ipv4/ip_gre.c +++ b/net/ipv4/ip_gre.c @@ -266,7 +266,7 @@ static int erspan_rcv(struct sk_buff *skb, struct tnl_ptk_info *tpi, len = gre_hdr_len + sizeof(*ershdr); if (unlikely(!pskb_may_pull(skb, len))) - return -ENOMEM; + return PACKET_REJECT; iph = ip_hdr(skb); ershdr = (struct erspanhdr *)(skb->data + gre_hdr_len); -- GitLab From c156618e15101a9cc8c815108fec0300a0ec6637 Mon Sep 17 00:00:00 2001 From: Scott Mayhew Date: Tue, 5 Dec 2017 13:55:44 -0500 Subject: [PATCH 1603/2547] nfs: fix a deadlock in nfs client initialization The following deadlock can occur between a process waiting for a client to initialize in while walking the client list during nfsv4 server trunking detection and another process waiting for the nfs_clid_init_mutex so it can initialize that client: Process 1 Process 2 --------- --------- spin_lock(&nn->nfs_client_lock); list_add_tail(&CLIENTA->cl_share_link, &nn->nfs_client_list); spin_unlock(&nn->nfs_client_lock); spin_lock(&nn->nfs_client_lock); list_add_tail(&CLIENTB->cl_share_link, &nn->nfs_client_list); spin_unlock(&nn->nfs_client_lock); mutex_lock(&nfs_clid_init_mutex); nfs41_walk_client_list(clp, result, cred); nfs_wait_client_init_complete(CLIENTA); (waiting for nfs_clid_init_mutex) Make sure nfs_match_client() only evaluates clients that have completed initialization in order to prevent that deadlock. This patch also fixes v4.0 trunking behavior by not marking the client NFS_CS_READY until the clientid has been confirmed. Signed-off-by: Scott Mayhew Signed-off-by: Anna Schumaker --- fs/nfs/client.c | 11 +++++++++++ fs/nfs/nfs4client.c | 17 +++++++++++++---- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/fs/nfs/client.c b/fs/nfs/client.c index 0ac2fb1c6b63..b9129e2befea 100644 --- a/fs/nfs/client.c +++ b/fs/nfs/client.c @@ -291,12 +291,23 @@ static struct nfs_client *nfs_match_client(const struct nfs_client_initdata *dat const struct sockaddr *sap = data->addr; struct nfs_net *nn = net_generic(data->net, nfs_net_id); +again: list_for_each_entry(clp, &nn->nfs_client_list, cl_share_link) { const struct sockaddr *clap = (struct sockaddr *)&clp->cl_addr; /* Don't match clients that failed to initialise properly */ if (clp->cl_cons_state < 0) continue; + /* If a client is still initializing then we need to wait */ + if (clp->cl_cons_state > NFS_CS_READY) { + refcount_inc(&clp->cl_count); + spin_unlock(&nn->nfs_client_lock); + nfs_wait_client_init_complete(clp); + nfs_put_client(clp); + spin_lock(&nn->nfs_client_lock); + goto again; + } + /* Different NFS versions cannot share the same nfs_client */ if (clp->rpc_ops != data->nfs_mod->rpc_ops) continue; diff --git a/fs/nfs/nfs4client.c b/fs/nfs/nfs4client.c index 12bbab0becb4..65a7e5da508c 100644 --- a/fs/nfs/nfs4client.c +++ b/fs/nfs/nfs4client.c @@ -404,15 +404,19 @@ struct nfs_client *nfs4_init_client(struct nfs_client *clp, if (error < 0) goto error; - if (!nfs4_has_session(clp)) - nfs_mark_client_ready(clp, NFS_CS_READY); - error = nfs4_discover_server_trunking(clp, &old); if (error < 0) goto error; - if (clp != old) + if (clp != old) { clp->cl_preserve_clid = true; + /* + * Mark the client as having failed initialization so other + * processes walking the nfs_client_list in nfs_match_client() + * won't try to use it. + */ + nfs_mark_client_ready(clp, -EPERM); + } nfs_put_client(clp); clear_bit(NFS_CS_TSM_POSSIBLE, &clp->cl_flags); return old; @@ -539,6 +543,9 @@ int nfs40_walk_client_list(struct nfs_client *new, spin_lock(&nn->nfs_client_lock); list_for_each_entry(pos, &nn->nfs_client_list, cl_share_link) { + if (pos == new) + goto found; + status = nfs4_match_client(pos, new, &prev, nn); if (status < 0) goto out_unlock; @@ -559,6 +566,7 @@ int nfs40_walk_client_list(struct nfs_client *new, * way that a SETCLIENTID_CONFIRM to pos can succeed is * if new and pos point to the same server: */ +found: refcount_inc(&pos->cl_count); spin_unlock(&nn->nfs_client_lock); @@ -572,6 +580,7 @@ int nfs40_walk_client_list(struct nfs_client *new, case 0: nfs4_swap_callback_idents(pos, new); pos->cl_confirm = new->cl_confirm; + nfs_mark_client_ready(pos, NFS_CS_READY); prev = NULL; *result = pos; -- GitLab From ccede7598588ae344143f82fb763912535648d58 Mon Sep 17 00:00:00 2001 From: Chuck Lever Date: Mon, 4 Dec 2017 14:04:04 -0500 Subject: [PATCH 1604/2547] xprtrdma: Spread reply processing over more CPUs Commit d8f532d20ee4 ("xprtrdma: Invoke rpcrdma_reply_handler directly from RECV completion") introduced a performance regression for NFS I/O small enough to not need memory registration. In multi- threaded benchmarks that generate primarily small I/O requests, IOPS throughput is reduced by nearly a third. This patch restores the previous level of throughput. Because workqueues are typically BOUND (in particular ib_comp_wq, nfsiod_workqueue, and rpciod_workqueue), NFS/RDMA workloads tend to aggregate on the CPU that is handling Receive completions. The usual approach to addressing this problem is to create a QP and CQ for each CPU, and then schedule transactions on the QP for the CPU where you want the transaction to complete. The transaction then does not require an extra context switch during completion to end up on the same CPU where the transaction was started. This approach doesn't work for the Linux NFS/RDMA client because currently the Linux NFS client does not support multiple connections per client-server pair, and the RDMA core API does not make it straightforward for ULPs to determine which CPU is responsible for handling Receive completions for a CQ. So for the moment, record the CPU number in the rpcrdma_req before the transport sends each RPC Call. Then during Receive completion, queue the RPC completion on that same CPU. Additionally, move all RPC completion processing to the deferred handler so that even RPCs with simple small replies complete on the CPU that sent the corresponding RPC Call. Fixes: d8f532d20ee4 ("xprtrdma: Invoke rpcrdma_reply_handler ...") Signed-off-by: Chuck Lever Signed-off-by: Anna Schumaker --- net/sunrpc/xprtrdma/rpc_rdma.c | 6 +----- net/sunrpc/xprtrdma/transport.c | 2 ++ net/sunrpc/xprtrdma/verbs.c | 2 +- net/sunrpc/xprtrdma/xprt_rdma.h | 1 + 4 files changed, 5 insertions(+), 6 deletions(-) diff --git a/net/sunrpc/xprtrdma/rpc_rdma.c b/net/sunrpc/xprtrdma/rpc_rdma.c index ed34dc0f144c..a3f2ab283aeb 100644 --- a/net/sunrpc/xprtrdma/rpc_rdma.c +++ b/net/sunrpc/xprtrdma/rpc_rdma.c @@ -1408,11 +1408,7 @@ void rpcrdma_reply_handler(struct rpcrdma_rep *rep) dprintk("RPC: %s: reply %p completes request %p (xid 0x%08x)\n", __func__, rep, req, be32_to_cpu(rep->rr_xid)); - if (list_empty(&req->rl_registered) && - !test_bit(RPCRDMA_REQ_F_TX_RESOURCES, &req->rl_flags)) - rpcrdma_complete_rqst(rep); - else - queue_work(rpcrdma_receive_wq, &rep->rr_work); + queue_work_on(req->rl_cpu, rpcrdma_receive_wq, &rep->rr_work); return; out_badstatus: diff --git a/net/sunrpc/xprtrdma/transport.c b/net/sunrpc/xprtrdma/transport.c index 646c24494ea7..6ee1ad8978f3 100644 --- a/net/sunrpc/xprtrdma/transport.c +++ b/net/sunrpc/xprtrdma/transport.c @@ -52,6 +52,7 @@ #include #include #include +#include #include "xprt_rdma.h" @@ -656,6 +657,7 @@ xprt_rdma_allocate(struct rpc_task *task) task->tk_pid, __func__, rqst->rq_callsize, rqst->rq_rcvsize, req); + req->rl_cpu = smp_processor_id(); req->rl_connect_cookie = 0; /* our reserved value */ rpcrdma_set_xprtdata(rqst, req); rqst->rq_buffer = req->rl_sendbuf->rg_base; diff --git a/net/sunrpc/xprtrdma/verbs.c b/net/sunrpc/xprtrdma/verbs.c index 710b3f77db82..8607c029c0dd 100644 --- a/net/sunrpc/xprtrdma/verbs.c +++ b/net/sunrpc/xprtrdma/verbs.c @@ -83,7 +83,7 @@ rpcrdma_alloc_wq(void) struct workqueue_struct *recv_wq; recv_wq = alloc_workqueue("xprtrdma_receive", - WQ_MEM_RECLAIM | WQ_UNBOUND | WQ_HIGHPRI, + WQ_MEM_RECLAIM | WQ_HIGHPRI, 0); if (!recv_wq) return -ENOMEM; diff --git a/net/sunrpc/xprtrdma/xprt_rdma.h b/net/sunrpc/xprtrdma/xprt_rdma.h index 51686d9eac5f..1342f743f1c4 100644 --- a/net/sunrpc/xprtrdma/xprt_rdma.h +++ b/net/sunrpc/xprtrdma/xprt_rdma.h @@ -342,6 +342,7 @@ enum { struct rpcrdma_buffer; struct rpcrdma_req { struct list_head rl_list; + int rl_cpu; unsigned int rl_connect_cookie; struct rpcrdma_buffer *rl_buffer; struct rpcrdma_rep *rl_reply; -- GitLab From dc4fd9ab01ab379ae5af522b3efd4187a7c30a31 Mon Sep 17 00:00:00 2001 From: Scott Mayhew Date: Fri, 8 Dec 2017 16:00:12 -0500 Subject: [PATCH 1605/2547] nfs: don't wait on commit in nfs_commit_inode() if there were no commit requests If there were no commit requests, then nfs_commit_inode() should not wait on the commit or mark the inode dirty, otherwise the following BUG_ON can be triggered: [ 1917.130762] kernel BUG at fs/inode.c:578! [ 1917.130766] Oops: Exception in kernel mode, sig: 5 [#1] [ 1917.130768] SMP NR_CPUS=2048 NUMA pSeries [ 1917.130772] Modules linked in: iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi blocklayoutdriver rpcsec_gss_krb5 auth_rpcgss nfsv4 dns_resolver nfs lockd grace fscache sunrpc sg nx_crypto pseries_rng ip_tables xfs libcrc32c sd_mod crc_t10dif crct10dif_generic crct10dif_common ibmvscsi scsi_transport_srp ibmveth scsi_tgt dm_mirror dm_region_hash dm_log dm_mod [ 1917.130805] CPU: 2 PID: 14923 Comm: umount.nfs4 Tainted: G ------------ T 3.10.0-768.el7.ppc64 #1 [ 1917.130810] task: c0000005ecd88040 ti: c00000004cea0000 task.ti: c00000004cea0000 [ 1917.130813] NIP: c000000000354178 LR: c000000000354160 CTR: c00000000012db80 [ 1917.130816] REGS: c00000004cea3720 TRAP: 0700 Tainted: G ------------ T (3.10.0-768.el7.ppc64) [ 1917.130820] MSR: 8000000100029032 CR: 22002822 XER: 20000000 [ 1917.130828] CFAR: c00000000011f594 SOFTE: 1 GPR00: c000000000354160 c00000004cea39a0 c0000000014c4700 c0000000018cc750 GPR04: 000000000000c750 80c0000000000000 0600000000000000 04eeb76bea749a03 GPR08: 0000000000000034 c0000000018cc758 0000000000000001 d000000005e619e8 GPR12: c00000000012db80 c000000007b31200 0000000000000000 0000000000000000 GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR20: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR24: 0000000000000000 c000000000dfc3ec 0000000000000000 c0000005eefc02c0 GPR28: d0000000079dbd50 c0000005b94a02c0 c0000005b94a0250 c0000005b94a01c8 [ 1917.130867] NIP [c000000000354178] .evict+0x1c8/0x350 [ 1917.130871] LR [c000000000354160] .evict+0x1b0/0x350 [ 1917.130873] Call Trace: [ 1917.130876] [c00000004cea39a0] [c000000000354160] .evict+0x1b0/0x350 (unreliable) [ 1917.130880] [c00000004cea3a30] [c0000000003558cc] .evict_inodes+0x13c/0x270 [ 1917.130884] [c00000004cea3af0] [c000000000327d20] .kill_anon_super+0x70/0x1e0 [ 1917.130896] [c00000004cea3b80] [d000000005e43e30] .nfs_kill_super+0x20/0x60 [nfs] [ 1917.130900] [c00000004cea3c00] [c000000000328a20] .deactivate_locked_super+0xa0/0x1b0 [ 1917.130903] [c00000004cea3c80] [c00000000035ba54] .cleanup_mnt+0xd4/0x180 [ 1917.130907] [c00000004cea3d10] [c000000000119034] .task_work_run+0x114/0x150 [ 1917.130912] [c00000004cea3db0] [c00000000001ba6c] .do_notify_resume+0xcc/0x100 [ 1917.130916] [c00000004cea3e30] [c00000000000a7b0] .ret_from_except_lite+0x5c/0x60 [ 1917.130919] Instruction dump: [ 1917.130921] 7fc3f378 486734b5 60000000 387f00a0 38800003 4bdcb365 60000000 e95f00a0 [ 1917.130927] 694a0060 7d4a0074 794ad182 694a0001 <0b0a0000> 892d02a4 2f890000 40de0134 Signed-off-by: Scott Mayhew Cc: stable@vger.kernel.org # 4.5+ Signed-off-by: Anna Schumaker --- fs/nfs/write.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fs/nfs/write.c b/fs/nfs/write.c index 5b5f464f6f2a..4a379d7918f2 100644 --- a/fs/nfs/write.c +++ b/fs/nfs/write.c @@ -1890,6 +1890,8 @@ int nfs_commit_inode(struct inode *inode, int how) if (res) error = nfs_generic_commit_list(inode, &head, how, &cinfo); nfs_commit_end(cinfo.mds); + if (res == 0) + return res; if (error < 0) goto out_error; if (!may_wait) -- GitLab From 90d91b0cd371193d9dbfa9beacab8ab9a4cb75e0 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Thu, 14 Dec 2017 21:24:08 -0500 Subject: [PATCH 1606/2547] SUNRPC: Fix a race in the receive code path We must ensure that the call to rpc_sleep_on() in xprt_transmit() cannot race with the call to xprt_complete_rqst(). Reported-by: Chuck Lever Link: https://bugzilla.linux-nfs.org/show_bug.cgi?id=317 Fixes: ce7c252a8c74 ("SUNRPC: Add a separate spinlock to protect..") Cc: stable@vger.kernel.org # 4.14+ Reviewed-by: Chuck Lever Signed-off-by: Trond Myklebust Signed-off-by: Anna Schumaker --- net/sunrpc/xprt.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/net/sunrpc/xprt.c b/net/sunrpc/xprt.c index 02a9bacb239b..5b06f6906a27 100644 --- a/net/sunrpc/xprt.c +++ b/net/sunrpc/xprt.c @@ -1001,6 +1001,7 @@ void xprt_transmit(struct rpc_task *task) { struct rpc_rqst *req = task->tk_rqstp; struct rpc_xprt *xprt = req->rq_xprt; + unsigned int connect_cookie; int status, numreqs; dprintk("RPC: %5u xprt_transmit(%u)\n", task->tk_pid, req->rq_slen); @@ -1024,6 +1025,7 @@ void xprt_transmit(struct rpc_task *task) } else if (!req->rq_bytes_sent) return; + connect_cookie = xprt->connect_cookie; req->rq_xtime = ktime_get(); status = xprt->ops->send_request(task); trace_xprt_transmit(xprt, req->rq_xid, status); @@ -1047,20 +1049,28 @@ void xprt_transmit(struct rpc_task *task) xprt->stat.bklog_u += xprt->backlog.qlen; xprt->stat.sending_u += xprt->sending.qlen; xprt->stat.pending_u += xprt->pending.qlen; + spin_unlock_bh(&xprt->transport_lock); - /* Don't race with disconnect */ - if (!xprt_connected(xprt)) - task->tk_status = -ENOTCONN; - else { + req->rq_connect_cookie = connect_cookie; + if (rpc_reply_expected(task) && !READ_ONCE(req->rq_reply_bytes_recvd)) { /* - * Sleep on the pending queue since - * we're expecting a reply. + * Sleep on the pending queue if we're expecting a reply. + * The spinlock ensures atomicity between the test of + * req->rq_reply_bytes_recvd, and the call to rpc_sleep_on(). */ - if (!req->rq_reply_bytes_recvd && rpc_reply_expected(task)) + spin_lock(&xprt->recv_lock); + if (!req->rq_reply_bytes_recvd) { rpc_sleep_on(&xprt->pending, task, xprt_timer); - req->rq_connect_cookie = xprt->connect_cookie; + /* + * Send an extra queue wakeup call if the + * connection was dropped in case the call to + * rpc_sleep_on() raced. + */ + if (!xprt_connected(xprt)) + xprt_wake_pending_tasks(xprt, -ENOTCONN); + } + spin_unlock(&xprt->recv_lock); } - spin_unlock_bh(&xprt->transport_lock); } static void xprt_add_backlog(struct rpc_xprt *xprt, struct rpc_task *task) -- GitLab From 343723dd51ef1025a860e54df9472b5ba21ee3d9 Mon Sep 17 00:00:00 2001 From: Jiri Pirko Date: Fri, 15 Dec 2017 12:40:12 +0100 Subject: [PATCH 1607/2547] net: sched: fix clsact init error path Since in qdisc_create, the destroy op is called when init fails, we don't do cleanup in init and leave it up to destroy. This fixes use-after-free when trying to put already freed block. Fixes: 6e40cf2d4dee ("net: sched: use extended variants of block_get/put in ingress and clsact qdiscs") Signed-off-by: Jiri Pirko Acked-by: Cong Wang Signed-off-by: David S. Miller --- net/sched/cls_api.c | 4 ++-- net/sched/sch_ingress.c | 6 +----- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c index f40256a3e7f0..b91ea03e3afa 100644 --- a/net/sched/cls_api.c +++ b/net/sched/cls_api.c @@ -351,6 +351,8 @@ void tcf_block_put_ext(struct tcf_block *block, struct Qdisc *q, { struct tcf_chain *chain; + if (!block) + return; /* Hold a refcnt for all chains, except 0, so that they don't disappear * while we are iterating. */ @@ -377,8 +379,6 @@ void tcf_block_put(struct tcf_block *block) { struct tcf_block_ext_info ei = {0, }; - if (!block) - return; tcf_block_put_ext(block, block->q, &ei); } diff --git a/net/sched/sch_ingress.c b/net/sched/sch_ingress.c index 5ecc38f35d47..5e1cd2e5df87 100644 --- a/net/sched/sch_ingress.c +++ b/net/sched/sch_ingress.c @@ -190,7 +190,7 @@ static int clsact_init(struct Qdisc *sch, struct nlattr *opt) err = tcf_block_get_ext(&q->egress_block, sch, &q->egress_block_info); if (err) - goto err_egress_block_get; + return err; net_inc_ingress_queue(); net_inc_egress_queue(); @@ -198,10 +198,6 @@ static int clsact_init(struct Qdisc *sch, struct nlattr *opt) sch->flags |= TCQ_F_CPUSTATS; return 0; - -err_egress_block_get: - tcf_block_put_ext(q->ingress_block, sch, &q->ingress_block_info); - return err; } static void clsact_destroy(struct Qdisc *sch) -- GitLab From b59e6979a86384e68b0ab6ffeab11f0034fba82d Mon Sep 17 00:00:00 2001 From: Jiri Pirko Date: Fri, 15 Dec 2017 12:40:13 +0100 Subject: [PATCH 1608/2547] net: sched: fix static key imbalance in case of ingress/clsact_init error Move static key increments to the beginning of the init function so they pair 1:1 with decrements in ingress/clsact_destroy, which is called in case ingress/clsact_init fails. Fixes: 6529eaba33f0 ("net: sched: introduce tcf block infractructure") Signed-off-by: Jiri Pirko Acked-by: Cong Wang Signed-off-by: David S. Miller --- net/sched/sch_ingress.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/net/sched/sch_ingress.c b/net/sched/sch_ingress.c index 5e1cd2e5df87..fc1286f499c1 100644 --- a/net/sched/sch_ingress.c +++ b/net/sched/sch_ingress.c @@ -68,6 +68,8 @@ static int ingress_init(struct Qdisc *sch, struct nlattr *opt) struct net_device *dev = qdisc_dev(sch); int err; + net_inc_ingress_queue(); + mini_qdisc_pair_init(&q->miniqp, sch, &dev->miniq_ingress); q->block_info.binder_type = TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS; @@ -78,7 +80,6 @@ static int ingress_init(struct Qdisc *sch, struct nlattr *opt) if (err) return err; - net_inc_ingress_queue(); sch->flags |= TCQ_F_CPUSTATS; return 0; @@ -172,6 +173,9 @@ static int clsact_init(struct Qdisc *sch, struct nlattr *opt) struct net_device *dev = qdisc_dev(sch); int err; + net_inc_ingress_queue(); + net_inc_egress_queue(); + mini_qdisc_pair_init(&q->miniqp_ingress, sch, &dev->miniq_ingress); q->ingress_block_info.binder_type = TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS; @@ -192,9 +196,6 @@ static int clsact_init(struct Qdisc *sch, struct nlattr *opt) if (err) return err; - net_inc_ingress_queue(); - net_inc_egress_queue(); - sch->flags |= TCQ_F_CPUSTATS; return 0; -- GitLab From 043ee1debd0b29c16c4c4b11a348ca667bfe9144 Mon Sep 17 00:00:00 2001 From: Hemanth Puranik Date: Fri, 15 Dec 2017 20:05:58 +0530 Subject: [PATCH 1609/2547] net: qcom/emac: Reduce timeout for mdio read/write Currently mdio read/write takes around ~115us as the timeout between status check is set to 100us. By reducing the timeout to 1us mdio read/write takes ~15us to complete. This improves the link up event response. Signed-off-by: Hemanth Puranik Acked-by: Timur Tabi Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- drivers/net/ethernet/qualcomm/emac/emac-phy.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/qualcomm/emac/emac-phy.c b/drivers/net/ethernet/qualcomm/emac/emac-phy.c index 18461fcb9815..53dbf1e163a8 100644 --- a/drivers/net/ethernet/qualcomm/emac/emac-phy.c +++ b/drivers/net/ethernet/qualcomm/emac/emac-phy.c @@ -47,6 +47,7 @@ #define MDIO_CLK_25_28 7 #define MDIO_WAIT_TIMES 1000 +#define MDIO_STATUS_DELAY_TIME 1 static int emac_mdio_read(struct mii_bus *bus, int addr, int regnum) { @@ -65,7 +66,7 @@ static int emac_mdio_read(struct mii_bus *bus, int addr, int regnum) if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg, !(reg & (MDIO_START | MDIO_BUSY)), - 100, MDIO_WAIT_TIMES * 100)) + MDIO_STATUS_DELAY_TIME, MDIO_WAIT_TIMES * 100)) return -EIO; return (reg >> MDIO_DATA_SHFT) & MDIO_DATA_BMSK; @@ -88,8 +89,8 @@ static int emac_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) writel(reg, adpt->base + EMAC_MDIO_CTRL); if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg, - !(reg & (MDIO_START | MDIO_BUSY)), 100, - MDIO_WAIT_TIMES * 100)) + !(reg & (MDIO_START | MDIO_BUSY)), + MDIO_STATUS_DELAY_TIME, MDIO_WAIT_TIMES * 100)) return -EIO; return 0; -- GitLab From 33aa69ed8aacd92dea12671e52eb3ca6ac2d7a49 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Wed, 13 Dec 2017 12:04:25 -0800 Subject: [PATCH 1610/2547] x86/gpu: add CFL to early quirks CFL was missing from intel_early_ids[]. The PCI ID needs to be there to allow the memory region to be stolen, otherwise we could have RAM being arbitrarily overwritten if for example we keep using the UEFI framebuffer, depending on how BIOS has set up the e820 map. Fixes: b056f8f3d6b9 ("drm/i915/cfl: Add Coffee Lake PCI IDs for S Skus.") Signed-off-by: Lucas De Marchi Cc: Rodrigo Vivi Cc: Anusha Srivatsa Cc: Jani Nikula Cc: Joonas Lahtinen Cc: David Airlie Cc: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: Ingo Molnar Cc: H. Peter Anvin Cc: Thomas Gleixner Cc: x86@kernel.org Cc: # v4.13+ 0890540e21cf drm/i915: add GT number to intel_device_info Cc: # v4.13+ 41693fd52373 drm/i915/kbl: Change a KBL pci id to GT2 from GT1.5 Cc: # v4.13+ Reviewed-by: Rodrigo Vivi Acked-by: Jani Nikula Acked-by: Ingo Molnar Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20171213200425.2954-1-lucas.demarchi@intel.com --- arch/x86/kernel/early-quirks.c | 1 + include/drm/i915_pciids.h | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 3cbb2c78a9df..bae0d32e327b 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -528,6 +528,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_SKL_IDS(&gen9_early_ops), INTEL_BXT_IDS(&gen9_early_ops), INTEL_KBL_IDS(&gen9_early_ops), + INTEL_CFL_IDS(&gen9_early_ops), INTEL_GLK_IDS(&gen9_early_ops), INTEL_CNL_IDS(&gen9_early_ops), }; diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 972a25633525..c65e4489006d 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -392,6 +392,12 @@ INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x3EA5, info) /* ULT GT3 */ +#define INTEL_CFL_IDS(info) \ + INTEL_CFL_S_GT1_IDS(info), \ + INTEL_CFL_S_GT2_IDS(info), \ + INTEL_CFL_H_GT2_IDS(info), \ + INTEL_CFL_U_GT3_IDS(info) + /* CNL U 2+2 */ #define INTEL_CNL_U_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x5A52, info), \ -- GitLab From caea4f384858ee7861367920df36995e7acfe160 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 15 Dec 2017 16:21:50 +0100 Subject: [PATCH 1611/2547] drm/sun4i: validate modes for HDMI When I connected my cubieboard running 4.15-rc1 to my 4k display I got no picture. Some digging found that there is no check against the upper pixelclock limit of the HDMI output, so X selects a 4kp60 format at 594 MHz, which obviously won't work. The patch below adds a check for the upper bound of what this hardware can do, and it checks if the requested tmds clock can be obtained. It also allows for the +/- 0.5% pixel clock variation that the HDMI spec permits. That code is based on commit 22d0be2a557e ("drm: arcpgu: Allow some clock deviation in crtc->mode_valid() callback") from Jose Abreu for drm/arc. Signed-off-by: Hans Verkuil Thanks-to: Jose Abreu Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/162854cb-c7bd-d9ce-9fa0-9a6cd89c621b@xs4all.nl --- drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c index dda904ec0534..c12f9bd12904 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c @@ -208,8 +208,27 @@ static int sun4i_hdmi_get_modes(struct drm_connector *connector) return ret; } +static int sun4i_hdmi_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); + long rate = mode->clock * 1000; + long diff = rate / 200; /* +-0.5% allowed by HDMI spec */ + long rounded_rate; + + /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */ + if (rate > 165000000) + return MODE_CLOCK_HIGH; + rounded_rate = clk_round_rate(hdmi->tmds_clk, rate); + if (max(rounded_rate, rate) - min(rounded_rate, rate) < diff && + rounded_rate > 0) + return MODE_OK; + return MODE_NOCLOCK; +} + static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = { .get_modes = sun4i_hdmi_get_modes, + .mode_valid = sun4i_hdmi_mode_valid, }; static enum drm_connector_status -- GitLab From fdf2e821052958a114618a95ab18a300d0b080cb Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 5 Dec 2017 11:51:40 +0100 Subject: [PATCH 1612/2547] mtd: nand: gpmi: Fix failure when a erased page has a bitflip at BBM When erased subpages are read then the BCH decoder returns STATUS_ERASED if they are all empty, or STATUS_UNCORRECTABLE if there are bitflips. When there are bitflips, we have to set these bits again to show the upper layers a completely erased page. When a bitflip happens in the exact byte where the bad block marker is, then this byte is swapped with another byte in block_mark_swapping(). The correction code then detects a bitflip in another subpage and no longer corrects the bitflip where it really happens. Correct this behaviour by calling block_mark_swapping() after the bitflips have been corrected. In our case UBIFS failed with this bug because it expects erased pages to be really empty: UBIFS error (pid 187): ubifs_scan: corrupt empty space at LEB 36:118735 UBIFS error (pid 187): ubifs_scanned_corruption: corruption at LEB 36:118735 UBIFS error (pid 187): ubifs_scanned_corruption: first 8192 bytes from LEB 36:118735 UBIFS error (pid 187): ubifs_scan: LEB 36 scanning failed UBIFS error (pid 187): do_commit: commit failed, error -117 Signed-off-by: Sascha Hauer Reviewed-by: Richard Weinberger Acked-by: Boris Brezillon Signed-off-by: Richard Weinberger --- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 50f8d4a1b983..d4d824ef64e9 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -1067,9 +1067,6 @@ static int gpmi_ecc_read_page(struct mtd_info *mtd, struct nand_chip *chip, return ret; } - /* handle the block mark swapping */ - block_mark_swapping(this, payload_virt, auxiliary_virt); - /* Loop over status bytes, accumulating ECC status. */ status = auxiliary_virt + nfc_geo->auxiliary_status_offset; @@ -1158,6 +1155,9 @@ static int gpmi_ecc_read_page(struct mtd_info *mtd, struct nand_chip *chip, max_bitflips = max_t(unsigned int, max_bitflips, *status); } + /* handle the block mark swapping */ + block_mark_swapping(this, buf, auxiliary_virt); + if (oob_required) { /* * It's time to deliver the OOB bytes. See gpmi_ecc_read_oob() -- GitLab From e44b9a9c135727f3410e029910275f40681dc8bc Mon Sep 17 00:00:00 2001 From: Albert Hsieh Date: Mon, 20 Nov 2017 11:26:26 +0800 Subject: [PATCH 1613/2547] mtd: nand: brcmnand: Zero bitflip is not an error A negative return value of brcmstb_nand_verify_erased_page() indicates a real bitflip error of an erased page, and other return values (>= 0) show the corrected bitflip number. Zero return value means no bitflip, but the current driver code treats it as an error, and eventually leads to falsely reported ECC error. Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflip") Signed-off-by: Albert Hsieh Acked-by: Boris Brezillon Signed-off-by: Richard Weinberger --- drivers/mtd/nand/brcmnand/brcmnand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c b/drivers/mtd/nand/brcmnand/brcmnand.c index e0eb51d8c012..dd56a671ea42 100644 --- a/drivers/mtd/nand/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/brcmnand/brcmnand.c @@ -1763,7 +1763,7 @@ static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip, err = brcmstb_nand_verify_erased_page(mtd, chip, buf, addr); /* erased page bitflips corrected */ - if (err > 0) + if (err >= 0) return err; } -- GitLab From bc2fd1b11097ad981478abcc0328784ea131ac29 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Wed, 6 Dec 2017 18:27:14 +0100 Subject: [PATCH 1614/2547] mtd: nand: gpio: Fix ALE gpio configuration Fixes a copy/paste error in commit f3d0d8d938b4d ("mtd: nand: gpio: Convert to use GPIO descriptors") which breaks gpio-nand driver Fixes: f3d0d8d938b4d ("mtd: nand: gpio: Convert to use GPIO descriptors") Cc: Linus Walleij Signed-off-by: Christophe Leroy Reviewed-by: Richard Weinberger Acked-by: Boris Brezillon Reviewed-by: Linus Walleij Signed-off-by: Richard Weinberger --- drivers/mtd/nand/gpio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/gpio.c b/drivers/mtd/nand/gpio.c index 484f7fbc3f7d..a8bde6665c24 100644 --- a/drivers/mtd/nand/gpio.c +++ b/drivers/mtd/nand/gpio.c @@ -253,9 +253,9 @@ static int gpio_nand_probe(struct platform_device *pdev) goto out_ce; } - gpiomtd->nwp = devm_gpiod_get(dev, "ale", GPIOD_OUT_LOW); - if (IS_ERR(gpiomtd->nwp)) { - ret = PTR_ERR(gpiomtd->nwp); + gpiomtd->ale = devm_gpiod_get(dev, "ale", GPIOD_OUT_LOW); + if (IS_ERR(gpiomtd->ale)) { + ret = PTR_ERR(gpiomtd->ale); goto out_ce; } -- GitLab From 8836e4b8d3a04a5097a83c5f9b25662fa6a9ebbc Mon Sep 17 00:00:00 2001 From: Roger He Date: Fri, 8 Dec 2017 11:36:46 +0800 Subject: [PATCH 1615/2547] drm/ttm: add allow_reserved_eviction and resv into ttm_operation_ctx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit allow_reserved_eviction: Allow eviction of reserved BOs resv: Reservation object to allow reserved evictions with Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- include/drm/ttm/ttm_bo_api.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index 368eb02b54a9..c1263308145a 100644 --- a/include/drm/ttm/ttm_bo_api.h +++ b/include/drm/ttm/ttm_bo_api.h @@ -263,6 +263,8 @@ struct ttm_bo_kmap_obj { * * @interruptible: Sleep interruptible if sleeping. * @no_wait_gpu: Return immediately if the GPU is busy. + * @allow_reserved_eviction: Allow eviction of reserved BOs. + * @resv: Reservation object to allow reserved evictions with. * * Context for TTM operations like changing buffer placement or general memory * allocation. @@ -270,6 +272,8 @@ struct ttm_bo_kmap_obj { struct ttm_operation_ctx { bool interruptible; bool no_wait_gpu; + bool allow_reserved_eviction; + struct reservation_object *resv; uint64_t bytes_moved; }; -- GitLab From 9251859a9adb8e5906402acc9d705149d937bf8b Mon Sep 17 00:00:00 2001 From: Roger He Date: Fri, 8 Dec 2017 13:31:52 +0800 Subject: [PATCH 1616/2547] drm/amdgpu: set allow_reserved_eviction and resv when bo allocation and cs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit enable eviction of other per VM BOs during allocation and allows reaping of deleted BOs during CS. Reviewed-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 ++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 7 ++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 44523a88ebb2..5e539fc5b05f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -343,7 +343,12 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, struct amdgpu_bo *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - struct ttm_operation_ctx ctx = { true, false }; + struct ttm_operation_ctx ctx = { + .interruptible = true, + .no_wait_gpu = false, + .allow_reserved_eviction = false, + .resv = bo->tbo.resv + }; uint32_t domain; int r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index dc0a8be98043..86340cfa6be7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -327,7 +327,12 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, uint64_t init_value, struct amdgpu_bo **bo_ptr) { - struct ttm_operation_ctx ctx = { !kernel, false }; + struct ttm_operation_ctx ctx = { + .interruptible = !kernel, + .no_wait_gpu = false, + .allow_reserved_eviction = true, + .resv = resv + }; struct amdgpu_bo *bo; enum ttm_bo_type type; unsigned long page_align; -- GitLab From 4985c9fc5f5231e93c4dcfd067d2c6a70e4fe6b8 Mon Sep 17 00:00:00 2001 From: Roger He Date: Wed, 6 Dec 2017 14:16:09 +0800 Subject: [PATCH 1617/2547] drm/ttm: enable eviction for Per-VM-BO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit allow eviction of BOs reserved by the caller when they are not part of the current working set. Reviewed-by: Christian König Signed-off-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 7a9abc2a3a98..17f64c836bf9 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -709,7 +709,6 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, EXPORT_SYMBOL(ttm_bo_eviction_valuable); static int ttm_mem_evict_first(struct ttm_bo_device *bdev, - struct reservation_object *resv, uint32_t mem_type, const struct ttm_place *place, struct ttm_operation_ctx *ctx) @@ -724,8 +723,9 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev, spin_lock(&glob->lru_lock); for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) { list_for_each_entry(bo, &man->lru[i], lru) { - if (bo->resv == resv) { - if (list_empty(&bo->ddestroy)) + if (bo->resv == ctx->resv) { + if (!ctx->allow_reserved_eviction && + list_empty(&bo->ddestroy)) continue; } else { locked = reservation_object_trylock(bo->resv); @@ -837,7 +837,7 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object *bo, return ret; if (mem->mm_node) break; - ret = ttm_mem_evict_first(bdev, bo->resv, mem_type, place, ctx); + ret = ttm_mem_evict_first(bdev, mem_type, place, ctx); if (unlikely(ret != 0)) return ret; } while (1); @@ -1334,8 +1334,7 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) { while (!list_empty(&man->lru[i])) { spin_unlock(&glob->lru_lock); - ret = ttm_mem_evict_first(bdev, NULL, mem_type, - NULL, &ctx); + ret = ttm_mem_evict_first(bdev, mem_type, NULL, &ctx); if (ret) return ret; spin_lock(&glob->lru_lock); -- GitLab From 3e98d829ad0a59425f816c94447b4ac39a72f632 Mon Sep 17 00:00:00 2001 From: Roger He Date: Fri, 8 Dec 2017 20:19:32 +0800 Subject: [PATCH 1618/2547] drm/ttm: use an ttm operation ctx for ttm_bo_move_xxx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit include ttm_bo_move_memcpy and ttm_bo_move_ttm Signed-off-by: Roger He Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 7 +++---- drivers/gpu/drm/nouveau/nouveau_bo.c | 7 +++---- drivers/gpu/drm/qxl/qxl_ttm.c | 3 +-- drivers/gpu/drm/radeon/radeon_ttm.c | 7 +++---- drivers/gpu/drm/ttm/ttm_bo.c | 6 ++---- drivers/gpu/drm/ttm/ttm_bo_util.c | 8 ++++---- include/drm/ttm/ttm_bo_driver.h | 4 ++-- 7 files changed, 18 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 7db9556b389b..c307a7d2cf16 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -505,7 +505,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, if (unlikely(r)) { goto out_cleanup; } - r = ttm_bo_move_ttm(bo, ctx->interruptible, ctx->no_wait_gpu, new_mem); + r = ttm_bo_move_ttm(bo, ctx, new_mem); out_cleanup: ttm_bo_mem_put(bo, &tmp_mem); return r; @@ -536,7 +536,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, if (unlikely(r)) { return r; } - r = ttm_bo_move_ttm(bo, ctx->interruptible, ctx->no_wait_gpu, &tmp_mem); + r = ttm_bo_move_ttm(bo, ctx, &tmp_mem); if (unlikely(r)) { goto out_cleanup; } @@ -597,8 +597,7 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, if (r) { memcpy: - r = ttm_bo_move_memcpy(bo, ctx->interruptible, - ctx->no_wait_gpu, new_mem); + r = ttm_bo_move_memcpy(bo, ctx, new_mem); if (r) { return r; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 949bf6b3feab..6b6fb2080ac3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1226,7 +1226,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, if (ret) goto out; - ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, new_reg); + ret = ttm_bo_move_ttm(bo, &ctx, new_reg); out: ttm_bo_mem_put(bo, &tmp_reg); return ret; @@ -1255,7 +1255,7 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, if (ret) return ret; - ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, &tmp_reg); + ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg); if (ret) goto out; @@ -1380,8 +1380,7 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, /* Fallback to software copy. */ ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (ret == 0) - ret = ttm_bo_move_memcpy(bo, ctx->interruptible, - ctx->no_wait_gpu, new_reg); + ret = ttm_bo_move_memcpy(bo, ctx, new_reg); out: if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c index d866f329e7d8..78ce118d9157 100644 --- a/drivers/gpu/drm/qxl/qxl_ttm.c +++ b/drivers/gpu/drm/qxl/qxl_ttm.c @@ -357,8 +357,7 @@ static int qxl_bo_move(struct ttm_buffer_object *bo, bool evict, qxl_move_null(bo, new_mem); return 0; } - return ttm_bo_move_memcpy(bo, ctx->interruptible, ctx->no_wait_gpu, - new_mem); + return ttm_bo_move_memcpy(bo, ctx, new_mem); } static void qxl_bo_move_notify(struct ttm_buffer_object *bo, diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 98e30d71d9e0..557fd7915973 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -347,7 +347,7 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo, if (unlikely(r)) { goto out_cleanup; } - r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem); + r = ttm_bo_move_ttm(bo, &ctx, new_mem); out_cleanup: ttm_bo_mem_put(bo, &tmp_mem); return r; @@ -380,7 +380,7 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo, if (unlikely(r)) { return r; } - r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem); + r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem); if (unlikely(r)) { goto out_cleanup; } @@ -445,8 +445,7 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, if (r) { memcpy: - r = ttm_bo_move_memcpy(bo, ctx->interruptible, - ctx->no_wait_gpu, new_mem); + r = ttm_bo_move_memcpy(bo, ctx, new_mem); if (r) { return r; } diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 17f64c836bf9..ba5b48617bba 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -324,13 +324,11 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, if (!(old_man->flags & TTM_MEMTYPE_FLAG_FIXED) && !(new_man->flags & TTM_MEMTYPE_FLAG_FIXED)) - ret = ttm_bo_move_ttm(bo, ctx->interruptible, - ctx->no_wait_gpu, mem); + ret = ttm_bo_move_ttm(bo, ctx, mem); else if (bdev->driver->move) ret = bdev->driver->move(bo, evict, ctx, mem); else - ret = ttm_bo_move_memcpy(bo, ctx->interruptible, - ctx->no_wait_gpu, mem); + ret = ttm_bo_move_memcpy(bo, ctx, mem); if (ret) { if (bdev->driver->move_notify) { diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index e7a519f1849b..9237099a7c49 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -45,7 +45,7 @@ void ttm_bo_free_old_node(struct ttm_buffer_object *bo) } int ttm_bo_move_ttm(struct ttm_buffer_object *bo, - bool interruptible, bool no_wait_gpu, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem) { struct ttm_tt *ttm = bo->ttm; @@ -53,7 +53,7 @@ int ttm_bo_move_ttm(struct ttm_buffer_object *bo, int ret; if (old_mem->mem_type != TTM_PL_SYSTEM) { - ret = ttm_bo_wait(bo, interruptible, no_wait_gpu); + ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (unlikely(ret != 0)) { if (ret != -ERESTARTSYS) @@ -329,7 +329,7 @@ static int ttm_copy_ttm_io_page(struct ttm_tt *ttm, void *dst, } int ttm_bo_move_memcpy(struct ttm_buffer_object *bo, - bool interruptible, bool no_wait_gpu, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem) { struct ttm_bo_device *bdev = bo->bdev; @@ -345,7 +345,7 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object *bo, unsigned long add = 0; int dir; - ret = ttm_bo_wait(bo, interruptible, no_wait_gpu); + ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (ret) return ret; diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index 6996d884c508..5115718ca607 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -976,7 +976,7 @@ void ttm_mem_io_free(struct ttm_bo_device *bdev, */ int ttm_bo_move_ttm(struct ttm_buffer_object *bo, - bool interruptible, bool no_wait_gpu, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem); /** @@ -998,7 +998,7 @@ int ttm_bo_move_ttm(struct ttm_buffer_object *bo, */ int ttm_bo_move_memcpy(struct ttm_buffer_object *bo, - bool interruptible, bool no_wait_gpu, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem); /** -- GitLab From dcebf026e6f69fb79e7f88d10681faf4f8a985ba Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 12 Dec 2017 14:09:30 -0500 Subject: [PATCH 1619/2547] drm/amdgpu: Add gpu_recovery parameter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add new parameter to control GPU recovery procedure. v2: Add auto logic where reset is disabled for bare metal and enabled for SR-IOV. Allow forced reset from debugfs. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 ++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 2 +- drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +- 8 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c31c5496dc5e..ffbe99d839a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -126,6 +126,7 @@ extern int amdgpu_param_buf_per_se; extern int amdgpu_job_hang_limit; extern int amdgpu_lbpw; extern int amdgpu_compute_multipipe; +extern int amdgpu_gpu_recovery; #ifdef CONFIG_DRM_AMDGPU_SI extern int amdgpu_si_support; @@ -1910,7 +1911,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) /* Common functions */ -int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job); +int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job, bool force); bool amdgpu_need_backup(struct amdgpu_device *adev); void amdgpu_pci_config_reset(struct amdgpu_device *adev); bool amdgpu_need_post(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 046b9d5bc14d..3f63f5ca4fa7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3009,11 +3009,12 @@ static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, * * @adev: amdgpu device pointer * @job: which job trigger hang + * @force forces reset regardless of amdgpu_gpu_recovery * * Attempt to reset the GPU if it has hung (all asics). * Returns 0 for success or an error on failure. */ -int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job) +int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job, bool force) { struct drm_atomic_state *state = NULL; uint64_t reset_flags = 0; @@ -3024,6 +3025,12 @@ int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job) return 0; } + if (!force && (amdgpu_gpu_recovery == 0 || + (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev)))) { + DRM_INFO("GPU recovery disabled.\n"); + return 0; + } + dev_info(adev->dev, "GPU reset begin!\n"); mutex_lock(&adev->lock_reset); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 0b039bdcf84e..b734cd668ff1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -128,6 +128,7 @@ int amdgpu_param_buf_per_se = 0; int amdgpu_job_hang_limit = 0; int amdgpu_lbpw = -1; int amdgpu_compute_multipipe = -1; +int amdgpu_gpu_recovery = -1; /* auto */ MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); @@ -280,6 +281,9 @@ module_param_named(lbpw, amdgpu_lbpw, int, 0444); MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); +MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto"); +module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); + #ifdef CONFIG_DRM_AMDGPU_SI #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 7cb71a8e21df..d3ce12149542 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -705,7 +705,7 @@ static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) struct amdgpu_device *adev = dev->dev_private; seq_printf(m, "gpu recover\n"); - amdgpu_gpu_recover(adev, NULL); + amdgpu_gpu_recover(adev, NULL, true); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index c340774082ea..c43643e8c8c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -88,7 +88,7 @@ static void amdgpu_irq_reset_work_func(struct work_struct *work) reset_work); if (!amdgpu_sriov_vf(adev)) - amdgpu_gpu_recover(adev, NULL); + amdgpu_gpu_recover(adev, NULL, false); } /* Disable *all* interrupts */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 013c0a8cfb60..be8a437fad54 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -37,7 +37,7 @@ static void amdgpu_job_timedout(struct drm_sched_job *s_job) atomic_read(&job->ring->fence_drv.last_seq), job->ring->fence_drv.sync_seq); - amdgpu_gpu_recover(job->adev, job); + amdgpu_gpu_recover(job->adev, job, false); } int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index 71f56900d6fe..7ade56d59c27 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -253,7 +253,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) } /* Trigger recovery due to world switch failure */ - amdgpu_gpu_recover(adev, NULL); + amdgpu_gpu_recover(adev, NULL, false); } static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index df52824c0cd4..e05823d86cfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -521,7 +521,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work) } /* Trigger recovery due to world switch failure */ - amdgpu_gpu_recover(adev, NULL); + amdgpu_gpu_recover(adev, NULL, false); } static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev, -- GitLab From 8854695add1eaaeafae728850c905c4727e56f35 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Wed, 13 Dec 2017 14:36:53 -0500 Subject: [PATCH 1620/2547] drm/amdgpu: Simplify amdgpu_lockup_timeout usage. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With introduction of amdgpu_gpu_recovery we don't need any more to rely on amdgpu_lockup_timeout == 0 for disabling GPU reset. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 14 +------------- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 2 +- drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +- 5 files changed, 11 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 3f63f5ca4fa7..79869827985f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1229,6 +1229,11 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) amdgpu_vram_page_split); amdgpu_vram_page_split = 1024; } + + if (amdgpu_lockup_timeout == 0) { + dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n"); + amdgpu_lockup_timeout = 10000; + } } /** @@ -2827,7 +2832,7 @@ bool amdgpu_need_backup(struct amdgpu_device *adev) if (adev->flags & AMD_IS_APU) return false; - return amdgpu_lockup_timeout > 0 ? true : false; + return amdgpu_gpu_recovery; } static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index b734cd668ff1..1fc5499cb5fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -90,7 +90,7 @@ int amdgpu_disp_priority = 0; int amdgpu_hw_i2c = 0; int amdgpu_pcie_gen2 = -1; int amdgpu_msi = -1; -int amdgpu_lockup_timeout = 0; +int amdgpu_lockup_timeout = 10000; int amdgpu_dpm = -1; int amdgpu_fw_load_type = -1; int amdgpu_aspm = -1; @@ -166,7 +166,7 @@ module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); module_param_named(msi, amdgpu_msi, int, 0444); -MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); +MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)"); module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index d3ce12149542..da1510f65ee0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -410,7 +410,6 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, unsigned num_hw_submission) { - long timeout; int r; /* Check that num_hw_submission is a power of two */ @@ -434,20 +433,9 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, /* No need to setup the GPU scheduler for KIQ ring */ if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) { - timeout = msecs_to_jiffies(amdgpu_lockup_timeout); - if (timeout == 0) { - /* - * FIXME: - * Delayed workqueue cannot use it directly, - * so the scheduler will not use delayed workqueue if - * MAX_SCHEDULE_TIMEOUT is set. - * Currently keep it simple and silly. - */ - timeout = MAX_SCHEDULE_TIMEOUT; - } r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, num_hw_submission, amdgpu_job_hang_limit, - timeout, ring->name); + msecs_to_jiffies(amdgpu_lockup_timeout), ring->name); if (r) { DRM_ERROR("Failed to create scheduler on ring %s.\n", ring->name); diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index 7ade56d59c27..43e74ec93147 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -277,7 +277,7 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev, int r; /* trigger gpu-reset by hypervisor only if TDR disbaled */ - if (amdgpu_lockup_timeout == 0) { + if (!amdgpu_gpu_recovery) { /* see what event we get */ r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION); diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index e05823d86cfb..da7c261d5d87 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -545,7 +545,7 @@ static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device *adev, int r; /* trigger gpu-reset by hypervisor only if TDR disbaled */ - if (amdgpu_lockup_timeout == 0) { + if (!amdgpu_gpu_recovery) { /* see what event we get */ r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION); -- GitLab From a7ea6548a5d3e458cd0ad0c41cea04eee64f1fb8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 8 Dec 2017 15:09:20 -0500 Subject: [PATCH 1621/2547] drm/amdgpu: setup the shared and private apertures on gfx9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Same as previous asics. This was not yet set for gfx9. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 17 ++++++++++++----- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 ++++++++ 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index e9a668bae194..9f7be230734c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1529,11 +1529,18 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) for (i = 0; i < 16; i++) { soc15_grbm_select(adev, 0, 0, 0, i); /* CP and shaders */ - tmp = 0; - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, - SH_MEM_ALIGNMENT_MODE_UNALIGNED); - WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); - WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); + if (i == 0) { + tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); + } else { + tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); + tmp = adev->mc.shared_aperture_start >> 48; + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); + } } soc15_grbm_select(adev, 0, 0, 0, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 1b5dfccfd5d5..5da2272bd313 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -499,6 +499,14 @@ static int gmc_v9_0_early_init(void *handle) gmc_v9_0_set_gart_funcs(adev); gmc_v9_0_set_irq_funcs(adev); + adev->mc.shared_aperture_start = 0x2000000000000000ULL; + adev->mc.shared_aperture_end = + adev->mc.shared_aperture_start + (4ULL << 30) - 1; + adev->mc.private_aperture_start = + adev->mc.shared_aperture_end + 1; + adev->mc.private_aperture_end = + adev->mc.private_aperture_start + (4ULL << 30) - 1; + return 0; } -- GitLab From a89ff457d6f6200cd58db568c0138988bb60579c Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Fri, 15 Dec 2017 10:53:43 +0000 Subject: [PATCH 1622/2547] drm/amd/display: remove redundant null check of array 'data' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The null check on aconnector->base.edid_blob_ptr->data is redundant since data is an array and can never be null. Remove it. Detected by CoverityScan, CID#1460369 ("Array compared against 0") Acked-by: Christian König Reviewed-by: Harry Wentland Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8e7621931b92..1cf51bcbbb4a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2725,8 +2725,7 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) }; struct edid *edid; - if (!aconnector->base.edid_blob_ptr || - !aconnector->base.edid_blob_ptr->data) { + if (!aconnector->base.edid_blob_ptr) { DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", aconnector->base.name); -- GitLab From b2162117171864ef48d43cf5d888f3e8012c6c06 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Fri, 24 Nov 2017 17:26:28 -0500 Subject: [PATCH 1623/2547] drm/amd/display: add pipe locking before front end programing Add pipe locking/unlocking before we program the front end Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../display/dc/dce110/dce110_hw_sequencer.c | 26 +++++++++++++++---- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 07ff8d2faf3f..d844fadcd56f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2866,16 +2866,19 @@ static void dce110_apply_ctx_for_surface( int num_planes, struct dc_state *context) { - int i, be_idx; + int i; if (num_planes == 0) return; - be_idx = -1; for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (stream == context->res_ctx.pipe_ctx[i].stream) { - be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst; - break; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (stream == pipe_ctx->stream) { + if (!pipe_ctx->top_pipe && + (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) + dc->hwss.pipe_control_lock(dc, pipe_ctx, true); } } @@ -2895,9 +2898,22 @@ static void dce110_apply_ctx_for_surface( context->stream_count); dce110_program_front_end_for_pipe(dc, pipe_ctx); + + dc->hwss.update_plane_addr(dc, pipe_ctx); + program_surface_visibility(dc, pipe_ctx); } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + if ((stream == pipe_ctx->stream) && + (!pipe_ctx->top_pipe) && + (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) + dc->hwss.pipe_control_lock(dc, pipe_ctx, false); + } } static void dce110_power_down_fe(struct dc *dc, int fe_idx) -- GitLab From 56a9b95c4d3386a98f69f641dd6018886ed2e9d6 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Mon, 13 Nov 2017 17:03:53 -0500 Subject: [PATCH 1624/2547] drm/amd/display: set chroma taps to 1 when not scaling Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 9 +++++++++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 9 ++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 3dce35e66b09..b142629a1058 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -900,6 +900,15 @@ bool dcn_validate_bandwidth( v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c; v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c; + /* + * Spreadsheet doesn't handle taps_c is one properly, + * need to force Chroma to always be scaled to pass + * bandwidth validation. + */ + if (v->override_hta_pschroma[input_idx] == 1) + v->override_hta_pschroma[input_idx] = 2; + if (v->override_vta_pschroma[input_idx] == 1) + v->override_vta_pschroma[input_idx] = 2; v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; } if (v->is_line_buffer_bpp_fixed == dcn_bw_yes) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 74e7c82bdc76..a9d55d0dd69e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -159,11 +159,10 @@ bool dpp_get_optimal_number_of_taps( scl_data->taps.h_taps = 1; if (IDENTITY_RATIO(scl_data->ratios.vert)) scl_data->taps.v_taps = 1; - /* - * Spreadsheet doesn't handle taps_c is one properly, - * need to force Chroma to always be scaled to pass - * bandwidth validation. - */ + if (IDENTITY_RATIO(scl_data->ratios.horz_c)) + scl_data->taps.h_taps_c = 1; + if (IDENTITY_RATIO(scl_data->ratios.vert_c)) + scl_data->taps.v_taps_c = 1; } return true; -- GitLab From 78288503199d0a33b69b972a44a4cf15df989899 Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Fri, 10 Nov 2017 10:44:24 -0500 Subject: [PATCH 1625/2547] drm/amd/display: fix missing pixel clock adjustment for dongle Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Reviewed-by: Andrew Jiang Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index e27ed4a45265..42a111b9505d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1801,7 +1801,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal) link->link_enc->funcs->disable_output(link->link_enc, signal, link); } -bool dp_active_dongle_validate_timing( +static bool dp_active_dongle_validate_timing( const struct dc_crtc_timing *timing, const struct dc_dongle_caps *dongle_caps) { @@ -1833,6 +1833,8 @@ bool dp_active_dongle_validate_timing( /* Check Color Depth and Pixel Clock */ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) required_pix_clk /= 2; + else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) + required_pix_clk = required_pix_clk * 2 / 3; switch (timing->display_color_depth) { case COLOR_DEPTH_666: -- GitLab From becd0875f4393a992afbf57aa323f7bf1a71c3ff Mon Sep 17 00:00:00 2001 From: "Jerry (Fangzhi) Zuo" Date: Fri, 1 Dec 2017 13:26:05 -0500 Subject: [PATCH 1626/2547] drm/amd/display: Fix rehook MST display not light back on Original applied dm_restore_drm_connector_state() has got removed. Set link status to BAD before hotplug() event could trigger another modeset from userspace. The fix "Fix MST daisy chain SST not light up" commit makes so it is trying to create a stream prior to dc_sink. That makes dc_sink is not present in create_stream_for_sink(). Signed-off-by: Jerry (Fangzhi) Zuo Reviewed-by: Roman Li Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 + .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 51 +++++++++++++++++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.h | 1 + 4 files changed, 62 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f71fe6d2ddda..bb5fa895fb64 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2336,7 +2336,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, const struct dm_connector_state *dm_state) { struct drm_display_mode *preferred_mode = NULL; - const struct drm_connector *drm_connector; + struct drm_connector *drm_connector; struct dc_stream_state *stream = NULL; struct drm_display_mode mode = *drm_mode; bool native_mode_found = false; @@ -2355,11 +2355,13 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, if (!aconnector->dc_sink) { /* - * Exclude MST from creating fake_sink - * TODO: need to enable MST into fake_sink feature + * Create dc_sink when necessary to MST + * Don't apply fake_sink to MST */ - if (aconnector->mst_port) - goto stream_create_fail; + if (aconnector->mst_port) { + dm_dp_mst_dc_sink_create(drm_connector); + goto mst_dc_sink_create_done; + } if (create_fake_sink(aconnector)) goto stream_create_fail; @@ -2410,6 +2412,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, stream_create_fail: dm_state_null: drm_connector_null: +mst_dc_sink_create_done: return stream; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 117521c6a6ed..0230250a1164 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -189,6 +189,8 @@ struct amdgpu_dm_connector { struct mutex hpd_lock; bool fake_enable; + + bool mst_connected; }; #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index f8efb98b1fa7..638c2c2b5cd7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -185,6 +185,42 @@ static int dm_connector_update_modes(struct drm_connector *connector, return ret; } +void dm_dp_mst_dc_sink_create(struct drm_connector *connector) +{ + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + struct edid *edid; + struct dc_sink *dc_sink; + struct dc_sink_init_data init_params = { + .link = aconnector->dc_link, + .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; + + edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port); + + if (!edid) { + drm_mode_connector_update_edid_property( + &aconnector->base, + NULL); + return; + } + + aconnector->edid = edid; + + dc_sink = dc_link_add_remote_sink( + aconnector->dc_link, + (uint8_t *)aconnector->edid, + (aconnector->edid->extensions + 1) * EDID_LENGTH, + &init_params); + + dc_sink->priv = aconnector; + aconnector->dc_sink = dc_sink; + + amdgpu_dm_add_sink_to_freesync_module( + connector, aconnector->edid); + + drm_mode_connector_update_edid_property( + &aconnector->base, aconnector->edid); +} + static int dm_dp_mst_get_modes(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -311,6 +347,7 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, drm_mode_connector_set_path_property(connector, pathprop); drm_connector_list_iter_end(&conn_iter); + aconnector->mst_connected = true; return &aconnector->base; } } @@ -363,6 +400,8 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, */ amdgpu_dm_connector_funcs_reset(connector); + aconnector->mst_connected = true; + DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n", aconnector, connector->base.id, aconnector->mst_port); @@ -394,6 +433,8 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, drm_mode_connector_update_edid_property( &aconnector->base, NULL); + + aconnector->mst_connected = false; } static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) @@ -404,10 +445,18 @@ static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) drm_kms_helper_hotplug_event(dev); } +static void dm_dp_mst_link_status_reset(struct drm_connector *connector) +{ + mutex_lock(&connector->dev->mode_config.mutex); + drm_mode_connector_set_link_status_property(connector, DRM_MODE_LINK_STATUS_BAD); + mutex_unlock(&connector->dev->mode_config.mutex); +} + static void dm_dp_mst_register_connector(struct drm_connector *connector) { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); if (adev->mode_info.rfbdev) drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); @@ -416,6 +465,8 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) drm_connector_register(connector); + if (aconnector->mst_connected) + dm_dp_mst_link_status_reset(connector); } static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h index 2da851b40042..8cf51da26657 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h @@ -31,5 +31,6 @@ struct amdgpu_dm_connector; void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, struct amdgpu_dm_connector *aconnector); +void dm_dp_mst_dc_sink_create(struct drm_connector *connector); #endif -- GitLab From f6f3732162b5ae3c771b9285a5a32d72b8586920 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Fri, 15 Dec 2017 18:53:22 -0800 Subject: [PATCH 1627/2547] Revert "mm: replace p??_write with pte_access_permitted in fault + gup paths" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commits 5c9d2d5c269c, c7da82b894e9, and e7fe7b5cae90. We'll probably need to revisit this, but basically we should not complicate the get_user_pages_fast() case, and checking the actual page table protection key bits will require more care anyway, since the protection keys depend on the exact state of the VM in question. Particularly when doing a "remote" page lookup (ie in somebody elses VM, not your own), you need to be much more careful than this was. Dave Hansen says: "So, the underlying bug here is that we now a get_user_pages_remote() and then go ahead and do the p*_access_permitted() checks against the current PKRU. This was introduced recently with the addition of the new p??_access_permitted() calls. We have checks in the VMA path for the "remote" gups and we avoid consulting PKRU for them. This got missed in the pkeys selftests because I did a ptrace read, but not a *write*. I also didn't explicitly test it against something where a COW needed to be done" It's also not entirely clear that it makes sense to check the protection key bits at this level at all. But one possible eventual solution is to make the get_user_pages_fast() case just abort if it sees protection key bits set, which makes us fall back to the regular get_user_pages() case, which then has a vma and can do the check there if we want to. We'll see. Somewhat related to this all: what we _do_ want to do some day is to check the PAGE_USER bit - it should obviously always be set for user pages, but it would be a good check to have back. Because we have no generic way to test for it, we lost it as part of moving over from the architecture-specific x86 GUP implementation to the generic one in commit e585513b76f7 ("x86/mm/gup: Switch GUP to the generic get_user_page_fast() implementation"). Cc: Peter Zijlstra Cc: Dan Williams Cc: Dave Hansen Cc: Kirill A. Shutemov Cc: "Jérôme Glisse" Cc: Andrew Morton Cc: Al Viro Signed-off-by: Linus Torvalds --- arch/s390/include/asm/pgtable.h | 6 ------ arch/sparc/mm/gup.c | 4 ++-- fs/dax.c | 3 +-- mm/gup.c | 2 +- mm/hmm.c | 8 ++++---- mm/huge_memory.c | 6 +++--- mm/memory.c | 8 ++++---- 7 files changed, 15 insertions(+), 22 deletions(-) diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index 57d7bc92e0b8..0a6b0286c32e 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -1264,12 +1264,6 @@ static inline pud_t pud_mkwrite(pud_t pud) return pud; } -#define pud_write pud_write -static inline int pud_write(pud_t pud) -{ - return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; -} - static inline pud_t pud_mkclean(pud_t pud) { if (pud_large(pud)) { diff --git a/arch/sparc/mm/gup.c b/arch/sparc/mm/gup.c index 33c0f8bb0f33..5335ba3c850e 100644 --- a/arch/sparc/mm/gup.c +++ b/arch/sparc/mm/gup.c @@ -75,7 +75,7 @@ static int gup_huge_pmd(pmd_t *pmdp, pmd_t pmd, unsigned long addr, if (!(pmd_val(pmd) & _PAGE_VALID)) return 0; - if (!pmd_access_permitted(pmd, write)) + if (write && !pmd_write(pmd)) return 0; refs = 0; @@ -114,7 +114,7 @@ static int gup_huge_pud(pud_t *pudp, pud_t pud, unsigned long addr, if (!(pud_val(pud) & _PAGE_VALID)) return 0; - if (!pud_access_permitted(pud, write)) + if (write && !pud_write(pud)) return 0; refs = 0; diff --git a/fs/dax.c b/fs/dax.c index 78b72c48374e..95981591977a 100644 --- a/fs/dax.c +++ b/fs/dax.c @@ -627,8 +627,7 @@ static void dax_mapping_entry_mkclean(struct address_space *mapping, if (pfn != pmd_pfn(*pmdp)) goto unlock_pmd; - if (!pmd_dirty(*pmdp) - && !pmd_access_permitted(*pmdp, WRITE)) + if (!pmd_dirty(*pmdp) && !pmd_write(*pmdp)) goto unlock_pmd; flush_cache_page(vma, address, pfn); diff --git a/mm/gup.c b/mm/gup.c index d3fb60e5bfac..e0d82b6706d7 100644 --- a/mm/gup.c +++ b/mm/gup.c @@ -66,7 +66,7 @@ static int follow_pfn_pte(struct vm_area_struct *vma, unsigned long address, */ static inline bool can_follow_write_pte(pte_t pte, unsigned int flags) { - return pte_access_permitted(pte, WRITE) || + return pte_write(pte) || ((flags & FOLL_FORCE) && (flags & FOLL_COW) && pte_dirty(pte)); } diff --git a/mm/hmm.c b/mm/hmm.c index 3a5c172af560..ea19742a5d60 100644 --- a/mm/hmm.c +++ b/mm/hmm.c @@ -391,11 +391,11 @@ static int hmm_vma_walk_pmd(pmd_t *pmdp, if (pmd_protnone(pmd)) return hmm_vma_walk_clear(start, end, walk); - if (!pmd_access_permitted(pmd, write_fault)) + if (write_fault && !pmd_write(pmd)) return hmm_vma_walk_clear(start, end, walk); pfn = pmd_pfn(pmd) + pte_index(addr); - flag |= pmd_access_permitted(pmd, WRITE) ? HMM_PFN_WRITE : 0; + flag |= pmd_write(pmd) ? HMM_PFN_WRITE : 0; for (; addr < end; addr += PAGE_SIZE, i++, pfn++) pfns[i] = hmm_pfn_t_from_pfn(pfn) | flag; return 0; @@ -456,11 +456,11 @@ static int hmm_vma_walk_pmd(pmd_t *pmdp, continue; } - if (!pte_access_permitted(pte, write_fault)) + if (write_fault && !pte_write(pte)) goto fault; pfns[i] = hmm_pfn_t_from_pfn(pte_pfn(pte)) | flag; - pfns[i] |= pte_access_permitted(pte, WRITE) ? HMM_PFN_WRITE : 0; + pfns[i] |= pte_write(pte) ? HMM_PFN_WRITE : 0; continue; fault: diff --git a/mm/huge_memory.c b/mm/huge_memory.c index 2f2f5e774902..0e7ded98d114 100644 --- a/mm/huge_memory.c +++ b/mm/huge_memory.c @@ -870,7 +870,7 @@ struct page *follow_devmap_pmd(struct vm_area_struct *vma, unsigned long addr, */ WARN_ONCE(flags & FOLL_COW, "mm: In follow_devmap_pmd with FOLL_COW set"); - if (!pmd_access_permitted(*pmd, flags & FOLL_WRITE)) + if (flags & FOLL_WRITE && !pmd_write(*pmd)) return NULL; if (pmd_present(*pmd) && pmd_devmap(*pmd)) @@ -1012,7 +1012,7 @@ struct page *follow_devmap_pud(struct vm_area_struct *vma, unsigned long addr, assert_spin_locked(pud_lockptr(mm, pud)); - if (!pud_access_permitted(*pud, flags & FOLL_WRITE)) + if (flags & FOLL_WRITE && !pud_write(*pud)) return NULL; if (pud_present(*pud) && pud_devmap(*pud)) @@ -1386,7 +1386,7 @@ int do_huge_pmd_wp_page(struct vm_fault *vmf, pmd_t orig_pmd) */ static inline bool can_follow_write_pmd(pmd_t pmd, unsigned int flags) { - return pmd_access_permitted(pmd, WRITE) || + return pmd_write(pmd) || ((flags & FOLL_FORCE) && (flags & FOLL_COW) && pmd_dirty(pmd)); } diff --git a/mm/memory.c b/mm/memory.c index cfaba6287702..ca5674cbaff2 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -3949,7 +3949,7 @@ static int handle_pte_fault(struct vm_fault *vmf) if (unlikely(!pte_same(*vmf->pte, entry))) goto unlock; if (vmf->flags & FAULT_FLAG_WRITE) { - if (!pte_access_permitted(entry, WRITE)) + if (!pte_write(entry)) return do_wp_page(vmf); entry = pte_mkdirty(entry); } @@ -4014,7 +4014,7 @@ static int __handle_mm_fault(struct vm_area_struct *vma, unsigned long address, /* NUMA case for anonymous PUDs would go here */ - if (dirty && !pud_access_permitted(orig_pud, WRITE)) { + if (dirty && !pud_write(orig_pud)) { ret = wp_huge_pud(&vmf, orig_pud); if (!(ret & VM_FAULT_FALLBACK)) return ret; @@ -4047,7 +4047,7 @@ static int __handle_mm_fault(struct vm_area_struct *vma, unsigned long address, if (pmd_protnone(orig_pmd) && vma_is_accessible(vma)) return do_huge_pmd_numa_page(&vmf, orig_pmd); - if (dirty && !pmd_access_permitted(orig_pmd, WRITE)) { + if (dirty && !pmd_write(orig_pmd)) { ret = wp_huge_pmd(&vmf, orig_pmd); if (!(ret & VM_FAULT_FALLBACK)) return ret; @@ -4337,7 +4337,7 @@ int follow_phys(struct vm_area_struct *vma, goto out; pte = *ptep; - if (!pte_access_permitted(pte, flags & FOLL_WRITE)) + if ((flags & FOLL_WRITE) && !pte_write(pte)) goto unlock; *prot = pgprot_val(pte_pgprot(pte)); -- GitLab From f6ba181ada5572304c29cff44f04c15fa295f547 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 16 Dec 2017 00:22:06 +0000 Subject: [PATCH 1628/2547] drm/i915: Skip an engine reset if it recovered before our preparations At the beginning of a reset, we disable the submission method and find the stuck request. We expect to find a stuck request for we have declared the engine stalled. However, if we find no active request, the engine must have recovered from its stall before we could issue a reset, so let the engine continue on without a reset. If the engine is truly stuck, we will back soon enough with the next reset attempt. v2: Remove the stale debug message. Signed-off-by: Chris Wilson Cc: Michel Thierry Cc: Mika Kuoppala Reviewed-by: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20171216002206.31737-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_drv.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ca9f4b2862eb..6d39fdf2b604 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -2011,19 +2011,19 @@ int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags) GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags)); + active_request = i915_gem_reset_prepare_engine(engine); + if (IS_ERR_OR_NULL(active_request)) { + /* Either the previous reset failed, or we pardon the reset. */ + ret = PTR_ERR(active_request); + goto out; + } + if (!(flags & I915_RESET_QUIET)) { dev_notice(engine->i915->drm.dev, "Resetting %s after gpu hang\n", engine->name); } error->reset_engine_count[engine->id]++; - active_request = i915_gem_reset_prepare_engine(engine); - if (IS_ERR(active_request)) { - DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n"); - ret = PTR_ERR(active_request); - goto out; - } - if (!engine->i915->guc.execbuf_client) ret = intel_gt_reset_engine(engine->i915, engine); else -- GitLab From 7b6da818d86fddfc88ddb523d6539c1bf7fc6302 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 16 Dec 2017 00:03:34 +0000 Subject: [PATCH 1629/2547] drm/i915: Restore the kernel context after a GPU reset on an idle engine As part of the system requirement for powersaving is that we always have a context loaded. Upon boot and resume, we load the kernel_context to ensure that some valid state is set before powersaving kicks in, we should do so after a full GPU reset as well. We only need to do so for an idle engine, as any active engines will restart by executing the stuck request, loading its context. For the idle engine, we create a new request to load the kernel_context instead. For whatever reason, perfoming a dummy execute on the idle engine after reset papers over a subsequent GPU hang in rare circumstances, even on machines not using contexts (e.g. Pineview). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104259 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104261 Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Reviewed-by: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20171216000334.8197-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 4a7f5579a7a5..dca15c13af35 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3119,6 +3119,25 @@ void i915_gem_reset(struct drm_i915_private *dev_priv) ctx = fetch_and_zero(&engine->last_retired_context); if (ctx) engine->context_unpin(engine, ctx); + + /* + * Ostensibily, we always want a context loaded for powersaving, + * so if the engine is idle after the reset, send a request + * to load our scratch kernel_context. + * + * More mysteriously, if we leave the engine idle after a reset, + * the next userspace batch may hang, with what appears to be + * an incoherent read by the CS (presumably stale TLB). An + * empty request appears sufficient to paper over the glitch. + */ + if (list_empty(&engine->timeline->requests)) { + struct drm_i915_gem_request *rq; + + rq = i915_gem_request_alloc(engine, + dev_priv->kernel_context); + if (!IS_ERR(rq)) + __i915_add_request(rq, false); + } } i915_gem_restore_fences(dev_priv); -- GitLab From 5f0e3fe6b1504d4e6530294ec87c473aa6d2d02f Mon Sep 17 00:00:00 2001 From: Matthew Wilcox Date: Tue, 14 Nov 2017 09:10:11 -0500 Subject: [PATCH 1630/2547] x86/build: Make isoimage work on Debian Debian does not ship a 'mkisofs' symlink to genisoimage. All modern distros ship genisoimage, so just use that directly. That requires renaming the 'genisoimage' function. Also neaten up the 'for' loop while I'm in here. Signed-off-by: Matthew Wilcox Cc: Changbin Du Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/x86/boot/genimage.sh | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/x86/boot/genimage.sh b/arch/x86/boot/genimage.sh index c9e8499fbfe7..6a10d52a4145 100644 --- a/arch/x86/boot/genimage.sh +++ b/arch/x86/boot/genimage.sh @@ -80,39 +80,43 @@ genfdimage288() { mcopy $FBZIMAGE w:linux } -genisoimage() { +geniso() { tmp_dir=`dirname $FIMAGE`/isoimage rm -rf $tmp_dir mkdir $tmp_dir - for i in lib lib64 share end ; do + for i in lib lib64 share ; do for j in syslinux ISOLINUX ; do if [ -f /usr/$i/$j/isolinux.bin ] ; then isolinux=/usr/$i/$j/isolinux.bin - cp $isolinux $tmp_dir fi done for j in syslinux syslinux/modules/bios ; do if [ -f /usr/$i/$j/ldlinux.c32 ]; then ldlinux=/usr/$i/$j/ldlinux.c32 - cp $ldlinux $tmp_dir fi done if [ -n "$isolinux" -a -n "$ldlinux" ] ; then break fi - if [ $i = end -a -z "$isolinux" ] ; then - echo 'Need an isolinux.bin file, please install syslinux/isolinux.' - exit 1 - fi done + if [ -z "$isolinux" ] ; then + echo 'Need an isolinux.bin file, please install syslinux/isolinux.' + exit 1 + fi + if [ -z "$ldlinux" ] ; then + echo 'Need an ldlinux.c32 file, please install syslinux/isolinux.' + exit 1 + fi + cp $isolinux $tmp_dir + cp $ldlinux $tmp_dir cp $FBZIMAGE $tmp_dir/linux echo "$KCMDLINE" > $tmp_dir/isolinux.cfg if [ -f "$FDINITRD" ] ; then cp "$FDINITRD" $tmp_dir/initrd.img fi - mkisofs -J -r -input-charset=utf-8 -quiet -o $FIMAGE -b isolinux.bin \ - -c boot.cat -no-emul-boot -boot-load-size 4 -boot-info-table \ - $tmp_dir + genisoimage -J -r -input-charset=utf-8 -quiet -o $FIMAGE \ + -b isolinux.bin -c boot.cat -no-emul-boot -boot-load-size 4 \ + -boot-info-table $tmp_dir isohybrid $FIMAGE 2>/dev/null || true rm -rf $tmp_dir } @@ -121,6 +125,6 @@ case $1 in bzdisk) genbzdisk;; fdimage144) genfdimage144;; fdimage288) genfdimage288;; - isoimage) genisoimage;; + isoimage) geniso;; *) echo 'Unknown image format'; exit 1; esac -- GitLab From cce1fea50e3be6b78fc677e8cf20cd0ca4c851b0 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 1 Dec 2017 15:08:03 +0300 Subject: [PATCH 1631/2547] thunderbolt: Make pathname to force_power shorter WMI is the bus inside kernel, so, we may access the GUID via /sys/bus/wmi instead of doing this through /sys/devices path. Signed-off-by: Andy Shevchenko Acked-by: Mario Limonciello Signed-off-by: Mika Westerberg Signed-off-by: Greg Kroah-Hartman --- Documentation/admin-guide/thunderbolt.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/admin-guide/thunderbolt.rst b/Documentation/admin-guide/thunderbolt.rst index de50a8561774..9b55952039a6 100644 --- a/Documentation/admin-guide/thunderbolt.rst +++ b/Documentation/admin-guide/thunderbolt.rst @@ -230,7 +230,7 @@ If supported by your machine this will be exposed by the WMI bus with a sysfs attribute called "force_power". For example the intel-wmi-thunderbolt driver exposes this attribute in: - /sys/devices/platform/PNP0C14:00/wmi_bus/wmi_bus-PNP0C14:00/86CCFD48-205E-4A77-9C48-2021CBEDE341/force_power + /sys/bus/wmi/devices/86CCFD48-205E-4A77-9C48-2021CBEDE341/force_power To force the power to on, write 1 to this attribute file. To disable force power, write 0 to this attribute file. -- GitLab From 78dfa29c84bab548910490cf7508c53ad99d1d9e Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Fri, 1 Dec 2017 15:08:04 +0300 Subject: [PATCH 1632/2547] MAINTAINERS: Add thunderbolt.rst to the Thunderbolt driver entry Make sure Thunderbolt maintainers get to see patches that touch documentation of the Thunderbolt driver as well. Signed-off-by: Mika Westerberg Signed-off-by: Greg Kroah-Hartman --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 82ad0eabce4f..5da966e19e8a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13492,6 +13492,7 @@ M: Mika Westerberg M: Yehezkel Bernat T: git git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt.git S: Maintained +F: Documentation/admin-guide/thunderbolt.rst F: drivers/thunderbolt/ F: include/linux/thunderbolt.h -- GitLab From 74657181e7c449351d1ad28cf43941bc333e1bd6 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Fri, 1 Dec 2017 15:08:05 +0300 Subject: [PATCH 1633/2547] thunderbolt: Mask ring interrupt properly when polling starts When ring enters polling mode we are expected to mask the ring interrupt before the callback is called. However, the current code actually unmasks it probably because of a copy-paste mistake. Mask the interrupt properly from now on. Fixes: 4ffe722eefcb ("thunderbolt: Add polling mode for rings") Signed-off-by: Mika Westerberg Acked-by: Yehezkel Bernat Signed-off-by: Greg Kroah-Hartman --- drivers/thunderbolt/nhi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index 419a7a90bce0..f45bcbc63738 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -339,7 +339,7 @@ static void __ring_interrupt(struct tb_ring *ring) return; if (ring->start_poll) { - __ring_interrupt_mask(ring, false); + __ring_interrupt_mask(ring, true); ring->start_poll(ring->poll_data); } else { schedule_work(&ring->work); -- GitLab From 588753f1eb18978512b1c9b85fddb457d46f9033 Mon Sep 17 00:00:00 2001 From: Brendan McGrath Date: Wed, 13 Dec 2017 22:14:57 +1100 Subject: [PATCH 1634/2547] ipv6: icmp6: Allow icmp messages to be looped back One example of when an ICMPv6 packet is required to be looped back is when a host acts as both a Multicast Listener and a Multicast Router. A Multicast Router will listen on address ff02::16 for MLDv2 messages. Currently, MLDv2 messages originating from a Multicast Listener running on the same host as the Multicast Router are not being delivered to the Multicast Router. This is due to dst.input being assigned the default value of dst_discard. This results in the packet being looped back but discarded before being delivered to the Multicast Router. This patch sets dst.input to ip6_input to ensure a looped back packet is delivered to the Multicast Router. Signed-off-by: Brendan McGrath Signed-off-by: David S. Miller --- net/ipv6/route.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/ipv6/route.c b/net/ipv6/route.c index 7a8d1500d374..2bc91c349273 100644 --- a/net/ipv6/route.c +++ b/net/ipv6/route.c @@ -2336,6 +2336,7 @@ struct dst_entry *icmp6_dst_alloc(struct net_device *dev, } rt->dst.flags |= DST_HOST; + rt->dst.input = ip6_input; rt->dst.output = ip6_output; rt->rt6i_gateway = fl6->daddr; rt->rt6i_dst.addr = fl6->daddr; -- GitLab From f870c1ff65a6d1f3a083f277280802ee09a5b44d Mon Sep 17 00:00:00 2001 From: Alexey Kodanev Date: Thu, 14 Dec 2017 20:20:00 +0300 Subject: [PATCH 1635/2547] vxlan: restore dev->mtu setting based on lower device Stefano Brivio says: Commit a985343ba906 ("vxlan: refactor verification and application of configuration") introduced a change in the behaviour of initial MTU setting: earlier, the MTU for a link created on top of a given lower device, without an initial MTU specification, was set to the MTU of the lower device minus headroom as a result of this path in vxlan_dev_configure(): if (!conf->mtu) dev->mtu = lowerdev->mtu - (use_ipv6 ? VXLAN6_HEADROOM : VXLAN_HEADROOM); which is now gone. Now, the initial MTU, in absence of a configured value, is simply set by ether_setup() to ETH_DATA_LEN (1500 bytes). This breaks userspace expectations in case the MTU of the lower device is higher than 1500 bytes minus headroom. This patch restores the previous behaviour on newlink operation. Since max_mtu can be negative and we update dev->mtu directly, also check it for valid minimum. Reported-by: Junhan Yan Fixes: a985343ba906 ("vxlan: refactor verification and application of configuration") Signed-off-by: Alexey Kodanev Acked-by: Stefano Brivio Signed-off-by: Stefano Brivio Signed-off-by: David S. Miller --- drivers/net/vxlan.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/vxlan.c b/drivers/net/vxlan.c index 19b9cc51079e..1000b0e4ee01 100644 --- a/drivers/net/vxlan.c +++ b/drivers/net/vxlan.c @@ -3103,6 +3103,11 @@ static void vxlan_config_apply(struct net_device *dev, max_mtu = lowerdev->mtu - (use_ipv6 ? VXLAN6_HEADROOM : VXLAN_HEADROOM); + if (max_mtu < ETH_MIN_MTU) + max_mtu = ETH_MIN_MTU; + + if (!changelink && !conf->mtu) + dev->mtu = max_mtu; } if (dev->mtu > max_mtu) -- GitLab From 1784f9144b143a1e8b19fe94083b040aa559182b Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Tue, 5 Dec 2017 14:14:47 +0100 Subject: [PATCH 1636/2547] drivers/misc/intel/pti: Rename the header file to free up the namespace We'd like to use the 'PTI' acronym for 'Page Table Isolation' - free up the namespace by renaming the driver header to . (Also standardize the header guard name while at it.) Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: J Freyensee Cc: Greg Kroah-Hartman Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- drivers/misc/pti.c | 2 +- include/linux/{pti.h => intel-pti.h} | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) rename include/linux/{pti.h => intel-pti.h} (94%) diff --git a/drivers/misc/pti.c b/drivers/misc/pti.c index eda38cbe8530..41f2a9f6851d 100644 --- a/drivers/misc/pti.c +++ b/drivers/misc/pti.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include diff --git a/include/linux/pti.h b/include/linux/intel-pti.h similarity index 94% rename from include/linux/pti.h rename to include/linux/intel-pti.h index b3ea01a3197e..2710d72de3c9 100644 --- a/include/linux/pti.h +++ b/include/linux/intel-pti.h @@ -22,8 +22,8 @@ * interface to write out it's contents for debugging a mobile system. */ -#ifndef PTI_H_ -#define PTI_H_ +#ifndef LINUX_INTEL_PTI_H_ +#define LINUX_INTEL_PTI_H_ /* offset for last dword of any PTI message. Part of MIPI P1149.7 */ #define PTI_LASTDWORD_DTS 0x30 @@ -40,4 +40,4 @@ struct pti_masterchannel *pti_request_masterchannel(u8 type, const char *thread_name); void pti_release_masterchannel(struct pti_masterchannel *mc); -#endif /*PTI_H_*/ +#endif /* LINUX_INTEL_PTI_H_ */ -- GitLab From a8b4db562e7283a1520f9e9730297ecaab7622ea Mon Sep 17 00:00:00 2001 From: Ricardo Neri Date: Sun, 5 Nov 2017 18:27:51 -0800 Subject: [PATCH 1637/2547] x86/cpufeature: Add User-Mode Instruction Prevention definitions [ Note, this is a Git cherry-pick of the following commit: (limited to the cpufeatures.h file) 3522c2a6a4f3 ("x86/cpufeature: Add User-Mode Instruction Prevention definitions") ... for easier x86 PTI code testing and back-porting. ] User-Mode Instruction Prevention is a security feature present in new Intel processors that, when set, prevents the execution of a subset of instructions if such instructions are executed in user mode (CPL > 0). Attempting to execute such instructions causes a general protection exception. The subset of instructions comprises: * SGDT - Store Global Descriptor Table * SIDT - Store Interrupt Descriptor Table * SLDT - Store Local Descriptor Table * SMSW - Store Machine Status Word * STR - Store Task Register This feature is also added to the list of disabled-features to allow a cleaner handling of build-time configuration. Signed-off-by: Ricardo Neri Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Andrew Morton Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Brian Gerst Cc: Chen Yucong Cc: Chris Metcalf Cc: Dave Hansen Cc: Denys Vlasenko Cc: Fenghua Yu Cc: H. Peter Anvin Cc: Huang Rui Cc: Jiri Slaby Cc: Jonathan Corbet Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Masami Hiramatsu Cc: Michael S. Tsirkin Cc: Paolo Bonzini Cc: Paul Gortmaker Cc: Peter Zijlstra Cc: Ravi V. Shankar Cc: Shuah Khan Cc: Tony Luck Cc: Vlastimil Babka Cc: ricardo.neri@intel.com Link: http://lkml.kernel.org/r/1509935277-22138-7-git-send-email-ricardo.neri-calderon@linux.intel.com Signed-off-by: Ingo Molnar --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index cdf5be866863..c0b0e9e8aa66 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -296,6 +296,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ +#define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ -- GitLab From f2dbad36c55e5d3a91dccbde6e8cae345fe5632f Mon Sep 17 00:00:00 2001 From: Rudolf Marek Date: Tue, 28 Nov 2017 22:01:06 +0100 Subject: [PATCH 1638/2547] x86: Make X86_BUG_FXSAVE_LEAK detectable in CPUID on AMD [ Note, this is a Git cherry-pick of the following commit: 2b67799bdf25 ("x86: Make X86_BUG_FXSAVE_LEAK detectable in CPUID on AMD") ... for easier x86 PTI code testing and back-porting. ] The latest AMD AMD64 Architecture Programmer's Manual adds a CPUID feature XSaveErPtr (CPUID_Fn80000008_EBX[2]). If this feature is set, the FXSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES / FXRSTOR, XRSTOR, XRSTORS always save/restore error pointers, thus making the X86_BUG_FXSAVE_LEAK workaround obsolete on such CPUs. Signed-Off-By: Rudolf Marek Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Tested-by: Borislav Petkov Cc: Andy Lutomirski Link: https://lkml.kernel.org/r/bdcebe90-62c5-1f05-083c-eba7f08b2540@assembler.cz Signed-off-by: Ingo Molnar --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/amd.c | 7 +++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index c0b0e9e8aa66..800104c8a3ed 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -266,6 +266,7 @@ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ +#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index d58184b7cd44..bcb75dc97d44 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -804,8 +804,11 @@ static void init_amd(struct cpuinfo_x86 *c) case 0x17: init_amd_zn(c); break; } - /* Enable workaround for FXSAVE leak */ - if (c->x86 >= 6) + /* + * Enable workaround for FXSAVE leak on CPUs + * without a XSaveErPtr feature + */ + if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); cpu_detect_cache_sizes(c); -- GitLab From 2fe1bc1f501d55e5925b4035bcd85781adc76c63 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Thu, 31 Aug 2017 14:46:30 -0700 Subject: [PATCH 1639/2547] perf/x86: Enable free running PEBS for REGS_USER/INTR [ Note, this is a Git cherry-pick of the following commit: a47ba4d77e12 ("perf/x86: Enable free running PEBS for REGS_USER/INTR") ... for easier x86 PTI code testing and back-porting. ] Currently free running PEBS is disabled when user or interrupt registers are requested. Most of the registers are actually available in the PEBS record and can be supported. So we just need to check for the supported registers and then allow it: it is all except for the segment register. For user registers this only works when the counter is limited to ring 3 only, so this also needs to be checked. Signed-off-by: Andi Kleen Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/20170831214630.21892-1-andi@firstfloor.org Signed-off-by: Ingo Molnar --- arch/x86/events/intel/core.c | 4 ++++ arch/x86/events/perf_event.h | 24 +++++++++++++++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 9fb9a1f1e47b..43445da30cea 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2958,6 +2958,10 @@ static unsigned long intel_pmu_free_running_flags(struct perf_event *event) if (event->attr.use_clockid) flags &= ~PERF_SAMPLE_TIME; + if (!event->attr.exclude_kernel) + flags &= ~PERF_SAMPLE_REGS_USER; + if (event->attr.sample_regs_user & ~PEBS_REGS) + flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); return flags; } diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 4196f81ec0e1..f7aaadf9331f 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -85,13 +85,15 @@ struct amd_nb { * Flags PEBS can handle without an PMI. * * TID can only be handled by flushing at context switch. + * REGS_USER can be handled for events limited to ring 3. * */ #define PEBS_FREERUNNING_FLAGS \ (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ - PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR) + PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ + PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER) /* * A debug store configuration. @@ -110,6 +112,26 @@ struct debug_store { u64 pebs_event_reset[MAX_PEBS_EVENTS]; }; +#define PEBS_REGS \ + (PERF_REG_X86_AX | \ + PERF_REG_X86_BX | \ + PERF_REG_X86_CX | \ + PERF_REG_X86_DX | \ + PERF_REG_X86_DI | \ + PERF_REG_X86_SI | \ + PERF_REG_X86_SP | \ + PERF_REG_X86_BP | \ + PERF_REG_X86_IP | \ + PERF_REG_X86_FLAGS | \ + PERF_REG_X86_R8 | \ + PERF_REG_X86_R9 | \ + PERF_REG_X86_R10 | \ + PERF_REG_X86_R11 | \ + PERF_REG_X86_R12 | \ + PERF_REG_X86_R13 | \ + PERF_REG_X86_R14 | \ + PERF_REG_X86_R15) + /* * Per register state. */ -- GitLab From ab95477e7cb35557ecfc837687007b646bab9a9f Mon Sep 17 00:00:00 2001 From: Daniel Borkmann Date: Tue, 12 Dec 2017 02:25:31 +0100 Subject: [PATCH 1640/2547] bpf: fix build issues on um due to mising bpf_perf_event.h [ Note, this is a Git cherry-pick of the following commit: a23f06f06dbe ("bpf: fix build issues on um due to mising bpf_perf_event.h") ... for easier x86 PTI code testing and back-porting. ] Since c895f6f703ad ("bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program type") um (uml) won't build on i386 or x86_64: [...] CC init/main.o In file included from ../include/linux/perf_event.h:18:0, from ../include/linux/trace_events.h:10, from ../include/trace/syscall.h:7, from ../include/linux/syscalls.h:82, from ../init/main.c:20: ../include/uapi/linux/bpf_perf_event.h:11:32: fatal error: asm/bpf_perf_event.h: No such file or directory #include [...] Lets add missing bpf_perf_event.h also to um arch. This seems to be the only one still missing. Fixes: c895f6f703ad ("bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program type") Reported-by: Randy Dunlap Suggested-by: Richard Weinberger Signed-off-by: Daniel Borkmann Tested-by: Randy Dunlap Cc: Hendrik Brueckner Cc: Richard Weinberger Acked-by: Alexei Starovoitov Acked-by: Richard Weinberger Signed-off-by: Alexei Starovoitov Signed-off-by: Ingo Molnar --- arch/um/include/asm/Kbuild | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/um/include/asm/Kbuild b/arch/um/include/asm/Kbuild index 50a32c33d729..73c57f614c9e 100644 --- a/arch/um/include/asm/Kbuild +++ b/arch/um/include/asm/Kbuild @@ -1,4 +1,5 @@ generic-y += barrier.h +generic-y += bpf_perf_event.h generic-y += bug.h generic-y += clkdev.h generic-y += current.h -- GitLab From c2bc66082e1048c7573d72e62f597bdc5ce13fea Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 24 Oct 2017 11:22:47 +0100 Subject: [PATCH 1641/2547] locking/barriers: Add implicit smp_read_barrier_depends() to READ_ONCE() [ Note, this is a Git cherry-pick of the following commit: 76ebbe78f739 ("locking/barriers: Add implicit smp_read_barrier_depends() to READ_ONCE()") ... for easier x86 PTI code testing and back-porting. ] In preparation for the removal of lockless_dereference(), which is the same as READ_ONCE() on all architectures other than Alpha, add an implicit smp_read_barrier_depends() to READ_ONCE() so that it can be used to head dependency chains on all architectures. Signed-off-by: Will Deacon Cc: Linus Torvalds Cc: Paul E. McKenney Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/1508840570-22169-3-git-send-email-will.deacon@arm.com Signed-off-by: Ingo Molnar --- include/linux/compiler.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/compiler.h b/include/linux/compiler.h index 202710420d6d..712cd8bb00b4 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -341,6 +341,7 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s __read_once_size(&(x), __u.__c, sizeof(x)); \ else \ __read_once_size_nocheck(&(x), __u.__c, sizeof(x)); \ + smp_read_barrier_depends(); /* Enforce dependency ordering from x */ \ __u.__val; \ }) #define READ_ONCE(x) __READ_ONCE(x, 1) -- GitLab From 3382290ed2d5e275429cef510ab21889d3ccd164 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 24 Oct 2017 11:22:48 +0100 Subject: [PATCH 1642/2547] locking/barriers: Convert users of lockless_dereference() to READ_ONCE() [ Note, this is a Git cherry-pick of the following commit: 506458efaf15 ("locking/barriers: Convert users of lockless_dereference() to READ_ONCE()") ... for easier x86 PTI code testing and back-porting. ] READ_ONCE() now has an implicit smp_read_barrier_depends() call, so it can be used instead of lockless_dereference() without any change in semantics. Signed-off-by: Will Deacon Cc: Linus Torvalds Cc: Paul E. McKenney Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/1508840570-22169-4-git-send-email-will.deacon@arm.com Signed-off-by: Ingo Molnar --- arch/x86/events/core.c | 2 +- arch/x86/include/asm/mmu_context.h | 4 ++-- arch/x86/kernel/ldt.c | 2 +- drivers/md/dm-mpath.c | 20 ++++++++++---------- fs/dcache.c | 4 ++-- fs/overlayfs/ovl_entry.h | 2 +- fs/overlayfs/readdir.c | 2 +- include/linux/rculist.h | 4 ++-- include/linux/rcupdate.h | 4 ++-- kernel/events/core.c | 4 ++-- kernel/seccomp.c | 2 +- kernel/task_work.c | 2 +- mm/slab.h | 2 +- 13 files changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 80534d3c2480..589af1eec7c1 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2371,7 +2371,7 @@ static unsigned long get_segment_base(unsigned int segment) struct ldt_struct *ldt; /* IRQs are off, so this synchronizes with smp_store_release */ - ldt = lockless_dereference(current->active_mm->context.ldt); + ldt = READ_ONCE(current->active_mm->context.ldt); if (!ldt || idx >= ldt->nr_entries) return 0; diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h index 6699fc441644..6d16d15d09a0 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -73,8 +73,8 @@ static inline void load_mm_ldt(struct mm_struct *mm) #ifdef CONFIG_MODIFY_LDT_SYSCALL struct ldt_struct *ldt; - /* lockless_dereference synchronizes with smp_store_release */ - ldt = lockless_dereference(mm->context.ldt); + /* READ_ONCE synchronizes with smp_store_release */ + ldt = READ_ONCE(mm->context.ldt); /* * Any change to mm->context.ldt is followed by an IPI to all diff --git a/arch/x86/kernel/ldt.c b/arch/x86/kernel/ldt.c index ae5615b03def..1c1eae961340 100644 --- a/arch/x86/kernel/ldt.c +++ b/arch/x86/kernel/ldt.c @@ -103,7 +103,7 @@ static void finalize_ldt_struct(struct ldt_struct *ldt) static void install_ldt(struct mm_struct *current_mm, struct ldt_struct *ldt) { - /* Synchronizes with lockless_dereference in load_mm_ldt. */ + /* Synchronizes with READ_ONCE in load_mm_ldt. */ smp_store_release(¤t_mm->context.ldt, ldt); /* Activate the LDT for all CPUs using current_mm. */ diff --git a/drivers/md/dm-mpath.c b/drivers/md/dm-mpath.c index 11f273d2f018..3f88c9d32f7e 100644 --- a/drivers/md/dm-mpath.c +++ b/drivers/md/dm-mpath.c @@ -366,7 +366,7 @@ static struct pgpath *choose_path_in_pg(struct multipath *m, pgpath = path_to_pgpath(path); - if (unlikely(lockless_dereference(m->current_pg) != pg)) { + if (unlikely(READ_ONCE(m->current_pg) != pg)) { /* Only update current_pgpath if pg changed */ spin_lock_irqsave(&m->lock, flags); m->current_pgpath = pgpath; @@ -390,7 +390,7 @@ static struct pgpath *choose_pgpath(struct multipath *m, size_t nr_bytes) } /* Were we instructed to switch PG? */ - if (lockless_dereference(m->next_pg)) { + if (READ_ONCE(m->next_pg)) { spin_lock_irqsave(&m->lock, flags); pg = m->next_pg; if (!pg) { @@ -406,7 +406,7 @@ static struct pgpath *choose_pgpath(struct multipath *m, size_t nr_bytes) /* Don't change PG until it has no remaining paths */ check_current_pg: - pg = lockless_dereference(m->current_pg); + pg = READ_ONCE(m->current_pg); if (pg) { pgpath = choose_path_in_pg(m, pg, nr_bytes); if (!IS_ERR_OR_NULL(pgpath)) @@ -473,7 +473,7 @@ static int multipath_clone_and_map(struct dm_target *ti, struct request *rq, struct request *clone; /* Do we need to select a new pgpath? */ - pgpath = lockless_dereference(m->current_pgpath); + pgpath = READ_ONCE(m->current_pgpath); if (!pgpath || !test_bit(MPATHF_QUEUE_IO, &m->flags)) pgpath = choose_pgpath(m, nr_bytes); @@ -535,7 +535,7 @@ static int __multipath_map_bio(struct multipath *m, struct bio *bio, struct dm_m bool queue_io; /* Do we need to select a new pgpath? */ - pgpath = lockless_dereference(m->current_pgpath); + pgpath = READ_ONCE(m->current_pgpath); queue_io = test_bit(MPATHF_QUEUE_IO, &m->flags); if (!pgpath || !queue_io) pgpath = choose_pgpath(m, nr_bytes); @@ -1804,7 +1804,7 @@ static int multipath_prepare_ioctl(struct dm_target *ti, struct pgpath *current_pgpath; int r; - current_pgpath = lockless_dereference(m->current_pgpath); + current_pgpath = READ_ONCE(m->current_pgpath); if (!current_pgpath) current_pgpath = choose_pgpath(m, 0); @@ -1826,7 +1826,7 @@ static int multipath_prepare_ioctl(struct dm_target *ti, } if (r == -ENOTCONN) { - if (!lockless_dereference(m->current_pg)) { + if (!READ_ONCE(m->current_pg)) { /* Path status changed, redo selection */ (void) choose_pgpath(m, 0); } @@ -1895,9 +1895,9 @@ static int multipath_busy(struct dm_target *ti) return (m->queue_mode != DM_TYPE_MQ_REQUEST_BASED); /* Guess which priority_group will be used at next mapping time */ - pg = lockless_dereference(m->current_pg); - next_pg = lockless_dereference(m->next_pg); - if (unlikely(!lockless_dereference(m->current_pgpath) && next_pg)) + pg = READ_ONCE(m->current_pg); + next_pg = READ_ONCE(m->next_pg); + if (unlikely(!READ_ONCE(m->current_pgpath) && next_pg)) pg = next_pg; if (!pg) { diff --git a/fs/dcache.c b/fs/dcache.c index f90141387f01..34c852af215c 100644 --- a/fs/dcache.c +++ b/fs/dcache.c @@ -231,7 +231,7 @@ static inline int dentry_cmp(const struct dentry *dentry, const unsigned char *c { /* * Be careful about RCU walk racing with rename: - * use 'lockless_dereference' to fetch the name pointer. + * use 'READ_ONCE' to fetch the name pointer. * * NOTE! Even if a rename will mean that the length * was not loaded atomically, we don't care. The @@ -245,7 +245,7 @@ static inline int dentry_cmp(const struct dentry *dentry, const unsigned char *c * early because the data cannot match (there can * be no NUL in the ct/tcount data) */ - const unsigned char *cs = lockless_dereference(dentry->d_name.name); + const unsigned char *cs = READ_ONCE(dentry->d_name.name); return dentry_string_cmp(cs, ct, tcount); } diff --git a/fs/overlayfs/ovl_entry.h b/fs/overlayfs/ovl_entry.h index 25d9b5adcd42..36b49bd09264 100644 --- a/fs/overlayfs/ovl_entry.h +++ b/fs/overlayfs/ovl_entry.h @@ -77,5 +77,5 @@ static inline struct ovl_inode *OVL_I(struct inode *inode) static inline struct dentry *ovl_upperdentry_dereference(struct ovl_inode *oi) { - return lockless_dereference(oi->__upperdentry); + return READ_ONCE(oi->__upperdentry); } diff --git a/fs/overlayfs/readdir.c b/fs/overlayfs/readdir.c index 698b74dd750e..c310e3ff7f3f 100644 --- a/fs/overlayfs/readdir.c +++ b/fs/overlayfs/readdir.c @@ -754,7 +754,7 @@ static int ovl_dir_fsync(struct file *file, loff_t start, loff_t end, if (!od->is_upper && OVL_TYPE_UPPER(ovl_path_type(dentry))) { struct inode *inode = file_inode(file); - realfile = lockless_dereference(od->upperfile); + realfile = READ_ONCE(od->upperfile); if (!realfile) { struct path upperpath; diff --git a/include/linux/rculist.h b/include/linux/rculist.h index c2cdd45a880a..127f534fec94 100644 --- a/include/linux/rculist.h +++ b/include/linux/rculist.h @@ -275,7 +275,7 @@ static inline void list_splice_tail_init_rcu(struct list_head *list, * primitives such as list_add_rcu() as long as it's guarded by rcu_read_lock(). */ #define list_entry_rcu(ptr, type, member) \ - container_of(lockless_dereference(ptr), type, member) + container_of(READ_ONCE(ptr), type, member) /* * Where are list_empty_rcu() and list_first_entry_rcu()? @@ -368,7 +368,7 @@ static inline void list_splice_tail_init_rcu(struct list_head *list, * example is when items are added to the list, but never deleted. */ #define list_entry_lockless(ptr, type, member) \ - container_of((typeof(ptr))lockless_dereference(ptr), type, member) + container_of((typeof(ptr))READ_ONCE(ptr), type, member) /** * list_for_each_entry_lockless - iterate over rcu list of given type diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h index 1a9f70d44af9..a6ddc42f87a5 100644 --- a/include/linux/rcupdate.h +++ b/include/linux/rcupdate.h @@ -346,7 +346,7 @@ static inline void rcu_preempt_sleep_check(void) { } #define __rcu_dereference_check(p, c, space) \ ({ \ /* Dependency order vs. p above. */ \ - typeof(*p) *________p1 = (typeof(*p) *__force)lockless_dereference(p); \ + typeof(*p) *________p1 = (typeof(*p) *__force)READ_ONCE(p); \ RCU_LOCKDEP_WARN(!(c), "suspicious rcu_dereference_check() usage"); \ rcu_dereference_sparse(p, space); \ ((typeof(*p) __force __kernel *)(________p1)); \ @@ -360,7 +360,7 @@ static inline void rcu_preempt_sleep_check(void) { } #define rcu_dereference_raw(p) \ ({ \ /* Dependency order vs. p above. */ \ - typeof(p) ________p1 = lockless_dereference(p); \ + typeof(p) ________p1 = READ_ONCE(p); \ ((typeof(*p) __force __kernel *)(________p1)); \ }) diff --git a/kernel/events/core.c b/kernel/events/core.c index 10cdb9c26b5d..6eee4ed97af0 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -4233,7 +4233,7 @@ static void perf_remove_from_owner(struct perf_event *event) * indeed free this event, otherwise we need to serialize on * owner->perf_event_mutex. */ - owner = lockless_dereference(event->owner); + owner = READ_ONCE(event->owner); if (owner) { /* * Since delayed_put_task_struct() also drops the last @@ -4330,7 +4330,7 @@ int perf_event_release_kernel(struct perf_event *event) * Cannot change, child events are not migrated, see the * comment with perf_event_ctx_lock_nested(). */ - ctx = lockless_dereference(child->ctx); + ctx = READ_ONCE(child->ctx); /* * Since child_mutex nests inside ctx::mutex, we must jump * through hoops. We start by grabbing a reference on the ctx. diff --git a/kernel/seccomp.c b/kernel/seccomp.c index 418a1c045933..5f0dfb2abb8d 100644 --- a/kernel/seccomp.c +++ b/kernel/seccomp.c @@ -190,7 +190,7 @@ static u32 seccomp_run_filters(const struct seccomp_data *sd, u32 ret = SECCOMP_RET_ALLOW; /* Make sure cross-thread synced filter points somewhere sane. */ struct seccomp_filter *f = - lockless_dereference(current->seccomp.filter); + READ_ONCE(current->seccomp.filter); /* Ensure unexpected behavior doesn't result in failing open. */ if (unlikely(WARN_ON(f == NULL))) diff --git a/kernel/task_work.c b/kernel/task_work.c index 5718b3ea202a..0fef395662a6 100644 --- a/kernel/task_work.c +++ b/kernel/task_work.c @@ -68,7 +68,7 @@ task_work_cancel(struct task_struct *task, task_work_func_t func) * we raced with task_work_run(), *pprev == NULL/exited. */ raw_spin_lock_irqsave(&task->pi_lock, flags); - while ((work = lockless_dereference(*pprev))) { + while ((work = READ_ONCE(*pprev))) { if (work->func != func) pprev = &work->next; else if (cmpxchg(pprev, work, work->next) == work) diff --git a/mm/slab.h b/mm/slab.h index 028cdc7df67e..86d7c7d860f9 100644 --- a/mm/slab.h +++ b/mm/slab.h @@ -259,7 +259,7 @@ cache_from_memcg_idx(struct kmem_cache *s, int idx) * memcg_caches issues a write barrier to match this (see * memcg_create_kmem_cache()). */ - cachep = lockless_dereference(arr->entries[idx]); + cachep = READ_ONCE(arr->entries[idx]); rcu_read_unlock(); return cachep; -- GitLab From 2aeb07365bcd489620f71390a7d2031cd4dfb83e Mon Sep 17 00:00:00 2001 From: Andrey Ryabinin Date: Wed, 15 Nov 2017 17:36:35 -0800 Subject: [PATCH 1643/2547] x86/mm/kasan: Don't use vmemmap_populate() to initialize shadow [ Note, this is a Git cherry-pick of the following commit: d17a1d97dc20: ("x86/mm/kasan: don't use vmemmap_populate() to initialize shadow") ... for easier x86 PTI code testing and back-porting. ] The KASAN shadow is currently mapped using vmemmap_populate() since that provides a semi-convenient way to map pages into init_top_pgt. However, since that no longer zeroes the mapped pages, it is not suitable for KASAN, which requires zeroed shadow memory. Add kasan_populate_shadow() interface and use it instead of vmemmap_populate(). Besides, this allows us to take advantage of gigantic pages and use them to populate the shadow, which should save us some memory wasted on page tables and reduce TLB pressure. Link: http://lkml.kernel.org/r/20171103185147.2688-2-pasha.tatashin@oracle.com Signed-off-by: Andrey Ryabinin Signed-off-by: Pavel Tatashin Cc: Andy Lutomirski Cc: Steven Sistare Cc: Daniel Jordan Cc: Bob Picco Cc: Michal Hocko Cc: Alexander Potapenko Cc: Ard Biesheuvel Cc: Catalin Marinas Cc: Christian Borntraeger Cc: David S. Miller Cc: Dmitry Vyukov Cc: Heiko Carstens Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Mark Rutland Cc: Matthew Wilcox Cc: Mel Gorman Cc: Michal Hocko Cc: Sam Ravnborg Cc: Thomas Gleixner Cc: Will Deacon Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Ingo Molnar --- arch/x86/Kconfig | 2 +- arch/x86/mm/kasan_init_64.c | 143 ++++++++++++++++++++++++++++++++++-- 2 files changed, 137 insertions(+), 8 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 4ae940a0ed3b..665eba1b6103 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -108,7 +108,7 @@ config X86 select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_HUGE_VMAP if X86_64 || X86_PAE select HAVE_ARCH_JUMP_LABEL - select HAVE_ARCH_KASAN if X86_64 && SPARSEMEM_VMEMMAP + select HAVE_ARCH_KASAN if X86_64 select HAVE_ARCH_KGDB select HAVE_ARCH_KMEMCHECK select HAVE_ARCH_MMAP_RND_BITS if MMU diff --git a/arch/x86/mm/kasan_init_64.c b/arch/x86/mm/kasan_init_64.c index 2b60dc6e64b1..99dfed6dfef8 100644 --- a/arch/x86/mm/kasan_init_64.c +++ b/arch/x86/mm/kasan_init_64.c @@ -4,12 +4,14 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -18,7 +20,134 @@ extern struct range pfn_mapped[E820_MAX_ENTRIES]; static p4d_t tmp_p4d_table[PTRS_PER_P4D] __initdata __aligned(PAGE_SIZE); -static int __init map_range(struct range *range) +static __init void *early_alloc(size_t size, int nid) +{ + return memblock_virt_alloc_try_nid_nopanic(size, size, + __pa(MAX_DMA_ADDRESS), BOOTMEM_ALLOC_ACCESSIBLE, nid); +} + +static void __init kasan_populate_pmd(pmd_t *pmd, unsigned long addr, + unsigned long end, int nid) +{ + pte_t *pte; + + if (pmd_none(*pmd)) { + void *p; + + if (boot_cpu_has(X86_FEATURE_PSE) && + ((end - addr) == PMD_SIZE) && + IS_ALIGNED(addr, PMD_SIZE)) { + p = early_alloc(PMD_SIZE, nid); + if (p && pmd_set_huge(pmd, __pa(p), PAGE_KERNEL)) + return; + else if (p) + memblock_free(__pa(p), PMD_SIZE); + } + + p = early_alloc(PAGE_SIZE, nid); + pmd_populate_kernel(&init_mm, pmd, p); + } + + pte = pte_offset_kernel(pmd, addr); + do { + pte_t entry; + void *p; + + if (!pte_none(*pte)) + continue; + + p = early_alloc(PAGE_SIZE, nid); + entry = pfn_pte(PFN_DOWN(__pa(p)), PAGE_KERNEL); + set_pte_at(&init_mm, addr, pte, entry); + } while (pte++, addr += PAGE_SIZE, addr != end); +} + +static void __init kasan_populate_pud(pud_t *pud, unsigned long addr, + unsigned long end, int nid) +{ + pmd_t *pmd; + unsigned long next; + + if (pud_none(*pud)) { + void *p; + + if (boot_cpu_has(X86_FEATURE_GBPAGES) && + ((end - addr) == PUD_SIZE) && + IS_ALIGNED(addr, PUD_SIZE)) { + p = early_alloc(PUD_SIZE, nid); + if (p && pud_set_huge(pud, __pa(p), PAGE_KERNEL)) + return; + else if (p) + memblock_free(__pa(p), PUD_SIZE); + } + + p = early_alloc(PAGE_SIZE, nid); + pud_populate(&init_mm, pud, p); + } + + pmd = pmd_offset(pud, addr); + do { + next = pmd_addr_end(addr, end); + if (!pmd_large(*pmd)) + kasan_populate_pmd(pmd, addr, next, nid); + } while (pmd++, addr = next, addr != end); +} + +static void __init kasan_populate_p4d(p4d_t *p4d, unsigned long addr, + unsigned long end, int nid) +{ + pud_t *pud; + unsigned long next; + + if (p4d_none(*p4d)) { + void *p = early_alloc(PAGE_SIZE, nid); + + p4d_populate(&init_mm, p4d, p); + } + + pud = pud_offset(p4d, addr); + do { + next = pud_addr_end(addr, end); + if (!pud_large(*pud)) + kasan_populate_pud(pud, addr, next, nid); + } while (pud++, addr = next, addr != end); +} + +static void __init kasan_populate_pgd(pgd_t *pgd, unsigned long addr, + unsigned long end, int nid) +{ + void *p; + p4d_t *p4d; + unsigned long next; + + if (pgd_none(*pgd)) { + p = early_alloc(PAGE_SIZE, nid); + pgd_populate(&init_mm, pgd, p); + } + + p4d = p4d_offset(pgd, addr); + do { + next = p4d_addr_end(addr, end); + kasan_populate_p4d(p4d, addr, next, nid); + } while (p4d++, addr = next, addr != end); +} + +static void __init kasan_populate_shadow(unsigned long addr, unsigned long end, + int nid) +{ + pgd_t *pgd; + unsigned long next; + + addr = addr & PAGE_MASK; + end = round_up(end, PAGE_SIZE); + pgd = pgd_offset_k(addr); + do { + next = pgd_addr_end(addr, end); + kasan_populate_pgd(pgd, addr, next, nid); + } while (pgd++, addr = next, addr != end); +} + +static void __init map_range(struct range *range) { unsigned long start; unsigned long end; @@ -26,7 +155,7 @@ static int __init map_range(struct range *range) start = (unsigned long)kasan_mem_to_shadow(pfn_to_kaddr(range->start)); end = (unsigned long)kasan_mem_to_shadow(pfn_to_kaddr(range->end)); - return vmemmap_populate(start, end, NUMA_NO_NODE); + kasan_populate_shadow(start, end, early_pfn_to_nid(range->start)); } static void __init clear_pgds(unsigned long start, @@ -189,16 +318,16 @@ void __init kasan_init(void) if (pfn_mapped[i].end == 0) break; - if (map_range(&pfn_mapped[i])) - panic("kasan: unable to allocate shadow!"); + map_range(&pfn_mapped[i]); } + kasan_populate_zero_shadow( kasan_mem_to_shadow((void *)PAGE_OFFSET + MAXMEM), kasan_mem_to_shadow((void *)__START_KERNEL_map)); - vmemmap_populate((unsigned long)kasan_mem_to_shadow(_stext), - (unsigned long)kasan_mem_to_shadow(_end), - NUMA_NO_NODE); + kasan_populate_shadow((unsigned long)kasan_mem_to_shadow(_stext), + (unsigned long)kasan_mem_to_shadow(_end), + early_pfn_to_nid(__pa(_stext))); kasan_populate_zero_shadow(kasan_mem_to_shadow((void *)MODULES_END), (void *)KASAN_SHADOW_END); -- GitLab From e17f8234538d1ff708673f287a42457c4dee720d Mon Sep 17 00:00:00 2001 From: Boris Ostrovsky Date: Mon, 4 Dec 2017 15:07:07 +0100 Subject: [PATCH 1644/2547] x86/entry/64/paravirt: Use paravirt-safe macro to access eflags Commit 1d3e53e8624a ("x86/entry/64: Refactor IRQ stacks and make them NMI-safe") added DEBUG_ENTRY_ASSERT_IRQS_OFF macro that acceses eflags using 'pushfq' instruction when testing for IF bit. On PV Xen guests looking at IF flag directly will always see it set, resulting in 'ud2'. Introduce SAVE_FLAGS() macro that will use appropriate save_fl pv op when running paravirt. Signed-off-by: Boris Ostrovsky Signed-off-by: Thomas Gleixner Reviewed-by: Juergen Gross Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Cc: xen-devel@lists.xenproject.org Link: https://lkml.kernel.org/r/20171204150604.899457242@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/entry/entry_64.S | 7 ++++--- arch/x86/include/asm/irqflags.h | 3 +++ arch/x86/include/asm/paravirt.h | 9 +++++++++ arch/x86/kernel/asm-offsets_64.c | 3 +++ 4 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index a2b30ec69497..32306788821c 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -462,12 +462,13 @@ END(irq_entries_start) .macro DEBUG_ENTRY_ASSERT_IRQS_OFF #ifdef CONFIG_DEBUG_ENTRY - pushfq - testl $X86_EFLAGS_IF, (%rsp) + pushq %rax + SAVE_FLAGS(CLBR_RAX) + testl $X86_EFLAGS_IF, %eax jz .Lokay_\@ ud2 .Lokay_\@: - addq $8, %rsp + popq %rax #endif .endm diff --git a/arch/x86/include/asm/irqflags.h b/arch/x86/include/asm/irqflags.h index c8ef23f2c28f..89f08955fff7 100644 --- a/arch/x86/include/asm/irqflags.h +++ b/arch/x86/include/asm/irqflags.h @@ -142,6 +142,9 @@ static inline notrace unsigned long arch_local_irq_save(void) swapgs; \ sysretl +#ifdef CONFIG_DEBUG_ENTRY +#define SAVE_FLAGS(x) pushfq; popq %rax +#endif #else #define INTERRUPT_RETURN iret #define ENABLE_INTERRUPTS_SYSEXIT sti; sysexit diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index 283efcaac8af..892df375b615 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -927,6 +927,15 @@ extern void default_banner(void); PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \ CLBR_NONE, \ jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64)) + +#ifdef CONFIG_DEBUG_ENTRY +#define SAVE_FLAGS(clobbers) \ + PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_save_fl), clobbers, \ + PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ + call PARA_INDIRECT(pv_irq_ops+PV_IRQ_save_fl); \ + PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) +#endif + #endif /* CONFIG_X86_32 */ #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/kernel/asm-offsets_64.c b/arch/x86/kernel/asm-offsets_64.c index 630212fa9b9d..e3a5175a444b 100644 --- a/arch/x86/kernel/asm-offsets_64.c +++ b/arch/x86/kernel/asm-offsets_64.c @@ -23,6 +23,9 @@ int main(void) #ifdef CONFIG_PARAVIRT OFFSET(PV_CPU_usergs_sysret64, pv_cpu_ops, usergs_sysret64); OFFSET(PV_CPU_swapgs, pv_cpu_ops, swapgs); +#ifdef CONFIG_DEBUG_ENTRY + OFFSET(PV_IRQ_save_fl, pv_irq_ops, save_fl); +#endif BLANK(); #endif -- GitLab From d3a09104018cf2ad5973dfa8a9c138ef9f5015a3 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:08 +0100 Subject: [PATCH 1645/2547] x86/unwinder/orc: Dont bail on stack overflow If the stack overflows into a guard page and the ORC unwinder should work well: by construction, there can't be any meaningful data in the guard page because no writes to the guard page will have succeeded. But there is a bug that prevents unwinding from working correctly: if the starting register state has RSP pointing into a stack guard page, the ORC unwinder bails out immediately. Instead of bailing out immediately check whether the next page up is a valid check page and if so analyze that. As a result the ORC unwinder will start the unwind. Tested by intentionally overflowing the task stack. The result is an accurate call trace instead of a trace consisting purely of '?' entries. There are a few other bugs that are triggered if the unwinder encounters a stack overflow after the first step, but they are outside the scope of this fix. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150604.991389777@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/kernel/unwind_orc.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/unwind_orc.c b/arch/x86/kernel/unwind_orc.c index a3f973b2c97a..ff8e1132b2ae 100644 --- a/arch/x86/kernel/unwind_orc.c +++ b/arch/x86/kernel/unwind_orc.c @@ -553,8 +553,18 @@ void __unwind_start(struct unwind_state *state, struct task_struct *task, } if (get_stack_info((unsigned long *)state->sp, state->task, - &state->stack_info, &state->stack_mask)) - return; + &state->stack_info, &state->stack_mask)) { + /* + * We weren't on a valid stack. It's possible that + * we overflowed a valid stack into a guard page. + * See if the next page up is valid so that we can + * generate some kind of backtrace if this happens. + */ + void *next_page = (void *)PAGE_ALIGN((unsigned long)state->sp); + if (get_stack_info(next_page, state->task, &state->stack_info, + &state->stack_mask)) + return; + } /* * The caller can provide the address of the first frame directly -- GitLab From b02fcf9ba1211097754b286043cd87a8b4907e75 Mon Sep 17 00:00:00 2001 From: Josh Poimboeuf Date: Mon, 4 Dec 2017 15:07:09 +0100 Subject: [PATCH 1646/2547] x86/unwinder: Handle stack overflows more gracefully There are at least two unwinder bugs hindering the debugging of stack-overflow crashes: - It doesn't deal gracefully with the case where the stack overflows and the stack pointer itself isn't on a valid stack but the to-be-dereferenced data *is*. - The ORC oops dump code doesn't know how to print partial pt_regs, for the case where if we get an interrupt/exception in *early* entry code before the full pt_regs have been saved. Fix both issues. http://lkml.kernel.org/r/20171126024031.uxi4numpbjm5rlbr@treble Signed-off-by: Josh Poimboeuf Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Andy Lutomirski Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150605.071425003@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/kdebug.h | 1 + arch/x86/include/asm/unwind.h | 7 ++++ arch/x86/kernel/dumpstack.c | 32 ++++++++++++--- arch/x86/kernel/process_64.c | 11 +++--- arch/x86/kernel/unwind_orc.c | 74 ++++++++++++----------------------- 5 files changed, 65 insertions(+), 60 deletions(-) diff --git a/arch/x86/include/asm/kdebug.h b/arch/x86/include/asm/kdebug.h index f86a8caa561e..395c9631e000 100644 --- a/arch/x86/include/asm/kdebug.h +++ b/arch/x86/include/asm/kdebug.h @@ -26,6 +26,7 @@ extern void die(const char *, struct pt_regs *,long); extern int __must_check __die(const char *, struct pt_regs *, long); extern void show_stack_regs(struct pt_regs *regs); extern void __show_regs(struct pt_regs *regs, int all); +extern void show_iret_regs(struct pt_regs *regs); extern unsigned long oops_begin(void); extern void oops_end(unsigned long, struct pt_regs *, int signr); diff --git a/arch/x86/include/asm/unwind.h b/arch/x86/include/asm/unwind.h index e9cc6fe1fc6f..c1688c2d0a12 100644 --- a/arch/x86/include/asm/unwind.h +++ b/arch/x86/include/asm/unwind.h @@ -7,6 +7,9 @@ #include #include +#define IRET_FRAME_OFFSET (offsetof(struct pt_regs, ip)) +#define IRET_FRAME_SIZE (sizeof(struct pt_regs) - IRET_FRAME_OFFSET) + struct unwind_state { struct stack_info stack_info; unsigned long stack_mask; @@ -52,6 +55,10 @@ void unwind_start(struct unwind_state *state, struct task_struct *task, } #if defined(CONFIG_UNWINDER_ORC) || defined(CONFIG_UNWINDER_FRAME_POINTER) +/* + * WARNING: The entire pt_regs may not be safe to dereference. In some cases, + * only the iret frame registers are accessible. Use with caution! + */ static inline struct pt_regs *unwind_get_entry_regs(struct unwind_state *state) { if (unwind_done(state)) diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index f13b4c00a5de..0bc95be5c638 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -50,6 +50,28 @@ static void printk_stack_address(unsigned long address, int reliable, printk("%s %s%pB\n", log_lvl, reliable ? "" : "? ", (void *)address); } +void show_iret_regs(struct pt_regs *regs) +{ + printk(KERN_DEFAULT "RIP: %04x:%pS\n", (int)regs->cs, (void *)regs->ip); + printk(KERN_DEFAULT "RSP: %04x:%016lx EFLAGS: %08lx", (int)regs->ss, + regs->sp, regs->flags); +} + +static void show_regs_safe(struct stack_info *info, struct pt_regs *regs) +{ + if (on_stack(info, regs, sizeof(*regs))) + __show_regs(regs, 0); + else if (on_stack(info, (void *)regs + IRET_FRAME_OFFSET, + IRET_FRAME_SIZE)) { + /* + * When an interrupt or exception occurs in entry code, the + * full pt_regs might not have been saved yet. In that case + * just print the iret frame. + */ + show_iret_regs(regs); + } +} + void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, unsigned long *stack, char *log_lvl) { @@ -94,8 +116,8 @@ void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, if (stack_name) printk("%s <%s>\n", log_lvl, stack_name); - if (regs && on_stack(&stack_info, regs, sizeof(*regs))) - __show_regs(regs, 0); + if (regs) + show_regs_safe(&stack_info, regs); /* * Scan the stack, printing any text addresses we find. At the @@ -119,7 +141,7 @@ void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, /* * Don't print regs->ip again if it was already printed - * by __show_regs() below. + * by show_regs_safe() below. */ if (regs && stack == ®s->ip) goto next; @@ -155,8 +177,8 @@ void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, /* if the frame has entry regs, print them */ regs = unwind_get_entry_regs(&state); - if (regs && on_stack(&stack_info, regs, sizeof(*regs))) - __show_regs(regs, 0); + if (regs) + show_regs_safe(&stack_info, regs); } if (stack_name) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index eeeb34f85c25..01b119bebb68 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -69,9 +69,8 @@ void __show_regs(struct pt_regs *regs, int all) unsigned int fsindex, gsindex; unsigned int ds, cs, es; - printk(KERN_DEFAULT "RIP: %04lx:%pS\n", regs->cs, (void *)regs->ip); - printk(KERN_DEFAULT "RSP: %04lx:%016lx EFLAGS: %08lx", regs->ss, - regs->sp, regs->flags); + show_iret_regs(regs); + if (regs->orig_ax != -1) pr_cont(" ORIG_RAX: %016lx\n", regs->orig_ax); else @@ -88,6 +87,9 @@ void __show_regs(struct pt_regs *regs, int all) printk(KERN_DEFAULT "R13: %016lx R14: %016lx R15: %016lx\n", regs->r13, regs->r14, regs->r15); + if (!all) + return; + asm("movl %%ds,%0" : "=r" (ds)); asm("movl %%cs,%0" : "=r" (cs)); asm("movl %%es,%0" : "=r" (es)); @@ -98,9 +100,6 @@ void __show_regs(struct pt_regs *regs, int all) rdmsrl(MSR_GS_BASE, gs); rdmsrl(MSR_KERNEL_GS_BASE, shadowgs); - if (!all) - return; - cr0 = read_cr0(); cr2 = read_cr2(); cr3 = __read_cr3(); diff --git a/arch/x86/kernel/unwind_orc.c b/arch/x86/kernel/unwind_orc.c index ff8e1132b2ae..be86a865087a 100644 --- a/arch/x86/kernel/unwind_orc.c +++ b/arch/x86/kernel/unwind_orc.c @@ -253,22 +253,15 @@ unsigned long *unwind_get_return_address_ptr(struct unwind_state *state) return NULL; } -static bool stack_access_ok(struct unwind_state *state, unsigned long addr, +static bool stack_access_ok(struct unwind_state *state, unsigned long _addr, size_t len) { struct stack_info *info = &state->stack_info; + void *addr = (void *)_addr; - /* - * If the address isn't on the current stack, switch to the next one. - * - * We may have to traverse multiple stacks to deal with the possibility - * that info->next_sp could point to an empty stack and the address - * could be on a subsequent stack. - */ - while (!on_stack(info, (void *)addr, len)) - if (get_stack_info(info->next_sp, state->task, info, - &state->stack_mask)) - return false; + if (!on_stack(info, addr, len) && + (get_stack_info(addr, state->task, info, &state->stack_mask))) + return false; return true; } @@ -283,42 +276,32 @@ static bool deref_stack_reg(struct unwind_state *state, unsigned long addr, return true; } -#define REGS_SIZE (sizeof(struct pt_regs)) -#define SP_OFFSET (offsetof(struct pt_regs, sp)) -#define IRET_REGS_SIZE (REGS_SIZE - offsetof(struct pt_regs, ip)) -#define IRET_SP_OFFSET (SP_OFFSET - offsetof(struct pt_regs, ip)) - static bool deref_stack_regs(struct unwind_state *state, unsigned long addr, - unsigned long *ip, unsigned long *sp, bool full) + unsigned long *ip, unsigned long *sp) { - size_t regs_size = full ? REGS_SIZE : IRET_REGS_SIZE; - size_t sp_offset = full ? SP_OFFSET : IRET_SP_OFFSET; - struct pt_regs *regs = (struct pt_regs *)(addr + regs_size - REGS_SIZE); - - if (IS_ENABLED(CONFIG_X86_64)) { - if (!stack_access_ok(state, addr, regs_size)) - return false; - - *ip = regs->ip; - *sp = regs->sp; + struct pt_regs *regs = (struct pt_regs *)addr; - return true; - } + /* x86-32 support will be more complicated due to the ®s->sp hack */ + BUILD_BUG_ON(IS_ENABLED(CONFIG_X86_32)); - if (!stack_access_ok(state, addr, sp_offset)) + if (!stack_access_ok(state, addr, sizeof(struct pt_regs))) return false; *ip = regs->ip; + *sp = regs->sp; + return true; +} - if (user_mode(regs)) { - if (!stack_access_ok(state, addr + sp_offset, - REGS_SIZE - SP_OFFSET)) - return false; +static bool deref_stack_iret_regs(struct unwind_state *state, unsigned long addr, + unsigned long *ip, unsigned long *sp) +{ + struct pt_regs *regs = (void *)addr - IRET_FRAME_OFFSET; - *sp = regs->sp; - } else - *sp = (unsigned long)®s->sp; + if (!stack_access_ok(state, addr, IRET_FRAME_SIZE)) + return false; + *ip = regs->ip; + *sp = regs->sp; return true; } @@ -327,7 +310,6 @@ bool unwind_next_frame(struct unwind_state *state) unsigned long ip_p, sp, orig_ip, prev_sp = state->sp; enum stack_type prev_type = state->stack_info.type; struct orc_entry *orc; - struct pt_regs *ptregs; bool indirect = false; if (unwind_done(state)) @@ -435,7 +417,7 @@ bool unwind_next_frame(struct unwind_state *state) break; case ORC_TYPE_REGS: - if (!deref_stack_regs(state, sp, &state->ip, &state->sp, true)) { + if (!deref_stack_regs(state, sp, &state->ip, &state->sp)) { orc_warn("can't dereference registers at %p for ip %pB\n", (void *)sp, (void *)orig_ip); goto done; @@ -447,20 +429,14 @@ bool unwind_next_frame(struct unwind_state *state) break; case ORC_TYPE_REGS_IRET: - if (!deref_stack_regs(state, sp, &state->ip, &state->sp, false)) { + if (!deref_stack_iret_regs(state, sp, &state->ip, &state->sp)) { orc_warn("can't dereference iret registers at %p for ip %pB\n", (void *)sp, (void *)orig_ip); goto done; } - ptregs = container_of((void *)sp, struct pt_regs, ip); - if ((unsigned long)ptregs >= prev_sp && - on_stack(&state->stack_info, ptregs, REGS_SIZE)) { - state->regs = ptregs; - state->full_regs = false; - } else - state->regs = NULL; - + state->regs = (void *)sp - IRET_FRAME_OFFSET; + state->full_regs = false; state->signal = true; break; -- GitLab From 6669a692605547892a026445e460bf233958bd7f Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:10 +0100 Subject: [PATCH 1647/2547] x86/irq: Remove an old outdated comment about context tracking races That race has been fixed and code cleaned up for a while now. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Reviewed-by: Thomas Gleixner Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150605.150551639@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/kernel/irq.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 52089c043160..aa9d51eea9d0 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -219,18 +219,6 @@ __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs) /* high bit used in ret_from_ code */ unsigned vector = ~regs->orig_ax; - /* - * NB: Unlike exception entries, IRQ entries do not reliably - * handle context tracking in the low-level entry code. This is - * because syscall entries execute briefly with IRQs on before - * updating context tracking state, so we can take an IRQ from - * kernel mode with CONTEXT_USER. The low-level entry code only - * updates the context if we came from user mode, so we won't - * switch to CONTEXT_KERNEL. We'll fix that once the syscall - * code is cleaned up enough that we can cleanly defer enabling - * IRQs. - */ - entering_irq(); /* entering_irq() tells RCU that we're not quiescent. Check it. */ -- GitLab From 4f3789e792296e21405f708cf3cb409d7c7d5683 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:11 +0100 Subject: [PATCH 1648/2547] x86/irq/64: Print the offending IP in the stack overflow warning In case something goes wrong with unwind (not unlikely in case of overflow), print the offending IP where we detected the overflow. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Reviewed-by: Thomas Gleixner Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150605.231677119@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/kernel/irq_64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/irq_64.c b/arch/x86/kernel/irq_64.c index 020efbf5786b..d86e344f5b3d 100644 --- a/arch/x86/kernel/irq_64.c +++ b/arch/x86/kernel/irq_64.c @@ -57,10 +57,10 @@ static inline void stack_overflow_check(struct pt_regs *regs) if (regs->sp >= estack_top && regs->sp <= estack_bottom) return; - WARN_ONCE(1, "do_IRQ(): %s has overflown the kernel stack (cur:%Lx,sp:%lx,irq stk top-bottom:%Lx-%Lx,exception stk top-bottom:%Lx-%Lx)\n", + WARN_ONCE(1, "do_IRQ(): %s has overflown the kernel stack (cur:%Lx,sp:%lx,irq stk top-bottom:%Lx-%Lx,exception stk top-bottom:%Lx-%Lx,ip:%pF)\n", current->comm, curbase, regs->sp, irq_stack_top, irq_stack_bottom, - estack_top, estack_bottom); + estack_top, estack_bottom, (void *)regs->ip); if (sysctl_panic_on_stackoverflow) panic("low stack detected by irq handler - check messages\n"); -- GitLab From 1a79797b58cddfa948420a7553241c79c013e3ca Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:12 +0100 Subject: [PATCH 1649/2547] x86/entry/64: Allocate and enable the SYSENTER stack This will simplify future changes that want scratch variables early in the SYSENTER handler -- they'll be able to spill registers to the stack. It also lets us get rid of a SWAPGS_UNSAFE_STACK user. This does not depend on CONFIG_IA32_EMULATION=y because we'll want the stack space even without IA32 emulation. As far as I can tell, the reason that this wasn't done from day 1 is that we use IST for #DB and #BP, which is IMO rather nasty and causes a lot more problems than it solves. But, since #DB uses IST, we don't actually need a real stack for SYSENTER (because SYSENTER with TF set will invoke #DB on the IST stack rather than the SYSENTER stack). I want to remove IST usage from these vectors some day, and this patch is a prerequisite for that as well. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150605.312726423@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/entry/entry_64_compat.S | 2 +- arch/x86/include/asm/processor.h | 3 --- arch/x86/kernel/asm-offsets.c | 5 +++++ arch/x86/kernel/asm-offsets_32.c | 5 ----- arch/x86/kernel/cpu/common.c | 4 +++- arch/x86/kernel/process.c | 2 -- arch/x86/kernel/traps.c | 3 +-- 7 files changed, 10 insertions(+), 14 deletions(-) diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_compat.S index 568e130d932c..dcc6987f9bae 100644 --- a/arch/x86/entry/entry_64_compat.S +++ b/arch/x86/entry/entry_64_compat.S @@ -48,7 +48,7 @@ */ ENTRY(entry_SYSENTER_compat) /* Interrupts are off on entry. */ - SWAPGS_UNSAFE_STACK + SWAPGS movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp /* diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 2db7cf720b04..789dad5da20f 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -339,14 +339,11 @@ struct tss_struct { */ unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; -#ifdef CONFIG_X86_32 /* * Space for the temporary SYSENTER stack. */ unsigned long SYSENTER_stack_canary; unsigned long SYSENTER_stack[64]; -#endif - } ____cacheline_aligned; DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c index 8ea78275480d..b275863128eb 100644 --- a/arch/x86/kernel/asm-offsets.c +++ b/arch/x86/kernel/asm-offsets.c @@ -93,4 +93,9 @@ void common(void) { BLANK(); DEFINE(PTREGS_SIZE, sizeof(struct pt_regs)); + + /* Offset from cpu_tss to SYSENTER_stack */ + OFFSET(CPU_TSS_SYSENTER_stack, tss_struct, SYSENTER_stack); + /* Size of SYSENTER_stack */ + DEFINE(SIZEOF_SYSENTER_stack, sizeof(((struct tss_struct *)0)->SYSENTER_stack)); } diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c index dedf428b20b6..52ce4ea16e53 100644 --- a/arch/x86/kernel/asm-offsets_32.c +++ b/arch/x86/kernel/asm-offsets_32.c @@ -50,11 +50,6 @@ void foo(void) DEFINE(TSS_sysenter_sp0, offsetof(struct tss_struct, x86_tss.sp0) - offsetofend(struct tss_struct, SYSENTER_stack)); - /* Offset from cpu_tss to SYSENTER_stack */ - OFFSET(CPU_TSS_SYSENTER_stack, tss_struct, SYSENTER_stack); - /* Size of SYSENTER_stack */ - DEFINE(SIZEOF_SYSENTER_stack, sizeof(((struct tss_struct *)0)->SYSENTER_stack)); - #ifdef CONFIG_CC_STACKPROTECTOR BLANK(); OFFSET(stack_canary_offset, stack_canary, canary); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index cdf79ab628c2..22f542170198 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1361,7 +1361,9 @@ void syscall_init(void) * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). */ wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); - wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); + wrmsrl_safe(MSR_IA32_SYSENTER_ESP, + (unsigned long)this_cpu_ptr(&cpu_tss) + + offsetofend(struct tss_struct, SYSENTER_stack)); wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); #else wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 97fb3e5737f5..35d674157fda 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -71,9 +71,7 @@ __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { */ .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, #endif -#ifdef CONFIG_X86_32 .SYSENTER_stack_canary = STACK_END_MAGIC, -#endif }; EXPORT_PER_CPU_SYMBOL(cpu_tss); diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index d366adfc61da..d3e3bbd5d3a0 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -794,14 +794,13 @@ dotraplinkage void do_debug(struct pt_regs *regs, long error_code) debug_stack_usage_dec(); exit: -#if defined(CONFIG_X86_32) /* * This is the most likely code path that involves non-trivial use * of the SYSENTER stack. Check that we haven't overrun it. */ WARN(this_cpu_read(cpu_tss.SYSENTER_stack_canary) != STACK_END_MAGIC, "Overran or corrupted SYSENTER stack\n"); -#endif + ist_exit(regs); } NOKPROBE_SYMBOL(do_debug); -- GitLab From 33a2f1a6c4d7c0a02d1c006fb0379cc5ca3b96bb Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:13 +0100 Subject: [PATCH 1650/2547] x86/dumpstack: Add get_stack_info() support for the SYSENTER stack get_stack_info() doesn't currently know about the SYSENTER stack, so unwinding will fail if we entered the kernel on the SYSENTER stack and haven't fully switched off. Teach get_stack_info() about the SYSENTER stack. With future patches applied that run part of the entry code on the SYSENTER stack and introduce an intentional BUG(), I would get: PANIC: double fault, error_code: 0x0 ... RIP: 0010:do_error_trap+0x33/0x1c0 ... Call Trace: Code: ... With this patch, I get: PANIC: double fault, error_code: 0x0 ... Call Trace: ? async_page_fault+0x36/0x60 ? invalid_op+0x22/0x40 ? async_page_fault+0x36/0x60 ? sync_regs+0x3c/0x40 ? sync_regs+0x2e/0x40 ? error_entry+0x6c/0xd0 ? async_page_fault+0x36/0x60 Code: ... which is a lot more informative. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150605.392711508@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/stacktrace.h | 3 +++ arch/x86/kernel/dumpstack.c | 19 +++++++++++++++++++ arch/x86/kernel/dumpstack_32.c | 6 ++++++ arch/x86/kernel/dumpstack_64.c | 6 ++++++ 4 files changed, 34 insertions(+) diff --git a/arch/x86/include/asm/stacktrace.h b/arch/x86/include/asm/stacktrace.h index 8da111b3c342..f8062bfd43a0 100644 --- a/arch/x86/include/asm/stacktrace.h +++ b/arch/x86/include/asm/stacktrace.h @@ -16,6 +16,7 @@ enum stack_type { STACK_TYPE_TASK, STACK_TYPE_IRQ, STACK_TYPE_SOFTIRQ, + STACK_TYPE_SYSENTER, STACK_TYPE_EXCEPTION, STACK_TYPE_EXCEPTION_LAST = STACK_TYPE_EXCEPTION + N_EXCEPTION_STACKS-1, }; @@ -28,6 +29,8 @@ struct stack_info { bool in_task_stack(unsigned long *stack, struct task_struct *task, struct stack_info *info); +bool in_sysenter_stack(unsigned long *stack, struct stack_info *info); + int get_stack_info(unsigned long *stack, struct task_struct *task, struct stack_info *info, unsigned long *visit_mask); diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index 0bc95be5c638..a33a1373a252 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -43,6 +43,25 @@ bool in_task_stack(unsigned long *stack, struct task_struct *task, return true; } +bool in_sysenter_stack(unsigned long *stack, struct stack_info *info) +{ + struct tss_struct *tss = this_cpu_ptr(&cpu_tss); + + /* Treat the canary as part of the stack for unwinding purposes. */ + void *begin = &tss->SYSENTER_stack_canary; + void *end = (void *)&tss->SYSENTER_stack + sizeof(tss->SYSENTER_stack); + + if ((void *)stack < begin || (void *)stack >= end) + return false; + + info->type = STACK_TYPE_SYSENTER; + info->begin = begin; + info->end = end; + info->next_sp = NULL; + + return true; +} + static void printk_stack_address(unsigned long address, int reliable, char *log_lvl) { diff --git a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c index daefae83a3aa..5ff13a6b3680 100644 --- a/arch/x86/kernel/dumpstack_32.c +++ b/arch/x86/kernel/dumpstack_32.c @@ -26,6 +26,9 @@ const char *stack_type_name(enum stack_type type) if (type == STACK_TYPE_SOFTIRQ) return "SOFTIRQ"; + if (type == STACK_TYPE_SYSENTER) + return "SYSENTER"; + return NULL; } @@ -93,6 +96,9 @@ int get_stack_info(unsigned long *stack, struct task_struct *task, if (task != current) goto unknown; + if (in_sysenter_stack(stack, info)) + goto recursion_check; + if (in_hardirq_stack(stack, info)) goto recursion_check; diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c index 88ce2ffdb110..abc828f8c297 100644 --- a/arch/x86/kernel/dumpstack_64.c +++ b/arch/x86/kernel/dumpstack_64.c @@ -37,6 +37,9 @@ const char *stack_type_name(enum stack_type type) if (type == STACK_TYPE_IRQ) return "IRQ"; + if (type == STACK_TYPE_SYSENTER) + return "SYSENTER"; + if (type >= STACK_TYPE_EXCEPTION && type <= STACK_TYPE_EXCEPTION_LAST) return exception_stack_names[type - STACK_TYPE_EXCEPTION]; @@ -115,6 +118,9 @@ int get_stack_info(unsigned long *stack, struct task_struct *task, if (in_irq_stack(stack, info)) goto recursion_check; + if (in_sysenter_stack(stack, info)) + goto recursion_check; + goto unknown; recursion_check: -- GitLab From aaeed3aeb39c1ba69f0a49baec8cb728121d0a91 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:14 +0100 Subject: [PATCH 1651/2547] x86/entry/gdt: Put per-CPU GDT remaps in ascending order We currently have CPU 0's GDT at the top of the GDT range and higher-numbered CPUs at lower addresses. This happens because the fixmap is upside down (index 0 is the top of the fixmap). Flip it so that GDTs are in ascending order by virtual address. This will simplify a future patch that will generalize the GDT remap to contain multiple pages. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Reviewed-by: Thomas Gleixner Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150605.471561421@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/desc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h index 0a3e808b9123..01fd944fd721 100644 --- a/arch/x86/include/asm/desc.h +++ b/arch/x86/include/asm/desc.h @@ -63,7 +63,7 @@ static inline struct desc_struct *get_current_gdt_rw(void) /* Get the fixmap index for a specific processor */ static inline unsigned int get_cpu_gdt_ro_index(int cpu) { - return FIX_GDT_REMAP_BEGIN + cpu; + return FIX_GDT_REMAP_END - cpu; } /* Provide the fixmap address of the remapped GDT */ -- GitLab From ef8813ab280507972bb57e4b1b502811ad4411e9 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:15 +0100 Subject: [PATCH 1652/2547] x86/mm/fixmap: Generalize the GDT fixmap mechanism, introduce struct cpu_entry_area Currently, the GDT is an ad-hoc array of pages, one per CPU, in the fixmap. Generalize it to be an array of a new 'struct cpu_entry_area' so that we can cleanly add new things to it. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150605.563271721@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/desc.h | 9 +-------- arch/x86/include/asm/fixmap.h | 37 +++++++++++++++++++++++++++++++++-- arch/x86/kernel/cpu/common.c | 14 ++++++------- arch/x86/xen/mmu_pv.c | 2 +- 4 files changed, 44 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h index 01fd944fd721..f6f428432a68 100644 --- a/arch/x86/include/asm/desc.h +++ b/arch/x86/include/asm/desc.h @@ -60,17 +60,10 @@ static inline struct desc_struct *get_current_gdt_rw(void) return this_cpu_ptr(&gdt_page)->gdt; } -/* Get the fixmap index for a specific processor */ -static inline unsigned int get_cpu_gdt_ro_index(int cpu) -{ - return FIX_GDT_REMAP_END - cpu; -} - /* Provide the fixmap address of the remapped GDT */ static inline struct desc_struct *get_cpu_gdt_ro(int cpu) { - unsigned int idx = get_cpu_gdt_ro_index(cpu); - return (struct desc_struct *)__fix_to_virt(idx); + return (struct desc_struct *)&get_cpu_entry_area(cpu)->gdt; } /* Provide the current read-only GDT */ diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h index b0c505fe9a95..b61f0242f9d0 100644 --- a/arch/x86/include/asm/fixmap.h +++ b/arch/x86/include/asm/fixmap.h @@ -44,6 +44,19 @@ extern unsigned long __FIXADDR_TOP; PAGE_SIZE) #endif +/* + * cpu_entry_area is a percpu region in the fixmap that contains things + * needed by the CPU and early entry/exit code. Real types aren't used + * for all fields here to avoid circular header dependencies. + * + * Every field is a virtual alias of some other allocated backing store. + * There is no direct allocation of a struct cpu_entry_area. + */ +struct cpu_entry_area { + char gdt[PAGE_SIZE]; +}; + +#define CPU_ENTRY_AREA_PAGES (sizeof(struct cpu_entry_area) / PAGE_SIZE) /* * Here we define all the compile-time 'special' virtual @@ -101,8 +114,8 @@ enum fixed_addresses { FIX_LNW_VRTC, #endif /* Fixmap entries to remap the GDTs, one per processor. */ - FIX_GDT_REMAP_BEGIN, - FIX_GDT_REMAP_END = FIX_GDT_REMAP_BEGIN + NR_CPUS - 1, + FIX_CPU_ENTRY_AREA_TOP, + FIX_CPU_ENTRY_AREA_BOTTOM = FIX_CPU_ENTRY_AREA_TOP + (CPU_ENTRY_AREA_PAGES * NR_CPUS) - 1, #ifdef CONFIG_ACPI_APEI_GHES /* Used for GHES mapping from assorted contexts */ @@ -191,5 +204,25 @@ void __init *early_memremap_decrypted_wp(resource_size_t phys_addr, void __early_set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t flags); +static inline unsigned int __get_cpu_entry_area_page_index(int cpu, int page) +{ + BUILD_BUG_ON(sizeof(struct cpu_entry_area) % PAGE_SIZE != 0); + + return FIX_CPU_ENTRY_AREA_BOTTOM - cpu*CPU_ENTRY_AREA_PAGES - page; +} + +#define __get_cpu_entry_area_offset_index(cpu, offset) ({ \ + BUILD_BUG_ON(offset % PAGE_SIZE != 0); \ + __get_cpu_entry_area_page_index(cpu, offset / PAGE_SIZE); \ + }) + +#define get_cpu_entry_area_index(cpu, field) \ + __get_cpu_entry_area_offset_index((cpu), offsetof(struct cpu_entry_area, field)) + +static inline struct cpu_entry_area *get_cpu_entry_area(int cpu) +{ + return (struct cpu_entry_area *)__fix_to_virt(__get_cpu_entry_area_page_index(cpu, 0)); +} + #endif /* !__ASSEMBLY__ */ #endif /* _ASM_X86_FIXMAP_H */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 22f542170198..2cb394dc4153 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -466,12 +466,12 @@ void load_percpu_segment(int cpu) load_stack_canary_segment(); } -/* Setup the fixmap mapping only once per-processor */ -static inline void setup_fixmap_gdt(int cpu) +/* Setup the fixmap mappings only once per-processor */ +static inline void setup_cpu_entry_area(int cpu) { #ifdef CONFIG_X86_64 /* On 64-bit systems, we use a read-only fixmap GDT. */ - pgprot_t prot = PAGE_KERNEL_RO; + pgprot_t gdt_prot = PAGE_KERNEL_RO; #else /* * On native 32-bit systems, the GDT cannot be read-only because @@ -482,11 +482,11 @@ static inline void setup_fixmap_gdt(int cpu) * On Xen PV, the GDT must be read-only because the hypervisor requires * it. */ - pgprot_t prot = boot_cpu_has(X86_FEATURE_XENPV) ? + pgprot_t gdt_prot = boot_cpu_has(X86_FEATURE_XENPV) ? PAGE_KERNEL_RO : PAGE_KERNEL; #endif - __set_fixmap(get_cpu_gdt_ro_index(cpu), get_cpu_gdt_paddr(cpu), prot); + __set_fixmap(get_cpu_entry_area_index(cpu, gdt), get_cpu_gdt_paddr(cpu), gdt_prot); } /* Load the original GDT from the per-cpu structure */ @@ -1589,7 +1589,7 @@ void cpu_init(void) if (is_uv_system()) uv_cpu_init(); - setup_fixmap_gdt(cpu); + setup_cpu_entry_area(cpu); load_fixmap_gdt(cpu); } @@ -1651,7 +1651,7 @@ void cpu_init(void) fpu__init_cpu(); - setup_fixmap_gdt(cpu); + setup_cpu_entry_area(cpu); load_fixmap_gdt(cpu); } #endif diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c index 2ccdaba31a07..c2454237fa67 100644 --- a/arch/x86/xen/mmu_pv.c +++ b/arch/x86/xen/mmu_pv.c @@ -2272,7 +2272,7 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot) #endif case FIX_TEXT_POKE0: case FIX_TEXT_POKE1: - case FIX_GDT_REMAP_BEGIN ... FIX_GDT_REMAP_END: + case FIX_CPU_ENTRY_AREA_TOP ... FIX_CPU_ENTRY_AREA_BOTTOM: /* All local page mappings */ pte = pfn_pte(phys, prot); break; -- GitLab From 21506525fb8ddb0342f2a2370812d47f6a1f3833 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:16 +0100 Subject: [PATCH 1653/2547] x86/kasan/64: Teach KASAN about the cpu_entry_area The cpu_entry_area will contain stacks. Make sure that KASAN has appropriate shadow mappings for them. Signed-off-by: Andy Lutomirski Signed-off-by: Andrey Ryabinin Signed-off-by: Thomas Gleixner Cc: Alexander Potapenko Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Dmitry Vyukov Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: kasan-dev@googlegroups.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150605.642806442@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/mm/kasan_init_64.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/kasan_init_64.c b/arch/x86/mm/kasan_init_64.c index 99dfed6dfef8..9ec70d780f1f 100644 --- a/arch/x86/mm/kasan_init_64.c +++ b/arch/x86/mm/kasan_init_64.c @@ -277,6 +277,7 @@ void __init kasan_early_init(void) void __init kasan_init(void) { int i; + void *shadow_cpu_entry_begin, *shadow_cpu_entry_end; #ifdef CONFIG_KASAN_INLINE register_die_notifier(&kasan_die_notifier); @@ -329,8 +330,23 @@ void __init kasan_init(void) (unsigned long)kasan_mem_to_shadow(_end), early_pfn_to_nid(__pa(_stext))); + shadow_cpu_entry_begin = (void *)__fix_to_virt(FIX_CPU_ENTRY_AREA_BOTTOM); + shadow_cpu_entry_begin = kasan_mem_to_shadow(shadow_cpu_entry_begin); + shadow_cpu_entry_begin = (void *)round_down((unsigned long)shadow_cpu_entry_begin, + PAGE_SIZE); + + shadow_cpu_entry_end = (void *)(__fix_to_virt(FIX_CPU_ENTRY_AREA_TOP) + PAGE_SIZE); + shadow_cpu_entry_end = kasan_mem_to_shadow(shadow_cpu_entry_end); + shadow_cpu_entry_end = (void *)round_up((unsigned long)shadow_cpu_entry_end, + PAGE_SIZE); + kasan_populate_zero_shadow(kasan_mem_to_shadow((void *)MODULES_END), - (void *)KASAN_SHADOW_END); + shadow_cpu_entry_begin); + + kasan_populate_shadow((unsigned long)shadow_cpu_entry_begin, + (unsigned long)shadow_cpu_entry_end, 0); + + kasan_populate_zero_shadow(shadow_cpu_entry_end, (void *)KASAN_SHADOW_END); load_cr3(init_top_pgt); __flush_tlb_all(); -- GitLab From 7fb983b4dd569e08564134a850dfd4eb1c63d9b8 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:17 +0100 Subject: [PATCH 1654/2547] x86/entry: Fix assumptions that the HW TSS is at the beginning of cpu_tss A future patch will move SYSENTER_stack to the beginning of cpu_tss to help detect overflow. Before this can happen, fix several code paths that hardcode assumptions about the old layout. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Reviewed-by: Dave Hansen Reviewed-by: Thomas Gleixner Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150605.722425540@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/desc.h | 2 +- arch/x86/include/asm/processor.h | 9 ++++++-- arch/x86/kernel/cpu/common.c | 8 +++---- arch/x86/kernel/doublefault.c | 36 +++++++++++++++----------------- arch/x86/kvm/vmx.c | 2 +- arch/x86/power/cpu.c | 13 ++++++------ 6 files changed, 37 insertions(+), 33 deletions(-) diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h index f6f428432a68..2ace1f90d138 100644 --- a/arch/x86/include/asm/desc.h +++ b/arch/x86/include/asm/desc.h @@ -178,7 +178,7 @@ static inline void set_tssldt_descriptor(void *d, unsigned long addr, #endif } -static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr) +static inline void __set_tss_desc(unsigned cpu, unsigned int entry, struct x86_hw_tss *addr) { struct desc_struct *d = get_cpu_gdt_rw(cpu); tss_desc tss; diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 789dad5da20f..555c9478f3df 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -162,7 +162,7 @@ enum cpuid_regs_idx { extern struct cpuinfo_x86 boot_cpu_data; extern struct cpuinfo_x86 new_cpu_data; -extern struct tss_struct doublefault_tss; +extern struct x86_hw_tss doublefault_tss; extern __u32 cpu_caps_cleared[NCAPINTS]; extern __u32 cpu_caps_set[NCAPINTS]; @@ -252,6 +252,11 @@ static inline void load_cr3(pgd_t *pgdir) write_cr3(__sme_pa(pgdir)); } +/* + * Note that while the legacy 'TSS' name comes from 'Task State Segment', + * on modern x86 CPUs the TSS also holds information important to 64-bit mode, + * unrelated to the task-switch mechanism: + */ #ifdef CONFIG_X86_32 /* This is the TSS defined by the hardware. */ struct x86_hw_tss { @@ -322,7 +327,7 @@ struct x86_hw_tss { #define IO_BITMAP_BITS 65536 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) -#define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) +#define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss)) #define INVALID_IO_BITMAP_OFFSET 0x8000 struct tss_struct { diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 2cb394dc4153..3f285b973f50 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1557,7 +1557,7 @@ void cpu_init(void) } } - t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); + t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; /* * <= is required because the CPU will access up to @@ -1576,7 +1576,7 @@ void cpu_init(void) * Initialize the TSS. Don't bother initializing sp0, as the initial * task never enters user mode. */ - set_tss_desc(cpu, t); + set_tss_desc(cpu, &t->x86_tss); load_TR_desc(); load_mm_ldt(&init_mm); @@ -1634,12 +1634,12 @@ void cpu_init(void) * Initialize the TSS. Don't bother initializing sp0, as the initial * task never enters user mode. */ - set_tss_desc(cpu, t); + set_tss_desc(cpu, &t->x86_tss); load_TR_desc(); load_mm_ldt(&init_mm); - t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); + t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; #ifdef CONFIG_DOUBLEFAULT /* Set up doublefault TSS pointer in the GDT */ diff --git a/arch/x86/kernel/doublefault.c b/arch/x86/kernel/doublefault.c index 0e662c55ae90..0b8cedb20d6d 100644 --- a/arch/x86/kernel/doublefault.c +++ b/arch/x86/kernel/doublefault.c @@ -50,25 +50,23 @@ static void doublefault_fn(void) cpu_relax(); } -struct tss_struct doublefault_tss __cacheline_aligned = { - .x86_tss = { - .sp0 = STACK_START, - .ss0 = __KERNEL_DS, - .ldt = 0, - .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, - - .ip = (unsigned long) doublefault_fn, - /* 0x2 bit is always set */ - .flags = X86_EFLAGS_SF | 0x2, - .sp = STACK_START, - .es = __USER_DS, - .cs = __KERNEL_CS, - .ss = __KERNEL_DS, - .ds = __USER_DS, - .fs = __KERNEL_PERCPU, - - .__cr3 = __pa_nodebug(swapper_pg_dir), - } +struct x86_hw_tss doublefault_tss __cacheline_aligned = { + .sp0 = STACK_START, + .ss0 = __KERNEL_DS, + .ldt = 0, + .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, + + .ip = (unsigned long) doublefault_fn, + /* 0x2 bit is always set */ + .flags = X86_EFLAGS_SF | 0x2, + .sp = STACK_START, + .es = __USER_DS, + .cs = __KERNEL_CS, + .ss = __KERNEL_DS, + .ds = __USER_DS, + .fs = __KERNEL_PERCPU, + + .__cr3 = __pa_nodebug(swapper_pg_dir), }; /* dummy for do_double_fault() call */ diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index a6f4f095f8f4..2abe0073b573 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -2291,7 +2291,7 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) * processors. See 22.2.4. */ vmcs_writel(HOST_TR_BASE, - (unsigned long)this_cpu_ptr(&cpu_tss)); + (unsigned long)this_cpu_ptr(&cpu_tss.x86_tss)); vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ /* diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index 84fcfde53f8f..50593e138281 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -165,12 +165,13 @@ static void fix_processor_context(void) struct desc_struct *desc = get_cpu_gdt_rw(cpu); tss_desc tss; #endif - set_tss_desc(cpu, t); /* - * This just modifies memory; should not be - * necessary. But... This is necessary, because - * 386 hardware has concept of busy TSS or some - * similar stupidity. - */ + + /* + * This just modifies memory; should not be necessary. But... This is + * necessary, because 386 hardware has concept of busy TSS or some + * similar stupidity. + */ + set_tss_desc(cpu, &t->x86_tss); #ifdef CONFIG_X86_64 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc)); -- GitLab From 6e60e583426c2f8751c22c2dfe5c207083b4483a Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:18 +0100 Subject: [PATCH 1655/2547] x86/dumpstack: Handle stack overflow on all stacks We currently special-case stack overflow on the task stack. We're going to start putting special stacks in the fixmap with a custom layout, so they'll have guard pages, too. Teach the unwinder to be able to unwind an overflow of any of the stacks. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150605.802057305@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/kernel/dumpstack.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index a33a1373a252..64f8ed2a4827 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -112,24 +112,28 @@ void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, * - task stack * - interrupt stack * - HW exception stacks (double fault, nmi, debug, mce) + * - SYSENTER stack * - * x86-32 can have up to three stacks: + * x86-32 can have up to four stacks: * - task stack * - softirq stack * - hardirq stack + * - SYSENTER stack */ for (regs = NULL; stack; stack = PTR_ALIGN(stack_info.next_sp, sizeof(long))) { const char *stack_name; - /* - * If we overflowed the task stack into a guard page, jump back - * to the bottom of the usable stack. - */ - if (task_stack_page(task) - (void *)stack < PAGE_SIZE) - stack = task_stack_page(task); - - if (get_stack_info(stack, task, &stack_info, &visit_mask)) - break; + if (get_stack_info(stack, task, &stack_info, &visit_mask)) { + /* + * We weren't on a valid stack. It's possible that + * we overflowed a valid stack into a guard page. + * See if the next page up is valid so that we can + * generate some kind of backtrace if this happens. + */ + stack = (unsigned long *)PAGE_ALIGN((unsigned long)stack); + if (get_stack_info(stack, task, &stack_info, &visit_mask)) + break; + } stack_name = stack_type_name(stack_info.type); if (stack_name) -- GitLab From 1a935bc3d4ea61556461a9e92a68ca3556232efd Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:19 +0100 Subject: [PATCH 1656/2547] x86/entry: Move SYSENTER_stack to the beginning of struct tss_struct SYSENTER_stack should have reliable overflow detection, which means that it needs to be at the bottom of a page, not the top. Move it to the beginning of struct tss_struct and page-align it. Also add an assertion to make sure that the fixed hardware TSS doesn't cross a page boundary. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150605.881827433@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/processor.h | 21 ++++++++++++--------- arch/x86/kernel/cpu/common.c | 21 +++++++++++++++++++++ 2 files changed, 33 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 555c9478f3df..759051251664 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -332,7 +332,16 @@ struct x86_hw_tss { struct tss_struct { /* - * The hardware state: + * Space for the temporary SYSENTER stack, used for SYSENTER + * and the entry trampoline as well. + */ + unsigned long SYSENTER_stack_canary; + unsigned long SYSENTER_stack[64]; + + /* + * The fixed hardware portion. This must not cross a page boundary + * at risk of violating the SDM's advice and potentially triggering + * errata. */ struct x86_hw_tss x86_tss; @@ -343,15 +352,9 @@ struct tss_struct { * be within the limit. */ unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; +} __aligned(PAGE_SIZE); - /* - * Space for the temporary SYSENTER stack. - */ - unsigned long SYSENTER_stack_canary; - unsigned long SYSENTER_stack[64]; -} ____cacheline_aligned; - -DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); +DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss); /* * sizeof(unsigned long) coming from an extra "long" at the end diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3f285b973f50..60b2dfd2a58b 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -487,6 +487,27 @@ static inline void setup_cpu_entry_area(int cpu) #endif __set_fixmap(get_cpu_entry_area_index(cpu, gdt), get_cpu_gdt_paddr(cpu), gdt_prot); + + /* + * The Intel SDM says (Volume 3, 7.2.1): + * + * Avoid placing a page boundary in the part of the TSS that the + * processor reads during a task switch (the first 104 bytes). The + * processor may not correctly perform address translations if a + * boundary occurs in this area. During a task switch, the processor + * reads and writes into the first 104 bytes of each TSS (using + * contiguous physical addresses beginning with the physical address + * of the first byte of the TSS). So, after TSS access begins, if + * part of the 104 bytes is not physically contiguous, the processor + * will access incorrect information without generating a page-fault + * exception. + * + * There are also a lot of errata involving the TSS spanning a page + * boundary. Assert that we're not doing that. + */ + BUILD_BUG_ON((offsetof(struct tss_struct, x86_tss) ^ + offsetofend(struct tss_struct, x86_tss)) & PAGE_MASK); + } /* Load the original GDT from the per-cpu structure */ -- GitLab From 72f5e08dbba2d01aa90b592cf76c378ea233b00b Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:20 +0100 Subject: [PATCH 1657/2547] x86/entry: Remap the TSS into the CPU entry area This has a secondary purpose: it puts the entry stack into a region with a well-controlled layout. A subsequent patch will take advantage of this to streamline the SYSCALL entry code to be able to find it more easily. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150605.962042855@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/entry/entry_32.S | 6 +++-- arch/x86/include/asm/fixmap.h | 7 ++++++ arch/x86/kernel/asm-offsets.c | 3 +++ arch/x86/kernel/cpu/common.c | 41 ++++++++++++++++++++++++++++++----- arch/x86/kernel/dumpstack.c | 3 ++- arch/x86/kvm/vmx.c | 2 +- arch/x86/power/cpu.c | 11 +++++----- 7 files changed, 58 insertions(+), 15 deletions(-) diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S index 4838037f97f6..0ab316c46806 100644 --- a/arch/x86/entry/entry_32.S +++ b/arch/x86/entry/entry_32.S @@ -941,7 +941,8 @@ ENTRY(debug) movl %esp, %eax # pt_regs pointer /* Are we currently on the SYSENTER stack? */ - PER_CPU(cpu_tss + CPU_TSS_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx) + movl PER_CPU_VAR(cpu_entry_area), %ecx + addl $CPU_ENTRY_AREA_tss + CPU_TSS_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx subl %eax, %ecx /* ecx = (end of SYSENTER_stack) - esp */ cmpl $SIZEOF_SYSENTER_stack, %ecx jb .Ldebug_from_sysenter_stack @@ -984,7 +985,8 @@ ENTRY(nmi) movl %esp, %eax # pt_regs pointer /* Are we currently on the SYSENTER stack? */ - PER_CPU(cpu_tss + CPU_TSS_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx) + movl PER_CPU_VAR(cpu_entry_area), %ecx + addl $CPU_ENTRY_AREA_tss + CPU_TSS_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx subl %eax, %ecx /* ecx = (end of SYSENTER_stack) - esp */ cmpl $SIZEOF_SYSENTER_stack, %ecx jb .Lnmi_from_sysenter_stack diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h index b61f0242f9d0..84558b611ad3 100644 --- a/arch/x86/include/asm/fixmap.h +++ b/arch/x86/include/asm/fixmap.h @@ -54,6 +54,13 @@ extern unsigned long __FIXADDR_TOP; */ struct cpu_entry_area { char gdt[PAGE_SIZE]; + + /* + * The GDT is just below cpu_tss and thus serves (on x86_64) as a + * a read-only guard page for the SYSENTER stack at the bottom + * of the TSS region. + */ + struct tss_struct tss; }; #define CPU_ENTRY_AREA_PAGES (sizeof(struct cpu_entry_area) / PAGE_SIZE) diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c index b275863128eb..55858b277cf6 100644 --- a/arch/x86/kernel/asm-offsets.c +++ b/arch/x86/kernel/asm-offsets.c @@ -98,4 +98,7 @@ void common(void) { OFFSET(CPU_TSS_SYSENTER_stack, tss_struct, SYSENTER_stack); /* Size of SYSENTER_stack */ DEFINE(SIZEOF_SYSENTER_stack, sizeof(((struct tss_struct *)0)->SYSENTER_stack)); + + /* Layout info for cpu_entry_area */ + OFFSET(CPU_ENTRY_AREA_tss, cpu_entry_area, tss); } diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 60b2dfd2a58b..e5837bd6c672 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -466,6 +466,22 @@ void load_percpu_segment(int cpu) load_stack_canary_segment(); } +static void set_percpu_fixmap_pages(int fixmap_index, void *ptr, + int pages, pgprot_t prot) +{ + int i; + + for (i = 0; i < pages; i++) { + __set_fixmap(fixmap_index - i, + per_cpu_ptr_to_phys(ptr + i * PAGE_SIZE), prot); + } +} + +#ifdef CONFIG_X86_32 +/* The 32-bit entry code needs to find cpu_entry_area. */ +DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); +#endif + /* Setup the fixmap mappings only once per-processor */ static inline void setup_cpu_entry_area(int cpu) { @@ -507,7 +523,15 @@ static inline void setup_cpu_entry_area(int cpu) */ BUILD_BUG_ON((offsetof(struct tss_struct, x86_tss) ^ offsetofend(struct tss_struct, x86_tss)) & PAGE_MASK); + BUILD_BUG_ON(sizeof(struct tss_struct) % PAGE_SIZE != 0); + set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, tss), + &per_cpu(cpu_tss, cpu), + sizeof(struct tss_struct) / PAGE_SIZE, + PAGE_KERNEL); +#ifdef CONFIG_X86_32 + this_cpu_write(cpu_entry_area, get_cpu_entry_area(cpu)); +#endif } /* Load the original GDT from the per-cpu structure */ @@ -1257,7 +1281,8 @@ void enable_sep_cpu(void) wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); wrmsr(MSR_IA32_SYSENTER_ESP, - (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), + (unsigned long)&get_cpu_entry_area(cpu)->tss + + offsetofend(struct tss_struct, SYSENTER_stack), 0); wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); @@ -1370,6 +1395,8 @@ static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks /* May not be marked __init: used by software suspend */ void syscall_init(void) { + int cpu = smp_processor_id(); + wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); @@ -1383,7 +1410,7 @@ void syscall_init(void) */ wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); wrmsrl_safe(MSR_IA32_SYSENTER_ESP, - (unsigned long)this_cpu_ptr(&cpu_tss) + + (unsigned long)&get_cpu_entry_area(cpu)->tss + offsetofend(struct tss_struct, SYSENTER_stack)); wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); #else @@ -1593,11 +1620,13 @@ void cpu_init(void) initialize_tlbstate_and_flush(); enter_lazy_tlb(&init_mm, me); + setup_cpu_entry_area(cpu); + /* * Initialize the TSS. Don't bother initializing sp0, as the initial * task never enters user mode. */ - set_tss_desc(cpu, &t->x86_tss); + set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); load_TR_desc(); load_mm_ldt(&init_mm); @@ -1610,7 +1639,6 @@ void cpu_init(void) if (is_uv_system()) uv_cpu_init(); - setup_cpu_entry_area(cpu); load_fixmap_gdt(cpu); } @@ -1651,11 +1679,13 @@ void cpu_init(void) initialize_tlbstate_and_flush(); enter_lazy_tlb(&init_mm, curr); + setup_cpu_entry_area(cpu); + /* * Initialize the TSS. Don't bother initializing sp0, as the initial * task never enters user mode. */ - set_tss_desc(cpu, &t->x86_tss); + set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); load_TR_desc(); load_mm_ldt(&init_mm); @@ -1672,7 +1702,6 @@ void cpu_init(void) fpu__init_cpu(); - setup_cpu_entry_area(cpu); load_fixmap_gdt(cpu); } #endif diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index 64f8ed2a4827..60267850125e 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -45,7 +45,8 @@ bool in_task_stack(unsigned long *stack, struct task_struct *task, bool in_sysenter_stack(unsigned long *stack, struct stack_info *info) { - struct tss_struct *tss = this_cpu_ptr(&cpu_tss); + int cpu = smp_processor_id(); + struct tss_struct *tss = &get_cpu_entry_area(cpu)->tss; /* Treat the canary as part of the stack for unwinding purposes. */ void *begin = &tss->SYSENTER_stack_canary; diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 2abe0073b573..62ee4362e1c1 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -2291,7 +2291,7 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) * processors. See 22.2.4. */ vmcs_writel(HOST_TR_BASE, - (unsigned long)this_cpu_ptr(&cpu_tss.x86_tss)); + (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ /* diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index 50593e138281..04d5157fe7f8 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -160,18 +160,19 @@ static void do_fpu_end(void) static void fix_processor_context(void) { int cpu = smp_processor_id(); - struct tss_struct *t = &per_cpu(cpu_tss, cpu); #ifdef CONFIG_X86_64 struct desc_struct *desc = get_cpu_gdt_rw(cpu); tss_desc tss; #endif /* - * This just modifies memory; should not be necessary. But... This is - * necessary, because 386 hardware has concept of busy TSS or some - * similar stupidity. + * We need to reload TR, which requires that we change the + * GDT entry to indicate "available" first. + * + * XXX: This could probably all be replaced by a call to + * force_reload_TR(). */ - set_tss_desc(cpu, &t->x86_tss); + set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); #ifdef CONFIG_X86_64 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc)); -- GitLab From 9aaefe7b59ae00605256a7d6bd1c1456432495fc Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:21 +0100 Subject: [PATCH 1658/2547] x86/entry/64: Separate cpu_current_top_of_stack from TSS.sp0 On 64-bit kernels, we used to assume that TSS.sp0 was the current top of stack. With the addition of an entry trampoline, this will no longer be the case. Store the current top of stack in TSS.sp1, which is otherwise unused but shares the same cacheline. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150606.050864668@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/processor.h | 18 +++++++++++++----- arch/x86/include/asm/thread_info.h | 2 +- arch/x86/kernel/asm-offsets_64.c | 1 + arch/x86/kernel/process.c | 10 ++++++++++ arch/x86/kernel/process_64.c | 1 + 5 files changed, 26 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 759051251664..b0cf0612a454 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -309,7 +309,13 @@ struct x86_hw_tss { struct x86_hw_tss { u32 reserved1; u64 sp0; + + /* + * We store cpu_current_top_of_stack in sp1 so it's always accessible. + * Linux does not use ring 1, so sp1 is not otherwise needed. + */ u64 sp1; + u64 sp2; u64 reserved2; u64 ist[7]; @@ -368,6 +374,8 @@ DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss); #ifdef CONFIG_X86_32 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); +#else +#define cpu_current_top_of_stack cpu_tss.x86_tss.sp1 #endif /* @@ -539,12 +547,12 @@ static inline void native_swapgs(void) static inline unsigned long current_top_of_stack(void) { -#ifdef CONFIG_X86_64 - return this_cpu_read_stable(cpu_tss.x86_tss.sp0); -#else - /* sp0 on x86_32 is special in and around vm86 mode. */ + /* + * We can't read directly from tss.sp0: sp0 on x86_32 is special in + * and around vm86 mode and sp0 on x86_64 is special because of the + * entry trampoline. + */ return this_cpu_read_stable(cpu_current_top_of_stack); -#endif } static inline bool on_thread_stack(void) diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index 70f425947dc5..44a04999791e 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -207,7 +207,7 @@ static inline int arch_within_stack_frames(const void * const stack, #else /* !__ASSEMBLY__ */ #ifdef CONFIG_X86_64 -# define cpu_current_top_of_stack (cpu_tss + TSS_sp0) +# define cpu_current_top_of_stack (cpu_tss + TSS_sp1) #endif #endif diff --git a/arch/x86/kernel/asm-offsets_64.c b/arch/x86/kernel/asm-offsets_64.c index e3a5175a444b..bf51e51d808d 100644 --- a/arch/x86/kernel/asm-offsets_64.c +++ b/arch/x86/kernel/asm-offsets_64.c @@ -66,6 +66,7 @@ int main(void) OFFSET(TSS_ist, tss_struct, x86_tss.ist); OFFSET(TSS_sp0, tss_struct, x86_tss.sp0); + OFFSET(TSS_sp1, tss_struct, x86_tss.sp1); BLANK(); #ifdef CONFIG_CC_STACKPROTECTOR diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 35d674157fda..86e83762e3b3 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -56,6 +56,16 @@ __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { * Poison it. */ .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, + +#ifdef CONFIG_X86_64 + /* + * .sp1 is cpu_current_top_of_stack. The init task never + * runs user code, but cpu_current_top_of_stack should still + * be well defined before the first context switch. + */ + .sp1 = TOP_OF_INIT_STACK, +#endif + #ifdef CONFIG_X86_32 .ss0 = __KERNEL_DS, .ss1 = __KERNEL_CS, diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 01b119bebb68..157f81816915 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -461,6 +461,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) * Switch the PDA and FPU contexts. */ this_cpu_write(current_task, next_p); + this_cpu_write(cpu_current_top_of_stack, task_top_of_stack(next_p)); /* Reload sp0. */ update_sp0(next_p); -- GitLab From 6d9256f0a89eaff97fca6006100bcaea8d1d8bdb Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:22 +0100 Subject: [PATCH 1659/2547] x86/espfix/64: Stop assuming that pt_regs is on the entry stack When we start using an entry trampoline, a #GP from userspace will be delivered on the entry stack, not on the task stack. Fix the espfix64 #DF fixup to set up #GP according to TSS.SP0, rather than assuming that pt_regs + 1 == SP0. This won't change anything without an entry stack, but it will make the code continue to work when an entry stack is added. While we're at it, improve the comments to explain what's actually going on. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150606.130778051@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/kernel/traps.c | 37 ++++++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index d3e3bbd5d3a0..f0029d17b14b 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -348,9 +348,15 @@ dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) /* * If IRET takes a non-IST fault on the espfix64 stack, then we - * end up promoting it to a doublefault. In that case, modify - * the stack to make it look like we just entered the #GP - * handler from user space, similar to bad_iret. + * end up promoting it to a doublefault. In that case, take + * advantage of the fact that we're not using the normal (TSS.sp0) + * stack right now. We can write a fake #GP(0) frame at TSS.sp0 + * and then modify our own IRET frame so that, when we return, + * we land directly at the #GP(0) vector with the stack already + * set up according to its expectations. + * + * The net result is that our #GP handler will think that we + * entered from usermode with the bad user context. * * No need for ist_enter here because we don't use RCU. */ @@ -358,13 +364,26 @@ dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) regs->cs == __KERNEL_CS && regs->ip == (unsigned long)native_irq_return_iret) { - struct pt_regs *normal_regs = task_pt_regs(current); + struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss.x86_tss.sp0) - 1; + + /* + * regs->sp points to the failing IRET frame on the + * ESPFIX64 stack. Copy it to the entry stack. This fills + * in gpregs->ss through gpregs->ip. + * + */ + memmove(&gpregs->ip, (void *)regs->sp, 5*8); + gpregs->orig_ax = 0; /* Missing (lost) #GP error code */ - /* Fake a #GP(0) from userspace. */ - memmove(&normal_regs->ip, (void *)regs->sp, 5*8); - normal_regs->orig_ax = 0; /* Missing (lost) #GP error code */ + /* + * Adjust our frame so that we return straight to the #GP + * vector with the expected RSP value. This is safe because + * we won't enable interupts or schedule before we invoke + * general_protection, so nothing will clobber the stack + * frame we just set up. + */ regs->ip = (unsigned long)general_protection; - regs->sp = (unsigned long)&normal_regs->orig_ax; + regs->sp = (unsigned long)&gpregs->orig_ax; return; } @@ -389,7 +408,7 @@ dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) * * Processors update CR2 whenever a page fault is detected. If a * second page fault occurs while an earlier page fault is being - * deliv- ered, the faulting linear address of the second fault will + * delivered, the faulting linear address of the second fault will * overwrite the contents of CR2 (replacing the previous * address). These updates to CR2 occur even if the page fault * results in a double fault or occurs during the delivery of a -- GitLab From 7f2590a110b837af5679d08fc25c6227c5a8c497 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:23 +0100 Subject: [PATCH 1660/2547] x86/entry/64: Use a per-CPU trampoline stack for IDT entries Historically, IDT entries from usermode have always gone directly to the running task's kernel stack. Rearrange it so that we enter on a per-CPU trampoline stack and then manually switch to the task's stack. This touches a couple of extra cachelines, but it gives us a chance to run some code before we touch the kernel stack. The asm isn't exactly beautiful, but I think that fully refactoring it can wait. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Reviewed-by: Thomas Gleixner Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150606.225330557@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/entry/entry_64.S | 67 ++++++++++++++++++++++++-------- arch/x86/entry/entry_64_compat.S | 5 ++- arch/x86/include/asm/switch_to.h | 4 +- arch/x86/include/asm/traps.h | 1 - arch/x86/kernel/cpu/common.c | 6 ++- arch/x86/kernel/traps.c | 21 +++++----- 6 files changed, 72 insertions(+), 32 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 32306788821c..35b8e949ac2f 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -560,6 +560,13 @@ END(irq_entries_start) /* 0(%rsp): ~(interrupt number) */ .macro interrupt func cld + + testb $3, CS-ORIG_RAX(%rsp) + jz 1f + SWAPGS + call switch_to_thread_stack +1: + ALLOC_PT_GPREGS_ON_STACK SAVE_C_REGS SAVE_EXTRA_REGS @@ -569,12 +576,8 @@ END(irq_entries_start) jz 1f /* - * IRQ from user mode. Switch to kernel gsbase and inform context - * tracking that we're in kernel mode. - */ - SWAPGS - - /* + * IRQ from user mode. + * * We need to tell lockdep that IRQs are off. We can't do this until * we fix gsbase, and we should do it before enter_from_user_mode * (which can take locks). Since TRACE_IRQS_OFF idempotent, @@ -828,6 +831,32 @@ apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt */ #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss) + (TSS_ist + ((x) - 1) * 8) +/* + * Switch to the thread stack. This is called with the IRET frame and + * orig_ax on the stack. (That is, RDI..R12 are not on the stack and + * space has not been allocated for them.) + */ +ENTRY(switch_to_thread_stack) + UNWIND_HINT_FUNC + + pushq %rdi + movq %rsp, %rdi + movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp + UNWIND_HINT sp_offset=16 sp_reg=ORC_REG_DI + + pushq 7*8(%rdi) /* regs->ss */ + pushq 6*8(%rdi) /* regs->rsp */ + pushq 5*8(%rdi) /* regs->eflags */ + pushq 4*8(%rdi) /* regs->cs */ + pushq 3*8(%rdi) /* regs->ip */ + pushq 2*8(%rdi) /* regs->orig_ax */ + pushq 8(%rdi) /* return address */ + UNWIND_HINT_FUNC + + movq (%rdi), %rdi + ret +END(switch_to_thread_stack) + .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 ENTRY(\sym) UNWIND_HINT_IRET_REGS offset=\has_error_code*8 @@ -845,11 +874,12 @@ ENTRY(\sym) ALLOC_PT_GPREGS_ON_STACK - .if \paranoid - .if \paranoid == 1 + .if \paranoid < 2 testb $3, CS(%rsp) /* If coming from userspace, switch stacks */ - jnz 1f + jnz .Lfrom_usermode_switch_stack_\@ .endif + + .if \paranoid call paranoid_entry .else call error_entry @@ -891,20 +921,15 @@ ENTRY(\sym) jmp error_exit .endif - .if \paranoid == 1 + .if \paranoid < 2 /* - * Paranoid entry from userspace. Switch stacks and treat it + * Entry from userspace. Switch stacks and treat it * as a normal entry. This means that paranoid handlers * run in real process context if user_mode(regs). */ -1: +.Lfrom_usermode_switch_stack_\@: call error_entry - - movq %rsp, %rdi /* pt_regs pointer */ - call sync_regs - movq %rax, %rsp /* switch stack */ - movq %rsp, %rdi /* pt_regs pointer */ .if \has_error_code @@ -1165,6 +1190,14 @@ ENTRY(error_entry) SWAPGS .Lerror_entry_from_usermode_after_swapgs: + /* Put us onto the real thread stack. */ + popq %r12 /* save return addr in %12 */ + movq %rsp, %rdi /* arg0 = pt_regs pointer */ + call sync_regs + movq %rax, %rsp /* switch stack */ + ENCODE_FRAME_POINTER + pushq %r12 + /* * We need to tell lockdep that IRQs are off. We can't do this until * we fix gsbase, and we should do it before enter_from_user_mode diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_compat.S index dcc6987f9bae..95ad40eb7eff 100644 --- a/arch/x86/entry/entry_64_compat.S +++ b/arch/x86/entry/entry_64_compat.S @@ -306,8 +306,11 @@ ENTRY(entry_INT80_compat) */ movl %eax, %eax - /* Construct struct pt_regs on stack (iret frame is already on stack) */ pushq %rax /* pt_regs->orig_ax */ + + /* switch to thread stack expects orig_ax to be pushed */ + call switch_to_thread_stack + pushq %rdi /* pt_regs->di */ pushq %rsi /* pt_regs->si */ pushq %rdx /* pt_regs->dx */ diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h index 8c6bd6863db9..cbc71e73bd32 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -90,10 +90,12 @@ static inline void refresh_sysenter_cs(struct thread_struct *thread) /* This is used when switching tasks or entering/exiting vm86 mode. */ static inline void update_sp0(struct task_struct *task) { + /* On x86_64, sp0 always points to the entry trampoline stack, which is constant: */ #ifdef CONFIG_X86_32 load_sp0(task->thread.sp0); #else - load_sp0(task_top_of_stack(task)); + if (static_cpu_has(X86_FEATURE_XENPV)) + load_sp0(task_top_of_stack(task)); #endif } diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index 1fadd310ff68..31051f35cbb7 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -75,7 +75,6 @@ dotraplinkage void do_segment_not_present(struct pt_regs *, long); dotraplinkage void do_stack_segment(struct pt_regs *, long); #ifdef CONFIG_X86_64 dotraplinkage void do_double_fault(struct pt_regs *, long); -asmlinkage struct pt_regs *sync_regs(struct pt_regs *); #endif dotraplinkage void do_general_protection(struct pt_regs *, long); dotraplinkage void do_page_fault(struct pt_regs *, unsigned long); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index e5837bd6c672..57968880e39b 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1623,11 +1623,13 @@ void cpu_init(void) setup_cpu_entry_area(cpu); /* - * Initialize the TSS. Don't bother initializing sp0, as the initial - * task never enters user mode. + * Initialize the TSS. sp0 points to the entry trampoline stack + * regardless of what task is running. */ set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); load_TR_desc(); + load_sp0((unsigned long)&get_cpu_entry_area(cpu)->tss + + offsetofend(struct tss_struct, SYSENTER_stack)); load_mm_ldt(&init_mm); diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index f0029d17b14b..ee9ca0ad4388 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -619,14 +619,15 @@ NOKPROBE_SYMBOL(do_int3); #ifdef CONFIG_X86_64 /* - * Help handler running on IST stack to switch off the IST stack if the - * interrupted code was in user mode. The actual stack switch is done in - * entry_64.S + * Help handler running on a per-cpu (IST or entry trampoline) stack + * to switch to the normal thread stack if the interrupted code was in + * user mode. The actual stack switch is done in entry_64.S */ asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs) { - struct pt_regs *regs = task_pt_regs(current); - *regs = *eregs; + struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1; + if (regs != eregs) + *regs = *eregs; return regs; } NOKPROBE_SYMBOL(sync_regs); @@ -642,13 +643,13 @@ struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s) /* * This is called from entry_64.S early in handling a fault * caused by a bad iret to user mode. To handle the fault - * correctly, we want move our stack frame to task_pt_regs - * and we want to pretend that the exception came from the - * iret target. + * correctly, we want to move our stack frame to where it would + * be had we entered directly on the entry stack (rather than + * just below the IRET frame) and we want to pretend that the + * exception came from the IRET target. */ struct bad_iret_stack *new_stack = - container_of(task_pt_regs(current), - struct bad_iret_stack, regs); + (struct bad_iret_stack *)this_cpu_read(cpu_tss.x86_tss.sp0) - 1; /* Copy the IRET target to the new stack. */ memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8); -- GitLab From 3e3b9293d392c577b62e24e4bc9982320438e749 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:24 +0100 Subject: [PATCH 1661/2547] x86/entry/64: Return to userspace from the trampoline stack By itself, this is useless. It gives us the ability to run some final code before exit that cannnot run on the kernel stack. This could include a CR3 switch a la PAGE_TABLE_ISOLATION or some kernel stack erasing, for example. (Or even weird things like *changing* which kernel stack gets used as an ASLR-strengthening mechanism.) The SYSRET32 path is not covered yet. It could be in the future or we could just ignore it and force the slow path if needed. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150606.306546484@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/entry/entry_64.S | 55 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 51 insertions(+), 4 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 35b8e949ac2f..42a9379f7acb 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -326,8 +326,24 @@ syscall_return_via_sysret: popq %rsi /* skip rcx */ popq %rdx popq %rsi + + /* + * Now all regs are restored except RSP and RDI. + * Save old stack pointer and switch to trampoline stack. + */ + movq %rsp, %rdi + movq PER_CPU_VAR(cpu_tss + TSS_sp0), %rsp + + pushq RSP-RDI(%rdi) /* RSP */ + pushq (%rdi) /* RDI */ + + /* + * We are on the trampoline stack. All regs except RDI are live. + * We can do future final exit work right here. + */ + popq %rdi - movq RSP-ORIG_RAX(%rsp), %rsp + popq %rsp USERGS_SYSRET64 END(entry_SYSCALL_64) @@ -630,10 +646,41 @@ GLOBAL(swapgs_restore_regs_and_return_to_usermode) ud2 1: #endif - SWAPGS POP_EXTRA_REGS - POP_C_REGS - addq $8, %rsp /* skip regs->orig_ax */ + popq %r11 + popq %r10 + popq %r9 + popq %r8 + popq %rax + popq %rcx + popq %rdx + popq %rsi + + /* + * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. + * Save old stack pointer and switch to trampoline stack. + */ + movq %rsp, %rdi + movq PER_CPU_VAR(cpu_tss + TSS_sp0), %rsp + + /* Copy the IRET frame to the trampoline stack. */ + pushq 6*8(%rdi) /* SS */ + pushq 5*8(%rdi) /* RSP */ + pushq 4*8(%rdi) /* EFLAGS */ + pushq 3*8(%rdi) /* CS */ + pushq 2*8(%rdi) /* RIP */ + + /* Push user RDI on the trampoline stack. */ + pushq (%rdi) + + /* + * We are on the trampoline stack. All regs except RDI are live. + * We can do future final exit work right here. + */ + + /* Restore RDI. */ + popq %rdi + SWAPGS INTERRUPT_RETURN -- GitLab From 3386bc8aed825e9f1f65ce38df4b109b2019b71a Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:25 +0100 Subject: [PATCH 1662/2547] x86/entry/64: Create a per-CPU SYSCALL entry trampoline Handling SYSCALL is tricky: the SYSCALL handler is entered with every single register (except FLAGS), including RSP, live. It somehow needs to set RSP to point to a valid stack, which means it needs to save the user RSP somewhere and find its own stack pointer. The canonical way to do this is with SWAPGS, which lets us access percpu data using the %gs prefix. With PAGE_TABLE_ISOLATION-like pagetable switching, this is problematic. Without a scratch register, switching CR3 is impossible, so %gs-based percpu memory would need to be mapped in the user pagetables. Doing that without information leaks is difficult or impossible. Instead, use a different sneaky trick. Map a copy of the first part of the SYSCALL asm at a different address for each CPU. Now RIP varies depending on the CPU, so we can use RIP-relative memory access to access percpu memory. By putting the relevant information (one scratch slot and the stack address) at a constant offset relative to RIP, we can make SYSCALL work without relying on %gs. A nice thing about this approach is that we can easily switch it on and off if we want pagetable switching to be configurable. The compat variant of SYSCALL doesn't have this problem in the first place -- there are plenty of scratch registers, since we don't care about preserving r8-r15. This patch therefore doesn't touch SYSCALL32 at all. This patch actually seems to be a small speedup. With this patch, SYSCALL touches an extra cache line and an extra virtual page, but the pipeline no longer stalls waiting for SWAPGS. It seems that, at least in a tight loop, the latter outweights the former. Thanks to David Laight for an optimization tip. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150606.403607157@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/entry/entry_64.S | 58 +++++++++++++++++++++++++++++++++++ arch/x86/include/asm/fixmap.h | 2 ++ arch/x86/kernel/asm-offsets.c | 1 + arch/x86/kernel/cpu/common.c | 15 ++++++++- arch/x86/kernel/vmlinux.lds.S | 9 ++++++ 5 files changed, 84 insertions(+), 1 deletion(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 42a9379f7acb..2582984ffb4b 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -136,6 +136,64 @@ END(native_usergs_sysret64) * with them due to bugs in both AMD and Intel CPUs. */ + .pushsection .entry_trampoline, "ax" + +/* + * The code in here gets remapped into cpu_entry_area's trampoline. This means + * that the assembler and linker have the wrong idea as to where this code + * lives (and, in fact, it's mapped more than once, so it's not even at a + * fixed address). So we can't reference any symbols outside the entry + * trampoline and expect it to work. + * + * Instead, we carefully abuse %rip-relative addressing. + * _entry_trampoline(%rip) refers to the start of the remapped) entry + * trampoline. We can thus find cpu_entry_area with this macro: + */ + +#define CPU_ENTRY_AREA \ + _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip) + +/* The top word of the SYSENTER stack is hot and is usable as scratch space. */ +#define RSP_SCRATCH CPU_ENTRY_AREA_tss + CPU_TSS_SYSENTER_stack + \ + SIZEOF_SYSENTER_stack - 8 + CPU_ENTRY_AREA + +ENTRY(entry_SYSCALL_64_trampoline) + UNWIND_HINT_EMPTY + swapgs + + /* Stash the user RSP. */ + movq %rsp, RSP_SCRATCH + + /* Load the top of the task stack into RSP */ + movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp + + /* Start building the simulated IRET frame. */ + pushq $__USER_DS /* pt_regs->ss */ + pushq RSP_SCRATCH /* pt_regs->sp */ + pushq %r11 /* pt_regs->flags */ + pushq $__USER_CS /* pt_regs->cs */ + pushq %rcx /* pt_regs->ip */ + + /* + * x86 lacks a near absolute jump, and we can't jump to the real + * entry text with a relative jump. We could push the target + * address and then use retq, but this destroys the pipeline on + * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead, + * spill RDI and restore it in a second-stage trampoline. + */ + pushq %rdi + movq $entry_SYSCALL_64_stage2, %rdi + jmp *%rdi +END(entry_SYSCALL_64_trampoline) + + .popsection + +ENTRY(entry_SYSCALL_64_stage2) + UNWIND_HINT_EMPTY + popq %rdi + jmp entry_SYSCALL_64_after_hwframe +END(entry_SYSCALL_64_stage2) + ENTRY(entry_SYSCALL_64) UNWIND_HINT_EMPTY /* diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h index 84558b611ad3..6a699474c2c7 100644 --- a/arch/x86/include/asm/fixmap.h +++ b/arch/x86/include/asm/fixmap.h @@ -61,6 +61,8 @@ struct cpu_entry_area { * of the TSS region. */ struct tss_struct tss; + + char entry_trampoline[PAGE_SIZE]; }; #define CPU_ENTRY_AREA_PAGES (sizeof(struct cpu_entry_area) / PAGE_SIZE) diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c index 55858b277cf6..61b1af88ac07 100644 --- a/arch/x86/kernel/asm-offsets.c +++ b/arch/x86/kernel/asm-offsets.c @@ -101,4 +101,5 @@ void common(void) { /* Layout info for cpu_entry_area */ OFFSET(CPU_ENTRY_AREA_tss, cpu_entry_area, tss); + OFFSET(CPU_ENTRY_AREA_entry_trampoline, cpu_entry_area, entry_trampoline); } diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 57968880e39b..430f950b0b7f 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -486,6 +486,8 @@ DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); static inline void setup_cpu_entry_area(int cpu) { #ifdef CONFIG_X86_64 + extern char _entry_trampoline[]; + /* On 64-bit systems, we use a read-only fixmap GDT. */ pgprot_t gdt_prot = PAGE_KERNEL_RO; #else @@ -532,6 +534,11 @@ static inline void setup_cpu_entry_area(int cpu) #ifdef CONFIG_X86_32 this_cpu_write(cpu_entry_area, get_cpu_entry_area(cpu)); #endif + +#ifdef CONFIG_X86_64 + __set_fixmap(get_cpu_entry_area_index(cpu, entry_trampoline), + __pa_symbol(_entry_trampoline), PAGE_KERNEL_RX); +#endif } /* Load the original GDT from the per-cpu structure */ @@ -1395,10 +1402,16 @@ static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks /* May not be marked __init: used by software suspend */ void syscall_init(void) { + extern char _entry_trampoline[]; + extern char entry_SYSCALL_64_trampoline[]; + int cpu = smp_processor_id(); + unsigned long SYSCALL64_entry_trampoline = + (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + + (entry_SYSCALL_64_trampoline - _entry_trampoline); wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); - wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); + wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); #ifdef CONFIG_IA32_EMULATION wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S index a4009fb9be87..d2a8b5a24a44 100644 --- a/arch/x86/kernel/vmlinux.lds.S +++ b/arch/x86/kernel/vmlinux.lds.S @@ -107,6 +107,15 @@ SECTIONS SOFTIRQENTRY_TEXT *(.fixup) *(.gnu.warning) + +#ifdef CONFIG_X86_64 + . = ALIGN(PAGE_SIZE); + _entry_trampoline = .; + *(.entry_trampoline) + . = ALIGN(PAGE_SIZE); + ASSERT(. - _entry_trampoline == PAGE_SIZE, "entry trampoline is too big"); +#endif + /* End of text section */ _etext = .; } :text = 0x9090 -- GitLab From 40e7f949e0d9a33968ebde5d67f7e3a47c97742a Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:26 +0100 Subject: [PATCH 1663/2547] x86/entry/64: Move the IST stacks into struct cpu_entry_area The IST stacks are needed when an IST exception occurs and are accessed before any kernel code at all runs. Move them into struct cpu_entry_area. The IST stacks are unlike the rest of cpu_entry_area: they're used even for entries from kernel mode. This means that they should be set up before we load the final IDT. Move cpu_entry_area setup to trap_init() for the boot CPU and set it up for all possible CPUs at once in native_smp_prepare_cpus(). Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150606.480598743@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/fixmap.h | 12 ++++++ arch/x86/kernel/cpu/common.c | 74 ++++++++++++++++++++--------------- arch/x86/kernel/traps.c | 3 ++ 3 files changed, 57 insertions(+), 32 deletions(-) diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h index 6a699474c2c7..451da7d9a502 100644 --- a/arch/x86/include/asm/fixmap.h +++ b/arch/x86/include/asm/fixmap.h @@ -63,10 +63,22 @@ struct cpu_entry_area { struct tss_struct tss; char entry_trampoline[PAGE_SIZE]; + +#ifdef CONFIG_X86_64 + /* + * Exception stacks used for IST entries. + * + * In the future, this should have a separate slot for each stack + * with guard pages between them. + */ + char exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]; +#endif }; #define CPU_ENTRY_AREA_PAGES (sizeof(struct cpu_entry_area) / PAGE_SIZE) +extern void setup_cpu_entry_areas(void); + /* * Here we define all the compile-time 'special' virtual * addresses. The point is to have a constant address at diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 430f950b0b7f..fb01a8e5e9b7 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -466,24 +466,36 @@ void load_percpu_segment(int cpu) load_stack_canary_segment(); } -static void set_percpu_fixmap_pages(int fixmap_index, void *ptr, - int pages, pgprot_t prot) -{ - int i; - - for (i = 0; i < pages; i++) { - __set_fixmap(fixmap_index - i, - per_cpu_ptr_to_phys(ptr + i * PAGE_SIZE), prot); - } -} - #ifdef CONFIG_X86_32 /* The 32-bit entry code needs to find cpu_entry_area. */ DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); #endif +#ifdef CONFIG_X86_64 +/* + * Special IST stacks which the CPU switches to when it calls + * an IST-marked descriptor entry. Up to 7 stacks (hardware + * limit), all of them are 4K, except the debug stack which + * is 8K. + */ +static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { + [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, + [DEBUG_STACK - 1] = DEBUG_STKSZ +}; + +static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks + [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); +#endif + +static void __init +set_percpu_fixmap_pages(int idx, void *ptr, int pages, pgprot_t prot) +{ + for ( ; pages; pages--, idx--, ptr += PAGE_SIZE) + __set_fixmap(idx, per_cpu_ptr_to_phys(ptr), prot); +} + /* Setup the fixmap mappings only once per-processor */ -static inline void setup_cpu_entry_area(int cpu) +static void __init setup_cpu_entry_area(int cpu) { #ifdef CONFIG_X86_64 extern char _entry_trampoline[]; @@ -532,15 +544,31 @@ static inline void setup_cpu_entry_area(int cpu) PAGE_KERNEL); #ifdef CONFIG_X86_32 - this_cpu_write(cpu_entry_area, get_cpu_entry_area(cpu)); + per_cpu(cpu_entry_area, cpu) = get_cpu_entry_area(cpu); #endif #ifdef CONFIG_X86_64 + BUILD_BUG_ON(sizeof(exception_stacks) % PAGE_SIZE != 0); + BUILD_BUG_ON(sizeof(exception_stacks) != + sizeof(((struct cpu_entry_area *)0)->exception_stacks)); + set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, exception_stacks), + &per_cpu(exception_stacks, cpu), + sizeof(exception_stacks) / PAGE_SIZE, + PAGE_KERNEL); + __set_fixmap(get_cpu_entry_area_index(cpu, entry_trampoline), __pa_symbol(_entry_trampoline), PAGE_KERNEL_RX); #endif } +void __init setup_cpu_entry_areas(void) +{ + unsigned int cpu; + + for_each_possible_cpu(cpu) + setup_cpu_entry_area(cpu); +} + /* Load the original GDT from the per-cpu structure */ void load_direct_gdt(int cpu) { @@ -1385,20 +1413,6 @@ DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; EXPORT_PER_CPU_SYMBOL(__preempt_count); -/* - * Special IST stacks which the CPU switches to when it calls - * an IST-marked descriptor entry. Up to 7 stacks (hardware - * limit), all of them are 4K, except the debug stack which - * is 8K. - */ -static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { - [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, - [DEBUG_STACK - 1] = DEBUG_STKSZ -}; - -static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks - [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); - /* May not be marked __init: used by software suspend */ void syscall_init(void) { @@ -1607,7 +1621,7 @@ void cpu_init(void) * set up and load the per-CPU TSS */ if (!oist->ist[0]) { - char *estacks = per_cpu(exception_stacks, cpu); + char *estacks = get_cpu_entry_area(cpu)->exception_stacks; for (v = 0; v < N_EXCEPTION_STACKS; v++) { estacks += exception_stack_sizes[v]; @@ -1633,8 +1647,6 @@ void cpu_init(void) initialize_tlbstate_and_flush(); enter_lazy_tlb(&init_mm, me); - setup_cpu_entry_area(cpu); - /* * Initialize the TSS. sp0 points to the entry trampoline stack * regardless of what task is running. @@ -1694,8 +1706,6 @@ void cpu_init(void) initialize_tlbstate_and_flush(); enter_lazy_tlb(&init_mm, curr); - setup_cpu_entry_area(cpu); - /* * Initialize the TSS. Don't bother initializing sp0, as the initial * task never enters user mode. diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index ee9ca0ad4388..3e29aad5c7cc 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -947,6 +947,9 @@ dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code) void __init trap_init(void) { + /* Init cpu_entry_area before IST entries are set up */ + setup_cpu_entry_areas(); + idt_setup_traps(); /* -- GitLab From 7fbbd5cbebf118a9e09f5453f686656a167c3d1c Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:27 +0100 Subject: [PATCH 1664/2547] x86/entry/64: Remove the SYSENTER stack canary Now that the SYSENTER stack has a guard page, there's no need for a canary to detect overflow after the fact. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150606.572577316@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/processor.h | 1 - arch/x86/kernel/dumpstack.c | 3 +-- arch/x86/kernel/process.c | 1 - arch/x86/kernel/traps.c | 7 ------- 4 files changed, 1 insertion(+), 11 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index b0cf0612a454..d34ac13c5866 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -341,7 +341,6 @@ struct tss_struct { * Space for the temporary SYSENTER stack, used for SYSENTER * and the entry trampoline as well. */ - unsigned long SYSENTER_stack_canary; unsigned long SYSENTER_stack[64]; /* diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index 60267850125e..ae1ce2e3f132 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -48,8 +48,7 @@ bool in_sysenter_stack(unsigned long *stack, struct stack_info *info) int cpu = smp_processor_id(); struct tss_struct *tss = &get_cpu_entry_area(cpu)->tss; - /* Treat the canary as part of the stack for unwinding purposes. */ - void *begin = &tss->SYSENTER_stack_canary; + void *begin = &tss->SYSENTER_stack; void *end = (void *)&tss->SYSENTER_stack + sizeof(tss->SYSENTER_stack); if ((void *)stack < begin || (void *)stack >= end) diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 86e83762e3b3..6a04287f222b 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -81,7 +81,6 @@ __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { */ .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, #endif - .SYSENTER_stack_canary = STACK_END_MAGIC, }; EXPORT_PER_CPU_SYMBOL(cpu_tss); diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 3e29aad5c7cc..5ade4f89a6d1 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -814,13 +814,6 @@ dotraplinkage void do_debug(struct pt_regs *regs, long error_code) debug_stack_usage_dec(); exit: - /* - * This is the most likely code path that involves non-trivial use - * of the SYSENTER stack. Check that we haven't overrun it. - */ - WARN(this_cpu_read(cpu_tss.SYSENTER_stack_canary) != STACK_END_MAGIC, - "Overran or corrupted SYSENTER stack\n"); - ist_exit(regs); } NOKPROBE_SYMBOL(do_debug); -- GitLab From 0f9a48100fba3f189724ae88a450c2261bf91c80 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:28 +0100 Subject: [PATCH 1665/2547] x86/entry: Clean up the SYSENTER_stack code The existing code was a mess, mainly because C arrays are nasty. Turn SYSENTER_stack into a struct, add a helper to find it, and do all the obvious cleanups this enables. Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150606.653244723@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/entry/entry_32.S | 4 ++-- arch/x86/entry/entry_64.S | 2 +- arch/x86/include/asm/fixmap.h | 5 +++++ arch/x86/include/asm/processor.h | 6 +++++- arch/x86/kernel/asm-offsets.c | 6 ++---- arch/x86/kernel/cpu/common.c | 14 +++----------- arch/x86/kernel/dumpstack.c | 7 +++---- 7 files changed, 21 insertions(+), 23 deletions(-) diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S index 0ab316c46806..3629bcbf85a2 100644 --- a/arch/x86/entry/entry_32.S +++ b/arch/x86/entry/entry_32.S @@ -942,7 +942,7 @@ ENTRY(debug) /* Are we currently on the SYSENTER stack? */ movl PER_CPU_VAR(cpu_entry_area), %ecx - addl $CPU_ENTRY_AREA_tss + CPU_TSS_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx + addl $CPU_ENTRY_AREA_tss + TSS_STRUCT_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx subl %eax, %ecx /* ecx = (end of SYSENTER_stack) - esp */ cmpl $SIZEOF_SYSENTER_stack, %ecx jb .Ldebug_from_sysenter_stack @@ -986,7 +986,7 @@ ENTRY(nmi) /* Are we currently on the SYSENTER stack? */ movl PER_CPU_VAR(cpu_entry_area), %ecx - addl $CPU_ENTRY_AREA_tss + CPU_TSS_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx + addl $CPU_ENTRY_AREA_tss + TSS_STRUCT_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx subl %eax, %ecx /* ecx = (end of SYSENTER_stack) - esp */ cmpl $SIZEOF_SYSENTER_stack, %ecx jb .Lnmi_from_sysenter_stack diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 2582984ffb4b..575b184f377f 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -154,7 +154,7 @@ END(native_usergs_sysret64) _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip) /* The top word of the SYSENTER stack is hot and is usable as scratch space. */ -#define RSP_SCRATCH CPU_ENTRY_AREA_tss + CPU_TSS_SYSENTER_stack + \ +#define RSP_SCRATCH CPU_ENTRY_AREA_tss + TSS_STRUCT_SYSENTER_stack + \ SIZEOF_SYSENTER_stack - 8 + CPU_ENTRY_AREA ENTRY(entry_SYSCALL_64_trampoline) diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h index 451da7d9a502..cc5d98bdca37 100644 --- a/arch/x86/include/asm/fixmap.h +++ b/arch/x86/include/asm/fixmap.h @@ -245,5 +245,10 @@ static inline struct cpu_entry_area *get_cpu_entry_area(int cpu) return (struct cpu_entry_area *)__fix_to_virt(__get_cpu_entry_area_page_index(cpu, 0)); } +static inline struct SYSENTER_stack *cpu_SYSENTER_stack(int cpu) +{ + return &get_cpu_entry_area(cpu)->tss.SYSENTER_stack; +} + #endif /* !__ASSEMBLY__ */ #endif /* _ASM_X86_FIXMAP_H */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index d34ac13c5866..f933869470b8 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -336,12 +336,16 @@ struct x86_hw_tss { #define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss)) #define INVALID_IO_BITMAP_OFFSET 0x8000 +struct SYSENTER_stack { + unsigned long words[64]; +}; + struct tss_struct { /* * Space for the temporary SYSENTER stack, used for SYSENTER * and the entry trampoline as well. */ - unsigned long SYSENTER_stack[64]; + struct SYSENTER_stack SYSENTER_stack; /* * The fixed hardware portion. This must not cross a page boundary diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c index 61b1af88ac07..46c0995344aa 100644 --- a/arch/x86/kernel/asm-offsets.c +++ b/arch/x86/kernel/asm-offsets.c @@ -94,10 +94,8 @@ void common(void) { BLANK(); DEFINE(PTREGS_SIZE, sizeof(struct pt_regs)); - /* Offset from cpu_tss to SYSENTER_stack */ - OFFSET(CPU_TSS_SYSENTER_stack, tss_struct, SYSENTER_stack); - /* Size of SYSENTER_stack */ - DEFINE(SIZEOF_SYSENTER_stack, sizeof(((struct tss_struct *)0)->SYSENTER_stack)); + OFFSET(TSS_STRUCT_SYSENTER_stack, tss_struct, SYSENTER_stack); + DEFINE(SIZEOF_SYSENTER_stack, sizeof(struct SYSENTER_stack)); /* Layout info for cpu_entry_area */ OFFSET(CPU_ENTRY_AREA_tss, cpu_entry_area, tss); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index fb01a8e5e9b7..3de7480e4f32 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1314,12 +1314,7 @@ void enable_sep_cpu(void) tss->x86_tss.ss1 = __KERNEL_CS; wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); - - wrmsr(MSR_IA32_SYSENTER_ESP, - (unsigned long)&get_cpu_entry_area(cpu)->tss + - offsetofend(struct tss_struct, SYSENTER_stack), - 0); - + wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_SYSENTER_stack(cpu) + 1), 0); wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); put_cpu(); @@ -1436,9 +1431,7 @@ void syscall_init(void) * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). */ wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); - wrmsrl_safe(MSR_IA32_SYSENTER_ESP, - (unsigned long)&get_cpu_entry_area(cpu)->tss + - offsetofend(struct tss_struct, SYSENTER_stack)); + wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_SYSENTER_stack(cpu) + 1)); wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); #else wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); @@ -1653,8 +1646,7 @@ void cpu_init(void) */ set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); load_TR_desc(); - load_sp0((unsigned long)&get_cpu_entry_area(cpu)->tss + - offsetofend(struct tss_struct, SYSENTER_stack)); + load_sp0((unsigned long)(cpu_SYSENTER_stack(cpu) + 1)); load_mm_ldt(&init_mm); diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index ae1ce2e3f132..bbd6d986e2d0 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -45,11 +45,10 @@ bool in_task_stack(unsigned long *stack, struct task_struct *task, bool in_sysenter_stack(unsigned long *stack, struct stack_info *info) { - int cpu = smp_processor_id(); - struct tss_struct *tss = &get_cpu_entry_area(cpu)->tss; + struct SYSENTER_stack *ss = cpu_SYSENTER_stack(smp_processor_id()); - void *begin = &tss->SYSENTER_stack; - void *end = (void *)&tss->SYSENTER_stack + sizeof(tss->SYSENTER_stack); + void *begin = ss; + void *end = ss + 1; if ((void *)stack < begin || (void *)stack >= end) return false; -- GitLab From c482feefe1aeb150156248ba0fd3e029bc886605 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 4 Dec 2017 15:07:29 +0100 Subject: [PATCH 1666/2547] x86/entry/64: Make cpu_entry_area.tss read-only The TSS is a fairly juicy target for exploits, and, now that the TSS is in the cpu_entry_area, it's no longer protected by kASLR. Make it read-only on x86_64. On x86_32, it can't be RO because it's written by the CPU during task switches, and we use a task gate for double faults. I'd also be nervous about errata if we tried to make it RO even on configurations without double fault handling. [ tglx: AMD confirmed that there is no problem on 64-bit with TSS RO. So it's probably safe to assume that it's a non issue, though Intel might have been creative in that area. Still waiting for confirmation. ] Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Kees Cook Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150606.733700132@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/entry/entry_32.S | 4 ++-- arch/x86/entry/entry_64.S | 8 ++++---- arch/x86/include/asm/fixmap.h | 13 +++++++++---- arch/x86/include/asm/processor.h | 17 ++++++++--------- arch/x86/include/asm/switch_to.h | 4 ++-- arch/x86/include/asm/thread_info.h | 2 +- arch/x86/kernel/asm-offsets.c | 5 ++--- arch/x86/kernel/asm-offsets_32.c | 4 ++-- arch/x86/kernel/cpu/common.c | 29 +++++++++++++++++++---------- arch/x86/kernel/ioport.c | 2 +- arch/x86/kernel/process.c | 6 +++--- arch/x86/kernel/process_32.c | 2 +- arch/x86/kernel/process_64.c | 2 +- arch/x86/kernel/traps.c | 4 ++-- arch/x86/lib/delay.c | 4 ++-- arch/x86/xen/enlighten_pv.c | 2 +- 16 files changed, 60 insertions(+), 48 deletions(-) diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S index 3629bcbf85a2..bd8b57a5c874 100644 --- a/arch/x86/entry/entry_32.S +++ b/arch/x86/entry/entry_32.S @@ -942,7 +942,7 @@ ENTRY(debug) /* Are we currently on the SYSENTER stack? */ movl PER_CPU_VAR(cpu_entry_area), %ecx - addl $CPU_ENTRY_AREA_tss + TSS_STRUCT_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx + addl $CPU_ENTRY_AREA_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx subl %eax, %ecx /* ecx = (end of SYSENTER_stack) - esp */ cmpl $SIZEOF_SYSENTER_stack, %ecx jb .Ldebug_from_sysenter_stack @@ -986,7 +986,7 @@ ENTRY(nmi) /* Are we currently on the SYSENTER stack? */ movl PER_CPU_VAR(cpu_entry_area), %ecx - addl $CPU_ENTRY_AREA_tss + TSS_STRUCT_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx + addl $CPU_ENTRY_AREA_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx subl %eax, %ecx /* ecx = (end of SYSENTER_stack) - esp */ cmpl $SIZEOF_SYSENTER_stack, %ecx jb .Lnmi_from_sysenter_stack diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 575b184f377f..2812ce043a7a 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -154,7 +154,7 @@ END(native_usergs_sysret64) _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip) /* The top word of the SYSENTER stack is hot and is usable as scratch space. */ -#define RSP_SCRATCH CPU_ENTRY_AREA_tss + TSS_STRUCT_SYSENTER_stack + \ +#define RSP_SCRATCH CPU_ENTRY_AREA_SYSENTER_stack + \ SIZEOF_SYSENTER_stack - 8 + CPU_ENTRY_AREA ENTRY(entry_SYSCALL_64_trampoline) @@ -390,7 +390,7 @@ syscall_return_via_sysret: * Save old stack pointer and switch to trampoline stack. */ movq %rsp, %rdi - movq PER_CPU_VAR(cpu_tss + TSS_sp0), %rsp + movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp pushq RSP-RDI(%rdi) /* RSP */ pushq (%rdi) /* RDI */ @@ -719,7 +719,7 @@ GLOBAL(swapgs_restore_regs_and_return_to_usermode) * Save old stack pointer and switch to trampoline stack. */ movq %rsp, %rdi - movq PER_CPU_VAR(cpu_tss + TSS_sp0), %rsp + movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp /* Copy the IRET frame to the trampoline stack. */ pushq 6*8(%rdi) /* SS */ @@ -934,7 +934,7 @@ apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt /* * Exception entry points. */ -#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss) + (TSS_ist + ((x) - 1) * 8) +#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8) /* * Switch to the thread stack. This is called with the IRET frame and diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h index cc5d98bdca37..94fc4fa14127 100644 --- a/arch/x86/include/asm/fixmap.h +++ b/arch/x86/include/asm/fixmap.h @@ -56,9 +56,14 @@ struct cpu_entry_area { char gdt[PAGE_SIZE]; /* - * The GDT is just below cpu_tss and thus serves (on x86_64) as a - * a read-only guard page for the SYSENTER stack at the bottom - * of the TSS region. + * The GDT is just below SYSENTER_stack and thus serves (on x86_64) as + * a a read-only guard page. + */ + struct SYSENTER_stack_page SYSENTER_stack_page; + + /* + * On x86_64, the TSS is mapped RO. On x86_32, it's mapped RW because + * we need task switches to work, and task switches write to the TSS. */ struct tss_struct tss; @@ -247,7 +252,7 @@ static inline struct cpu_entry_area *get_cpu_entry_area(int cpu) static inline struct SYSENTER_stack *cpu_SYSENTER_stack(int cpu) { - return &get_cpu_entry_area(cpu)->tss.SYSENTER_stack; + return &get_cpu_entry_area(cpu)->SYSENTER_stack_page.stack; } #endif /* !__ASSEMBLY__ */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index f933869470b8..e8991d7f7034 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -340,13 +340,11 @@ struct SYSENTER_stack { unsigned long words[64]; }; -struct tss_struct { - /* - * Space for the temporary SYSENTER stack, used for SYSENTER - * and the entry trampoline as well. - */ - struct SYSENTER_stack SYSENTER_stack; +struct SYSENTER_stack_page { + struct SYSENTER_stack stack; +} __aligned(PAGE_SIZE); +struct tss_struct { /* * The fixed hardware portion. This must not cross a page boundary * at risk of violating the SDM's advice and potentially triggering @@ -363,7 +361,7 @@ struct tss_struct { unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; } __aligned(PAGE_SIZE); -DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss); +DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); /* * sizeof(unsigned long) coming from an extra "long" at the end @@ -378,7 +376,8 @@ DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss); #ifdef CONFIG_X86_32 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); #else -#define cpu_current_top_of_stack cpu_tss.x86_tss.sp1 +/* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */ +#define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1 #endif /* @@ -538,7 +537,7 @@ static inline void native_set_iopl_mask(unsigned mask) static inline void native_load_sp0(unsigned long sp0) { - this_cpu_write(cpu_tss.x86_tss.sp0, sp0); + this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); } static inline void native_swapgs(void) diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h index cbc71e73bd32..9b6df68d8fd1 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -79,10 +79,10 @@ do { \ static inline void refresh_sysenter_cs(struct thread_struct *thread) { /* Only happens when SEP is enabled, no need to test "SEP"arately: */ - if (unlikely(this_cpu_read(cpu_tss.x86_tss.ss1) == thread->sysenter_cs)) + if (unlikely(this_cpu_read(cpu_tss_rw.x86_tss.ss1) == thread->sysenter_cs)) return; - this_cpu_write(cpu_tss.x86_tss.ss1, thread->sysenter_cs); + this_cpu_write(cpu_tss_rw.x86_tss.ss1, thread->sysenter_cs); wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); } #endif diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index 44a04999791e..00223333821a 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -207,7 +207,7 @@ static inline int arch_within_stack_frames(const void * const stack, #else /* !__ASSEMBLY__ */ #ifdef CONFIG_X86_64 -# define cpu_current_top_of_stack (cpu_tss + TSS_sp1) +# define cpu_current_top_of_stack (cpu_tss_rw + TSS_sp1) #endif #endif diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c index 46c0995344aa..cd360a5e0dca 100644 --- a/arch/x86/kernel/asm-offsets.c +++ b/arch/x86/kernel/asm-offsets.c @@ -94,10 +94,9 @@ void common(void) { BLANK(); DEFINE(PTREGS_SIZE, sizeof(struct pt_regs)); - OFFSET(TSS_STRUCT_SYSENTER_stack, tss_struct, SYSENTER_stack); - DEFINE(SIZEOF_SYSENTER_stack, sizeof(struct SYSENTER_stack)); - /* Layout info for cpu_entry_area */ OFFSET(CPU_ENTRY_AREA_tss, cpu_entry_area, tss); OFFSET(CPU_ENTRY_AREA_entry_trampoline, cpu_entry_area, entry_trampoline); + OFFSET(CPU_ENTRY_AREA_SYSENTER_stack, cpu_entry_area, SYSENTER_stack_page); + DEFINE(SIZEOF_SYSENTER_stack, sizeof(struct SYSENTER_stack)); } diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c index 52ce4ea16e53..7d20d9c0b3d6 100644 --- a/arch/x86/kernel/asm-offsets_32.c +++ b/arch/x86/kernel/asm-offsets_32.c @@ -47,8 +47,8 @@ void foo(void) BLANK(); /* Offset from the sysenter stack to tss.sp0 */ - DEFINE(TSS_sysenter_sp0, offsetof(struct tss_struct, x86_tss.sp0) - - offsetofend(struct tss_struct, SYSENTER_stack)); + DEFINE(TSS_sysenter_sp0, offsetof(struct cpu_entry_area, tss.x86_tss.sp0) - + offsetofend(struct cpu_entry_area, SYSENTER_stack_page.stack)); #ifdef CONFIG_CC_STACKPROTECTOR BLANK(); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3de7480e4f32..c2eada1056de 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -487,6 +487,9 @@ static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); #endif +static DEFINE_PER_CPU_PAGE_ALIGNED(struct SYSENTER_stack_page, + SYSENTER_stack_storage); + static void __init set_percpu_fixmap_pages(int idx, void *ptr, int pages, pgprot_t prot) { @@ -500,23 +503,29 @@ static void __init setup_cpu_entry_area(int cpu) #ifdef CONFIG_X86_64 extern char _entry_trampoline[]; - /* On 64-bit systems, we use a read-only fixmap GDT. */ + /* On 64-bit systems, we use a read-only fixmap GDT and TSS. */ pgprot_t gdt_prot = PAGE_KERNEL_RO; + pgprot_t tss_prot = PAGE_KERNEL_RO; #else /* * On native 32-bit systems, the GDT cannot be read-only because * our double fault handler uses a task gate, and entering through - * a task gate needs to change an available TSS to busy. If the GDT - * is read-only, that will triple fault. + * a task gate needs to change an available TSS to busy. If the + * GDT is read-only, that will triple fault. The TSS cannot be + * read-only because the CPU writes to it on task switches. * - * On Xen PV, the GDT must be read-only because the hypervisor requires - * it. + * On Xen PV, the GDT must be read-only because the hypervisor + * requires it. */ pgprot_t gdt_prot = boot_cpu_has(X86_FEATURE_XENPV) ? PAGE_KERNEL_RO : PAGE_KERNEL; + pgprot_t tss_prot = PAGE_KERNEL; #endif __set_fixmap(get_cpu_entry_area_index(cpu, gdt), get_cpu_gdt_paddr(cpu), gdt_prot); + set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, SYSENTER_stack_page), + per_cpu_ptr(&SYSENTER_stack_storage, cpu), 1, + PAGE_KERNEL); /* * The Intel SDM says (Volume 3, 7.2.1): @@ -539,9 +548,9 @@ static void __init setup_cpu_entry_area(int cpu) offsetofend(struct tss_struct, x86_tss)) & PAGE_MASK); BUILD_BUG_ON(sizeof(struct tss_struct) % PAGE_SIZE != 0); set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, tss), - &per_cpu(cpu_tss, cpu), + &per_cpu(cpu_tss_rw, cpu), sizeof(struct tss_struct) / PAGE_SIZE, - PAGE_KERNEL); + tss_prot); #ifdef CONFIG_X86_32 per_cpu(cpu_entry_area, cpu) = get_cpu_entry_area(cpu); @@ -1305,7 +1314,7 @@ void enable_sep_cpu(void) return; cpu = get_cpu(); - tss = &per_cpu(cpu_tss, cpu); + tss = &per_cpu(cpu_tss_rw, cpu); /* * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- @@ -1575,7 +1584,7 @@ void cpu_init(void) if (cpu) load_ucode_ap(); - t = &per_cpu(cpu_tss, cpu); + t = &per_cpu(cpu_tss_rw, cpu); oist = &per_cpu(orig_ist, cpu); #ifdef CONFIG_NUMA @@ -1667,7 +1676,7 @@ void cpu_init(void) { int cpu = smp_processor_id(); struct task_struct *curr = current; - struct tss_struct *t = &per_cpu(cpu_tss, cpu); + struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); wait_for_master_cpu(cpu); diff --git a/arch/x86/kernel/ioport.c b/arch/x86/kernel/ioport.c index 3feb648781c4..2f723301eb58 100644 --- a/arch/x86/kernel/ioport.c +++ b/arch/x86/kernel/ioport.c @@ -67,7 +67,7 @@ asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on) * because the ->io_bitmap_max value must match the bitmap * contents: */ - tss = &per_cpu(cpu_tss, get_cpu()); + tss = &per_cpu(cpu_tss_rw, get_cpu()); if (turn_on) bitmap_clear(t->io_bitmap_ptr, from, num); diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 6a04287f222b..517415978409 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -47,7 +47,7 @@ * section. Since TSS's are completely CPU-local, we want them * on exact cacheline boundaries, to eliminate cacheline ping-pong. */ -__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { +__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss_rw) = { .x86_tss = { /* * .sp0 is only used when entering ring 0 from a lower @@ -82,7 +82,7 @@ __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, #endif }; -EXPORT_PER_CPU_SYMBOL(cpu_tss); +EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); DEFINE_PER_CPU(bool, __tss_limit_invalid); EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); @@ -111,7 +111,7 @@ void exit_thread(struct task_struct *tsk) struct fpu *fpu = &t->fpu; if (bp) { - struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu()); + struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu()); t->io_bitmap_ptr = NULL; clear_thread_flag(TIF_IO_BITMAP); diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c index 45bf0c5f93e1..5224c6099184 100644 --- a/arch/x86/kernel/process_32.c +++ b/arch/x86/kernel/process_32.c @@ -234,7 +234,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) struct fpu *prev_fpu = &prev->fpu; struct fpu *next_fpu = &next->fpu; int cpu = smp_processor_id(); - struct tss_struct *tss = &per_cpu(cpu_tss, cpu); + struct tss_struct *tss = &per_cpu(cpu_tss_rw, cpu); /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */ diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 157f81816915..c75466232016 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -399,7 +399,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) struct fpu *prev_fpu = &prev->fpu; struct fpu *next_fpu = &next->fpu; int cpu = smp_processor_id(); - struct tss_struct *tss = &per_cpu(cpu_tss, cpu); + struct tss_struct *tss = &per_cpu(cpu_tss_rw, cpu); WARN_ON_ONCE(IS_ENABLED(CONFIG_DEBUG_ENTRY) && this_cpu_read(irq_count) != -1); diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 5ade4f89a6d1..74136fd16f49 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -364,7 +364,7 @@ dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) regs->cs == __KERNEL_CS && regs->ip == (unsigned long)native_irq_return_iret) { - struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss.x86_tss.sp0) - 1; + struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; /* * regs->sp points to the failing IRET frame on the @@ -649,7 +649,7 @@ struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s) * exception came from the IRET target. */ struct bad_iret_stack *new_stack = - (struct bad_iret_stack *)this_cpu_read(cpu_tss.x86_tss.sp0) - 1; + (struct bad_iret_stack *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; /* Copy the IRET target to the new stack. */ memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8); diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c index 553f8fd23cc4..4846eff7e4c8 100644 --- a/arch/x86/lib/delay.c +++ b/arch/x86/lib/delay.c @@ -107,10 +107,10 @@ static void delay_mwaitx(unsigned long __loops) delay = min_t(u64, MWAITX_MAX_LOOPS, loops); /* - * Use cpu_tss as a cacheline-aligned, seldomly + * Use cpu_tss_rw as a cacheline-aligned, seldomly * accessed per-cpu variable as the monitor target. */ - __monitorx(raw_cpu_ptr(&cpu_tss), 0, 0); + __monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0); /* * AMD, like Intel, supports the EAX hint and EAX=0xf diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index fbd054d6ac97..ae3a071e1d0f 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -818,7 +818,7 @@ static void xen_load_sp0(unsigned long sp0) mcs = xen_mc_entry(0); MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0); xen_mc_issue(PARAVIRT_LAZY_CPU); - this_cpu_write(cpu_tss.x86_tss.sp0, sp0); + this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); } void xen_set_iopl_mask(unsigned mask) -- GitLab From a035795499ca1c2bd1928808d1a156eda1420383 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 4 Dec 2017 15:07:30 +0100 Subject: [PATCH 1667/2547] x86/paravirt: Dont patch flush_tlb_single native_flush_tlb_single() will be changed with the upcoming PAGE_TABLE_ISOLATION feature. This requires to have more code in there than INVLPG. Remove the paravirt patching for it. Signed-off-by: Thomas Gleixner Reviewed-by: Josh Poimboeuf Reviewed-by: Juergen Gross Acked-by: Peter Zijlstra Cc: Andy Lutomirski Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Cc: linux-mm@kvack.org Cc: michael.schwarz@iaik.tugraz.at Cc: moritz.lipp@iaik.tugraz.at Cc: richard.fellner@student.tugraz.at Link: https://lkml.kernel.org/r/20171204150606.828111617@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/kernel/paravirt_patch_64.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/x86/kernel/paravirt_patch_64.c b/arch/x86/kernel/paravirt_patch_64.c index ac0be8283325..9edadabf04f6 100644 --- a/arch/x86/kernel/paravirt_patch_64.c +++ b/arch/x86/kernel/paravirt_patch_64.c @@ -10,7 +10,6 @@ DEF_NATIVE(pv_irq_ops, save_fl, "pushfq; popq %rax"); DEF_NATIVE(pv_mmu_ops, read_cr2, "movq %cr2, %rax"); DEF_NATIVE(pv_mmu_ops, read_cr3, "movq %cr3, %rax"); DEF_NATIVE(pv_mmu_ops, write_cr3, "movq %rdi, %cr3"); -DEF_NATIVE(pv_mmu_ops, flush_tlb_single, "invlpg (%rdi)"); DEF_NATIVE(pv_cpu_ops, wbinvd, "wbinvd"); DEF_NATIVE(pv_cpu_ops, usergs_sysret64, "swapgs; sysretq"); @@ -60,7 +59,6 @@ unsigned native_patch(u8 type, u16 clobbers, void *ibuf, PATCH_SITE(pv_mmu_ops, read_cr2); PATCH_SITE(pv_mmu_ops, read_cr3); PATCH_SITE(pv_mmu_ops, write_cr3); - PATCH_SITE(pv_mmu_ops, flush_tlb_single); PATCH_SITE(pv_cpu_ops, wbinvd); #if defined(CONFIG_PARAVIRT_SPINLOCKS) case PARAVIRT_PATCH(pv_lock_ops.queued_spin_unlock): -- GitLab From 79cc74155218316b9a5d28577c7077b2adba8e58 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 4 Dec 2017 15:07:31 +0100 Subject: [PATCH 1668/2547] x86/paravirt: Provide a way to check for hypervisors There is no generic way to test whether a kernel is running on a specific hypervisor. But that's required to prevent the upcoming user address space separation feature in certain guest modes. Make the hypervisor type enum unconditionally available and provide a helper function which allows to test for a specific type. Signed-off-by: Thomas Gleixner Reviewed-by: Juergen Gross Cc: Andy Lutomirski Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150606.912938129@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/hypervisor.h | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/hypervisor.h b/arch/x86/include/asm/hypervisor.h index 1b0a5abcd8ae..96aa6b9884dc 100644 --- a/arch/x86/include/asm/hypervisor.h +++ b/arch/x86/include/asm/hypervisor.h @@ -20,16 +20,7 @@ #ifndef _ASM_X86_HYPERVISOR_H #define _ASM_X86_HYPERVISOR_H -#ifdef CONFIG_HYPERVISOR_GUEST - -#include -#include -#include - -/* - * x86 hypervisor information - */ - +/* x86 hypervisor types */ enum x86_hypervisor_type { X86_HYPER_NATIVE = 0, X86_HYPER_VMWARE, @@ -39,6 +30,12 @@ enum x86_hypervisor_type { X86_HYPER_KVM, }; +#ifdef CONFIG_HYPERVISOR_GUEST + +#include +#include +#include + struct hypervisor_x86 { /* Hypervisor name */ const char *name; @@ -58,7 +55,15 @@ struct hypervisor_x86 { extern enum x86_hypervisor_type x86_hyper_type; extern void init_hypervisor_platform(void); +static inline bool hypervisor_is_type(enum x86_hypervisor_type type) +{ + return x86_hyper_type == type; +} #else static inline void init_hypervisor_platform(void) { } +static inline bool hypervisor_is_type(enum x86_hypervisor_type type) +{ + return type == X86_HYPER_NATIVE; +} #endif /* CONFIG_HYPERVISOR_GUEST */ #endif /* _ASM_X86_HYPERVISOR_H */ -- GitLab From 6cbd2171e89b13377261d15e64384df60ecb530e Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 4 Dec 2017 15:07:32 +0100 Subject: [PATCH 1669/2547] x86/cpufeatures: Make CPU bugs sticky There is currently no way to force CPU bug bits like CPU feature bits. That makes it impossible to set a bug bit once at boot and have it stick for all upcoming CPUs. Extend the force set/clear arrays to handle bug bits as well. Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Andy Lutomirski Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150606.992156574@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/cpufeature.h | 2 ++ arch/x86/include/asm/processor.h | 4 ++-- arch/x86/kernel/cpu/common.c | 6 +++--- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index bf6a76202a77..ea9a7dde62e5 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -135,6 +135,8 @@ extern void clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int bit); set_bit(bit, (unsigned long *)cpu_caps_set); \ } while (0) +#define setup_force_cpu_bug(bit) setup_force_cpu_cap(bit) + #if defined(CC_HAVE_ASM_GOTO) && defined(CONFIG_X86_FAST_FEATURE_TESTS) /* * Static testing of CPU features. Used the same as boot_cpu_has(). diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index e8991d7f7034..da943411d3d8 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -163,8 +163,8 @@ extern struct cpuinfo_x86 boot_cpu_data; extern struct cpuinfo_x86 new_cpu_data; extern struct x86_hw_tss doublefault_tss; -extern __u32 cpu_caps_cleared[NCAPINTS]; -extern __u32 cpu_caps_set[NCAPINTS]; +extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; +extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; #ifdef CONFIG_SMP DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index c2eada1056de..034900623adf 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -452,8 +452,8 @@ static const char *table_lookup_model(struct cpuinfo_x86 *c) return NULL; /* Not found */ } -__u32 cpu_caps_cleared[NCAPINTS]; -__u32 cpu_caps_set[NCAPINTS]; +__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; +__u32 cpu_caps_set[NCAPINTS + NBUGINTS]; void load_percpu_segment(int cpu) { @@ -812,7 +812,7 @@ static void apply_forced_caps(struct cpuinfo_x86 *c) { int i; - for (i = 0; i < NCAPINTS; i++) { + for (i = 0; i < NCAPINTS + NBUGINTS; i++) { c->x86_capability[i] &= ~cpu_caps_cleared[i]; c->x86_capability[i] |= cpu_caps_set[i]; } -- GitLab From ab309a6a3a0b3b6ce495c7a31731ff82cff7faa2 Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Fri, 15 Dec 2017 14:36:35 +0000 Subject: [PATCH 1670/2547] drm/i915: Unifying debugfs return codes for unsupported features Instead of trying different seq_puts messages, lets use common -ENODEV error code to indicate missing/unsupported feature. v2: don't forget about guc_log_control fops (Sagar) Suggested-by: Chris Wilson Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Sagar Arun Kamble Cc: Sujaritha Sundaresan Link: https://patchwork.freedesktop.org/patch/msgid/20171215143635.17884-1-michal.wajdeczko@intel.com Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c | 76 ++++++++++++----------------- 1 file changed, 31 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index d8c6ec3cca71..0ddce72552bf 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1602,10 +1602,8 @@ static int i915_fbc_status(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - if (!HAS_FBC(dev_priv)) { - seq_puts(m, "FBC unsupported on this chipset\n"); - return 0; - } + if (!HAS_FBC(dev_priv)) + return -ENODEV; intel_runtime_pm_get(dev_priv); mutex_lock(&dev_priv->fbc.lock); @@ -1681,10 +1679,8 @@ static int i915_ips_status(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - if (!HAS_IPS(dev_priv)) { - seq_puts(m, "not supported\n"); - return 0; - } + if (!HAS_IPS(dev_priv)) + return -ENODEV; intel_runtime_pm_get(dev_priv); @@ -1770,10 +1766,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) int gpu_freq, ia_freq; unsigned int max_gpu_freq, min_gpu_freq; - if (!HAS_LLC(dev_priv)) { - seq_puts(m, "unsupported on this chipset\n"); - return 0; - } + if (!HAS_LLC(dev_priv)) + return -ENODEV; intel_runtime_pm_get(dev_priv); @@ -2253,8 +2247,8 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = node_to_i915(m->private); struct drm_printer p; - if (!HAS_HUC_UCODE(dev_priv)) - return 0; + if (!HAS_HUC(dev_priv)) + return -ENODEV; p = drm_seq_file_printer(m); intel_uc_fw_dump(&dev_priv->huc.fw, &p); @@ -2272,8 +2266,8 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data) struct drm_printer p; u32 tmp, i; - if (!HAS_GUC_UCODE(dev_priv)) - return 0; + if (!HAS_GUC(dev_priv)) + return -ENODEV; p = drm_seq_file_printer(m); intel_uc_fw_dump(&dev_priv->guc.fw, &p); @@ -2346,29 +2340,16 @@ static void i915_guc_client_info(struct seq_file *m, seq_printf(m, "\tTotal: %llu\n", tot); } -static bool check_guc_submission(struct seq_file *m) -{ - struct drm_i915_private *dev_priv = node_to_i915(m->private); - const struct intel_guc *guc = &dev_priv->guc; - - if (!guc->execbuf_client) { - seq_printf(m, "GuC submission %s\n", - HAS_GUC_SCHED(dev_priv) ? - "disabled" : - "not supported"); - return false; - } - - return true; -} - static int i915_guc_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); const struct intel_guc *guc = &dev_priv->guc; - if (!check_guc_submission(m)) - return 0; + if (!USES_GUC_SUBMISSION(dev_priv)) + return -ENODEV; + + GEM_BUG_ON(!guc->execbuf_client); + GEM_BUG_ON(!guc->preempt_client); seq_printf(m, "Doorbell map:\n"); seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap); @@ -2395,8 +2376,8 @@ static int i915_guc_stage_pool(struct seq_file *m, void *data) unsigned int tmp; int index; - if (!check_guc_submission(m)) - return 0; + if (!USES_GUC_SUBMISSION(dev_priv)) + return -ENODEV; for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) { struct intel_engine_cs *engine; @@ -2449,6 +2430,9 @@ static int i915_guc_log_dump(struct seq_file *m, void *data) u32 *log; int i = 0; + if (!HAS_GUC(dev_priv)) + return -ENODEV; + if (dump_load_err) obj = dev_priv->guc.load_err_log; else if (dev_priv->guc.log.vma) @@ -2480,6 +2464,9 @@ static int i915_guc_log_control_get(void *data, u64 *val) { struct drm_i915_private *dev_priv = data; + if (!HAS_GUC(dev_priv)) + return -ENODEV; + if (!dev_priv->guc.log.vma) return -EINVAL; @@ -2493,6 +2480,9 @@ static int i915_guc_log_control_set(void *data, u64 val) struct drm_i915_private *dev_priv = data; int ret; + if (!HAS_GUC(dev_priv)) + return -ENODEV; + if (!dev_priv->guc.log.vma) return -EINVAL; @@ -2543,10 +2533,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) enum pipe pipe; bool enabled = false; - if (!HAS_PSR(dev_priv)) { - seq_puts(m, "PSR not supported\n"); - return 0; - } + if (!HAS_PSR(dev_priv)) + return -ENODEV; intel_runtime_pm_get(dev_priv); @@ -2785,10 +2773,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused) struct drm_i915_private *dev_priv = node_to_i915(m->private); struct intel_csr *csr; - if (!HAS_CSR(dev_priv)) { - seq_puts(m, "not supported\n"); - return 0; - } + if (!HAS_CSR(dev_priv)) + return -ENODEV; csr = &dev_priv->csr; @@ -3324,7 +3310,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused) int plane; if (INTEL_GEN(dev_priv) < 9) - return 0; + return -ENODEV; drm_modeset_lock_all(dev); -- GitLab From 203c110b39a89b48156c7450504e454fedb7f7f6 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Tue, 12 Dec 2017 21:32:16 +0100 Subject: [PATCH 1671/2547] parisc: Fix indenting in puts() Static analysis tools complain that we intended to have curly braces around this indent block. In this case this assumption is wrong, so fix the indenting. Fixes: 2f3c7b8137ef ("parisc: Add core code for self-extracting kernel") Reported-by: Dan Carpenter Signed-off-by: Helge Deller Cc: # v4.14+ --- arch/parisc/boot/compressed/misc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/parisc/boot/compressed/misc.c b/arch/parisc/boot/compressed/misc.c index 9345b44b86f0..f57118e1f6b4 100644 --- a/arch/parisc/boot/compressed/misc.c +++ b/arch/parisc/boot/compressed/misc.c @@ -123,8 +123,8 @@ int puts(const char *s) while ((nuline = strchr(s, '\n')) != NULL) { if (nuline != s) pdc_iodc_print(s, nuline - s); - pdc_iodc_print("\r\n", 2); - s = nuline + 1; + pdc_iodc_print("\r\n", 2); + s = nuline + 1; } if (*s != '\0') pdc_iodc_print(s, strlen(s)); -- GitLab From 0ed9d3de5f8f97e6efd5ca0e3377cab5f0451ead Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Tue, 12 Dec 2017 21:25:41 +0100 Subject: [PATCH 1672/2547] parisc: Align os_hpmc_size on word boundary The os_hpmc_size variable sometimes wasn't aligned at word boundary and thus triggered the unaligned fault handler at startup. Fix it by aligning it properly. Signed-off-by: Helge Deller Cc: # v4.14+ --- arch/parisc/kernel/hpmc.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/parisc/kernel/hpmc.S b/arch/parisc/kernel/hpmc.S index e3a8e5e4d5de..8d072c44f300 100644 --- a/arch/parisc/kernel/hpmc.S +++ b/arch/parisc/kernel/hpmc.S @@ -305,6 +305,7 @@ ENDPROC_CFI(os_hpmc) __INITRODATA + .align 4 .export os_hpmc_size os_hpmc_size: .word .os_hpmc_end-.os_hpmc -- GitLab From bcf3f1752a622f1372d3252d0fea8855d89812e7 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Tue, 12 Dec 2017 21:52:26 +0100 Subject: [PATCH 1673/2547] parisc: Hide Diva-built-in serial aux and graphics card Diva GSP card has built-in serial AUX port and ATI graphic card which simply don't work and which both don't have external connectors. User Guides even mention that those devices shouldn't be used. So, prevent that Linux drivers try to enable those devices. Signed-off-by: Helge Deller Cc: # v3.0+ --- drivers/parisc/lba_pci.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c index a25fed52f7e9..41b740aed3a3 100644 --- a/drivers/parisc/lba_pci.c +++ b/drivers/parisc/lba_pci.c @@ -1692,3 +1692,36 @@ void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask) iounmap(base_addr); } + +/* + * The design of the Diva management card in rp34x0 machines (rp3410, rp3440) + * seems rushed, so that many built-in components simply don't work. + * The following quirks disable the serial AUX port and the built-in ATI RV100 + * Radeon 7000 graphics card which both don't have any external connectors and + * thus are useless, and even worse, e.g. the AUX port occupies ttyS0 and as + * such makes those machines the only PARISC machines on which we can't use + * ttyS0 as boot console. + */ +static void quirk_diva_ati_card(struct pci_dev *dev) +{ + if (dev->subsystem_vendor != PCI_VENDOR_ID_HP || + dev->subsystem_device != 0x1292) + return; + + dev_info(&dev->dev, "Hiding Diva built-in ATI card"); + dev->device = 0; +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY, + quirk_diva_ati_card); + +static void quirk_diva_aux_disable(struct pci_dev *dev) +{ + if (dev->subsystem_vendor != PCI_VENDOR_ID_HP || + dev->subsystem_device != 0x1291) + return; + + dev_info(&dev->dev, "Hiding Diva built-in AUX serial device"); + dev->device = 0; +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, + quirk_diva_aux_disable); -- GitLab From 6a16fc322085bb3163d7d6e44856adfda06a8001 Mon Sep 17 00:00:00 2001 From: Pravin Shedge Date: Sun, 10 Dec 2017 23:54:33 +0530 Subject: [PATCH 1674/2547] parisc: remove duplicate includes These duplicate includes have been found with scripts/checkincludes.pl but they have been removed manually to avoid removing false positives. Signed-off-by: Pravin Shedge Signed-off-by: Helge Deller --- arch/parisc/kernel/unwind.c | 1 - arch/parisc/lib/delay.c | 2 -- 2 files changed, 3 deletions(-) diff --git a/arch/parisc/kernel/unwind.c b/arch/parisc/kernel/unwind.c index 5a657986ebbf..143f90e2f9f3 100644 --- a/arch/parisc/kernel/unwind.c +++ b/arch/parisc/kernel/unwind.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include diff --git a/arch/parisc/lib/delay.c b/arch/parisc/lib/delay.c index 7eab4bb8abe6..66e506520505 100644 --- a/arch/parisc/lib/delay.c +++ b/arch/parisc/lib/delay.c @@ -16,9 +16,7 @@ #include #include -#include #include - #include /* for mfctl() */ #include /* for boot_cpu_data */ -- GitLab From 9352aeada4d8d8753fc0e414fbfe8fdfcb68a12c Mon Sep 17 00:00:00 2001 From: John David Anglin Date: Mon, 13 Nov 2017 19:35:33 -0500 Subject: [PATCH 1675/2547] Revert "parisc: Re-enable interrupts early" This reverts commit 5c38602d83e584047906b41b162ababd4db4106d. Interrupts can't be enabled early because the register saves are done on the thread stack prior to switching to the IRQ stack. This caused stack overflows and the thread stack needed increasing to 32k. Even then, stack overflows still occasionally occurred. Background: Even with a 32 kB thread stack, I have seen instances where the thread stack overflowed on the mx3210 buildd. Detection of stack overflow only occurs when we have an external interrupt. When an external interrupt occurs, we switch to the thread stack if we are not already on a kernel stack. Then, registers and specials are saved to the kernel stack. The bug occurs in intr_return where interrupts are reenabled prior to returning from the interrupt. This was done incase we need to schedule or deliver signals. However, it introduces the possibility that multiple external interrupts may occur on the thread stack and cause a stack overflow. These might not be detected and cause the kernel to misbehave in random ways. This patch changes the code back to only reenable interrupts when we are going to schedule or deliver signals. As a result, we generally return from an interrupt before reenabling interrupts. This minimizes the growth of the thread stack. Fixes: 5c38602d83e5 ("parisc: Re-enable interrupts early") Signed-off-by: John David Anglin Cc: # v4.10+ Signed-off-by: Helge Deller --- arch/parisc/kernel/entry.S | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index a4fd296c958e..f3cecf5117cf 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -878,9 +878,6 @@ ENTRY_CFI(syscall_exit_rfi) STREG %r19,PT_SR7(%r16) intr_return: - /* NOTE: Need to enable interrupts incase we schedule. */ - ssm PSW_SM_I, %r0 - /* check for reschedule */ mfctl %cr30,%r1 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */ @@ -907,6 +904,11 @@ intr_check_sig: LDREG PT_IASQ1(%r16), %r20 cmpib,COND(=),n 0,%r20,intr_restore /* backward */ + /* NOTE: We need to enable interrupts if we have to deliver + * signals. We used to do this earlier but it caused kernel + * stack overflows. */ + ssm PSW_SM_I, %r0 + copy %r0, %r25 /* long in_syscall = 0 */ #ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ @@ -958,6 +960,10 @@ intr_do_resched: cmpib,COND(=) 0, %r20, intr_do_preempt nop + /* NOTE: We need to enable interrupts if we schedule. We used + * to do this earlier but it caused kernel stack overflows. */ + ssm PSW_SM_I, %r0 + #ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #endif -- GitLab From da57c5414f49ef9e4bcb9ae0bbafd1d650b31411 Mon Sep 17 00:00:00 2001 From: John David Anglin Date: Mon, 13 Nov 2017 19:35:33 -0500 Subject: [PATCH 1676/2547] parisc: Reduce thread stack to 16 kb In testing, I found that the thread stack can be 16 kB when using an irq stack. Without it, the thread stack needs to be 32 kB. Currently, the irq stack is 32 kB. While it probably could be 16 kB, I would prefer to leave it as is for safety. Signed-off-by: John David Anglin Signed-off-by: Helge Deller --- arch/parisc/include/asm/thread_info.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/parisc/include/asm/thread_info.h b/arch/parisc/include/asm/thread_info.h index c980a02a52bc..598c8d60fa5e 100644 --- a/arch/parisc/include/asm/thread_info.h +++ b/arch/parisc/include/asm/thread_info.h @@ -35,7 +35,12 @@ struct thread_info { /* thread information allocation */ +#ifdef CONFIG_IRQSTACKS +#define THREAD_SIZE_ORDER 2 /* PA-RISC requires at least 16k stack */ +#else #define THREAD_SIZE_ORDER 3 /* PA-RISC requires at least 32k stack */ +#endif + /* Be sure to hunt all references to this down when you change the size of * the kernel stack */ #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) -- GitLab From b9f5fb1800d8a4a3bc6cd3152c5f3d252986cf79 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 10 Nov 2017 15:57:21 +0100 Subject: [PATCH 1677/2547] cramfs: fix MTD dependency With CONFIG_MTD=m and CONFIG_CRAMFS=y, we now get a link failure: fs/cramfs/inode.o: In function `cramfs_mount': inode.c:(.text+0x220): undefined reference to `mount_mtd' fs/cramfs/inode.o: In function `cramfs_mtd_fill_super': inode.c:(.text+0x6d8): undefined reference to `mtd_point' inode.c:(.text+0xae4): undefined reference to `mtd_unpoint' This adds a more specific Kconfig dependency to avoid the broken configuration. Alternatively we could make CRAMFS itself depend on "MTD || !MTD" with a similar result. Fixes: 99c18ce580c6 ("cramfs: direct memory access support") Signed-off-by: Arnd Bergmann Signed-off-by: Nicolas Pitre Signed-off-by: Linus Torvalds --- fs/cramfs/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/cramfs/Kconfig b/fs/cramfs/Kconfig index f937082f3244..58e2fe40b2a0 100644 --- a/fs/cramfs/Kconfig +++ b/fs/cramfs/Kconfig @@ -34,6 +34,7 @@ config CRAMFS_BLOCKDEV config CRAMFS_MTD bool "Support CramFs image directly mapped in physical memory" depends on CRAMFS && MTD + depends on CRAMFS=m || MTD=y default y if !CRAMFS_BLOCKDEV help This option allows the CramFs driver to load data directly from -- GitLab From 36b0cb84ee858f02c256d26f0cb4229c78e3399e Mon Sep 17 00:00:00 2001 From: Chunyan Zhang Date: Fri, 1 Dec 2017 03:51:04 +0100 Subject: [PATCH 1678/2547] ARM: 8731/1: Fix csum_partial_copy_from_user() stack mismatch An additional 'ip' will be pushed to the stack, for restoring the DACR later, if CONFIG_CPU_SW_DOMAIN_PAN defined. However, the fixup still get the err_ptr by add #8*4 to sp, which results in the fact that the code area pointed by the LR will be overwritten, or the kernel will crash if CONFIG_DEBUG_RODATA is enabled. This patch fixes the stack mismatch. Fixes: a5e090acbf54 ("ARM: software-based priviledged-no-access support") Signed-off-by: Lvqiang Huang Signed-off-by: Chunyan Zhang Signed-off-by: Russell King --- arch/arm/lib/csumpartialcopyuser.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S index 1712f132b80d..b83fdc06286a 100644 --- a/arch/arm/lib/csumpartialcopyuser.S +++ b/arch/arm/lib/csumpartialcopyuser.S @@ -85,7 +85,11 @@ .pushsection .text.fixup,"ax" .align 4 9001: mov r4, #-EFAULT +#ifdef CONFIG_CPU_SW_DOMAIN_PAN + ldr r5, [sp, #9*4] @ *err_ptr +#else ldr r5, [sp, #8*4] @ *err_ptr +#endif str r4, [r5] ldmia sp, {r1, r2} @ retrieve dst, len add r2, r2, r1 -- GitLab From 779f4e1c6c7c661db40dfebd6dd6bda7b5f88aa3 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Tue, 12 Dec 2017 11:28:38 -0800 Subject: [PATCH 1679/2547] Revert "exec: avoid RLIMIT_STACK races with prlimit()" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 04e35f4495dd560db30c25efca4eecae8ec8c375. SELinux runs with secureexec for all non-"noatsecure" domain transitions, which means lots of processes end up hitting the stack hard-limit change that was introduced in order to fix a race with prlimit(). That race fix will need to be redesigned. Reported-by: Laura Abbott Reported-by: Tomáš Trnka Cc: stable@vger.kernel.org Signed-off-by: Kees Cook Signed-off-by: Linus Torvalds --- fs/exec.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/fs/exec.c b/fs/exec.c index 156f56acfe8e..5688b5e1b937 100644 --- a/fs/exec.c +++ b/fs/exec.c @@ -1339,15 +1339,10 @@ void setup_new_exec(struct linux_binprm * bprm) * avoid bad behavior from the prior rlimits. This has to * happen before arch_pick_mmap_layout(), which examines * RLIMIT_STACK, but after the point of no return to avoid - * races from other threads changing the limits. This also - * must be protected from races with prlimit() calls. + * needing to clean up the change on failure. */ - task_lock(current->group_leader); if (current->signal->rlim[RLIMIT_STACK].rlim_cur > _STK_LIM) current->signal->rlim[RLIMIT_STACK].rlim_cur = _STK_LIM; - if (current->signal->rlim[RLIMIT_STACK].rlim_max > _STK_LIM) - current->signal->rlim[RLIMIT_STACK].rlim_max = _STK_LIM; - task_unlock(current->group_leader); } arch_pick_mmap_layout(current->mm); -- GitLab From 1291a0d5049dbc06baaaf66a9ff3f53db493b19b Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sun, 17 Dec 2017 18:59:59 -0800 Subject: [PATCH 1680/2547] Linux 4.15-rc4 --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3f4d157add54..7e02f951b284 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ VERSION = 4 PATCHLEVEL = 15 SUBLEVEL = 0 -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc4 NAME = Fearless Coyote # *DOCUMENTATION* -- GitLab From d82c3682168431d29ba1741d0cd5ef45c68bf8e0 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 18 Dec 2017 08:26:28 +0100 Subject: [PATCH 1681/2547] mtd: Fix mtd_check_oob_ops() The mtd_check_oob_ops() helper verifies if the operation defined by the user is correct. Fix the check that verifies if the entire requested area exists. This check is too restrictive and will fail anytime the last data byte of the very last page is included in an operation. Fixes: 5cdd929da53d ("mtd: Add sanity checks in mtd_write/read_oob()") Signed-off-by: Miquel Raynal Acked-by: Boris Brezillon Signed-off-by: Richard Weinberger --- drivers/mtd/mtdcore.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index f80e911b8843..73b605577447 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -1114,7 +1114,7 @@ static int mtd_check_oob_ops(struct mtd_info *mtd, loff_t offs, if (!ops->oobbuf) ops->ooblen = 0; - if (offs < 0 || offs + ops->len >= mtd->size) + if (offs < 0 || offs + ops->len > mtd->size) return -EINVAL; if (ops->ooblen) { -- GitLab From dc5718f47cda438f47420591f4ac7338d7964bce Mon Sep 17 00:00:00 2001 From: Weinan Li Date: Wed, 13 Dec 2017 10:46:59 +0800 Subject: [PATCH 1682/2547] drm/i915/gvt: refine trace_render_mmio Refine trace_render_mmio to show the vm id before and after vgpu switch, tag host id as '0', this patch will be used in the future patch for refine mocs switch policy. Signed-off-by: Weinan Li Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/mmio_context.c | 4 ++-- drivers/gpu/drm/i915/gvt/trace.h | 15 +++++++++------ 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 8a52b56f0e86..77d3a0d43d7c 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -304,7 +304,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) I915_WRITE_FW(mmio->reg, v); - trace_render_mmio(vgpu->id, "load", + trace_render_mmio(0, vgpu->id, "switch", i915_mmio_reg_offset(mmio->reg), mmio->value, v); } @@ -340,7 +340,7 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) I915_WRITE_FW(mmio->reg, v); - trace_render_mmio(vgpu->id, "restore", + trace_render_mmio(vgpu->id, 0, "switch", i915_mmio_reg_offset(mmio->reg), mmio->value, v); } diff --git a/drivers/gpu/drm/i915/gvt/trace.h b/drivers/gpu/drm/i915/gvt/trace.h index 8c150381d9a4..7a2511538f34 100644 --- a/drivers/gpu/drm/i915/gvt/trace.h +++ b/drivers/gpu/drm/i915/gvt/trace.h @@ -330,13 +330,14 @@ TRACE_EVENT(inject_msi, ); TRACE_EVENT(render_mmio, - TP_PROTO(int id, char *action, unsigned int reg, + TP_PROTO(int old_id, int new_id, char *action, unsigned int reg, unsigned int old_val, unsigned int new_val), - TP_ARGS(id, action, reg, new_val, old_val), + TP_ARGS(old_id, new_id, action, reg, new_val, old_val), TP_STRUCT__entry( - __field(int, id) + __field(int, old_id) + __field(int, new_id) __array(char, buf, GVT_TEMP_STR_LEN) __field(unsigned int, reg) __field(unsigned int, old_val) @@ -344,15 +345,17 @@ TRACE_EVENT(render_mmio, ), TP_fast_assign( - __entry->id = id; + __entry->old_id = old_id; + __entry->new_id = new_id; snprintf(__entry->buf, GVT_TEMP_STR_LEN, "%s", action); __entry->reg = reg; __entry->old_val = old_val; __entry->new_val = new_val; ), - TP_printk("VM%u %s reg %x, old %08x new %08x\n", - __entry->id, __entry->buf, __entry->reg, + TP_printk("VM%u -> VM%u %s reg %x, old %08x new %08x\n", + __entry->old_id, __entry->new_id, + __entry->buf, __entry->reg, __entry->old_val, __entry->new_val) ); -- GitLab From e47107ad37c3774be9d5bf6fb4625c59e59f632c Mon Sep 17 00:00:00 2001 From: Weinan Li Date: Wed, 13 Dec 2017 10:47:00 +0800 Subject: [PATCH 1683/2547] drm/i915/gvt: optimize for vGPU mmio switch Now mmio switch between vGPUs need to switch to host first then to expected vGPU, it waste one time mmio save/restore. r/w mmio usually is time-consuming, and there are so many mocs registers need to save/restore during vGPU switch. Combine the switch_to_host and switch_to_vgpu can reduce 1 time mmio save/restore, it will reduce the CPU utilization and performance while there is multi VMs with heavy work load. Signed-off-by: Weinan Li Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/mmio_context.c | 196 ++++++++++-------------- 1 file changed, 85 insertions(+), 111 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 77d3a0d43d7c..5ad72fc0f9e7 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -198,9 +198,10 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) gvt_dbg_core("invalidate TLB for ring %d\n", ring_id); } -static void load_mocs(struct intel_vgpu *vgpu, int ring_id) +static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, + int ring_id) { - struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + struct drm_i915_private *dev_priv; i915_reg_t offset, l3_offset; u32 regs[] = { [RCS] = 0xc800, @@ -211,54 +212,44 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) }; int i; + dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) return; offset.reg = regs[ring_id]; - for (i = 0; i < 64; i++) { - gen9_render_mocs[ring_id][i] = I915_READ_FW(offset); - I915_WRITE_FW(offset, vgpu_vreg(vgpu, offset)); - offset.reg += 4; - } - - if (ring_id == RCS) { - l3_offset.reg = 0xb020; - for (i = 0; i < 32; i++) { - gen9_render_mocs_L3[i] = I915_READ_FW(l3_offset); - I915_WRITE_FW(l3_offset, vgpu_vreg(vgpu, l3_offset)); - l3_offset.reg += 4; - } - } -} -static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) -{ - struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; - i915_reg_t offset, l3_offset; - u32 regs[] = { - [RCS] = 0xc800, - [VCS] = 0xc900, - [VCS2] = 0xca00, - [BCS] = 0xcc00, - [VECS] = 0xcb00, - }; - int i; + for (i = 0; i < 64; i++) { + if (pre) + vgpu_vreg(pre, offset) = + I915_READ_FW(offset); + else + gen9_render_mocs[ring_id][i] = + I915_READ_FW(offset); - if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) - return; + if (next) + I915_WRITE_FW(offset, vgpu_vreg(next, offset)); + else + I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]); - offset.reg = regs[ring_id]; - for (i = 0; i < 64; i++) { - vgpu_vreg(vgpu, offset) = I915_READ_FW(offset); - I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]); offset.reg += 4; } if (ring_id == RCS) { l3_offset.reg = 0xb020; for (i = 0; i < 32; i++) { - vgpu_vreg(vgpu, l3_offset) = I915_READ_FW(l3_offset); - I915_WRITE_FW(l3_offset, gen9_render_mocs_L3[i]); + if (pre) + vgpu_vreg(pre, l3_offset) = + I915_READ_FW(l3_offset); + else + gen9_render_mocs_L3[i] = + I915_READ_FW(l3_offset); + if (next) + I915_WRITE_FW(l3_offset, + vgpu_vreg(next, l3_offset)); + else + I915_WRITE_FW(l3_offset, + gen9_render_mocs_L3[i]); + l3_offset.reg += 4; } } @@ -266,84 +257,77 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) #define CTX_CONTEXT_CONTROL_VAL 0x03 -/* Switch ring mmio values (context) from host to a vgpu. */ -static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) +/* Switch ring mmio values (context). */ +static void switch_mmio(struct intel_vgpu *pre, + struct intel_vgpu *next, + int ring_id) { - struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; - struct intel_vgpu_submission *s = &vgpu->submission; - u32 *reg_state = s->shadow_ctx->engine[ring_id].lrc_reg_state; - u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL]; + struct drm_i915_private *dev_priv; + struct intel_vgpu_submission *s; + u32 *reg_state, ctx_ctrl; u32 inhibit_mask = _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); struct engine_mmio *mmio; - u32 v; - - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) - load_mocs(vgpu, ring_id); - - mmio = vgpu->gvt->engine_mmio_list; - while (i915_mmio_reg_offset((mmio++)->reg)) { - if (mmio->ring_id != ring_id) - continue; - - mmio->value = I915_READ_FW(mmio->reg); - - /* - * if it is an inhibit context, load in_context mmio - * into HW by mmio write. If it is not, skip this mmio - * write. - */ - if (mmio->in_context && - (ctx_ctrl & inhibit_mask) != inhibit_mask) - continue; - - if (mmio->mask) - v = vgpu_vreg(vgpu, mmio->reg) | (mmio->mask << 16); - else - v = vgpu_vreg(vgpu, mmio->reg); - - I915_WRITE_FW(mmio->reg, v); - - trace_render_mmio(0, vgpu->id, "switch", - i915_mmio_reg_offset(mmio->reg), - mmio->value, v); - } - - handle_tlb_pending_event(vgpu, ring_id); -} - -/* Switch ring mmio values (context) from vgpu to host. */ -static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) -{ - struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; - struct engine_mmio *mmio; - u32 v; + u32 old_v, new_v; + dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) - restore_mocs(vgpu, ring_id); + switch_mocs(pre, next, ring_id); - mmio = vgpu->gvt->engine_mmio_list; + mmio = dev_priv->gvt->engine_mmio_list; while (i915_mmio_reg_offset((mmio++)->reg)) { if (mmio->ring_id != ring_id) continue; - - vgpu_vreg(vgpu, mmio->reg) = I915_READ_FW(mmio->reg); - - if (mmio->mask) { - vgpu_vreg(vgpu, mmio->reg) &= ~(mmio->mask << 16); - v = mmio->value | (mmio->mask << 16); + // save + if (pre) { + vgpu_vreg(pre, mmio->reg) = I915_READ_FW(mmio->reg); + if (mmio->mask) + vgpu_vreg(pre, mmio->reg) &= + ~(mmio->mask << 16); + old_v = vgpu_vreg(pre, mmio->reg); } else - v = mmio->value; - - if (mmio->in_context) - continue; + old_v = mmio->value = I915_READ_FW(mmio->reg); + + // restore + if (next) { + s = &next->submission; + reg_state = + s->shadow_ctx->engine[ring_id].lrc_reg_state; + ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL]; + /* + * if it is an inhibit context, load in_context mmio + * into HW by mmio write. If it is not, skip this mmio + * write. + */ + if (mmio->in_context && + (ctx_ctrl & inhibit_mask) != inhibit_mask) + continue; + + if (mmio->mask) + new_v = vgpu_vreg(next, mmio->reg) | + (mmio->mask << 16); + else + new_v = vgpu_vreg(next, mmio->reg); + } else { + if (mmio->in_context) + continue; + if (mmio->mask) + new_v = mmio->value | (mmio->mask << 16); + else + new_v = mmio->value; + } - I915_WRITE_FW(mmio->reg, v); + I915_WRITE_FW(mmio->reg, new_v); - trace_render_mmio(vgpu->id, 0, "switch", + trace_render_mmio(pre ? pre->id : 0, + next ? next->id : 0, + "switch", i915_mmio_reg_offset(mmio->reg), - mmio->value, v); + old_v, new_v); } + + if (next) + handle_tlb_pending_event(next, ring_id); } /** @@ -374,17 +358,7 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre, * handle forcewake mannually. */ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); - - /** - * TODO: Optimize for vGPU to vGPU switch by merging - * switch_mmio_to_host() and switch_mmio_to_vgpu(). - */ - if (pre) - switch_mmio_to_host(pre, ring_id); - - if (next) - switch_mmio_to_vgpu(next, ring_id); - + switch_mmio(pre, next, ring_id); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } -- GitLab From f402f2d6c3c5a5192869ffbdc079b782ef32dd01 Mon Sep 17 00:00:00 2001 From: Weinan Li Date: Wed, 13 Dec 2017 10:47:01 +0800 Subject: [PATCH 1684/2547] drm/i915/gvt: refine mocs save restore policy Save and restore the mocs regs of one VM in GVT-g burning too much CPU utilization. Add LRI command scan to monitor the change of mocs registers, save the state in vreg, and use delta update policy to restore them. It can obviously reduce the MMIO r/w count, and improve the performance of context switch. Signed-off-by: Weinan Li Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 19 ++++++++++++++ drivers/gpu/drm/i915/gvt/mmio_context.c | 33 ++++++++++++++----------- 2 files changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 18c45734c7a2..be5c519b3324 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -825,6 +825,21 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s, return 0; } +static inline bool is_mocs_mmio(unsigned int offset) +{ + return ((offset >= 0xc800) && (offset <= 0xcff8)) || + ((offset >= 0xb020) && (offset <= 0xb0a0)); +} + +static int mocs_cmd_reg_handler(struct parser_exec_state *s, + unsigned int offset, unsigned int index) +{ + if (!is_mocs_mmio(offset)) + return -EINVAL; + vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1); + return 0; +} + static int cmd_reg_handler(struct parser_exec_state *s, unsigned int offset, unsigned int index, char *cmd) { @@ -848,6 +863,10 @@ static int cmd_reg_handler(struct parser_exec_state *s, return 0; } + if (is_mocs_mmio(offset) && + mocs_cmd_reg_handler(s, offset, index)) + return -EINVAL; + if (is_force_nonpriv_mmio(offset) && force_nonpriv_reg_handler(s, offset, index)) return -EPERM; diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 5ad72fc0f9e7..06ea3d24e8d0 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -203,6 +203,8 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, { struct drm_i915_private *dev_priv; i915_reg_t offset, l3_offset; + u32 old_v, new_v; + u32 regs[] = { [RCS] = 0xc800, [VCS] = 0xc900, @@ -220,16 +222,17 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, for (i = 0; i < 64; i++) { if (pre) - vgpu_vreg(pre, offset) = - I915_READ_FW(offset); + old_v = vgpu_vreg(pre, offset); else - gen9_render_mocs[ring_id][i] = - I915_READ_FW(offset); - + old_v = gen9_render_mocs[ring_id][i] + = I915_READ_FW(offset); if (next) - I915_WRITE_FW(offset, vgpu_vreg(next, offset)); + new_v = vgpu_vreg(next, offset); else - I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]); + new_v = gen9_render_mocs[ring_id][i]; + + if (old_v != new_v) + I915_WRITE_FW(offset, new_v); offset.reg += 4; } @@ -238,17 +241,17 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, l3_offset.reg = 0xb020; for (i = 0; i < 32; i++) { if (pre) - vgpu_vreg(pre, l3_offset) = - I915_READ_FW(l3_offset); + old_v = vgpu_vreg(pre, l3_offset); else - gen9_render_mocs_L3[i] = - I915_READ_FW(l3_offset); + old_v = gen9_render_mocs_L3[i] + = I915_READ_FW(offset); if (next) - I915_WRITE_FW(l3_offset, - vgpu_vreg(next, l3_offset)); + new_v = vgpu_vreg(next, l3_offset); else - I915_WRITE_FW(l3_offset, - gen9_render_mocs_L3[i]); + new_v = gen9_render_mocs_L3[i]; + + if (old_v != new_v) + I915_WRITE_FW(l3_offset, new_v); l3_offset.reg += 4; } -- GitLab From b05b33970e333ecf8f7985d5acad759972919470 Mon Sep 17 00:00:00 2001 From: Weinan Li Date: Wed, 13 Dec 2017 10:47:02 +0800 Subject: [PATCH 1685/2547] drm/i915/gvt: load host render mocs once in mocs switch Load host render mocs registers once for delta update of mocs switch, it reduces mmio read times obviously, then brings performance improvement during multi-vms switch. Signed-off-by: Weinan Li Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/mmio_context.c | 51 ++++++++++++++++++++----- 1 file changed, 42 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 06ea3d24e8d0..94ac93996969 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -149,8 +149,41 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { { /* Terminated */ } }; -static u32 gen9_render_mocs[I915_NUM_ENGINES][64]; -static u32 gen9_render_mocs_L3[32]; +static struct { + bool initialized; + u32 control_table[I915_NUM_ENGINES][64]; + u32 l3cc_table[32]; +} gen9_render_mocs; + +static void load_render_mocs(struct drm_i915_private *dev_priv) +{ + i915_reg_t offset; + u32 regs[] = { + [RCS] = 0xc800, + [VCS] = 0xc900, + [VCS2] = 0xca00, + [BCS] = 0xcc00, + [VECS] = 0xcb00, + }; + int ring_id, i; + + for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) { + offset.reg = regs[ring_id]; + for (i = 0; i < 64; i++) { + gen9_render_mocs.control_table[ring_id][i] = + I915_READ_FW(offset); + offset.reg += 4; + } + } + + offset.reg = 0xb020; + for (i = 0; i < 32; i++) { + gen9_render_mocs.l3cc_table[i] = + I915_READ_FW(offset); + offset.reg += 4; + } + gen9_render_mocs.initialized = true; +} static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) { @@ -218,18 +251,19 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) return; - offset.reg = regs[ring_id]; + if (!pre && !gen9_render_mocs.initialized) + load_render_mocs(dev_priv); + offset.reg = regs[ring_id]; for (i = 0; i < 64; i++) { if (pre) old_v = vgpu_vreg(pre, offset); else - old_v = gen9_render_mocs[ring_id][i] - = I915_READ_FW(offset); + old_v = gen9_render_mocs.control_table[ring_id][i]; if (next) new_v = vgpu_vreg(next, offset); else - new_v = gen9_render_mocs[ring_id][i]; + new_v = gen9_render_mocs.control_table[ring_id][i]; if (old_v != new_v) I915_WRITE_FW(offset, new_v); @@ -243,12 +277,11 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, if (pre) old_v = vgpu_vreg(pre, l3_offset); else - old_v = gen9_render_mocs_L3[i] - = I915_READ_FW(offset); + old_v = gen9_render_mocs.l3cc_table[i]; if (next) new_v = vgpu_vreg(next, l3_offset); else - new_v = gen9_render_mocs_L3[i]; + new_v = gen9_render_mocs.l3cc_table[i]; if (old_v != new_v) I915_WRITE_FW(l3_offset, new_v); -- GitLab From bfe766cf65fb65e68c4764f76158718560bdcee5 Mon Sep 17 00:00:00 2001 From: Julien Thierry Date: Wed, 6 Dec 2017 17:09:49 +0000 Subject: [PATCH 1686/2547] arm64: kvm: Prevent restoring stale PMSCR_EL1 for vcpu When VHE is not present, KVM needs to save and restores PMSCR_EL1 when possible. If SPE is used by the host, value of PMSCR_EL1 cannot be saved for the guest. If the host starts using SPE between two save+restore on the same vcpu, restore will write the value of PMSCR_EL1 read during the first save. Make sure __debug_save_spe_nvhe clears the value of the saved PMSCR_EL1 when the guest cannot use SPE. Signed-off-by: Julien Thierry Cc: Christoffer Dall Cc: Marc Zyngier Cc: Catalin Marinas Cc: Reviewed-by: Will Deacon Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall --- arch/arm64/kvm/hyp/debug-sr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c index 321c9c05dd9e..f4363d40e2cd 100644 --- a/arch/arm64/kvm/hyp/debug-sr.c +++ b/arch/arm64/kvm/hyp/debug-sr.c @@ -74,6 +74,9 @@ static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1) { u64 reg; + /* Clear pmscr in case of early return */ + *pmscr_el1 = 0; + /* SPE present on this CPU? */ if (!cpuid_feature_extract_unsigned_field(read_sysreg(id_aa64dfr0_el1), ID_AA64DFR0_PMSVER_SHIFT)) -- GitLab From 7839c672e58bf62da8f2f0197fefb442c02ba1dd Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 7 Dec 2017 11:45:45 +0000 Subject: [PATCH 1687/2547] KVM: arm/arm64: Fix HYP unmapping going off limits When we unmap the HYP memory, we try to be clever and unmap one PGD at a time. If we start with a non-PGD aligned address and try to unmap a whole PGD, things go horribly wrong in unmap_hyp_range (addr and end can never match, and it all goes really badly as we keep incrementing pgd and parse random memory as page tables...). The obvious fix is to let unmap_hyp_range do what it does best, which is to iterate over a range. The size of the linear mapping, which begins at PAGE_OFFSET, can be easily calculated by subtracting PAGE_OFFSET form high_memory, because high_memory is defined as the linear map address of the last byte of DRAM, plus one. The size of the vmalloc region is given trivially by VMALLOC_END - VMALLOC_START. Cc: stable@vger.kernel.org Reported-by: Andre Przywara Tested-by: Andre Przywara Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- virt/kvm/arm/mmu.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index b36945d49986..b4b69c2d1012 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -509,8 +509,6 @@ static void unmap_hyp_range(pgd_t *pgdp, phys_addr_t start, u64 size) */ void free_hyp_pgds(void) { - unsigned long addr; - mutex_lock(&kvm_hyp_pgd_mutex); if (boot_hyp_pgd) { @@ -521,10 +519,10 @@ void free_hyp_pgds(void) if (hyp_pgd) { unmap_hyp_range(hyp_pgd, hyp_idmap_start, PAGE_SIZE); - for (addr = PAGE_OFFSET; virt_addr_valid(addr); addr += PGDIR_SIZE) - unmap_hyp_range(hyp_pgd, kern_hyp_va(addr), PGDIR_SIZE); - for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE) - unmap_hyp_range(hyp_pgd, kern_hyp_va(addr), PGDIR_SIZE); + unmap_hyp_range(hyp_pgd, kern_hyp_va(PAGE_OFFSET), + (uintptr_t)high_memory - PAGE_OFFSET); + unmap_hyp_range(hyp_pgd, kern_hyp_va(VMALLOC_START), + VMALLOC_END - VMALLOC_START); free_pages((unsigned long)hyp_pgd, hyp_pgd_order); hyp_pgd = NULL; -- GitLab From f384dcfe4d918c1d80477d290c22ce0093823771 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 7 Dec 2017 11:46:15 +0000 Subject: [PATCH 1688/2547] KVM: arm/arm64: timer: Don't set irq as forwarded if no usable GIC If we don't have a usable GIC, do not try to set the vcpu affinity as this is guaranteed to fail. Reported-by: Andre Przywara Reviewed-by: Andre Przywara Tested-by: Andre Przywara Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- include/kvm/arm_arch_timer.h | 2 +- virt/kvm/arm/arch_timer.c | 13 ++++++++----- virt/kvm/arm/arm.c | 2 +- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index 6e45608b2399..9da6ce22803f 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -62,7 +62,7 @@ struct arch_timer_cpu { bool enabled; }; -int kvm_timer_hyp_init(void); +int kvm_timer_hyp_init(bool); int kvm_timer_enable(struct kvm_vcpu *vcpu); int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu); void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu); diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index f9555b1e7f15..aa9adfafe12b 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -720,7 +720,7 @@ static int kvm_timer_dying_cpu(unsigned int cpu) return 0; } -int kvm_timer_hyp_init(void) +int kvm_timer_hyp_init(bool has_gic) { struct arch_timer_kvm_info *info; int err; @@ -756,10 +756,13 @@ int kvm_timer_hyp_init(void) return err; } - err = irq_set_vcpu_affinity(host_vtimer_irq, kvm_get_running_vcpus()); - if (err) { - kvm_err("kvm_arch_timer: error setting vcpu affinity\n"); - goto out_free_irq; + if (has_gic) { + err = irq_set_vcpu_affinity(host_vtimer_irq, + kvm_get_running_vcpus()); + if (err) { + kvm_err("kvm_arch_timer: error setting vcpu affinity\n"); + goto out_free_irq; + } } kvm_info("virtual timer IRQ%d\n", host_vtimer_irq); diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index 6b60c98a6e22..2e43f9d42bd5 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -1326,7 +1326,7 @@ static int init_subsystems(void) /* * Init HYP architected timer support */ - err = kvm_timer_hyp_init(); + err = kvm_timer_hyp_init(vgic_present); if (err) goto out; -- GitLab From 36e5cfd410ad6060b527e51d1b4bc174a8068cfd Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Thu, 14 Dec 2017 19:54:50 +0100 Subject: [PATCH 1689/2547] KVM: arm/arm64: Properly handle arch-timer IRQs after vtimer_save_state The recent timer rework was assuming that once the timer was disabled, we should no longer see any interrupts from the timer. This assumption turns out to not be true, and instead we have to handle the case when the timer ISR runs even after the timer has been disabled. This requires a couple of changes: First, we should never overwrite the cached guest state of the timer control register when the ISR runs, because KVM may have disabled its timers when doing vcpu_put(), even though the guest still had the timer enabled. Second, we shouldn't assume that the timer is actually firing just because we see an interrupt, but we should check the actual state of the timer in the timer control register to understand if the hardware timer is really firing or not. We also add an ISB to vtimer_save_state() to ensure the timer is actually disabled once we enable interrupts, which should clarify the intention of the implementation, and reduce the risk of unwanted interrupts. Fixes: b103cc3f10c0 ("KVM: arm/arm64: Avoid timer save/restore in vcpu entry/exit") Reported-by: Marc Zyngier Reported-by: Jia He Reviewed-by: Marc Zyngier Tested-by: Marc Zyngier Signed-off-by: Christoffer Dall --- virt/kvm/arm/arch_timer.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index aa9adfafe12b..14c018f990a7 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -92,16 +92,23 @@ static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id) { struct kvm_vcpu *vcpu = *(struct kvm_vcpu **)dev_id; struct arch_timer_context *vtimer; + u32 cnt_ctl; - if (!vcpu) { - pr_warn_once("Spurious arch timer IRQ on non-VCPU thread\n"); - return IRQ_NONE; - } - vtimer = vcpu_vtimer(vcpu); + /* + * We may see a timer interrupt after vcpu_put() has been called which + * sets the CPU's vcpu pointer to NULL, because even though the timer + * has been disabled in vtimer_save_state(), the hardware interrupt + * signal may not have been retired from the interrupt controller yet. + */ + if (!vcpu) + return IRQ_HANDLED; + vtimer = vcpu_vtimer(vcpu); if (!vtimer->irq.level) { - vtimer->cnt_ctl = read_sysreg_el0(cntv_ctl); - if (kvm_timer_irq_can_fire(vtimer)) + cnt_ctl = read_sysreg_el0(cntv_ctl); + cnt_ctl &= ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_STAT | + ARCH_TIMER_CTRL_IT_MASK; + if (cnt_ctl == (ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_STAT)) kvm_timer_update_irq(vcpu, true, vtimer); } @@ -355,6 +362,7 @@ static void vtimer_save_state(struct kvm_vcpu *vcpu) /* Disable the virtual timer */ write_sysreg_el0(0, cntv_ctl); + isb(); vtimer->loaded = false; out: -- GitLab From 0eb7c33cadf6b2f1a94e58ded8b0eb89b4eba382 Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Fri, 15 Dec 2017 00:30:12 +0100 Subject: [PATCH 1690/2547] KVM: arm/arm64: Fix timer enable flow When enabling the timer on the first run, we fail to ever restore the state and mark it as loaded. That means, that in the initial entry to the VCPU ioctl, unless we exit to userspace for some reason such as a pending signal, if the guest programs a timer and blocks, we will wait forever, because we never read back the hardware state (the loaded flag is not set), and so we think the timer is disabled, and we never schedule a background soft timer. The end result? The VCPU blocks forever, and the only solution is to kill the thread. Fixes: 4a2c4da1250d ("arm/arm64: KVM: Load the timer state when enabling the timer") Reported-by: Marc Zyngier Reviewed-by: Marc Zyngier Tested-by: Marc Zyngier Signed-off-by: Christoffer Dall --- virt/kvm/arm/arch_timer.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index 14c018f990a7..cc29a8148328 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -846,10 +846,7 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) no_vgic: preempt_disable(); timer->enabled = 1; - if (!irqchip_in_kernel(vcpu->kvm)) - kvm_timer_vcpu_load_user(vcpu); - else - kvm_timer_vcpu_load_vgic(vcpu); + kvm_timer_vcpu_load(vcpu); preempt_enable(); return 0; -- GitLab From 9226665159f0367ad08bc7d5dd194aeadb90316f Mon Sep 17 00:00:00 2001 From: Kailang Yang Date: Thu, 14 Dec 2017 15:28:58 +0800 Subject: [PATCH 1691/2547] ALSA: hda/realtek - Fix Dell AIO LineOut issue Dell AIO had LineOut jack. Add LineOut verb into this patch. [ Additional notes: the ALC274 codec seems requiring the fixed pin / DAC connections for HP / line-out pins for enabling EQ for speakers; i.e. the HP / LO pins expect to be connected with NID 0x03 while keeping the speaker with NID 0x02. However, by adding a new line-out pin, the auto-parser assigns the NID 0x02 for HP/LO pins as primary outputs. As an easy workaround, we provide the preferred_pairs[] to map forcibly for these pins. -- tiwai ] Fixes: 75ee94b20b46 ("ALSA: hda - fix headset mic problem for Dell machines with alc274") Signed-off-by: Kailang Yang Cc: Signed-off-by: Takashi Iwai --- sound/pci/hda/patch_realtek.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 4b21f71d685c..6a4db00511ab 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -5185,6 +5185,22 @@ static void alc233_alc662_fixup_lenovo_dual_codecs(struct hda_codec *codec, } } +/* Forcibly assign NID 0x03 to HP/LO while NID 0x02 to SPK for EQ */ +static void alc274_fixup_bind_dacs(struct hda_codec *codec, + const struct hda_fixup *fix, int action) +{ + struct alc_spec *spec = codec->spec; + static hda_nid_t preferred_pairs[] = { + 0x21, 0x03, 0x1b, 0x03, 0x16, 0x02, + 0 + }; + + if (action != HDA_FIXUP_ACT_PRE_PROBE) + return; + + spec->gen.preferred_dacs = preferred_pairs; +} + /* for hda_fixup_thinkpad_acpi() */ #include "thinkpad_helper.c" @@ -5302,6 +5318,8 @@ enum { ALC233_FIXUP_LENOVO_MULTI_CODECS, ALC294_FIXUP_LENOVO_MIC_LOCATION, ALC700_FIXUP_INTEL_REFERENCE, + ALC274_FIXUP_DELL_BIND_DACS, + ALC274_FIXUP_DELL_AIO_LINEOUT_VERB, }; static const struct hda_fixup alc269_fixups[] = { @@ -6112,6 +6130,21 @@ static const struct hda_fixup alc269_fixups[] = { {} } }, + [ALC274_FIXUP_DELL_BIND_DACS] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc274_fixup_bind_dacs, + .chained = true, + .chain_id = ALC269_FIXUP_DELL1_MIC_NO_PRESENCE + }, + [ALC274_FIXUP_DELL_AIO_LINEOUT_VERB] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x1b, 0x0401102f }, + { } + }, + .chained = true, + .chain_id = ALC274_FIXUP_DELL_BIND_DACS + }, }; static const struct snd_pci_quirk alc269_fixup_tbl[] = { @@ -6578,7 +6611,7 @@ static const struct snd_hda_pin_quirk alc269_pin_fixup_tbl[] = { {0x14, 0x90170110}, {0x1b, 0x90a70130}, {0x21, 0x03211020}), - SND_HDA_PIN_QUIRK(0x10ec0274, 0x1028, "Dell", ALC269_FIXUP_DELL1_MIC_NO_PRESENCE, + SND_HDA_PIN_QUIRK(0x10ec0274, 0x1028, "Dell", ALC274_FIXUP_DELL_AIO_LINEOUT_VERB, {0x12, 0xb7a60130}, {0x13, 0xb8a61140}, {0x16, 0x90170110}, -- GitLab From 5839ee7389e893a31e4e3c9cf17b50d14103c902 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Fri, 15 Dec 2017 03:07:18 +0100 Subject: [PATCH 1692/2547] PCI / PM: Force devices to D0 in pci_pm_thaw_noirq() It is incorrect to call pci_restore_state() for devices in low-power states (D1-D3), as that involves the restoration of MSI setup which requires MMIO to be operational and that is only the case in D0. However, pci_pm_thaw_noirq() may do that if the driver's "freeze" callbacks put the device into a low-power state, so fix it by making it force devices into D0 via pci_set_power_state() instead of trying to "update" their power state which is pointless. Fixes: e60514bd4485 (PCI/PM: Restore the status of PCI devices across hibernation) Cc: 4.13+ # 4.13+ Reported-by: Thomas Gleixner Reported-by: Maarten Lankhorst Tested-by: Thomas Gleixner Tested-by: Maarten Lankhorst Signed-off-by: Rafael J. Wysocki Acked-by: Bjorn Helgaas --- drivers/pci/pci-driver.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 945099d49f8f..14fd865a5120 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -1012,7 +1012,12 @@ static int pci_pm_thaw_noirq(struct device *dev) if (pci_has_legacy_pm_support(pci_dev)) return pci_legacy_resume_early(dev); - pci_update_current_state(pci_dev, PCI_D0); + /* + * pci_restore_state() requires the device to be in D0 (because of MSI + * restoration among other things), so force it into D0 in case the + * driver's "freeze" callbacks put it into a low-power state directly. + */ + pci_set_power_state(pci_dev, PCI_D0); pci_restore_state(pci_dev); if (drv && drv->pm && drv->pm->thaw_noirq) -- GitLab From ccc153a6de1f7741b5ef7c996f9be133772b2092 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 11 Dec 2017 14:19:00 +0100 Subject: [PATCH 1693/2547] cpufreq: imx6q: fix speed grading regression on i.MX6 QuadPlus The commit moving the speed grading check to the cpufreq driver introduced some additional checks, so the OPP disable is only attempted on SoCs where those OPPs are present. The compatible checks are missing the QuadPlus compatible, so invalid OPPs are not correctly disabled there. Move both checks to a single condition, so we don't need to sprinkle even more calls to of_machine_is_compatible(). Fixes: 2b3d58a3adca (cpufreq: imx6q: Move speed grading check to cpufreq driver) Signed-off-by: Lucas Stach Acked-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki --- drivers/cpufreq/imx6q-cpufreq.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..d9b2c2de49c4 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -226,17 +226,18 @@ static void imx6q_opp_check_speed_grading(struct device *dev) val >>= OCOTP_CFG3_SPEED_SHIFT; val &= 0x3; - if ((val != OCOTP_CFG3_SPEED_1P2GHZ) && - of_machine_is_compatible("fsl,imx6q")) - if (dev_pm_opp_disable(dev, 1200000000)) - dev_warn(dev, "failed to disable 1.2GHz OPP\n"); if (val < OCOTP_CFG3_SPEED_996MHZ) if (dev_pm_opp_disable(dev, 996000000)) dev_warn(dev, "failed to disable 996MHz OPP\n"); - if (of_machine_is_compatible("fsl,imx6q")) { + + if (of_machine_is_compatible("fsl,imx6q") || + of_machine_is_compatible("fsl,imx6qp")) { if (val != OCOTP_CFG3_SPEED_852MHZ) if (dev_pm_opp_disable(dev, 852000000)) dev_warn(dev, "failed to disable 852MHz OPP\n"); + if (val != OCOTP_CFG3_SPEED_1P2GHZ) + if (dev_pm_opp_disable(dev, 1200000000)) + dev_warn(dev, "failed to disable 1.2GHz OPP\n"); } iounmap(base); put_node: -- GitLab From 56026645e2b6f11ede34a5e6ab69d3eb56f9c8fc Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Mon, 18 Dec 2017 02:15:32 +0100 Subject: [PATCH 1694/2547] cpufreq: governor: Ensure sufficiently large sampling intervals After commit aa7519af450d (cpufreq: Use transition_delay_us for legacy governors as well) the sampling_rate field of struct dbs_data may be less than the tick period which causes dbs_update() to produce incorrect results, so make the code ensure that the value of that field will always be sufficiently large. Fixes: aa7519af450d (cpufreq: Use transition_delay_us for legacy governors as well) Reported-by: Andy Tang Reported-by: Doug Smythies Tested-by: Andy Tang Signed-off-by: Rafael J. Wysocki Acked-by: Viresh Kumar --- drivers/cpufreq/cpufreq_governor.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/cpufreq_governor.c b/drivers/cpufreq/cpufreq_governor.c index 58d4f4e1ad6a..ca38229b045a 100644 --- a/drivers/cpufreq/cpufreq_governor.c +++ b/drivers/cpufreq/cpufreq_governor.c @@ -22,6 +22,8 @@ #include "cpufreq_governor.h" +#define CPUFREQ_DBS_MIN_SAMPLING_INTERVAL (2 * TICK_NSEC / NSEC_PER_USEC) + static DEFINE_PER_CPU(struct cpu_dbs_info, cpu_dbs); static DEFINE_MUTEX(gov_dbs_data_mutex); @@ -47,11 +49,15 @@ ssize_t store_sampling_rate(struct gov_attr_set *attr_set, const char *buf, { struct dbs_data *dbs_data = to_dbs_data(attr_set); struct policy_dbs_info *policy_dbs; + unsigned int sampling_interval; int ret; - ret = sscanf(buf, "%u", &dbs_data->sampling_rate); - if (ret != 1) + + ret = sscanf(buf, "%u", &sampling_interval); + if (ret != 1 || sampling_interval < CPUFREQ_DBS_MIN_SAMPLING_INTERVAL) return -EINVAL; + dbs_data->sampling_rate = sampling_interval; + /* * We are operating under dbs_data->mutex and so the list and its * entries can't be freed concurrently. @@ -430,7 +436,14 @@ int cpufreq_dbs_governor_init(struct cpufreq_policy *policy) if (ret) goto free_policy_dbs_info; - dbs_data->sampling_rate = cpufreq_policy_transition_delay_us(policy); + /* + * The sampling interval should not be less than the transition latency + * of the CPU and it also cannot be too small for dbs_update() to work + * correctly. + */ + dbs_data->sampling_rate = max_t(unsigned int, + CPUFREQ_DBS_MIN_SAMPLING_INTERVAL, + cpufreq_policy_transition_delay_us(policy)); if (!have_governor_per_policy()) gov->gdbs_data = dbs_data; -- GitLab From 951ef0e19f0736b45d1c4d81f4dfa04a43f87df5 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Fri, 8 Dec 2017 23:59:49 +0000 Subject: [PATCH 1695/2547] ACPI: CPPC: remove initial assignment of pcc_ss_data The initialization of pcc_ss_data from pcc_data[pcc_ss_id] before pcc_ss_id is being range checked could lead to an out-of-bounds array read. This very same initialization is also being performed after the range check on pcc_ss_id, so we can just remove this problematic and also redundant assignment to fix the issue. Detected by cppcheck: warning: Value stored to 'pcc_ss_data' during its initialization is never read Fixes: 85b1407bf6d2 (ACPI / CPPC: Make CPPC ACPI driver aware of PCC subspace IDs) Signed-off-by: Colin Ian King Signed-off-by: Rafael J. Wysocki --- drivers/acpi/cppc_acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 30e84cc600ae..06ea4749ebd9 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1171,7 +1171,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); struct cpc_register_resource *desired_reg; int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); - struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; + struct cppc_pcc_data *pcc_ss_data; int ret = 0; if (!cpc_desc || pcc_ss_id < 0) { -- GitLab From bb82e0b4a7e96494f0c1004ce50cec3d7b5fb3d1 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Thu, 14 Dec 2017 13:31:16 +0100 Subject: [PATCH 1696/2547] ACPI: APEI / ERST: Fix missing error handling in erst_reader() The commit f6f828513290 ("pstore: pass allocated memory region back to caller") changed the check of the return value from erst_read() in erst_reader() in the following way: if (len == -ENOENT) goto skip; - else if (len < 0) { - rc = -1; + else if (len < sizeof(*rcd)) { + rc = -EIO; goto out; This introduced another bug: since the comparison with sizeof() is cast to unsigned, a negative len value doesn't hit any longer. As a result, when an error is returned from erst_read(), the code falls through, and it may eventually lead to some weird thing like memory corruption. This patch adds the negative error value check more explicitly for addressing the issue. Fixes: f6f828513290 (pstore: pass allocated memory region back to caller) Cc: All applicable Tested-by: Jerry Tang Signed-off-by: Takashi Iwai Acked-by: Kees Cook Reviewed-by: Borislav Petkov Signed-off-by: Rafael J. Wysocki --- drivers/acpi/apei/erst.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/apei/erst.c b/drivers/acpi/apei/erst.c index 6742f6c68034..9bff853e85f3 100644 --- a/drivers/acpi/apei/erst.c +++ b/drivers/acpi/apei/erst.c @@ -1007,7 +1007,7 @@ static ssize_t erst_reader(struct pstore_record *record) /* The record may be cleared by others, try read next record */ if (len == -ENOENT) goto skip; - else if (len < sizeof(*rcd)) { + else if (len < 0 || len < sizeof(*rcd)) { rc = -EIO; goto out; } -- GitLab From a31d73c3a7218539bc25fc298ac6cd5b66d96b86 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sun, 17 Dec 2017 13:28:50 +0000 Subject: [PATCH 1697/2547] drm/i915: Re-enable GGTT earlier after GPU reset Inside i915_gem_reset(), we start touching the HW and so require the low-level HW to be re-enabled, in particular the PCI BARs. Fixes: 7b6da818d86f ("drm/i915: Restore the kernel context after a GPU reset on an idle engine") References: 0db8c9612091 ("drm/i915: Re-enable GTT following a device reset") Testcase: igt/drv_hangman #i915g/i915gm Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Cc: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20171217132852.30642-1-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_drv.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6d39fdf2b604..72bea281edb7 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1924,9 +1924,6 @@ void i915_reset(struct drm_i915_private *i915, unsigned int flags) goto taint; } - i915_gem_reset(i915); - intel_overlay_reset(i915); - /* Ok, now get things going again... */ /* @@ -1939,6 +1936,9 @@ void i915_reset(struct drm_i915_private *i915, unsigned int flags) goto error; } + i915_gem_reset(i915); + intel_overlay_reset(i915); + /* * Next we need to restore the context, but we don't use those * yet either... -- GitLab From 4e5ca2d930aa8714400aedf4bf1dc959cb04280f Mon Sep 17 00:00:00 2001 From: Logan Gunthorpe Date: Tue, 5 Dec 2017 16:30:51 -0700 Subject: [PATCH 1698/2547] drm/tilcdc: ensure nonatomic iowrite64 is not used Add a check to ensure iowrite64 is only used if it is atomic. It was decided in [1] that the tilcdc driver should not be using an atomic operation (so it was left out of this patchset). However, it turns out that through the drm code, a nonatomic header is actually included: include/linux/io-64-nonatomic-lo-hi.h is included from include/drm/drm_os_linux.h:9:0, from include/drm/drmP.h:74, from include/drm/drm_modeset_helper.h:26, from include/drm/drm_atomic_helper.h:33, from drivers/gpu/drm/tilcdc/tilcdc_crtc.c:19: And thus, without this change, this patchset would inadvertantly change the behaviour of the tilcdc driver. [1] lkml.kernel.org/r/CAK8P3a2HhO_zCnsTzq7hmWSz5La5Thu19FWZpun16iMnyyNreQ@mail.gmail.com Signed-off-by: Logan Gunthorpe Reviewed-by: Andy Shevchenko Cc: Jyri Sarha Cc: Arnd Bergmann Cc: Tomi Valkeinen Cc: David Airlie Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_regs.h b/drivers/gpu/drm/tilcdc/tilcdc_regs.h index 9d528c0a67a4..5048ebb86835 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_regs.h +++ b/drivers/gpu/drm/tilcdc/tilcdc_regs.h @@ -133,7 +133,7 @@ static inline void tilcdc_write64(struct drm_device *dev, u32 reg, u64 data) struct tilcdc_drm_private *priv = dev->dev_private; volatile void __iomem *addr = priv->mmio + reg; -#ifdef iowrite64 +#if defined(iowrite64) && !defined(iowrite64_is_nonatomic) iowrite64(data, addr); #else __iowmb(); -- GitLab From 1775ede035a425ff35b73d6daceb619061278ade Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Fri, 3 Nov 2017 23:30:54 +0200 Subject: [PATCH 1699/2547] drm/tilcdc: Remove drm_framebuffer_get() and *_put() calls The drm_framebuffer_get() and drm_framebuffer_put() calls in the tilcdc driver are obsolete. The drm atomic modesetting core should take care of holding the references while the atomic state object is in use. The old state is deleted when a commit of a new one is completed after drm_atomic_helper_wait_for_vblanks(). This also fixes an occasional framebuffer leak the old drm_framebuffer_get() and drm_framebuffer_put() code had. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 49 ---------------------------- 1 file changed, 49 deletions(-) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index 6ef4d1a1e3a9..b81a593aefb2 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -51,12 +51,8 @@ struct tilcdc_crtc { ktime_t last_vblank; unsigned int hvtotal_us; - struct drm_framebuffer *curr_fb; struct drm_framebuffer *next_fb; - /* for deferred fb unref's: */ - struct drm_flip_work unref_work; - /* Only set if an external encoder is connected */ bool simulate_vesa_sync; @@ -70,20 +66,8 @@ struct tilcdc_crtc { }; #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) -static void unref_worker(struct drm_flip_work *work, void *val) -{ - struct tilcdc_crtc *tilcdc_crtc = - container_of(work, struct tilcdc_crtc, unref_work); - struct drm_device *dev = tilcdc_crtc->base.dev; - - mutex_lock(&dev->mode_config.mutex); - drm_framebuffer_put(val); - mutex_unlock(&dev->mode_config.mutex); -} - static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) { - struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); struct drm_device *dev = crtc->dev; struct tilcdc_drm_private *priv = dev->dev_private; struct drm_gem_cma_object *gem; @@ -108,12 +92,6 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) dma_base_and_ceiling = (u64)end << 32 | start; tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling); - - if (tilcdc_crtc->curr_fb) - drm_flip_work_queue(&tilcdc_crtc->unref_work, - tilcdc_crtc->curr_fb); - - tilcdc_crtc->curr_fb = fb; } /* @@ -464,8 +442,6 @@ static void tilcdc_crtc_set_mode(struct drm_crtc *crtc) set_scanout(crtc, fb); - drm_framebuffer_get(fb); - crtc->hwmode = crtc->state->adjusted_mode; tilcdc_crtc->hvtotal_us = @@ -524,7 +500,6 @@ static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown) { struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); struct drm_device *dev = crtc->dev; - struct tilcdc_drm_private *priv = dev->dev_private; int ret; mutex_lock(&tilcdc_crtc->enable_lock); @@ -554,20 +529,6 @@ static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown) pm_runtime_put_sync(dev->dev); - if (tilcdc_crtc->next_fb) { - drm_flip_work_queue(&tilcdc_crtc->unref_work, - tilcdc_crtc->next_fb); - tilcdc_crtc->next_fb = NULL; - } - - if (tilcdc_crtc->curr_fb) { - drm_flip_work_queue(&tilcdc_crtc->unref_work, - tilcdc_crtc->curr_fb); - tilcdc_crtc->curr_fb = NULL; - } - - drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); - tilcdc_crtc->enabled = false; mutex_unlock(&tilcdc_crtc->enable_lock); } @@ -614,7 +575,6 @@ static void tilcdc_crtc_recover_work(struct work_struct *work) static void tilcdc_crtc_destroy(struct drm_crtc *crtc) { - struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); struct tilcdc_drm_private *priv = crtc->dev->dev_private; tilcdc_crtc_shutdown(crtc); @@ -623,7 +583,6 @@ static void tilcdc_crtc_destroy(struct drm_crtc *crtc) of_node_put(crtc->port); drm_crtc_cleanup(crtc); - drm_flip_work_cleanup(&tilcdc_crtc->unref_work); } int tilcdc_crtc_update_fb(struct drm_crtc *crtc, @@ -638,9 +597,6 @@ int tilcdc_crtc_update_fb(struct drm_crtc *crtc, return -EBUSY; } - drm_framebuffer_get(fb); - - crtc->primary->fb = fb; tilcdc_crtc->event = event; mutex_lock(&tilcdc_crtc->enable_lock); @@ -936,8 +892,6 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) now = ktime_get(); - drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); - spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); tilcdc_crtc->last_vblank = now; @@ -1064,9 +1018,6 @@ int tilcdc_crtc_create(struct drm_device *dev) init_waitqueue_head(&tilcdc_crtc->frame_done_wq); - drm_flip_work_init(&tilcdc_crtc->unref_work, - "unref", unref_worker); - spin_lock_init(&tilcdc_crtc->irq_lock); INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work); -- GitLab From b65a9b98218fe1e3ae1ad2c240c39179f1dd1b9a Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Mon, 18 Dec 2017 10:38:55 +0000 Subject: [PATCH 1700/2547] drm/i915: prefer i915_gem_object_has_pages() We have an existing helper for testing obj->mm.pages, so use it. Signed-off-by: Matthew Auld Cc: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171218103855.25274-1-matthew.auld@intel.com Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index dca15c13af35..5b4cfb20de97 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2596,7 +2596,7 @@ static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) } err = obj->ops->get_pages(obj); - GEM_BUG_ON(!err && IS_ERR_OR_NULL(obj->mm.pages)); + GEM_BUG_ON(!err && !i915_gem_object_has_pages(obj)); return err; } diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c index e6b31041cc88..2ea69394f428 100644 --- a/drivers/gpu/drm/i915/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c @@ -1637,7 +1637,7 @@ static int igt_shrink_thp(void *arg) * shmem to truncate our pages. */ i915_gem_shrink_all(i915); - if (!IS_ERR_OR_NULL(obj->mm.pages)) { + if (i915_gem_object_has_pages(obj)) { pr_err("shrink-all didn't truncate the pages\n"); err = -EINVAL; goto out_close; -- GitLab From e39d200fa5bf5b94a0948db0dae44c1b73b84a56 Mon Sep 17 00:00:00 2001 From: Wanpeng Li Date: Thu, 14 Dec 2017 17:40:50 -0800 Subject: [PATCH 1701/2547] KVM: Fix stack-out-of-bounds read in write_mmio MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reported by syzkaller: BUG: KASAN: stack-out-of-bounds in write_mmio+0x11e/0x270 [kvm] Read of size 8 at addr ffff8803259df7f8 by task syz-executor/32298 CPU: 6 PID: 32298 Comm: syz-executor Tainted: G OE 4.15.0-rc2+ #18 Hardware name: LENOVO ThinkCentre M8500t-N000/SHARKBAY, BIOS FBKTC1AUS 02/16/2016 Call Trace: dump_stack+0xab/0xe1 print_address_description+0x6b/0x290 kasan_report+0x28a/0x370 write_mmio+0x11e/0x270 [kvm] emulator_read_write_onepage+0x311/0x600 [kvm] emulator_read_write+0xef/0x240 [kvm] emulator_fix_hypercall+0x105/0x150 [kvm] em_hypercall+0x2b/0x80 [kvm] x86_emulate_insn+0x2b1/0x1640 [kvm] x86_emulate_instruction+0x39a/0xb90 [kvm] handle_exception+0x1b4/0x4d0 [kvm_intel] vcpu_enter_guest+0x15a0/0x2640 [kvm] kvm_arch_vcpu_ioctl_run+0x549/0x7d0 [kvm] kvm_vcpu_ioctl+0x479/0x880 [kvm] do_vfs_ioctl+0x142/0x9a0 SyS_ioctl+0x74/0x80 entry_SYSCALL_64_fastpath+0x23/0x9a The path of patched vmmcall will patch 3 bytes opcode 0F 01 C1(vmcall) to the guest memory, however, write_mmio tracepoint always prints 8 bytes through *(u64 *)val since kvm splits the mmio access into 8 bytes. This leaks 5 bytes from the kernel stack (CVE-2017-17741). This patch fixes it by just accessing the bytes which we operate on. Before patch: syz-executor-5567 [007] .... 51370.561696: kvm_mmio: mmio write len 3 gpa 0x10 val 0x1ffff10077c1010f After patch: syz-executor-13416 [002] .... 51302.299573: kvm_mmio: mmio write len 3 gpa 0x10 val 0xc1010f Reported-by: Dmitry Vyukov Reviewed-by: Darren Kenny Reviewed-by: Marc Zyngier Tested-by: Marc Zyngier Cc: Paolo Bonzini Cc: Radim Krčmář Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Wanpeng Li Signed-off-by: Paolo Bonzini --- arch/x86/kvm/x86.c | 8 ++++---- include/trace/events/kvm.h | 7 +++++-- virt/kvm/arm/mmio.c | 6 +++--- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 3a82f2d4333b..1cec2c62a0b0 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4384,7 +4384,7 @@ static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) addr, n, v)) && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) break; - trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); + trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); handled += n; addr += n; len -= n; @@ -4643,7 +4643,7 @@ static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) { if (vcpu->mmio_read_completed) { trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, - vcpu->mmio_fragments[0].gpa, *(u64 *)val); + vcpu->mmio_fragments[0].gpa, val); vcpu->mmio_read_completed = 0; return 1; } @@ -4665,14 +4665,14 @@ static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) { - trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); + trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); return vcpu_mmio_write(vcpu, gpa, bytes, val); } static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, void *val, int bytes) { - trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); + trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); return X86EMUL_IO_NEEDED; } diff --git a/include/trace/events/kvm.h b/include/trace/events/kvm.h index e4b0b8e09932..2c735a3e6613 100644 --- a/include/trace/events/kvm.h +++ b/include/trace/events/kvm.h @@ -211,7 +211,7 @@ TRACE_EVENT(kvm_ack_irq, { KVM_TRACE_MMIO_WRITE, "write" } TRACE_EVENT(kvm_mmio, - TP_PROTO(int type, int len, u64 gpa, u64 val), + TP_PROTO(int type, int len, u64 gpa, void *val), TP_ARGS(type, len, gpa, val), TP_STRUCT__entry( @@ -225,7 +225,10 @@ TRACE_EVENT(kvm_mmio, __entry->type = type; __entry->len = len; __entry->gpa = gpa; - __entry->val = val; + __entry->val = 0; + if (val) + memcpy(&__entry->val, val, + min_t(u32, sizeof(__entry->val), len)); ), TP_printk("mmio %s len %u gpa 0x%llx val 0x%llx", diff --git a/virt/kvm/arm/mmio.c b/virt/kvm/arm/mmio.c index b6e715fd3c90..dac7ceb1a677 100644 --- a/virt/kvm/arm/mmio.c +++ b/virt/kvm/arm/mmio.c @@ -112,7 +112,7 @@ int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run) } trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr, - data); + &data); data = vcpu_data_host_to_guest(vcpu, data, len); vcpu_set_reg(vcpu, vcpu->arch.mmio_decode.rt, data); } @@ -182,14 +182,14 @@ int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run, data = vcpu_data_guest_to_host(vcpu, vcpu_get_reg(vcpu, rt), len); - trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, len, fault_ipa, data); + trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, len, fault_ipa, &data); kvm_mmio_write_buf(data_buf, len, data); ret = kvm_io_bus_write(vcpu, KVM_MMIO_BUS, fault_ipa, len, data_buf); } else { trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, len, - fault_ipa, 0); + fault_ipa, NULL); ret = kvm_io_bus_read(vcpu, KVM_MMIO_BUS, fault_ipa, len, data_buf); -- GitLab From 9d5f38ba6c82359b7cec31fb27fb78ecc02f3946 Mon Sep 17 00:00:00 2001 From: Tom Lendacky Date: Fri, 15 Dec 2017 10:20:12 -0600 Subject: [PATCH 1702/2547] x86/mm: Unbreak modules that use the DMA API Commit d8aa7eea78a1 ("x86/mm: Add Secure Encrypted Virtualization (SEV) support") changed sme_active() from an inline function that referenced sme_me_mask to a non-inlined function in order to make the sev_enabled variable a static variable. This function was marked EXPORT_SYMBOL_GPL because at the time the patch was submitted, sme_me_mask was marked EXPORT_SYMBOL_GPL. Commit 87df26175e67 ("x86/mm: Unbreak modules that rely on external PAGE_KERNEL availability") changed sme_me_mask variable from EXPORT_SYMBOL_GPL to EXPORT_SYMBOL, allowing external modules the ability to build with CONFIG_AMD_MEM_ENCRYPT=y. Now, however, with sev_active() no longer an inline function and marked as EXPORT_SYMBOL_GPL, external modules that use the DMA API are once again broken in 4.15. Since the DMA API is meant to be used by external modules, this needs to be changed. Change the sme_active() and sev_active() functions from EXPORT_SYMBOL_GPL to EXPORT_SYMBOL. Signed-off-by: Tom Lendacky Signed-off-by: Thomas Gleixner Cc: Borislav Petkov Cc: Brijesh Singh Link: https://lkml.kernel.org/r/20171215162011.14125.7113.stgit@tlendack-t1.amdoffice.net --- arch/x86/mm/mem_encrypt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index d9a9e9fc75dd..391b13402e40 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -405,13 +405,13 @@ bool sme_active(void) { return sme_me_mask && !sev_enabled; } -EXPORT_SYMBOL_GPL(sme_active); +EXPORT_SYMBOL(sme_active); bool sev_active(void) { return sme_me_mask && sev_enabled; } -EXPORT_SYMBOL_GPL(sev_active); +EXPORT_SYMBOL(sev_active); static const struct dma_map_ops sev_dma_ops = { .alloc = sev_alloc, -- GitLab From bf29cb238dc0656e6564b6a94bb82e11d2129437 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 14 Dec 2017 19:18:25 +0100 Subject: [PATCH 1703/2547] sched/isolation: Make CONFIG_NO_HZ_FULL select CONFIG_CPU_ISOLATION CONFIG_NO_HZ_FULL doesn't make sense without CONFIG_CPU_ISOLATION. In fact enabling the first without the second is a regression as nohz_full= boot parameter gets silently ignored. Besides this unnatural combination hangs RCU gp kthread when running rcutorture for reasons that are not yet fully understood: rcu_preempt kthread starved for 9974 jiffies! g4294967208 +c4294967207 f0x0 RCU_GP_WAIT_FQS(3) ->state=0x402 ->cpu=0 rcu_preempt I 7464 8 2 0x80000000 Call Trace: __schedule+0x493/0x620 schedule+0x24/0x40 schedule_timeout+0x330/0x3b0 ? preempt_count_sub+0xea/0x140 ? collect_expired_timers+0xb0/0xb0 rcu_gp_kthread+0x6bf/0xef0 This commit therefore makes NO_HZ_FULL select CPU_ISOLATION, which prevents all these bad behaviours. Reported-by: kernel test robot Signed-off-by: Paul E. McKenney Signed-off-by: Frederic Weisbecker Cc: Chris Metcalf Cc: Christoph Lameter Cc: John Stultz Cc: Linus Torvalds Cc: Luiz Capitulino Cc: Mike Galbraith Cc: Peter Zijlstra Cc: Rik van Riel Cc: Thomas Gleixner Cc: Wanpeng Li Fixes: 5c4991e24c69 ("sched/isolation: Split out new CONFIG_CPU_ISOLATION=y config from CONFIG_NO_HZ_FULL") Link: http://lkml.kernel.org/r/1513275507-29200-2-git-send-email-frederic@kernel.org Signed-off-by: Ingo Molnar --- kernel/time/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/time/Kconfig b/kernel/time/Kconfig index e776fc8cc1df..f6b5f19223d6 100644 --- a/kernel/time/Kconfig +++ b/kernel/time/Kconfig @@ -95,6 +95,7 @@ config NO_HZ_FULL select RCU_NOCB_CPU select VIRT_CPU_ACCOUNTING_GEN select IRQ_WORK + select CPU_ISOLATION help Adaptively try to shutdown the tick whenever possible, even when the CPU is running tasks. Typically this requires running a single -- GitLab From 2c43838c99d9d23f17eb2bdadafcb2879cca6995 Mon Sep 17 00:00:00 2001 From: Frederic Weisbecker Date: Thu, 14 Dec 2017 19:18:26 +0100 Subject: [PATCH 1704/2547] sched/isolation: Enable CONFIG_CPU_ISOLATION=y by default The "isolcpus=" boot parameter support was always built-in before we moved the related code under CONFIG_CPU_ISOLATION. Having it disabled by default is very confusing for people accustomed to use this parameter. So enable it by dafault to keep the previous behaviour but keep it optable for those who want to tinify their kernels. Signed-off-by: Frederic Weisbecker Cc: Chris Metcalf Cc: Christoph Lameter Cc: John Stultz Cc: Linus Torvalds Cc: Luiz Capitulino Cc: Mike Galbraith Cc: Paul E. McKenney Cc: Peter Zijlstra Cc: Rik van Riel Cc: Thomas Gleixner Cc: Wanpeng Li Cc: kernel test robot Link: http://lkml.kernel.org/r/1513275507-29200-3-git-send-email-frederic@kernel.org Signed-off-by: Ingo Molnar --- init/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/init/Kconfig b/init/Kconfig index 2934249fba46..690a381adee0 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -461,10 +461,14 @@ endmenu # "CPU/Task time and stats accounting" config CPU_ISOLATION bool "CPU isolation" + default y help Make sure that CPUs running critical tasks are not disturbed by any source of "noise" such as unbound workqueues, timers, kthreads... - Unbound jobs get offloaded to housekeeping CPUs. + Unbound jobs get offloaded to housekeeping CPUs. This is driven by + the "isolcpus=" boot parameter. + + Say Y if unsure. source "kernel/rcu/Kconfig" -- GitLab From d94d105329e4a8a874853b5bd854b6587c41adda Mon Sep 17 00:00:00 2001 From: Frederic Weisbecker Date: Thu, 14 Dec 2017 19:18:27 +0100 Subject: [PATCH 1705/2547] sched/isolation: Document boot parameters dependency on CONFIG_CPU_ISOLATION=y The "isolcpus=" and "nohz_full=" boot parameters depend on CPU Isolation support. Let's document that. Signed-off-by: Frederic Weisbecker Cc: Chris Metcalf Cc: Christoph Lameter Cc: John Stultz Cc: Linus Torvalds Cc: Luiz Capitulino Cc: Mike Galbraith Cc: Paul E. McKenney Cc: Peter Zijlstra Cc: Rik van Riel Cc: Thomas Gleixner Cc: Wanpeng Li Cc: kernel test robot Link: http://lkml.kernel.org/r/1513275507-29200-4-git-send-email-frederic@kernel.org Signed-off-by: Ingo Molnar --- Documentation/admin-guide/kernel-parameters.rst | 1 + Documentation/admin-guide/kernel-parameters.txt | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.rst b/Documentation/admin-guide/kernel-parameters.rst index b2598cc9834c..7242cbda15dd 100644 --- a/Documentation/admin-guide/kernel-parameters.rst +++ b/Documentation/admin-guide/kernel-parameters.rst @@ -109,6 +109,7 @@ parameter is applicable:: IPV6 IPv6 support is enabled. ISAPNP ISA PnP code is enabled. ISDN Appropriate ISDN support is enabled. + ISOL CPU Isolation is enabled. JOY Appropriate joystick support is enabled. KGDB Kernel debugger support is enabled. KVM Kernel Virtual Machine support is enabled. diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 6571fbfdb2a1..168310707ec2 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1737,7 +1737,7 @@ isapnp= [ISAPNP] Format: ,,, - isolcpus= [KNL,SMP] Isolate a given set of CPUs from disturbance. + isolcpus= [KNL,SMP,ISOL] Isolate a given set of CPUs from disturbance. [Deprecated - use cpusets instead] Format: [flag-list,] @@ -2662,7 +2662,7 @@ Valid arguments: on, off Default: on - nohz_full= [KNL,BOOT] + nohz_full= [KNL,BOOT,SMP,ISOL] The argument is a cpu list, as described above. In kernels built with CONFIG_NO_HZ_FULL=y, set the specified list of CPUs whose tick will be stopped -- GitLab From a0cf579080a89a47a5441a4ba79f970009171e76 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 18 Dec 2017 12:39:14 +0000 Subject: [PATCH 1706/2547] drm/i915: Show IPEIR and IPEHR in the engine dump A useful bit of information for inspecting GPU stalls from intel_engine_dump() are the error registers, IPEIR and IPEHR. v2: Fixup gen changes in register offsets (Tvrtko) v3: Old FADDR location as well v4: Use I915_READ64_2x32 Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20171218123914.19027-1-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_engine_cs.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 510e0bc3a377..b4807497e92d 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1757,6 +1757,24 @@ void intel_engine_dump(struct intel_engine_cs *engine, addr = intel_engine_get_last_batch_head(engine); drm_printf(m, "\tBBADDR: 0x%08x_%08x\n", upper_32_bits(addr), lower_32_bits(addr)); + if (INTEL_GEN(dev_priv) >= 8) + addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base), + RING_DMA_FADD_UDW(engine->mmio_base)); + else if (INTEL_GEN(dev_priv) >= 4) + addr = I915_READ(RING_DMA_FADD(engine->mmio_base)); + else + addr = I915_READ(DMA_FADD_I8XX); + drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n", + upper_32_bits(addr), lower_32_bits(addr)); + if (INTEL_GEN(dev_priv) >= 4) { + drm_printf(m, "\tIPEIR: 0x%08x\n", + I915_READ(RING_IPEIR(engine->mmio_base))); + drm_printf(m, "\tIPEHR: 0x%08x\n", + I915_READ(RING_IPEHR(engine->mmio_base))); + } else { + drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR)); + drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR)); + } if (HAS_EXECLISTS(dev_priv)) { const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX]; -- GitLab From 869b5567e12f63ea7407f81728ca87f8c0abbfdb Mon Sep 17 00:00:00 2001 From: Dexuan Cui Date: Tue, 14 Nov 2017 06:53:32 -0700 Subject: [PATCH 1707/2547] vmbus: unregister device_obj->channels_kset Without the patch, a device can't be thoroughly destroyed, because vmbus_device_register() -> kset_create_and_add() still holds a reference to the hv_device's device.kobj. Signed-off-by: Dexuan Cui Cc: Stephen Hemminger Fixes: c2e5df616e1a ("vmbus: add per-channel sysfs info") Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- drivers/hv/vmbus_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c index 76ed9a216f10..610223f0e945 100644 --- a/drivers/hv/vmbus_drv.c +++ b/drivers/hv/vmbus_drv.c @@ -1378,6 +1378,8 @@ void vmbus_device_unregister(struct hv_device *device_obj) pr_debug("child device %s unregistered\n", dev_name(&device_obj->device)); + kset_unregister(device_obj->channels_kset); + /* * Kick off the process of unregistering the device. * This will call vmbus_remove() and eventually vmbus_device_release() -- GitLab From 7f3dc0088b98533f17128058fac73cd8b2752ef1 Mon Sep 17 00:00:00 2001 From: Todd Kjos Date: Mon, 27 Nov 2017 09:32:33 -0800 Subject: [PATCH 1708/2547] binder: fix proc->files use-after-free proc->files cleanup is initiated by binder_vma_close. Therefore a reference on the binder_proc is not enough to prevent the files_struct from being released while the binder_proc still has a reference. This can lead to an attempt to dereference the stale pointer obtained from proc->files prior to proc->files cleanup. This has been seen once in task_get_unused_fd_flags() when __alloc_fd() is called with a stale "files". The fix is to protect proc->files with a mutex to prevent cleanup while in use. Signed-off-by: Todd Kjos Cc: stable # 4.14 Signed-off-by: Greg Kroah-Hartman --- drivers/android/binder.c | 44 ++++++++++++++++++++++++++++------------ 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/drivers/android/binder.c b/drivers/android/binder.c index bccec9de0533..a7ecfde66b7b 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -482,7 +482,8 @@ enum binder_deferred_state { * @tsk task_struct for group_leader of process * (invariant after initialized) * @files files_struct for process - * (invariant after initialized) + * (protected by @files_lock) + * @files_lock mutex to protect @files * @deferred_work_node: element for binder_deferred_list * (protected by binder_deferred_lock) * @deferred_work: bitmap of deferred work to perform @@ -530,6 +531,7 @@ struct binder_proc { int pid; struct task_struct *tsk; struct files_struct *files; + struct mutex files_lock; struct hlist_node deferred_work_node; int deferred_work; bool is_dead; @@ -877,20 +879,26 @@ static void binder_inc_node_tmpref_ilocked(struct binder_node *node); static int task_get_unused_fd_flags(struct binder_proc *proc, int flags) { - struct files_struct *files = proc->files; unsigned long rlim_cur; unsigned long irqs; + int ret; - if (files == NULL) - return -ESRCH; - - if (!lock_task_sighand(proc->tsk, &irqs)) - return -EMFILE; - + mutex_lock(&proc->files_lock); + if (proc->files == NULL) { + ret = -ESRCH; + goto err; + } + if (!lock_task_sighand(proc->tsk, &irqs)) { + ret = -EMFILE; + goto err; + } rlim_cur = task_rlimit(proc->tsk, RLIMIT_NOFILE); unlock_task_sighand(proc->tsk, &irqs); - return __alloc_fd(files, 0, rlim_cur, flags); + ret = __alloc_fd(proc->files, 0, rlim_cur, flags); +err: + mutex_unlock(&proc->files_lock); + return ret; } /* @@ -899,8 +907,10 @@ static int task_get_unused_fd_flags(struct binder_proc *proc, int flags) static void task_fd_install( struct binder_proc *proc, unsigned int fd, struct file *file) { + mutex_lock(&proc->files_lock); if (proc->files) __fd_install(proc->files, fd, file); + mutex_unlock(&proc->files_lock); } /* @@ -910,9 +920,11 @@ static long task_close_fd(struct binder_proc *proc, unsigned int fd) { int retval; - if (proc->files == NULL) - return -ESRCH; - + mutex_lock(&proc->files_lock); + if (proc->files == NULL) { + retval = -ESRCH; + goto err; + } retval = __close_fd(proc->files, fd); /* can't restart close syscall because file table entry was cleared */ if (unlikely(retval == -ERESTARTSYS || @@ -920,7 +932,8 @@ static long task_close_fd(struct binder_proc *proc, unsigned int fd) retval == -ERESTARTNOHAND || retval == -ERESTART_RESTARTBLOCK)) retval = -EINTR; - +err: + mutex_unlock(&proc->files_lock); return retval; } @@ -4627,7 +4640,9 @@ static int binder_mmap(struct file *filp, struct vm_area_struct *vma) ret = binder_alloc_mmap_handler(&proc->alloc, vma); if (ret) return ret; + mutex_lock(&proc->files_lock); proc->files = get_files_struct(current); + mutex_unlock(&proc->files_lock); return 0; err_bad_arg: @@ -4651,6 +4666,7 @@ static int binder_open(struct inode *nodp, struct file *filp) spin_lock_init(&proc->outer_lock); get_task_struct(current->group_leader); proc->tsk = current->group_leader; + mutex_init(&proc->files_lock); INIT_LIST_HEAD(&proc->todo); proc->default_priority = task_nice(current); binder_dev = container_of(filp->private_data, struct binder_device, @@ -4903,9 +4919,11 @@ static void binder_deferred_func(struct work_struct *work) files = NULL; if (defer & BINDER_DEFERRED_PUT_FILES) { + mutex_lock(&proc->files_lock); files = proc->files; if (files) proc->files = NULL; + mutex_unlock(&proc->files_lock); } if (defer & BINDER_DEFERRED_FLUSH) -- GitLab From 5cfee7a357f60675cae32b494bb2096d7203efd3 Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Wed, 8 Nov 2017 11:27:37 +0100 Subject: [PATCH 1709/2547] perf tools: Use shell function for perl cflags retrieval Using the shell function for perl CFLAGS retrieval instead of back quotes (``). Both execute shell with the command, but the latter is more explicit and seems to be the preferred way. Also we don't have any other use of the back quotes in perf Makefiles. Signed-off-by: Jiri Olsa Cc: David Ahern Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/20171108102739.30338-2-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index ed65e82f034e..710623ddb8af 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -583,7 +583,7 @@ else PERL_EMBED_LDOPTS = $(shell perl -MExtUtils::Embed -e ldopts 2>/dev/null) PERL_EMBED_LDFLAGS = $(call strip-libs,$(PERL_EMBED_LDOPTS)) PERL_EMBED_LIBADD = $(call grep-libs,$(PERL_EMBED_LDOPTS)) - PERL_EMBED_CCOPTS = `perl -MExtUtils::Embed -e ccopts 2>/dev/null` + PERL_EMBED_CCOPTS = $(shell perl -MExtUtils::Embed -e ccopts 2>/dev/null) FLAGS_PERL_EMBED=$(PERL_EMBED_CCOPTS) $(PERL_EMBED_LDOPTS) ifneq ($(feature-libperl), 1) -- GitLab From 61fb26a6a23c0f1a07a0f8a11b54bafb1ac2398b Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Mon, 4 Dec 2017 12:23:08 -0300 Subject: [PATCH 1710/2547] perf tools: Fix up build in hardened environments On Fedora systems the perl and python CFLAGS/LDFLAGS include the hardened specs from redhat-rpm-config package. We apply them only for perl/python objects, which makes them not compatible with the rest of the objects and the build fails with: /usr/bin/ld: perf-in.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -f +PIC /usr/bin/ld: libperf.a(libperf-in.o): relocation R_X86_64_32S against `.text' can not be used when making a shared object; recompile w +ith -fPIC /usr/bin/ld: final link failed: Nonrepresentable section on output collect2: error: ld returned 1 exit status make[2]: *** [Makefile.perf:507: perf] Error 1 make[1]: *** [Makefile.perf:210: sub-make] Error 2 make: *** [Makefile:69: all] Error 2 Mainly it's caused by perl/python objects being compiled with: -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 which prevent the final link impossible, because it will check for 'proper' objects with following option: -specs=/usr/lib/rpm/redhat/redhat-hardened-ld Signed-off-by: Jiri Olsa Cc: David Ahern Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lkml.kernel.org/r/20171204082437.GC30564@krava Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 710623ddb8af..0294bfb6c5f8 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -188,9 +188,7 @@ ifdef PYTHON_CONFIG PYTHON_EMBED_LDFLAGS := $(call strip-libs,$(PYTHON_EMBED_LDOPTS)) PYTHON_EMBED_LIBADD := $(call grep-libs,$(PYTHON_EMBED_LDOPTS)) -lutil PYTHON_EMBED_CCOPTS := $(shell $(PYTHON_CONFIG_SQ) --cflags 2>/dev/null) - ifeq ($(CC_NO_CLANG), 1) - PYTHON_EMBED_CCOPTS := $(filter-out -specs=%,$(PYTHON_EMBED_CCOPTS)) - endif + PYTHON_EMBED_CCOPTS := $(filter-out -specs=%,$(PYTHON_EMBED_CCOPTS)) FLAGS_PYTHON_EMBED := $(PYTHON_EMBED_CCOPTS) $(PYTHON_EMBED_LDOPTS) endif @@ -576,7 +574,6 @@ ifndef NO_GTK2 endif endif - ifdef NO_LIBPERL CFLAGS += -DNO_LIBPERL else @@ -584,6 +581,8 @@ else PERL_EMBED_LDFLAGS = $(call strip-libs,$(PERL_EMBED_LDOPTS)) PERL_EMBED_LIBADD = $(call grep-libs,$(PERL_EMBED_LDOPTS)) PERL_EMBED_CCOPTS = $(shell perl -MExtUtils::Embed -e ccopts 2>/dev/null) + PERL_EMBED_CCOPTS := $(filter-out -specs=%,$(PERL_EMBED_CCOPTS)) + PERL_EMBED_LDOPTS := $(filter-out -specs=%,$(PERL_EMBED_LDOPTS)) FLAGS_PERL_EMBED=$(PERL_EMBED_CCOPTS) $(PERL_EMBED_LDOPTS) ifneq ($(feature-libperl), 1) -- GitLab From ca58d7e64bdfc54f7dfe46713c1e2acc68d7522d Mon Sep 17 00:00:00 2001 From: Ben Gainey Date: Wed, 22 Nov 2017 18:25:41 -0600 Subject: [PATCH 1711/2547] perf jvmti: Generate correct debug information for inlined code tools/perf/jvmti is broken in so far as it generates incorrect debug information. Specifically it attributes all debug lines to the original method being output even in the case that some code is being inlined from elsewhere. This patch fixes the issue. To test (from within linux/tools/perf): export JDIR=/usr/lib/jvm/java-8-openjdk-amd64/ make cat << __EOF > Test.java public class Test { private StringBuilder b = new StringBuilder(); private void loop(int i, String... args) { for (String a : args) b.append(a); long hc = b.hashCode() * System.nanoTime(); b = new StringBuilder(); b.append(hc); System.out.printf("Iteration %d = %d\n", i, hc); } public void run(String... args) { for (int i = 0; i < 10000; ++i) { loop(i, args); } } public static void main(String... args) { Test t = new Test(); t.run(args); } } __EOF $JDIR/bin/javac Test.java ./perf record -F 10000 -g -k mono $JDIR/bin/java -agentpath:`pwd`/libperf-jvmti.so Test ./perf inject --jit -i perf.data -o perf.data.jitted ./perf annotate -i perf.data.jitted --stdio | grep Test\.java: | sort -u Before this patch, Test.java line numbers get reported that are greater than the number of lines in the Test.java file. They come from the source file of the inlined function, e.g. java/lang/String.java:1085. For further validation one can examine those lines in the JDK source distribution and confirm that they map to inlined functions called by Test.java. After this patch, the filename of the inlined function is output rather than the incorrect original source filename. Signed-off-by: Ben Gainey Tested-by: Arnaldo Carvalho de Melo Tested-by: Stephane Eranian Cc: Alexander Shishkin Cc: Ben Gainey Cc: Colin King Cc: Darren Hart Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Thomas Gleixner Fixes: 598b7c6919c7 ("perf jit: add source line info support") Link: http://lkml.kernel.org/r/20171122182541.d25599a3eb1ada3480d142fa@arm.com Signed-off-by: Kim Phillips Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/jvmti/jvmti_agent.c | 16 ++-- tools/perf/jvmti/jvmti_agent.h | 7 +- tools/perf/jvmti/libjvmti.c | 147 +++++++++++++++++++++++++++------ 3 files changed, 134 insertions(+), 36 deletions(-) diff --git a/tools/perf/jvmti/jvmti_agent.c b/tools/perf/jvmti/jvmti_agent.c index cf36de7ea255..0c6d1002b524 100644 --- a/tools/perf/jvmti/jvmti_agent.c +++ b/tools/perf/jvmti/jvmti_agent.c @@ -384,13 +384,13 @@ jvmti_write_code(void *agent, char const *sym, } int -jvmti_write_debug_info(void *agent, uint64_t code, const char *file, - jvmti_line_info_t *li, int nr_lines) +jvmti_write_debug_info(void *agent, uint64_t code, + int nr_lines, jvmti_line_info_t *li, + const char * const * file_names) { struct jr_code_debug_info rec; - size_t sret, len, size, flen; + size_t sret, len, size, flen = 0; uint64_t addr; - const char *fn = file; FILE *fp = agent; int i; @@ -405,7 +405,9 @@ jvmti_write_debug_info(void *agent, uint64_t code, const char *file, return -1; } - flen = strlen(file) + 1; + for (i = 0; i < nr_lines; ++i) { + flen += strlen(file_names[i]) + 1; + } rec.p.id = JIT_CODE_DEBUG_INFO; size = sizeof(rec); @@ -421,7 +423,7 @@ jvmti_write_debug_info(void *agent, uint64_t code, const char *file, * file[] : source file name */ size += nr_lines * sizeof(struct debug_entry); - size += flen * nr_lines; + size += flen; rec.p.total_size = size; /* @@ -452,7 +454,7 @@ jvmti_write_debug_info(void *agent, uint64_t code, const char *file, if (sret != 1) goto error; - sret = fwrite_unlocked(fn, flen, 1, fp); + sret = fwrite_unlocked(file_names[i], strlen(file_names[i]) + 1, 1, fp); if (sret != 1) goto error; } diff --git a/tools/perf/jvmti/jvmti_agent.h b/tools/perf/jvmti/jvmti_agent.h index fe32d8344a82..6ed82f6c06dd 100644 --- a/tools/perf/jvmti/jvmti_agent.h +++ b/tools/perf/jvmti/jvmti_agent.h @@ -14,6 +14,7 @@ typedef struct { unsigned long pc; int line_number; int discrim; /* discriminator -- 0 for now */ + jmethodID methodID; } jvmti_line_info_t; void *jvmti_open(void); @@ -22,11 +23,9 @@ int jvmti_write_code(void *agent, char const *symbol_name, uint64_t vma, void const *code, const unsigned int code_size); -int jvmti_write_debug_info(void *agent, - uint64_t code, - const char *file, +int jvmti_write_debug_info(void *agent, uint64_t code, int nr_lines, jvmti_line_info_t *li, - int nr_lines); + const char * const * file_names); #if defined(__cplusplus) } diff --git a/tools/perf/jvmti/libjvmti.c b/tools/perf/jvmti/libjvmti.c index c62c9fc9a525..6add3e982614 100644 --- a/tools/perf/jvmti/libjvmti.c +++ b/tools/perf/jvmti/libjvmti.c @@ -47,6 +47,7 @@ do_get_line_numbers(jvmtiEnv *jvmti, void *pc, jmethodID m, jint bci, tab[lines].pc = (unsigned long)pc; tab[lines].line_number = loc_tab[i].line_number; tab[lines].discrim = 0; /* not yet used */ + tab[lines].methodID = m; lines++; } else { break; @@ -125,6 +126,99 @@ get_line_numbers(jvmtiEnv *jvmti, const void *compile_info, jvmti_line_info_t ** return JVMTI_ERROR_NONE; } +static void +copy_class_filename(const char * class_sign, const char * file_name, char * result, size_t max_length) +{ + /* + * Assume path name is class hierarchy, this is a common practice with Java programs + */ + if (*class_sign == 'L') { + int j, i = 0; + char *p = strrchr(class_sign, '/'); + if (p) { + /* drop the 'L' prefix and copy up to the final '/' */ + for (i = 0; i < (p - class_sign); i++) + result[i] = class_sign[i+1]; + } + /* + * append file name, we use loops and not string ops to avoid modifying + * class_sign which is used later for the symbol name + */ + for (j = 0; i < (max_length - 1) && file_name && j < strlen(file_name); j++, i++) + result[i] = file_name[j]; + + result[i] = '\0'; + } else { + /* fallback case */ + size_t file_name_len = strlen(file_name); + strncpy(result, file_name, file_name_len < max_length ? file_name_len : max_length); + } +} + +static jvmtiError +get_source_filename(jvmtiEnv *jvmti, jmethodID methodID, char ** buffer) +{ + jvmtiError ret; + jclass decl_class; + char *file_name = NULL; + char *class_sign = NULL; + char fn[PATH_MAX]; + size_t len; + + ret = (*jvmti)->GetMethodDeclaringClass(jvmti, methodID, &decl_class); + if (ret != JVMTI_ERROR_NONE) { + print_error(jvmti, "GetMethodDeclaringClass", ret); + return ret; + } + + ret = (*jvmti)->GetSourceFileName(jvmti, decl_class, &file_name); + if (ret != JVMTI_ERROR_NONE) { + print_error(jvmti, "GetSourceFileName", ret); + return ret; + } + + ret = (*jvmti)->GetClassSignature(jvmti, decl_class, &class_sign, NULL); + if (ret != JVMTI_ERROR_NONE) { + print_error(jvmti, "GetClassSignature", ret); + goto free_file_name_error; + } + + copy_class_filename(class_sign, file_name, fn, PATH_MAX); + len = strlen(fn); + *buffer = malloc((len + 1) * sizeof(char)); + if (!*buffer) { + print_error(jvmti, "GetClassSignature", ret); + ret = JVMTI_ERROR_OUT_OF_MEMORY; + goto free_class_sign_error; + } + strcpy(*buffer, fn); + ret = JVMTI_ERROR_NONE; + +free_class_sign_error: + (*jvmti)->Deallocate(jvmti, (unsigned char *)class_sign); +free_file_name_error: + (*jvmti)->Deallocate(jvmti, (unsigned char *)file_name); + + return ret; +} + +static jvmtiError +fill_source_filenames(jvmtiEnv *jvmti, int nr_lines, + const jvmti_line_info_t * line_tab, + char ** file_names) +{ + int index; + jvmtiError ret; + + for (index = 0; index < nr_lines; ++index) { + ret = get_source_filename(jvmti, line_tab[index].methodID, &(file_names[index])); + if (ret != JVMTI_ERROR_NONE) + return ret; + } + + return JVMTI_ERROR_NONE; +} + static void JNICALL compiled_method_load_cb(jvmtiEnv *jvmti, jmethodID method, @@ -135,16 +229,18 @@ compiled_method_load_cb(jvmtiEnv *jvmti, const void *compile_info) { jvmti_line_info_t *line_tab = NULL; + char ** line_file_names = NULL; jclass decl_class; char *class_sign = NULL; char *func_name = NULL; char *func_sign = NULL; - char *file_name= NULL; + char *file_name = NULL; char fn[PATH_MAX]; uint64_t addr = (uint64_t)(uintptr_t)code_addr; jvmtiError ret; int nr_lines = 0; /* in line_tab[] */ size_t len; + int output_debug_info = 0; ret = (*jvmti)->GetMethodDeclaringClass(jvmti, method, &decl_class); @@ -158,6 +254,19 @@ compiled_method_load_cb(jvmtiEnv *jvmti, if (ret != JVMTI_ERROR_NONE) { warnx("jvmti: cannot get line table for method"); nr_lines = 0; + } else if (nr_lines > 0) { + line_file_names = malloc(sizeof(char*) * nr_lines); + if (!line_file_names) { + warnx("jvmti: cannot allocate space for line table method names"); + } else { + memset(line_file_names, 0, sizeof(char*) * nr_lines); + ret = fill_source_filenames(jvmti, nr_lines, line_tab, line_file_names); + if (ret != JVMTI_ERROR_NONE) { + warnx("jvmti: fill_source_filenames failed"); + } else { + output_debug_info = 1; + } + } } } @@ -181,33 +290,14 @@ compiled_method_load_cb(jvmtiEnv *jvmti, goto error; } - /* - * Assume path name is class hierarchy, this is a common practice with Java programs - */ - if (*class_sign == 'L') { - int j, i = 0; - char *p = strrchr(class_sign, '/'); - if (p) { - /* drop the 'L' prefix and copy up to the final '/' */ - for (i = 0; i < (p - class_sign); i++) - fn[i] = class_sign[i+1]; - } - /* - * append file name, we use loops and not string ops to avoid modifying - * class_sign which is used later for the symbol name - */ - for (j = 0; i < (PATH_MAX - 1) && file_name && j < strlen(file_name); j++, i++) - fn[i] = file_name[j]; - fn[i] = '\0'; - } else { - /* fallback case */ - strcpy(fn, file_name); - } + copy_class_filename(class_sign, file_name, fn, PATH_MAX); + /* * write source line info record if we have it */ - if (jvmti_write_debug_info(jvmti_agent, addr, fn, line_tab, nr_lines)) - warnx("jvmti: write_debug_info() failed"); + if (output_debug_info) + if (jvmti_write_debug_info(jvmti_agent, addr, nr_lines, line_tab, (const char * const *) line_file_names)) + warnx("jvmti: write_debug_info() failed"); len = strlen(func_name) + strlen(class_sign) + strlen(func_sign) + 2; { @@ -223,6 +313,13 @@ compiled_method_load_cb(jvmtiEnv *jvmti, (*jvmti)->Deallocate(jvmti, (unsigned char *)class_sign); (*jvmti)->Deallocate(jvmti, (unsigned char *)file_name); free(line_tab); + while (line_file_names && (nr_lines > 0)) { + if (line_file_names[nr_lines - 1]) { + free(line_file_names[nr_lines - 1]); + } + nr_lines -= 1; + } + free(line_file_names); } static void JNICALL -- GitLab From 10b9baa701d5023897f70a4acb3bf0235da3dc4f Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 28 Nov 2017 11:08:41 -0300 Subject: [PATCH 1712/2547] tools arch s390: Do not include header files from the kernel sources Long ago we decided to be verbotten including files in the kernel git sources from tools/ living source code, to avoid disturbing kernel development (and perf's and other tools/) when, say, a kernel hacker adds something, tests everything but tools/ and have tools/ build broken. This got broken recently by s/390, fix it by copying arch/s390/include/uapi/asm/perf_regs.h to tools/arch/s390/include/uapi/asm/, making this one be used by means of and updating tools/perf/check_headers.sh to make sure we are notified when the original changes, so that we can check if anything is needed on the tooling side. This would have been caught by the 'tarkpg' test entry in: $ make -C tools/perf build-test When run on a s/390 build system or container. Acked-by: Heiko Carstens Cc: Hendrik Brueckner Cc: Thomas Richter Cc: Martin Schwidefsky Cc: Adrian Hunter Cc: David Ahern Cc: Jiri Olsa Cc: Namhyung Kim Cc: Wang Nan Fixes: f704ef44602f ("s390/perf: add support for perf_regs and libdw") Link: https://lkml.kernel.org/n/tip-n57139ic0v9uffx8wdqi3d8a@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/arch/s390/include/uapi/asm/perf_regs.h | 44 ++++++++++++++++++++ tools/perf/arch/s390/include/perf_regs.h | 2 +- tools/perf/check-headers.sh | 1 + 3 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 tools/arch/s390/include/uapi/asm/perf_regs.h diff --git a/tools/arch/s390/include/uapi/asm/perf_regs.h b/tools/arch/s390/include/uapi/asm/perf_regs.h new file mode 100644 index 000000000000..d17dd9e5d516 --- /dev/null +++ b/tools/arch/s390/include/uapi/asm/perf_regs.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _ASM_S390_PERF_REGS_H +#define _ASM_S390_PERF_REGS_H + +enum perf_event_s390_regs { + PERF_REG_S390_R0, + PERF_REG_S390_R1, + PERF_REG_S390_R2, + PERF_REG_S390_R3, + PERF_REG_S390_R4, + PERF_REG_S390_R5, + PERF_REG_S390_R6, + PERF_REG_S390_R7, + PERF_REG_S390_R8, + PERF_REG_S390_R9, + PERF_REG_S390_R10, + PERF_REG_S390_R11, + PERF_REG_S390_R12, + PERF_REG_S390_R13, + PERF_REG_S390_R14, + PERF_REG_S390_R15, + PERF_REG_S390_FP0, + PERF_REG_S390_FP1, + PERF_REG_S390_FP2, + PERF_REG_S390_FP3, + PERF_REG_S390_FP4, + PERF_REG_S390_FP5, + PERF_REG_S390_FP6, + PERF_REG_S390_FP7, + PERF_REG_S390_FP8, + PERF_REG_S390_FP9, + PERF_REG_S390_FP10, + PERF_REG_S390_FP11, + PERF_REG_S390_FP12, + PERF_REG_S390_FP13, + PERF_REG_S390_FP14, + PERF_REG_S390_FP15, + PERF_REG_S390_MASK, + PERF_REG_S390_PC, + + PERF_REG_S390_MAX +}; + +#endif /* _ASM_S390_PERF_REGS_H */ diff --git a/tools/perf/arch/s390/include/perf_regs.h b/tools/perf/arch/s390/include/perf_regs.h index d2df54a6bc5a..bcfbaed78cc2 100644 --- a/tools/perf/arch/s390/include/perf_regs.h +++ b/tools/perf/arch/s390/include/perf_regs.h @@ -3,7 +3,7 @@ #include #include -#include <../../../../arch/s390/include/uapi/asm/perf_regs.h> +#include void perf_regs_load(u64 *regs); diff --git a/tools/perf/check-headers.sh b/tools/perf/check-headers.sh index 6db9d809fe97..3e64f10b6d66 100755 --- a/tools/perf/check-headers.sh +++ b/tools/perf/check-headers.sh @@ -21,6 +21,7 @@ arch/x86/include/asm/cpufeatures.h arch/arm/include/uapi/asm/perf_regs.h arch/arm64/include/uapi/asm/perf_regs.h arch/powerpc/include/uapi/asm/perf_regs.h +arch/s390/include/uapi/asm/perf_regs.h arch/x86/include/uapi/asm/perf_regs.h arch/x86/include/uapi/asm/kvm.h arch/x86/include/uapi/asm/kvm_perf.h -- GitLab From ca26cffa4e4aaeb09bb9e308f95c7835cb149248 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 4 Dec 2017 13:08:47 -0300 Subject: [PATCH 1713/2547] x86/asm: Allow again using asm.h when building for the 'bpf' clang target Up to f5caf621ee35 ("x86/asm: Fix inline asm call constraints for Clang") we were able to use x86 headers to build to the 'bpf' clang target, as done by the BPF code in tools/perf/. With that commit, we ended up with following failure for 'perf test LLVM', this is because "clang ... -target bpf ..." fails since 4.0 does not have bpf inline asm support and 6.0 does not recognize the register 'esp', fix it by guarding that part with an #ifndef __BPF__, that is defined by clang when building to the "bpf" target. # perf test -v LLVM 37: LLVM search and compile : 37.1: Basic BPF llvm compile : --- start --- test child forked, pid 25526 Kernel build dir is set to /lib/modules/4.14.0+/build set env: KBUILD_DIR=/lib/modules/4.14.0+/build unset env: KBUILD_OPTS include option is set to -nostdinc -isystem /usr/lib/gcc/x86_64-redhat-linux/7/include -I/home/acme/git/linux/arch/x86/include -I./arch/x86/include/generated -I/home/acme/git/linux/include -I./include -I/home/acme/git/linux/arch/x86/include/uapi -I./arch/x86/include/generated/uapi -I/home/acme/git/linux/include/uapi -I./include/generated/uapi -include /home/acme/git/linux/include/linux/kconfig.h set env: NR_CPUS=4 set env: LINUX_VERSION_CODE=0x40e00 set env: CLANG_EXEC=/usr/local/bin/clang set env: CLANG_OPTIONS=-xc set env: KERNEL_INC_OPTIONS= -nostdinc -isystem /usr/lib/gcc/x86_64-redhat-linux/7/include -I/home/acme/git/linux/arch/x86/include -I./arch/x86/include/generated -I/home/acme/git/linux/include -I./include -I/home/acme/git/linux/arch/x86/include/uapi -I./arch/x86/include/generated/uapi -I/home/acme/git/linux/include/uapi -I./include/generated/uapi -include /home/acme/git/linux/include/linux/kconfig.h set env: WORKING_DIR=/lib/modules/4.14.0+/build set env: CLANG_SOURCE=- llvm compiling command template: echo '/* * bpf-script-example.c * Test basic LLVM building */ #ifndef LINUX_VERSION_CODE # error Need LINUX_VERSION_CODE # error Example: for 4.2 kernel, put 'clang-opt="-DLINUX_VERSION_CODE=0x40200" into llvm section of ~/.perfconfig' #endif #define BPF_ANY 0 #define BPF_MAP_TYPE_ARRAY 2 #define BPF_FUNC_map_lookup_elem 1 #define BPF_FUNC_map_update_elem 2 static void *(*bpf_map_lookup_elem)(void *map, void *key) = (void *) BPF_FUNC_map_lookup_elem; static void *(*bpf_map_update_elem)(void *map, void *key, void *value, int flags) = (void *) BPF_FUNC_map_update_elem; struct bpf_map_def { unsigned int type; unsigned int key_size; unsigned int value_size; unsigned int max_entries; }; #define SEC(NAME) __attribute__((section(NAME), used)) struct bpf_map_def SEC("maps") flip_table = { .type = BPF_MAP_TYPE_ARRAY, .key_size = sizeof(int), .value_size = sizeof(int), .max_entries = 1, }; SEC("func=SyS_epoll_wait") int bpf_func__SyS_epoll_wait(void *ctx) { int ind =0; int *flag = bpf_map_lookup_elem(&flip_table, &ind); int new_flag; if (!flag) return 0; /* flip flag and store back */ new_flag = !*flag; bpf_map_update_elem(&flip_table, &ind, &new_flag, BPF_ANY); return new_flag; } char _license[] SEC("license") = "GPL"; int _version SEC("version") = LINUX_VERSION_CODE; ' | $CLANG_EXEC -D__KERNEL__ -D__NR_CPUS__=$NR_CPUS -DLINUX_VERSION_CODE=$LINUX_VERSION_CODE $CLANG_OPTIONS $KERNEL_INC_OPTIONS -Wno-unused-value -Wno-pointer-sign -working-directory $WORKING_DIR -c "$CLANG_SOURCE" -target bpf -O2 -o - test child finished with 0 ---- end ---- LLVM search and compile subtest 0: Ok 37.2: kbuild searching : --- start --- test child forked, pid 25950 Kernel build dir is set to /lib/modules/4.14.0+/build set env: KBUILD_DIR=/lib/modules/4.14.0+/build unset env: KBUILD_OPTS include option is set to -nostdinc -isystem /usr/lib/gcc/x86_64-redhat-linux/7/include -I/home/acme/git/linux/arch/x86/include -I./arch/x86/include/generated -I/home/acme/git/linux/include -I./include -I/home/acme/git/linux/arch/x86/include/uapi -I./arch/x86/include/generated/uapi -I/home/acme/git/linux/include/uapi -I./include/generated/uapi -include /home/acme/git/linux/include/linux/kconfig.h set env: NR_CPUS=4 set env: LINUX_VERSION_CODE=0x40e00 set env: CLANG_EXEC=/usr/local/bin/clang set env: CLANG_OPTIONS=-xc set env: KERNEL_INC_OPTIONS= -nostdinc -isystem /usr/lib/gcc/x86_64-redhat-linux/7/include -I/home/acme/git/linux/arch/x86/include -I./arch/x86/include/generated -I/home/acme/git/linux/include -I./include -I/home/acme/git/linux/arch/x86/include/uapi -I./arch/x86/include/generated/uapi -I/home/acme/git/linux/include/uapi -I./include/generated/uapi -include /home/acme/git/linux/include/linux/kconfig.h set env: WORKING_DIR=/lib/modules/4.14.0+/build set env: CLANG_SOURCE=- llvm compiling command template: echo '/* * bpf-script-test-kbuild.c * Test include from kernel header */ #ifndef LINUX_VERSION_CODE # error Need LINUX_VERSION_CODE # error Example: for 4.2 kernel, put 'clang-opt="-DLINUX_VERSION_CODE=0x40200" into llvm section of ~/.perfconfig' #endif #define SEC(NAME) __attribute__((section(NAME), used)) #include #include SEC("func=vfs_llseek") int bpf_func__vfs_llseek(void *ctx) { return 0; } char _license[] SEC("license") = "GPL"; int _version SEC("version") = LINUX_VERSION_CODE; ' | $CLANG_EXEC -D__KERNEL__ -D__NR_CPUS__=$NR_CPUS -DLINUX_VERSION_CODE=$LINUX_VERSION_CODE $CLANG_OPTIONS $KERNEL_INC_OPTIONS -Wno-unused-value -Wno-pointer-sign -working-directory $WORKING_DIR -c "$CLANG_SOURCE" -target bpf -O2 -o - In file included from :12: In file included from /home/acme/git/linux/arch/x86/include/uapi/asm/ptrace.h:5: In file included from /home/acme/git/linux/include/linux/compiler.h:242: In file included from /home/acme/git/linux/arch/x86/include/asm/barrier.h:5: In file included from /home/acme/git/linux/arch/x86/include/asm/alternative.h:10: /home/acme/git/linux/arch/x86/include/asm/asm.h:145:50: error: unknown register name 'esp' in asm register unsigned long current_stack_pointer asm(_ASM_SP); ^ /home/acme/git/linux/arch/x86/include/asm/asm.h:44:18: note: expanded from macro '_ASM_SP' #define _ASM_SP __ASM_REG(sp) ^ /home/acme/git/linux/arch/x86/include/asm/asm.h:27:32: note: expanded from macro '__ASM_REG' #define __ASM_REG(reg) __ASM_SEL_RAW(e##reg, r##reg) ^ /home/acme/git/linux/arch/x86/include/asm/asm.h:18:29: note: expanded from macro '__ASM_SEL_RAW' # define __ASM_SEL_RAW(a,b) __ASM_FORM_RAW(a) ^ /home/acme/git/linux/arch/x86/include/asm/asm.h:11:32: note: expanded from macro '__ASM_FORM_RAW' # define __ASM_FORM_RAW(x) #x ^ :4:1: note: expanded from here "esp" ^ 1 error generated. ERROR: unable to compile - Hint: Check error message shown above. Hint: You can also pre-compile it into .o using: clang -target bpf -O2 -c - with proper -I and -D options. Failed to compile test case: 'kbuild searching' test child finished with -1 ---- end ---- LLVM search and compile subtest 1: FAILED! Cc: Adrian Hunter Cc: Alexander Potapenko Cc: Alexei Starovoitov Cc: Andrey Ryabinin Cc: Andy Lutomirski Cc: Arnd Bergmann Cc: Daniel Borkmann Cc: David Ahern Cc: Dmitriy Vyukov Cc: Jiri Olsa Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Matthias Kaehlcke Cc: Miguel Bernal Marin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Wang Nan Cc: Yonghong Song Link: https://lkml.kernel.org/r/20171128175948.GL3298@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- arch/x86/include/asm/asm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/include/asm/asm.h b/arch/x86/include/asm/asm.h index 219faaec51df..386a6900e206 100644 --- a/arch/x86/include/asm/asm.h +++ b/arch/x86/include/asm/asm.h @@ -136,6 +136,7 @@ #endif #ifndef __ASSEMBLY__ +#ifndef __BPF__ /* * This output constraint should be used for any inline asm which has a "call" * instruction. Otherwise the asm may be inserted before the frame pointer @@ -145,5 +146,6 @@ register unsigned long current_stack_pointer asm(_ASM_SP); #define ASM_CALL_CONSTRAINT "+r" (current_stack_pointer) #endif +#endif #endif /* _ASM_X86_ASM_H */ -- GitLab From 4e89df63c110d7fb4883c8b3d653d3d0e5dac67d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 14 Dec 2017 14:32:53 -0500 Subject: [PATCH 1714/2547] drm/amdgpu: move atom functions from amdgpu_device.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit and move them to amdgpu_atombios.c for consistency. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 236 ++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 231 ------------------ 3 files changed, 236 insertions(+), 235 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index ffaf0534e33c..bf872f694f50 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -27,6 +27,7 @@ #include #include "amdgpu.h" #include "amdgpu_atombios.h" +#include "amdgpu_atomfirmware.h" #include "amdgpu_i2c.h" #include "atom.h" @@ -1699,7 +1700,7 @@ void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock) WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch); } -void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev) +static void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev) { uint32_t bios_2_scratch, bios_6_scratch; @@ -1776,7 +1777,7 @@ void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) #endif } -int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev) +static int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev) { struct atom_context *ctx = adev->mode_info.atom_context; int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware); @@ -1819,3 +1820,234 @@ int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev) ctx->scratch_size_bytes = usage_bytes; return 0; } + +/* ATOM accessor methods */ +/* + * ATOM is an interpreted byte code stored in tables in the vbios. The + * driver registers callbacks to access registers and the interpreter + * in the driver parses the tables and executes then to program specific + * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, + * atombios.h, and atom.c + */ + +/** + * cail_pll_read - read PLL register + * + * @info: atom card_info pointer + * @reg: PLL register offset + * + * Provides a PLL register accessor for the atom interpreter (r4xx+). + * Returns the value of the PLL register. + */ +static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) +{ + return 0; +} + +/** + * cail_pll_write - write PLL register + * + * @info: atom card_info pointer + * @reg: PLL register offset + * @val: value to write to the pll register + * + * Provides a PLL register accessor for the atom interpreter (r4xx+). + */ +static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) +{ + +} + +/** + * cail_mc_read - read MC (Memory Controller) register + * + * @info: atom card_info pointer + * @reg: MC register offset + * + * Provides an MC register accessor for the atom interpreter (r4xx+). + * Returns the value of the MC register. + */ +static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) +{ + return 0; +} + +/** + * cail_mc_write - write MC (Memory Controller) register + * + * @info: atom card_info pointer + * @reg: MC register offset + * @val: value to write to the pll register + * + * Provides a MC register accessor for the atom interpreter (r4xx+). + */ +static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) +{ + +} + +/** + * cail_reg_write - write MMIO register + * + * @info: atom card_info pointer + * @reg: MMIO register offset + * @val: value to write to the pll register + * + * Provides a MMIO register accessor for the atom interpreter (r4xx+). + */ +static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) +{ + struct amdgpu_device *adev = info->dev->dev_private; + + WREG32(reg, val); +} + +/** + * cail_reg_read - read MMIO register + * + * @info: atom card_info pointer + * @reg: MMIO register offset + * + * Provides an MMIO register accessor for the atom interpreter (r4xx+). + * Returns the value of the MMIO register. + */ +static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) +{ + struct amdgpu_device *adev = info->dev->dev_private; + uint32_t r; + + r = RREG32(reg); + return r; +} + +/** + * cail_ioreg_write - write IO register + * + * @info: atom card_info pointer + * @reg: IO register offset + * @val: value to write to the pll register + * + * Provides a IO register accessor for the atom interpreter (r4xx+). + */ +static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) +{ + struct amdgpu_device *adev = info->dev->dev_private; + + WREG32_IO(reg, val); +} + +/** + * cail_ioreg_read - read IO register + * + * @info: atom card_info pointer + * @reg: IO register offset + * + * Provides an IO register accessor for the atom interpreter (r4xx+). + * Returns the value of the IO register. + */ +static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) +{ + struct amdgpu_device *adev = info->dev->dev_private; + uint32_t r; + + r = RREG32_IO(reg); + return r; +} + +static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = ddev->dev_private; + struct atom_context *ctx = adev->mode_info.atom_context; + + return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version); +} + +static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, + NULL); + +/** + * amdgpu_atombios_fini - free the driver info and callbacks for atombios + * + * @adev: amdgpu_device pointer + * + * Frees the driver info and register access callbacks for the ATOM + * interpreter (r4xx+). + * Called at driver shutdown. + */ +void amdgpu_atombios_fini(struct amdgpu_device *adev) +{ + if (adev->mode_info.atom_context) { + kfree(adev->mode_info.atom_context->scratch); + kfree(adev->mode_info.atom_context->iio); + } + kfree(adev->mode_info.atom_context); + adev->mode_info.atom_context = NULL; + kfree(adev->mode_info.atom_card_info); + adev->mode_info.atom_card_info = NULL; + device_remove_file(adev->dev, &dev_attr_vbios_version); +} + +/** + * amdgpu_atombios_init - init the driver info and callbacks for atombios + * + * @adev: amdgpu_device pointer + * + * Initializes the driver info and register access callbacks for the + * ATOM interpreter (r4xx+). + * Returns 0 on sucess, -ENOMEM on failure. + * Called at driver startup. + */ +int amdgpu_atombios_init(struct amdgpu_device *adev) +{ + struct card_info *atom_card_info = + kzalloc(sizeof(struct card_info), GFP_KERNEL); + int ret; + + if (!atom_card_info) + return -ENOMEM; + + adev->mode_info.atom_card_info = atom_card_info; + atom_card_info->dev = adev->ddev; + atom_card_info->reg_read = cail_reg_read; + atom_card_info->reg_write = cail_reg_write; + /* needed for iio ops */ + if (adev->rio_mem) { + atom_card_info->ioreg_read = cail_ioreg_read; + atom_card_info->ioreg_write = cail_ioreg_write; + } else { + DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); + atom_card_info->ioreg_read = cail_reg_read; + atom_card_info->ioreg_write = cail_reg_write; + } + atom_card_info->mc_read = cail_mc_read; + atom_card_info->mc_write = cail_mc_write; + atom_card_info->pll_read = cail_pll_read; + atom_card_info->pll_write = cail_pll_write; + + adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); + if (!adev->mode_info.atom_context) { + amdgpu_atombios_fini(adev); + return -ENOMEM; + } + + mutex_init(&adev->mode_info.atom_context->mutex); + if (adev->is_atom_fw) { + amdgpu_atomfirmware_scratch_regs_init(adev); + amdgpu_atomfirmware_allocate_fb_scratch(adev); + } else { + amdgpu_atombios_scratch_regs_init(adev); + amdgpu_atombios_allocate_fb_scratch(adev); + } + + ret = device_create_file(adev->dev, &dev_attr_vbios_version); + if (ret) { + DRM_ERROR("Failed to create device file for VBIOS version\n"); + return ret; + } + + return 0; +} + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h index 58507f9ff856..fd8f18074f7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h @@ -195,7 +195,6 @@ int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev); void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock); -void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev); void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev, bool hung); bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev); @@ -217,6 +216,7 @@ int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev, u8 voltage_type, u8 *svd_gpio_id, u8 *svc_gpio_id); -int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev); +void amdgpu_atombios_fini(struct amdgpu_device *adev); +int amdgpu_atombios_init(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 79869827985f..a3632c757ca4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -898,237 +898,6 @@ void amdgpu_dummy_page_fini(struct amdgpu_device *adev) adev->dummy_page.page = NULL; } - -/* ATOM accessor methods */ -/* - * ATOM is an interpreted byte code stored in tables in the vbios. The - * driver registers callbacks to access registers and the interpreter - * in the driver parses the tables and executes then to program specific - * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, - * atombios.h, and atom.c - */ - -/** - * cail_pll_read - read PLL register - * - * @info: atom card_info pointer - * @reg: PLL register offset - * - * Provides a PLL register accessor for the atom interpreter (r4xx+). - * Returns the value of the PLL register. - */ -static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) -{ - return 0; -} - -/** - * cail_pll_write - write PLL register - * - * @info: atom card_info pointer - * @reg: PLL register offset - * @val: value to write to the pll register - * - * Provides a PLL register accessor for the atom interpreter (r4xx+). - */ -static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) -{ - -} - -/** - * cail_mc_read - read MC (Memory Controller) register - * - * @info: atom card_info pointer - * @reg: MC register offset - * - * Provides an MC register accessor for the atom interpreter (r4xx+). - * Returns the value of the MC register. - */ -static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) -{ - return 0; -} - -/** - * cail_mc_write - write MC (Memory Controller) register - * - * @info: atom card_info pointer - * @reg: MC register offset - * @val: value to write to the pll register - * - * Provides a MC register accessor for the atom interpreter (r4xx+). - */ -static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) -{ - -} - -/** - * cail_reg_write - write MMIO register - * - * @info: atom card_info pointer - * @reg: MMIO register offset - * @val: value to write to the pll register - * - * Provides a MMIO register accessor for the atom interpreter (r4xx+). - */ -static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) -{ - struct amdgpu_device *adev = info->dev->dev_private; - - WREG32(reg, val); -} - -/** - * cail_reg_read - read MMIO register - * - * @info: atom card_info pointer - * @reg: MMIO register offset - * - * Provides an MMIO register accessor for the atom interpreter (r4xx+). - * Returns the value of the MMIO register. - */ -static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) -{ - struct amdgpu_device *adev = info->dev->dev_private; - uint32_t r; - - r = RREG32(reg); - return r; -} - -/** - * cail_ioreg_write - write IO register - * - * @info: atom card_info pointer - * @reg: IO register offset - * @val: value to write to the pll register - * - * Provides a IO register accessor for the atom interpreter (r4xx+). - */ -static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) -{ - struct amdgpu_device *adev = info->dev->dev_private; - - WREG32_IO(reg, val); -} - -/** - * cail_ioreg_read - read IO register - * - * @info: atom card_info pointer - * @reg: IO register offset - * - * Provides an IO register accessor for the atom interpreter (r4xx+). - * Returns the value of the IO register. - */ -static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) -{ - struct amdgpu_device *adev = info->dev->dev_private; - uint32_t r; - - r = RREG32_IO(reg); - return r; -} - -static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = ddev->dev_private; - struct atom_context *ctx = adev->mode_info.atom_context; - - return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version); -} - -static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, - NULL); - -/** - * amdgpu_atombios_fini - free the driver info and callbacks for atombios - * - * @adev: amdgpu_device pointer - * - * Frees the driver info and register access callbacks for the ATOM - * interpreter (r4xx+). - * Called at driver shutdown. - */ -static void amdgpu_atombios_fini(struct amdgpu_device *adev) -{ - if (adev->mode_info.atom_context) { - kfree(adev->mode_info.atom_context->scratch); - kfree(adev->mode_info.atom_context->iio); - } - kfree(adev->mode_info.atom_context); - adev->mode_info.atom_context = NULL; - kfree(adev->mode_info.atom_card_info); - adev->mode_info.atom_card_info = NULL; - device_remove_file(adev->dev, &dev_attr_vbios_version); -} - -/** - * amdgpu_atombios_init - init the driver info and callbacks for atombios - * - * @adev: amdgpu_device pointer - * - * Initializes the driver info and register access callbacks for the - * ATOM interpreter (r4xx+). - * Returns 0 on sucess, -ENOMEM on failure. - * Called at driver startup. - */ -static int amdgpu_atombios_init(struct amdgpu_device *adev) -{ - struct card_info *atom_card_info = - kzalloc(sizeof(struct card_info), GFP_KERNEL); - int ret; - - if (!atom_card_info) - return -ENOMEM; - - adev->mode_info.atom_card_info = atom_card_info; - atom_card_info->dev = adev->ddev; - atom_card_info->reg_read = cail_reg_read; - atom_card_info->reg_write = cail_reg_write; - /* needed for iio ops */ - if (adev->rio_mem) { - atom_card_info->ioreg_read = cail_ioreg_read; - atom_card_info->ioreg_write = cail_ioreg_write; - } else { - DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); - atom_card_info->ioreg_read = cail_reg_read; - atom_card_info->ioreg_write = cail_reg_write; - } - atom_card_info->mc_read = cail_mc_read; - atom_card_info->mc_write = cail_mc_write; - atom_card_info->pll_read = cail_pll_read; - atom_card_info->pll_write = cail_pll_write; - - adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); - if (!adev->mode_info.atom_context) { - amdgpu_atombios_fini(adev); - return -ENOMEM; - } - - mutex_init(&adev->mode_info.atom_context->mutex); - if (adev->is_atom_fw) { - amdgpu_atomfirmware_scratch_regs_init(adev); - amdgpu_atomfirmware_allocate_fb_scratch(adev); - } else { - amdgpu_atombios_scratch_regs_init(adev); - amdgpu_atombios_allocate_fb_scratch(adev); - } - - ret = device_create_file(adev->dev, &dev_attr_vbios_version); - if (ret) { - DRM_ERROR("Failed to create device file for VBIOS version\n"); - return ret; - } - - return 0; -} - /* if we get transitioned to only one device, take VGA back */ /** * amdgpu_vga_set_decode - enable/disable vga decode -- GitLab From 06ec907054c5a48f28ff6856885522e3a7103bb7 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 14 Dec 2017 15:02:39 -0500 Subject: [PATCH 1715/2547] drm/amdgpu: use consistent naming for static funcs in amdgpu_device.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Prefix the functions with device or device_ip for functions which deal with ip blocks for consistency. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 176 +++++++++++---------- 1 file changed, 90 insertions(+), 86 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a3632c757ca4..92b5064b3391 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -332,7 +332,7 @@ static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, BUG(); } -static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) +static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) { return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, @@ -341,7 +341,7 @@ static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) (void **)&adev->vram_scratch.ptr); } -static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) +static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) { amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); } @@ -391,14 +391,14 @@ void amdgpu_pci_config_reset(struct amdgpu_device *adev) * GPU doorbell aperture helpers function. */ /** - * amdgpu_doorbell_init - Init doorbell driver information. + * amdgpu_device_doorbell_init - Init doorbell driver information. * * @adev: amdgpu_device pointer * * Init doorbell driver information (CIK) * Returns 0 on success, error on failure. */ -static int amdgpu_doorbell_init(struct amdgpu_device *adev) +static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) { /* No doorbell on SI hardware generation */ if (adev->asic_type < CHIP_BONAIRE) { @@ -431,13 +431,13 @@ static int amdgpu_doorbell_init(struct amdgpu_device *adev) } /** - * amdgpu_doorbell_fini - Tear down doorbell driver information. + * amdgpu_device_doorbell_fini - Tear down doorbell driver information. * * @adev: amdgpu_device pointer * * Tear down doorbell driver information (CIK) */ -static void amdgpu_doorbell_fini(struct amdgpu_device *adev) +static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) { iounmap(adev->doorbell.ptr); adev->doorbell.ptr = NULL; @@ -477,20 +477,20 @@ void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, } /* - * amdgpu_wb_*() + * amdgpu_device_wb_*() * Writeback is the method by which the GPU updates special pages in memory * with the status of certain GPU events (fences, ring pointers,etc.). */ /** - * amdgpu_wb_fini - Disable Writeback and free memory + * amdgpu_device_wb_fini - Disable Writeback and free memory * * @adev: amdgpu_device pointer * * Disables Writeback and frees the Writeback memory (all asics). * Used at driver shutdown. */ -static void amdgpu_wb_fini(struct amdgpu_device *adev) +static void amdgpu_device_wb_fini(struct amdgpu_device *adev) { if (adev->wb.wb_obj) { amdgpu_bo_free_kernel(&adev->wb.wb_obj, @@ -501,7 +501,7 @@ static void amdgpu_wb_fini(struct amdgpu_device *adev) } /** - * amdgpu_wb_init- Init Writeback driver info and allocate memory + * amdgpu_device_wb_init- Init Writeback driver info and allocate memory * * @adev: amdgpu_device pointer * @@ -509,7 +509,7 @@ static void amdgpu_wb_fini(struct amdgpu_device *adev) * Used at driver startup. * Returns 0 on success or an -error on failure. */ -static int amdgpu_wb_init(struct amdgpu_device *adev) +static int amdgpu_device_wb_init(struct amdgpu_device *adev) { int r; @@ -770,7 +770,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) cmd & ~PCI_COMMAND_MEMORY); /* Free the VRAM and doorbell BAR, we most likely need to move both. */ - amdgpu_doorbell_fini(adev); + amdgpu_device_doorbell_fini(adev); if (adev->asic_type >= CHIP_BONAIRE) pci_release_resource(adev->pdev, 2); @@ -787,7 +787,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) /* When the doorbell or fb BAR isn't available we have no chance of * using the device. */ - r = amdgpu_doorbell_init(adev); + r = amdgpu_device_doorbell_init(adev); if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) return -ENODEV; @@ -900,7 +900,7 @@ void amdgpu_dummy_page_fini(struct amdgpu_device *adev) /* if we get transitioned to only one device, take VGA back */ /** - * amdgpu_vga_set_decode - enable/disable vga decode + * amdgpu_device_vga_set_decode - enable/disable vga decode * * @cookie: amdgpu_device pointer * @state: enable/disable vga decode @@ -908,7 +908,7 @@ void amdgpu_dummy_page_fini(struct amdgpu_device *adev) * Enable/disable vga decode (all asics). * Returns VGA resource flags. */ -static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) +static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) { struct amdgpu_device *adev = cookie; amdgpu_asic_set_vga_state(adev, state); @@ -919,7 +919,7 @@ static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; } -static void amdgpu_check_block_size(struct amdgpu_device *adev) +static void amdgpu_device_check_block_size(struct amdgpu_device *adev) { /* defines number of bits in page table versus page directory, * a page is 4KB so we have 12 bits offset, minimum 9 bits in the @@ -934,7 +934,7 @@ static void amdgpu_check_block_size(struct amdgpu_device *adev) } } -static void amdgpu_check_vm_size(struct amdgpu_device *adev) +static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) { /* no need to check the default value */ if (amdgpu_vm_size == -1) @@ -948,14 +948,14 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev) } /** - * amdgpu_check_arguments - validate module params + * amdgpu_device_check_arguments - validate module params * * @adev: amdgpu_device pointer * * Validates certain module parameters and updates * the associated values used by the driver (all asics). */ -static void amdgpu_check_arguments(struct amdgpu_device *adev) +static void amdgpu_device_check_arguments(struct amdgpu_device *adev) { if (amdgpu_sched_jobs < 4) { dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", @@ -988,9 +988,9 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) amdgpu_vm_fragment_size = -1; } - amdgpu_check_vm_size(adev); + amdgpu_device_check_vm_size(adev); - amdgpu_check_block_size(adev); + amdgpu_device_check_block_size(adev); if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || !is_power_of_2(amdgpu_vram_page_split))) { @@ -1359,7 +1359,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) return err; } -static int amdgpu_early_init(struct amdgpu_device *adev) +static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) { int i, r; @@ -1468,7 +1468,7 @@ static int amdgpu_early_init(struct amdgpu_device *adev) return 0; } -static int amdgpu_init(struct amdgpu_device *adev) +static int amdgpu_device_ip_init(struct amdgpu_device *adev) { int i, r; @@ -1484,7 +1484,7 @@ static int amdgpu_init(struct amdgpu_device *adev) adev->ip_blocks[i].status.sw = true; /* need to do gmc hw init early so we can allocate gpu mem */ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { - r = amdgpu_vram_scratch_init(adev); + r = amdgpu_device_vram_scratch_init(adev); if (r) { DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); return r; @@ -1494,9 +1494,9 @@ static int amdgpu_init(struct amdgpu_device *adev) DRM_ERROR("hw_init %d failed %d\n", i, r); return r; } - r = amdgpu_wb_init(adev); + r = amdgpu_device_wb_init(adev); if (r) { - DRM_ERROR("amdgpu_wb_init failed %d\n", r); + DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); return r; } adev->ip_blocks[i].status.hw = true; @@ -1535,18 +1535,18 @@ static int amdgpu_init(struct amdgpu_device *adev) return 0; } -static void amdgpu_fill_reset_magic(struct amdgpu_device *adev) +static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) { memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); } -static bool amdgpu_check_vram_lost(struct amdgpu_device *adev) +static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) { return !!memcmp(adev->gart.ptr, adev->reset_magic, AMDGPU_RESET_MAGIC_NUM); } -static int amdgpu_late_set_cg_state(struct amdgpu_device *adev) +static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev) { int i = 0, r; @@ -1569,7 +1569,7 @@ static int amdgpu_late_set_cg_state(struct amdgpu_device *adev) return 0; } -static int amdgpu_late_init(struct amdgpu_device *adev) +static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) { int i = 0, r; @@ -1590,12 +1590,12 @@ static int amdgpu_late_init(struct amdgpu_device *adev) mod_delayed_work(system_wq, &adev->late_init_work, msecs_to_jiffies(AMDGPU_RESUME_MS)); - amdgpu_fill_reset_magic(adev); + amdgpu_device_fill_reset_magic(adev); return 0; } -static int amdgpu_fini(struct amdgpu_device *adev) +static int amdgpu_device_ip_fini(struct amdgpu_device *adev) { int i, r; @@ -1629,8 +1629,8 @@ static int amdgpu_fini(struct amdgpu_device *adev) continue; if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { amdgpu_free_static_csa(adev); - amdgpu_wb_fini(adev); - amdgpu_vram_scratch_fini(adev); + amdgpu_device_wb_fini(adev); + amdgpu_device_vram_scratch_fini(adev); } if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && @@ -1683,11 +1683,11 @@ static int amdgpu_fini(struct amdgpu_device *adev) return 0; } -static void amdgpu_late_init_func_handler(struct work_struct *work) +static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work) { struct amdgpu_device *adev = container_of(work, struct amdgpu_device, late_init_work.work); - amdgpu_late_set_cg_state(adev); + amdgpu_device_ip_late_set_cg_state(adev); } int amdgpu_suspend(struct amdgpu_device *adev) @@ -1731,7 +1731,7 @@ int amdgpu_suspend(struct amdgpu_device *adev) return 0; } -static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) +static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) { int i, r; @@ -1760,7 +1760,7 @@ static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) return 0; } -static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) +static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) { int i, r; @@ -1793,7 +1793,7 @@ static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) return 0; } -static int amdgpu_resume_phase1(struct amdgpu_device *adev) +static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) { int i, r; @@ -1816,7 +1816,7 @@ static int amdgpu_resume_phase1(struct amdgpu_device *adev) return 0; } -static int amdgpu_resume_phase2(struct amdgpu_device *adev) +static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) { int i, r; @@ -1838,14 +1838,14 @@ static int amdgpu_resume_phase2(struct amdgpu_device *adev) return 0; } -static int amdgpu_resume(struct amdgpu_device *adev) +static int amdgpu_device_ip_resume(struct amdgpu_device *adev) { int r; - r = amdgpu_resume_phase1(adev); + r = amdgpu_device_ip_resume_phase1(adev); if (r) return r; - r = amdgpu_resume_phase2(adev); + r = amdgpu_device_ip_resume_phase2(adev); return r; } @@ -1984,7 +1984,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, hash_init(adev->mn_hash); mutex_init(&adev->lock_reset); - amdgpu_check_arguments(adev); + amdgpu_device_check_arguments(adev); spin_lock_init(&adev->mmio_idx_lock); spin_lock_init(&adev->smc_idx_lock); @@ -2002,7 +2002,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, INIT_LIST_HEAD(&adev->ring_lru_list); spin_lock_init(&adev->ring_lru_list_lock); - INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler); + INIT_DELAYED_WORK(&adev->late_init_work, + amdgpu_device_ip_late_init_func_handler); /* Registers mapping */ /* TODO: block userspace mapping of io register */ @@ -2022,7 +2023,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); /* doorbell bar mapping */ - amdgpu_doorbell_init(adev); + amdgpu_device_doorbell_init(adev); /* io port mapping */ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { @@ -2036,14 +2037,14 @@ int amdgpu_device_init(struct amdgpu_device *adev, DRM_INFO("PCI I/O BAR is not found.\n"); /* early init functions */ - r = amdgpu_early_init(adev); + r = amdgpu_device_ip_early_init(adev); if (r) return r; /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ /* this will fail for cards that aren't VGA class devices, just * ignore it */ - vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); + vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); if (amdgpu_runtime_pm == 1) runtime = true; @@ -2118,7 +2119,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* init the mode config */ drm_mode_config_init(adev->ddev); - r = amdgpu_init(adev); + r = amdgpu_device_ip_init(adev); if (r) { /* failed in exclusive mode due to timeout */ if (amdgpu_sriov_vf(adev) && @@ -2132,9 +2133,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, r = -EAGAIN; goto failed; } - dev_err(adev->dev, "amdgpu_init failed\n"); + dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); - amdgpu_fini(adev); + amdgpu_device_ip_fini(adev); goto failed; } @@ -2202,9 +2203,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* enable clockgating, etc. after ib tests, etc. since some blocks require * explicit gating rather than handling it automatically. */ - r = amdgpu_late_init(adev); + r = amdgpu_device_ip_late_init(adev); if (r) { - dev_err(adev->dev, "amdgpu_late_init failed\n"); + dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); goto failed; } @@ -2239,7 +2240,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev) amdgpu_ib_pool_fini(adev); amdgpu_fence_driver_fini(adev); amdgpu_fbdev_fini(adev); - r = amdgpu_fini(adev); + r = amdgpu_device_ip_fini(adev); if (adev->firmware.gpu_info_fw) { release_firmware(adev->firmware.gpu_info_fw); adev->firmware.gpu_info_fw = NULL; @@ -2262,7 +2263,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev) adev->rio_mem = NULL; iounmap(adev->rmmio); adev->rmmio = NULL; - amdgpu_doorbell_fini(adev); + amdgpu_device_doorbell_fini(adev); amdgpu_pm_sysfs_fini(adev); amdgpu_debugfs_regs_cleanup(adev); } @@ -2407,9 +2408,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) DRM_ERROR("amdgpu asic init failed\n"); } - r = amdgpu_resume(adev); + r = amdgpu_device_ip_resume(adev); if (r) { - DRM_ERROR("amdgpu_resume failed (%d).\n", r); + DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r); goto unlock; } amdgpu_fence_driver_resume(adev); @@ -2420,7 +2421,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) DRM_ERROR("ib ring test failed (%d).\n", r); } - r = amdgpu_late_init(adev); + r = amdgpu_device_ip_late_init(adev); if (r) goto unlock; @@ -2500,7 +2501,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) return r; } -static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) +static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) { int i; bool asic_hang = false; @@ -2522,7 +2523,7 @@ static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) return asic_hang; } -static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) +static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) { int i, r = 0; @@ -2540,7 +2541,7 @@ static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) return 0; } -static bool amdgpu_need_full_reset(struct amdgpu_device *adev) +static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) { int i; @@ -2561,7 +2562,7 @@ static bool amdgpu_need_full_reset(struct amdgpu_device *adev) return false; } -static int amdgpu_soft_reset(struct amdgpu_device *adev) +static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) { int i, r = 0; @@ -2579,7 +2580,7 @@ static int amdgpu_soft_reset(struct amdgpu_device *adev) return 0; } -static int amdgpu_post_soft_reset(struct amdgpu_device *adev) +static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) { int i, r = 0; @@ -2604,10 +2605,10 @@ bool amdgpu_need_backup(struct amdgpu_device *adev) return amdgpu_gpu_recovery; } -static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, - struct amdgpu_ring *ring, - struct amdgpu_bo *bo, - struct dma_fence **fence) +static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev, + struct amdgpu_ring *ring, + struct amdgpu_bo *bo, + struct dma_fence **fence) { uint32_t domain; int r; @@ -2640,7 +2641,7 @@ static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, } /* - * amdgpu_reset - reset ASIC/GPU for bare-metal or passthrough + * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough * * @adev: amdgpu device pointer * @reset_flags: output param tells caller the reset result @@ -2648,18 +2649,19 @@ static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, * attempt to do soft-reset or full-reset and reinitialize Asic * return 0 means successed otherwise failed */ -static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags) +static int amdgpu_device_reset(struct amdgpu_device *adev, + uint64_t* reset_flags) { bool need_full_reset, vram_lost = 0; int r; - need_full_reset = amdgpu_need_full_reset(adev); + need_full_reset = amdgpu_device_ip_need_full_reset(adev); if (!need_full_reset) { - amdgpu_pre_soft_reset(adev); - r = amdgpu_soft_reset(adev); - amdgpu_post_soft_reset(adev); - if (r || amdgpu_check_soft_reset(adev)) { + amdgpu_device_ip_pre_soft_reset(adev); + r = amdgpu_device_ip_soft_reset(adev); + amdgpu_device_ip_post_soft_reset(adev); + if (r || amdgpu_device_ip_check_soft_reset(adev)) { DRM_INFO("soft reset failed, will fallback to full reset!\n"); need_full_reset = true; } @@ -2676,11 +2678,11 @@ static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags) if (!r) { dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); - r = amdgpu_resume_phase1(adev); + r = amdgpu_device_ip_resume_phase1(adev); if (r) goto out; - vram_lost = amdgpu_check_vram_lost(adev); + vram_lost = amdgpu_device_check_vram_lost(adev); if (vram_lost) { DRM_ERROR("VRAM is lost!\n"); atomic_inc(&adev->vram_lost_counter); @@ -2691,12 +2693,12 @@ static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags) if (r) goto out; - r = amdgpu_resume_phase2(adev); + r = amdgpu_device_ip_resume_phase2(adev); if (r) goto out; if (vram_lost) - amdgpu_fill_reset_magic(adev); + amdgpu_device_fill_reset_magic(adev); } } @@ -2724,7 +2726,7 @@ static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags) } /* - * amdgpu_reset_sriov - reset ASIC for SR-IOV vf + * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf * * @adev: amdgpu device pointer * @reset_flags: output param tells caller the reset result @@ -2732,7 +2734,9 @@ static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags) * do VF FLR and reinitialize Asic * return 0 means successed otherwise failed */ -static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, bool from_hypervisor) +static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, + uint64_t *reset_flags, + bool from_hypervisor) { int r; @@ -2744,7 +2748,7 @@ static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, return r; /* Resume IP prior to SMC */ - r = amdgpu_sriov_reinit_early(adev); + r = amdgpu_device_ip_reinit_early_sriov(adev); if (r) goto error; @@ -2752,7 +2756,7 @@ static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]); /* now we are okay to resume SMC/CP/SDMA */ - r = amdgpu_sriov_reinit_late(adev); + r = amdgpu_device_ip_reinit_late_sriov(adev); if (r) goto error; @@ -2794,7 +2798,7 @@ int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job, bool uint64_t reset_flags = 0; int i, r, resched; - if (!amdgpu_check_soft_reset(adev)) { + if (!amdgpu_device_ip_check_soft_reset(adev)) { DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); return 0; } @@ -2836,9 +2840,9 @@ int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job, bool } if (amdgpu_sriov_vf(adev)) - r = amdgpu_reset_sriov(adev, &reset_flags, job ? false : true); + r = amdgpu_device_reset_sriov(adev, &reset_flags, job ? false : true); else - r = amdgpu_reset(adev, &reset_flags); + r = amdgpu_device_reset(adev, &reset_flags); if (!r) { if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) || @@ -2851,7 +2855,7 @@ int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job, bool mutex_lock(&adev->shadow_list_lock); list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { next = NULL; - amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); + amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next); if (fence) { r = dma_fence_wait(fence, false); if (r) { -- GitLab From cdd61df614851d18b8ee72f0615202bef67f5b91 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 14 Dec 2017 16:47:40 -0500 Subject: [PATCH 1716/2547] drm/amdgpu: rename amdgpu_suspend to amdgpu_device_ip_suspend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit for consistency with the other functions in that file. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ffbe99d839a3..169c71d48d49 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1961,7 +1961,7 @@ void amdgpu_driver_lastclose_kms(struct drm_device *dev); int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); void amdgpu_driver_postclose_kms(struct drm_device *dev, struct drm_file *file_priv); -int amdgpu_suspend(struct amdgpu_device *adev); +int amdgpu_device_ip_suspend(struct amdgpu_device *adev); int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 92b5064b3391..3beea322bc12 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1690,7 +1690,7 @@ static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work) amdgpu_device_ip_late_set_cg_state(adev); } -int amdgpu_suspend(struct amdgpu_device *adev) +int amdgpu_device_ip_suspend(struct amdgpu_device *adev) { int i, r; @@ -2344,7 +2344,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) amdgpu_fence_driver_suspend(adev); - r = amdgpu_suspend(adev); + r = amdgpu_device_ip_suspend(adev); /* evict remaining vram memory * This second call to evict vram is to evict the gart page table @@ -2669,7 +2669,7 @@ static int amdgpu_device_reset(struct amdgpu_device *adev, } if (need_full_reset) { - r = amdgpu_suspend(adev); + r = amdgpu_device_ip_suspend(adev); retry: r = amdgpu_asic_reset(adev); @@ -2708,7 +2708,7 @@ static int amdgpu_device_reset(struct amdgpu_device *adev, r = amdgpu_ib_ring_tests(adev); if (r) { dev_err(adev->dev, "ib ring test failed (%d).\n", r); - r = amdgpu_suspend(adev); + r = amdgpu_device_ip_suspend(adev); need_full_reset = true; goto retry; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 1fc5499cb5fd..50afcf65181a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -649,7 +649,7 @@ amdgpu_pci_shutdown(struct pci_dev *pdev) * unfortunately we can't detect certain * hypervisors so just do this all the time. */ - amdgpu_suspend(adev); + amdgpu_device_ip_suspend(adev); } static int amdgpu_pmops_suspend(struct device *dev) -- GitLab From 75758255dc0fae76a845fd5185cfcdf60990cc99 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 14 Dec 2017 15:23:14 -0500 Subject: [PATCH 1717/2547] drm/amdgpu: move debugfs functions to their own file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_device.c was getting pretty cluttered. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 +- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 792 ++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 42 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 769 +------------------ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +- 6 files changed, 838 insertions(+), 785 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index f778a3b4abe6..d8da12c114b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -52,7 +52,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \ amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \ - amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o + amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o # add asic specific block amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 169c71d48d49..c15b9441190f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -71,7 +71,7 @@ #include "amdgpu_dm.h" #include "amdgpu_virt.h" #include "amdgpu_gart.h" - +#include "amdgpu_debugfs.h" /* * Modules parameters. @@ -425,7 +425,6 @@ struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); -int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); /* sub-allocation manager, it has to be protected by another lock. * By conception this is an helper for other part of the driver @@ -1240,19 +1239,6 @@ void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); */ void amdgpu_test_moves(struct amdgpu_device *adev); -/* - * Debugfs - */ -struct amdgpu_debugfs { - const struct drm_info_list *files; - unsigned num_files; -}; - -int amdgpu_debugfs_add_files(struct amdgpu_device *adev, - const struct drm_info_list *files, - unsigned nfiles); -int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); -int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); /* * amdgpu smumgr functions diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c new file mode 100644 index 000000000000..ee76b468774a --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -0,0 +1,792 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include +#include +#include "amdgpu.h" + +/* + * Debugfs + */ +int amdgpu_debugfs_add_files(struct amdgpu_device *adev, + const struct drm_info_list *files, + unsigned nfiles) +{ + unsigned i; + + for (i = 0; i < adev->debugfs_count; i++) { + if (adev->debugfs[i].files == files) { + /* Already registered */ + return 0; + } + } + + i = adev->debugfs_count + 1; + if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { + DRM_ERROR("Reached maximum number of debugfs components.\n"); + DRM_ERROR("Report so we increase " + "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); + return -EINVAL; + } + adev->debugfs[adev->debugfs_count].files = files; + adev->debugfs[adev->debugfs_count].num_files = nfiles; + adev->debugfs_count = i; +#if defined(CONFIG_DEBUG_FS) + drm_debugfs_create_files(files, nfiles, + adev->ddev->primary->debugfs_root, + adev->ddev->primary); +#endif + return 0; +} + +#if defined(CONFIG_DEBUG_FS) + +static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + bool pm_pg_lock, use_bank; + unsigned instance_bank, sh_bank, se_bank; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + /* are we reading registers for which a PG lock is necessary? */ + pm_pg_lock = (*pos >> 23) & 1; + + if (*pos & (1ULL << 62)) { + se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; + sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; + instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; + + if (se_bank == 0x3FF) + se_bank = 0xFFFFFFFF; + if (sh_bank == 0x3FF) + sh_bank = 0xFFFFFFFF; + if (instance_bank == 0x3FF) + instance_bank = 0xFFFFFFFF; + use_bank = 1; + } else { + use_bank = 0; + } + + *pos &= (1UL << 22) - 1; + + if (use_bank) { + if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || + (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) + return -EINVAL; + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, se_bank, + sh_bank, instance_bank); + } + + if (pm_pg_lock) + mutex_lock(&adev->pm.mutex); + + while (size) { + uint32_t value; + + if (*pos > adev->rmmio_size) + goto end; + + value = RREG32(*pos >> 2); + r = put_user(value, (uint32_t *)buf); + if (r) { + result = r; + goto end; + } + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + +end: + if (use_bank) { + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + } + + if (pm_pg_lock) + mutex_unlock(&adev->pm.mutex); + + return result; +} + +static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + bool pm_pg_lock, use_bank; + unsigned instance_bank, sh_bank, se_bank; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + /* are we reading registers for which a PG lock is necessary? */ + pm_pg_lock = (*pos >> 23) & 1; + + if (*pos & (1ULL << 62)) { + se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; + sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; + instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; + + if (se_bank == 0x3FF) + se_bank = 0xFFFFFFFF; + if (sh_bank == 0x3FF) + sh_bank = 0xFFFFFFFF; + if (instance_bank == 0x3FF) + instance_bank = 0xFFFFFFFF; + use_bank = 1; + } else { + use_bank = 0; + } + + *pos &= (1UL << 22) - 1; + + if (use_bank) { + if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || + (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) + return -EINVAL; + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, se_bank, + sh_bank, instance_bank); + } + + if (pm_pg_lock) + mutex_lock(&adev->pm.mutex); + + while (size) { + uint32_t value; + + if (*pos > adev->rmmio_size) + return result; + + r = get_user(value, (uint32_t *)buf); + if (r) + return r; + + WREG32(*pos >> 2, value); + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + if (use_bank) { + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + } + + if (pm_pg_lock) + mutex_unlock(&adev->pm.mutex); + + return result; +} + +static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + value = RREG32_PCIE(*pos >> 2); + r = put_user(value, (uint32_t *)buf); + if (r) + return r; + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + r = get_user(value, (uint32_t *)buf); + if (r) + return r; + + WREG32_PCIE(*pos >> 2, value); + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + value = RREG32_DIDT(*pos >> 2); + r = put_user(value, (uint32_t *)buf); + if (r) + return r; + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + r = get_user(value, (uint32_t *)buf); + if (r) + return r; + + WREG32_DIDT(*pos >> 2, value); + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + value = RREG32_SMC(*pos); + r = put_user(value, (uint32_t *)buf); + if (r) + return r; + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + r = get_user(value, (uint32_t *)buf); + if (r) + return r; + + WREG32_SMC(*pos, value); + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + uint32_t *config, no_regs = 0; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); + if (!config) + return -ENOMEM; + + /* version, increment each time something is added */ + config[no_regs++] = 3; + config[no_regs++] = adev->gfx.config.max_shader_engines; + config[no_regs++] = adev->gfx.config.max_tile_pipes; + config[no_regs++] = adev->gfx.config.max_cu_per_sh; + config[no_regs++] = adev->gfx.config.max_sh_per_se; + config[no_regs++] = adev->gfx.config.max_backends_per_se; + config[no_regs++] = adev->gfx.config.max_texture_channel_caches; + config[no_regs++] = adev->gfx.config.max_gprs; + config[no_regs++] = adev->gfx.config.max_gs_threads; + config[no_regs++] = adev->gfx.config.max_hw_contexts; + config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; + config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; + config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; + config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; + config[no_regs++] = adev->gfx.config.num_tile_pipes; + config[no_regs++] = adev->gfx.config.backend_enable_mask; + config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; + config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; + config[no_regs++] = adev->gfx.config.shader_engine_tile_size; + config[no_regs++] = adev->gfx.config.num_gpus; + config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; + config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; + config[no_regs++] = adev->gfx.config.gb_addr_config; + config[no_regs++] = adev->gfx.config.num_rbs; + + /* rev==1 */ + config[no_regs++] = adev->rev_id; + config[no_regs++] = adev->pg_flags; + config[no_regs++] = adev->cg_flags; + + /* rev==2 */ + config[no_regs++] = adev->family; + config[no_regs++] = adev->external_rev_id; + + /* rev==3 */ + config[no_regs++] = adev->pdev->device; + config[no_regs++] = adev->pdev->revision; + config[no_regs++] = adev->pdev->subsystem_device; + config[no_regs++] = adev->pdev->subsystem_vendor; + + while (size && (*pos < no_regs * 4)) { + uint32_t value; + + value = config[*pos >> 2]; + r = put_user(value, (uint32_t *)buf); + if (r) { + kfree(config); + return r; + } + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + kfree(config); + return result; +} + +static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + int idx, x, outsize, r, valuesize; + uint32_t values[16]; + + if (size & 3 || *pos & 0x3) + return -EINVAL; + + if (amdgpu_dpm == 0) + return -EINVAL; + + /* convert offset to sensor number */ + idx = *pos >> 2; + + valuesize = sizeof(values); + if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) + r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize); + else + return -EINVAL; + + if (size > valuesize) + return -EINVAL; + + outsize = 0; + x = 0; + if (!r) { + while (size) { + r = put_user(values[x++], (int32_t *)buf); + buf += 4; + size -= 4; + outsize += 4; + } + } + + return !r ? outsize : r; +} + +static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + int r, x; + ssize_t result=0; + uint32_t offset, se, sh, cu, wave, simd, data[32]; + + if (size & 3 || *pos & 3) + return -EINVAL; + + /* decode offset */ + offset = (*pos & GENMASK_ULL(6, 0)); + se = (*pos & GENMASK_ULL(14, 7)) >> 7; + sh = (*pos & GENMASK_ULL(22, 15)) >> 15; + cu = (*pos & GENMASK_ULL(30, 23)) >> 23; + wave = (*pos & GENMASK_ULL(36, 31)) >> 31; + simd = (*pos & GENMASK_ULL(44, 37)) >> 37; + + /* switch to the specific se/sh/cu */ + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, se, sh, cu); + + x = 0; + if (adev->gfx.funcs->read_wave_data) + adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); + + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); + mutex_unlock(&adev->grbm_idx_mutex); + + if (!x) + return -EINVAL; + + while (size && (offset < x * 4)) { + uint32_t value; + + value = data[offset >> 2]; + r = put_user(value, (uint32_t *)buf); + if (r) + return r; + + result += 4; + buf += 4; + offset += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + int r; + ssize_t result = 0; + uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; + + if (size & 3 || *pos & 3) + return -EINVAL; + + /* decode offset */ + offset = *pos & GENMASK_ULL(11, 0); + se = (*pos & GENMASK_ULL(19, 12)) >> 12; + sh = (*pos & GENMASK_ULL(27, 20)) >> 20; + cu = (*pos & GENMASK_ULL(35, 28)) >> 28; + wave = (*pos & GENMASK_ULL(43, 36)) >> 36; + simd = (*pos & GENMASK_ULL(51, 44)) >> 44; + thread = (*pos & GENMASK_ULL(59, 52)) >> 52; + bank = (*pos & GENMASK_ULL(61, 60)) >> 60; + + data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + /* switch to the specific se/sh/cu */ + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, se, sh, cu); + + if (bank == 0) { + if (adev->gfx.funcs->read_wave_vgprs) + adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); + } else { + if (adev->gfx.funcs->read_wave_sgprs) + adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); + } + + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); + mutex_unlock(&adev->grbm_idx_mutex); + + while (size) { + uint32_t value; + + value = data[offset++]; + r = put_user(value, (uint32_t *)buf); + if (r) { + result = r; + goto err; + } + + result += 4; + buf += 4; + size -= 4; + } + +err: + kfree(data); + return result; +} + +static const struct file_operations amdgpu_debugfs_regs_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_regs_read, + .write = amdgpu_debugfs_regs_write, + .llseek = default_llseek +}; +static const struct file_operations amdgpu_debugfs_regs_didt_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_regs_didt_read, + .write = amdgpu_debugfs_regs_didt_write, + .llseek = default_llseek +}; +static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_regs_pcie_read, + .write = amdgpu_debugfs_regs_pcie_write, + .llseek = default_llseek +}; +static const struct file_operations amdgpu_debugfs_regs_smc_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_regs_smc_read, + .write = amdgpu_debugfs_regs_smc_write, + .llseek = default_llseek +}; + +static const struct file_operations amdgpu_debugfs_gca_config_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_gca_config_read, + .llseek = default_llseek +}; + +static const struct file_operations amdgpu_debugfs_sensors_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_sensor_read, + .llseek = default_llseek +}; + +static const struct file_operations amdgpu_debugfs_wave_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_wave_read, + .llseek = default_llseek +}; +static const struct file_operations amdgpu_debugfs_gpr_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_gpr_read, + .llseek = default_llseek +}; + +static const struct file_operations *debugfs_regs[] = { + &amdgpu_debugfs_regs_fops, + &amdgpu_debugfs_regs_didt_fops, + &amdgpu_debugfs_regs_pcie_fops, + &amdgpu_debugfs_regs_smc_fops, + &amdgpu_debugfs_gca_config_fops, + &amdgpu_debugfs_sensors_fops, + &amdgpu_debugfs_wave_fops, + &amdgpu_debugfs_gpr_fops, +}; + +static const char *debugfs_regs_names[] = { + "amdgpu_regs", + "amdgpu_regs_didt", + "amdgpu_regs_pcie", + "amdgpu_regs_smc", + "amdgpu_gca_config", + "amdgpu_sensors", + "amdgpu_wave", + "amdgpu_gpr", +}; + +int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) +{ + struct drm_minor *minor = adev->ddev->primary; + struct dentry *ent, *root = minor->debugfs_root; + unsigned i, j; + + for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { + ent = debugfs_create_file(debugfs_regs_names[i], + S_IFREG | S_IRUGO, root, + adev, debugfs_regs[i]); + if (IS_ERR(ent)) { + for (j = 0; j < i; j++) { + debugfs_remove(adev->debugfs_regs[i]); + adev->debugfs_regs[i] = NULL; + } + return PTR_ERR(ent); + } + + if (!i) + i_size_write(ent->d_inode, adev->rmmio_size); + adev->debugfs_regs[i] = ent; + } + + return 0; +} + +void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { + if (adev->debugfs_regs[i]) { + debugfs_remove(adev->debugfs_regs[i]); + adev->debugfs_regs[i] = NULL; + } + } +} + +static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = dev->dev_private; + int r = 0, i; + + /* hold on the scheduler */ + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { + struct amdgpu_ring *ring = adev->rings[i]; + + if (!ring || !ring->sched.thread) + continue; + kthread_park(ring->sched.thread); + } + + seq_printf(m, "run ib test:\n"); + r = amdgpu_ib_ring_tests(adev); + if (r) + seq_printf(m, "ib ring tests failed (%d).\n", r); + else + seq_printf(m, "ib ring tests passed.\n"); + + /* go on the scheduler */ + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { + struct amdgpu_ring *ring = adev->rings[i]; + + if (!ring || !ring->sched.thread) + continue; + kthread_unpark(ring->sched.thread); + } + + return 0; +} + +static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = dev->dev_private; + + seq_write(m, adev->bios, adev->bios_size); + return 0; +} + +static int amdgpu_debugfs_evict_vram(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = dev->dev_private; + + seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev)); + return 0; +} + +static const struct drm_info_list amdgpu_debugfs_list[] = { + {"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump}, + {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}, + {"amdgpu_evict_vram", &amdgpu_debugfs_evict_vram} +}; + +int amdgpu_debugfs_init(struct amdgpu_device *adev) +{ + return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list, + ARRAY_SIZE(amdgpu_debugfs_list)); +} + +#else +int amdgpu_debugfs_init(struct amdgpu_device *adev) +{ + return 0; +} +int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) +{ + return 0; +} +void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h new file mode 100644 index 000000000000..8260d8073c26 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h @@ -0,0 +1,42 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/* + * Debugfs + */ +struct amdgpu_debugfs { + const struct drm_info_list *files; + unsigned num_files; +}; + +int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); +void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); +int amdgpu_debugfs_init(struct amdgpu_device *adev); +int amdgpu_debugfs_add_files(struct amdgpu_device *adev, + const struct drm_info_list *files, + unsigned nfiles); +int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); +int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); +int amdgpu_debugfs_gem_init(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 3beea322bc12..ec078a9a5de8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -64,10 +63,6 @@ MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); #define AMDGPU_RESUME_MS 2000 -static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); -static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); -static int amdgpu_debugfs_init(struct amdgpu_device *adev); - static const char *amdgpu_asic_name[] = { "TAHITI", "PITCAIRN", @@ -2171,7 +2166,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (r) DRM_ERROR("registering pm debugfs failed (%d).\n", r); - r = amdgpu_gem_debugfs_init(adev); + r = amdgpu_debugfs_gem_init(adev); if (r) DRM_ERROR("registering gem debugfs failed (%d).\n", r); @@ -3020,765 +3015,3 @@ void amdgpu_get_pcie_info(struct amdgpu_device *adev) } } -/* - * Debugfs - */ -int amdgpu_debugfs_add_files(struct amdgpu_device *adev, - const struct drm_info_list *files, - unsigned nfiles) -{ - unsigned i; - - for (i = 0; i < adev->debugfs_count; i++) { - if (adev->debugfs[i].files == files) { - /* Already registered */ - return 0; - } - } - - i = adev->debugfs_count + 1; - if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { - DRM_ERROR("Reached maximum number of debugfs components.\n"); - DRM_ERROR("Report so we increase " - "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); - return -EINVAL; - } - adev->debugfs[adev->debugfs_count].files = files; - adev->debugfs[adev->debugfs_count].num_files = nfiles; - adev->debugfs_count = i; -#if defined(CONFIG_DEBUG_FS) - drm_debugfs_create_files(files, nfiles, - adev->ddev->primary->debugfs_root, - adev->ddev->primary); -#endif - return 0; -} - -#if defined(CONFIG_DEBUG_FS) - -static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = file_inode(f)->i_private; - ssize_t result = 0; - int r; - bool pm_pg_lock, use_bank; - unsigned instance_bank, sh_bank, se_bank; - - if (size & 0x3 || *pos & 0x3) - return -EINVAL; - - /* are we reading registers for which a PG lock is necessary? */ - pm_pg_lock = (*pos >> 23) & 1; - - if (*pos & (1ULL << 62)) { - se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; - sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; - instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; - - if (se_bank == 0x3FF) - se_bank = 0xFFFFFFFF; - if (sh_bank == 0x3FF) - sh_bank = 0xFFFFFFFF; - if (instance_bank == 0x3FF) - instance_bank = 0xFFFFFFFF; - use_bank = 1; - } else { - use_bank = 0; - } - - *pos &= (1UL << 22) - 1; - - if (use_bank) { - if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || - (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) - return -EINVAL; - mutex_lock(&adev->grbm_idx_mutex); - amdgpu_gfx_select_se_sh(adev, se_bank, - sh_bank, instance_bank); - } - - if (pm_pg_lock) - mutex_lock(&adev->pm.mutex); - - while (size) { - uint32_t value; - - if (*pos > adev->rmmio_size) - goto end; - - value = RREG32(*pos >> 2); - r = put_user(value, (uint32_t *)buf); - if (r) { - result = r; - goto end; - } - - result += 4; - buf += 4; - *pos += 4; - size -= 4; - } - -end: - if (use_bank) { - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); - mutex_unlock(&adev->grbm_idx_mutex); - } - - if (pm_pg_lock) - mutex_unlock(&adev->pm.mutex); - - return result; -} - -static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = file_inode(f)->i_private; - ssize_t result = 0; - int r; - bool pm_pg_lock, use_bank; - unsigned instance_bank, sh_bank, se_bank; - - if (size & 0x3 || *pos & 0x3) - return -EINVAL; - - /* are we reading registers for which a PG lock is necessary? */ - pm_pg_lock = (*pos >> 23) & 1; - - if (*pos & (1ULL << 62)) { - se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; - sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; - instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; - - if (se_bank == 0x3FF) - se_bank = 0xFFFFFFFF; - if (sh_bank == 0x3FF) - sh_bank = 0xFFFFFFFF; - if (instance_bank == 0x3FF) - instance_bank = 0xFFFFFFFF; - use_bank = 1; - } else { - use_bank = 0; - } - - *pos &= (1UL << 22) - 1; - - if (use_bank) { - if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || - (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) - return -EINVAL; - mutex_lock(&adev->grbm_idx_mutex); - amdgpu_gfx_select_se_sh(adev, se_bank, - sh_bank, instance_bank); - } - - if (pm_pg_lock) - mutex_lock(&adev->pm.mutex); - - while (size) { - uint32_t value; - - if (*pos > adev->rmmio_size) - return result; - - r = get_user(value, (uint32_t *)buf); - if (r) - return r; - - WREG32(*pos >> 2, value); - - result += 4; - buf += 4; - *pos += 4; - size -= 4; - } - - if (use_bank) { - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); - mutex_unlock(&adev->grbm_idx_mutex); - } - - if (pm_pg_lock) - mutex_unlock(&adev->pm.mutex); - - return result; -} - -static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = file_inode(f)->i_private; - ssize_t result = 0; - int r; - - if (size & 0x3 || *pos & 0x3) - return -EINVAL; - - while (size) { - uint32_t value; - - value = RREG32_PCIE(*pos >> 2); - r = put_user(value, (uint32_t *)buf); - if (r) - return r; - - result += 4; - buf += 4; - *pos += 4; - size -= 4; - } - - return result; -} - -static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = file_inode(f)->i_private; - ssize_t result = 0; - int r; - - if (size & 0x3 || *pos & 0x3) - return -EINVAL; - - while (size) { - uint32_t value; - - r = get_user(value, (uint32_t *)buf); - if (r) - return r; - - WREG32_PCIE(*pos >> 2, value); - - result += 4; - buf += 4; - *pos += 4; - size -= 4; - } - - return result; -} - -static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = file_inode(f)->i_private; - ssize_t result = 0; - int r; - - if (size & 0x3 || *pos & 0x3) - return -EINVAL; - - while (size) { - uint32_t value; - - value = RREG32_DIDT(*pos >> 2); - r = put_user(value, (uint32_t *)buf); - if (r) - return r; - - result += 4; - buf += 4; - *pos += 4; - size -= 4; - } - - return result; -} - -static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = file_inode(f)->i_private; - ssize_t result = 0; - int r; - - if (size & 0x3 || *pos & 0x3) - return -EINVAL; - - while (size) { - uint32_t value; - - r = get_user(value, (uint32_t *)buf); - if (r) - return r; - - WREG32_DIDT(*pos >> 2, value); - - result += 4; - buf += 4; - *pos += 4; - size -= 4; - } - - return result; -} - -static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = file_inode(f)->i_private; - ssize_t result = 0; - int r; - - if (size & 0x3 || *pos & 0x3) - return -EINVAL; - - while (size) { - uint32_t value; - - value = RREG32_SMC(*pos); - r = put_user(value, (uint32_t *)buf); - if (r) - return r; - - result += 4; - buf += 4; - *pos += 4; - size -= 4; - } - - return result; -} - -static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = file_inode(f)->i_private; - ssize_t result = 0; - int r; - - if (size & 0x3 || *pos & 0x3) - return -EINVAL; - - while (size) { - uint32_t value; - - r = get_user(value, (uint32_t *)buf); - if (r) - return r; - - WREG32_SMC(*pos, value); - - result += 4; - buf += 4; - *pos += 4; - size -= 4; - } - - return result; -} - -static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = file_inode(f)->i_private; - ssize_t result = 0; - int r; - uint32_t *config, no_regs = 0; - - if (size & 0x3 || *pos & 0x3) - return -EINVAL; - - config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); - if (!config) - return -ENOMEM; - - /* version, increment each time something is added */ - config[no_regs++] = 3; - config[no_regs++] = adev->gfx.config.max_shader_engines; - config[no_regs++] = adev->gfx.config.max_tile_pipes; - config[no_regs++] = adev->gfx.config.max_cu_per_sh; - config[no_regs++] = adev->gfx.config.max_sh_per_se; - config[no_regs++] = adev->gfx.config.max_backends_per_se; - config[no_regs++] = adev->gfx.config.max_texture_channel_caches; - config[no_regs++] = adev->gfx.config.max_gprs; - config[no_regs++] = adev->gfx.config.max_gs_threads; - config[no_regs++] = adev->gfx.config.max_hw_contexts; - config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; - config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; - config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; - config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; - config[no_regs++] = adev->gfx.config.num_tile_pipes; - config[no_regs++] = adev->gfx.config.backend_enable_mask; - config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; - config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; - config[no_regs++] = adev->gfx.config.shader_engine_tile_size; - config[no_regs++] = adev->gfx.config.num_gpus; - config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; - config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; - config[no_regs++] = adev->gfx.config.gb_addr_config; - config[no_regs++] = adev->gfx.config.num_rbs; - - /* rev==1 */ - config[no_regs++] = adev->rev_id; - config[no_regs++] = adev->pg_flags; - config[no_regs++] = adev->cg_flags; - - /* rev==2 */ - config[no_regs++] = adev->family; - config[no_regs++] = adev->external_rev_id; - - /* rev==3 */ - config[no_regs++] = adev->pdev->device; - config[no_regs++] = adev->pdev->revision; - config[no_regs++] = adev->pdev->subsystem_device; - config[no_regs++] = adev->pdev->subsystem_vendor; - - while (size && (*pos < no_regs * 4)) { - uint32_t value; - - value = config[*pos >> 2]; - r = put_user(value, (uint32_t *)buf); - if (r) { - kfree(config); - return r; - } - - result += 4; - buf += 4; - *pos += 4; - size -= 4; - } - - kfree(config); - return result; -} - -static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = file_inode(f)->i_private; - int idx, x, outsize, r, valuesize; - uint32_t values[16]; - - if (size & 3 || *pos & 0x3) - return -EINVAL; - - if (amdgpu_dpm == 0) - return -EINVAL; - - /* convert offset to sensor number */ - idx = *pos >> 2; - - valuesize = sizeof(values); - if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) - r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize); - else - return -EINVAL; - - if (size > valuesize) - return -EINVAL; - - outsize = 0; - x = 0; - if (!r) { - while (size) { - r = put_user(values[x++], (int32_t *)buf); - buf += 4; - size -= 4; - outsize += 4; - } - } - - return !r ? outsize : r; -} - -static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = f->f_inode->i_private; - int r, x; - ssize_t result=0; - uint32_t offset, se, sh, cu, wave, simd, data[32]; - - if (size & 3 || *pos & 3) - return -EINVAL; - - /* decode offset */ - offset = (*pos & GENMASK_ULL(6, 0)); - se = (*pos & GENMASK_ULL(14, 7)) >> 7; - sh = (*pos & GENMASK_ULL(22, 15)) >> 15; - cu = (*pos & GENMASK_ULL(30, 23)) >> 23; - wave = (*pos & GENMASK_ULL(36, 31)) >> 31; - simd = (*pos & GENMASK_ULL(44, 37)) >> 37; - - /* switch to the specific se/sh/cu */ - mutex_lock(&adev->grbm_idx_mutex); - amdgpu_gfx_select_se_sh(adev, se, sh, cu); - - x = 0; - if (adev->gfx.funcs->read_wave_data) - adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); - - amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); - mutex_unlock(&adev->grbm_idx_mutex); - - if (!x) - return -EINVAL; - - while (size && (offset < x * 4)) { - uint32_t value; - - value = data[offset >> 2]; - r = put_user(value, (uint32_t *)buf); - if (r) - return r; - - result += 4; - buf += 4; - offset += 4; - size -= 4; - } - - return result; -} - -static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = f->f_inode->i_private; - int r; - ssize_t result = 0; - uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; - - if (size & 3 || *pos & 3) - return -EINVAL; - - /* decode offset */ - offset = *pos & GENMASK_ULL(11, 0); - se = (*pos & GENMASK_ULL(19, 12)) >> 12; - sh = (*pos & GENMASK_ULL(27, 20)) >> 20; - cu = (*pos & GENMASK_ULL(35, 28)) >> 28; - wave = (*pos & GENMASK_ULL(43, 36)) >> 36; - simd = (*pos & GENMASK_ULL(51, 44)) >> 44; - thread = (*pos & GENMASK_ULL(59, 52)) >> 52; - bank = (*pos & GENMASK_ULL(61, 60)) >> 60; - - data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - /* switch to the specific se/sh/cu */ - mutex_lock(&adev->grbm_idx_mutex); - amdgpu_gfx_select_se_sh(adev, se, sh, cu); - - if (bank == 0) { - if (adev->gfx.funcs->read_wave_vgprs) - adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); - } else { - if (adev->gfx.funcs->read_wave_sgprs) - adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); - } - - amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); - mutex_unlock(&adev->grbm_idx_mutex); - - while (size) { - uint32_t value; - - value = data[offset++]; - r = put_user(value, (uint32_t *)buf); - if (r) { - result = r; - goto err; - } - - result += 4; - buf += 4; - size -= 4; - } - -err: - kfree(data); - return result; -} - -static const struct file_operations amdgpu_debugfs_regs_fops = { - .owner = THIS_MODULE, - .read = amdgpu_debugfs_regs_read, - .write = amdgpu_debugfs_regs_write, - .llseek = default_llseek -}; -static const struct file_operations amdgpu_debugfs_regs_didt_fops = { - .owner = THIS_MODULE, - .read = amdgpu_debugfs_regs_didt_read, - .write = amdgpu_debugfs_regs_didt_write, - .llseek = default_llseek -}; -static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { - .owner = THIS_MODULE, - .read = amdgpu_debugfs_regs_pcie_read, - .write = amdgpu_debugfs_regs_pcie_write, - .llseek = default_llseek -}; -static const struct file_operations amdgpu_debugfs_regs_smc_fops = { - .owner = THIS_MODULE, - .read = amdgpu_debugfs_regs_smc_read, - .write = amdgpu_debugfs_regs_smc_write, - .llseek = default_llseek -}; - -static const struct file_operations amdgpu_debugfs_gca_config_fops = { - .owner = THIS_MODULE, - .read = amdgpu_debugfs_gca_config_read, - .llseek = default_llseek -}; - -static const struct file_operations amdgpu_debugfs_sensors_fops = { - .owner = THIS_MODULE, - .read = amdgpu_debugfs_sensor_read, - .llseek = default_llseek -}; - -static const struct file_operations amdgpu_debugfs_wave_fops = { - .owner = THIS_MODULE, - .read = amdgpu_debugfs_wave_read, - .llseek = default_llseek -}; -static const struct file_operations amdgpu_debugfs_gpr_fops = { - .owner = THIS_MODULE, - .read = amdgpu_debugfs_gpr_read, - .llseek = default_llseek -}; - -static const struct file_operations *debugfs_regs[] = { - &amdgpu_debugfs_regs_fops, - &amdgpu_debugfs_regs_didt_fops, - &amdgpu_debugfs_regs_pcie_fops, - &amdgpu_debugfs_regs_smc_fops, - &amdgpu_debugfs_gca_config_fops, - &amdgpu_debugfs_sensors_fops, - &amdgpu_debugfs_wave_fops, - &amdgpu_debugfs_gpr_fops, -}; - -static const char *debugfs_regs_names[] = { - "amdgpu_regs", - "amdgpu_regs_didt", - "amdgpu_regs_pcie", - "amdgpu_regs_smc", - "amdgpu_gca_config", - "amdgpu_sensors", - "amdgpu_wave", - "amdgpu_gpr", -}; - -static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) -{ - struct drm_minor *minor = adev->ddev->primary; - struct dentry *ent, *root = minor->debugfs_root; - unsigned i, j; - - for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { - ent = debugfs_create_file(debugfs_regs_names[i], - S_IFREG | S_IRUGO, root, - adev, debugfs_regs[i]); - if (IS_ERR(ent)) { - for (j = 0; j < i; j++) { - debugfs_remove(adev->debugfs_regs[i]); - adev->debugfs_regs[i] = NULL; - } - return PTR_ERR(ent); - } - - if (!i) - i_size_write(ent->d_inode, adev->rmmio_size); - adev->debugfs_regs[i] = ent; - } - - return 0; -} - -static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) -{ - unsigned i; - - for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { - if (adev->debugfs_regs[i]) { - debugfs_remove(adev->debugfs_regs[i]); - adev->debugfs_regs[i] = NULL; - } - } -} - -static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = dev->dev_private; - int r = 0, i; - - /* hold on the scheduler */ - for (i = 0; i < AMDGPU_MAX_RINGS; i++) { - struct amdgpu_ring *ring = adev->rings[i]; - - if (!ring || !ring->sched.thread) - continue; - kthread_park(ring->sched.thread); - } - - seq_printf(m, "run ib test:\n"); - r = amdgpu_ib_ring_tests(adev); - if (r) - seq_printf(m, "ib ring tests failed (%d).\n", r); - else - seq_printf(m, "ib ring tests passed.\n"); - - /* go on the scheduler */ - for (i = 0; i < AMDGPU_MAX_RINGS; i++) { - struct amdgpu_ring *ring = adev->rings[i]; - - if (!ring || !ring->sched.thread) - continue; - kthread_unpark(ring->sched.thread); - } - - return 0; -} - -static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = dev->dev_private; - - seq_write(m, adev->bios, adev->bios_size); - return 0; -} - -static int amdgpu_debugfs_evict_vram(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *)m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = dev->dev_private; - - seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev)); - return 0; -} - -static const struct drm_info_list amdgpu_debugfs_list[] = { - {"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump}, - {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}, - {"amdgpu_evict_vram", &amdgpu_debugfs_evict_vram} -}; - -static int amdgpu_debugfs_init(struct amdgpu_device *adev) -{ - return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list, - ARRAY_SIZE(amdgpu_debugfs_list)); -} - -#else -static int amdgpu_debugfs_init(struct amdgpu_device *adev) -{ - return 0; -} -static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) -{ - return 0; -} -static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } -#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index eb75eb44efc6..10805edcf964 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -851,7 +851,7 @@ static const struct drm_info_list amdgpu_debugfs_gem_list[] = { }; #endif -int amdgpu_gem_debugfs_init(struct amdgpu_device *adev) +int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) { #if defined(CONFIG_DEBUG_FS) return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); -- GitLab From 131b4b3686b701079e8fb82eb9384c8acdd3fc72 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 14 Dec 2017 16:03:43 -0500 Subject: [PATCH 1718/2547] drm/amdgpu: rename amdgpu_wb_* functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add device for consistency. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 16 ++++++++-------- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/si_dma.c | 10 +++++----- 10 files changed, 46 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c15b9441190f..81c1ddb9eb3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1171,8 +1171,8 @@ struct amdgpu_wb { unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; }; -int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); -void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); +int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); +void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); void amdgpu_get_pcie_info(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ec078a9a5de8..7b44ca29a2c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -530,7 +530,7 @@ static int amdgpu_device_wb_init(struct amdgpu_device *adev) } /** - * amdgpu_wb_get - Allocate a wb entry + * amdgpu_device_wb_get - Allocate a wb entry * * @adev: amdgpu_device pointer * @wb: wb index @@ -538,7 +538,7 @@ static int amdgpu_device_wb_init(struct amdgpu_device *adev) * Allocate a wb slot for use by the driver (all asics). * Returns 0 on success or -EINVAL on failure. */ -int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) +int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) { unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); @@ -552,14 +552,14 @@ int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) } /** - * amdgpu_wb_free - Free a wb entry + * amdgpu_device_wb_free - Free a wb entry * * @adev: amdgpu_device pointer * @wb: wb index * * Free a wb slot allocated for use by the driver (all asics) */ -void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) +void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) { if (wb < adev->wb.num_wb) __clear_bit(wb >> 3, adev->wb.used); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index ef043361009f..bb40d2529a30 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -203,7 +203,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, spin_lock_init(&kiq->ring_lock); - r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); + r = amdgpu_device_wb_get(adev, &adev->virt.reg_val_offs); if (r) return r; @@ -229,7 +229,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring, struct amdgpu_irq_src *irq) { - amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); + amdgpu_device_wb_free(ring->adev, ring->adev->virt.reg_val_offs); amdgpu_ring_fini(ring); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index f5f27e4f0f7f..06373d44b3da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -92,15 +92,15 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size, } return 0; } else { - r = amdgpu_wb_get(adev, &adev->irq.ih.wptr_offs); + r = amdgpu_device_wb_get(adev, &adev->irq.ih.wptr_offs); if (r) { dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r); return r; } - r = amdgpu_wb_get(adev, &adev->irq.ih.rptr_offs); + r = amdgpu_device_wb_get(adev, &adev->irq.ih.rptr_offs); if (r) { - amdgpu_wb_free(adev, adev->irq.ih.wptr_offs); + amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs); dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r); return r; } @@ -133,8 +133,8 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev) amdgpu_bo_free_kernel(&adev->irq.ih.ring_obj, &adev->irq.ih.gpu_addr, (void **)&adev->irq.ih.ring); - amdgpu_wb_free(adev, adev->irq.ih.wptr_offs); - amdgpu_wb_free(adev, adev->irq.ih.rptr_offs); + amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs); + amdgpu_device_wb_free(adev, adev->irq.ih.rptr_offs); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 41c75f9632dc..13044e66dcaf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -263,25 +263,25 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, return r; } - r = amdgpu_wb_get(adev, &ring->rptr_offs); + r = amdgpu_device_wb_get(adev, &ring->rptr_offs); if (r) { dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); return r; } - r = amdgpu_wb_get(adev, &ring->wptr_offs); + r = amdgpu_device_wb_get(adev, &ring->wptr_offs); if (r) { dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); return r; } - r = amdgpu_wb_get(adev, &ring->fence_offs); + r = amdgpu_device_wb_get(adev, &ring->fence_offs); if (r) { dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); return r; } - r = amdgpu_wb_get(adev, &ring->cond_exe_offs); + r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs); if (r) { dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); return r; @@ -348,11 +348,11 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring) if (!(ring->adev) || !(ring->adev->rings[ring->idx])) return; - amdgpu_wb_free(ring->adev, ring->rptr_offs); - amdgpu_wb_free(ring->adev, ring->wptr_offs); + amdgpu_device_wb_free(ring->adev, ring->rptr_offs); + amdgpu_device_wb_free(ring->adev, ring->wptr_offs); - amdgpu_wb_free(ring->adev, ring->cond_exe_offs); - amdgpu_wb_free(ring->adev, ring->fence_offs); + amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs); + amdgpu_device_wb_free(ring->adev, ring->fence_offs); amdgpu_bo_free_kernel(&ring->ring_obj, &ring->gpu_addr, diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index ed26dcbc4f79..e406c93d01d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -626,7 +626,7 @@ static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) u32 tmp; u64 gpu_addr; - r = amdgpu_wb_get(adev, &index); + r = amdgpu_device_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); return r; @@ -639,7 +639,7 @@ static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 5); if (r) { DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); @@ -663,7 +663,7 @@ static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) ring->idx, tmp); r = -EINVAL; } - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } @@ -686,7 +686,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) u64 gpu_addr; long r; - r = amdgpu_wb_get(adev, &index); + r = amdgpu_device_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); return r; @@ -735,7 +735,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(adev, &ib, NULL); dma_fence_put(f); err0: - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 121e628e7cdb..0c5b91a40f22 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -600,7 +600,7 @@ static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) u32 tmp; u64 gpu_addr; - r = amdgpu_wb_get(adev, &index); + r = amdgpu_device_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); return r; @@ -613,7 +613,7 @@ static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 5); if (r) { DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } @@ -639,7 +639,7 @@ static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) ring->idx, tmp); r = -EINVAL; } - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } @@ -662,7 +662,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) u64 gpu_addr; long r; - r = amdgpu_wb_get(adev, &index); + r = amdgpu_device_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); return r; @@ -715,7 +715,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(adev, &ib, NULL); dma_fence_put(f); err0: - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 41c60f5ac96e..4e031a2aad9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -867,7 +867,7 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) u32 tmp; u64 gpu_addr; - r = amdgpu_wb_get(adev, &index); + r = amdgpu_device_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); return r; @@ -880,7 +880,7 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 5); if (r) { DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } @@ -906,7 +906,7 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) ring->idx, tmp); r = -EINVAL; } - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } @@ -929,7 +929,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) u64 gpu_addr; long r; - r = amdgpu_wb_get(adev, &index); + r = amdgpu_device_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); return r; @@ -981,7 +981,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(adev, &ib, NULL); dma_fence_put(f); err0: - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 79e82bf35f7d..73477c5ed9b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -869,7 +869,7 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) u32 tmp; u64 gpu_addr; - r = amdgpu_wb_get(adev, &index); + r = amdgpu_device_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); return r; @@ -882,7 +882,7 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 5); if (r) { DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } @@ -908,7 +908,7 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) ring->idx, tmp); r = -EINVAL; } - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } @@ -931,7 +931,7 @@ static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) u32 tmp = 0; u64 gpu_addr; - r = amdgpu_wb_get(adev, &index); + r = amdgpu_device_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); return r; @@ -983,7 +983,7 @@ static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(adev, &ib, NULL); dma_fence_put(f); err0: - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index ee469a906cd3..9adca5d8b045 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -221,7 +221,7 @@ static int si_dma_ring_test_ring(struct amdgpu_ring *ring) u32 tmp; u64 gpu_addr; - r = amdgpu_wb_get(adev, &index); + r = amdgpu_device_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); return r; @@ -234,7 +234,7 @@ static int si_dma_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 4); if (r) { DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } @@ -258,7 +258,7 @@ static int si_dma_ring_test_ring(struct amdgpu_ring *ring) ring->idx, tmp); r = -EINVAL; } - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } @@ -281,7 +281,7 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout) u64 gpu_addr; long r; - r = amdgpu_wb_get(adev, &index); + r = amdgpu_device_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); return r; @@ -328,7 +328,7 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(adev, &ib, NULL); dma_fence_put(f); err0: - amdgpu_wb_free(adev, index); + amdgpu_device_wb_free(adev, index); return r; } -- GitLab From 9c3f2b54746f764e1b695797c78bc46b8713f067 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 14 Dec 2017 16:20:19 -0500 Subject: [PATCH 1719/2547] drm/amdgpu: rename amdgpu_program_register_sequence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add device for consistency with other functions in this file. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +- drivers/gpu/drm/amd/amdgpu/cik.c | 120 ++++++++++----------- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 24 ++--- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 30 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 114 ++++++++++---------- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 12 +-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 54 +++++----- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 48 ++++----- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 12 +-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 60 +++++------ drivers/gpu/drm/amd/amdgpu/si.c | 102 +++++++++--------- drivers/gpu/drm/amd/amdgpu/vi.c | 30 +++--- 14 files changed, 311 insertions(+), 311 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 81c1ddb9eb3a..f10f4fc7dbe0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1913,7 +1913,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); -void amdgpu_program_register_sequence(struct amdgpu_device *adev, +void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, const u32 *registers, const u32 array_size); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7b44ca29a2c8..05e5c6822f9c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -342,7 +342,7 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) } /** - * amdgpu_program_register_sequence - program an array of registers. + * amdgpu_device_program_register_sequence - program an array of registers. * * @adev: amdgpu_device pointer * @registers: pointer to the register array @@ -351,9 +351,9 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) * Programs an array or registers with and and or masks. * This is a helper for setting golden registers. */ -void amdgpu_program_register_sequence(struct amdgpu_device *adev, - const u32 *registers, - const u32 array_size) +void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, + const u32 *registers, + const u32 array_size) { u32 tmp, reg, and_mask, or_mask; int i; diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 8ba056a2a5da..39d49712f8c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -755,74 +755,74 @@ static void cik_init_golden_registers(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_BONAIRE: - amdgpu_program_register_sequence(adev, - bonaire_mgcg_cgcg_init, - ARRAY_SIZE(bonaire_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - bonaire_golden_registers, - ARRAY_SIZE(bonaire_golden_registers)); - amdgpu_program_register_sequence(adev, - bonaire_golden_common_registers, - ARRAY_SIZE(bonaire_golden_common_registers)); - amdgpu_program_register_sequence(adev, - bonaire_golden_spm_registers, - ARRAY_SIZE(bonaire_golden_spm_registers)); + amdgpu_device_program_register_sequence(adev, + bonaire_mgcg_cgcg_init, + ARRAY_SIZE(bonaire_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + bonaire_golden_registers, + ARRAY_SIZE(bonaire_golden_registers)); + amdgpu_device_program_register_sequence(adev, + bonaire_golden_common_registers, + ARRAY_SIZE(bonaire_golden_common_registers)); + amdgpu_device_program_register_sequence(adev, + bonaire_golden_spm_registers, + ARRAY_SIZE(bonaire_golden_spm_registers)); break; case CHIP_KABINI: - amdgpu_program_register_sequence(adev, - kalindi_mgcg_cgcg_init, - ARRAY_SIZE(kalindi_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - kalindi_golden_registers, - ARRAY_SIZE(kalindi_golden_registers)); - amdgpu_program_register_sequence(adev, - kalindi_golden_common_registers, - ARRAY_SIZE(kalindi_golden_common_registers)); - amdgpu_program_register_sequence(adev, - kalindi_golden_spm_registers, - ARRAY_SIZE(kalindi_golden_spm_registers)); + amdgpu_device_program_register_sequence(adev, + kalindi_mgcg_cgcg_init, + ARRAY_SIZE(kalindi_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + kalindi_golden_registers, + ARRAY_SIZE(kalindi_golden_registers)); + amdgpu_device_program_register_sequence(adev, + kalindi_golden_common_registers, + ARRAY_SIZE(kalindi_golden_common_registers)); + amdgpu_device_program_register_sequence(adev, + kalindi_golden_spm_registers, + ARRAY_SIZE(kalindi_golden_spm_registers)); break; case CHIP_MULLINS: - amdgpu_program_register_sequence(adev, - kalindi_mgcg_cgcg_init, - ARRAY_SIZE(kalindi_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - godavari_golden_registers, - ARRAY_SIZE(godavari_golden_registers)); - amdgpu_program_register_sequence(adev, - kalindi_golden_common_registers, - ARRAY_SIZE(kalindi_golden_common_registers)); - amdgpu_program_register_sequence(adev, - kalindi_golden_spm_registers, - ARRAY_SIZE(kalindi_golden_spm_registers)); + amdgpu_device_program_register_sequence(adev, + kalindi_mgcg_cgcg_init, + ARRAY_SIZE(kalindi_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + godavari_golden_registers, + ARRAY_SIZE(godavari_golden_registers)); + amdgpu_device_program_register_sequence(adev, + kalindi_golden_common_registers, + ARRAY_SIZE(kalindi_golden_common_registers)); + amdgpu_device_program_register_sequence(adev, + kalindi_golden_spm_registers, + ARRAY_SIZE(kalindi_golden_spm_registers)); break; case CHIP_KAVERI: - amdgpu_program_register_sequence(adev, - spectre_mgcg_cgcg_init, - ARRAY_SIZE(spectre_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - spectre_golden_registers, - ARRAY_SIZE(spectre_golden_registers)); - amdgpu_program_register_sequence(adev, - spectre_golden_common_registers, - ARRAY_SIZE(spectre_golden_common_registers)); - amdgpu_program_register_sequence(adev, - spectre_golden_spm_registers, - ARRAY_SIZE(spectre_golden_spm_registers)); + amdgpu_device_program_register_sequence(adev, + spectre_mgcg_cgcg_init, + ARRAY_SIZE(spectre_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + spectre_golden_registers, + ARRAY_SIZE(spectre_golden_registers)); + amdgpu_device_program_register_sequence(adev, + spectre_golden_common_registers, + ARRAY_SIZE(spectre_golden_common_registers)); + amdgpu_device_program_register_sequence(adev, + spectre_golden_spm_registers, + ARRAY_SIZE(spectre_golden_spm_registers)); break; case CHIP_HAWAII: - amdgpu_program_register_sequence(adev, - hawaii_mgcg_cgcg_init, - ARRAY_SIZE(hawaii_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - hawaii_golden_registers, - ARRAY_SIZE(hawaii_golden_registers)); - amdgpu_program_register_sequence(adev, - hawaii_golden_common_registers, - ARRAY_SIZE(hawaii_golden_common_registers)); - amdgpu_program_register_sequence(adev, - hawaii_golden_spm_registers, - ARRAY_SIZE(hawaii_golden_spm_registers)); + amdgpu_device_program_register_sequence(adev, + hawaii_mgcg_cgcg_init, + ARRAY_SIZE(hawaii_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + hawaii_golden_registers, + ARRAY_SIZE(hawaii_golden_registers)); + amdgpu_device_program_register_sequence(adev, + hawaii_golden_common_registers, + ARRAY_SIZE(hawaii_golden_common_registers)); + amdgpu_device_program_register_sequence(adev, + hawaii_golden_spm_registers, + ARRAY_SIZE(hawaii_golden_spm_registers)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index a397111c2ced..f34bc68aadfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -145,20 +145,20 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_FIJI: - amdgpu_program_register_sequence(adev, - fiji_mgcg_cgcg_init, - ARRAY_SIZE(fiji_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - golden_settings_fiji_a10, - ARRAY_SIZE(golden_settings_fiji_a10)); + amdgpu_device_program_register_sequence(adev, + fiji_mgcg_cgcg_init, + ARRAY_SIZE(fiji_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + golden_settings_fiji_a10, + ARRAY_SIZE(golden_settings_fiji_a10)); break; case CHIP_TONGA: - amdgpu_program_register_sequence(adev, - tonga_mgcg_cgcg_init, - ARRAY_SIZE(tonga_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - golden_settings_tonga_a11, - ARRAY_SIZE(golden_settings_tonga_a11)); + amdgpu_device_program_register_sequence(adev, + tonga_mgcg_cgcg_init, + ARRAY_SIZE(tonga_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + golden_settings_tonga_a11, + ARRAY_SIZE(golden_settings_tonga_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 67e670989e81..26378bd6aba4 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -154,28 +154,28 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_CARRIZO: - amdgpu_program_register_sequence(adev, - cz_mgcg_cgcg_init, - ARRAY_SIZE(cz_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - cz_golden_settings_a11, - ARRAY_SIZE(cz_golden_settings_a11)); + amdgpu_device_program_register_sequence(adev, + cz_mgcg_cgcg_init, + ARRAY_SIZE(cz_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + cz_golden_settings_a11, + ARRAY_SIZE(cz_golden_settings_a11)); break; case CHIP_STONEY: - amdgpu_program_register_sequence(adev, - stoney_golden_settings_a11, - ARRAY_SIZE(stoney_golden_settings_a11)); + amdgpu_device_program_register_sequence(adev, + stoney_golden_settings_a11, + ARRAY_SIZE(stoney_golden_settings_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: - amdgpu_program_register_sequence(adev, - polaris11_golden_settings_a11, - ARRAY_SIZE(polaris11_golden_settings_a11)); + amdgpu_device_program_register_sequence(adev, + polaris11_golden_settings_a11, + ARRAY_SIZE(polaris11_golden_settings_a11)); break; case CHIP_POLARIS10: - amdgpu_program_register_sequence(adev, - polaris10_golden_settings_a11, - ARRAY_SIZE(polaris10_golden_settings_a11)); + amdgpu_device_program_register_sequence(adev, + polaris10_golden_settings_a11, + ARRAY_SIZE(polaris10_golden_settings_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index c7dc69031fb5..4a9c28cd144d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -679,55 +679,55 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_TOPAZ: - amdgpu_program_register_sequence(adev, - iceland_mgcg_cgcg_init, - ARRAY_SIZE(iceland_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - golden_settings_iceland_a11, - ARRAY_SIZE(golden_settings_iceland_a11)); - amdgpu_program_register_sequence(adev, - iceland_golden_common_all, - ARRAY_SIZE(iceland_golden_common_all)); + amdgpu_device_program_register_sequence(adev, + iceland_mgcg_cgcg_init, + ARRAY_SIZE(iceland_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + golden_settings_iceland_a11, + ARRAY_SIZE(golden_settings_iceland_a11)); + amdgpu_device_program_register_sequence(adev, + iceland_golden_common_all, + ARRAY_SIZE(iceland_golden_common_all)); break; case CHIP_FIJI: - amdgpu_program_register_sequence(adev, - fiji_mgcg_cgcg_init, - ARRAY_SIZE(fiji_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - golden_settings_fiji_a10, - ARRAY_SIZE(golden_settings_fiji_a10)); - amdgpu_program_register_sequence(adev, - fiji_golden_common_all, - ARRAY_SIZE(fiji_golden_common_all)); + amdgpu_device_program_register_sequence(adev, + fiji_mgcg_cgcg_init, + ARRAY_SIZE(fiji_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + golden_settings_fiji_a10, + ARRAY_SIZE(golden_settings_fiji_a10)); + amdgpu_device_program_register_sequence(adev, + fiji_golden_common_all, + ARRAY_SIZE(fiji_golden_common_all)); break; case CHIP_TONGA: - amdgpu_program_register_sequence(adev, - tonga_mgcg_cgcg_init, - ARRAY_SIZE(tonga_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - golden_settings_tonga_a11, - ARRAY_SIZE(golden_settings_tonga_a11)); - amdgpu_program_register_sequence(adev, - tonga_golden_common_all, - ARRAY_SIZE(tonga_golden_common_all)); + amdgpu_device_program_register_sequence(adev, + tonga_mgcg_cgcg_init, + ARRAY_SIZE(tonga_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + golden_settings_tonga_a11, + ARRAY_SIZE(golden_settings_tonga_a11)); + amdgpu_device_program_register_sequence(adev, + tonga_golden_common_all, + ARRAY_SIZE(tonga_golden_common_all)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: - amdgpu_program_register_sequence(adev, - golden_settings_polaris11_a11, - ARRAY_SIZE(golden_settings_polaris11_a11)); - amdgpu_program_register_sequence(adev, - polaris11_golden_common_all, - ARRAY_SIZE(polaris11_golden_common_all)); + amdgpu_device_program_register_sequence(adev, + golden_settings_polaris11_a11, + ARRAY_SIZE(golden_settings_polaris11_a11)); + amdgpu_device_program_register_sequence(adev, + polaris11_golden_common_all, + ARRAY_SIZE(polaris11_golden_common_all)); break; case CHIP_POLARIS10: - amdgpu_program_register_sequence(adev, - golden_settings_polaris10_a11, - ARRAY_SIZE(golden_settings_polaris10_a11)); - amdgpu_program_register_sequence(adev, - polaris10_golden_common_all, - ARRAY_SIZE(polaris10_golden_common_all)); + amdgpu_device_program_register_sequence(adev, + golden_settings_polaris10_a11, + ARRAY_SIZE(golden_settings_polaris10_a11)); + amdgpu_device_program_register_sequence(adev, + polaris10_golden_common_all, + ARRAY_SIZE(polaris10_golden_common_all)); WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); if (adev->pdev->revision == 0xc7 && ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || @@ -738,26 +738,26 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) } break; case CHIP_CARRIZO: - amdgpu_program_register_sequence(adev, - cz_mgcg_cgcg_init, - ARRAY_SIZE(cz_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - cz_golden_settings_a11, - ARRAY_SIZE(cz_golden_settings_a11)); - amdgpu_program_register_sequence(adev, - cz_golden_common_all, - ARRAY_SIZE(cz_golden_common_all)); + amdgpu_device_program_register_sequence(adev, + cz_mgcg_cgcg_init, + ARRAY_SIZE(cz_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + cz_golden_settings_a11, + ARRAY_SIZE(cz_golden_settings_a11)); + amdgpu_device_program_register_sequence(adev, + cz_golden_common_all, + ARRAY_SIZE(cz_golden_common_all)); break; case CHIP_STONEY: - amdgpu_program_register_sequence(adev, - stoney_mgcg_cgcg_init, - ARRAY_SIZE(stoney_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - stoney_golden_settings_a11, - ARRAY_SIZE(stoney_golden_settings_a11)); - amdgpu_program_register_sequence(adev, - stoney_golden_common_all, - ARRAY_SIZE(stoney_golden_common_all)); + amdgpu_device_program_register_sequence(adev, + stoney_mgcg_cgcg_init, + ARRAY_SIZE(stoney_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + stoney_golden_settings_a11, + ARRAY_SIZE(stoney_golden_settings_a11)); + amdgpu_device_program_register_sequence(adev, + stoney_golden_common_all, + ARRAY_SIZE(stoney_golden_common_all)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 9c28e18741ea..c4285395b5fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -67,12 +67,12 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_TOPAZ: - amdgpu_program_register_sequence(adev, - iceland_mgcg_cgcg_init, - ARRAY_SIZE(iceland_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - golden_settings_iceland_a11, - ARRAY_SIZE(golden_settings_iceland_a11)); + amdgpu_device_program_register_sequence(adev, + iceland_mgcg_cgcg_init, + ARRAY_SIZE(iceland_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + golden_settings_iceland_a11, + ARRAY_SIZE(golden_settings_iceland_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index efed20ac4a01..6641276ecbdf 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -120,44 +120,44 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_FIJI: - amdgpu_program_register_sequence(adev, - fiji_mgcg_cgcg_init, - ARRAY_SIZE(fiji_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - golden_settings_fiji_a10, - ARRAY_SIZE(golden_settings_fiji_a10)); + amdgpu_device_program_register_sequence(adev, + fiji_mgcg_cgcg_init, + ARRAY_SIZE(fiji_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + golden_settings_fiji_a10, + ARRAY_SIZE(golden_settings_fiji_a10)); break; case CHIP_TONGA: - amdgpu_program_register_sequence(adev, - tonga_mgcg_cgcg_init, - ARRAY_SIZE(tonga_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - golden_settings_tonga_a11, - ARRAY_SIZE(golden_settings_tonga_a11)); + amdgpu_device_program_register_sequence(adev, + tonga_mgcg_cgcg_init, + ARRAY_SIZE(tonga_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + golden_settings_tonga_a11, + ARRAY_SIZE(golden_settings_tonga_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: - amdgpu_program_register_sequence(adev, - golden_settings_polaris11_a11, - ARRAY_SIZE(golden_settings_polaris11_a11)); + amdgpu_device_program_register_sequence(adev, + golden_settings_polaris11_a11, + ARRAY_SIZE(golden_settings_polaris11_a11)); break; case CHIP_POLARIS10: - amdgpu_program_register_sequence(adev, - golden_settings_polaris10_a11, - ARRAY_SIZE(golden_settings_polaris10_a11)); + amdgpu_device_program_register_sequence(adev, + golden_settings_polaris10_a11, + ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: - amdgpu_program_register_sequence(adev, - cz_mgcg_cgcg_init, - ARRAY_SIZE(cz_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + cz_mgcg_cgcg_init, + ARRAY_SIZE(cz_mgcg_cgcg_init)); break; case CHIP_STONEY: - amdgpu_program_register_sequence(adev, - stoney_mgcg_cgcg_init, - ARRAY_SIZE(stoney_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - golden_settings_stoney_common, - ARRAY_SIZE(golden_settings_stoney_common)); + amdgpu_device_program_register_sequence(adev, + stoney_mgcg_cgcg_init, + ARRAY_SIZE(stoney_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + golden_settings_stoney_common, + ARRAY_SIZE(golden_settings_stoney_common)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 5da2272bd313..899ffe50cb50 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -918,9 +918,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) bool value; u32 tmp; - amdgpu_program_register_sequence(adev, - golden_settings_vega10_hdp, - ARRAY_SIZE(golden_settings_vega10_hdp)); + amdgpu_device_program_register_sequence(adev, + golden_settings_vega10_hdp, + ARRAY_SIZE(golden_settings_vega10_hdp)); if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index da7c261d5d87..af2d47e9abdc 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -279,32 +279,32 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_FIJI: - amdgpu_program_register_sequence(adev, - xgpu_fiji_mgcg_cgcg_init, - ARRAY_SIZE( - xgpu_fiji_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - xgpu_fiji_golden_settings_a10, - ARRAY_SIZE( - xgpu_fiji_golden_settings_a10)); - amdgpu_program_register_sequence(adev, - xgpu_fiji_golden_common_all, - ARRAY_SIZE( - xgpu_fiji_golden_common_all)); + amdgpu_device_program_register_sequence(adev, + xgpu_fiji_mgcg_cgcg_init, + ARRAY_SIZE( + xgpu_fiji_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + xgpu_fiji_golden_settings_a10, + ARRAY_SIZE( + xgpu_fiji_golden_settings_a10)); + amdgpu_device_program_register_sequence(adev, + xgpu_fiji_golden_common_all, + ARRAY_SIZE( + xgpu_fiji_golden_common_all)); break; case CHIP_TONGA: - amdgpu_program_register_sequence(adev, - xgpu_tonga_mgcg_cgcg_init, - ARRAY_SIZE( - xgpu_tonga_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - xgpu_tonga_golden_settings_a11, - ARRAY_SIZE( - xgpu_tonga_golden_settings_a11)); - amdgpu_program_register_sequence(adev, - xgpu_tonga_golden_common_all, - ARRAY_SIZE( - xgpu_tonga_golden_common_all)); + amdgpu_device_program_register_sequence(adev, + xgpu_tonga_mgcg_cgcg_init, + ARRAY_SIZE( + xgpu_tonga_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + xgpu_tonga_golden_settings_a11, + ARRAY_SIZE( + xgpu_tonga_golden_settings_a11)); + amdgpu_device_program_register_sequence(adev, + xgpu_tonga_golden_common_all, + ARRAY_SIZE( + xgpu_tonga_golden_common_all)); break; default: BUG_ON("Doesn't support chip type.\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 0c5b91a40f22..401552bae7f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -93,12 +93,12 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_TOPAZ: - amdgpu_program_register_sequence(adev, - iceland_mgcg_cgcg_init, - ARRAY_SIZE(iceland_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - golden_settings_iceland_a11, - ARRAY_SIZE(golden_settings_iceland_a11)); + amdgpu_device_program_register_sequence(adev, + iceland_mgcg_cgcg_init, + ARRAY_SIZE(iceland_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + golden_settings_iceland_a11, + ARRAY_SIZE(golden_settings_iceland_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 4e031a2aad9d..0735d4d0e56a 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -192,47 +192,47 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_FIJI: - amdgpu_program_register_sequence(adev, - fiji_mgcg_cgcg_init, - ARRAY_SIZE(fiji_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - golden_settings_fiji_a10, - ARRAY_SIZE(golden_settings_fiji_a10)); + amdgpu_device_program_register_sequence(adev, + fiji_mgcg_cgcg_init, + ARRAY_SIZE(fiji_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + golden_settings_fiji_a10, + ARRAY_SIZE(golden_settings_fiji_a10)); break; case CHIP_TONGA: - amdgpu_program_register_sequence(adev, - tonga_mgcg_cgcg_init, - ARRAY_SIZE(tonga_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - golden_settings_tonga_a11, - ARRAY_SIZE(golden_settings_tonga_a11)); + amdgpu_device_program_register_sequence(adev, + tonga_mgcg_cgcg_init, + ARRAY_SIZE(tonga_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + golden_settings_tonga_a11, + ARRAY_SIZE(golden_settings_tonga_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: - amdgpu_program_register_sequence(adev, - golden_settings_polaris11_a11, - ARRAY_SIZE(golden_settings_polaris11_a11)); + amdgpu_device_program_register_sequence(adev, + golden_settings_polaris11_a11, + ARRAY_SIZE(golden_settings_polaris11_a11)); break; case CHIP_POLARIS10: - amdgpu_program_register_sequence(adev, - golden_settings_polaris10_a11, - ARRAY_SIZE(golden_settings_polaris10_a11)); + amdgpu_device_program_register_sequence(adev, + golden_settings_polaris10_a11, + ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: - amdgpu_program_register_sequence(adev, - cz_mgcg_cgcg_init, - ARRAY_SIZE(cz_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - cz_golden_settings_a11, - ARRAY_SIZE(cz_golden_settings_a11)); + amdgpu_device_program_register_sequence(adev, + cz_mgcg_cgcg_init, + ARRAY_SIZE(cz_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + cz_golden_settings_a11, + ARRAY_SIZE(cz_golden_settings_a11)); break; case CHIP_STONEY: - amdgpu_program_register_sequence(adev, - stoney_mgcg_cgcg_init, - ARRAY_SIZE(stoney_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - stoney_golden_settings_a11, - ARRAY_SIZE(stoney_golden_settings_a11)); + amdgpu_device_program_register_sequence(adev, + stoney_mgcg_cgcg_init, + ARRAY_SIZE(stoney_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + stoney_golden_settings_a11, + ARRAY_SIZE(stoney_golden_settings_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 49eef3090f08..78baddb5d300 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1390,65 +1390,65 @@ static void si_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_TAHITI: - amdgpu_program_register_sequence(adev, - tahiti_golden_registers, - ARRAY_SIZE(tahiti_golden_registers)); - amdgpu_program_register_sequence(adev, - tahiti_golden_rlc_registers, - ARRAY_SIZE(tahiti_golden_rlc_registers)); - amdgpu_program_register_sequence(adev, - tahiti_mgcg_cgcg_init, - ARRAY_SIZE(tahiti_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - tahiti_golden_registers2, - ARRAY_SIZE(tahiti_golden_registers2)); + amdgpu_device_program_register_sequence(adev, + tahiti_golden_registers, + ARRAY_SIZE(tahiti_golden_registers)); + amdgpu_device_program_register_sequence(adev, + tahiti_golden_rlc_registers, + ARRAY_SIZE(tahiti_golden_rlc_registers)); + amdgpu_device_program_register_sequence(adev, + tahiti_mgcg_cgcg_init, + ARRAY_SIZE(tahiti_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + tahiti_golden_registers2, + ARRAY_SIZE(tahiti_golden_registers2)); break; case CHIP_PITCAIRN: - amdgpu_program_register_sequence(adev, - pitcairn_golden_registers, - ARRAY_SIZE(pitcairn_golden_registers)); - amdgpu_program_register_sequence(adev, - pitcairn_golden_rlc_registers, - ARRAY_SIZE(pitcairn_golden_rlc_registers)); - amdgpu_program_register_sequence(adev, - pitcairn_mgcg_cgcg_init, - ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + pitcairn_golden_registers, + ARRAY_SIZE(pitcairn_golden_registers)); + amdgpu_device_program_register_sequence(adev, + pitcairn_golden_rlc_registers, + ARRAY_SIZE(pitcairn_golden_rlc_registers)); + amdgpu_device_program_register_sequence(adev, + pitcairn_mgcg_cgcg_init, + ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); break; case CHIP_VERDE: - amdgpu_program_register_sequence(adev, - verde_golden_registers, - ARRAY_SIZE(verde_golden_registers)); - amdgpu_program_register_sequence(adev, - verde_golden_rlc_registers, - ARRAY_SIZE(verde_golden_rlc_registers)); - amdgpu_program_register_sequence(adev, - verde_mgcg_cgcg_init, - ARRAY_SIZE(verde_mgcg_cgcg_init)); - amdgpu_program_register_sequence(adev, - verde_pg_init, - ARRAY_SIZE(verde_pg_init)); + amdgpu_device_program_register_sequence(adev, + verde_golden_registers, + ARRAY_SIZE(verde_golden_registers)); + amdgpu_device_program_register_sequence(adev, + verde_golden_rlc_registers, + ARRAY_SIZE(verde_golden_rlc_registers)); + amdgpu_device_program_register_sequence(adev, + verde_mgcg_cgcg_init, + ARRAY_SIZE(verde_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + verde_pg_init, + ARRAY_SIZE(verde_pg_init)); break; case CHIP_OLAND: - amdgpu_program_register_sequence(adev, - oland_golden_registers, - ARRAY_SIZE(oland_golden_registers)); - amdgpu_program_register_sequence(adev, - oland_golden_rlc_registers, - ARRAY_SIZE(oland_golden_rlc_registers)); - amdgpu_program_register_sequence(adev, - oland_mgcg_cgcg_init, - ARRAY_SIZE(oland_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + oland_golden_registers, + ARRAY_SIZE(oland_golden_registers)); + amdgpu_device_program_register_sequence(adev, + oland_golden_rlc_registers, + ARRAY_SIZE(oland_golden_rlc_registers)); + amdgpu_device_program_register_sequence(adev, + oland_mgcg_cgcg_init, + ARRAY_SIZE(oland_mgcg_cgcg_init)); break; case CHIP_HAINAN: - amdgpu_program_register_sequence(adev, - hainan_golden_registers, - ARRAY_SIZE(hainan_golden_registers)); - amdgpu_program_register_sequence(adev, - hainan_golden_registers2, - ARRAY_SIZE(hainan_golden_registers2)); - amdgpu_program_register_sequence(adev, - hainan_mgcg_cgcg_init, - ARRAY_SIZE(hainan_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + hainan_golden_registers, + ARRAY_SIZE(hainan_golden_registers)); + amdgpu_device_program_register_sequence(adev, + hainan_golden_registers2, + ARRAY_SIZE(hainan_golden_registers2)); + amdgpu_device_program_register_sequence(adev, + hainan_mgcg_cgcg_init, + ARRAY_SIZE(hainan_mgcg_cgcg_init)); break; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index bb8ca9489546..0b57c5d24510 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -282,29 +282,29 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_TOPAZ: - amdgpu_program_register_sequence(adev, - iceland_mgcg_cgcg_init, - ARRAY_SIZE(iceland_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + iceland_mgcg_cgcg_init, + ARRAY_SIZE(iceland_mgcg_cgcg_init)); break; case CHIP_FIJI: - amdgpu_program_register_sequence(adev, - fiji_mgcg_cgcg_init, - ARRAY_SIZE(fiji_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + fiji_mgcg_cgcg_init, + ARRAY_SIZE(fiji_mgcg_cgcg_init)); break; case CHIP_TONGA: - amdgpu_program_register_sequence(adev, - tonga_mgcg_cgcg_init, - ARRAY_SIZE(tonga_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + tonga_mgcg_cgcg_init, + ARRAY_SIZE(tonga_mgcg_cgcg_init)); break; case CHIP_CARRIZO: - amdgpu_program_register_sequence(adev, - cz_mgcg_cgcg_init, - ARRAY_SIZE(cz_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + cz_mgcg_cgcg_init, + ARRAY_SIZE(cz_mgcg_cgcg_init)); break; case CHIP_STONEY: - amdgpu_program_register_sequence(adev, - stoney_mgcg_cgcg_init, - ARRAY_SIZE(stoney_mgcg_cgcg_init)); + amdgpu_device_program_register_sequence(adev, + stoney_mgcg_cgcg_init, + ARRAY_SIZE(stoney_mgcg_cgcg_init)); break; case CHIP_POLARIS11: case CHIP_POLARIS10: -- GitLab From 8111c387275f64aae972d5717d32b0f756bb6e5f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 14 Dec 2017 16:22:53 -0500 Subject: [PATCH 1720/2547] drm/amdgpu: rename amdgpu_pci_config_reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add device for consistency with other functions in this file. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik.c | 2 +- drivers/gpu/drm/amd/amdgpu/vi.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index f10f4fc7dbe0..941535d94f87 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1899,7 +1899,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) /* Common functions */ int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job, bool force); bool amdgpu_need_backup(struct amdgpu_device *adev); -void amdgpu_pci_config_reset(struct amdgpu_device *adev); +void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); bool amdgpu_need_post(struct amdgpu_device *adev); void amdgpu_update_display_priority(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 05e5c6822f9c..2ff4194fd153 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -377,7 +377,7 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, } } -void amdgpu_pci_config_reset(struct amdgpu_device *adev) +void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) { pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); } diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 39d49712f8c9..132ba226f289 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1246,7 +1246,7 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev) /* disable BM */ pci_clear_master(adev->pdev); /* reset */ - amdgpu_pci_config_reset(adev); + amdgpu_device_pci_config_reset(adev); udelay(100); diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 0b57c5d24510..0e1202914fa8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -667,7 +667,7 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) /* disable BM */ pci_clear_master(adev->pdev); /* reset */ - amdgpu_pci_config_reset(adev); + amdgpu_device_pci_config_reset(adev); udelay(100); -- GitLab From 22cb0164378c6511423f79d429e0b2e4290934df Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 14 Dec 2017 16:27:11 -0500 Subject: [PATCH 1721/2547] drm/amdgpu: move amdgpu_doorbell_get_kfd_info to amdgpu_amdkfd.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's the only place it's used. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 33 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 +--------------------- 3 files changed, 34 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 941535d94f87..b03f9242448c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -651,12 +651,6 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT AMDGPU_DOORBELL64_INVALID = 0xFFFF } AMDGPU_DOORBELL64_ASSIGNMENT; - -void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, - phys_addr_t *aperture_base, - size_t *aperture_size, - size_t *start_offset); - /* * IRQS. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index c70cda04dbfb..896b16db58aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -93,6 +93,39 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) adev->pdev, kfd2kgd); } +/** + * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to + * setup amdkfd + * + * @adev: amdgpu_device pointer + * @aperture_base: output returning doorbell aperture base physical address + * @aperture_size: output returning doorbell aperture size in bytes + * @start_offset: output returning # of doorbell bytes reserved for amdgpu. + * + * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, + * takes doorbells required for its own rings and reports the setup to amdkfd. + * amdgpu reserved doorbells are at the start of the doorbell aperture. + */ +static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, + phys_addr_t *aperture_base, + size_t *aperture_size, + size_t *start_offset) +{ + /* + * The first num_doorbells are used by amdgpu. + * amdkfd takes whatever's left in the aperture. + */ + if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { + *aperture_base = adev->doorbell.base; + *aperture_size = adev->doorbell.size; + *start_offset = adev->doorbell.num_doorbells * sizeof(u32); + } else { + *aperture_base = 0; + *aperture_size = 0; + *start_offset = 0; + } +} + void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) { int i; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2ff4194fd153..ae9a3a0334d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -438,38 +438,7 @@ static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) adev->doorbell.ptr = NULL; } -/** - * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to - * setup amdkfd - * - * @adev: amdgpu_device pointer - * @aperture_base: output returning doorbell aperture base physical address - * @aperture_size: output returning doorbell aperture size in bytes - * @start_offset: output returning # of doorbell bytes reserved for amdgpu. - * - * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, - * takes doorbells required for its own rings and reports the setup to amdkfd. - * amdgpu reserved doorbells are at the start of the doorbell aperture. - */ -void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, - phys_addr_t *aperture_base, - size_t *aperture_size, - size_t *start_offset) -{ - /* - * The first num_doorbells are used by amdgpu. - * amdkfd takes whatever's left in the aperture. - */ - if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { - *aperture_base = adev->doorbell.base; - *aperture_size = adev->doorbell.size; - *start_offset = adev->doorbell.num_doorbells * sizeof(u32); - } else { - *aperture_base = 0; - *aperture_size = 0; - *start_offset = 0; - } -} + /* * amdgpu_device_wb_*() -- GitLab From 2543e28a81b8d687880315475ba1203ca2f7496a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 14 Dec 2017 16:33:36 -0500 Subject: [PATCH 1722/2547] drm/amdgpu: rename amdgpu_*_location functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add device to the name for consistency. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++++++---- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- 6 files changed, 18 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index b03f9242448c..ac21addcde7d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1901,8 +1901,10 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, u64 num_vis_bytes); void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); -void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); -void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); +void amdgpu_device_vram_location(struct amdgpu_device *adev, + struct amdgpu_mc *mc, u64 base); +void amdgpu_device_gart_location(struct amdgpu_device *adev, + struct amdgpu_mc *mc); int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); int amdgpu_ttm_init(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ae9a3a0334d7..09ffa9fbcd92 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -535,7 +535,7 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) } /** - * amdgpu_vram_location - try to find VRAM location + * amdgpu_device_vram_location - try to find VRAM location * @adev: amdgpu device structure holding all necessary informations * @mc: memory controller structure holding memory informations * @base: base address at which to put VRAM @@ -543,7 +543,8 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) * Function will try to place VRAM at base address provided * as parameter. */ -void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) +void amdgpu_device_vram_location(struct amdgpu_device *adev, + struct amdgpu_mc *mc, u64 base) { uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; @@ -557,7 +558,7 @@ void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 } /** - * amdgpu_gart_location - try to find GTT location + * amdgpu_device_gart_location - try to find GTT location * @adev: amdgpu device structure holding all necessary informations * @mc: memory controller structure holding memory informations * @@ -568,7 +569,8 @@ void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 * * FIXME: when reducing GTT size align new size on power of 2. */ -void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) +void amdgpu_device_gart_location(struct amdgpu_device *adev, + struct amdgpu_mc *mc) { u64 size_af, size_bf; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 279f43a2b1a4..e1a73c43f32d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -222,8 +222,8 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - amdgpu_vram_location(adev, &adev->mc, base); - amdgpu_gart_location(adev, mc); + amdgpu_device_vram_location(adev, &adev->mc, base); + amdgpu_device_gart_location(adev, mc); } static void gmc_v6_0_mc_program(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index c4285395b5fe..356a9a71b8cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -240,8 +240,8 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - amdgpu_vram_location(adev, &adev->mc, base); - amdgpu_gart_location(adev, mc); + amdgpu_device_vram_location(adev, &adev->mc, base); + amdgpu_device_gart_location(adev, mc); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 6641276ecbdf..fce45578f5fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -405,8 +405,8 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - amdgpu_vram_location(adev, &adev->mc, base); - amdgpu_gart_location(adev, mc); + amdgpu_device_vram_location(adev, &adev->mc, base); + amdgpu_device_gart_location(adev, mc); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 899ffe50cb50..3c84f82687f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -638,8 +638,8 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, u64 base = 0; if (!amdgpu_sriov_vf(adev)) base = mmhub_v1_0_get_fb_location(adev); - amdgpu_vram_location(adev, &adev->mc, base); - amdgpu_gart_location(adev, mc); + amdgpu_device_vram_location(adev, &adev->mc, base); + amdgpu_device_gart_location(adev, mc); /* base offset of vram pages */ if (adev->flags & AMD_IS_APU) adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); -- GitLab From f5ec697e37023ce60dc1c38bf6b2bf32de767376 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 14 Dec 2017 16:39:02 -0500 Subject: [PATCH 1723/2547] drm/amdgpu: move fw_reserve functions to amdgpu_ttm.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's the only place they are used. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 95 --------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 99 +++++++++++++++++++++- 3 files changed, 97 insertions(+), 100 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ac21addcde7d..a8390abe13a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1387,9 +1387,6 @@ struct amdgpu_fw_vram_usage { void *va; }; -int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev); -void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev); - /* * CGS */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 09ffa9fbcd92..3135287c0f5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -597,101 +597,6 @@ void amdgpu_device_gart_location(struct amdgpu_device *adev, mc->gart_size >> 20, mc->gart_start, mc->gart_end); } -/* - * Firmware Reservation functions - */ -/** - * amdgpu_fw_reserve_vram_fini - free fw reserved vram - * - * @adev: amdgpu_device pointer - * - * free fw reserved vram if it has been reserved. - */ -void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev) -{ - amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo, - NULL, &adev->fw_vram_usage.va); -} - -/** - * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw - * - * @adev: amdgpu_device pointer - * - * create bo vram reservation from fw. - */ -int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) -{ - struct ttm_operation_ctx ctx = { false, false }; - int r = 0; - int i; - u64 vram_size = adev->mc.visible_vram_size; - u64 offset = adev->fw_vram_usage.start_offset; - u64 size = adev->fw_vram_usage.size; - struct amdgpu_bo *bo; - - adev->fw_vram_usage.va = NULL; - adev->fw_vram_usage.reserved_bo = NULL; - - if (adev->fw_vram_usage.size > 0 && - adev->fw_vram_usage.size <= vram_size) { - - r = amdgpu_bo_create(adev, adev->fw_vram_usage.size, - PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0, - &adev->fw_vram_usage.reserved_bo); - if (r) - goto error_create; - - r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false); - if (r) - goto error_reserve; - - /* remove the original mem node and create a new one at the - * request position - */ - bo = adev->fw_vram_usage.reserved_bo; - offset = ALIGN(offset, PAGE_SIZE); - for (i = 0; i < bo->placement.num_placement; ++i) { - bo->placements[i].fpfn = offset >> PAGE_SHIFT; - bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; - } - - ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem); - r = ttm_bo_mem_space(&bo->tbo, &bo->placement, - &bo->tbo.mem, &ctx); - if (r) - goto error_pin; - - r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo, - AMDGPU_GEM_DOMAIN_VRAM, - adev->fw_vram_usage.start_offset, - (adev->fw_vram_usage.start_offset + - adev->fw_vram_usage.size), NULL); - if (r) - goto error_pin; - r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo, - &adev->fw_vram_usage.va); - if (r) - goto error_kmap; - - amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo); - } - return r; - -error_kmap: - amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo); -error_pin: - amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo); -error_reserve: - amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo); -error_create: - adev->fw_vram_usage.va = NULL; - adev->fw_vram_usage.reserved_bo = NULL; - return r; -} - /** * amdgpu_device_resize_fb_bar - try to resize FB BAR * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index c307a7d2cf16..5b5554cba35f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1269,6 +1269,101 @@ static struct ttm_bo_driver amdgpu_bo_driver = { .access_memory = &amdgpu_ttm_access_memory }; +/* + * Firmware Reservation functions + */ +/** + * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram + * + * @adev: amdgpu_device pointer + * + * free fw reserved vram if it has been reserved. + */ +static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) +{ + amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo, + NULL, &adev->fw_vram_usage.va); +} + +/** + * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw + * + * @adev: amdgpu_device pointer + * + * create bo vram reservation from fw. + */ +static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) +{ + struct ttm_operation_ctx ctx = { false, false }; + int r = 0; + int i; + u64 vram_size = adev->mc.visible_vram_size; + u64 offset = adev->fw_vram_usage.start_offset; + u64 size = adev->fw_vram_usage.size; + struct amdgpu_bo *bo; + + adev->fw_vram_usage.va = NULL; + adev->fw_vram_usage.reserved_bo = NULL; + + if (adev->fw_vram_usage.size > 0 && + adev->fw_vram_usage.size <= vram_size) { + + r = amdgpu_bo_create(adev, adev->fw_vram_usage.size, + PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0, + &adev->fw_vram_usage.reserved_bo); + if (r) + goto error_create; + + r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false); + if (r) + goto error_reserve; + + /* remove the original mem node and create a new one at the + * request position + */ + bo = adev->fw_vram_usage.reserved_bo; + offset = ALIGN(offset, PAGE_SIZE); + for (i = 0; i < bo->placement.num_placement; ++i) { + bo->placements[i].fpfn = offset >> PAGE_SHIFT; + bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; + } + + ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem); + r = ttm_bo_mem_space(&bo->tbo, &bo->placement, + &bo->tbo.mem, &ctx); + if (r) + goto error_pin; + + r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo, + AMDGPU_GEM_DOMAIN_VRAM, + adev->fw_vram_usage.start_offset, + (adev->fw_vram_usage.start_offset + + adev->fw_vram_usage.size), NULL); + if (r) + goto error_pin; + r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo, + &adev->fw_vram_usage.va); + if (r) + goto error_kmap; + + amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo); + } + return r; + +error_kmap: + amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo); +error_pin: + amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo); +error_reserve: + amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo); +error_create: + adev->fw_vram_usage.va = NULL; + adev->fw_vram_usage.reserved_bo = NULL; + return r; +} + int amdgpu_ttm_init(struct amdgpu_device *adev) { uint64_t gtt_size; @@ -1311,7 +1406,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) *The reserved vram for firmware must be pinned to the specified *place on the VRAM, so reserve it early. */ - r = amdgpu_fw_reserve_vram_init(adev); + r = amdgpu_ttm_fw_reserve_vram_init(adev); if (r) { return r; } @@ -1395,7 +1490,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) amdgpu_ttm_debugfs_fini(adev); amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); - amdgpu_fw_reserve_vram_fini(adev); + amdgpu_ttm_fw_reserve_vram_fini(adev); ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); -- GitLab From 2990a1fc012e1bb4523a54d2c27eebc21a2c7e7e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 15 Dec 2017 16:18:00 -0500 Subject: [PATCH 1724/2547] drm/amdgpu: rename ip block helper functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add device to the name for consistency. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 38 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 18 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 18 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 16 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 8 +- drivers/gpu/drm/amd/amdgpu/cik.c | 88 +++++++------- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 18 +-- drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 8 +- drivers/gpu/drm/amd/amdgpu/si.c | 54 ++++----- drivers/gpu/drm/amd/amdgpu/soc15.c | 46 +++---- drivers/gpu/drm/amd/amdgpu/vi.c | 132 ++++++++++----------- 14 files changed, 252 insertions(+), 246 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index a8390abe13a6..5c016b3d494d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -224,17 +224,18 @@ enum amdgpu_kiq_irq { AMDGPU_CP_KIQ_IRQ_LAST }; -int amdgpu_set_clockgating_state(struct amdgpu_device *adev, - enum amd_ip_block_type block_type, - enum amd_clockgating_state state); -int amdgpu_set_powergating_state(struct amdgpu_device *adev, - enum amd_ip_block_type block_type, - enum amd_powergating_state state); -void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); -int amdgpu_wait_for_idle(struct amdgpu_device *adev, - enum amd_ip_block_type block_type); -bool amdgpu_is_idle(struct amdgpu_device *adev, - enum amd_ip_block_type block_type); +int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev, + enum amd_ip_block_type block_type, + enum amd_clockgating_state state); +int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev, + enum amd_ip_block_type block_type, + enum amd_powergating_state state); +void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, + u32 *flags); +int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, + enum amd_ip_block_type block_type); +bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, + enum amd_ip_block_type block_type); #define AMDGPU_MAX_IP_NUM 16 @@ -259,15 +260,16 @@ struct amdgpu_ip_block { const struct amdgpu_ip_block_version *version; }; -int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, - enum amd_ip_block_type type, - u32 major, u32 minor); +int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, + enum amd_ip_block_type type, + u32 major, u32 minor); -struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, - enum amd_ip_block_type type); +struct amdgpu_ip_block * +amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, + enum amd_ip_block_type type); -int amdgpu_ip_block_add(struct amdgpu_device *adev, - const struct amdgpu_ip_block_version *ip_block_version); +int amdgpu_device_ip_block_add(struct amdgpu_device *adev, + const struct amdgpu_ip_block_version *ip_block_version); /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ struct amdgpu_buffer_funcs { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index c04f44a90392..a29362f9ef41 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -277,7 +277,7 @@ static int acp_hw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; const struct amdgpu_ip_block *ip_block = - amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); + amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); if (!ip_block) return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 3135287c0f5b..38e14525721c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -937,9 +937,9 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { .can_switch = amdgpu_switcheroo_can_switch, }; -int amdgpu_set_clockgating_state(struct amdgpu_device *adev, - enum amd_ip_block_type block_type, - enum amd_clockgating_state state) +int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev, + enum amd_ip_block_type block_type, + enum amd_clockgating_state state) { int i, r = 0; @@ -959,9 +959,9 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev, return r; } -int amdgpu_set_powergating_state(struct amdgpu_device *adev, - enum amd_ip_block_type block_type, - enum amd_powergating_state state) +int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev, + enum amd_ip_block_type block_type, + enum amd_powergating_state state) { int i, r = 0; @@ -981,7 +981,8 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev, return r; } -void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) +void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, + u32 *flags) { int i; @@ -993,8 +994,8 @@ void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) } } -int amdgpu_wait_for_idle(struct amdgpu_device *adev, - enum amd_ip_block_type block_type) +int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, + enum amd_ip_block_type block_type) { int i, r; @@ -1012,8 +1013,8 @@ int amdgpu_wait_for_idle(struct amdgpu_device *adev, } -bool amdgpu_is_idle(struct amdgpu_device *adev, - enum amd_ip_block_type block_type) +bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, + enum amd_ip_block_type block_type) { int i; @@ -1027,8 +1028,9 @@ bool amdgpu_is_idle(struct amdgpu_device *adev, } -struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, - enum amd_ip_block_type type) +struct amdgpu_ip_block * +amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, + enum amd_ip_block_type type) { int i; @@ -1040,7 +1042,7 @@ struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, } /** - * amdgpu_ip_block_version_cmp + * amdgpu_device_ip_block_version_cmp * * @adev: amdgpu_device pointer * @type: enum amd_ip_block_type @@ -1050,11 +1052,11 @@ struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, * return 0 if equal or greater * return 1 if smaller or the ip_block doesn't exist */ -int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, - enum amd_ip_block_type type, - u32 major, u32 minor) +int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, + enum amd_ip_block_type type, + u32 major, u32 minor) { - struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); + struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); if (ip_block && ((ip_block->version->major > major) || ((ip_block->version->major == major) && @@ -1065,7 +1067,7 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, } /** - * amdgpu_ip_block_add + * amdgpu_device_ip_block_add * * @adev: amdgpu_device pointer * @ip_block_version: pointer to the IP to add @@ -1073,8 +1075,8 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, * Adds the IP block driver information to the collection of IPs * on the asic. */ -int amdgpu_ip_block_add(struct amdgpu_device *adev, - const struct amdgpu_ip_block_version *ip_block_version) +int amdgpu_device_ip_block_add(struct amdgpu_device *adev, + const struct amdgpu_ip_block_version *ip_block_version) { if (!ip_block_version) return -EINVAL; @@ -1569,10 +1571,10 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev) amdgpu_virt_request_full_gpu(adev, false); /* ungate SMC block first */ - r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, - AMD_CG_STATE_UNGATE); + r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, + AMD_CG_STATE_UNGATE); if (r) { - DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); + DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r); } for (i = adev->num_ip_blocks - 1; i >= 0; i--) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 83205b93e62d..01a996c6b802 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -1278,16 +1278,16 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) /* XXX select vce level based on ring/task */ adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; mutex_unlock(&adev->pm.mutex); - amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, - AMD_CG_STATE_UNGATE); - amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, - AMD_PG_STATE_UNGATE); + amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_CG_STATE_UNGATE); + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_PG_STATE_UNGATE); amdgpu_pm_compute_clocks(adev); } else { - amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, - AMD_PG_STATE_GATE); - amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, - AMD_CG_STATE_GATE); + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_PG_STATE_GATE); + amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_CG_STATE_GATE); mutex_lock(&adev->pm.mutex); adev->pm.dpm.vce_active = false; mutex_unlock(&adev->pm.mutex); @@ -1584,7 +1584,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) struct drm_device *ddev = adev->ddev; u32 flags = 0; - amdgpu_get_clockgating_state(adev, &flags); + amdgpu_device_ip_get_clockgating_state(adev, &flags); seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags); amdgpu_parse_cg_state(m, flags); seq_printf(m, "\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 916e51670bfd..bd6d3a1c1d65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -244,7 +244,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) } /* from uvd v5.0 HW addressing capacity increased to 64 bits */ - if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) + if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) adev->uvd.address_64_bit = true; switch (adev->asic_type) { @@ -1153,10 +1153,10 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work) } else { amdgpu_asic_set_uvd_clocks(adev, 0, 0); /* shutdown the UVD block */ - amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_GATE); - amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_GATE); + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_GATE); + amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_CG_STATE_GATE); } } else { schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); @@ -1176,10 +1176,10 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) amdgpu_dpm_enable_uvd(adev, true); } else { amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); - amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); - amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_UNGATE); + amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_CG_STATE_UNGATE); + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_UNGATE); } } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 641deb0527ae..9857d482c942 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -311,10 +311,10 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work) amdgpu_dpm_enable_vce(adev, false); } else { amdgpu_asic_set_vce_clocks(adev, 0, 0); - amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, - AMD_PG_STATE_GATE); - amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, - AMD_CG_STATE_GATE); + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_PG_STATE_GATE); + amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_CG_STATE_GATE); } } else { schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT); @@ -343,10 +343,10 @@ void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring) amdgpu_dpm_enable_vce(adev, true); } else { amdgpu_asic_set_vce_clocks(adev, 53300, 40000); - amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, - AMD_CG_STATE_UNGATE); - amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, - AMD_PG_STATE_UNGATE); + amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_CG_STATE_UNGATE); + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_PG_STATE_UNGATE); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 564e1b1962f1..398abbcbf029 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -741,7 +741,7 @@ void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) has_compute_vm_bug = false; - ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); if (ip_block) { /* Compute has a VM bug for GFX version < 7. Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index f11c0aacf19f..a0943aa8d1d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -891,12 +891,12 @@ static void ci_dpm_powergate_uvd(void *handle, bool gate) if (gate) { /* stop the UVD block */ - amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_GATE); + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_GATE); ci_update_uvd_dpm(adev, gate); } else { - amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_UNGATE); + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_UNGATE); ci_update_uvd_dpm(adev, gate); } } diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 132ba226f289..6a92abc736e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1974,77 +1974,77 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_BONAIRE: - amdgpu_ip_block_add(adev, &cik_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); - amdgpu_ip_block_add(adev, &cik_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &cik_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block); + amdgpu_device_ip_block_add(adev, &cik_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) - amdgpu_ip_block_add(adev, &dm_ip_block); + amdgpu_device_ip_block_add(adev, &dm_ip_block); #endif else - amdgpu_ip_block_add(adev, &dce_v8_2_ip_block); - amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block); - amdgpu_ip_block_add(adev, &cik_sdma_ip_block); - amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); - amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); + amdgpu_device_ip_block_add(adev, &dce_v8_2_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block); + amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block); + amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block); + amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block); break; case CHIP_HAWAII: - amdgpu_ip_block_add(adev, &cik_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); - amdgpu_ip_block_add(adev, &cik_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &cik_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block); + amdgpu_device_ip_block_add(adev, &cik_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) - amdgpu_ip_block_add(adev, &dm_ip_block); + amdgpu_device_ip_block_add(adev, &dm_ip_block); #endif else - amdgpu_ip_block_add(adev, &dce_v8_5_ip_block); - amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block); - amdgpu_ip_block_add(adev, &cik_sdma_ip_block); - amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); - amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); + amdgpu_device_ip_block_add(adev, &dce_v8_5_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block); + amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block); + amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block); + amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block); break; case CHIP_KAVERI: - amdgpu_ip_block_add(adev, &cik_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); - amdgpu_ip_block_add(adev, &cik_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &cik_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block); + amdgpu_device_ip_block_add(adev, &cik_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) - amdgpu_ip_block_add(adev, &dm_ip_block); + amdgpu_device_ip_block_add(adev, &dm_ip_block); #endif else - amdgpu_ip_block_add(adev, &dce_v8_1_ip_block); - amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block); - amdgpu_ip_block_add(adev, &cik_sdma_ip_block); - amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); - amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); + amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block); + amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block); + amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block); + amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block); break; case CHIP_KABINI: case CHIP_MULLINS: - amdgpu_ip_block_add(adev, &cik_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); - amdgpu_ip_block_add(adev, &cik_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &cik_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block); + amdgpu_device_ip_block_add(adev, &cik_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) - amdgpu_ip_block_add(adev, &dm_ip_block); + amdgpu_device_ip_block_add(adev, &dm_ip_block); #endif else - amdgpu_ip_block_add(adev, &dce_v8_3_ip_block); - amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block); - amdgpu_ip_block_add(adev, &cik_sdma_ip_block); - amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); - amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); + amdgpu_device_ip_block_add(adev, &dce_v8_3_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block); + amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block); + amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block); + amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block); break; default: /* FIXME: not supported yet */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 4a9c28cd144d..46550b588982 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5062,8 +5062,9 @@ static int gfx_v8_0_hw_fini(void *handle) gfx_v8_0_cp_enable(adev, false); gfx_v8_0_rlc_stop(adev); - amdgpu_set_powergating_state(adev, - AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE); + amdgpu_device_ip_set_powergating_state(adev, + AMD_IP_BLOCK_TYPE_GFX, + AMD_PG_STATE_UNGATE); return 0; } @@ -5480,8 +5481,9 @@ static int gfx_v8_0_late_init(void *handle) if (r) return r; - amdgpu_set_powergating_state(adev, - AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE); + amdgpu_device_ip_set_powergating_state(adev, + AMD_IP_BLOCK_TYPE_GFX, + AMD_PG_STATE_GATE); return 0; } @@ -5492,10 +5494,10 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade if ((adev->asic_type == CHIP_POLARIS11) || (adev->asic_type == CHIP_POLARIS12)) /* Send msg to SMU via Powerplay */ - amdgpu_set_powergating_state(adev, - AMD_IP_BLOCK_TYPE_SMC, - enable ? - AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE); + amdgpu_device_ip_set_powergating_state(adev, + AMD_IP_BLOCK_TYPE_SMC, + enable ? + AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE); WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c index f33d1ffdb20b..d9e9e52a0def 100644 --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c @@ -1682,8 +1682,8 @@ static void kv_dpm_powergate_uvd(void *handle, bool gate) if (gate) { /* stop the UVD block */ - ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_GATE); + ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_GATE); kv_update_uvd_dpm(adev, gate); if (pi->caps_uvd_pg) /* power off the UVD block */ @@ -1695,8 +1695,8 @@ static void kv_dpm_powergate_uvd(void *handle, bool gate) /* re-init the UVD block */ kv_update_uvd_dpm(adev, gate); - ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_UNGATE); + ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_UNGATE); } } diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 78baddb5d300..543101d5a5ed 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1959,42 +1959,42 @@ int si_set_ip_blocks(struct amdgpu_device *adev) case CHIP_VERDE: case CHIP_TAHITI: case CHIP_PITCAIRN: - amdgpu_ip_block_add(adev, &si_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); - amdgpu_ip_block_add(adev, &si_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &si_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); + amdgpu_device_ip_block_add(adev, &si_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); else - amdgpu_ip_block_add(adev, &dce_v6_0_ip_block); - amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); - amdgpu_ip_block_add(adev, &si_dma_ip_block); - /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */ - /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */ + amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); + amdgpu_device_ip_block_add(adev, &si_dma_ip_block); + /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */ + /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */ break; case CHIP_OLAND: - amdgpu_ip_block_add(adev, &si_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); - amdgpu_ip_block_add(adev, &si_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &si_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); + amdgpu_device_ip_block_add(adev, &si_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); else - amdgpu_ip_block_add(adev, &dce_v6_4_ip_block); - amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); - amdgpu_ip_block_add(adev, &si_dma_ip_block); - /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */ - /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */ + amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); + amdgpu_device_ip_block_add(adev, &si_dma_ip_block); + /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */ + /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */ break; case CHIP_HAINAN: - amdgpu_ip_block_add(adev, &si_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); - amdgpu_ip_block_add(adev, &si_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &si_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); + amdgpu_device_ip_block_add(adev, &si_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); - amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); - amdgpu_ip_block_add(adev, &si_dma_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); + amdgpu_device_ip_block_add(adev, &si_dma_ip_block); break; default: BUG(); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 49ff552cd6fe..f0fb4161e866 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -533,43 +533,43 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_VEGA10: - amdgpu_ip_block_add(adev, &vega10_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); - amdgpu_ip_block_add(adev, &vega10_ih_ip_block); + amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); + amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1) - amdgpu_ip_block_add(adev, &psp_v3_1_ip_block); + amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); if (!amdgpu_sriov_vf(adev)) - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) - amdgpu_ip_block_add(adev, &dm_ip_block); + amdgpu_device_ip_block_add(adev, &dm_ip_block); #else # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." #endif - amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); - amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); - amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block); - amdgpu_ip_block_add(adev, &vce_v4_0_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); + amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); + amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); break; case CHIP_RAVEN: - amdgpu_ip_block_add(adev, &vega10_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); - amdgpu_ip_block_add(adev, &vega10_ih_ip_block); - amdgpu_ip_block_add(adev, &psp_v10_0_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); + amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); + amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) - amdgpu_ip_block_add(adev, &dm_ip_block); + amdgpu_device_ip_block_add(adev, &dm_ip_block); #else # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." #endif - amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); - amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); - amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); + amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); break; default: return -EINVAL; @@ -616,8 +616,8 @@ static int soc15_common_early_init(void *handle) adev->asic_funcs = &soc15_asic_funcs; - if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && - (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) + if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && + (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) psp_enabled = true; adev->rev_id = soc15_get_rev_id(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 0e1202914fa8..66072063bc7c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -891,8 +891,8 @@ static int vi_common_early_init(void *handle) adev->asic_funcs = &vi_asic_funcs; - if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) && - (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC))) + if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) && + (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC))) smc_enabled = true; adev->rev_id = vi_get_rev_id(adev); @@ -1487,115 +1487,115 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_TOPAZ: /* topaz has no DCE, UVD, VCE */ - amdgpu_ip_block_add(adev, &vi_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block); - amdgpu_ip_block_add(adev, &iceland_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &vi_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block); + amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); - amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); - amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block); break; case CHIP_FIJI: - amdgpu_ip_block_add(adev, &vi_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block); - amdgpu_ip_block_add(adev, &tonga_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &vi_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block); + amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) - amdgpu_ip_block_add(adev, &dm_ip_block); + amdgpu_device_ip_block_add(adev, &dm_ip_block); #endif else - amdgpu_ip_block_add(adev, &dce_v10_1_ip_block); - amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); - amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); + amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); if (!amdgpu_sriov_vf(adev)) { - amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); - amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); + amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); + amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); } break; case CHIP_TONGA: - amdgpu_ip_block_add(adev, &vi_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); - amdgpu_ip_block_add(adev, &tonga_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &vi_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); + amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) - amdgpu_ip_block_add(adev, &dm_ip_block); + amdgpu_device_ip_block_add(adev, &dm_ip_block); #endif else - amdgpu_ip_block_add(adev, &dce_v10_0_ip_block); - amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); - amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); + amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); if (!amdgpu_sriov_vf(adev)) { - amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block); - amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); + amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block); + amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); } break; case CHIP_POLARIS11: case CHIP_POLARIS10: case CHIP_POLARIS12: - amdgpu_ip_block_add(adev, &vi_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block); - amdgpu_ip_block_add(adev, &tonga_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &vi_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block); + amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) - amdgpu_ip_block_add(adev, &dm_ip_block); + amdgpu_device_ip_block_add(adev, &dm_ip_block); #endif else - amdgpu_ip_block_add(adev, &dce_v11_2_ip_block); - amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); - amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block); - amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block); - amdgpu_ip_block_add(adev, &vce_v3_4_ip_block); + amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block); + amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); + amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); break; case CHIP_CARRIZO: - amdgpu_ip_block_add(adev, &vi_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); - amdgpu_ip_block_add(adev, &cz_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &vi_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); + amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) - amdgpu_ip_block_add(adev, &dm_ip_block); + amdgpu_device_ip_block_add(adev, &dm_ip_block); #endif else - amdgpu_ip_block_add(adev, &dce_v11_0_ip_block); - amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); - amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); - amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); - amdgpu_ip_block_add(adev, &vce_v3_1_ip_block); + amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); + amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); + amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block); #if defined(CONFIG_DRM_AMD_ACP) - amdgpu_ip_block_add(adev, &acp_ip_block); + amdgpu_device_ip_block_add(adev, &acp_ip_block); #endif break; case CHIP_STONEY: - amdgpu_ip_block_add(adev, &vi_common_ip_block); - amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); - amdgpu_ip_block_add(adev, &cz_ih_ip_block); - amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + amdgpu_device_ip_block_add(adev, &vi_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); + amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); + amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display) - amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) - amdgpu_ip_block_add(adev, &dm_ip_block); + amdgpu_device_ip_block_add(adev, &dm_ip_block); #endif else - amdgpu_ip_block_add(adev, &dce_v11_0_ip_block); - amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block); - amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); - amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block); - amdgpu_ip_block_add(adev, &vce_v3_4_ip_block); + amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); + amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block); + amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); #if defined(CONFIG_DRM_AMD_ACP) - amdgpu_ip_block_add(adev, &acp_ip_block); + amdgpu_device_ip_block_add(adev, &acp_ip_block); #endif break; default: -- GitLab From 39c640c086ad12005e88cf6f9de03c32111ef081 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 15 Dec 2017 16:22:11 -0500 Subject: [PATCH 1725/2547] drm/amdgpu: rename amdgpu_need_post MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add device to the name for consistency. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 5c016b3d494d..149ed8a67664 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1893,7 +1893,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job, bool force); bool amdgpu_need_backup(struct amdgpu_device *adev); void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); -bool amdgpu_need_post(struct amdgpu_device *adev); +bool amdgpu_device_need_post(struct amdgpu_device *adev); void amdgpu_update_display_priority(struct amdgpu_device *adev); void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 057e1ecd83ce..a5df80d50d44 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -93,7 +93,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev) resource_size_t size = 256 * 1024; /* ??? */ if (!(adev->flags & AMD_IS_APU)) - if (amdgpu_need_post(adev)) + if (amdgpu_device_need_post(adev)) return false; adev->bios = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 38e14525721c..8cc3dcf120d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -671,7 +671,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) * GPU helpers function. */ /** - * amdgpu_need_post - check if the hw need post or not + * amdgpu_device_need_post - check if the hw need post or not * * @adev: amdgpu_device pointer * @@ -679,7 +679,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) * or post is needed if hw reset is performed. * Returns true if need or false if not. */ -bool amdgpu_need_post(struct amdgpu_device *adev) +bool amdgpu_device_need_post(struct amdgpu_device *adev) { uint32_t reg; @@ -1946,7 +1946,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_device_detect_sriov_bios(adev); /* Post card if necessary */ - if (amdgpu_need_post(adev)) { + if (amdgpu_device_need_post(adev)) { if (!adev->bios) { dev_err(adev->dev, "no vBIOS found\n"); r = -EINVAL; @@ -2275,7 +2275,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) } /* post card */ - if (amdgpu_need_post(adev)) { + if (amdgpu_device_need_post(adev)) { r = amdgpu_atom_asic_init(adev->mode_info.atom_context); if (r) DRM_ERROR("amdgpu asic init failed\n"); -- GitLab From 55e0037aab6503453eef663eded60e530896eaef Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 15 Dec 2017 16:28:33 -0500 Subject: [PATCH 1726/2547] drm/amdgpu: move dummy page functions to amdgpu_gart.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's the only place they are used. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 -- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 45 -------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 49 +++++++++++++++++++++- 3 files changed, 47 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 149ed8a67664..d4abb7f04a86 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -377,9 +377,6 @@ struct amdgpu_dummy_page { struct page *page; dma_addr_t addr; }; -int amdgpu_dummy_page_init(struct amdgpu_device *adev); -void amdgpu_dummy_page_fini(struct amdgpu_device *adev); - /* * Clocks diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 8cc3dcf120d0..0080776c4936 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -724,51 +724,6 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev) return true; } -/** - * amdgpu_dummy_page_init - init dummy page used by the driver - * - * @adev: amdgpu_device pointer - * - * Allocate the dummy page used by the driver (all asics). - * This dummy page is used by the driver as a filler for gart entries - * when pages are taken out of the GART - * Returns 0 on sucess, -ENOMEM on failure. - */ -int amdgpu_dummy_page_init(struct amdgpu_device *adev) -{ - if (adev->dummy_page.page) - return 0; - adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); - if (adev->dummy_page.page == NULL) - return -ENOMEM; - adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, - 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); - if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { - dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); - __free_page(adev->dummy_page.page); - adev->dummy_page.page = NULL; - return -ENOMEM; - } - return 0; -} - -/** - * amdgpu_dummy_page_fini - free dummy page used by the driver - * - * @adev: amdgpu_device pointer - * - * Frees the dummy page used by the driver (all asics). - */ -void amdgpu_dummy_page_fini(struct amdgpu_device *adev) -{ - if (adev->dummy_page.page == NULL) - return; - pci_unmap_page(adev->pdev, adev->dummy_page.addr, - PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); - __free_page(adev->dummy_page.page); - adev->dummy_page.page = NULL; -} - /* if we get transitioned to only one device, take VGA back */ /** * amdgpu_device_vga_set_decode - enable/disable vga decode diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 1f51897acc5b..0a4f34afaaaa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -56,6 +56,51 @@ * Common GART table functions. */ +/** + * amdgpu_dummy_page_init - init dummy page used by the driver + * + * @adev: amdgpu_device pointer + * + * Allocate the dummy page used by the driver (all asics). + * This dummy page is used by the driver as a filler for gart entries + * when pages are taken out of the GART + * Returns 0 on sucess, -ENOMEM on failure. + */ +static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) +{ + if (adev->dummy_page.page) + return 0; + adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); + if (adev->dummy_page.page == NULL) + return -ENOMEM; + adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, + 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { + dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); + __free_page(adev->dummy_page.page); + adev->dummy_page.page = NULL; + return -ENOMEM; + } + return 0; +} + +/** + * amdgpu_dummy_page_fini - free dummy page used by the driver + * + * @adev: amdgpu_device pointer + * + * Frees the dummy page used by the driver (all asics). + */ +static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) +{ + if (adev->dummy_page.page == NULL) + return; + pci_unmap_page(adev->pdev, adev->dummy_page.addr, + PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + __free_page(adev->dummy_page.page); + adev->dummy_page.page = NULL; +} + /** * amdgpu_gart_table_vram_alloc - allocate vram for gart page table * @@ -308,7 +353,7 @@ int amdgpu_gart_init(struct amdgpu_device *adev) DRM_ERROR("Page size is smaller than GPU page size!\n"); return -EINVAL; } - r = amdgpu_dummy_page_init(adev); + r = amdgpu_gart_dummy_page_init(adev); if (r) return r; /* Compute table size */ @@ -340,5 +385,5 @@ void amdgpu_gart_fini(struct amdgpu_device *adev) vfree(adev->gart.pages); adev->gart.pages = NULL; #endif - amdgpu_dummy_page_fini(adev); + amdgpu_gart_dummy_page_fini(adev); } -- GitLab From 5f152b5e69a5392181b0a84bd55fe17a417364ac Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 15 Dec 2017 16:40:49 -0500 Subject: [PATCH 1727/2547] drm/amdgpu: rename amdgpu_gpu_recover MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add device to the name for consistency. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 2 +- drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +- 7 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index d4abb7f04a86..04e5498929c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1887,7 +1887,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) /* Common functions */ -int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job, bool force); +int amdgpu_device_gpu_recover(struct amdgpu_device *adev, + struct amdgpu_job* job, bool force); bool amdgpu_need_backup(struct amdgpu_device *adev); void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); bool amdgpu_device_need_post(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0080776c4936..cfeceab29224 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2611,7 +2611,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, } /** - * amdgpu_gpu_recover - reset the asic and recover scheduler + * amdgpu_device_gpu_recover - reset the asic and recover scheduler * * @adev: amdgpu device pointer * @job: which job trigger hang @@ -2620,7 +2620,8 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, * Attempt to reset the GPU if it has hung (all asics). * Returns 0 for success or an error on failure. */ -int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job, bool force) +int amdgpu_device_gpu_recover(struct amdgpu_device *adev, + struct amdgpu_job *job, bool force) { struct drm_atomic_state *state = NULL; uint64_t reset_flags = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index da1510f65ee0..008e1984b7e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -693,7 +693,7 @@ static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) struct amdgpu_device *adev = dev->dev_private; seq_printf(m, "gpu recover\n"); - amdgpu_gpu_recover(adev, NULL, true); + amdgpu_device_gpu_recover(adev, NULL, true); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index c43643e8c8c8..56bcd59c3399 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -88,7 +88,7 @@ static void amdgpu_irq_reset_work_func(struct work_struct *work) reset_work); if (!amdgpu_sriov_vf(adev)) - amdgpu_gpu_recover(adev, NULL, false); + amdgpu_device_gpu_recover(adev, NULL, false); } /* Disable *all* interrupts */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index be8a437fad54..56d9ee5013a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -37,7 +37,7 @@ static void amdgpu_job_timedout(struct drm_sched_job *s_job) atomic_read(&job->ring->fence_drv.last_seq), job->ring->fence_drv.sync_seq); - amdgpu_gpu_recover(job->adev, job, false); + amdgpu_device_gpu_recover(job->adev, job, false); } int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index 43e74ec93147..271452d3999a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -253,7 +253,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) } /* Trigger recovery due to world switch failure */ - amdgpu_gpu_recover(adev, NULL, false); + amdgpu_device_gpu_recover(adev, NULL, false); } static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index af2d47e9abdc..9fc1c37344ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -521,7 +521,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work) } /* Trigger recovery due to world switch failure */ - amdgpu_gpu_recover(adev, NULL, false); + amdgpu_device_gpu_recover(adev, NULL, false); } static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev, -- GitLab From 6b8f4ee56fb27ac36fb3dbec91b5eb04beb90287 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 15 Dec 2017 16:45:02 -0500 Subject: [PATCH 1728/2547] drm/amdgpu: move amdgpu_need_backup to amdgpu_object.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's the only place it's used. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 -------- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 ++++++++ 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 04e5498929c3..91b4fda42873 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1889,7 +1889,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) /* Common functions */ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job, bool force); -bool amdgpu_need_backup(struct amdgpu_device *adev); void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); bool amdgpu_device_need_post(struct amdgpu_device *adev); void amdgpu_update_display_priority(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index cfeceab29224..f80081ecb02c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2425,14 +2425,6 @@ static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) return 0; } -bool amdgpu_need_backup(struct amdgpu_device *adev) -{ - if (adev->flags & AMD_IS_APU) - return false; - - return amdgpu_gpu_recovery; -} - static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev, struct amdgpu_ring *ring, struct amdgpu_bo *bo, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 86340cfa6be7..4feee9927bce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -37,6 +37,14 @@ #include "amdgpu.h" #include "amdgpu_trace.h" +static bool amdgpu_need_backup(struct amdgpu_device *adev) +{ + if (adev->flags & AMD_IS_APU) + return false; + + return amdgpu_gpu_recovery; +} + static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) { struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); -- GitLab From 041d9d93b5dba8fa41134a4e5fc7a432b76fa308 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 15 Dec 2017 16:49:33 -0500 Subject: [PATCH 1729/2547] drm/amdgpu: rename amdgpu_get_pcie_info MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add device to the name for consistency. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +- drivers/gpu/drm/amd/amdgpu/vi.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 91b4fda42873..6b296e1fecf2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1167,7 +1167,7 @@ struct amdgpu_wb { int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); -void amdgpu_get_pcie_info(struct amdgpu_device *adev); +void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); /* * SDMA diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index f80081ecb02c..357cd8bf2e55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2749,7 +2749,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, return r; } -void amdgpu_get_pcie_info(struct amdgpu_device *adev) +void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) { u32 mask; int ret; diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 6a92abc736e0..8e59e65efd44 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1866,7 +1866,7 @@ static int cik_common_early_init(void *handle) adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); - amdgpu_get_pcie_info(adev); + amdgpu_device_get_pcie_info(adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index f0fb4161e866..8f2cff7b7e0c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -682,7 +682,7 @@ static int soc15_common_early_init(void *handle) adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); - amdgpu_get_pcie_info(adev); + amdgpu_device_get_pcie_info(adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 66072063bc7c..d9bb26322850 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1074,7 +1074,7 @@ static int vi_common_early_init(void *handle) /* vi use smc load by default */ adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); - amdgpu_get_pcie_info(adev); + amdgpu_device_get_pcie_info(adev); return 0; } -- GitLab From 3c2d06714d6e083eba94a1a4e865f6acb98ef611 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 18 Dec 2017 15:19:58 +0000 Subject: [PATCH 1730/2547] drm/i915: reorder field in gem_request tracepoints Let's make the order of the fields of the tracepoints involving gem request match across i915. This makes userspace processing of tracepoint a bit easier. Suggested-by: Chris Wilson Signed-off-by: Lionel Landwerlin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171218151959.14073-2-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/i915_trace.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index 4e76768ffa95..321f74bae0e1 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -641,8 +641,8 @@ DECLARE_EVENT_CLASS(i915_gem_request, TP_STRUCT__entry( __field(u32, dev) - __field(u32, ctx) __field(u32, ring) + __field(u32, ctx) __field(u32, seqno) __field(u32, global) ), @@ -684,9 +684,9 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw, TP_STRUCT__entry( __field(u32, dev) __field(u32, ring) + __field(u32, ctx) __field(u32, seqno) __field(u32, global_seqno) - __field(u32, ctx) __field(u32, port) ), -- GitLab From 151a99ec771c49fbfaa785e2e2bc3672641f2076 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 18 Dec 2017 15:19:59 +0000 Subject: [PATCH 1731/2547] drm/i915/trace: add hw_id to gem requests trace points When monitoring the GPU with i915 perf, reports are tagged with a hw id. Gem context creation tracepoints already have a hw_id field, unfortunately you only get this correlation between a process id and a hw context id once when the context is created. It doesn't help if you started monitoring after the process was initialized or if the drm fd was transfered from one process to another. This change adds the hw_id field to gem requests, so that correlation can also be done on submission. v2: Place hw_id at the end of the tracepoint to not disrupt too much existing tools (Chris) v3: Reorder hw_id field again (Chris) v4: Add missing hw_id to i915_gem_request_wait_begin tracepoint (Chris) Signed-off-by: Lionel Landwerlin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171218151959.14073-3-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/i915_trace.h | 36 +++++++++++++++++++------------ 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index 321f74bae0e1..e1169c02eb2b 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -616,6 +616,7 @@ TRACE_EVENT(i915_gem_request_queue, TP_STRUCT__entry( __field(u32, dev) + __field(u32, hw_id) __field(u32, ring) __field(u32, ctx) __field(u32, seqno) @@ -624,15 +625,16 @@ TRACE_EVENT(i915_gem_request_queue, TP_fast_assign( __entry->dev = req->i915->drm.primary->index; + __entry->hw_id = req->ctx->hw_id; __entry->ring = req->engine->id; __entry->ctx = req->fence.context; __entry->seqno = req->fence.seqno; __entry->flags = flags; ), - TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, flags=0x%x", - __entry->dev, __entry->ring, __entry->ctx, __entry->seqno, - __entry->flags) + TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, flags=0x%x", + __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx, + __entry->seqno, __entry->flags) ); DECLARE_EVENT_CLASS(i915_gem_request, @@ -641,6 +643,7 @@ DECLARE_EVENT_CLASS(i915_gem_request, TP_STRUCT__entry( __field(u32, dev) + __field(u32, hw_id) __field(u32, ring) __field(u32, ctx) __field(u32, seqno) @@ -649,15 +652,16 @@ DECLARE_EVENT_CLASS(i915_gem_request, TP_fast_assign( __entry->dev = req->i915->drm.primary->index; + __entry->hw_id = req->ctx->hw_id; __entry->ring = req->engine->id; __entry->ctx = req->fence.context; __entry->seqno = req->fence.seqno; __entry->global = req->global_seqno; ), - TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u", - __entry->dev, __entry->ring, __entry->ctx, __entry->seqno, - __entry->global) + TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, global=%u", + __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx, + __entry->seqno, __entry->global) ); DEFINE_EVENT(i915_gem_request, i915_gem_request_add, @@ -683,6 +687,7 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw, TP_STRUCT__entry( __field(u32, dev) + __field(u32, hw_id) __field(u32, ring) __field(u32, ctx) __field(u32, seqno) @@ -692,6 +697,7 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw, TP_fast_assign( __entry->dev = req->i915->drm.primary->index; + __entry->hw_id = req->ctx->hw_id; __entry->ring = req->engine->id; __entry->ctx = req->fence.context; __entry->seqno = req->fence.seqno; @@ -699,10 +705,10 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw, __entry->port = port; ), - TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u, port=%u", - __entry->dev, __entry->ring, __entry->ctx, - __entry->seqno, __entry->global_seqno, - __entry->port) + TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, global=%u, port=%u", + __entry->dev, __entry->hw_id, __entry->ring, + __entry->ctx, __entry->seqno, + __entry->global_seqno, __entry->port) ); DEFINE_EVENT(i915_gem_request_hw, i915_gem_request_in, @@ -772,6 +778,7 @@ TRACE_EVENT(i915_gem_request_wait_begin, TP_STRUCT__entry( __field(u32, dev) + __field(u32, hw_id) __field(u32, ring) __field(u32, ctx) __field(u32, seqno) @@ -787,6 +794,7 @@ TRACE_EVENT(i915_gem_request_wait_begin, */ TP_fast_assign( __entry->dev = req->i915->drm.primary->index; + __entry->hw_id = req->ctx->hw_id; __entry->ring = req->engine->id; __entry->ctx = req->fence.context; __entry->seqno = req->fence.seqno; @@ -794,10 +802,10 @@ TRACE_EVENT(i915_gem_request_wait_begin, __entry->flags = flags; ), - TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u, blocking=%u, flags=0x%x", - __entry->dev, __entry->ring, __entry->ctx, __entry->seqno, - __entry->global, !!(__entry->flags & I915_WAIT_LOCKED), - __entry->flags) + TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, global=%u, blocking=%u, flags=0x%x", + __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx, + __entry->seqno, __entry->global, + !!(__entry->flags & I915_WAIT_LOCKED), __entry->flags) ); DEFINE_EVENT(i915_gem_request, i915_gem_request_wait_end, -- GitLab From 8daf94e9002dafb8c425eef1f6ff6dbb49a38d90 Mon Sep 17 00:00:00 2001 From: Jim Qu Date: Fri, 15 Dec 2017 15:27:57 +0800 Subject: [PATCH 1732/2547] drm/amdgpu: always cancel uvd idle handler in uvd suspend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jim Qu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index bd6d3a1c1d65..2b47c0de5620 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -297,6 +297,8 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) if (adev->uvd.vcpu_bo == NULL) return 0; + cancel_delayed_work_sync(&adev->uvd.idle_work); + for (i = 0; i < adev->uvd.max_handles; ++i) if (atomic_read(&adev->uvd.handles[i])) break; @@ -304,8 +306,6 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) if (i == AMDGPU_MAX_UVD_HANDLES) return 0; - cancel_delayed_work_sync(&adev->uvd.idle_work); - size = amdgpu_bo_size(adev->uvd.vcpu_bo); ptr = adev->uvd.cpu_addr; -- GitLab From 3b1186fd2aa4ab09b199580d9254c61eb6b6cfbc Mon Sep 17 00:00:00 2001 From: Jim Qu Date: Mon, 18 Dec 2017 10:08:38 +0800 Subject: [PATCH 1733/2547] drm/amdgpu: restore uvd fence seq in uvd resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit otherwise, uvd block will be never powered up in ring begin_use() callback. uvd ring test will be fail in resume in rumtime pm. Signed-off-by: Jim Qu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 2b47c0de5620..b2eae86bf906 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -346,6 +346,8 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev) ptr += le32_to_cpu(hdr->ucode_size_bytes); } memset_io(ptr, 0, size); + /* to restore uvd fence seq */ + amdgpu_fence_driver_force_completion(&adev->uvd.ring); } return 0; -- GitLab From 827ed2b06b05a9e9791e10f03096cc5ddd85bc44 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 15 Dec 2017 13:36:49 +0100 Subject: [PATCH 1734/2547] drm/ttm: use try_lock in ttm_bo_delayed_delete again MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We only need to wait for the contended lock when the reservation object is shared or when we want to remove everything. A trylock should be sufficient in all other cases. Signed-off-by: Christian König Reviewed-by: Roger He Reviewed-by: Thomas Hellstrom Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index ba5b48617bba..122a964cac40 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -586,12 +586,17 @@ static bool ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) ddestroy); kref_get(&bo->list_kref); list_move_tail(&bo->ddestroy, &removed); - spin_unlock(&glob->lru_lock); - reservation_object_lock(bo->resv, NULL); + if (remove_all || bo->resv != &bo->ttm_resv) { + spin_unlock(&glob->lru_lock); + reservation_object_lock(bo->resv, NULL); - spin_lock(&glob->lru_lock); - ttm_bo_cleanup_refs(bo, false, !remove_all, true); + spin_lock(&glob->lru_lock); + ttm_bo_cleanup_refs(bo, false, !remove_all, true); + + } else if (reservation_object_trylock(bo->resv)) { + ttm_bo_cleanup_refs(bo, false, !remove_all, true); + } kref_put(&bo->list_kref, ttm_bo_release_list); spin_lock(&glob->lru_lock); -- GitLab From 2b7e35fbf818a517e727186116cd31421c8aaeac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 15 Dec 2017 17:27:28 +0100 Subject: [PATCH 1735/2547] drm/ttm: cleanup some more resv->lock uses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the reservation wrapper for this. Signed-off-by: Christian König Reviewed-by: Roger He Reviewed-by: Thomas Hellstrom Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 14 +++++++------- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 122a964cac40..5cc96b232c17 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -165,7 +165,7 @@ void ttm_bo_add_to_lru(struct ttm_buffer_object *bo) struct ttm_bo_device *bdev = bo->bdev; struct ttm_mem_type_manager *man; - lockdep_assert_held(&bo->resv->lock.base); + reservation_object_assert_held(bo->resv); if (!(bo->mem.placement & TTM_PL_FLAG_NO_EVICT)) { @@ -216,7 +216,7 @@ EXPORT_SYMBOL(ttm_bo_del_sub_from_lru); void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo) { - lockdep_assert_held(&bo->resv->lock.base); + reservation_object_assert_held(bo->resv); ttm_bo_del_from_lru(bo); ttm_bo_add_to_lru(bo); @@ -665,7 +665,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, struct ttm_placement placement; int ret = 0; - lockdep_assert_held(&bo->resv->lock.base); + reservation_object_assert_held(bo->resv); evict_mem = bo->mem; evict_mem.mm_node = NULL; @@ -1022,7 +1022,7 @@ static int ttm_bo_move_buffer(struct ttm_buffer_object *bo, int ret = 0; struct ttm_mem_reg mem; - lockdep_assert_held(&bo->resv->lock.base); + reservation_object_assert_held(bo->resv); mem.num_pages = bo->num_pages; mem.size = mem.num_pages << PAGE_SHIFT; @@ -1092,7 +1092,7 @@ int ttm_bo_validate(struct ttm_buffer_object *bo, int ret; uint32_t new_flags; - lockdep_assert_held(&bo->resv->lock.base); + reservation_object_assert_held(bo->resv); /* * Check whether we need to move buffer. */ @@ -1186,7 +1186,7 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev, bo->sg = sg; if (resv) { bo->resv = resv; - lockdep_assert_held(&bo->resv->lock.base); + reservation_object_assert_held(bo->resv); } else { bo->resv = &bo->ttm_resv; } @@ -1208,7 +1208,7 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev, * since otherwise lockdep will be angered in radeon. */ if (!resv) { - locked = ww_mutex_trylock(&bo->resv->lock); + locked = reservation_object_trylock(bo->resv); WARN_ON(!locked); } diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 9237099a7c49..6e353df4e4bc 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -485,7 +485,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, fbo->acc_size = 0; fbo->resv = &fbo->ttm_resv; reservation_object_init(fbo->resv); - ret = ww_mutex_trylock(&fbo->resv->lock); + ret = reservation_object_trylock(fbo->resv); WARN_ON(!ret); *new_obj = fbo; -- GitLab From 78f99c6d5c8ea707cf1953aaa73b911679f9066a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 15 Dec 2017 17:39:32 +0100 Subject: [PATCH 1736/2547] drm/ttm: cleanup some old defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use pr_debug instead of TTM_DEBUG, fix the lockdep assert and remove the unused constant. Signed-off-by: Christian König Reviewed-by: Roger He Reviewed-by: Thomas Hellstrom Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 5cc96b232c17..60bb5c12b568 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -42,10 +42,6 @@ #include #include -#define TTM_ASSERT_LOCKED(param) -#define TTM_DEBUG(fmt, arg...) -#define TTM_BO_HASH_ORDER 13 - static int ttm_bo_swapout(struct ttm_mem_shrink *shrink); static void ttm_bo_global_kobj_release(struct kobject *kobj); @@ -233,7 +229,7 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc) int ret = 0; uint32_t page_flags = 0; - TTM_ASSERT_LOCKED(&bo->mutex); + reservation_object_assert_held(bo->resv); bo->ttm = NULL; if (bdev->need_dma32) @@ -1544,12 +1540,12 @@ int ttm_bo_device_release(struct ttm_bo_device *bdev) cancel_delayed_work_sync(&bdev->wq); if (ttm_bo_delayed_delete(bdev, true)) - TTM_DEBUG("Delayed destroy list was clean\n"); + pr_debug("Delayed destroy list was clean\n"); spin_lock(&glob->lru_lock); for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) if (list_empty(&bdev->man[0].lru[0])) - TTM_DEBUG("Swap list %d was clean\n", i); + pr_debug("Swap list %d was clean\n", i); spin_unlock(&glob->lru_lock); drm_vma_offset_manager_destroy(&bdev->vma_manager); -- GitLab From 6a42fd6fbf5340968b1fb41bf6a700699ddb5a13 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Tue, 5 Dec 2017 15:23:26 +0100 Subject: [PATCH 1737/2547] drm/amdgpu: implement 2+1 PD support for Raven v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of falling back to 2 level and very limited address space use 2+1 PD support and 128TB + 512GB of virtual address space. v2: cleanup defines, rebase on top of level enum v3: fix inverted check in hardware setup Signed-off-by: Christian König Reviewed-and-Tested-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 6 +++ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 42 +++++++++++++------- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 26 +++++++++++-- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 49 +++++++++++++++--------- 5 files changed, 89 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 6b296e1fecf2..bbe06e04dcb6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -540,6 +540,7 @@ struct amdgpu_mc { u64 private_aperture_end; /* protects concurrent invalidation */ spinlock_t invalidate_lock; + bool translate_further; }; /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 1056484de0e3..edd2ea52dc00 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -70,6 +70,12 @@ struct amdgpu_bo_list_entry; /* PDE is handled as PTE for VEGA10 */ #define AMDGPU_PDE_PTE (1ULL << 54) +/* PTE is handled as PDE for VEGA10 (Translate Further) */ +#define AMDGPU_PTE_TF (1ULL << 56) + +/* PDE Block Fragment Size for VEGA10 */ +#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) + /* VEGA10 only */ #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57) #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 1d392f186e0d..56f5fe4e2fee 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -143,8 +143,15 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); tmp = mmVM_L2_CNTL3_DEFAULT; - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6); + if (adev->mc.translate_further) { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); + } else { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 6); + } WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); tmp = mmVM_L2_CNTL4_DEFAULT; @@ -182,31 +189,40 @@ static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) { - int i; + unsigned num_level, block_size; uint32_t tmp; + int i; + + num_level = adev->vm_manager.num_level; + block_size = adev->vm_manager.block_size; + if (adev->mc.translate_further) + num_level -= 1; + else + block_size -= 9; for (i = 0; i <= 14; i++) { tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, - adev->vm_manager.num_level); + num_level); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, + 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - PAGE_TABLE_BLOCK_SIZE, - adev->vm_manager.block_size - 9); + PAGE_TABLE_BLOCK_SIZE, + block_size); /* Send no-retry XNACK on fault to suppress VM fault storm. */ tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 3c84f82687f9..b776df4c999f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -476,6 +476,21 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, *addr = adev->vm_manager.vram_base_offset + *addr - adev->mc.vram_start; BUG_ON(*addr & 0xFFFF00000000003FULL); + + if (!adev->mc.translate_further) + return; + + if (level == AMDGPU_VM_PDB1) { + /* Set the block fragment size */ + if (!(*flags & AMDGPU_PDE_PTE)) + *flags |= AMDGPU_PDE_BFS(0x9); + + } else if (level == AMDGPU_VM_PDB0) { + if (*flags & AMDGPU_PDE_PTE) + *flags &= ~AMDGPU_PDE_PTE; + else + *flags |= AMDGPU_PTE_TF; + } } static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = { @@ -773,11 +788,14 @@ static int gmc_v9_0_sw_init(void *handle) switch (adev->asic_type) { case CHIP_RAVEN: adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; - if (adev->rev_id == 0x0 || adev->rev_id == 0x1) + if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); - else - /* vm_size is 64GB for legacy 2-level page support */ - amdgpu_vm_adjust_size(adev, 64, 9, 1, 48); + } else { + /* vm_size is 128TB + 512GB for legacy 3-level page support */ + amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); + adev->mc.translate_further = + adev->vm_manager.num_level > 1; + } break; case CHIP_VEGA10: /* XXX Don't know how to get VRAM type yet. */ diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index 0c5a76f88d35..ffd5b7ee49c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -155,10 +155,15 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); - tmp = mmVM_L2_CNTL3_DEFAULT; - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6); - WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); + if (adev->mc.translate_further) { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); + } else { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 6); + } tmp = mmVM_L2_CNTL4_DEFAULT; tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); @@ -196,32 +201,40 @@ static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) { - int i; + unsigned num_level, block_size; uint32_t tmp; + int i; + + num_level = adev->vm_manager.num_level; + block_size = adev->vm_manager.block_size; + if (adev->mc.translate_further) + num_level -= 1; + else + block_size -= 9; for (i = 0; i <= 14; i++) { tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, + num_level); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - ENABLE_CONTEXT, 1); - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - PAGE_TABLE_DEPTH, adev->vm_manager.num_level); - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, + 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - PAGE_TABLE_BLOCK_SIZE, - adev->vm_manager.block_size - 9); + PAGE_TABLE_BLOCK_SIZE, + block_size); /* Send no-retry XNACK on fault to suppress VM fault storm. */ tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); -- GitLab From 979311191ee6f350bb7ee04a6db54f182f952840 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 6 Dec 2017 14:07:22 +0100 Subject: [PATCH 1738/2547] MAINTAINERS: add separate entry for DRM TTM v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit AMD is the major user of TTM, so it also makes sense that we maintain it. v2: mention Alex git tree as well Signed-off-by: Christian König Acked-by: Alex Deucher Acked-by: Thomas Hellstrom Signed-off-by: Alex Deucher --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 069ba63190b2..64e7b5f77440 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4805,6 +4805,15 @@ S: Maintained F: drivers/gpu/drm/tinydrm/ F: include/drm/tinydrm/ +DRM TTM SUBSYSTEM +M: Christian Koenig +M: Roger He +T: git git://people.freedesktop.org/~agd5f/linux +S: Maintained +L: dri-devel@lists.freedesktop.org +F: include/drm/ttm/ +F: drivers/gpu/drm/ttm/ + DSBR100 USB FM RADIO DRIVER M: Alexey Klimov L: linux-media@vger.kernel.org -- GitLab From 24562523688bebc7ec17a88271b4e8c3fc337b74 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 15 Dec 2017 12:09:16 -0500 Subject: [PATCH 1739/2547] Revert "drm/amd/amdgpu: set gtt size according to system memory size only" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit ba851eed895c76be0eb4260bdbeb7e26f9ccfaa2. With that change piglit max size tests (running with -t max.*size) are causing OOM and hard hang on my CZ with 1GB RAM. Signed-off-by: Andrey Grodzovsky Acked-by: Alex Deucher Reviewed-by: Christian König Reviewed-by: Roger He Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 5b5554cba35f..f1b7d987bd57 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1424,9 +1424,11 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) struct sysinfo si; si_meminfo(&si); - gtt_size = max(AMDGPU_DEFAULT_GTT_SIZE_MB << 20, - (uint64_t)si.totalram * si.mem_unit * 3/4); - } else + gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), + adev->mc.mc_vram_size), + ((uint64_t)si.totalram * si.mem_unit * 3/4)); + } + else gtt_size = (uint64_t)amdgpu_gtt_size << 20; r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT); if (r) { -- GitLab From 234833991e14681f61cbfd93e65a5c976089cf11 Mon Sep 17 00:00:00 2001 From: Jon Maloy Date: Mon, 18 Dec 2017 17:34:16 +0100 Subject: [PATCH 1740/2547] tipc: fix lost member events bug Group messages are not supposed to be returned to sender when the destination socket disappears. This is done correctly for regular traffic messages, by setting the 'dest_droppable' bit in the header. But we forget to do that in group protocol messages. This has the effect that such messages may sometimes bounce back to the sender, be perceived as a legitimate peer message, and wreak general havoc for the rest of the session. In particular, we have seen that a member in state LEAVING may go back to state RECLAIMED or REMITTED, hence causing suppression of an otherwise expected 'member down' event to the user. We fix this by setting the 'dest_droppable' bit even in group protocol messages. Signed-off-by: Jon Maloy Signed-off-by: David S. Miller --- net/tipc/group.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/tipc/group.c b/net/tipc/group.c index 95fec2c057d6..efb5714e7a85 100644 --- a/net/tipc/group.c +++ b/net/tipc/group.c @@ -648,6 +648,7 @@ static void tipc_group_proto_xmit(struct tipc_group *grp, struct tipc_member *m, } else if (mtyp == GRP_REMIT_MSG) { msg_set_grp_remitted(hdr, m->window); } + msg_set_dest_droppable(hdr, true); __skb_queue_tail(xmitq, skb); } -- GitLab From 3f42f5fe31c8715a34064bfd7b788488d1ea2f7c Mon Sep 17 00:00:00 2001 From: Jon Maloy Date: Mon, 18 Dec 2017 18:13:34 +0100 Subject: [PATCH 1741/2547] tipc: remove leaving group member from all lists A group member going into state LEAVING should never go back to any other state before it is finally deleted. However, this might happen if the socket needs to send out a RECLAIM message during this interval. Since we forget to remove the leaving member from the group's 'active' or 'pending' list, the member might be selected for reclaiming, change state to RECLAIMING, and get stuck in this state instead of being deleted. This might lead to suppression of the expected 'member down' event to the receiver. We fix this by removing the member from all lists, except the RB tree, at the moment it goes into state LEAVING. Signed-off-by: Jon Maloy Signed-off-by: David S. Miller --- net/tipc/group.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/net/tipc/group.c b/net/tipc/group.c index efb5714e7a85..b96ec429bb9b 100644 --- a/net/tipc/group.c +++ b/net/tipc/group.c @@ -699,6 +699,9 @@ void tipc_group_proto_rcv(struct tipc_group *grp, bool *usr_wakeup, if (!m) return; m->bc_syncpt = msg_grp_bc_syncpt(hdr); + list_del_init(&m->list); + list_del_init(&m->congested); + *usr_wakeup = true; /* Wait until WITHDRAW event is received */ if (m->state != MBR_LEAVING) { @@ -710,8 +713,6 @@ void tipc_group_proto_rcv(struct tipc_group *grp, bool *usr_wakeup, ehdr = buf_msg(m->event_msg); msg_set_grp_bc_seqno(ehdr, m->bc_syncpt); __skb_queue_tail(inputq, m->event_msg); - *usr_wakeup = true; - list_del_init(&m->congested); return; case GRP_ADV_MSG: if (!m) @@ -863,6 +864,7 @@ void tipc_group_member_evt(struct tipc_group *grp, msg_set_grp_bc_seqno(hdr, m->bc_rcv_nxt); __skb_queue_tail(inputq, skb); } + list_del_init(&m->list); list_del_init(&m->congested); } *sk_rcvbuf = tipc_group_rcvbuf_limit(grp); -- GitLab From c505873eaece2b4aefd07d339dc7e1400e0235ac Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Mon, 18 Dec 2017 10:26:43 +0800 Subject: [PATCH 1742/2547] net: phy: marvell: Limit 88m1101 autoneg errata to 88E1145 as well. 88E1145 also need this autoneg errata. Fixes: f2899788353c ("net: phy: marvell: Limit errata to 88m1101") Signed-off-by: Zhao Qiang Signed-off-by: David S. Miller --- drivers/net/phy/marvell.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index b5a8f750e433..26c9a11220ca 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -2073,7 +2073,7 @@ static struct phy_driver marvell_drivers[] = { .flags = PHY_HAS_INTERRUPT, .probe = marvell_probe, .config_init = &m88e1145_config_init, - .config_aneg = &marvell_config_aneg, + .config_aneg = &m88e1101_config_aneg, .read_status = &genphy_read_status, .ack_interrupt = &marvell_ack_interrupt, .config_intr = &marvell_config_intr, -- GitLab From ac3241d5c81bf6e85095481435f29a4627ff820e Mon Sep 17 00:00:00 2001 From: Hemanth Puranik Date: Mon, 18 Dec 2017 11:27:47 +0530 Subject: [PATCH 1743/2547] net: qcom/emac: Change the order of mac up and sgmii open This patch fixes the order of mac_up and sgmii_open for the reasons noted below: - If open takes more time(if the SGMII block is not responding or if we want to do some delay based task) in this situation we will hit NETDEV watchdog - The main reason : We should signal to upper layers that we are ready to receive packets "only" when the entire path is initialized not the other way around, this is followed in the reset path where we do mac_down, sgmii_reset and mac_up. This also makes the driver uniform across the reset and open paths. - In the future there may be need for delay based tasks to be done in sgmii open which will result in NETDEV watchdog - As per the documentation the order of init should be sgmii, mac, rings and DMA Signed-off-by: Hemanth Puranik Acked-by: Timur Tabi Signed-off-by: David S. Miller --- drivers/net/ethernet/qualcomm/emac/emac.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/qualcomm/emac/emac.c b/drivers/net/ethernet/qualcomm/emac/emac.c index 70c92b649b29..38c924bdd32e 100644 --- a/drivers/net/ethernet/qualcomm/emac/emac.c +++ b/drivers/net/ethernet/qualcomm/emac/emac.c @@ -253,18 +253,18 @@ static int emac_open(struct net_device *netdev) return ret; } - ret = emac_mac_up(adpt); + ret = adpt->phy.open(adpt); if (ret) { emac_mac_rx_tx_rings_free_all(adpt); free_irq(irq->irq, irq); return ret; } - ret = adpt->phy.open(adpt); + ret = emac_mac_up(adpt); if (ret) { - emac_mac_down(adpt); emac_mac_rx_tx_rings_free_all(adpt); free_irq(irq->irq, irq); + adpt->phy.close(adpt); return ret; } -- GitLab From 5c468674d17056148da06218d4da5d04baf22eac Mon Sep 17 00:00:00 2001 From: Xin Long Date: Mon, 18 Dec 2017 14:07:25 +0800 Subject: [PATCH 1744/2547] sctp: fix the issue that a __u16 variable may overflow in sctp_ulpq_renege Now when reneging events in sctp_ulpq_renege(), the variable freed could be increased by a __u16 value twice while freed is of __u16 type. It means freed may overflow at the second addition. This patch is to fix it by using __u32 type for 'freed', while at it, also to remove 'if (chunk)' check, as all renege commands are generated in sctp_eat_data and it can't be NULL. Reported-by: Marcelo Ricardo Leitner Signed-off-by: Xin Long Acked-by: Neil Horman Signed-off-by: David S. Miller --- net/sctp/ulpqueue.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/net/sctp/ulpqueue.c b/net/sctp/ulpqueue.c index a71be33f3afe..e36ec5dd64c6 100644 --- a/net/sctp/ulpqueue.c +++ b/net/sctp/ulpqueue.c @@ -1084,29 +1084,21 @@ void sctp_ulpq_partial_delivery(struct sctp_ulpq *ulpq, void sctp_ulpq_renege(struct sctp_ulpq *ulpq, struct sctp_chunk *chunk, gfp_t gfp) { - struct sctp_association *asoc; - __u16 needed, freed; - - asoc = ulpq->asoc; + struct sctp_association *asoc = ulpq->asoc; + __u32 freed = 0; + __u16 needed; - if (chunk) { - needed = ntohs(chunk->chunk_hdr->length); - needed -= sizeof(struct sctp_data_chunk); - } else - needed = SCTP_DEFAULT_MAXWINDOW; - - freed = 0; + needed = ntohs(chunk->chunk_hdr->length) - + sizeof(struct sctp_data_chunk); if (skb_queue_empty(&asoc->base.sk->sk_receive_queue)) { freed = sctp_ulpq_renege_order(ulpq, needed); - if (freed < needed) { + if (freed < needed) freed += sctp_ulpq_renege_frags(ulpq, needed - freed); - } } /* If able to free enough room, accept this chunk. */ - if (chunk && (freed >= needed)) { - int retval; - retval = sctp_ulpq_tail_data(ulpq, chunk, gfp); + if (freed >= needed) { + int retval = sctp_ulpq_tail_data(ulpq, chunk, gfp); /* * Enter partial delivery if chunk has not been * delivered; otherwise, drain the reassembly queue. -- GitLab From d196975905b2bb227dc54547c03b3d9d0013805c Mon Sep 17 00:00:00 2001 From: Xin Long Date: Mon, 18 Dec 2017 14:13:17 +0800 Subject: [PATCH 1745/2547] sctp: add SCTP_CID_RECONF conversion in sctp_cname Whenever a new type of chunk is added, the corresp conversion in sctp_cname should be added. Otherwise, in some places, pr_debug will print it as "unknown chunk". Fixes: cc16f00f6529 ("sctp: add support for generating stream reconf ssn reset request chunk") Signed-off-by: Xin Long Acked-by: Marcelo R. Leitner Acked-by: Neil Horman Signed-off-by: David S. Miller --- net/sctp/debug.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/sctp/debug.c b/net/sctp/debug.c index 3f619fdcbf0a..291c97b07058 100644 --- a/net/sctp/debug.c +++ b/net/sctp/debug.c @@ -78,6 +78,9 @@ const char *sctp_cname(const union sctp_subtype cid) case SCTP_CID_AUTH: return "AUTH"; + case SCTP_CID_RECONF: + return "RECONF"; + default: break; } -- GitLab From 84aeb437ab98a2bce3d4b2111c79723aedfceb33 Mon Sep 17 00:00:00 2001 From: Nikolay Aleksandrov Date: Mon, 18 Dec 2017 17:35:09 +0200 Subject: [PATCH 1746/2547] net: bridge: fix early call to br_stp_change_bridge_id and plug newlink leaks The early call to br_stp_change_bridge_id in bridge's newlink can cause a memory leak if an error occurs during the newlink because the fdb entries are not cleaned up if a different lladdr was specified, also another minor issue is that it generates fdb notifications with ifindex = 0. Another unrelated memory leak is the bridge sysfs entries which get added on NETDEV_REGISTER event, but are not cleaned up in the newlink error path. To remove this special case the call to br_stp_change_bridge_id is done after netdev register and we cleanup the bridge on changelink error via br_dev_delete to plug all leaks. This patch makes netlink bridge destruction on newlink error the same as dellink and ioctl del which is necessary since at that point we have a fully initialized bridge device. To reproduce the issue: $ ip l add br0 address 00:11:22:33:44:55 type bridge group_fwd_mask 1 RTNETLINK answers: Invalid argument $ rmmod bridge [ 1822.142525] ============================================================================= [ 1822.143640] BUG bridge_fdb_cache (Tainted: G O ): Objects remaining in bridge_fdb_cache on __kmem_cache_shutdown() [ 1822.144821] ----------------------------------------------------------------------------- [ 1822.145990] Disabling lock debugging due to kernel taint [ 1822.146732] INFO: Slab 0x0000000092a844b2 objects=32 used=2 fp=0x00000000fef011b0 flags=0x1ffff8000000100 [ 1822.147700] CPU: 2 PID: 13584 Comm: rmmod Tainted: G B O 4.15.0-rc2+ #87 [ 1822.148578] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.7.5-20140531_083030-gandalf 04/01/2014 [ 1822.150008] Call Trace: [ 1822.150510] dump_stack+0x78/0xa9 [ 1822.151156] slab_err+0xb1/0xd3 [ 1822.151834] ? __kmalloc+0x1bb/0x1ce [ 1822.152546] __kmem_cache_shutdown+0x151/0x28b [ 1822.153395] shutdown_cache+0x13/0x144 [ 1822.154126] kmem_cache_destroy+0x1c0/0x1fb [ 1822.154669] SyS_delete_module+0x194/0x244 [ 1822.155199] ? trace_hardirqs_on_thunk+0x1a/0x1c [ 1822.155773] entry_SYSCALL_64_fastpath+0x23/0x9a [ 1822.156343] RIP: 0033:0x7f929bd38b17 [ 1822.156859] RSP: 002b:00007ffd160e9a98 EFLAGS: 00000202 ORIG_RAX: 00000000000000b0 [ 1822.157728] RAX: ffffffffffffffda RBX: 00005578316ba090 RCX: 00007f929bd38b17 [ 1822.158422] RDX: 00007f929bd9ec60 RSI: 0000000000000800 RDI: 00005578316ba0f0 [ 1822.159114] RBP: 0000000000000003 R08: 00007f929bff5f20 R09: 00007ffd160e8a11 [ 1822.159808] R10: 00007ffd160e9860 R11: 0000000000000202 R12: 00007ffd160e8a80 [ 1822.160513] R13: 0000000000000000 R14: 0000000000000000 R15: 00005578316ba090 [ 1822.161278] INFO: Object 0x000000007645de29 @offset=0 [ 1822.161666] INFO: Object 0x00000000d5df2ab5 @offset=128 Fixes: 30313a3d5794 ("bridge: Handle IFLA_ADDRESS correctly when creating bridge device") Fixes: 5b8d5429daa0 ("bridge: netlink: register netdevice before executing changelink") Signed-off-by: Nikolay Aleksandrov Signed-off-by: David S. Miller --- net/bridge/br_netlink.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/net/bridge/br_netlink.c b/net/bridge/br_netlink.c index d0ef0a8e8831..015f465c514b 100644 --- a/net/bridge/br_netlink.c +++ b/net/bridge/br_netlink.c @@ -1262,19 +1262,20 @@ static int br_dev_newlink(struct net *src_net, struct net_device *dev, struct net_bridge *br = netdev_priv(dev); int err; + err = register_netdevice(dev); + if (err) + return err; + if (tb[IFLA_ADDRESS]) { spin_lock_bh(&br->lock); br_stp_change_bridge_id(br, nla_data(tb[IFLA_ADDRESS])); spin_unlock_bh(&br->lock); } - err = register_netdevice(dev); - if (err) - return err; - err = br_changelink(dev, tb, data, extack); if (err) - unregister_netdevice(dev); + br_dev_delete(dev, NULL); + return err; } -- GitLab From bb422a738f6566f7439cd347d54e321e4fe92a9f Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Mon, 18 Dec 2017 20:31:41 +0900 Subject: [PATCH 1747/2547] mm,vmscan: Make unregister_shrinker() no-op if register_shrinker() failed. Syzbot caught an oops at unregister_shrinker() because combination of commit 1d3d4437eae1bb29 ("vmscan: per-node deferred work") and fault injection made register_shrinker() fail and the caller of register_shrinker() did not check for failure. ---------- [ 554.881422] FAULT_INJECTION: forcing a failure. [ 554.881422] name failslab, interval 1, probability 0, space 0, times 0 [ 554.881438] CPU: 1 PID: 13231 Comm: syz-executor1 Not tainted 4.14.0-rc8+ #82 [ 554.881443] Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 [ 554.881445] Call Trace: [ 554.881459] dump_stack+0x194/0x257 [ 554.881474] ? arch_local_irq_restore+0x53/0x53 [ 554.881486] ? find_held_lock+0x35/0x1d0 [ 554.881507] should_fail+0x8c0/0xa40 [ 554.881522] ? fault_create_debugfs_attr+0x1f0/0x1f0 [ 554.881537] ? check_noncircular+0x20/0x20 [ 554.881546] ? find_next_zero_bit+0x2c/0x40 [ 554.881560] ? ida_get_new_above+0x421/0x9d0 [ 554.881577] ? find_held_lock+0x35/0x1d0 [ 554.881594] ? __lock_is_held+0xb6/0x140 [ 554.881628] ? check_same_owner+0x320/0x320 [ 554.881634] ? lock_downgrade+0x990/0x990 [ 554.881649] ? find_held_lock+0x35/0x1d0 [ 554.881672] should_failslab+0xec/0x120 [ 554.881684] __kmalloc+0x63/0x760 [ 554.881692] ? lock_downgrade+0x990/0x990 [ 554.881712] ? register_shrinker+0x10e/0x2d0 [ 554.881721] ? trace_event_raw_event_module_request+0x320/0x320 [ 554.881737] register_shrinker+0x10e/0x2d0 [ 554.881747] ? prepare_kswapd_sleep+0x1f0/0x1f0 [ 554.881755] ? _down_write_nest_lock+0x120/0x120 [ 554.881765] ? memcpy+0x45/0x50 [ 554.881785] sget_userns+0xbcd/0xe20 (...snipped...) [ 554.898693] kasan: CONFIG_KASAN_INLINE enabled [ 554.898724] kasan: GPF could be caused by NULL-ptr deref or user memory access [ 554.898732] general protection fault: 0000 [#1] SMP KASAN [ 554.898737] Dumping ftrace buffer: [ 554.898741] (ftrace buffer empty) [ 554.898743] Modules linked in: [ 554.898752] CPU: 1 PID: 13231 Comm: syz-executor1 Not tainted 4.14.0-rc8+ #82 [ 554.898755] Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 [ 554.898760] task: ffff8801d1dbe5c0 task.stack: ffff8801c9e38000 [ 554.898772] RIP: 0010:__list_del_entry_valid+0x7e/0x150 [ 554.898775] RSP: 0018:ffff8801c9e3f108 EFLAGS: 00010246 [ 554.898780] RAX: dffffc0000000000 RBX: 0000000000000000 RCX: 0000000000000000 [ 554.898784] RDX: 0000000000000000 RSI: ffff8801c53c6f98 RDI: ffff8801c53c6fa0 [ 554.898788] RBP: ffff8801c9e3f120 R08: 1ffff100393c7d55 R09: 0000000000000004 [ 554.898791] R10: ffff8801c9e3ef70 R11: 0000000000000000 R12: 0000000000000000 [ 554.898795] R13: dffffc0000000000 R14: 1ffff100393c7e45 R15: ffff8801c53c6f98 [ 554.898800] FS: 0000000000000000(0000) GS:ffff8801db300000(0000) knlGS:0000000000000000 [ 554.898804] CS: 0010 DS: 002b ES: 002b CR0: 0000000080050033 [ 554.898807] CR2: 00000000dbc23000 CR3: 00000001c7269000 CR4: 00000000001406e0 [ 554.898813] DR0: 0000000020000000 DR1: 0000000020000000 DR2: 0000000000000000 [ 554.898816] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000600 [ 554.898818] Call Trace: [ 554.898828] unregister_shrinker+0x79/0x300 [ 554.898837] ? perf_trace_mm_vmscan_writepage+0x750/0x750 [ 554.898844] ? down_write+0x87/0x120 [ 554.898851] ? deactivate_super+0x139/0x1b0 [ 554.898857] ? down_read+0x150/0x150 [ 554.898864] ? check_same_owner+0x320/0x320 [ 554.898875] deactivate_locked_super+0x64/0xd0 [ 554.898883] deactivate_super+0x141/0x1b0 ---------- Since allowing register_shrinker() callers to call unregister_shrinker() when register_shrinker() failed can simplify error recovery path, this patch makes unregister_shrinker() no-op when register_shrinker() failed. Also, reset shrinker->nr_deferred in case unregister_shrinker() was by error called twice. Signed-off-by: Tetsuo Handa Signed-off-by: Aliaksei Karaliou Reported-by: syzbot Cc: Glauber Costa Cc: Al Viro Signed-off-by: Al Viro --- mm/vmscan.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/mm/vmscan.c b/mm/vmscan.c index c02c850ea349..47d5ced51f2d 100644 --- a/mm/vmscan.c +++ b/mm/vmscan.c @@ -297,10 +297,13 @@ EXPORT_SYMBOL(register_shrinker); */ void unregister_shrinker(struct shrinker *shrinker) { + if (!shrinker->nr_deferred) + return; down_write(&shrinker_rwsem); list_del(&shrinker->list); up_write(&shrinker_rwsem); kfree(shrinker->nr_deferred); + shrinker->nr_deferred = NULL; } EXPORT_SYMBOL(unregister_shrinker); -- GitLab From 6623c0fba10ef45b64ca213ad5dec926f37fa9a0 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 15 Dec 2017 16:10:20 +0000 Subject: [PATCH 1748/2547] net: phy: marvell: avoid pause mode on SGMII-to-Copper for 88e151x Observed on the 88e1512 in SGMII-to-Copper mode, negotiating pause is unreliable. While the pause bits can be set in the advertisment register, they clear shortly after negotiation with a link partner commences irrespective of the cause of the negotiation. While these bits may be correctly conveyed to the link partner on the first negotiation, a subsequent negotiation (eg, due to negotiation restart by the link partner, or reconnection of the cable) will result in the link partner seeing these bits as zero, while the kernel believes that it has advertised pause modes. This leads to the local kernel evaluating (eg) symmetric pause mode, while the remote end evaluates that we have no pause mode capability. Since we can't guarantee the advertisment, disable pause mode support with this PHY when used in SGMII-to-Copper mode. The 88e1510 in RGMII-to-Copper mode appears to behave correctly. Reviewed-by: Andrew Lunn Signed-off-by: Russell King Signed-off-by: David S. Miller --- drivers/net/phy/marvell.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 26c9a11220ca..82104edca393 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -879,6 +879,8 @@ static int m88e1510_config_init(struct phy_device *phydev) /* SGMII-to-Copper mode initialization */ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + u32 pause; + /* Select page 18 */ err = marvell_set_page(phydev, 18); if (err < 0) @@ -902,6 +904,16 @@ static int m88e1510_config_init(struct phy_device *phydev) err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE); if (err < 0) return err; + + /* There appears to be a bug in the 88e1512 when used in + * SGMII to copper mode, where the AN advertisment register + * clears the pause bits each time a negotiation occurs. + * This means we can never be truely sure what was advertised, + * so disable Pause support. + */ + pause = SUPPORTED_Pause | SUPPORTED_Asym_Pause; + phydev->supported &= ~pause; + phydev->advertising &= ~pause; } return m88e1121_config_init(phydev); -- GitLab From 9ee332d99e4d5a97548943b81c54668450ce641b Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 18 Dec 2017 15:05:07 -0500 Subject: [PATCH 1749/2547] sget(): handle failures of register_shrinker() Signed-off-by: Al Viro --- fs/super.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/fs/super.c b/fs/super.c index 7ff1349609e4..06bd25d90ba5 100644 --- a/fs/super.c +++ b/fs/super.c @@ -517,7 +517,11 @@ struct super_block *sget_userns(struct file_system_type *type, hlist_add_head(&s->s_instances, &type->fs_supers); spin_unlock(&sb_lock); get_filesystem(type); - register_shrinker(&s->s_shrink); + err = register_shrinker(&s->s_shrink); + if (err) { + deactivate_locked_super(s); + s = ERR_PTR(err); + } return s; } -- GitLab From ab14436065c8066c265540312742390d6d07ddd2 Mon Sep 17 00:00:00 2001 From: Alexey Khoroshilov Date: Sat, 16 Dec 2017 00:52:39 +0300 Subject: [PATCH 1750/2547] net: phy: xgene: disable clk on error paths There are several error paths in xgene_mdio_probe(), where clk is left undisabled. The patch fixes them. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov Signed-off-by: David S. Miller --- drivers/net/phy/mdio-xgene.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/mdio-xgene.c b/drivers/net/phy/mdio-xgene.c index bfd3090fb055..07c6048200c6 100644 --- a/drivers/net/phy/mdio-xgene.c +++ b/drivers/net/phy/mdio-xgene.c @@ -194,8 +194,11 @@ static int xgene_mdio_reset(struct xgene_mdio_pdata *pdata) } ret = xgene_enet_ecc_init(pdata); - if (ret) + if (ret) { + if (pdata->dev->of_node) + clk_disable_unprepare(pdata->clk); return ret; + } xgene_gmac_reset(pdata); return 0; @@ -388,8 +391,10 @@ static int xgene_mdio_probe(struct platform_device *pdev) return ret; mdio_bus = mdiobus_alloc(); - if (!mdio_bus) - return -ENOMEM; + if (!mdio_bus) { + ret = -ENOMEM; + goto out_clk; + } mdio_bus->name = "APM X-Gene MDIO bus"; @@ -418,7 +423,7 @@ static int xgene_mdio_probe(struct platform_device *pdev) mdio_bus->phy_mask = ~0; ret = mdiobus_register(mdio_bus); if (ret) - goto out; + goto out_mdiobus; acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_HANDLE(dev), 1, acpi_register_phy, NULL, mdio_bus, NULL); @@ -426,16 +431,20 @@ static int xgene_mdio_probe(struct platform_device *pdev) } if (ret) - goto out; + goto out_mdiobus; pdata->mdio_bus = mdio_bus; xgene_mdio_status = true; return 0; -out: +out_mdiobus: mdiobus_free(mdio_bus); +out_clk: + if (dev->of_node) + clk_disable_unprepare(pdata->clk); + return ret; } -- GitLab From 584d4ed80e93889c54daeee75243c765f9d1e879 Mon Sep 17 00:00:00 2001 From: Xiongwei Song Date: Sat, 2 Dec 2017 19:24:22 +0800 Subject: [PATCH 1751/2547] drm/tilcdc: make tilcdc_mode_hvtotal() static The function tilcdc_mode_hvtotal is local to the source and does not need to be in global scope, so make it static. drivers/gpu/drm/tilcdc/tilcdc_crtc.c:297:6: warning: no previous prototype for 'tilcdc_mode_hvtotal' [-Wmissing-prototypes] uint tilcdc_mode_hvtotal(const struct drm_display_mode *mode) Signed-off-by: Xiongwei Song Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index b81a593aefb2..8bf6bb93dc79 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -272,7 +272,7 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) LCDC_V2_CORE_CLK_EN); } -uint tilcdc_mode_hvtotal(const struct drm_display_mode *mode) +static uint tilcdc_mode_hvtotal(const struct drm_display_mode *mode) { return (uint) div_u64(1000llu * mode->htotal * mode->vtotal, mode->clock); -- GitLab From 14cb0dc6479dc5ebc63b3a459a5d89a2f1b39fed Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Mon, 18 Dec 2017 15:40:43 +0800 Subject: [PATCH 1752/2547] block: don't let passthrough IO go into .make_request_fn() Commit a8821f3f3("block: Improvements to bounce-buffer handling") tries to make sure that the bio to .make_request_fn won't exceed BIO_MAX_PAGES, but ignores that passthrough I/O can use blk_queue_bounce() too. Especially, passthrough IO may not be sector-aligned, and the check of 'sectors < bio_sectors(*bio_orig)' inside __blk_queue_bounce() may become true even though the max bvec number doesn't exceed BIO_MAX_PAGES, then cause the bio splitted, and the original passthrough bio is submited to generic_make_request(). This patch fixes this issue by checking if the bio is passthrough IO, and use bio_kmalloc() to allocate the cloned passthrough bio. Cc: NeilBrown Fixes: a8821f3f3("block: Improvements to bounce-buffer handling") Tested-by: Michele Ballabio Signed-off-by: Ming Lei Signed-off-by: Jens Axboe --- block/bounce.c | 6 ++++-- include/linux/blkdev.h | 21 +++++++++++++++++++-- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/block/bounce.c b/block/bounce.c index fceb1a96480b..1d05c422c932 100644 --- a/block/bounce.c +++ b/block/bounce.c @@ -200,6 +200,7 @@ static void __blk_queue_bounce(struct request_queue *q, struct bio **bio_orig, unsigned i = 0; bool bounce = false; int sectors = 0; + bool passthrough = bio_is_passthrough(*bio_orig); bio_for_each_segment(from, *bio_orig, iter) { if (i++ < BIO_MAX_PAGES) @@ -210,13 +211,14 @@ static void __blk_queue_bounce(struct request_queue *q, struct bio **bio_orig, if (!bounce) return; - if (sectors < bio_sectors(*bio_orig)) { + if (!passthrough && sectors < bio_sectors(*bio_orig)) { bio = bio_split(*bio_orig, sectors, GFP_NOIO, bounce_bio_split); bio_chain(bio, *bio_orig); generic_make_request(*bio_orig); *bio_orig = bio; } - bio = bio_clone_bioset(*bio_orig, GFP_NOIO, bounce_bio_set); + bio = bio_clone_bioset(*bio_orig, GFP_NOIO, passthrough ? NULL : + bounce_bio_set); bio_for_each_segment_all(to, bio, i) { struct page *page = to->bv_page; diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index 8089ca17db9a..abd06f540863 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -241,14 +241,24 @@ struct request { struct request *next_rq; }; +static inline bool blk_op_is_scsi(unsigned int op) +{ + return op == REQ_OP_SCSI_IN || op == REQ_OP_SCSI_OUT; +} + +static inline bool blk_op_is_private(unsigned int op) +{ + return op == REQ_OP_DRV_IN || op == REQ_OP_DRV_OUT; +} + static inline bool blk_rq_is_scsi(struct request *rq) { - return req_op(rq) == REQ_OP_SCSI_IN || req_op(rq) == REQ_OP_SCSI_OUT; + return blk_op_is_scsi(req_op(rq)); } static inline bool blk_rq_is_private(struct request *rq) { - return req_op(rq) == REQ_OP_DRV_IN || req_op(rq) == REQ_OP_DRV_OUT; + return blk_op_is_private(req_op(rq)); } static inline bool blk_rq_is_passthrough(struct request *rq) @@ -256,6 +266,13 @@ static inline bool blk_rq_is_passthrough(struct request *rq) return blk_rq_is_scsi(rq) || blk_rq_is_private(rq); } +static inline bool bio_is_passthrough(struct bio *bio) +{ + unsigned op = bio_op(bio); + + return blk_op_is_scsi(op) || blk_op_is_private(op); +} + static inline unsigned short req_get_ioprio(struct request *req) { return req->ioprio; -- GitLab From 0abc2a10389f0c9070f76ca906c7382788036b93 Mon Sep 17 00:00:00 2001 From: Jens Axboe Date: Mon, 18 Dec 2017 15:40:44 +0800 Subject: [PATCH 1753/2547] block: fix blk_rq_append_bio Commit caa4b02476e3(blk-map: call blk_queue_bounce from blk_rq_append_bio) moves blk_queue_bounce() into blk_rq_append_bio(), but don't consider the fact that the bounced bio becomes invisible to caller since the parameter type is 'struct bio *'. Make it a pointer to a pointer to a bio, so the caller sees the right bio also after a bounce. Fixes: caa4b02476e3 ("blk-map: call blk_queue_bounce from blk_rq_append_bio") Cc: Christoph Hellwig Reported-by: Michele Ballabio (handling failure of blk_rq_append_bio(), only call bio_get() after blk_rq_append_bio() returns OK) Tested-by: Michele Ballabio Signed-off-by: Ming Lei Signed-off-by: Jens Axboe --- block/blk-map.c | 38 +++++++++++++++++------------- drivers/scsi/osd/osd_initiator.c | 4 +++- drivers/target/target_core_pscsi.c | 4 ++-- include/linux/blkdev.h | 2 +- 4 files changed, 28 insertions(+), 20 deletions(-) diff --git a/block/blk-map.c b/block/blk-map.c index b21f8e86f120..d3a94719f03f 100644 --- a/block/blk-map.c +++ b/block/blk-map.c @@ -12,22 +12,29 @@ #include "blk.h" /* - * Append a bio to a passthrough request. Only works can be merged into - * the request based on the driver constraints. + * Append a bio to a passthrough request. Only works if the bio can be merged + * into the request based on the driver constraints. */ -int blk_rq_append_bio(struct request *rq, struct bio *bio) +int blk_rq_append_bio(struct request *rq, struct bio **bio) { - blk_queue_bounce(rq->q, &bio); + struct bio *orig_bio = *bio; + + blk_queue_bounce(rq->q, bio); if (!rq->bio) { - blk_rq_bio_prep(rq->q, rq, bio); + blk_rq_bio_prep(rq->q, rq, *bio); } else { - if (!ll_back_merge_fn(rq->q, rq, bio)) + if (!ll_back_merge_fn(rq->q, rq, *bio)) { + if (orig_bio != *bio) { + bio_put(*bio); + *bio = orig_bio; + } return -EINVAL; + } - rq->biotail->bi_next = bio; - rq->biotail = bio; - rq->__data_len += bio->bi_iter.bi_size; + rq->biotail->bi_next = *bio; + rq->biotail = *bio; + rq->__data_len += (*bio)->bi_iter.bi_size; } return 0; @@ -73,14 +80,12 @@ static int __blk_rq_map_user_iov(struct request *rq, * We link the bounce buffer in and could have to traverse it * later so we have to get a ref to prevent it from being freed */ - ret = blk_rq_append_bio(rq, bio); - bio_get(bio); + ret = blk_rq_append_bio(rq, &bio); if (ret) { - bio_endio(bio); __blk_rq_unmap_user(orig_bio); - bio_put(bio); return ret; } + bio_get(bio); return 0; } @@ -213,7 +218,7 @@ int blk_rq_map_kern(struct request_queue *q, struct request *rq, void *kbuf, int reading = rq_data_dir(rq) == READ; unsigned long addr = (unsigned long) kbuf; int do_copy = 0; - struct bio *bio; + struct bio *bio, *orig_bio; int ret; if (len > (queue_max_hw_sectors(q) << 9)) @@ -236,10 +241,11 @@ int blk_rq_map_kern(struct request_queue *q, struct request *rq, void *kbuf, if (do_copy) rq->rq_flags |= RQF_COPY_USER; - ret = blk_rq_append_bio(rq, bio); + orig_bio = bio; + ret = blk_rq_append_bio(rq, &bio); if (unlikely(ret)) { /* request is too big */ - bio_put(bio); + bio_put(orig_bio); return ret; } diff --git a/drivers/scsi/osd/osd_initiator.c b/drivers/scsi/osd/osd_initiator.c index a4f28b7e4c65..e18877177f1b 100644 --- a/drivers/scsi/osd/osd_initiator.c +++ b/drivers/scsi/osd/osd_initiator.c @@ -1576,7 +1576,9 @@ static struct request *_make_request(struct request_queue *q, bool has_write, return req; for_each_bio(bio) { - ret = blk_rq_append_bio(req, bio); + struct bio *bounce_bio = bio; + + ret = blk_rq_append_bio(req, &bounce_bio); if (ret) return ERR_PTR(ret); } diff --git a/drivers/target/target_core_pscsi.c b/drivers/target/target_core_pscsi.c index 7c69b4a9694d..0d99b242e82e 100644 --- a/drivers/target/target_core_pscsi.c +++ b/drivers/target/target_core_pscsi.c @@ -920,7 +920,7 @@ pscsi_map_sg(struct se_cmd *cmd, struct scatterlist *sgl, u32 sgl_nents, " %d i: %d bio: %p, allocating another" " bio\n", bio->bi_vcnt, i, bio); - rc = blk_rq_append_bio(req, bio); + rc = blk_rq_append_bio(req, &bio); if (rc) { pr_err("pSCSI: failed to append bio\n"); goto fail; @@ -938,7 +938,7 @@ pscsi_map_sg(struct se_cmd *cmd, struct scatterlist *sgl, u32 sgl_nents, } if (bio) { - rc = blk_rq_append_bio(req, bio); + rc = blk_rq_append_bio(req, &bio); if (rc) { pr_err("pSCSI: failed to append bio\n"); goto fail; diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index abd06f540863..100d0df38026 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -965,7 +965,7 @@ extern int blk_rq_prep_clone(struct request *rq, struct request *rq_src, extern void blk_rq_unprep_clone(struct request *rq); extern blk_status_t blk_insert_cloned_request(struct request_queue *q, struct request *rq); -extern int blk_rq_append_bio(struct request *rq, struct bio *bio); +extern int blk_rq_append_bio(struct request *rq, struct bio **bio); extern void blk_delay_queue(struct request_queue *, unsigned long); extern void blk_queue_split(struct request_queue *, struct bio **); extern void blk_recount_segments(struct request_queue *, struct bio *); -- GitLab From 8b7e9d9e2d8b4de6f0d5d7a5fc63f48b1fbcf4d4 Mon Sep 17 00:00:00 2001 From: Anthony Kim Date: Mon, 18 Dec 2017 11:50:48 -0800 Subject: [PATCH 1754/2547] Input: hideep - fix compile error due to missing include file gpiod_() API requires including "linux/gpio/consumer.h". Also, we are not using the legacy API nor the static board files descriptions, so no need to include gpio.h nor gpio/machine.h. Reported-by: kbuild test robot Signed-off-by: Anthony Kim Patchwork-Id: 10094831 Signed-off-by: Dmitry Torokhov --- drivers/input/touchscreen/hideep.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/input/touchscreen/hideep.c b/drivers/input/touchscreen/hideep.c index fc080a7c2e1f..f1cd4dd9a4a3 100644 --- a/drivers/input/touchscreen/hideep.c +++ b/drivers/input/touchscreen/hideep.c @@ -10,8 +10,7 @@ #include #include #include -#include -#include +#include #include #include #include -- GitLab From 3fb04cb0bea5c68c23eaf0cfbd4de840a7948ee9 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sun, 17 Dec 2017 13:28:52 +0000 Subject: [PATCH 1755/2547] drm/i915/selftests: Fix up igt_reset_engine Now that we skip a per-engine reset on an idle engine, we need to update the selftest to take that into account. In the process, we find that we were not stressing the per-engine reset very hard, so add those missing active resets. v2: Actually test i915_reset_engine() by loading it with requests. Fixes: f6ba181ada55 ("drm/i915: Skip an engine reset if it recovered before our preparations") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104313 Signed-off-by: Chris Wilson Cc: Michel Thierry Cc: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20171217132852.30642-3-chris@chris-wilson.co.uk Reviewed-by: Michel Thierry --- .../gpu/drm/i915/selftests/intel_hangcheck.c | 315 ++++++++++++++---- 1 file changed, 251 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index f98546b8a7fa..d1f91a533afa 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -132,6 +132,12 @@ static int emit_recurse_batch(struct hang *h, *batch++ = lower_32_bits(hws_address(hws, rq)); *batch++ = upper_32_bits(hws_address(hws, rq)); *batch++ = rq->fence.seqno; + *batch++ = MI_ARB_CHECK; + + memset(batch, 0, 1024); + batch += 1024 / sizeof(*batch); + + *batch++ = MI_ARB_CHECK; *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; *batch++ = lower_32_bits(vma->node.start); *batch++ = upper_32_bits(vma->node.start); @@ -140,6 +146,12 @@ static int emit_recurse_batch(struct hang *h, *batch++ = 0; *batch++ = lower_32_bits(hws_address(hws, rq)); *batch++ = rq->fence.seqno; + *batch++ = MI_ARB_CHECK; + + memset(batch, 0, 1024); + batch += 1024 / sizeof(*batch); + + *batch++ = MI_ARB_CHECK; *batch++ = MI_BATCH_BUFFER_START | 1 << 8; *batch++ = lower_32_bits(vma->node.start); } else if (INTEL_GEN(i915) >= 4) { @@ -147,12 +159,24 @@ static int emit_recurse_batch(struct hang *h, *batch++ = 0; *batch++ = lower_32_bits(hws_address(hws, rq)); *batch++ = rq->fence.seqno; + *batch++ = MI_ARB_CHECK; + + memset(batch, 0, 1024); + batch += 1024 / sizeof(*batch); + + *batch++ = MI_ARB_CHECK; *batch++ = MI_BATCH_BUFFER_START | 2 << 6; *batch++ = lower_32_bits(vma->node.start); } else { *batch++ = MI_STORE_DWORD_IMM; *batch++ = lower_32_bits(hws_address(hws, rq)); *batch++ = rq->fence.seqno; + *batch++ = MI_ARB_CHECK; + + memset(batch, 0, 1024); + batch += 1024 / sizeof(*batch); + + *batch++ = MI_ARB_CHECK; *batch++ = MI_BATCH_BUFFER_START | 2 << 6 | 1; *batch++ = lower_32_bits(vma->node.start); } @@ -234,6 +258,16 @@ static void hang_fini(struct hang *h) i915_gem_wait_for_idle(h->i915, I915_WAIT_LOCKED); } +static bool wait_for_hang(struct hang *h, struct drm_i915_gem_request *rq) +{ + return !(wait_for_us(i915_seqno_passed(hws_seqno(h, rq), + rq->fence.seqno), + 10) && + wait_for(i915_seqno_passed(hws_seqno(h, rq), + rq->fence.seqno), + 1000)); +} + static int igt_hang_sanitycheck(void *arg) { struct drm_i915_private *i915 = arg; @@ -296,6 +330,9 @@ static void global_reset_lock(struct drm_i915_private *i915) struct intel_engine_cs *engine; enum intel_engine_id id; + pr_debug("%s: current gpu_error=%08lx\n", + __func__, i915->gpu_error.flags); + while (test_and_set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags)) wait_event(i915->gpu_error.reset_queue, !test_bit(I915_RESET_BACKOFF, @@ -353,54 +390,128 @@ static int igt_global_reset(void *arg) return err; } -static int igt_reset_engine(void *arg) +static int __igt_reset_engine(struct drm_i915_private *i915, bool active) { - struct drm_i915_private *i915 = arg; struct intel_engine_cs *engine; enum intel_engine_id id; - unsigned int reset_count, reset_engine_count; + struct hang h; int err = 0; - /* Check that we can issue a global GPU and engine reset */ + /* Check that we can issue an engine reset on an idle engine (no-op) */ if (!intel_has_reset_engine(i915)) return 0; + if (active) { + mutex_lock(&i915->drm.struct_mutex); + err = hang_init(&h, i915); + mutex_unlock(&i915->drm.struct_mutex); + if (err) + return err; + } + for_each_engine(engine, i915, id) { - set_bit(I915_RESET_ENGINE + engine->id, &i915->gpu_error.flags); + unsigned int reset_count, reset_engine_count; + IGT_TIMEOUT(end_time); + + if (active && !intel_engine_can_store_dword(engine)) + continue; + reset_count = i915_reset_count(&i915->gpu_error); reset_engine_count = i915_reset_engine_count(&i915->gpu_error, engine); - err = i915_reset_engine(engine, I915_RESET_QUIET); - if (err) { - pr_err("i915_reset_engine failed\n"); - break; - } + set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags); + do { + if (active) { + struct drm_i915_gem_request *rq; + + mutex_lock(&i915->drm.struct_mutex); + rq = hang_create_request(&h, engine, + i915->kernel_context); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + mutex_unlock(&i915->drm.struct_mutex); + break; + } + + i915_gem_request_get(rq); + __i915_add_request(rq, true); + mutex_unlock(&i915->drm.struct_mutex); + + if (!wait_for_hang(&h, rq)) { + struct drm_printer p = drm_info_printer(i915->drm.dev); + + pr_err("%s: Failed to start request %x, at %x\n", + __func__, rq->fence.seqno, hws_seqno(&h, rq)); + intel_engine_dump(engine, &p, + "%s\n", engine->name); + + i915_gem_request_put(rq); + err = -EIO; + break; + } - if (i915_reset_count(&i915->gpu_error) != reset_count) { - pr_err("Full GPU reset recorded! (engine reset expected)\n"); - err = -EINVAL; - break; - } + i915_gem_request_put(rq); + } + + engine->hangcheck.stalled = true; + engine->hangcheck.seqno = + intel_engine_get_seqno(engine); + + err = i915_reset_engine(engine, I915_RESET_QUIET); + if (err) { + pr_err("i915_reset_engine failed\n"); + break; + } + + if (i915_reset_count(&i915->gpu_error) != reset_count) { + pr_err("Full GPU reset recorded! (engine reset expected)\n"); + err = -EINVAL; + break; + } + + reset_engine_count += active; + if (i915_reset_engine_count(&i915->gpu_error, engine) != + reset_engine_count) { + pr_err("%s engine reset %srecorded!\n", + engine->name, active ? "not " : ""); + err = -EINVAL; + break; + } + + engine->hangcheck.stalled = false; + } while (time_before(jiffies, end_time)); + clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags); - if (i915_reset_engine_count(&i915->gpu_error, engine) == - reset_engine_count) { - pr_err("No %s engine reset recorded!\n", engine->name); - err = -EINVAL; + if (err) break; - } - clear_bit(I915_RESET_ENGINE + engine->id, - &i915->gpu_error.flags); + cond_resched(); } if (i915_terminally_wedged(&i915->gpu_error)) err = -EIO; + if (active) { + mutex_lock(&i915->drm.struct_mutex); + hang_fini(&h); + mutex_unlock(&i915->drm.struct_mutex); + } + return err; } +static int igt_reset_idle_engine(void *arg) +{ + return __igt_reset_engine(arg, false); +} + +static int igt_reset_active_engine(void *arg) +{ + return __igt_reset_engine(arg, true); +} + static int active_engine(void *data) { struct intel_engine_cs *engine = data; @@ -462,11 +573,12 @@ static int active_engine(void *data) return err; } -static int igt_reset_active_engines(void *arg) +static int __igt_reset_engine_others(struct drm_i915_private *i915, + bool active) { - struct drm_i915_private *i915 = arg; - struct intel_engine_cs *engine, *active; + struct intel_engine_cs *engine, *other; enum intel_engine_id id, tmp; + struct hang h; int err = 0; /* Check that issuing a reset on one engine does not interfere @@ -476,24 +588,36 @@ static int igt_reset_active_engines(void *arg) if (!intel_has_reset_engine(i915)) return 0; + if (active) { + mutex_lock(&i915->drm.struct_mutex); + err = hang_init(&h, i915); + mutex_unlock(&i915->drm.struct_mutex); + if (err) + return err; + } + for_each_engine(engine, i915, id) { - struct task_struct *threads[I915_NUM_ENGINES]; + struct task_struct *threads[I915_NUM_ENGINES] = {}; unsigned long resets[I915_NUM_ENGINES]; unsigned long global = i915_reset_count(&i915->gpu_error); + unsigned long count = 0; IGT_TIMEOUT(end_time); + if (active && !intel_engine_can_store_dword(engine)) + continue; + memset(threads, 0, sizeof(threads)); - for_each_engine(active, i915, tmp) { + for_each_engine(other, i915, tmp) { struct task_struct *tsk; - if (active == engine) - continue; - resets[tmp] = i915_reset_engine_count(&i915->gpu_error, - active); + other); - tsk = kthread_run(active_engine, active, - "igt/%s", active->name); + if (other == engine) + continue; + + tsk = kthread_run(active_engine, other, + "igt/%s", other->name); if (IS_ERR(tsk)) { err = PTR_ERR(tsk); goto unwind; @@ -503,20 +627,70 @@ static int igt_reset_active_engines(void *arg) get_task_struct(tsk); } - set_bit(I915_RESET_ENGINE + engine->id, &i915->gpu_error.flags); + set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags); do { + if (active) { + struct drm_i915_gem_request *rq; + + mutex_lock(&i915->drm.struct_mutex); + rq = hang_create_request(&h, engine, + i915->kernel_context); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + mutex_unlock(&i915->drm.struct_mutex); + break; + } + + i915_gem_request_get(rq); + __i915_add_request(rq, true); + mutex_unlock(&i915->drm.struct_mutex); + + if (!wait_for_hang(&h, rq)) { + struct drm_printer p = drm_info_printer(i915->drm.dev); + + pr_err("%s: Failed to start request %x, at %x\n", + __func__, rq->fence.seqno, hws_seqno(&h, rq)); + intel_engine_dump(engine, &p, + "%s\n", engine->name); + + i915_gem_request_put(rq); + err = -EIO; + break; + } + + i915_gem_request_put(rq); + } + + engine->hangcheck.stalled = true; + engine->hangcheck.seqno = + intel_engine_get_seqno(engine); + err = i915_reset_engine(engine, I915_RESET_QUIET); if (err) { - pr_err("i915_reset_engine(%s) failed, err=%d\n", - engine->name, err); + pr_err("i915_reset_engine(%s:%s) failed, err=%d\n", + engine->name, active ? "active" : "idle", err); break; } + + engine->hangcheck.stalled = false; + count++; } while (time_before(jiffies, end_time)); - clear_bit(I915_RESET_ENGINE + engine->id, - &i915->gpu_error.flags); + clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags); + pr_info("i915_reset_engine(%s:%s): %lu resets\n", + engine->name, active ? "active" : "idle", count); + + if (i915_reset_engine_count(&i915->gpu_error, engine) - + resets[engine->id] != (active ? count : 0)) { + pr_err("i915_reset_engine(%s:%s): reset %lu times, but reported %lu\n", + engine->name, active ? "active" : "idle", count, + i915_reset_engine_count(&i915->gpu_error, + engine) - resets[engine->id]); + if (!err) + err = -EINVAL; + } unwind: - for_each_engine(active, i915, tmp) { + for_each_engine(other, i915, tmp) { int ret; if (!threads[tmp]) @@ -524,27 +698,29 @@ static int igt_reset_active_engines(void *arg) ret = kthread_stop(threads[tmp]); if (ret) { - pr_err("kthread for active engine %s failed, err=%d\n", - active->name, ret); + pr_err("kthread for other engine %s failed, err=%d\n", + other->name, ret); if (!err) err = ret; } put_task_struct(threads[tmp]); if (resets[tmp] != i915_reset_engine_count(&i915->gpu_error, - active)) { + other)) { pr_err("Innocent engine %s was reset (count=%ld)\n", - active->name, + other->name, i915_reset_engine_count(&i915->gpu_error, - active) - resets[tmp]); - err = -EIO; + other) - resets[tmp]); + if (!err) + err = -EINVAL; } } if (global != i915_reset_count(&i915->gpu_error)) { pr_err("Global reset (count=%ld)!\n", i915_reset_count(&i915->gpu_error) - global); - err = -EIO; + if (!err) + err = -EINVAL; } if (err) @@ -556,9 +732,25 @@ static int igt_reset_active_engines(void *arg) if (i915_terminally_wedged(&i915->gpu_error)) err = -EIO; + if (active) { + mutex_lock(&i915->drm.struct_mutex); + hang_fini(&h); + mutex_unlock(&i915->drm.struct_mutex); + } + return err; } +static int igt_reset_idle_engine_others(void *arg) +{ + return __igt_reset_engine_others(arg, false); +} + +static int igt_reset_active_engine_others(void *arg) +{ + return __igt_reset_engine_others(arg, true); +} + static u32 fake_hangcheck(struct drm_i915_gem_request *rq) { u32 reset_count; @@ -574,16 +766,6 @@ static u32 fake_hangcheck(struct drm_i915_gem_request *rq) return reset_count; } -static bool wait_for_hang(struct hang *h, struct drm_i915_gem_request *rq) -{ - return !(wait_for_us(i915_seqno_passed(hws_seqno(h, rq), - rq->fence.seqno), - 10) && - wait_for(i915_seqno_passed(hws_seqno(h, rq), - rq->fence.seqno), - 1000)); -} - static int igt_wait_reset(void *arg) { struct drm_i915_private *i915 = arg; @@ -617,8 +799,8 @@ static int igt_wait_reset(void *arg) if (!wait_for_hang(&h, rq)) { struct drm_printer p = drm_info_printer(i915->drm.dev); - pr_err("Failed to start request %x, at %x\n", - rq->fence.seqno, hws_seqno(&h, rq)); + pr_err("%s: Failed to start request %x, at %x\n", + __func__, rq->fence.seqno, hws_seqno(&h, rq)); intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name); i915_reset(i915, 0); @@ -712,8 +894,8 @@ static int igt_reset_queue(void *arg) if (!wait_for_hang(&h, prev)) { struct drm_printer p = drm_info_printer(i915->drm.dev); - pr_err("Failed to start request %x, at %x\n", - prev->fence.seqno, hws_seqno(&h, prev)); + pr_err("%s: Failed to start request %x, at %x\n", + __func__, prev->fence.seqno, hws_seqno(&h, prev)); intel_engine_dump(prev->engine, &p, "%s\n", prev->engine->name); @@ -819,8 +1001,8 @@ static int igt_handle_error(void *arg) if (!wait_for_hang(&h, rq)) { struct drm_printer p = drm_info_printer(i915->drm.dev); - pr_err("Failed to start request %x, at %x\n", - rq->fence.seqno, hws_seqno(&h, rq)); + pr_err("%s: Failed to start request %x, at %x\n", + __func__, rq->fence.seqno, hws_seqno(&h, rq)); intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name); i915_reset(i915, 0); @@ -864,21 +1046,26 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915) static const struct i915_subtest tests[] = { SUBTEST(igt_global_reset), /* attempt to recover GPU first */ SUBTEST(igt_hang_sanitycheck), - SUBTEST(igt_reset_engine), - SUBTEST(igt_reset_active_engines), + SUBTEST(igt_reset_idle_engine), + SUBTEST(igt_reset_active_engine), + SUBTEST(igt_reset_idle_engine_others), + SUBTEST(igt_reset_active_engine_others), SUBTEST(igt_wait_reset), SUBTEST(igt_reset_queue), SUBTEST(igt_handle_error), }; + bool saved_hangcheck; int err; if (!intel_has_gpu_reset(i915)) return 0; intel_runtime_pm_get(i915); + saved_hangcheck = fetch_and_zero(&i915_modparams.enable_hangcheck); err = i915_subtests(tests, i915); + i915_modparams.enable_hangcheck = saved_hangcheck; intel_runtime_pm_put(i915); return err; -- GitLab From 8edcda1266f93816fde77c9754f388ae0ae343fc Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Fri, 15 Dec 2017 14:43:10 -0800 Subject: [PATCH 1756/2547] drm/i915: Protect DDI port to DPLL map from theoretical race. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In case we have multiple modesets for different connectors happening in parallel we could have a race on the RMW on these shared registers. This possibility was initially raised by Paulo when reviewing commit '555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")' but the original possibility comes from commit '5416d871136d ("drm/i915/skl: Set the eDP link rate on DPLL0")'. Or maybe later when atomic commits entered into picture. Apparently the discussion around this topic showed that the right solution would be on serializing the atomic commits in a way that we don't have the possibility of races here since if that parallel modeset happenings apparently many other things will be on fire. Code is there since SKL and there was no report of issue, but since we never looked back to that serialization possibility, and also we don't have an igt case for that it is better to at least protect this corner. Suggested-by: Paulo Zanoni Fixes: 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping") Fixes: 5416d871136d ("drm/i915/skl: Set the eDP link rate on DPLL0") Cc: Paulo Zanoni Cc: Ville Syrjälä Cc: Maarten Lankhorst maarten.lankhorst@linux.intel.com Signed-off-by: Rodrigo Vivi Reviewed-by: Maarten Lankhorst maarten.lankhorst@linux.intel.com Link: https://patchwork.freedesktop.org/patch/msgid/20171215224310.19103-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_ddi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 369f780588fb..f624ba8e23be 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2095,6 +2095,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, if (WARN_ON(!pll)) return; + mutex_lock(&dev_priv->dpll_lock); + if (IS_CANNONLAKE(dev_priv)) { /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ val = I915_READ(DPCLKA_CFGCR0); @@ -2124,6 +2126,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, } else if (INTEL_INFO(dev_priv)->gen < 9) { I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); } + + mutex_unlock(&dev_priv->dpll_lock); } static void intel_ddi_clk_disable(struct intel_encoder *encoder) -- GitLab From 5f8e3f57acf9f28bda1b91545fb204c29f39cc6d Mon Sep 17 00:00:00 2001 From: Joonas Lahtinen Date: Fri, 15 Dec 2017 13:38:00 -0800 Subject: [PATCH 1757/2547] drm/i915/cnl: Add support for horizontal plane flipping MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CNL supports horizontal plane flipping on non-linear plane formats. v2: - Avoid BUG unlike elsewhere in the code (Ville) - Hoist the rotation-tiling restriction check (Ville) v3 (Rodrigo): - Rebased after a while. - Fix small indentation issues. Bspec: 7656 Suggested-by: Anusha Srivatsa Cc: Ville Syrjala Cc: Rodrigo Vivi Cc: Anusha Srivatsa Signed-off-by: Joonas Lahtinen Reviewed-by: Ville Syrjälä Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20171215213800.7896-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 40 ++++++++++++++++++++++++---- 2 files changed, 36 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 09bf043c1c2e..14ade8f88dcc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6329,6 +6329,7 @@ enum { #define PLANE_CTL_TILED_X ( 1 << 10) #define PLANE_CTL_TILED_Y ( 4 << 10) #define PLANE_CTL_TILED_YF ( 5 << 10) +#define PLANE_CTL_FLIP_HORIZONTAL ( 1 << 8) #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */ #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index efa6c6d19664..fb5ee413dc30 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3073,6 +3073,12 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state) unsigned int rotation = plane_state->base.rotation; int ret; + if (rotation & DRM_MODE_REFLECT_X && + fb->modifier == DRM_FORMAT_MOD_LINEAR) { + DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n"); + return -EINVAL; + } + if (!plane_state->base.visible) return 0; @@ -3453,9 +3459,9 @@ static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) return 0; } -static u32 skl_plane_ctl_rotation(unsigned int rotation) +static u32 skl_plane_ctl_rotate(unsigned int rotate) { - switch (rotation) { + switch (rotate) { case DRM_MODE_ROTATE_0: break; /* @@ -3469,7 +3475,22 @@ static u32 skl_plane_ctl_rotation(unsigned int rotation) case DRM_MODE_ROTATE_270: return PLANE_CTL_ROTATE_90; default: - MISSING_CASE(rotation); + MISSING_CASE(rotate); + } + + return 0; +} + +static u32 cnl_plane_ctl_flip(unsigned int reflect) +{ + switch (reflect) { + case 0: + break; + case DRM_MODE_REFLECT_X: + return PLANE_CTL_FLIP_HORIZONTAL; + case DRM_MODE_REFLECT_Y: + default: + MISSING_CASE(reflect); } return 0; @@ -3497,7 +3518,11 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, plane_ctl |= skl_plane_ctl_format(fb->format->format); plane_ctl |= skl_plane_ctl_tiling(fb->modifier); - plane_ctl |= skl_plane_ctl_rotation(rotation); + plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); + + if (INTEL_GEN(dev_priv) >= 10) + plane_ctl |= cnl_plane_ctl_flip(rotation & + DRM_MODE_REFLECT_MASK); if (key->flags & I915_SET_COLORKEY_DESTINATION) plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; @@ -13300,7 +13325,12 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) if (ret) goto fail; - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_GEN(dev_priv) >= 10) { + supported_rotations = + DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | + DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 | + DRM_MODE_REFLECT_X; + } else if (INTEL_GEN(dev_priv) >= 9) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; -- GitLab From 34112bf4935dabe3c1d1fd42842ed771e279bf61 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Mon, 6 Nov 2017 16:20:33 +0100 Subject: [PATCH 1758/2547] drm/nouveau/fbcon: fix NULL pointer access in nouveau_fbcon_destroy When the fbcon object is initialized, but nouveau_fbcon_create is not called, we run into a NULL pointer access within nouveau_fbcon_create when unloading nouveau. The call to drm_fb_helper_funcs.fb_probe is deferred until there is a display for real since 4.14, that's why fbcon->helper.fb is still not set. Signed-off-by: Karol Herbst Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index c533d8e04afc..be7357bf2246 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -429,7 +429,7 @@ nouveau_fbcon_destroy(struct drm_device *dev, struct nouveau_fbdev *fbcon) drm_fb_helper_unregister_fbi(&fbcon->helper); drm_fb_helper_fini(&fbcon->helper); - if (nouveau_fb->nvbo) { + if (nouveau_fb && nouveau_fb->nvbo) { nouveau_vma_del(&nouveau_fb->vma); nouveau_bo_unmap(nouveau_fb->nvbo); nouveau_bo_unpin(nouveau_fb->nvbo); -- GitLab From f60707a69a225f2dd87f42628b44e24ceb219d28 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 7 Dec 2017 10:49:35 +1000 Subject: [PATCH 1759/2547] drm/nouveau/bios/dp: support DP Info Table 2.0 Reported-by: Hans de Goede Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c index 972370ed36f0..7c7efa4ea0d0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c @@ -36,6 +36,7 @@ nvbios_dp_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) if (data) { *ver = nvbios_rd08(bios, data + 0x00); switch (*ver) { + case 0x20: case 0x21: case 0x30: case 0x40: @@ -63,6 +64,7 @@ nvbios_dpout_entry(struct nvkm_bios *bios, u8 idx, if (data && idx < *cnt) { u16 outp = nvbios_rd16(bios, data + *hdr + idx * *len); switch (*ver * !!outp) { + case 0x20: case 0x21: case 0x30: *hdr = nvbios_rd08(bios, data + 0x04); @@ -96,12 +98,16 @@ nvbios_dpout_parse(struct nvkm_bios *bios, u8 idx, info->type = nvbios_rd16(bios, data + 0x00); info->mask = nvbios_rd16(bios, data + 0x02); switch (*ver) { + case 0x20: + info->mask |= 0x00c0; /* match any link */ + /* fall-through */ case 0x21: case 0x30: info->flags = nvbios_rd08(bios, data + 0x05); info->script[0] = nvbios_rd16(bios, data + 0x06); info->script[1] = nvbios_rd16(bios, data + 0x08); - info->lnkcmp = nvbios_rd16(bios, data + 0x0a); + if (*len >= 0x0c) + info->lnkcmp = nvbios_rd16(bios, data + 0x0a); if (*len >= 0x0f) { info->script[2] = nvbios_rd16(bios, data + 0x0c); info->script[3] = nvbios_rd16(bios, data + 0x0e); @@ -170,6 +176,7 @@ nvbios_dpcfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx, memset(info, 0x00, sizeof(*info)); if (data) { switch (*ver) { + case 0x20: case 0x21: info->dc = nvbios_rd08(bios, data + 0x02); info->pe = nvbios_rd08(bios, data + 0x03); -- GitLab From 81a24b9ae8eea95b74337c253059da761043ed06 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 7 Dec 2017 11:08:52 +1000 Subject: [PATCH 1760/2547] drm/nouveau/imem/nv50: fix refcount_t warning Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c index 1ba7289684aa..db48a1daca0c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c @@ -249,7 +249,7 @@ nv50_instobj_acquire(struct nvkm_memory *memory) iobj->base.memory.ptrs = &nv50_instobj_fast; else iobj->base.memory.ptrs = &nv50_instobj_slow; - refcount_inc(&iobj->maps); + refcount_set(&iobj->maps, 1); } mutex_unlock(&imem->subdev.mutex); -- GitLab From a121027d2747168df0aac0c3da35509eea39f61c Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Fri, 24 Nov 2017 03:56:26 +0100 Subject: [PATCH 1761/2547] drm/nouveau/pci: do a msi rearm on init On my GP107 when I load nouveau after unloading it, for some reason the GPU stopped sending or the CPU stopped receiving interrupts if MSI was enabled. Doing a rearm once before getting any interrupts fixes this. Signed-off-by: Karol Herbst Reviewed-by: Thierry Reding Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c index b1b1f3626b96..deb96de54b00 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c @@ -136,6 +136,13 @@ nvkm_pci_init(struct nvkm_subdev *subdev) return ret; pci->irq = pdev->irq; + + /* Ensure MSI interrupts are armed, for the case where there are + * already interrupts pending (for whatever reason) at load time. + */ + if (pci->msi) + pci->func->msi_rearm(pci); + return ret; } -- GitLab From 6cb0f2a39d3b7ccdd7269af4ddadb38e78aee744 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 7 Dec 2017 15:04:32 +1000 Subject: [PATCH 1762/2547] drm/nouveau/mmu/gp10b: use correct implementation Reported-by: Mikko Perttunen Fixes: 6359c98224 ("drm/nouveau/mmu/gp10b: fork from gf100") Signed-off-by: Ben Skeggs Tested-by: Thierry Reding --- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index e14643615698..00eeaaffeae5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2369,7 +2369,7 @@ nv13b_chipset = { .imem = gk20a_instmem_new, .ltc = gp100_ltc_new, .mc = gp10b_mc_new, - .mmu = gf100_mmu_new, + .mmu = gp10b_mmu_new, .secboot = gp10b_secboot_new, .pmu = gm20b_pmu_new, .timer = gk20a_timer_new, -- GitLab From f29f18eb952bc3e71deedf8bd8fc902f66853c48 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 7 Dec 2017 15:25:14 +1000 Subject: [PATCH 1763/2547] drm/nouveau: avoid GPU page sizes > PAGE_SIZE for buffer objects in host memory While the Tegra (GK20A, GM20B, GP10B) MMUs support large pages in host memory, we're currently lacking IOMMU support for merging system pages into large enough chunks to be mapped as such by the GPU. The core VMM code actually supports automatically determining the best page size to map with, which is intended for these situations, but for various complicated reasons the DRM is currently forcing the page size selection on a per-BO basis. This should fix breakage reported on Tegra GPUs in the meantime, until one or both of the above issues are resolved properly. Reported-by: Mikko Perttunen Fixes: 7dc6a446da7c ("drm/nouveau: improve selection of GPU page size") Signed-off-by: Ben Skeggs Tested-by: Thierry Reding --- drivers/gpu/drm/nouveau/nouveau_bo.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 2615912430cc..42c1827bbb8e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -262,7 +262,8 @@ nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE && (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram) continue; - if ((flags & TTM_PL_FLAG_TT ) && !vmm->page[i].host) + if ((flags & TTM_PL_FLAG_TT) && + (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) continue; /* Select this page size if it's the first that supports -- GitLab From 74a39954a4900a7dea7010e3063e2bf16b23934b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 14 Dec 2017 11:19:27 +1000 Subject: [PATCH 1764/2547] drm/nouveau: use alternate memory type for system-memory buffers with kind != 0 Fixes bug on Tegra where we'd strip kind information from system memory (ie. all) buffers, resulting in misrendering. Behaviour on dGPU should be unchanged. Reported-by: Thierry Reding Fixes: d7722134b8 ("drm/nouveau: switch over to new memory and vmm interfaces") Signed-off-by: Ben Skeggs Tested-by: Thierry Reding --- drivers/gpu/drm/nouveau/nouveau_bo.c | 2 +- drivers/gpu/drm/nouveau/nouveau_drv.h | 11 ++++++-- drivers/gpu/drm/nouveau/nouveau_mem.c | 6 ++--- drivers/gpu/drm/nouveau/nouveau_ttm.c | 39 ++++++++++++++++++++------- 4 files changed, 42 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 42c1827bbb8e..435ff8662cfa 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -224,7 +224,7 @@ nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, /* Determine if we can get a cache-coherent map, forcing * uncached mapping if we can't. */ - if (mmu->type[drm->ttm.type_host].type & NVIF_MEM_UNCACHED) + if (!nouveau_drm_use_coherent_gpu_mapping(drm)) nvbo->force_coherent = true; } diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index e86b8220a4bb..6a1b1debe5b8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -156,8 +156,8 @@ struct nouveau_drm { struct nvif_object copy; int mtrr; int type_vram; - int type_host; - int type_ncoh; + int type_host[2]; + int type_ncoh[2]; } ttm; /* GEM interface support */ @@ -216,6 +216,13 @@ nouveau_drm(struct drm_device *dev) return dev->dev_private; } +static inline bool +nouveau_drm_use_coherent_gpu_mapping(struct nouveau_drm *drm) +{ + struct nvif_mmu *mmu = &drm->client.mmu; + return !(mmu->type[drm->ttm.type_host[0]].type & NVIF_MEM_UNCACHED); +} + int nouveau_pmops_suspend(struct device *); int nouveau_pmops_resume(struct device *); bool nouveau_pmops_runtime(void); diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index 589a9621db76..c002f8968507 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c @@ -103,10 +103,10 @@ nouveau_mem_host(struct ttm_mem_reg *reg, struct ttm_dma_tt *tt) u8 type; int ret; - if (mmu->type[drm->ttm.type_host].type & NVIF_MEM_UNCACHED) - type = drm->ttm.type_ncoh; + if (!nouveau_drm_use_coherent_gpu_mapping(drm)) + type = drm->ttm.type_ncoh[!!mem->kind]; else - type = drm->ttm.type_host; + type = drm->ttm.type_host[0]; if (mem->kind && !(mmu->type[type].type & NVIF_MEM_KIND)) mem->comp = mem->kind = 0; diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index 08b974b30482..dff51a0ee028 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -235,27 +235,46 @@ nouveau_ttm_global_release(struct nouveau_drm *drm) drm->ttm.mem_global_ref.release = NULL; } -int -nouveau_ttm_init(struct nouveau_drm *drm) +static int +nouveau_ttm_init_host(struct nouveau_drm *drm, u8 kind) { - struct nvkm_device *device = nvxx_device(&drm->client.device); - struct nvkm_pci *pci = device->pci; struct nvif_mmu *mmu = &drm->client.mmu; - struct drm_device *dev = drm->dev; - int typei, ret; + int typei; typei = nvif_mmu_type(mmu, NVIF_MEM_HOST | NVIF_MEM_MAPPABLE | - NVIF_MEM_COHERENT); + kind | NVIF_MEM_COHERENT); if (typei < 0) return -ENOSYS; - drm->ttm.type_host = typei; + drm->ttm.type_host[!!kind] = typei; - typei = nvif_mmu_type(mmu, NVIF_MEM_HOST | NVIF_MEM_MAPPABLE); + typei = nvif_mmu_type(mmu, NVIF_MEM_HOST | NVIF_MEM_MAPPABLE | kind); if (typei < 0) return -ENOSYS; - drm->ttm.type_ncoh = typei; + drm->ttm.type_ncoh[!!kind] = typei; + return 0; +} + +int +nouveau_ttm_init(struct nouveau_drm *drm) +{ + struct nvkm_device *device = nvxx_device(&drm->client.device); + struct nvkm_pci *pci = device->pci; + struct nvif_mmu *mmu = &drm->client.mmu; + struct drm_device *dev = drm->dev; + int typei, ret; + + ret = nouveau_ttm_init_host(drm, 0); + if (ret) + return ret; + + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && + drm->client.device.info.chipset != 0x50) { + ret = nouveau_ttm_init_host(drm, NVIF_MEM_KIND); + if (ret) + return ret; + } if (drm->client.device.info.platform != NV_DEVICE_INFO_V0_SOC && drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { -- GitLab From c682ccc4962a8fab949e1f2d7325b3e825dbf6d1 Mon Sep 17 00:00:00 2001 From: Hendrik Brueckner Date: Mon, 18 Dec 2017 14:09:57 +0100 Subject: [PATCH 1765/2547] bpf: fix broken BPF selftest build on s390 With 720f228e8d31 ("bpf: fix broken BPF selftest build") the inclusion of arch-specific header files changed. Including the asm/bpf_perf_event.h on s390, correctly includes the s390 specific header file. This header file tries then to include the s390 asm/ptrace.h and the build fails with: cc -Wall -O2 -I../../../include/uapi -I../../../lib -I../../../../include/generated -I../../../include test_verifier.c +/root/git/linux/tools/testing/selftests/bpf/libbpf.a /root/git/linux/tools/testing/selftests/bpf/cgroup_helpers.c -lcap -lelf -o +/root/git/linux/tools/testing/selftests/bpf/test_verifier In file included from ../../../include/uapi/asm/bpf_perf_event.h:4:0, from ../../../include/uapi/linux/bpf_perf_event.h:11, from test_verifier.c:29: ../../../include/uapi/../../arch/s390/include/uapi/asm/bpf_perf_event.h:7:9: error: unknown type name 'user_pt_regs' typedef user_pt_regs bpf_user_pt_regs_t; ^~~~~~~~~~~~ make: *** [../lib.mk:109: /root/git/linux/tools/testing/selftests/bpf/test_verifier] Error 1 This is caused by a recent update to the s390 asm/ptrace.h file that is not (yet) available in the local installation. That means, the s390 asm/ptrace.h must be included from the tools/arch/s390 directory. Because there is no proper framework to deal with asm specific includes in tools/, slightly modify the s390 asm/bpf_perf_event.h to include the local ptrace.h header file. See also discussion on https://marc.info/?l=linux-s390&m=151359424420691&w=2 Please note that this needs to be preserved until tools/ is able to correctly handle asm specific headers. References: https://marc.info/?l=linux-s390&m=151359424420691&w=2 Fixes: 720f228e8d31 ("bpf: fix broken BPF selftest build") Signed-off-by: Hendrik Brueckner Cc: Daniel Borkmann Cc: Hendrik Brueckner Cc: Arnaldo Carvalho de Melo Cc: Alexei Starovoitov Signed-off-by: Daniel Borkmann --- tools/arch/s390/include/uapi/asm/bpf_perf_event.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/arch/s390/include/uapi/asm/bpf_perf_event.h b/tools/arch/s390/include/uapi/asm/bpf_perf_event.h index cefe7c7cd4f6..0a8e37a519f2 100644 --- a/tools/arch/s390/include/uapi/asm/bpf_perf_event.h +++ b/tools/arch/s390/include/uapi/asm/bpf_perf_event.h @@ -2,7 +2,7 @@ #ifndef _UAPI__ASM_BPF_PERF_EVENT_H__ #define _UAPI__ASM_BPF_PERF_EVENT_H__ -#include +#include "ptrace.h" typedef user_pt_regs bpf_user_pt_regs_t; -- GitLab From 182dc9c7f217146d69d9c0b75c150c0314b9b170 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Mon, 18 Dec 2017 16:33:36 +1100 Subject: [PATCH 1766/2547] powerpc/kernel: Print actual address of regs when oopsing When we oops or otherwise call show_regs() we print the address of the regs structure. Being able to see the address is fairly useful, firstly to verify that the regs pointer is not completely bogus, and secondly it allows you to dump the regs and surrounding memory with a debugger if you have one. In the normal case the regs will be located somewhere on the stack, so printing their location discloses no further information than printing the stack pointer does already. So switch to %px and print the actual address, not the hashed value. Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/process.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 5acb5a176dbe..72be0c32e902 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -1403,7 +1403,7 @@ void show_regs(struct pt_regs * regs) printk("NIP: "REG" LR: "REG" CTR: "REG"\n", regs->nip, regs->link, regs->ctr); - printk("REGS: %p TRAP: %04lx %s (%s)\n", + printk("REGS: %px TRAP: %04lx %s (%s)\n", regs, regs->trap, print_tainted(), init_utsname()->release); printk("MSR: "REG" ", regs->msr); print_msr_bits(regs->msr); -- GitLab From 81b6c999897919d5a16fedc018fe375dbab091c5 Mon Sep 17 00:00:00 2001 From: Hannes Reinecke Date: Wed, 13 Dec 2017 14:21:37 +0100 Subject: [PATCH 1767/2547] scsi: core: check for device state in __scsi_remove_target() As it turned out device_get() doesn't use kref_get_unless_zero(), so we will be always getting a device pointer. Consequently, we need to check for the device state in __scsi_remove_target() to avoid tripping over deleted objects. Fixes: fbce4d97fd43 ("scsi: fixup kernel warning during rmmod()") Reported-by: Jason Yan Signed-off-by: Hannes Reinecke Reviewed-by: Bart Van Assche Reviewed-by: Ewan D. Milne Signed-off-by: Martin K. Petersen --- drivers/scsi/scsi_sysfs.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/scsi_sysfs.c b/drivers/scsi/scsi_sysfs.c index a9996c16f4ae..26ce17178401 100644 --- a/drivers/scsi/scsi_sysfs.c +++ b/drivers/scsi/scsi_sysfs.c @@ -1415,7 +1415,10 @@ static void __scsi_remove_target(struct scsi_target *starget) * check. */ if (sdev->channel != starget->channel || - sdev->id != starget->id || + sdev->id != starget->id) + continue; + if (sdev->sdev_state == SDEV_DEL || + sdev->sdev_state == SDEV_CANCEL || !get_device(&sdev->sdev_gendev)) continue; spin_unlock_irqrestore(shost->host_lock, flags); -- GitLab From 5a15f289ee87eaf33f13f08a4909ec99d837ec5f Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Mon, 18 Dec 2017 23:36:57 +0100 Subject: [PATCH 1768/2547] ALSA: usb-audio: Fix the missing ctl name suffix at parsing SU The commit 89b89d121ffc ("ALSA: usb-audio: Add check return value for usb_string()") added the check of the return value from snd_usb_copy_string_desc(), which is correct per se, but it introduced a regression. In the original code, either the "Clock Source", "Playback Source" or "Capture Source" suffix is added after the terminal string, while the commit changed it to add the suffix only when get_term_name() is failing. It ended up with an incorrect ctl name like "PCM" instead of "PCM Capture Source". Also, even the original code has a similar bug: when the ctl name is generated from snd_usb_copy_string_desc() for the given iSelector, it also doesn't put the suffix. This patch addresses these issues: the suffix is added always when no static mapping is found. Also the patch tries to put more comments and cleans up the if/else block for better readability in order to avoid the same pitfall again. Fixes: 89b89d121ffc ("ALSA: usb-audio: Add check return value for usb_string()") Reported-and-tested-by: Mauro Santos Cc: Signed-off-by: Takashi Iwai --- sound/usb/mixer.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c index afc208e1c756..60ebc99ae323 100644 --- a/sound/usb/mixer.c +++ b/sound/usb/mixer.c @@ -2173,20 +2173,25 @@ static int parse_audio_selector_unit(struct mixer_build *state, int unitid, kctl->private_value = (unsigned long)namelist; kctl->private_free = usb_mixer_selector_elem_free; - nameid = uac_selector_unit_iSelector(desc); + /* check the static mapping table at first */ len = check_mapped_name(map, kctl->id.name, sizeof(kctl->id.name)); - if (len) - ; - else if (nameid) - len = snd_usb_copy_string_desc(state, nameid, kctl->id.name, - sizeof(kctl->id.name)); - else - len = get_term_name(state, &state->oterm, - kctl->id.name, sizeof(kctl->id.name), 0); - if (!len) { - strlcpy(kctl->id.name, "USB", sizeof(kctl->id.name)); + /* no mapping ? */ + /* if iSelector is given, use it */ + nameid = uac_selector_unit_iSelector(desc); + if (nameid) + len = snd_usb_copy_string_desc(state, nameid, + kctl->id.name, + sizeof(kctl->id.name)); + /* ... or pick up the terminal name at next */ + if (!len) + len = get_term_name(state, &state->oterm, + kctl->id.name, sizeof(kctl->id.name), 0); + /* ... or use the fixed string "USB" as the last resort */ + if (!len) + strlcpy(kctl->id.name, "USB", sizeof(kctl->id.name)); + /* and add the proper suffix */ if (desc->bDescriptorSubtype == UAC2_CLOCK_SELECTOR) append_ctl_name(kctl, " Clock Source"); else if ((state->oterm.type & 0xff00) == 0x0100) -- GitLab From acf568ee859f098279eadf551612f103afdacb4e Mon Sep 17 00:00:00 2001 From: Herbert Xu Date: Fri, 15 Dec 2017 16:40:44 +1100 Subject: [PATCH 1769/2547] xfrm: Reinject transport-mode packets through tasklet This is an old bugbear of mine: https://www.mail-archive.com/netdev@vger.kernel.org/msg03894.html By crafting special packets, it is possible to cause recursion in our kernel when processing transport-mode packets at levels that are only limited by packet size. The easiest one is with DNAT, but an even worse one is where UDP encapsulation is used in which case you just have to insert an UDP encapsulation header in between each level of recursion. This patch avoids this problem by reinjecting tranport-mode packets through a tasklet. Fixes: b05e106698d9 ("[IPV4/6]: Netfilter IPsec input hooks") Signed-off-by: Herbert Xu Signed-off-by: Steffen Klassert --- include/net/xfrm.h | 3 +++ net/ipv4/xfrm4_input.c | 12 ++++++++- net/ipv6/xfrm6_input.c | 10 +++++++- net/xfrm/xfrm_input.c | 57 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 80 insertions(+), 2 deletions(-) diff --git a/include/net/xfrm.h b/include/net/xfrm.h index dc28a98ce97c..ae35991b5877 100644 --- a/include/net/xfrm.h +++ b/include/net/xfrm.h @@ -1570,6 +1570,9 @@ int xfrm_init_state(struct xfrm_state *x); int xfrm_prepare_input(struct xfrm_state *x, struct sk_buff *skb); int xfrm_input(struct sk_buff *skb, int nexthdr, __be32 spi, int encap_type); int xfrm_input_resume(struct sk_buff *skb, int nexthdr); +int xfrm_trans_queue(struct sk_buff *skb, + int (*finish)(struct net *, struct sock *, + struct sk_buff *)); int xfrm_output_resume(struct sk_buff *skb, int err); int xfrm_output(struct sock *sk, struct sk_buff *skb); int xfrm_inner_extract_output(struct xfrm_state *x, struct sk_buff *skb); diff --git a/net/ipv4/xfrm4_input.c b/net/ipv4/xfrm4_input.c index e50b7fea57ee..bcfc00e88756 100644 --- a/net/ipv4/xfrm4_input.c +++ b/net/ipv4/xfrm4_input.c @@ -23,6 +23,12 @@ int xfrm4_extract_input(struct xfrm_state *x, struct sk_buff *skb) return xfrm4_extract_header(skb); } +static int xfrm4_rcv_encap_finish2(struct net *net, struct sock *sk, + struct sk_buff *skb) +{ + return dst_input(skb); +} + static inline int xfrm4_rcv_encap_finish(struct net *net, struct sock *sk, struct sk_buff *skb) { @@ -33,7 +39,11 @@ static inline int xfrm4_rcv_encap_finish(struct net *net, struct sock *sk, iph->tos, skb->dev)) goto drop; } - return dst_input(skb); + + if (xfrm_trans_queue(skb, xfrm4_rcv_encap_finish2)) + goto drop; + + return 0; drop: kfree_skb(skb); return NET_RX_DROP; diff --git a/net/ipv6/xfrm6_input.c b/net/ipv6/xfrm6_input.c index fe04e23af986..841f4a07438e 100644 --- a/net/ipv6/xfrm6_input.c +++ b/net/ipv6/xfrm6_input.c @@ -32,6 +32,14 @@ int xfrm6_rcv_spi(struct sk_buff *skb, int nexthdr, __be32 spi, } EXPORT_SYMBOL(xfrm6_rcv_spi); +static int xfrm6_transport_finish2(struct net *net, struct sock *sk, + struct sk_buff *skb) +{ + if (xfrm_trans_queue(skb, ip6_rcv_finish)) + __kfree_skb(skb); + return -1; +} + int xfrm6_transport_finish(struct sk_buff *skb, int async) { struct xfrm_offload *xo = xfrm_offload(skb); @@ -56,7 +64,7 @@ int xfrm6_transport_finish(struct sk_buff *skb, int async) NF_HOOK(NFPROTO_IPV6, NF_INET_PRE_ROUTING, dev_net(skb->dev), NULL, skb, skb->dev, NULL, - ip6_rcv_finish); + xfrm6_transport_finish2); return -1; } diff --git a/net/xfrm/xfrm_input.c b/net/xfrm/xfrm_input.c index da6447389ffb..3f6f6f8c9fa5 100644 --- a/net/xfrm/xfrm_input.c +++ b/net/xfrm/xfrm_input.c @@ -8,15 +8,29 @@ * */ +#include +#include #include #include #include +#include #include #include #include #include #include +struct xfrm_trans_tasklet { + struct tasklet_struct tasklet; + struct sk_buff_head queue; +}; + +struct xfrm_trans_cb { + int (*finish)(struct net *net, struct sock *sk, struct sk_buff *skb); +}; + +#define XFRM_TRANS_SKB_CB(__skb) ((struct xfrm_trans_cb *)&((__skb)->cb[0])) + static struct kmem_cache *secpath_cachep __read_mostly; static DEFINE_SPINLOCK(xfrm_input_afinfo_lock); @@ -25,6 +39,8 @@ static struct xfrm_input_afinfo const __rcu *xfrm_input_afinfo[AF_INET6 + 1]; static struct gro_cells gro_cells; static struct net_device xfrm_napi_dev; +static DEFINE_PER_CPU(struct xfrm_trans_tasklet, xfrm_trans_tasklet); + int xfrm_input_register_afinfo(const struct xfrm_input_afinfo *afinfo) { int err = 0; @@ -477,9 +493,41 @@ int xfrm_input_resume(struct sk_buff *skb, int nexthdr) } EXPORT_SYMBOL(xfrm_input_resume); +static void xfrm_trans_reinject(unsigned long data) +{ + struct xfrm_trans_tasklet *trans = (void *)data; + struct sk_buff_head queue; + struct sk_buff *skb; + + __skb_queue_head_init(&queue); + skb_queue_splice_init(&trans->queue, &queue); + + while ((skb = __skb_dequeue(&queue))) + XFRM_TRANS_SKB_CB(skb)->finish(dev_net(skb->dev), NULL, skb); +} + +int xfrm_trans_queue(struct sk_buff *skb, + int (*finish)(struct net *, struct sock *, + struct sk_buff *)) +{ + struct xfrm_trans_tasklet *trans; + + trans = this_cpu_ptr(&xfrm_trans_tasklet); + + if (skb_queue_len(&trans->queue) >= netdev_max_backlog) + return -ENOBUFS; + + XFRM_TRANS_SKB_CB(skb)->finish = finish; + skb_queue_tail(&trans->queue, skb); + tasklet_schedule(&trans->tasklet); + return 0; +} +EXPORT_SYMBOL(xfrm_trans_queue); + void __init xfrm_input_init(void) { int err; + int i; init_dummy_netdev(&xfrm_napi_dev); err = gro_cells_init(&gro_cells, &xfrm_napi_dev); @@ -490,4 +538,13 @@ void __init xfrm_input_init(void) sizeof(struct sec_path), 0, SLAB_HWCACHE_ALIGN|SLAB_PANIC, NULL); + + for_each_possible_cpu(i) { + struct xfrm_trans_tasklet *trans; + + trans = &per_cpu(xfrm_trans_tasklet, i); + __skb_queue_head_init(&trans->queue); + tasklet_init(&trans->tasklet, xfrm_trans_reinject, + (unsigned long)trans); + } } -- GitLab From 6454b3bdd138dfc640deb5e7b9a0668fca2d55dd Mon Sep 17 00:00:00 2001 From: Josh Poimboeuf Date: Mon, 18 Dec 2017 15:13:44 -0600 Subject: [PATCH 1770/2547] x86/stacktrace: Make zombie stack traces reliable Commit: 1959a60182f4 ("x86/dumpstack: Pin the target stack when dumping it") changed the behavior of stack traces for zombies. Before that commit, /proc//stack reported the last execution path of the zombie before it died: [] do_exit+0x6f7/0xa80 [] do_group_exit+0x39/0xa0 [] __wake_up_parent+0x0/0x30 [] system_call_fastpath+0x16/0x1b [<00007fd128f9c4f9>] 0x7fd128f9c4f9 [] 0xffffffffffffffff After the commit, it just reports an empty stack trace. The new behavior is actually probably more correct. If the stack refcount has gone down to zero, then the task has already gone through do_exit() and isn't going to run anymore. The stack could be freed at any time and is basically gone, so reporting an empty stack makes sense. However, save_stack_trace_tsk_reliable() treats such a missing stack condition as an error. That can cause livepatch transition stalls if there are any unreaped zombies. Instead, just treat it as a reliable, empty stack. Reported-and-tested-by: Miroslav Benes Signed-off-by: Josh Poimboeuf Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: live-patching@vger.kernel.org Fixes: af085d9084b4 ("stacktrace/x86: add function for detecting reliable stack traces") Link: http://lkml.kernel.org/r/e4b09e630e99d0c1080528f0821fc9d9dbaeea82.1513631620.git.jpoimboe@redhat.com Signed-off-by: Ingo Molnar --- arch/x86/kernel/stacktrace.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/stacktrace.c b/arch/x86/kernel/stacktrace.c index 77835bc021c7..20161ef53537 100644 --- a/arch/x86/kernel/stacktrace.c +++ b/arch/x86/kernel/stacktrace.c @@ -164,8 +164,12 @@ int save_stack_trace_tsk_reliable(struct task_struct *tsk, { int ret; + /* + * If the task doesn't have a stack (e.g., a zombie), the stack is + * "reliably" empty. + */ if (!try_get_task_stack(tsk)) - return -EINVAL; + return 0; ret = __save_stack_trace_reliable(trace, tsk); -- GitLab From b65c7b8aeac818eb8f80ce825073c12ad081b177 Mon Sep 17 00:00:00 2001 From: Adiel Aloni Date: Mon, 18 Dec 2017 12:14:04 +0200 Subject: [PATCH 1771/2547] mac80211_hwsim: enable TODS BIT in null data frame Same as in ieee80211_nullfunc_get, enable the TODS bit, otherwise the nullfunc packet will not be handled in ap rx path. (will be dropped in ieee80211_accept_frame()). Signed-off-by: Adiel Aloni Signed-off-by: Luca Coelho Signed-off-by: Johannes Berg --- drivers/net/wireless/mac80211_hwsim.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c index 10b075a46b26..59b0cedcdf7b 100644 --- a/drivers/net/wireless/mac80211_hwsim.c +++ b/drivers/net/wireless/mac80211_hwsim.c @@ -684,6 +684,7 @@ static void hwsim_send_nullfunc(struct mac80211_hwsim_data *data, u8 *mac, hdr = skb_put(skb, sizeof(*hdr) - ETH_ALEN); hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC | + IEEE80211_FCTL_TODS | (ps ? IEEE80211_FCTL_PM : 0)); hdr->duration_id = cpu_to_le16(0); memcpy(hdr->addr1, vp->bssid, ETH_ALEN); -- GitLab From 5d32407396b0433f9b738fcfcb9599bcba7379ae Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 14 Dec 2017 14:33:38 +0100 Subject: [PATCH 1772/2547] cfg80211: always rewrite generated files from scratch Currently the certs C code generation appends to the generated files, which is most likely a leftover from commit 715a12334764 ("wireless: don't write C files on failures"). This causes duplicate code in the generated files if the certificates have their timestamps modified between builds and thereby trigger the generation rules. Fixes: 715a12334764 ("wireless: don't write C files on failures") Signed-off-by: Thierry Reding Signed-off-by: Johannes Berg --- net/wireless/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/wireless/Makefile b/net/wireless/Makefile index d7d6cb00c47b..b662be3422e1 100644 --- a/net/wireless/Makefile +++ b/net/wireless/Makefile @@ -43,7 +43,7 @@ $(obj)/shipped-certs.c: $(wildcard $(srctree)/$(src)/certs/*.x509) echo "$$allf"; \ echo '};'; \ echo 'unsigned int shipped_regdb_certs_len = sizeof(shipped_regdb_certs);'; \ - ) >> $@) + ) > $@) $(obj)/extra-certs.c: $(CONFIG_CFG80211_EXTRA_REGDB_KEYDIR:"%"=%) \ $(wildcard $(CONFIG_CFG80211_EXTRA_REGDB_KEYDIR:"%"=%)/*.x509) @@ -66,4 +66,4 @@ $(obj)/extra-certs.c: $(CONFIG_CFG80211_EXTRA_REGDB_KEYDIR:"%"=%) \ echo "$$allf"; \ echo '};'; \ echo 'unsigned int extra_regdb_certs_len = sizeof(extra_regdb_certs);'; \ - ) >> $@) + ) > $@) -- GitLab From 162bd5e5fd921785077b5862d8f2ffabe2fe11e5 Mon Sep 17 00:00:00 2001 From: Jia-Ju Bai Date: Tue, 12 Dec 2017 17:26:36 +0800 Subject: [PATCH 1773/2547] mac80211_hwsim: Fix a possible sleep-in-atomic bug in hwsim_get_radio_nl The driver may sleep under a spinlock. The function call path is: hwsim_get_radio_nl (acquire the spinlock) nlmsg_new(GFP_KERNEL) --> may sleep To fix it, GFP_KERNEL is replaced with GFP_ATOMIC. This bug is found by my static analysis tool(DSAC) and checked by my code review. Signed-off-by: Jia-Ju Bai Signed-off-by: Johannes Berg --- drivers/net/wireless/mac80211_hwsim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c index 59b0cedcdf7b..e8189c07b41f 100644 --- a/drivers/net/wireless/mac80211_hwsim.c +++ b/drivers/net/wireless/mac80211_hwsim.c @@ -3216,7 +3216,7 @@ static int hwsim_get_radio_nl(struct sk_buff *msg, struct genl_info *info) if (!net_eq(wiphy_net(data->hw->wiphy), genl_info_net(info))) continue; - skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); + skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_ATOMIC); if (!skb) { res = -ENOMEM; goto out_err; -- GitLab From 958a1b5a5ed02a768eb27760268251af93090caf Mon Sep 17 00:00:00 2001 From: Jonathan Corbet Date: Mon, 11 Dec 2017 15:37:49 -0700 Subject: [PATCH 1774/2547] nl80211: Remove obsolete kerneldoc line Commit ca986ad9bcd3 (nl80211: allow multiple active scheduled scan requests) removed WIPHY_FLAG_SUPPORTS_SCHED_SCAN but left the kerneldoc description in place, leading to this docs-build warning: ./include/net/cfg80211.h:3278: warning: Excess enum value 'WIPHY_FLAG_SUPPORTS_SCHED_SCAN' description in 'wiphy_flags' Remove the line and gain a bit of peace. Signed-off-by: Jonathan Corbet Acked-by: Arend van Spriel Signed-off-by: Johannes Berg --- include/net/cfg80211.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h index 8b8118a7fadb..cb4d92b79cd9 100644 --- a/include/net/cfg80211.h +++ b/include/net/cfg80211.h @@ -3226,7 +3226,6 @@ struct cfg80211_ops { * @WIPHY_FLAG_IBSS_RSN: The device supports IBSS RSN. * @WIPHY_FLAG_MESH_AUTH: The device supports mesh authentication by routing * auth frames to userspace. See @NL80211_MESH_SETUP_USERSPACE_AUTH. - * @WIPHY_FLAG_SUPPORTS_SCHED_SCAN: The device supports scheduled scans. * @WIPHY_FLAG_SUPPORTS_FW_ROAM: The device supports roaming feature in the * firmware. * @WIPHY_FLAG_AP_UAPSD: The device supports uapsd on AP. -- GitLab From 04a7279ff12fc47b657f70731d401c0064f5838a Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Tue, 19 Dec 2017 09:26:17 +0100 Subject: [PATCH 1775/2547] cfg80211: ship certificates as hex files Not only does this remove the need for the hexdump code in most normal kernel builds (still there for the extra directory), but it also removes the need to ship binary files, which apparently is somewhat problematic, as Randy reported. While at it, also add the generated files to clean-files. Reported-by: Randy Dunlap Signed-off-by: Johannes Berg --- net/wireless/Makefile | 29 ++++------- net/wireless/certs/sforshee.hex | 86 +++++++++++++++++++++++++++++++ net/wireless/certs/sforshee.x509 | Bin 680 -> 0 bytes 3 files changed, 95 insertions(+), 20 deletions(-) create mode 100644 net/wireless/certs/sforshee.hex delete mode 100644 net/wireless/certs/sforshee.x509 diff --git a/net/wireless/Makefile b/net/wireless/Makefile index b662be3422e1..1d84f91bbfb0 100644 --- a/net/wireless/Makefile +++ b/net/wireless/Makefile @@ -23,27 +23,14 @@ ifneq ($(CONFIG_CFG80211_EXTRA_REGDB_KEYDIR),) cfg80211-y += extra-certs.o endif -$(obj)/shipped-certs.c: $(wildcard $(srctree)/$(src)/certs/*.x509) +$(obj)/shipped-certs.c: $(wildcard $(srctree)/$(src)/certs/*.hex) @$(kecho) " GEN $@" - @(set -e; \ - allf=""; \ - for f in $^ ; do \ - # similar to hexdump -v -e '1/1 "0x%.2x," "\n"' \ - thisf=$$(od -An -v -tx1 < $$f | \ - sed -e 's/ /\n/g' | \ - sed -e 's/^[0-9a-f]\+$$/\0/;t;d' | \ - sed -e 's/^/0x/;s/$$/,/'); \ - # file should not be empty - maybe command substitution failed? \ - test ! -z "$$thisf";\ - allf=$$allf$$thisf;\ - done; \ - ( \ - echo '#include "reg.h"'; \ - echo 'const u8 shipped_regdb_certs[] = {'; \ - echo "$$allf"; \ - echo '};'; \ - echo 'unsigned int shipped_regdb_certs_len = sizeof(shipped_regdb_certs);'; \ - ) > $@) + @(echo '#include "reg.h"'; \ + echo 'const u8 shipped_regdb_certs[] = {'; \ + cat $^ ; \ + echo '};'; \ + echo 'unsigned int shipped_regdb_certs_len = sizeof(shipped_regdb_certs);'; \ + ) > $@ $(obj)/extra-certs.c: $(CONFIG_CFG80211_EXTRA_REGDB_KEYDIR:"%"=%) \ $(wildcard $(CONFIG_CFG80211_EXTRA_REGDB_KEYDIR:"%"=%)/*.x509) @@ -67,3 +54,5 @@ $(obj)/extra-certs.c: $(CONFIG_CFG80211_EXTRA_REGDB_KEYDIR:"%"=%) \ echo '};'; \ echo 'unsigned int extra_regdb_certs_len = sizeof(extra_regdb_certs);'; \ ) > $@) + +clean-files += shipped-certs.c extra-certs.c diff --git a/net/wireless/certs/sforshee.hex b/net/wireless/certs/sforshee.hex new file mode 100644 index 000000000000..14ea66643ffa --- /dev/null +++ b/net/wireless/certs/sforshee.hex @@ -0,0 +1,86 @@ +/* Seth Forshee's regdb certificate */ +0x30, 0x82, 0x02, 0xa4, 0x30, 0x82, 0x01, 0x8c, +0x02, 0x09, 0x00, 0xb2, 0x8d, 0xdf, 0x47, 0xae, +0xf9, 0xce, 0xa7, 0x30, 0x0d, 0x06, 0x09, 0x2a, +0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x0b, +0x05, 0x00, 0x30, 0x13, 0x31, 0x11, 0x30, 0x0f, +0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x08, 0x73, +0x66, 0x6f, 0x72, 0x73, 0x68, 0x65, 0x65, 0x30, +0x20, 0x17, 0x0d, 0x31, 0x37, 0x31, 0x30, 0x30, +0x36, 0x31, 0x39, 0x34, 0x30, 0x33, 0x35, 0x5a, +0x18, 0x0f, 0x32, 0x31, 0x31, 0x37, 0x30, 0x39, +0x31, 0x32, 0x31, 0x39, 0x34, 0x30, 0x33, 0x35, +0x5a, 0x30, 0x13, 0x31, 0x11, 0x30, 0x0f, 0x06, +0x03, 0x55, 0x04, 0x03, 0x0c, 0x08, 0x73, 0x66, +0x6f, 0x72, 0x73, 0x68, 0x65, 0x65, 0x30, 0x82, +0x01, 0x22, 0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, +0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x01, 0x05, +0x00, 0x03, 0x82, 0x01, 0x0f, 0x00, 0x30, 0x82, +0x01, 0x0a, 0x02, 0x82, 0x01, 0x01, 0x00, 0xb5, +0x40, 0xe3, 0x9c, 0x28, 0x84, 0x39, 0x03, 0xf2, +0x39, 0xd7, 0x66, 0x2c, 0x41, 0x38, 0x15, 0xac, +0x7e, 0xa5, 0x83, 0x71, 0x25, 0x7e, 0x90, 0x7c, +0x68, 0xdd, 0x6f, 0x3f, 0xd9, 0xd7, 0x59, 0x38, +0x9f, 0x7c, 0x6a, 0x52, 0xc2, 0x03, 0x2a, 0x2d, +0x7e, 0x66, 0xf4, 0x1e, 0xb3, 0x12, 0x70, 0x20, +0x5b, 0xd4, 0x97, 0x32, 0x3d, 0x71, 0x8b, 0x3b, +0x1b, 0x08, 0x17, 0x14, 0x6b, 0x61, 0xc4, 0x57, +0x8b, 0x96, 0x16, 0x1c, 0xfd, 0x24, 0xd5, 0x0b, +0x09, 0xf9, 0x68, 0x11, 0x84, 0xfb, 0xca, 0x51, +0x0c, 0xd1, 0x45, 0x19, 0xda, 0x10, 0x44, 0x8a, +0xd9, 0xfe, 0x76, 0xa9, 0xfd, 0x60, 0x2d, 0x18, +0x0b, 0x28, 0x95, 0xb2, 0x2d, 0xea, 0x88, 0x98, +0xb8, 0xd1, 0x56, 0x21, 0xf0, 0x53, 0x1f, 0xf1, +0x02, 0x6f, 0xe9, 0x46, 0x9b, 0x93, 0x5f, 0x28, +0x90, 0x0f, 0xac, 0x36, 0xfa, 0x68, 0x23, 0x71, +0x57, 0x56, 0xf6, 0xcc, 0xd3, 0xdf, 0x7d, 0x2a, +0xd9, 0x1b, 0x73, 0x45, 0xeb, 0xba, 0x27, 0x85, +0xef, 0x7a, 0x7f, 0xa5, 0xcb, 0x80, 0xc7, 0x30, +0x36, 0xd2, 0x53, 0xee, 0xec, 0xac, 0x1e, 0xe7, +0x31, 0xf1, 0x36, 0xa2, 0x9c, 0x63, 0xc6, 0x65, +0x5b, 0x7f, 0x25, 0x75, 0x68, 0xa1, 0xea, 0xd3, +0x7e, 0x00, 0x5c, 0x9a, 0x5e, 0xd8, 0x20, 0x18, +0x32, 0x77, 0x07, 0x29, 0x12, 0x66, 0x1e, 0x36, +0x73, 0xe7, 0x97, 0x04, 0x41, 0x37, 0xb1, 0xb1, +0x72, 0x2b, 0xf4, 0xa1, 0x29, 0x20, 0x7c, 0x96, +0x79, 0x0b, 0x2b, 0xd0, 0xd8, 0xde, 0xc8, 0x6c, +0x3f, 0x93, 0xfb, 0xc5, 0xee, 0x78, 0x52, 0x11, +0x15, 0x1b, 0x7a, 0xf6, 0xe2, 0x68, 0x99, 0xe7, +0xfb, 0x46, 0x16, 0x84, 0xe3, 0xc7, 0xa1, 0xe6, +0xe0, 0xd2, 0x46, 0xd5, 0xe1, 0xc4, 0x5f, 0xa0, +0x66, 0xf4, 0xda, 0xc4, 0xff, 0x95, 0x1d, 0x02, +0x03, 0x01, 0x00, 0x01, 0x30, 0x0d, 0x06, 0x09, +0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, +0x0b, 0x05, 0x00, 0x03, 0x82, 0x01, 0x01, 0x00, +0x87, 0x03, 0xda, 0xf2, 0x82, 0xc2, 0xdd, 0xaf, +0x7c, 0x44, 0x2f, 0x86, 0xd3, 0x5f, 0x4c, 0x93, +0x48, 0xb9, 0xfe, 0x07, 0x17, 0xbb, 0x21, 0xf7, +0x25, 0x23, 0x4e, 0xaa, 0x22, 0x0c, 0x16, 0xb9, +0x73, 0xae, 0x9d, 0x46, 0x7c, 0x75, 0xd9, 0xc3, +0x49, 0x57, 0x47, 0xbf, 0x33, 0xb7, 0x97, 0xec, +0xf5, 0x40, 0x75, 0xc0, 0x46, 0x22, 0xf0, 0xa0, +0x5d, 0x9c, 0x79, 0x13, 0xa1, 0xff, 0xb8, 0xa3, +0x2f, 0x7b, 0x8e, 0x06, 0x3f, 0xc8, 0xb6, 0xe4, +0x6a, 0x28, 0xf2, 0x34, 0x5c, 0x23, 0x3f, 0x32, +0xc0, 0xe6, 0xad, 0x0f, 0xac, 0xcf, 0x55, 0x74, +0x47, 0x73, 0xd3, 0x01, 0x85, 0xb7, 0x0b, 0x22, +0x56, 0x24, 0x7d, 0x9f, 0x09, 0xa9, 0x0e, 0x86, +0x9e, 0x37, 0x5b, 0x9c, 0x6d, 0x02, 0xd9, 0x8c, +0xc8, 0x50, 0x6a, 0xe2, 0x59, 0xf3, 0x16, 0x06, +0xea, 0xb2, 0x42, 0xb5, 0x58, 0xfe, 0xba, 0xd1, +0x81, 0x57, 0x1a, 0xef, 0xb2, 0x38, 0x88, 0x58, +0xf6, 0xaa, 0xc4, 0x2e, 0x8b, 0x5a, 0x27, 0xe4, +0xa5, 0xe8, 0xa4, 0xca, 0x67, 0x5c, 0xac, 0x72, +0x67, 0xc3, 0x6f, 0x13, 0xc3, 0x2d, 0x35, 0x79, +0xd7, 0x8a, 0xe7, 0xf5, 0xd4, 0x21, 0x30, 0x4a, +0xd5, 0xf6, 0xa3, 0xd9, 0x79, 0x56, 0xf2, 0x0f, +0x10, 0xf7, 0x7d, 0xd0, 0x51, 0x93, 0x2f, 0x47, +0xf8, 0x7d, 0x4b, 0x0a, 0x84, 0x55, 0x12, 0x0a, +0x7d, 0x4e, 0x3b, 0x1f, 0x2b, 0x2f, 0xfc, 0x28, +0xb3, 0x69, 0x34, 0xe1, 0x80, 0x80, 0xbb, 0xe2, +0xaf, 0xb9, 0xd6, 0x30, 0xf1, 0x1d, 0x54, 0x87, +0x23, 0x99, 0x9f, 0x51, 0x03, 0x4c, 0x45, 0x7d, +0x02, 0x65, 0x73, 0xab, 0xfd, 0xcf, 0x94, 0xcc, +0x0d, 0x3a, 0x60, 0xfd, 0x3c, 0x14, 0x2f, 0x16, +0x33, 0xa9, 0x21, 0x1f, 0xcb, 0x50, 0xb1, 0x8f, +0x03, 0xee, 0xa0, 0x66, 0xa9, 0x16, 0x79, 0x14, diff --git a/net/wireless/certs/sforshee.x509 b/net/wireless/certs/sforshee.x509 deleted file mode 100644 index c6f8f9d6b98839048822ebbe27ecb831614ccf3d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 680 zcmXqLVp?L*#Mr~c$*`&SzWchL=aw7rvT6C)$TR)@!PG+Hc~KUrQ+({Z#AT~oKTxlpxkLQTfqeEXZ%BQ56FWCa~!*3zv@ z`y#hls6Zk5%5)>!!ftD64sns}#3SL|)5K){s$Avf{Fx!x^7~XE&qY_sTLLa!H~*Eb z{F|UF!L2cMlkTgI89Oe9DSil+|Hzd8(rxzSc#R4CYs`LSC>Mr@eLHjcey!F`>0;N{ zyVP6XSJf{)-EiE%>{9T%H*4gc8-6rfG$;93YIMD7X~x1=m+Kf}X2so5kT5D|*Az;V zGb?^RoyF07_b*lri)9Z#S`)$Hx~w zdvM9^>cb=P3(~&aI`V(2EE6*$10!+>af3sMk)fUW)~BXJch}dr=(k;t_nGXm^B=qT zZpH7a%6_Yqc*J%Vubb;uQ+o5TXSn-*vL^0OG* zt4&T@BmV8W*cdMLev?H<#J5#P^tz+epDcZ``ND^FO)IZ=J^y+|(ZK8K zx5YOr!#?o~e6PI_I9cEQN3AzkOQ;Z6t)I2Lw*DWD&6y?-8ya>$TEFv}!AIGUcIBD# r1DSnXYnf7uSN}af Date: Tue, 28 Nov 2017 16:48:54 +0100 Subject: [PATCH 1776/2547] omapdrm: panel: fix compatible vendor string for td028ttec1 The vendor name was "toppoly" but other panels and the vendor list have defined it as "tpo". So let's fix it in driver and bindings. We keep the old definition in parallel to stay compatible with potential older DTB setup. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tomi Valkeinen --- .../panel/{toppoly,td028ttec1.txt => tpo,td028ttec1.txt} | 4 ++-- drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c | 3 +++ .../video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c | 3 +++ 3 files changed, 8 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/display/panel/{toppoly,td028ttec1.txt => tpo,td028ttec1.txt} (84%) diff --git a/Documentation/devicetree/bindings/display/panel/toppoly,td028ttec1.txt b/Documentation/devicetree/bindings/display/panel/tpo,td028ttec1.txt similarity index 84% rename from Documentation/devicetree/bindings/display/panel/toppoly,td028ttec1.txt rename to Documentation/devicetree/bindings/display/panel/tpo,td028ttec1.txt index 7175dc3740ac..ed34253d9fb1 100644 --- a/Documentation/devicetree/bindings/display/panel/toppoly,td028ttec1.txt +++ b/Documentation/devicetree/bindings/display/panel/tpo,td028ttec1.txt @@ -2,7 +2,7 @@ Toppoly TD028TTEC1 Panel ======================== Required properties: -- compatible: "toppoly,td028ttec1" +- compatible: "tpo,td028ttec1" Optional properties: - label: a symbolic name for the panel @@ -14,7 +14,7 @@ Example ------- lcd-panel: td028ttec1@0 { - compatible = "toppoly,td028ttec1"; + compatible = "tpo,td028ttec1"; reg = <0>; spi-max-frequency = <100000>; spi-cpol; diff --git a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c index 0a38a0e8c925..a0dfa14f4fab 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c @@ -452,6 +452,8 @@ static int td028ttec1_panel_remove(struct spi_device *spi) } static const struct of_device_id td028ttec1_of_match[] = { + { .compatible = "omapdss,tpo,td028ttec1", }, + /* keep to not break older DTB */ { .compatible = "omapdss,toppoly,td028ttec1", }, {}, }; @@ -471,6 +473,7 @@ static struct spi_driver td028ttec1_spi_driver = { module_spi_driver(td028ttec1_spi_driver); +MODULE_ALIAS("spi:tpo,td028ttec1"); MODULE_ALIAS("spi:toppoly,td028ttec1"); MODULE_AUTHOR("H. Nikolaus Schaller "); MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver"); diff --git a/drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c b/drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c index 57e9e146ff74..4aeb908f2d1e 100644 --- a/drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c +++ b/drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c @@ -455,6 +455,8 @@ static int td028ttec1_panel_remove(struct spi_device *spi) } static const struct of_device_id td028ttec1_of_match[] = { + { .compatible = "omapdss,tpo,td028ttec1", }, + /* keep to not break older DTB */ { .compatible = "omapdss,toppoly,td028ttec1", }, {}, }; @@ -474,6 +476,7 @@ static struct spi_driver td028ttec1_spi_driver = { module_spi_driver(td028ttec1_spi_driver); +MODULE_ALIAS("spi:tpo,td028ttec1"); MODULE_ALIAS("spi:toppoly,td028ttec1"); MODULE_AUTHOR("H. Nikolaus Schaller "); MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver"); -- GitLab From aa8eeb996710abbb309bcf0839f575738ec43f96 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Tue, 28 Nov 2017 16:48:55 +0100 Subject: [PATCH 1777/2547] omapdrm: panel: td028ttec1: replace MODULE_ALIAS by MODULE_DEVICE_TABLE to make it easier to keep in sync with the OF device table. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tomi Valkeinen --- .../gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c | 12 ++++++++++-- .../omap2/omapfb/displays/panel-tpo-td028ttec1.c | 11 +++++++++-- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c index a0dfa14f4fab..2721a86ac5e7 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c @@ -460,9 +460,19 @@ static const struct of_device_id td028ttec1_of_match[] = { MODULE_DEVICE_TABLE(of, td028ttec1_of_match); +static const struct spi_device_id td028ttec1_ids[] = { + { "toppoly,td028ttec1", 0 }, + { "tpo,td028ttec1", 0}, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(spi, td028ttec1_ids); + + static struct spi_driver td028ttec1_spi_driver = { .probe = td028ttec1_panel_probe, .remove = td028ttec1_panel_remove, + .id_table = td028ttec1_ids, .driver = { .name = "panel-tpo-td028ttec1", @@ -473,8 +483,6 @@ static struct spi_driver td028ttec1_spi_driver = { module_spi_driver(td028ttec1_spi_driver); -MODULE_ALIAS("spi:tpo,td028ttec1"); -MODULE_ALIAS("spi:toppoly,td028ttec1"); MODULE_AUTHOR("H. Nikolaus Schaller "); MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c b/drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c index 4aeb908f2d1e..f6da8755b859 100644 --- a/drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c +++ b/drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c @@ -463,9 +463,18 @@ static const struct of_device_id td028ttec1_of_match[] = { MODULE_DEVICE_TABLE(of, td028ttec1_of_match); +static const struct spi_device_id td028ttec1_ids[] = { + { "toppoly,td028ttec1", 0 }, + { "tpo,td028ttec1", 0}, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(spi, td028ttec1_ids); + static struct spi_driver td028ttec1_spi_driver = { .probe = td028ttec1_panel_probe, .remove = td028ttec1_panel_remove, + .id_table = td028ttec1_ids, .driver = { .name = "panel-tpo-td028ttec1", @@ -476,8 +485,6 @@ static struct spi_driver td028ttec1_spi_driver = { module_spi_driver(td028ttec1_spi_driver); -MODULE_ALIAS("spi:tpo,td028ttec1"); -MODULE_ALIAS("spi:toppoly,td028ttec1"); MODULE_AUTHOR("H. Nikolaus Schaller "); MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver"); MODULE_LICENSE("GPL"); -- GitLab From 32fdb624236e17f28813eecd9c6e4d6235974de4 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 30 Nov 2017 14:12:35 +0200 Subject: [PATCH 1778/2547] dt-bindings: display/ti: Add optional property to set memory bandwidth limit max-memory-bandwidth can be used to specify the maximum bandwidth dispc can use when reading display data from main memory. In some SoC (am437x for example) we have memory bandwidth limitation which causes underflow in the display subsystem. Signed-off-by: Peter Ujfalusi Acked-by: Rob Herring Signed-off-by: Tomi Valkeinen --- Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt | 5 +++++ .../devicetree/bindings/display/ti/ti,omap2-dss.txt | 4 ++++ .../devicetree/bindings/display/ti/ti,omap3-dss.txt | 4 ++++ .../devicetree/bindings/display/ti/ti,omap4-dss.txt | 4 ++++ .../devicetree/bindings/display/ti/ti,omap5-dss.txt | 4 ++++ 5 files changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt index c30f9ec189ed..91279f1060fe 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt +++ b/Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt @@ -47,6 +47,11 @@ Required properties: - clocks: handle to fclk - clock-names: "fck" +Optional properties: +- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit + in bytes per second + + HDMI ---- diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap2-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap2-dss.txt index afcd5a86c6a4..ee867c4d1152 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,omap2-dss.txt +++ b/Documentation/devicetree/bindings/display/ti/ti,omap2-dss.txt @@ -28,6 +28,10 @@ Required properties: - ti,hwmods: "dss_dispc" - interrupts: the DISPC interrupt +Optional properties: +- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit + in bytes per second + RFBI ---- diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt index dc66e1447c31..cd02516a40b6 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt +++ b/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt @@ -37,6 +37,10 @@ Required properties: - clocks: handle to fclk - clock-names: "fck" +Optional properties: +- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit + in bytes per second + RFBI ---- diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap4-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap4-dss.txt index bc624db8888d..0f85f6b3a5a8 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,omap4-dss.txt +++ b/Documentation/devicetree/bindings/display/ti/ti,omap4-dss.txt @@ -36,6 +36,10 @@ Required properties: - clocks: handle to fclk - clock-names: "fck" +Optional properties: +- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit + in bytes per second + RFBI ---- diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt index 118a486c47bb..20861218649f 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt +++ b/Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt @@ -36,6 +36,10 @@ Required properties: - clocks: handle to fclk - clock-names: "fck" +Optional properties: +- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit + in bytes per second + RFBI ---- -- GitLab From 867d7e0212170a24f0889e940a5b05ee34551e27 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 30 Nov 2017 14:12:36 +0200 Subject: [PATCH 1779/2547] drm/omap: dss: Add support for reporting memory bandwidth limitation The get_memory_bandwidth_limit() in dispc_ops can be used to query the memory bandwidth limit of dispc by upper layers. Signed-off-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dispc.c | 13 +++++++++++++ drivers/gpu/drm/omapdrm/dss/omapdss.h | 2 ++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 0f4fdb221498..90f9ad89af0d 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -4325,6 +4325,17 @@ static void dispc_free_irq(void *dev_id) dispc.user_data = NULL; } +static u32 dispc_get_memory_bandwidth_limit(void) +{ + u32 limit = 0; + + /* Optional maximum memory bandwidth */ + of_property_read_u32(dispc.pdev->dev.of_node, "max-memory-bandwidth", + &limit); + + return limit; +} + /* * Workaround for errata i734 in DSS dispc * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled @@ -4497,6 +4508,8 @@ static const struct dispc_ops dispc_ops = { .get_num_ovls = dispc_get_num_ovls, .get_num_mgrs = dispc_get_num_mgrs, + .get_memory_bandwidth_limit = dispc_get_memory_bandwidth_limit, + .mgr_enable = dispc_mgr_enable, .mgr_is_enabled = dispc_mgr_is_enabled, .mgr_get_vsync_irq = dispc_mgr_get_vsync_irq, diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index 990422b35784..c2166d2d3f29 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -695,6 +695,8 @@ struct dispc_ops { int (*get_num_ovls)(void); int (*get_num_mgrs)(void); + u32 (*get_memory_bandwidth_limit)(void); + void (*mgr_enable)(enum omap_channel channel, bool enable); bool (*mgr_is_enabled)(enum omap_channel channel); u32 (*mgr_get_vsync_irq)(enum omap_channel channel); -- GitLab From a7631c4b9846a433c06422c6cc64a8a5025071a2 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 30 Nov 2017 14:12:37 +0200 Subject: [PATCH 1780/2547] drm/omap: Filter displays mode based on bandwidth limit If we have memory bandwidth limit configured, reject the modes which would require more bandwidth than the limit if it is used with one full resolution plane (most common use case). This filtering is not providing full protection as it is possible that application would pick smaller crtc resolution with high resolution planes and down scaling, or can enable more smaller planes where the sum of their bandwidth need would be higher than the limit. This patch only allows us to filter out modes which would need more bandwidth if they were used with one full screen plane. Signed-off-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_crtc.c | 37 +++++++++++++++++++++++++++++ drivers/gpu/drm/omapdrm/omap_drv.c | 5 ++++ drivers/gpu/drm/omapdrm/omap_drv.h | 3 +++ 3 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index cc85c16cbc2a..ae2e16ed3874 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "omap_drv.h" @@ -400,6 +401,41 @@ static void omap_crtc_atomic_disable(struct drm_crtc *crtc, drm_crtc_vblank_off(crtc); } +static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + struct omap_drm_private *priv = crtc->dev->dev_private; + + /* Check for bandwidth limit */ + if (priv->max_bandwidth) { + /* + * Estimation for the bandwidth need of a given mode with one + * full screen plane: + * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal)) + * ^^ Refresh rate ^^ + * + * The interlaced mode is taken into account by using the + * pixelclock in the calculation. + * + * The equation is rearranged for 64bit arithmetic. + */ + uint64_t bandwidth = mode->clock * 1000; + unsigned int bpp = 4; + + bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; + bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); + + /* + * Reject modes which would need more bandwidth if used with one + * full resolution plane (most common use case). + */ + if (priv->max_bandwidth < bandwidth) + return MODE_BAD; + } + + return MODE_OK; +} + static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc) { struct omap_crtc *omap_crtc = to_omap_crtc(crtc); @@ -621,6 +657,7 @@ static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { .atomic_flush = omap_crtc_atomic_flush, .atomic_enable = omap_crtc_atomic_enable, .atomic_disable = omap_crtc_atomic_disable, + .mode_valid = omap_crtc_mode_valid, }; /* ----------------------------------------------------------------------------- diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index 96857c508ee0..c4bb261dfcd9 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -563,6 +563,11 @@ static int pdev_probe(struct platform_device *pdev) ddev->dev_private = priv; platform_set_drvdata(pdev, ddev); + /* Get memory bandwidth limits */ + if (priv->dispc_ops->get_memory_bandwidth_limit) + priv->max_bandwidth = + priv->dispc_ops->get_memory_bandwidth_limit(); + omap_gem_init(ddev); ret = omap_modeset_init(ddev); diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index 4bd1e9070b31..d404e8c56b61 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h @@ -83,6 +83,9 @@ struct omap_drm_private { spinlock_t wait_lock; /* protects the wait_list */ struct list_head wait_list; /* list of omap_irq_wait */ uint32_t irq_mask; /* enabled irqs in addition to wait_list */ + + /* memory bandwidth limit if it is needed on the platform */ + unsigned int max_bandwidth; }; -- GitLab From dc47c0cfadffc2d5ca3049dee6371b9615cf84d1 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 24 Jul 2017 19:32:58 +0200 Subject: [PATCH 1781/2547] drm/omap: remove unused function defines Remove driver (un)register API defines. They do not even exist anymore. Signed-off-by: Sebastian Reichel Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/omapdss.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index c2166d2d3f29..6c6d888416a7 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -585,9 +585,6 @@ struct omap_dss_driver { bool omapdss_is_initialized(void); -int omap_dss_register_driver(struct omap_dss_driver *); -void omap_dss_unregister_driver(struct omap_dss_driver *); - int omapdss_register_display(struct omap_dss_device *dssdev); void omapdss_unregister_display(struct omap_dss_device *dssdev); -- GitLab From 1a80d6ac2f82cd587bb12012b52d555e0a27d121 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 24 Jul 2017 19:32:59 +0200 Subject: [PATCH 1782/2547] drm/omap: drop incorrect comment The wrappers have been removed in commit 5a35876e2830 (drm: omapdrm: Remove manual update display support) and will not be reintroduced, since the normal sys functions properly call the dirty callback. Signed-off-by: Sebastian Reichel Acked-by: Pavel Machek Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_fbdev.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/omap_fbdev.c b/drivers/gpu/drm/omapdrm/omap_fbdev.c index 9273118040b7..e0378182bd7c 100644 --- a/drivers/gpu/drm/omapdrm/omap_fbdev.c +++ b/drivers/gpu/drm/omapdrm/omap_fbdev.c @@ -84,9 +84,6 @@ static struct fb_ops omap_fb_ops = { .owner = THIS_MODULE, DRM_FB_HELPER_DEFAULT_OPS, - /* Note: to properly handle manual update displays, we wrap the - * basic fbdev ops which write to the framebuffer - */ .fb_read = drm_fb_helper_sys_read, .fb_write = drm_fb_helper_sys_write, .fb_fillrect = drm_fb_helper_sys_fillrect, -- GitLab From b070d6e84ad20666a8856cfb8f9bd90197ec6c6d Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 24 Jul 2017 19:33:04 +0200 Subject: [PATCH 1783/2547] drm/omap: add support for physical size hints from display drivers While physical size information is automatically parsed for EDID based displays, we need to provide it manually for displays providing one fixed mode. Signed-off-by: Sebastian Reichel Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/omapdss.h | 2 ++ drivers/gpu/drm/omapdrm/omap_connector.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index 6c6d888416a7..6aa4c377492d 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -563,6 +563,8 @@ struct omap_dss_driver { struct videomode *vm); void (*get_timings)(struct omap_dss_device *dssdev, struct videomode *vm); + void (*get_size)(struct omap_dss_device *dssdev, + unsigned int *width, unsigned int *height); int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); u32 (*get_wss)(struct omap_dss_device *dssdev); diff --git a/drivers/gpu/drm/omapdrm/omap_connector.c b/drivers/gpu/drm/omapdrm/omap_connector.c index aa5ba9ae2191..188124adc8a8 100644 --- a/drivers/gpu/drm/omapdrm/omap_connector.c +++ b/drivers/gpu/drm/omapdrm/omap_connector.c @@ -149,6 +149,12 @@ static int omap_connector_get_modes(struct drm_connector *connector) drm_mode_set_name(mode); drm_mode_probed_add(connector, mode); + if (dssdrv->get_size) { + dssdrv->get_size(dssdev, + &connector->display_info.width_mm, + &connector->display_info.height_mm); + } + n = 1; } -- GitLab From e128310ddd379b0fdd21dc41d176c3b3505a0832 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 24 Jul 2017 19:33:05 +0200 Subject: [PATCH 1784/2547] drm/omap: panel-dsi-cm: fix driver This adds support for get_timings() and check_timings() to get the driver working and properly initializes the timing information from DT. Signed-off-by: Tony Lindgren Signed-off-by: Sebastian Reichel Signed-off-by: Tomi Valkeinen --- .../gpu/drm/omapdrm/displays/panel-dsi-cm.c | 56 +++++++++++++++++-- 1 file changed, 51 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c index 92c556ac22c7..905b71719d65 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c @@ -25,6 +25,7 @@ #include #include